From 852e4500bc56ffc2b21d5b67d479b4dd667f567c Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Sun, 7 Dec 2025 21:53:32 +0800 Subject: [PATCH 001/238] Memrouter changes for virtualization(#16) --- .../framework/balldomain/bbus/bbus.scala | 39 +++----- .../bbus/memrouter/SramIOAdapter.scala | 24 +++-- .../balldomain/bbus/memrouter/memRouter.scala | 63 +++++-------- .../framework/balldomain/blink/blink.scala | 4 +- .../framework/switcher/ToPhysicalLine.scala | 88 +++++++++---------- docs/bb-note/src/tutorial/tutorial.md | 2 +- 6 files changed, 95 insertions(+), 125 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 6b9e05ea..8de5995c 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -75,22 +75,8 @@ class BBus(ballGenerators: Seq[() => BallRegist with Module]) // memory router // ----------------------------------------------------------------------------- val memoryrouter = Module(new MemRouter(numBalls)(b, p)) - io.sramRead <> memoryrouter.io.sramRead_o - io.sramWrite <> memoryrouter.io.sramWrite_o - io.accRead <> memoryrouter.io.accRead_o - io.accWrite <> memoryrouter.io.accWrite_o memoryrouter.io.bbusConfig_i <> cmdRouter.io.bbusConfig_o - // be replaced by ToVirtualLine and ToPhysicalLine modules - //begin - // for(i <- 0 until numBalls){ - // memoryrouter.io.sramRead_i(i) <> balls(i).Blink.sramRead - // memoryrouter.io.sramWrite_i(i) <> balls(i).Blink.sramWrite - // memoryrouter.io.accRead_i(i) <> balls(i).Blink.accRead - // memoryrouter.io.accWrite_i(i) <> balls(i).Blink.accWrite - // } - //end - // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- @@ -116,21 +102,24 @@ class BBus(ballGenerators: Seq[() => BallRegist with Module]) toVirtualLines(i).io.accWrite_i <> balls(i).Blink.accWrite } + for(i <- 0 until numBalls){ + memoryrouter.io.sramRead_i(i) <> toVirtualLines(i).io.sramRead_o + memoryrouter.io.sramWrite_i(i) <> toVirtualLines(i).io.sramWrite_o + } // ----------------------------------------------------------------------------- // ToPhysicalLine - per-ball conversion from virtual to physical line // ----------------------------------------------------------------------------- - val toPhysicalLines = Seq.fill(numBalls){ Module(new ToPhysicalLine()(b, p)) } - for (i <- 0 until numBalls) { - toPhysicalLines(i).io.sramRead_i <> toVirtualLines(i).io.sramRead_o - toPhysicalLines(i).io.sramWrite_i <> toVirtualLines(i).io.sramWrite_o - - memoryrouter.io.sramRead_i(i) <> toPhysicalLines(i).io.sramRead_o - memoryrouter.io.sramWrite_i(i) <> toPhysicalLines(i).io.sramWrite_o - memoryrouter.io.accRead_i(i) <> toPhysicalLines(i).io.accRead_o - memoryrouter.io.accWrite_i(i) <> toPhysicalLines(i).io.accWrite_o - } + val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) + + toPhysicalLines.io.sramRead_i <> memoryrouter.io.sramRead_o + toPhysicalLines.io.sramWrite_i <> memoryrouter.io.sramWrite_o + + io.sramRead <> toPhysicalLines.io.sramRead_o + io.sramWrite <> toPhysicalLines.io.sramWrite_o + io.accRead <> toPhysicalLines.io.accRead_o + io.accWrite <> toPhysicalLines.io.accWrite_o override lazy val desiredName = "BBus" -} +} \ No newline at end of file diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala index 690e52c2..f7556bd8 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala @@ -7,15 +7,25 @@ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.balldomain.rs.{BallRsIssue, BallRsComplete} import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq, SramReadResp, SramWriteReq} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} class SramIOAdapter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val io = IO(new Bundle { - val sramWrite_i = new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len) - val sramRead_o = new SramReadIO(b.spad_bank_entries, b.spad_w) + val sramWrite_i = new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len) + val sramRead_o = new SramReadWithInfo(b.spad_bank_entries, b.spad_w) }) - io.sramRead_o.req.ready := true.B - io.sramWrite_i.req.ready := io.sramRead_o.resp.ready - io.sramRead_o.resp.valid := io.sramWrite_i.req.valid - io.sramRead_o.resp.bits.data := io.sramWrite_i.req.bits.data - io.sramRead_o.resp.bits.fromDMA := false.B + + val read_o = Wire(new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) + + read_o.io.req.ready := true.B + io.sramWrite_i.io.req.ready := read_o.io.resp.ready + read_o.io.resp.valid := io.sramWrite_i.io.req.valid + read_o.io.resp.bits.data := io.sramWrite_i.io.req.bits.data + read_o.io.resp.bits.fromDMA := false.B + + read_o.rob_id := io.sramWrite_i.rob_id + read_o.is_acc := io.sramWrite_i.is_acc + read_o.bank_id := io.sramWrite_i.bank_id + + io.sramRead_o <> read_o } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index c363a3ae..c702cced 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -6,21 +6,20 @@ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.balldomain.rs.{BallRsIssue, BallRsComplete} import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq, SramReadResp, SramWriteReq} -import framework.balldomain.blink.{SramReadWithRobId, SramWriteWithRobId} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} import framework.balldomain.bbus.BBusConfigIO class MemRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { + private val numBanks = b.sp_banks + b.acc_banks val io = IO(new Bundle { - val sramRead_i = Vec(numBalls, Vec(b.sp_banks, new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) - val sramWrite_i = Vec(numBalls, Vec(b.sp_banks, new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accRead_i = Vec(numBalls, Vec(b.acc_banks, new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) - val accWrite_i = Vec(numBalls, Vec(b.acc_banks, new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val sramRead_i = Vec(numBalls, Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) + val sramWrite_i = Vec(numBalls, Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + val bbusConfig_i = Flipped(Decoupled(new BBusConfigIO(numBalls))) - val sramRead_o = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val sramWrite_o = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accRead_o = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accWrite_o = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val sramRead_o = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) + val sramWrite_o = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + }) val list_valid = RegInit(VecInit(Seq.fill(numBalls)(false.B))) @@ -33,17 +32,12 @@ class MemRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) // Default assignment io.sramRead_o := DontCare io.sramWrite_o := DontCare - io.accRead_o := DontCare - io.accWrite_o := DontCare + for (i <- 0 until numBalls) { io.sramRead_i(i).foreach(_.io.req.ready := false.B) io.sramRead_i(i).foreach(_.io.resp.valid := false.B) io.sramRead_i(i).foreach(_.io.resp.bits := DontCare) io.sramWrite_i(i).foreach(_.io.req.ready := false.B) - io.accRead_i(i).foreach(_.io.req.ready := false.B) - io.accRead_i(i).foreach(_.io.resp.valid := false.B) - io.accRead_i(i).foreach(_.io.resp.bits := DontCare) - io.accWrite_i(i).foreach(_.io.req.ready := false.B) } // Routing selection @@ -62,35 +56,20 @@ class MemRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) } */ - for(j <- 0 until b.sp_banks){ + for(j <- 0 until numBanks){ when(io.sramRead_i(i)(j).io.req.valid){ - io.sramRead_o(j).req <> io.sramRead_i(i)(j).io.req + io.sramRead_o(j).io.req <> io.sramRead_i(i)(j).io.req } } - for(j <- 0 until b.sp_banks){ - when(io.sramRead_o(j).resp.valid){ - io.sramRead_i(i)(j).io.resp <> io.sramRead_o(j).resp + for(j <- 0 until numBanks){ + when(io.sramRead_o(j).io.resp.valid){ + io.sramRead_i(i)(j).io.resp <> io.sramRead_o(j).io.resp } } - for(j <- 0 until b.acc_banks){ - when(io.accRead_i(i)(j).io.req.valid){ - io.accRead_o(j).req <> io.accRead_i(i)(j).io.req - } - } - for(j <- 0 until b.acc_banks){ - when(io.accRead_o(j).resp.valid){ - io.accRead_i(i)(j).io.resp <> io.accRead_o(j).resp - } - } - for(j <- 0 until b.sp_banks){ + for(j <- 0 until numBanks){ when(io.sramWrite_i(i)(j).io.req.valid){ - io.sramWrite_o(j)<> io.sramWrite_i(i)(j).io - } - } - for(j <- 0 until b.acc_banks){ - when(io.accWrite_i(i)(j).io.req.valid){ - io.accWrite_o(j) <> io.accWrite_i(i)(j).io + io.sramWrite_o(j)<> io.sramWrite_i(i)(j) } } } @@ -109,11 +88,11 @@ class MemRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) when(list_valid(i)){ val sramIOadapter = Module(new SramIOAdapter(numBalls)(b, p)) val dst_bid = list_dst_bid(i) - sramIOadapter.io.sramWrite_i <> io.sramWrite_i(i)(0).io - io.sramRead_i(dst_bid)(0).io <> sramIOadapter.io.sramRead_o - io.sramWrite_o(0).req.valid := false.B - io.sramWrite_o(0).req.bits := DontCare + sramIOadapter.io.sramWrite_i <> io.sramWrite_i(i)(0) + io.sramRead_i(dst_bid)(0) <> sramIOadapter.io.sramRead_o + io.sramWrite_o(0).io.req.valid := false.B + io.sramWrite_o(0).io.req.bits := DontCare } } override lazy val desiredName = "MemRouter" -} +} \ No newline at end of file diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index f1d018b1..d5b127aa 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -40,7 +40,7 @@ class SramWriteWithRobId(val n: Int, val w: Int, val mask_len: Int)(implicit b: val rob_id = Input(UInt(log2Up(b.rob_entries).W)) } -// SramReadIO with rob_id +// SramReadIO with rob_id, is_acc, bank_id class SramReadWithInfo(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { val io = new SramReadIO(n, w) // Input because the outer layer has Flipped @@ -49,7 +49,7 @@ class SramReadWithInfo(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) } -// SramWriteIO with rob_id +// SramWriteIO with rob_id, is_acc, bank_id class SramWriteWithInfo(val n: Int, val w: Int, val mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { val io = new SramWriteIO(n, w, mask_len) // Input because theSramWriteIO outer layer has Flipped diff --git a/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala b/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala index 1307e7e8..4d43edf1 100644 --- a/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala +++ b/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala @@ -5,7 +5,7 @@ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.blink.{SramReadWithRobId, SramWriteWithRobId, SramReadWithInfo, SramWriteWithInfo} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { @@ -17,11 +17,11 @@ class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends M val sramWrite_i = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) // Physical memory endpoints - val sramRead_o = Vec(b.sp_banks, Flipped(new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) - val sramWrite_o = Vec(b.sp_banks, Flipped(new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + val sramRead_o = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) + val sramWrite_o = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accRead_o = Vec(b.acc_banks, Flipped(new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) - val accWrite_o = Vec(b.acc_banks, Flipped(new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val accRead_o = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) + val accWrite_o = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) }) // -------------------------------------------------------------------------- @@ -31,29 +31,25 @@ class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends M // SPAD read/write ports for (i <- 0 until b.sp_banks) { val spR = io.sramRead_o(i) - spR.io.req.valid := false.B - spR.io.req.bits := DontCare - spR.io.resp.ready := false.B - spR.rob_id := 0.U + spR.req.valid := false.B + spR.req.bits := DontCare + spR.resp.ready := false.B val spW = io.sramWrite_o(i) - spW.io.req.valid := false.B - spW.io.req.bits := DontCare - spW.rob_id := 0.U + spW.req.valid := false.B + spW.req.bits := DontCare } // ACC read/write ports for (i <- 0 until b.acc_banks) { val accR = io.accRead_o(i) - accR.io.req.valid := false.B - accR.io.req.bits := DontCare - accR.io.resp.ready := false.B - accR.rob_id := 0.U + accR.req.valid := false.B + accR.req.bits := DontCare + accR.resp.ready := false.B val accW = io.accWrite_o(i) - accW.io.req.valid := false.B - accW.io.req.bits := DontCare - accW.rob_id := 0.U + accW.req.valid := false.B + accW.req.bits := DontCare } // Default values for all virtual ports @@ -76,17 +72,16 @@ class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends M val spR = io.sramRead_o(i) // Request path (virtual → SPAD) - spR.io.req.valid := vR.io.req.valid - spR.io.req.bits.addr := vR.io.req.bits.addr - spR.io.req.bits.fromDMA := vR.io.req.bits.fromDMA - spR.rob_id := vR.rob_id + spR.req.valid := vR.io.req.valid + spR.req.bits.addr := vR.io.req.bits.addr + spR.req.bits.fromDMA := vR.io.req.bits.fromDMA - vR.io.req.ready := spR.io.req.ready + vR.io.req.ready := spR.req.ready // Response path (SPAD → virtual) - vR.io.resp.valid := spR.io.resp.valid - vR.io.resp.bits := spR.io.resp.bits - spR.io.resp.ready := vR.io.resp.ready + vR.io.resp.valid := spR.resp.valid + vR.io.resp.bits := spR.resp.bits + spR.resp.ready := vR.io.resp.ready } // -------------------------------------------------------------------------- @@ -99,17 +94,16 @@ class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends M val accR = io.accRead_o(i) // Request path (virtual → ACC) - accR.io.req.valid := vR.io.req.valid - accR.io.req.bits.addr := vR.io.req.bits.addr - accR.io.req.bits.fromDMA := vR.io.req.bits.fromDMA - accR.rob_id := vR.rob_id + accR.req.valid := vR.io.req.valid + accR.req.bits.addr := vR.io.req.bits.addr + accR.req.bits.fromDMA := vR.io.req.bits.fromDMA - vR.io.req.ready := accR.io.req.ready + vR.io.req.ready := accR.req.ready // Response path (ACC → virtual) - vR.io.resp.valid := accR.io.resp.valid - vR.io.resp.bits := accR.io.resp.bits - accR.io.resp.ready := vR.io.resp.ready + vR.io.resp.valid := accR.resp.valid + vR.io.resp.bits := accR.resp.bits + accR.resp.ready := vR.io.resp.ready } // -------------------------------------------------------------------------- @@ -120,13 +114,12 @@ class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends M val vW = io.sramWrite_i(i) val spW = io.sramWrite_o(i) - spW.io.req.valid := vW.io.req.valid - spW.io.req.bits.addr := vW.io.req.bits.addr - spW.io.req.bits.data := vW.io.req.bits.data - spW.io.req.bits.mask := vW.io.req.bits.mask - spW.rob_id := vW.rob_id + spW.req.valid := vW.io.req.valid + spW.req.bits.addr := vW.io.req.bits.addr + spW.req.bits.data := vW.io.req.bits.data + spW.req.bits.mask := vW.io.req.bits.mask - vW.io.req.ready := spW.io.req.ready + vW.io.req.ready := spW.req.ready } // -------------------------------------------------------------------------- @@ -138,12 +131,11 @@ class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends M val vW = io.sramWrite_i(idx) val accW = io.accWrite_o(i) - accW.io.req.valid := vW.io.req.valid - accW.io.req.bits.addr := vW.io.req.bits.addr - accW.io.req.bits.data := vW.io.req.bits.data - accW.io.req.bits.mask := vW.io.req.bits.mask - accW.rob_id := vW.rob_id + accW.req.valid := vW.io.req.valid + accW.req.bits.addr := vW.io.req.bits.addr + accW.req.bits.data := vW.io.req.bits.data + accW.req.bits.mask := vW.io.req.bits.mask - vW.io.req.ready := accW.io.req.ready + vW.io.req.ready := accW.req.ready } -} +} \ No newline at end of file diff --git a/docs/bb-note/src/tutorial/tutorial.md b/docs/bb-note/src/tutorial/tutorial.md index 13a6b4b1..044e05be 100644 --- a/docs/bb-note/src/tutorial/tutorial.md +++ b/docs/bb-note/src/tutorial/tutorial.md @@ -239,7 +239,7 @@ Compile/package the selected workload source code or configuration into artifact ``` cd buckyball -bbdev verilator --verilog +bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' ``` If `bbdev verilator --verilog` reports an error after execution, this means hardware compilation failed, please check **"I. Writing Chisel Hardware Module II. Compilation Adaptation Preparation"** related files. From c259f27b4313ab876ee298f4d7e43f2beda3a049 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 7 Dec 2025 22:17:29 +0800 Subject: [PATCH 002/238] [docs] fix: add mdbook missing files --- docs/bb-note/mermaid-init.js | 4 + docs/bb-note/mermaid.min.js | 2609 ++++++++++++++++++++++++++++++++++ docs/bb-note/src/SUMMARY.md | 1 - 3 files changed, 2613 insertions(+), 1 deletion(-) create mode 100644 docs/bb-note/mermaid.min.js diff --git a/docs/bb-note/mermaid-init.js b/docs/bb-note/mermaid-init.js index 15a7f4e5..0469ff16 100644 --- a/docs/bb-note/mermaid-init.js +++ b/docs/bb-note/mermaid-init.js @@ -1,3 +1,7 @@ +// This Source Code Form is subject to the terms of the Mozilla Public +// License, v. 2.0. If a copy of the MPL was not distributed with this +// file, You can obtain one at https://mozilla.org/MPL/2.0/. + (() => { const darkThemes = ['ayu', 'navy', 'coal']; const lightThemes = ['light', 'rust']; diff --git a/docs/bb-note/mermaid.min.js b/docs/bb-note/mermaid.min.js new file mode 100644 index 00000000..1a66ed0f --- /dev/null +++ b/docs/bb-note/mermaid.min.js @@ -0,0 +1,2609 @@ +/* MIT Licensed. Copyright (c) 2014 - 2022 Knut Sveidqvist */ +/* For license information please see https://github.com/mermaid-js/mermaid/blob/develop/LICENSE */ +"use strict";var __esbuild_esm_mermaid=(()=>{var B2e=Object.create;var by=Object.defineProperty;var F2e=Object.getOwnPropertyDescriptor;var $2e=Object.getOwnPropertyNames;var z2e=Object.getPrototypeOf,G2e=Object.prototype.hasOwnProperty;var o=(t,e)=>by(t,"name",{value:e,configurable:!0});var N=(t,e)=>()=>(t&&(e=t(t=0)),e);var Mi=(t,e)=>()=>(e||t((e={exports:{}}).exports,e),e.exports),hr=(t,e)=>{for(var r in e)by(t,r,{get:e[r],enumerable:!0})},L4=(t,e,r,n)=>{if(e&&typeof e=="object"||typeof e=="function")for(let i of $2e(e))!G2e.call(t,i)&&i!==r&&by(t,i,{get:()=>e[i],enumerable:!(n=F2e(e,i))||n.enumerable});return t},Sr=(t,e,r)=>(L4(t,e,"default"),r&&L4(r,e,"default")),Sa=(t,e,r)=>(r=t!=null?B2e(z2e(t)):{},L4(e||!t||!t.__esModule?by(r,"default",{value:t,enumerable:!0}):r,t)),V2e=t=>L4(by({},"__esModule",{value:!0}),t);var R4=Mi((EC,SC)=>{"use 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e=0;e{this[n]==="calculated"&&(this[n]=void 0)}),typeof e!="object"){this.updateColors();return}let r=Object.keys(e);r.forEach(n=>{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},oh=o(t=>{let e=new QC;return e.calculate(t),e},"getThemeVariables")});var ZC,N$,M$=N(()=>{"use strict";Ys();Ay();o0();ZC=class{static{o(this,"Theme")}constructor(){this.background="#f4f4f4",this.primaryColor="#cde498",this.secondaryColor="#cdffb2",this.background="white",this.mainBkg="#cde498",this.secondBkg="#cdffb2",this.lineColor="green",this.border1="#13540c",this.border2="#6eaa49",this.arrowheadColor="green",this.fontFamily='"trebuchet ms", verdana, arial, sans-serif',this.fontSize="16px",this.tertiaryColor=Dt("#cde498",10),this.primaryBorderColor=Ti(this.primaryColor,this.darkMode),this.secondaryBorderColor=Ti(this.secondaryColor,this.darkMode),this.tertiaryBorderColor=Ti(this.tertiaryColor,this.darkMode),this.primaryTextColor=wt(this.primaryColor),this.secondaryTextColor=wt(this.secondaryColor),this.tertiaryTextColor=wt(this.primaryColor),this.lineColor=wt(this.background),this.textColor=wt(this.background),this.THEME_COLOR_LIMIT=12,this.nodeBkg="calculated",this.nodeBorder="calculated",this.clusterBkg="calculated",this.clusterBorder="calculated",this.defaultLinkColor="calculated",this.titleColor="#333",this.edgeLabelBackground="#e8e8e8",this.actorBorder="calculated",this.actorBkg="calculated",this.actorTextColor="black",this.actorLineColor="calculated",this.signalColor="#333",this.signalTextColor="#333",this.labelBoxBkgColor="calculated",this.labelBoxBorderColor="#326932",this.labelTextColor="calculated",this.loopTextColor="calculated",this.noteBorderColor="calculated",this.noteBkgColor="#fff5ad",this.noteTextColor="calculated",this.activationBorderColor="#666",this.activationBkgColor="#f4f4f4",this.sequenceNumberColor="white",this.sectionBkgColor="#6eaa49",this.altSectionBkgColor="white",this.sectionBkgColor2="#6eaa49",this.excludeBkgColor="#eeeeee",this.taskBorderColor="calculated",this.taskBkgColor="#487e3a",this.taskTextLightColor="white",this.taskTextColor="calculated",this.taskTextDarkColor="black",this.taskTextOutsideColor="calculated",this.taskTextClickableColor="#003163",this.activeTaskBorderColor="calculated",this.activeTaskBkgColor="calculated",this.gridColor="lightgrey",this.doneTaskBkgColor="lightgrey",this.doneTaskBorderColor="grey",this.critBorderColor="#ff8888",this.critBkgColor="red",this.todayLineColor="red",this.personBorder=this.primaryBorderColor,this.personBkg=this.mainBkg,this.archEdgeColor="calculated",this.archEdgeArrowColor="calculated",this.archEdgeWidth="3",this.archGroupBorderColor=this.primaryBorderColor,this.archGroupBorderWidth="2px",this.labelColor="black",this.errorBkgColor="#552222",this.errorTextColor="#552222"}updateColors(){this.actorBorder=Ot(this.mainBkg,20),this.actorBkg=this.mainBkg,this.labelBoxBkgColor=this.actorBkg,this.labelTextColor=this.actorTextColor,this.loopTextColor=this.actorTextColor,this.noteBorderColor=this.border2,this.noteTextColor=this.actorTextColor,this.actorLineColor=this.actorBorder,this.cScale0=this.cScale0||this.primaryColor,this.cScale1=this.cScale1||this.secondaryColor,this.cScale2=this.cScale2||this.tertiaryColor,this.cScale3=this.cScale3||Me(this.primaryColor,{h:30}),this.cScale4=this.cScale4||Me(this.primaryColor,{h:60}),this.cScale5=this.cScale5||Me(this.primaryColor,{h:90}),this.cScale6=this.cScale6||Me(this.primaryColor,{h:120}),this.cScale7=this.cScale7||Me(this.primaryColor,{h:150}),this.cScale8=this.cScale8||Me(this.primaryColor,{h:210}),this.cScale9=this.cScale9||Me(this.primaryColor,{h:270}),this.cScale10=this.cScale10||Me(this.primaryColor,{h:300}),this.cScale11=this.cScale11||Me(this.primaryColor,{h:330}),this.cScalePeer1=this.cScalePeer1||Ot(this.secondaryColor,45),this.cScalePeer2=this.cScalePeer2||Ot(this.tertiaryColor,40);for(let e=0;e{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},N$=o(t=>{let e=new ZC;return e.calculate(t),e},"getThemeVariables")});var JC,I$,O$=N(()=>{"use strict";Ys();o0();Ay();JC=class{static{o(this,"Theme")}constructor(){this.primaryColor="#eee",this.contrast="#707070",this.secondaryColor=Dt(this.contrast,55),this.background="#ffffff",this.tertiaryColor=Me(this.primaryColor,{h:-160}),this.primaryBorderColor=Ti(this.primaryColor,this.darkMode),this.secondaryBorderColor=Ti(this.secondaryColor,this.darkMode),this.tertiaryBorderColor=Ti(this.tertiaryColor,this.darkMode),this.primaryTextColor=wt(this.primaryColor),this.secondaryTextColor=wt(this.secondaryColor),this.tertiaryTextColor=wt(this.tertiaryColor),this.lineColor=wt(this.background),this.textColor=wt(this.background),this.mainBkg="#eee",this.secondBkg="calculated",this.lineColor="#666",this.border1="#999",this.border2="calculated",this.note="#ffa",this.text="#333",this.critical="#d42",this.done="#bbb",this.arrowheadColor="#333333",this.fontFamily='"trebuchet ms", verdana, arial, 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e=0;e{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},I$=o(t=>{let e=new JC;return e.calculate(t),e},"getThemeVariables")});var To,q4=N(()=>{"use strict";D$();R$();_y();M$();O$();To={base:{getThemeVariables:_$},dark:{getThemeVariables:L$},default:{getThemeVariables:oh},forest:{getThemeVariables:N$},neutral:{getThemeVariables:I$}}});var ql,P$=N(()=>{"use strict";ql={flowchart:{useMaxWidth:!0,titleTopMargin:25,subGraphTitleMargin:{top:0,bottom:0},diagramPadding:8,htmlLabels:!0,nodeSpacing:50,rankSpacing:50,curve:"basis",padding:15,defaultRenderer:"dagre-wrapper",wrappingWidth:200},sequence:{useMaxWidth:!0,hideUnusedParticipants:!1,activationWidth:10,diagramMarginX:50,diagramMarginY:10,actorMargin:50,width:150,height:65,boxMargin:10,boxTextMargin:5,noteMargin:10,messageMargin:35,messageAlign:"center",mirrorActors:!0,forceMenus:!1,bottomMarginAdj:1,rightAngles:!1,showSequenceNumbers:!1,actorFontSize:14,actorFontFamily:'"Open Sans", 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this.expect("}"),this.nextToken=r,n}parseExpression(e,r){for(var n=[];;){this.mode==="math"&&this.consumeSpaces();var i=this.fetch();if(t.endOfExpression.indexOf(i.text)!==-1||r&&i.text===r||e&&hh[i.text]&&hh[i.text].infix)break;var a=this.parseAtom(r);if(a){if(a.type==="internal")continue}else break;n.push(a)}return this.mode==="text"&&this.formLigatures(n),this.handleInfixNodes(n)}handleInfixNodes(e){for(var r=-1,n,i=0;i=0&&this.settings.reportNonstrict("unicodeTextInMathMode",'Latin-1/Unicode text character "'+r[0]+'" used in math mode',e);var l=An[this.mode][r].group,u=Xs.range(e),h;if(Mbe.hasOwnProperty(l)){var f=l;h={type:"atom",mode:this.mode,family:f,loc:u,text:r}}else h={type:l,mode:this.mode,loc:u,text:r};s=h}else if(r.charCodeAt(0)>=128)this.settings.strict&&($z(r.charCodeAt(0))?this.mode==="math"&&this.settings.reportNonstrict("unicodeTextInMathMode",'Unicode text character "'+r[0]+'" used in math mode',e):this.settings.reportNonstrict("unknownSymbol",'Unrecognized Unicode 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i=f2(n,"#");(this.options.pedantic||!i||this.rules.other.endingSpaceChar.test(i))&&(n=i.trim())}return{type:"heading",raw:r[0],depth:r[1].length,text:n,tokens:this.lexer.inline(n)}}}hr(e){let r=this.rules.block.hr.exec(e);if(r)return{type:"hr",raw:f2(r[0],` +`)}}blockquote(e){let r=this.rules.block.blockquote.exec(e);if(r){let n=f2(r[0],` +`).split(` +`),i="",a="",s=[];for(;n.length>0;){let l=!1,u=[],h;for(h=0;h1,a={type:"list",raw:"",ordered:i,start:i?+n.slice(0,-1):"",loose:!1,items:[]};n=i?`\\d{1,9}\\${n.slice(-1)}`:`\\${n}`,this.options.pedantic&&(n=i?n:"[*+-]");let s=this.rules.other.listItemRegex(n),l=!1;for(;e;){let h=!1,f="",d="";if(!(r=s.exec(e))||this.rules.block.hr.test(e))break;f=r[0],e=e.substring(f.length);let p=r[2].split(` +`,1)[0].replace(this.rules.other.listReplaceTabs,b=>" ".repeat(3*b.length)),m=e.split(` +`,1)[0],g=!p.trim(),y=0;if(this.options.pedantic?(y=2,d=p.trimStart()):g?y=r[1].length+1:(y=r[2].search(this.rules.other.nonSpaceChar),y=y>4?1:y,d=p.slice(y),y+=r[1].length),g&&this.rules.other.blankLine.test(m)&&(f+=m+` +`,e=e.substring(m.length+1),h=!0),!h){let b=this.rules.other.nextBulletRegex(y),w=this.rules.other.hrRegex(y),C=this.rules.other.fencesBeginRegex(y),T=this.rules.other.headingBeginRegex(y),E=this.rules.other.htmlBeginRegex(y);for(;e;){let A=e.split(` +`,1)[0],S;if(m=A,this.options.pedantic?(m=m.replace(this.rules.other.listReplaceNesting," "),S=m):S=m.replace(this.rules.other.tabCharGlobal," "),C.test(m)||T.test(m)||E.test(m)||b.test(m)||w.test(m))break;if(S.search(this.rules.other.nonSpaceChar)>=y||!m.trim())d+=` +`+S.slice(y);else{if(g||p.replace(this.rules.other.tabCharGlobal," ").search(this.rules.other.nonSpaceChar)>=4||C.test(p)||T.test(p)||w.test(p))break;d+=` +`+m}!g&&!m.trim()&&(g=!0),f+=A+` +`,e=e.substring(A.length+1),p=S.slice(y)}}a.loose||(l?a.loose=!0:this.rules.other.doubleBlankLine.test(f)&&(l=!0));let v=null,x;this.options.gfm&&(v=this.rules.other.listIsTask.exec(d),v&&(x=v[0]!=="[ ] ",d=d.replace(this.rules.other.listReplaceTask,""))),a.items.push({type:"list_item",raw:f,task:!!v,checked:x,loose:!1,text:d,tokens:[]}),a.raw+=f}let u=a.items.at(-1);if(u)u.raw=u.raw.trimEnd(),u.text=u.text.trimEnd();else return;a.raw=a.raw.trimEnd();for(let h=0;hp.type==="space"),d=f.length>0&&f.some(p=>this.rules.other.anyLine.test(p.raw));a.loose=d}if(a.loose)for(let h=0;h({text:u,tokens:this.lexer.inline(u),header:!1,align:s.align[h]})));return s}}lheading(e){let r=this.rules.block.lheading.exec(e);if(r)return{type:"heading",raw:r[0],depth:r[2].charAt(0)==="="?1:2,text:r[1],tokens:this.lexer.inline(r[1])}}paragraph(e){let r=this.rules.block.paragraph.exec(e);if(r){let n=r[1].charAt(r[1].length-1)===` +`?r[1].slice(0,-1):r[1];return{type:"paragraph",raw:r[0],text:n,tokens:this.lexer.inline(n)}}}text(e){let r=this.rules.block.text.exec(e);if(r)return{type:"text",raw:r[0],text:r[0],tokens:this.lexer.inline(r[0])}}escape(e){let r=this.rules.inline.escape.exec(e);if(r)return{type:"escape",raw:r[0],text:r[1]}}tag(e){let r=this.rules.inline.tag.exec(e);if(r)return!this.lexer.state.inLink&&this.rules.other.startATag.test(r[0])?this.lexer.state.inLink=!0:this.lexer.state.inLink&&this.rules.other.endATag.test(r[0])&&(this.lexer.state.inLink=!1),!this.lexer.state.inRawBlock&&this.rules.other.startPreScriptTag.test(r[0])?this.lexer.state.inRawBlock=!0:this.lexer.state.inRawBlock&&this.rules.other.endPreScriptTag.test(r[0])&&(this.lexer.state.inRawBlock=!1),{type:"html",raw:r[0],inLink:this.lexer.state.inLink,inRawBlock:this.lexer.state.inRawBlock,block:!1,text:r[0]}}link(e){let r=this.rules.inline.link.exec(e);if(r){let n=r[2].trim();if(!this.options.pedantic&&this.rules.other.startAngleBracket.test(n)){if(!this.rules.other.endAngleBracket.test(n))return;let s=f2(n.slice(0,-1),"\\");if((n.length-s.length)%2===0)return}else{let s=$8e(r[2],"()");if(s>-1){let u=(r[0].indexOf("!")===0?5:4)+r[1].length+s;r[2]=r[2].substring(0,s),r[0]=r[0].substring(0,u).trim(),r[3]=""}}let i=r[2],a="";if(this.options.pedantic){let s=this.rules.other.pedanticHrefTitle.exec(i);s&&(i=s[1],a=s[3])}else a=r[3]?r[3].slice(1,-1):"";return i=i.trim(),this.rules.other.startAngleBracket.test(i)&&(this.options.pedantic&&!this.rules.other.endAngleBracket.test(n)?i=i.slice(1):i=i.slice(1,-1)),zj(r,{href:i&&i.replace(this.rules.inline.anyPunctuation,"$1"),title:a&&a.replace(this.rules.inline.anyPunctuation,"$1")},r[0],this.lexer,this.rules)}}reflink(e,r){let n;if((n=this.rules.inline.reflink.exec(e))||(n=this.rules.inline.nolink.exec(e))){let i=(n[2]||n[1]).replace(this.rules.other.multipleSpaceGlobal," "),a=r[i.toLowerCase()];if(!a){let s=n[0].charAt(0);return{type:"text",raw:s,text:s}}return zj(n,a,n[0],this.lexer,this.rules)}}emStrong(e,r,n=""){let i=this.rules.inline.emStrongLDelim.exec(e);if(!i||i[3]&&n.match(this.rules.other.unicodeAlphaNumeric))return;if(!(i[1]||i[2]||"")||!n||this.rules.inline.punctuation.exec(n)){let s=[...i[0]].length-1,l,u,h=s,f=0,d=i[0][0]==="*"?this.rules.inline.emStrongRDelimAst:this.rules.inline.emStrongRDelimUnd;for(d.lastIndex=0,r=r.slice(-1*e.length+s);(i=d.exec(r))!=null;){if(l=i[1]||i[2]||i[3]||i[4]||i[5]||i[6],!l)continue;if(u=[...l].length,i[3]||i[4]){h+=u;continue}else if((i[5]||i[6])&&s%3&&!((s+u)%3)){f+=u;continue}if(h-=u,h>0)continue;u=Math.min(u,u+h+f);let p=[...i[0]][0].length,m=e.slice(0,s+i.index+p+u);if(Math.min(s,u)%2){let y=m.slice(1,-1);return{type:"em",raw:m,text:y,tokens:this.lexer.inlineTokens(y)}}let g=m.slice(2,-2);return{type:"strong",raw:m,text:g,tokens:this.lexer.inlineTokens(g)}}}}codespan(e){let r=this.rules.inline.code.exec(e);if(r){let n=r[2].replace(this.rules.other.newLineCharGlobal," "),i=this.rules.other.nonSpaceChar.test(n),a=this.rules.other.startingSpaceChar.test(n)&&this.rules.other.endingSpaceChar.test(n);return i&&a&&(n=n.substring(1,n.length-1)),{type:"codespan",raw:r[0],text:n}}}br(e){let r=this.rules.inline.br.exec(e);if(r)return{type:"br",raw:r[0]}}del(e){let r=this.rules.inline.del.exec(e);if(r)return{type:"del",raw:r[0],text:r[2],tokens:this.lexer.inlineTokens(r[2])}}autolink(e){let r=this.rules.inline.autolink.exec(e);if(r){let n,i;return r[2]==="@"?(n=r[1],i="mailto:"+n):(n=r[1],i=n),{type:"link",raw:r[0],text:n,href:i,tokens:[{type:"text",raw:n,text:n}]}}}url(e){let r;if(r=this.rules.inline.url.exec(e)){let n,i;if(r[2]==="@")n=r[0],i="mailto:"+n;else{let a;do a=r[0],r[0]=this.rules.inline._backpedal.exec(r[0])?.[0]??"";while(a!==r[0]);n=r[0],r[1]==="www."?i="http://"+r[0]:i=r[0]}return{type:"link",raw:r[0],text:n,href:i,tokens:[{type:"text",raw:n,text:n}]}}}inlineText(e){let r=this.rules.inline.text.exec(e);if(r){let n=this.lexer.state.inRawBlock;return{type:"text",raw:r[0],text:r[0],escaped:n}}}},Al=class t{static{o(this,"_Lexer")}tokens;options;state;tokenizer;inlineQueue;constructor(e){this.tokens=[],this.tokens.links=Object.create(null),this.options=e||Id,this.options.tokenizer=this.options.tokenizer||new hm,this.tokenizer=this.options.tokenizer,this.tokenizer.options=this.options,this.tokenizer.lexer=this,this.inlineQueue=[],this.state={inLink:!1,inRawBlock:!1,top:!0};let r={other:ts,block:Sw.normal,inline:h2.normal};this.options.pedantic?(r.block=Sw.pedantic,r.inline=h2.pedantic):this.options.gfm&&(r.block=Sw.gfm,this.options.breaks?r.inline=h2.breaks:r.inline=h2.gfm),this.tokenizer.rules=r}static get rules(){return{block:Sw,inline:h2}}static lex(e,r){return new t(r).lex(e)}static lexInline(e,r){return new t(r).inlineTokens(e)}lex(e){e=e.replace(ts.carriageReturn,` +`),this.blockTokens(e,this.tokens);for(let r=0;r(i=s.call({lexer:this},e,r))?(e=e.substring(i.raw.length),r.push(i),!0):!1))continue;if(i=this.tokenizer.space(e)){e=e.substring(i.raw.length);let s=r.at(-1);i.raw.length===1&&s!==void 0?s.raw+=` +`:r.push(i);continue}if(i=this.tokenizer.code(e)){e=e.substring(i.raw.length);let s=r.at(-1);s?.type==="paragraph"||s?.type==="text"?(s.raw+=` +`+i.raw,s.text+=` +`+i.text,this.inlineQueue.at(-1).src=s.text):r.push(i);continue}if(i=this.tokenizer.fences(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.heading(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.hr(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.blockquote(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.list(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.html(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.def(e)){e=e.substring(i.raw.length);let s=r.at(-1);s?.type==="paragraph"||s?.type==="text"?(s.raw+=` +`+i.raw,s.text+=` +`+i.raw,this.inlineQueue.at(-1).src=s.text):this.tokens.links[i.tag]||(this.tokens.links[i.tag]={href:i.href,title:i.title});continue}if(i=this.tokenizer.table(e)){e=e.substring(i.raw.length),r.push(i);continue}if(i=this.tokenizer.lheading(e)){e=e.substring(i.raw.length),r.push(i);continue}let a=e;if(this.options.extensions?.startBlock){let s=1/0,l=e.slice(1),u;this.options.extensions.startBlock.forEach(h=>{u=h.call({lexer:this},l),typeof u=="number"&&u>=0&&(s=Math.min(s,u))}),s<1/0&&s>=0&&(a=e.substring(0,s+1))}if(this.state.top&&(i=this.tokenizer.paragraph(a))){let s=r.at(-1);n&&s?.type==="paragraph"?(s.raw+=` +`+i.raw,s.text+=` +`+i.text,this.inlineQueue.pop(),this.inlineQueue.at(-1).src=s.text):r.push(i),n=a.length!==e.length,e=e.substring(i.raw.length);continue}if(i=this.tokenizer.text(e)){e=e.substring(i.raw.length);let s=r.at(-1);s?.type==="text"?(s.raw+=` +`+i.raw,s.text+=` +`+i.text,this.inlineQueue.pop(),this.inlineQueue.at(-1).src=s.text):r.push(i);continue}if(e){let s="Infinite loop on byte: "+e.charCodeAt(0);if(this.options.silent){console.error(s);break}else throw new Error(s)}}return this.state.top=!0,r}inline(e,r=[]){return this.inlineQueue.push({src:e,tokens:r}),r}inlineTokens(e,r=[]){let n=e,i=null;if(this.tokens.links){let l=Object.keys(this.tokens.links);if(l.length>0)for(;(i=this.tokenizer.rules.inline.reflinkSearch.exec(n))!=null;)l.includes(i[0].slice(i[0].lastIndexOf("[")+1,-1))&&(n=n.slice(0,i.index)+"["+"a".repeat(i[0].length-2)+"]"+n.slice(this.tokenizer.rules.inline.reflinkSearch.lastIndex))}for(;(i=this.tokenizer.rules.inline.blockSkip.exec(n))!=null;)n=n.slice(0,i.index)+"["+"a".repeat(i[0].length-2)+"]"+n.slice(this.tokenizer.rules.inline.blockSkip.lastIndex);for(;(i=this.tokenizer.rules.inline.anyPunctuation.exec(n))!=null;)n=n.slice(0,i.index)+"++"+n.slice(this.tokenizer.rules.inline.anyPunctuation.lastIndex);let a=!1,s="";for(;e;){a||(s=""),a=!1;let l;if(this.options.extensions?.inline?.some(h=>(l=h.call({lexer:this},e,r))?(e=e.substring(l.raw.length),r.push(l),!0):!1))continue;if(l=this.tokenizer.escape(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.tag(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.link(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.reflink(e,this.tokens.links)){e=e.substring(l.raw.length);let h=r.at(-1);l.type==="text"&&h?.type==="text"?(h.raw+=l.raw,h.text+=l.text):r.push(l);continue}if(l=this.tokenizer.emStrong(e,n,s)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.codespan(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.br(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.del(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.autolink(e)){e=e.substring(l.raw.length),r.push(l);continue}if(!this.state.inLink&&(l=this.tokenizer.url(e))){e=e.substring(l.raw.length),r.push(l);continue}let u=e;if(this.options.extensions?.startInline){let h=1/0,f=e.slice(1),d;this.options.extensions.startInline.forEach(p=>{d=p.call({lexer:this},f),typeof d=="number"&&d>=0&&(h=Math.min(h,d))}),h<1/0&&h>=0&&(u=e.substring(0,h+1))}if(l=this.tokenizer.inlineText(u)){e=e.substring(l.raw.length),l.raw.slice(-1)!=="_"&&(s=l.raw.slice(-1)),a=!0;let h=r.at(-1);h?.type==="text"?(h.raw+=l.raw,h.text+=l.text):r.push(l);continue}if(e){let h="Infinite loop on byte: "+e.charCodeAt(0);if(this.options.silent){console.error(h);break}else throw new Error(h)}}return r}},fm=class{static{o(this,"_Renderer")}options;parser;constructor(e){this.options=e||Id}space(e){return""}code({text:e,lang:r,escaped:n}){let i=(r||"").match(ts.notSpaceStart)?.[0],a=e.replace(ts.endingNewline,"")+` +`;return i?'
'+(n?a:pc(a,!0))+`
+`:"
"+(n?a:pc(a,!0))+`
+`}blockquote({tokens:e}){return`
+${this.parser.parse(e)}
+`}html({text:e}){return e}heading({tokens:e,depth:r}){return`${this.parser.parseInline(e)} +`}hr(e){return`
+`}list(e){let r=e.ordered,n=e.start,i="";for(let l=0;l +`+i+" +`}listitem(e){let r="";if(e.task){let n=this.checkbox({checked:!!e.checked});e.loose?e.tokens[0]?.type==="paragraph"?(e.tokens[0].text=n+" "+e.tokens[0].text,e.tokens[0].tokens&&e.tokens[0].tokens.length>0&&e.tokens[0].tokens[0].type==="text"&&(e.tokens[0].tokens[0].text=n+" "+pc(e.tokens[0].tokens[0].text),e.tokens[0].tokens[0].escaped=!0)):e.tokens.unshift({type:"text",raw:n+" ",text:n+" ",escaped:!0}):r+=n+" "}return r+=this.parser.parse(e.tokens,!!e.loose),`
  • ${r}
    • +`}checkbox({checked:e}){return"'}paragraph({tokens:e}){return`

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70:this.$=ye[Te-3],lt.addVertex(ye[Te-3],ye[Te-1],"lean_right");break;case 71:this.$=ye[Te-3],lt.addVertex(ye[Te-3],ye[Te-1],"lean_left");break;case 72:this.$=ye[Te],lt.addVertex(ye[Te]);break;case 73:ye[Te-1].text=ye[Te],this.$=ye[Te-1];break;case 74:case 75:ye[Te-2].text=ye[Te-1],this.$=ye[Te-2];break;case 76:this.$=ye[Te];break;case 77:var wi=lt.destructLink(ye[Te],ye[Te-2]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length,text:ye[Te-1]};break;case 78:var wi=lt.destructLink(ye[Te],ye[Te-2]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length,text:ye[Te-1],id:ye[Te-3]};break;case 79:this.$={text:ye[Te],type:"text"};break;case 80:this.$={text:ye[Te-1].text+""+ye[Te],type:ye[Te-1].type};break;case 81:this.$={text:ye[Te],type:"string"};break;case 82:this.$={text:ye[Te],type:"markdown"};break;case 83:var wi=lt.destructLink(ye[Te]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length};break;case 84:var wi=lt.destructLink(ye[Te]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length,id:ye[Te-1]};break;case 85:this.$=ye[Te-1];break;case 86:this.$={text:ye[Te],type:"text"};break;case 87:this.$={text:ye[Te-1].text+""+ye[Te],type:ye[Te-1].type};break;case 88:this.$={text:ye[Te],type:"string"};break;case 89:case 104:this.$={text:ye[Te],type:"markdown"};break;case 101:this.$={text:ye[Te],type:"text"};break;case 102:this.$={text:ye[Te-1].text+""+ye[Te],type:ye[Te-1].type};break;case 103:this.$={text:ye[Te],type:"text"};break;case 105:this.$=ye[Te-4],lt.addClass(ye[Te-2],ye[Te]);break;case 106:this.$=ye[Te-4],lt.setClass(ye[Te-2],ye[Te]);break;case 107:case 115:this.$=ye[Te-1],lt.setClickEvent(ye[Te-1],ye[Te]);break;case 108:case 116:this.$=ye[Te-3],lt.setClickEvent(ye[Te-3],ye[Te-2]),lt.setTooltip(ye[Te-3],ye[Te]);break;case 109:this.$=ye[Te-2],lt.setClickEvent(ye[Te-2],ye[Te-1],ye[Te]);break;case 110:this.$=ye[Te-4],lt.setClickEvent(ye[Te-4],ye[Te-3],ye[Te-2]),lt.setTooltip(ye[Te-4],ye[Te]);break;case 111:this.$=ye[Te-2],lt.setLink(ye[Te-2],ye[Te]);break;case 112:this.$=ye[Te-4],lt.setLink(ye[Te-4],ye[Te-2]),lt.setTooltip(ye[Te-4],ye[Te]);break;case 113:this.$=ye[Te-4],lt.setLink(ye[Te-4],ye[Te-2],ye[Te]);break;case 114:this.$=ye[Te-6],lt.setLink(ye[Te-6],ye[Te-4],ye[Te]),lt.setTooltip(ye[Te-6],ye[Te-2]);break;case 117:this.$=ye[Te-1],lt.setLink(ye[Te-1],ye[Te]);break;case 118:this.$=ye[Te-3],lt.setLink(ye[Te-3],ye[Te-2]),lt.setTooltip(ye[Te-3],ye[Te]);break;case 119:this.$=ye[Te-3],lt.setLink(ye[Te-3],ye[Te-2],ye[Te]);break;case 120:this.$=ye[Te-5],lt.setLink(ye[Te-5],ye[Te-4],ye[Te]),lt.setTooltip(ye[Te-5],ye[Te-2]);break;case 121:this.$=ye[Te-4],lt.addVertex(ye[Te-2],void 0,void 0,ye[Te]);break;case 122:this.$=ye[Te-4],lt.updateLink([ye[Te-2]],ye[Te]);break;case 123:this.$=ye[Te-4],lt.updateLink(ye[Te-2],ye[Te]);break;case 124:this.$=ye[Te-8],lt.updateLinkInterpolate([ye[Te-6]],ye[Te-2]),lt.updateLink([ye[Te-6]],ye[Te]);break;case 125:this.$=ye[Te-8],lt.updateLinkInterpolate(ye[Te-6],ye[Te-2]),lt.updateLink(ye[Te-6],ye[Te]);break;case 126:this.$=ye[Te-6],lt.updateLinkInterpolate([ye[Te-4]],ye[Te]);break;case 127:this.$=ye[Te-6],lt.updateLinkInterpolate(ye[Te-4],ye[Te]);break;case 128:case 130:this.$=[ye[Te]];break;case 129:case 131:ye[Te-2].push(ye[Te]),this.$=ye[Te-2];break;case 133:this.$=ye[Te-1]+ye[Te];break;case 181:this.$=ye[Te];break;case 182:this.$=ye[Te-1]+""+ye[Te];break;case 184:this.$=ye[Te-1]+""+ye[Te];break;case 185:this.$={stmt:"dir",value:"TB"};break;case 186:this.$={stmt:"dir",value:"BT"};break;case 187:this.$={stmt:"dir",value:"RL"};break;case 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this.yy=mt||this.yy||{},this._input=et,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var et=this._input[0];this.yytext+=et,this.yyleng++,this.offset++,this.match+=et,this.matched+=et;var mt=et.match(/(?:\r\n?|\n).*/g);return mt?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),et},"input"),unput:o(function(et){var mt=et.length,Kt=et.split(/(?:\r\n?|\n)/g);this._input=et+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-mt),this.offset-=mt;var lt=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),Kt.length-1&&(this.yylineno-=Kt.length-1);var Cn=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:Kt?(Kt.length===lt.length?this.yylloc.first_column:0)+lt[lt.length-Kt.length].length-Kt[0].length:this.yylloc.first_column-mt},this.options.ranges&&(this.yylloc.range=[Cn[0],Cn[0]+this.yyleng-mt]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). +`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(et){this.unput(this.match.slice(et))},"less"),pastInput:o(function(){var et=this.matched.substr(0,this.matched.length-this.match.length);return(et.length>20?"...":"")+et.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var et=this.match;return et.length<20&&(et+=this._input.substr(0,20-et.length)),(et.substr(0,20)+(et.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var et=this.pastInput(),mt=new Array(et.length+1).join("-");return et+this.upcomingInput()+` +`+mt+"^"},"showPosition"),test_match:o(function(et,mt){var Kt,lt,Cn;if(this.options.backtrack_lexer&&(Cn={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(Cn.yylloc.range=this.yylloc.range.slice(0))),lt=et[0].match(/(?:\r\n?|\n).*/g),lt&&(this.yylineno+=lt.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:lt?lt[lt.length-1].length-lt[lt.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+et[0].length},this.yytext+=et[0],this.match+=et[0],this.matches=et,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(et[0].length),this.matched+=et[0],Kt=this.performAction.call(this,this.yy,this,mt,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),Kt)return Kt;if(this._backtrack){for(var ye in Cn)this[ye]=Cn[ye];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var et,mt,Kt,lt;this._more||(this.yytext="",this.match="");for(var Cn=this._currentRules(),ye=0;yemt[0].length)){if(mt=Kt,lt=ye,this.options.backtrack_lexer){if(et=this.test_match(Kt,Cn[ye]),et!==!1)return et;if(this._backtrack){mt=!1;continue}else return!1}else if(!this.options.flex)break}return mt?(et=this.test_match(mt,Cn[lt]),et!==!1?et:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. +`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var mt=this.next();return mt||this.lex()},"lex"),begin:o(function(mt){this.conditionStack.push(mt)},"begin"),popState:o(function(){var mt=this.conditionStack.length-1;return mt>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(mt){return mt=this.conditionStack.length-1-Math.abs(mt||0),mt>=0?this.conditionStack[mt]:"INITIAL"},"topState"),pushState:o(function(mt){this.begin(mt)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{},performAction:o(function(mt,Kt,lt,Cn){var ye=Cn;switch(lt){case 0:return this.begin("acc_title"),34;break;case 1:return this.popState(),"acc_title_value";break;case 2:return this.begin("acc_descr"),36;break;case 3:return this.popState(),"acc_descr_value";break;case 4:this.begin("acc_descr_multiline");break;case 5:this.popState();break;case 6:return"acc_descr_multiline_value";case 7:return this.pushState("shapeData"),Kt.yytext="",40;break;case 8:return this.pushState("shapeDataStr"),40;break;case 9:return this.popState(),40;break;case 10:let Vf=/\n\s*/g;return Kt.yytext=Kt.yytext.replace(Vf,"
    "),40;break;case 11:return 40;case 12:this.popState();break;case 13:this.begin("callbackname");break;case 14:this.popState();break;case 15:this.popState(),this.begin("callbackargs");break;case 16:return 95;case 17:this.popState();break;case 18:return 96;case 19:return"MD_STR";case 20:this.popState();break;case 21:this.begin("md_string");break;case 22:return"STR";case 23:this.popState();break;case 24:this.pushState("string");break;case 25:return 84;case 26:return 102;case 27:return 85;case 28:return 104;case 29:return 86;case 30:return 87;case 31:return 97;case 32:this.begin("click");break;case 33:this.popState();break;case 34:return 88;case 35:return mt.lex.firstGraph()&&this.begin("dir"),12;break;case 36:return mt.lex.firstGraph()&&this.begin("dir"),12;break;case 37:return mt.lex.firstGraph()&&this.begin("dir"),12;break;case 38:return 27;case 39:return 32;case 40:return 98;case 41:return 98;case 42:return 98;case 43:return 98;case 44:return this.popState(),13;break;case 45:return this.popState(),14;break;case 46:return this.popState(),14;break;case 47:return this.popState(),14;break;case 48:return this.popState(),14;break;case 49:return this.popState(),14;break;case 50:return this.popState(),14;break;case 51:return this.popState(),14;break;case 52:return this.popState(),14;break;case 53:return this.popState(),14;break;case 54:return this.popState(),14;break;case 55:return 121;case 56:return 122;case 57:return 123;case 58:return 124;case 59:return 78;case 60:return 105;case 61:return 111;case 62:return 46;case 63:return 60;case 64:return 44;case 65:return 8;case 66:return 106;case 67:return 115;case 68:return this.popState(),77;break;case 69:return this.pushState("edgeText"),75;break;case 70:return 119;case 71:return this.popState(),77;break;case 72:return this.pushState("thickEdgeText"),75;break;case 73:return 119;case 74:return this.popState(),77;break;case 75:return this.pushState("dottedEdgeText"),75;break;case 76:return 119;case 77:return 77;case 78:return this.popState(),53;break;case 79:return"TEXT";case 80:return this.pushState("ellipseText"),52;break;case 81:return this.popState(),55;break;case 82:return this.pushState("text"),54;break;case 83:return this.popState(),57;break;case 84:return this.pushState("text"),56;break;case 85:return 58;case 86:return this.pushState("text"),67;break;case 87:return this.popState(),64;break;case 88:return this.pushState("text"),63;break;case 89:return this.popState(),49;break;case 90:return this.pushState("text"),48;break;case 91:return this.popState(),69;break;case 92:return this.popState(),71;break;case 93:return 117;case 94:return this.pushState("trapText"),68;break;case 95:return this.pushState("trapText"),70;break;case 96:return 118;case 97:return 67;case 98:return 90;case 99:return"SEP";case 100:return 89;case 101:return 115;case 102:return 111;case 103:return 44;case 104:return 109;case 105:return 114;case 106:return 116;case 107:return this.popState(),62;break;case 108:return this.pushState("text"),62;break;case 109:return this.popState(),51;break;case 110:return this.pushState("text"),50;break;case 111:return this.popState(),31;break;case 112:return this.pushState("text"),29;break;case 113:return this.popState(),66;break;case 114:return this.pushState("text"),65;break;case 115:return"TEXT";case 116:return"QUOTE";case 117:return 9;case 118:return 10;case 119:return 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.icon-shape .label { + text-anchor: middle; + } + // .flowchart-label .text-outer-tspan { + // text-anchor: middle; + // } + // .flowchart-label .text-inner-tspan { + // text-anchor: start; + // } + + .node .katex path { + fill: #000; + stroke: #000; + stroke-width: 1px; + } + + .rough-node .label,.node .label, .image-shape .label, .icon-shape .label { + text-align: center; + } + .node.clickable { + cursor: pointer; + } + + + .root .anchor path { + fill: ${t.lineColor} !important; + stroke-width: 0; + stroke: ${t.lineColor}; + } + + .arrowheadPath { + fill: ${t.arrowheadColor}; + } + + .edgePath .path { + stroke: ${t.lineColor}; + stroke-width: 2.0px; + } + + .flowchart-link { + stroke: ${t.lineColor}; + fill: none; + } + + .edgeLabel { + background-color: ${t.edgeLabelBackground}; + p { + background-color: ${t.edgeLabelBackground}; + } + rect { + opacity: 0.5; + background-color: ${t.edgeLabelBackground}; + fill: ${t.edgeLabelBackground}; + } + text-align: center; + } + + /* For html labels only */ + .labelBkg { + background-color: ${gOe(t.edgeLabelBackground,.5)}; + // background-color: + } + + .cluster rect { + fill: ${t.clusterBkg}; + stroke: ${t.clusterBorder}; + stroke-width: 1px; + } + + .cluster text { + fill: ${t.titleColor}; + } + + .cluster span { + color: ${t.titleColor}; + } + /* .cluster div { + color: ${t.titleColor}; + } */ + + div.mermaidTooltip { + position: absolute; + text-align: center; + max-width: 200px; + padding: 2px; + font-family: ${t.fontFamily}; + font-size: 12px; + background: ${t.tertiaryColor}; + border: 1px solid ${t.border2}; + border-radius: 2px; + pointer-events: none; + z-index: 100; + } + + .flowchartTitleText { + text-anchor: middle; + font-size: 18px; + fill: ${t.textColor}; + } + + rect.text { + fill: none; + stroke-width: 0; + } + + .icon-shape, .image-shape { + background-color: ${t.edgeLabelBackground}; + p { + background-color: ${t.edgeLabelBackground}; + padding: 2px; + } + rect { + opacity: 0.5; + background-color: ${t.edgeLabelBackground}; + fill: ${t.edgeLabelBackground}; + } + text-align: center; + } +`,"getStyles"),qie=yOe});var ik={};hr(ik,{diagram:()=>vOe});var vOe,ak=N(()=>{"use strict";zt();qZ();Gie();Wie();Yie();vOe={parser:Hie,get db(){return new Uw},renderer:zie,styles:qie,init:o(t=>{t.flowchart||(t.flowchart={}),t.layout&&Yy({layout:t.layout}),t.flowchart.arrowMarkerAbsolute=t.arrowMarkerAbsolute,Yy({flowchart:{arrowMarkerAbsolute:t.arrowMarkerAbsolute}})},"init")}});var wR,Zie,Jie=N(()=>{"use strict";wR=function(){var t=o(function(J,se,ue,Z){for(ue=ue||{},Z=J.length;Z--;ue[J[Z]]=se);return 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e=e.concat(_Pe(r)),e=e.concat(RPe(r)),e=e.concat(NPe(r)),e=e.concat(MPe(r)),e=e.concat(DPe(r)),e}function SPe(t){let e=Yr(t,i=>!Bt(i,lp)),r=Je(e,i=>({message:"Token Type: ->"+i.name+"<- missing static 'PATTERN' property",type:Yn.MISSING_PATTERN,tokenTypes:[i]})),n=Zh(t,e);return{errors:r,valid:n}}function CPe(t){let e=Yr(t,i=>{let a=i[lp];return!zo(a)&&!Si(a)&&!Bt(a,"exec")&&!yi(a)}),r=Je(e,i=>({message:"Token Type: ->"+i.name+"<- static 'PATTERN' can only be a RegExp, a Function matching the {CustomPatternMatcherFunc} type or an Object matching the {ICustomPattern} interface.",type:Yn.INVALID_PATTERN,tokenTypes:[i]})),n=Zh(t,e);return{errors:r,valid:n}}function _Pe(t){class e extends Mc{static{o(this,"EndAnchorFinder")}constructor(){super(...arguments),this.found=!1}visitEndAnchor(a){this.found=!0}}let r=Yr(t,i=>{let a=i.PATTERN;try{let s=Bg(a),l=new e;return l.visit(s),l.found}catch{return APe.test(a.source)}});return Je(r,i=>({message:`Unexpected RegExp Anchor Error: + Token Type: ->`+i.name+`<- static 'PATTERN' cannot contain end of input anchor '$' + See chevrotain.io/docs/guide/resolving_lexer_errors.html#ANCHORS for details.`,type:Yn.EOI_ANCHOR_FOUND,tokenTypes:[i]}))}function DPe(t){let e=Yr(t,n=>n.PATTERN.test(""));return Je(e,n=>({message:"Token Type: ->"+n.name+"<- static 'PATTERN' must not match an empty string",type:Yn.EMPTY_MATCH_PATTERN,tokenTypes:[n]}))}function RPe(t){class e extends Mc{static{o(this,"StartAnchorFinder")}constructor(){super(...arguments),this.found=!1}visitStartAnchor(a){this.found=!0}}let r=Yr(t,i=>{let a=i.PATTERN;try{let s=Bg(a),l=new e;return l.visit(s),l.found}catch{return LPe.test(a.source)}});return Je(r,i=>({message:`Unexpected RegExp Anchor Error: + Token Type: ->`+i.name+`<- static 'PATTERN' cannot contain start of input anchor '^' + See https://chevrotain.io/docs/guide/resolving_lexer_errors.html#ANCHORS for details.`,type:Yn.SOI_ANCHOR_FOUND,tokenTypes:[i]}))}function NPe(t){let e=Yr(t,n=>{let i=n[lp];return i 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->${i.name}<- static 'PUSH_MODE' value cannot refer to a Lexer Mode ->${i.PUSH_MODE}<-which does not exist`,type:Yn.PUSH_MODE_DOES_NOT_EXIST,tokenTypes:[i]}))}function PPe(t){let e=[],r=Xr(t,(n,i,a)=>{let s=i.PATTERN;return s===Xn.NA||(yi(s)?n.push({str:s,idx:a,tokenType:i}):zo(s)&&FPe(s)&&n.push({str:s.source,idx:a,tokenType:i})),n},[]);return Ae(t,(n,i)=>{Ae(r,({str:a,idx:s,tokenType:l})=>{if(i${l.name}<- can never be matched. +Because it appears AFTER the Token Type ->${n.name}<-in the lexer's definition. +See https://chevrotain.io/docs/guide/resolving_lexer_errors.html#UNREACHABLE`;e.push({message:u,type:Yn.UNREACHABLE_PATTERN,tokenTypes:[n,l]})}})}),e}function BPe(t,e){if(zo(e)){let r=e.exec(t);return r!==null&&r.index===0}else{if(Si(e))return e(t,0,[],{});if(Bt(e,"exec"))return e.exec(t,0,[],{});if(typeof e=="string")return e===t;throw Error("non exhaustive match")}}function FPe(t){return ns([".","\\","[","]","|","^","$","(",")","?","*","+","{"],r=>t.source.indexOf(r)!==-1)===void 0}function Gae(t){let e=t.ignoreCase?"i":"";return new RegExp(`^(?:${t.source})`,e)}function Vae(t){let e=t.ignoreCase?"iy":"y";return new RegExp(`${t.source}`,e)}function Wae(t,e,r){let n=[];return Bt(t,$g)||n.push({message:"A MultiMode Lexer cannot be initialized without a <"+$g+`> property in its definition +`,type:Yn.MULTI_MODE_LEXER_WITHOUT_DEFAULT_MODE}),Bt(t,Mk)||n.push({message:"A MultiMode Lexer cannot be initialized without a <"+Mk+`> property in its definition +`,type:Yn.MULTI_MODE_LEXER_WITHOUT_MODES_PROPERTY}),Bt(t,Mk)&&Bt(t,$g)&&!Bt(t.modes,t.defaultMode)&&n.push({message:`A MultiMode Lexer cannot be initialized with a ${$g}: <${t.defaultMode}>which does not exist +`,type:Yn.MULTI_MODE_LEXER_DEFAULT_MODE_VALUE_DOES_NOT_EXIST}),Bt(t,Mk)&&Ae(t.modes,(i,a)=>{Ae(i,(s,l)=>{if(pr(s))n.push({message:`A Lexer cannot be initialized using an undefined Token Type. Mode:<${a}> at index: <${l}> +`,type:Yn.LEXER_DEFINITION_CANNOT_CONTAIN_UNDEFINED});else if(Bt(s,"LONGER_ALT")){let u=Pt(s.LONGER_ALT)?s.LONGER_ALT:[s.LONGER_ALT];Ae(u,h=>{!pr(h)&&!qn(i,h)&&n.push({message:`A MultiMode Lexer cannot be initialized with a longer_alt <${h.name}> on token <${s.name}> outside of mode <${a}> +`,type:Yn.MULTI_MODE_LEXER_LONGER_ALT_NOT_IN_CURRENT_MODE})})}})}),n}function qae(t,e,r){let n=[],i=!1,a=Tc(qr(br(t.modes))),s=Jh(a,u=>u[lp]===Xn.NA),l=Qae(r);return e&&Ae(s,u=>{let h=Kae(u,l);if(h!==!1){let d={message:zPe(u,h),type:h.issue,tokenType:u};n.push(d)}else Bt(u,"LINE_BREAKS")?u.LINE_BREAKS===!0&&(i=!0):Nk(l,u.PATTERN)&&(i=!0)}),e&&!i&&n.push({message:`Warning: No LINE_BREAKS Found. + This Lexer has been defined to track line and column information, + But none of the Token Types can be identified as matching a line terminator. + See https://chevrotain.io/docs/guide/resolving_lexer_errors.html#LINE_BREAKS + for details.`,type:Yn.NO_LINE_BREAKS_FLAGS}),n}function Yae(t){let e={},r=zr(t);return Ae(r,n=>{let i=t[n];if(Pt(i))e[n]=[];else throw Error("non exhaustive match")}),e}function Xae(t){let e=t.PATTERN;if(zo(e))return!1;if(Si(e))return!0;if(Bt(e,"exec"))return!0;if(yi(e))return!1;throw Error("non exhaustive match")}function $Pe(t){return yi(t)&&t.length===1?t.charCodeAt(0):!1}function Kae(t,e){if(Bt(t,"LINE_BREAKS"))return!1;if(zo(t.PATTERN)){try{Nk(e,t.PATTERN)}catch(r){return{issue:Yn.IDENTIFY_TERMINATOR,errMsg:r.message}}return!1}else{if(yi(t.PATTERN))return!1;if(Xae(t))return{issue:Yn.CUSTOM_LINE_BREAK};throw Error("non exhaustive match")}}function zPe(t,e){if(e.issue===Yn.IDENTIFY_TERMINATOR)return`Warning: unable to identify line terminator usage in pattern. + The problem is in the <${t.name}> Token Type + Root cause: ${e.errMsg}. + For details See: https://chevrotain.io/docs/guide/resolving_lexer_errors.html#IDENTIFY_TERMINATOR`;if(e.issue===Yn.CUSTOM_LINE_BREAK)return`Warning: A Custom Token Pattern should specify the option. + The problem is in the <${t.name}> Token Type + For details See: https://chevrotain.io/docs/guide/resolving_lexer_errors.html#CUSTOM_LINE_BREAK`;throw Error("non exhaustive match")}function Qae(t){return Je(t,r=>yi(r)?r.charCodeAt(0):r)}function CN(t,e,r){t[e]===void 0?t[e]=[r]:t[e].push(r)}function Ic(t){return t255?255+~~(t/255):t}}var lp,$g,Mk,AN,APe,LPe,jae,Fg,Ik,SN=N(()=>{"use strict";j2();ix();qt();Og();zae();Lk();lp="PATTERN",$g="defaultMode",Mk="modes",AN=typeof new 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UPe(t){Ae(t,e=>{_N(e)||(ese[Zae]=e,e.tokenTypeIdx=Zae++),Jae(e)&&!Pt(e.CATEGORIES)&&(e.CATEGORIES=[e.CATEGORIES]),Jae(e)||(e.CATEGORIES=[]),qPe(e)||(e.categoryMatches=[]),YPe(e)||(e.categoryMatchesMap={})})}function HPe(t){Ae(t,e=>{e.categoryMatches=[],Ae(e.categoryMatchesMap,(r,n)=>{e.categoryMatches.push(ese[n].tokenTypeIdx)})})}function WPe(t){Ae(t,e=>{tse([],e)})}function tse(t,e){Ae(t,r=>{e.categoryMatchesMap[r.tokenTypeIdx]=!0}),Ae(e.CATEGORIES,r=>{let n=t.concat(e);qn(n,r)||tse(n,r)})}function _N(t){return Bt(t,"tokenTypeIdx")}function Jae(t){return Bt(t,"CATEGORIES")}function qPe(t){return Bt(t,"categoryMatches")}function YPe(t){return Bt(t,"categoryMatchesMap")}function rse(t){return Bt(t,"tokenTypeIdx")}var Zae,ese,cp=N(()=>{"use strict";qt();o(Pu,"tokenStructuredMatcher");o(zg,"tokenStructuredMatcherNoCategories");Zae=1,ese={};o(Bu,"augmentTokenTypes");o(VPe,"expandCategories");o(UPe,"assignTokenDefaultProps");o(HPe,"assignCategoriesTokensProp");o(WPe,"assignCategoriesMapProp");o(tse,"singleAssignCategoriesToksMap");o(_N,"hasShortKeyProperty");o(Jae,"hasCategoriesProperty");o(qPe,"hasExtendingTokensTypesProperty");o(YPe,"hasExtendingTokensTypesMapProperty");o(rse,"isTokenType")});var Gg,DN=N(()=>{"use strict";Gg={buildUnableToPopLexerModeMessage(t){return`Unable to pop Lexer Mode after encountering Token ->${t.image}<- The Mode Stack is empty`},buildUnexpectedCharactersMessage(t,e,r,n,i){return`unexpected character: ->${t.charAt(e)}<- at offset: ${e}, skipped ${r} characters.`}}});var Yn,ax,Xn,ix=N(()=>{"use strict";SN();qt();Og();cp();DN();Lk();(function(t){t[t.MISSING_PATTERN=0]="MISSING_PATTERN",t[t.INVALID_PATTERN=1]="INVALID_PATTERN",t[t.EOI_ANCHOR_FOUND=2]="EOI_ANCHOR_FOUND",t[t.UNSUPPORTED_FLAGS_FOUND=3]="UNSUPPORTED_FLAGS_FOUND",t[t.DUPLICATE_PATTERNS_FOUND=4]="DUPLICATE_PATTERNS_FOUND",t[t.INVALID_GROUP_TYPE_FOUND=5]="INVALID_GROUP_TYPE_FOUND",t[t.PUSH_MODE_DOES_NOT_EXIST=6]="PUSH_MODE_DOES_NOT_EXIST",t[t.MULTI_MODE_LEXER_WITHOUT_DEFAULT_MODE=7]="MULTI_MODE_LEXER_WITHOUT_DEFAULT_MODE",t[t.MULTI_MODE_LEXER_WITHOUT_MODES_PROPERTY=8]="MULTI_MODE_LEXER_WITHOUT_MODES_PROPERTY",t[t.MULTI_MODE_LEXER_DEFAULT_MODE_VALUE_DOES_NOT_EXIST=9]="MULTI_MODE_LEXER_DEFAULT_MODE_VALUE_DOES_NOT_EXIST",t[t.LEXER_DEFINITION_CANNOT_CONTAIN_UNDEFINED=10]="LEXER_DEFINITION_CANNOT_CONTAIN_UNDEFINED",t[t.SOI_ANCHOR_FOUND=11]="SOI_ANCHOR_FOUND",t[t.EMPTY_MATCH_PATTERN=12]="EMPTY_MATCH_PATTERN",t[t.NO_LINE_BREAKS_FLAGS=13]="NO_LINE_BREAKS_FLAGS",t[t.UNREACHABLE_PATTERN=14]="UNREACHABLE_PATTERN",t[t.IDENTIFY_TERMINATOR=15]="IDENTIFY_TERMINATOR",t[t.CUSTOM_LINE_BREAK=16]="CUSTOM_LINE_BREAK",t[t.MULTI_MODE_LEXER_LONGER_ALT_NOT_IN_CURRENT_MODE=17]="MULTI_MODE_LEXER_LONGER_ALT_NOT_IN_CURRENT_MODE"})(Yn||(Yn={}));ax={deferDefinitionErrorsHandling:!1,positionTracking:"full",lineTerminatorsPattern:/\n|\r\n?/g,lineTerminatorCharacters:[` +`,"\r"],ensureOptimizations:!1,safeMode:!1,errorMessageProvider:Gg,traceInitPerf:!1,skipValidations:!1,recoveryEnabled:!0};Object.freeze(ax);Xn=class{static{o(this,"Lexer")}constructor(e,r=ax){if(this.lexerDefinition=e,this.lexerDefinitionErrors=[],this.lexerDefinitionWarning=[],this.patternIdxToConfig={},this.charCodeToPatternIdxToConfig={},this.modes=[],this.emptyGroups={},this.trackStartLines=!0,this.trackEndLines=!0,this.hasCustom=!1,this.canModeBeOptimized={},this.TRACE_INIT=(i,a)=>{if(this.traceInitPerf===!0){this.traceInitIndent++;let s=new Array(this.traceInitIndent+1).join(" ");this.traceInitIndent <${i}>`);let{time:l,value:u}=tx(a),h=l>10?console.warn:console.log;return this.traceInitIndent time: ${l}ms`),this.traceInitIndent--,u}else return a()},typeof r=="boolean")throw Error(`The second argument to the Lexer constructor is now an ILexerConfig Object. +a boolean 2nd argument is no longer supported`);this.config=ma({},ax,r);let n=this.config.traceInitPerf;n===!0?(this.traceInitMaxIdent=1/0,this.traceInitPerf=!0):typeof n=="number"&&(this.traceInitMaxIdent=n,this.traceInitPerf=!0),this.traceInitIndent=-1,this.TRACE_INIT("Lexer Constructor",()=>{let i,a=!0;this.TRACE_INIT("Lexer Config handling",()=>{if(this.config.lineTerminatorsPattern===ax.lineTerminatorsPattern)this.config.lineTerminatorsPattern=jae;else if(this.config.lineTerminatorCharacters===ax.lineTerminatorCharacters)throw Error(`Error: Missing property on the Lexer config. + For details See: https://chevrotain.io/docs/guide/resolving_lexer_errors.html#MISSING_LINE_TERM_CHARS`);if(r.safeMode&&r.ensureOptimizations)throw Error('"safeMode" and "ensureOptimizations" flags are mutually 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h;this.TRACE_INIT("analyzeTokenTypes",()=>{h=Uae(l,{lineTerminatorCharacters:this.config.lineTerminatorCharacters,positionTracking:r.positionTracking,ensureOptimizations:r.ensureOptimizations,safeMode:r.safeMode,tracer:this.TRACE_INIT})}),this.patternIdxToConfig[u]=h.patternIdxToConfig,this.charCodeToPatternIdxToConfig[u]=h.charCodeToPatternIdxToConfig,this.emptyGroups=ma({},this.emptyGroups,h.emptyGroups),this.hasCustom=h.hasCustom||this.hasCustom,this.canModeBeOptimized[u]=h.canBeOptimized}})}),this.defaultMode=i.defaultMode,!ur(this.lexerDefinitionErrors)&&!this.config.deferDefinitionErrorsHandling){let u=Je(this.lexerDefinitionErrors,h=>h.message).join(`----------------------- +`);throw new Error(`Errors detected in definition of Lexer: +`+u)}Ae(this.lexerDefinitionWarning,l=>{ex(l.message)}),this.TRACE_INIT("Choosing sub-methods implementations",()=>{if(AN?(this.chopInput=ta,this.match=this.matchWithTest):(this.updateLastIndex=ni,this.match=this.matchWithExec),a&&(this.handleModes=ni),this.trackStartLines===!1&&(this.computeNewColumn=ta),this.trackEndLines===!1&&(this.updateTokenEndLineColumnLocation=ni),/full/i.test(this.config.positionTracking))this.createTokenInstance=this.createFullToken;else if(/onlyStart/i.test(this.config.positionTracking))this.createTokenInstance=this.createStartOnlyToken;else if(/onlyOffset/i.test(this.config.positionTracking))this.createTokenInstance=this.createOffsetOnlyToken;else throw Error(`Invalid config option: "${this.config.positionTracking}"`);this.hasCustom?(this.addToken=this.addTokenUsingPush,this.handlePayload=this.handlePayloadWithCustom):(this.addToken=this.addTokenUsingMemberAccess,this.handlePayload=this.handlePayloadNoCustom)}),this.TRACE_INIT("Failed Optimization Warnings",()=>{let l=Xr(this.canModeBeOptimized,(u,h,f)=>(h===!1&&u.push(f),u),[]);if(r.ensureOptimizations&&!ur(l))throw Error(`Lexer Modes: < ${l.join(", ")} > cannot be optimized. + Disable the "ensureOptimizations" lexer config flag to silently ignore this and run the lexer in an un-optimized mode. + Or inspect the console log for details on how to resolve these issues.`)}),this.TRACE_INIT("clearRegExpParserCache",()=>{Pae()}),this.TRACE_INIT("toFastProperties",()=>{rx(this)})})}tokenize(e,r=this.defaultMode){if(!ur(this.lexerDefinitionErrors)){let i=Je(this.lexerDefinitionErrors,a=>a.message).join(`----------------------- +`);throw new Error(`Unable to Tokenize because Errors detected in definition of Lexer: +`+i)}return this.tokenizeInternal(e,r)}tokenizeInternal(e,r){let n,i,a,s,l,u,h,f,d,p,m,g,y,v,x,b,w=e,C=w.length,T=0,E=0,A=this.hasCustom?0:Math.floor(e.length/10),S=new Array(A),_=[],I=this.trackStartLines?1:void 0,D=this.trackStartLines?1:void 0,k=Yae(this.emptyGroups),L=this.trackStartLines,R=this.config.lineTerminatorsPattern,O=0,M=[],B=[],F=[],P=[];Object.freeze(P);let z;function $(){return M}o($,"getPossiblePatternsSlow");function H(le){let he=Ic(le),K=B[he];return K===void 0?P:K}o(H,"getPossiblePatternsOptimized");let Q=o(le=>{if(F.length===1&&le.tokenType.PUSH_MODE===void 0){let he=this.config.errorMessageProvider.buildUnableToPopLexerModeMessage(le);_.push({offset:le.startOffset,line:le.startLine,column:le.startColumn,length:le.image.length,message:he})}else{F.pop();let he=ga(F);M=this.patternIdxToConfig[he],B=this.charCodeToPatternIdxToConfig[he],O=M.length;let K=this.canModeBeOptimized[he]&&this.config.safeMode===!1;B&&K?z=H:z=$}},"pop_mode");function j(le){F.push(le),B=this.charCodeToPatternIdxToConfig[le],M=this.patternIdxToConfig[le],O=M.length,O=M.length;let he=this.canModeBeOptimized[le]&&this.config.safeMode===!1;B&&he?z=H:z=$}o(j,"push_mode"),j.call(this,r);let ie,ne=this.config.recoveryEnabled;for(;Tu.length){u=s,h=f,ie=se;break}}}break}}if(u!==null){if(d=u.length,p=ie.group,p!==void 0&&(m=ie.tokenTypeIdx,g=this.createTokenInstance(u,T,m,ie.tokenType,I,D,d),this.handlePayload(g,h),p===!1?E=this.addToken(S,E,g):k[p].push(g)),e=this.chopInput(e,d),T=T+d,D=this.computeNewColumn(D,d),L===!0&&ie.canLineTerminator===!0){let X=0,te,J;R.lastIndex=0;do te=R.test(u),te===!0&&(J=R.lastIndex-1,X++);while(te===!0);X!==0&&(I=I+X,D=d-J,this.updateTokenEndLineColumnLocation(g,p,J,X,I,D,d))}this.handleModes(ie,Q,j,g)}else{let X=T,te=I,J=D,se=ne===!1;for(;se===!1&&T{"use strict";qt();ix();cp();o(Fu,"tokenLabel");o(LN,"hasTokenLabel");XPe="parent",nse="categories",ise="label",ase="group",sse="push_mode",ose="pop_mode",lse="longer_alt",cse="line_breaks",use="start_chars_hint";o(of,"createToken");o(jPe,"createTokenInternal");lo=of({name:"EOF",pattern:Xn.NA});Bu([lo]);o($u,"createTokenInstance");o(sx,"tokenMatcher")});var zu,hse,Pl,Vg=N(()=>{"use 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<${Je(t,h=>`[${Je(h,f=>Fu(f)).join(",")}]`).join(" ,")}>`;return i+u+s}}};Object.freeze(zu);hse={buildRuleNotFoundError(t,e){return"Invalid grammar, reference to a rule which is not defined: ->"+e.nonTerminalName+`<- +inside top level rule: ->`+t.name+"<-"}},Pl={buildDuplicateFoundError(t,e){function r(f){return f instanceof kr?f.terminalType.name:f instanceof on?f.nonTerminalName:""}o(r,"getExtraProductionArgument");let n=t.name,i=ia(e),a=i.idx,s=Bs(i),l=r(i),u=a>0,h=`->${s}${u?a:""}<- ${l?`with argument: ->${l}<-`:""} + appears more than once (${e.length} times) in the top level rule: ->${n}<-. + For further details see: https://chevrotain.io/docs/FAQ.html#NUMERICAL_SUFFIXES + `;return h=h.replace(/[ \t]+/g," "),h=h.replace(/\s\s+/g,` +`),h},buildNamespaceConflictError(t){return`Namespace conflict found in grammar. +The grammar has both a Terminal(Token) and a Non-Terminal(Rule) named: <${t.name}>. +To resolve this make sure each Terminal and Non-Terminal names are unique +This is easy to accomplish by using the convention that Terminal names start with an uppercase letter +and Non-Terminal names start with a lower case letter.`},buildAlternationPrefixAmbiguityError(t){let e=Je(t.prefixPath,i=>Fu(i)).join(", "),r=t.alternation.idx===0?"":t.alternation.idx;return`Ambiguous alternatives: <${t.ambiguityIndices.join(" ,")}> due to common lookahead prefix +in inside <${t.topLevelRule.name}> Rule, +<${e}> may appears as a prefix path in all these alternatives. +See: https://chevrotain.io/docs/guide/resolving_grammar_errors.html#COMMON_PREFIX +For Further details.`},buildAlternationAmbiguityError(t){let e=Je(t.prefixPath,i=>Fu(i)).join(", "),r=t.alternation.idx===0?"":t.alternation.idx,n=`Ambiguous Alternatives Detected: <${t.ambiguityIndices.join(" ,")}> in inside <${t.topLevelRule.name}> Rule, +<${e}> may appears as a prefix path in all these alternatives. +`;return n=n+`See: https://chevrotain.io/docs/guide/resolving_grammar_errors.html#AMBIGUOUS_ALTERNATIVES +For Further details.`,n},buildEmptyRepetitionError(t){let e=Bs(t.repetition);return t.repetition.idx!==0&&(e+=t.repetition.idx),`The repetition <${e}> within Rule <${t.topLevelRule.name}> can never consume any tokens. +This could lead to an infinite loop.`},buildTokenNameError(t){return"deprecated"},buildEmptyAlternationError(t){return`Ambiguous empty alternative: <${t.emptyChoiceIdx+1}> in inside <${t.topLevelRule.name}> Rule. +Only the last alternative may be an empty alternative.`},buildTooManyAlternativesError(t){return`An Alternation cannot have more than 256 alternatives: + inside <${t.topLevelRule.name}> Rule. + has ${t.alternation.definition.length+1} alternatives.`},buildLeftRecursionError(t){let e=t.topLevelRule.name,r=Je(t.leftRecursionPath,a=>a.name),n=`${e} --> ${r.concat([e]).join(" --> ")}`;return`Left Recursion found in grammar. +rule: <${e}> can be invoked from itself (directly or indirectly) +without consuming any Tokens. The grammar path that causes this is: + ${n} + To fix this refactor your grammar to remove the left recursion. +see: https://en.wikipedia.org/wiki/LL_parser#Left_factoring.`},buildInvalidRuleNameError(t){return"deprecated"},buildDuplicateRuleNameError(t){let e;return t.topLevelRule instanceof as?e=t.topLevelRule.name:e=t.topLevelRule,`Duplicate definition, rule: ->${e}<- is already defined in the grammar: ->${t.grammarName}<-`}}});function fse(t,e){let r=new RN(t,e);return r.resolveRefs(),r.errors}var RN,dse=N(()=>{"use strict";Fs();qt();os();o(fse,"resolveGrammar");RN=class extends ss{static{o(this,"GastRefResolverVisitor")}constructor(e,r){super(),this.nameToTopRule=e,this.errMsgProvider=r,this.errors=[]}resolveRefs(){Ae(br(this.nameToTopRule),e=>{this.currTopLevel=e,e.accept(this)})}visitNonTerminal(e){let r=this.nameToTopRule[e.nonTerminalName];if(r)e.referencedRule=r;else{let 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this.ruleStack=an(this.path.ruleStack).reverse(),this.occurrenceStack=an(this.path.occurrenceStack).reverse(),this.ruleStack.pop(),this.occurrenceStack.pop(),this.updateExpectedNext(),this.walk(this.topProd),this.possibleTokTypes}walk(e,r=[]){this.found||super.walk(e,r)}walkProdRef(e,r,n){if(e.referencedRule.name===this.nextProductionName&&e.idx===this.nextProductionOccurrence){let i=r.concat(n);this.updateExpectedNext(),this.walk(e.referencedRule,i)}}updateExpectedNext(){ur(this.ruleStack)?(this.nextProductionName="",this.nextProductionOccurrence=0,this.isAtEndOfPath=!0):(this.nextProductionName=this.ruleStack.pop(),this.nextProductionOccurrence=this.occurrenceStack.pop())}},Ok=class extends NN{static{o(this,"NextAfterTokenWalker")}constructor(e,r){super(e,r),this.path=r,this.nextTerminalName="",this.nextTerminalOccurrence=0,this.nextTerminalName=this.path.lastTok.name,this.nextTerminalOccurrence=this.path.lastTokOccurrence}walkTerminal(e,r,n){if(this.isAtEndOfPath&&e.terminalType.name===this.nextTerminalName&&e.idx===this.nextTerminalOccurrence&&!this.found){let i=r.concat(n),a=new Dn({definition:i});this.possibleTokTypes=op(a),this.found=!0}}},Ug=class extends Ou{static{o(this,"AbstractNextTerminalAfterProductionWalker")}constructor(e,r){super(),this.topRule=e,this.occurrence=r,this.result={token:void 0,occurrence:void 0,isEndOfRule:void 0}}startWalking(){return this.walk(this.topRule),this.result}},Pk=class extends Ug{static{o(this,"NextTerminalAfterManyWalker")}walkMany(e,r,n){if(e.idx===this.occurrence){let i=ia(r.concat(n));this.result.isEndOfRule=i===void 0,i instanceof kr&&(this.result.token=i.terminalType,this.result.occurrence=i.idx)}else super.walkMany(e,r,n)}},ox=class extends Ug{static{o(this,"NextTerminalAfterManySepWalker")}walkManySep(e,r,n){if(e.idx===this.occurrence){let i=ia(r.concat(n));this.result.isEndOfRule=i===void 0,i instanceof kr&&(this.result.token=i.terminalType,this.result.occurrence=i.idx)}else super.walkManySep(e,r,n)}},Bk=class extends Ug{static{o(this,"NextTerminalAfterAtLeastOneWalker")}walkAtLeastOne(e,r,n){if(e.idx===this.occurrence){let i=ia(r.concat(n));this.result.isEndOfRule=i===void 0,i instanceof kr&&(this.result.token=i.terminalType,this.result.occurrence=i.idx)}else super.walkAtLeastOne(e,r,n)}},lx=class extends Ug{static{o(this,"NextTerminalAfterAtLeastOneSepWalker")}walkAtLeastOneSep(e,r,n){if(e.idx===this.occurrence){let i=ia(r.concat(n));this.result.isEndOfRule=i===void 0,i instanceof kr&&(this.result.token=i.terminalType,this.result.occurrence=i.idx)}else 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l=Je(s,u=>u.GATE);for(let u=0;uqr(u)),l=Xr(s,(u,h,f)=>(Ae(h,d=>{Bt(u,d.tokenTypeIdx)||(u[d.tokenTypeIdx]=f),Ae(d.categoryMatches,p=>{Bt(u,p)||(u[p]=f)})}),u),{});return function(){let u=this.LA(1);return l[u.tokenTypeIdx]}}else return function(){for(let s=0;sa.length===1),i=t.length;if(n&&!r){let a=qr(t);if(a.length===1&&ur(a[0].categoryMatches)){let l=a[0].tokenTypeIdx;return function(){return this.LA(1).tokenTypeIdx===l}}else{let s=Xr(a,(l,u,h)=>(l[u.tokenTypeIdx]=!0,Ae(u.categoryMatches,f=>{l[f]=!0}),l),[]);return function(){let l=this.LA(1);return s[l.tokenTypeIdx]===!0}}}else return function(){e:for(let a=0;aFk([s],1)),n=pse(r.length),i=Je(r,s=>{let l={};return Ae(s,u=>{let h=MN(u.partialPath);Ae(h,f=>{l[f]=!0})}),l}),a=r;for(let s=1;s<=e;s++){let l=a;a=pse(l.length);for(let u=0;u{let x=MN(v.partialPath);Ae(x,b=>{i[u][b]=!0})})}}}}return n}function Hg(t,e,r,n){let i=new zk(t,jn.ALTERNATION,n);return e.accept(i),xse(i.result,r)}function Wg(t,e,r,n){let i=new zk(t,r);e.accept(i);let a=i.result,l=new IN(e,t,r).startWalking(),u=new Dn({definition:a}),h=new Dn({definition:l});return xse([u,h],n)}function Vk(t,e){e:for(let r=0;r{let i=e[n];return r===i||i.categoryMatchesMap[r.tokenTypeIdx]})}function wse(t){return Ma(t,e=>Ma(e,r=>Ma(r,n=>ur(n.categoryMatches))))}var jn,IN,zk,qg=N(()=>{"use strict";qt();cx();Ak();cp();os();(function(t){t[t.OPTION=0]="OPTION",t[t.REPETITION=1]="REPETITION",t[t.REPETITION_MANDATORY=2]="REPETITION_MANDATORY",t[t.REPETITION_MANDATORY_WITH_SEPARATOR=3]="REPETITION_MANDATORY_WITH_SEPARATOR",t[t.REPETITION_WITH_SEPARATOR=4]="REPETITION_WITH_SEPARATOR",t[t.ALTERNATION=5]="ALTERNATION"})(jn||(jn={}));o(ux,"getProdType");o(Gk,"getLookaheadPaths");o(mse,"buildLookaheadFuncForOr");o(gse,"buildLookaheadFuncForOptionalProd");o(yse,"buildAlternativesLookAheadFunc");o(vse,"buildSingleAlternativeLookaheadFunction");IN=class extends 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i=ya(t,u=>ZPe(u,r)),a=iBe(t,e,r),s=ya(t,u=>tBe(u,r)),l=ya(t,u=>eBe(u,t,n,r));return i.concat(a,s,l)}function ZPe(t,e){let r=new ON;t.accept(r);let n=r.allProductions,i=IL(n,JPe),a=Os(i,l=>l.length>1);return Je(br(a),l=>{let u=ia(l),h=e.buildDuplicateFoundError(t,l),f=Bs(u),d={message:h,type:zi.DUPLICATE_PRODUCTIONS,ruleName:t.name,dslName:f,occurrence:u.idx},p=Ese(u);return p&&(d.parameter=p),d})}function JPe(t){return`${Bs(t)}_#_${t.idx}_#_${Ese(t)}`}function Ese(t){return t instanceof kr?t.terminalType.name:t instanceof on?t.nonTerminalName:""}function eBe(t,e,r,n){let i=[];if(Xr(e,(s,l)=>l.name===t.name?s+1:s,0)>1){let s=n.buildDuplicateRuleNameError({topLevelRule:t,grammarName:r});i.push({message:s,type:zi.DUPLICATE_RULE_NAME,ruleName:t.name})}return i}function Sse(t,e,r){let n=[],i;return qn(e,t)||(i=`Invalid rule override, rule: ->${t}<- cannot be overridden in the grammar: ->${r}<-as it is not defined in any of the super grammars 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ur(h)?[{message:e.buildEmptyAlternationError({topLevelRule:t,alternation:a,emptyChoiceIdx:u}),type:zi.NONE_LAST_EMPTY_ALT,ruleName:t.name,occurrence:a.idx,alternative:u+1}]:[]})})}function Ase(t,e,r){let n=new hx;t.accept(n);let i=n.alternations;return i=Jh(i,s=>s.ignoreAmbiguities===!0),ya(i,s=>{let l=s.idx,u=s.maxLookahead||e,h=Hg(l,t,u,s),f=rBe(h,s,t,r),d=nBe(h,s,t,r);return f.concat(d)})}function tBe(t,e){let r=new hx;t.accept(r);let n=r.alternations;return ya(n,a=>a.definition.length>255?[{message:e.buildTooManyAlternativesError({topLevelRule:t,alternation:a}),type:zi.TOO_MANY_ALTS,ruleName:t.name,occurrence:a.idx}]:[])}function _se(t,e,r){let n=[];return Ae(t,i=>{let a=new PN;i.accept(a);let s=a.allProductions;Ae(s,l=>{let u=ux(l),h=l.maxLookahead||e,f=l.idx,p=Wg(f,i,u,h)[0];if(ur(qr(p))){let m=r.buildEmptyRepetitionError({topLevelRule:i,repetition:l});n.push({message:m,type:zi.NO_NON_EMPTY_LOOKAHEAD,ruleName:i.name})}})}),n}function rBe(t,e,r,n){let i=[],a=Xr(t,(l,u,h)=>(e.definition[h].ignoreAmbiguities===!0||Ae(u,f=>{let d=[h];Ae(t,(p,m)=>{h!==m&&Vk(p,f)&&e.definition[m].ignoreAmbiguities!==!0&&d.push(m)}),d.length>1&&!Vk(i,f)&&(i.push(f),l.push({alts:d,path:f}))}),l),[]);return Je(a,l=>{let u=Je(l.alts,f=>f+1);return{message:n.buildAlternationAmbiguityError({topLevelRule:r,alternation:e,ambiguityIndices:u,prefixPath:l.path}),type:zi.AMBIGUOUS_ALTS,ruleName:r.name,occurrence:e.idx,alternatives:l.alts}})}function nBe(t,e,r,n){let i=Xr(t,(s,l,u)=>{let h=Je(l,f=>({idx:u,path:f}));return s.concat(h)},[]);return Tc(ya(i,s=>{if(e.definition[s.idx].ignoreAmbiguities===!0)return[];let u=s.idx,h=s.path,f=Yr(i,p=>e.definition[p.idx].ignoreAmbiguities!==!0&&p.idx{let m=[p.idx+1,u+1],g=e.idx===0?"":e.idx;return{message:n.buildAlternationPrefixAmbiguityError({topLevelRule:r,alternation:e,ambiguityIndices:m,prefixPath:p.path}),type:zi.AMBIGUOUS_PREFIX_ALTS,ruleName:r.name,occurrence:g,alternatives:m}})}))}function iBe(t,e,r){let n=[],i=Je(e,a=>a.name);return Ae(t,a=>{let s=a.name;if(qn(i,s)){let l=r.buildNamespaceConflictError(a);n.push({message:l,type:zi.CONFLICT_TOKENS_RULES_NAMESPACE,ruleName:s})}}),n}var ON,hx,PN,fx=N(()=>{"use strict";qt();Fs();os();qg();cx();cp();o(Tse,"validateLookahead");o(kse,"validateGrammar");o(ZPe,"validateDuplicateProductions");o(JPe,"identifyProductionForDuplicates");o(Ese,"getExtraProductionArgument");ON=class extends ss{static{o(this,"OccurrenceValidationCollector")}constructor(){super(...arguments),this.allProductions=[]}visitNonTerminal(e){this.allProductions.push(e)}visitOption(e){this.allProductions.push(e)}visitRepetitionWithSeparator(e){this.allProductions.push(e)}visitRepetitionMandatory(e){this.allProductions.push(e)}visitRepetitionMandatoryWithSeparator(e){this.allProductions.push(e)}visitRepetition(e){this.allProductions.push(e)}visitAlternation(e){this.allProductions.push(e)}visitTerminal(e){this.allProductions.push(e)}};o(eBe,"validateRuleDoesNotAlreadyExist");o(Sse,"validateRuleIsOverridden");o(BN,"validateNoLeftRecursion");o(Uk,"getFirstNoneTerminal");hx=class extends ss{static{o(this,"OrCollector")}constructor(){super(...arguments),this.alternations=[]}visitAlternation(e){this.alternations.push(e)}};o(Cse,"validateEmptyOrAlternative");o(Ase,"validateAmbiguousAlternationAlternatives");PN=class extends ss{static{o(this,"RepetitionCollector")}constructor(){super(...arguments),this.allProductions=[]}visitRepetitionWithSeparator(e){this.allProductions.push(e)}visitRepetitionMandatory(e){this.allProductions.push(e)}visitRepetitionMandatoryWithSeparator(e){this.allProductions.push(e)}visitRepetition(e){this.allProductions.push(e)}};o(tBe,"validateTooManyAlts");o(_se,"validateSomeNonEmptyLookaheadPath");o(rBe,"checkAlternativesAmbiguities");o(nBe,"checkPrefixAlternativesAmbiguities");o(iBe,"checkTerminalAndNoneTerminalsNameSpace")});function Dse(t){let e=Qh(t,{errMsgProvider:hse}),r={};return Ae(t.rules,n=>{r[n.name]=n}),fse(r,e.errMsgProvider)}function Lse(t){return t=Qh(t,{errMsgProvider:Pl}),kse(t.rules,t.tokenTypes,t.errMsgProvider,t.grammarName)}var Rse=N(()=>{"use strict";qt();dse();fx();Vg();o(Dse,"resolveGrammar");o(Lse,"validateGrammar")});function lf(t){return qn(Pse,t.name)}var Nse,Mse,Ise,Ose,Pse,Yg,hp,dx,px,mx,Xg=N(()=>{"use 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l=this.getKeyForAutomaticLookahead(n,i),u=this.firstAfterRepMap[l];if(u===void 0){let p=this.getCurrRuleFullName(),m=this.getGAstProductions()[p];u=new a(m,i).startWalking(),this.firstAfterRepMap[l]=u}let h=u.token,f=u.occurrence,d=u.isEndOfRule;this.RULE_STACK.length===1&&d&&h===void 0&&(h=lo,f=1),!(h===void 0||f===void 0)&&this.shouldInRepetitionRecoveryBeTried(h,f,s)&&this.tryInRepetitionRecovery(t,e,r,h)}var FN,zN,$N,Hk,GN=N(()=>{"use strict";up();qt();Xg();bN();Fs();FN={},zN="InRuleRecoveryException",$N=class extends Error{static{o(this,"InRuleRecoveryException")}constructor(e){super(e),this.name=zN}},Hk=class{static{o(this,"Recoverable")}initRecoverable(e){this.firstAfterRepMap={},this.resyncFollows={},this.recoveryEnabled=Bt(e,"recoveryEnabled")?e.recoveryEnabled:ls.recoveryEnabled,this.recoveryEnabled&&(this.attemptInRepetitionRecovery=aBe)}getTokenToInsert(e){let r=$u(e,"",NaN,NaN,NaN,NaN,NaN,NaN);return r.isInsertedInRecovery=!0,r}canTokenTypeBeInsertedInRecovery(e){return!0}canTokenTypeBeDeletedInRecovery(e){return!0}tryInRepetitionRecovery(e,r,n,i){let a=this.findReSyncTokenType(),s=this.exportLexerState(),l=[],u=!1,h=this.LA(1),f=this.LA(1),d=o(()=>{let p=this.LA(0),m=this.errorMessageProvider.buildMismatchTokenMessage({expected:i,actual:h,previous:p,ruleName:this.getCurrRuleFullName()}),g=new hp(m,h,this.LA(0));g.resyncedTokens=Nu(l),this.SAVE_ERROR(g)},"generateErrorMessage");for(;!u;)if(this.tokenMatcher(f,i)){d();return}else if(n.call(this)){d(),e.apply(this,r);return}else this.tokenMatcher(f,a)?u=!0:(f=this.SKIP_TOKEN(),this.addToResyncTokens(f,l));this.importLexerState(s)}shouldInRepetitionRecoveryBeTried(e,r,n){return!(n===!1||this.tokenMatcher(this.LA(1),e)||this.isBackTracking()||this.canPerformInRuleRecovery(e,this.getFollowsForInRuleRecovery(e,r)))}getFollowsForInRuleRecovery(e,r){let n=this.getCurrentGrammarPath(e,r);return this.getNextPossibleTokenTypes(n)}tryInRuleRecovery(e,r){if(this.canRecoverWithSingleTokenInsertion(e,r))return this.getTokenToInsert(e);if(this.canRecoverWithSingleTokenDeletion(e)){let n=this.SKIP_TOKEN();return this.consumeToken(),n}throw new $N("sad sad panda")}canPerformInRuleRecovery(e,r){return this.canRecoverWithSingleTokenInsertion(e,r)||this.canRecoverWithSingleTokenDeletion(e)}canRecoverWithSingleTokenInsertion(e,r){if(!this.canTokenTypeBeInsertedInRecovery(e)||ur(r))return!1;let n=this.LA(1);return ns(r,a=>this.tokenMatcher(n,a))!==void 0}canRecoverWithSingleTokenDeletion(e){return this.canTokenTypeBeDeletedInRecovery(e)?this.tokenMatcher(this.LA(2),e):!1}isInCurrentRuleReSyncSet(e){let r=this.getCurrFollowKey(),n=this.getFollowSetFromFollowKey(r);return qn(n,e)}findReSyncTokenType(){let e=this.flattenFollowSet(),r=this.LA(1),n=2;for(;;){let i=ns(e,a=>sx(r,a));if(i!==void 0)return i;r=this.LA(n),n++}}getCurrFollowKey(){if(this.RULE_STACK.length===1)return FN;let e=this.getLastExplicitRuleShortName(),r=this.getLastExplicitRuleOccurrenceIndex(),n=this.getPreviousExplicitRuleShortName();return{ruleName:this.shortRuleNameToFullName(e),idxInCallingRule:r,inRule:this.shortRuleNameToFullName(n)}}buildFullFollowKeyStack(){let e=this.RULE_STACK,r=this.RULE_OCCURRENCE_STACK;return Je(e,(n,i)=>i===0?FN:{ruleName:this.shortRuleNameToFullName(n),idxInCallingRule:r[i],inRule:this.shortRuleNameToFullName(e[i-1])})}flattenFollowSet(){let e=Je(this.buildFullFollowKeyStack(),r=>this.getFollowSetFromFollowKey(r));return qr(e)}getFollowSetFromFollowKey(e){if(e===FN)return[lo];let r=e.ruleName+e.idxInCallingRule+_k+e.inRule;return this.resyncFollows[r]}addToResyncTokens(e,r){return this.tokenMatcher(e,lo)||r.push(e),r}reSyncTo(e){let r=[],n=this.LA(1);for(;this.tokenMatcher(n,e)===!1;)n=this.SKIP_TOKEN(),this.addToResyncTokens(n,r);return Nu(r)}attemptInRepetitionRecovery(e,r,n,i,a,s,l){}getCurrentGrammarPath(e,r){let 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ss{static{o(this,"DslMethodsCollectorVisitor")}constructor(){super(...arguments),this.dslMethods={option:[],alternation:[],repetition:[],repetitionWithSeparator:[],repetitionMandatory:[],repetitionMandatoryWithSeparator:[]}}reset(){this.dslMethods={option:[],alternation:[],repetition:[],repetitionWithSeparator:[],repetitionMandatory:[],repetitionMandatoryWithSeparator:[]}}visitOption(e){this.dslMethods.option.push(e)}visitRepetitionWithSeparator(e){this.dslMethods.repetitionWithSeparator.push(e)}visitRepetitionMandatory(e){this.dslMethods.repetitionMandatory.push(e)}visitRepetitionMandatoryWithSeparator(e){this.dslMethods.repetitionMandatoryWithSeparator.push(e)}visitRepetition(e){this.dslMethods.repetition.push(e)}visitAlternation(e){this.dslMethods.alternation.push(e)}},Yk=new UN;o(sBe,"collectMethods")});function qN(t,e){isNaN(t.startOffset)===!0?(t.startOffset=e.startOffset,t.endOffset=e.endOffset):t.endOffset{"use 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if(/full/i.test(this.nodeLocationTracking))this.recoveryEnabled?(this.setNodeLocationFromToken=YN,this.setNodeLocationFromNode=YN,this.cstPostRule=ni,this.setInitialNodeLocation=this.setInitialNodeLocationFullRecovery):(this.setNodeLocationFromToken=ni,this.setNodeLocationFromNode=ni,this.cstPostRule=this.cstPostRuleFull,this.setInitialNodeLocation=this.setInitialNodeLocationFullRegular);else if(/onlyOffset/i.test(this.nodeLocationTracking))this.recoveryEnabled?(this.setNodeLocationFromToken=qN,this.setNodeLocationFromNode=qN,this.cstPostRule=ni,this.setInitialNodeLocation=this.setInitialNodeLocationOnlyOffsetRecovery):(this.setNodeLocationFromToken=ni,this.setNodeLocationFromNode=ni,this.cstPostRule=this.cstPostRuleOnlyOffset,this.setInitialNodeLocation=this.setInitialNodeLocationOnlyOffsetRegular);else if(/none/i.test(this.nodeLocationTracking))this.setNodeLocationFromToken=ni,this.setNodeLocationFromNode=ni,this.cstPostRule=ni,this.setInitialNodeLocation=ni;else throw Error(`Invalid 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r=this.LA(0),n=e.location;n.startOffset<=r.startOffset?n.endOffset=r.endOffset:n.startOffset=NaN}cstPostTerminal(e,r){let n=this.CST_STACK[this.CST_STACK.length-1];Fse(n,r,e),this.setNodeLocationFromToken(n.location,r)}cstPostNonTerminal(e,r){let n=this.CST_STACK[this.CST_STACK.length-1];$se(n,r,e),this.setNodeLocationFromNode(n.location,e.location)}getBaseCstVisitorConstructor(){if(pr(this.baseCstVisitorConstructor)){let e=Vse(this.className,zr(this.gastProductionsCache));return this.baseCstVisitorConstructor=e,e}return this.baseCstVisitorConstructor}getBaseCstVisitorConstructorWithDefaults(){if(pr(this.baseCstVisitorWithDefaultsConstructor)){let e=Use(this.className,zr(this.gastProductionsCache),this.getBaseCstVisitorConstructor());return this.baseCstVisitorWithDefaultsConstructor=e,e}return this.baseCstVisitorWithDefaultsConstructor}getLastExplicitRuleShortName(){let e=this.RULE_STACK;return e[e.length-1]}getPreviousExplicitRuleShortName(){let e=this.RULE_STACK;return e[e.length-2]}getLastExplicitRuleOccurrenceIndex(){let e=this.RULE_OCCURRENCE_STACK;return e[e.length-1]}}});var Jk,qse=N(()=>{"use strict";Fs();Jk=class{static{o(this,"LexerAdapter")}initLexerAdapter(){this.tokVector=[],this.tokVectorLength=0,this.currIdx=-1}set input(e){if(this.selfAnalysisDone!==!0)throw Error("Missing invocation at the end of the Parser's constructor.");this.reset(),this.tokVector=e,this.tokVectorLength=e.length}get input(){return this.tokVector}SKIP_TOKEN(){return this.currIdx<=this.tokVector.length-2?(this.consumeToken(),this.LA(1)):jg}LA(e){let r=this.currIdx+e;return r<0||this.tokVectorLength<=r?jg:this.tokVector[r]}consumeToken(){this.currIdx++}exportLexerState(){return this.currIdx}importLexerState(e){this.currIdx=e}resetLexerState(){this.currIdx=-1}moveToTerminatedState(){this.currIdx=this.tokVector.length-1}getLexerPosition(){return this.exportLexerState()}}});var eE,Yse=N(()=>{"use strict";qt();Xg();Fs();Vg();fx();os();eE=class{static{o(this,"RecognizerApi")}ACTION(e){return e.call(this)}consume(e,r,n){return this.consumeInternal(r,e,n)}subrule(e,r,n){return this.subruleInternal(r,e,n)}option(e,r){return this.optionInternal(r,e)}or(e,r){return this.orInternal(r,e)}many(e,r){return this.manyInternal(e,r)}atLeastOne(e,r){return this.atLeastOneInternal(e,r)}CONSUME(e,r){return this.consumeInternal(e,0,r)}CONSUME1(e,r){return this.consumeInternal(e,1,r)}CONSUME2(e,r){return this.consumeInternal(e,2,r)}CONSUME3(e,r){return this.consumeInternal(e,3,r)}CONSUME4(e,r){return this.consumeInternal(e,4,r)}CONSUME5(e,r){return this.consumeInternal(e,5,r)}CONSUME6(e,r){return this.consumeInternal(e,6,r)}CONSUME7(e,r){return this.consumeInternal(e,7,r)}CONSUME8(e,r){return this.consumeInternal(e,8,r)}CONSUME9(e,r){return this.consumeInternal(e,9,r)}SUBRULE(e,r){return this.subruleInternal(e,0,r)}SUBRULE1(e,r){return this.subruleInternal(e,1,r)}SUBRULE2(e,r){return this.subruleInternal(e,2,r)}SUBRULE3(e,r){return this.subruleInternal(e,3,r)}SUBRULE4(e,r){return this.subruleInternal(e,4,r)}SUBRULE5(e,r){return this.subruleInternal(e,5,r)}SUBRULE6(e,r){return this.subruleInternal(e,6,r)}SUBRULE7(e,r){return this.subruleInternal(e,7,r)}SUBRULE8(e,r){return this.subruleInternal(e,8,r)}SUBRULE9(e,r){return this.subruleInternal(e,9,r)}OPTION(e){return this.optionInternal(e,0)}OPTION1(e){return this.optionInternal(e,1)}OPTION2(e){return this.optionInternal(e,2)}OPTION3(e){return this.optionInternal(e,3)}OPTION4(e){return this.optionInternal(e,4)}OPTION5(e){return this.optionInternal(e,5)}OPTION6(e){return this.optionInternal(e,6)}OPTION7(e){return this.optionInternal(e,7)}OPTION8(e){return this.optionInternal(e,8)}OPTION9(e){return this.optionInternal(e,9)}OR(e){return this.orInternal(e,0)}OR1(e){return this.orInternal(e,1)}OR2(e){return this.orInternal(e,2)}OR3(e){return this.orInternal(e,3)}OR4(e){return this.orInternal(e,4)}OR5(e){return this.orInternal(e,5)}OR6(e){return this.orInternal(e,6)}OR7(e){return this.orInternal(e,7)}OR8(e){return this.orInternal(e,8)}OR9(e){return this.orInternal(e,9)}MANY(e){this.manyInternal(0,e)}MANY1(e){this.manyInternal(1,e)}MANY2(e){this.manyInternal(2,e)}MANY3(e){this.manyInternal(3,e)}MANY4(e){this.manyInternal(4,e)}MANY5(e){this.manyInternal(5,e)}MANY6(e){this.manyInternal(6,e)}MANY7(e){this.manyInternal(7,e)}MANY8(e){this.manyInternal(8,e)}MANY9(e){this.manyInternal(9,e)}MANY_SEP(e){this.manySepFirstInternal(0,e)}MANY_SEP1(e){this.manySepFirstInternal(1,e)}MANY_SEP2(e){this.manySepFirstInternal(2,e)}MANY_SEP3(e){this.manySepFirstInternal(3,e)}MANY_SEP4(e){this.manySepFirstInternal(4,e)}MANY_SEP5(e){this.manySepFirstInternal(5,e)}MANY_SEP6(e){this.manySepFirstInternal(6,e)}MANY_SEP7(e){this.manySepFirstInternal(7,e)}MANY_SEP8(e){this.manySepFirstInternal(8,e)}MANY_SEP9(e){this.manySepFirstInternal(9,e)}AT_LEAST_ONE(e){this.atLeastOneInternal(0,e)}AT_LEAST_ONE1(e){return this.atLeastOneInternal(1,e)}AT_LEAST_ONE2(e){this.atLeastOneInternal(2,e)}AT_LEAST_ONE3(e){this.atLeastOneInternal(3,e)}AT_LEAST_ONE4(e){this.atLeastOneInternal(4,e)}AT_LEAST_ONE5(e){this.atLeastOneInternal(5,e)}AT_LEAST_ONE6(e){this.atLeastOneInternal(6,e)}AT_LEAST_ONE7(e){this.atLeastOneInternal(7,e)}AT_LEAST_ONE8(e){this.atLeastOneInternal(8,e)}AT_LEAST_ONE9(e){this.atLeastOneInternal(9,e)}AT_LEAST_ONE_SEP(e){this.atLeastOneSepFirstInternal(0,e)}AT_LEAST_ONE_SEP1(e){this.atLeastOneSepFirstInternal(1,e)}AT_LEAST_ONE_SEP2(e){this.atLeastOneSepFirstInternal(2,e)}AT_LEAST_ONE_SEP3(e){this.atLeastOneSepFirstInternal(3,e)}AT_LEAST_ONE_SEP4(e){this.atLeastOneSepFirstInternal(4,e)}AT_LEAST_ONE_SEP5(e){this.atLeastOneSepFirstInternal(5,e)}AT_LEAST_ONE_SEP6(e){this.atLeastOneSepFirstInternal(6,e)}AT_LEAST_ONE_SEP7(e){this.atLeastOneSepFirstInternal(7,e)}AT_LEAST_ONE_SEP8(e){this.atLeastOneSepFirstInternal(8,e)}AT_LEAST_ONE_SEP9(e){this.atLeastOneSepFirstInternal(9,e)}RULE(e,r,n=Kg){if(qn(this.definedRulesNames,e)){let s={message:Pl.buildDuplicateRuleNameError({topLevelRule:e,grammarName:this.className}),type:zi.DUPLICATE_RULE_NAME,ruleName:e};this.definitionErrors.push(s)}this.definedRulesNames.push(e);let i=this.defineRule(e,r,n);return this[e]=i,i}OVERRIDE_RULE(e,r,n=Kg){let i=Sse(e,this.definedRulesNames,this.className);this.definitionErrors=this.definitionErrors.concat(i);let a=this.defineRule(e,r,n);return this[e]=a,a}BACKTRACK(e,r){return function(){this.isBackTrackingStack.push(1);let n=this.saveRecogState();try{return e.apply(this,r),!0}catch(i){if(lf(i))return!1;throw i}finally{this.reloadRecogState(n),this.isBackTrackingStack.pop()}}}getGAstProductions(){return this.gastProductionsCache}getSerializedGastProductions(){return Sk(br(this.gastProductionsCache))}}});var tE,Xse=N(()=>{"use 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+ For Further details.`)}if(Pt(e))this.tokensMap=Xr(e,(a,s)=>(a[s.name]=s,a),{});else if(Bt(e,"modes")&&Ma(qr(br(e.modes)),rse)){let a=qr(br(e.modes)),s=Bm(a);this.tokensMap=Xr(s,(l,u)=>(l[u.name]=u,l),{})}else if(bn(e))this.tokensMap=an(e);else throw new Error(" argument must be An Array of Token constructors, A dictionary of Token constructors or an IMultiModeLexerDefinition");this.tokensMap.EOF=lo;let n=Bt(e,"modes")?qr(br(e.modes)):br(e),i=Ma(n,a=>ur(a.categoryMatches));this.tokenMatcher=i?zg:Pu,Bu(br(this.tokensMap))}defineRule(e,r,n){if(this.selfAnalysisDone)throw Error(`Grammar rule <${e}> may not be defined after the 'performSelfAnalysis' method has been called' +Make sure that all grammar rule definitions are done before 'performSelfAnalysis' is called.`);let i=Bt(n,"resyncEnabled")?n.resyncEnabled:Kg.resyncEnabled,a=Bt(n,"recoveryValueFunc")?n.recoveryValueFunc:Kg.recoveryValueFunc,s=this.ruleShortNameIdx<<12;this.ruleShortNameIdx++,this.shortRuleNameToFull[s]=e,this.fullRuleNameToShort[e]=s;let l;return this.outputCst===!0?l=o(function(...f){try{this.ruleInvocationStateUpdate(s,e,this.subruleIdx),r.apply(this,f);let d=this.CST_STACK[this.CST_STACK.length-1];return this.cstPostRule(d),d}catch(d){return this.invokeRuleCatch(d,i,a)}finally{this.ruleFinallyStateUpdate()}},"invokeRuleWithTry"):l=o(function(...f){try{return this.ruleInvocationStateUpdate(s,e,this.subruleIdx),r.apply(this,f)}catch(d){return this.invokeRuleCatch(d,i,a)}finally{this.ruleFinallyStateUpdate()}},"invokeRuleWithTryCst"),Object.assign(l,{ruleName:e,originalGrammarAction:r})}invokeRuleCatch(e,r,n){let i=this.RULE_STACK.length===1,a=r&&!this.isBackTracking()&&this.recoveryEnabled;if(lf(e)){let s=e;if(a){let l=this.findReSyncTokenType();if(this.isInCurrentRuleReSyncSet(l))if(s.resyncedTokens=this.reSyncTo(l),this.outputCst){let u=this.CST_STACK[this.CST_STACK.length-1];return u.recoveredNode=!0,u}else return n(e);else{if(this.outputCst){let u=this.CST_STACK[this.CST_STACK.length-1];u.recoveredNode=!0,s.partialCstResult=u}throw s}}else{if(i)return this.moveToTerminatedState(),n(e);throw s}}else throw e}optionInternal(e,r){let n=this.getKeyForAutomaticLookahead(512,r);return this.optionInternalLogic(e,r,n)}optionInternalLogic(e,r,n){let i=this.getLaFuncFromCache(n),a;if(typeof e!="function"){a=e.DEF;let s=e.GATE;if(s!==void 0){let l=i;i=o(()=>s.call(this)&&l.call(this),"lookAheadFunc")}}else a=e;if(i.call(this)===!0)return a.call(this)}atLeastOneInternal(e,r){let n=this.getKeyForAutomaticLookahead(1024,e);return this.atLeastOneInternalLogic(e,r,n)}atLeastOneInternalLogic(e,r,n){let i=this.getLaFuncFromCache(n),a;if(typeof r!="function"){a=r.DEF;let s=r.GATE;if(s!==void 0){let l=i;i=o(()=>s.call(this)&&l.call(this),"lookAheadFunc")}}else a=r;if(i.call(this)===!0){let s=this.doSingleRepetition(a);for(;i.call(this)===!0&&s===!0;)s=this.doSingleRepetition(a)}else throw this.raiseEarlyExitException(e,jn.REPETITION_MANDATORY,r.ERR_MSG);this.attemptInRepetitionRecovery(this.atLeastOneInternal,[e,r],i,1024,e,Bk)}atLeastOneSepFirstInternal(e,r){let n=this.getKeyForAutomaticLookahead(1536,e);this.atLeastOneSepFirstInternalLogic(e,r,n)}atLeastOneSepFirstInternalLogic(e,r,n){let i=r.DEF,a=r.SEP;if(this.getLaFuncFromCache(n).call(this)===!0){i.call(this);let l=o(()=>this.tokenMatcher(this.LA(1),a),"separatorLookAheadFunc");for(;this.tokenMatcher(this.LA(1),a)===!0;)this.CONSUME(a),i.call(this);this.attemptInRepetitionRecovery(this.repetitionSepSecondInternal,[e,a,l,i,lx],l,1536,e,lx)}else throw this.raiseEarlyExitException(e,jn.REPETITION_MANDATORY_WITH_SEPARATOR,r.ERR_MSG)}manyInternal(e,r){let n=this.getKeyForAutomaticLookahead(768,e);return this.manyInternalLogic(e,r,n)}manyInternalLogic(e,r,n){let i=this.getLaFuncFromCache(n),a;if(typeof r!="function"){a=r.DEF;let l=r.GATE;if(l!==void 0){let u=i;i=o(()=>l.call(this)&&u.call(this),"lookaheadFunction")}}else a=r;let s=!0;for(;i.call(this)===!0&&s===!0;)s=this.doSingleRepetition(a);this.attemptInRepetitionRecovery(this.manyInternal,[e,r],i,768,e,Pk,s)}manySepFirstInternal(e,r){let n=this.getKeyForAutomaticLookahead(1280,e);this.manySepFirstInternalLogic(e,r,n)}manySepFirstInternalLogic(e,r,n){let i=r.DEF,a=r.SEP;if(this.getLaFuncFromCache(n).call(this)===!0){i.call(this);let l=o(()=>this.tokenMatcher(this.LA(1),a),"separatorLookAheadFunc");for(;this.tokenMatcher(this.LA(1),a)===!0;)this.CONSUME(a),i.call(this);this.attemptInRepetitionRecovery(this.repetitionSepSecondInternal,[e,a,l,i,ox],l,1280,e,ox)}}repetitionSepSecondInternal(e,r,n,i,a){for(;n();)this.CONSUME(r),i.call(this);this.attemptInRepetitionRecovery(this.repetitionSepSecondInternal,[e,r,n,i,a],n,1536,e,a)}doSingleRepetition(e){let r=this.getLexerPosition();return e.call(this),this.getLexerPosition()>r}orInternal(e,r){let n=this.getKeyForAutomaticLookahead(256,r),i=Pt(e)?e:e.DEF,s=this.getLaFuncFromCache(n).call(this,i);if(s!==void 0)return i[s].ALT.call(this);this.raiseNoAltException(r,e.ERR_MSG)}ruleFinallyStateUpdate(){if(this.RULE_STACK.pop(),this.RULE_OCCURRENCE_STACK.pop(),this.cstFinallyStateUpdate(),this.RULE_STACK.length===0&&this.isAtEndOfInput()===!1){let e=this.LA(1),r=this.errorMessageProvider.buildNotAllInputParsedMessage({firstRedundant:e,ruleName:this.getCurrRuleFullName()});this.SAVE_ERROR(new px(r,e))}}subruleInternal(e,r,n){let i;try{let a=n!==void 0?n.ARGS:void 0;return this.subruleIdx=r,i=e.apply(this,a),this.cstPostNonTerminal(i,n!==void 0&&n.LABEL!==void 0?n.LABEL:e.ruleName),i}catch(a){throw this.subruleInternalError(a,n,e.ruleName)}}subruleInternalError(e,r,n){throw lf(e)&&e.partialCstResult!==void 0&&(this.cstPostNonTerminal(e.partialCstResult,r!==void 0&&r.LABEL!==void 0?r.LABEL:n),delete e.partialCstResult),e}consumeInternal(e,r,n){let i;try{let a=this.LA(1);this.tokenMatcher(a,e)===!0?(this.consumeToken(),i=a):this.consumeInternalError(e,a,n)}catch(a){i=this.consumeInternalRecovery(e,r,a)}return this.cstPostTerminal(n!==void 0&&n.LABEL!==void 0?n.LABEL:e.name,i),i}consumeInternalError(e,r,n){let i,a=this.LA(0);throw n!==void 0&&n.ERR_MSG?i=n.ERR_MSG:i=this.errorMessageProvider.buildMismatchTokenMessage({expected:e,actual:r,previous:a,ruleName:this.getCurrRuleFullName()}),this.SAVE_ERROR(new hp(i,r,a))}consumeInternalRecovery(e,r,n){if(this.recoveryEnabled&&n.name==="MismatchedTokenException"&&!this.isBackTracking()){let i=this.getFollowsForInRuleRecovery(e,r);try{return this.tryInRuleRecovery(e,i)}catch(a){throw a.name===zN?n:a}}else throw n}saveRecogState(){let e=this.errors,r=an(this.RULE_STACK);return{errors:e,lexerState:this.exportLexerState(),RULE_STACK:r,CST_STACK:this.CST_STACK}}reloadRecogState(e){this.errors=e.errors,this.importLexerState(e.lexerState),this.RULE_STACK=e.RULE_STACK}ruleInvocationStateUpdate(e,r,n){this.RULE_OCCURRENCE_STACK.push(n),this.RULE_STACK.push(e),this.cstInvocationStateUpdate(r)}isBackTracking(){return this.isBackTrackingStack.length!==0}getCurrRuleFullName(){let e=this.getLastExplicitRuleShortName();return this.shortRuleNameToFull[e]}shortRuleNameToFullName(e){return this.shortRuleNameToFull[e]}isAtEndOfInput(){return this.tokenMatcher(this.LA(1),lo)}reset(){this.resetLexerState(),this.subruleIdx=0,this.isBackTrackingStack=[],this.errors=[],this.RULE_STACK=[],this.CST_STACK=[],this.RULE_OCCURRENCE_STACK=[]}}});var rE,jse=N(()=>{"use strict";Xg();qt();qg();Fs();rE=class{static{o(this,"ErrorHandler")}initErrorHandler(e){this._errors=[],this.errorMessageProvider=Bt(e,"errorMessageProvider")?e.errorMessageProvider:ls.errorMessageProvider}SAVE_ERROR(e){if(lf(e))return e.context={ruleStack:this.getHumanReadableRuleStack(),ruleOccurrenceStack:an(this.RULE_OCCURRENCE_STACK)},this._errors.push(e),e;throw Error("Trying to save an Error which is not a RecognitionException")}get errors(){return an(this._errors)}set errors(e){this._errors=e}raiseEarlyExitException(e,r,n){let i=this.getCurrRuleFullName(),a=this.getGAstProductions()[i],l=Wg(e,a,r,this.maxLookahead)[0],u=[];for(let f=1;f<=this.maxLookahead;f++)u.push(this.LA(f));let h=this.errorMessageProvider.buildEarlyExitMessage({expectedIterationPaths:l,actual:u,previous:this.LA(0),customUserDescription:n,ruleName:i});throw this.SAVE_ERROR(new mx(h,this.LA(1),this.LA(0)))}raiseNoAltException(e,r){let n=this.getCurrRuleFullName(),i=this.getGAstProductions()[n],a=Hg(e,i,this.maxLookahead),s=[];for(let h=1;h<=this.maxLookahead;h++)s.push(this.LA(h));let l=this.LA(0),u=this.errorMessageProvider.buildNoViableAltMessage({expectedPathsPerAlt:a,actual:s,previous:l,customUserDescription:r,ruleName:this.getCurrRuleFullName()});throw this.SAVE_ERROR(new dx(u,this.LA(1),l))}}});var nE,Kse=N(()=>{"use strict";cx();qt();nE=class{static{o(this,"ContentAssist")}initContentAssist(){}computeContentAssist(e,r){let n=this.gastProductionsCache[e];if(pr(n))throw Error(`Rule ->${e}<- does not exist in this grammar.`);return $k([n],r,this.tokenMatcher,this.maxLookahead)}getNextPossibleTokenTypes(e){let r=ia(e.ruleStack),i=this.getGAstProductions()[r];return new Ok(i,e).startWalking()}}});function yx(t,e,r,n=!1){aE(r);let i=ga(this.recordingProdStack),a=Si(e)?e:e.DEF,s=new t({definition:[],idx:r});return n&&(s.separator=e.SEP),Bt(e,"MAX_LOOKAHEAD")&&(s.maxLookahead=e.MAX_LOOKAHEAD),this.recordingProdStack.push(s),a.call(this),i.definition.push(s),this.recordingProdStack.pop(),sE}function dBe(t,e){aE(e);let r=ga(this.recordingProdStack),n=Pt(t)===!1,i=n===!1?t:t.DEF,a=new Tn({definition:[],idx:e,ignoreAmbiguities:n&&t.IGNORE_AMBIGUITIES===!0});Bt(t,"MAX_LOOKAHEAD")&&(a.maxLookahead=t.MAX_LOOKAHEAD);let s=A2(i,l=>Si(l.GATE));return a.hasPredicates=s,r.definition.push(a),Ae(i,l=>{let u=new Dn({definition:[]});a.definition.push(u),Bt(l,"IGNORE_AMBIGUITIES")?u.ignoreAmbiguities=l.IGNORE_AMBIGUITIES:Bt(l,"GATE")&&(u.ignoreAmbiguities=!0),this.recordingProdStack.push(u),l.ALT.call(this),this.recordingProdStack.pop()}),sE}function Jse(t){return t===0?"":`${t}`}function aE(t){if(t<0||t>Zse){let e=new Error(`Invalid DSL Method idx value: <${t}> + Idx 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You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). +`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(q){this.unput(this.match.slice(q))},"less"),pastInput:o(function(){var q=this.matched.substr(0,this.matched.length-this.match.length);return(q.length>20?"...":"")+q.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var q=this.match;return q.length<20&&(q+=this._input.substr(0,20-q.length)),(q.substr(0,20)+(q.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var q=this.pastInput(),pe=new Array(q.length+1).join("-");return q+this.upcomingInput()+` +`+pe+"^"},"showPosition"),test_match:o(function(q,pe){var ve,Pe,_e;if(this.options.backtrack_lexer&&(_e={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(_e.yylloc.range=this.yylloc.range.slice(0))),Pe=q[0].match(/(?:\r\n?|\n).*/g),Pe&&(this.yylineno+=Pe.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:Pe?Pe[Pe.length-1].length-Pe[Pe.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+q[0].length},this.yytext+=q[0],this.match+=q[0],this.matches=q,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(q[0].length),this.matched+=q[0],ve=this.performAction.call(this,this.yy,this,pe,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),ve)return ve;if(this._backtrack){for(var we in _e)this[we]=_e[we];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var q,pe,ve,Pe;this._more||(this.yytext="",this.match="");for(var _e=this._currentRules(),we=0;we<_e.length;we++)if(ve=this._input.match(this.rules[_e[we]]),ve&&(!pe||ve[0].length>pe[0].length)){if(pe=ve,Pe=we,this.options.backtrack_lexer){if(q=this.test_match(ve,_e[we]),q!==!1)return q;if(this._backtrack){pe=!1;continue}else return!1}else if(!this.options.flex)break}return pe?(q=this.test_match(pe,_e[Pe]),q!==!1?q:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. +`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var pe=this.next();return pe||this.lex()},"lex"),begin:o(function(pe){this.conditionStack.push(pe)},"begin"),popState:o(function(){var pe=this.conditionStack.length-1;return pe>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(pe){return pe=this.conditionStack.length-1-Math.abs(pe||0),pe>=0?this.conditionStack[pe]:"INITIAL"},"topState"),pushState:o(function(pe){this.begin(pe)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{"case-insensitive":!0},performAction:o(function(pe,ve,Pe,_e){var we=_e;switch(Pe){case 0:break;case 1:break;case 2:return 55;case 3:break;case 4:return this.begin("title"),35;break;case 5:return this.popState(),"title_value";break;case 6:return this.begin("acc_title"),37;break;case 7:return this.popState(),"acc_title_value";break;case 8:return this.begin("acc_descr"),39;break;case 9:return this.popState(),"acc_descr_value";break;case 10:this.begin("acc_descr_multiline");break;case 11:this.popState();break;case 12:return"acc_descr_multiline_value";case 13:return 48;case 14:return 50;case 15:return 49;case 16:return 51;case 17:return 52;case 18:return 53;case 19:return 54;case 20:return 25;case 21:this.begin("md_string");break;case 22:return"MD_STR";case 23:this.popState();break;case 24:this.begin("string");break;case 25:this.popState();break;case 26:return"STR";case 27:this.begin("class_name");break;case 28:return this.popState(),47;break;case 29:return this.begin("point_start"),44;break;case 30:return this.begin("point_x"),45;break;case 31:this.popState();break;case 32:this.popState(),this.begin("point_y");break;case 33:return this.popState(),46;break;case 34:return 28;case 35:return 4;case 36:return 11;case 37:return 64;case 38:return 10;case 39:return 65;case 40:return 65;case 41:return 14;case 42:return 13;case 43:return 67;case 44:return 66;case 45:return 12;case 46:return 8;case 47:return 5;case 48:return 18;case 49:return 56;case 50:return 63;case 51:return 57}},"anonymous"),rules:[/^(?:%%(?!\{)[^\n]*)/i,/^(?:[^\}]%%[^\n]*)/i,/^(?:[\n\r]+)/i,/^(?:%%[^\n]*)/i,/^(?:title\b)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accTitle\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*\{\s*)/i,/^(?:[\}])/i,/^(?:[^\}]*)/i,/^(?: *x-axis *)/i,/^(?: *y-axis *)/i,/^(?: *--+> *)/i,/^(?: *quadrant-1 *)/i,/^(?: *quadrant-2 *)/i,/^(?: *quadrant-3 *)/i,/^(?: *quadrant-4 *)/i,/^(?:classDef\b)/i,/^(?:["][`])/i,/^(?:[^`"]+)/i,/^(?:[`]["])/i,/^(?:["])/i,/^(?:["])/i,/^(?:[^"]*)/i,/^(?::::)/i,/^(?:^\w+)/i,/^(?:\s*:\s*\[\s*)/i,/^(?:(1)|(0(.\d+)?))/i,/^(?:\s*\] *)/i,/^(?:\s*,\s*)/i,/^(?:(1)|(0(.\d+)?))/i,/^(?: *quadrantChart *)/i,/^(?:[A-Za-z]+)/i,/^(?::)/i,/^(?:\+)/i,/^(?:,)/i,/^(?:=)/i,/^(?:=)/i,/^(?:\*)/i,/^(?:#)/i,/^(?:[\_])/i,/^(?:\.)/i,/^(?:&)/i,/^(?:-)/i,/^(?:[0-9]+)/i,/^(?:\s)/i,/^(?:;)/i,/^(?:[!"#$%&'*+,-.`?\\_/])/i,/^(?:$)/i],conditions:{class_name:{rules:[28],inclusive:!1},point_y:{rules:[33],inclusive:!1},point_x:{rules:[32],inclusive:!1},point_start:{rules:[30,31],inclusive:!1},acc_descr_multiline:{rules:[11,12],inclusive:!1},acc_descr:{rules:[9],inclusive:!1},acc_title:{rules:[7],inclusive:!1},title:{rules:[5],inclusive:!1},md_string:{rules:[22,23],inclusive:!1},string:{rules:[25,26],inclusive:!1},INITIAL:{rules:[0,1,2,3,4,6,8,10,13,14,15,16,17,18,19,20,21,24,27,29,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51],inclusive:!0}}};return xe}();re.lexer=oe;function V(){this.yy={}}return o(V,"Parser"),V.prototype=re,re.Parser=V,new V}();hO.parser=hO;uhe=hO});var ms,y6,fhe=N(()=>{"use strict";dr();Ya();vt();_y();ms=oh(),y6=class{constructor(){this.classes=new Map;this.config=this.getDefaultConfig(),this.themeConfig=this.getDefaultThemeConfig(),this.data=this.getDefaultData()}static{o(this,"QuadrantBuilder")}getDefaultData(){return{titleText:"",quadrant1Text:"",quadrant2Text:"",quadrant3Text:"",quadrant4Text:"",xAxisLeftText:"",xAxisRightText:"",yAxisBottomText:"",yAxisTopText:"",points:[]}}getDefaultConfig(){return{showXAxis:!0,showYAxis:!0,showTitle:!0,chartHeight:or.quadrantChart?.chartWidth||500,chartWidth:or.quadrantChart?.chartHeight||500,titlePadding:or.quadrantChart?.titlePadding||10,titleFontSize:or.quadrantChart?.titleFontSize||20,quadrantPadding:or.quadrantChart?.quadrantPadding||5,xAxisLabelPadding:or.quadrantChart?.xAxisLabelPadding||5,yAxisLabelPadding:or.quadrantChart?.yAxisLabelPadding||5,xAxisLabelFontSize:or.quadrantChart?.xAxisLabelFontSize||16,yAxisLabelFontSize:or.quadrantChart?.yAxisLabelFontSize||16,quadrantLabelFontSize:or.quadrantChart?.quadrantLabelFontSize||16,quadrantTextTopPadding:or.quadrantChart?.quadrantTextTopPadding||5,pointTextPadding:or.quadrantChart?.pointTextPadding||5,pointLabelFontSize:or.quadrantChart?.pointLabelFontSize||12,pointRadius:or.quadrantChart?.pointRadius||5,xAxisPosition:or.quadrantChart?.xAxisPosition||"top",yAxisPosition:or.quadrantChart?.yAxisPosition||"left",quadrantInternalBorderStrokeWidth:or.quadrantChart?.quadrantInternalBorderStrokeWidth||1,quadrantExternalBorderStrokeWidth:or.quadrantChart?.quadrantExternalBorderStrokeWidth||2}}getDefaultThemeConfig(){return{quadrant1Fill:ms.quadrant1Fill,quadrant2Fill:ms.quadrant2Fill,quadrant3Fill:ms.quadrant3Fill,quadrant4Fill:ms.quadrant4Fill,quadrant1TextFill:ms.quadrant1TextFill,quadrant2TextFill:ms.quadrant2TextFill,quadrant3TextFill:ms.quadrant3TextFill,quadrant4TextFill:ms.quadrant4TextFill,quadrantPointFill:ms.quadrantPointFill,quadrantPointTextFill:ms.quadrantPointTextFill,quadrantXAxisTextFill:ms.quadrantXAxisTextFill,quadrantYAxisTextFill:ms.quadrantYAxisTextFill,quadrantTitleFill:ms.quadrantTitleFill,quadrantInternalBorderStrokeFill:ms.quadrantInternalBorderStrokeFill,quadrantExternalBorderStrokeFill:ms.quadrantExternalBorderStrokeFill}}clear(){this.config=this.getDefaultConfig(),this.themeConfig=this.getDefaultThemeConfig(),this.data=this.getDefaultData(),this.classes=new Map,Y.info("clear called")}setData(e){this.data={...this.data,...e}}addPoints(e){this.data.points=[...e,...this.data.points]}addClass(e,r){this.classes.set(e,r)}setConfig(e){Y.trace("setConfig called with: ",e),this.config={...this.config,...e}}setThemeConfig(e){Y.trace("setThemeConfig called with: ",e),this.themeConfig={...this.themeConfig,...e}}calculateSpace(e,r,n,i){let a=this.config.xAxisLabelPadding*2+this.config.xAxisLabelFontSize,s={top:e==="top"&&r?a:0,bottom:e==="bottom"&&r?a:0},l=this.config.yAxisLabelPadding*2+this.config.yAxisLabelFontSize,u={left:this.config.yAxisPosition==="left"&&n?l:0,right:this.config.yAxisPosition==="right"&&n?l:0},h=this.config.titleFontSize+this.config.titlePadding*2,f={top:i?h:0},d=this.config.quadrantPadding+u.left,p=this.config.quadrantPadding+s.top+f.top,m=this.config.chartWidth-this.config.quadrantPadding*2-u.left-u.right,g=this.config.chartHeight-this.config.quadrantPadding*2-s.top-s.bottom-f.top,y=m/2,v=g/2;return{xAxisSpace:s,yAxisSpace:u,titleSpace:f,quadrantSpace:{quadrantLeft:d,quadrantTop:p,quadrantWidth:m,quadrantHalfWidth:y,quadrantHeight:g,quadrantHalfHeight:v}}}getAxisLabels(e,r,n,i){let{quadrantSpace:a,titleSpace:s}=i,{quadrantHalfHeight:l,quadrantHeight:u,quadrantLeft:h,quadrantHalfWidth:f,quadrantTop:d,quadrantWidth:p}=a,m=!!this.data.xAxisRightText,g=!!this.data.yAxisTopText,y=[];return this.data.xAxisLeftText&&r&&y.push({text:this.data.xAxisLeftText,fill:this.themeConfig.quadrantXAxisTextFill,x:h+(m?f/2:0),y:e==="top"?this.config.xAxisLabelPadding+s.top:this.config.xAxisLabelPadding+d+u+this.config.quadrantPadding,fontSize:this.config.xAxisLabelFontSize,verticalPos:m?"center":"left",horizontalPos:"top",rotation:0}),this.data.xAxisRightText&&r&&y.push({text:this.data.xAxisRightText,fill:this.themeConfig.quadrantXAxisTextFill,x:h+f+(m?f/2:0),y:e==="top"?this.config.xAxisLabelPadding+s.top:this.config.xAxisLabelPadding+d+u+this.config.quadrantPadding,fontSize:this.config.xAxisLabelFontSize,verticalPos:m?"center":"left",horizontalPos:"top",rotation:0}),this.data.yAxisBottomText&&n&&y.push({text:this.data.yAxisBottomText,fill:this.themeConfig.quadrantYAxisTextFill,x:this.config.yAxisPosition==="left"?this.config.yAxisLabelPadding:this.config.yAxisLabelPadding+h+p+this.config.quadrantPadding,y:d+u-(g?l/2:0),fontSize:this.config.yAxisLabelFontSize,verticalPos:g?"center":"left",horizontalPos:"top",rotation:-90}),this.data.yAxisTopText&&n&&y.push({text:this.data.yAxisTopText,fill:this.themeConfig.quadrantYAxisTextFill,x:this.config.yAxisPosition==="left"?this.config.yAxisLabelPadding:this.config.yAxisLabelPadding+h+p+this.config.quadrantPadding,y:d+l-(g?l/2:0),fontSize:this.config.yAxisLabelFontSize,verticalPos:g?"center":"left",horizontalPos:"top",rotation:-90}),y}getQuadrants(e){let{quadrantSpace:r}=e,{quadrantHalfHeight:n,quadrantLeft:i,quadrantHalfWidth:a,quadrantTop:s}=r,l=[{text:{text:this.data.quadrant1Text,fill:this.themeConfig.quadrant1TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i+a,y:s,width:a,height:n,fill:this.themeConfig.quadrant1Fill},{text:{text:this.data.quadrant2Text,fill:this.themeConfig.quadrant2TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i,y:s,width:a,height:n,fill:this.themeConfig.quadrant2Fill},{text:{text:this.data.quadrant3Text,fill:this.themeConfig.quadrant3TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i,y:s+n,width:a,height:n,fill:this.themeConfig.quadrant3Fill},{text:{text:this.data.quadrant4Text,fill:this.themeConfig.quadrant4TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i+a,y:s+n,width:a,height:n,fill:this.themeConfig.quadrant4Fill}];for(let u of l)u.text.x=u.x+u.width/2,this.data.points.length===0?(u.text.y=u.y+u.height/2,u.text.horizontalPos="middle"):(u.text.y=u.y+this.config.quadrantTextTopPadding,u.text.horizontalPos="top");return l}getQuadrantPoints(e){let{quadrantSpace:r}=e,{quadrantHeight:n,quadrantLeft:i,quadrantTop:a,quadrantWidth:s}=r,l=gl().domain([0,1]).range([i,s+i]),u=gl().domain([0,1]).range([n+a,a]);return this.data.points.map(f=>{let d=this.classes.get(f.className);return d&&(f={...d,...f}),{x:l(f.x),y:u(f.y),fill:f.color??this.themeConfig.quadrantPointFill,radius:f.radius??this.config.pointRadius,text:{text:f.text,fill:this.themeConfig.quadrantPointTextFill,x:l(f.x),y:u(f.y)+this.config.pointTextPadding,verticalPos:"center",horizontalPos:"top",fontSize:this.config.pointLabelFontSize,rotation:0},strokeColor:f.strokeColor??this.themeConfig.quadrantPointFill,strokeWidth:f.strokeWidth??"0px"}})}getBorders(e){let r=this.config.quadrantExternalBorderStrokeWidth/2,{quadrantSpace:n}=e,{quadrantHalfHeight:i,quadrantHeight:a,quadrantLeft:s,quadrantHalfWidth:l,quadrantTop:u,quadrantWidth:h}=n;return[{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s-r,y1:u,x2:s+h+r,y2:u},{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s+h,y1:u+r,x2:s+h,y2:u+a-r},{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s-r,y1:u+a,x2:s+h+r,y2:u+a},{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s,y1:u+r,x2:s,y2:u+a-r},{strokeFill:this.themeConfig.quadrantInternalBorderStrokeFill,strokeWidth:this.config.quadrantInternalBorderStrokeWidth,x1:s+l,y1:u+r,x2:s+l,y2:u+a-r},{strokeFill:this.themeConfig.quadrantInternalBorderStrokeFill,strokeWidth:this.config.quadrantInternalBorderStrokeWidth,x1:s+r,y1:u+i,x2:s+h-r,y2:u+i}]}getTitle(e){if(e)return{text:this.data.titleText,fill:this.themeConfig.quadrantTitleFill,fontSize:this.config.titleFontSize,horizontalPos:"top",verticalPos:"center",rotation:0,y:this.config.titlePadding,x:this.config.chartWidth/2}}build(){let e=this.config.showXAxis&&!!(this.data.xAxisLeftText||this.data.xAxisRightText),r=this.config.showYAxis&&!!(this.data.yAxisTopText||this.data.yAxisBottomText),n=this.config.showTitle&&!!this.data.titleText,i=this.data.points.length>0?"bottom":this.config.xAxisPosition,a=this.calculateSpace(i,e,r,n);return{points:this.getQuadrantPoints(a),quadrants:this.getQuadrants(a),axisLabels:this.getAxisLabels(i,e,r,a),borderLines:this.getBorders(a),title:this.getTitle(n)}}}});function fO(t){return!/^#?([\dA-Fa-f]{6}|[\dA-Fa-f]{3})$/.test(t)}function dhe(t){return!/^\d+$/.test(t)}function phe(t){return!/^\d+px$/.test(t)}var Ap,mhe=N(()=>{"use strict";Ap=class extends Error{static{o(this,"InvalidStyleError")}constructor(e,r,n){super(`value for ${e} ${r} is invalid, please use a valid ${n}`),this.name="InvalidStyleError"}};o(fO,"validateHexCode");o(dhe,"validateNumber");o(phe,"validateSizeInPixels")});function Xu(t){return Tr(t.trim(),pGe)}function mGe(t){ba.setData({quadrant1Text:Xu(t.text)})}function gGe(t){ba.setData({quadrant2Text:Xu(t.text)})}function yGe(t){ba.setData({quadrant3Text:Xu(t.text)})}function vGe(t){ba.setData({quadrant4Text:Xu(t.text)})}function xGe(t){ba.setData({xAxisLeftText:Xu(t.text)})}function bGe(t){ba.setData({xAxisRightText:Xu(t.text)})}function wGe(t){ba.setData({yAxisTopText:Xu(t.text)})}function TGe(t){ba.setData({yAxisBottomText:Xu(t.text)})}function dO(t){let e={};for(let r of t){let[n,i]=r.trim().split(/\s*:\s*/);if(n==="radius"){if(dhe(i))throw new Ap(n,i,"number");e.radius=parseInt(i)}else if(n==="color"){if(fO(i))throw new Ap(n,i,"hex code");e.color=i}else if(n==="stroke-color"){if(fO(i))throw new Ap(n,i,"hex code");e.strokeColor=i}else if(n==="stroke-width"){if(phe(i))throw new Ap(n,i,"number of pixels (eg. 10px)");e.strokeWidth=i}else throw new Error(`style named ${n} is not supported.`)}return e}function kGe(t,e,r,n,i){let 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this.textDimensionCalculator.getMaxDimension(this.getTickValues().map(e=>e.toString()),this.axisConfig.labelFontSize)}recalculateOuterPaddingToDrawBar(){.7*this.getTickDistance()>this.outerPadding*2&&(this.outerPadding=Math.floor(.7*this.getTickDistance()/2)),this.recalculateScale()}calculateSpaceIfDrawnHorizontally(e){let r=e.height;if(this.axisConfig.showAxisLine&&r>this.axisConfig.axisLineWidth&&(r-=this.axisConfig.axisLineWidth,this.showAxisLine=!0),this.axisConfig.showLabel){let n=this.getLabelDimension(),i=.2*e.width;this.outerPadding=Math.min(n.width/2,i);let a=n.height+this.axisConfig.labelPadding*2;this.labelTextHeight=n.height,a<=r&&(r-=a,this.showLabel=!0)}if(this.axisConfig.showTick&&r>=this.axisConfig.tickLength&&(this.showTick=!0,r-=this.axisConfig.tickLength),this.axisConfig.showTitle&&this.title){let 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n=this.textDimensionCalculator.getMaxDimension([this.title],this.axisConfig.titleFontSize),i=n.height+this.axisConfig.titlePadding*2;this.titleTextHeight=n.height,i<=r&&(r-=i,this.showTitle=!0)}this.boundingRect.width=e.width-r,this.boundingRect.height=e.height}calculateSpace(e){return this.axisPosition==="left"||this.axisPosition==="right"?this.calculateSpaceIfDrawnVertical(e):this.calculateSpaceIfDrawnHorizontally(e),this.recalculateScale(),{width:this.boundingRect.width,height:this.boundingRect.height}}setBoundingBoxXY(e){this.boundingRect.x=e.x,this.boundingRect.y=e.y}getDrawableElementsForLeftAxis(){let e=[];if(this.showAxisLine){let r=this.boundingRect.x+this.boundingRect.width-this.axisConfig.axisLineWidth/2;e.push({type:"path",groupTexts:["left-axis","axisl-line"],data:[{path:`M ${r},${this.boundingRect.y} L ${r},${this.boundingRect.y+this.boundingRect.height} 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this.showTitle&&e.push({type:"text",groupTexts:["left-axis","title"],data:[{text:this.title,x:this.boundingRect.x+this.axisConfig.titlePadding,y:this.boundingRect.y+this.boundingRect.height/2,fill:this.axisThemeConfig.titleColor,fontSize:this.axisConfig.titleFontSize,rotation:270,verticalPos:"top",horizontalPos:"center"}]}),e}getDrawableElementsForBottomAxis(){let e=[];if(this.showAxisLine){let r=this.boundingRect.y+this.axisConfig.axisLineWidth/2;e.push({type:"path",groupTexts:["bottom-axis","axis-line"],data:[{path:`M ${this.boundingRect.x},${r} L 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this.showTitle&&e.push({type:"text",groupTexts:["bottom-axis","title"],data:[{text:this.title,x:this.range[0]+(this.range[1]-this.range[0])/2,y:this.boundingRect.y+this.boundingRect.height-this.axisConfig.titlePadding-this.titleTextHeight,fill:this.axisThemeConfig.titleColor,fontSize:this.axisConfig.titleFontSize,rotation:0,verticalPos:"top",horizontalPos:"center"}]}),e}getDrawableElementsForTopAxis(){let e=[];if(this.showAxisLine){let r=this.boundingRect.y+this.boundingRect.height-this.axisConfig.axisLineWidth/2;e.push({type:"path",groupTexts:["top-axis","axis-line"],data:[{path:`M ${this.boundingRect.x},${r} L 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68:this.$=ve[_e-1]+ve[_e];break}},"anonymous"),table:[{3:1,4:2,6:e,9:r,11:n,13:i},{1:[3]},{3:8,4:2,5:[1,7],6:e,9:r,11:n,13:i},{5:[1,9]},{10:[1,10]},{12:[1,11]},t(a,[2,6]),{3:12,4:2,6:e,9:r,11:n,13:i},{1:[2,2]},{4:17,5:s,7:13,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},t(a,[2,4]),t(a,[2,5]),{1:[2,1]},{8:[1,41]},{4:17,5:s,7:42,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:43,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:44,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:45,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:46,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:47,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:48,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:49,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:50,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{26:51,89:[1,52],90:[1,53]},{55:54,89:[1,55],90:[1,56]},{29:[1,59],61:[1,57],63:[1,58]},t(S,[2,17]),t(S,[2,18]),t(S,[2,19]),t(S,[2,20]),{30:60,33:62,75:_,89:E,90:A},{30:63,33:62,75:_,89:E,90:A},{30:64,33:62,75:_,89:E,90:A},t(I,[2,29]),t(I,[2,30]),t(I,[2,31]),t(I,[2,32]),t(I,[2,33]),t(I,[2,34]),t(D,[2,81]),t(D,[2,82]),{1:[2,3]},{8:[2,8]},{8:[2,9]},{8:[2,10]},{8:[2,11]},{8:[2,12]},{8:[2,13]},{8:[2,14]},{8:[2,15]},{8:[2,16]},{27:[1,65],29:[1,66]},t(k,[2,79]),t(k,[2,80]),{27:[1,67],29:[1,68]},t(k,[2,85]),t(k,[2,86]),{62:69,65:L,66:R,67:O,68:M,69:B,70:F,71:P},{62:77,65:L,66:R,67:O,68:M,69:B,70:F,71:P},{30:78,33:62,75:_,89:E,90:A},{73:79,75:z,76:$,78:81,79:82,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X},t(te,[2,60]),t(te,[2,62]),{73:93,75:z,76:$,78:81,79:82,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X},{30:94,33:62,75:_,76:$,89:E,90:A},{5:[1,95]},{30:96,33:62,75:_,89:E,90:A},{5:[1,97]},{30:98,33:62,75:_,89:E,90:A},{63:[1,99]},t(J,[2,50]),t(J,[2,51]),t(J,[2,52]),t(J,[2,53]),t(J,[2,54]),t(J,[2,55]),t(J,[2,56]),{64:[1,100]},t(S,[2,59],{76:$}),t(S,[2,64],{76:se}),{33:103,75:[1,102],89:E,90:A},t(ue,[2,65],{79:104,75:z,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X}),t(Z,[2,67]),t(Z,[2,69]),t(Z,[2,70]),t(Z,[2,71]),t(Z,[2,72]),t(Z,[2,73]),t(Z,[2,74]),t(Z,[2,75]),t(Z,[2,76]),t(Z,[2,77]),t(Z,[2,78]),t(S,[2,57],{76:se}),t(S,[2,58],{76:$}),{5:Se,28:105,31:ce,34:ae,36:Oe,38:ge,40:ze},{27:[1,112],76:$},{5:He,40:$e,56:113,57:Re,59:Ie},{27:[1,118],76:$},{33:119,89:E,90:A},{33:120,89:E,90:A},{75:z,78:121,79:82,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X},t(te,[2,61]),t(te,[2,63]),t(Z,[2,68]),t(S,[2,21]),{32:[1,122]},{32:[1,123]},{32:[1,124]},{32:[1,125]},{5:Se,28:126,31:ce,34:ae,36:Oe,38:ge,40:ze},t(S,[2,28]),{5:[1,127]},t(S,[2,42]),{32:[1,128]},{32:[1,129]},{5:He,40:$e,56:130,57:Re,59:Ie},t(S,[2,47]),{5:[1,131]},t(S,[2,48]),t(S,[2,49]),t(ue,[2,66],{79:104,75:z,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X}),{33:132,89:E,90:A},{35:133,89:[1,134],90:[1,135]},{37:136,47:[1,137],48:[1,138],49:[1,139]},{39:140,50:[1,141],51:[1,142],52:[1,143],53:[1,144]},t(S,[2,27]),{5:Se,28:145,31:ce,34:ae,36:Oe,38:ge,40:ze},{58:146,89:[1,147],90:[1,148]},{60:149,89:[1,150],90:[1,151]},t(S,[2,46]),{5:He,40:$e,56:152,57:Re,59:Ie},{5:[1,153]},{5:[1,154]},{5:[2,83]},{5:[2,84]},{5:[1,155]},{5:[2,35]},{5:[2,36]},{5:[2,37]},{5:[1,156]},{5:[2,38]},{5:[2,39]},{5:[2,40]},{5:[2,41]},t(S,[2,22]),{5:[1,157]},{5:[2,87]},{5:[2,88]},{5:[1,158]},{5:[2,89]},{5:[2,90]},t(S,[2,43]),{5:Se,28:159,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:Se,28:160,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:Se,28:161,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:Se,28:162,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:He,40:$e,56:163,57:Re,59:Ie},{5:He,40:$e,56:164,57:Re,59:Ie},t(S,[2,23]),t(S,[2,24]),t(S,[2,25]),t(S,[2,26]),t(S,[2,44]),t(S,[2,45])],defaultActions:{8:[2,2],12:[2,1],41:[2,3],42:[2,8],43:[2,9],44:[2,10],45:[2,11],46:[2,12],47:[2,13],48:[2,14],49:[2,15],50:[2,16],134:[2,83],135:[2,84],137:[2,35],138:[2,36],139:[2,37],141:[2,38],142:[2,39],143:[2,40],144:[2,41],147:[2,87],148:[2,88],150:[2,89],151:[2,90]},parseError:o(function(oe,V){if(V.recoverable)this.trace(oe);else{var xe=new Error(oe);throw xe.hash=V,xe}},"parseError"),parse:o(function(oe){var V=this,xe=[0],q=[],pe=[null],ve=[],Pe=this.table,_e="",we=0,Ve=0,De=0,qe=2,at=1,Rt=ve.slice.call(arguments,1),st=Object.create(this.lexer),Ue={yy:{}};for(var ct in this.yy)Object.prototype.hasOwnProperty.call(this.yy,ct)&&(Ue.yy[ct]=this.yy[ct]);st.setInput(oe,Ue.yy),Ue.yy.lexer=st,Ue.yy.parser=this,typeof st.yylloc>"u"&&(st.yylloc={});var We=st.yylloc;ve.push(We);var ot=st.options&&st.options.ranges;typeof Ue.yy.parseError=="function"?this.parseError=Ue.yy.parseError:this.parseError=Object.getPrototypeOf(this).parseError;function Yt(Dr){xe.length=xe.length-2*Dr,pe.length=pe.length-Dr,ve.length=ve.length-Dr}o(Yt,"popStack");function bt(){var Dr;return Dr=q.pop()||st.lex()||at,typeof Dr!="number"&&(Dr instanceof Array&&(q=Dr,Dr=q.pop()),Dr=V.symbols_[Dr]||Dr),Dr}o(bt,"lex");for(var Mt,xt,ut,Et,ft,yt,nt={},dn,Tt,On,tn;;){if(ut=xe[xe.length-1],this.defaultActions[ut]?Et=this.defaultActions[ut]:((Mt===null||typeof Mt>"u")&&(Mt=bt()),Et=Pe[ut]&&Pe[ut][Mt]),typeof Et>"u"||!Et.length||!Et[0]){var _r="";tn=[];for(dn in Pe[ut])this.terminals_[dn]&&dn>qe&&tn.push("'"+this.terminals_[dn]+"'");st.showPosition?_r="Parse error on line "+(we+1)+`: +`+st.showPosition()+` +Expecting `+tn.join(", ")+", got '"+(this.terminals_[Mt]||Mt)+"'":_r="Parse error on line "+(we+1)+": Unexpected "+(Mt==at?"end of input":"'"+(this.terminals_[Mt]||Mt)+"'"),this.parseError(_r,{text:st.match,token:this.terminals_[Mt]||Mt,line:st.yylineno,loc:We,expected:tn})}if(Et[0]instanceof Array&&Et.length>1)throw new Error("Parse Error: multiple actions possible at state: "+ut+", token: "+Mt);switch(Et[0]){case 1:xe.push(Mt),pe.push(st.yytext),ve.push(st.yylloc),xe.push(Et[1]),Mt=null,xt?(Mt=xt,xt=null):(Ve=st.yyleng,_e=st.yytext,we=st.yylineno,We=st.yylloc,De>0&&De--);break;case 2:if(Tt=this.productions_[Et[1]][1],nt.$=pe[pe.length-Tt],nt._$={first_line:ve[ve.length-(Tt||1)].first_line,last_line:ve[ve.length-1].last_line,first_column:ve[ve.length-(Tt||1)].first_column,last_column:ve[ve.length-1].last_column},ot&&(nt._$.range=[ve[ve.length-(Tt||1)].range[0],ve[ve.length-1].range[1]]),yt=this.performAction.apply(nt,[_e,Ve,we,Ue.yy,Et[1],pe,ve].concat(Rt)),typeof yt<"u")return yt;Tt&&(xe=xe.slice(0,-1*Tt*2),pe=pe.slice(0,-1*Tt),ve=ve.slice(0,-1*Tt)),xe.push(this.productions_[Et[1]][0]),pe.push(nt.$),ve.push(nt._$),On=Pe[xe[xe.length-2]][xe[xe.length-1]],xe.push(On);break;case 3:return!0}}return!0},"parse")},W=function(){var re={EOF:1,parseError:o(function(V,xe){if(this.yy.parser)this.yy.parser.parseError(V,xe);else throw new Error(V)},"parseError"),setInput:o(function(oe,V){return this.yy=V||this.yy||{},this._input=oe,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var oe=this._input[0];this.yytext+=oe,this.yyleng++,this.offset++,this.match+=oe,this.matched+=oe;var V=oe.match(/(?:\r\n?|\n).*/g);return V?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),oe},"input"),unput:o(function(oe){var V=oe.length,xe=oe.split(/(?:\r\n?|\n)/g);this._input=oe+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-V),this.offset-=V;var q=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),xe.length-1&&(this.yylineno-=xe.length-1);var pe=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:xe?(xe.length===q.length?this.yylloc.first_column:0)+q[q.length-xe.length].length-xe[0].length:this.yylloc.first_column-V},this.options.ranges&&(this.yylloc.range=[pe[0],pe[0]+this.yyleng-V]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). +`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(oe){this.unput(this.match.slice(oe))},"less"),pastInput:o(function(){var oe=this.matched.substr(0,this.matched.length-this.match.length);return(oe.length>20?"...":"")+oe.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var oe=this.match;return oe.length<20&&(oe+=this._input.substr(0,20-oe.length)),(oe.substr(0,20)+(oe.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var oe=this.pastInput(),V=new Array(oe.length+1).join("-");return oe+this.upcomingInput()+` +`+V+"^"},"showPosition"),test_match:o(function(oe,V){var xe,q,pe;if(this.options.backtrack_lexer&&(pe={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(pe.yylloc.range=this.yylloc.range.slice(0))),q=oe[0].match(/(?:\r\n?|\n).*/g),q&&(this.yylineno+=q.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:q?q[q.length-1].length-q[q.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+oe[0].length},this.yytext+=oe[0],this.match+=oe[0],this.matches=oe,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(oe[0].length),this.matched+=oe[0],xe=this.performAction.call(this,this.yy,this,V,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),xe)return xe;if(this._backtrack){for(var ve in pe)this[ve]=pe[ve];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var oe,V,xe,q;this._more||(this.yytext="",this.match="");for(var pe=this._currentRules(),ve=0;veV[0].length)){if(V=xe,q=ve,this.options.backtrack_lexer){if(oe=this.test_match(xe,pe[ve]),oe!==!1)return oe;if(this._backtrack){V=!1;continue}else return!1}else if(!this.options.flex)break}return V?(oe=this.test_match(V,pe[q]),oe!==!1?oe:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. +`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var V=this.next();return V||this.lex()},"lex"),begin:o(function(V){this.conditionStack.push(V)},"begin"),popState:o(function(){var V=this.conditionStack.length-1;return V>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(V){return V=this.conditionStack.length-1-Math.abs(V||0),V>=0?this.conditionStack[V]:"INITIAL"},"topState"),pushState:o(function(V){this.begin(V)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{"case-insensitive":!0},performAction:o(function(V,xe,q,pe){var ve=pe;switch(q){case 0:return"title";case 1:return this.begin("acc_title"),9;break;case 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49:return this.begin("style"),77;break;case 50:return 75;case 51:return 81;case 52:return 88;case 53:return"PERCENT";case 54:return 86;case 55:return 84;case 56:break;case 57:this.begin("string");break;case 58:this.popState();break;case 59:return this.begin("style"),72;break;case 60:return this.begin("style"),74;break;case 61:return 61;case 62:return 64;case 63:return 63;case 64:this.begin("string");break;case 65:this.popState();break;case 66:return"qString";case 67:return xe.yytext=xe.yytext.trim(),89;break;case 68:return 75;case 69:return 80;case 70:return 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40:Z[ce-1].unshift({type:"criticalStart",criticalText:se.parseMessage(Z[ce-2]),signalType:se.LINETYPE.CRITICAL_START}),Z[ce-1].push({type:"criticalEnd",signalType:se.LINETYPE.CRITICAL_END}),this.$=Z[ce-1];break;case 41:Z[ce-1].unshift({type:"breakStart",breakText:se.parseMessage(Z[ce-2]),signalType:se.LINETYPE.BREAK_START}),Z[ce-1].push({type:"breakEnd",optText:se.parseMessage(Z[ce-2]),signalType:se.LINETYPE.BREAK_END}),this.$=Z[ce-1];break;case 43:this.$=Z[ce-3].concat([{type:"option",optionText:se.parseMessage(Z[ce-1]),signalType:se.LINETYPE.CRITICAL_OPTION},Z[ce]]);break;case 45:this.$=Z[ce-3].concat([{type:"and",parText:se.parseMessage(Z[ce-1]),signalType:se.LINETYPE.PAR_AND},Z[ce]]);break;case 47:this.$=Z[ce-3].concat([{type:"else",altText:se.parseMessage(Z[ce-1]),signalType:se.LINETYPE.ALT_ELSE},Z[ce]]);break;case 48:Z[ce-3].draw="participant",Z[ce-3].type="addParticipant",Z[ce-3].description=se.parseMessage(Z[ce-1]),this.$=Z[ce-3];break;case 49:Z[ce-1].draw="participant",Z[ce-1].type="addParticipant",this.$=Z[ce-1];break;case 50:Z[ce-3].draw="actor",Z[ce-3].type="addParticipant",Z[ce-3].description=se.parseMessage(Z[ce-1]),this.$=Z[ce-3];break;case 51:Z[ce-1].draw="actor",Z[ce-1].type="addParticipant",this.$=Z[ce-1];break;case 52:Z[ce-1].type="destroyParticipant",this.$=Z[ce-1];break;case 53:this.$=[Z[ce-1],{type:"addNote",placement:Z[ce-2],actor:Z[ce-1].actor,text:Z[ce]}];break;case 54:Z[ce-2]=[].concat(Z[ce-1],Z[ce-1]).slice(0,2),Z[ce-2][0]=Z[ce-2][0].actor,Z[ce-2][1]=Z[ce-2][1].actor,this.$=[Z[ce-1],{type:"addNote",placement:se.PLACEMENT.OVER,actor:Z[ce-2].slice(0,2),text:Z[ce]}];break;case 55:this.$=[Z[ce-1],{type:"addLinks",actor:Z[ce-1].actor,text:Z[ce]}];break;case 56:this.$=[Z[ce-1],{type:"addALink",actor:Z[ce-1].actor,text:Z[ce]}];break;case 57:this.$=[Z[ce-1],{type:"addProperties",actor:Z[ce-1].actor,text:Z[ce]}];break;case 58:this.$=[Z[ce-1],{type:"addDetails",actor:Z[ce-1].actor,text:Z[ce]}];break;case 61:this.$=[Z[ce-2],Z[ce]];break;case 62:this.$=Z[ce];break;case 63:this.$=se.PLACEMENT.LEFTOF;break;case 64:this.$=se.PLACEMENT.RIGHTOF;break;case 65:this.$=[Z[ce-4],Z[ce-1],{type:"addMessage",from:Z[ce-4].actor,to:Z[ce-1].actor,signalType:Z[ce-3],msg:Z[ce],activate:!0},{type:"activeStart",signalType:se.LINETYPE.ACTIVE_START,actor:Z[ce-1].actor}];break;case 66:this.$=[Z[ce-4],Z[ce-1],{type:"addMessage",from:Z[ce-4].actor,to:Z[ce-1].actor,signalType:Z[ce-3],msg:Z[ce]},{type:"activeEnd",signalType:se.LINETYPE.ACTIVE_END,actor:Z[ce-4].actor}];break;case 67:this.$=[Z[ce-3],Z[ce-1],{type:"addMessage",from:Z[ce-3].actor,to:Z[ce-1].actor,signalType:Z[ce-2],msg:Z[ce]}];break;case 68:this.$={type:"addParticipant",actor:Z[ce]};break;case 69:this.$=se.LINETYPE.SOLID_OPEN;break;case 70:this.$=se.LINETYPE.DOTTED_OPEN;break;case 71:this.$=se.LINETYPE.SOLID;break;case 72:this.$=se.LINETYPE.BIDIRECTIONAL_SOLID;break;case 73:this.$=se.LINETYPE.DOTTED;break;case 74:this.$=se.LINETYPE.BIDIRECTIONAL_DOTTED;break;case 75:this.$=se.LINETYPE.SOLID_CROSS;break;case 76:this.$=se.LINETYPE.DOTTED_CROSS;break;case 77:this.$=se.LINETYPE.SOLID_POINT;break;case 78:this.$=se.LINETYPE.DOTTED_POINT;break;case 79:this.$=se.parseMessage(Z[ce].trim().substring(1));break}},"anonymous"),table:[{3:1,4:e,5:r,6:n},{1:[3]},{3:5,4:e,5:r,6:n},{3:6,4:e,5:r,6:n},t([1,4,5,13,14,18,21,23,29,30,31,33,35,36,37,38,39,41,43,44,46,50,52,53,54,59,60,61,62,70],i,{7:7}),{1:[2,1]},{1:[2,2]},{1:[2,3],4:a,5:s,8:8,9:10,12:12,13:l,14:u,17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},t(F,[2,5]),{9:47,12:12,13:l,14:u,17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},t(F,[2,7]),t(F,[2,8]),t(F,[2,14]),{12:48,50:_,52:I,53:D},{15:[1,49]},{5:[1,50]},{5:[1,53],19:[1,51],20:[1,52]},{22:54,70:B},{22:55,70:B},{5:[1,56]},{5:[1,57]},{5:[1,58]},{5:[1,59]},{5:[1,60]},t(F,[2,29]),t(F,[2,30]),{32:[1,61]},{34:[1,62]},t(F,[2,33]),{15:[1,63]},{15:[1,64]},{15:[1,65]},{15:[1,66]},{15:[1,67]},{15:[1,68]},{15:[1,69]},{15:[1,70]},{22:71,70:B},{22:72,70:B},{22:73,70:B},{67:74,71:[1,75],72:[1,76],73:[1,77],74:[1,78],75:[1,79],76:[1,80],77:[1,81],78:[1,82],79:[1,83],80:[1,84]},{55:85,57:[1,86],65:[1,87],66:[1,88]},{22:89,70:B},{22:90,70:B},{22:91,70:B},{22:92,70:B},t([5,51,64,71,72,73,74,75,76,77,78,79,80,81],[2,68]),t(F,[2,6]),t(F,[2,15]),t(P,[2,9],{10:93}),t(F,[2,17]),{5:[1,95],19:[1,94]},{5:[1,96]},t(F,[2,21]),{5:[1,97]},{5:[1,98]},t(F,[2,24]),t(F,[2,25]),t(F,[2,26]),t(F,[2,27]),t(F,[2,28]),t(F,[2,31]),t(F,[2,32]),t(z,i,{7:99}),t(z,i,{7:100}),t(z,i,{7:101}),t($,i,{40:102,7:103}),t(H,i,{42:104,7:105}),t(H,i,{7:105,42:106}),t(Q,i,{45:107,7:108}),t(z,i,{7:109}),{5:[1,111],51:[1,110]},{5:[1,113],51:[1,112]},{5:[1,114]},{22:117,68:[1,115],69:[1,116],70:B},t(j,[2,69]),t(j,[2,70]),t(j,[2,71]),t(j,[2,72]),t(j,[2,73]),t(j,[2,74]),t(j,[2,75]),t(j,[2,76]),t(j,[2,77]),t(j,[2,78]),{22:118,70:B},{22:120,58:119,70:B},{70:[2,63]},{70:[2,64]},{56:121,81:ie},{56:123,81:ie},{56:124,81:ie},{56:125,81:ie},{4:[1,128],5:[1,130],11:127,12:129,16:[1,126],50:_,52:I,53:D},{5:[1,131]},t(F,[2,19]),t(F,[2,20]),t(F,[2,22]),t(F,[2,23]),{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,132],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,133],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,134],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{16:[1,135]},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[2,46],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,49:[1,136],50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{16:[1,137]},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[2,44],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,48:[1,138],50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{16:[1,139]},{16:[1,140]},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[2,42],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,47:[1,141],50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,142],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{15:[1,143]},t(F,[2,49]),{15:[1,144]},t(F,[2,51]),t(F,[2,52]),{22:145,70:B},{22:146,70:B},{56:147,81:ie},{56:148,81:ie},{56:149,81:ie},{64:[1,150],81:[2,62]},{5:[2,55]},{5:[2,79]},{5:[2,56]},{5:[2,57]},{5:[2,58]},t(F,[2,16]),t(P,[2,10]),{12:151,50:_,52:I,53:D},t(P,[2,12]),t(P,[2,13]),t(F,[2,18]),t(F,[2,34]),t(F,[2,35]),t(F,[2,36]),t(F,[2,37]),{15:[1,152]},t(F,[2,38]),{15:[1,153]},t(F,[2,39]),t(F,[2,40]),{15:[1,154]},t(F,[2,41]),{5:[1,155]},{5:[1,156]},{56:157,81:ie},{56:158,81:ie},{5:[2,67]},{5:[2,53]},{5:[2,54]},{22:159,70:B},t(P,[2,11]),t($,i,{7:103,40:160}),t(H,i,{7:105,42:161}),t(Q,i,{7:108,45:162}),t(F,[2,48]),t(F,[2,50]),{5:[2,65]},{5:[2,66]},{81:[2,61]},{16:[2,47]},{16:[2,45]},{16:[2,43]}],defaultActions:{5:[2,1],6:[2,2],87:[2,63],88:[2,64],121:[2,55],122:[2,79],123:[2,56],124:[2,57],125:[2,58],147:[2,67],148:[2,53],149:[2,54],157:[2,65],158:[2,66],159:[2,61],160:[2,47],161:[2,45],162:[2,43]},parseError:o(function(X,te){if(te.recoverable)this.trace(X);else{var J=new Error(X);throw J.hash=te,J}},"parseError"),parse:o(function(X){var te=this,J=[0],se=[],ue=[null],Z=[],Se=this.table,ce="",ae=0,Oe=0,ge=0,ze=2,He=1,$e=Z.slice.call(arguments,1),Re=Object.create(this.lexer),Ie={yy:{}};for(var be in this.yy)Object.prototype.hasOwnProperty.call(this.yy,be)&&(Ie.yy[be]=this.yy[be]);Re.setInput(X,Ie.yy),Ie.yy.lexer=Re,Ie.yy.parser=this,typeof Re.yylloc>"u"&&(Re.yylloc={});var W=Re.yylloc;Z.push(W);var de=Re.options&&Re.options.ranges;typeof Ie.yy.parseError=="function"?this.parseError=Ie.yy.parseError:this.parseError=Object.getPrototypeOf(this).parseError;function re(Rt){J.length=J.length-2*Rt,ue.length=ue.length-Rt,Z.length=Z.length-Rt}o(re,"popStack");function oe(){var Rt;return Rt=se.pop()||Re.lex()||He,typeof Rt!="number"&&(Rt instanceof Array&&(se=Rt,Rt=se.pop()),Rt=te.symbols_[Rt]||Rt),Rt}o(oe,"lex");for(var V,xe,q,pe,ve,Pe,_e={},we,Ve,De,qe;;){if(q=J[J.length-1],this.defaultActions[q]?pe=this.defaultActions[q]:((V===null||typeof V>"u")&&(V=oe()),pe=Se[q]&&Se[q][V]),typeof pe>"u"||!pe.length||!pe[0]){var at="";qe=[];for(we in Se[q])this.terminals_[we]&&we>ze&&qe.push("'"+this.terminals_[we]+"'");Re.showPosition?at="Parse error on line "+(ae+1)+`: +`+Re.showPosition()+` +Expecting `+qe.join(", ")+", got '"+(this.terminals_[V]||V)+"'":at="Parse error on line "+(ae+1)+": Unexpected "+(V==He?"end of input":"'"+(this.terminals_[V]||V)+"'"),this.parseError(at,{text:Re.match,token:this.terminals_[V]||V,line:Re.yylineno,loc:W,expected:qe})}if(pe[0]instanceof Array&&pe.length>1)throw new Error("Parse Error: multiple actions possible at state: "+q+", token: "+V);switch(pe[0]){case 1:J.push(V),ue.push(Re.yytext),Z.push(Re.yylloc),J.push(pe[1]),V=null,xe?(V=xe,xe=null):(Oe=Re.yyleng,ce=Re.yytext,ae=Re.yylineno,W=Re.yylloc,ge>0&&ge--);break;case 2:if(Ve=this.productions_[pe[1]][1],_e.$=ue[ue.length-Ve],_e._$={first_line:Z[Z.length-(Ve||1)].first_line,last_line:Z[Z.length-1].last_line,first_column:Z[Z.length-(Ve||1)].first_column,last_column:Z[Z.length-1].last_column},de&&(_e._$.range=[Z[Z.length-(Ve||1)].range[0],Z[Z.length-1].range[1]]),Pe=this.performAction.apply(_e,[ce,Oe,ae,Ie.yy,pe[1],ue,Z].concat($e)),typeof Pe<"u")return Pe;Ve&&(J=J.slice(0,-1*Ve*2),ue=ue.slice(0,-1*Ve),Z=Z.slice(0,-1*Ve)),J.push(this.productions_[pe[1]][0]),ue.push(_e.$),Z.push(_e._$),De=Se[J[J.length-2]][J[J.length-1]],J.push(De);break;case 3:return!0}}return!0},"parse")},le=function(){var K={EOF:1,parseError:o(function(te,J){if(this.yy.parser)this.yy.parser.parseError(te,J);else throw new Error(te)},"parseError"),setInput:o(function(X,te){return this.yy=te||this.yy||{},this._input=X,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var X=this._input[0];this.yytext+=X,this.yyleng++,this.offset++,this.match+=X,this.matched+=X;var te=X.match(/(?:\r\n?|\n).*/g);return te?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),X},"input"),unput:o(function(X){var te=X.length,J=X.split(/(?:\r\n?|\n)/g);this._input=X+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-te),this.offset-=te;var se=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),J.length-1&&(this.yylineno-=J.length-1);var ue=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:J?(J.length===se.length?this.yylloc.first_column:0)+se[se.length-J.length].length-J[0].length:this.yylloc.first_column-te},this.options.ranges&&(this.yylloc.range=[ue[0],ue[0]+this.yyleng-te]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). +`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(X){this.unput(this.match.slice(X))},"less"),pastInput:o(function(){var X=this.matched.substr(0,this.matched.length-this.match.length);return(X.length>20?"...":"")+X.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var X=this.match;return X.length<20&&(X+=this._input.substr(0,20-X.length)),(X.substr(0,20)+(X.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var X=this.pastInput(),te=new Array(X.length+1).join("-");return X+this.upcomingInput()+` +`+te+"^"},"showPosition"),test_match:o(function(X,te){var J,se,ue;if(this.options.backtrack_lexer&&(ue={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(ue.yylloc.range=this.yylloc.range.slice(0))),se=X[0].match(/(?:\r\n?|\n).*/g),se&&(this.yylineno+=se.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:se?se[se.length-1].length-se[se.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+X[0].length},this.yytext+=X[0],this.match+=X[0],this.matches=X,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(X[0].length),this.matched+=X[0],J=this.performAction.call(this,this.yy,this,te,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),J)return J;if(this._backtrack){for(var Z in ue)this[Z]=ue[Z];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var X,te,J,se;this._more||(this.yytext="",this.match="");for(var ue=this._currentRules(),Z=0;Zte[0].length)){if(te=J,se=Z,this.options.backtrack_lexer){if(X=this.test_match(J,ue[Z]),X!==!1)return X;if(this._backtrack){te=!1;continue}else return!1}else if(!this.options.flex)break}return te?(X=this.test_match(te,ue[se]),X!==!1?X:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. +`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var te=this.next();return te||this.lex()},"lex"),begin:o(function(te){this.conditionStack.push(te)},"begin"),popState:o(function(){var te=this.conditionStack.length-1;return te>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(te){return te=this.conditionStack.length-1-Math.abs(te||0),te>=0?this.conditionStack[te]:"INITIAL"},"topState"),pushState:o(function(te){this.begin(te)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{"case-insensitive":!0},performAction:o(function(te,J,se,ue){var Z=ue;switch(se){case 0:return 5;case 1:break;case 2:break;case 3:break;case 4:break;case 5:break;case 6:return 19;case 7:return this.begin("LINE"),14;break;case 8:return this.begin("ID"),50;break;case 9:return this.begin("ID"),52;break;case 10:return 13;case 11:return this.begin("ID"),53;break;case 12:return J.yytext=J.yytext.trim(),this.begin("ALIAS"),70;break;case 13:return this.popState(),this.popState(),this.begin("LINE"),51;break;case 14:return this.popState(),this.popState(),5;break;case 15:return this.begin("LINE"),36;break;case 16:return this.begin("LINE"),37;break;case 17:return this.begin("LINE"),38;break;case 18:return this.begin("LINE"),39;break;case 19:return this.begin("LINE"),49;break;case 20:return this.begin("LINE"),41;break;case 21:return this.begin("LINE"),43;break;case 22:return this.begin("LINE"),48;break;case 23:return this.begin("LINE"),44;break;case 24:return this.begin("LINE"),47;break;case 25:return this.begin("LINE"),46;break;case 26:return this.popState(),15;break;case 27:return 16;case 28:return 65;case 29:return 66;case 30:return 59;case 31:return 60;case 32:return 61;case 33:return 62;case 34:return 57;case 35:return 54;case 36:return this.begin("ID"),21;break;case 37:return this.begin("ID"),23;break;case 38:return 29;case 39:return 30;case 40:return this.begin("acc_title"),31;break;case 41:return this.popState(),"acc_title_value";break;case 42:return this.begin("acc_descr"),33;break;case 43:return this.popState(),"acc_descr_value";break;case 44:this.begin("acc_descr_multiline");break;case 45:this.popState();break;case 46:return"acc_descr_multiline_value";case 47:return 6;case 48:return 18;case 49:return 20;case 50:return 64;case 51:return 5;case 52:return J.yytext=J.yytext.trim(),70;break;case 53:return 73;case 54:return 74;case 55:return 75;case 56:return 76;case 57:return 71;case 58:return 72;case 59:return 77;case 60:return 78;case 61:return 79;case 62:return 80;case 63:return 81;case 64:return 68;case 65:return 69;case 66:return 5;case 67:return"INVALID"}},"anonymous"),rules:[/^(?:[\n]+)/i,/^(?:\s+)/i,/^(?:((?!\n)\s)+)/i,/^(?:#[^\n]*)/i,/^(?:%(?!\{)[^\n]*)/i,/^(?:[^\}]%%[^\n]*)/i,/^(?:[0-9]+(?=[ \n]+))/i,/^(?:box\b)/i,/^(?:participant\b)/i,/^(?:actor\b)/i,/^(?:create\b)/i,/^(?:destroy\b)/i,/^(?:[^\<->\->:\n,;]+?([\-]*[^\<->\->:\n,;]+?)*?(?=((?!\n)\s)+as(?!\n)\s|[#\n;]|$))/i,/^(?:as\b)/i,/^(?:(?:))/i,/^(?:loop\b)/i,/^(?:rect\b)/i,/^(?:opt\b)/i,/^(?:alt\b)/i,/^(?:else\b)/i,/^(?:par\b)/i,/^(?:par_over\b)/i,/^(?:and\b)/i,/^(?:critical\b)/i,/^(?:option\b)/i,/^(?:break\b)/i,/^(?:(?:[:]?(?:no)?wrap)?[^#\n;]*)/i,/^(?:end\b)/i,/^(?:left of\b)/i,/^(?:right of\b)/i,/^(?:links\b)/i,/^(?:link\b)/i,/^(?:properties\b)/i,/^(?:details\b)/i,/^(?:over\b)/i,/^(?:note\b)/i,/^(?:activate\b)/i,/^(?:deactivate\b)/i,/^(?:title\s[^#\n;]+)/i,/^(?:title:\s[^#\n;]+)/i,/^(?:accTitle\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*\{\s*)/i,/^(?:[\}])/i,/^(?:[^\}]*)/i,/^(?:sequenceDiagram\b)/i,/^(?:autonumber\b)/i,/^(?:off\b)/i,/^(?:,)/i,/^(?:;)/i,/^(?:[^\+\<->\->:\n,;]+((?!(-x|--x|-\)|--\)))[\-]*[^\+\<->\->:\n,;]+)*)/i,/^(?:->>)/i,/^(?:<<->>)/i,/^(?:-->>)/i,/^(?:<<-->>)/i,/^(?:->)/i,/^(?:-->)/i,/^(?:-[x])/i,/^(?:--[x])/i,/^(?:-[\)])/i,/^(?:--[\)])/i,/^(?::(?:(?:no)?wrap)?[^#\n;]+)/i,/^(?:\+)/i,/^(?:-)/i,/^(?:$)/i,/^(?:.)/i],conditions:{acc_descr_multiline:{rules:[45,46],inclusive:!1},acc_descr:{rules:[43],inclusive:!1},acc_title:{rules:[41],inclusive:!1},ID:{rules:[2,3,12],inclusive:!1},ALIAS:{rules:[2,3,13,14],inclusive:!1},LINE:{rules:[2,3,26],inclusive:!1},INITIAL:{rules:[0,1,3,4,5,6,7,8,9,10,11,15,16,17,18,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,35,36,37,38,39,40,42,44,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67],inclusive:!0}}};return K}();ne.lexer=le;function he(){this.yy={}}return o(he,"Parser"),he.prototype=ne,ne.Parser=he,new he}();CO.parser=CO;lfe=CO});var iVe,aVe,sVe,_6,ufe=N(()=>{"use strict";zt();vt();s6();gr();mi();iVe={SOLID:0,DOTTED:1,NOTE:2,SOLID_CROSS:3,DOTTED_CROSS:4,SOLID_OPEN:5,DOTTED_OPEN:6,LOOP_START:10,LOOP_END:11,ALT_START:12,ALT_ELSE:13,ALT_END:14,OPT_START:15,OPT_END:16,ACTIVE_START:17,ACTIVE_END:18,PAR_START:19,PAR_AND:20,PAR_END:21,RECT_START:22,RECT_END:23,SOLID_POINT:24,DOTTED_POINT:25,AUTONUMBER:26,CRITICAL_START:27,CRITICAL_OPTION:28,CRITICAL_END:29,BREAK_START:30,BREAK_END:31,PAR_OVER_START:32,BIDIRECTIONAL_SOLID:33,BIDIRECTIONAL_DOTTED:34},aVe={FILLED:0,OPEN:1},sVe={LEFTOF:0,RIGHTOF:1,OVER:2},_6=class{constructor(){this.state=new pf(()=>({prevActor:void 0,actors:new Map,createdActors:new Map,destroyedActors:new Map,boxes:[],messages:[],notes:[],sequenceNumbersEnabled:!1,wrapEnabled:void 0,currentBox:void 0,lastCreated:void 0,lastDestroyed:void 0}));this.setAccTitle=Lr;this.setAccDescription=Nr;this.setDiagramTitle=$r;this.getAccTitle=Rr;this.getAccDescription=Mr;this.getDiagramTitle=Ir;this.apply=this.apply.bind(this),this.parseBoxData=this.parseBoxData.bind(this),this.parseMessage=this.parseMessage.bind(this),this.clear(),this.setWrap(me().wrap),this.LINETYPE=iVe,this.ARROWTYPE=aVe,this.PLACEMENT=sVe}static{o(this,"SequenceDB")}addBox(e){this.state.records.boxes.push({name:e.text,wrap:e.wrap??this.autoWrap(),fill:e.color,actorKeys:[]}),this.state.records.currentBox=this.state.records.boxes.slice(-1)[0]}addActor(e,r,n,i){let a=this.state.records.currentBox,s=this.state.records.actors.get(e);if(s){if(this.state.records.currentBox&&s.box&&this.state.records.currentBox!==s.box)throw new Error(`A same participant should only be defined in one Box: ${s.name} can't be in '${s.box.name}' and in '${this.state.records.currentBox.name}' at the same time.`);if(a=s.box?s.box:this.state.records.currentBox,s.box=a,s&&r===s.name&&n==null)return}if(n?.text==null&&(n={text:r,type:i}),(i==null||n.text==null)&&(n={text:r,type:i}),this.state.records.actors.set(e,{box:a,name:r,description:n.text,wrap:n.wrap??this.autoWrap(),prevActor:this.state.records.prevActor,links:{},properties:{},actorCnt:null,rectData:null,type:i??"participant"}),this.state.records.prevActor){let l=this.state.records.actors.get(this.state.records.prevActor);l&&(l.nextActor=e)}this.state.records.currentBox&&this.state.records.currentBox.actorKeys.push(e),this.state.records.prevActor=e}activationCount(e){let r,n=0;if(!e)return 0;for(r=0;r>-",token:"->>-",line:"1",loc:{first_line:1,last_line:1,first_column:1,last_column:1},expected:["'ACTIVE_PARTICIPANT'"]},l}return this.state.records.messages.push({id:this.state.records.messages.length.toString(),from:e,to:r,message:n?.text??"",wrap:n?.wrap??this.autoWrap(),type:i,activate:a}),!0}hasAtLeastOneBox(){return this.state.records.boxes.length>0}hasAtLeastOneBoxWithTitle(){return this.state.records.boxes.some(e=>e.name)}getMessages(){return this.state.records.messages}getBoxes(){return this.state.records.boxes}getActors(){return this.state.records.actors}getCreatedActors(){return this.state.records.createdActors}getDestroyedActors(){return this.state.records.destroyedActors}getActor(e){return this.state.records.actors.get(e)}getActorKeys(){return[...this.state.records.actors.keys()]}enableSequenceNumbers(){this.state.records.sequenceNumbersEnabled=!0}disableSequenceNumbers(){this.state.records.sequenceNumbersEnabled=!1}showSequenceNumbers(){return this.state.records.sequenceNumbersEnabled}setWrap(e){this.state.records.wrapEnabled=e}extractWrap(e){if(e===void 0)return{};e=e.trim();let r=/^:?wrap:/.exec(e)!==null?!0:/^:?nowrap:/.exec(e)!==null?!1:void 0;return{cleanedText:(r===void 0?e:e.replace(/^:?(?:no)?wrap:/,"")).trim(),wrap:r}}autoWrap(){return this.state.records.wrapEnabled!==void 0?this.state.records.wrapEnabled:me().sequence?.wrap??!1}clear(){this.state.reset(),Ar()}parseMessage(e){let r=e.trim(),{wrap:n,cleanedText:i}=this.extractWrap(r),a={text:i,wrap:n};return Y.debug(`parseMessage: ${JSON.stringify(a)}`),a}parseBoxData(e){let r=/^((?:rgba?|hsla?)\s*\(.*\)|\w*)(.*)$/.exec(e),n=r?.[1]?r[1].trim():"transparent",i=r?.[2]?r[2].trim():void 0;if(window?.CSS)window.CSS.supports("color",n)||(n="transparent",i=e.trim());else{let l=new Option().style;l.color=n,l.color!==n&&(n="transparent",i=e.trim())}let{wrap:a,cleanedText:s}=this.extractWrap(i);return{text:s?Tr(s,me()):void 0,color:n,wrap:a}}addNote(e,r,n){let i={actor:e,placement:r,message:n.text,wrap:n.wrap??this.autoWrap()},a=[].concat(e,e);this.state.records.notes.push(i),this.state.records.messages.push({id:this.state.records.messages.length.toString(),from:a[0],to:a[1],message:n.text,wrap:n.wrap??this.autoWrap(),type:this.LINETYPE.NOTE,placement:r})}addLinks(e,r){let n=this.getActor(e);try{let i=Tr(r.text,me());i=i.replace(/=/g,"="),i=i.replace(/&/g,"&");let a=JSON.parse(i);this.insertLinks(n,a)}catch(i){Y.error("error while parsing actor link text",i)}}addALink(e,r){let n=this.getActor(e);try{let i={},a=Tr(r.text,me()),s=a.indexOf("@");a=a.replace(/=/g,"="),a=a.replace(/&/g,"&");let l=a.slice(0,s-1).trim(),u=a.slice(s+1).trim();i[l]=u,this.insertLinks(n,i)}catch(i){Y.error("error while parsing actor link text",i)}}insertLinks(e,r){if(e.links==null)e.links=r;else for(let n in r)e.links[n]=r[n]}addProperties(e,r){let n=this.getActor(e);try{let i=Tr(r.text,me()),a=JSON.parse(i);this.insertProperties(n,a)}catch(i){Y.error("error while parsing actor properties text",i)}}insertProperties(e,r){if(e.properties==null)e.properties=r;else for(let n in r)e.properties[n]=r[n]}boxEnd(){this.state.records.currentBox=void 0}addDetails(e,r){let n=this.getActor(e),i=document.getElementById(r.text);try{let a=i.innerHTML,s=JSON.parse(a);s.properties&&this.insertProperties(n,s.properties),s.links&&this.insertLinks(n,s.links)}catch(a){Y.error("error while parsing actor details text",a)}}getActorProperty(e,r){if(e?.properties!==void 0)return e.properties[r]}apply(e){if(Array.isArray(e))e.forEach(r=>{this.apply(r)});else switch(e.type){case"sequenceIndex":this.state.records.messages.push({id:this.state.records.messages.length.toString(),from:void 0,to:void 0,message:{start:e.sequenceIndex,step:e.sequenceIndexStep,visible:e.sequenceVisible},wrap:!1,type:e.signalType});break;case"addParticipant":this.addActor(e.actor,e.actor,e.description,e.draw);break;case"createParticipant":if(this.state.records.actors.has(e.actor))throw new Error("It is not possible to have actors with the same id, even if one is destroyed before the next is created. Use 'AS' aliases to simulate the behavior");this.state.records.lastCreated=e.actor,this.addActor(e.actor,e.actor,e.description,e.draw),this.state.records.createdActors.set(e.actor,this.state.records.messages.length);break;case"destroyParticipant":this.state.records.lastDestroyed=e.actor,this.state.records.destroyedActors.set(e.actor,this.state.records.messages.length);break;case"activeStart":this.addSignal(e.actor,void 0,void 0,e.signalType);break;case"activeEnd":this.addSignal(e.actor,void 0,void 0,e.signalType);break;case"addNote":this.addNote(e.actor,e.placement,e.text);break;case"addLinks":this.addLinks(e.actor,e.text);break;case"addALink":this.addALink(e.actor,e.text);break;case"addProperties":this.addProperties(e.actor,e.text);break;case"addDetails":this.addDetails(e.actor,e.text);break;case"addMessage":if(this.state.records.lastCreated){if(e.to!==this.state.records.lastCreated)throw new Error("The created participant "+this.state.records.lastCreated.name+" does not have an associated creating message after its declaration. Please check the sequence diagram.");this.state.records.lastCreated=void 0}else if(this.state.records.lastDestroyed){if(e.to!==this.state.records.lastDestroyed&&e.from!==this.state.records.lastDestroyed)throw new Error("The destroyed participant "+this.state.records.lastDestroyed.name+" does not have an associated destroying message after its declaration. Please check the sequence diagram.");this.state.records.lastDestroyed=void 0}this.addSignal(e.from,e.to,e.msg,e.signalType,e.activate);break;case"boxStart":this.addBox(e.boxData);break;case"boxEnd":this.boxEnd();break;case"loopStart":this.addSignal(void 0,void 0,e.loopText,e.signalType);break;case"loopEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"rectStart":this.addSignal(void 0,void 0,e.color,e.signalType);break;case"rectEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"optStart":this.addSignal(void 0,void 0,e.optText,e.signalType);break;case"optEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"altStart":this.addSignal(void 0,void 0,e.altText,e.signalType);break;case"else":this.addSignal(void 0,void 0,e.altText,e.signalType);break;case"altEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"setAccTitle":Lr(e.text);break;case"parStart":this.addSignal(void 0,void 0,e.parText,e.signalType);break;case"and":this.addSignal(void 0,void 0,e.parText,e.signalType);break;case"parEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"criticalStart":this.addSignal(void 0,void 0,e.criticalText,e.signalType);break;case"option":this.addSignal(void 0,void 0,e.optionText,e.signalType);break;case"criticalEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"breakStart":this.addSignal(void 0,void 0,e.breakText,e.signalType);break;case"breakEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break}}getConfig(){return me().sequence}}});var oVe,hfe,ffe=N(()=>{"use strict";oVe=o(t=>`.actor { + stroke: ${t.actorBorder}; + fill: ${t.actorBkg}; + } + + text.actor > tspan { + fill: ${t.actorTextColor}; + stroke: none; + } + + .actor-line { + stroke: ${t.actorLineColor}; + } + + .messageLine0 { + stroke-width: 1.5; + stroke-dasharray: none; + stroke: ${t.signalColor}; + } + + .messageLine1 { + stroke-width: 1.5; + stroke-dasharray: 2, 2; + stroke: ${t.signalColor}; + } + + #arrowhead path { + fill: ${t.signalColor}; + stroke: ${t.signalColor}; + } + + .sequenceNumber { + fill: ${t.sequenceNumberColor}; + } + + #sequencenumber { + fill: ${t.signalColor}; + } + + #crosshead path { + fill: ${t.signalColor}; + stroke: ${t.signalColor}; + } + + .messageText { + fill: ${t.signalTextColor}; + stroke: none; + } + + .labelBox { + stroke: ${t.labelBoxBorderColor}; + fill: ${t.labelBoxBkgColor}; + } + + .labelText, .labelText > tspan { + fill: ${t.labelTextColor}; + stroke: none; + } + + .loopText, .loopText > tspan { + fill: ${t.loopTextColor}; + stroke: none; + } + + .loopLine { + stroke-width: 2px; + stroke-dasharray: 2, 2; + stroke: ${t.labelBoxBorderColor}; + fill: ${t.labelBoxBorderColor}; + } + + .note { + //stroke: #decc93; + stroke: ${t.noteBorderColor}; + fill: ${t.noteBkgColor}; + } + + .noteText, .noteText > tspan { + fill: ${t.noteTextColor}; + stroke: none; + } + + .activation0 { + fill: ${t.activationBkgColor}; + stroke: ${t.activationBorderColor}; + } + + .activation1 { + fill: ${t.activationBkgColor}; + stroke: ${t.activationBorderColor}; + } + + .activation2 { + fill: ${t.activationBkgColor}; + stroke: ${t.activationBorderColor}; + } + + .actorPopupMenu { + position: absolute; + } + + .actorPopupMenuPanel { + position: absolute; + fill: ${t.actorBkg}; + box-shadow: 0px 8px 16px 0px rgba(0,0,0,0.2); + filter: drop-shadow(3px 5px 2px rgb(0 0 0 / 0.4)); +} + .actor-man line { + stroke: ${t.actorBorder}; + fill: ${t.actorBkg}; + } + .actor-man circle, line { + stroke: ${t.actorBorder}; + fill: ${t.actorBkg}; + stroke-width: 2px; + } +`,"getStyles"),hfe=oVe});var AO,vf,pfe,mfe,lVe,dfe,_O,cVe,uVe,Tb,_p,gfe,Uc,DO,hVe,fVe,dVe,pVe,mVe,gVe,yVe,yfe,vVe,xVe,bVe,wVe,TVe,kVe,EVe,vfe,SVe,LO,CVe,hi,xfe=N(()=>{"use strict";gr();Wv();ir();AO=Sa(z0(),1);ji();vf=18*2,pfe="actor-top",mfe="actor-bottom",lVe="actor-box",dfe="actor-man",_O=o(function(t,e){return kd(t,e)},"drawRect"),cVe=o(function(t,e,r,n,i){if(e.links===void 0||e.links===null||Object.keys(e.links).length===0)return{height:0,width:0};let a=e.links,s=e.actorCnt,l=e.rectData;var u="none";i&&(u="block !important");let h=t.append("g");h.attr("id","actor"+s+"_popup"),h.attr("class","actorPopupMenu"),h.attr("display",u);var f="";l.class!==void 0&&(f=" "+l.class);let d=l.width>r?l.width:r,p=h.append("rect");if(p.attr("class","actorPopupMenuPanel"+f),p.attr("x",l.x),p.attr("y",l.height),p.attr("fill",l.fill),p.attr("stroke",l.stroke),p.attr("width",d),p.attr("height",l.height),p.attr("rx",l.rx),p.attr("ry",l.ry),a!=null){var m=20;for(let v in a){var g=h.append("a"),y=(0,AO.sanitizeUrl)(a[v]);g.attr("xlink:href",y),g.attr("target","_blank"),CVe(n)(v,g,l.x+10,l.height+m,d,20,{class:"actor"},n),m+=30}}return p.attr("height",m),{height:l.height+m,width:d}},"drawPopup"),uVe=o(function(t){return"var pu = document.getElementById('"+t+"'); if (pu != null) { pu.style.display = pu.style.display == 'block' ? 'none' : 'block'; }"},"popupMenuToggle"),Tb=o(async function(t,e,r=null){let n=t.append("foreignObject"),i=await mh(e.text,cr()),s=n.append("xhtml:div").attr("style","width: fit-content;").attr("xmlns","http://www.w3.org/1999/xhtml").html(i).node().getBoundingClientRect();if(n.attr("height",Math.round(s.height)).attr("width",Math.round(s.width)),e.class==="noteText"){let l=t.node().firstChild;l.setAttribute("height",s.height+2*e.textMargin);let u=l.getBBox();n.attr("x",Math.round(u.x+u.width/2-s.width/2)).attr("y",Math.round(u.y+u.height/2-s.height/2))}else if(r){let{startx:l,stopx:u,starty:h}=r;if(l>u){let f=l;l=u,u=f}n.attr("x",Math.round(l+Math.abs(l-u)/2-s.width/2)),e.class==="loopText"?n.attr("y",Math.round(h)):n.attr("y",Math.round(h-s.height))}return[n]},"drawKatex"),_p=o(function(t,e){let r=0,n=0,i=e.text.split(Ze.lineBreakRegex),[a,s]=Bo(e.fontSize),l=[],u=0,h=o(()=>e.y,"yfunc");if(e.valign!==void 0&&e.textMargin!==void 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n=t.append("g"),i=hi.drawRect(n,r),a=Hv();a.x=e.startx,a.y=e.starty,a.width=r.width,a.dy="1em",a.text=e.message,a.class="noteText",a.fontFamily=Ne.noteFontFamily,a.fontSize=Ne.noteFontSize,a.fontWeight=Ne.noteFontWeight,a.anchor=Ne.noteAlign,a.textMargin=Ne.noteMargin,a.valign="center";let s=pi(a.text)?await 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function(t,e,r,n){let{startx:i,stopx:a,starty:s,message:l,type:u,sequenceIndex:h,sequenceVisible:f}=e,d=Gt.calculateTextDimensions(l,Dp(Ne)),p=Hv();p.x=i,p.y=s+10,p.width=a-i,p.class="messageText",p.dy="1em",p.text=l,p.fontFamily=Ne.messageFontFamily,p.fontSize=Ne.messageFontSize,p.fontWeight=Ne.messageFontWeight,p.anchor=Ne.messageAlign,p.valign="center",p.textMargin=Ne.wrapPadding,p.tspan=!1,pi(p.text)?await Tb(t,p,{startx:i,stopx:a,starty:r}):_p(t,p);let m=d.width,g;i===a?Ne.rightAngles?g=t.append("path").attr("d",`M ${i},${r} H ${i+Ze.getMax(Ne.width/2,m/2)} V ${r+25} H ${i}`):g=t.append("path").attr("d","M "+i+","+r+" C "+(i+60)+","+(r-10)+" "+(i+60)+","+(r+30)+" "+i+","+(r+20)):(g=t.append("line"),g.attr("x1",i),g.attr("y1",r),g.attr("x2",a),g.attr("y2",r)),u===n.db.LINETYPE.DOTTED||u===n.db.LINETYPE.DOTTED_CROSS||u===n.db.LINETYPE.DOTTED_POINT||u===n.db.LINETYPE.DOTTED_OPEN||u===n.db.LINETYPE.BIDIRECTIONAL_DOTTED?(g.style("stroke-dasharray","3, 3"),g.attr("class","messageLine1")):g.attr("class","messageLine0");let y="";Ne.arrowMarkerAbsolute&&(y=window.location.protocol+"//"+window.location.host+window.location.pathname+window.location.search,y=y.replace(/\(/g,"\\("),y=y.replace(/\)/g,"\\)")),g.attr("stroke-width",2),g.attr("stroke","none"),g.style("fill","none"),(u===n.db.LINETYPE.SOLID||u===n.db.LINETYPE.DOTTED)&&g.attr("marker-end","url("+y+"#arrowhead)"),(u===n.db.LINETYPE.BIDIRECTIONAL_SOLID||u===n.db.LINETYPE.BIDIRECTIONAL_DOTTED)&&(g.attr("marker-start","url("+y+"#arrowhead)"),g.attr("marker-end","url("+y+"#arrowhead)")),(u===n.db.LINETYPE.SOLID_POINT||u===n.db.LINETYPE.DOTTED_POINT)&&g.attr("marker-end","url("+y+"#filled-head)"),(u===n.db.LINETYPE.SOLID_CROSS||u===n.db.LINETYPE.DOTTED_CROSS)&&g.attr("marker-end","url("+y+"#crosshead)"),(f||Ne.showSequenceNumbers)&&(g.attr("marker-start","url("+y+"#sequencenumber)"),t.append("text").attr("x",i).attr("y",r+4).attr("font-family","sans-serif").attr("font-size","12px").attr("text-anchor","middle").attr("class","sequenceNumber").text(h))},"drawMessage"),LVe=o(function(t,e,r,n,i,a,s){let l=0,u=0,h,f=0;for(let d of n){let p=e.get(d),m=p.box;h&&h!=m&&(s||rt.models.addBox(h),u+=Ne.boxMargin+h.margin),m&&m!=h&&(s||(m.x=l+u,m.y=i),u+=m.margin),p.width=p.width||Ne.width,p.height=Ze.getMax(p.height||Ne.height,Ne.height),p.margin=p.margin||Ne.actorMargin,f=Ze.getMax(f,p.height),r.get(p.name)&&(u+=p.width/2),p.x=l+u,p.starty=rt.getVerticalPos(),rt.insert(p.x,i,p.x+p.width,p.height),l+=p.width+u,p.box&&(p.box.width=l+m.margin-p.box.x),u=p.margin,h=p.box,rt.models.addActor(p)}h&&!s&&rt.models.addBox(h),rt.bumpVerticalPos(f)},"addActorRenderingData"),NO=o(async function(t,e,r,n){if(n){let i=0;rt.bumpVerticalPos(Ne.boxMargin*2);for(let a of r){let s=e.get(a);s.stopy||(s.stopy=rt.getVerticalPos());let l=await hi.drawActor(t,s,Ne,!0);i=Ze.getMax(i,l)}rt.bumpVerticalPos(i+Ne.boxMargin)}else for(let i of r){let a=e.get(i);await hi.drawActor(t,a,Ne,!1)}},"drawActors"),wfe=o(function(t,e,r,n){let i=0,a=0;for(let s of r){let l=e.get(s),u=IVe(l),h=hi.drawPopup(t,l,u,Ne,Ne.forceMenus,n);h.height>i&&(i=h.height),h.width+l.x>a&&(a=h.width+l.x)}return{maxHeight:i,maxWidth:a}},"drawActorsPopup"),Tfe=o(function(t){Gn(Ne,t),t.fontFamily&&(Ne.actorFontFamily=Ne.noteFontFamily=Ne.messageFontFamily=t.fontFamily),t.fontSize&&(Ne.actorFontSize=Ne.noteFontSize=Ne.messageFontSize=t.fontSize),t.fontWeight&&(Ne.actorFontWeight=Ne.noteFontWeight=Ne.messageFontWeight=t.fontWeight)},"setConf"),D6=o(function(t){return rt.activations.filter(function(e){return e.actor===t})},"actorActivations"),bfe=o(function(t,e){let r=e.get(t),n=D6(t),i=n.reduce(function(s,l){return Ze.getMin(s,l.startx)},r.x+r.width/2-1),a=n.reduce(function(s,l){return Ze.getMax(s,l.stopx)},r.x+r.width/2+1);return[i,a]},"activationBounds");o(Hc,"adjustLoopHeightForWrap");o(RVe,"adjustCreatedDestroyedData");NVe=o(async function(t,e,r,n){let{securityLevel:i,sequence:a}=me();Ne=a;let s;i==="sandbox"&&(s=Ge("#i"+e));let l=i==="sandbox"?Ge(s.nodes()[0].contentDocument.body):Ge("body"),u=i==="sandbox"?s.nodes()[0].contentDocument:document;rt.init(),Y.debug(n.db);let h=i==="sandbox"?l.select(`[id="${e}"]`):Ge(`[id="${e}"]`),f=n.db.getActors(),d=n.db.getCreatedActors(),p=n.db.getDestroyedActors(),m=n.db.getBoxes(),g=n.db.getActorKeys(),y=n.db.getMessages(),v=n.db.getDiagramTitle(),x=n.db.hasAtLeastOneBox(),b=n.db.hasAtLeastOneBoxWithTitle(),w=await MVe(f,y,n);if(Ne.height=await OVe(f,w,m),hi.insertComputerIcon(h),hi.insertDatabaseIcon(h),hi.insertClockIcon(h),x&&(rt.bumpVerticalPos(Ne.boxMargin),b&&rt.bumpVerticalPos(m[0].textMaxHeight)),Ne.hideUnusedParticipants===!0){let F=new Set;y.forEach(P=>{F.add(P.from),F.add(P.to)}),g=g.filter(P=>F.has(P))}LVe(h,f,d,g,0,y,!1);let C=await FVe(y,f,w,n);hi.insertArrowHead(h),hi.insertArrowCrossHead(h),hi.insertArrowFilledHead(h),hi.insertSequenceNumber(h);function T(F,P){let z=rt.endActivation(F);z.starty+18>P&&(z.starty=P-6,P+=12),hi.drawActivation(h,z,P,Ne,D6(F.from).length),rt.insert(z.startx,P-10,z.stopx,P)}o(T,"activeEnd");let E=1,A=1,S=[],_=[],I=0;for(let F of y){let P,z,$;switch(F.type){case n.db.LINETYPE.NOTE:rt.resetVerticalPos(),z=F.noteModel,await AVe(h,z);break;case n.db.LINETYPE.ACTIVE_START:rt.newActivation(F,h,f);break;case n.db.LINETYPE.ACTIVE_END:T(F,rt.getVerticalPos());break;case n.db.LINETYPE.LOOP_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.LOOP_END:P=rt.endLoop(),await hi.drawLoop(h,P,"loop",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.RECT_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin,H=>rt.newLoop(void 0,H.message));break;case n.db.LINETYPE.RECT_END:P=rt.endLoop(),_.push(P),rt.models.addLoop(P),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos());break;case n.db.LINETYPE.OPT_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.OPT_END:P=rt.endLoop(),await hi.drawLoop(h,P,"opt",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.ALT_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.ALT_ELSE:Hc(C,F,Ne.boxMargin+Ne.boxTextMargin,Ne.boxMargin,H=>rt.addSectionToLoop(H));break;case n.db.LINETYPE.ALT_END:P=rt.endLoop(),await hi.drawLoop(h,P,"alt",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.PAR_START:case n.db.LINETYPE.PAR_OVER_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H)),rt.saveVerticalPos();break;case n.db.LINETYPE.PAR_AND:Hc(C,F,Ne.boxMargin+Ne.boxTextMargin,Ne.boxMargin,H=>rt.addSectionToLoop(H));break;case n.db.LINETYPE.PAR_END:P=rt.endLoop(),await hi.drawLoop(h,P,"par",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.AUTONUMBER:E=F.message.start||E,A=F.message.step||A,F.message.visible?n.db.enableSequenceNumbers():n.db.disableSequenceNumbers();break;case n.db.LINETYPE.CRITICAL_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.CRITICAL_OPTION:Hc(C,F,Ne.boxMargin+Ne.boxTextMargin,Ne.boxMargin,H=>rt.addSectionToLoop(H));break;case n.db.LINETYPE.CRITICAL_END:P=rt.endLoop(),await hi.drawLoop(h,P,"critical",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.BREAK_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.BREAK_END:P=rt.endLoop(),await hi.drawLoop(h,P,"break",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;default:try{$=F.msgModel,$.starty=rt.getVerticalPos(),$.sequenceIndex=E,$.sequenceVisible=n.db.showSequenceNumbers();let H=await _Ve(h,$);RVe(F,$,H,I,f,d,p),S.push({messageModel:$,lineStartY:H}),rt.models.addMessage($)}catch(H){Y.error("error while drawing message",H)}}[n.db.LINETYPE.SOLID_OPEN,n.db.LINETYPE.DOTTED_OPEN,n.db.LINETYPE.SOLID,n.db.LINETYPE.DOTTED,n.db.LINETYPE.SOLID_CROSS,n.db.LINETYPE.DOTTED_CROSS,n.db.LINETYPE.SOLID_POINT,n.db.LINETYPE.DOTTED_POINT,n.db.LINETYPE.BIDIRECTIONAL_SOLID,n.db.LINETYPE.BIDIRECTIONAL_DOTTED].includes(F.type)&&(E=E+A),I++}Y.debug("createdActors",d),Y.debug("destroyedActors",p),await NO(h,f,g,!1);for(let F of S)await DVe(h,F.messageModel,F.lineStartY,n);Ne.mirrorActors&&await NO(h,f,g,!0),_.forEach(F=>hi.drawBackgroundRect(h,F)),DO(h,f,g,Ne);for(let F of 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g=Gt.calculateTextDimensions(t.message,Dp(Ne));return{width:Ze.getMax(t.wrap?0:g.width+2*Ne.wrapPadding,m+2*Ne.wrapPadding,Ne.width),height:0,startx:u,stopx:h,starty:0,stopy:0,message:t.message,type:t.type,wrap:t.wrap,fromBounds:Math.min.apply(null,p),toBounds:Math.max.apply(null,p)}},"buildMessageModel"),FVe=o(async function(t,e,r,n){let i={},a=[],s,l,u;for(let h of t){switch(h.type){case n.db.LINETYPE.LOOP_START:case n.db.LINETYPE.ALT_START:case n.db.LINETYPE.OPT_START:case n.db.LINETYPE.PAR_START:case n.db.LINETYPE.PAR_OVER_START:case n.db.LINETYPE.CRITICAL_START:case n.db.LINETYPE.BREAK_START:a.push({id:h.id,msg:h.message,from:Number.MAX_SAFE_INTEGER,to:Number.MIN_SAFE_INTEGER,width:0});break;case n.db.LINETYPE.ALT_ELSE:case n.db.LINETYPE.PAR_AND:case n.db.LINETYPE.CRITICAL_OPTION:h.message&&(s=a.pop(),i[s.id]=s,i[h.id]=s,a.push(s));break;case n.db.LINETYPE.LOOP_END:case n.db.LINETYPE.ALT_END:case n.db.LINETYPE.OPT_END:case n.db.LINETYPE.PAR_END:case n.db.LINETYPE.CRITICAL_END:case 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0?s:l.styleEnabled,zoom:Ct(l.zoom)?l.zoom:1,pan:{x:Ur(l.pan)&&Ct(l.pan.x)?l.pan.x:0,y:Ur(l.pan)&&Ct(l.pan.y)?l.pan.y:0},animation:{current:[],queue:[]},hasCompoundNodes:!1,multiClickDebounceTime:u(250,l.multiClickDebounceTime)};this.createEmitter(),this.selectionType(l.selectionType),this.zoomRange({min:l.minZoom,max:l.maxZoom});var f=o(function(g,y){var v=g.some(nWe);if(v)return ey.all(g).then(y);y(g)},"loadExtData");h.styleEnabled&&r.setStyle([]);var d=rr({},l,l.renderer);r.initRenderer(d);var p=o(function(g,y,v){r.notifications(!1);var x=r.mutableElements();x.length>0&&x.remove(),g!=null&&(Ur(g)||En(g))&&r.add(g),r.one("layoutready",function(w){r.notifications(!0),r.emit(w),r.one("load",y),r.emitAndNotify("load")}).one("layoutstop",function(){r.one("done",v),r.emit("done")});var b=rr({},r._private.options.layout);b.eles=r.elements(),r.layout(b).run()},"setElesAndLayout");f([l.style,l.elements],function(m){var g=m[0],y=m[1];h.styleEnabled&&r.style().append(g),p(y,function(){r.startAnimationLoop(),h.ready=!0,si(l.ready)&&r.on("ready",l.ready);for(var v=0;v0,l=!!t.boundingBox,u=e.extent(),h=Hs(l?t.boundingBox:{x1:u.x1,y1:u.y1,w:u.w,h:u.h}),f;if(go(t.roots))f=t.roots;else if(En(t.roots)){for(var d=[],p=0;p0;){var O=R(),M=I(O,k);if(M)O.outgoers().filter(function(ae){return ae.isNode()&&r.has(ae)}).forEach(L);else if(M===null){un("Detected double maximal shift for node `"+O.id()+"`. Bailing maximal adjustment due to cycle. Use `options.maximal: true` only on DAGs.");break}}}var B=0;if(t.avoidOverlap)for(var F=0;F0&&b[0].length<=3?$e/2:0),Ie=2*Math.PI/b[ze].length*He;return ze===0&&b[0].length===1&&(Re=1),{x:se.x+Re*Math.cos(Ie),y:se.y+Re*Math.sin(Ie)}}else{var be=b[ze].length,W=Math.max(be===1?0:l?(h.w-t.padding*2-ue.w)/((t.grid?Se:be)-1):(h.w-t.padding*2-ue.w)/((t.grid?Se:be)+1),B),de={x:se.x+(He+1-(be+1)/2)*W,y:se.y+(ze+1-(ne+1)/2)*Z};return de}},"getPosition");return r.nodes().layoutPositions(this,t,ce),this};rQe={fit:!0,padding:30,boundingBox:void 0,avoidOverlap:!0,nodeDimensionsIncludeLabels:!1,spacingFactor:void 0,radius:void 0,startAngle:3/2*Math.PI,sweep:void 0,clockwise:!0,sort:void 0,animate:!1,animationDuration:500,animationEasing:void 0,animateFilter:o(function(e,r){return!0},"animateFilter"),ready:void 0,stop:void 0,transform:o(function(e,r){return r},"transform")};o(rge,"CircleLayout");rge.prototype.run=function(){var t=this.options,e=t,r=t.cy,n=e.eles,i=e.counterclockwise!==void 0?!e.counterclockwise:e.clockwise,a=n.nodes().not(":parent");e.sort&&(a=a.sort(e.sort));for(var s=Hs(e.boundingBox?e.boundingBox:{x1:0,y1:0,w:r.width(),h:r.height()}),l={x:s.x1+s.w/2,y:s.y1+s.h/2},u=e.sweep===void 0?2*Math.PI-2*Math.PI/a.length:e.sweep,h=u/Math.max(1,a.length-1),f,d=0,p=0;p1&&e.avoidOverlap){d*=1.75;var x=Math.cos(h)-Math.cos(0),b=Math.sin(h)-Math.sin(0),w=Math.sqrt(d*d/(x*x+b*b));f=Math.max(w,f)}var C=o(function(E,A){var S=e.startAngle+A*h*(i?1:-1),_=f*Math.cos(S),I=f*Math.sin(S),D={x:l.x+_,y:l.y+I};return D},"getPos");return n.nodes().layoutPositions(this,e,C),this};nQe={fit:!0,padding:30,startAngle:3/2*Math.PI,sweep:void 0,clockwise:!0,equidistant:!1,minNodeSpacing:10,boundingBox:void 0,avoidOverlap:!0,nodeDimensionsIncludeLabels:!1,height:void 0,width:void 0,spacingFactor:void 0,concentric:o(function(e){return e.degree()},"concentric"),levelWidth:o(function(e){return e.maxDegree()/4},"levelWidth"),animate:!1,animationDuration:500,animationEasing:void 0,animateFilter:o(function(e,r){return!0},"animateFilter"),ready:void 0,stop:void 0,transform:o(function(e,r){return r},"transform")};o(nge,"ConcentricLayout");nge.prototype.run=function(){for(var t=this.options,e=t,r=e.counterclockwise!==void 0?!e.counterclockwise:e.clockwise,n=t.cy,i=e.eles,a=i.nodes().not(":parent"),s=Hs(e.boundingBox?e.boundingBox:{x1:0,y1:0,w:n.width(),h:n.height()}),l={x:s.x1+s.w/2,y:s.y1+s.h/2},u=[],h=0,f=0;f0){var T=Math.abs(b[0].value-C.value);T>=v&&(b=[],x.push(b))}b.push(C)}var E=h+e.minNodeSpacing;if(!e.avoidOverlap){var A=x.length>0&&x[0].length>1,S=Math.min(s.w,s.h)/2-E,_=S/(x.length+A?1:0);E=Math.min(E,_)}for(var I=0,D=0;D1&&e.avoidOverlap){var O=Math.cos(R)-Math.cos(0),M=Math.sin(R)-Math.sin(0),B=Math.sqrt(E*E/(O*O+M*M));I=Math.max(B,I)}k.r=I,I+=E}if(e.equidistant){for(var F=0,P=0,z=0;z=t.numIter||(hQe(n,t),n.temperature=n.temperature*t.coolingFactor,n.temperature=t.animationThreshold&&a(),xS(d)}},"frame");f()}else{for(;h;)h=s(u),u++;E0e(n,t),l()}return this};HS.prototype.stop=function(){return this.stopped=!0,this.thread&&this.thread.stop(),this.emit("layoutstop"),this};HS.prototype.destroy=function(){return this.thread&&this.thread.stop(),this};aQe=o(function(e,r,n){for(var i=n.eles.edges(),a=n.eles.nodes(),s=Hs(n.boundingBox?n.boundingBox:{x1:0,y1:0,w:e.width(),h:e.height()}),l={isCompound:e.hasCompoundNodes(),layoutNodes:[],idToIndex:{},nodeSize:a.size(),graphSet:[],indexToGraph:[],layoutEdges:[],edgeSize:i.size(),temperature:n.initialTemp,clientWidth:s.w,clientHeight:s.h,boundingBox:s},u=n.eles.components(),h={},f=0;f0){l.graphSet.push(S);for(var f=0;fi.count?0:i.graph},"findLCA"),oQe=o(function t(e,r,n,i){var a=i.graphSet[n];if(-10)var d=i.nodeOverlap*f,p=Math.sqrt(l*l+u*u),m=d*l/p,g=d*u/p;else var y=CS(e,l,u),v=CS(r,-1*l,-1*u),x=v.x-y.x,b=v.y-y.y,w=x*x+b*b,p=Math.sqrt(w),d=(e.nodeRepulsion+r.nodeRepulsion)/w,m=d*x/p,g=d*b/p;e.isLocked||(e.offsetX-=m,e.offsetY-=g),r.isLocked||(r.offsetX+=m,r.offsetY+=g)}},"nodeRepulsion"),pQe=o(function(e,r,n,i){if(n>0)var a=e.maxX-r.minX;else var a=r.maxX-e.minX;if(i>0)var s=e.maxY-r.minY;else var s=r.maxY-e.minY;return a>=0&&s>=0?Math.sqrt(a*a+s*s):0},"nodesOverlap"),CS=o(function(e,r,n){var i=e.positionX,a=e.positionY,s=e.height||1,l=e.width||1,u=n/r,h=s/l,f={};return r===0&&0n?(f.x=i,f.y=a+s/2,f):0r&&-1*h<=u&&u<=h?(f.x=i-l/2,f.y=a-l*n/2/r,f):0=h)?(f.x=i+s*r/2/n,f.y=a+s/2,f):(0>n&&(u<=-1*h||u>=h)&&(f.x=i-s*r/2/n,f.y=a-s/2),f)},"findClippingPoint"),mQe=o(function(e,r){for(var n=0;nn){var v=r.gravity*m/y,x=r.gravity*g/y;p.offsetX+=v,p.offsetY+=x}}}}},"calculateGravityForces"),yQe=o(function(e,r){var n=[],i=0,a=-1;for(n.push.apply(n,e.graphSet[0]),a+=e.graphSet[0].length;i<=a;){var s=n[i++],l=e.idToIndex[s],u=e.layoutNodes[l],h=u.children;if(0n)var a={x:n*e/i,y:n*r/i};else var a={x:e,y:r};return a},"limitForce"),bQe=o(function t(e,r){var n=e.parentId;if(n!=null){var i=r.layoutNodes[r.idToIndex[n]],a=!1;if((i.maxX==null||e.maxX+i.padRight>i.maxX)&&(i.maxX=e.maxX+i.padRight,a=!0),(i.minX==null||e.minX-i.padLefti.maxY)&&(i.maxY=e.maxY+i.padBottom,a=!0),(i.minY==null||e.minY-i.padTopx&&(g+=v+r.componentSpacing,m=0,y=0,v=0)}}},"separateComponents"),wQe={fit:!0,padding:30,boundingBox:void 0,avoidOverlap:!0,avoidOverlapPadding:10,nodeDimensionsIncludeLabels:!1,spacingFactor:void 0,condense:!1,rows:void 0,cols:void 0,position:o(function(e){},"position"),sort:void 0,animate:!1,animationDuration:500,animationEasing:void 0,animateFilter:o(function(e,r){return!0},"animateFilter"),ready:void 0,stop:void 0,transform:o(function(e,r){return r},"transform")};o(age,"GridLayout");age.prototype.run=function(){var t=this.options,e=t,r=t.cy,n=e.eles,i=n.nodes().not(":parent");e.sort&&(i=i.sort(e.sort));var a=Hs(e.boundingBox?e.boundingBox:{x1:0,y1:0,w:r.width(),h:r.height()});if(a.h===0||a.w===0)n.nodes().layoutPositions(this,e,function(Q){return{x:a.x1,y:a.y1}});else{var s=i.size(),l=Math.sqrt(s*a.h/a.w),u=Math.round(l),h=Math.round(a.w/a.h*l),f=o(function(j){if(j==null)return Math.min(u,h);var ie=Math.min(u,h);ie==u?u=j:h=j},"small"),d=o(function(j){if(j==null)return Math.max(u,h);var ie=Math.max(u,h);ie==u?u=j:h=j},"large"),p=e.rows,m=e.cols!=null?e.cols:e.columns;if(p!=null&&m!=null)u=p,h=m;else if(p!=null&&m==null)u=p,h=Math.ceil(s/u);else if(p==null&&m!=null)h=m,u=Math.ceil(s/h);else if(h*u>s){var g=f(),y=d();(g-1)*y>=s?f(g-1):(y-1)*g>=s&&d(y-1)}else for(;h*u=s?d(x+1):f(v+1)}var b=a.w/h,w=a.h/u;if(e.condense&&(b=0,w=0),e.avoidOverlap)for(var C=0;C=h&&(O=0,R++)},"moveToNextCell"),B={},F=0;F(O=Wqe(t,e,M[B],M[B+1],M[B+2],M[B+3])))return v(A,O),!0}else if(_.edgeType==="bezier"||_.edgeType==="multibezier"||_.edgeType==="self"||_.edgeType==="compound"){for(var M=_.allpts,B=0;B+5<_.allpts.length;B+=4)if(Gqe(t,e,M[B],M[B+1],M[B+2],M[B+3],M[B+4],M[B+5],R)&&L>(O=Hqe(t,e,M[B],M[B+1],M[B+2],M[B+3],M[B+4],M[B+5])))return v(A,O),!0}for(var F=F||S.source,P=P||S.target,z=i.getArrowWidth(I,D),$=[{name:"source",x:_.arrowStartX,y:_.arrowStartY,angle:_.srcArrowAngle},{name:"target",x:_.arrowEndX,y:_.arrowEndY,angle:_.tgtArrowAngle},{name:"mid-source",x:_.midX,y:_.midY,angle:_.midsrcArrowAngle},{name:"mid-target",x:_.midX,y:_.midY,angle:_.midtgtArrowAngle}],B=0;B<$.length;B++){var H=$[B],Q=a.arrowShapes[A.pstyle(H.name+"-arrow-shape").value],j=A.pstyle("width").pfValue;if(Q.roughCollide(t,e,z,H.angle,{x:H.x,y:H.y},j,f)&&Q.collide(t,e,z,H.angle,{x:H.x,y:H.y},j,f))return v(A),!0}h&&l.length>0&&(x(F),x(P))}o(b,"checkEdge");function w(A,S,_){return Gl(A,S,_)}o(w,"preprop");function C(A,S){var _=A._private,I=p,D;S?D=S+"-":D="",A.boundingBox();var k=_.labelBounds[S||"main"],L=A.pstyle(D+"label").value,R=A.pstyle("text-events").strValue==="yes";if(!(!R||!L)){var O=w(_.rscratch,"labelX",S),M=w(_.rscratch,"labelY",S),B=w(_.rscratch,"labelAngle",S),F=A.pstyle(D+"text-margin-x").pfValue,P=A.pstyle(D+"text-margin-y").pfValue,z=k.x1-I-F,$=k.x2+I-F,H=k.y1-I-P,Q=k.y2+I-P;if(B){var j=Math.cos(B),ie=Math.sin(B),ne=o(function(se,ue){return se=se-O,ue=ue-M,{x:se*j-ue*ie+O,y:se*ie+ue*j+M}},"rotate"),le=ne(z,H),he=ne(z,Q),K=ne($,H),X=ne($,Q),te=[le.x+F,le.y+P,K.x+F,K.y+P,X.x+F,X.y+P,he.x+F,he.y+P];if(Us(t,e,te))return v(A),!0}else if(K1(k,t,e))return v(A),!0}}o(C,"checkLabel");for(var T=s.length-1;T>=0;T--){var E=s[T];E.isNode()?x(E)||C(E):b(E)||C(E)||C(E,"source")||C(E,"target")}return l};qp.getAllInBox=function(t,e,r,n){var i=this.getCachedZSortedEles().interactive,a=[],s=Math.min(t,r),l=Math.max(t,r),u=Math.min(e,n),h=Math.max(e,n);t=s,r=l,e=u,n=h;for(var f=Hs({x1:t,y1:e,x2:r,y2:n}),d=0;d0?-(Math.PI-e.ang):Math.PI+e.ang},"invertVec"),AQe=o(function(e,r,n,i,a){if(e!==D0e?L0e(r,e,qc):CQe(Jo,qc),L0e(r,n,Jo),A0e=qc.nx*Jo.ny-qc.ny*Jo.nx,_0e=qc.nx*Jo.nx-qc.ny*-Jo.ny,Ku=Math.asin(Math.max(-1,Math.min(1,A0e))),Math.abs(Ku)<1e-6){HP=r.x,WP=r.y,Bp=G1=0;return}Fp=1,gS=!1,_0e<0?Ku<0?Ku=Math.PI+Ku:(Ku=Math.PI-Ku,Fp=-1,gS=!0):Ku>0&&(Fp=-1,gS=!0),r.radius!==void 0?G1=r.radius:G1=i,Mp=Ku/2,aS=Math.min(qc.len/2,Jo.len/2),a?(Wc=Math.abs(Math.cos(Mp)*G1/Math.sin(Mp)),Wc>aS?(Wc=aS,Bp=Math.abs(Wc*Math.sin(Mp)/Math.cos(Mp))):Bp=G1):(Wc=Math.min(aS,G1),Bp=Math.abs(Wc*Math.sin(Mp)/Math.cos(Mp))),qP=r.x+Jo.nx*Wc,YP=r.y+Jo.ny*Wc,HP=qP-Jo.ny*Bp*Fp,WP=YP+Jo.nx*Bp*Fp,cge=r.x+qc.nx*Wc,uge=r.y+qc.ny*Wc,D0e=r},"calcCornerArc");o(hge,"drawPreparedRoundCorner");o(vB,"getRoundCorner");Va={};Va.findMidptPtsEtc=function(t,e){var r=e.posPts,n=e.intersectionPts,i=e.vectorNormInverse,a,s=t.pstyle("source-endpoint"),l=t.pstyle("target-endpoint"),u=s.units!=null&&l.units!=null,h=o(function(T,E,A,S){var _=S-E,I=A-T,D=Math.sqrt(I*I+_*_);return{x:-_/D,y:I/D}},"recalcVectorNormInverse"),f=t.pstyle("edge-distances").value;switch(f){case"node-position":a=r;break;case"intersection":a=n;break;case"endpoints":{if(u){var d=this.manualEndptToPx(t.source()[0],s),p=_i(d,2),m=p[0],g=p[1],y=this.manualEndptToPx(t.target()[0],l),v=_i(y,2),x=v[0],b=v[1],w={x1:m,y1:g,x2:x,y2:b};i=h(m,g,x,b),a=w}else un("Edge ".concat(t.id()," has edge-distances:endpoints specified without manual endpoints specified via source-endpoint and target-endpoint. Falling back on edge-distances:intersection (default).")),a=n;break}}return{midptPts:a,vectorNormInverse:i}};Va.findHaystackPoints=function(t){for(var e=0;e0?Math.max(q-pe,0):Math.min(q+pe,0)},"subDWH"),L=k(I,S),R=k(D,_),O=!1;b===h?x=Math.abs(L)>Math.abs(R)?i:n:b===u||b===l?(x=n,O=!0):(b===a||b===s)&&(x=i,O=!0);var M=x===n,B=M?R:L,F=M?D:I,P=mme(F),z=!1;!(O&&(C||E))&&(b===l&&F<0||b===u&&F>0||b===a&&F>0||b===s&&F<0)&&(P*=-1,B=P*Math.abs(B),z=!0);var $;if(C){var H=T<0?1+T:T;$=H*B}else{var Q=T<0?B:0;$=Q+T*P}var j=o(function(q){return Math.abs(q)=Math.abs(B)},"getIsTooClose"),ie=j($),ne=j(Math.abs(B)-Math.abs($)),le=ie||ne;if(le&&!z)if(M){var he=Math.abs(F)<=p/2,K=Math.abs(I)<=m/2;if(he){var X=(f.x1+f.x2)/2,te=f.y1,J=f.y2;r.segpts=[X,te,X,J]}else if(K){var se=(f.y1+f.y2)/2,ue=f.x1,Z=f.x2;r.segpts=[ue,se,Z,se]}else r.segpts=[f.x1,f.y2]}else{var Se=Math.abs(F)<=d/2,ce=Math.abs(D)<=g/2;if(Se){var ae=(f.y1+f.y2)/2,Oe=f.x1,ge=f.x2;r.segpts=[Oe,ae,ge,ae]}else if(ce){var ze=(f.x1+f.x2)/2,He=f.y1,$e=f.y2;r.segpts=[ze,He,ze,$e]}else r.segpts=[f.x2,f.y1]}else if(M){var Re=f.y1+$+(v?p/2*P:0),Ie=f.x1,be=f.x2;r.segpts=[Ie,Re,be,Re]}else{var W=f.x1+$+(v?d/2*P:0),de=f.y1,re=f.y2;r.segpts=[W,de,W,re]}if(r.isRound){var oe=t.pstyle("taxi-radius").value,V=t.pstyle("radius-type").value[0]==="arc-radius";r.radii=new Array(r.segpts.length/2).fill(oe),r.isArcRadius=new Array(r.segpts.length/2).fill(V)}};Va.tryToCorrectInvalidPoints=function(t,e){var r=t._private.rscratch;if(r.edgeType==="bezier"){var n=e.srcPos,i=e.tgtPos,a=e.srcW,s=e.srcH,l=e.tgtW,u=e.tgtH,h=e.srcShape,f=e.tgtShape,d=e.srcCornerRadius,p=e.tgtCornerRadius,m=e.srcRs,g=e.tgtRs,y=!Ct(r.startX)||!Ct(r.startY),v=!Ct(r.arrowStartX)||!Ct(r.arrowStartY),x=!Ct(r.endX)||!Ct(r.endY),b=!Ct(r.arrowEndX)||!Ct(r.arrowEndY),w=3,C=this.getArrowWidth(t.pstyle("width").pfValue,t.pstyle("arrow-scale").value)*this.arrowShapeWidth,T=w*C,E=Gp({x:r.ctrlpts[0],y:r.ctrlpts[1]},{x:r.startX,y:r.startY}),A=ER.poolIndex()){var O=L;L=R,R=O}var M=_.srcPos=L.position(),B=_.tgtPos=R.position(),F=_.srcW=L.outerWidth(),P=_.srcH=L.outerHeight(),z=_.tgtW=R.outerWidth(),$=_.tgtH=R.outerHeight(),H=_.srcShape=r.nodeShapes[e.getNodeShape(L)],Q=_.tgtShape=r.nodeShapes[e.getNodeShape(R)],j=_.srcCornerRadius=L.pstyle("corner-radius").value==="auto"?"auto":L.pstyle("corner-radius").pfValue,ie=_.tgtCornerRadius=R.pstyle("corner-radius").value==="auto"?"auto":R.pstyle("corner-radius").pfValue,ne=_.tgtRs=R._private.rscratch,le=_.srcRs=L._private.rscratch;_.dirCounts={north:0,west:0,south:0,east:0,northwest:0,southwest:0,northeast:0,southeast:0};for(var he=0;he<_.eles.length;he++){var K=_.eles[he],X=K[0]._private.rscratch,te=K.pstyle("curve-style").value,J=te==="unbundled-bezier"||te.endsWith("segments")||te.endsWith("taxi"),se=!L.same(K.source());if(!_.calculatedIntersection&&L!==R&&(_.hasBezier||_.hasUnbundled)){_.calculatedIntersection=!0;var ue=H.intersectLine(M.x,M.y,F,P,B.x,B.y,0,j,le),Z=_.srcIntn=ue,Se=Q.intersectLine(B.x,B.y,z,$,M.x,M.y,0,ie,ne),ce=_.tgtIntn=Se,ae=_.intersectionPts={x1:ue[0],x2:Se[0],y1:ue[1],y2:Se[1]},Oe=_.posPts={x1:M.x,x2:B.x,y1:M.y,y2:B.y},ge=Se[1]-ue[1],ze=Se[0]-ue[0],He=Math.sqrt(ze*ze+ge*ge),$e=_.vector={x:ze,y:ge},Re=_.vectorNorm={x:$e.x/He,y:$e.y/He},Ie={x:-Re.y,y:Re.x};_.nodesOverlap=!Ct(He)||Q.checkPoint(ue[0],ue[1],0,z,$,B.x,B.y,ie,ne)||H.checkPoint(Se[0],Se[1],0,F,P,M.x,M.y,j,le),_.vectorNormInverse=Ie,I={nodesOverlap:_.nodesOverlap,dirCounts:_.dirCounts,calculatedIntersection:!0,hasBezier:_.hasBezier,hasUnbundled:_.hasUnbundled,eles:_.eles,srcPos:B,srcRs:ne,tgtPos:M,tgtRs:le,srcW:z,srcH:$,tgtW:F,tgtH:P,srcIntn:ce,tgtIntn:Z,srcShape:Q,tgtShape:H,posPts:{x1:Oe.x2,y1:Oe.y2,x2:Oe.x1,y2:Oe.y1},intersectionPts:{x1:ae.x2,y1:ae.y2,x2:ae.x1,y2:ae.y1},vector:{x:-$e.x,y:-$e.y},vectorNorm:{x:-Re.x,y:-Re.y},vectorNormInverse:{x:-Ie.x,y:-Ie.y}}}var be=se?I:_;X.nodesOverlap=be.nodesOverlap,X.srcIntn=be.srcIntn,X.tgtIntn=be.tgtIntn,X.isRound=te.startsWith("round"),i&&(L.isParent()||L.isChild()||R.isParent()||R.isChild())&&(L.parents().anySame(R)||R.parents().anySame(L)||L.same(R)&&L.isParent())?e.findCompoundLoopPoints(K,be,he,J):L===R?e.findLoopPoints(K,be,he,J):te.endsWith("segments")?e.findSegmentsPoints(K,be):te.endsWith("taxi")?e.findTaxiPoints(K,be):te==="straight"||!J&&_.eles.length%2===1&&he===Math.floor(_.eles.length/2)?e.findStraightEdgePoints(K):e.findBezierPoints(K,be,he,J,se),e.findEndpoints(K),e.tryToCorrectInvalidPoints(K,be),e.checkForInvalidEdgeWarning(K),e.storeAllpts(K),e.storeEdgeProjections(K),e.calculateArrowAngles(K),e.recalculateEdgeLabelProjections(K),e.calculateLabelAngles(K)}},"_loop"),T=0;T0){var J=a,se=Op(J,U1(r)),ue=Op(J,U1(te)),Z=se;if(ue2){var Se=Op(J,{x:te[2],y:te[3]});Se0){var re=s,oe=Op(re,U1(r)),V=Op(re,U1(de)),xe=oe;if(V2){var q=Op(re,{x:de[2],y:de[3]});q=g||A){v={cp:C,segment:E};break}}if(v)break}var S=v.cp,_=v.segment,I=(g-x)/_.length,D=_.t1-_.t0,k=m?_.t0+D*I:_.t1-D*I;k=Yb(0,k,1),e=W1(S.p0,S.p1,S.p2,k),p=DQe(S.p0,S.p1,S.p2,k);break}case"straight":case"segments":case"haystack":{for(var L=0,R,O,M,B,F=n.allpts.length,P=0;P+3=g));P+=2);var z=g-O,$=z/R;$=Yb(0,$,1),e=Iqe(M,B,$),p=pge(M,B);break}}s("labelX",d,e.x),s("labelY",d,e.y),s("labelAutoAngle",d,p)}},"calculateEndProjection");h("source"),h("target"),this.applyLabelDimensions(t)}};Kc.applyLabelDimensions=function(t){this.applyPrefixedLabelDimensions(t),t.isEdge()&&(this.applyPrefixedLabelDimensions(t,"source"),this.applyPrefixedLabelDimensions(t,"target"))};Kc.applyPrefixedLabelDimensions=function(t,e){var r=t._private,n=this.getLabelText(t,e),i=this.calculateLabelDimensions(t,n),a=t.pstyle("line-height").pfValue,s=t.pstyle("text-wrap").strValue,l=Gl(r.rscratch,"labelWrapCachedLines",e)||[],u=s!=="wrap"?1:Math.max(l.length,1),h=i.height/u,f=h*a,d=i.width,p=i.height+(u-1)*(a-1)*h;kf(r.rstyle,"labelWidth",e,d),kf(r.rscratch,"labelWidth",e,d),kf(r.rstyle,"labelHeight",e,p),kf(r.rscratch,"labelHeight",e,p),kf(r.rscratch,"labelLineHeight",e,f)};Kc.getLabelText=function(t,e){var r=t._private,n=e?e+"-":"",i=t.pstyle(n+"label").strValue,a=t.pstyle("text-transform").value,s=o(function(Q,j){return j?(kf(r.rscratch,Q,e,j),j):Gl(r.rscratch,Q,e)},"rscratch");if(!i)return"";a=="none"||(a=="uppercase"?i=i.toUpperCase():a=="lowercase"&&(i=i.toLowerCase()));var l=t.pstyle("text-wrap").value;if(l==="wrap"){var u=s("labelKey");if(u!=null&&s("labelWrapKey")===u)return s("labelWrapCachedText");for(var h="\u200B",f=i.split(` +`),d=t.pstyle("text-max-width").pfValue,p=t.pstyle("text-overflow-wrap").value,m=p==="anywhere",g=[],y=/[\s\u200b]+|$/g,v=0;vd){var T=x.matchAll(y),E="",A=0,S=mo(T),_;try{for(S.s();!(_=S.n()).done;){var I=_.value,D=I[0],k=x.substring(A,I.index);A=I.index+D.length;var L=E.length===0?k:E+k+D,R=this.calculateLabelDimensions(t,L),O=R.width;O<=d?E+=k+D:(E&&g.push(E),E=k+D)}}catch(H){S.e(H)}finally{S.f()}E.match(/^[\s\u200b]+$/)||g.push(E)}else g.push(x)}s("labelWrapCachedLines",g),i=s("labelWrapCachedText",g.join(` +`)),s("labelWrapKey",u)}else if(l==="ellipsis"){var M=t.pstyle("text-max-width").pfValue,B="",F="\u2026",P=!1;if(this.calculateLabelDimensions(t,i).widthM)break;B+=i[z],z===i.length-1&&(P=!0)}return P||(B+=F),B}return i};Kc.getLabelJustification=function(t){var e=t.pstyle("text-justification").strValue,r=t.pstyle("text-halign").strValue;if(e==="auto")if(t.isNode())switch(r){case"left":return"right";case"right":return"left";default:return"center"}else return"center";else return e};Kc.calculateLabelDimensions=function(t,e){var r=this,n=r.cy.window(),i=n.document,a=_f(e,t._private.labelDimsKey),s=r.labelDimCache||(r.labelDimCache=[]),l=s[a];if(l!=null)return l;var u=0,h=t.pstyle("font-style").strValue,f=t.pstyle("font-size").pfValue,d=t.pstyle("font-family").strValue,p=t.pstyle("font-weight").strValue,m=this.labelCalcCanvas,g=this.labelCalcCanvasContext;if(!m){m=this.labelCalcCanvas=i.createElement("canvas"),g=this.labelCalcCanvasContext=m.getContext("2d");var y=m.style;y.position="absolute",y.left="-9999px",y.top="-9999px",y.zIndex="-1",y.visibility="hidden",y.pointerEvents="none"}g.font="".concat(h," ").concat(p," ").concat(f,"px ").concat(d);for(var v=0,x=0,b=e.split(` +`),w=0;w1&&arguments[1]!==void 0?arguments[1]:!0;if(e.merge(s),l)for(var u=0;u=t.desktopTapThreshold2}var ot=a(W);at&&(t.hoverData.tapholdCancelled=!0);var Yt=o(function(){var Tt=t.hoverData.dragDelta=t.hoverData.dragDelta||[];Tt.length===0?(Tt.push(De[0]),Tt.push(De[1])):(Tt[0]+=De[0],Tt[1]+=De[1])},"updateDragDelta");re=!0,i(_e,["mousemove","vmousemove","tapdrag"],W,{x:q[0],y:q[1]});var bt=o(function(){t.data.bgActivePosistion=void 0,t.hoverData.selecting||oe.emit({originalEvent:W,type:"boxstart",position:{x:q[0],y:q[1]}}),Pe[4]=1,t.hoverData.selecting=!0,t.redrawHint("select",!0),t.redraw()},"goIntoBoxMode");if(t.hoverData.which===3){if(at){var Mt={originalEvent:W,type:"cxtdrag",position:{x:q[0],y:q[1]}};Ve?Ve.emit(Mt):oe.emit(Mt),t.hoverData.cxtDragged=!0,(!t.hoverData.cxtOver||_e!==t.hoverData.cxtOver)&&(t.hoverData.cxtOver&&t.hoverData.cxtOver.emit({originalEvent:W,type:"cxtdragout",position:{x:q[0],y:q[1]}}),t.hoverData.cxtOver=_e,_e&&_e.emit({originalEvent:W,type:"cxtdragover",position:{x:q[0],y:q[1]}}))}}else if(t.hoverData.dragging){if(re=!0,oe.panningEnabled()&&oe.userPanningEnabled()){var xt;if(t.hoverData.justStartedPan){var ut=t.hoverData.mdownPos;xt={x:(q[0]-ut[0])*V,y:(q[1]-ut[1])*V},t.hoverData.justStartedPan=!1}else xt={x:De[0]*V,y:De[1]*V};oe.panBy(xt),oe.emit("dragpan"),t.hoverData.dragged=!0}q=t.projectIntoViewport(W.clientX,W.clientY)}else if(Pe[4]==1&&(Ve==null||Ve.pannable())){if(at){if(!t.hoverData.dragging&&oe.boxSelectionEnabled()&&(ot||!oe.panningEnabled()||!oe.userPanningEnabled()))bt();else if(!t.hoverData.selecting&&oe.panningEnabled()&&oe.userPanningEnabled()){var Et=s(Ve,t.hoverData.downs);Et&&(t.hoverData.dragging=!0,t.hoverData.justStartedPan=!0,Pe[4]=0,t.data.bgActivePosistion=U1(pe),t.redrawHint("select",!0),t.redraw())}Ve&&Ve.pannable()&&Ve.active()&&Ve.unactivate()}}else{if(Ve&&Ve.pannable()&&Ve.active()&&Ve.unactivate(),(!Ve||!Ve.grabbed())&&_e!=we&&(we&&i(we,["mouseout","tapdragout"],W,{x:q[0],y:q[1]}),_e&&i(_e,["mouseover","tapdragover"],W,{x:q[0],y:q[1]}),t.hoverData.last=_e),Ve)if(at){if(oe.boxSelectionEnabled()&&ot)Ve&&Ve.grabbed()&&(x(qe),Ve.emit("freeon"),qe.emit("free"),t.dragData.didDrag&&(Ve.emit("dragfreeon"),qe.emit("dragfree"))),bt();else if(Ve&&Ve.grabbed()&&t.nodeIsDraggable(Ve)){var ft=!t.dragData.didDrag;ft&&t.redrawHint("eles",!0),t.dragData.didDrag=!0,t.hoverData.draggingEles||y(qe,{inDragLayer:!0});var yt={x:0,y:0};if(Ct(De[0])&&Ct(De[1])&&(yt.x+=De[0],yt.y+=De[1],ft)){var nt=t.hoverData.dragDelta;nt&&Ct(nt[0])&&Ct(nt[1])&&(yt.x+=nt[0],yt.y+=nt[1])}t.hoverData.draggingEles=!0,qe.silentShift(yt).emit("position drag"),t.redrawHint("drag",!0),t.redraw()}}else Yt();re=!0}if(Pe[2]=q[0],Pe[3]=q[1],re)return W.stopPropagation&&W.stopPropagation(),W.preventDefault&&W.preventDefault(),!1}},"mousemoveHandler"),!1);var k,L,R;t.registerBinding(e,"mouseup",o(function(W){if(!(t.hoverData.which===1&&W.which!==1&&t.hoverData.capture)){var de=t.hoverData.capture;if(de){t.hoverData.capture=!1;var re=t.cy,oe=t.projectIntoViewport(W.clientX,W.clientY),V=t.selection,xe=t.findNearestElement(oe[0],oe[1],!0,!1),q=t.dragData.possibleDragElements,pe=t.hoverData.down,ve=a(W);if(t.data.bgActivePosistion&&(t.redrawHint("select",!0),t.redraw()),t.hoverData.tapholdCancelled=!0,t.data.bgActivePosistion=void 0,pe&&pe.unactivate(),t.hoverData.which===3){var Pe={originalEvent:W,type:"cxttapend",position:{x:oe[0],y:oe[1]}};if(pe?pe.emit(Pe):re.emit(Pe),!t.hoverData.cxtDragged){var _e={originalEvent:W,type:"cxttap",position:{x:oe[0],y:oe[1]}};pe?pe.emit(_e):re.emit(_e)}t.hoverData.cxtDragged=!1,t.hoverData.which=null}else if(t.hoverData.which===1){if(i(xe,["mouseup","tapend","vmouseup"],W,{x:oe[0],y:oe[1]}),!t.dragData.didDrag&&!t.hoverData.dragged&&!t.hoverData.selecting&&!t.hoverData.isOverThresholdDrag&&(i(pe,["click","tap","vclick"],W,{x:oe[0],y:oe[1]}),L=!1,W.timeStamp-R<=re.multiClickDebounceTime()?(k&&clearTimeout(k),L=!0,R=null,i(pe,["dblclick","dbltap","vdblclick"],W,{x:oe[0],y:oe[1]})):(k=setTimeout(function(){L||i(pe,["oneclick","onetap","voneclick"],W,{x:oe[0],y:oe[1]})},re.multiClickDebounceTime()),R=W.timeStamp)),pe==null&&!t.dragData.didDrag&&!t.hoverData.selecting&&!t.hoverData.dragged&&!a(W)&&(re.$(r).unselect(["tapunselect"]),q.length>0&&t.redrawHint("eles",!0),t.dragData.possibleDragElements=q=re.collection()),xe==pe&&!t.dragData.didDrag&&!t.hoverData.selecting&&xe!=null&&xe._private.selectable&&(t.hoverData.dragging||(re.selectionType()==="additive"||ve?xe.selected()?xe.unselect(["tapunselect"]):xe.select(["tapselect"]):ve||(re.$(r).unmerge(xe).unselect(["tapunselect"]),xe.select(["tapselect"]))),t.redrawHint("eles",!0)),t.hoverData.selecting){var we=re.collection(t.getAllInBox(V[0],V[1],V[2],V[3]));t.redrawHint("select",!0),we.length>0&&t.redrawHint("eles",!0),re.emit({type:"boxend",originalEvent:W,position:{x:oe[0],y:oe[1]}});var Ve=o(function(at){return at.selectable()&&!at.selected()},"eleWouldBeSelected");re.selectionType()==="additive"||ve||re.$(r).unmerge(we).unselect(),we.emit("box").stdFilter(Ve).select().emit("boxselect"),t.redraw()}if(t.hoverData.dragging&&(t.hoverData.dragging=!1,t.redrawHint("select",!0),t.redrawHint("eles",!0),t.redraw()),!V[4]){t.redrawHint("drag",!0),t.redrawHint("eles",!0);var De=pe&&pe.grabbed();x(q),De&&(pe.emit("freeon"),q.emit("free"),t.dragData.didDrag&&(pe.emit("dragfreeon"),q.emit("dragfree")))}}V[4]=0,t.hoverData.down=null,t.hoverData.cxtStarted=!1,t.hoverData.draggingEles=!1,t.hoverData.selecting=!1,t.hoverData.isOverThresholdDrag=!1,t.dragData.didDrag=!1,t.hoverData.dragged=!1,t.hoverData.dragDelta=[],t.hoverData.mdownPos=null,t.hoverData.mdownGPos=null,t.hoverData.which=null}}},"mouseupHandler"),!1);var O=o(function(W){if(!t.scrollingPage){var de=t.cy,re=de.zoom(),oe=de.pan(),V=t.projectIntoViewport(W.clientX,W.clientY),xe=[V[0]*re+oe.x,V[1]*re+oe.y];if(t.hoverData.draggingEles||t.hoverData.dragging||t.hoverData.cxtStarted||_()){W.preventDefault();return}if(de.panningEnabled()&&de.userPanningEnabled()&&de.zoomingEnabled()&&de.userZoomingEnabled()){W.preventDefault(),t.data.wheelZooming=!0,clearTimeout(t.data.wheelTimeout),t.data.wheelTimeout=setTimeout(function(){t.data.wheelZooming=!1,t.redrawHint("eles",!0),t.redraw()},150);var q;W.deltaY!=null?q=W.deltaY/-250:W.wheelDeltaY!=null?q=W.wheelDeltaY/1e3:q=W.wheelDelta/1e3,q=q*t.wheelSensitivity;var pe=W.deltaMode===1;pe&&(q*=33);var ve=de.zoom()*Math.pow(10,q);W.type==="gesturechange"&&(ve=t.gestureStartZoom*W.scale),de.zoom({level:ve,renderedPosition:{x:xe[0],y:xe[1]}}),de.emit(W.type==="gesturechange"?"pinchzoom":"scrollzoom")}}},"wheelHandler");t.registerBinding(t.container,"wheel",O,!0),t.registerBinding(e,"scroll",o(function(W){t.scrollingPage=!0,clearTimeout(t.scrollingPageTimeout),t.scrollingPageTimeout=setTimeout(function(){t.scrollingPage=!1},250)},"scrollHandler"),!0),t.registerBinding(t.container,"gesturestart",o(function(W){t.gestureStartZoom=t.cy.zoom(),t.hasTouchStarted||W.preventDefault()},"gestureStartHandler"),!0),t.registerBinding(t.container,"gesturechange",function(be){t.hasTouchStarted||O(be)},!0),t.registerBinding(t.container,"mouseout",o(function(W){var de=t.projectIntoViewport(W.clientX,W.clientY);t.cy.emit({originalEvent:W,type:"mouseout",position:{x:de[0],y:de[1]}})},"mouseOutHandler"),!1),t.registerBinding(t.container,"mouseover",o(function(W){var de=t.projectIntoViewport(W.clientX,W.clientY);t.cy.emit({originalEvent:W,type:"mouseover",position:{x:de[0],y:de[1]}})},"mouseOverHandler"),!1);var M,B,F,P,z,$,H,Q,j,ie,ne,le,he,K=o(function(W,de,re,oe){return Math.sqrt((re-W)*(re-W)+(oe-de)*(oe-de))},"distance"),X=o(function(W,de,re,oe){return(re-W)*(re-W)+(oe-de)*(oe-de)},"distanceSq"),te;t.registerBinding(t.container,"touchstart",te=o(function(W){if(t.hasTouchStarted=!0,!!I(W)){w(),t.touchData.capture=!0,t.data.bgActivePosistion=void 0;var de=t.cy,re=t.touchData.now,oe=t.touchData.earlier;if(W.touches[0]){var V=t.projectIntoViewport(W.touches[0].clientX,W.touches[0].clientY);re[0]=V[0],re[1]=V[1]}if(W.touches[1]){var V=t.projectIntoViewport(W.touches[1].clientX,W.touches[1].clientY);re[2]=V[0],re[3]=V[1]}if(W.touches[2]){var V=t.projectIntoViewport(W.touches[2].clientX,W.touches[2].clientY);re[4]=V[0],re[5]=V[1]}if(W.touches[1]){t.touchData.singleTouchMoved=!0,x(t.dragData.touchDragEles);var xe=t.findContainerClientCoords();j=xe[0],ie=xe[1],ne=xe[2],le=xe[3],M=W.touches[0].clientX-j,B=W.touches[0].clientY-ie,F=W.touches[1].clientX-j,P=W.touches[1].clientY-ie,he=0<=M&&M<=ne&&0<=F&&F<=ne&&0<=B&&B<=le&&0<=P&&P<=le;var q=de.pan(),pe=de.zoom();z=K(M,B,F,P),$=X(M,B,F,P),H=[(M+F)/2,(B+P)/2],Q=[(H[0]-q.x)/pe,(H[1]-q.y)/pe];var ve=200,Pe=ve*ve;if($=1){for(var st=t.touchData.startPosition=[null,null,null,null,null,null],Ue=0;Ue=t.touchTapThreshold2}if(de&&t.touchData.cxt){W.preventDefault();var st=W.touches[0].clientX-j,Ue=W.touches[0].clientY-ie,ct=W.touches[1].clientX-j,We=W.touches[1].clientY-ie,ot=X(st,Ue,ct,We),Yt=ot/$,bt=150,Mt=bt*bt,xt=1.5,ut=xt*xt;if(Yt>=ut||ot>=Mt){t.touchData.cxt=!1,t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);var Et={originalEvent:W,type:"cxttapend",position:{x:V[0],y:V[1]}};t.touchData.start?(t.touchData.start.unactivate().emit(Et),t.touchData.start=null):oe.emit(Et)}}if(de&&t.touchData.cxt){var Et={originalEvent:W,type:"cxtdrag",position:{x:V[0],y:V[1]}};t.data.bgActivePosistion=void 0,t.redrawHint("select",!0),t.touchData.start?t.touchData.start.emit(Et):oe.emit(Et),t.touchData.start&&(t.touchData.start._private.grabbed=!1),t.touchData.cxtDragged=!0;var ft=t.findNearestElement(V[0],V[1],!0,!0);(!t.touchData.cxtOver||ft!==t.touchData.cxtOver)&&(t.touchData.cxtOver&&t.touchData.cxtOver.emit({originalEvent:W,type:"cxtdragout",position:{x:V[0],y:V[1]}}),t.touchData.cxtOver=ft,ft&&ft.emit({originalEvent:W,type:"cxtdragover",position:{x:V[0],y:V[1]}}))}else if(de&&W.touches[2]&&oe.boxSelectionEnabled())W.preventDefault(),t.data.bgActivePosistion=void 0,this.lastThreeTouch=+new Date,t.touchData.selecting||oe.emit({originalEvent:W,type:"boxstart",position:{x:V[0],y:V[1]}}),t.touchData.selecting=!0,t.touchData.didSelect=!0,re[4]=1,!re||re.length===0||re[0]===void 0?(re[0]=(V[0]+V[2]+V[4])/3,re[1]=(V[1]+V[3]+V[5])/3,re[2]=(V[0]+V[2]+V[4])/3+1,re[3]=(V[1]+V[3]+V[5])/3+1):(re[2]=(V[0]+V[2]+V[4])/3,re[3]=(V[1]+V[3]+V[5])/3),t.redrawHint("select",!0),t.redraw();else if(de&&W.touches[1]&&!t.touchData.didSelect&&oe.zoomingEnabled()&&oe.panningEnabled()&&oe.userZoomingEnabled()&&oe.userPanningEnabled()){W.preventDefault(),t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);var yt=t.dragData.touchDragEles;if(yt){t.redrawHint("drag",!0);for(var nt=0;nt0&&!t.hoverData.draggingEles&&!t.swipePanning&&t.data.bgActivePosistion!=null&&(t.data.bgActivePosistion=void 0,t.redrawHint("select",!0),t.redraw())}},"touchmoveHandler"),!1);var se;t.registerBinding(e,"touchcancel",se=o(function(W){var de=t.touchData.start;t.touchData.capture=!1,de&&de.unactivate()},"touchcancelHandler"));var ue,Z,Se,ce;if(t.registerBinding(e,"touchend",ue=o(function(W){var de=t.touchData.start,re=t.touchData.capture;if(re)W.touches.length===0&&(t.touchData.capture=!1),W.preventDefault();else return;var oe=t.selection;t.swipePanning=!1,t.hoverData.draggingEles=!1;var V=t.cy,xe=V.zoom(),q=t.touchData.now,pe=t.touchData.earlier;if(W.touches[0]){var ve=t.projectIntoViewport(W.touches[0].clientX,W.touches[0].clientY);q[0]=ve[0],q[1]=ve[1]}if(W.touches[1]){var ve=t.projectIntoViewport(W.touches[1].clientX,W.touches[1].clientY);q[2]=ve[0],q[3]=ve[1]}if(W.touches[2]){var ve=t.projectIntoViewport(W.touches[2].clientX,W.touches[2].clientY);q[4]=ve[0],q[5]=ve[1]}de&&de.unactivate();var Pe;if(t.touchData.cxt){if(Pe={originalEvent:W,type:"cxttapend",position:{x:q[0],y:q[1]}},de?de.emit(Pe):V.emit(Pe),!t.touchData.cxtDragged){var _e={originalEvent:W,type:"cxttap",position:{x:q[0],y:q[1]}};de?de.emit(_e):V.emit(_e)}t.touchData.start&&(t.touchData.start._private.grabbed=!1),t.touchData.cxt=!1,t.touchData.start=null,t.redraw();return}if(!W.touches[2]&&V.boxSelectionEnabled()&&t.touchData.selecting){t.touchData.selecting=!1;var we=V.collection(t.getAllInBox(oe[0],oe[1],oe[2],oe[3]));oe[0]=void 0,oe[1]=void 0,oe[2]=void 0,oe[3]=void 0,oe[4]=0,t.redrawHint("select",!0),V.emit({type:"boxend",originalEvent:W,position:{x:q[0],y:q[1]}});var Ve=o(function(Mt){return Mt.selectable()&&!Mt.selected()},"eleWouldBeSelected");we.emit("box").stdFilter(Ve).select().emit("boxselect"),we.nonempty()&&t.redrawHint("eles",!0),t.redraw()}if(de?.unactivate(),W.touches[2])t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);else if(!W.touches[1]){if(!W.touches[0]){if(!W.touches[0]){t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);var De=t.dragData.touchDragEles;if(de!=null){var qe=de._private.grabbed;x(De),t.redrawHint("drag",!0),t.redrawHint("eles",!0),qe&&(de.emit("freeon"),De.emit("free"),t.dragData.didDrag&&(de.emit("dragfreeon"),De.emit("dragfree"))),i(de,["touchend","tapend","vmouseup","tapdragout"],W,{x:q[0],y:q[1]}),de.unactivate(),t.touchData.start=null}else{var at=t.findNearestElement(q[0],q[1],!0,!0);i(at,["touchend","tapend","vmouseup","tapdragout"],W,{x:q[0],y:q[1]})}var Rt=t.touchData.startPosition[0]-q[0],st=Rt*Rt,Ue=t.touchData.startPosition[1]-q[1],ct=Ue*Ue,We=st+ct,ot=We*xe*xe;t.touchData.singleTouchMoved||(de||V.$(":selected").unselect(["tapunselect"]),i(de,["tap","vclick"],W,{x:q[0],y:q[1]}),Z=!1,W.timeStamp-ce<=V.multiClickDebounceTime()?(Se&&clearTimeout(Se),Z=!0,ce=null,i(de,["dbltap","vdblclick"],W,{x:q[0],y:q[1]})):(Se=setTimeout(function(){Z||i(de,["onetap","voneclick"],W,{x:q[0],y:q[1]})},V.multiClickDebounceTime()),ce=W.timeStamp)),de!=null&&!t.dragData.didDrag&&de._private.selectable&&ot"u"){var ae=[],Oe=o(function(W){return{clientX:W.clientX,clientY:W.clientY,force:1,identifier:W.pointerId,pageX:W.pageX,pageY:W.pageY,radiusX:W.width/2,radiusY:W.height/2,screenX:W.screenX,screenY:W.screenY,target:W.target}},"makeTouch"),ge=o(function(W){return{event:W,touch:Oe(W)}},"makePointer"),ze=o(function(W){ae.push(ge(W))},"addPointer"),He=o(function(W){for(var de=0;de0)return H[0]}return null},"getCurveT"),g=Object.keys(p),y=0;y0?m:vme(a,s,e,r,n,i,l,u)},"intersectLine"),checkPoint:o(function(e,r,n,i,a,s,l,u){u=u==="auto"?Vp(i,a):u;var h=2*u;if(Zu(e,r,this.points,s,l,i,a-h,[0,-1],n)||Zu(e,r,this.points,s,l,i-h,a,[0,-1],n))return!0;var f=i/2+2*n,d=a/2+2*n,p=[s-f,l-d,s-f,l,s+f,l,s+f,l-d];return!!(Us(e,r,p)||$p(e,r,h,h,s+i/2-u,l+a/2-u,n)||$p(e,r,h,h,s-i/2+u,l+a/2-u,n))},"checkPoint")}};eh.registerNodeShapes=function(){var t=this.nodeShapes={},e=this;this.generateEllipse(),this.generatePolygon("triangle",gs(3,0)),this.generateRoundPolygon("round-triangle",gs(3,0)),this.generatePolygon("rectangle",gs(4,0)),t.square=t.rectangle,this.generateRoundRectangle(),this.generateCutRectangle(),this.generateBarrel(),this.generateBottomRoundrectangle();{var r=[0,1,1,0,0,-1,-1,0];this.generatePolygon("diamond",r),this.generateRoundPolygon("round-diamond",r)}this.generatePolygon("pentagon",gs(5,0)),this.generateRoundPolygon("round-pentagon",gs(5,0)),this.generatePolygon("hexagon",gs(6,0)),this.generateRoundPolygon("round-hexagon",gs(6,0)),this.generatePolygon("heptagon",gs(7,0)),this.generateRoundPolygon("round-heptagon",gs(7,0)),this.generatePolygon("octagon",gs(8,0)),this.generateRoundPolygon("round-octagon",gs(8,0));var n=new Array(20);{var i=PP(5,0),a=PP(5,Math.PI/5),s=.5*(3-Math.sqrt(5));s*=1.57;for(var l=0;l=e.deqFastCost*C)break}else if(h){if(b>=e.deqCost*m||b>=e.deqAvgCost*p)break}else if(w>=e.deqNoDrawCost*DP)break;var T=e.deq(n,v,y);if(T.length>0)for(var E=0;E0&&(e.onDeqd(n,g),!h&&e.shouldRedraw(n,g,v,y)&&a())},"dequeue"),l=e.priority||rB;i.beforeRender(s,l(n))}},"setupDequeueingImpl")},"setupDequeueing")},RQe=function(){function t(e){var r=arguments.length>1&&arguments[1]!==void 0?arguments[1]:bS;Mf(this,t),this.idsByKey=new Xc,this.keyForId=new Xc,this.cachesByLvl=new Xc,this.lvls=[],this.getKey=e,this.doesEleInvalidateKey=r}return o(t,"ElementTextureCacheLookup"),If(t,[{key:"getIdsFor",value:o(function(r){r==null&&ai("Can not get id list for null key");var n=this.idsByKey,i=this.idsByKey.get(r);return i||(i=new J1,n.set(r,i)),i},"getIdsFor")},{key:"addIdForKey",value:o(function(r,n){r!=null&&this.getIdsFor(r).add(n)},"addIdForKey")},{key:"deleteIdForKey",value:o(function(r,n){r!=null&&this.getIdsFor(r).delete(n)},"deleteIdForKey")},{key:"getNumberOfIdsForKey",value:o(function(r){return r==null?0:this.getIdsFor(r).size},"getNumberOfIdsForKey")},{key:"updateKeyMappingFor",value:o(function(r){var n=r.id(),i=this.keyForId.get(n),a=this.getKey(r);this.deleteIdForKey(i,n),this.addIdForKey(a,n),this.keyForId.set(n,a)},"updateKeyMappingFor")},{key:"deleteKeyMappingFor",value:o(function(r){var n=r.id(),i=this.keyForId.get(n);this.deleteIdForKey(i,n),this.keyForId.delete(n)},"deleteKeyMappingFor")},{key:"keyHasChangedFor",value:o(function(r){var n=r.id(),i=this.keyForId.get(n),a=this.getKey(r);return i!==a},"keyHasChangedFor")},{key:"isInvalid",value:o(function(r){return this.keyHasChangedFor(r)||this.doesEleInvalidateKey(r)},"isInvalid")},{key:"getCachesAt",value:o(function(r){var n=this.cachesByLvl,i=this.lvls,a=n.get(r);return a||(a=new Xc,n.set(r,a),i.push(r)),a},"getCachesAt")},{key:"getCache",value:o(function(r,n){return this.getCachesAt(n).get(r)},"getCache")},{key:"get",value:o(function(r,n){var i=this.getKey(r),a=this.getCache(i,n);return a!=null&&this.updateKeyMappingFor(r),a},"get")},{key:"getForCachedKey",value:o(function(r,n){var i=this.keyForId.get(r.id()),a=this.getCache(i,n);return a},"getForCachedKey")},{key:"hasCache",value:o(function(r,n){return this.getCachesAt(n).has(r)},"hasCache")},{key:"has",value:o(function(r,n){var i=this.getKey(r);return this.hasCache(i,n)},"has")},{key:"setCache",value:o(function(r,n,i){i.key=r,this.getCachesAt(n).set(r,i)},"setCache")},{key:"set",value:o(function(r,n,i){var a=this.getKey(r);this.setCache(a,n,i),this.updateKeyMappingFor(r)},"set")},{key:"deleteCache",value:o(function(r,n){this.getCachesAt(n).delete(r)},"deleteCache")},{key:"delete",value:o(function(r,n){var i=this.getKey(r);this.deleteCache(i,n)},"_delete")},{key:"invalidateKey",value:o(function(r){var n=this;this.lvls.forEach(function(i){return n.deleteCache(r,i)})},"invalidateKey")},{key:"invalidate",value:o(function(r){var n=r.id(),i=this.keyForId.get(n);this.deleteKeyMappingFor(r);var a=this.doesEleInvalidateKey(r);return a&&this.invalidateKey(i),a||this.getNumberOfIdsForKey(i)===0},"invalidate")}]),t}(),I0e=25,sS=50,yS=-4,XP=3,bge=7.99,NQe=8,MQe=1024,IQe=1024,OQe=1024,PQe=.2,BQe=.8,FQe=10,$Qe=.15,zQe=.1,GQe=.9,VQe=.9,UQe=100,HQe=1,H1={dequeue:"dequeue",downscale:"downscale",highQuality:"highQuality"},WQe=la({getKey:null,doesEleInvalidateKey:bS,drawElement:null,getBoundingBox:null,getRotationPoint:null,getRotationOffset:null,isVisible:ume,allowEdgeTxrCaching:!0,allowParentTxrCaching:!0}),Fb=o(function(e,r){var n=this;n.renderer=e,n.onDequeues=[];var i=WQe(r);rr(n,i),n.lookup=new RQe(i.getKey,i.doesEleInvalidateKey),n.setupDequeueing()},"ElementTextureCache"),qi=Fb.prototype;qi.reasons=H1;qi.getTextureQueue=function(t){var e=this;return e.eleImgCaches=e.eleImgCaches||{},e.eleImgCaches[t]=e.eleImgCaches[t]||[]};qi.getRetiredTextureQueue=function(t){var e=this,r=e.eleImgCaches.retired=e.eleImgCaches.retired||{},n=r[t]=r[t]||[];return n};qi.getElementQueue=function(){var t=this,e=t.eleCacheQueue=t.eleCacheQueue||new i4(function(r,n){return n.reqs-r.reqs});return e};qi.getElementKeyToQueue=function(){var t=this,e=t.eleKeyToCacheQueue=t.eleKeyToCacheQueue||{};return e};qi.getElement=function(t,e,r,n,i){var a=this,s=this.renderer,l=s.cy.zoom(),u=this.lookup;if(!e||e.w===0||e.h===0||isNaN(e.w)||isNaN(e.h)||!t.visible()||t.removed()||!a.allowEdgeTxrCaching&&t.isEdge()||!a.allowParentTxrCaching&&t.isParent())return null;if(n==null&&(n=Math.ceil(iB(l*r))),n=bge||n>XP)return null;var h=Math.pow(2,n),f=e.h*h,d=e.w*h,p=s.eleTextBiggerThanMin(t,h);if(!this.isVisible(t,p))return null;var m=u.get(t,n);if(m&&m.invalidated&&(m.invalidated=!1,m.texture.invalidatedWidth-=m.width),m)return m;var g;if(f<=I0e?g=I0e:f<=sS?g=sS:g=Math.ceil(f/sS)*sS,f>OQe||d>IQe)return null;var y=a.getTextureQueue(g),v=y[y.length-2],x=o(function(){return a.recycleTexture(g,d)||a.addTexture(g,d)},"addNewTxr");v||(v=y[y.length-1]),v||(v=x()),v.width-v.usedWidthn;D--)_=a.getElement(t,e,r,D,H1.downscale);I()}else return a.queueElement(t,E.level-1),E;else{var k;if(!w&&!C&&!T)for(var L=n-1;L>=yS;L--){var R=u.get(t,L);if(R){k=R;break}}if(b(k))return a.queueElement(t,n),k;v.context.translate(v.usedWidth,0),v.context.scale(h,h),this.drawElement(v.context,t,e,p,!1),v.context.scale(1/h,1/h),v.context.translate(-v.usedWidth,0)}return m={x:v.usedWidth,texture:v,level:n,scale:h,width:d,height:f,scaledLabelShown:p},v.usedWidth+=Math.ceil(d+NQe),v.eleCaches.push(m),u.set(t,n,m),a.checkTextureFullness(v),m};qi.invalidateElements=function(t){for(var e=0;e=PQe*t.width&&this.retireTexture(t)};qi.checkTextureFullness=function(t){var e=this,r=e.getTextureQueue(t.height);t.usedWidth/t.width>BQe&&t.fullnessChecks>=FQe?Df(r,t):t.fullnessChecks++};qi.retireTexture=function(t){var e=this,r=t.height,n=e.getTextureQueue(r),i=this.lookup;Df(n,t),t.retired=!0;for(var a=t.eleCaches,s=0;s=e)return s.retired=!1,s.usedWidth=0,s.invalidatedWidth=0,s.fullnessChecks=0,nB(s.eleCaches),s.context.setTransform(1,0,0,1,0,0),s.context.clearRect(0,0,s.width,s.height),Df(i,s),n.push(s),s}};qi.queueElement=function(t,e){var r=this,n=r.getElementQueue(),i=r.getElementKeyToQueue(),a=this.getKey(t),s=i[a];if(s)s.level=Math.max(s.level,e),s.eles.merge(t),s.reqs++,n.updateItem(s);else{var l={eles:t.spawn().merge(t),level:e,reqs:1,key:a};n.push(l),i[a]=l}};qi.dequeue=function(t){for(var e=this,r=e.getElementQueue(),n=e.getElementKeyToQueue(),i=[],a=e.lookup,s=0;s0;s++){var l=r.pop(),u=l.key,h=l.eles[0],f=a.hasCache(h,l.level);if(n[u]=null,f)continue;i.push(l);var d=e.getBoundingBox(h);e.getElement(h,d,t,l.level,H1.dequeue)}return i};qi.removeFromQueue=function(t){var e=this,r=e.getElementQueue(),n=e.getElementKeyToQueue(),i=this.getKey(t),a=n[i];a!=null&&(a.eles.length===1?(a.reqs=tB,r.updateItem(a),r.pop(),n[i]=null):a.eles.unmerge(t))};qi.onDequeue=function(t){this.onDequeues.push(t)};qi.offDequeue=function(t){Df(this.onDequeues,t)};qi.setupDequeueing=xge.setupDequeueing({deqRedrawThreshold:UQe,deqCost:$Qe,deqAvgCost:zQe,deqNoDrawCost:GQe,deqFastCost:VQe,deq:o(function(e,r,n){return e.dequeue(r,n)},"deq"),onDeqd:o(function(e,r){for(var n=0;n=YQe||r>_S)return null}n.validateLayersElesOrdering(r,t);var u=n.layersByLevel,h=Math.pow(2,r),f=u[r]=u[r]||[],d,p=n.levelIsComplete(r,t),m,g=o(function(){var I=o(function(O){if(n.validateLayersElesOrdering(O,t),n.levelIsComplete(O,t))return m=u[O],!0},"canUseAsTmpLvl"),D=o(function(O){if(!m)for(var M=r+O;zb<=M&&M<=_S&&!I(M);M+=O);},"checkLvls");D(1),D(-1);for(var k=f.length-1;k>=0;k--){var L=f[k];L.invalid&&Df(f,L)}},"checkTempLevels");if(!p)g();else return f;var y=o(function(){if(!d){d=Hs();for(var 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m=n.padding();a=n.width()+2*m,s=n.height()+2*m}l.colorFillStyle(r,f[0],f[1],f[2],h),l.nodeShapes[d].draw(r,i.x,i.y,a+u*2,s+u*2,p),r.fill()}}}},"drawNodeOverlayUnderlay");ly.drawNodeOverlay=Ege("overlay");ly.drawNodeUnderlay=Ege("underlay");ly.hasPie=function(t){return t=t[0],t._private.hasPie};ly.drawPie=function(t,e,r,n){e=e[0],n=n||e.position();var i=e.cy().style(),a=e.pstyle("pie-size"),s=n.x,l=n.y,u=e.width(),h=e.height(),f=Math.min(u,h)/2,d=0,p=this.usePaths();p&&(s=0,l=0),a.units==="%"?f=f*a.pfValue:a.pfValue!==void 0&&(f=a.pfValue/2);for(var m=1;m<=i.pieBackgroundN;m++){var g=e.pstyle("pie-"+m+"-background-size").value,y=e.pstyle("pie-"+m+"-background-color").value,v=e.pstyle("pie-"+m+"-background-opacity").value*r,x=g/100;x+d>1&&(x=1-d);var b=1.5*Math.PI+2*Math.PI*d,w=2*Math.PI*x,C=b+w;g===0||d>=1||d+x>1||(t.beginPath(),t.moveTo(s,l),t.arc(s,l,f,b,C),t.closePath(),this.colorFillStyle(t,y[0],y[1],y[2],v),t.fill(),d+=x)}};ys={},dZe=100;ys.getPixelRatio=function(){var t=this.data.contexts[0];if(this.forcedPixelRatio!=null)return this.forcedPixelRatio;var e=this.cy.window(),r=t.backingStorePixelRatio||t.webkitBackingStorePixelRatio||t.mozBackingStorePixelRatio||t.msBackingStorePixelRatio||t.oBackingStorePixelRatio||t.backingStorePixelRatio||1;return(e.devicePixelRatio||1)/r};ys.paintCache=function(t){for(var e=this.paintCaches=this.paintCaches||[],r=!0,n,i=0;ie.minMbLowQualFrames&&(e.motionBlurPxRatio=e.mbPxRBlurry)),e.clearingMotionBlur&&(e.motionBlurPxRatio=1),e.textureDrawLastFrame&&!d&&(f[e.NODE]=!0,f[e.SELECT_BOX]=!0);var b=r.style(),w=r.zoom(),C=s!==void 0?s:w,T=r.pan(),E={x:T.x,y:T.y},A={zoom:w,pan:{x:T.x,y:T.y}},S=e.prevViewport,_=S===void 0||A.zoom!==S.zoom||A.pan.x!==S.pan.x||A.pan.y!==S.pan.y;!_&&!(y&&!g)&&(e.motionBlurPxRatio=1),l&&(E=l),C*=u,E.x*=u,E.y*=u;var I=e.getCachedZSortedEles();function D(K,X,te,J,se){var ue=K.globalCompositeOperation;K.globalCompositeOperation="destination-out",e.colorFillStyle(K,255,255,255,e.motionBlurTransparency),K.fillRect(X,te,J,se),K.globalCompositeOperation=ue}o(D,"mbclear");function k(K,X){var te,J,se,ue;!e.clearingMotionBlur&&(K===h.bufferContexts[e.MOTIONBLUR_BUFFER_NODE]||K===h.bufferContexts[e.MOTIONBLUR_BUFFER_DRAG])?(te={x:T.x*m,y:T.y*m},J=w*m,se=e.canvasWidth*m,ue=e.canvasHeight*m):(te=E,J=C,se=e.canvasWidth,ue=e.canvasHeight),K.setTransform(1,0,0,1,0,0),X==="motionBlur"?D(K,0,0,se,ue):!n&&(X===void 0||X)&&K.clearRect(0,0,se,ue),i||(K.translate(te.x,te.y),K.scale(J,J)),l&&K.translate(l.x,l.y),s&&K.scale(s,s)}if(o(k,"setContextTransform"),d||(e.textureDrawLastFrame=!1),d){if(e.textureDrawLastFrame=!0,!e.textureCache){e.textureCache={},e.textureCache.bb=r.mutableElements().boundingBox(),e.textureCache.texture=e.data.bufferCanvases[e.TEXTURE_BUFFER];var L=e.data.bufferContexts[e.TEXTURE_BUFFER];L.setTransform(1,0,0,1,0,0),L.clearRect(0,0,e.canvasWidth*e.textureMult,e.canvasHeight*e.textureMult),e.render({forcedContext:L,drawOnlyNodeLayer:!0,forcedPxRatio:u*e.textureMult});var A=e.textureCache.viewport={zoom:r.zoom(),pan:r.pan(),width:e.canvasWidth,height:e.canvasHeight};A.mpan={x:(0-A.pan.x)/A.zoom,y:(0-A.pan.y)/A.zoom}}f[e.DRAG]=!1,f[e.NODE]=!1;var R=h.contexts[e.NODE],O=e.textureCache.texture,A=e.textureCache.viewport;R.setTransform(1,0,0,1,0,0),p?D(R,0,0,A.width,A.height):R.clearRect(0,0,A.width,A.height);var M=b.core("outside-texture-bg-color").value,B=b.core("outside-texture-bg-opacity").value;e.colorFillStyle(R,M[0],M[1],M[2],B),R.fillRect(0,0,A.width,A.height);var w=r.zoom();k(R,!1),R.clearRect(A.mpan.x,A.mpan.y,A.width/A.zoom/u,A.height/A.zoom/u),R.drawImage(O,A.mpan.x,A.mpan.y,A.width/A.zoom/u,A.height/A.zoom/u)}else e.textureOnViewport&&!n&&(e.textureCache=null);var F=r.extent(),P=e.pinching||e.hoverData.dragging||e.swipePanning||e.data.wheelZooming||e.hoverData.draggingEles||e.cy.animated(),z=e.hideEdgesOnViewport&&P,$=[];if($[e.NODE]=!f[e.NODE]&&p&&!e.clearedForMotionBlur[e.NODE]||e.clearingMotionBlur,$[e.NODE]&&(e.clearedForMotionBlur[e.NODE]=!0),$[e.DRAG]=!f[e.DRAG]&&p&&!e.clearedForMotionBlur[e.DRAG]||e.clearingMotionBlur,$[e.DRAG]&&(e.clearedForMotionBlur[e.DRAG]=!0),f[e.NODE]||i||a||$[e.NODE]){var H=p&&!$[e.NODE]&&m!==1,R=n||(H?e.data.bufferContexts[e.MOTIONBLUR_BUFFER_NODE]:h.contexts[e.NODE]),Q=p&&!H?"motionBlur":void 0;k(R,Q),z?e.drawCachedNodes(R,I.nondrag,u,F):e.drawLayeredElements(R,I.nondrag,u,F),e.debug&&e.drawDebugPoints(R,I.nondrag),!i&&!p&&(f[e.NODE]=!1)}if(!a&&(f[e.DRAG]||i||$[e.DRAG])){var H=p&&!$[e.DRAG]&&m!==1,R=n||(H?e.data.bufferContexts[e.MOTIONBLUR_BUFFER_DRAG]:h.contexts[e.DRAG]);k(R,p&&!H?"motionBlur":void 0),z?e.drawCachedNodes(R,I.drag,u,F):e.drawCachedElements(R,I.drag,u,F),e.debug&&e.drawDebugPoints(R,I.drag),!i&&!p&&(f[e.DRAG]=!1)}if(this.drawSelectionRectangle(t,k),p&&m!==1){var j=h.contexts[e.NODE],ie=e.data.bufferCanvases[e.MOTIONBLUR_BUFFER_NODE],ne=h.contexts[e.DRAG],le=e.data.bufferCanvases[e.MOTIONBLUR_BUFFER_DRAG],he=o(function(X,te,J){X.setTransform(1,0,0,1,0,0),J||!x?X.clearRect(0,0,e.canvasWidth,e.canvasHeight):D(X,0,0,e.canvasWidth,e.canvasHeight);var se=m;X.drawImage(te,0,0,e.canvasWidth*se,e.canvasHeight*se,0,0,e.canvasWidth,e.canvasHeight)},"drawMotionBlur");(f[e.NODE]||$[e.NODE])&&(he(j,ie,$[e.NODE]),f[e.NODE]=!1),(f[e.DRAG]||$[e.DRAG])&&(he(ne,le,$[e.DRAG]),f[e.DRAG]=!1)}e.prevViewport=A,e.clearingMotionBlur&&(e.clearingMotionBlur=!1,e.motionBlurCleared=!0,e.motionBlur=!0),p&&(e.motionBlurTimeout=setTimeout(function(){e.motionBlurTimeout=null,e.clearedForMotionBlur[e.NODE]=!1,e.clearedForMotionBlur[e.DRAG]=!1,e.motionBlur=!1,e.clearingMotionBlur=!d,e.mbFrames=0,f[e.NODE]=!0,f[e.DRAG]=!0,e.redraw()},dZe)),n||r.emit("render")};ys.drawSelectionRectangle=function(t,e){var r=this,n=r.cy,i=r.data,a=n.style(),s=t.drawOnlyNodeLayer,l=t.drawAllLayers,u=i.canvasNeedsRedraw,h=t.forcedContext;if(r.showFps||!s&&u[r.SELECT_BOX]&&!l){var f=h||i.contexts[r.SELECT_BOX];if(e(f),r.selection[4]==1&&(r.hoverData.selecting||r.touchData.selecting)){var d=r.cy.zoom(),p=a.core("selection-box-border-width").value/d;f.lineWidth=p,f.fillStyle="rgba("+a.core("selection-box-color").value[0]+","+a.core("selection-box-color").value[1]+","+a.core("selection-box-color").value[2]+","+a.core("selection-box-opacity").value+")",f.fillRect(r.selection[0],r.selection[1],r.selection[2]-r.selection[0],r.selection[3]-r.selection[1]),p>0&&(f.strokeStyle="rgba("+a.core("selection-box-border-color").value[0]+","+a.core("selection-box-border-color").value[1]+","+a.core("selection-box-border-color").value[2]+","+a.core("selection-box-opacity").value+")",f.strokeRect(r.selection[0],r.selection[1],r.selection[2]-r.selection[0],r.selection[3]-r.selection[1]))}if(i.bgActivePosistion&&!r.hoverData.selecting){var d=r.cy.zoom(),m=i.bgActivePosistion;f.fillStyle="rgba("+a.core("active-bg-color").value[0]+","+a.core("active-bg-color").value[1]+","+a.core("active-bg-color").value[2]+","+a.core("active-bg-opacity").value+")",f.beginPath(),f.arc(m.x,m.y,a.core("active-bg-size").pfValue/d,0,2*Math.PI),f.fill()}var g=r.lastRedrawTime;if(r.showFps&&g){g=Math.round(g);var y=Math.round(1e3/g),v="1 frame = "+g+" ms = "+y+" fps";if(f.setTransform(1,0,0,1,0,0),f.fillStyle="rgba(255, 0, 0, 0.75)",f.strokeStyle="rgba(255, 0, 0, 0.75)",f.font="30px Arial",!Nb){var x=f.measureText(v);Nb=x.actualBoundingBoxAscent}f.fillText(v,0,Nb);var b=60;f.strokeRect(0,Nb+10,250,20),f.fillRect(0,Nb+10,250*Math.min(y/b,1),20)}l||(u[r.SELECT_BOX]=!1)}};o(z0e,"compileShader");o(pZe,"createProgram");o(mZe,"createTextureCanvas");o(wB,"getEffectivePanZoom");o(NP,"modelToRenderedPosition");o(oS,"toWebGLColor");o(lS,"indexToVec4");o(gZe,"vec4ToIndex");o(yZe,"createTexture");o(Sge,"getTypeInfo");o(Cge,"createTypedArray");o(vZe,"createTypedArrayView");o(xZe,"createBufferStaticDraw");o(po,"createBufferDynamicDraw");o(bZe,"createPickingFrameBuffer");G0e=typeof Float32Array<"u"?Float32Array:Array;Math.hypot||(Math.hypot=function(){for(var t=0,e=arguments.length;e--;)t+=arguments[e]*arguments[e];return Math.sqrt(t)});o(Gb,"create");o(Age,"identity");o(wZe,"multiply");o(DS,"translate");o(_ge,"rotate");o(TB,"scale");o(TZe,"projection");Vb={SCREEN:{name:"screen",screen:!0},PICKING:{name:"picking",picking:!0}},Mb=la({getKey:null,drawElement:null,getBoundingBox:null,getRotation:null,getRotationPoint:null,getRotationOffset:null,isVisible:null,getPadding:null}),kZe=function(){function t(e,r){Mf(this,t),this.debugID=Math.floor(Math.random()*1e4),this.r=e,this.atlasSize=r.webglTexSize,this.rows=r.webglTexRows,this.enableWrapping=r.enableWrapping,this.texHeight=Math.floor(this.atlasSize/this.rows),this.maxTexWidth=this.atlasSize,this.texture=null,this.canvas=null,this.needsBuffer=!0,this.freePointer={x:0,row:0},this.keyToLocation=new Map,this.canvas=r.createTextureCanvas(e,this.atlasSize,this.atlasSize),this.scratch=r.createTextureCanvas(e,this.atlasSize,this.texHeight,"scratch")}return o(t,"Atlas"),If(t,[{key:"getKeys",value:o(function(){return new Set(this.keyToLocation.keys())},"getKeys")},{key:"getScale",value:o(function(r){var n=r.w,i=r.h,a=this.texHeight,s=this.maxTexWidth,l=a/i,u=n*l,h=i*l;return u>s&&(l=s/n,u=n*l,h=i*l),{scale:l,texW:u,texH:h}},"getScale")},{key:"draw",value:o(function(r,n,i){var a=this,s=this.atlasSize,l=this.rows,u=this.texHeight,h=this.getScale(n),f=h.scale,d=h.texW,p=h.texH,m=[null,null],g=o(function(w,C){if(i&&C){var T=C.context,E=w.x,A=w.row,S=E,_=u*A;T.save(),T.translate(S,_),T.scale(f,f),i(T,n),T.restore()}},"drawAt"),y=o(function(){g(a.freePointer,a.canvas),m[0]={x:a.freePointer.x,y:a.freePointer.row*u,w:d,h:p},m[1]={x:a.freePointer.x+d,y:a.freePointer.row*u,w:0,h:p},a.freePointer.x+=d,a.freePointer.x==s&&(a.freePointer.x=0,a.freePointer.row++)},"drawNormal"),v=o(function(){var w=a.scratch,C=a.canvas;w.clear(),g({x:0,row:0},w);var T=s-a.freePointer.x,E=d-T,A=u;{var S=a.freePointer.x,_=a.freePointer.row*u,I=T;C.context.drawImage(w,0,0,I,A,S,_,I,A),m[0]={x:S,y:_,w:I,h:p}}{var D=T,k=(a.freePointer.row+1)*u,L=E;C&&C.context.drawImage(w,D,0,L,A,0,k,L,A),m[1]={x:0,y:k,w:L,h:p}}a.freePointer.x=E,a.freePointer.row++},"drawWrapped"),x=o(function(){a.freePointer.x=0,a.freePointer.row++},"moveToStartOfNextRow");if(this.freePointer.x+d<=s)y();else{if(this.freePointer.row>=l-1)return!1;this.freePointer.x===s?(x(),y()):this.enableWrapping?v():(x(),y())}return this.keyToLocation.set(r,m),this.needsBuffer=!0,m},"draw")},{key:"getOffsets",value:o(function(r){return this.keyToLocation.get(r)},"getOffsets")},{key:"isEmpty",value:o(function(){return this.freePointer.x===0&&this.freePointer.row===0},"isEmpty")},{key:"canFit",value:o(function(r){var n=this.atlasSize,i=this.rows,a=this.getScale(r),s=a.texW;return this.freePointer.x+s>n?this.freePointer.row1&&arguments[1]!==void 0?arguments[1]:{},i=n.forceRedraw,a=i===void 0?!1:i,s=n.filterEle,l=s===void 0?function(){return!0}:s,u=n.filterType,h=u===void 0?function(){return!0}:u,f=!1,d=mo(r),p;try{for(d.s();!(p=d.n()).done;){var m=p.value;if(l(m)){var g=m.id(),y=mo(this.getRenderTypes()),v;try{for(y.s();!(v=y.n()).done;){var x=v.value;if(h(x.type)){var b=x.getKey(m);a?(x.atlasCollection.deleteKey(g,b),x.atlasCollection.styleKeyNeedsRedraw.add(b),f=!0):f|=x.atlasCollection.checkKeyIsInvalid(g,b)}}}catch(w){y.e(w)}finally{y.f()}}}}catch(w){d.e(w)}finally{d.f()}return f},"invalidate")},{key:"gc",value:o(function(){var r=mo(this.getRenderTypes()),n;try{for(r.s();!(n=r.n()).done;){var i=n.value;i.atlasCollection.gc()}}catch(a){r.e(a)}finally{r.f()}},"gc")},{key:"isRenderable",value:o(function(r,n){var i=this.getRenderTypeOpts(n);return i&&i.isVisible(r)},"isRenderable")},{key:"startBatch",value:o(function(){this.batchAtlases=[]},"startBatch")},{key:"getAtlasCount",value:o(function(){return this.batchAtlases.length},"getAtlasCount")},{key:"getAtlases",value:o(function(){return this.batchAtlases},"getAtlases")},{key:"getOrCreateAtlas",value:o(function(r,n,i){var a=this.renderTypes.get(i),s=a.getKey(r),l=r.id();return a.atlasCollection.draw(l,s,n,function(u){a.drawElement(u,r,n,!0,!0)})},"getOrCreateAtlas")},{key:"getAtlasIndexForBatch",value:o(function(r){var n=this.batchAtlases.indexOf(r);if(n<0){if(this.batchAtlases.length===this.maxAtlasesPerBatch)return;this.batchAtlases.push(r),n=this.batchAtlases.length-1}return n},"getAtlasIndexForBatch")},{key:"getIndexArray",value:o(function(){return Array.from({length:this.maxAtlases},function(r,n){return n})},"getIndexArray")},{key:"getAtlasInfo",value:o(function(r,n){var i=this.renderTypes.get(n),a=i.getBoundingBox(r),s=this.getOrCreateAtlas(r,a,n),l=this.getAtlasIndexForBatch(s);if(l!==void 0){var u=i.getKey(r),h=s.getOffsets(u),f=_i(h,2),d=f[0],p=f[1];return{atlasID:l,tex:d,tex1:d,tex2:p,bb:a,type:n,styleKey:u}}},"getAtlasInfo")},{key:"canAddToCurrentBatch",value:o(function(r,n){if(this.batchAtlases.length===this.maxAtlasesPerBatch){var i=this.renderTypes.get(n),a=i.getKey(r),s=i.atlasCollection.getAtlas(a);return s&&this.batchAtlases.includes(s)}return!0},"canAddToCurrentBatch")},{key:"setTransformMatrix",value:o(function(r,n,i){var a=arguments.length>3&&arguments[3]!==void 0?arguments[3]:!0,s=n.bb,l=n.type,u=n.tex1,h=n.tex2,f=this.getRenderTypeOpts(l),d=f.getPadding?f.getPadding(i):0,p=u.w/(u.w+h.w);a||(p=1-p);var m=this.getAdjustedBB(s,d,a,p),g,y;Age(r);var v=f.getRotation?f.getRotation(i):0;if(v!==0){var x=f.getRotationPoint(i),b=x.x,w=x.y;DS(r,r,[b,w]),_ge(r,r,v);var C=f.getRotationOffset(i);g=C.x+m.xOffset,y=C.y}else g=m.x1,y=m.y1;DS(r,r,[g,y]),TB(r,r,[m.w,m.h])},"setTransformMatrix")},{key:"getTransformMatrix",value:o(function(r,n){var i=arguments.length>2&&arguments[2]!==void 0?arguments[2]:!0,a=Gb();return this.setTransformMatrix(a,r,n,i),a},"getTransformMatrix")},{key:"getAdjustedBB",value:o(function(r,n,i,a){var s=r.x1,l=r.y1,u=r.w,h=r.h;n&&(s-=n,l-=n,u+=2*n,h+=2*n);var f=0,d=u*a;return i&&a<1?u=d:!i&&a<1&&(f=u-d,s+=f,u=d),{x1:s,y1:l,w:u,h,xOffset:f}},"getAdjustedBB")},{key:"getDebugInfo",value:o(function(){var r=[],n=mo(this.renderTypes),i;try{for(n.s();!(i=n.n()).done;){var a=_i(i.value,2),s=a[0],l=a[1],u=l.atlasCollection.getCounts(),h=u.keyCount,f=u.atlasCount;r.push({type:s,keyCount:h,atlasCount:f})}}catch(d){n.e(d)}finally{n.f()}return r},"getDebugInfo")}]),t}(),MP=0,V0e=1,U0e=2,IP=3,AZe=function(){function t(e,r,n){Mf(this,t),this.r=e,this.gl=r,this.maxInstances=n.webglBatchSize,this.maxAtlases=n.webglTexPerBatch,this.atlasSize=n.webglTexSize,this.bgColor=n.bgColor,n.enableWrapping=!0,n.createTextureCanvas=mZe,this.atlasManager=new CZe(e,n),this.program=this.createShaderProgram(Vb.SCREEN),this.pickingProgram=this.createShaderProgram(Vb.PICKING),this.vao=this.createVAO(),this.debugInfo=[]}return o(t,"ElementDrawingWebGL"),If(t,[{key:"addTextureRenderType",value:o(function(r,n){this.atlasManager.addRenderType(r,n)},"addTextureRenderType")},{key:"invalidate",value:o(function(r){var n=arguments.length>1&&arguments[1]!==void 0?arguments[1]:{},i=n.type,a=this.atlasManager;return i?a.invalidate(r,{filterType:o(function(l){return l===i},"filterType"),forceRedraw:!0}):a.invalidate(r)},"invalidate")},{key:"gc",value:o(function(){this.atlasManager.gc()},"gc")},{key:"createShaderProgram",value:o(function(r){var n=this.gl,i=`#version 300 es + precision highp float; + + uniform mat3 uPanZoomMatrix; + uniform int uAtlasSize; + + // instanced + in vec2 aPosition; + + // what are we rendering? + in int aVertType; + + // for picking + in vec4 aIndex; + + // For textures + in int aAtlasId; // which shader unit/atlas to use + in vec4 aTex1; // x/y/w/h of texture in atlas + in vec4 aTex2; + + // for any transforms that are needed + in vec4 aScaleRotate1; // vectors use fewer attributes than matrices + in vec2 aTranslate1; + in vec4 aScaleRotate2; + in vec2 aTranslate2; + + // for edges + in vec4 aPointAPointB; + in vec4 aPointCPointD; + in float aLineWidth; + in vec4 aEdgeColor; + + out vec2 vTexCoord; + out vec4 vEdgeColor; + flat out int vAtlasId; + flat out vec4 vIndex; + flat out int vVertType; + + void main(void) { + int vid = gl_VertexID; + vec2 position = aPosition; + + if(aVertType == `.concat(MP,`) { + float texX; + float texY; + float texW; + float texH; + mat3 texMatrix; + + int vid = gl_VertexID; + if(vid <= 5) { + texX = aTex1.x; + texY = aTex1.y; + texW = aTex1.z; + texH = aTex1.w; + texMatrix = mat3( + vec3(aScaleRotate1.xy, 0.0), + vec3(aScaleRotate2.zw, 0.0), + vec3(aTranslate1, 1.0) + ); + } else { + texX = aTex2.x; + texY = aTex2.y; + texW = aTex2.z; + texH = aTex2.w; + texMatrix = mat3( + vec3(aScaleRotate2.xy, 0.0), + vec3(aScaleRotate2.zw, 0.0), + vec3(aTranslate2, 1.0) + ); + } + + if(vid == 1 || vid == 2 || vid == 4 || vid == 7 || vid == 8 || vid == 10) { + texX += texW; + } + if(vid == 2 || vid == 4 || vid == 5 || vid == 8 || vid == 10 || vid == 11) { + texY += texH; + } + + float d = float(uAtlasSize); + vTexCoord = vec2(texX / d, texY / d); // tex coords must be between 0 and 1 + + gl_Position = vec4(uPanZoomMatrix * texMatrix * vec3(position, 1.0), 1.0); + } + else if(aVertType == `).concat(V0e,` && vid < 6) { + vec2 source = aPointAPointB.xy; + vec2 target = aPointAPointB.zw; + + // adjust the geometry so that the line is centered on the edge + position.y = position.y - 0.5; + + vec2 xBasis = target - source; + vec2 yBasis = normalize(vec2(-xBasis.y, xBasis.x)); + vec2 point = source + xBasis * position.x + yBasis * aLineWidth * position.y; + + gl_Position = vec4(uPanZoomMatrix * vec3(point, 1.0), 1.0); + vEdgeColor = aEdgeColor; + } + else if(aVertType == `).concat(U0e,` && vid < 6) { + vec2 pointA = aPointAPointB.xy; + vec2 pointB = aPointAPointB.zw; + vec2 pointC = aPointCPointD.xy; + vec2 pointD = aPointCPointD.zw; + + // adjust the geometry so that the line is centered on the edge + position.y = position.y - 0.5; + + vec2 p0 = pointA; + vec2 p1 = pointB; + vec2 p2 = pointC; + vec2 pos = position; + if(position.x == 1.0) { + p0 = pointD; + p1 = pointC; + p2 = pointB; + pos = vec2(0.0, -position.y); + } + + vec2 p01 = p1 - p0; + vec2 p12 = p2 - p1; + vec2 p21 = p1 - p2; + + // Find the normal vector. + vec2 tangent = normalize(normalize(p12) + normalize(p01)); + vec2 normal = vec2(-tangent.y, tangent.x); + + // Find the vector perpendicular to p0 -> p1. + vec2 p01Norm = normalize(vec2(-p01.y, p01.x)); + + // Determine the bend direction. + float sigma = sign(dot(p01 + p21, normal)); + float width = aLineWidth; + + if(sign(pos.y) == -sigma) { + // This is an intersecting vertex. Adjust the position so that there's no overlap. + vec2 point = 0.5 * width * normal * -sigma / dot(normal, p01Norm); + gl_Position = vec4(uPanZoomMatrix * vec3(p1 + point, 1.0), 1.0); + } else { + // This is a non-intersecting vertex. Treat it like a mitre join. + vec2 point = 0.5 * width * normal * sigma * dot(normal, p01Norm); + gl_Position = vec4(uPanZoomMatrix * vec3(p1 + point, 1.0), 1.0); + } + + vEdgeColor = aEdgeColor; + } + else if(aVertType == `).concat(IP,` && vid < 3) { + // massage the first triangle into an edge arrow + if(vid == 0) + position = vec2(-0.15, -0.3); + if(vid == 1) + position = vec2( 0.0, 0.0); + if(vid == 2) + position = vec2( 0.15, -0.3); + + mat3 transform = mat3( + vec3(aScaleRotate1.xy, 0.0), + vec3(aScaleRotate1.zw, 0.0), + vec3(aTranslate1, 1.0) + ); + gl_Position = vec4(uPanZoomMatrix * transform * vec3(position, 1.0), 1.0); + vEdgeColor = aEdgeColor; + } else { + gl_Position = vec4(2.0, 0.0, 0.0, 1.0); // discard vertex by putting it outside webgl clip space + } + + vAtlasId = aAtlasId; + vIndex = aIndex; + vVertType = aVertType; + } + `),a=this.atlasManager.getIndexArray(),s=`#version 300 es + precision highp float; + + // define texture unit for each node in the batch + `.concat(a.map(function(h){return"uniform sampler2D uTexture".concat(h,";")}).join(` + `),` + + uniform vec4 uBGColor; + + in vec2 vTexCoord; + in vec4 vEdgeColor; + flat in int vAtlasId; + flat in vec4 vIndex; + flat in int vVertType; + + out vec4 outColor; + + void main(void) { + if(vVertType == `).concat(MP,`) { + `).concat(a.map(function(h){return"if(vAtlasId == ".concat(h,") outColor = texture(uTexture").concat(h,", vTexCoord);")}).join(` + else `),` + } else if(vVertType == `).concat(IP,`) { + // blend arrow color with background (using premultiplied alpha) + outColor.rgb = vEdgeColor.rgb + (uBGColor.rgb * (1.0 - vEdgeColor.a)); + outColor.a = 1.0; // make opaque, masks out line under arrow + } else { + outColor = vEdgeColor; + } + + `).concat(r.picking?`if(outColor.a == 0.0) discard; + else outColor = vIndex;`:"",` + } + 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s(u,h,f){n.call(this,f),this.isOverlapingSourceAndTarget=!1,this.vGraphObject=f,this.bendpoints=[],this.source=u,this.target=h}o(s,"LEdge"),s.prototype=Object.create(n.prototype);for(var l in n)s[l]=n[l];s.prototype.getSource=function(){return this.source},s.prototype.getTarget=function(){return this.target},s.prototype.isInterGraph=function(){return this.isInterGraph},s.prototype.getLength=function(){return this.length},s.prototype.isOverlapingSourceAndTarget=function(){return this.isOverlapingSourceAndTarget},s.prototype.getBendpoints=function(){return this.bendpoints},s.prototype.getLca=function(){return this.lca},s.prototype.getSourceInLca=function(){return this.sourceInLca},s.prototype.getTargetInLca=function(){return this.targetInLca},s.prototype.getOtherEnd=function(u){if(this.source===u)return this.target;if(this.target===u)return this.source;throw"Node is not incident with this edge"},s.prototype.getOtherEndInGraph=function(u,h){for(var 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strict";function n(i){this.vGraphObject=i}o(n,"LGraphObject"),t.exports=n},function(t,e,r){"use strict";var n=r(2),i=r(10),a=r(13),s=r(0),l=r(16),u=r(4);function h(d,p,m,g){m==null&&g==null&&(g=p),n.call(this,g),d.graphManager!=null&&(d=d.graphManager),this.estimatedSize=i.MIN_VALUE,this.inclusionTreeDepth=i.MAX_VALUE,this.vGraphObject=g,this.edges=[],this.graphManager=d,m!=null&&p!=null?this.rect=new a(p.x,p.y,m.width,m.height):this.rect=new a}o(h,"LNode"),h.prototype=Object.create(n.prototype);for(var f in n)h[f]=n[f];h.prototype.getEdges=function(){return this.edges},h.prototype.getChild=function(){return this.child},h.prototype.getOwner=function(){return this.owner},h.prototype.getWidth=function(){return this.rect.width},h.prototype.setWidth=function(d){this.rect.width=d},h.prototype.getHeight=function(){return this.rect.height},h.prototype.setHeight=function(d){this.rect.height=d},h.prototype.getCenterX=function(){return this.rect.x+this.rect.width/2},h.prototype.getCenterY=function(){return this.rect.y+this.rect.height/2},h.prototype.getCenter=function(){return new u(this.rect.x+this.rect.width/2,this.rect.y+this.rect.height/2)},h.prototype.getLocation=function(){return new u(this.rect.x,this.rect.y)},h.prototype.getRect=function(){return this.rect},h.prototype.getDiagonal=function(){return Math.sqrt(this.rect.width*this.rect.width+this.rect.height*this.rect.height)},h.prototype.getHalfTheDiagonal=function(){return Math.sqrt(this.rect.height*this.rect.height+this.rect.width*this.rect.width)/2},h.prototype.setRect=function(d,p){this.rect.x=d.x,this.rect.y=d.y,this.rect.width=p.width,this.rect.height=p.height},h.prototype.setCenter=function(d,p){this.rect.x=d-this.rect.width/2,this.rect.y=p-this.rect.height/2},h.prototype.setLocation=function(d,p){this.rect.x=d,this.rect.y=p},h.prototype.moveBy=function(d,p){this.rect.x+=d,this.rect.y+=p},h.prototype.getEdgeListToNode=function(d){var p=[],m,g=this;return g.edges.forEach(function(y){if(y.target==d){if(y.source!=g)throw"Incorrect edge source!";p.push(y)}}),p},h.prototype.getEdgesBetween=function(d){var p=[],m,g=this;return g.edges.forEach(function(y){if(!(y.source==g||y.target==g))throw"Incorrect edge source and/or target";(y.target==d||y.source==d)&&p.push(y)}),p},h.prototype.getNeighborsList=function(){var d=new Set,p=this;return p.edges.forEach(function(m){if(m.source==p)d.add(m.target);else{if(m.target!=p)throw"Incorrect incidency!";d.add(m.source)}}),d},h.prototype.withChildren=function(){var d=new Set,p,m;if(d.add(this),this.child!=null)for(var g=this.child.getNodes(),y=0;yp&&(this.rect.x-=(this.labelWidth-p)/2,this.setWidth(this.labelWidth)),this.labelHeight>m&&(this.labelPos=="center"?this.rect.y-=(this.labelHeight-m)/2:this.labelPos=="top"&&(this.rect.y-=this.labelHeight-m),this.setHeight(this.labelHeight))}}},h.prototype.getInclusionTreeDepth=function(){if(this.inclusionTreeDepth==i.MAX_VALUE)throw"assert failed";return this.inclusionTreeDepth},h.prototype.transform=function(d){var p=this.rect.x;p>s.WORLD_BOUNDARY?p=s.WORLD_BOUNDARY:p<-s.WORLD_BOUNDARY&&(p=-s.WORLD_BOUNDARY);var m=this.rect.y;m>s.WORLD_BOUNDARY?m=s.WORLD_BOUNDARY:m<-s.WORLD_BOUNDARY&&(m=-s.WORLD_BOUNDARY);var g=new u(p,m),y=d.inverseTransformPoint(g);this.setLocation(y.x,y.y)},h.prototype.getLeft=function(){return this.rect.x},h.prototype.getRight=function(){return this.rect.x+this.rect.width},h.prototype.getTop=function(){return this.rect.y},h.prototype.getBottom=function(){return this.rect.y+this.rect.height},h.prototype.getParent=function(){return this.owner==null?null:this.owner.getParent()},t.exports=h},function(t,e,r){"use strict";function n(i,a){i==null&&a==null?(this.x=0,this.y=0):(this.x=i,this.y=a)}o(n,"PointD"),n.prototype.getX=function(){return this.x},n.prototype.getY=function(){return this.y},n.prototype.setX=function(i){this.x=i},n.prototype.setY=function(i){this.y=i},n.prototype.getDifference=function(i){return new DimensionD(this.x-i.x,this.y-i.y)},n.prototype.getCopy=function(){return new n(this.x,this.y)},n.prototype.translate=function(i){return this.x+=i.width,this.y+=i.height,this},t.exports=n},function(t,e,r){"use strict";var n=r(2),i=r(10),a=r(0),s=r(6),l=r(3),u=r(1),h=r(13),f=r(12),d=r(11);function p(g,y,v){n.call(this,v),this.estimatedSize=i.MIN_VALUE,this.margin=a.DEFAULT_GRAPH_MARGIN,this.edges=[],this.nodes=[],this.isConnected=!1,this.parent=g,y!=null&&y instanceof s?this.graphManager=y:y!=null&&y instanceof Layout&&(this.graphManager=y.graphManager)}o(p,"LGraph"),p.prototype=Object.create(n.prototype);for(var m in n)p[m]=n[m];p.prototype.getNodes=function(){return this.nodes},p.prototype.getEdges=function(){return this.edges},p.prototype.getGraphManager=function(){return this.graphManager},p.prototype.getParent=function(){return this.parent},p.prototype.getLeft=function(){return this.left},p.prototype.getRight=function(){return this.right},p.prototype.getTop=function(){return this.top},p.prototype.getBottom=function(){return this.bottom},p.prototype.isConnected=function(){return this.isConnected},p.prototype.add=function(g,y,v){if(y==null&&v==null){var x=g;if(this.graphManager==null)throw"Graph has no graph mgr!";if(this.getNodes().indexOf(x)>-1)throw"Node already in graph!";return x.owner=this,this.getNodes().push(x),x}else{var b=g;if(!(this.getNodes().indexOf(y)>-1&&this.getNodes().indexOf(v)>-1))throw"Source or target not in graph!";if(!(y.owner==v.owner&&y.owner==this))throw"Both owners must be this graph!";return y.owner!=v.owner?null:(b.source=y,b.target=v,b.isInterGraph=!1,this.getEdges().push(b),y.edges.push(b),v!=y&&v.edges.push(b),b)}},p.prototype.remove=function(g){var y=g;if(g instanceof l){if(y==null)throw"Node is null!";if(!(y.owner!=null&&y.owner==this))throw"Owner graph is invalid!";if(this.graphManager==null)throw"Owner graph manager is invalid!";for(var v=y.edges.slice(),x,b=v.length,w=0;w-1&&E>-1))throw"Source and/or target doesn't know this edge!";x.source.edges.splice(T,1),x.target!=x.source&&x.target.edges.splice(E,1);var C=x.source.owner.getEdges().indexOf(x);if(C==-1)throw"Not in owner's edge list!";x.source.owner.getEdges().splice(C,1)}},p.prototype.updateLeftTop=function(){for(var g=i.MAX_VALUE,y=i.MAX_VALUE,v,x,b,w=this.getNodes(),C=w.length,T=0;Tv&&(g=v),y>x&&(y=x)}return g==i.MAX_VALUE?null:(w[0].getParent().paddingLeft!=null?b=w[0].getParent().paddingLeft:b=this.margin,this.left=y-b,this.top=g-b,new f(this.left,this.top))},p.prototype.updateBounds=function(g){for(var y=i.MAX_VALUE,v=-i.MAX_VALUE,x=i.MAX_VALUE,b=-i.MAX_VALUE,w,C,T,E,A,S=this.nodes,_=S.length,I=0;I<_;I++){var D=S[I];g&&D.child!=null&&D.updateBounds(),w=D.getLeft(),C=D.getRight(),T=D.getTop(),E=D.getBottom(),y>w&&(y=w),vT&&(x=T),bw&&(y=w),vT&&(x=T),b=this.nodes.length){var _=0;v.forEach(function(I){I.owner==g&&_++}),_==this.nodes.length&&(this.isConnected=!0)}},t.exports=p},function(t,e,r){"use strict";var n,i=r(1);function a(s){n=r(5),this.layout=s,this.graphs=[],this.edges=[]}o(a,"LGraphManager"),a.prototype.addRoot=function(){var s=this.layout.newGraph(),l=this.layout.newNode(null),u=this.add(s,l);return this.setRootGraph(u),this.rootGraph},a.prototype.add=function(s,l,u,h,f){if(u==null&&h==null&&f==null){if(s==null)throw"Graph is null!";if(l==null)throw"Parent node is null!";if(this.graphs.indexOf(s)>-1)throw"Graph already in this graph mgr!";if(this.graphs.push(s),s.parent!=null)throw"Already has a parent!";if(l.child!=null)throw"Already has a child!";return s.parent=l,l.child=s,s}else{f=u,h=l,u=s;var d=h.getOwner(),p=f.getOwner();if(!(d!=null&&d.getGraphManager()==this))throw"Source not in this graph mgr!";if(!(p!=null&&p.getGraphManager()==this))throw"Target not in this graph mgr!";if(d==p)return u.isInterGraph=!1,d.add(u,h,f);if(u.isInterGraph=!0,u.source=h,u.target=f,this.edges.indexOf(u)>-1)throw"Edge already in inter-graph edge list!";if(this.edges.push(u),!(u.source!=null&&u.target!=null))throw"Edge source and/or target is null!";if(!(u.source.edges.indexOf(u)==-1&&u.target.edges.indexOf(u)==-1))throw"Edge already in source and/or target incidency list!";return u.source.edges.push(u),u.target.edges.push(u),u}},a.prototype.remove=function(s){if(s instanceof n){var l=s;if(l.getGraphManager()!=this)throw"Graph not in this graph mgr";if(!(l==this.rootGraph||l.parent!=null&&l.parent.graphManager==this))throw"Invalid parent node!";var u=[];u=u.concat(l.getEdges());for(var h,f=u.length,d=0;d=s.getRight()?l[0]+=Math.min(s.getX()-a.getX(),a.getRight()-s.getRight()):s.getX()<=a.getX()&&s.getRight()>=a.getRight()&&(l[0]+=Math.min(a.getX()-s.getX(),s.getRight()-a.getRight())),a.getY()<=s.getY()&&a.getBottom()>=s.getBottom()?l[1]+=Math.min(s.getY()-a.getY(),a.getBottom()-s.getBottom()):s.getY()<=a.getY()&&s.getBottom()>=a.getBottom()&&(l[1]+=Math.min(a.getY()-s.getY(),s.getBottom()-a.getBottom()));var f=Math.abs((s.getCenterY()-a.getCenterY())/(s.getCenterX()-a.getCenterX()));s.getCenterY()===a.getCenterY()&&s.getCenterX()===a.getCenterX()&&(f=1);var d=f*l[0],p=l[1]/f;l[0]d)return l[0]=u,l[1]=m,l[2]=f,l[3]=S,!1;if(hf)return l[0]=p,l[1]=h,l[2]=E,l[3]=d,!1;if(uf?(l[0]=y,l[1]=v,k=!0):(l[0]=g,l[1]=m,k=!0):R===M&&(u>f?(l[0]=p,l[1]=m,k=!0):(l[0]=x,l[1]=v,k=!0)),-O===M?f>u?(l[2]=A,l[3]=S,L=!0):(l[2]=E,l[3]=T,L=!0):O===M&&(f>u?(l[2]=C,l[3]=T,L=!0):(l[2]=_,l[3]=S,L=!0)),k&&L)return!1;if(u>f?h>d?(B=this.getCardinalDirection(R,M,4),F=this.getCardinalDirection(O,M,2)):(B=this.getCardinalDirection(-R,M,3),F=this.getCardinalDirection(-O,M,1)):h>d?(B=this.getCardinalDirection(-R,M,1),F=this.getCardinalDirection(-O,M,3)):(B=this.getCardinalDirection(R,M,2),F=this.getCardinalDirection(O,M,4)),!k)switch(B){case 1:z=m,P=u+-w/M,l[0]=P,l[1]=z;break;case 2:P=x,z=h+b*M,l[0]=P,l[1]=z;break;case 3:z=v,P=u+w/M,l[0]=P,l[1]=z;break;case 4:P=y,z=h+-b*M,l[0]=P,l[1]=z;break}if(!L)switch(F){case 1:H=T,$=f+-D/M,l[2]=$,l[3]=H;break;case 2:$=_,H=d+I*M,l[2]=$,l[3]=H;break;case 3:H=S,$=f+D/M,l[2]=$,l[3]=H;break;case 4:$=A,H=d+-I*M,l[2]=$,l[3]=H;break}}return!1},i.getCardinalDirection=function(a,s,l){return a>s?l:1+l%4},i.getIntersection=function(a,s,l,u){if(u==null)return this.getIntersection2(a,s,l);var h=a.x,f=a.y,d=s.x,p=s.y,m=l.x,g=l.y,y=u.x,v=u.y,x=void 0,b=void 0,w=void 0,C=void 0,T=void 0,E=void 0,A=void 0,S=void 0,_=void 0;return w=p-f,T=h-d,A=d*f-h*p,C=v-g,E=m-y,S=y*g-m*v,_=w*E-C*T,_===0?null:(x=(T*S-E*A)/_,b=(C*A-w*S)/_,new n(x,b))},i.angleOfVector=function(a,s,l,u){var h=void 0;return a!==l?(h=Math.atan((u-s)/(l-a)),l0?1:i<0?-1:0},n.floor=function(i){return i<0?Math.ceil(i):Math.floor(i)},n.ceil=function(i){return i<0?Math.floor(i):Math.ceil(i)},t.exports=n},function(t,e,r){"use strict";function n(){}o(n,"Integer"),n.MAX_VALUE=2147483647,n.MIN_VALUE=-2147483648,t.exports=n},function(t,e,r){"use strict";var n=function(){function h(f,d){for(var p=0;p"u"?"undefined":n(a);return a==null||s!="object"&&s!="function"},t.exports=i},function(t,e,r){"use strict";function n(m){if(Array.isArray(m)){for(var g=0,y=Array(m.length);g0&&g;){for(w.push(T[0]);w.length>0&&g;){var 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i(a,s){this.lworldOrgX=0,this.lworldOrgY=0,this.ldeviceOrgX=0,this.ldeviceOrgY=0,this.lworldExtX=1,this.lworldExtY=1,this.ldeviceExtX=1,this.ldeviceExtY=1}o(i,"Transform"),i.prototype.getWorldOrgX=function(){return this.lworldOrgX},i.prototype.setWorldOrgX=function(a){this.lworldOrgX=a},i.prototype.getWorldOrgY=function(){return this.lworldOrgY},i.prototype.setWorldOrgY=function(a){this.lworldOrgY=a},i.prototype.getWorldExtX=function(){return this.lworldExtX},i.prototype.setWorldExtX=function(a){this.lworldExtX=a},i.prototype.getWorldExtY=function(){return this.lworldExtY},i.prototype.setWorldExtY=function(a){this.lworldExtY=a},i.prototype.getDeviceOrgX=function(){return this.ldeviceOrgX},i.prototype.setDeviceOrgX=function(a){this.ldeviceOrgX=a},i.prototype.getDeviceOrgY=function(){return this.ldeviceOrgY},i.prototype.setDeviceOrgY=function(a){this.ldeviceOrgY=a},i.prototype.getDeviceExtX=function(){return this.ldeviceExtX},i.prototype.setDeviceExtX=function(a){this.ldeviceExtX=a},i.prototype.getDeviceExtY=function(){return this.ldeviceExtY},i.prototype.setDeviceExtY=function(a){this.ldeviceExtY=a},i.prototype.transformX=function(a){var s=0,l=this.lworldExtX;return l!=0&&(s=this.ldeviceOrgX+(a-this.lworldOrgX)*this.ldeviceExtX/l),s},i.prototype.transformY=function(a){var s=0,l=this.lworldExtY;return l!=0&&(s=this.ldeviceOrgY+(a-this.lworldOrgY)*this.ldeviceExtY/l),s},i.prototype.inverseTransformX=function(a){var s=0,l=this.ldeviceExtX;return l!=0&&(s=this.lworldOrgX+(a-this.ldeviceOrgX)*this.lworldExtX/l),s},i.prototype.inverseTransformY=function(a){var s=0,l=this.ldeviceExtY;return l!=0&&(s=this.lworldOrgY+(a-this.ldeviceOrgY)*this.lworldExtY/l),s},i.prototype.inverseTransformPoint=function(a){var s=new n(this.inverseTransformX(a.x),this.inverseTransformY(a.y));return s},t.exports=i},function(t,e,r){"use strict";function n(d){if(Array.isArray(d)){for(var p=0,m=Array(d.length);pa.ADAPTATION_LOWER_NODE_LIMIT&&(this.coolingFactor=Math.max(this.coolingFactor*a.COOLING_ADAPTATION_FACTOR,this.coolingFactor-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*this.coolingFactor*(1-a.COOLING_ADAPTATION_FACTOR))),this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT_INCREMENTAL):(d>a.ADAPTATION_LOWER_NODE_LIMIT?this.coolingFactor=Math.max(a.COOLING_ADAPTATION_FACTOR,1-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*(1-a.COOLING_ADAPTATION_FACTOR)):this.coolingFactor=1,this.initialCoolingFactor=this.coolingFactor,this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT),this.maxIterations=Math.max(this.getAllNodes().length*5,this.maxIterations),this.totalDisplacementThreshold=this.displacementThresholdPerNode*this.getAllNodes().length,this.repulsionRange=this.calcRepulsionRange()},h.prototype.calcSpringForces=function(){for(var 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E=-1,A=Number.MAX_VALUE,S=0;SA&&(E=S,A=T.rowWidth[S]);return E},w.prototype.canAddHorizontal=function(T,E,A){var S=this.getShortestRowIndex(T);if(S<0)return!0;var _=T.rowWidth[S];if(_+T.horizontalPadding+E<=T.width)return!0;var I=0;T.rowHeight[S]0&&(I=A+T.verticalPadding-T.rowHeight[S]);var D;T.width-_>=E+T.horizontalPadding?D=(T.height+I)/(_+E+T.horizontalPadding):D=(T.height+I)/T.width,I=A+T.verticalPadding;var k;return T.widthI&&E!=A){S.splice(-1,1),T.rows[A].push(_),T.rowWidth[E]=T.rowWidth[E]-I,T.rowWidth[A]=T.rowWidth[A]+I,T.width=T.rowWidth[instance.getLongestRowIndex(T)];for(var D=Number.MIN_VALUE,k=0;kD&&(D=S[k].height);E>0&&(D+=T.verticalPadding);var L=T.rowHeight[E]+T.rowHeight[A];T.rowHeight[E]=D,T.rowHeight[A]<_.height+T.verticalPadding&&(T.rowHeight[A]=_.height+T.verticalPadding);var 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38:this.$={type:"applyStyles",id:_[D-1].trim(),stylesStr:_[D].trim()};break}},"anonymous"),table:[{9:1,10:[1,2]},{1:[3]},{11:3,13:4,19:5,20:6,21:e,22:8,23:9,24:10,25:11,26:12,28:r,29:n,31:i,32:a,40:s,44:l,47:u},{8:[1,20]},t(h,[2,12],{13:4,19:5,20:6,22:8,23:9,24:10,25:11,26:12,11:21,21:e,28:r,29:n,31:i,32:a,40:s,44:l,47:u}),t(f,[2,16],{14:22,15:d,16:p}),t(f,[2,17]),t(f,[2,18]),t(f,[2,19]),t(f,[2,20]),t(f,[2,21]),t(f,[2,22]),t(m,[2,25],{27:[1,25]}),t(f,[2,26]),{19:26,26:12,32:a},{11:27,13:4,19:5,20:6,21:e,22:8,23:9,24:10,25:11,26:12,28:r,29:n,31:i,32:a,40:s,44:l,47:u},{41:[1,28],43:[1,29]},{45:[1,30]},{48:[1,31]},t(g,[2,29],{33:32,36:[1,33],38:[1,34]}),{1:[2,7]},t(h,[2,13]),{26:35,32:a},{32:[2,14]},{17:[1,36]},t(m,[2,24]),{11:37,13:4,14:22,15:d,16:p,19:5,20:6,21:e,22:8,23:9,24:10,25:11,26:12,28:r,29:n,31:i,32:a,40:s,44:l,47:u},{30:[1,38]},{42:[1,39]},{42:[1,40]},{46:[1,41]},{49:[1,42]},t(g,[2,30]),{18:[1,43]},{18:[1,44]},t(m,[2,23]),{18:[1,45]},{30:[1,46]},t(f,[2,28]),t(f,[2,35]),t(f,[2,36]),t(f,[2,37]),t(f,[2,38]),{37:[1,47]},{34:48,35:y},{15:[1,50]},t(f,[2,27]),t(g,[2,33]),{39:[1,51]},{34:52,35:y,39:[2,31]},{32:[2,15]},t(g,[2,34]),{39:[2,32]}],defaultActions:{20:[2,7],23:[2,14],50:[2,15],52:[2,32]},parseError:o(function(C,T){if(T.recoverable)this.trace(C);else{var E=new Error(C);throw E.hash=T,E}},"parseError"),parse:o(function(C){var T=this,E=[0],A=[],S=[null],_=[],I=this.table,D="",k=0,L=0,R=0,O=2,M=1,B=_.slice.call(arguments,1),F=Object.create(this.lexer),P={yy:{}};for(var z in this.yy)Object.prototype.hasOwnProperty.call(this.yy,z)&&(P.yy[z]=this.yy[z]);F.setInput(C,P.yy),P.yy.lexer=F,P.yy.parser=this,typeof F.yylloc>"u"&&(F.yylloc={});var $=F.yylloc;_.push($);var H=F.options&&F.options.ranges;typeof P.yy.parseError=="function"?this.parseError=P.yy.parseError:this.parseError=Object.getPrototypeOf(this).parseError;function Q(ce){E.length=E.length-2*ce,S.length=S.length-ce,_.length=_.length-ce}o(Q,"popStack");function j(){var ce;return ce=A.pop()||F.lex()||M,typeof ce!="number"&&(ce instanceof Array&&(A=ce,ce=A.pop()),ce=T.symbols_[ce]||ce),ce}o(j,"lex");for(var ie,ne,le,he,K,X,te={},J,se,ue,Z;;){if(le=E[E.length-1],this.defaultActions[le]?he=this.defaultActions[le]:((ie===null||typeof ie>"u")&&(ie=j()),he=I[le]&&I[le][ie]),typeof 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S=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:E?(E.length===A.length?this.yylloc.first_column:0)+A[A.length-E.length].length-E[0].length:this.yylloc.first_column-T},this.options.ranges&&(this.yylloc.range=[S[0],S[0]+this.yyleng-T]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). +`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(C){this.unput(this.match.slice(C))},"less"),pastInput:o(function(){var C=this.matched.substr(0,this.matched.length-this.match.length);return(C.length>20?"...":"")+C.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var C=this.match;return C.length<20&&(C+=this._input.substr(0,20-C.length)),(C.substr(0,20)+(C.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var C=this.pastInput(),T=new Array(C.length+1).join("-");return C+this.upcomingInput()+` +`+T+"^"},"showPosition"),test_match:o(function(C,T){var E,A,S;if(this.options.backtrack_lexer&&(S={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(S.yylloc.range=this.yylloc.range.slice(0))),A=C[0].match(/(?:\r\n?|\n).*/g),A&&(this.yylineno+=A.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:A?A[A.length-1].length-A[A.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+C[0].length},this.yytext+=C[0],this.match+=C[0],this.matches=C,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(C[0].length),this.matched+=C[0],E=this.performAction.call(this,this.yy,this,T,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),E)return E;if(this._backtrack){for(var _ in S)this[_]=S[_];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var C,T,E,A;this._more||(this.yytext="",this.match="");for(var S=this._currentRules(),_=0;_T[0].length)){if(T=E,A=_,this.options.backtrack_lexer){if(C=this.test_match(E,S[_]),C!==!1)return C;if(this._backtrack){T=!1;continue}else return!1}else if(!this.options.flex)break}return T?(C=this.test_match(T,S[A]),C!==!1?C:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. +`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var T=this.next();return T||this.lex()},"lex"),begin:o(function(T){this.conditionStack.push(T)},"begin"),popState:o(function(){var T=this.conditionStack.length-1;return T>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(T){return T=this.conditionStack.length-1-Math.abs(T||0),T>=0?this.conditionStack[T]:"INITIAL"},"topState"),pushState:o(function(T){this.begin(T)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{},performAction:o(function(T,E,A,S){var _=S;switch(A){case 0:return 10;case 1:return T.getLogger().debug("Found space-block"),31;break;case 2:return T.getLogger().debug("Found nl-block"),31;break;case 3:return T.getLogger().debug("Found space-block"),29;break;case 4:T.getLogger().debug(".",E.yytext);break;case 5:T.getLogger().debug("_",E.yytext);break;case 6:return 5;case 7:return E.yytext=-1,28;break;case 8:return E.yytext=E.yytext.replace(/columns\s+/,""),T.getLogger().debug("COLUMNS (LEX)",E.yytext),28;break;case 9:this.pushState("md_string");break;case 10:return"MD_STR";case 11:this.popState();break;case 12:this.pushState("string");break;case 13:T.getLogger().debug("LEX: POPPING STR:",E.yytext),this.popState();break;case 14:return T.getLogger().debug("LEX: STR end:",E.yytext),"STR";break;case 15:return E.yytext=E.yytext.replace(/space\:/,""),T.getLogger().debug("SPACE NUM (LEX)",E.yytext),21;break;case 16:return E.yytext="1",T.getLogger().debug("COLUMNS (LEX)",E.yytext),21;break;case 17:return 43;case 18:return"LINKSTYLE";case 19:return"INTERPOLATE";case 20:return this.pushState("CLASSDEF"),40;break;case 21:return this.popState(),this.pushState("CLASSDEFID"),"DEFAULT_CLASSDEF_ID";break;case 22:return this.popState(),this.pushState("CLASSDEFID"),41;break;case 23:return this.popState(),42;break;case 24:return this.pushState("CLASS"),44;break;case 25:return this.popState(),this.pushState("CLASS_STYLE"),45;break;case 26:return this.popState(),46;break;case 27:return this.pushState("STYLE_STMNT"),47;break;case 28:return this.popState(),this.pushState("STYLE_DEFINITION"),48;break;case 29:return this.popState(),49;break;case 30:return this.pushState("acc_title"),"acc_title";break;case 31:return this.popState(),"acc_title_value";break;case 32:return this.pushState("acc_descr"),"acc_descr";break;case 33:return this.popState(),"acc_descr_value";break;case 34:this.pushState("acc_descr_multiline");break;case 35:this.popState();break;case 36:return"acc_descr_multiline_value";case 37:return 30;case 38:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 39:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 40:return this.popState(),T.getLogger().debug("Lex: ))"),"NODE_DEND";break;case 41:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 42:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 43:return this.popState(),T.getLogger().debug("Lex: (-"),"NODE_DEND";break;case 44:return this.popState(),T.getLogger().debug("Lex: -)"),"NODE_DEND";break;case 45:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 46:return this.popState(),T.getLogger().debug("Lex: ]]"),"NODE_DEND";break;case 47:return this.popState(),T.getLogger().debug("Lex: ("),"NODE_DEND";break;case 48:return this.popState(),T.getLogger().debug("Lex: ])"),"NODE_DEND";break;case 49:return this.popState(),T.getLogger().debug("Lex: /]"),"NODE_DEND";break;case 50:return this.popState(),T.getLogger().debug("Lex: /]"),"NODE_DEND";break;case 51:return this.popState(),T.getLogger().debug("Lex: )]"),"NODE_DEND";break;case 52:return this.popState(),T.getLogger().debug("Lex: )"),"NODE_DEND";break;case 53:return this.popState(),T.getLogger().debug("Lex: ]>"),"NODE_DEND";break;case 54:return this.popState(),T.getLogger().debug("Lex: ]"),"NODE_DEND";break;case 55:return T.getLogger().debug("Lexa: -)"),this.pushState("NODE"),36;break;case 56:return T.getLogger().debug("Lexa: (-"),this.pushState("NODE"),36;break;case 57:return T.getLogger().debug("Lexa: ))"),this.pushState("NODE"),36;break;case 58:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 59:return T.getLogger().debug("Lex: ((("),this.pushState("NODE"),36;break;case 60:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 61:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 62:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 63:return T.getLogger().debug("Lexc: >"),this.pushState("NODE"),36;break;case 64:return T.getLogger().debug("Lexa: (["),this.pushState("NODE"),36;break;case 65:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 66:return this.pushState("NODE"),36;break;case 67:return this.pushState("NODE"),36;break;case 68:return this.pushState("NODE"),36;break;case 69:return this.pushState("NODE"),36;break;case 70:return this.pushState("NODE"),36;break;case 71:return this.pushState("NODE"),36;break;case 72:return this.pushState("NODE"),36;break;case 73:return T.getLogger().debug("Lexa: ["),this.pushState("NODE"),36;break;case 74:return this.pushState("BLOCK_ARROW"),T.getLogger().debug("LEX ARR START"),38;break;case 75:return T.getLogger().debug("Lex: NODE_ID",E.yytext),32;break;case 76:return T.getLogger().debug("Lex: EOF",E.yytext),8;break;case 77:this.pushState("md_string");break;case 78:this.pushState("md_string");break;case 79:return"NODE_DESCR";case 80:this.popState();break;case 81:T.getLogger().debug("Lex: Starting string"),this.pushState("string");break;case 82:T.getLogger().debug("LEX ARR: Starting string"),this.pushState("string");break;case 83:return T.getLogger().debug("LEX: NODE_DESCR:",E.yytext),"NODE_DESCR";break;case 84:T.getLogger().debug("LEX POPPING"),this.popState();break;case 85:T.getLogger().debug("Lex: =>BAE"),this.pushState("ARROW_DIR");break;case 86:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (right): dir:",E.yytext),"DIR";break;case 87:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (left):",E.yytext),"DIR";break;case 88:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (x):",E.yytext),"DIR";break;case 89:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (y):",E.yytext),"DIR";break;case 90:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (up):",E.yytext),"DIR";break;case 91:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex 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g=this.child.getNodes(),y=0;yp?(this.rect.x-=(this.labelWidth-p)/2,this.setWidth(this.labelWidth)):this.labelPosHorizontal=="right"&&this.setWidth(p+this.labelWidth)),this.labelHeight&&(this.labelPosVertical=="top"?(this.rect.y-=this.labelHeight,this.setHeight(m+this.labelHeight)):this.labelPosVertical=="center"&&this.labelHeight>m?(this.rect.y-=(this.labelHeight-m)/2,this.setHeight(this.labelHeight)):this.labelPosVertical=="bottom"&&this.setHeight(m+this.labelHeight))}}},h.prototype.getInclusionTreeDepth=function(){if(this.inclusionTreeDepth==i.MAX_VALUE)throw"assert failed";return this.inclusionTreeDepth},h.prototype.transform=function(d){var p=this.rect.x;p>s.WORLD_BOUNDARY?p=s.WORLD_BOUNDARY:p<-s.WORLD_BOUNDARY&&(p=-s.WORLD_BOUNDARY);var m=this.rect.y;m>s.WORLD_BOUNDARY?m=s.WORLD_BOUNDARY:m<-s.WORLD_BOUNDARY&&(m=-s.WORLD_BOUNDARY);var g=new u(p,m),y=d.inverseTransformPoint(g);this.setLocation(y.x,y.y)},h.prototype.getLeft=function(){return this.rect.x},h.prototype.getRight=function(){return this.rect.x+this.rect.width},h.prototype.getTop=function(){return this.rect.y},h.prototype.getBottom=function(){return this.rect.y+this.rect.height},h.prototype.getParent=function(){return this.owner==null?null:this.owner.getParent()},t.exports=h},function(t,e,r){"use strict";var n=r(0);function i(){}o(i,"FDLayoutConstants");for(var a in n)i[a]=n[a];i.MAX_ITERATIONS=2500,i.DEFAULT_EDGE_LENGTH=50,i.DEFAULT_SPRING_STRENGTH=.45,i.DEFAULT_REPULSION_STRENGTH=4500,i.DEFAULT_GRAVITY_STRENGTH=.4,i.DEFAULT_COMPOUND_GRAVITY_STRENGTH=1,i.DEFAULT_GRAVITY_RANGE_FACTOR=3.8,i.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR=1.5,i.DEFAULT_USE_SMART_IDEAL_EDGE_LENGTH_CALCULATION=!0,i.DEFAULT_USE_SMART_REPULSION_RANGE_CALCULATION=!0,i.DEFAULT_COOLING_FACTOR_INCREMENTAL=.3,i.COOLING_ADAPTATION_FACTOR=.33,i.ADAPTATION_LOWER_NODE_LIMIT=1e3,i.ADAPTATION_UPPER_NODE_LIMIT=5e3,i.MAX_NODE_DISPLACEMENT_INCREMENTAL=100,i.MAX_NODE_DISPLACEMENT=i.MAX_NODE_DISPLACEMENT_INCREMENTAL*3,i.MIN_REPULSION_DIST=i.DEFAULT_EDGE_LENGTH/10,i.CONVERGENCE_CHECK_PERIOD=100,i.PER_LEVEL_IDEAL_EDGE_LENGTH_FACTOR=.1,i.MIN_EDGE_LENGTH=1,i.GRID_CALCULATION_CHECK_PERIOD=10,t.exports=i},function(t,e,r){"use strict";function n(i,a){i==null&&a==null?(this.x=0,this.y=0):(this.x=i,this.y=a)}o(n,"PointD"),n.prototype.getX=function(){return this.x},n.prototype.getY=function(){return this.y},n.prototype.setX=function(i){this.x=i},n.prototype.setY=function(i){this.y=i},n.prototype.getDifference=function(i){return new DimensionD(this.x-i.x,this.y-i.y)},n.prototype.getCopy=function(){return new n(this.x,this.y)},n.prototype.translate=function(i){return this.x+=i.width,this.y+=i.height,this},t.exports=n},function(t,e,r){"use strict";var n=r(2),i=r(10),a=r(0),s=r(7),l=r(3),u=r(1),h=r(13),f=r(12),d=r(11);function p(g,y,v){n.call(this,v),this.estimatedSize=i.MIN_VALUE,this.margin=a.DEFAULT_GRAPH_MARGIN,this.edges=[],this.nodes=[],this.isConnected=!1,this.parent=g,y!=null&&y instanceof s?this.graphManager=y:y!=null&&y instanceof Layout&&(this.graphManager=y.graphManager)}o(p,"LGraph"),p.prototype=Object.create(n.prototype);for(var m in n)p[m]=n[m];p.prototype.getNodes=function(){return this.nodes},p.prototype.getEdges=function(){return this.edges},p.prototype.getGraphManager=function(){return this.graphManager},p.prototype.getParent=function(){return this.parent},p.prototype.getLeft=function(){return this.left},p.prototype.getRight=function(){return this.right},p.prototype.getTop=function(){return this.top},p.prototype.getBottom=function(){return this.bottom},p.prototype.isConnected=function(){return this.isConnected},p.prototype.add=function(g,y,v){if(y==null&&v==null){var x=g;if(this.graphManager==null)throw"Graph has no graph mgr!";if(this.getNodes().indexOf(x)>-1)throw"Node already in graph!";return x.owner=this,this.getNodes().push(x),x}else{var b=g;if(!(this.getNodes().indexOf(y)>-1&&this.getNodes().indexOf(v)>-1))throw"Source or target not in graph!";if(!(y.owner==v.owner&&y.owner==this))throw"Both owners must be this graph!";return y.owner!=v.owner?null:(b.source=y,b.target=v,b.isInterGraph=!1,this.getEdges().push(b),y.edges.push(b),v!=y&&v.edges.push(b),b)}},p.prototype.remove=function(g){var y=g;if(g instanceof l){if(y==null)throw"Node is null!";if(!(y.owner!=null&&y.owner==this))throw"Owner graph is invalid!";if(this.graphManager==null)throw"Owner graph manager is invalid!";for(var v=y.edges.slice(),x,b=v.length,w=0;w-1&&E>-1))throw"Source and/or target doesn't know this edge!";x.source.edges.splice(T,1),x.target!=x.source&&x.target.edges.splice(E,1);var C=x.source.owner.getEdges().indexOf(x);if(C==-1)throw"Not in owner's edge list!";x.source.owner.getEdges().splice(C,1)}},p.prototype.updateLeftTop=function(){for(var g=i.MAX_VALUE,y=i.MAX_VALUE,v,x,b,w=this.getNodes(),C=w.length,T=0;Tv&&(g=v),y>x&&(y=x)}return g==i.MAX_VALUE?null:(w[0].getParent().paddingLeft!=null?b=w[0].getParent().paddingLeft:b=this.margin,this.left=y-b,this.top=g-b,new f(this.left,this.top))},p.prototype.updateBounds=function(g){for(var y=i.MAX_VALUE,v=-i.MAX_VALUE,x=i.MAX_VALUE,b=-i.MAX_VALUE,w,C,T,E,A,S=this.nodes,_=S.length,I=0;I<_;I++){var D=S[I];g&&D.child!=null&&D.updateBounds(),w=D.getLeft(),C=D.getRight(),T=D.getTop(),E=D.getBottom(),y>w&&(y=w),vT&&(x=T),bw&&(y=w),vT&&(x=T),b=this.nodes.length){var _=0;v.forEach(function(I){I.owner==g&&_++}),_==this.nodes.length&&(this.isConnected=!0)}},t.exports=p},function(t,e,r){"use strict";var n,i=r(1);function a(s){n=r(6),this.layout=s,this.graphs=[],this.edges=[]}o(a,"LGraphManager"),a.prototype.addRoot=function(){var s=this.layout.newGraph(),l=this.layout.newNode(null),u=this.add(s,l);return this.setRootGraph(u),this.rootGraph},a.prototype.add=function(s,l,u,h,f){if(u==null&&h==null&&f==null){if(s==null)throw"Graph is null!";if(l==null)throw"Parent node is null!";if(this.graphs.indexOf(s)>-1)throw"Graph already in this graph mgr!";if(this.graphs.push(s),s.parent!=null)throw"Already has a parent!";if(l.child!=null)throw"Already has a child!";return s.parent=l,l.child=s,s}else{f=u,h=l,u=s;var d=h.getOwner(),p=f.getOwner();if(!(d!=null&&d.getGraphManager()==this))throw"Source not in this graph mgr!";if(!(p!=null&&p.getGraphManager()==this))throw"Target not in this graph mgr!";if(d==p)return u.isInterGraph=!1,d.add(u,h,f);if(u.isInterGraph=!0,u.source=h,u.target=f,this.edges.indexOf(u)>-1)throw"Edge already in inter-graph edge list!";if(this.edges.push(u),!(u.source!=null&&u.target!=null))throw"Edge source and/or target is null!";if(!(u.source.edges.indexOf(u)==-1&&u.target.edges.indexOf(u)==-1))throw"Edge already in source and/or target incidency list!";return u.source.edges.push(u),u.target.edges.push(u),u}},a.prototype.remove=function(s){if(s instanceof n){var l=s;if(l.getGraphManager()!=this)throw"Graph not in this graph mgr";if(!(l==this.rootGraph||l.parent!=null&&l.parent.graphManager==this))throw"Invalid parent node!";var u=[];u=u.concat(l.getEdges());for(var h,f=u.length,d=0;d=s.getRight()?l[0]+=Math.min(s.getX()-a.getX(),a.getRight()-s.getRight()):s.getX()<=a.getX()&&s.getRight()>=a.getRight()&&(l[0]+=Math.min(a.getX()-s.getX(),s.getRight()-a.getRight())),a.getY()<=s.getY()&&a.getBottom()>=s.getBottom()?l[1]+=Math.min(s.getY()-a.getY(),a.getBottom()-s.getBottom()):s.getY()<=a.getY()&&s.getBottom()>=a.getBottom()&&(l[1]+=Math.min(a.getY()-s.getY(),s.getBottom()-a.getBottom()));var f=Math.abs((s.getCenterY()-a.getCenterY())/(s.getCenterX()-a.getCenterX()));s.getCenterY()===a.getCenterY()&&s.getCenterX()===a.getCenterX()&&(f=1);var d=f*l[0],p=l[1]/f;l[0]d)return l[0]=u,l[1]=m,l[2]=f,l[3]=S,!1;if(hf)return l[0]=p,l[1]=h,l[2]=E,l[3]=d,!1;if(uf?(l[0]=y,l[1]=v,k=!0):(l[0]=g,l[1]=m,k=!0):R===M&&(u>f?(l[0]=p,l[1]=m,k=!0):(l[0]=x,l[1]=v,k=!0)),-O===M?f>u?(l[2]=A,l[3]=S,L=!0):(l[2]=E,l[3]=T,L=!0):O===M&&(f>u?(l[2]=C,l[3]=T,L=!0):(l[2]=_,l[3]=S,L=!0)),k&&L)return!1;if(u>f?h>d?(B=this.getCardinalDirection(R,M,4),F=this.getCardinalDirection(O,M,2)):(B=this.getCardinalDirection(-R,M,3),F=this.getCardinalDirection(-O,M,1)):h>d?(B=this.getCardinalDirection(-R,M,1),F=this.getCardinalDirection(-O,M,3)):(B=this.getCardinalDirection(R,M,2),F=this.getCardinalDirection(O,M,4)),!k)switch(B){case 1:z=m,P=u+-w/M,l[0]=P,l[1]=z;break;case 2:P=x,z=h+b*M,l[0]=P,l[1]=z;break;case 3:z=v,P=u+w/M,l[0]=P,l[1]=z;break;case 4:P=y,z=h+-b*M,l[0]=P,l[1]=z;break}if(!L)switch(F){case 1:H=T,$=f+-D/M,l[2]=$,l[3]=H;break;case 2:$=_,H=d+I*M,l[2]=$,l[3]=H;break;case 3:H=S,$=f+D/M,l[2]=$,l[3]=H;break;case 4:$=A,H=d+-I*M,l[2]=$,l[3]=H;break}}return!1},i.getCardinalDirection=function(a,s,l){return a>s?l:1+l%4},i.getIntersection=function(a,s,l,u){if(u==null)return this.getIntersection2(a,s,l);var h=a.x,f=a.y,d=s.x,p=s.y,m=l.x,g=l.y,y=u.x,v=u.y,x=void 0,b=void 0,w=void 0,C=void 0,T=void 0,E=void 0,A=void 0,S=void 0,_=void 0;return w=p-f,T=h-d,A=d*f-h*p,C=v-g,E=m-y,S=y*g-m*v,_=w*E-C*T,_===0?null:(x=(T*S-E*A)/_,b=(C*A-w*S)/_,new n(x,b))},i.angleOfVector=function(a,s,l,u){var h=void 0;return a!==l?(h=Math.atan((u-s)/(l-a)),l=0){var v=(-m+Math.sqrt(m*m-4*p*g))/(2*p),x=(-m-Math.sqrt(m*m-4*p*g))/(2*p),b=null;return v>=0&&v<=1?[v]:x>=0&&x<=1?[x]:b}else return null},i.HALF_PI=.5*Math.PI,i.ONE_AND_HALF_PI=1.5*Math.PI,i.TWO_PI=2*Math.PI,i.THREE_PI=3*Math.PI,t.exports=i},function(t,e,r){"use strict";function n(){}o(n,"IMath"),n.sign=function(i){return i>0?1:i<0?-1:0},n.floor=function(i){return i<0?Math.ceil(i):Math.floor(i)},n.ceil=function(i){return i<0?Math.floor(i):Math.ceil(i)},t.exports=n},function(t,e,r){"use strict";function n(){}o(n,"Integer"),n.MAX_VALUE=2147483647,n.MIN_VALUE=-2147483648,t.exports=n},function(t,e,r){"use strict";var n=function(){function h(f,d){for(var p=0;p"u"?"undefined":n(a);return a==null||s!="object"&&s!="function"},t.exports=i},function(t,e,r){"use strict";function n(m){if(Array.isArray(m)){for(var g=0,y=Array(m.length);g0&&g;){for(w.push(T[0]);w.length>0&&g;){var E=w[0];w.splice(0,1),b.add(E);for(var A=E.getEdges(),x=0;x-1&&T.splice(D,1)}b=new Set,C=new Map}}return m},p.prototype.createDummyNodesForBendpoints=function(m){for(var g=[],y=m.source,v=this.graphManager.calcLowestCommonAncestor(m.source,m.target),x=0;x0){for(var v=this.edgeToDummyNodes.get(y),x=0;x=0&&g.splice(S,1);var _=C.getNeighborsList();_.forEach(function(k){if(y.indexOf(k)<0){var L=v.get(k),R=L-1;R==1&&E.push(k),v.set(k,R)}})}y=y.concat(E),(g.length==1||g.length==2)&&(x=!0,b=g[0])}return b},p.prototype.setGraphManager=function(m){this.graphManager=m},t.exports=p},function(t,e,r){"use strict";function n(){}o(n,"RandomSeed"),n.seed=1,n.x=0,n.nextDouble=function(){return n.x=Math.sin(n.seed++)*1e4,n.x-Math.floor(n.x)},t.exports=n},function(t,e,r){"use strict";var n=r(5);function i(a,s){this.lworldOrgX=0,this.lworldOrgY=0,this.ldeviceOrgX=0,this.ldeviceOrgY=0,this.lworldExtX=1,this.lworldExtY=1,this.ldeviceExtX=1,this.ldeviceExtY=1}o(i,"Transform"),i.prototype.getWorldOrgX=function(){return this.lworldOrgX},i.prototype.setWorldOrgX=function(a){this.lworldOrgX=a},i.prototype.getWorldOrgY=function(){return this.lworldOrgY},i.prototype.setWorldOrgY=function(a){this.lworldOrgY=a},i.prototype.getWorldExtX=function(){return this.lworldExtX},i.prototype.setWorldExtX=function(a){this.lworldExtX=a},i.prototype.getWorldExtY=function(){return this.lworldExtY},i.prototype.setWorldExtY=function(a){this.lworldExtY=a},i.prototype.getDeviceOrgX=function(){return this.ldeviceOrgX},i.prototype.setDeviceOrgX=function(a){this.ldeviceOrgX=a},i.prototype.getDeviceOrgY=function(){return this.ldeviceOrgY},i.prototype.setDeviceOrgY=function(a){this.ldeviceOrgY=a},i.prototype.getDeviceExtX=function(){return this.ldeviceExtX},i.prototype.setDeviceExtX=function(a){this.ldeviceExtX=a},i.prototype.getDeviceExtY=function(){return this.ldeviceExtY},i.prototype.setDeviceExtY=function(a){this.ldeviceExtY=a},i.prototype.transformX=function(a){var s=0,l=this.lworldExtX;return l!=0&&(s=this.ldeviceOrgX+(a-this.lworldOrgX)*this.ldeviceExtX/l),s},i.prototype.transformY=function(a){var s=0,l=this.lworldExtY;return l!=0&&(s=this.ldeviceOrgY+(a-this.lworldOrgY)*this.ldeviceExtY/l),s},i.prototype.inverseTransformX=function(a){var s=0,l=this.ldeviceExtX;return l!=0&&(s=this.lworldOrgX+(a-this.ldeviceOrgX)*this.lworldExtX/l),s},i.prototype.inverseTransformY=function(a){var s=0,l=this.ldeviceExtY;return l!=0&&(s=this.lworldOrgY+(a-this.ldeviceOrgY)*this.lworldExtY/l),s},i.prototype.inverseTransformPoint=function(a){var s=new n(this.inverseTransformX(a.x),this.inverseTransformY(a.y));return s},t.exports=i},function(t,e,r){"use strict";function n(d){if(Array.isArray(d)){for(var p=0,m=Array(d.length);pa.ADAPTATION_LOWER_NODE_LIMIT&&(this.coolingFactor=Math.max(this.coolingFactor*a.COOLING_ADAPTATION_FACTOR,this.coolingFactor-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*this.coolingFactor*(1-a.COOLING_ADAPTATION_FACTOR))),this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT_INCREMENTAL):(d>a.ADAPTATION_LOWER_NODE_LIMIT?this.coolingFactor=Math.max(a.COOLING_ADAPTATION_FACTOR,1-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*(1-a.COOLING_ADAPTATION_FACTOR)):this.coolingFactor=1,this.initialCoolingFactor=this.coolingFactor,this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT),this.maxIterations=Math.max(this.getAllNodes().length*5,this.maxIterations),this.displacementThresholdPerNode=3*a.DEFAULT_EDGE_LENGTH/100,this.totalDisplacementThreshold=this.displacementThresholdPerNode*this.getAllNodes().length,this.repulsionRange=this.calcRepulsionRange()},h.prototype.calcSpringForces=function(){for(var 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n(){}o(n,"SVD"),n.svd=function(i){this.U=null,this.V=null,this.s=null,this.m=0,this.n=0,this.m=i.length,this.n=i[0].length;var a=Math.min(this.m,this.n);this.s=function(xt){for(var ut=[];xt-- >0;)ut.push(0);return ut}(Math.min(this.m+1,this.n)),this.U=function(xt){var ut=o(function Et(ft){if(ft.length==0)return 0;for(var yt=[],nt=0;nt0;)ut.push(0);return ut}(this.n),l=function(xt){for(var ut=[];xt-- >0;)ut.push(0);return ut}(this.m),u=!0,h=!0,f=Math.min(this.m-1,this.n),d=Math.max(0,Math.min(this.n-2,this.m)),p=0;p=0;M--)if(this.s[M]!==0){for(var B=M+1;B=0;j--){if(function(xt,ut){return xt&&ut}(j0;){var ue=void 0,Z=void 0;for(ue=L-2;ue>=-1&&ue!==-1;ue--)if(Math.abs(s[ue])<=se+J*(Math.abs(this.s[ue])+Math.abs(this.s[ue+1]))){s[ue]=0;break}if(ue===L-2)Z=4;else{var Se=void 0;for(Se=L-1;Se>=ue&&Se!==ue;Se--){var ce=(Se!==L?Math.abs(s[Se]):0)+(Se!==ue+1?Math.abs(s[Se-1]):0);if(Math.abs(this.s[Se])<=se+J*ce){this.s[Se]=0;break}}Se===ue?Z=3:Se===L-1?Z=1:(Z=2,ue=Se)}switch(ue++,Z){case 1:{var ae=s[L-2];s[L-2]=0;for(var Oe=L-2;Oe>=ue;Oe--){var ge=n.hypot(this.s[Oe],ae),ze=this.s[Oe]/ge,He=ae/ge;if(this.s[Oe]=ge,Oe!==ue&&(ae=-He*s[Oe-1],s[Oe-1]=ze*s[Oe-1]),h)for(var $e=0;$e=this.s[ue+1]);){var ot=this.s[ue];if(this.s[ue]=this.s[ue+1],this.s[ue+1]=ot,h&&ueMath.abs(a)?(s=a/i,s=Math.abs(i)*Math.sqrt(1+s*s)):a!=0?(s=i/a,s=Math.abs(a)*Math.sqrt(1+s*s)):s=0,s},t.exports=n},function(t,e,r){"use strict";var n=function(){function s(l,u){for(var h=0;h2&&arguments[2]!==void 0?arguments[2]:1,f=arguments.length>3&&arguments[3]!==void 0?arguments[3]:-1,d=arguments.length>4&&arguments[4]!==void 0?arguments[4]:-1;i(this,s),this.sequence1=l,this.sequence2=u,this.match_score=h,this.mismatch_penalty=f,this.gap_penalty=d,this.iMax=l.length+1,this.jMax=u.length+1,this.grid=new Array(this.iMax);for(var p=0;p=0;l--){var u=this.listeners[l];u.event===a&&u.callback===s&&this.listeners.splice(l,1)}},i.emit=function(a,s){for(var l=0;l{"use strict";o(function(e,r){typeof k4=="object"&&typeof pF=="object"?pF.exports=r(dF()):typeof define=="function"&&define.amd?define(["layout-base"],r):typeof k4=="object"?k4.coseBase=r(dF()):e.coseBase=r(e.layoutBase)},"webpackUniversalModuleDefinition")(k4,function(t){return(()=>{"use strict";var e={45:(a,s,l)=>{var u={};u.layoutBase=l(551),u.CoSEConstants=l(806),u.CoSEEdge=l(767),u.CoSEGraph=l(880),u.CoSEGraphManager=l(578),u.CoSELayout=l(765),u.CoSENode=l(991),u.ConstraintHandler=l(902),a.exports=u},806:(a,s,l)=>{var u=l(551).FDLayoutConstants;function h(){}o(h,"CoSEConstants");for(var f in u)h[f]=u[f];h.DEFAULT_USE_MULTI_LEVEL_SCALING=!1,h.DEFAULT_RADIAL_SEPARATION=u.DEFAULT_EDGE_LENGTH,h.DEFAULT_COMPONENT_SEPERATION=60,h.TILE=!0,h.TILING_PADDING_VERTICAL=10,h.TILING_PADDING_HORIZONTAL=10,h.TRANSFORM_ON_CONSTRAINT_HANDLING=!0,h.ENFORCE_CONSTRAINTS=!0,h.APPLY_LAYOUT=!0,h.RELAX_MOVEMENT_ON_CONSTRAINTS=!0,h.TREE_REDUCTION_ON_INCREMENTAL=!0,h.PURE_INCREMENTAL=h.DEFAULT_INCREMENTAL,a.exports=h},767:(a,s,l)=>{var u=l(551).FDLayoutEdge;function h(d,p,m){u.call(this,d,p,m)}o(h,"CoSEEdge"),h.prototype=Object.create(u.prototype);for(var f in u)h[f]=u[f];a.exports=h},880:(a,s,l)=>{var u=l(551).LGraph;function h(d,p,m){u.call(this,d,p,m)}o(h,"CoSEGraph"),h.prototype=Object.create(u.prototype);for(var f in u)h[f]=u[f];a.exports=h},578:(a,s,l)=>{var u=l(551).LGraphManager;function h(d){u.call(this,d)}o(h,"CoSEGraphManager"),h.prototype=Object.create(u.prototype);for(var f in u)h[f]=u[f];a.exports=h},765:(a,s,l)=>{var u=l(551).FDLayout,h=l(578),f=l(880),d=l(991),p=l(767),m=l(806),g=l(902),y=l(551).FDLayoutConstants,v=l(551).LayoutConstants,x=l(551).Point,b=l(551).PointD,w=l(551).DimensionD,C=l(551).Layout,T=l(551).Integer,E=l(551).IGeometry,A=l(551).LGraph,S=l(551).Transform,_=l(551).LinkedList;function I(){u.call(this),this.toBeTiled={},this.constraints={}}o(I,"CoSELayout"),I.prototype=Object.create(u.prototype);for(var D in u)I[D]=u[D];I.prototype.newGraphManager=function(){var k=new h(this);return this.graphManager=k,k},I.prototype.newGraph=function(k){return new f(null,this.graphManager,k)},I.prototype.newNode=function(k){return new d(this.graphManager,k)},I.prototype.newEdge=function(k){return new p(null,null,k)},I.prototype.initParameters=function(){u.prototype.initParameters.call(this,arguments),this.isSubLayout||(m.DEFAULT_EDGE_LENGTH<10?this.idealEdgeLength=10:this.idealEdgeLength=m.DEFAULT_EDGE_LENGTH,this.useSmartIdealEdgeLengthCalculation=m.DEFAULT_USE_SMART_IDEAL_EDGE_LENGTH_CALCULATION,this.gravityConstant=y.DEFAULT_GRAVITY_STRENGTH,this.compoundGravityConstant=y.DEFAULT_COMPOUND_GRAVITY_STRENGTH,this.gravityRangeFactor=y.DEFAULT_GRAVITY_RANGE_FACTOR,this.compoundGravityRangeFactor=y.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR,this.prunedNodesAll=[],this.growTreeIterations=0,this.afterGrowthIterations=0,this.isTreeGrowing=!1,this.isGrowthFinished=!1)},I.prototype.initSpringEmbedder=function(){u.prototype.initSpringEmbedder.call(this),this.coolingCycle=0,this.maxCoolingCycle=this.maxIterations/y.CONVERGENCE_CHECK_PERIOD,this.finalTemperature=.04,this.coolingAdjuster=1},I.prototype.layout=function(){var k=v.DEFAULT_CREATE_BENDS_AS_NEEDED;return k&&(this.createBendpoints(),this.graphManager.resetAllEdges()),this.level=0,this.classicLayout()},I.prototype.classicLayout=function(){if(this.nodesWithGravity=this.calculateNodesToApplyGravitationTo(),this.graphManager.setAllNodesToApplyGravitation(this.nodesWithGravity),this.calcNoOfChildrenForAllNodes(),this.graphManager.calcLowestCommonAncestors(),this.graphManager.calcInclusionTreeDepths(),this.graphManager.getRoot().calcEstimatedSize(),this.calcIdealEdgeLengths(),this.incremental){if(m.TREE_REDUCTION_ON_INCREMENTAL){this.reduceTrees(),this.graphManager.resetAllNodesToApplyGravitation();var L=new Set(this.getAllNodes()),R=this.nodesWithGravity.filter(function(B){return L.has(B)});this.graphManager.setAllNodesToApplyGravitation(R)}}else{var k=this.getFlatForest();if(k.length>0)this.positionNodesRadially(k);else{this.reduceTrees(),this.graphManager.resetAllNodesToApplyGravitation();var L=new Set(this.getAllNodes()),R=this.nodesWithGravity.filter(function(O){return L.has(O)});this.graphManager.setAllNodesToApplyGravitation(R),this.positionNodesRandomly()}}return Object.keys(this.constraints).length>0&&(g.handleConstraints(this),this.initConstraintVariables()),this.initSpringEmbedder(),m.APPLY_LAYOUT&&this.runSpringEmbedder(),!0},I.prototype.tick=function(){if(this.totalIterations++,this.totalIterations===this.maxIterations&&!this.isTreeGrowing&&!this.isGrowthFinished)if(this.prunedNodesAll.length>0)this.isTreeGrowing=!0;else return!0;if(this.totalIterations%y.CONVERGENCE_CHECK_PERIOD==0&&!this.isTreeGrowing&&!this.isGrowthFinished){if(this.isConverged())if(this.prunedNodesAll.length>0)this.isTreeGrowing=!0;else return!0;this.coolingCycle++,this.layoutQuality==0?this.coolingAdjuster=this.coolingCycle:this.layoutQuality==1&&(this.coolingAdjuster=this.coolingCycle/3),this.coolingFactor=Math.max(this.initialCoolingFactor-Math.pow(this.coolingCycle,Math.log(100*(this.initialCoolingFactor-this.finalTemperature))/Math.log(this.maxCoolingCycle))/100*this.coolingAdjuster,this.finalTemperature),this.animationPeriod=Math.ceil(this.initialAnimationPeriod*Math.sqrt(this.coolingFactor))}if(this.isTreeGrowing){if(this.growTreeIterations%10==0)if(this.prunedNodesAll.length>0){this.graphManager.updateBounds(),this.updateGrid(),this.growTree(this.prunedNodesAll),this.graphManager.resetAllNodesToApplyGravitation();var k=new Set(this.getAllNodes()),L=this.nodesWithGravity.filter(function(M){return k.has(M)});this.graphManager.setAllNodesToApplyGravitation(L),this.graphManager.updateBounds(),this.updateGrid(),m.PURE_INCREMENTAL?this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL/2:this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL}else this.isTreeGrowing=!1,this.isGrowthFinished=!0;this.growTreeIterations++}if(this.isGrowthFinished){if(this.isConverged())return!0;this.afterGrowthIterations%10==0&&(this.graphManager.updateBounds(),this.updateGrid()),m.PURE_INCREMENTAL?this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL/2*((100-this.afterGrowthIterations)/100):this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL*((100-this.afterGrowthIterations)/100),this.afterGrowthIterations++}var R=!this.isTreeGrowing&&!this.isGrowthFinished,O=this.growTreeIterations%10==1&&this.isTreeGrowing||this.afterGrowthIterations%10==1&&this.isGrowthFinished;return this.totalDisplacement=0,this.graphManager.updateBounds(),this.calcSpringForces(),this.calcRepulsionForces(R,O),this.calcGravitationalForces(),this.moveNodes(),this.animate(),!1},I.prototype.getPositionsData=function(){for(var k=this.graphManager.getAllNodes(),L={},R=0;R0&&this.updateDisplacements();for(var R=0;R0&&(O.fixedNodeWeight=B)}}if(this.constraints.relativePlacementConstraint){var F=new Map,P=new Map;if(this.dummyToNodeForVerticalAlignment=new Map,this.dummyToNodeForHorizontalAlignment=new Map,this.fixedNodesOnHorizontal=new Set,this.fixedNodesOnVertical=new Set,this.fixedNodeSet.forEach(function(le){k.fixedNodesOnHorizontal.add(le),k.fixedNodesOnVertical.add(le)}),this.constraints.alignmentConstraint){if(this.constraints.alignmentConstraint.vertical)for(var z=this.constraints.alignmentConstraint.vertical,R=0;R=2*le.length/3;X--)he=Math.floor(Math.random()*(X+1)),K=le[X],le[X]=le[he],le[he]=K;return le},this.nodesInRelativeHorizontal=[],this.nodesInRelativeVertical=[],this.nodeToRelativeConstraintMapHorizontal=new Map,this.nodeToRelativeConstraintMapVertical=new Map,this.nodeToTempPositionMapHorizontal=new Map,this.nodeToTempPositionMapVertical=new Map,this.constraints.relativePlacementConstraint.forEach(function(le){if(le.left){var he=F.has(le.left)?F.get(le.left):le.left,K=F.has(le.right)?F.get(le.right):le.right;k.nodesInRelativeHorizontal.includes(he)||(k.nodesInRelativeHorizontal.push(he),k.nodeToRelativeConstraintMapHorizontal.set(he,[]),k.dummyToNodeForVerticalAlignment.has(he)?k.nodeToTempPositionMapHorizontal.set(he,k.idToNodeMap.get(k.dummyToNodeForVerticalAlignment.get(he)[0]).getCenterX()):k.nodeToTempPositionMapHorizontal.set(he,k.idToNodeMap.get(he).getCenterX())),k.nodesInRelativeHorizontal.includes(K)||(k.nodesInRelativeHorizontal.push(K),k.nodeToRelativeConstraintMapHorizontal.set(K,[]),k.dummyToNodeForVerticalAlignment.has(K)?k.nodeToTempPositionMapHorizontal.set(K,k.idToNodeMap.get(k.dummyToNodeForVerticalAlignment.get(K)[0]).getCenterX()):k.nodeToTempPositionMapHorizontal.set(K,k.idToNodeMap.get(K).getCenterX())),k.nodeToRelativeConstraintMapHorizontal.get(he).push({right:K,gap:le.gap}),k.nodeToRelativeConstraintMapHorizontal.get(K).push({left:he,gap:le.gap})}else{var X=P.has(le.top)?P.get(le.top):le.top,te=P.has(le.bottom)?P.get(le.bottom):le.bottom;k.nodesInRelativeVertical.includes(X)||(k.nodesInRelativeVertical.push(X),k.nodeToRelativeConstraintMapVertical.set(X,[]),k.dummyToNodeForHorizontalAlignment.has(X)?k.nodeToTempPositionMapVertical.set(X,k.idToNodeMap.get(k.dummyToNodeForHorizontalAlignment.get(X)[0]).getCenterY()):k.nodeToTempPositionMapVertical.set(X,k.idToNodeMap.get(X).getCenterY())),k.nodesInRelativeVertical.includes(te)||(k.nodesInRelativeVertical.push(te),k.nodeToRelativeConstraintMapVertical.set(te,[]),k.dummyToNodeForHorizontalAlignment.has(te)?k.nodeToTempPositionMapVertical.set(te,k.idToNodeMap.get(k.dummyToNodeForHorizontalAlignment.get(te)[0]).getCenterY()):k.nodeToTempPositionMapVertical.set(te,k.idToNodeMap.get(te).getCenterY())),k.nodeToRelativeConstraintMapVertical.get(X).push({bottom:te,gap:le.gap}),k.nodeToRelativeConstraintMapVertical.get(te).push({top:X,gap:le.gap})}});else{var H=new Map,Q=new Map;this.constraints.relativePlacementConstraint.forEach(function(le){if(le.left){var he=F.has(le.left)?F.get(le.left):le.left,K=F.has(le.right)?F.get(le.right):le.right;H.has(he)?H.get(he).push(K):H.set(he,[K]),H.has(K)?H.get(K).push(he):H.set(K,[he])}else{var X=P.has(le.top)?P.get(le.top):le.top,te=P.has(le.bottom)?P.get(le.bottom):le.bottom;Q.has(X)?Q.get(X).push(te):Q.set(X,[te]),Q.has(te)?Q.get(te).push(X):Q.set(te,[X])}});var j=o(function(he,K){var X=[],te=[],J=new _,se=new Set,ue=0;return he.forEach(function(Z,Se){if(!se.has(Se)){X[ue]=[],te[ue]=!1;var ce=Se;for(J.push(ce),se.add(ce),X[ue].push(ce);J.length!=0;){ce=J.shift(),K.has(ce)&&(te[ue]=!0);var ae=he.get(ce);ae.forEach(function(Oe){se.has(Oe)||(J.push(Oe),se.add(Oe),X[ue].push(Oe))})}ue++}}),{components:X,isFixed:te}},"constructComponents"),ie=j(H,k.fixedNodesOnHorizontal);this.componentsOnHorizontal=ie.components,this.fixedComponentsOnHorizontal=ie.isFixed;var ne=j(Q,k.fixedNodesOnVertical);this.componentsOnVertical=ne.components,this.fixedComponentsOnVertical=ne.isFixed}}},I.prototype.updateDisplacements=function(){var k=this;if(this.constraints.fixedNodeConstraint&&this.constraints.fixedNodeConstraint.forEach(function(ne){var le=k.idToNodeMap.get(ne.nodeId);le.displacementX=0,le.displacementY=0}),this.constraints.alignmentConstraint){if(this.constraints.alignmentConstraint.vertical)for(var L=this.constraints.alignmentConstraint.vertical,R=0;R1){var P;for(P=0;PO&&(O=Math.floor(F.y)),B=Math.floor(F.x+m.DEFAULT_COMPONENT_SEPERATION)}this.transform(new b(v.WORLD_CENTER_X-F.x/2,v.WORLD_CENTER_Y-F.y/2))},I.radialLayout=function(k,L,R){var O=Math.max(this.maxDiagonalInTree(k),m.DEFAULT_RADIAL_SEPARATION);I.branchRadialLayout(L,null,0,359,0,O);var M=A.calculateBounds(k),B=new S;B.setDeviceOrgX(M.getMinX()),B.setDeviceOrgY(M.getMinY()),B.setWorldOrgX(R.x),B.setWorldOrgY(R.y);for(var F=0;F1;){var X=K[0];K.splice(0,1);var te=j.indexOf(X);te>=0&&j.splice(te,1),le--,ie--}L!=null?he=(j.indexOf(K[0])+1)%le:he=0;for(var J=Math.abs(O-R)/ie,se=he;ne!=ie;se=++se%le){var ue=j[se].getOtherEnd(k);if(ue!=L){var Z=(R+ne*J)%360,Se=(Z+J)%360;I.branchRadialLayout(ue,k,Z,Se,M+B,B),ne++}}},I.maxDiagonalInTree=function(k){for(var L=T.MIN_VALUE,R=0;RL&&(L=M)}return L},I.prototype.calcRepulsionRange=function(){return 2*(this.level+1)*this.idealEdgeLength},I.prototype.groupZeroDegreeMembers=function(){var k=this,L={};this.memberGroups={},this.idToDummyNode={};for(var R=[],O=this.graphManager.getAllNodes(),M=0;M"u"&&(L[P]=[]),L[P]=L[P].concat(B)}Object.keys(L).forEach(function(z){if(L[z].length>1){var $="DummyCompound_"+z;k.memberGroups[$]=L[z];var H=L[z][0].getParent(),Q=new d(k.graphManager);Q.id=$,Q.paddingLeft=H.paddingLeft||0,Q.paddingRight=H.paddingRight||0,Q.paddingBottom=H.paddingBottom||0,Q.paddingTop=H.paddingTop||0,k.idToDummyNode[$]=Q;var j=k.getGraphManager().add(k.newGraph(),Q),ie=H.getChild();ie.add(Q);for(var ne=0;neM?(O.rect.x-=(O.labelWidth-M)/2,O.setWidth(O.labelWidth),O.labelMarginLeft=(O.labelWidth-M)/2):O.labelPosHorizontal=="right"&&O.setWidth(M+O.labelWidth)),O.labelHeight&&(O.labelPosVertical=="top"?(O.rect.y-=O.labelHeight,O.setHeight(B+O.labelHeight),O.labelMarginTop=O.labelHeight):O.labelPosVertical=="center"&&O.labelHeight>B?(O.rect.y-=(O.labelHeight-B)/2,O.setHeight(O.labelHeight),O.labelMarginTop=(O.labelHeight-B)/2):O.labelPosVertical=="bottom"&&O.setHeight(B+O.labelHeight))}})},I.prototype.repopulateCompounds=function(){for(var k=this.compoundOrder.length-1;k>=0;k--){var L=this.compoundOrder[k],R=L.id,O=L.paddingLeft,M=L.paddingTop,B=L.labelMarginLeft,F=L.labelMarginTop;this.adjustLocations(this.tiledMemberPack[R],L.rect.x,L.rect.y,O,M,B,F)}},I.prototype.repopulateZeroDegreeMembers=function(){var k=this,L=this.tiledZeroDegreePack;Object.keys(L).forEach(function(R){var O=k.idToDummyNode[R],M=O.paddingLeft,B=O.paddingTop,F=O.labelMarginLeft,P=O.labelMarginTop;k.adjustLocations(L[R],O.rect.x,O.rect.y,M,B,F,P)})},I.prototype.getToBeTiled=function(k){var L=k.id;if(this.toBeTiled[L]!=null)return this.toBeTiled[L];var R=k.getChild();if(R==null)return this.toBeTiled[L]=!1,!1;for(var O=R.getNodes(),M=0;M0)return this.toBeTiled[L]=!1,!1;if(B.getChild()==null){this.toBeTiled[B.id]=!1;continue}if(!this.getToBeTiled(B))return this.toBeTiled[L]=!1,!1}return this.toBeTiled[L]=!0,!0},I.prototype.getNodeDegree=function(k){for(var L=k.id,R=k.getEdges(),O=0,M=0;MH&&(H=j.rect.height)}R+=H+k.verticalPadding}},I.prototype.tileCompoundMembers=function(k,L){var R=this;this.tiledMemberPack=[],Object.keys(k).forEach(function(O){var M=L[O];if(R.tiledMemberPack[O]=R.tileNodes(k[O],M.paddingLeft+M.paddingRight),M.rect.width=R.tiledMemberPack[O].width,M.rect.height=R.tiledMemberPack[O].height,M.setCenter(R.tiledMemberPack[O].centerX,R.tiledMemberPack[O].centerY),M.labelMarginLeft=0,M.labelMarginTop=0,m.NODE_DIMENSIONS_INCLUDE_LABELS){var B=M.rect.width,F=M.rect.height;M.labelWidth&&(M.labelPosHorizontal=="left"?(M.rect.x-=M.labelWidth,M.setWidth(B+M.labelWidth),M.labelMarginLeft=M.labelWidth):M.labelPosHorizontal=="center"&&M.labelWidth>B?(M.rect.x-=(M.labelWidth-B)/2,M.setWidth(M.labelWidth),M.labelMarginLeft=(M.labelWidth-B)/2):M.labelPosHorizontal=="right"&&M.setWidth(B+M.labelWidth)),M.labelHeight&&(M.labelPosVertical=="top"?(M.rect.y-=M.labelHeight,M.setHeight(F+M.labelHeight),M.labelMarginTop=M.labelHeight):M.labelPosVertical=="center"&&M.labelHeight>F?(M.rect.y-=(M.labelHeight-F)/2,M.setHeight(M.labelHeight),M.labelMarginTop=(M.labelHeight-F)/2):M.labelPosVertical=="bottom"&&M.setHeight(F+M.labelHeight))}})},I.prototype.tileNodes=function(k,L){var R=this.tileNodesByFavoringDim(k,L,!0),O=this.tileNodesByFavoringDim(k,L,!1),M=this.getOrgRatio(R),B=this.getOrgRatio(O),F;return BP&&(P=ne.getWidth())});var z=B/M,$=F/M,H=Math.pow(R-O,2)+4*(z+O)*($+R)*M,Q=(O-R+Math.sqrt(H))/(2*(z+O)),j;L?(j=Math.ceil(Q),j==Q&&j++):j=Math.floor(Q);var ie=j*(z+O)-O;return P>ie&&(ie=P),ie+=O*2,ie},I.prototype.tileNodesByFavoringDim=function(k,L,R){var O=m.TILING_PADDING_VERTICAL,M=m.TILING_PADDING_HORIZONTAL,B=m.TILING_COMPARE_BY,F={rows:[],rowWidth:[],rowHeight:[],width:0,height:L,verticalPadding:O,horizontalPadding:M,centerX:0,centerY:0};B&&(F.idealRowWidth=this.calcIdealRowWidth(k,R));var P=o(function(le){return le.rect.width*le.rect.height},"getNodeArea"),z=o(function(le,he){return P(he)-P(le)},"areaCompareFcn");k.sort(function(ne,le){var he=z;return F.idealRowWidth?(he=B,he(ne.id,le.id)):he(ne,le)});for(var $=0,H=0,Q=0;Q0&&(F+=k.horizontalPadding),k.rowWidth[R]=F,k.width0&&(P+=k.verticalPadding);var z=0;P>k.rowHeight[R]&&(z=k.rowHeight[R],k.rowHeight[R]=P,z=k.rowHeight[R]-z),k.height+=z,k.rows[R].push(L)},I.prototype.getShortestRowIndex=function(k){for(var L=-1,R=Number.MAX_VALUE,O=0;OR&&(L=O,R=k.rowWidth[O]);return L},I.prototype.canAddHorizontal=function(k,L,R){if(k.idealRowWidth){var O=k.rows.length-1,M=k.rowWidth[O];return M+L+k.horizontalPadding<=k.idealRowWidth}var B=this.getShortestRowIndex(k);if(B<0)return!0;var F=k.rowWidth[B];if(F+k.horizontalPadding+L<=k.width)return!0;var P=0;k.rowHeight[B]0&&(P=R+k.verticalPadding-k.rowHeight[B]);var z;k.width-F>=L+k.horizontalPadding?z=(k.height+P)/(F+L+k.horizontalPadding):z=(k.height+P)/k.width,P=R+k.verticalPadding;var $;return k.widthB&&L!=R){O.splice(-1,1),k.rows[R].push(M),k.rowWidth[L]=k.rowWidth[L]-B,k.rowWidth[R]=k.rowWidth[R]+B,k.width=k.rowWidth[instance.getLongestRowIndex(k)];for(var F=Number.MIN_VALUE,P=0;PF&&(F=O[P].height);L>0&&(F+=k.verticalPadding);var z=k.rowHeight[L]+k.rowHeight[R];k.rowHeight[L]=F,k.rowHeight[R]0)for(var ie=M;ie<=B;ie++)j[0]+=this.grid[ie][F-1].length+this.grid[ie][F].length-1;if(B0)for(var ie=F;ie<=P;ie++)j[3]+=this.grid[M-1][ie].length+this.grid[M][ie].length-1;for(var ne=T.MAX_VALUE,le,he,K=0;K{var u=l(551).FDLayoutNode,h=l(551).IMath;function f(p,m,g,y){u.call(this,p,m,g,y)}o(f,"CoSENode"),f.prototype=Object.create(u.prototype);for(var d in u)f[d]=u[d];f.prototype.calculateDisplacement=function(){var p=this.graphManager.getLayout();this.getChild()!=null&&this.fixedNodeWeight?(this.displacementX+=p.coolingFactor*(this.springForceX+this.repulsionForceX+this.gravitationForceX)/this.fixedNodeWeight,this.displacementY+=p.coolingFactor*(this.springForceY+this.repulsionForceY+this.gravitationForceY)/this.fixedNodeWeight):(this.displacementX+=p.coolingFactor*(this.springForceX+this.repulsionForceX+this.gravitationForceX)/this.noOfChildren,this.displacementY+=p.coolingFactor*(this.springForceY+this.repulsionForceY+this.gravitationForceY)/this.noOfChildren),Math.abs(this.displacementX)>p.coolingFactor*p.maxNodeDisplacement&&(this.displacementX=p.coolingFactor*p.maxNodeDisplacement*h.sign(this.displacementX)),Math.abs(this.displacementY)>p.coolingFactor*p.maxNodeDisplacement&&(this.displacementY=p.coolingFactor*p.maxNodeDisplacement*h.sign(this.displacementY)),this.child&&this.child.getNodes().length>0&&this.propogateDisplacementToChildren(this.displacementX,this.displacementY)},f.prototype.propogateDisplacementToChildren=function(p,m){for(var g=this.getChild().getNodes(),y,v=0;v{function u(g){if(Array.isArray(g)){for(var y=0,v=Array(g.length);y0){var ct=0;Ue.forEach(function(ot){xe=="horizontal"?(we.set(ot,x.has(ot)?b[x.get(ot)]:pe.get(ot)),ct+=we.get(ot)):(we.set(ot,x.has(ot)?w[x.get(ot)]:pe.get(ot)),ct+=we.get(ot))}),ct=ct/Ue.length,st.forEach(function(ot){q.has(ot)||we.set(ot,ct)})}else{var We=0;st.forEach(function(ot){xe=="horizontal"?We+=x.has(ot)?b[x.get(ot)]:pe.get(ot):We+=x.has(ot)?w[x.get(ot)]:pe.get(ot)}),We=We/st.length,st.forEach(function(ot){we.set(ot,We)})}});for(var qe=o(function(){var Ue=De.shift(),ct=V.get(Ue);ct.forEach(function(We){if(we.get(We.id)ot&&(ot=yt),ntYt&&(Yt=nt)}}catch(At){Mt=!0,xt=At}finally{try{!bt&&ut.return&&ut.return()}finally{if(Mt)throw xt}}var dn=(ct+ot)/2-(We+Yt)/2,Tt=!0,On=!1,tn=void 0;try{for(var _r=st[Symbol.iterator](),Dr;!(Tt=(Dr=_r.next()).done);Tt=!0){var Pn=Dr.value;we.set(Pn,we.get(Pn)+dn)}}catch(At){On=!0,tn=At}finally{try{!Tt&&_r.return&&_r.return()}finally{if(On)throw tn}}})}return we},"findAppropriatePositionForRelativePlacement"),D=o(function(V){var xe=0,q=0,pe=0,ve=0;if(V.forEach(function(Ve){Ve.left?b[x.get(Ve.left)]-b[x.get(Ve.right)]>=0?xe++:q++:w[x.get(Ve.top)]-w[x.get(Ve.bottom)]>=0?pe++:ve++}),xe>q&&pe>ve)for(var Pe=0;Peq)for(var _e=0;_eve)for(var we=0;we1)y.fixedNodeConstraint.forEach(function(oe,V){O[V]=[oe.position.x,oe.position.y],M[V]=[b[x.get(oe.nodeId)],w[x.get(oe.nodeId)]]}),B=!0;else if(y.alignmentConstraint)(function(){var oe=0;if(y.alignmentConstraint.vertical){for(var V=y.alignmentConstraint.vertical,xe=o(function(we){var Ve=new Set;V[we].forEach(function(at){Ve.add(at)});var De=new Set([].concat(u(Ve)).filter(function(at){return P.has(at)})),qe=void 0;De.size>0?qe=b[x.get(De.values().next().value)]:qe=_(Ve).x,V[we].forEach(function(at){O[oe]=[qe,w[x.get(at)]],M[oe]=[b[x.get(at)],w[x.get(at)]],oe++})},"_loop2"),q=0;q0?qe=b[x.get(De.values().next().value)]:qe=_(Ve).y,pe[we].forEach(function(at){O[oe]=[b[x.get(at)],qe],M[oe]=[b[x.get(at)],w[x.get(at)]],oe++})},"_loop3"),Pe=0;PeQ&&(Q=H[ie].length,j=ie);if(Q<$.size/2)D(y.relativePlacementConstraint),B=!1,F=!1;else{var ne=new Map,le=new Map,he=[];H[j].forEach(function(oe){z.get(oe).forEach(function(V){V.direction=="horizontal"?(ne.has(oe)?ne.get(oe).push(V):ne.set(oe,[V]),ne.has(V.id)||ne.set(V.id,[]),he.push({left:oe,right:V.id})):(le.has(oe)?le.get(oe).push(V):le.set(oe,[V]),le.has(V.id)||le.set(V.id,[]),he.push({top:oe,bottom:V.id}))})}),D(he),F=!1;var K=I(ne,"horizontal"),X=I(le,"vertical");H[j].forEach(function(oe,V){M[V]=[b[x.get(oe)],w[x.get(oe)]],O[V]=[],K.has(oe)?O[V][0]=K.get(oe):O[V][0]=b[x.get(oe)],X.has(oe)?O[V][1]=X.get(oe):O[V][1]=w[x.get(oe)]}),B=!0}}if(B){for(var te=void 0,J=d.transpose(O),se=d.transpose(M),ue=0;ue0){var ze={x:0,y:0};y.fixedNodeConstraint.forEach(function(oe,V){var xe={x:b[x.get(oe.nodeId)],y:w[x.get(oe.nodeId)]},q=oe.position,pe=S(q,xe);ze.x+=pe.x,ze.y+=pe.y}),ze.x/=y.fixedNodeConstraint.length,ze.y/=y.fixedNodeConstraint.length,b.forEach(function(oe,V){b[V]+=ze.x}),w.forEach(function(oe,V){w[V]+=ze.y}),y.fixedNodeConstraint.forEach(function(oe){b[x.get(oe.nodeId)]=oe.position.x,w[x.get(oe.nodeId)]=oe.position.y})}if(y.alignmentConstraint){if(y.alignmentConstraint.vertical)for(var He=y.alignmentConstraint.vertical,$e=o(function(V){var xe=new Set;He[V].forEach(function(ve){xe.add(ve)});var q=new Set([].concat(u(xe)).filter(function(ve){return P.has(ve)})),pe=void 0;q.size>0?pe=b[x.get(q.values().next().value)]:pe=_(xe).x,xe.forEach(function(ve){P.has(ve)||(b[x.get(ve)]=pe)})},"_loop4"),Re=0;Re0?pe=w[x.get(q.values().next().value)]:pe=_(xe).y,xe.forEach(function(ve){P.has(ve)||(w[x.get(ve)]=pe)})},"_loop5"),W=0;W{a.exports=t}},r={};function n(a){var s=r[a];if(s!==void 0)return s.exports;var l=r[a]={exports:{}};return e[a](l,l.exports,n),l.exports}o(n,"__webpack_require__");var i=n(45);return i})()})});var Pve=Mi((E4,gF)=>{"use strict";o(function(e,r){typeof E4=="object"&&typeof gF=="object"?gF.exports=r(mF()):typeof define=="function"&&define.amd?define(["cose-base"],r):typeof E4=="object"?E4.cytoscapeFcose=r(mF()):e.cytoscapeFcose=r(e.coseBase)},"webpackUniversalModuleDefinition")(E4,function(t){return(()=>{"use strict";var e={658:a=>{a.exports=Object.assign!=null?Object.assign.bind(Object):function(s){for(var l=arguments.length,u=Array(l>1?l-1:0),h=1;h{var u=function(){function d(p,m){var g=[],y=!0,v=!1,x=void 0;try{for(var b=p[Symbol.iterator](),w;!(y=(w=b.next()).done)&&(g.push(w.value),!(m&&g.length===m));y=!0);}catch(C){v=!0,x=C}finally{try{!y&&b.return&&b.return()}finally{if(v)throw x}}return g}return o(d,"sliceIterator"),function(p,m){if(Array.isArray(p))return p;if(Symbol.iterator in Object(p))return d(p,m);throw new TypeError("Invalid attempt to destructure non-iterable instance")}}(),h=l(140).layoutBase.LinkedList,f={};f.getTopMostNodes=function(d){for(var p={},m=0;m0&&B.merge($)});for(var F=0;F1){w=x[0],C=w.connectedEdges().length,x.forEach(function(M){M.connectedEdges().length0&&g.set("dummy"+(g.size+1),A),S},f.relocateComponent=function(d,p,m){if(!m.fixedNodeConstraint){var g=Number.POSITIVE_INFINITY,y=Number.NEGATIVE_INFINITY,v=Number.POSITIVE_INFINITY,x=Number.NEGATIVE_INFINITY;if(m.quality=="draft"){var b=!0,w=!1,C=void 0;try{for(var T=p.nodeIndexes[Symbol.iterator](),E;!(b=(E=T.next()).done);b=!0){var A=E.value,S=u(A,2),_=S[0],I=S[1],D=m.cy.getElementById(_);if(D){var k=D.boundingBox(),L=p.xCoords[I]-k.w/2,R=p.xCoords[I]+k.w/2,O=p.yCoords[I]-k.h/2,M=p.yCoords[I]+k.h/2;Ly&&(y=R),Ox&&(x=M)}}}catch($){w=!0,C=$}finally{try{!b&&T.return&&T.return()}finally{if(w)throw C}}var B=d.x-(y+g)/2,F=d.y-(x+v)/2;p.xCoords=p.xCoords.map(function($){return $+B}),p.yCoords=p.yCoords.map(function($){return $+F})}else{Object.keys(p).forEach(function($){var H=p[$],Q=H.getRect().x,j=H.getRect().x+H.getRect().width,ie=H.getRect().y,ne=H.getRect().y+H.getRect().height;Qy&&(y=j),iex&&(x=ne)});var P=d.x-(y+g)/2,z=d.y-(x+v)/2;Object.keys(p).forEach(function($){var H=p[$];H.setCenter(H.getCenterX()+P,H.getCenterY()+z)})}}},f.calcBoundingBox=function(d,p,m,g){for(var y=Number.MAX_SAFE_INTEGER,v=Number.MIN_SAFE_INTEGER,x=Number.MAX_SAFE_INTEGER,b=Number.MIN_SAFE_INTEGER,w=void 0,C=void 0,T=void 0,E=void 0,A=d.descendants().not(":parent"),S=A.length,_=0;_w&&(y=w),vT&&(x=T),b{var u=l(548),h=l(140).CoSELayout,f=l(140).CoSENode,d=l(140).layoutBase.PointD,p=l(140).layoutBase.DimensionD,m=l(140).layoutBase.LayoutConstants,g=l(140).layoutBase.FDLayoutConstants,y=l(140).CoSEConstants,v=o(function(b,w){var C=b.cy,T=b.eles,E=T.nodes(),A=T.edges(),S=void 0,_=void 0,I=void 0,D={};b.randomize&&(S=w.nodeIndexes,_=w.xCoords,I=w.yCoords);var k=o(function($){return typeof $=="function"},"isFn"),L=o(function($,H){return k($)?$(H):$},"optFn"),R=u.calcParentsWithoutChildren(C,T),O=o(function z($,H,Q,j){for(var ie=H.length,ne=0;ne0){var J=void 0;J=Q.getGraphManager().add(Q.newGraph(),K),z(J,he,Q,j)}}},"processChildrenList"),M=o(function($,H,Q){for(var j=0,ie=0,ne=0;ne0?y.DEFAULT_EDGE_LENGTH=g.DEFAULT_EDGE_LENGTH=j/ie:k(b.idealEdgeLength)?y.DEFAULT_EDGE_LENGTH=g.DEFAULT_EDGE_LENGTH=50:y.DEFAULT_EDGE_LENGTH=g.DEFAULT_EDGE_LENGTH=b.idealEdgeLength,y.MIN_REPULSION_DIST=g.MIN_REPULSION_DIST=g.DEFAULT_EDGE_LENGTH/10,y.DEFAULT_RADIAL_SEPARATION=g.DEFAULT_EDGE_LENGTH)},"processEdges"),B=o(function($,H){H.fixedNodeConstraint&&($.constraints.fixedNodeConstraint=H.fixedNodeConstraint),H.alignmentConstraint&&($.constraints.alignmentConstraint=H.alignmentConstraint),H.relativePlacementConstraint&&($.constraints.relativePlacementConstraint=H.relativePlacementConstraint)},"processConstraints");b.nestingFactor!=null&&(y.PER_LEVEL_IDEAL_EDGE_LENGTH_FACTOR=g.PER_LEVEL_IDEAL_EDGE_LENGTH_FACTOR=b.nestingFactor),b.gravity!=null&&(y.DEFAULT_GRAVITY_STRENGTH=g.DEFAULT_GRAVITY_STRENGTH=b.gravity),b.numIter!=null&&(y.MAX_ITERATIONS=g.MAX_ITERATIONS=b.numIter),b.gravityRange!=null&&(y.DEFAULT_GRAVITY_RANGE_FACTOR=g.DEFAULT_GRAVITY_RANGE_FACTOR=b.gravityRange),b.gravityCompound!=null&&(y.DEFAULT_COMPOUND_GRAVITY_STRENGTH=g.DEFAULT_COMPOUND_GRAVITY_STRENGTH=b.gravityCompound),b.gravityRangeCompound!=null&&(y.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR=g.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR=b.gravityRangeCompound),b.initialEnergyOnIncremental!=null&&(y.DEFAULT_COOLING_FACTOR_INCREMENTAL=g.DEFAULT_COOLING_FACTOR_INCREMENTAL=b.initialEnergyOnIncremental),b.tilingCompareBy!=null&&(y.TILING_COMPARE_BY=b.tilingCompareBy),b.quality=="proof"?m.QUALITY=2:m.QUALITY=0,y.NODE_DIMENSIONS_INCLUDE_LABELS=g.NODE_DIMENSIONS_INCLUDE_LABELS=m.NODE_DIMENSIONS_INCLUDE_LABELS=b.nodeDimensionsIncludeLabels,y.DEFAULT_INCREMENTAL=g.DEFAULT_INCREMENTAL=m.DEFAULT_INCREMENTAL=!b.randomize,y.ANIMATE=g.ANIMATE=m.ANIMATE=b.animate,y.TILE=b.tile,y.TILING_PADDING_VERTICAL=typeof b.tilingPaddingVertical=="function"?b.tilingPaddingVertical.call():b.tilingPaddingVertical,y.TILING_PADDING_HORIZONTAL=typeof b.tilingPaddingHorizontal=="function"?b.tilingPaddingHorizontal.call():b.tilingPaddingHorizontal,y.DEFAULT_INCREMENTAL=g.DEFAULT_INCREMENTAL=m.DEFAULT_INCREMENTAL=!0,y.PURE_INCREMENTAL=!b.randomize,m.DEFAULT_UNIFORM_LEAF_NODE_SIZES=b.uniformNodeDimensions,b.step=="transformed"&&(y.TRANSFORM_ON_CONSTRAINT_HANDLING=!0,y.ENFORCE_CONSTRAINTS=!1,y.APPLY_LAYOUT=!1),b.step=="enforced"&&(y.TRANSFORM_ON_CONSTRAINT_HANDLING=!1,y.ENFORCE_CONSTRAINTS=!0,y.APPLY_LAYOUT=!1),b.step=="cose"&&(y.TRANSFORM_ON_CONSTRAINT_HANDLING=!1,y.ENFORCE_CONSTRAINTS=!1,y.APPLY_LAYOUT=!0),b.step=="all"&&(b.randomize?y.TRANSFORM_ON_CONSTRAINT_HANDLING=!0:y.TRANSFORM_ON_CONSTRAINT_HANDLING=!1,y.ENFORCE_CONSTRAINTS=!0,y.APPLY_LAYOUT=!0),b.fixedNodeConstraint||b.alignmentConstraint||b.relativePlacementConstraint?y.TREE_REDUCTION_ON_INCREMENTAL=!1:y.TREE_REDUCTION_ON_INCREMENTAL=!0;var F=new h,P=F.newGraphManager();return O(P.addRoot(),u.getTopMostNodes(E),F,b),M(F,P,A),B(F,b),F.runLayout(),D},"coseLayout");a.exports={coseLayout:v}},212:(a,s,l)=>{var u=function(){function b(w,C){for(var T=0;T0)if(M){var P=d.getTopMostNodes(T.eles.nodes());if(k=d.connectComponents(E,T.eles,P),k.forEach(function(ce){var ae=ce.boundingBox();L.push({x:ae.x1+ae.w/2,y:ae.y1+ae.h/2})}),T.randomize&&k.forEach(function(ce){T.eles=ce,S.push(m(T))}),T.quality=="default"||T.quality=="proof"){var z=E.collection();if(T.tile){var $=new Map,H=[],Q=[],j=0,ie={nodeIndexes:$,xCoords:H,yCoords:Q},ne=[];if(k.forEach(function(ce,ae){ce.edges().length==0&&(ce.nodes().forEach(function(Oe,ge){z.merge(ce.nodes()[ge]),Oe.isParent()||(ie.nodeIndexes.set(ce.nodes()[ge].id(),j++),ie.xCoords.push(ce.nodes()[0].position().x),ie.yCoords.push(ce.nodes()[0].position().y))}),ne.push(ae))}),z.length>1){var le=z.boundingBox();L.push({x:le.x1+le.w/2,y:le.y1+le.h/2}),k.push(z),S.push(ie);for(var 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D[ae][He.id()]&&ge.nodes.push({x:D[ae][He.id()].getLeft(),y:D[ae][He.id()].getTop(),width:D[ae][He.id()].getWidth(),height:D[ae][He.id()].getHeight()})}),ce.edges().forEach(function(He){var $e=He.source(),Re=He.target();if($e.css("display")!="none"&&Re.css("display")!="none")if(T.quality=="draft"){var Ie=Oe.get($e.id()),be=Oe.get(Re.id()),W=[],de=[];if($e.isParent()){var re=d.calcBoundingBox($e,S[ae].xCoords,S[ae].yCoords,Oe);W.push(re.topLeftX+re.width/2),W.push(re.topLeftY+re.height/2)}else W.push(S[ae].xCoords[Ie]),W.push(S[ae].yCoords[Ie]);if(Re.isParent()){var oe=d.calcBoundingBox(Re,S[ae].xCoords,S[ae].yCoords,Oe);de.push(oe.topLeftX+oe.width/2),de.push(oe.topLeftY+oe.height/2)}else de.push(S[ae].xCoords[be]),de.push(S[ae].yCoords[be]);ge.edges.push({startX:W[0],startY:W[1],endX:de[0],endY:de[1]})}else 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Check if previously processed */ +/*! + * Wait for document loaded before starting the execution + */ +/*! Bundled license information: + +dompurify/dist/purify.es.mjs: + (*! @license DOMPurify 3.2.4 | (c) Cure53 and other contributors | Released under the Apache license 2.0 and Mozilla Public License 2.0 | github.com/cure53/DOMPurify/blob/3.2.4/LICENSE *) + +js-yaml/dist/js-yaml.mjs: + (*! js-yaml 4.1.0 https://github.com/nodeca/js-yaml @license MIT *) + +lodash-es/lodash.js: + (** + * @license + * Lodash (Custom Build) + * Build: `lodash modularize exports="es" -o ./` + * Copyright OpenJS Foundation and other contributors + * Released under MIT license + * Based on Underscore.js 1.8.3 + * Copyright Jeremy Ashkenas, DocumentCloud and Investigative Reporters & Editors + *) + +cytoscape/dist/cytoscape.esm.mjs: + (*! + Embeddable Minimum Strictly-Compliant Promises/A+ 1.1.1 Thenable + Copyright (c) 2013-2014 Ralf S. Engelschall (http://engelschall.com) + Licensed under The MIT License (http://opensource.org/licenses/MIT) + *) + (*! + Event object based on jQuery events, MIT license + + https://jquery.org/license/ + https://tldrlegal.com/license/mit-license + https://github.com/jquery/jquery/blob/master/src/event.js + *) + (*! Bezier curve function generator. Copyright Gaetan Renaudeau. MIT License: http://en.wikipedia.org/wiki/MIT_License *) + (*! Runge-Kutta spring physics function generator. Adapted from Framer.js, copyright Koen Bok. MIT License: http://en.wikipedia.org/wiki/MIT_License *) +*/ +globalThis.mermaid = globalThis.__esbuild_esm_mermaid.default; diff --git a/docs/bb-note/src/SUMMARY.md b/docs/bb-note/src/SUMMARY.md index c1ce3e07..1d3dc767 100644 --- a/docs/bb-note/src/SUMMARY.md +++ b/docs/bb-note/src/SUMMARY.md @@ -33,7 +33,6 @@ - [agent](./workflow/steps/agent/README.md) - [compiler](./workflow/steps/compiler/README.md) - [doc-agent](./workflow/steps/doc-agent/README.md) - - [funcsim](./workflow/steps/funcsim/README.md) - [marshal](./workflow/steps/marshal/README.md) - [sardine](./workflow/steps/sardine/README.md) - [uvm](./workflow/steps/uvm/README.md) From a10a66625b62c726eba5458b6ffcd523162885ea Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Mon, 8 Dec 2025 14:24:19 +0800 Subject: [PATCH 003/238] Virtualizetion of the whole BallDomain (#17) --- .../scala/examples/toy/ToyBuckyBall.scala | 2 -- .../examples/toy/balldomain/BallDomain.scala | 12 ++++----- .../framework/balldomain/bbus/bbus.scala | 26 +++++++++---------- .../scala/framework/memdomain/MemDomain.scala | 24 +++++++++++------ 4 files changed, 34 insertions(+), 30 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index fb0bd3d9..97a8c3a5 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -125,8 +125,6 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) // ----------------------------------------------------------------------------- ballDomain.io.sramRead <> memDomain.io.ballDomain.sramRead ballDomain.io.sramWrite <> memDomain.io.ballDomain.sramWrite - ballDomain.io.accRead <> memDomain.io.ballDomain.accRead - ballDomain.io.accWrite <> memDomain.io.ballDomain.accWrite // --------------------------------------------------------------------------- // RoCC response and status signals diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 9c87492b..034ddc2b 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -11,9 +11,11 @@ import examples.toy.balldomain.rs.BallRSModule import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.GlobalRsIssue import framework.frontend.globalrs.GlobalRsComplete +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} // Ball Domain input/output interface class BallDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { + private val numBanks = b.sp_banks + b.acc_banks // Issue interface from global RS (single channel) val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) @@ -21,10 +23,10 @@ class BallDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bun val global_complete_o = Decoupled(new GlobalRsComplete) // Execution interface connected to Scratchpad - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val sramRead = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) + val sramWrite = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + // val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) + // val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) } // Ball Domain top level - uses new simplified BBus architecture @@ -67,8 +69,6 @@ class BallDomain(implicit b: CustomBuckyballConfig, p: Parameters) extends Modul //--------------------------------------------------------------------------- bbus.io.sramRead <> io.sramRead bbus.io.sramWrite <> io.sramWrite - bbus.io.accRead <> io.accRead - bbus.io.accWrite <> io.accWrite //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 8de5995c..db08c4fa 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -11,6 +11,7 @@ import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter import framework.switcher.{ToPhysicalLine, ToVirtualLine} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} class BBusConfigIO(numBalls: Int)extends Bundle { @@ -24,15 +25,15 @@ class BBusConfigIO(numBalls: Int)extends Bundle { class BBus(ballGenerators: Seq[() => BallRegist with Module]) (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val numBalls = ballGenerators.length - + private val numBanks = b.sp_banks + b.acc_banks val io = IO(new Bundle { val cmdReq = Vec(numBalls, Flipped(Decoupled(new BallRsIssue))) val cmdResp = Vec(numBalls, Decoupled(new BallRsComplete)) - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val sramRead = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) + val sramWrite = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + // val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) + // val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) }) // Instantiate all registered Balls @@ -76,7 +77,8 @@ class BBus(ballGenerators: Seq[() => BallRegist with Module]) // ----------------------------------------------------------------------------- val memoryrouter = Module(new MemRouter(numBalls)(b, p)) memoryrouter.io.bbusConfig_i <> cmdRouter.io.bbusConfig_o - + io.sramRead <> memoryrouter.io.sramRead_o + io.sramWrite <> memoryrouter.io.sramWrite_o // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- @@ -111,15 +113,11 @@ class BBus(ballGenerators: Seq[() => BallRegist with Module]) // ToPhysicalLine - per-ball conversion from virtual to physical line // ----------------------------------------------------------------------------- - val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) + // val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) + + // toPhysicalLines.io.sramRead_i <> memoryrouter.io.sramRead_o + // toPhysicalLines.io.sramWrite_i <> memoryrouter.io.sramWrite_o - toPhysicalLines.io.sramRead_i <> memoryrouter.io.sramRead_o - toPhysicalLines.io.sramWrite_i <> memoryrouter.io.sramWrite_o - - io.sramRead <> toPhysicalLines.io.sramRead_o - io.sramWrite <> toPhysicalLines.io.sramWrite_o - io.accRead <> toPhysicalLines.io.accRead_o - io.accWrite <> toPhysicalLines.io.accWrite_o override lazy val desiredName = "BBus" } \ No newline at end of file diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 4efc9b33..f0fe2731 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -15,8 +15,11 @@ import framework.memdomain.pmc.MemCyclePMC import freechips.rocketchip.tilelink.TLEdgeOut import freechips.rocketchip.rocket.TLBPTWIO import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} +import framework.switcher.{ToPhysicalLine, ToVirtualLine} class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOut) extends Module { + private val numBanks = b.sp_banks + b.acc_banks val io = IO(new Bundle { // Issue interface from global RS (single channel) val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) @@ -26,10 +29,8 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu // SRAM interface for interaction with Ball Domain val ballDomain = new Bundle { - val sramRead = Vec(b.sp_banks, new SramReadIO(b.spad_bank_entries, b.spad_w)) - val sramWrite = Vec(b.sp_banks, new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - val accRead = Vec(b.acc_banks, new SramReadIO(b.acc_bank_entries, b.acc_w)) - val accWrite = Vec(b.acc_banks, new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len)) + val sramRead = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) + val sramWrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) } // DMA interface @@ -124,11 +125,18 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu memStorer.io.sramRead <> memController.io.dma.sramRead memStorer.io.accRead <> memController.io.dma.accRead + + // ToPhysical interface // Ball Domain SRAM interface connected to MemController's Ball Domain interface - io.ballDomain.sramRead <> memController.io.ballDomain.sramRead - io.ballDomain.sramWrite <> memController.io.ballDomain.sramWrite - io.ballDomain.accRead <> memController.io.ballDomain.accRead - io.ballDomain.accWrite <> memController.io.ballDomain.accWrite + val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) + + toPhysicalLines.io.sramRead_i <> io.ballDomain.sramRead + toPhysicalLines.io.sramWrite_i <> io.ballDomain.sramWrite + + toPhysicalLines.io.sramRead_o <> memController.io.ballDomain.sramRead + toPhysicalLines.io.sramWrite_o <> memController.io.ballDomain.sramWrite + toPhysicalLines.io.accRead_o <> memController.io.ballDomain.accRead + toPhysicalLines.io.accWrite_o <> memController.io.ballDomain.accWrite // Completion signal connected to global RS io.global_complete_o <> memRs.io.complete_o From d3b81ab79615271a9304db845c382de802d8ee73 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 9 Dec 2025 19:22:17 +0800 Subject: [PATCH 004/238] [arch] feat: replace saturn with t1 --- .gitmodules | 3 + README.md | 8 +- .../scala/examples/toy/CustomConfigs.scala | 8 - .../main/scala/framework/gendomain/LICENSE | 33 -- .../framework/gendomain/backend/Backend.scala | 446 ------------------ .../gendomain/backend/ExecuteSequencer.scala | 360 -------------- .../gendomain/backend/IssueQueue.scala | 47 -- .../gendomain/backend/LoadSequencer.scala | 92 ---- .../gendomain/backend/PermuteSequencer.scala | 111 ----- .../gendomain/backend/PipeSequencer.scala | 74 --- .../gendomain/backend/RegisterFile.scala | 180 ------- .../gendomain/backend/StoreSequencer.scala | 98 ---- .../framework/gendomain/common/Bundles.scala | 265 ----------- .../gendomain/common/Compactor.scala | 73 --- .../framework/gendomain/common/Consts.scala | 157 ------ .../framework/gendomain/common/DCEQueue.scala | 83 ---- .../gendomain/common/Parameters.scala | 404 ---------------- .../gendomain/common/ReorderBuffer.scala | 62 --- .../gendomain/common/ShiftPacker.scala | 59 --- .../gendomain/exu/ExecutionUnit.scala | 173 ------- .../gendomain/exu/FunctionalUnit.scala | 84 ---- .../framework/gendomain/exu/MaskUnit.scala | 134 ------ .../framework/gendomain/exu/PermuteUnit.scala | 95 ---- .../framework/gendomain/exu/Rounding.scala | 21 - .../gendomain/exu/fp/ElementwiseFPU.scala | 326 ------------- .../framework/gendomain/exu/fp/FPComp.scala | 155 ------ .../framework/gendomain/exu/fp/FPConv.scala | 176 ------- .../framework/gendomain/exu/fp/FPDiv.scala | 370 --------------- .../gendomain/exu/fp/FPFMAPipe.scala | 205 -------- .../gendomain/exu/fp/SharedFPFMA.scala | 157 ------ .../gendomain/exu/fp/SharedFPMisc.scala | 222 --------- .../gendomain/exu/int/BitwisePipe.scala | 52 -- .../exu/int/ElementwiseMultiplyPipe.scala | 68 --- .../gendomain/exu/int/IntegerDivide.scala | 131 ----- .../gendomain/exu/int/IntegerPipe.scala | 386 --------------- .../exu/int/SegmentedMultiplyPipe.scala | 272 ----------- .../gendomain/exu/int/ShiftPipe.scala | 240 ---------- .../gendomain/frontend/Dispatch.scala | 129 ----- .../gendomain/frontend/EarlyDecode.scala | 56 --- .../gendomain/frontend/EarlyTrapCheck.scala | 235 --------- .../gendomain/frontend/HwachaLimiter.scala | 57 --- .../frontend/IterativeTrapCheck.scala | 270 ----------- .../framework/gendomain/insns/Base.scala | 56 --- .../framework/gendomain/insns/Control.scala | 96 ---- .../framework/gendomain/insns/Decode.scala | 46 -- .../gendomain/insns/Instructions.scala | 233 --------- .../framework/gendomain/mem/AddrGen.scala | 127 ----- .../gendomain/mem/LoadOrderBuffer.scala | 112 ----- .../gendomain/mem/LoadSegmenter.scala | 93 ---- .../scala/framework/gendomain/mem/Mem.scala | 402 ---------------- .../framework/gendomain/mem/SGAddrGen.scala | 140 ------ .../gendomain/mem/SGTLInterface.scala | 38 -- .../gendomain/mem/SegmentBuffer.scala | 235 --------- .../gendomain/mem/StoreSegmenter.scala | 85 ---- .../framework/gendomain/mem/TLInterface.scala | 87 ---- .../framework/gendomain/rocket/Configs.scala | 83 ---- .../framework/gendomain/rocket/Frontend.scala | 94 ---- .../gendomain/rocket/HellaInterface.scala | 94 ---- .../gendomain/rocket/Integration.scala | 119 ----- .../framework/gendomain/shuttle/Configs.scala | 49 -- .../gendomain/shuttle/Frontend.scala | 112 ----- .../gendomain/shuttle/Integration.scala | 77 --- .../scala/sims/verilator/TargetConfig.scala | 4 - arch/thirdparty/t1 | 1 + 64 files changed, 8 insertions(+), 8952 deletions(-) delete mode 100644 arch/src/main/scala/framework/gendomain/LICENSE delete mode 100644 arch/src/main/scala/framework/gendomain/backend/Backend.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/ExecuteSequencer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/IssueQueue.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/LoadSequencer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/PermuteSequencer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/PipeSequencer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/RegisterFile.scala delete mode 100644 arch/src/main/scala/framework/gendomain/backend/StoreSequencer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/Bundles.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/Compactor.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/Consts.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/DCEQueue.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/Parameters.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/ReorderBuffer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/common/ShiftPacker.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/ExecutionUnit.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/FunctionalUnit.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/MaskUnit.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/PermuteUnit.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/Rounding.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/ElementwiseFPU.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/FPComp.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/FPConv.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/FPDiv.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/FPFMAPipe.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/SharedFPFMA.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/fp/SharedFPMisc.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/int/BitwisePipe.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/int/ElementwiseMultiplyPipe.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/int/IntegerDivide.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/int/IntegerPipe.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/int/SegmentedMultiplyPipe.scala delete mode 100644 arch/src/main/scala/framework/gendomain/exu/int/ShiftPipe.scala delete mode 100644 arch/src/main/scala/framework/gendomain/frontend/Dispatch.scala delete mode 100644 arch/src/main/scala/framework/gendomain/frontend/EarlyDecode.scala delete mode 100644 arch/src/main/scala/framework/gendomain/frontend/EarlyTrapCheck.scala delete mode 100644 arch/src/main/scala/framework/gendomain/frontend/HwachaLimiter.scala delete mode 100644 arch/src/main/scala/framework/gendomain/frontend/IterativeTrapCheck.scala delete mode 100644 arch/src/main/scala/framework/gendomain/insns/Base.scala delete mode 100644 arch/src/main/scala/framework/gendomain/insns/Control.scala delete mode 100644 arch/src/main/scala/framework/gendomain/insns/Decode.scala delete mode 100644 arch/src/main/scala/framework/gendomain/insns/Instructions.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/AddrGen.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/LoadOrderBuffer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/LoadSegmenter.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/Mem.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/SGAddrGen.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/SGTLInterface.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/SegmentBuffer.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/StoreSegmenter.scala delete mode 100644 arch/src/main/scala/framework/gendomain/mem/TLInterface.scala delete mode 100644 arch/src/main/scala/framework/gendomain/rocket/Configs.scala delete mode 100644 arch/src/main/scala/framework/gendomain/rocket/Frontend.scala delete mode 100644 arch/src/main/scala/framework/gendomain/rocket/HellaInterface.scala delete mode 100644 arch/src/main/scala/framework/gendomain/rocket/Integration.scala delete mode 100644 arch/src/main/scala/framework/gendomain/shuttle/Configs.scala delete mode 100644 arch/src/main/scala/framework/gendomain/shuttle/Frontend.scala delete mode 100644 arch/src/main/scala/framework/gendomain/shuttle/Integration.scala create mode 160000 arch/thirdparty/t1 diff --git a/.gitmodules b/.gitmodules index c0478c59..2c0e5f58 100644 --- a/.gitmodules +++ b/.gitmodules @@ -22,3 +22,6 @@ [submodule "compiler"] path = compiler url = https://github.com/DangoSys/bb-compiler.git +[submodule "arch/thirdparty/t1"] + path = arch/thirdparty/t1 + url = https://github.com/DangoSys/t1.git diff --git a/README.md b/README.md index d422b8c9..1c4a850e 100644 --- a/README.md +++ b/README.md @@ -7,7 +7,7 @@ [![Ask DeepWiki](https://deepwiki.com/badge.svg)](https://deepwiki.com/DangoSys/buckyball) [![zread](https://img.shields.io/badge/Ask_Zread-_.svg?style=flat&color=00b0aa&labelColor=000000&logo=data%3Aimage%2Fsvg%2Bxml%3Bbase64%2CPHN2ZyB3aWR0aD0iMTYiIGhlaWdodD0iMTYiIHZpZXdCb3g9IjAgMCAxNiAxNiIgZmlsbD0ibm9uZSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIj4KPHBhdGggZD0iTTQuOTYxNTYgMS42MDAxSDIuMjQxNTZDMS44ODgxIDEuNjAwMSAxLjYwMTU2IDEuODg2NjQgMS42MDE1NiAyLjI0MDFWNC45NjAxQzEuNjAxNTYgNS4zMTM1NiAxLjg4ODEgNS42MDAxIDIuMjQxNTYgNS42MDAxSDQuOTYxNTZDNS4zMTUwMiA1LjYwMDEgNS42MDE1NiA1LjMxMzU2IDUuNjAxNTYgNC45NjAxVjIuMjQwMUM1LjYwMTU2IDEuODg2NjQgNS4zMTUwMiAxLjYwMDEgNC45NjE1NiAxLjYwMDFaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00Ljk2MTU2IDEwLjM5OTlIMi4yNDE1NkMxLjg4ODEgMTAuMzk5OSAxLjYwMTU2IDEwLjY4NjQgMS42MDE1NiAxMS4wMzk5VjEzLjc1OTlDMS42MDE1NiAxNC4xMTM0IDEuODg4MSAxNC4zOTk5IDIuMjQxNTYgMTQuMzk5OUg0Ljk2MTU2QzUuMzE1MDIgMTQuMzk5OSA1LjYwMTU2IDE0LjExMzQgNS42MDE1NiAxMy43NTk5VjExLjAzOTlDNS42MDE1NiAxMC42ODY0IDUuMzE1MDIgMTAuMzk5OSA0Ljk2MTU2IDEwLjM5OTlaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik0xMy43NTg0IDEuNjAwMUgxMS4wMzg0QzEwLjY4NSAxLjYwMDEgMTAuMzk4NCAxLjg4NjY0IDEwLjM5ODQgMi4yNDAxVjQuOTYwMUMxMC4zOTg0IDUuMzEzNTYgMTAuNjg1IDUuNjAwMSAxMS4wMzg0IDUuNjAwMUgxMy43NTg0QzE0LjExMTkgNS42MDAxIDE0LjM5ODQgNS4zMTM1NiAxNC4zOTg0IDQuOTYwMVYyLjI0MDFDMTQuMzk4NCAxLjg4NjY0IDE0LjExMTkgMS42MDAxIDEzLjc1ODQgMS42MDAxWiIgZmlsbD0iI2ZmZiIvPgo8cGF0aCBkPSJNNCAxMkwxMiA0TDQgMTJaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00IDEyTDEyIDQiIHN0cm9rZT0iI2ZmZiIgc3Ryb2tlLXdpZHRoPSIxLjUiIHN0cm9rZS1saW5lY2FwPSJyb3VuZCIvPgo8L3N2Zz4K&logoColor=ffffff)](https://zread.ai/DangoSys/buckyball) [![Document](https://github.com/DangoSys/buckyball/actions/workflows/doc.yml/badge.svg?branch=main)](https://dangosys.github.io/buckyball) -[![Buckyball CI](https://github.com/DangoSys/buckyball/actions/workflows/test.yml/badge.svg)](https://github.com/DangoSys/buckyball/actions/workflows/test.yml) +[![buckyball CI](https://github.com/DangoSys/buckyball/actions/workflows/test.yml/badge.svg)](https://github.com/DangoSys/buckyball/actions/workflows/test.yml) @@ -17,7 +17,7 @@ Buckyball is a scalable framework for Domain Specific Architecture, built on RIS ## Project Overview -The Buckyball framework provides a complete hardware design, simulation verification, and software development toolchain, supporting the full development process from RTL design to system-level verification. The framework adopts a modular design that supports flexible configuration and extension, suitable for various specialized computing scenarios. +The buckyball framework provides a complete hardware design, simulation verification, and software development toolchain, supporting the full development process from RTL design to system-level verification. The framework adopts a modular design that supports flexible configuration and extension, suitable for various specialized computing scenarios. ## Quick Start @@ -83,7 +83,7 @@ bbdev verilator --run '--jobs 16 --binary ctest_vecunit_matmul_ones_singlecore-b We support providing a streamlined version of buckyball installation, integrated as a generator within Chipyard. **Notice**: -- Buckyball-as-a-lib are maintained only for specific release versions. +- buckyball-as-a-lib are maintained only for specific release versions. > We do not provide support for this version as it is not a stable release. @@ -100,7 +100,7 @@ You can learn more from [DeepWiki](https://deepwiki.com/DangoSys/buckyball) and Join our discussion on [Slack](https://dangosys-buckyball.slack.com/) ## Contributors -Thank you for considering contributing to Buckyball! +Thank you for considering contributing to buckyball!     diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 878bc86a..8d636077 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -48,7 +48,6 @@ class BuckyballCustomConfig( // } // }) -import framework.gendomain.common.VectorParams class BuckyballToyConfig extends Config( new BuckyballCustomConfig ++ @@ -56,13 +55,6 @@ class BuckyballToyConfig extends Config( new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) -class BuckyballToyVectorConfig extends Config( - new BuckyballCustomConfig ++ - new framework.gendomain.rocket.WithRocketVectorUnit(64, 64, VectorParams.minParams) ++ - new framework.rocket.WithNBuckyballCores(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) - import freechips.rocketchip.subsystem.{InCluster, InSubsystem, SBUS, MBUS} import freechips.rocketchip.devices.tilelink.{BootROMParams, BootROMLocated} import constellation.channel._ diff --git a/arch/src/main/scala/framework/gendomain/LICENSE b/arch/src/main/scala/framework/gendomain/LICENSE deleted file mode 100644 index b81ee094..00000000 --- a/arch/src/main/scala/framework/gendomain/LICENSE +++ /dev/null @@ -1,33 +0,0 @@ -BSD 3-Clause License - -Copyright (c) 2024, The Regents of the University of California (Regents) -All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -The generic domain is built based on the Saturn, Berkeley's vector processor -design, which is available at https://github.com/ucb-bar/saturn-vectors. -Thanks for the great design! diff --git a/arch/src/main/scala/framework/gendomain/backend/Backend.scala b/arch/src/main/scala/framework/gendomain/backend/Backend.scala deleted file mode 100644 index bfafaaec..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/Backend.scala +++ /dev/null @@ -1,446 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.dataview._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import framework.gendomain.mem._ -import framework.gendomain.exu._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class VectorBackend(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val dis = Flipped(Decoupled(new VectorIssueInst)) - - val vmu = Flipped(new VectorMemDatapathIO) - - val busy = Output(Bool()) - - val index_access = new VectorIndexAccessIO - val mask_access = new VectorMaskAccessIO - - val scalar_resp = Decoupled(new ScalarWrite) - - val set_vxsat = Output(Bool()) - val set_fflags = Output(Valid(UInt(5.W))) - - val fp_req = Decoupled(new FPInput()) - val fp_resp = Flipped(Valid(new FPResult())) - - val vat_tail = Input(UInt(vParams.vatSz.W)) - val vat_head = Input(UInt(vParams.vatSz.W)) - - val vat_release = Output(Vec(nRelease, Valid(UInt(vParams.vatSz.W)))) - }) - - require(vLen >= 64) - require(xLen == 64) - require(vLen >= dLen) - require(vLen % dLen == 0) - - def vatOlder(i0: UInt, i1: UInt) = cqOlder(i0, i1, io.vat_tail) - - val vdq = Module(new DCEQueue(new VectorIssueInst, vParams.vdqEntries)) - vdq.io.enq <> io.dis - - val perm_buffer = Module(new Compactor(dLenB, dLenB, UInt(8.W), false)) - - val xissParams = vParams.issStructure.generate(vParams) - val all_supported_insns = xissParams.map(_.insns).flatten - - val vlissq = Module(new IssueQueue(vParams.vlissqEntries, 1)) - val vsissq = Module(new IssueQueue(vParams.vsissqEntries, 1)) - val vpissq = Module(new IssueQueue(vParams.vpissqEntries, 1)) - val vxissqs = xissParams.map(q => Module(new IssueQueue(q.depth, q.seqs.size)).suggestName(s"vxissq_${q.name}")) - - val vls = Module(new LoadSequencer) - val vss = Module(new StoreSequencer) - val vps = Module(new PermuteSequencer(xissParams.map(_.insns).flatten)) - val vxs = xissParams.map(q => q.seqs.map(s => - Module(new ExecuteSequencer(s.insns)).suggestName(s"vxs${s.name}") - )) - - val allSeqs = Seq(vls, vss, vps) ++ vxs.flatten - val allIssQs = Seq(vlissq, vsissq, vpissq) ++ vxissqs - - val vxus = xissParams.map(_.seqs.map(s => Module(new ExecutionUnit(s.fus)).suggestName(s"vxu${s.name}"))) - - - io.fp_req.valid := false.B - io.fp_req.bits := DontCare - vxus.foreach(_.foreach(_.io.shared_fp_req := DontCare)) - vxus.foreach(_.foreach(_.io.shared_fp_resp := DontCare)) - - val shared_fp_vxu = vxus.flatten.filter(_.hasSharedFPUnits) - require(shared_fp_vxu.size <= 1) - shared_fp_vxu.headOption.foreach { vxu => - io.fp_req <> vxu.io.shared_fp_req - vxu.io.shared_fp_resp <> io.fp_resp - } - - case class IssueGroup( - issq: IssueQueue, - seqs: Seq[PipeSequencer[_]]) - - - val issGroups = Seq( - IssueGroup(vlissq, Seq(vls)), - IssueGroup(vsissq, Seq(vss)), - IssueGroup(vpissq, Seq(vps)) - ) ++ (vxissqs.zip(vxs).map { case (q, seqs) => - IssueGroup(q, seqs) - }) - - vlissq.io.enq.bits.reduction := false.B - vlissq.io.enq.bits.wide_vd := false.B - vlissq.io.enq.bits.wide_vs2 := false.B - vlissq.io.enq.bits.writes_mask := false.B - vlissq.io.enq.bits.reads_vs1_mask := false.B - vlissq.io.enq.bits.reads_vs2_mask := false.B - vlissq.io.enq.bits.nf_log2 := log2_up(vdq.io.deq.bits.nf, 8) - vlissq.io.enq.bits.renv1 := false.B - vlissq.io.enq.bits.renv2 := false.B - vlissq.io.enq.bits.renvd := false.B - vlissq.io.enq.bits.renvm := !vdq.io.deq.bits.vm - vlissq.io.enq.bits.wvd := true.B - vlissq.io.enq.bits.scalar_to_vd0 := false.B - vlissq.io.enq.bits.rs1_is_rs2 := false.B - - vsissq.io.enq.bits.reduction := false.B - vsissq.io.enq.bits.wide_vd := false.B - vsissq.io.enq.bits.wide_vs2 := false.B - vsissq.io.enq.bits.writes_mask := false.B - vsissq.io.enq.bits.reads_vs1_mask := false.B - vsissq.io.enq.bits.reads_vs2_mask := false.B - vsissq.io.enq.bits.nf_log2 := log2_up(vdq.io.deq.bits.nf, 8) - vsissq.io.enq.bits.renv1 := false.B - vsissq.io.enq.bits.renv2 := false.B - vsissq.io.enq.bits.renvd := true.B - vsissq.io.enq.bits.renvm := !vdq.io.deq.bits.vm && vdq.io.deq.bits.mop === mopUnit - vsissq.io.enq.bits.wvd := false.B - vsissq.io.enq.bits.scalar_to_vd0 := false.B - vsissq.io.enq.bits.rs1_is_rs2 := false.B - - vpissq.io.enq.bits.reduction := false.B - vpissq.io.enq.bits.wide_vd := false.B - vpissq.io.enq.bits.wide_vs2 := false.B - vpissq.io.enq.bits.writes_mask := false.B - vpissq.io.enq.bits.reads_vs1_mask := false.B - vpissq.io.enq.bits.reads_vs2_mask := false.B - vpissq.io.enq.bits.nf_log2 := 0.U - vpissq.io.enq.bits.renv1 := false.B - vpissq.io.enq.bits.renv2 := vdq.io.deq.bits.mop(0) || !vdq.io.deq.bits.vmu - vpissq.io.enq.bits.renvd := true.B - vpissq.io.enq.bits.renvm := !vdq.io.deq.bits.vm && vdq.io.deq.bits.mop =/= mopUnit && vdq.io.deq.bits.vmu - vpissq.io.enq.bits.wvd := false.B - vpissq.io.enq.bits.scalar_to_vd0 := false.B - vpissq.io.enq.bits.rs1_is_rs2 := !vdq.io.deq.bits.vmu && (vdq.io.deq.bits.opif6 === OPIFunct6.rgather || (vdq.io.deq.bits.funct3 === OPIVV && vdq.io.deq.bits.opif6 === OPIFunct6.rgatherei16)) - - val xdis_ctrl = new VectorDecoder(vdq.io.deq.bits.funct3, vdq.io.deq.bits.funct6, vdq.io.deq.bits.rs1, vdq.io.deq.bits.rs2, all_supported_insns, - Seq(Reduction, Wide2VD, Wide2VS2, WritesAsMask, ReadsVS1AsMask, ReadsVS2AsMask, ReadsVS1, ReadsVS2, ReadsVD, - VMBitReadsVM, AlwaysReadsVM, WritesVD, WritesScalar, ScalarToVD0)) - vxissqs.foreach { vxissq => - vxissq.io.enq.bits.wide_vd := xdis_ctrl.bool(Wide2VD) - vxissq.io.enq.bits.wide_vs2 := xdis_ctrl.bool(Wide2VS2) - vxissq.io.enq.bits.writes_mask := xdis_ctrl.bool(WritesAsMask) - vxissq.io.enq.bits.reads_vs1_mask := xdis_ctrl.bool(ReadsVS1AsMask) - vxissq.io.enq.bits.reads_vs2_mask := xdis_ctrl.bool(ReadsVS2AsMask) - vxissq.io.enq.bits.nf_log2 := 0.U - vxissq.io.enq.bits.renv1 := xdis_ctrl.bool(ReadsVS1) - vxissq.io.enq.bits.renv2 := xdis_ctrl.bool(ReadsVS2) - vxissq.io.enq.bits.renvd := xdis_ctrl.bool(ReadsVD) - vxissq.io.enq.bits.renvm := (!vdq.io.deq.bits.vm && xdis_ctrl.bool(VMBitReadsVM)) || xdis_ctrl.bool(AlwaysReadsVM) - vxissq.io.enq.bits.wvd := !xdis_ctrl.bool(WritesScalar) - vxissq.io.enq.bits.scalar_to_vd0 := xdis_ctrl.bool(ScalarToVD0) - vxissq.io.enq.bits.reduction := xdis_ctrl.bool(Reduction) - vxissq.io.enq.bits.rs1_is_rs2 := false.B - } - - val issq_stall = Wire(Vec(issGroups.size, Bool())) - vdq.io.deq.ready := !issq_stall.orR - - for ((group, i) <- issGroups.zipWithIndex) { - val otherIssGroups = issGroups.zipWithIndex.filter(_._2 != i).map(_._1) - val otherIssqs = otherIssGroups.map(_.issq) - val otherIssqSeqs = otherIssGroups.map(_.seqs).flatten - - for ((seq, j) <- group.seqs.zipWithIndex) { - val otherSameIssqSeqs = group.seqs.zipWithIndex.filter(_._2 != j).map(_._1) - val otherSeqs = otherIssqSeqs ++ otherSameIssqSeqs - - val vat = seq.io.vat - - seq.io.rvs1 := DontCare - seq.io.rvs2 := DontCare - seq.io.rvd := DontCare - seq.io.rvm := DontCare - seq.io.perm := DontCare - seq.io.acc.valid := false.B - seq.io.acc.bits := DontCare - seq.io.vat_head := io.vat_head - - val older_issq_wintents = FillInterleaved(egsPerVReg, otherIssqs.map { i => - i.io.hazards.map(h => Mux(vatOlder(h.bits.vat, vat) && h.valid, h.bits.wintent, 0.U)) - }.flatten.foldLeft(0.U)(_|_)) - val older_seq_wintents = otherSeqs.map { s => - Mux(vatOlder(s.io.seq_hazard.bits.vat, vat) && s.io.seq_hazard.valid, s.io.seq_hazard.bits.wintent, 0.U) - }.reduce(_|_) - val older_wintents = older_issq_wintents | older_seq_wintents - - val older_issq_rintents = FillInterleaved(egsPerVReg, otherIssqs.map { i => - i.io.hazards.map(h => Mux(vatOlder(h.bits.vat, vat) && h.valid, h.bits.rintent, 0.U)) - }.flatten.foldLeft(0.U)(_|_)) - val older_seq_rintents = otherSeqs.map { s => - Mux(vatOlder(s.io.seq_hazard.bits.vat, vat) && s.io.seq_hazard.valid, s.io.seq_hazard.bits.rintent, 0.U) - }.reduce(_|_) - val older_rintents = older_issq_rintents | older_seq_rintents - - val older_pipe_writes = vxus.flatten.map(_.io.pipe_hazards.toSeq).flatten.map { h => - Mux(h.valid, h.bits.eg_oh, 0.U) - }.reduce(_|_) - - val older_iter_writes = vxus.flatten.map(_.io.iter_hazards.toSeq).flatten.map { h => - Mux(h.valid, h.bits.eg_oh, 0.U) - }.reduce(_|_) - - seq.io.older_writes := older_pipe_writes | older_iter_writes | older_wintents - seq.io.older_reads := older_rintents - - if (!vParams.enableOOO) { - // stall dispatch if any other sequencers are at the head and stalled - seq.io.dis_stall := otherSeqs.map { s => - s.io.busy && s.io.head && !(s.io.iss.valid && s.io.iss.ready) - }.orR - } else { - seq.io.dis_stall := false.B // never stall dispatch - } - } - - val accepts = group.seqs.map(_.accepts(vdq.io.deq.bits)) - issq_stall(i) := !group.issq.io.enq.ready && accepts.orR - - group.issq.io.enq.valid := vdq.io.deq.valid && !issq_stall.orR && accepts.orR - group.issq.io.enq.bits.viewAsSupertype(new VectorIssueInst) := vdq.io.deq.bits - group.issq.io.enq.bits.seq := VecInit(accepts).asUInt - - // In case of multiple available sequencers, select the first ready one - val valid_seqs = group.issq.io.deq.bits.seq - val ready_seqs = VecInit(group.seqs.map(_.io.dis.ready)).asUInt - val chosen_seq = PriorityEncoder(valid_seqs & ready_seqs) - - group.seqs.zipWithIndex.foreach{ case(s, j) => - s.io.dis.valid := group.issq.io.deq.valid && chosen_seq === j.U - s.io.dis.bits := group.issq.io.deq.bits.viewAsSupertype(new BackendIssueInst) - } - group.issq.io.deq.ready := (valid_seqs & ready_seqs) =/= 0.U - } - - val flat_vxs = vxs.flatten - val flat_vxus = vxus.flatten - require(flat_vxs.size == flat_vxus.size) - - // Hazard checking for multi-VXS - // Check if there is a VRF write port hazard against the in-flight insns in other VXUs - // Check if there is a VRF write port hazard against a simultaneously issuing insn - // from another VXS (check that it's actually a valid hazard) - val inflight_hazards = WireInit(VecInit(Seq.fill(flat_vxs.length)(false.B))) - for (i <- 0 until flat_vxs.length) { - val other_vxu_idx = (0 until flat_vxs.length).filter(_ != i) - - val inflight_hazard = other_vxu_idx.map(flat_vxus(_).io.pipe_hazards).flatten.map { hazard => - hazard.valid && - (hazard.bits.latency === flat_vxus(i).io.issue_pipe_latency) && - (hazard.bits.eg(vrfBankBits-1,0) === flat_vxs(i).io.iss.bits.wvd_eg(vrfBankBits-1,0)) - }.reduceOption(_ || _).getOrElse(false.B) - - inflight_hazards(i) := inflight_hazard - - val issue_hazard = other_vxu_idx.map { other_iss => - (flat_vxus(other_iss).io.issue_pipe_latency === flat_vxus(i).io.issue_pipe_latency) && - (flat_vxs(other_iss).io.iss.bits.wvd_eg(vrfBankBits-1,0) === flat_vxs(i).io.iss.bits.wvd_eg(vrfBankBits-1,0)) && - vatOlder(flat_vxs(other_iss).io.iss.bits.vat, flat_vxs(i).io.iss.bits.vat) && - !inflight_hazards(other_iss) && - flat_vxs(other_iss).io.iss.valid && - flat_vxus(other_iss).io.iss.ready - }.reduceOption(_ || _).getOrElse(false.B) - - flat_vxus(i).io.iss.valid := flat_vxs(i).io.iss.valid && !inflight_hazard && !issue_hazard - flat_vxs(i).io.iss.ready := flat_vxus(i).io.iss.ready && !inflight_hazard && !issue_hazard - flat_vxus(i).io.iss.bits := flat_vxs(i).io.iss.bits - flat_vxs(i).io.acc := flat_vxus(i).io.acc_write - } - - // Read ports are - // vxs0-vrs1, vxs1-vrs1, vmu-index, frontend-index - // vxs0-vrs2, vxs1-vrs2 - // vxs0-vrs3, vxs1-vrs3, vss-vrd - // vxs0-mask, vxs1-mask, vls-mask, vss-mask, vps-mask, frontend-mask - // Mask ports are - // vxs0-mask, vxs1-mask, vls-mask, vss-mask, vps-mask, frontend-mask - val vrf = Module(new RegisterFile( - reads = Seq(2 + flat_vxs.size, flat_vxs.size, 1 + flat_vxs.size), - maskReads = Seq(4 + flat_vxs.size), - pipeWrites = flat_vxus.size, - llWrites = flat_vxus.size + 2 // vxus + load + reset - )) - - val load_write = Wire(Decoupled(new VectorWrite(dLen))) - io.vmu.lresp.ready := vls.io.iss.valid && load_write.ready - vls.io.iss.ready := io.vmu.lresp.valid && load_write.ready - load_write.valid := vls.io.iss.valid && io.vmu.lresp.valid - load_write.bits.eg := vls.io.iss.bits.wvd_eg - load_write.bits.data := io.vmu.lresp.bits.data - load_write.bits.mask := FillInterleaved(8, vls.io.iss.bits.wmask) - when (io.vmu.lresp.fire) { - assert(io.vmu.lresp.bits.debug_id === vls.io.iss.bits.debug_id) - } - - val resetting = RegInit(true.B) - val reset_ctr = RegInit(0.U(log2Ceil(egsTotal).W)) - when (resetting) { - reset_ctr := reset_ctr + 1.U - io.dis.ready := false.B - } - when (~reset_ctr === 0.U) { resetting := false.B } - - // Write ports - vrf.io.pipe_writes.zip(vxus.flatten).foreach { case (w,vxu) => - w := vxu.io.pipe_write - } - - vrf.io.ll_writes(0) <> load_write - vrf.io.ll_writes(1).valid := resetting - vrf.io.ll_writes(1).bits.eg := reset_ctr - vrf.io.ll_writes(1).bits.data := 0.U - vrf.io.ll_writes(1).bits.mask := ~(0.U(dLen.W)) - vxus.flatten.zipWithIndex.foreach { case (vxu,i) => - vrf.io.ll_writes(2+i) <> vxu.io.iter_write - } - - flat_vxs.zipWithIndex.foreach { case(xs, i) => - vrf.io.read(0)(i) <> xs.io.rvs1 - vrf.io.read(1)(i) <> xs.io.rvs2 - vrf.io.read(2)(i) <> xs.io.rvd - vrf.io.mask_read(0)(i) <> xs.io.rvm - } - - vrf.io.read(0)(flat_vxs.length) <> vps.io.rvs2 - vps.io.rvs1.req.ready := true.B - - val index_access_eg = getEgId(io.index_access.vrs, io.index_access.eidx, io.index_access.eew, false.B) - val index_access_eg_oh = UIntToOH(index_access_eg) - val index_access_hazard = (allSeqs.map(_.io.seq_hazard).map { h => - h.valid && ((h.bits.wintent & index_access_eg_oh) =/= 0.U) - } ++ allIssQs.map(_.io.hazards).flatten.map { h => - h.valid && h.bits.wintent(io.index_access.vrs) - } ++ vxus.flatten.map(_.io.pipe_hazards).flatten.map { h => - h.valid && h.bits.eg === index_access_eg - } ++ vxus.flatten.map(_.io.iter_hazards).flatten.map { h => - h.valid && h.bits.eg === index_access_eg - }).orR || vdq.io.peek.map(i => i.valid && !(i.bits.vmu && i.bits.store)).orR - // TODO: this conservatively assumes a index data hazard against anything in the vdq - - vrf.io.read(0)(flat_vxs.size+1).req.valid := io.index_access.valid && !index_access_hazard - io.index_access.ready := vrf.io.read(0)(flat_vxs.size+1).req.ready && !index_access_hazard - vrf.io.read(0)(flat_vxs.size+1).req.bits.eg := index_access_eg - vrf.io.read(0)(flat_vxs.size+1).req.bits.oldest := false.B - io.index_access.idx := vrf.io.read(0)(flat_vxs.size+1).resp >> ((io.index_access.eidx << io.index_access.eew)(dLenOffBits-1,0) << 3) & eewBitMask(io.index_access.eew) - - vrf.io.read(2)(flat_vxs.size) <> vss.io.rvd - io.vmu.sdata.valid := vss.io.iss.valid - io.vmu.sdata.bits := vss.io.iss.bits - vss.io.iss.ready := io.vmu.sdata.ready - - vrf.io.mask_read(0)(flat_vxs.length) <> vls.io.rvm - vrf.io.mask_read(0)(flat_vxs.length+1) <> vss.io.rvm - vrf.io.mask_read(0)(flat_vxs.length+2) <> vps.io.rvm - val vm_busy = Wire(Bool()) - vrf.io.mask_read(0)(flat_vxs.length+3).req.valid := io.mask_access.valid && !vm_busy - vrf.io.mask_read(0)(flat_vxs.length+3).req.bits.eg := getEgId(0.U, io.mask_access.eidx, 0.U, true.B) - vrf.io.mask_read(0)(flat_vxs.length+3).req.bits.oldest := false.B - io.mask_access.ready := vrf.io.mask_read(0)(flat_vxs.length+3).req.ready && !vm_busy - io.mask_access.mask := vrf.io.mask_read(0)(flat_vxs.length+3).resp >> io.mask_access.eidx(log2Ceil(dLen)-1,0) - - - val vmu_index_q = Module(new Compactor(dLenB, dLenB, UInt(8.W), false)) - val vmu_mask_q = Module(new Compactor(dLenB, dLenB, Bool(), false)) - val perm_q = Module(new DCEQueue(new PermuteMicroOp, 2)) - - vmu_index_q.io.push_data := vps.io.iss.bits.rvs2_data.asTypeOf(Vec(dLenB, UInt(8.W))) - vmu_index_q.io.push.bits.head := vps.io.iss.bits.eidx << vps.io.iss.bits.rvs2_eew - vmu_index_q.io.push.bits.tail := Mux(vps.io.iss.bits.tail, - vps.io.iss.bits.vl << vps.io.iss.bits.rvs2_eew, - 0.U) - - vmu_mask_q.io.push_data := (vps.io.iss.bits.rvm_data >> vps.io.iss.bits.eidx(log2Ceil(dLen)-1,0))(dLenB-1,0).asBools - vmu_mask_q.io.push.bits.head := 0.U - vmu_mask_q.io.push.bits.tail := Mux(vps.io.iss.bits.tail, vps.io.iss.bits.vl, 0.U) - vps.io.iss.bits.eidx - - - vps.io.iss.ready := Mux(vps.io.iss.bits.vmu, - vmu_index_q.io.push.ready && vmu_mask_q.io.push.ready, - perm_q.io.enq.ready) - - vmu_index_q.io.push.valid := vps.io.iss.valid && vps.io.iss.bits.vmu && vps.io.iss.bits.renv2 && vps.io.iss.ready - vmu_mask_q.io.push.valid := vps.io.iss.valid && vps.io.iss.bits.vmu && vps.io.iss.bits.renvm && vps.io.iss.ready - - io.vmu.mask_pop <> vmu_mask_q.io.pop - io.vmu.mask_data := vmu_mask_q.io.pop_data - io.vmu.index_pop <> vmu_index_q.io.pop - io.vmu.index_data := vmu_index_q.io.pop_data - - perm_q.io.enq.valid := vps.io.iss.valid && !vps.io.iss.bits.vmu - perm_q.io.enq.bits := vps.io.iss.bits - - perm_q.io.deq.ready := perm_buffer.io.push.ready - perm_buffer.io.push.valid := perm_q.io.deq.valid - perm_buffer.io.push.bits.head := perm_q.io.deq.bits.eidx << perm_q.io.deq.bits.rvs2_eew - perm_buffer.io.push.bits.tail := Mux(perm_q.io.deq.bits.tail, - perm_q.io.deq.bits.vl << perm_q.io.deq.bits.rvs2_eew, - 0.U) - perm_buffer.io.push_data := perm_q.io.deq.bits.rvs2_data.asTypeOf(Vec(dLenB, UInt(8.W))) - - perm_buffer.io.pop <> vxs.head.head.io.perm.req - vxs.head.head.io.perm.data := perm_buffer.io.pop_data.asUInt - - // Clear the age tags - var r_idx = 0 - def clearVat(fire: Bool, tag: UInt) = { - assert(r_idx < nRelease) - io.vat_release(r_idx).valid := fire - io.vat_release(r_idx).bits := tag - r_idx += 1 - } - - clearVat(vls.io.iss.fire && vls.io.iss.bits.tail, vls.io.iss.bits.vat) - clearVat(vss.io.iss.fire && vss.io.iss.bits.tail, vss.io.iss.bits.vat) - vxs.flatten.foreach(xs => clearVat(xs.io.iss.fire && xs.io.iss.bits.tail, xs.io.iss.bits.vat)) - - // Signalling to frontend - val seq_inflight_wv0 = (allSeqs.map(_.io.seq_hazard).map { h => - h.valid && ((h.bits.wintent & ~(0.U(egsPerVReg.W))) =/= 0.U) - } ++ allIssQs.map(_.io.hazards).flatten.map { h => - h.valid && h.bits.wintent(0) - } ++ vxus.flatten.map(_.io.pipe_hazards).flatten.map { h => - h.valid && (h.bits.eg < egsPerVReg.U) - } ++ vxus.flatten.map(_.io.iter_hazards).flatten.map { h => - h.valid && (h.bits.eg < egsPerVReg.U) - }).orR - val vdq_inflight_wv0 = vdq.io.peek.map { h => - h.valid && h.bits.may_write_v0 - }.orR - - vm_busy := seq_inflight_wv0 || vdq_inflight_wv0 - io.busy := vdq.io.deq.valid || allSeqs.map(_.io.busy).orR || vxus.flatten.map(_.io.busy).asUInt.orR || resetting - io.set_vxsat := vxus.flatten.map(_.io.set_vxsat).asUInt.orR - io.set_fflags.valid := vxus.flatten.map(_.io.set_fflags.valid).asUInt.orR - io.set_fflags.bits := vxus.flatten.map( xu => Mux(xu.io.set_fflags.valid, xu.io.set_fflags.bits, 0.U)).reduce(_|_) - - // Only one of these should actually be connected - val scalar_write_arb = Module(new Arbiter(new ScalarWrite, flat_vxus.size)) - vxus.flatten.map(_.io.scalar_write).zip(scalar_write_arb.io.in).foreach { case (i,o) => o <> i } - io.scalar_resp <> scalar_write_arb.io.out -} diff --git a/arch/src/main/scala/framework/gendomain/backend/ExecuteSequencer.scala b/arch/src/main/scala/framework/gendomain/backend/ExecuteSequencer.scala deleted file mode 100644 index f4553d23..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/ExecuteSequencer.scala +++ /dev/null @@ -1,360 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.dataview._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class ExecuteSequencer(supported_insns: Seq[VectorInstruction])(implicit p: Parameters) extends PipeSequencer(new ExecuteMicroOp)(p) { - def accepts(inst: VectorIssueInst) = !inst.vmu && new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, supported_insns, Nil).matched - - val valid = RegInit(false.B) - val inst = Reg(new BackendIssueInst) - val head = Reg(Bool()) - val reduction_head = Reg(Bool()) - val wvd_mask = Reg(UInt(egsTotal.W)) - val rvs1_mask = Reg(UInt(egsTotal.W)) - val rvs2_mask = Reg(UInt(egsTotal.W)) - val rvd_mask = Reg(UInt(egsTotal.W)) - val rvm_mask = Reg(UInt(egsPerVReg.W)) - val slide = Reg(Bool()) - val slide_up = Reg(Bool()) - val slide1 = Reg(Bool()) - val slide_offset = Reg(UInt((1+log2Ceil(maxVLMax)).W)) - val perm_head = Reg(UInt(dLenOffBits.W)) - val perm_tail = Reg(UInt(dLenOffBits.W)) - - val acc = Reg(Vec(dLenB, UInt(8.W))) - val acc_ready = Reg(Bool()) - val acc_tail = Reg(Bool()) - val acc_tail_id = Reg(UInt(log2Ceil(dLenB).W)) - - val ctrl = new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, supported_insns, - Seq(SetsWMask, UsesPermuteSeq, FPAdd, FPComp, Elementwise, UsesNarrowingSext, ZextImm5)) - - val mvnrr = inst.funct3 === OPIVI && inst.opif6 === OPIFunct6.mvnrr - val rgatherei16 = inst.funct3 === OPIVV && inst.opif6 === OPIFunct6.rgatherei16 - val compress = inst.opmf6 === OPMFunct6.compress - val vs1_eew = Mux(rgatherei16, 1.U, inst.vconfig.vtype.vsew) - val vs2_eew = inst.vconfig.vtype.vsew + inst.wide_vs2 - Mux(ctrl.bool(UsesNarrowingSext), ~inst.rs1(2,1) + 1.U, 0.U) - val vs3_eew = inst.vconfig.vtype.vsew + inst.wide_vd - val vd_eew = inst.vconfig.vtype.vsew + inst.wide_vd - val incr_eew = Seq( - Mux(inst.renv1, vs1_eew, 0.U), - Mux(inst.renv2, vs2_eew, 0.U), - Mux(inst.renvd, vs3_eew, 0.U), - vd_eew).foldLeft(0.U(2.W)) { case (b, a) => Mux(a > b, a, b) } - val acc_elementwise_opcodes = (Seq(OPFFunct6.fredosum, OPFFunct6.fwredosum) ++ - (if (vParams.useScalarFPMisc) Seq(OPFFunct6.fredmax, OPFFunct6.fredmin) else Nil) ++ - (if (vParams.useScalarFPFMA) Seq(OPFFunct6.fredusum, OPFFunct6.fwredusum) else Nil) - ) - val acc_copy = (vd_eew === 3.U && (dLenB == 8).B) || inst.opff6.isOneOf(acc_elementwise_opcodes) - val acc_last = acc_tail_id + 1.U === log2Ceil(dLenB).U - vd_eew || acc_copy - val uscalar = Mux(inst.funct3(2), inst.rs1_data, inst.imm5) - val sscalar = Mux(inst.funct3(2), inst.rs1_data, inst.imm5_sext) - val rgather = inst.opif6 === OPIFunct6.rgather - val rgather_ix = rgather && inst.funct3.isOneOf(OPIVX, OPIVI) - val rgather_v = rgather && inst.funct3.isOneOf(OPIVV) - val renv1 = Mux(inst.reduction, reduction_head, inst.renv1) - val renv2 = Mux(rgather_ix, head, Mux(inst.reduction, !reduction_head && !acc_tail, inst.renv2)) - val renvd = inst.renvd - val renvm = inst.renvm - val renacc = inst.reduction - - val use_wmask = !inst.vm && ctrl.bool(SetsWMask) - val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val eff_vl = Mux(mvnrr, ((vLen/8).U >> vd_eew) << inst.emul, Mux(inst.scalar_to_vd0, 1.U, inst.vconfig.vl)) - val increments_as_mask = (!inst.renv1 || inst.reads_vs1_mask) && (!inst.renv2 || inst.reads_vs2_mask) && (!inst.wvd || inst.writes_mask) - val next_eidx = get_next_eidx(eff_vl, eidx, incr_eew, 0.U, increments_as_mask, ctrl.bool(Elementwise)) - val eidx_tail = next_eidx === eff_vl - val tail = Mux(inst.reduction, acc_tail && acc_last, eidx_tail) - - io.dis.ready := (!valid || (tail && io.iss.fire)) && !io.dis_stall - - when (io.dis.fire) { - val dis_inst = io.dis.bits - valid := true.B - inst := io.dis.bits - assert(dis_inst.vstart === 0.U) - eidx := 0.U - - val vd_arch_mask = get_arch_mask(dis_inst.rd , dis_inst.emul +& dis_inst.wide_vd) - val vs1_arch_mask = get_arch_mask(dis_inst.rs1, Mux(dis_inst.reads_vs1_mask, 0.U, dis_inst.emul)) - val vs2_arch_mask = get_arch_mask(dis_inst.rs2, Mux(dis_inst.reads_vs2_mask, 0.U, dis_inst.emul +& dis_inst.wide_vs2)) - - wvd_mask := Mux(dis_inst.wvd , FillInterleaved(egsPerVReg, vd_arch_mask), 0.U) - rvs1_mask := Mux(dis_inst.renv1, FillInterleaved(egsPerVReg, vs1_arch_mask), 0.U) - rvs2_mask := Mux(dis_inst.renv2, FillInterleaved(egsPerVReg, vs2_arch_mask), 0.U) - rvd_mask := Mux(dis_inst.renvd, FillInterleaved(egsPerVReg, vd_arch_mask), 0.U) - rvm_mask := Mux(dis_inst.renvm, ~(0.U(egsPerVReg.W)), 0.U) - head := true.B - reduction_head := true.B - acc_tail := false.B - acc_tail_id := 0.U - acc_ready := true.B - - val dis_slide = (dis_inst.funct6.isOneOf(OPIFunct6.slideup.litValue.U, OPIFunct6.slidedown.litValue.U) - && dis_inst.funct3 =/= OPIVV) - val dis_slide_up = !dis_inst.funct6(0) - val dis_vl = dis_inst.vconfig.vl - val dis_sew = dis_inst.vconfig.vtype.vsew - val dis_vlmax = dis_inst.vconfig.vtype.vlMax - val dis_next_eidx = get_next_eidx(dis_vl, 0.U, dis_sew, 0.U, false.B, false.B) - val dis_slide1 = !dis_inst.isOpi - val dis_uscalar = Mux(dis_inst.funct3(2), dis_inst.rs1_data, dis_inst.imm5) - val dis_slide_offset = Mux(!dis_slide1, get_max_offset(dis_uscalar), 1.U) - val dis_tail = dis_next_eidx === dis_vl - val dis_rgather_eew = Mux(dis_inst.opif6 === OPIFunct6.rgatherei16, 1.U, dis_sew) - slide := dis_slide - when (dis_slide) { - slide_up := dis_slide_up - slide1 := dis_slide1 - slide_offset := dis_slide_offset - } - perm_head := Mux(dis_slide && dis_slide_up, - (dis_slide_offset << dis_sew)(dLenOffBits-1,0), - 0.U) - perm_tail := Mux(dis_slide, - Mux(dis_slide_up, - Mux(dis_tail, dis_vl << dis_sew, 0.U), - (Mux(dis_next_eidx + dis_slide_offset <= dis_vlmax, dis_next_eidx, dis_vlmax - dis_slide_offset) << dis_sew)(dLenOffBits-1,0) - ), - 1.U << dis_rgather_eew) - } .elsewhen (io.iss.fire) { - valid := !tail - head := false.B - } - - when (io.acc.valid) { - acc_ready := true.B - for (i <- 0 until dLenB) when (io.acc.bits.mask(i*8)) { acc(i) := io.acc.bits.data >> (i*8) } - } - - io.vat := inst.vat - io.seq_hazard.valid := valid - io.seq_hazard.bits.rintent := hazardMultiply(rvs1_mask | rvs2_mask | rvd_mask | rvm_mask) - io.seq_hazard.bits.wintent := hazardMultiply(wvd_mask) - io.seq_hazard.bits.vat := inst.vat - - val vs1_read_oh = Mux(renv1 , UIntToOH(io.rvs1.req.bits.eg), 0.U) - val vs2_read_oh = Mux(renv2 , UIntToOH(io.rvs2.req.bits.eg), 0.U) - val vd_read_oh = Mux(renvd , UIntToOH(io.rvd.req.bits.eg ), 0.U) - val vm_read_oh = Mux(renvm , UIntToOH(io.rvm.req.bits.eg ), 0.U) - val vd_write_oh = Mux(inst.wvd, UIntToOH(io.iss.bits.wvd_eg), 0.U) - - val raw_hazard = ((vs1_read_oh | vs2_read_oh | vd_read_oh | vm_read_oh) & io.older_writes) =/= 0.U - val waw_hazard = (vd_write_oh & io.older_writes) =/= 0.U - val war_hazard = (vd_write_oh & io.older_reads) =/= 0.U - val data_hazard = raw_hazard || waw_hazard || war_hazard - - val acc_insns = supported_insns.filter(_.props.contains(Reduction.Y)) - val acc_ctrl = new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, acc_insns, Seq(AccInitZeros, AccInitOnes, AccInitPos, AccInitNeg)) - val acc_init_fp_pos = inst.opff6 === OPFFunct6.fredmin - val acc_init_fp_neg = inst.opff6 === OPFFunct6.fredmax - - val acc_init = Mux1H(Seq( - (acc_ctrl.bool(AccInitZeros) , 0.U(dLen.W)), - (acc_ctrl.bool(AccInitOnes) , ~(0.U(dLen.W))), - (acc_ctrl.bool(AccInitPos) , VecInit.tabulate(4)({sew => Fill(dLenB >> sew, maxPosUInt(sew))})(vd_eew)), - (acc_ctrl.bool(AccInitNeg) , VecInit.tabulate(4)({sew => Fill(dLenB >> sew, minNegUInt(sew))})(vd_eew)), - (acc_init_fp_pos, VecInit.tabulate(4)({sew => Fill(dLenB >> sew, maxPosFPUInt(sew))})(vd_eew)), - (acc_init_fp_neg, VecInit.tabulate(4)({sew => Fill(dLenB >> sew, minNegFPUInt(sew))})(vd_eew)), - )) - - val rgather_eidx = get_max_offset(Mux(rgather_ix && rgather, uscalar, io.perm.data & eewBitMask(vs1_eew))) - val rgather_zero = rgather_eidx >= inst.vconfig.vtype.vlMax - val rvs2_eidx = Mux(rgather || rgatherei16, rgather_eidx, eidx) - io.rvs1.req.bits.eg := getEgId(inst.rs1, eidx , vs1_eew, inst.reads_vs1_mask) - io.rvs2.req.bits.eg := getEgId(inst.rs2, rvs2_eidx, vs2_eew, inst.reads_vs2_mask) - io.rvd.req.bits.eg := getEgId(inst.rd , eidx , vs3_eew, false.B) - io.rvm.req.bits.eg := getEgId(0.U , eidx , 0.U , true.B) - - io.rvs1.req.valid := valid && renv1 - io.rvs2.req.valid := valid && renv2 - io.rvd.req.valid := valid && renvd - io.rvm.req.valid := valid && renvm - - val oldest = inst.vat === io.vat_head - io.rvs1.req.bits.oldest := oldest - io.rvs2.req.bits.oldest := oldest - io.rvd.req.bits.oldest := oldest - io.rvm.req.bits.oldest := oldest - - val read_perm_buffer = ctrl.bool(UsesPermuteSeq) && (!slide || Mux(slide_up, - next_eidx > slide_offset, - eidx +& slide_offset < inst.vconfig.vtype.vlMax)) - - io.perm.req.bits.head := perm_head - io.perm.req.bits.tail := perm_tail - - val slide_down_byte_mask = Mux(slide && !slide_up && next_eidx + slide_offset > inst.vconfig.vtype.vlMax, - Mux(eidx +& slide_offset >= inst.vconfig.vtype.vlMax, - 0.U, - ~(0.U(dLenB.W)) >> (0.U(dLenOffBits.W) - ((inst.vconfig.vtype.vlMax - slide_offset) << vs2_eew))(dLenOffBits-1,0)), - ~(0.U(dLenB.W))) - val slide_down_bit_mask = FillInterleaved(8, slide_down_byte_mask) - val iss_valid = (valid && - !data_hazard && - !(renv1 && !io.rvs1.req.ready) && - !(renv2 && !io.rvs2.req.ready) && - !(renvd && !io.rvd.req.ready) && - !(renvm && !io.rvm.req.ready) && - !(read_perm_buffer && !io.perm.req.ready) && - !(renacc && !acc_ready) - ) - io.perm.req.valid := iss_valid && read_perm_buffer && io.iss.ready - io.iss.valid := iss_valid && !(inst.reduction && reduction_head) - - io.iss.bits.rvs1_data := io.rvs1.resp - io.iss.bits.rvs2_data := io.rvs2.resp - io.iss.bits.rvd_data := io.rvd.resp - io.iss.bits.rvs1_elem := extractElem(io.rvs1.resp, vs1_eew, eidx) - io.iss.bits.rvs2_elem := extractElem(io.rvs2.resp, vs2_eew, eidx) - io.iss.bits.rvd_elem := extractElem(io.rvd.resp , vs3_eew, eidx) - io.iss.bits.rvs1_eew := vs1_eew - io.iss.bits.rvs2_eew := vs2_eew - io.iss.bits.rvd_eew := vs3_eew - io.iss.bits.vd_eew := vd_eew - io.iss.bits.eidx := eidx - io.iss.bits.vl := inst.vconfig.vl - io.iss.bits.wvd_eg := getEgId(inst.rd, Mux(inst.reduction, 0.U, eidx), vd_eew, inst.writes_mask) - io.iss.bits.rs1 := inst.rs1 - io.iss.bits.rs2 := inst.rs2 - io.iss.bits.rd := inst.rd - io.iss.bits.funct3 := inst.funct3 - io.iss.bits.funct6 := inst.funct6 - io.iss.bits.tail := tail - io.iss.bits.head := head - io.iss.bits.acc := inst.reduction - io.iss.bits.vat := inst.vat - io.iss.bits.vm := inst.vm - io.iss.bits.rm := inst.rm - - val dlen_mask = ~(0.U(dLenB.W)) - val head_mask = dlen_mask << (eidx << vd_eew)(dLenOffBits-1,0) - val tail_mask = dlen_mask >> (0.U(dLenOffBits.W) - (next_eidx << vd_eew)(dLenOffBits-1,0)) - val slide1up_mask = Mux(head && !inst.isOpi, eewByteMask(vs2_eew), 0.U) - val slideup_mask = Mux(slide && slide_up && eidx < slide_offset, - Mux(next_eidx <= slide_offset, 0.U, dlen_mask << (slide_offset << vd_eew)(dLenOffBits-1,0)) | slide1up_mask, - dlen_mask) - val full_tail_mask = Mux(tail, - ~(0.U(dLen.W)) >> (0.U(log2Ceil(dLen).W) - eff_vl(log2Ceil(dLen)-1,0)), - ~(0.U(dLen.W)) - ) - val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W) - val vm_eidx = (eidx & ~(vm_off >> vd_eew))(log2Ceil(dLen)-1,0) - val vm_resp = (io.rvm.resp >> vm_eidx)(dLenB-1,0) - val vm_mask = Mux(use_wmask, - VecInit.tabulate(4)({ sew => FillInterleaved(1 << sew, vm_resp)(dLenB-1,0) })(vd_eew), - ~(0.U(dLenB.W)) - ) - val acc_mask = Mux(acc_last, - eewByteMask(vd_eew), - VecInit.tabulate(log2Ceil(dLenB))(i => ~(0.U((dLen>>i).W)))(acc_tail_id)) - io.iss.bits.wmask := Mux(inst.reduction && acc_tail, - acc_mask, - head_mask & tail_mask & vm_mask & slideup_mask) - - io.iss.bits.rmask := Mux(inst.vm, ~(0.U(dLenB.W)), vm_resp) - io.iss.bits.rvm_data := Mux(inst.vm, ~(0.U(dLen.W)), io.rvm.resp) - io.iss.bits.full_tail_mask := full_tail_mask - - when (inst.funct3.isOneOf(OPIVI, OPIVX, OPMVX, OPFVF)) { - io.iss.bits.rvs1_elem := sscalar - io.iss.bits.rvs1_data := dLenSplat(Mux(ctrl.bool(ZextImm5), uscalar, sscalar), vs1_eew) - } - - when (inst.reduction) { - val acc_bits = acc.asUInt - val elementwise_acc = inst.opff6.isOneOf(OPFFunct6.fredosum, OPFFunct6.fwredosum) || ( - vParams.useScalarFPMisc.B && ctrl.bool(FPComp) && inst.isOpf - ) || ( - vParams.useScalarFPFMA.B && ctrl.bool(FPAdd) && inst.isOpf - ) - - when (elementwise_acc && !acc_tail) { - io.iss.bits.rvs2_data := io.iss.bits.rvs2_elem - val mask_bit = Mux(use_wmask, (io.rvm.resp >> eidx(log2Ceil(dLen)-1,0))(0), true.B) - io.iss.bits.wmask := VecInit.tabulate(4)({sew => Fill(1 << sew, mask_bit)})(vd_eew) - } - when (acc_tail) { - val folded = VecInit.tabulate(log2Ceil(dLenB))(i => { - val start = dLen >> (1 + i) - acc_bits(2*start-1,start) - })(acc_tail_id) - io.iss.bits.rvs1_elem := Mux(acc_copy, acc_init, folded) - io.iss.bits.rvs1_data := Mux(acc_copy, acc_init, folded) - io.iss.bits.rvs1_eew := vd_eew - io.iss.bits.rvs2_elem := acc_bits - io.iss.bits.rvs2_data := acc_bits - io.iss.bits.rvs2_eew := vd_eew - } .otherwise { - io.iss.bits.rvs1_elem := acc_bits - io.iss.bits.rvs1_data := acc_bits - io.iss.bits.rvs1_eew := vd_eew - } - } - when (rgather_v || rgatherei16) { - io.iss.bits.rvs1_elem := rgather_eidx - io.iss.bits.rvs1_data := rgather_eidx - } - when (rgather_zero && (rgather || rgatherei16)) { - io.iss.bits.rvs2_elem := 0.U - io.iss.bits.rvs2_data := 0.U - } - when (slide) { - io.iss.bits.rvs2_elem := io.perm.data & slide_down_bit_mask - io.iss.bits.rvs2_data := io.perm.data & slide_down_bit_mask - } - - when (iss_valid && inst.reduction && reduction_head) { - val v0_mask = eewBitMask(vd_eew) - acc := ((acc_init & ~v0_mask.pad(dLen)) | (io.rvs1.resp & v0_mask)).asTypeOf(Vec(dLenB, UInt(8.W))) - reduction_head := false.B - } - - when (io.iss.fire && !tail) { - when (next_is_new_eg(eidx, next_eidx, vd_eew, inst.writes_mask) && !inst.reduction && !compress && vParams.enableChaining.B) { - val wvd_clr_mask = UIntToOH(io.iss.bits.wvd_eg) - wvd_mask := wvd_mask & ~wvd_clr_mask - } - when (next_is_new_eg(eidx, next_eidx, vs2_eew, inst.reads_vs2_mask) && !(inst.reduction && head) && !rgather_v && !rgatherei16 && vParams.enableChaining.B) { - rvs2_mask := rvs2_mask & ~UIntToOH(io.rvs2.req.bits.eg) - } - when (rgather_ix && vParams.enableChaining.B) { - rvs2_mask := 0.U - } - when (next_is_new_eg(eidx, next_eidx, vs1_eew, inst.reads_vs1_mask) && vParams.enableChaining.B) { - rvs1_mask := rvs1_mask & ~UIntToOH(io.rvs1.req.bits.eg) - } - when (next_is_new_eg(eidx, next_eidx, vs3_eew, false.B) && vParams.enableChaining.B) { - rvd_mask := rvd_mask & ~UIntToOH(io.rvd.req.bits.eg) - } - when (next_is_new_eg(eidx, next_eidx, 0.U , true.B) && vParams.enableChaining.B) { - rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg) - } - acc_ready := false.B - when (eidx_tail) { acc_tail := true.B } - when (acc_tail) { acc_tail_id := acc_tail_id + 1.U } - eidx := next_eidx - - when (ctrl.bool(UsesPermuteSeq) && slide) { - val next_next_eidx = get_next_eidx(eff_vl, next_eidx, incr_eew, 0.U, increments_as_mask, ctrl.bool(Elementwise)) - val next_tail = next_next_eidx === eff_vl - perm_head := Mux(slide_up, - Mux(next_eidx < slide_offset, (slide_offset << vs2_eew)(dLenOffBits-1,0), 0.U), - next_eidx << vs2_eew) - perm_tail := Mux(slide_up, - Mux(next_tail, eff_vl << vs2_eew, 0.U), - (Mux(next_next_eidx + slide_offset <= inst.vconfig.vtype.vlMax, next_next_eidx, inst.vconfig.vtype.vlMax - slide_offset) << vs2_eew)(dLenOffBits-1,0)) - } - } - - io.busy := valid - io.head := head -} diff --git a/arch/src/main/scala/framework/gendomain/backend/IssueQueue.scala b/arch/src/main/scala/framework/gendomain/backend/IssueQueue.scala deleted file mode 100644 index 74973a9d..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/IssueQueue.scala +++ /dev/null @@ -1,47 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.dataview._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class IssueQueue(depth: Int, nSeqs: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - - val io = IO(new Bundle { - val enq = Flipped(Decoupled(new IssueQueueInst(nSeqs))) - val deq = Decoupled(new IssueQueueInst(nSeqs)) - val hazards = Output(Vec(depth, Valid(new InstructionHazard))) - }) - - if (depth > 0) { - val q = Module(new DCEQueue(new IssueQueueInst(nSeqs), depth, pipe=true)) - q.io.enq <> io.enq - io.deq <> q.io.deq - - q.io.peek.zip(io.hazards).foreach { case (e,h) => - h.valid := e.valid - h.bits.vat := e.bits.vat - val rs2 = Mux(e.bits.rs1_is_rs2, e.bits.rs1, e.bits.rs2) - val only_writes_vd0 = e.bits.scalar_to_vd0 || e.bits.reduction - val vd_lmul = Mux(only_writes_vd0 , 0.U, e.bits.emul +& e.bits.wide_vd +& e.bits.nf_log2) - val vs1_lmul = Mux(e.bits.reads_vs1_mask, 0.U, e.bits.emul) - val vs2_lmul = Mux(e.bits.reads_vs2_mask, 0.U, e.bits.emul +& e.bits.wide_vs2 +& e.bits.nf_log2) - val vd_arch_mask = get_arch_mask(e.bits.rd , vd_lmul ) - val vs1_arch_mask = get_arch_mask(e.bits.rs1, vs1_lmul) - val vs2_arch_mask = get_arch_mask(rs2 , vs2_lmul) - h.bits.rintent := Seq( - (e.bits.renv1, vs1_arch_mask), - (e.bits.renv2, vs2_arch_mask), - (e.bits.renvd, vd_arch_mask), - (e.bits.renvm, 1.U) - ).map(t => Mux(t._1, t._2, 0.U)).reduce(_|_) - h.bits.wintent := Mux(e.bits.wvd, vd_arch_mask, 0.U) - } - } else { - io.deq <> io.enq - } -} diff --git a/arch/src/main/scala/framework/gendomain/backend/LoadSequencer.scala b/arch/src/main/scala/framework/gendomain/backend/LoadSequencer.scala deleted file mode 100644 index 1a05321c..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/LoadSequencer.scala +++ /dev/null @@ -1,92 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import framework.gendomain.common._ - -class LoadSequencer(implicit p: Parameters) extends PipeSequencer(new LoadRespMicroOp)(p) { - def accepts(inst: VectorIssueInst) = inst.vmu && !inst.opcode(5) - - val valid = RegInit(false.B) - val inst = Reg(new BackendIssueInst) - val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val sidx = Reg(UInt(3.W)) - val wvd_mask = Reg(UInt(egsTotal.W)) - val rvm_mask = Reg(UInt(egsPerVReg.W)) - val head = Reg(Bool()) - - val renvm = !inst.vm - val next_eidx = get_next_eidx(inst.vconfig.vl, eidx, inst.mem_elem_size, 0.U, false.B, false.B) - val tail = next_eidx === inst.vconfig.vl && sidx === inst.seg_nf - - io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall - - when (io.dis.fire) { - val iss_inst = io.dis.bits - valid := true.B - inst := iss_inst - eidx := iss_inst.vstart - sidx := iss_inst.segstart - - val wvd_arch_mask = Wire(Vec(32, Bool())) - for (i <- 0 until 32) { - val group = i.U >> iss_inst.emul - val rd_group = iss_inst.rd >> iss_inst.emul - wvd_arch_mask(i) := group >= rd_group && group <= (rd_group + iss_inst.nf) - } - wvd_mask := FillInterleaved(egsPerVReg, wvd_arch_mask.asUInt) - rvm_mask := Mux(!iss_inst.vm, ~(0.U(egsPerVReg.W)), 0.U) - head := true.B - } .elsewhen (io.iss.fire) { - valid := !tail - head := false.B - } - - io.vat := inst.vat - io.seq_hazard.valid := valid - io.seq_hazard.bits.rintent := hazardMultiply(rvm_mask) - io.seq_hazard.bits.wintent := hazardMultiply(wvd_mask) - io.seq_hazard.bits.vat := inst.vat - - val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U) - val vd_write_oh = UIntToOH(io.iss.bits.wvd_eg) - - val raw_hazard = (vm_read_oh & io.older_writes) =/= 0.U - val waw_hazard = (vd_write_oh & io.older_writes) =/= 0.U - val war_hazard = (vd_write_oh & io.older_reads) =/= 0.U - val data_hazard = raw_hazard || waw_hazard || war_hazard - - io.rvm.req.valid := valid && renvm - io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B) - io.rvm.req.bits.oldest := inst.vat === io.vat_head - - io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) - io.iss.bits.wvd_eg := getEgId(inst.rd + (sidx << inst.emul), eidx, inst.mem_elem_size, false.B) - io.iss.bits.tail := tail - io.iss.bits.vat := inst.vat - io.iss.bits.debug_id := inst.debug_id - - val head_mask = get_head_mask(~(0.U(dLenB.W)), eidx , inst.mem_elem_size) - val tail_mask = get_tail_mask(~(0.U(dLenB.W)), next_eidx, inst.mem_elem_size) - val vm_mask = Mux(!renvm, ~(0.U(dLenB.W)), get_vm_mask(io.rvm.resp, eidx, inst.mem_elem_size)) - io.iss.bits.wmask := Mux(sidx > inst.segend && inst.seg_nf =/= 0.U, 0.U, head_mask & tail_mask & vm_mask) - - when (io.iss.fire && !tail) { - when (next_is_new_eg(eidx, next_eidx, inst.mem_elem_size, false.B) && vParams.enableChaining.B) { - wvd_mask := wvd_mask & ~vd_write_oh - } - when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) { - rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg) - } - when (sidx === inst.seg_nf) { - sidx := 0.U - eidx := next_eidx - } .otherwise { - sidx := sidx + 1.U - } - } - - io.busy := valid - io.head := head -} diff --git a/arch/src/main/scala/framework/gendomain/backend/PermuteSequencer.scala b/arch/src/main/scala/framework/gendomain/backend/PermuteSequencer.scala deleted file mode 100644 index c91311f9..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/PermuteSequencer.scala +++ /dev/null @@ -1,111 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class PermuteSequencer(exu_insns: Seq[VectorInstruction])(implicit p: Parameters) extends PipeSequencer(new PermuteMicroOp)(p) { - def accepts(inst: VectorIssueInst) = { - val needs_mask = inst.vmu && (!inst.vm && inst.mop =/= mopUnit) - val needs_index = inst.vmu && inst.mop(0) - val arith = !inst.vmu && new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, exu_insns.filter(_.props.contains(UsesPermuteSeq.Y)), Nil).matched - needs_mask || needs_index || arith - } - - val valid = RegInit(false.B) - val inst = Reg(new BackendIssueInst) - val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val rvs2_mask = Reg(UInt(egsTotal.W)) - val rvm_mask = Reg(UInt(egsPerVReg.W)) - val head = Reg(Bool()) - val slide_offset = Reg(UInt((1+log2Ceil(maxVLMax)).W)) - val slide = !inst.vmu && inst.funct3 =/= OPIVV - val slide_up = !inst.funct6(0) - val rs2 = Mux(inst.rs1_is_rs2, inst.rs1, inst.rs2) - val gatherei16 = inst.funct3 === OPIVV && inst.opif6 === OPIFunct6.rgatherei16 - - val renvm = inst.renvm - val renv2 = inst.renv2 - val incr_eew = Mux(inst.vmu, inst.mem_idx_size, - Mux(gatherei16, 1.U, inst.vconfig.vtype.vsew)) - val eff_vl = Mux(slide, - Mux(slide_up, inst.vconfig.vl - slide_offset, min(inst.vconfig.vtype.vlMax, inst.vconfig.vl + slide_offset)), - inst.vconfig.vl - )(log2Ceil(maxVLMax),0) - val next_eidx = get_next_eidx(eff_vl, eidx, incr_eew, 0.U, false.B, false.B) - val tail = next_eidx === eff_vl - - io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall - - when (io.dis.fire) { - val iss_inst = io.dis.bits - val offset = Mux(iss_inst.isOpi, get_max_offset(Mux(iss_inst.funct3(2), iss_inst.rs1_data, iss_inst.imm5)), 1.U) - val slide = !iss_inst.vmu && iss_inst.funct3 =/= OPIVV - val slide_up = !iss_inst.funct6(0) - val slide_start = Mux(slide_up, 0.U, offset) - val vlmax = iss_inst.vconfig.vtype.vlMax - val slide_no_read = Mux(slide_up, - iss_inst.vconfig.vl <= offset, - offset >= vlmax) - valid := Mux(!slide, true.B, !slide_no_read) - inst := iss_inst - eidx := Mux(!slide, iss_inst.vstart, slide_start) - slide_offset := offset - - val rs2 = Mux(iss_inst.rs1_is_rs2, iss_inst.rs1, iss_inst.rs2) - val renv2_arch_mask = get_arch_mask(rs2, iss_inst.emul) - rvs2_mask := Mux(iss_inst.renv2, FillInterleaved(egsPerVReg, renv2_arch_mask), 0.U) - rvm_mask := Mux(iss_inst.renvm, ~(0.U(egsPerVReg.W)), 0.U) - head := true.B - } .elsewhen (io.iss.fire) { - valid := !tail - head := false.B - } - - io.vat := inst.vat - io.seq_hazard.valid := valid - io.seq_hazard.bits.rintent := hazardMultiply(rvs2_mask | rvm_mask) - io.seq_hazard.bits.wintent := false.B - io.seq_hazard.bits.vat := inst.vat - - val vs2_read_oh = Mux(renv2, UIntToOH(io.rvs2.req.bits.eg), 0.U) - val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U) - - val raw_hazard = ((vm_read_oh | vs2_read_oh) & io.older_writes) =/= 0.U - val data_hazard = raw_hazard - - val oldest = inst.vat === io.vat_head - - io.rvs2.req.valid := valid && renv2 - io.rvs2.req.bits.eg := getEgId(rs2, eidx, incr_eew, false.B) - io.rvs2.req.bits.oldest := oldest - io.rvm.req.valid := valid && renvm - io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B) - io.rvm.req.bits.oldest := oldest - - io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && (!renv2 || io.rvs2.req.ready) - io.iss.bits.renv2 := renv2 - io.iss.bits.renvm := renvm - io.iss.bits.rvs2_data := io.rvs2.resp - io.iss.bits.rvs2_eew := incr_eew - io.iss.bits.eidx := eidx - io.iss.bits.vl := eff_vl - io.iss.bits.rvm_data := Mux(renvm, io.rvm.resp, ~(0.U(dLen.W))) - io.iss.bits.vmu := inst.vmu - io.iss.bits.tail := tail - - when (io.iss.fire && !tail) { - when (next_is_new_eg(eidx, next_eidx, incr_eew, false.B) && vParams.enableChaining.B) { - rvs2_mask := rvs2_mask & ~vs2_read_oh - } - when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) { - rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg) - } - eidx := next_eidx - } - - io.busy := valid - io.head := head -} diff --git a/arch/src/main/scala/framework/gendomain/backend/PipeSequencer.scala b/arch/src/main/scala/framework/gendomain/backend/PipeSequencer.scala deleted file mode 100644 index cd9db257..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/PipeSequencer.scala +++ /dev/null @@ -1,74 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tile.{CoreModule} -import framework.gendomain.common._ - -abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - - val io = IO(new Bundle { - val dis = Flipped(Decoupled(new BackendIssueInst)) - val dis_stall = Input(Bool()) // used to disable OOO - - val seq_hazard = Output(Valid(new SequencerHazard)) - - val vat = Output(UInt(vParams.vatSz.W)) - val vat_head = Input(UInt(vParams.vatSz.W)) - val older_writes = Input(UInt(egsTotal.W)) - val older_reads = Input(UInt(egsTotal.W)) - - val busy = Output(Bool()) - val head = Output(Bool()) - - val rvs1 = new VectorReadIO - val rvs2 = new VectorReadIO - val rvd = new VectorReadIO - val rvm = new VectorReadIO - val perm = new Bundle { - val req = Decoupled(new CompactorReq(dLenB)) - val data = Input(UInt(dLen.W)) - } - - val iss = Decoupled(issType) - - val acc = Input(Valid(new VectorWrite(dLen))) - }) - def accepts(inst: VectorIssueInst): Bool - - def min(a: UInt, b: UInt) = Mux(a > b, b, a) - def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0) - def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0) - def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0)) - def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = { - val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W) - val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0) - val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0) - Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) }) - } - def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = { - val next = Wire(UInt((1+log2Ceil(maxVLMax)).W)) - next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask, - eidx +& dLen.U, - (((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen)) - )) - min(vl, next) - } - def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = { - val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew) - (next_eidx >> offset) =/= (eidx >> offset) - } - - - io.rvs1.req.valid := false.B - io.rvs1.req.bits := DontCare - io.rvs2.req.valid := false.B - io.rvs2.req.bits := DontCare - io.rvd.req.valid := false.B - io.rvd.req.bits := DontCare - io.rvm.req.valid := false.B - io.rvm.req.bits := DontCare - io.perm.req.valid := false.B - io.perm.req.bits := DontCare -} diff --git a/arch/src/main/scala/framework/gendomain/backend/RegisterFile.scala b/arch/src/main/scala/framework/gendomain/backend/RegisterFile.scala deleted file mode 100644 index ccd37d1f..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/RegisterFile.scala +++ /dev/null @@ -1,180 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tile.{CoreModule} -import freechips.rocketchip.util._ -import framework.gendomain.common._ - -class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { - val io = IO(new ArbiterIO(new VectorReadReq, n)) - - val arb = Module(new RRArbiter(new VectorReadReq, n)) - io <> arb.io - val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) - //assert(PopCount(oldest_oh) <= 1.U) - when (oldest_oh.orR) { - io.chosen := VecInit(oldest_oh).asUInt - io.out.valid := true.B - io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) - for (i <- 0 until n) { - io.in(i).ready := oldest_oh(i) && io.out.ready - } - } -} - -class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val in = Vec(n, Flipped(new VectorReadIO)) - val out = Vec(banks, new VectorReadIO) - }) - - val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } - for (i <- 0 until banks) { - io.out(i).req <> arbs(i).io.out - } - - val bankOffset = log2Ceil(banks) - - for (i <- 0 until n) { - val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) - for (j <- 0 until banks) { - arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) - arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset - arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest - } - io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) - io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) - } -} - -class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val read = Vec(reads, Flipped(new VectorReadIO)) - val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) - val write = Input(Valid(new VectorWrite(dLen))) - val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) - }) - val ll_write_valid = RegInit(false.B) - val ll_write_bits = Reg(new VectorWrite(dLen)) - - val vrf = Mem(rows, Vec(dLen, Bool())) - val v0_mask = Mem(maskRows, Vec(dLen, Bool())) - for (read <- io.read) { - read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) - read.resp := DontCare - when (read.req.valid) { - read.resp := vrf.read(read.req.bits.eg).asUInt - } - } - for (mask_read <- io.mask_read) { - mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) - mask_read.resp := DontCare - when (mask_read.req.valid) { - mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt - } - } - - val write = WireInit(io.write) - io.ll_write.ready := false.B - if (vParams.vrfHiccupBuffer) { - when (!io.write.valid) { // drain hiccup buffer - write.valid := ll_write_valid || io.ll_write.valid - write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) - ll_write_valid := false.B - when (io.ll_write.valid && ll_write_valid) { - ll_write_valid := true.B - ll_write_bits := io.ll_write.bits - } - io.ll_write.ready := true.B - } .elsewhen (!ll_write_valid) { // fill hiccup buffer - when (io.ll_write.valid) { - ll_write_valid := true.B - ll_write_bits := io.ll_write.bits - } - io.ll_write.ready := true.B - } - } else { - when (!io.write.valid) { - io.ll_write.ready := true.B - write.valid := io.ll_write.valid - write.bits := io.ll_write.bits - } - } - - when (write.valid) { - vrf.write( - write.bits.eg, - VecInit(write.bits.data.asBools), - write.bits.mask.asBools) - when (write.bits.eg < maskRows.U) { - v0_mask.write( - write.bits.eg, - VecInit(write.bits.data.asBools), - write.bits.mask.asBools) - } - } -} - -class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - - val nBanks = vParams.vrfBanking - // Support 1, 2, and 4 banks for the VRF - require(nBanks == 1 || nBanks == 2 || nBanks == 4) - - val io = IO(new Bundle { - val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) - val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) - - val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) - val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) - }) - - val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } - - reads.zipWithIndex.foreach { case (rc, i) => - val xbar = Module(new RegisterReadXbar(rc, nBanks)) - vrf.zipWithIndex.foreach { case (bank, j) => - bank.io.read(i) <> xbar.io.out(j) - } - xbar.io.in <> io.read(i) - } - - maskReads.zipWithIndex.foreach { case (rc, i) => - val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) - vrf.zipWithIndex.foreach { case (bank, j) => - bank.io.mask_read(i) <> mask_xbar.io.out(j) - } - mask_xbar.io.in <> io.mask_read(i) - } - - io.ll_writes.foreach(_.ready := false.B) - - vrf.zipWithIndex.foreach { case (rf, i) => - val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } - val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) - val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) - val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) - val bank_write_valid = bank_match.orR - - rf.io.write.valid := bank_write_valid - rf.io.write.bits.data := bank_write_data - rf.io.write.bits.mask := bank_write_mask - rf.io.write.bits.eg := bank_write_eg >> vrfBankBits - when (bank_write_valid) { PopCount(bank_match) === 1.U } - - val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) - rf.io.ll_write <> ll_arb.io.out - - io.ll_writes.zipWithIndex.foreach { case (w, j) => - ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U - ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits - ll_arb.io.in(j).bits.data := w.bits.data - ll_arb.io.in(j).bits.mask := w.bits.mask - when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { - w.ready := true.B - } - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/backend/StoreSequencer.scala b/arch/src/main/scala/framework/gendomain/backend/StoreSequencer.scala deleted file mode 100644 index 5f3bfbba..00000000 --- a/arch/src/main/scala/framework/gendomain/backend/StoreSequencer.scala +++ /dev/null @@ -1,98 +0,0 @@ -package framework.gendomain.backend - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import framework.gendomain.common._ - -class StoreSequencer(implicit p: Parameters) extends PipeSequencer(new StoreDataMicroOp)(p) { - def accepts(inst: VectorIssueInst) = inst.vmu && inst.opcode(5) - - val valid = RegInit(false.B) - val inst = Reg(new VectorIssueInst) - val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val sidx = Reg(UInt(3.W)) - val rvd_mask = Reg(UInt(egsTotal.W)) - val rvm_mask = Reg(UInt(egsPerVReg.W)) - val sub_dlen = Reg(UInt(2.W)) - val head = Reg(Bool()) - - val renvm = !inst.vm && inst.mop === mopUnit - val next_eidx = get_next_eidx(inst.vconfig.vl, eidx, inst.mem_elem_size, sub_dlen, false.B, false.B) - val tail = next_eidx === inst.vconfig.vl && sidx === inst.seg_nf - - io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall - - when (io.dis.fire) { - val iss_inst = io.dis.bits - valid := true.B - inst := iss_inst - eidx := iss_inst.vstart - sidx := 0.U - - val rvd_arch_mask = Wire(Vec(32, Bool())) - for (i <- 0 until 32) { - val group = i.U >> iss_inst.emul - val rd_group = iss_inst.rd >> iss_inst.emul - rvd_arch_mask(i) := group >= rd_group && group <= (rd_group + iss_inst.nf) - } - rvd_mask := FillInterleaved(egsPerVReg, rvd_arch_mask.asUInt) - rvm_mask := Mux(!iss_inst.vm, ~(0.U(egsPerVReg.W)), 0.U) - sub_dlen := Mux(iss_inst.seg_nf =/= 0.U && (dLenOffBits.U > (3.U +& iss_inst.mem_elem_size)), - dLenOffBits.U - 3.U - iss_inst.mem_elem_size, - 0.U) - head := true.B - } .elsewhen (io.iss.fire) { - valid := !tail - head := false.B - } - - io.vat := inst.vat - io.seq_hazard.valid := valid - io.seq_hazard.bits.rintent := hazardMultiply(rvd_mask | rvm_mask) - io.seq_hazard.bits.wintent := 0.U - io.seq_hazard.bits.vat := inst.vat - - val vd_read_oh = UIntToOH(io.rvd.req.bits.eg) - val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U) - - val raw_hazard = ((vm_read_oh | vd_read_oh) & io.older_writes) =/= 0.U - val data_hazard = raw_hazard - - val oldest = inst.vat === io.vat_head - - io.rvd.req.valid := valid && io.iss.ready - io.rvd.req.bits.eg := getEgId(inst.rd + (sidx << inst.emul), eidx, inst.mem_elem_size, false.B) - io.rvd.req.bits.oldest := oldest - io.rvm.req.valid := valid && renvm && io.iss.ready - io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B) - io.rvm.req.bits.oldest := oldest - - io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && io.rvd.req.ready - io.iss.bits.stdata := io.rvd.resp - val head_mask = get_head_mask(~(0.U(dLenB.W)), eidx , inst.mem_elem_size) - val tail_mask = get_tail_mask(~(0.U(dLenB.W)), next_eidx, inst.mem_elem_size) - val vm_mask = Mux(!renvm, ~(0.U(dLenB.W)), get_vm_mask(io.rvm.resp, eidx, inst.mem_elem_size)) - io.iss.bits.stmask := vm_mask - io.iss.bits.debug_id := inst.debug_id - io.iss.bits.tail := tail - io.iss.bits.vat := inst.vat - - when (io.iss.fire && !tail) { - when (next_is_new_eg(eidx, next_eidx, inst.mem_elem_size, false.B) && vParams.enableChaining.B) { - rvd_mask := rvd_mask & ~UIntToOH(io.rvd.req.bits.eg) - } - when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) { - rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg) - } - when (sidx === inst.seg_nf) { - sidx := 0.U - eidx := next_eidx - } .otherwise { - sidx := sidx + 1.U - } - } - - io.busy := valid - io.head := head -} diff --git a/arch/src/main/scala/framework/gendomain/common/Bundles.scala b/arch/src/main/scala/framework/gendomain/common/Bundles.scala deleted file mode 100644 index b70fab7f..00000000 --- a/arch/src/main/scala/framework/gendomain/common/Bundles.scala +++ /dev/null @@ -1,265 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ - -class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val debug_id = UInt(debugIdSz.W) - - val base_offset = UInt(pgIdxBits.W) - val page = UInt((paddrBits - pgIdxBits).W) - val stride = UInt(pgIdxBits.W) - - val segstart = UInt(3.W) - val segend = UInt(3.W) - val vstart = UInt(log2Ceil(maxVLMax).W) - val vl = UInt((1+log2Ceil(maxVLMax)).W) - - val mop = UInt(2.W) - val vm = Bool() - val nf = UInt(3.W) - - val idx_size = UInt(2.W) - val elem_size = UInt(2.W) - val whole_reg = Bool() - val store = Bool() - val fast_sg = Bool() - - def indexed = !mop.isOneOf(mopUnit, mopStrided) - def seg_nf = Mux(whole_reg, 0.U, nf) - def wr_nf = Mux(whole_reg, nf, 0.U) -} - - -class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val pc = UInt(vaddrBitsExtended.W) - val bits = UInt(32.W) - val vconfig = new VConfig - - val vstart = UInt(log2Ceil(maxVLMax).W) - val segstart = UInt(3.W) - val segend = UInt(3.W) - val rs1_data = UInt(xLen.W) - val rs2_data = UInt(xLen.W) - val page = UInt((paddrBits - pgIdxBits).W) - val vat = UInt(vParams.vatSz.W) - val rm = UInt(3.W) - val emul = UInt(2.W) - val fast_sg = Bool() - val debug_id = UInt(debugIdSz.W) - val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this - - def opcode = bits(6,0) - def store = opcode(5) - def mem_idx_size = bits(13,12) - def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12)) - def vm = bits(25) - def orig_mop = bits(27,26) - def umop = bits(24,20) - def nf = bits(31,29) - def wr = orig_mop === mopUnit && umop === lumopWhole - def seg_nf = Mux(wr, 0.U, nf) - def wr_nf = Mux(wr, nf, 0.U) - def vmu = opcode.isOneOf(opcLoad, opcStore) - def rs1 = bits(19,15) - def rs2 = bits(24,20) - def rd = bits(11,7) - def may_write_v0 = rd === 0.U && opcode =/= opcStore - def funct3 = bits(14,12) - def imm5 = bits(19,15) - def imm5_sext = Cat(Fill(59, imm5(4)), imm5) - def funct6 = bits(31,26) - def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) || (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0)) - def writes_frf = !vmu && (funct3 === OPFVV) - - def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) - def isOpm = funct3.isOneOf(OPMVV, OPMVX) - def isOpf = funct3.isOneOf(OPFVV, OPFVF) - - def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) - def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) - def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) -} - -class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) { - val reduction = Bool() // accumulates into vd[0] - val scalar_to_vd0 = Bool() // mv scalar to vd[0] - val wide_vd = Bool() // vd reads/writes at 2xSEW - val wide_vs2 = Bool() // vs2 reads at 2xSEW - val writes_mask = Bool() // writes dest as a mask - val reads_vs1_mask = Bool() // vs1 read as mask - val reads_vs2_mask = Bool() // vs2 read as mask - val rs1_is_rs2 = Bool() - val nf_log2 = UInt(2.W) - - val renv1 = Bool() - val renv2 = Bool() - val renvd = Bool() - val renvm = Bool() - val wvd = Bool() -} - -class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) { - val seq = UInt(nSeqs.W) -} - -class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val eg = UInt(log2Ceil(32 * vLen / writeBits).W) - def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0) - val data = UInt(writeBits.W) - val mask = UInt(writeBits.W) -} - -class ScalarWrite extends Bundle { - val data = UInt(64.W) - val fp = Bool() - val size = UInt(2.W) - val rd = UInt(5.W) -} - -class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val eg = UInt(log2Ceil(egsTotal).W) - val oldest = Bool() -} - -class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val req = Decoupled(new VectorReadReq) - val resp = Input(UInt(dLen.W)) -} - -class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val ready = Output(Bool()) - val valid = Input(Bool()) - val vrs = Input(UInt(5.W)) - val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) - val eew = Input(UInt(2.W)) - val idx = Output(UInt(64.W)) -} - -class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val ready = Output(Bool()) - val valid = Input(Bool()) - val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) - val mask = Output(Bool()) -} - -class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val debug_id = UInt(debugIdSz.W) - val data = UInt(8.W) - val mask = Bool() -} - -class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val eidx = UInt(log2Ceil(maxVLMax).W) - val vl = UInt((1+log2Ceil(maxVLMax)).W) - - val rvs1_data = UInt(dLen.W) - val rvs2_data = UInt(dLen.W) - val rvd_data = UInt(dLen.W) - val rvm_data = UInt(dLen.W) - - val rvs1_elem = UInt(64.W) - val rvs2_elem = UInt(64.W) - val rvd_elem = UInt(64.W) - - val rvs1_eew = UInt(2.W) - val rvs2_eew = UInt(2.W) - val rvd_eew = UInt(2.W) - val vd_eew = UInt(2.W) - - val rmask = UInt(dLenB.W) - val wmask = UInt(dLenB.W) - - val full_tail_mask = UInt(dLen.W) - - val wvd_eg = UInt(log2Ceil(egsTotal).W) - - val funct3 = UInt(3.W) - def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) - def isOpm = funct3.isOneOf(OPMVV, OPMVX) - def isOpf = funct3.isOneOf(OPFVV, OPFVF) - - def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) - def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) - def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) - - def vd_eew8 = vd_eew === 0.U - def vd_eew16 = vd_eew === 1.U - def vd_eew32 = vd_eew === 2.U - def vd_eew64 = vd_eew === 3.U - - val funct6 = UInt(6.W) - val rs1 = UInt(5.W) - val rs2 = UInt(5.W) - val rd = UInt(5.W) - val vm = Bool() - - val head = Bool() - val tail = Bool() - val vat = UInt(vParams.vatSz.W) - val acc = Bool() - - val rm = UInt(3.W) - def vxrm = rm(1,0) - def frm = rm -} - -class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val stdata = UInt(dLen.W) - val stmask = UInt(dLenB.W) - val debug_id = UInt(debugIdSz.W) - val tail = Bool() - val vat = UInt(vParams.vatSz.W) - def asMaskedBytes = { - val bytes = Wire(Vec(dLenB, new MaskedByte)) - for (i <- 0 until dLenB) { - bytes(i).data := stdata(((i+1)*8)-1,i*8) - bytes(i).mask := stmask(i) - bytes(i).debug_id := debug_id - } - bytes - } -} - -class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val wvd_eg = UInt(log2Ceil(egsTotal).W) - val wmask = UInt(dLenB.W) - val tail = Bool() - val debug_id = UInt(debugIdSz.W) - val vat = UInt(vParams.vatSz.W) -} - -class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val renv2 = Bool() - val renvm = Bool() - val rvs2_data = UInt(dLen.W) - val eidx = UInt(log2Ceil(maxVLMax).W) - val rvs2_eew = UInt(2.W) - val rvm_data = UInt(dLen.W) - val vmu = Bool() - val vl = UInt((1+log2Ceil(maxVLMax)).W) - val tail = Bool() -} - -class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val latency = UInt(log2Ceil(pipe_depth).W) - val eg = UInt(log2Ceil(egsTotal).W) - def eg_oh = UIntToOH(eg) -} - -class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val vat = UInt(vParams.vatSz.W) - val rintent = UInt(egsTotal.W) - val wintent = UInt(egsTotal.W) -} - - -class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val vat = UInt(vParams.vatSz.W) - val rintent = UInt(32.W) - val wintent = UInt(32.W) -} diff --git a/arch/src/main/scala/framework/gendomain/common/Compactor.scala b/arch/src/main/scala/framework/gendomain/common/Compactor.scala deleted file mode 100644 index 49ae19ba..00000000 --- a/arch/src/main/scala/framework/gendomain/common/Compactor.scala +++ /dev/null @@ -1,73 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ - -class CompactorReq(n: Int) extends Bundle { - val head = UInt(log2Ceil(n).W) - val tail = UInt(log2Ceil(n).W) - def count = Mux(tail === 0.U, n.U, tail) - head -} - -class Compactor[T <: Data](pushN: Int, popN: Int, gen: => T, forward: Boolean) extends Module { - require (pushN >= popN) - val io = IO(new Bundle { - val push = Flipped(Decoupled(new CompactorReq(pushN))) - val push_data = Input(Vec(pushN, gen)) - - val pop = Flipped(Decoupled(new CompactorReq(popN))) - val pop_data = Output(Vec(popN, gen)) - }) - - val (push, push_data) = if (forward) { - (io.push, io.push_data) - } else { - val push_q = Module(new Queue(new CompactorReq(pushN) { - val data = Vec(pushN, gen) - }, 2)) - push_q.io.enq.valid := io.push.valid - push_q.io.enq.bits.head := io.push.bits.head - push_q.io.enq.bits.tail := io.push.bits.tail - push_q.io.enq.bits.data := io.push_data - io.push.ready := push_q.io.enq.ready - (push_q.io.deq, push_q.io.deq.bits.data) - } - - def wshr(in: Seq[T], shamt: UInt): Seq[T] = - (0 until in.size).map { i => VecInit(in.drop(i))(shamt) } - def wshl(in: Seq[T], shamt: UInt): Seq[T] = - wshr(in.reverse, shamt).reverse - - val count = RegInit(0.U((1+log2Ceil(pushN)).W)) - val regs = Seq.fill(pushN) { Reg(gen) } - val valid = (1.U << count) - 1.U - - push.ready := pushN.U +& Mux(io.pop.valid, io.pop.bits.count, 0.U) >= count +& push.bits.count - io.pop.ready := count +& Mux(push.valid, push.bits.count, 0.U) >= io.pop.bits.count - - val regs_shr = wshr(regs, io.pop.bits.count) - val valid_shr = valid >> io.pop.bits.count - - when (push.fire || io.pop.fire) { - count := count +& Mux(push.fire, push.bits.count, 0.U) - Mux(io.pop.fire, io.pop.bits.count, 0.U) - } - - val push_elems = push_data - val push_shr = wshr((Seq.fill(pushN)(0.U.asTypeOf(gen)) ++ push_elems), pushN.U +& push.bits.head - count) - val push_shr_pop = wshr((Seq.fill(pushN)(0.U.asTypeOf(gen)) ++ push_elems), pushN.U +& push.bits.head +& io.pop.bits.count - count) - - when (io.pop.fire) { - for (i <- 0 until pushN) regs(i) := Mux(valid_shr(i), regs_shr(i), push_shr_pop(i)) - } .elsewhen (push.fire) { - for (i <- 0 until pushN) when (!valid(i)) { - regs(i) := push_shr(i) - } - } - - val out_data = (0 until popN).map { i => Mux(valid(i), regs(i), push_shr(i)) } - io.pop_data := VecInit(wshl(out_data, io.pop.bits.head).take(popN)) -} diff --git a/arch/src/main/scala/framework/gendomain/common/Consts.scala b/arch/src/main/scala/framework/gendomain/common/Consts.scala deleted file mode 100644 index e9efcd68..00000000 --- a/arch/src/main/scala/framework/gendomain/common/Consts.scala +++ /dev/null @@ -1,157 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import chisel3.util.experimental.decode._ - -object OPIFunct6 extends ChiselEnum { - val add = Value - val andn = Value - val sub, rsub, minu, min, maxu, max = Value - val _ = Value - val and, or, xor, rgather = Value - val _ = Value - val slideup, slidedown = Value - def rgatherei16 = slideup - - val adc = Value - val madc, sbc, msbc = Value - val ror, rol, _ = Value - val merge, mseq, msne, msltu, mslt, msleu, msle, msgtu, msgt = Value - - val saddu, sadd, ssubu, ssub = Value - val _ = Value - val sll = Value - val _ = Value - val smul = Value - def mvnrr = smul - val srl, sra, ssrl, ssra, nsrl, nsra, nclipu, nclip = Value - val wredsumu, wredsum = Value - val _, _, _ = Value - val wsll = Value - - val illegal = Value(0x40.U) -} - -object OPMFunct6 extends ChiselEnum { - val redsum, redand, redor, redxor, redminu, redmin, redmaxu, redmax, aaddu, aadd, asubu, asub = Value - val _, _ = Value - val slide1up, slide1down = Value - - val wrxunary0 = Value - val _ = Value - val xunary0 = Value - val _ = Value - val munary0 = Value - val _, _ = Value - val compress, mandnot, mand, mor, mxor, mornot, mnand, mnor, mxnor = Value - - val divu, div, remu, rem, mulhu, mul, mulhsu, mulh = Value - val _ = Value - val madd = Value - val _ = Value - val nmsub = Value - val _ = Value - val macc = Value - val _ = Value - val nmsac = Value - - val waddu, wadd, wsubu, wsub, wadduw, waddw, wsubuw, wsubw, wmulu = Value - val _ = Value - val wmulsu, wmul, wmaccu, wmacc, wmaccus, wmaccsu = Value - - val illegal = Value(0x40.U) -} - -object OPFFunct6 extends ChiselEnum { - val fadd, fredusum, fsub, fredosum, fmin, fredmin, fmax, fredmax, fsgnj, fsgnjn, fsgnjx = Value - val _, _, _ = Value - val fslide1up, fslide1down = Value - val wrfunary0 = Value - val _ = Value - val funary0, funary1 = Value - val _, _, _ = Value - val fmerge, mfeq, mfle = Value - val _ = Value - val mflt, mfne, mfgt = Value - val _ = Value - val mfge, fdiv, frdiv = Value - val _, _ = Value - val fmul = Value - val _, _ = Value - val frsub = Value - val fmadd, fnmadd, fmsub, fnmsub, fmacc, fnmacc, fmsac, fnmsac, fwadd, fwredusum, fwsub, fwredosum = Value - val fwaddw, _, fwsubw, _, fwmul, _, _, _, fwmacc, fwnmacc, fwmsac, fwnmsac = Value - val illegal = Value(0x40.U) -} - -trait HasVectorConsts { - def mopUnit = 0.U(2.W) - def mopUnordered = 1.U(2.W) - def mopStrided = 2.U(2.W) - def mopOrdered = 3.U(2.W) - - def lumopUnit = "b00000".U - def lumopWhole = "b01000".U - def lumopMask = "b01011".U - def lumopFF = "b10000".U - - - def sumopUnit = "b00000".U - def sumopWhole = "b01000".U - def sumopMask = "b01011".U - - def opcLoad = "b0000111".U - def opcStore = "b0100111".U - def opcVector = "b1010111".U - - def OPIVV = "b000".U(3.W) - def OPFVV = "b001".U(3.W) - def OPMVV = "b010".U(3.W) - def OPIVI = "b011".U(3.W) - def OPIVX = "b100".U(3.W) - def OPFVF = "b101".U(3.W) - def OPMVX = "b110".U(3.W) - def OPCFG = "b111".U(3.W) - - def X = BitPat("b?") - def N = BitPat("b0") - def Y = BitPat("b1") -} - -object VectorConsts extends HasVectorConsts - -object VecDecode extends HasVectorConsts { - def apply(funct3: UInt, funct6: UInt, default: Seq[BitPat], table: Seq[(EnumType, Seq[BitPat])]): Seq[UInt] = { - def enumToUInt(e: EnumType): Seq[UInt] = e match { - case v: OPIFunct6.Type => Seq(OPIVV, OPIVI, OPIVX).map { f3 => ((f3.litValue << 6) + v.litValue).U(9.W) } - case v: OPMFunct6.Type => Seq(OPMVV, OPMVX ).map { f3 => ((f3.litValue << 6) + v.litValue).U(9.W) } - case v: OPFFunct6.Type => Seq(OPFVV, OPFVF ).map { f3 => ((f3.litValue << 6) + v.litValue).U(9.W) } - } - val nElts = default.size - require(table.forall(_._2.size == nElts)) - - val elementsGrouped = table.map(_._2).transpose - val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => - require(elts.forall(_.getWidth == default.getWidth)) - default.getWidth - } - val resultWidth = elementWidths.sum - val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } - val truthTable = TruthTable(table.map(e => enumToUInt(e._1).map(u => (BitPat(u), e._2.reduce(_ ## _)))).flatten, default.reduce(_ ## _)) - val decoded = chisel3.util.experimental.decode.decoder(Cat(funct3(2,0), funct6(5,0)), truthTable) - elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toSeq - } - - - def applyBools(funct3: UInt, funct6: UInt, default: Seq[BitPat], table: Seq[(EnumType, Seq[BitPat])]): Seq[Bool] = apply( - funct3, funct6, default, table).map(_(0)) - - def apply(funct3: UInt, funct6: UInt, trues: Seq[EnumType], falses: Seq[EnumType]): Bool = applyBools( - funct3, funct6, Seq(BitPat.dontCare(1)), trues.map(e => (e, Seq(BitPat(true.B)))) ++ falses.map(e => (e, Seq(BitPat(false.B)))))(0) - def apply(funct3: UInt, funct6: UInt, trues: Seq[EnumType]): Bool = applyBools( - funct3, funct6, Seq(BitPat(false.B)), trues.map(e => (e, Seq(BitPat(true.B)))))(0) -} diff --git a/arch/src/main/scala/framework/gendomain/common/DCEQueue.scala b/arch/src/main/scala/framework/gendomain/common/DCEQueue.scala deleted file mode 100644 index 73340d25..00000000 --- a/arch/src/main/scala/framework/gendomain/common/DCEQueue.scala +++ /dev/null @@ -1,83 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.rocket.Instructions._ - -class DCEQueue[T <: Data]( - val gen: T, - val entries: Int, - val pipe: Boolean = false, - val flow: Boolean = false)(implicit val p: Parameters) extends Module { - require(entries > -1, "Queue must have non-negative number of entries") - require(entries != 0, "Use companion object Queue.apply for zero entries") - - val io = IO(new QueueIO(gen, entries, false) { - val peek = Output(Vec(entries, Valid(gen))) - }) - val valids = RegInit(VecInit.fill(entries)(false.B)) - val ram = Reg(Vec(entries, gen)) - val enq_ptr = Counter(entries) - val deq_ptr = Counter(entries) - val maybe_full = RegInit(false.B) - val ptr_match = enq_ptr.value === deq_ptr.value - val empty = ptr_match && !maybe_full - val full = ptr_match && maybe_full - val do_enq = WireDefault(io.enq.fire) - val do_deq = WireDefault(io.deq.fire) - - for (i <- 0 until entries) { - io.peek(i).bits := ram(i) - io.peek(i).valid := valids(i) - } - - when(do_deq) { - deq_ptr.inc() - valids(deq_ptr.value) := false.B - } - - when(do_enq) { - ram(enq_ptr.value) := io.enq.bits - valids(enq_ptr.value) := true.B - enq_ptr.inc() - } - - when(do_enq =/= do_deq) { - maybe_full := do_enq - } - - io.deq.valid := !empty - io.enq.ready := !full - - io.deq.bits := ram(deq_ptr.value) - - if (flow) { - when(io.enq.valid) { io.deq.valid := true.B } - when(empty) { - io.deq.bits := io.enq.bits - do_deq := false.B - when(io.deq.ready) { do_enq := false.B } - } - } - - if (pipe) { - when(io.deq.ready) { io.enq.ready := true.B } - } - - val ptr_diff = enq_ptr.value - deq_ptr.value - - if (isPow2(entries)) { - io.count := Mux(maybe_full && ptr_match, entries.U, 0.U) | ptr_diff - } else { - io.count := Mux( - ptr_match, - Mux(maybe_full, entries.asUInt, 0.U), - Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff) - ) - } -} diff --git a/arch/src/main/scala/framework/gendomain/common/Parameters.scala b/arch/src/main/scala/framework/gendomain/common/Parameters.scala deleted file mode 100644 index 6c89a602..00000000 --- a/arch/src/main/scala/framework/gendomain/common/Parameters.scala +++ /dev/null @@ -1,404 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.diplomacy.{BufferParams} -import framework.gendomain.exu._ - -object VectorParams { - - // minParams: - // For a very small area-efficient vector unit with iterative - // and element-wise functional units - def minParams = VectorParams() - - // refParams - // For a standard modestly capable small vector unit with - // SIMD functional units - def refParams = minParams.copy( - vlrobEntries = 4, - vlissqEntries = 3, - vsissqEntries = 3, - vxissqEntries = 3, - vatSz = 5, - useSegmentedIMul = true, - doubleBufferSegments = true, - useScalarFPFMA = false, - vrfBanking = 4, - ) - - // dspParams - // For a wide high-performance vector unit with multi-issue - def dspParams = refParams.copy( - issStructure = VectorIssueStructure.Shared - ) - - // genParams: - // For a vector unit that performs better on less-optimized - // code sequences - def genParams = dspParams.copy( - issStructure = VectorIssueStructure.Split, - vlifqEntries = 16, - vlrobEntries = 16 - ) - - // multiFMAParams: - // Provides a second sequencer and set of functional units for FMA operations - def multiFMAParams = genParams.copy( - issStructure = VectorIssueStructure.MultiFMA - ) - - // multiMACParams: - // Provides a second sequencer and set of functional units for integer MAC operations - def multiMACParams = genParams.copy( - issStructure = VectorIssueStructure.MultiMAC - ) - - // dmaParams: - // For a vector unit that only does memcpys, and no arithmetic - def dmaParams = VectorParams( - vdqEntries = 2, - vliqEntries = 4, - vsiqEntries = 4, - vlifqEntries = 32, - vlrobEntries = 4, - vsifqEntries = 32, - vlissqEntries = 2, - vsissqEntries = 1, - vrfBanking = 1, - useIterativeIMul = true - ) - - // The parameters below are approximations - - // hwaParams - // For a vector unit with limited sequencer slots akin to Hwacha - def hwaParams = genParams.copy( - vatSz = 3, // 8 mseq Entries - vdqEntries = 1, - vlissqEntries = 8, - vsissqEntries = 8, - vxissqEntries = 8, - vpissqEntries = 8, - hwachaLimiter = Some(8), // sequencer slots - ) - - // lgvParams - // For a vector unit with very long vector lengths - def lgvParams = VectorParams( - vatSz = 5, - vlifqEntries = 32, - vsifqEntries = 32, - vlrobEntries = 32, - vlissqEntries = 8, - vsissqEntries = 8, - vxissqEntries = 8, - vpissqEntries = 8, - useSegmentedIMul = true, - useScalarFPMisc = false, - useScalarFPFMA = false, - vrfBanking = 4, - issStructure = VectorIssueStructure.Split - ) -} - -case class VXSequencerParams( - name: String, - fus: Seq[FunctionalUnitFactory] -) { - def insns = fus.map(_.insns).flatten -} - -case class VXIssuePathParams( - name: String, - depth: Int, - seqs: Seq[VXSequencerParams] -) { - def insns = seqs.map(_.insns).flatten -} - -object VXFunctionalUnitGroups { - def integerFUs(idivDoesImul: Boolean = false) = Seq( - IntegerPipeFactory, - ShiftPipeFactory, - BitwisePipeFactory, - IntegerDivideFactory(idivDoesImul), - MaskUnitFactory, - PermuteUnitFactory - ) - def integerMAC(pipeDepth: Int, useSegmented: Boolean) = Seq( - IntegerMultiplyFactory(pipeDepth, useSegmented) - ) - - def allIntegerFUs(idivDoesImul: Boolean, imaDepth: Int, useSegmentedImul: Boolean) = ( - integerFUs(idivDoesImul) ++ integerMAC(imaDepth, useSegmentedImul) - ) - - def sharedFPFMA(pipeDepth: Int) = Seq( - FPFMAFactory(pipeDepth, true) - ) - def sharedFPMisc = Seq( - SharedFPMiscFactory - ) - def fpFMA(pipeDepth: Int) = Seq( - FPFMAFactory(pipeDepth, false) - ) - def fpMisc = Seq( - FPDivSqrtFactory, - FPCmpFactory, - FPConvFactory - ) - - def allFPFUs(fmaPipeDepth: Int, useScalarFPFMA: Boolean, useScalarFPMisc: Boolean) = ( - (if (useScalarFPFMA) sharedFPFMA(fmaPipeDepth) else fpFMA(fmaPipeDepth)) ++ - (if (useScalarFPMisc) sharedFPMisc else fpMisc) - ) -} - -sealed trait VectorIssueStructure { - def generate(params: VectorParams): Seq[VXIssuePathParams] -} - -object VectorIssueStructure { - import VXFunctionalUnitGroups._ - - case object Unified extends VectorIssueStructure { - def generate(params: VectorParams) = { - val fp_int_path = VXIssuePathParams( - name = "fp_int", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("fp_int", ( - allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul) ++ - allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc) - )) - ) - ) - Seq(fp_int_path) - } - } - - case object Shared extends VectorIssueStructure { - def generate(params: VectorParams) = { - val fp_int_path = VXIssuePathParams( - name = "fp_int", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), - VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) - ) - ) - Seq(fp_int_path) - } - } - - case object Split extends VectorIssueStructure { - def generate(params: VectorParams) = { - val int_path = VXIssuePathParams( - name = "int", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), - ) - ) - val fp_path = VXIssuePathParams( - name = "fp", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) - ) - ) - Seq(int_path, fp_path) - } - } - - case object MultiFMA extends VectorIssueStructure { - def generate(params: VectorParams) = { - require(!params.useScalarFPFMA) - val int_path = VXIssuePathParams( - name = "int", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), - ) - ) - val fp_path = VXIssuePathParams( - name = "fp", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("fp0", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)), - VXSequencerParams("fp1", fpFMA(params.fmaPipeDepth)) - ) - ) - Seq(int_path, fp_path) - } - } - - case object MultiMAC extends VectorIssueStructure { - def generate(params: VectorParams) = { - require(!params.useIterativeIMul && params.useSegmentedIMul) - val int_path = VXIssuePathParams( - name = "int", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("int0", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), - VXSequencerParams("int1", integerMAC(params.imaPipeDepth, params.useSegmentedIMul)) - ) - ) - val fp_path = VXIssuePathParams( - name = "fp", - depth = params.vxissqEntries, - seqs = Seq( - VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) - ) - ) - Seq(int_path, fp_path) - } - } -} - -case class VectorParams( - // In-order dispatch Queue - vdqEntries: Int = 4, - - // Load store instruction queues (in VLSU) - vliqEntries: Int = 4, - vsiqEntries: Int = 4, - - // Load store in-flight queues (in VLSU) - vlifqEntries: Int = 8, - vsifqEntries: Int = 16, - vlrobEntries: Int = 2, - - // Scatter-gather engine params - vsgPorts: Int = 8, - vsgifqEntries: Int = 4, - vsgBuffers: Int = 3, - - // Load/store/execute/permute/maskindex issue queues - vlissqEntries: Int = 0, - vsissqEntries: Int = 0, - vxissqEntries: Int = 0, - vpissqEntries: Int = 0, - - dLen: Int = 64, - vatSz: Int = 3, - - - useSegmentedIMul: Boolean = false, - useScalarFPFMA: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions - useScalarFPMisc: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions - useIterativeIMul: Boolean = false, - fmaPipeDepth: Int = 4, - imaPipeDepth: Int = 3, - - // for comparisons only - hazardingMultiplier: Int = 0, - hwachaLimiter: Option[Int] = None, - enableChaining: Boolean = true, - latencyInject: Boolean = false, - enableDAE: Boolean = true, - enableOOO: Boolean = true, - enableScalarVectorAddrDisambiguation: Boolean = true, - - doubleBufferSegments: Boolean = false, - - vrfBanking: Int = 2, - vrfHiccupBuffer: Boolean = true, - - issStructure: VectorIssueStructure = VectorIssueStructure.Unified, - - tlBuffer: BufferParams = BufferParams.default, -) { - def supported_ex_insns = issStructure.generate(this).map(_.insns).flatten -} - -case object VectorParamsKey extends Field[VectorParams] - -trait HasVectorParams extends HasVectorConsts { this: HasCoreParameters => - implicit val p: Parameters - def vParams: VectorParams = p(VectorParamsKey) - def dLen = vParams.dLen - def dLenB = dLen / 8 - def dLenOffBits = log2Ceil(dLenB) - def dmemTagBits = log2Ceil(vParams.vlifqEntries.max(vParams.vsifqEntries)) - def sgmemTagBits = log2Ceil(vParams.vsgifqEntries) - def egsPerVReg = vLen / dLen - def egsTotal = (vLen / dLen) * 32 - def vrfBankBits = log2Ceil(vParams.vrfBanking) - def lsiqIdBits = log2Ceil(vParams.vliqEntries.max(vParams.vsiqEntries)) - val debugIdSz = 16 - val nRelease = vParams.issStructure match { - case VectorIssueStructure.Unified => 3 - case VectorIssueStructure.Shared | VectorIssueStructure.Split => 4 - case VectorIssueStructure.MultiFMA | VectorIssueStructure.MultiMAC => 5 - } - - def getEgId(vreg: UInt, eidx: UInt, eew: UInt, bitwise: Bool): UInt = { - val base = vreg << log2Ceil(egsPerVReg) - val off = eidx >> Mux(bitwise, log2Ceil(dLen).U, (log2Ceil(dLenB).U - eew)) - base +& off - } - def getByteId(vreg: UInt, eidx: UInt, eew: UInt): UInt = { - Cat(getEgId(vreg, eidx, eew, false.B), (eidx << eew)(log2Ceil(dLenB)-1,0)) - } - - def eewByteMask(eew: UInt) = (0 until (1+log2Ceil(eLen/8))).map { e => - Mux(e.U === eew, ((1 << (1 << e)) - 1).U, 0.U) - }.reduce(_|_)((eLen/8)-1,0) - def eewBitMask(eew: UInt) = FillInterleaved(8, eewByteMask(eew)) - - - def cqOlder(i0: UInt, i1: UInt, tail: UInt) = (i0 < i1) ^ (i0 < tail) ^ (i1 < tail) - def dLenSplat(in: UInt, eew: UInt) = { - val v = Wire(UInt(64.W)) - v := in - Mux1H(UIntToOH(eew), (0 until 4).map { i => Fill(dLenB >> i, v((8< - Cat(in((8 << eew)-1), in((8 << eew)-1,0)).asSInt - })(in_eew)(64,0) - - def extractElem(in: UInt, in_eew: UInt, eidx: UInt): UInt = { - val bytes = in.asTypeOf(Vec(dLenB, UInt(8.W))) - VecInit.tabulate(4) { eew => - val elem = if (dLen == 64 && eew == 3) { - in - } else { - VecInit(bytes.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq)(eidx(log2Ceil(dLenB)-1-eew,0)) - } - elem((8 << eew)-1,0) - }(in_eew) - } - - def maxPosUInt(sew: Int) = Cat(0.U, ~(0.U(((8 << sew)-1).W))) - def minNegUInt(sew: Int) = Cat(1.U, 0.U(((8 << sew)-1).W)) - def maxPosSInt(sew: Int) = ((1 << ((8 << sew)-1))-1).S - def minNegSInt(sew: Int) = (-1 << ((8 << sew)-1)).S - def maxPosFPUInt(sew: Int) = { - val expBits = Seq(4, 5, 8, 11)(sew) - val fracBits = (8 << sew) - expBits - 1 - Cat(0.U, ~(0.U(expBits.W)), 0.U(fracBits.W)) - } - def minNegFPUInt(sew: Int) = { - val expBits = Seq(4, 5, 8, 11)(sew) - val fracBits = (8 << sew) - expBits - 1 - Cat(1.U, ~(0.U(expBits.W)), 0.U(fracBits.W)) - } - def get_arch_mask(reg: UInt, emul: UInt) = VecInit.tabulate(4)({ lmul => - FillInterleaved(1 << lmul, UIntToOH(reg >> lmul)((32>>lmul)-1,0)) - })(emul) - def log2_up(f: UInt, max: Int) = VecInit.tabulate(max)({nf => log2Ceil(nf+1).U})(f) - - def hazardMultiply(mask: UInt): UInt = if (vParams.hazardingMultiplier == 0) { mask } else { - require((1 << vParams.hazardingMultiplier) <= egsTotal) - VecInit(mask.asBools.grouped(1 << vParams.hazardingMultiplier).map { g => - Fill(1 << vParams.hazardingMultiplier, g.orR) - }.toSeq).asUInt - } -} diff --git a/arch/src/main/scala/framework/gendomain/common/ReorderBuffer.scala b/arch/src/main/scala/framework/gendomain/common/ReorderBuffer.scala deleted file mode 100644 index 005be980..00000000 --- a/arch/src/main/scala/framework/gendomain/common/ReorderBuffer.scala +++ /dev/null @@ -1,62 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.rocket.Instructions._ - -class ReorderBuffer[T <: Data]( - gen: => T, - val entries: Int)(implicit val p: Parameters) extends Module { - require(entries > -1, "Queue must have non-negative number of entries") - require(entries != 0, "Use companion object Queue.apply for zero entries") - - val tagBits = log2Ceil(entries) - val io = IO(new Bundle { - val reserve = Decoupled(UInt(tagBits.W)) - val push = Input(Valid(new Bundle { - val data = gen - val tag = UInt(tagBits.W) - })) - val deq = Decoupled(gen) - val busy = Output(Bool()) - }) - - val valids = RegInit(VecInit.fill(entries)(false.B)) - val ram = Reg(Vec(entries, gen)) - val enq_ptr = Counter(entries) - val deq_ptr = Counter(entries) - val maybe_full = RegInit(false.B) - val ptr_match = enq_ptr.value === deq_ptr.value - val empty = ptr_match && !maybe_full - val full = ptr_match && maybe_full - - io.busy := !empty - io.reserve.valid := !full - io.reserve.bits := enq_ptr.value - when (io.reserve.fire) { - enq_ptr.inc() - } - - when (io.push.fire) { - assert(!valids(io.push.bits.tag)) - valids(io.push.bits.tag) := !(io.deq.ready && deq_ptr.value === io.push.bits.tag) - ram(io.push.bits.tag) := io.push.bits.data - } - - io.deq.valid := !empty && (valids(deq_ptr.value) || (io.push.fire && io.push.bits.tag === deq_ptr.value)) - io.deq.bits := Mux(valids(deq_ptr.value), ram(deq_ptr.value), io.push.bits.data) - - when (io.deq.fire) { - deq_ptr.inc() - valids(deq_ptr.value) := false.B - } - - when (io.reserve.fire =/= io.deq.fire) { - maybe_full := io.reserve.fire - } -} diff --git a/arch/src/main/scala/framework/gendomain/common/ShiftPacker.scala b/arch/src/main/scala/framework/gendomain/common/ShiftPacker.scala deleted file mode 100644 index 81f2e030..00000000 --- a/arch/src/main/scala/framework/gendomain/common/ShiftPacker.scala +++ /dev/null @@ -1,59 +0,0 @@ -package framework.gendomain.common - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ - -class ShiftPackerReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val head = UInt(log2Ceil(dLenB).W) - val tail = UInt(log2Ceil(dLenB).W) - def count = Mux(tail === 0.U, dLenB.U, tail) - head -} - -class ShiftPacker(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val push = Flipped(Decoupled(new ShiftPackerReq)) - val push_data = Input(Vec(dLenB, UInt(8.W))) - - val pop = Flipped(Decoupled(new ShiftPackerReq)) - val pop_data = Output(Vec(dLenB, UInt(8.W))) - }) - - def wshr(in: Seq[UInt], shamt: UInt): Seq[UInt] = - (0 until in.size).map { i => VecInit(in.drop(i))(shamt) } - def wshl(in: Seq[UInt], shamt: UInt): Seq[UInt] = - wshr(in.reverse, shamt).reverse - - val count = RegInit(0.U(log2Ceil(dLenB).W)) - val regs = Seq.fill(dLenB) { Reg(UInt(8.W)) } - val valid = (1.U << count) - 1.U - - val may_forward = io.pop.bits.count > count - - io.push.ready := dLenB.U +& Mux(io.pop.valid, io.pop.bits.count, 0.U) >= count +& io.push.bits.count - io.pop.ready := count +& Mux(io.push.valid, io.push.bits.count, 0.U) >= io.pop.bits.count - - val regs_shr = wshr(regs, io.pop.bits.count) - val valid_shr = valid >> io.pop.bits.count - - when (io.push.fire || io.pop.fire) { - count := count +& Mux(io.push.fire, io.push.bits.count, 0.U) - Mux(io.pop.fire, io.pop.bits.count, 0.U) - } - - val push_shr = wshr((Seq.fill(dLenB)(0.U(8.W)) ++ io.push_data), dLenB.U +& io.push.bits.head - count) - val push_shr_pop = wshr((Seq.fill(dLenB)(0.U(8.W)) ++ io.push_data), dLenB.U +& io.push.bits.head +& io.pop.bits.count - count) - - when (io.pop.fire) { - for (i <- 0 until dLenB) regs(i) := Mux(valid_shr(i), regs_shr(i), push_shr_pop(i)) - } .elsewhen (io.push.fire) { - for (i <- 0 until dLenB) when (!valid(i)) { - regs(i) := push_shr(i) - } - } - - val out_data = (0 until dLenB).map { i => Mux(valid(i), regs(i), push_shr(i)) } - io.pop_data := VecInit(wshl(out_data, io.pop.bits.head)) -} diff --git a/arch/src/main/scala/framework/gendomain/exu/ExecutionUnit.scala b/arch/src/main/scala/framework/gendomain/exu/ExecutionUnit.scala deleted file mode 100644 index 28dae4c8..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/ExecutionUnit.scala +++ /dev/null @@ -1,173 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class ExecutionUnit(genFUs: Seq[FunctionalUnitFactory])(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val fus = genFUs.map(gen => Module(gen.generate(p))) - - val pipe_fus: Seq[PipelinedFunctionalUnit] = fus.collect { case p: PipelinedFunctionalUnit => p } - val iter_fus: Seq[IterativeFunctionalUnit] = fus.collect { case i: IterativeFunctionalUnit => i } - - val pipe_depth = (pipe_fus.map(_.depth) :+ 0).max - - val io = IO(new Bundle { - val iss = Flipped(Decoupled(new ExecuteMicroOp)) - val iter_hazards = Output(Vec(iter_fus.size, Valid(new PipeHazard(pipe_depth)))) - val iter_write = Decoupled(new VectorWrite(dLen)) - val pipe_write = Output(Valid(new VectorWrite(dLen))) - val acc_write = Output(Valid(new VectorWrite(dLen))) - val scalar_write = Decoupled(new ScalarWrite) - - val pipe_hazards = Output(Vec(pipe_depth, Valid(new PipeHazard(pipe_depth)))) - val issue_pipe_latency = Output(UInt((log2Ceil(pipe_depth) + 1).W)) - - val shared_fp_req = Decoupled(new FPInput()) - val shared_fp_resp = Flipped(Valid(new FPResult())) - - val set_vxsat = Output(Bool()) - val set_fflags = Output(Valid(UInt(5.W))) - val busy = Output(Bool()) - }) - - val sharedFPUnits = fus.collect { case fp: HasSharedFPUIO => fp } - val hasSharedFPUnits = sharedFPUnits.size > 0 - - io.shared_fp_req.valid := false.B - io.shared_fp_req.bits := DontCare - if (sharedFPUnits.size > 0) { - val shared_fp_arb = Module(new Arbiter(new FPInput, sharedFPUnits.size)) - for ((u, i) <- sharedFPUnits.zipWithIndex) { - val otherUnits = sharedFPUnits.zipWithIndex.filter(_._2 != i).map(_._1) - val other_busy = otherUnits.map(_.io_fp_active).orR - u.io_fp_req.ready := shared_fp_arb.io.in(i).ready && !other_busy - shared_fp_arb.io.in(i).valid := u.io_fp_req.valid && !other_busy - shared_fp_arb.io.in(i).bits := u.io_fp_req.bits - u.io_fp_resp := io.shared_fp_resp - } - io.shared_fp_req <> shared_fp_arb.io.out - } - - val pipe_stall = WireInit(false.B) - - fus.foreach { fu => - fu.io.iss.op := io.iss.bits - fu.io.iss.valid := io.iss.valid && !pipe_stall - } - - val pipe_write_hazard = WireInit(false.B) - val readies = fus.map(_.io.iss.ready) - io.iss.ready := readies.orR && !pipe_write_hazard && !pipe_stall - when (io.iss.valid) { assert(PopCount(readies) <= 1.U) } - - io.issue_pipe_latency := Mux1H(pipe_fus.map(_.io.iss.ready), pipe_fus.map(_.depth.U)) - - val pipe_write = WireInit(false.B) - - io.pipe_write.valid := false.B - io.pipe_write.bits := DontCare - io.iter_write.valid := false.B - io.iter_write.bits := DontCare - io.acc_write.valid := false.B - io.acc_write.bits := DontCare - io.busy := false.B - io.set_vxsat := fus.map(_.io.set_vxsat).orR - io.set_fflags.valid := fus.map(_.io.set_fflags.valid).orR - io.set_fflags.bits := fus.map(f => Mux(f.io.set_fflags.valid, f.io.set_fflags.bits, 0.U)).reduce(_|_) - - - val scalar_write_arb = Module(new Arbiter(new ScalarWrite, fus.size)) - scalar_write_arb.io.in.zip(fus.map(_.io.scalar_write)).foreach { case (l, r) => l <> r } - io.scalar_write <> scalar_write_arb.io.out - - if (pipe_fus.size > 0) { - val pipe_iss_depth = Mux1H(pipe_fus.map(_.io.iss.ready), pipe_fus.map(_.depth.U)) - - val pipe_valids = Seq.fill(pipe_depth)(RegInit(false.B)) - val pipe_sels = Seq.fill(pipe_depth)(Reg(UInt(pipe_fus.size.W))) - val pipe_bits = Seq.fill(pipe_depth)(Reg(new ExecuteMicroOp)) - val pipe_latencies = Seq.fill(pipe_depth)(Reg(UInt(log2Ceil(pipe_depth).W))) - - pipe_stall := Mux1H(pipe_sels.head, pipe_fus.map(_.io.pipe0_stall)) - - pipe_write_hazard := (0 until pipe_depth).map { i => - pipe_valids(i) && pipe_latencies(i) === pipe_iss_depth - }.orR - - val pipe_iss = io.iss.fire && pipe_fus.map(_.io.iss.ready).orR - when (!pipe_stall) { - pipe_valids.head := pipe_iss - when (pipe_iss) { - pipe_bits.head := io.iss.bits - pipe_latencies.head := pipe_iss_depth - 1.U - pipe_sels.head := VecInit(pipe_fus.map(_.io.iss.ready)).asUInt - } - } - for (i <- 1 until pipe_depth) { - val fire = pipe_valids(i-1) && pipe_latencies(i-1) =/= 0.U && !((i == 1).B && pipe_stall) - pipe_valids(i) := fire - when (fire) { - pipe_bits(i) := pipe_bits(i-1) - pipe_latencies(i) := pipe_latencies(i-1) - 1.U - pipe_sels(i) := pipe_sels(i-1) - } - } - for ((fu, j) <- pipe_fus.zipWithIndex) { - for (i <- 0 until fu.depth) { - fu.io.pipe(i).valid := pipe_valids(i) && pipe_sels(i)(j) - fu.io.pipe(i).bits := Mux(pipe_valids(i) && pipe_sels(i)(j), - pipe_bits(i), 0.U.asTypeOf(new ExecuteMicroOp)) - } - } - - val write_sel = pipe_valids.zip(pipe_latencies).map { case (v,l) => v && l === 0.U } - val fu_sel = Mux1H(write_sel, pipe_sels) - pipe_write := write_sel.orR - when (write_sel.orR) { - val acc = Mux1H(write_sel, pipe_bits.map(_.acc)) - val tail = Mux1H(write_sel, pipe_bits.map(_.tail)) - io.pipe_write.valid := Mux1H(fu_sel, pipe_fus.map(_.io.write.valid)) && (!acc || tail) - io.pipe_write.bits := Mux1H(fu_sel, pipe_fus.map(_.io.write.bits)) - io.acc_write.valid := acc && !tail - io.acc_write.bits := Mux1H(fu_sel, pipe_fus.map(_.io.write.bits)) - } - - when (pipe_valids.orR) { io.busy := true.B } - for (i <- 0 until pipe_depth) { - io.pipe_hazards(i).valid := pipe_valids(i) - io.pipe_hazards(i).bits.eg := pipe_bits(i).wvd_eg - when (pipe_latencies(i) === 0.U) { // hack to deal with compress unit - io.pipe_hazards(i).bits.eg := Mux1H(pipe_sels(i), pipe_fus.map(_.io.write.bits.eg)) - } - io.pipe_hazards(i).bits.latency := pipe_latencies(i) - } - } - - if (iter_fus.size > 0) { - val iter_write_arb = Module(new Arbiter(new VectorWrite(dLen), iter_fus.size)) - iter_write_arb.io.in.zip(iter_fus.map(_.io.write)).foreach { case (l,r) => l <> r } - iter_write_arb.io.out.ready := !pipe_write && io.iter_write.ready - - val acc = Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.acc)) - val tail = Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.tail)) - io.iter_write.valid := iter_write_arb.io.out.valid && (!acc || tail) && !pipe_write - io.iter_write.bits.eg := iter_write_arb.io.out.bits.eg - io.iter_write.bits.mask := iter_write_arb.io.out.bits.mask - io.iter_write.bits.data := iter_write_arb.io.out.bits.data - when (!pipe_write) { - io.acc_write.valid := iter_write_arb.io.out.valid && acc - io.acc_write.bits.eg := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.eg)) - io.acc_write.bits.data := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.data)) - io.acc_write.bits.mask := Mux1H(iter_write_arb.io.in.map(_.fire), iter_fus.map(_.io.write.bits.mask)) - } - when (iter_fus.map(_.io.busy).orR) { io.busy := true.B } - for (i <- 0 until iter_fus.size) { - io.iter_hazards(i) := iter_fus(i).io.hazard - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/exu/FunctionalUnit.scala b/arch/src/main/scala/framework/gendomain/exu/FunctionalUnit.scala deleted file mode 100644 index 27b2f7f4..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/FunctionalUnit.scala +++ /dev/null @@ -1,84 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns.{VectorInstruction} - -abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val iss = new Bundle { - val valid = Input(Bool()) - val op = Input(new ExecuteMicroOp) - val ready = Output(Bool()) - } - - val scalar_write = Decoupled(new ScalarWrite) - val set_vxsat = Output(Bool()) - val set_fflags = Output(Valid(UInt(5.W))) -} - -class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { - val write = Valid(new VectorWrite(dLen)) - val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) - val pipe0_stall = Output(Bool()) -} - -class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { - val write = Decoupled(new VectorWrite(dLen)) - val hazard = Output(Valid(new PipeHazard(10))) - val acc = Output(Bool()) - val tail = Output(Bool()) - - val busy = Output(Bool()) -} - -trait FunctionalUnitFactory { - def insns: Seq[VectorInstruction] - def generate(implicit p: Parameters): FunctionalUnit -} - -abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io: FunctionalUnitIO -} - -abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { - val io = IO(new PipelinedFunctionalUnitIO(depth)) - - require (depth > 0) - - def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { - val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } - for (eew <- 0 until 3) { - val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq - for (i <- 0 until dLenB >> (eew + 1)) { - val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) - val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) - narrow_eew(eew)(i) := Cat(hi, lo) - } - } - VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) - } -} - -abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { - val io = IO(new IterativeFunctionalUnitIO) - - val valid = RegInit(false.B) - val op = Reg(new ExecuteMicroOp) - val last = Wire(Bool()) - - io.busy := valid - - io.hazard.bits.latency := DontCare - - when (io.iss.valid && io.iss.ready) { - valid := true.B - op := io.iss.op - } .elsewhen (last) { - valid := false.B - } -} diff --git a/arch/src/main/scala/framework/gendomain/exu/MaskUnit.scala b/arch/src/main/scala/framework/gendomain/exu/MaskUnit.scala deleted file mode 100644 index 97a5088d..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/MaskUnit.scala +++ /dev/null @@ -1,134 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case object MaskUnitFactory extends FunctionalUnitFactory { - def insns = Seq(MV_S_X, MV_X_S, POPC, FIRST, FMV_S_F, FMV_F_S, MSBF, MSOF, MSIF, IOTA, ID) - def generate(implicit p: Parameters) = new MaskUnit()(p) -} - -class MaskUnit(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { - val supported_insns = MaskUnitFactory.insns - - val scalar_wb_busy = RegInit(false.B) - val scalar_wb_data = Reg(UInt(64.W)) - val scalar_wb_rd = Reg(UInt(5.W)) - val scalar_wb_fp = Reg(Bool()) - val scalar_wb_size = Reg(UInt(2.W)) - val found_first = Reg(Bool()) - - def accepts(op: ExecuteMicroOp): Bool = (op.opff6.isOneOf(OPFFunct6.wrfunary0) || op.opmf6.isOneOf(OPMFunct6.wrxunary0, OPMFunct6.munary0)) && !scalar_wb_busy - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, io.iss.op.rs1, io.iss.op.rs2, supported_insns, Nil).matched && !scalar_wb_busy && !io.pipe(0).bits.tail - - io.set_vxsat := false.B - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - - val op = io.pipe(0).bits - val opmvv = op.funct3 === OPMVV - val opmvx = op.funct3 === OPMVX - val opfvv = op.funct3 === OPFVV - val opfvf = op.funct3 === OPFVF - - val wxunary0 = opmvv && !op.funct6(2) - val rxunary0 = opmvx - val wfunary0 = opfvv - val rfunary0 = opfvf - val munary0 = opmvv && op.funct6(2) - - val set_before = op.rs1.isOneOf(1.U, 3.U) - val set_first = op.rs1.isOneOf(2.U, 3.U) - - val elems = (op.rvs2_data & op.rvm_data & op.full_tail_mask) - val popc = PopCount(elems) - val ff = PriorityEncoder(elems) - val ff_oh = PriorityEncoderOH(elems) - val bf = ~((0 until dLen).map { i => (elems << i)(dLen-1,0) }.reduce(_|_)) - val nonzero = elems =/= 0.U - val first_here = (!found_first || op.head) && nonzero - val before = Mux(found_first && !op.head, 0.U, Mux(nonzero, bf, ~(0.U(dLen.W)))) - val first = Mux(first_here, ff_oh, 0.U) - val set = Mux(set_before, before, 0.U) | Mux(set_first, first, 0.U) - val sign = VecInit.tabulate(4)({sew => op.rvs2_data((8 << sew)-1)})(op.rvs2_eew) - val eew_mask = eewBitMask(op.rvs2_eew).pad(64) - val elem = (op.rvs2_data & eew_mask) | (Fill(64, sign && op.isOpm) & ~eew_mask) - val scalar_wb_rdata = Mux(op.head, 0.U, scalar_wb_data) - - val iota_dlenb = VecInit.tabulate(4)({sew => - val grouped = Mux(op.rs1(0), ~(0.U(dLen.W)), elems).asTypeOf(Vec(8 << sew, UInt((dLenB >> sew).W))) - grouped(op.eidx(log2Ceil(dLen)-1,log2Ceil(dLenB) - sew)) - })(op.rvd_eew) - val iota_sums = (0 until dLenB).map { i => - (PopCount(iota_dlenb & ((1< - val out = Wire(Vec(dLenB >> sew, UInt((8<> sew) - out.asUInt - })(op.vd_eew) - - when (io.pipe(0).valid) { - scalar_wb_rd := io.pipe(0).bits.rd - scalar_wb_size := io.pipe(0).bits.rvs2_eew - when (op.head) { - found_first := false.B - scalar_wb_data := 0.U - } - when (first_here) { found_first := true.B } - when (wxunary0) { - when (op.rs1 === 16.U) { // popc - scalar_wb_data := (scalar_wb_rdata + popc)(log2Ceil(maxVLMax),0) - } .elsewhen (op.rs1 === 17.U) { // first - when (first_here) { - scalar_wb_data := op.eidx + ff - } .elsewhen (!found_first || op.head) { - scalar_wb_data := ~(0.U(64.W)) - } - } .otherwise { // mv - scalar_wb_data := elem - } - } - when (wfunary0) { // fmv - scalar_wb_data := elem - } - when (munary0) { - val mask = VecInit.tabulate(4)({sew => ~(0.U((dLenB >> sew).W))})(op.vd_eew) - val incr = PopCount(iota_dlenb & mask) - scalar_wb_data := (scalar_wb_rdata + incr)(log2Ceil(maxVLMax),0) - } - when (op.tail) { - scalar_wb_busy := wxunary0 || wfunary0 - scalar_wb_fp := wfunary0 - } - } - - io.scalar_write.valid := scalar_wb_busy - io.scalar_write.bits.data := scalar_wb_data - io.scalar_write.bits.rd := scalar_wb_rd - io.scalar_write.bits.fp := scalar_wb_fp - io.scalar_write.bits.size := scalar_wb_size - - io.pipe0_stall := false.B - io.write.valid := io.pipe(0).valid && (rxunary0 || rfunary0 || munary0) - io.write.bits.eg := op.wvd_eg - io.write.bits.mask := Mux1H(Seq( - (rxunary0 || rfunary0 , eewBitMask(op.vd_eew)), - (munary0 && op.rs1(4) , FillInterleaved(8, op.wmask)), - (munary0 && !op.rs1(4), op.full_tail_mask & op.rvm_data) - )) - io.write.bits.data := Mux1H(Seq( - (rxunary0 || rfunary0 , op.rvs1_data(63,0)), - (munary0 && op.rs1(4) , iota_out), - (munary0 && !op.rs1(4), set) - )) - - when (io.scalar_write.fire) { scalar_wb_busy := false.B } -} diff --git a/arch/src/main/scala/framework/gendomain/exu/PermuteUnit.scala b/arch/src/main/scala/framework/gendomain/exu/PermuteUnit.scala deleted file mode 100644 index 41dd681d..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/PermuteUnit.scala +++ /dev/null @@ -1,95 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case object PermuteUnitFactory extends FunctionalUnitFactory { - def insns = Seq( - SLIDEUP.VI, SLIDEUP.VX, SLIDEDOWN.VI, SLIDEDOWN.VX, - SLIDE1UP.VX, SLIDE1DOWN.VX, FSLIDE1UP.VF, FSLIDE1DOWN.VF, - RGATHER_VV, RGATHER_VI, RGATHER_VX, - RGATHEREI16, COMPRESS.VV, - MVNRR - ) - - def generate(implicit p: Parameters) = new PermuteUnit()(p) -} - -class PermuteUnit(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { - val supported_insns = PermuteUnitFactory.insns - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, io.iss.op.rs1, io.iss.op.rs2, - supported_insns, Nil).matched - - val wvd_reg = Reg(UInt(5.W)) - val result_reg = Reg(UInt(64.W)) - - val mvnrr = io.pipe(0).bits.funct3 === OPIVV && io.pipe(0).bits.opif6 === OPIFunct6.mvnrr - val compress = io.pipe(0).bits.opmf6 === OPMFunct6.compress - val rgatherei16 = io.pipe(0).bits.funct3 === OPIVV && io.pipe(0).bits.opif6 === OPIFunct6.rgatherei16 - val rgather = io.pipe(0).bits.opif6 === OPIFunct6.rgather || rgatherei16 - - - val index_eew = Mux(rgatherei16, 1.U, io.pipe(0).bits.rvs2_eew) - val elem_eidx = Mux(rgather, io.pipe(0).bits.rvs1_data, io.pipe(0).bits.eidx) - val elem = VecInit.tabulate(4)({sew => if (sew == 3 && dLenB == 8) { - io.pipe(0).bits.rvs2_data - } else { - io.pipe(0).bits.rvs2_data.asTypeOf(Vec(dLenB >> sew, UInt((8 << sew).W)))(elem_eidx) - }})(io.pipe(0).bits.rvs2_eew) - val rgather_elem = Mux(io.pipe(0).bits.head || io.pipe(0).bits.funct3 === OPIVV, elem, result_reg) - val splat = dLenSplat(Mux(compress, elem, rgather_elem), io.pipe(0).bits.rvs2_eew) - - val compress_wvd = Mux(io.pipe(0).bits.head, io.pipe(0).bits.wvd_eg >> log2Ceil(egsPerVReg), wvd_reg) - val compress_bit = (io.pipe(0).bits.rvs1_data >> io.pipe(0).bits.eidx(log2Ceil(dLen)-1,0))(0) - val compress_eidx = Mux(io.pipe(0).bits.head, 0.U, result_reg)(log2Ceil(maxVLMax),0) - - when (io.pipe(0).valid && io.pipe(0).bits.head && rgather) { - result_reg := elem - } - when (io.pipe(0).valid && io.pipe(0).bits.head) { - wvd_reg := io.pipe(0).bits.wvd_eg >> log2Ceil(egsPerVReg) - } - when (io.pipe(0).valid && compress) { - result_reg := (compress_eidx + compress_bit)(log2Ceil(maxVLMax),0) - } - - val shifted_mask_eidx = Mux(compress, compress_eidx, io.pipe(0).bits.vl - 1.U) - val shifted_mask = VecInit.tabulate(4)({sew => if (sew == 3 && dLenB == 8) { ~(0.U(8.W)) } else { - FillInterleaved(1 << sew, UIntToOH(shifted_mask_eidx(dLenOffBits-sew-1,0))) - }})(io.pipe(0).bits.rvs2_eew) - - - val slide_up = !io.pipe(0).bits.funct6(0) - val slide1 = !io.pipe(0).bits.isOpi - val slide1up_mask = eewByteMask(io.pipe(0).bits.rvs2_eew) - val slide1_mask = Mux(slide_up, - Mux(io.pipe(0).bits.head, slide1up_mask, 0.U), - Mux(io.pipe(0).bits.tail, shifted_mask, 0.U)) - val use_rvs1_mask = FillInterleaved(8, Mux(slide1, slide1_mask, 0.U).pad(dLenB)) - - val wmask = Mux(mvnrr, ~(0.U(dLenB.W)), - Mux(compress, Mux(compress_bit, shifted_mask, 0.U), io.pipe(0).bits.wmask)) - - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.set_vxsat := false.B - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - - io.pipe0_stall := false.B - io.write.valid := io.pipe(0).valid && (!compress || compress_bit) - io.write.bits.eg := Mux(compress, - getEgId(compress_wvd, compress_eidx, io.pipe(0).bits.rvs2_eew, false.B), - io.pipe(0).bits.wvd_eg) - io.write.bits.mask := FillInterleaved(8, wmask) - io.write.bits.data := Mux(rgather || compress, - splat, - (io.pipe(0).bits.rvs2_data & ~use_rvs1_mask) | (io.pipe(0).bits.rvs1_data & use_rvs1_mask)) -} diff --git a/arch/src/main/scala/framework/gendomain/exu/Rounding.scala b/arch/src/main/scala/framework/gendomain/exu/Rounding.scala deleted file mode 100644 index a2373081..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/Rounding.scala +++ /dev/null @@ -1,21 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ - -object RoundingIncrement { - - def apply(vxrm: UInt, v_d: Bool, v_d1: Bool, v_d20: Option[UInt]): Bool = MuxLookup(vxrm(1,0), false.B)(Seq( - (0.U -> (v_d1)), - (1.U -> (v_d1 && (v_d20.map(_ =/= 0.U).getOrElse(false.B) || v_d))), - (2.U -> (false.B)), - (3.U -> (!v_d && Cat(v_d1, v_d20.getOrElse(false.B)) =/= 0.U)) - )) - - def apply(vxrm: UInt, bits: UInt): UInt = { - val w = bits.getWidth - val d = w - 1 - require(w >= 2) - apply(vxrm, bits(d), bits(d-1), if (w > 2) Some(bits(d-2,0)) else None) - } -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/ElementwiseFPU.scala b/arch/src/main/scala/framework/gendomain/exu/fp/ElementwiseFPU.scala deleted file mode 100644 index 655e3b88..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/ElementwiseFPU.scala +++ /dev/null @@ -1,326 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - - -class ElementwiseFPUFMA(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) with HasFPUParameters { - val io_fp_req = IO(Decoupled(new FPInput())) - val io_fp_resp = IO(Flipped(Valid(new FPResult()))) - - val supported_insns = Seq( - FADD.VV, FADD.VF, FSUB.VV, FSUB.VF, FRSUB.VF, - FMUL.VV, FMUL.VF, - FMACC.VV, FMACC.VF, FNMACC.VV, FNMACC.VF, - FMSAC.VV, FMSAC.VF, FNMSAC.VV, FNMSAC.VF, - FMADD.VV, FMADD.VF, FNMADD.VV, FNMADD.VF, - FMSUB.VV, FMSUB.VF, FNMSUB.VV, FNMSUB.VF, - FWADD.VV, FWADD.VF, FWSUB.VV, FWSUB.VF, - FWADDW.VV, FWADDW.VF, FWSUBW.VV, FWSUBW.VF, - FWMUL.VV, FWMUL.VF, - FWMACC.VV, FWMACC.VF, FWNMACC.VV, FWNMACC.VF, - FWMSAC.VV, FWMSAC.VF, FWNMSAC.VV, FWNMSAC.VF, - FREDOSUM.VV, FREDUSUM.VV, FWREDOSUM.VV, FWREDUSUM.VV, - ).map(_.elementWise) - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( - FPAdd, FPMul, FPSwapVdV2, FPFMACmd, ReadsVD, FPSpecRM, Wide2VD, Wide2VS2, Reduction)) - - val vs1_eew = io.pipe(0).bits.rvs1_eew - val vs2_eew = io.pipe(0).bits.rvs2_eew - val vd_eew = io.pipe(0).bits.vd_eew - val vd_eew64 = io.pipe(0).bits.vd_eew64 - val eidx = Mux(io.pipe(0).bits.acc, 0.U, io.pipe(0).bits.eidx) - - // Functional unit is ready if not currently running and the scalar FPU is available - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched && io_fp_req.ready - - // Create FPInput - val req = Wire(new FPInput) - req.ldst := false.B - req.wen := false.B - req.ren1 := true.B - req.ren2 := true.B - req.ren3 := ctrl.bool(ReadsVD) - req.swap12 := false.B - req.swap23 := ctrl.bool(FPAdd) && !ctrl.bool(FPMul) - req.typeTagIn := Mux(vd_eew64, D, S) - req.typeTagOut := Mux(vd_eew64, D, S) - req.fromint := false.B - req.toint := false.B - req.fastpipe := false.B - req.fma := true.B - req.div := false.B - req.sqrt := false.B - req.wflags := true.B - req.vec := true.B - req.rm := io.pipe(0).bits.frm - req.fmaCmd := ctrl.uint(FPFMACmd) - req.typ := 0.U - req.fmt := 0.U - - val rvs2_elem = io.pipe(0).bits.rvs2_elem - val rvs1_elem = io.pipe(0).bits.rvs1_elem - val rvd_elem = io.pipe(0).bits.rvd_elem - - val s_rvs2 = FType.S.recode(rvs2_elem(31,0)) - val s_rvs1 = FType.S.recode(rvs1_elem(31,0)) - val s_rvd = FType.S.recode(rvd_elem(31,0)) - - // For widening operations, widen the narrow operands to compute with the scalar FPU - val widen_rvs1 = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53)) - widen_rvs1.io.in := s_rvs1 - widen_rvs1.io.roundingMode := io.pipe(0).bits.frm - widen_rvs1.io.detectTininess := hardfloat.consts.tininess_afterRounding - - val widen_rvs2 = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53)) - widen_rvs2.io.in := s_rvs2 - widen_rvs2.io.roundingMode := io.pipe(0).bits.frm - widen_rvs2.io.detectTininess := hardfloat.consts.tininess_afterRounding - - val d_rvs2 = FType.D.recode(rvs2_elem) - val d_rvs1 = FType.D.recode(rvs1_elem) - val d_rvd = FType.D.recode(rvd_elem) - - val rvs2_recoded_elem = Mux(vd_eew64, d_rvs2, s_rvs2) - val rvs1_recoded_elem = Mux(vd_eew64, d_rvs1, s_rvs1) - val rvd_recoded_elem = Mux(vd_eew64, d_rvd, s_rvd) - - // Set req.in1 - when (ctrl.bool(FPSwapVdV2)) { - req.in1 := rvd_recoded_elem - } .elsewhen (vs2_eew === 3.U) { - req.in1 := d_rvs2 - } .elsewhen (ctrl.bool(Wide2VD)) { - req.in1 := widen_rvs2.io.out - } .otherwise { - req.in1 := s_rvs2 - } - - // Set req.in2 - when (vs1_eew === 3.U) { - req.in2 := d_rvs1 - } .elsewhen (ctrl.bool(Wide2VD) && !io.pipe(0).bits.acc) { - req.in2 := widen_rvs1.io.out - } .otherwise { - req.in2 := s_rvs1 - } - - // Set req.in3 - when (ctrl.bool(FPSwapVdV2)) { - req.in3 := rvs2_recoded_elem - } .otherwise { - req.in3 := rvd_recoded_elem - } - - io_fp_req.bits := req - io_fp_req.valid := io.pipe(0).valid - - io.write.valid := io.pipe(depth-1).valid - io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg - io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) - io.write.bits.data := Fill(dLenB >> 3, Mux(io.pipe(depth-1).bits.vd_eew === 3.U, FType.D.ieee(io_fp_resp.bits.data), Fill(2, FType.S.ieee(unbox(io_fp_resp.bits.data, 0.U, Some(FType.S)))))) - - io.set_fflags := DontCare - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.set_vxsat := false.B - io.pipe0_stall := false.B -} - - -class ElementwiseFPU(implicit p: Parameters) extends IterativeFunctionalUnit()(p) with HasFPUParameters { - val io_fp_req = IO(Decoupled(new FPInput())) - val io_fp_resp = IO(Flipped(Valid(new FPResult()))) - - val supported_insns = Seq( - FDIV.VV, FDIV.VF, - FRDIV.VF, - FSQRT_V, - FRSQRT7_V, - FREC7_V, - FCLASS_V, - FMIN.VV, FMIN.VF, FMAX.VV, FMAX.VF, - FSGNJ.VV, FSGNJ.VF, FSGNJN.VV, FSGNJN.VF, FSGNJX.VV, FSGNJX.VF, - MFEQ.VV, MFEQ.VF, MFNE.VV, MFNE.VF, - MFLT.VV, MFLT.VF, MFLE.VV, MFLE.VF, - MFGT.VF, MFGE.VF, - FREDMIN.VV, FREDMAX.VV, - FCVT_SGL, FCVT_WID, FCVT_NRW - ).map(_.elementWise) - - val ctrl = new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Seq( - FPSwapVdV2, ReadsVD, WritesAsMask, FPSgnj, FPComp, FPSpecRM, FPMNE, FPMGT, Wide2VD, Wide2VS2, Reduction)) - - val vs1_eew = io.iss.op.rvs1_eew - val vs2_eew = io.iss.op.rvs2_eew - val vd_eew = io.iss.op.vd_eew - val vd_eew64 = io.iss.op.vd_eew64 - val eidx = Mux(io.iss.op.acc, 0.U, io.iss.op.eidx) - - val ctrl_isDiv = io.iss.op.opff6.isOneOf(OPFFunct6.fdiv, OPFFunct6.frdiv) - val ctrl_funary0 = io.iss.op.opff6.isOneOf(OPFFunct6.funary0) - val ctrl_funary1 = io.iss.op.opff6.isOneOf(OPFFunct6.funary1) - val ctrl_vfclass = ctrl_funary1 && (io.iss.op.rs1 === 16.U) - val ctrl_swap12 = io.iss.op.opff6.isOneOf(OPFFunct6.frdiv) - - val rs1 = io.iss.op.rs1 - val ctrl_widen = ctrl_funary0 && rs1(3) - val ctrl_narrow = rs1(4) - val ctrl_single_wide = ctrl_funary0 && !ctrl_widen && !ctrl_narrow - val ctrl_signed = rs1(0) - val ctrl_truncating = rs1(2) && rs1(1) - val ctrl_round_to_odd = rs1(0) - val ctrl_fptoint = ctrl_funary0 && ((!rs1(2) && !rs1(1)) || (rs1(2) && rs1(1))) - val ctrl_inttofp = ctrl_funary0 && (!rs1(2) && rs1(1)) - val ctrl_fptofp = ctrl_funary0 && (rs1(2) && !rs1(1)) - - val vfclass_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 16.U && valid - val vfrsqrt7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 4.U && valid - val vfrec7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 5.U && valid - - // Functional unit is ready if not currently running and the scalar FPU is available - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched && !valid && io_fp_req.ready - - io.hazard.valid := valid - io.hazard.bits.eg := op.wvd_eg - - val has_wdata = Reg(Bool()) - val wdata = Reg(UInt(64.W)) - when (io.iss.valid && io.iss.ready) { - has_wdata := false.B - } - - // Create FPInput - val req = Wire(new FPInput) - req.ldst := false.B - req.wen := false.B - req.ren1 := true.B - req.ren2 := !(ctrl_funary0 || ctrl_funary1) - req.ren3 := false.B - req.swap12 := false.B - req.swap23 := false.B - req.typeTagIn := Mux(((ctrl_single_wide || !ctrl_funary0) && vd_eew64) || (ctrl_inttofp && ctrl_widen) || (ctrl_fptofp && ctrl_narrow), D, S) - req.typeTagOut := Mux(((ctrl_single_wide || !ctrl_funary0) && vd_eew64) || (ctrl_fptoint && ctrl_narrow) || (ctrl_fptofp && ctrl_widen) || (ctrl_inttofp && ctrl_widen), D, S) - req.fromint := ctrl_inttofp - req.toint := (ctrl_fptoint) || ctrl_vfclass || ctrl.bool(WritesAsMask) - req.fastpipe := ctrl_fptofp || ctrl.bool(FPSgnj) || ctrl.bool(FPComp) - req.fma := false.B - req.div := ctrl_isDiv - req.sqrt := ctrl_funary1 && (rs1 === 0.U) - req.wflags := !ctrl_vfclass && !ctrl.bool(FPSgnj) - req.vec := true.B - req.rm := Mux(ctrl_fptofp && ctrl_round_to_odd, "b110".U, Mux((!ctrl_isDiv && !ctrl_funary1 && !ctrl_funary0) || ctrl_vfclass, ctrl.uint(FPSpecRM), io.iss.op.frm)) - req.fmaCmd := 0.U - req.typ := Mux(ctrl_funary0, Cat((ctrl_inttofp && ctrl_narrow) || (ctrl_fptoint && ctrl_widen) || (ctrl_single_wide && vd_eew64), !ctrl_signed), 0.U) - req.fmt := 0.U - - val rvs2_elem = io.iss.op.rvs2_elem - val rvs1_elem = io.iss.op.rvs1_elem - val rvd_elem = io.iss.op.rvd_elem - - val s_rvs2_int = rvs2_elem(31,0) - val s_rvs2_fp = FType.S.recode(Mux(ctrl_funary0 && ctrl_truncating, rvs2_elem(31,22) << 22, rvs2_elem(31,0))) - val s_rvs2_unbox = unbox(box(s_rvs2_fp, FType.S), S, None) - - val s_rvs1 = FType.S.recode(rvs1_elem(31,0)) - val s_rvs1_unbox = unbox(box(s_rvs1, FType.S), S, None) - val s_rvd = FType.S.recode(rvd_elem(31,0)) - - val d_rvs2_int = rvs2_elem - val d_rvs2_fp = FType.D.recode(Mux(ctrl_funary0 && ctrl_truncating, rvs2_elem(63, 51) << 51, rvs2_elem)) - - val d_rvs1 = FType.D.recode(rvs1_elem) - val d_rvd = FType.D.recode(rvd_elem) - - val s_isNaN = FType.S.isNaN(s_rvs2_fp) || FType.S.isNaN(s_rvs1) - val d_isNaN = FType.D.isNaN(d_rvs2_fp) || FType.D.isNaN(d_rvs1) - - val mgt_NaN = ctrl.bool(WritesAsMask) && ctrl.bool(FPMGT) && ((vd_eew64 && d_isNaN) || (io.iss.op.vd_eew32 && s_isNaN)) - val mgt_NaN_reg = RegInit(false.B) - - when (io.iss.ready && io.iss.valid && mgt_NaN) { - mgt_NaN_reg := true.B - } .elsewhen (io.write.fire) { - mgt_NaN_reg := false.B - } - - // Set req.in1 - when (ctrl_swap12) { - req.in1 := Mux(vd_eew64, d_rvs1, s_rvs1_unbox) - } .elsewhen (ctrl_inttofp) { - req.in1 := Mux((vd_eew64 && !ctrl_widen) || (ctrl_funary0 && ctrl_narrow), d_rvs2_int, s_rvs2_int) - } .otherwise { - req.in1 := Mux((vd_eew64 && !ctrl_widen) || (ctrl_funary0 && ctrl_narrow), d_rvs2_fp, s_rvs2_unbox) - } - - // Set req.in2 - when (ctrl_swap12) { - req.in2 := Mux(vd_eew64, d_rvs2_fp, s_rvs2_unbox) - } .otherwise { - req.in2 := Mux(vd_eew64, d_rvs1, s_rvs1_unbox) - } - - // Set req.in3 - req.in3 := 0.U - - io_fp_req.bits := req - io_fp_req.valid := (io.iss.valid && io.iss.ready) && !vfrsqrt7_inst && !vfrec7_inst && !mgt_NaN - - // Approximation Instructions - val rvs2_op_bits = op.rvs2_elem - - // Reciprocal Sqrt Approximation - val recSqrt7 = Module(new VFRSQRT7) - recSqrt7.io.rvs2_input := rvs2_op_bits - recSqrt7.io.eew := op.rvs2_eew - - // Reciprocal Approximation - val rec7 = Module(new VFREC7) - rec7.io.rvs2_input := rvs2_op_bits - rec7.io.eew := op.rvs2_eew - rec7.io.frm := op.frm - - when (io_fp_resp.valid) { - when (ctrl.bool(WritesAsMask)) { - when (ctrl.bool(FPMNE) || (ctrl.bool(FPMGT) && !mgt_NaN_reg)) { - wdata := Fill(dLen, !io_fp_resp.bits.data(0)) - } .elsewhen (ctrl.bool(FPMGT) && mgt_NaN_reg) { - wdata := Fill(dLen, 0.U) - } .otherwise { - wdata := Fill(dLen, io_fp_resp.bits.data(0)) - } - } .elsewhen (vfclass_inst) { - wdata := Mux(vd_eew64, Cat(0.U(54.W), io_fp_resp.bits.data(9,0)), Fill(2, Cat(0.U(22.W), io_fp_resp.bits.data(9,0)))) - } .elsewhen (ctrl_fptoint) { - wdata := Mux(vd_eew64, io_fp_resp.bits.data(63,0), Fill(2, io_fp_resp.bits.data(31,0))) - } .otherwise { - wdata := Mux(vd_eew64, FType.D.ieee(io_fp_resp.bits.data), Fill(2, FType.S.ieee(unbox(io_fp_resp.bits.data, 0.U, Some(FType.S))))) - } - has_wdata := true.B - } - - val mask_bit = Mux(op.vd_eew64, op.wmask(0), Mux(op.eidx(0), op.wmask(4), op.wmask(0))) - - io.write.valid := (has_wdata || vfrsqrt7_inst || vfrec7_inst || mgt_NaN_reg) && valid - io.write.bits.eg := op.wvd_eg - io.write.bits.mask := Mux(ctrl.bool(WritesAsMask), ((1.U(dLen.W) & mask_bit) << (op.eidx % dLen.U)), FillInterleaved(8, op.wmask)) - io.write.bits.data := Mux1H(Seq(vfrsqrt7_inst, vfrec7_inst, io_fp_resp.fire), - Seq(Fill(dLenB >> 3, recSqrt7.io.out), Fill(dLenB >> 3, rec7.io.out), Fill(dLenB >> 3, wdata))) - - last := io.write.fire - - io.set_fflags := DontCare - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.set_vxsat := false.B - - io.acc := io.iss.op.acc - io.tail := io.iss.op.tail -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/FPComp.scala b/arch/src/main/scala/framework/gendomain/exu/fp/FPComp.scala deleted file mode 100644 index ef348d57..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/FPComp.scala +++ /dev/null @@ -1,155 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case object FPCmpFactory extends FunctionalUnitFactory { - def insns = Seq( - FMIN.VV, FMIN.VF, FMAX.VV, FMAX.VF, - FSGNJ.VV, FSGNJ.VF, FSGNJN.VV, FSGNJN.VF, FSGNJX.VV, FSGNJX.VF, - MFEQ.VV, MFEQ.VF, MFNE.VV, MFNE.VF, - MFLT.VV, MFLT.VF, MFLE.VV, MFLE.VF, - MFGT.VF, MFGE.VF, - FREDMIN.VV, FREDMAX.VV) - def generate(implicit p: Parameters) = new FPCompPipe()(p) -} - -class FPCompPipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) with HasFPUParameters { - val supported_insns = FPCmpFactory.insns - - io.set_vxsat := false.B - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, - supported_insns, Seq(WritesAsMask, FPComp, FPCompMin, FPMEQ, FPMNE, FPMLT, FPMGT, FPSgnj)) - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - - val ctrl_sgnjn = io.pipe(0).bits.funct6(0) - val ctrl_sgnjx = io.pipe(0).bits.funct6(1) - val rvs1_eew = io.pipe(0).bits.rvs1_eew - val rvs2_eew = io.pipe(0).bits.rvs2_eew - val rvd_eew = io.pipe(0).bits.rvd_eew - val rvs2_data = io.pipe(0).bits.rvs2_data - val rvs1_data = io.pipe(0).bits.rvs1_data - - val fTypes = Seq(FType.H, FType.S, FType.D) - val minmax_results = Wire(Vec(3, UInt(dLen.W))) // results for vfmin/vfmax - val comp_results_eew = Seq.tabulate(4)({sew => WireInit(0.U((dLenB >> sew).W))}) - val comp_results = (0 until 4).map({sew => Mux(rvd_eew === sew.U, Fill(1 << sew, comp_results_eew(sew)), 0.U(dLenB.W))}).reduce(_|_) - val exceptions = Wire(Vec(3, UInt(5.W))) - - for (eew <- 1 until 4) { - val fType = fTypes(eew-1) - val num_chunks = dLen / fType.ieeeWidth - val compare_modules = Seq.fill(num_chunks)(Module(new hardfloat.CompareRecFN(fType.exp, fType.sig))) - - val zip_compares = rvs2_data.asTypeOf(Vec(num_chunks, UInt(fType.ieeeWidth.W))).zip(rvs1_data.asTypeOf(Vec(num_chunks, UInt(fType.ieeeWidth.W)))).zip(compare_modules) - - val gen_compares = zip_compares.map { case((rvs2, rvs1), comp) => - val rvs2_rec = fType.recode(rvs2) - val rvs1_rec = fType.recode(rvs1) - val rvs2_nan = fType.isNaN(rvs2_rec) - val rvs1_nan = fType.isNaN(rvs1_rec) - - comp.io.signaling := true.B - comp.io.a := rvs2_rec - comp.io.b := rvs1_rec - (comp.io, rvs2, rvs2_nan, rvs1, rvs1_nan) - } - - val minmax = gen_compares.map{ case(comp, rvs2, rvs2_nan, rvs1, rvs1_nan) => - val minmax_out = Wire(UInt(fType.ieeeWidth.W)) - when(rvs2_nan && rvs1_nan) { - minmax_out := fType.ieeeQNaN - } .elsewhen (rvs2_nan) { - minmax_out := rvs1 - } .elsewhen (rvs1_nan) { - minmax_out := rvs2 - } .otherwise { - minmax_out := Mux((!ctrl.bool(FPCompMin) && comp.gt) || (ctrl.bool(FPCompMin) && comp.lt), rvs2, rvs1) - } - minmax_out - } - minmax_results(eew - 1) := minmax.asUInt - - val comparisons = gen_compares.map{ case(comp, rvs2, rvs2_nan, rvs1, rvs1_nan) => - val comparison_out = Wire(UInt(1.W)) - when (ctrl.bool(FPMNE)) { - when (rvs2_nan || rvs1_nan) { - comparison_out := 1.U - } .otherwise { - comparison_out := !comp.eq - } - } .elsewhen (rvs2_nan || rvs1_nan) { - comparison_out := 0.U - } .otherwise { - comparison_out := (comp.eq && ctrl.bool(FPMEQ)) || (comp.lt && ctrl.bool(FPMLT)) || (comp.gt && ctrl.bool(FPMGT)) - } - comparison_out - } - comp_results_eew(eew) := comparisons.asUInt - - exceptions(eew - 1) := gen_compares.map {case(comp, rvs2, rvs2_nan, rvs1, rvs1_nan) => comp.exceptionFlags}.reduce(_ | _) - } - - - val rvs1_vals = io.pipe(0).bits.rvs1_data.asTypeOf(Vec(dLenB / 8, UInt(64.W))) - val rvs2_vals = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(dLenB / 8, UInt(64.W))) - - // Sign-Injection Instructions - val sgnj = rvs2_vals.zip(rvs1_vals).map{ case(rvs2, rvs1) => - val d_bit = Wire(Bool()) - val s_bit = Wire(Bool()) - val h_bits = Wire(UInt(2.W)) - - when (ctrl_sgnjn) { - d_bit := !rvs1(63) - s_bit := Mux(rvd_eew <= 2.U, !rvs1(31), rvs2(31)) - h_bits := Mux(rvd_eew === 1.U, Cat(!rvs1(47), !rvs1(15)), Cat(rvs2(47), rvs2(15))) - } .elsewhen (ctrl_sgnjx) { - d_bit := rvs1(63) ^ rvs2(63) - s_bit := Mux(rvd_eew <= 2.U, rvs1(31) ^ rvs2(31), rvs2(31)) - h_bits := Mux(rvd_eew === 1.U, Cat(rvs1(47) ^ rvs2(47), rvs1(15) ^ rvs2(15)), Cat(rvs2(47), rvs2(15))) - } .otherwise { - d_bit := rvs1(63) - s_bit := Mux(rvd_eew <= 2.U, rvs1(31), rvs2(31)) - h_bits := Mux(rvd_eew === 1.U, Cat(rvs1(47), rvs1(15)), Cat(rvs2(47), rvs2(15))) - } - d_bit ## rvs2(62,48) ## h_bits(1) ## rvs2(46, 32) ## s_bit ## rvs2(30,16) ## h_bits(0) ## rvs2(14,0) - } - - val out = Wire(UInt(dLen.W)) - when (ctrl.bool(FPComp)) { - out := Mux(rvs1_eew === 3.U, minmax_results(1), minmax_results(0)) - out := Mux1H(Seq(rvs1_eew === 3.U, rvs1_eew === 2.U, rvs1_eew === 1.U), - Seq(minmax_results(2), minmax_results(1), minmax_results(0))) - } .elsewhen (ctrl.bool(WritesAsMask)) { - out := Fill(8, comp_results) - } .otherwise { - out := sgnj.asUInt - } - - // Mask writing - val mask_write_offset = VecInit.tabulate(4)({ eew => - Cat(io.pipe(0).bits.eidx(log2Ceil(dLen)-1, dLenOffBits-eew), 0.U((dLenOffBits-eew).W)) - })(rvs1_eew) - val mask_write_mask = (VecInit.tabulate(4)({ eew => - VecInit(io.pipe(0).bits.wmask.asBools.grouped(1 << eew).map(_.head).toSeq).asUInt - })(rvs1_eew) << mask_write_offset)(dLen-1,0) - - io.write.valid := io.pipe(0).valid - io.write.bits.eg := io.pipe(0).bits.wvd_eg - io.write.bits.mask := Mux(ctrl.bool(WritesAsMask), mask_write_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) - io.write.bits.data := out - - io.set_fflags.valid := io.write.valid - io.set_fflags.bits := Mux(rvd_eew === 3.U, exceptions(1), exceptions(0)) - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.pipe0_stall := false.B -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/FPConv.scala b/arch/src/main/scala/framework/gendomain/exu/fp/FPConv.scala deleted file mode 100644 index 5d83c8f3..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/FPConv.scala +++ /dev/null @@ -1,176 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case object FPConvFactory extends FunctionalUnitFactory { - def insns = Seq(FCVT_SGL, FCVT_NRW, FCVT_WID) - def generate(implicit p: Parameters) = new FPConvPipe()(p) -} - -class FPConvPipe(implicit p: Parameters) extends PipelinedFunctionalUnit(2)(p) with HasFPUParameters { - val supported_insns = FPConvFactory.insns - - io.set_vxsat := false.B - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, - supported_insns, Nil).matched - - val rs1 = io.pipe(0).bits.rs1 - val ctrl_widen = rs1(3) - val ctrl_narrow = rs1(4) - val ctrl_signed = rs1(0) - val ctrl_out = !rs1(2) && rs1(1) - val ctrl_truncating = rs1(2) && rs1(1) - val ctrl_round_to_odd = rs1(0) - - val rvs2_data = io.pipe(0).bits.rvs2_data - val vd_eew = io.pipe(0).bits.vd_eew - val rvs2_eew = io.pipe(0).bits.rvs2_eew - val eew_select = Seq(rvs2_eew === 1.U, rvs2_eew === 2.U, rvs2_eew === 3.U) - - val fTypes = Seq(FType.H, FType.S, FType.D) - - // Single Width Conversions - val single_width_conversions = fTypes.map { fType => - val num_chunks = dLen / fType.ieeeWidth - val rvs2_chunks = rvs2_data.asTypeOf(Vec(num_chunks, UInt(fType.ieeeWidth.W))) - - // FP to Int - val fptoint_modules = Seq.fill(num_chunks)(Module(new hardfloat.RecFNToIN(fType.exp, fType.sig, fType.ieeeWidth))) - val gen_fptoint = rvs2_chunks.zip(fptoint_modules).map { case(rvs2, conv) => - conv.io.signedOut := ctrl_signed - conv.io.roundingMode := Mux(ctrl_truncating, 1.U, io.pipe(0).bits.frm) - conv.io.in := fType.recode(rvs2) - conv.io.out - } - - // Int to FP - val inttofp_modules = Seq.fill(num_chunks)(Module(new hardfloat.INToRecFN(fType.ieeeWidth, fType.exp, fType.sig))) - val gen_inttofp = rvs2_chunks.zip(inttofp_modules).map { case(rvs2, conv) => - conv.io.signedIn := ctrl_signed - conv.io.roundingMode := io.pipe(0).bits.frm - conv.io.detectTininess := hardfloat.consts.tininess_afterRounding - conv.io.in := rvs2 - fType.ieee(conv.io.out) - } - - Mux(ctrl_out, gen_inttofp.asUInt, gen_fptoint.asUInt) - } - - val single_width_out = Mux1H(eew_select, single_width_conversions) - - // Widening Conversions - val widening_conversions = fTypes.zipWithIndex.filter(_._1.ieeeWidth <= 32).map { case (fType, i) => - val num_converts = dLen / (2 * fType.ieeeWidth) - val in_sew = log2Ceil(fType.ieeeWidth / 8) - val wideType = fTypes(i+1) - - // Int to FP conversions - val wide_inttofp_modules = Seq.fill(num_converts)(Module(new hardfloat.INToRecFN(fType.ieeeWidth, wideType.exp, wideType.sig))) - val gen_inttofp = wide_inttofp_modules.zipWithIndex.map { case(wide, idx) => - wide.io.signedIn := ctrl_signed - wide.io.roundingMode := io.pipe(0).bits.frm - wide.io.detectTininess := hardfloat.consts.tininess_afterRounding - wide.io.in := extractElem(rvs2_data, in_sew.U, io.pipe(0).bits.eidx + idx.U)(fType.ieeeWidth-1,0) - wideType.ieee(wide.io.out) - }.asUInt - - // FP to FP conversions - val wide_fptofp_modules = Seq.fill(num_converts)(Module(new hardfloat.RecFNToRecFN(fType.exp, fType.sig, wideType.exp, wideType.sig))) - val gen_fptofp = wide_fptofp_modules.zipWithIndex.map{ case(wide, idx) => - wide.io.in := fType.recode(extractElem(rvs2_data, in_sew.U, io.pipe(0).bits.eidx + idx.U)(fType.ieeeWidth-1,0)) - wide.io.roundingMode := io.pipe(0).bits.frm - wide.io.detectTininess := hardfloat.consts.tininess_afterRounding - wideType.ieee(wide.io.out) - }.asUInt - - // FP to Int conversions - val wide_fptoint_modules = Seq.fill(num_converts)(Module(new hardfloat.RecFNToIN(fType.exp, fType.sig, wideType.ieeeWidth))) - val gen_fptoint = wide_fptoint_modules.zipWithIndex.map{ case(wide, idx) => - val extracted_rvs2_bits = extractElem(rvs2_data, in_sew.U, io.pipe(0).bits.eidx + idx.U)(fType.ieeeWidth-1,0) - wide.io.signedOut := ctrl_signed - wide.io.roundingMode := Mux(ctrl_truncating, 1.U, io.pipe(0).bits.frm) - wide.io.in := fType.recode(extracted_rvs2_bits) - wide.io.out - }.asUInt - - Mux1H(Seq(!rs1(2) && rs1(1), rs1(2) && !rs1(1), (!rs1(2) && !rs1(1)) || (rs1(2) && rs1(1))), - Seq(gen_inttofp , gen_fptofp , gen_fptoint)) - } - - val widening_out = Mux1H(Seq(vd_eew === 2.U, vd_eew === 3.U), widening_conversions) - - // Narrowing Conversions - // Just EEW of 32 and 64 - val narrowing_conversions = fTypes.zipWithIndex.filter(_._1.ieeeWidth >= 32).map { case (fType, i) => - val num_converts = dLen / fType.ieeeWidth - val in_sew = log2Ceil(fType.ieeeWidth / 8) - val narrowType = fTypes(i-1) - - // Int to FP Conversions - val narrow_inttofp_modules = Seq.fill(num_converts)(Module(new hardfloat.INToRecFN(fType.ieeeWidth, narrowType.exp, narrowType.sig))) - val gen_inttofp = narrow_inttofp_modules.zipWithIndex.map { case(narrow, idx) => - narrow.io.signedIn := ctrl_signed - narrow.io.roundingMode := io.pipe(0).bits.frm - narrow.io.detectTininess := hardfloat.consts.tininess_afterRounding - narrow.io.in := extractElem(rvs2_data, in_sew.U, io.pipe(0).bits.eidx + idx.U)(fType.ieeeWidth-1,0) - narrowType.ieee(narrow.io.out) - }.asUInt - - // FP to FP Conversions - val fptofp_modules = Seq.fill(num_converts)(Module(new hardfloat.RecFNToRecFN(fType.exp, fType.sig, narrowType.exp, narrowType.sig))) - val gen_fptofp = fptofp_modules.zipWithIndex.map{ case(narrow, idx) => - narrow.io.in := fType.recode(extractElem(rvs2_data, in_sew.U, io.pipe(0).bits.eidx + idx.U)(fType.ieeeWidth-1,0)) - narrow.io.roundingMode := Mux(ctrl_round_to_odd, "b110".U, io.pipe(0).bits.frm) - narrow.io.detectTininess := hardfloat.consts.tininess_afterRounding - narrowType.ieee(narrow.io.out) - }.asUInt - - // FP to Int Conversions - val fptoint_modules = Seq.fill(num_converts)(Module(new hardfloat.RecFNToIN(fType.exp, fType.sig, narrowType.ieeeWidth))) - val gen_fptoint = fptoint_modules.zipWithIndex.map { case(conv, idx) => - val extracted_rvs2_bits = extractElem(rvs2_data, in_sew.U, io.pipe(0).bits.eidx + idx.U)(fType.ieeeWidth-1,0) - conv.io.signedOut := ctrl_signed - conv.io.roundingMode := Mux(ctrl_truncating, 1.U, io.pipe(0).bits.frm) - conv.io.in := fType.recode(extracted_rvs2_bits) - conv.io.out - }.asUInt - - Mux1H(Seq(!rs1(2) && rs1(1), rs1(2) && !rs1(1), (!rs1(2) && !rs1(1)) || (rs1(2) && rs1(1))), - Seq(gen_inttofp , gen_fptofp , gen_fptoint)) - } - - // Special Case for FP16 narrowing converts - // Only narrowing FP to Int - val fp16_fptoint_modules = Seq.fill(dLen/16)(Module(new hardfloat.RecFNToIN(FType.H.exp, FType.H.sig, FType.H.ieeeWidth/2))) - val fp16_gen_fptoint = fp16_fptoint_modules.zipWithIndex.map { case(conv, idx) => - val extracted_rvs2_bits = extractElem(rvs2_data, 1.U, io.pipe(0).bits.eidx + idx.U)(FType.H.ieeeWidth-1,0) - conv.io.signedOut := ctrl_signed - conv.io.roundingMode := io.pipe(0).bits.frm - conv.io.in := FType.H.recode(Mux(ctrl_truncating, extracted_rvs2_bits(FType.H.ieeeWidth-1, FType.H.sig-2) << (FType.H.sig - 2), extracted_rvs2_bits)) - conv.io.out - }.asUInt - - - val narrowing_out = Fill(2, Mux1H(Seq(vd_eew === 0.U, vd_eew === 1.U, vd_eew === 2.U), Seq(fp16_gen_fptoint) ++ narrowing_conversions)) - - val pipe_out = Pipe(io.pipe(0).valid, Mux1H(Seq(!ctrl_widen && !ctrl_narrow, ctrl_widen, ctrl_narrow), - Seq(single_width_out, widening_out, narrowing_out))).bits - - io.write.valid := io.pipe(depth-1).valid - io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg - io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) - io.write.bits.data := pipe_out - - io.set_fflags := DontCare - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.pipe0_stall := false.B -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/FPDiv.scala b/arch/src/main/scala/framework/gendomain/exu/fp/FPDiv.scala deleted file mode 100644 index a2124645..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/FPDiv.scala +++ /dev/null @@ -1,370 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import chisel3.util.experimental.decode._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class VFREC7(implicit p: Parameters) extends FPUModule()(p) { - val io = IO(new Bundle { - val rvs2_input = Input(UInt(64.W)) - val eew = Input(UInt(2.W)) - val frm = Input(UInt(3.W)) - val out = Output(UInt(64.W)) - val exc = Output(UInt(5.W)) - }) - - val table = Seq( - 127, 125, 123, 121, 119, 117, 116, 114, 112, 110, // 0-9 - 109, 107, 105, 104, 102, 100, 99, 97, 96, 94, - 93, 91, 90, 88, 87, 85, 84, 83, 81, 80, - 79, 77, 76, 75, 74, 72, 71, 70, 69, 68, - 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, - 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, - 46, 45, 44, 43, 42, 41, 40, 40, 39, 38, - 37, 36, 35, 35, 34, 33, 32, 31, 31, 30, - 29, 28, 28, 27, 26, 25, 25, 24, 23, 23, - 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, - 15, 15, 14, 14, 13, 12, 12, 11, 11, 10, - 9, 9, 8, 8, 7, 7, 6, 5, 5, 4, - 4, 3, 3, 2, 2, 1, 1, 0) - - def count_leading_zeros(in: UInt): UInt = { - PriorityEncoder(Reverse(in)) - } - - val rvs2_bits = io.rvs2_input - val fTypes = Seq(FType.H, FType.S, FType.D) - - val eew_sel = (1 to 3).map(_.U === io.eew) - val classify = Mux1H(eew_sel, fTypes.map(f => f.classify(f.recode(rvs2_bits(f.ieeeWidth-1,0))))) - - val dz = WireInit(false.B) - val nv = WireInit(false.B) - val of = WireInit(false.B) - val nx = WireInit(false.B) - - val ret = Wire(UInt(64.W)) - ret := 0.U // it should not be possible to fall into this case - when (classify(0)) { // -inf - ret := Mux1H(eew_sel, fTypes.map(f => 1.U ## 0.U((f.ieeeWidth-1).W))) - } .elsewhen (classify(7)) { // +inf - ret := 0.U - } .elsewhen (classify(3)) { // -0 - ret := Mux1H(eew_sel, fTypes.map(f => 1.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W))) - dz := true.B - } .elsewhen (classify(4)) { // +0 - ret := Mux1H(eew_sel, fTypes.map(f => 0.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W))) - dz := true.B - } .elsewhen (classify(8)) { // sNaN - ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN)) - nv := true.B - } .elsewhen (classify(9)) { // qNaN - ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN)) - } .otherwise { - val sub = classify(2) || classify(5) - val exp = Mux1H(eew_sel, fTypes.map(f => (rvs2_bits >> (f.sig - 1))(f.exp-1,0))) - val sig = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.sig-2,0))) - val sign = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.ieeeWidth-1))) - - val norm_exp = WireInit(exp) - val norm_sig = WireInit(sig) - val round_abnormal = WireInit(false.B) - - when (sub) { - val leading_zeros = Mux1H(eew_sel, fTypes.map(f => count_leading_zeros(sig(f.sig-2,0)))) - - val exp_new = exp - leading_zeros - val sig_new = (sig << (leading_zeros +& 1.U)) & Mux1H(eew_sel, fTypes.map(f => ~(0.U((f.sig-1).W)))) - norm_exp := exp_new - norm_sig := sig_new - - when (exp_new =/= 0.U && ~exp_new =/= 0.U) { - round_abnormal := true.B - when (io.frm === 1.U || - (io.frm === 2.U && !sign) || - (io.frm === 3.U && sign)) { - ret := Mux1H(eew_sel, fTypes.map(f => (sign << (f.sig + f.exp - 1)) | (~(0.U(f.exp.W)) << (f.sig - 1)))) - 1.U - } .otherwise { - ret := Mux1H(eew_sel, fTypes.map(f => (sign << (f.sig + f.exp - 1)) | (~(0.U(f.exp.W)) << (f.sig - 1)))) - } - } - } - - when (!round_abnormal) { - val idx = Mux1H(eew_sel, fTypes.map(f => norm_sig >> (f.sig - 1 - 7)))(6,0) - val lookup = VecInit(table.map(_.U(7.W)))(idx) - val default_out_sig = Mux1H(eew_sel, fTypes.map(f => lookup << (f.sig - 1 - 7))) - val biases = fTypes.map(f => (1 << (f.exp - 1)) - 1) - val default_out_exp = Mux1H(eew_sel, fTypes.zip(biases).map { case (f, b) => - (2 * b).U + ~norm_exp - }) - - val out_sig = WireInit(default_out_sig) - val out_exp = WireInit(default_out_exp) - - when (default_out_exp === 0.U || (~default_out_exp === 0.U)) { - out_sig := (default_out_sig >> 1) | Mux1H(eew_sel, fTypes.map(f => 1.U << (f.sig - 1 - 1))) - when (~default_out_exp === 0.U) { - out_sig := default_out_sig >> 1; - out_exp := 0.U - } - } - ret := Mux1H(eew_sel, fTypes.map(f => sign ## out_exp(f.exp-1,0) ## out_sig(f.sig-2,0))) - } - - when (round_abnormal) { - of := true.B - nx := true.B - } - } - - io.out := Mux1H(eew_sel, fTypes.map(f => Fill(64 / f.ieeeWidth, ret(f.ieeeWidth-1,0)))) - io.exc := nv ## dz ## of ## false.B ## nx -} - - -class VFRSQRT7(implicit p: Parameters) extends FPUModule()(p) { - val io = IO(new Bundle { - val rvs2_input = Input(UInt(64.W)) - val eew = Input(UInt(2.W)) - val out = Output(UInt(64.W)) - val exc = Output(UInt(5.W)) - }) - - val table = Seq( - 52, 51, 50, 48, 47, 46, 44, 43, - 42, 41, 40, 39, 38, 36, 35, 34, - 33, 32, 31, 30, 30, 29, 28, 27, - 26, 25, 24, 23, 23, 22, 21, 20, - 19, 19, 18, 17, 16, 16, 15, 14, - 14, 13, 12, 12, 11, 10, 10, 9, - 9, 8, 7, 7, 6, 6, 5, 4, - 4, 3, 3, 2, 2, 1, 1, 0, - 127, 125, 123, 121, 119, 118, 116, 114, - 113, 111, 109, 108, 106, 105, 103, 102, - 100, 99, 97, 96, 95, 93, 92, 91, - 90, 88, 87, 86, 85, 84, 83, 82, - 80, 79, 78, 77, 76, 75, 74, 73, - 72, 71, 70, 70, 69, 68, 67, 66, - 65, 64, 63, 63, 62, 61, 60, 59, - 59, 58, 57, 56, 56, 55, 54, 53 - ) - - def count_leading_zeros(in: UInt): UInt = { - PriorityEncoder(Reverse(in)) - } - - - val rvs2_bits = io.rvs2_input - val fTypes = Seq(FType.H, FType.S, FType.D) - - val eew_sel = (1 to 3).map(_.U === io.eew) - val classify = Mux1H(eew_sel, fTypes.map(f => f.classify(f.recode(rvs2_bits(f.ieeeWidth-1,0))))) - - val dz = WireInit(false.B) - val nv = WireInit(false.B) - val of = WireInit(false.B) - val nx = WireInit(false.B) - - val ret = Wire(UInt(64.W)) - ret := 0.U // it should not be possible to fall into this case - - when (classify(0) || classify(1) || classify(2) || classify(8)) { // -inf, -normal, -subnormal, sNaN - nv := true.B - ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN)) - } .elsewhen (classify(9)) { // qNaN - ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN)) - } .elsewhen (classify(3)) { // -0 - ret := Mux1H(eew_sel, fTypes.map(f => 1.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W))) - dz := true.B - } .elsewhen (classify(4)) { // +0 - ret := Mux1H(eew_sel, fTypes.map(f => 0.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W))) - dz := true.B - } .elsewhen (classify(7)) { // +inf - ret := 0.U - } .otherwise { - val sub = classify(5) - - val exp = Mux1H(eew_sel, fTypes.map(f => (rvs2_bits >> (f.sig - 1))(f.exp-1,0))) - val sig = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.sig-2,0))) - val sign = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.ieeeWidth-1))) - - val norm_exp = Wire(UInt((1+fTypes.map(_.exp).max).W)) - norm_exp := exp - val norm_sig = WireInit(sig) - - when (sub) { - val leading_zeros = Mux1H(eew_sel, fTypes.map(f => count_leading_zeros(sig(f.sig-2,0)))) - val exp_new = (0.U(1.W) ## exp) - leading_zeros - val sig_new = (sig << (leading_zeros +& 1.U)) & Mux1H(eew_sel, fTypes.map(f => ~(0.U((f.sig-1).W)))) - norm_exp := exp_new - norm_sig := sig_new - } - - val idx = ((norm_exp(0) << 6) | Mux1H(eew_sel, fTypes.map(f => norm_sig >> (f.sig - 1 - 7 + 1))))(6,0) - val lookup = VecInit(table.map(_.U(7.W)))(idx) - val out_sig = Mux1H(eew_sel, fTypes.map(f => lookup << (f.sig - 1 - 7))) - val biases = fTypes.map(f => (1 << (f.exp - 1)) - 1) - val out_exp = Mux1H(eew_sel, fTypes.zip(biases).map { case (f, b) => - val bias3 = ((3 * b).S((f.exp + 2).W) - norm_exp.asSInt - 1.S).asUInt - bias3 >> 1 - }) - - ret := Mux1H(eew_sel, fTypes.map(f => sign ## out_exp(f.exp-1,0) ## out_sig(f.sig-2,0))) - } - io.out := Mux1H(eew_sel, fTypes.map(f => Fill(64 / f.ieeeWidth, ret(f.ieeeWidth-1,0)))) - io.exc := nv ## dz ## of ## false.B ## nx - -} - -case object FPDivSqrtFactory extends FunctionalUnitFactory { - def insns = Seq( - FDIV.VV, FDIV.VF, - FRDIV.VF, - FSQRT_V, - FRSQRT7_V, - FREC7_V, - FCLASS_V - ).map(_.elementWise) - - def generate(implicit p: Parameters) = new FPDivSqrt()(p) -} - -class FPDivSqrt(implicit p: Parameters) extends IterativeFunctionalUnit()(p) with HasFPUParameters { - val supported_insns = FPDivSqrtFactory.insns - io.set_vxsat := false.B - - val divSqrt = Module(new hardfloat.DivSqrtRecF64) - val divSqrt16 = Module(new hardfloat.DivSqrtRecFN_small(FType.H.exp, FType.H.sig, 0)) - - val accept_inst = new VectorDecoder( - io.iss.op.funct3, io.iss.op.funct6, io.iss.op.rs1, io.iss.op.rs2, - supported_insns, - Seq(FPSwapVdV2)) - - val ctrl = new VectorDecoder( - op.funct3, op.funct6, op.rs1, op.rs2, - supported_insns, - Seq(FPSwapVdV2)) - - val ctrl_isDiv = io.iss.op.opff6.isOneOf(OPFFunct6.fdiv, OPFFunct6.frdiv) - val divSqrt_ready = (ctrl_isDiv && divSqrt.io.inReady_div) || (!ctrl_isDiv && divSqrt.io.inReady_sqrt) - val divSqrt16_ready = divSqrt16.io.inReady - - val div_op = op.opff6.isOneOf(OPFFunct6.fdiv, OPFFunct6.frdiv) - - val rvs2_bits = op.rvs2_elem - val rvs1_bits = op.rvs1_elem - - divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding - divSqrt.io.roundingMode := op.frm - divSqrt16.io.detectTininess := hardfloat.consts.tininess_afterRounding - divSqrt16.io.roundingMode := op.frm - - val iss_fire_pipe = Reg(Bool()) - iss_fire_pipe := io.iss.valid && io.iss.ready - - divSqrt.io.inValid := iss_fire_pipe && !(op.rvd_eew === 1.U) && (div_op || (op.opff6 === OPFFunct6.funary1 && op.rs1 === 0.U)) - divSqrt.io.sqrtOp := !div_op - divSqrt16.io.inValid := iss_fire_pipe && (op.rvd_eew === 1.U) && (div_op || (op.opff6 === OPFFunct6.funary1 && op.rs1 === 0.U)) - divSqrt16.io.sqrtOp := !div_op - - io.hazard.valid := valid - io.hazard.bits.eg := op.wvd_eg - - when (op.rvs1_eew === 3.U) { - divSqrt.io.a := Mux(ctrl.bool(FPSwapVdV2) && div_op, FType.D.recode(rvs1_bits), FType.D.recode(rvs2_bits)) - divSqrt.io.b := Mux(ctrl.bool(FPSwapVdV2) || !div_op, FType.D.recode(rvs2_bits), FType.D.recode(rvs1_bits)) - } .otherwise { - val narrow_rvs2_bits = rvs2_bits(31,0) - val narrow_rvs1_bits = rvs1_bits(31,0) - val widen = Seq(FType.S.recode(narrow_rvs2_bits), FType.S.recode(narrow_rvs1_bits)).zip( - Seq.fill(2)(Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53)))).map { case(input, upconvert) => - upconvert.io.in := input - upconvert.io.roundingMode := op.frm - upconvert.io.detectTininess := hardfloat.consts.tininess_afterRounding - upconvert - } - - divSqrt.io.a := Mux(ctrl.bool(FPSwapVdV2) && div_op, widen(1).io.out, widen(0).io.out) - divSqrt.io.b := Mux(ctrl.bool(FPSwapVdV2) || !div_op, widen(0).io.out, widen(1).io.out) - } - - divSqrt16.io.a := Mux(ctrl.bool(FPSwapVdV2) && div_op, FType.H.recode(rvs1_bits), FType.H.recode(rvs2_bits)) - divSqrt16.io.b := Mux(ctrl.bool(FPSwapVdV2) || !div_op, FType.H.recode(rvs2_bits), FType.H.recode(rvs1_bits)) - - val divSqrt_out_valid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt - val divSqrt16_out_valid = divSqrt16.io.outValid_div || divSqrt16.io.outValid_sqrt - - val narrow = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24)) - narrow.io.roundingMode := op.frm - narrow.io.detectTininess := hardfloat.consts.tininess_afterRounding - narrow.io.in := divSqrt.io.out - - val divSqrt_out = Mux(op.vd_eew === 3.U, FType.D.ieee(divSqrt.io.out), Fill(2, FType.S.ieee(narrow.io.out))) - - val out_buffer = RegEnable(divSqrt_out, divSqrt_out_valid) - val out_toWrite = RegInit(false.B) - val divSqrt_write = Mux(out_toWrite, out_buffer, divSqrt_out) - - val divSqrt16_out = FType.H.ieee(divSqrt16.io.out) - val out16_buffer = RegEnable(divSqrt16_out, divSqrt16_out_valid) - val out16_toWrite = RegInit(false.B) - val divSqrt16_write = Mux(out16_toWrite, out16_buffer, divSqrt16_out) - - // vfclass instruction - val gen_vfclass = Seq(FType.H, FType.S, FType.D).zipWithIndex.map { case(fType, i) => - Fill(2, Cat(0.U((fType.ieeeWidth-10).W), fType.classify(fType.recode(rvs2_bits(fType.ieeeWidth-1,0))))) - } - - val vfclass_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 16.U - val vfrsqrt7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 4.U - val vfrec7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 5.U - - // Reciprocal Sqrt Approximation - val recSqrt7 = Module(new VFRSQRT7) - recSqrt7.io.rvs2_input := Mux(valid && vfrsqrt7_inst, rvs2_bits, 0.U) - recSqrt7.io.eew := op.rvs2_eew - - // Reciprocal Approximation - val rec7 = Module(new VFREC7) - rec7.io.rvs2_input := Mux(valid && vfrec7_inst, rvs2_bits, 0.U) - rec7.io.eew := op.rvs2_eew - rec7.io.frm := op.frm - - // Capture result in case of write port backpressure - when (io.write.fire) { - out_toWrite := false.B - out16_toWrite := false.B - } .elsewhen (divSqrt_out_valid) { - out_toWrite := true.B - out16_toWrite := true.B - } - - val out = Mux1H( - Seq(vfclass_inst, vfrsqrt7_inst, vfrec7_inst, out_toWrite || divSqrt_out_valid || divSqrt16_out_valid), - Seq(Mux1H(Seq(op.rvs2_eew === 3.U, op.rvs2_eew === 2.U, op.rvs2_eew === 1.U), Seq(gen_vfclass(2), gen_vfclass(1), gen_vfclass(0))), recSqrt7.io.out, rec7.io.out, divSqrt_write) - )(63,0) - - io.write.valid := ((vfclass_inst || vfrsqrt7_inst || vfrec7_inst) && valid) || out_toWrite || divSqrt_out_valid - io.write.bits.eg := op.wvd_eg - io.write.bits.mask := FillInterleaved(8, op.wmask) - io.write.bits.data := Fill(dLenB >> 3, out) - io.iss.ready := accept_inst.matched && ((divSqrt_ready && io.iss.op.vd_eew >= 2.U) || (divSqrt16_ready && io.iss.op.vd_eew === 1.U)) && (!valid || last) - last := io.write.fire - - io.set_fflags.valid := divSqrt_out_valid || divSqrt16_out_valid || (vfrsqrt7_inst && io.write.fire) || (vfrec7_inst && io.write.fire) - io.set_fflags.bits := (divSqrt.io.exceptionFlags & Fill(5, divSqrt_out_valid)) | divSqrt16.io.exceptionFlags & Fill(5, divSqrt_out_valid) | (recSqrt7.io.exc & Fill(5, vfrsqrt7_inst)) | (rec7.io.exc & Fill(5, vfrec7_inst)) - - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - - io.acc := false.B - io.tail := false.B -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/FPFMAPipe.scala b/arch/src/main/scala/framework/gendomain/exu/fp/FPFMAPipe.scala deleted file mode 100644 index f0831052..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/FPFMAPipe.scala +++ /dev/null @@ -1,205 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - - -class TandemFMAPipe(depth: Int)(implicit p: Parameters) extends FPUModule()(p) { - val io = IO(new Bundle { - val valid = Input(Bool()) - val frm = Input(UInt(3.W)) - val addsub = Input(Bool()) - val mul = Input(Bool()) - val op = Input(UInt(2.W)) - val a_eew = Input(UInt(2.W)) - val b_eew = Input(UInt(2.W)) - val c_eew = Input(UInt(2.W)) - val out_eew = Input(UInt(2.W)) - val a = Input(UInt(64.W)) - val b = Input(UInt(64.W)) - val c = Input(UInt(64.W)) - val mask = Input(UInt(4.W)) - val out = Output(UInt(64.W)) - val exc = Output(UInt(5.W)) - }) - - val out_eew_pipe = Pipe(io.valid, io.out_eew, depth-1) - val frm_pipe = Pipe(io.valid, io.frm, depth-1) - val mask_pipe = Pipe(io.valid, io.mask, depth-1) - - val fTypes = Seq(FType.D, FType.S, FType.H) - - val fma_results = fTypes.zipWithIndex.map { case(fType, j) => - val n = 64 / fType.ieeeWidth - val fma_eew = log2Ceil(fType.ieeeWidth >> 3) - - val results = (0 until n).map { i => - val fma = Module(new MulAddRecFNPipe((depth-1) min 2, fType.exp, fType.sig)) - val validin = io.valid && (io.out_eew === fma_eew.U) - val msb_idx = ((i + 1) * fType.ieeeWidth) - 1 - val lsb_idx = i * fType.ieeeWidth - - val inputs = Seq((io.a, io.a_eew), (io.b, io.b_eew), (io.c, io.c_eew)).map { case(in, eew) => - if (j <= 1) { - val widen = Module(new hardfloat.RecFNToRecFN(fTypes(j+1).exp, fTypes(j+1).sig, fType.exp, fType.sig)) - widen.io.in := fTypes(j+1).recode(Mux(validin && io.mask(i*(4/n)), in(fTypes(j+1).ieeeWidth-1,0), 0.U)) - widen.io.roundingMode := io.frm - widen.io.detectTininess := hardfloat.consts.tininess_afterRounding - - Mux(eew =/= fma_eew.U, widen.io.out, fType.recode(Mux(validin && io.mask(i*(4/n)), in(msb_idx, lsb_idx), 0.U))) - } else { - fType.recode(Mux(validin && io.mask(i*(4/n)), in(msb_idx, lsb_idx), 0.U)) - } - } - - fma.io.validin := validin - fma.io.op := Mux(validin, io.op, 0.U) - fma.io.roundingMode := Mux(validin, io.frm, 0.U) - fma.io.detectTininess := hardfloat.consts.tininess_afterRounding - fma.io.a := inputs(0) - fma.io.b := Mux(io.addsub, 1.U << (fType.ieeeWidth - 1), inputs(1)) - fma.io.c := Mux(io.mul, (inputs(0) ^ inputs(1)) & (1.U << fType.ieeeWidth), inputs(2)) - - val out = Pipe(fma.io.validout, fType.ieee(fma.io.out), (depth-3) max 0).bits - val exc = Pipe(fma.io.validout, fma.io.exceptionFlags, (depth-3) max 0).bits - (out, exc) - } - val out = results.map(_._1).asUInt - val exc = results.map(_._2).zipWithIndex.map{ case(e, i) => e & Fill(5, mask_pipe.bits(i)) }.reduce(_ | _) - (out, exc) - } - - val out_sel_oh = fTypes.map{ fType => log2Ceil(fType.ieeeWidth >> 3).U === out_eew_pipe.bits} - io.out := Mux1H(out_sel_oh, fma_results.map(_._1)) - io.exc := Mux1H(out_sel_oh, fma_results.map(_._2)) -} - -case class FPFMAFactory(depth: Int, sharedScalar: Boolean) extends FunctionalUnitFactory { - def base_insns = Seq( - FADD.VV, FADD.VF, FSUB.VV, FSUB.VF, FRSUB.VF, - FMUL.VV, FMUL.VF, - FMACC.VV, FMACC.VF, FNMACC.VV, FNMACC.VF, - FMSAC.VV, FMSAC.VF, FNMSAC.VV, FNMSAC.VF, - FMADD.VV, FMADD.VF, FNMADD.VV, FNMADD.VF, - FMSUB.VV, FMSUB.VF, FNMSUB.VV, FNMSUB.VF, - FWADD.VV, FWADD.VF, FWSUB.VV, FWSUB.VF, - FWADDW.VV, FWADDW.VF, FWSUBW.VV, FWSUBW.VF, - FWMUL.VV, FWMUL.VF, - FWMACC.VV, FWMACC.VF, FWNMACC.VV, FWNMACC.VF, - FWMSAC.VV, FWMSAC.VF, FWNMSAC.VV, FWNMSAC.VF, - FREDOSUM.VV, FREDUSUM.VV, FWREDOSUM.VV, FWREDUSUM.VV - ) - def insns = if (sharedScalar) base_insns.map(_.elementWise) else base_insns - def generate(implicit p: Parameters) = if (sharedScalar) { - new SharedScalarElementwiseFPFMA(depth)(p) - } else { - new FPFMAPipe(depth)(p) - } -} - -class FPFMAPipe(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) with HasFPUParameters { - val supported_insns = FPFMAFactory(depth, false).insns - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - - io.set_vxsat := false.B - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( - FPAdd, FPMul, FPSwapVdV2, FPFMACmd)) - - val vs1_eew = io.pipe(0).bits.rvs1_eew - val vs2_eew = io.pipe(0).bits.rvs2_eew - val vd_eew = io.pipe(0).bits.vd_eew - val ctrl_widen_vs2 = vs2_eew =/= vd_eew - val ctrl_widen_vs1 = vs1_eew =/= vd_eew - val wmask = io.pipe(0).bits.wmask - - val nTandemFMA = dLenB / 8 - - val eidx = Mux(io.pipe(0).bits.acc, 0.U, io.pipe(0).bits.eidx) - val one_bits = Mux1H(Seq(vd_eew === 3.U, vd_eew === 2.U, vd_eew === 1.U), - Seq("h3FF0000000000000".U, "h3F8000003F800000".U, "h3C003C003C003C00".U)) - val fmaCmd = ctrl.uint(FPFMACmd) - - val vec_rvs1 = io.pipe(0).bits.rvs1_data.asTypeOf(Vec(nTandemFMA, UInt(64.W))) - val vec_rvs2 = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(nTandemFMA, UInt(64.W))) - val vec_rvd = io.pipe(0).bits.rvd_data.asTypeOf(Vec(nTandemFMA, UInt(64.W))) - - val fma_pipes = Seq.fill(nTandemFMA)(Module(new TandemFMAPipe(depth))).zipWithIndex.map { case(fma_pipe, i) => - val widening_vs1_bits = extractElem(io.pipe(0).bits.rvs1_data, 2.U, eidx + i.U)(31,0) - val rs1_bits = Mux(ctrl_widen_vs1, widening_vs1_bits, vec_rvs1(i)) - val widening_vs2_bits = extractElem(io.pipe(0).bits.rvs2_data, 2.U, eidx + i.U)(31,0) - val vs2_bits = Mux(ctrl_widen_vs2, widening_vs2_bits, vec_rvs2(i)) - - fma_pipe.io.mask := ((vs1_eew === 1.U) && wmask((i*8)+6)) ## ((vs1_eew <= 2.U) && wmask((i*8)+4)) ## - ((vs1_eew === 1.U) && wmask((i*8)+2)) ## wmask(i*8) - fma_pipe.io.addsub := ctrl.bool(FPAdd) && !ctrl.bool(FPMul) - fma_pipe.io.mul := ctrl.bool(FPMul) && !ctrl.bool(FPAdd) - fma_pipe.io.out_eew := vd_eew - - // FMA - when (ctrl.bool(FPMul) && ctrl.bool(FPAdd)) { - fma_pipe.io.b := rs1_bits - fma_pipe.io.b_eew := vs1_eew - when (ctrl.bool(FPSwapVdV2)) { - fma_pipe.io.a := vec_rvd(i) - fma_pipe.io.a_eew := vd_eew - fma_pipe.io.c := vs2_bits - fma_pipe.io.c_eew := vs2_eew - } .otherwise { - fma_pipe.io.a := vs2_bits - fma_pipe.io.a_eew := vs2_eew - fma_pipe.io.c := vec_rvd(i) - fma_pipe.io.c_eew := vd_eew - } - } - // Multiply - .elsewhen (ctrl.bool(FPMul)) { - fma_pipe.io.a := vs2_bits - fma_pipe.io.a_eew := vs2_eew - fma_pipe.io.b := rs1_bits - fma_pipe.io.b_eew := vs1_eew - fma_pipe.io.c := 0.U - fma_pipe.io.c_eew := vs2_eew - } - // Add type - .elsewhen (ctrl.bool(FPAdd)) { - fma_pipe.io.a := vs2_bits - fma_pipe.io.a_eew := vs2_eew - fma_pipe.io.b := one_bits - fma_pipe.io.b_eew := vd_eew - fma_pipe.io.c := rs1_bits - fma_pipe.io.c_eew := vs1_eew - } .otherwise { - fma_pipe.io.a := 0.U - fma_pipe.io.a_eew := 0.U - fma_pipe.io.b := 0.U - fma_pipe.io.b_eew := 0.U - fma_pipe.io.c := 0.U - fma_pipe.io.c_eew := 0.U - } - - fma_pipe.io.valid := io.pipe(0).valid - fma_pipe.io.frm := io.pipe(0).bits.frm - fma_pipe.io.op := fmaCmd - - fma_pipe.io - } - - io.write.valid := io.pipe(depth-1).valid - io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg - io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) - io.write.bits.data := fma_pipes.map(pipe => pipe.out).asUInt - - io.set_fflags.valid := io.write.valid - io.set_fflags.bits := fma_pipes.map(pipe => pipe.exc).reduce(_ | _) - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.pipe0_stall := false.B -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/SharedFPFMA.scala b/arch/src/main/scala/framework/gendomain/exu/fp/SharedFPFMA.scala deleted file mode 100644 index 6887beff..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/SharedFPFMA.scala +++ /dev/null @@ -1,157 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -trait HasSharedFPUIO { - implicit val p: Parameters - val io_fp_req = IO(Decoupled(new FPInput())) - val io_fp_active = IO(Output(Bool())) - val io_fp_resp = IO(Flipped(Valid(new FPResult()))) -} - -class SharedScalarElementwiseFPFMA(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) - with HasFPUParameters - with HasSharedFPUIO { - - val supported_insns = FPFMAFactory(depth, true).insns - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( - FPAdd, FPMul, FPSwapVdV2, FPFMACmd, ReadsVD, FPSpecRM, Wide2VD, Wide2VS2, Reduction)) - - val vs1_eew = io.pipe(0).bits.rvs1_eew - val vs2_eew = io.pipe(0).bits.rvs2_eew - val vd_eew = io.pipe(0).bits.vd_eew - val vd_eew64 = io.pipe(0).bits.vd_eew64 - val vd_eew32 = io.pipe(0).bits.vd_eew32 - val vd_eew16 = io.pipe(0).bits.vd_eew16 - val eidx = Mux(io.pipe(0).bits.acc, 0.U, io.pipe(0).bits.eidx) - - // Functional unit is ready if not currently running and the scalar FPU is available - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - - io_fp_active := io.pipe.tail.map(_.valid).orR // head is pipe0, issuing the request - - // Create FPInput - val req = Wire(new FPInput) - req.ldst := false.B - req.wen := false.B - req.ren1 := true.B - req.ren2 := true.B - req.ren3 := ctrl.bool(ReadsVD) - req.swap12 := false.B - req.swap23 := ctrl.bool(FPAdd) && !ctrl.bool(FPMul) - req.typeTagIn := Mux(vd_eew64, D, Mux(vd_eew32, S, H)) - req.typeTagOut := Mux(vd_eew64, D, Mux(vd_eew32, S, H)) - req.fromint := false.B - req.toint := false.B - req.fastpipe := false.B - req.fma := true.B - req.div := false.B - req.sqrt := false.B - req.wflags := true.B - req.vec := true.B - req.rm := io.pipe(0).bits.frm - req.fmaCmd := ctrl.uint(FPFMACmd) - req.typ := 0.U - req.fmt := 0.U - - val rvs2_elem = io.pipe(0).bits.rvs2_elem - val rvs1_elem = io.pipe(0).bits.rvs1_elem - val rvd_elem = io.pipe(0).bits.rvd_elem - - val h_rvs2 = FType.H.recode(rvs2_elem(15,0)) - val h_rvs1 = FType.H.recode(rvs1_elem(15,0)) - val h_rvd = FType.H.recode(rvd_elem(15,0)) - - // For widening operations, widen the narrow operands to compute with the scalar FPU - val h_widen_rvs1 = Module(new hardfloat.RecFNToRecFN(5, 11, 8, 24)) - h_widen_rvs1.io.in := h_rvs1 - h_widen_rvs1.io.roundingMode := io.pipe(0).bits.frm - h_widen_rvs1.io.detectTininess := hardfloat.consts.tininess_afterRounding - - val h_widen_rvs2 = Module(new hardfloat.RecFNToRecFN(5, 11, 8, 24)) - h_widen_rvs2.io.in := h_rvs2 - h_widen_rvs2.io.roundingMode := io.pipe(0).bits.frm - h_widen_rvs2.io.detectTininess := hardfloat.consts.tininess_afterRounding - - val s_rvs2 = FType.S.recode(rvs2_elem(31,0)) - val s_rvs1 = FType.S.recode(rvs1_elem(31,0)) - val s_rvd = FType.S.recode(rvd_elem(31,0)) - - // For widening operations, widen the narrow operands to compute with the scalar FPU - val s_widen_rvs1 = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53)) - s_widen_rvs1.io.in := s_rvs1 - s_widen_rvs1.io.roundingMode := io.pipe(0).bits.frm - s_widen_rvs1.io.detectTininess := hardfloat.consts.tininess_afterRounding - - val s_widen_rvs2 = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53)) - s_widen_rvs2.io.in := s_rvs2 - s_widen_rvs2.io.roundingMode := io.pipe(0).bits.frm - s_widen_rvs2.io.detectTininess := hardfloat.consts.tininess_afterRounding - - val d_rvs2 = FType.D.recode(rvs2_elem) - val d_rvs1 = FType.D.recode(rvs1_elem) - val d_rvd = FType.D.recode(rvd_elem) - - val rvs2_recoded = Mux(vd_eew64, d_rvs2, Mux(vd_eew32, s_rvs2, h_rvs2)) - val rvs1_recoded = Mux(vd_eew64, d_rvs1, Mux(vd_eew32, s_rvs1, h_rvs1)) - val rvd_recoded = Mux(vd_eew64, d_rvd, Mux(vd_eew32, s_rvd, h_rvd)) - - // Set req.in1 - when (ctrl.bool(FPSwapVdV2)) { - req.in1 := rvd_recoded - } .elsewhen (vs2_eew === 3.U) { - req.in1 := d_rvs2 - } .elsewhen (ctrl.bool(Wide2VD) && vd_eew64) { - req.in1 := s_widen_rvs2.io.out - } .elsewhen (ctrl.bool(Wide2VD) && vd_eew32) { - req.in1 := h_widen_rvs2.io.out - } .elsewhen (vs2_eew === 2.U) { - req.in1 := s_rvs2 - } .otherwise { - req.in1 := h_rvs2 - } - - // Set req.in2 - when (vs1_eew === 3.U) { - req.in2 := d_rvs1 - } .elsewhen (ctrl.bool(Wide2VD) && (vs1_eew === 2.U) && !io.pipe(0).bits.acc) { - req.in2 := s_widen_rvs1.io.out - } .elsewhen (ctrl.bool(Wide2VD) && (vs1_eew === 1.U) && !io.pipe(0).bits.acc) { - req.in2 := h_widen_rvs1.io.out - } .elsewhen (vs1_eew === 2.U) { - req.in2 := s_rvs1 - } .otherwise { - req.in2 := h_rvs1 - } - - // Set req.in3 - when (ctrl.bool(FPSwapVdV2)) { - req.in3 := rvs2_recoded - } .otherwise { - req.in3 := rvd_recoded - } - - io_fp_req.bits := req - io_fp_req.valid := io.pipe(0).valid - io.pipe0_stall := !io_fp_req.ready - - when (io.pipe(depth-1).valid) { assert(io_fp_resp.valid) } - io.write.valid := io.pipe(depth-1).valid - io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg - io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) - io.write.bits.data := Fill(dLenB >> 3, Mux(io.pipe(depth-1).bits.vd_eew === 3.U, FType.D.ieee(io_fp_resp.bits.data), Mux(io.pipe(depth-1).bits.vd_eew === 2.U, - Fill(2, FType.S.ieee(unbox(io_fp_resp.bits.data, S, Some(FType.S)))), Fill(4, FType.H.ieee(unbox(io_fp_resp.bits.data, H, Some(FType.H))))))) - - io.set_fflags := DontCare - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.set_vxsat := false.B -} diff --git a/arch/src/main/scala/framework/gendomain/exu/fp/SharedFPMisc.scala b/arch/src/main/scala/framework/gendomain/exu/fp/SharedFPMisc.scala deleted file mode 100644 index 37eb9f59..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/fp/SharedFPMisc.scala +++ /dev/null @@ -1,222 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case object SharedFPMiscFactory extends FunctionalUnitFactory { - def insns = Seq( - FDIV.VV, FDIV.VF, - FRDIV.VF, - FSQRT_V, - FRSQRT7_V, - FREC7_V, - FCLASS_V, - FMIN.VV, FMIN.VF, FMAX.VV, FMAX.VF, - FSGNJ.VV, FSGNJ.VF, FSGNJN.VV, FSGNJN.VF, FSGNJX.VV, FSGNJX.VF, - MFEQ.VV, MFEQ.VF, MFNE.VV, MFNE.VF, - MFLT.VV, MFLT.VF, MFLE.VV, MFLE.VF, - MFGT.VF, MFGE.VF, - FREDMIN.VV, FREDMAX.VV, - FCVT_SGL, FCVT_WID, FCVT_NRW - ).map(_.elementWise) - def generate(implicit p: Parameters) = new SharedScalarElementwiseFPMisc()(p) -} - -class SharedScalarElementwiseFPMisc(implicit p: Parameters) extends IterativeFunctionalUnit()(p) - with HasFPUParameters - with HasSharedFPUIO { - - val fp_req = Wire(Decoupled(new FPInput)) - io_fp_req <> fp_req - - val supported_insns = SharedFPMiscFactory.insns - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched && !valid && io_fp_req.ready - - val ctrl = new VectorDecoder(op.funct3, op.funct6, 0.U, 0.U, supported_insns, Seq( - FPSwapVdV2, ReadsVD, WritesAsMask, FPSgnj, FPComp, FPSpecRM, FPMNE, FPMGT, Wide2VD, Wide2VS2, Reduction)) - - val issued = Reg(Bool()) - val has_wdata = Reg(Bool()) - val wdata = Reg(UInt(64.W)) - when (io.iss.valid && io.iss.ready) { - issued := false.B - has_wdata := false.B - } - - val vs1_eew = op.rvs1_eew - val vs2_eew = op.rvs2_eew - val vd_eew = op.vd_eew - val vd_eew64 = op.vd_eew64 - val vd_eew32 = op.vd_eew32 - val vd_eew16 = op.vd_eew16 - val eidx = Mux(op.acc, 0.U, op.eidx) - - val ctrl_isDiv = op.opff6.isOneOf(OPFFunct6.fdiv, OPFFunct6.frdiv) - val ctrl_funary0 = op.opff6.isOneOf(OPFFunct6.funary0) - val ctrl_funary1 = op.opff6.isOneOf(OPFFunct6.funary1) - val ctrl_vfclass = ctrl_funary1 && (op.rs1 === 16.U) - val ctrl_swap12 = op.opff6.isOneOf(OPFFunct6.frdiv) - - val rs1 = op.rs1 - val ctrl_widen = ctrl_funary0 && rs1(3) - val ctrl_narrow = rs1(4) - val ctrl_single_wide = ctrl_funary0 && !ctrl_widen && !ctrl_narrow - val ctrl_signed = rs1(0) - val ctrl_truncating = rs1(2) && rs1(1) - val ctrl_round_to_odd = rs1(0) - val ctrl_fptoint = ctrl_funary0 && ((!rs1(2) && !rs1(1)) || (rs1(2) && rs1(1))) - val ctrl_inttofp = ctrl_funary0 && (!rs1(2) && rs1(1)) - val ctrl_fptofp = ctrl_funary0 && (rs1(2) && !rs1(1)) - - val vfclass_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 16.U && valid - val vfrsqrt7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 4.U && valid - val vfrec7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 5.U && valid - - io.hazard.valid := valid - io.hazard.bits.eg := op.wvd_eg - - io_fp_active := valid && issued - - // Create FPInput - val req = Wire(new FPInput) - req.ldst := false.B - req.wen := false.B - req.ren1 := true.B - req.ren2 := !(ctrl_funary0 || ctrl_funary1) - req.ren3 := false.B - req.swap12 := false.B - req.swap23 := false.B - req.typeTagIn := Mux1H(UIntToOH(op.rvs2_eew), Seq(S, H, S, D)) - req.typeTagOut := Mux1H(UIntToOH(op.rvd_eew), Seq(S, H, S, D)) - req.fromint := ctrl_inttofp - req.toint := (ctrl_fptoint) || ctrl_vfclass || ctrl.bool(WritesAsMask) - req.fastpipe := ctrl_fptofp || ctrl.bool(FPSgnj) || ctrl.bool(FPComp) - req.fma := false.B - req.div := ctrl_isDiv - req.sqrt := ctrl_funary1 && (rs1 === 0.U) - req.wflags := !ctrl_vfclass && !ctrl.bool(FPSgnj) - req.vec := true.B - req.rm := Mux(ctrl_fptofp && ctrl_round_to_odd, "b110".U, Mux(ctrl_fptoint && ctrl_truncating, 1.U, Mux((!ctrl_isDiv && !ctrl_funary1 && !ctrl_funary0) || ctrl_vfclass, ctrl.uint(FPSpecRM), op.frm))) - req.fmaCmd := 0.U - req.typ := Mux(ctrl_funary0, Cat((ctrl_inttofp && ctrl_narrow) || (ctrl_fptoint && ctrl_widen) || (ctrl_single_wide && vd_eew64), !ctrl_signed), 0.U) - req.fmt := 0.U - - val rvs2_elem = op.rvs2_elem - val rvs1_elem = op.rvs1_elem - val rvd_elem = op.rvd_elem - - val h_rvs2_int = rvs2_elem(15,0) - val h_rvs2_fp = FType.H.recode(Mux(ctrl_funary0 && ctrl_truncating, rvs2_elem(15,9) << 9, rvs2_elem(15,0))) - val h_rvs2_unbox = unbox(box(h_rvs2_fp, FType.H), H, None) - - val h_rvs1 = FType.H.recode(rvs1_elem(15,0)) - val h_rvs1_unbox = unbox(box(h_rvs1, FType.H), H, None) - val h_rvd = FType.H.recode(rvd_elem(15,0)) - - val s_rvs2_int = rvs2_elem(31,0) - val s_rvs2_fp = FType.S.recode(rvs2_elem(31,0)) - val s_rvs2_unbox = unbox(box(s_rvs2_fp, FType.S), S, None) - - val s_rvs1 = FType.S.recode(rvs1_elem(31,0)) - val s_rvs1_unbox = unbox(box(s_rvs1, FType.S), S, None) - val s_rvd = FType.S.recode(rvd_elem(31,0)) - - val d_rvs2_int = rvs2_elem - val d_rvs2_fp = FType.D.recode(rvs2_elem) - - val d_rvs1 = FType.D.recode(rvs1_elem) - val d_rvd = FType.D.recode(rvd_elem) - - val h_isNaN = FType.H.isNaN(h_rvs2_fp) || FType.H.isNaN(h_rvs1) - val s_isNaN = FType.S.isNaN(s_rvs2_fp) || FType.S.isNaN(s_rvs1) - val d_isNaN = FType.D.isNaN(d_rvs2_fp) || FType.D.isNaN(d_rvs1) - - val mgt_NaN = ctrl.bool(WritesAsMask) && ctrl.bool(FPMGT) && ((vd_eew64 && d_isNaN) || (vd_eew32 && s_isNaN) || (vd_eew16 && h_isNaN)) - val mgt_NaN_reg = RegInit(false.B) - - // Set req.in1 - when (ctrl_swap12) { - req.in1 := Mux(vd_eew64, d_rvs1, Mux(vd_eew32, s_rvs1_unbox, h_rvs1_unbox)) - } .elsewhen (ctrl_inttofp) { - req.in1 := rvs2_elem - } .otherwise { - req.in1 := Mux(vd_eew64 && (!ctrl_widen || (ctrl_funary0 && ctrl_narrow)), d_rvs2_fp, Mux(vd_eew32 && (!ctrl_widen || (ctrl_funary0 && ctrl_narrow)), s_rvs2_unbox, h_rvs2_unbox)) - } - - // Set req.in2 - when (ctrl_swap12) { - req.in2 := Mux(vd_eew64, d_rvs2_fp, Mux(vd_eew32, s_rvs2_unbox, h_rvs2_unbox)) - } .otherwise { - req.in2 := Mux(vd_eew64, d_rvs1, Mux(vd_eew32, s_rvs1_unbox, h_rvs1_unbox)) - } - - // Set req.in3 - req.in3 := 0.U - - fp_req.bits := req - fp_req.valid := valid && !issued && !vfrsqrt7_inst && !vfrec7_inst && !mgt_NaN - when (fp_req.fire) { issued := true.B } - - // Approximation Instructions - - // Reciprocal Sqrt Approximation - val recSqrt7 = Module(new VFRSQRT7) - recSqrt7.io.rvs2_input := rvs2_elem - recSqrt7.io.eew := op.rvs2_eew - - // Reciprocal Approximation - val rec7 = Module(new VFREC7) - rec7.io.rvs2_input := rvs2_elem - rec7.io.eew := op.rvs2_eew - rec7.io.frm := op.frm - - when (io_fp_resp.valid) { - has_wdata := true.B - when (ctrl.bool(WritesAsMask)) { - when (ctrl.bool(FPMNE) || (ctrl.bool(FPMGT) && !mgt_NaN)) { - wdata := Fill(dLen, !io_fp_resp.bits.data(0)) - } .elsewhen (ctrl.bool(FPMGT) && mgt_NaN) { - wdata := Fill(dLen, 0.U) - } .otherwise { - wdata := Fill(dLen, io_fp_resp.bits.data(0)) - } - } .elsewhen (vfclass_inst) { - wdata := Mux(vd_eew64, Cat(0.U(54.W), io_fp_resp.bits.data(9,0)), Fill(2, Cat(0.U(22.W), io_fp_resp.bits.data(9,0)))) - } .elsewhen (ctrl_fptoint) { - wdata := Mux(vd_eew64, io_fp_resp.bits.data(63,0), Fill(2, io_fp_resp.bits.data(31,0))) - } .otherwise { - wdata := Mux(vd_eew64, FType.D.ieee(io_fp_resp.bits.data), Mux(vd_eew32, Fill(2, FType.S.ieee(unbox(io_fp_resp.bits.data, 0.U, Some(FType.S)))), - Fill(4, FType.H.ieee(unbox(io_fp_resp.bits.data, H, Some(FType.H)))))) - } - } - - val mask_write_offset = VecInit.tabulate(4)({ eew => - Cat(op.eidx(log2Ceil(dLen)-1, dLenOffBits-eew), 0.U((dLenOffBits-eew).W)) - })(op.vd_eew) - val mask_write_mask = (VecInit.tabulate(4)({ eew => - VecInit(op.wmask.asBools.grouped(1 << eew).map(_.head).toSeq).asUInt - })(op.vd_eew) << mask_write_offset)(dLen-1,0) - - io.write.valid := (has_wdata || vfrsqrt7_inst || vfrec7_inst || mgt_NaN) && valid - io.write.bits.eg := op.wvd_eg - io.write.bits.mask := Mux(ctrl.bool(WritesAsMask), mask_write_mask, FillInterleaved(8, op.wmask)) - io.write.bits.data := Mux1H(Seq(vfrsqrt7_inst, vfrec7_inst, has_wdata), - Seq(Fill(dLenB >> 3, recSqrt7.io.out), Fill(dLenB >> 3, rec7.io.out), Fill(dLenB >> 3, wdata))) - - last := io.write.fire - - io.set_fflags := DontCare - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - io.set_vxsat := false.B - - io.acc := op.acc - io.tail := op.tail -} diff --git a/arch/src/main/scala/framework/gendomain/exu/int/BitwisePipe.scala b/arch/src/main/scala/framework/gendomain/exu/int/BitwisePipe.scala deleted file mode 100644 index c4cb9e06..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/int/BitwisePipe.scala +++ /dev/null @@ -1,52 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case object BitwisePipeFactory extends FunctionalUnitFactory { - def insns = Seq( - AND.VV, AND.VX, AND.VI, OR.VV, OR.VX, OR.VI, XOR.VV, XOR.VX, XOR.VI, - MANDNOT.VV, MAND.VV, MOR.VV, MXOR.VV, MORNOT.VV, MNAND.VV, MNOR.VV, MXNOR.VV, - REDAND.VV, REDOR.VV, REDXOR.VV, - // Zvbb - ANDN.VV, ANDN.VX - ) - def generate(implicit p: Parameters) = new BitwisePipe()(p) -} - -class BitwisePipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { - val supported_insns = BitwisePipeFactory.insns - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, - Seq(BWAnd, BWOr, BWXor, BWInvOut, BWInv1)) - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - - val in1 = Mux(ctrl.bool(BWInv1), ~io.pipe(0).bits.rvs1_data, io.pipe(0).bits.rvs1_data) - val in2 = io.pipe(0).bits.rvs2_data - val op = Mux1H(Seq( - (ctrl.bool(BWAnd), (in1 & in2)), - (ctrl.bool(BWOr) , (in1 | in2)), - (ctrl.bool(BWXor), (in1 ^ in2)) - )) - val out = Mux(ctrl.bool(BWInvOut), ~op, op) - - io.pipe0_stall := false.B - io.write.valid := io.pipe(0).valid - io.write.bits.eg := io.pipe(0).bits.wvd_eg - io.write.bits.mask := Mux(io.pipe(0).bits.isOpm && !io.pipe(0).bits.acc, - io.pipe(0).bits.full_tail_mask, - FillInterleaved(8, io.pipe(0).bits.wmask)) - io.write.bits.data := out - - io.set_vxsat := false.B - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare -} diff --git a/arch/src/main/scala/framework/gendomain/exu/int/ElementwiseMultiplyPipe.scala b/arch/src/main/scala/framework/gendomain/exu/int/ElementwiseMultiplyPipe.scala deleted file mode 100644 index 5e85599a..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/int/ElementwiseMultiplyPipe.scala +++ /dev/null @@ -1,68 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class ElementwiseMultiplyPipe(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) { - val supported_insns = IntegerMultiplyFactory(depth, false).insns - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - io.set_vxsat := false.B - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( - MULHi, MULSign1, MULSign2, MULSwapVdV2, MULAccumulate, MULSub)) - - val in_eew = io.pipe(0).bits.rvs1_eew - val eidx = io.pipe(0).bits.eidx - - val in_vs1 = Mux(ctrl.bool(MULSign1), sextElem(io.pipe(0).bits.rvs1_elem, in_eew), io.pipe(0).bits.rvs1_elem) - val in_vs2 = Mux(ctrl.bool(MULSign2), sextElem(io.pipe(0).bits.rvs2_elem, in_eew), io.pipe(0).bits.rvs2_elem) - val in_vd = io.pipe(0).bits.rvd_elem - - val prod = in_vs1.asSInt * Mux(ctrl.bool(MULSwapVdV2), in_vd, in_vs2).asSInt - ///////////////// pipe - val prod_pipe = Pipe(io.pipe(0).valid, prod, depth-2).bits - val in_vs2_pipe = Pipe(io.pipe(0).valid, in_vs2, depth-2).bits - val in_vd_pipe = Pipe(io.pipe(0).valid, in_vd, depth-2).bits - val ctrl_MULSub = Pipe(io.pipe(0).valid, ctrl.bool(MULSub), depth-2).bits - val ctrl_MULSwapVdV2 = Pipe(io.pipe(0).valid, ctrl.bool(MULSwapVdV2), depth-2).bits - val ctrl_MULAccumulate = Pipe(io.pipe(0).valid, ctrl.bool(MULAccumulate), depth-2).bits - val ctrl_MULHi = Pipe(io.pipe(0).valid, ctrl.bool(MULHi), depth-2).bits - val ctrl_smul = io.pipe(depth-2).bits.isOpi - val out_eew = io.pipe(depth-2).bits.vd_eew - - val hi = VecInit.tabulate(4)({ eew => prod_pipe >> (8 << eew) })(out_eew)(63,0) - val lo = VecInit.tabulate(4)({ eew => prod_pipe((8 << eew)-1,0)})(out_eew)(63,0) - val madd = Mux(ctrl_MULSub, ~lo, lo) + ctrl_MULSub + Mux(ctrl_MULSwapVdV2, in_vs2_pipe, in_vd_pipe) - val rounding_incr = VecInit.tabulate(4)({ eew => RoundingIncrement(io.pipe(depth-2).bits.vxrm, prod_pipe((8 << eew)-1,0)) })(out_eew) - val smul = VecInit.tabulate(4)({ eew => prod_pipe >> ((8 << eew) - 1) })(out_eew) + Cat(0.U(1.W), rounding_incr).asSInt - val smul_clip_neg = VecInit.tabulate(4)({ eew => (-1 << ((8 << eew)-1)).S })(out_eew) - val smul_clip_pos = VecInit.tabulate(4)({ eew => ((1 << ((8 << eew)-1)) - 1).S })(out_eew) - val smul_clip_hi = smul > smul_clip_pos - val smul_clip_lo = smul < smul_clip_neg - val smul_clipped = Mux(smul_clip_hi, smul_clip_pos, 0.S) | Mux(smul_clip_lo, smul_clip_neg, 0.S) | Mux(!smul_clip_hi && !smul_clip_lo, smul, 0.S) - val smul_sat = smul_clip_hi || smul_clip_lo - val out = Mux(ctrl_MULAccumulate, madd, 0.U) | Mux(ctrl_smul, smul_clipped.asUInt, 0.U) | Mux(!ctrl_MULAccumulate && !ctrl_smul, Mux(ctrl_MULHi, hi, lo), 0.U) - - ///////////////// pipe - val pipe_out = Pipe(io.pipe(depth-2).valid, out(63,0), 1).bits - val pipe_vxsat = Pipe(io.pipe(depth-2).valid, smul_sat && ctrl_smul, 1).bits - val wdata = VecInit.tabulate(4)({ eew => Fill(dLenB >> eew, pipe_out((8< Fill(dLenB >> eew, write_elem((8< prod >> (8 << eew) })(op.vd_eew)(63,0) - val lo = VecInit.tabulate(4)({ eew => prod((8 << eew)-1,0)})(op.vd_eew)(63,0) - val madd = Mux(mul_ctrl.bool(MULSub), ~lo, lo) + mul_ctrl.bool(MULSub) + Mux(mul_ctrl.bool(MULSwapVdV2), - op.rvs2_elem, op.rvd_elem) - val rounding_incr = VecInit.tabulate(4)({ eew => RoundingIncrement(op.vxrm, prod((8 << eew)-1,0)) })(op.vd_eew) - val smul = VecInit.tabulate(4)({ eew => prod >> ((8 << eew) - 1) })(op.vd_eew) + Cat(0.U(1.W), rounding_incr).asSInt - val smul_clip_neg = VecInit.tabulate(4)({ eew => (-1 << ((8 << eew)-1)).S })(op.vd_eew) - val smul_clip_pos = VecInit.tabulate(4)({ eew => ((1 << ((8 << eew)-1)) - 1).S })(op.vd_eew) - val smul_clip_hi = smul > smul_clip_pos - val smul_clip_lo = smul < smul_clip_neg - val smul_clipped = Mux(smul_clip_hi, smul_clip_pos, 0.S) | Mux(smul_clip_lo, smul_clip_neg, 0.S) | Mux(!smul_clip_hi && !smul_clip_lo, smul, 0.S) - val smul_sat = smul_clip_hi || smul_clip_lo - val mul_wdata = WireInit(Mux(mul_ctrl.bool(MULHi), hi, lo)) - when (mul_ctrl.bool(MULAccumulate) || is_smul) { - mul_wdata := Mux(mul_ctrl.bool(MULAccumulate), madd, 0.U) | Mux(is_smul, smul_clipped.asUInt, 0.U) - - } - when (mul_ctrl.matched) { - write_elem := mul_wdata - io.set_vxsat := is_smul && smul_sat && io.write.fire && op.wmask =/= 0.U - } - } - - div.io.resp.ready := io.write.ready - io.write.valid := div.io.resp.valid - io.write.bits.eg := op.wvd_eg - io.write.bits.mask := FillInterleaved(8, op.wmask) - io.write.bits.data := wdata - - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare - - last := io.write.fire - - io.acc := false.B - io.tail := false.B -} diff --git a/arch/src/main/scala/framework/gendomain/exu/int/IntegerPipe.scala b/arch/src/main/scala/framework/gendomain/exu/int/IntegerPipe.scala deleted file mode 100644 index 12470655..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/int/IntegerPipe.scala +++ /dev/null @@ -1,386 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class AdderArray(dLenB: Int) extends Module { - val io = IO(new Bundle { - val in1 = Input(Vec(dLenB, UInt(8.W))) - val in2 = Input(Vec(dLenB, UInt(8.W))) - val incr = Input(Vec(dLenB, Bool())) - val mask_carry = Input(UInt(dLenB.W)) - - val signed = Input(Bool()) - val eew = Input(UInt(2.W)) - val avg = Input(Bool()) - val rm = Input(UInt(2.W)) - val sub = Input(Bool()) - val cmask = Input(Bool()) - - val out = Output(Vec(dLenB, UInt(8.W))) - val carry = Output(Vec(dLenB, Bool())) - }) - - val use_carry = VecInit.tabulate(4)({ eew => - Fill(dLenB >> eew, ~(1.U((1 << eew).W))) - })(io.eew) - val carry_clear = Mux(io.avg, use_carry.asBools.map(Cat(~(0.U(8.W)), _)).asUInt, ~(0.U(73.W))) - val carry_restore = Mux(io.avg, use_carry.asBools.map(Cat(0.U(8.W), _)).asUInt, 0.U(73.W)) - - val avg_in1 = VecInit.tabulate(4) { eew => - VecInit(io.in1.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(e => Cat(io.signed && e((8<> 1)).asUInt - }(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) - val avg_in2 = VecInit.tabulate(4) { eew => - VecInit(io.in2.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(e => Cat(io.signed && e((8<> 1)).asUInt - }(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) - - val in1 = Mux(io.avg, avg_in1, io.in1) - val in2 = Mux(io.avg, avg_in2, io.in2) - - for (i <- 0 until (dLenB >> 3)) { - val h = (i+1)*8-1 - val l = i*8 - val io_in1_slice = io.in1.slice(l,h+1) - val io_in2_slice = io.in2.slice(l,h+1) - val in1_slice = in1.slice(l,h+1) - val in2_slice = in2.slice(l,h+1) - val use_carry_slice = use_carry(h,l).asBools - val mask_carry_slice = io.mask_carry(h,l).asBools - val incr_slice = io.incr.slice(l,h+1) - - val in1_dummy_bits = (io_in1_slice - .zip(io_in2_slice) - .zip(use_carry_slice) - .zip(mask_carry_slice).map { case(((i1, i2), carry), mask_bit) => { - val avg_bit = ((io.sub ^ i1(0)) & i2(0)) | (((io.sub ^ i1(0)) ^ i2(0)) & io.sub) - val bit = (!io.cmask & io.sub) | (io.cmask & (io.sub ^ mask_bit)) - Mux(carry, 1.U(1.W), Mux(io.avg, avg_bit, bit)) - }}) - val in2_dummy_bits = (io_in1_slice - .zip(io_in2_slice) - .zip(use_carry_slice) - .zip(mask_carry_slice).map { case(((i1, i2), carry), mask_bit) => { - val avg_bit = ((io.sub ^ i1(0)) & i2(0)) | (((io.sub ^ i1(0)) ^ i2(0)) & io.sub) - val bit = (!io.cmask & io.sub) | (io.cmask & (io.sub ^ mask_bit)) - Mux(carry, 0.U(1.W), Mux(io.avg, avg_bit, bit)) - }}) - val round_incrs = (io_in1_slice - .zip(io_in2_slice) - .zipWithIndex.map { case((l, r), i) => { - val sum = r(1,0) +& ((l(1,0) ^ Fill(2, io.sub)) +& io.sub) - Cat(0.U(7.W), Cat(Mux(io.avg, RoundingIncrement(io.rm, sum(1), sum(0), None) & !use_carry_slice(i), 0.U), 0.U(1.W))) - }} - .asUInt) - - - val in1_constructed = in1_slice.zip(in1_dummy_bits).map { case(i1, dummy_bit) => (i1 ^ Fill(8, io.sub)) ## dummy_bit }.asUInt - val in2_constructed = in2_slice.zip(in2_dummy_bits).map { case(i2, dummy_bit) => i2 ## dummy_bit }.asUInt - - val incr_constructed = incr_slice.zip(use_carry_slice).map { case(incr, masking) => Cat(0.U(7.W), Cat(Mux(!masking, incr, 0.U(1.W)), 0.U(1.W))) }.asUInt - - val sum = (((in1_constructed +& in2_constructed) & carry_clear) | carry_restore) +& round_incrs +& incr_constructed - - for (j <- 0 until 8) { - io.out((i*8) + j) := sum(((j+1)*9)-1, (j*9) + 1) - io.carry((i*8) + j) := sum((j+1)*9) - } - } -} - -class CompareArray(dLenB: Int) extends Module { - val io = IO(new Bundle { - val in1 = Input(Vec(dLenB, UInt(8.W))) - val in2 = Input(Vec(dLenB, UInt(8.W))) - val eew = Input(UInt(2.W)) - val signed = Input(Bool()) - val less = Input(Bool()) - val sle = Input(Bool()) - val inv = Input(Bool()) - - val minmax = Output(UInt(dLenB.W)) - val result = Output(UInt(dLenB.W)) - }) - - val eq = io.in2.zip(io.in1).map { x => x._1 === x._2 } - val lt = io.in2.zip(io.in1).map { x => x._1 < x._2 } - - val minmax_bits = Wire(Vec(4, UInt(dLenB.W))) - val result_bits = Wire(Vec(4, UInt(dLenB.W))) - - io.minmax := minmax_bits(io.eew) - io.result := result_bits(io.eew) - - for (eew <- 0 until 4) { - val lts = lt.grouped(1 << eew) - val eqs = eq.grouped(1 << eew) - val bits = VecInit(lts.zip(eqs).zipWithIndex.map { case ((e_lts, e_eqs), i) => - val eq = e_eqs.andR - val in1_hi = io.in1((i+1)*(1< l || (e && p) } - Mux(io.less, lt || (io.sle && eq), io.inv ^ eq) - }.toSeq).asUInt - minmax_bits(eew) := FillInterleaved(1 << eew, bits) - result_bits(eew) := Fill(1 << eew, bits) - } -} - -class SaturatedSumArray(dLenB: Int) extends Module { - val dLen = dLenB * 8 - val io = IO(new Bundle { - val sum = Input(Vec(dLenB, UInt(8.W))) - val carry = Input(Vec(dLenB, Bool())) - val in1_sign = Input(Vec(dLenB, Bool())) - val in2_sign = Input(Vec(dLenB, Bool())) - val sub = Input(Bool()) - val eew = Input(UInt(2.W)) - val signed = Input(Bool()) - - val set_vxsat = Output(UInt(dLenB.W)) - val out = Output(Vec(dLenB, UInt(8.W))) - }) - - val unsigned_mask = VecInit.tabulate(4)({ eew => - FillInterleaved(1 << eew, VecInit.tabulate(dLenB >> eew)(i => io.sub ^ io.carry(((i+1) << eew)-1)).asUInt) - })(io.eew) - val unsigned_clip = Mux(io.sub, 0.U(dLen.W), ~(0.U(dLen.W))).asTypeOf(Vec(dLenB, UInt(8.W))) - - val (signed_masks, signed_clips): (Seq[UInt], Seq[UInt]) = Seq.tabulate(4)({ eew => - val out_sign = VecInit.tabulate(dLenB >> eew)(i => io.sum(((i+1)<> eew)(i => io.in2_sign(((i+1)<> eew)(i => io.in1_sign(((i+1)< Mux(sign, clip_neg, clip_pos))).asUInt - (FillInterleaved((1 << eew), clip), clip_value) - }).unzip - val signed_mask = VecInit(signed_masks)(io.eew) - val signed_clip = VecInit(signed_clips)(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) - - val mask = Mux(io.signed, signed_mask, unsigned_mask) - val clip = Mux(io.signed, signed_clip, unsigned_clip) - io.out := io.sum.zipWithIndex.map { case (o,i) => Mux(mask(i), clip(i), o) } - io.set_vxsat := mask -} - -case object IntegerPipeFactory extends FunctionalUnitFactory { - def insns = Seq( - ADD.VV, ADD.VX, ADD.VI, SUB.VV, SUB.VX, RSUB.VX, RSUB.VI, - WADDU.VV, WADDU.VX, WADD.VV, WADD.VX, WSUBU.VV, WSUBU.VX, WSUB.VV, WSUB.VX, - WADDUW.VV, WADDUW.VX, WADDW.VV, WADDW.VX, WSUBUW.VV, WSUBUW.VX, WSUBW.VV, WSUBW.VX, - ADC.VV, ADC.VX, ADC.VI, MADC.VV, MADC.VX, MADC.VI, - SBC.VV, SBC.VX, MSBC.VV, MSBC.VX, - NEXT.VV, - MSEQ.VV, MSEQ.VX, MSEQ.VI, MSNE.VV, MSNE.VX, MSNE.VI, - MSLTU.VV, MSLTU.VX, MSLT.VV, MSLT.VX, - MSLEU.VV, MSLEU.VX, MSLEU.VI, MSLE.VV, MSLE.VX, MSLE.VI, - MSGTU.VX, MSGTU.VI, MSGT.VX, MSGT.VI, - MINU.VV, MINU.VX, MIN.VV, MIN.VX, - MAXU.VV, MAXU.VX, MAX.VV, MAX.VX, - MERGE.VV, MERGE.VX, MERGE.VI, - SADDU.VV, SADDU.VX, SADDU.VI, SADD.VV, SADD.VX, SADD.VI, - SSUBU.VV, SSUBU.VX, SSUB.VV, SSUB.VX, - AADDU.VV, AADDU.VX, AADD.VV, AADD.VX, - ASUBU.VV, ASUBU.VX, ASUB.VV, ASUB.VX, - REDSUM.VV, WREDSUM.VV, WREDSUMU.VV, - REDMINU.VV, REDMIN.VV, REDMAXU.VV, REDMAX.VV, - FMERGE.VF, - // zvbb - BREV8.VV, BREV.VV, REV8.VV, CLZ.VV, CTZ.VV, CPOP.VV - ) - def generate(implicit p: Parameters) = new IntegerPipe()(p) -} - -class IntegerPipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { - val supported_insns = IntegerPipeFactory.insns - - val rvs1_eew = io.pipe(0).bits.rvs1_eew - val rvs2_eew = io.pipe(0).bits.rvs2_eew - val vd_eew = io.pipe(0).bits.vd_eew - - val ctrl = new VectorDecoder( - io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, io.pipe(0).bits.rs1, io.pipe(0).bits.rs2, - supported_insns, - Seq(UsesCmp, UsesNarrowingSext, UsesMinMax, UsesMerge, UsesSat, - DoSub, WideningSext, Averaging, - CarryIn, AlwaysCarryIn, CmpLess, Swap12, WritesAsMask, - UsesBitSwap, UsesCountZeros)) - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - - val carry_in = ctrl.bool(CarryIn) && (!io.pipe(0).bits.vm || ctrl.bool(AlwaysCarryIn)) - - val sat_signed = io.pipe(0).bits.funct6(0) - val sat_addu = io.pipe(0).bits.funct6(1,0) === 0.U - val sat_subu = io.pipe(0).bits.funct6(1,0) === 2.U - - val rvs1_bytes = io.pipe(0).bits.rvs1_data.asTypeOf(Vec(dLenB, UInt(8.W))) - val rvs2_bytes = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(dLenB, UInt(8.W))) - - val in1_bytes = Mux(ctrl.bool(Swap12), rvs2_bytes, rvs1_bytes) - val in2_bytes = Mux(ctrl.bool(Swap12), rvs1_bytes, rvs2_bytes) - - val narrow_vs1 = narrow2_expand(rvs1_bytes, rvs1_eew, - (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), - ctrl.bool(WideningSext)) - val narrow_vs2 = narrow2_expand(rvs2_bytes, rvs2_eew, - (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), - ctrl.bool(WideningSext)) - - val add_mask_carry = VecInit.tabulate(4)({ eew => - VecInit((0 until dLenB >> eew).map { i => io.pipe(0).bits.rmask(i) | 0.U((1 << eew).W) }).asUInt - })(rvs2_eew) - val add_carry = Wire(Vec(dLenB, UInt(1.W))) - val add_out = Wire(Vec(dLenB, UInt(8.W))) - - val merge_mask = VecInit.tabulate(4)({eew => FillInterleaved(1 << eew, io.pipe(0).bits.rmask((dLenB >> eew)-1,0))})(rvs2_eew) - val merge_out = VecInit((0 until dLenB).map { i => Mux(merge_mask(i), rvs1_bytes(i), rvs2_bytes(i)) }).asUInt - - val carryborrow_res = VecInit.tabulate(4)({ eew => - Fill(1 << eew, VecInit(add_carry.grouped(1 << eew).map(_.last).toSeq).asUInt) - })(rvs1_eew) - - val adder_arr = Module(new AdderArray(dLenB)) - adder_arr.io.in1 := Mux(rvs1_eew < vd_eew, narrow_vs1, in1_bytes) - adder_arr.io.in2 := Mux(rvs2_eew < vd_eew, narrow_vs2, in2_bytes) - adder_arr.io.incr.foreach(_ := false.B) - adder_arr.io.avg := ctrl.bool(Averaging) - adder_arr.io.eew := vd_eew - adder_arr.io.rm := io.pipe(0).bits.vxrm - adder_arr.io.mask_carry := add_mask_carry - adder_arr.io.sub := ctrl.bool(DoSub) - adder_arr.io.cmask := carry_in - adder_arr.io.signed := io.pipe(0).bits.funct6(0) - add_out := adder_arr.io.out - add_carry := adder_arr.io.carry - - val cmp_arr = Module(new CompareArray(dLenB)) - cmp_arr.io.in1 := in1_bytes - cmp_arr.io.in2 := in2_bytes - cmp_arr.io.eew := rvs1_eew - cmp_arr.io.signed := io.pipe(0).bits.funct6(0) - cmp_arr.io.less := ctrl.bool(CmpLess) - cmp_arr.io.sle := io.pipe(0).bits.funct6(2,1) === 2.U - cmp_arr.io.inv := io.pipe(0).bits.funct6(0) - val minmax_out = VecInit(rvs1_bytes.zip(rvs2_bytes).zip(cmp_arr.io.minmax.asBools).map { case ((v1, v2), s) => Mux(s, v2, v1) }).asUInt - - val mask_out = Fill(8, Mux(ctrl.bool(UsesCmp), cmp_arr.io.result, carryborrow_res ^ Fill(dLenB, ctrl.bool(DoSub)))) - - val sat_arr = Module(new SaturatedSumArray(dLenB)) - sat_arr.io.sum := add_out - sat_arr.io.carry := add_carry - sat_arr.io.in1_sign := rvs1_bytes.map(_(7)) - sat_arr.io.in2_sign := rvs2_bytes.map(_(7)) - sat_arr.io.sub := ctrl.bool(DoSub) - sat_arr.io.eew := vd_eew - sat_arr.io.signed := io.pipe(0).bits.funct6(0) - val sat_out = sat_arr.io.out.asUInt - - val narrowing_ext_eew_mul = io.pipe(0).bits.vd_eew - rvs2_eew - val narrowing_ext_in = (1 until 4).map { m => - val w = dLen >> m - val in = Wire(UInt(w.W)) - val in_mul = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(1 << m, UInt(w.W))) - val sel = (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(m-1,0) - in := in_mul(sel) - in - } - val narrowing_ext_out = Mux1H((1 until 4).map { eew => (0 until eew).map { vs2_eew => - (vd_eew === eew.U && rvs2_eew === vs2_eew.U) -> { - val mul = eew - vs2_eew - val in = narrowing_ext_in(mul-1).asTypeOf(Vec(dLenB >> eew, UInt((8 << vs2_eew).W))) - val out = Wire(Vec(dLenB >> eew, UInt((8 << eew).W))) - out.zip(in).foreach { case (l, r) => l := Cat( - Fill((8 << eew) - (8 << vs2_eew), io.pipe(0).bits.rs1(0) && r((8 << vs2_eew)-1)), - r) - } - out.asUInt - } - }}.flatten) - - val brev_bytes = VecInit(in2_bytes.map(b => Reverse(b))).asUInt - val brev_elements = VecInit((0 until 4).map { eew => - VecInit(in2_bytes.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(b => Reverse(b))).asUInt - })(vd_eew) - val rev8_elements = VecInit((0 until 4).map { eew => - VecInit(in2_bytes.asTypeOf(Vec(dLenB >> eew, Vec(1 << eew, UInt(8.W)))).map(b => VecInit(b.reverse))).asUInt - })(vd_eew) - val swap_out = Mux1H(Seq( - (io.pipe(0).bits.rs1(1,0) === 0.U) -> brev_bytes, - (io.pipe(0).bits.rs1(1,0) === 1.U) -> rev8_elements, - (io.pipe(0).bits.rs1(1,0) === 2.U) -> brev_elements - )) - - val tz_in = Mux(io.pipe(0).bits.rs1(0), in2_bytes, brev_elements.asTypeOf(Vec(dLenB, UInt(8.W)))) - val tz_8b = tz_in.map(b => (b === 0.U, (PriorityEncoderOH(1.U ## b) - 1.U)(7,0))) - val tz_16b = tz_8b.grouped(2).toSeq.map(t => - (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(8.W)), t(0)._2)) - ) - val tz_32b = tz_16b.grouped(2).toSeq.map(t => - (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(16.W)), t(0)._2)) - ) - val tz_64b = tz_32b.grouped(2).toSeq.map(t => - (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(32.W)), t(0)._2)) - ) - val tz_out = WireInit(VecInit( - VecInit(tz_8b.map(_._2)).asUInt, - VecInit(tz_16b.map(_._2)).asUInt, - VecInit(tz_32b.map(_._2)).asUInt, - VecInit(tz_64b.map(_._2)).asUInt - )(vd_eew).asTypeOf(Vec(dLenB, UInt(8.W)))) - - val cpop_in = Mux(io.pipe(0).bits.rs1(1), in2_bytes, tz_out) - val cpop_8b = cpop_in.map(b => PopCount(b)) - val cpop_16b = cpop_8b.grouped(2).toSeq.map(_.reduce(_ +& _)) - val cpop_32b = cpop_16b.grouped(2).toSeq.map(_.reduce(_ +& _)) - val cpop_64b = cpop_32b.grouped(2).toSeq.map(_.reduce(_ +& _)) - val cpops = Seq(cpop_8b, cpop_16b, cpop_32b, cpop_64b) - val count_out = WireInit(VecInit((0 until 4).map { eew => - val out = Wire(Vec(dLenB >> eew, UInt((8 << eew).W))) - out := VecInit(cpops(eew)) - out.asUInt - })(vd_eew)) - - val outs = Seq( - (ctrl.bool(UsesNarrowingSext) , narrowing_ext_out), - (ctrl.bool(WritesAsMask) , mask_out), - (ctrl.bool(UsesMinMax) , minmax_out), - (ctrl.bool(UsesMerge) , merge_out), - (ctrl.bool(UsesSat) , sat_out), - (ctrl.bool(UsesBitSwap) , swap_out), - (ctrl.bool(UsesCountZeros) , count_out) - ) - val out = Mux(outs.map(_._1).orR, Mux1H(outs), add_out.asUInt) - - val mask_write_offset = VecInit.tabulate(4)({ eew => - Cat(io.pipe(0).bits.eidx(log2Ceil(dLen)-1, dLenOffBits-eew), 0.U((dLenOffBits-eew).W)) - })(rvs1_eew) - val mask_write_mask = (VecInit.tabulate(4)({ eew => - VecInit(io.pipe(0).bits.wmask.asBools.grouped(1 << eew).map(_.head).toSeq).asUInt - })(rvs1_eew) << mask_write_offset)(dLen-1,0) - - io.pipe0_stall := false.B - io.write.valid := io.pipe(0).valid - io.write.bits.eg := io.pipe(0).bits.wvd_eg - io.write.bits.mask := Mux(ctrl.bool(WritesAsMask), mask_write_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) - io.write.bits.data := out - - val sat_vxsat = Mux(ctrl.bool(UsesSat) , sat_arr.io.set_vxsat , 0.U) & io.pipe(0).bits.wmask - io.set_vxsat := io.pipe(0).valid && (sat_vxsat =/= 0.U) - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare -} diff --git a/arch/src/main/scala/framework/gendomain/exu/int/SegmentedMultiplyPipe.scala b/arch/src/main/scala/framework/gendomain/exu/int/SegmentedMultiplyPipe.scala deleted file mode 100644 index e7a404fa..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/int/SegmentedMultiplyPipe.scala +++ /dev/null @@ -1,272 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -case class IntegerMultiplyFactory(depth: Int, segmented: Boolean) extends FunctionalUnitFactory { - def base_insns = Seq( - MUL.VV, MUL.VX, MULH.VV, MULH.VX, - MULHU.VV, MULHU.VX, MULHSU.VV, MULHSU.VX, - WMUL.VV, WMUL.VX, WMULU.VV, WMULU.VX, - WMULSU.VV, WMULSU.VX, - MACC.VV, MACC.VX, NMSAC.VV, NMSAC.VX, - MADD.VV, MADD.VX, NMSUB.VV, NMSUB.VX, - WMACC.VV, WMACC.VX, WMACCU.VV, WMACCU.VX, - WMACCSU.VV , WMACCSU.VX, WMACCUS.VV, WMACCUS.VX, - SMUL.VV, SMUL.VX) - def insns = if (segmented) base_insns else base_insns.map(_.elementWise) - def generate(implicit p: Parameters) = if (segmented) { - new SegmentedMultiplyPipe(depth)(p) - } else { - new ElementwiseMultiplyPipe(depth)(p) - } -} - -class SegmentedMultiplyPipe(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p) { - val supported_insns = IntegerMultiplyFactory(depth, true).insns - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - io.set_vxsat := false.B - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - - val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq( - MULHi, MULSign1, MULSign2, MULSwapVdV2, MULAccumulate, MULSub)) - - val in_eew = io.pipe(0).bits.rvs1_eew - val out_eew = io.pipe(0).bits.vd_eew - - val in_vs1 = io.pipe(0).bits.rvs1_data - val in_vs2 = io.pipe(0).bits.rvs2_data - val in_vd = io.pipe(0).bits.rvd_data - - val mul_in1 = in_vs1 - val mul_in2 = Mux(ctrl.bool(MULSwapVdV2), in_vd, in_vs2) - - val multipliers = Seq.fill(dLenB >> 3)(Module(new MultiplyBlock)) - for (i <- 0 until (dLenB >> 3)) { - multipliers(i).io.in1_signed := ctrl.bool(MULSign1) - multipliers(i).io.in2_signed := ctrl.bool(MULSign2) - multipliers(i).io.eew := io.pipe(0).bits.rvs1_eew - multipliers(i).io.in1 := mul_in1.asTypeOf(Vec(dLenB >> 3, UInt(64.W)))(i) - multipliers(i).io.in2 := mul_in2.asTypeOf(Vec(dLenB >> 3, UInt(64.W)))(i) - } - val mul_out_comb = VecInit(multipliers.map(_.io.out_data)).asUInt - - //////////////////////////////////////////////////////////////////////////////////////////// - // Pipeline Stages Before Adder Array - //////////////////////////////////////////////////////////////////////////////////////////// - val mul_out = Pipe(io.pipe(0).valid, mul_out_comb, depth-2).bits - - val in_eew_pipe = io.pipe(depth-2).bits.rvs1_eew - val out_eew_pipe = io.pipe(depth-2).bits.vd_eew - val ctrl_wmul = out_eew_pipe > in_eew_pipe - val ctrl_smul = io.pipe(depth-2).bits.isOpi - val ctrl_MULSub = Pipe(io.pipe(0).valid, ctrl.bool(MULSub), depth-2).bits - val ctrl_MULSwapVdV2 = Pipe(io.pipe(0).valid, ctrl.bool(MULSwapVdV2), depth-2).bits - val ctrl_MULAccumulate = Pipe(io.pipe(0).valid, ctrl.bool(MULAccumulate), depth-2).bits - val ctrl_MULHi = Pipe(io.pipe(0).valid, ctrl.bool(MULHi), depth-2).bits - val in_vs2_pipe = io.pipe(depth-2).bits.rvs2_data - val in_vd_pipe = io.pipe(depth-2).bits.rvd_data - //////////////////////////////////////////////////////////////////////////////////////////// - - val hi = VecInit.tabulate(4)({sew => - VecInit(mul_out.asTypeOf(Vec((2*dLenB) >> sew, UInt((8 << sew).W))).grouped(2).map(_.last).toSeq).asUInt - })(in_eew_pipe) - val lo = VecInit.tabulate(4)({sew => - VecInit(mul_out.asTypeOf(Vec((2*dLenB) >> sew, UInt((8 << sew).W))).grouped(2).map(_.head).toSeq).asUInt - })(in_eew_pipe) - val half_sel = (io.pipe(depth-2).bits.eidx >> (dLenOffBits.U - out_eew_pipe))(0) - val wide = Mux(half_sel, mul_out >> dLen, mul_out)(dLen-1,0) - - val (smul_clipped, smul_sat) = { - val smul_arr = Module(new VectorSMul) - smul_arr.io.mul_in := mul_out - smul_arr.io.eew := out_eew_pipe - smul_arr.io.vxrm := io.pipe(depth-2).bits.vxrm - (smul_arr.io.clipped, smul_arr.io.sat) - } - - val adder_arr = Module(new AdderArray(dLenB)) - adder_arr.io.in1 := Mux(ctrl_wmul, wide, lo).asTypeOf(Vec(dLenB, UInt(8.W))) - adder_arr.io.in2 := Mux(ctrl_MULAccumulate, Mux(ctrl_MULSwapVdV2, in_vs2_pipe, in_vd_pipe), 0.U(dLen.W)).asTypeOf(Vec(dLenB, UInt(8.W))) - adder_arr.io.incr := VecInit.fill(dLenB)(false.B) - adder_arr.io.mask_carry := 0.U - adder_arr.io.signed := DontCare - adder_arr.io.eew := out_eew_pipe - adder_arr.io.avg := false.B - adder_arr.io.rm := DontCare - adder_arr.io.sub := ctrl_MULSub - adder_arr.io.cmask := false.B - - val add_out = adder_arr.io.out - - val out = Mux(ctrl_smul, smul_clipped, 0.U) | Mux(ctrl_MULHi, hi, 0.U) | Mux(!ctrl_smul && !ctrl_MULHi, add_out.asUInt, 0.U) - val pipe_out = Pipe(io.pipe(depth-2).valid, out, 1).bits - - val vxsat = Mux(ctrl_smul, smul_sat, 0.U) & io.pipe(depth-2).bits.wmask - val pipe_vxsat = Pipe(io.pipe(depth-2).valid, vxsat, 1).bits - - io.pipe0_stall := false.B - io.write.valid := io.pipe(depth-1).valid - io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg - io.write.bits.data := pipe_out - io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) - - io.set_vxsat := io.pipe(depth-1).valid && (pipe_vxsat =/= 0.U) - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare -} - -class MultiplyBlock extends Module { - val xLen = 64 - - val io = IO(new Bundle { - val in1_signed = Input(Bool()) - val in2_signed = Input(Bool()) - val eew = Input(UInt(2.W)) - - val in1 = Input(UInt(xLen.W)) - val in2 = Input(UInt(xLen.W)) - - val out_data = Output(UInt((2*xLen).W)) - }) - - val mul64 = Module(new Multiplier(64)) - mul64.io.in1_signed := io.in1_signed - mul64.io.in2_signed := io.in2_signed - mul64.io.in1 := io.in1 - mul64.io.in2 := io.in2 - - val mul32 = Module(new Multiplier(32)) - mul32.io.in1_signed := io.in1_signed - mul32.io.in2_signed := io.in2_signed - mul32.io.in1 := io.in1(63,32) - mul32.io.in2 := io.in2(63,32) - - val mul16 = Seq.tabulate(2) { i => - val indh = 32*(i+1) - 1 - val indl = 32*i + 16 - val in1 = io.in1(indh, indl) - val in2 = io.in2(indh, indl) - val mul = Module(new Multiplier(16)) - mul.io.in1_signed := io.in1_signed - mul.io.in2_signed := io.in2_signed - mul.io.in1 := in1 - mul.io.in2 := in2 - mul - } - val mul8 = Seq.tabulate(4) { i => - val indh = 16*(i+1) - 1 - val indl = 16*i + 8 - val in1 = io.in1(indh, indl) - val in2 = io.in2(indh, indl) - val mul = Module(new Multiplier(8)) - mul.io.in1_signed := io.in1_signed - mul.io.in2_signed := io.in2_signed - mul.io.in1 := in1 - mul.io.in2 := in2 - mul - } - when (io.eew === 0.U) { - mul16(1).io.in1 := Cat(Fill(8, io.in1_signed && io.in1(55)), io.in1(55, 48)) - mul16(1).io.in2 := Cat(Fill(8, io.in2_signed && io.in2(55)), io.in2(55, 48)) - mul32.io.in1 := Cat(Fill(8, io.in1_signed && io.in1(39)), io.in1(39, 32)) - mul32.io.in2 := Cat(Fill(8, io.in2_signed && io.in2(39)), io.in2(39, 32)) - mul16(0).io.in1 := Cat(Fill(8, io.in1_signed && io.in1(23)), io.in1(23, 16)) - mul16(0).io.in2 := Cat(Fill(8, io.in2_signed && io.in2(23)), io.in2(23, 16)) - mul64.io.in1 := Cat(Fill(8, io.in1_signed && io.in1(7)), io.in1(7,0)) - mul64.io.in2 := Cat(Fill(8, io.in2_signed && io.in2(7)), io.in2(7,0)) - - io.out_data := Cat(mul8(3).io.out_data, - mul16(1).io.out_data(15,0), - mul8(2).io.out_data, - mul32.io.out_data(15,0), - mul8(1).io.out_data, - mul16(0).io.out_data(15,0), - mul8(0).io.out_data, - mul64.io.out_data(15,0)) - } - .elsewhen (io.eew === 1.U) { - mul32.io.in1 := Cat(Fill(16, io.in1_signed && io.in1(47)), io.in1(47, 32)) - mul32.io.in2 := Cat(Fill(16, io.in2_signed && io.in2(47)), io.in2(47, 32)) - mul64.io.in1 := Cat(Fill(16, io.in1_signed && io.in1(15)), io.in1(15,0)) - mul64.io.in2 := Cat(Fill(16, io.in2_signed && io.in2(15)), io.in2(15,0)) - - io.out_data := Cat(mul16(1).io.out_data, - mul32.io.out_data(31,0), - mul16(0).io.out_data, - mul64.io.out_data(31,0)) - } - .elsewhen (io.eew === 2.U) { - mul64.io.in1 := Cat(Fill(32, io.in1_signed && io.in1(31)), io.in1(31,0)) - mul64.io.in2 := Cat(Fill(32, io.in2_signed && io.in2(31)), io.in2(31,0)) - - io.out_data := Cat(mul32.io.out_data, - mul64.io.out_data(63,0)) - } - .otherwise { - io.out_data := mul64.io.out_data - } -} - -class Multiplier(width: Int) extends Module { - val io = IO(new Bundle { - val in1_signed = Input(Bool()) - val in2_signed = Input(Bool()) - - val in1 = Input(UInt(width.W)) - val in2 = Input(UInt(width.W)) - - val out_data = Output(UInt((2*width).W)) - }) - - val lhs = Cat(io.in1_signed && io.in1(width-1), io.in1).asSInt - val rhs = Cat(io.in2_signed && io.in2(width-1), io.in2).asSInt - - val prod = lhs * rhs - - io.out_data := prod(2*width-1,0) -} - -class VectorSMul(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val eew = Input(UInt(2.W)) - val vxrm = Input(UInt(2.W)) - val mul_in = Input(UInt((2*dLen).W)) - - val clipped = Output(UInt((dLen).W)) - val sat = Output(UInt(dLenB.W)) - }) - val sat_sew = Wire(Vec(4, UInt(dLenB.W))) - val clipped_sew = Wire(Vec(4, UInt(dLen.W))) - for (sew <- 0 until 4) { - val wideProds = io.mul_in.asTypeOf(Vec(dLenB >> sew, SInt((16 << sew).W))) - val smul = wideProds.map { wideElem => - val rounding_incr = RoundingIncrement(io.vxrm, wideElem((8 << sew)-1, 0)) - (wideElem >> ((8 << sew) - 1)) + Cat(0.U(1.W), rounding_incr).asSInt - } - val clip_neg = (-1 << ((8 << sew)-1)).S - val clip_pos = ((1 << ((8 << sew)-1)) - 1).S - val clip_hi = smul.map{ _ > clip_pos } - val clip_lo = smul.map{ _ < clip_neg } - - clipped_sew(sew) := smul.zipWithIndex.map { case (sm, i) => - val long = Mux(clip_hi(i), clip_pos, 0.S) | Mux(clip_lo(i), clip_neg, 0.S) | Mux(!clip_hi(i) && !clip_lo(i), sm, 0.S) - long((8 << sew)-1, 0) - }.asUInt - val sat_vec_sew = smul.zipWithIndex.map { case (sm, i) => - clip_hi(i) || clip_lo(i) - } - sat_sew(sew) := FillInterleaved((1 << sew), sat_vec_sew) - } - - io.clipped := clipped_sew(io.eew) - io.sat := sat_sew(io.eew) -} diff --git a/arch/src/main/scala/framework/gendomain/exu/int/ShiftPipe.scala b/arch/src/main/scala/framework/gendomain/exu/int/ShiftPipe.scala deleted file mode 100644 index 251e2d9b..00000000 --- a/arch/src/main/scala/framework/gendomain/exu/int/ShiftPipe.scala +++ /dev/null @@ -1,240 +0,0 @@ -package framework.gendomain.exu - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class ShiftBlock(w: Int) extends Module { - val io = IO(new Bundle { - val in = Input(UInt(w.W)) - val shamt = Input(UInt((1+log2Ceil(w)).W)) - val shl = Input(Bool()) - val sign = Input(Bool()) - val rm = Input(UInt(2.W)) - val out = Output(UInt(w.W)) - val round = Output(Bool()) - }) - val full_shifted = (Mux(io.shl, - Cat(false.B, Reverse(io.in), false.B), - Cat(io.sign, io.in, false.B)).asSInt >> io.shamt)(w,0).asUInt - - val shifted = full_shifted(w,1) - - io.out := Mux(io.shl, Reverse(shifted), shifted) - io.round := RoundingIncrement(io.rm, shifted(0), full_shifted(0), - Some(io.in & (((1.U << io.shamt) - 1.U) >> 1)(w-1,0))) -} - -class ShiftUnit extends Module { - val io = IO(new Bundle { - val in_eew = Input(UInt(2.W)) - val in = Input(UInt(64.W)) - val shamt = Input(UInt(64.W)) - val rot = Input(Bool()) - val shl = Input(Bool()) - val signed = Input(Bool()) - val rm = Input(UInt(2.W)) - - val out = Output(UInt(64.W)) - val round = Output(UInt(8.W)) - }) - - val shamt_mask = VecInit.tabulate(4)({eew => ~(0.U((log2Ceil(8) + eew).W))})(io.in_eew) - - val shift_out = Seq.tabulate(4) { sew => Wire(Vec(8 >> sew, UInt((8 << sew).W))) } - val round_out = Seq.tabulate(4) { sew => Wire(Vec(8 >> sew, UInt((1 << sew).W))) } - - def sextElem(in: UInt, sew: Int, sext: Bool): UInt = Cat(Fill(65 - (8 << sew), sext && in((8 << sew)-1)), in((8 << sew)-1,0))(63,0) - - for (i <- 0 until 8) { - val sews = (0 until 4).filter { sew => i < (8 >> sew) } - val shifter = Module(new ShiftBlock(8 << (sews.max))) - val rotator = Module(new ShiftBlock(8 << (sews.max))) - shifter.io.in := Mux1H(sews - .map { sew => (io.in_eew === sew.U, sextElem(io.in((i+1)*(8< (io.in_eew === sew.U, io.in((i+1)*(8< (io.in_eew === sew.U, io.shamt((i+1)*(8< (io.in_eew === sew.U, io.in((i+1)*(8< - shift_out(sew)(i) := shifter.io.out | Mux(io.rot, rotator.io.out, 0.U) - round_out(sew)(i) := shifter.io.round - } - } - io.out := Mux1H(UIntToOH(io.in_eew), shift_out.map(_.asUInt)) - io.round := Mux1H(UIntToOH(io.in_eew), round_out.map(_.asUInt)) -} - -class ShiftArray(dLenB: Int) extends Module { - val dLen = dLenB * 8 - val io = IO(new Bundle { - val in_eew = Input(UInt(2.W)) - val in = Input(UInt(dLen.W)) - val shamt = Input(UInt(dLen.W)) - val rori_hi = Input(Bool()) - val rot = Input(Bool()) - val shl = Input(Bool()) - val signed = Input(Bool()) - val scaling = Input(Bool()) - val rm = Input(UInt(2.W)) - val narrowing = Input(Bool()) - - val out = Output(Vec(dLenB, UInt(8.W))) - val set_vxsat = Output(UInt(dLenB.W)) - }) - - val shifted = Reg(Vec(dLenB, UInt(8.W))) - val rounding_incrs = Reg(Vec(dLenB, Bool())) - val in_eew_pipe = RegNext(io.in_eew) - val signed_pipe = RegNext(io.signed) - val scaling_pipe = RegNext(io.scaling) - val narrowing_pipe = RegNext(io.narrowing) - - for (i <- 0 until (dLenB >> 3)) { - val shifter = Module(new ShiftUnit) - shifter.io.in_eew := io.in_eew - shifter.io.in := io.in((i+1)*64-1,i*64) - shifter.io.shamt := io.shamt((i+1)*64-1,i*64) | Mux(io.rori_hi, 0x20.U, 0.U) - shifter.io.rot := io.rot - shifter.io.shl := io.shl - shifter.io.signed := io.signed - shifter.io.rm := io.rm - for (j <- 0 until 8) { - shifted(i*8+j) := shifter.io.out((j+1)*8-1,j*8) - rounding_incrs(i*8+j) := shifter.io.round(j) - } - } - - val scaling_array = Module(new AdderArray(dLenB)) - scaling_array.io.in1 := shifted - scaling_array.io.in2.foreach(_ := 0.U) - scaling_array.io.incr := Mux(scaling_pipe, rounding_incrs, VecInit.fill(dLenB)(false.B)) - scaling_array.io.signed := DontCare - scaling_array.io.eew := in_eew_pipe - scaling_array.io.avg := false.B - scaling_array.io.rm := DontCare - scaling_array.io.sub := false.B - scaling_array.io.cmask := false.B - scaling_array.io.mask_carry := DontCare - - val narrow_out_elems: Seq[Seq[UInt]] = Seq.tabulate(3)({eew => - scaling_array.io.out.grouped(2 << eew).map(e => VecInit(e.take(1 << eew)).asUInt).toSeq - }) - val narrow_out_his: Seq[Seq[UInt]] = Seq.tabulate(3)({eew => - scaling_array.io.out.grouped(2 << eew).map(e => VecInit(e.drop(1 << eew)).asUInt).toSeq - }) - val narrow_out_carries = Seq.tabulate(3)({eew => - scaling_array.io.carry.grouped(2 << eew).map(_.last).toSeq - }) - - val narrow_unsigned_mask = VecInit.tabulate(3)({ eew => - FillInterleaved(1 << eew, VecInit.tabulate(dLenB >> (eew + 1))(i => - Cat(narrow_out_carries(eew)(i), narrow_out_his(eew)(i)) =/= 0.U - ).asUInt) - })(in_eew_pipe - 1.U) - val narrow_unsigned_clip = (~(0.U((dLen >> 1).W))).asTypeOf(Vec(dLenB >> 1, UInt(8.W))) - - val (narrow_signed_masks, narrow_signed_clips): (Seq[UInt], Seq[UInt]) = Seq.tabulate(3)({ eew => - val signs = narrow_out_his(eew).map(_((8 << eew)-1)) - val his = narrow_out_his(eew).zip(narrow_out_elems(eew)).map({ case (h,e) => Cat(h((8 << eew)-2,0), e((8< s && h =/= ~0.U((8 << eew).W) }) - val clip_hi = signs.zip(his).map({ case (s,h) => !s && h =/= 0.U((8 << eew).W) }) - val clip_neg = Cat(1.U, 0.U(((8 << eew)-1).W)) - val clip_pos = ~clip_neg - val clip_value = VecInit(signs.map(s => Mux(s, clip_neg, clip_pos))).asUInt - val clip = clip_lo.zip(clip_hi).map(t => t._1 || t._2) - (FillInterleaved((1 << eew), clip), clip_value) - }).unzip - val narrow_signed_mask = VecInit(narrow_signed_masks)(in_eew_pipe - 1.U) - val narrow_signed_clip = VecInit(narrow_signed_clips)(in_eew_pipe - 1.U).asTypeOf(Vec(dLenB >> 1, UInt(8.W))) - - val narrow_mask = Mux(signed_pipe, narrow_signed_mask, narrow_unsigned_mask) - val narrow_clip = Mux(signed_pipe, narrow_signed_clip, narrow_unsigned_clip) - - val narrow_out_clipped = VecInit(narrow_out_elems.map(e => VecInit(e).asUInt))(in_eew_pipe - 1.U) - .asTypeOf(Vec(dLenB >> 1, UInt(8.W))) - .zip(narrow_mask.asBools) - .zip(narrow_clip).map ({ case ((o,s),c) => Mux(s && scaling_pipe, c, o) }) - val narrow_out = Fill(2, narrow_out_clipped.asUInt).asTypeOf(Vec(dLenB, UInt(8.W))) - - io.out := Mux(narrowing_pipe, narrow_out, scaling_array.io.out) - io.set_vxsat := Mux(narrowing_pipe && scaling_pipe, Fill(2, narrow_mask), 0.U) -} - -case object ShiftPipeFactory extends FunctionalUnitFactory { - def insns = Seq( - SLL.VV, SLL.VX, SLL.VI, SRL.VV, SRL.VX, SRL.VI, SRA.VV, SRA.VX, SRA.VI, - NSRA.VV, NSRA.VX, NSRA.VI, NSRL.VV, NSRL.VX, NSRL.VI, - NCLIPU.VV, NCLIPU.VX, NCLIPU.VI, NCLIP.VV, NCLIP.VX, NCLIP.VI, - SSRL.VV, SSRL.VX, SSRL.VI, SSRA.VV, SSRA.VX, SSRA.VI, - // Zvbb - ROL.VV, ROL.VX, ROR.VV, ROR.VX, ROR.VI, RORI.VI, WSLL.VV, WSLL.VX, WSLL.VI - ) - def generate(implicit p: Parameters) = new ShiftPipe()(p) -} - -class ShiftPipe(implicit p: Parameters) extends PipelinedFunctionalUnit(2)(p) { - val supported_insns = ShiftPipeFactory.insns - - val rvs1_eew = io.pipe(0).bits.rvs1_eew - val rvs2_eew = io.pipe(0).bits.rvs2_eew - val vd_eew = io.pipe(0).bits.vd_eew - - val ctrl = new VectorDecoder( - io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, - supported_insns, - Seq(UsesShift, ShiftsLeft, ScalingShift)) - - io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched - - val shift_narrowing = vd_eew < rvs2_eew - val shift_widening = vd_eew > rvs2_eew - - val rvs1_bytes = io.pipe(0).bits.rvs1_data.asTypeOf(Vec(dLenB, UInt(8.W))) - val rvs2_bytes = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(dLenB, UInt(8.W))) - val narrow_vs1 = narrow2_expand(rvs1_bytes, rvs1_eew, - (io.pipe(0).bits.eidx >> (dLenOffBits.U - Mux(shift_narrowing, rvs2_eew, vd_eew)))(0), false.B) - val narrow_vs2 = narrow2_expand(rvs2_bytes, rvs2_eew, - (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), false.B) - - val shift_arr = Module(new ShiftArray(dLenB)) - shift_arr.io.in_eew := Mux(shift_widening, vd_eew, rvs2_eew) - shift_arr.io.in := Mux(shift_widening, narrow_vs2, rvs2_bytes).asUInt - shift_arr.io.shamt := Mux(shift_narrowing || shift_widening, narrow_vs1, rvs1_bytes).asUInt - shift_arr.io.rori_hi := io.pipe(0).bits.opif6 === OPIFunct6.rol && io.pipe(0).bits.funct3 === OPIVI - shift_arr.io.rot := io.pipe(0).bits.opif6.isOneOf(OPIFunct6.rol, OPIFunct6.ror) - shift_arr.io.shl := ctrl.bool(ShiftsLeft) - shift_arr.io.signed := io.pipe(0).bits.funct6(0) - shift_arr.io.rm := io.pipe(0).bits.vxrm - shift_arr.io.scaling := ctrl.bool(ScalingShift) - shift_arr.io.narrowing := shift_narrowing - - io.pipe0_stall := false.B - io.write.valid := io.pipe(depth-1).valid - io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg - io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask) - io.write.bits.data := shift_arr.io.out.asUInt - - val shift_vxsat = shift_arr.io.set_vxsat & io.pipe(depth-1).bits.wmask - io.set_vxsat := io.pipe(depth-1).valid && (shift_vxsat =/= 0.U) - io.set_fflags.valid := false.B - io.set_fflags.bits := DontCare - - io.scalar_write.valid := false.B - io.scalar_write.bits := DontCare -} diff --git a/arch/src/main/scala/framework/gendomain/frontend/Dispatch.scala b/arch/src/main/scala/framework/gendomain/frontend/Dispatch.scala deleted file mode 100644 index c249f8fd..00000000 --- a/arch/src/main/scala/framework/gendomain/frontend/Dispatch.scala +++ /dev/null @@ -1,129 +0,0 @@ -package framework.gendomain.frontend - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.dataview._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ - -import framework.gendomain.common._ -import framework.gendomain.insns._ - -class VectorDispatcher(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val issue = Flipped(Decoupled(new VectorIssueInst)) - - val mem = Decoupled(new VectorMemMacroOp) - val dis = Decoupled(new VectorIssueInst) - - val scalar_resp = Decoupled(new ScalarWrite) - - val vat_release = Input(Vec(nRelease, Valid(UInt(vParams.vatSz.W)))) - val vat_head = Output(UInt(vParams.vatSz.W)) - val vat_tail = Output(UInt(vParams.vatSz.W)) - }) - - val debug_id_ctr = RegInit(0.U(debugIdSz.W)) - val vat_valids = RegInit(VecInit.fill(1 << vParams.vatSz)(false.B)) - val vat_tail = RegInit(0.U(vParams.vatSz.W)) - val vat_head = RegInit(0.U(vParams.vatSz.W)) - def vatOlder(i0: UInt, i1: UInt) = cqOlder(i0, i1, vat_tail) - val vat_available = !vat_valids(vat_tail) - val vat_available_count = PopCount(~vat_valids.asUInt) - val vat_head_incr = WireInit(false.B) - - when (vat_head_incr) { - vat_head := vat_head + 1.U - } - - when (io.dis.fire) { - assert(!vat_valids(vat_tail)) - vat_valids(vat_tail) := true.B - vat_tail := vat_tail + 1.U - debug_id_ctr := debug_id_ctr + 1.U - } - - when (vat_tail =/= vat_head && !vat_valids(vat_head)) { - vat_head_incr := true.B - } - - val issue_inst = WireInit(io.issue.bits) - issue_inst.vat := vat_tail - issue_inst.debug_id := debug_id_ctr - - val hwacha_limiter = vParams.hwachaLimiter.map(n => Module(new HwachaLimiter(n))) - hwacha_limiter.foreach { h => - h.io.inst := issue_inst - h.io.fire := io.issue.fire - h.io.vat_release.foreach(_ := false.B) - } - val hwacha_block = hwacha_limiter.map(_.io.block).getOrElse(false.B) - - - io.issue.ready := vat_available && io.dis.ready && (!issue_inst.vmu || io.mem.ready) && !hwacha_block - io.dis.valid := vat_available && io.issue.valid && (!issue_inst.vmu || io.mem.ready) && !hwacha_block - io.mem.valid := vat_available && io.issue.valid && io.dis.ready && issue_inst.vmu && !hwacha_block - - io.vat_tail := vat_tail - io.vat_head := vat_head - - when ((io.issue.bits.funct3 === OPMVV && io.issue.bits.opmf6 === OPMFunct6.wrxunary0 && io.issue.bits.rs1 === 0.U) || - (io.issue.bits.funct3 === OPFVV && io.issue.bits.opff6 === OPFFunct6.wrfunary0 && io.issue.bits.rs1 === 0.U)) { - issue_inst.vconfig.vl := 1.U - issue_inst.vstart := 0.U - } - - // Strided with stride = 1 << eew is just unit-strided - when (io.issue.bits.mop === mopStrided && io.issue.bits.rs2_data === ((io.issue.bits.nf +& 1.U) << io.issue.bits.mem_elem_size)) { - issue_inst.mop := mopUnit - } - - io.scalar_resp.valid := false.B - io.scalar_resp.bits.fp := false.B - io.scalar_resp.bits.rd := io.issue.bits.rd - io.scalar_resp.bits.size := 3.U - io.scalar_resp.bits.data := Mux(io.issue.bits.rs1(0), - ~(0.U(xLen.W)), // vfirst - 0.U // vpopc - ) - - when (issue_inst.vconfig.vl <= issue_inst.vstart && !(issue_inst.funct3 === OPIVI && issue_inst.opif6 === OPIFunct6.mvnrr)) { - io.issue.ready := true.B - io.mem.valid := false.B - io.dis.valid := false.B - when (io.issue.bits.funct3 === OPMVV && io.issue.bits.opmf6 === OPMFunct6.wrxunary0) { - io.issue.ready := io.scalar_resp.ready - io.scalar_resp.valid := io.issue.valid - } - } - - io.dis.bits := issue_inst - - io.mem.bits.base_offset := issue_inst.rs1_data - io.mem.bits.stride := issue_inst.rs2_data - io.mem.bits.page := issue_inst.page - io.mem.bits.vstart := issue_inst.vstart - io.mem.bits.segstart := issue_inst.segstart - io.mem.bits.segend := issue_inst.segend - io.mem.bits.vl := issue_inst.vconfig.vl - io.mem.bits.mop := issue_inst.mop - io.mem.bits.vm := issue_inst.vm - io.mem.bits.nf := issue_inst.nf - io.mem.bits.idx_size := issue_inst.mem_idx_size - io.mem.bits.elem_size := issue_inst.mem_elem_size - io.mem.bits.whole_reg := issue_inst.umop === lumopWhole && issue_inst.orig_mop === mopUnit - io.mem.bits.store := issue_inst.bits(5) - io.mem.bits.fast_sg := issue_inst.fast_sg - io.mem.bits.debug_id := issue_inst.debug_id - - - for (r <- io.vat_release) { - when (r.valid) { - assert(vat_valids(r.bits)) - when (r.bits === vat_head) { vat_head_incr := true.B } - vat_valids(r.bits) := false.B - hwacha_limiter.foreach(_.io.vat_release(r.bits) := true.B) - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/frontend/EarlyDecode.scala b/arch/src/main/scala/framework/gendomain/frontend/EarlyDecode.scala deleted file mode 100644 index be92da6c..00000000 --- a/arch/src/main/scala/framework/gendomain/frontend/EarlyDecode.scala +++ /dev/null @@ -1,56 +0,0 @@ -package framework.gendomain.frontend - -import chisel3._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import framework.gendomain.common._ -import framework.gendomain.insns.{VectorInstruction, VectorDecoder} - -class EarlyVectorDecode(supported_ex_insns: Seq[VectorInstruction])(implicit p: Parameters) extends RocketVectorDecoder()(p) with HasVectorConsts { - - io.legal := false.B - io.fp := false.B - io.read_rs1 := false.B - io.read_rs2 := false.B - io.read_frs1 := false.B - io.write_rd := false.B - io.write_frd := false.B - - val opcode = io.inst(6,0) - - val width = io.inst(14,12) - val lumop = io.inst(24,20) - val sumop = lumop - val vm = io.inst(25) - val mop = io.inst(27,26) - val mew = io.inst(28) - val nf = io.inst(31,29) - val funct3 = io.inst(14,12) - val funct6 = io.inst(31,26) - val rs1 = io.inst(19,15) - val rs2 = io.inst(24,20) - - val v_load = opcode === opcLoad - val v_store = opcode === opcStore - val v_arith = opcode === opcVector && funct3 =/= 7.U && new VectorDecoder(funct3, funct6, rs1, rs2, supported_ex_insns, Nil).matched - - when (v_load || v_store) { - io.legal := mew === 0.U && width.isOneOf(0.U, 5.U, 6.U, 7.U) - val unit = mop === 0.U - when (unit) { - when (v_load && !lumop.isOneOf(lumopUnit, lumopWhole, lumopMask, lumopFF)) { io.legal := false.B } - when (v_store && !sumop.isOneOf(sumopUnit, sumopWhole, sumopMask)) { io.legal := false.B } - } - when (mew === 1.U) { io.legal := false.B } - io.read_rs1 := true.B - io.read_rs2 := mop === mopStrided - } .elsewhen (v_arith) { - io.legal := true.B - io.read_rs1 := funct3.isOneOf(OPIVX, OPMVX) - io.read_frs1 := funct3 === OPFVF - io.write_rd := funct3 === OPMVV && OPMFunct6(funct6) === OPMFunct6.wrxunary0 - io.write_frd := funct3 === OPFVV && OPFFunct6(funct6) === OPFFunct6.wrfunary0 - io.fp := funct3 === OPFVF - } -} diff --git a/arch/src/main/scala/framework/gendomain/frontend/EarlyTrapCheck.scala b/arch/src/main/scala/framework/gendomain/frontend/EarlyTrapCheck.scala deleted file mode 100644 index eef168f5..00000000 --- a/arch/src/main/scala/framework/gendomain/frontend/EarlyTrapCheck.scala +++ /dev/null @@ -1,235 +0,0 @@ -package framework.gendomain.frontend - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ -import framework.gendomain.backend.{VectorBackend} - -class EarlyTrapCheck(edge: TLEdge, sgSize: Option[BigInt])(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - - val unified_addresses = AddressSet.unify(edge.manager.managers.map(_.address).flatten) - require(unified_addresses.forall(_.alignment >= (1 << pgIdxBits)), - "Memory devices on this system must be at least page-aligned") - - val io = IO(new Bundle { - val sg_base = Input(UInt(coreMaxAddrBits.W)) - - val busy = Output(Bool()) - val s0 = new Bundle { - val in = Input(Valid(new Bundle { - val inst = UInt(32.W) - val pc = UInt(vaddrBitsExtended.W) - val status = new MStatus - val vconfig = new VConfig - val vstart = UInt(log2Ceil(maxVLMax).W) - val rs1 = UInt(xLen.W) - val rs2 = UInt(xLen.W) - val phys = Bool() - })) - val tlb_req = Valid(new TLBReq(3)) - } - - val s1 = new Bundle { - val inst = Output(new VectorIssueInst) - val rs1 = Input(Valid(UInt(xLen.W))) - val kill = Input(Bool()) - val tlb_req = Valid(new TLBReq(3)) - val tlb_resp = Input(new TLBResp) - } - - val s2 = new Bundle { - val scalar_store_pending = Input(Bool()) - val inst = Valid(new VectorIssueInst) - val replay = Output(Bool()) - val vstart = Valid(UInt(log2Ceil(maxVLMax).W)) - val retire = Output(Bool()) - val xcpt = Valid(new Bundle { - val cause = UInt(xLen.W) - val tval = UInt(coreMaxAddrBits.W) - }) - val pc = Output(UInt(vaddrBitsExtended.W)) - val internal_replay = Valid(new VectorIssueInst) - val issue = Decoupled(new VectorIssueInst) - val vxrm = Input(UInt(2.W)) - val frm = Input(UInt(3.W)) - } - }) - - val s1_valid = RegInit(false.B) - val s2_valid = RegInit(false.B) - io.busy := s1_valid || s2_valid - - val s0_inst = Wire(new VectorIssueInst) - s0_inst.pc := io.s0.in.bits.pc - s0_inst.bits := io.s0.in.bits.inst - s0_inst.vconfig := io.s0.in.bits.vconfig - s0_inst.vstart := Mux(s1_valid || s2_valid, 0.U, io.s0.in.bits.vstart) - s0_inst.segstart := 0.U - s0_inst.segend := s0_inst.seg_nf - s0_inst.rs1_data := io.s0.in.bits.rs1 - s0_inst.rs2_data := io.s0.in.bits.rs2 - s0_inst.emul := Mux(io.s0.in.bits.vconfig.vtype.vlmul_sign, 0.U, io.s0.in.bits.vconfig.vtype.vlmul_mag) - s0_inst.page := DontCare - s0_inst.vat := DontCare - s0_inst.debug_id := DontCare - s0_inst.rm := DontCare - s0_inst.fast_sg := false.B - s0_inst.mop := s0_inst.orig_mop - when (s0_inst.vmu && s0_inst.mop === mopUnit) { - val mask_vl = (io.s0.in.bits.vconfig.vl >> 3) + Mux(io.s0.in.bits.vconfig.vl(2,0) === 0.U, 0.U, 1.U) - val whole_vl = (vLen.U >> (s0_inst.mem_elem_size +& 3.U)) * (s0_inst.nf +& 1.U) - s0_inst.vconfig.vl := MuxLookup(s0_inst.umop, io.s0.in.bits.vconfig.vl)(Seq( - (lumopWhole -> whole_vl), (lumopMask -> mask_vl) - )) - when (s0_inst.umop === lumopWhole) { - s0_inst.emul := VecInit.tabulate(8)(nf => log2Ceil(nf+1).U)(s0_inst.nf) - } - } - when (!s0_inst.vmu && s0_inst.funct3 === OPIVI && s0_inst.funct6 === OPIFunct6.mvnrr.litValue.U) { - s0_inst.emul := log2_up(s0_inst.imm5, 8) - } - - val s0_unit = s0_inst.mop === mopUnit || (s0_inst.mop === mopStrided && io.s0.in.bits.rs2 === ((s0_inst.nf +& 1.U) << s0_inst.mem_elem_size)) - val s0_indexed = s0_inst.mop.isOneOf(mopOrdered, mopUnordered) - val s0_base = io.s0.in.bits.rs1 + (((s0_inst.seg_nf +& 1.U) * s0_inst.vstart ) << s0_inst.mem_elem_size) - val s0_bound = io.s0.in.bits.rs1 + (((s0_inst.seg_nf +& 1.U) * s0_inst.vconfig.vl) << s0_inst.mem_elem_size) - 1.U - val s0_single_page = (s0_base >> pgIdxBits) === (s0_bound >> pgIdxBits) - val s0_replay_next_page = s0_inst.vmu && s0_unit && s0_inst.nf === 0.U && !s0_single_page - val s0_iterative = (!s0_single_page || !s0_unit || s0_inst.umop === lumopFF) && !s0_replay_next_page - val s0_fast_sg = s0_iterative && io.s0.in.bits.phys && s0_inst.mop === mopUnordered && s0_inst.seg_nf === 0.U && sgSize.map { size => - s0_base >= io.sg_base && s0_base < (io.sg_base + size.U) - }.getOrElse(false.B) - - val s0_tlb_valid = !s0_iterative && s0_inst.vmu && s0_inst.vstart < s0_inst.vconfig.vl - - io.s0.tlb_req.valid := s0_tlb_valid && io.s0.in.valid - io.s0.tlb_req.bits.vaddr := s0_base - io.s0.tlb_req.bits.passthrough := false.B - io.s0.tlb_req.bits.size := s0_inst.mem_elem_size - io.s0.tlb_req.bits.cmd := Mux(s0_inst.opcode(5), M_XWR, M_XRD) - io.s0.tlb_req.bits.prv := io.s0.in.bits.status.prv - io.s0.tlb_req.bits.v := io.s0.in.bits.status.v - - // s1_stage - s1_valid := io.s0.in.fire - val s1_inst = RegEnable(s0_inst , io.s0.in.valid) - val s1_iterative = RegEnable(s0_iterative , io.s0.in.valid) - val s1_replay_next_page = RegEnable(s0_replay_next_page, io.s0.in.valid) - val s1_base = RegEnable(s0_base , io.s0.in.valid) - val s1_tlb_valid = RegEnable(s0_tlb_valid , io.s0.in.valid) - val s1_fast_sg = RegEnable(s0_fast_sg , io.s0.in.valid) - val s1_tlb_resp = WireInit(io.s1.tlb_resp) - - when (!s1_tlb_valid) { - s1_tlb_resp := 0.U.asTypeOf(new TLBResp) - when (s1_fast_sg) { - s1_tlb_resp.paddr := s1_base - } - } - - io.s1.inst := s1_inst - io.s1.tlb_req.valid := RegNext(io.s0.tlb_req.valid, false.B) - io.s1.tlb_req.bits := RegEnable(io.s0.tlb_req.bits, s0_tlb_valid) - - // s2 stage - s2_valid := s1_valid && !io.s1.kill - val s2_inst = Reg(new VectorIssueInst) - val s2_base = RegEnable(s1_base, s1_valid) - val s2_iterative = RegEnable(s1_iterative , s1_valid) - val s2_fast_sg = RegEnable(s1_fast_sg , s1_valid) - val s2_replay_next_page = RegEnable(s1_replay_next_page, s1_valid) - when (s1_valid) { - s2_inst := s1_inst - when (io.s1.rs1.valid) { s2_inst.rs1_data := io.s1.rs1.bits } - } - val s2_tlb_resp = RegEnable(s1_tlb_resp, s1_valid) - - val s2_xcpts = Seq( - (s2_tlb_resp.pf.st, Causes.store_page_fault.U), - (s2_tlb_resp.pf.ld, Causes.load_page_fault.U), - (s2_tlb_resp.gf.st, Causes.store_guest_page_fault.U), - (s2_tlb_resp.gf.ld, Causes.load_guest_page_fault.U), - (s2_tlb_resp.ae.st, Causes.store_access.U), - (s2_tlb_resp.ae.ld, Causes.load_access.U), - (s2_tlb_resp.ma.st, Causes.misaligned_store.U), - (s2_tlb_resp.ma.ld, Causes.misaligned_load.U) - ) - val s2_xcpt = s2_xcpts.map(_._1).orR - val s2_cause = PriorityMux(s2_xcpts) - val s2_go_to_itc = WireInit(s2_inst.vmu && s2_iterative) - val s2_generate_xcpt = WireInit(s2_xcpt) - - // masked checks, even in the fast case, need to - // to to ITC to get the precise element+address of the trap - when (s2_inst.vmu && s2_xcpt && !s2_inst.vm) { - s2_go_to_itc := true.B - s2_generate_xcpt := false.B - } - - io.s2.inst.valid := s2_valid - io.s2.inst.bits := s2_inst - io.s2.replay := false.B - io.s2.vstart.valid := false.B - io.s2.vstart.bits := 0.U - io.s2.retire := false.B - io.s2.internal_replay.valid := false.B - io.s2.internal_replay.bits := s2_inst - io.s2.internal_replay.bits.rm := Mux(s2_inst.isOpf, io.s2.frm, io.s2.vxrm) - io.s2.xcpt.valid := false.B - io.s2.xcpt.bits.cause := s2_cause - io.s2.xcpt.bits.tval := s2_base - io.s2.pc := s2_inst.pc - io.s2.issue.valid := false.B - io.s2.issue.bits := s2_inst - io.s2.issue.bits.segstart := 0.U - io.s2.issue.bits.segend := s2_inst.seg_nf - io.s2.issue.bits.rm := Mux(s2_inst.isOpf, io.s2.frm, io.s2.vxrm) - io.s2.issue.bits.page := s2_tlb_resp.paddr >> pgIdxBits - - val consumed = ((1 << pgIdxBits).U - s2_tlb_resp.paddr(pgIdxBits-1,0)) >> s2_inst.mem_elem_size - when (s2_inst.vmu && s2_replay_next_page) { - io.s2.issue.bits.vconfig.vl := s2_inst.vstart +& consumed - } - - when (s2_valid) { - when (!io.s2.issue.ready || (io.s2.scalar_store_pending && s2_inst.vmu)) { - io.s2.replay := true.B - } .elsewhen (s2_inst.vstart =/= 0.U && !s2_inst.vmu) { - io.s2.xcpt.valid := true.B - io.s2.xcpt.bits.cause := Causes.illegal_instruction.U - io.s2.xcpt.bits.tval := s2_inst.pc - } .elsewhen (s2_inst.vstart >= s2_inst.vconfig.vl) { - io.s2.retire := true.B - io.s2.issue.valid := true.B - io.s2.vstart.valid := true.B - } .elsewhen (s2_tlb_resp.miss) { - io.s2.replay := true.B - } .elsewhen (s2_generate_xcpt) { - io.s2.xcpt.valid := true.B - } .elsewhen (s2_inst.vmu && s2_fast_sg) { - io.s2.retire := true.B - io.s2.issue.valid := true.B - io.s2.issue.bits.fast_sg := true.B - io.s2.vstart.valid := true.B - } .elsewhen (s2_go_to_itc) { - io.s2.internal_replay.valid := true.B - } .elsewhen (s2_replay_next_page) { - io.s2.replay := true.B - io.s2.issue.valid := true.B - io.s2.vstart.valid := true.B - io.s2.vstart.bits := s2_inst.vstart +& consumed - } .otherwise { - io.s2.retire := true.B - io.s2.vstart.valid := true.B - io.s2.issue.valid := true.B - } - } - -} diff --git a/arch/src/main/scala/framework/gendomain/frontend/HwachaLimiter.scala b/arch/src/main/scala/framework/gendomain/frontend/HwachaLimiter.scala deleted file mode 100644 index a3b9b30b..00000000 --- a/arch/src/main/scala/framework/gendomain/frontend/HwachaLimiter.scala +++ /dev/null @@ -1,57 +0,0 @@ -package framework.gendomain.frontend - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.dataview._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import framework.gendomain.common._ - - -class HwachaLimiter(n: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val vatSz = vParams.vatSz - val io = IO(new Bundle { - val block = Output(Bool()) - val fire = Input(Bool()) - val inst = Input(new VectorIssueInst) - - val vat_release = Input(Vec(1 << vatSz, Bool())) - }) - - val slot_valids = RegInit(VecInit.fill(n)(false.B)) - val slot_vats = Reg(Vec(n, UInt(vatSz.W))) - val head = RegInit(0.U(log2Ceil(n).W)) - val head_p1 = incr(head) - val head_p2 = incr(head_p1) - - def incr(x: UInt) = Mux(x +& 1.U === n.U, 0.U, x + 1.U) - - val issue_2 = io.inst.vmu - val issue_3 = io.inst.vmu && io.inst.mop =/= mopUnit - val slots_available = !slot_valids(head) && (!issue_2 || !slot_valids(head_p1)) && (!issue_3 || !slot_valids(head_p2)) - - io.block := !slots_available - - when (io.fire) { - slot_valids(head) := true.B - slot_vats(head) := io.inst.vat - head := incr(head) - when (issue_2) { - slot_valids(head_p1) := true.B - slot_vats(head_p1) := io.inst.vat - head := incr(head_p1) - } - when (issue_3) { - slot_valids(head_p2) := true.B - slot_vats(head_p2) := io.inst.vat - head := incr(head_p2) - } - } - - for (i <- 0 until n) { - when (io.vat_release(slot_vats(i))) { - slot_valids(i) := false.B - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/frontend/IterativeTrapCheck.scala b/arch/src/main/scala/framework/gendomain/frontend/IterativeTrapCheck.scala deleted file mode 100644 index 98cf47b3..00000000 --- a/arch/src/main/scala/framework/gendomain/frontend/IterativeTrapCheck.scala +++ /dev/null @@ -1,270 +0,0 @@ -package framework.gendomain.frontend - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ - -class IndexMaskAccess(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val in = Input(Bool()) - val inst = Input(new VectorIssueInst) - - val index_access = Flipped(new VectorIndexAccessIO) - val mask_access = Flipped(new VectorMaskAccessIO) - - val access = new Bundle { - val ready = Output(Bool()) - val eidx = Input(UInt(log2Ceil(maxVLMax).W)) - val index = Output(UInt(64.W)) - val mask = Output(Bool()) - } - - val pop = Input(Valid(UInt(log2Ceil(maxVLMax).W))) - val flush = Input(Bool()) - }) - - val valid = RegInit(false.B) - val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - // This all works only with pow2 buffers and eidx starting at 0 - val valids = Reg(Vec(4, Bool())) - val indices = Reg(Vec(4, UInt(64.W))) - val masks = Reg(Vec(4, Bool())) - when (io.in) { - assert(!valid) - valid := true.B - eidx := 0.U - valids.foreach(_ := false.B) - } - - val needs_index = io.inst.mop.isOneOf(mopOrdered, mopUnordered) - val needs_mask = !io.inst.vm - - val index_ready = io.index_access.ready || !needs_index - val mask_ready = io.mask_access.ready || !needs_mask - - io.index_access.valid := valid && needs_index && !valids(eidx(1,0)) - io.mask_access.valid := valid && needs_mask && !valids(eidx(1,0)) - - io.index_access.vrs := io.inst.rs2 - io.index_access.eidx := eidx - io.index_access.eew := io.inst.mem_idx_size - io.mask_access.eidx := eidx - - when (valid && index_ready && mask_ready && !valids(eidx(1,0))) { - val next_eidx = eidx +& 1.U - eidx := eidx + 1.U - when (next_eidx === io.inst.vconfig.vl) { - valid := false.B - } - valids(eidx(1,0)) := true.B - indices(eidx(1,0)) := io.index_access.idx - masks(eidx(1,0)) := io.mask_access.mask - } - - io.access.ready := valids(io.access.eidx(1,0)) - io.access.index := indices(io.access.eidx(1,0)) - io.access.mask := masks(io.access.eidx(1,0)) - - when (io.pop.fire) { - valids(io.pop.bits(1,0)) := false.B - } - when (io.flush) { - valid := false.B - } -} - -class IterativeTrapCheck(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val status = Input(new MStatus) - val in = Input(Valid(new VectorIssueInst)) - val busy = Output(Bool()) - val s0_tlb_req = Valid(new TLBReq(3)) - val s1_tlb_req = Valid(new TLBReq(3)) - val tlb_resp = Input(new TLBResp) - val retire = Output(Bool()) - val pc = Output(UInt(vaddrBitsExtended.W)) - val vstart = Valid(UInt(log2Ceil(maxVLMax).W)) - val vconfig = Valid(new VConfig) - val xcpt = Valid(new Bundle { - val cause = UInt(xLen.W) - val tval = UInt(coreMaxAddrBits.W) - }) - val inst = Output(new VectorIssueInst) - val issue = Decoupled(new VectorIssueInst) - - val index_access = Flipped(new VectorIndexAccessIO) - val mask_access = Flipped(new VectorMaskAccessIO) - }) - - val replay_kill = WireInit(false.B) - - def nextPage(addr: UInt) = ((addr + (1 << pgIdxBits).U) >> pgIdxBits) << pgIdxBits - - val valid = RegInit(false.B) - val seg_hi = Reg(Bool()) - val inst = Reg(new VectorIssueInst) - val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val addr = Reg(UInt(vaddrBitsExtended.W)) - val tlb_backoff = RegInit(0.U(2.W)) - when (tlb_backoff =/= 0.U) { tlb_backoff := tlb_backoff - 1.U } - - val im_access = Module(new IndexMaskAccess) - im_access.io.in := io.in.valid - im_access.io.inst := inst - im_access.io.index_access <> io.index_access - im_access.io.mask_access <> io.mask_access - - when (io.in.valid) { - assert(!valid) - valid := true.B - seg_hi := false.B - inst := io.in.bits - eidx := 0.U - addr := io.in.bits.rs1_data - } - - - val stride = MuxLookup(inst.mop, 0.U)(Seq( - (mopUnit -> ((inst.seg_nf +& 1.U) << inst.mem_elem_size)), - (mopStrided -> inst.rs2_data) - )) - - val indexed = inst.mop.isOneOf(mopOrdered, mopUnordered) - val index_ready = !indexed || im_access.io.access.ready - val mask_ready = inst.vm || im_access.io.access.ready - val index = Mux(indexed, im_access.io.access.index & eewBitMask(inst.mem_idx_size), 0.U) - val base = Mux(indexed, inst.rs1_data, addr) - val indexaddr = base + index - val tlb_addr = Mux(seg_hi, nextPage(indexaddr), indexaddr) - val seg_nf_consumed = ((1 << pgIdxBits).U - Mux(seg_hi, indexaddr, tlb_addr)(pgIdxBits-1,0)) >> inst.mem_elem_size - val seg_single_page = seg_nf_consumed >= (inst.seg_nf +& 1.U) - val masked = !im_access.io.access.mask && !inst.vm - val tlb_valid = eidx < inst.vconfig.vl && eidx >= inst.vstart && !masked - val ff = inst.umop === lumopFF && inst.mop === mopUnit - - io.busy := valid - io.inst := inst - - im_access.io.access.eidx := eidx - - io.s0_tlb_req.valid := tlb_valid && tlb_backoff === 0.U && index_ready && mask_ready - io.s0_tlb_req.bits.vaddr := tlb_addr - io.s0_tlb_req.bits.passthrough := false.B - io.s0_tlb_req.bits.size := inst.mem_elem_size - io.s0_tlb_req.bits.cmd := Mux(inst.opcode(5), M_XWR, M_XRD) - io.s0_tlb_req.bits.prv := io.status.prv - io.s0_tlb_req.bits.v := io.status.v - - io.s1_tlb_req.valid := RegEnable(io.s0_tlb_req.valid, false.B, valid) - io.s1_tlb_req.bits := RegEnable(io.s0_tlb_req.bits, valid) - - val replay_fire = valid && eidx < inst.vconfig.vl && tlb_backoff === 0.U && index_ready && mask_ready - when (replay_fire) { - when (seg_hi || seg_single_page || inst.seg_nf === 0.U) { - eidx := eidx + 1.U - addr := addr + stride - seg_hi := false.B - } .otherwise { - seg_hi := true.B - } - } - - val s1_valid = RegNext(replay_fire && !replay_kill, false.B) - val s1_eidx = RegEnable(eidx, valid) - val s1_masked = RegEnable(masked, valid) - val s1_seg_hi = RegEnable(seg_hi, valid) - val s1_base = RegEnable(base, valid) - val s1_tlb_valid = RegEnable(tlb_valid, valid) - val s1_tlb_addr = RegEnable(tlb_addr, valid) - val s1_seg_nf_consumed = RegEnable(seg_nf_consumed, valid) - val s1_seg_single_page = RegEnable(seg_single_page, valid) - - when (io.tlb_resp.miss && s1_valid && tlb_backoff === 0.U) { tlb_backoff := 3.U } - - val tlb_resp = WireInit(io.tlb_resp) - when (!s1_tlb_valid) { - tlb_resp.miss := false.B - } - - val xcpts = Seq( - (tlb_resp.pf.st, Causes.store_page_fault.U), - (tlb_resp.pf.ld, Causes.load_page_fault.U), - (tlb_resp.gf.st, Causes.store_guest_page_fault.U), - (tlb_resp.gf.ld, Causes.load_guest_page_fault.U), - (tlb_resp.ae.st, Causes.store_access.U), - (tlb_resp.ae.ld, Causes.load_access.U), - (tlb_resp.ma.st, Causes.misaligned_store.U), - (tlb_resp.ma.ld, Causes.misaligned_load.U) - ) - val xcpt = xcpts.map(_._1).orR && s1_eidx >= inst.vstart && !s1_masked - val cause = PriorityMux(xcpts) - - - io.issue.valid := false.B - io.issue.bits := inst - io.issue.bits.vstart := s1_eidx - io.issue.bits.vconfig.vl := s1_eidx +& 1.U - io.issue.bits.segend := inst.seg_nf - io.issue.bits.segstart := 0.U - io.issue.bits.page := tlb_resp.paddr >> pgIdxBits - io.xcpt.valid := false.B - io.pc := inst.pc - io.xcpt.bits.cause := cause - io.xcpt.bits.tval := s1_tlb_addr - io.vstart.valid := false.B - io.vstart.bits := s1_eidx - io.retire := false.B - io.vconfig.valid := false.B - io.vconfig.bits := inst.vconfig - io.vconfig.bits.vl := s1_eidx - im_access.io.pop.valid := false.B - im_access.io.pop.bits := s1_eidx - im_access.io.flush := false.B - - when (s1_valid) { - io.issue.valid := !tlb_resp.miss && !xcpt && s1_eidx >= inst.vstart && !s1_masked - when (inst.seg_nf =/= 0.U && !s1_seg_single_page) { - when (!s1_seg_hi) { - io.issue.bits.segend := s1_seg_nf_consumed - 1.U - } .otherwise { - io.issue.bits.segstart := s1_seg_nf_consumed - } - } - - when (s1_seg_hi || s1_seg_single_page || inst.seg_nf === 0.U) { - im_access.io.pop.valid := true.B - } - - when (tlb_resp.miss || !io.issue.ready) { - tlb_backoff := 3.U - replay_kill := true.B - eidx := s1_eidx - addr := s1_base - seg_hi := s1_seg_hi - im_access.io.pop.valid := false.B - } .elsewhen (xcpt) { - val ff_nofault = ff && s1_eidx =/= 0.U - valid := false.B - replay_kill := true.B - io.retire := ff_nofault - io.xcpt.valid := !ff_nofault - io.vstart.valid := !ff_nofault - io.vconfig.valid := ff_nofault - im_access.io.flush := true.B - } .elsewhen ((s1_eidx +& 1.U) === inst.vconfig.vl && (s1_seg_hi || s1_seg_single_page || inst.seg_nf === 0.U)) { - valid := false.B - replay_kill := true.B - io.retire := true.B - io.vstart.valid := true.B - io.vstart.bits := 0.U - im_access.io.flush := true.B - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/insns/Base.scala b/arch/src/main/scala/framework/gendomain/insns/Base.scala deleted file mode 100644 index ef4092b4..00000000 --- a/arch/src/main/scala/framework/gendomain/insns/Base.scala +++ /dev/null @@ -1,56 +0,0 @@ -package framework.gendomain.insns - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.constants._ -import freechips.rocketchip.util._ - -trait InstructionField { - def default: BitPat - def width: Int - def Y = InstructionProperty(this, true.B) - def N = InstructionProperty(this, false.B) - def dontCare: BitPat = BitPat.dontCare(width) - def apply(v: UInt) = InstructionProperty(this, v(width-1,0)) - def apply(v: BitPat) = InstructionProperty(this, v) - def apply(e: EnumType) = InstructionProperty(this, e.litValue.U(width.W)) -} - -trait NDefaultInstructionField extends InstructionField { - val default: BitPat = false.B - val width: Int = 1 -} - -trait YDefaultInstructionField extends InstructionField { - val default: BitPat = true.B - val width: Int = 1 -} - -trait XDefaultInstructionField extends InstructionField { - def default: BitPat = BitPat.dontCare(width) - val width: Int = 1 -} - -case class InstructionProperty(val field: InstructionField, val value: BitPat) - -trait VectorInstruction { - val props: Seq[InstructionProperty] - def lookup(field: InstructionField) = { - val matches = props.collect { case InstructionProperty(`field`, value) => value } - if (matches.size > 0) { - require(matches.toSet.size <= 1, s"Field lookup for $field returned multiple results") - matches(0) - } else { - field.default - } - } - def elementWise: VectorInstruction = new ElementwiseVectorInstruction(props) -} - -class ElementwiseVectorInstruction(_props: Seq[InstructionProperty]) extends VectorInstruction { - val props = _props :+ Elementwise.Y -} diff --git a/arch/src/main/scala/framework/gendomain/insns/Control.scala b/arch/src/main/scala/framework/gendomain/insns/Control.scala deleted file mode 100644 index 45cd1bf7..00000000 --- a/arch/src/main/scala/framework/gendomain/insns/Control.scala +++ /dev/null @@ -1,96 +0,0 @@ -package framework.gendomain.insns - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.constants._ -import freechips.rocketchip.util._ - -object F6 extends XDefaultInstructionField { override val width: Int = 6 } -object F3 extends XDefaultInstructionField { override val width: Int = 3 } -object RS1 extends XDefaultInstructionField { override val width: Int = 5 } -object RS2 extends XDefaultInstructionField { override val width: Int = 5 } - -object AlwaysReadsVM extends NDefaultInstructionField -object VMBitReadsVM extends YDefaultInstructionField -object ReadsVS1 extends NDefaultInstructionField -object ReadsVS2 extends YDefaultInstructionField -object ReadsVD extends NDefaultInstructionField -object WritesVD extends YDefaultInstructionField -object ScalarToVD0 extends NDefaultInstructionField -object Reduction extends NDefaultInstructionField -object Wide2VD extends NDefaultInstructionField -object Wide2VS2 extends NDefaultInstructionField -object WritesAsMask extends NDefaultInstructionField -object ReadsVS1AsMask extends NDefaultInstructionField -object ReadsVS2AsMask extends NDefaultInstructionField -object WritesScalar extends NDefaultInstructionField -object UsesPermuteSeq extends NDefaultInstructionField -object ZextImm5 extends NDefaultInstructionField - -// Execute Sequencer control -object Elementwise extends NDefaultInstructionField -object SetsWMask extends YDefaultInstructionField -object AccInitZeros extends NDefaultInstructionField -object AccInitOnes extends NDefaultInstructionField -object AccInitPos extends NDefaultInstructionField -object AccInitNeg extends NDefaultInstructionField - -// Integer Pipe control -object Swap12 extends NDefaultInstructionField -object WideningSext extends XDefaultInstructionField - -object DoSub extends XDefaultInstructionField -object Averaging extends XDefaultInstructionField -object CarryIn extends XDefaultInstructionField -object AlwaysCarryIn extends XDefaultInstructionField - -object UsesShift extends NDefaultInstructionField -object ShiftsLeft extends XDefaultInstructionField -object ScalingShift extends XDefaultInstructionField - -object UsesCmp extends NDefaultInstructionField -object CmpLess extends XDefaultInstructionField - -object UsesNarrowingSext extends NDefaultInstructionField -object UsesMinMax extends NDefaultInstructionField -object UsesMerge extends NDefaultInstructionField -object UsesSat extends NDefaultInstructionField -object UsesBitSwap extends NDefaultInstructionField -object UsesCountZeros extends NDefaultInstructionField - -// Bitwise pipe control -object BWAnd extends NDefaultInstructionField -object BWOr extends NDefaultInstructionField -object BWXor extends NDefaultInstructionField -object BWInvOut extends NDefaultInstructionField -object BWInv1 extends NDefaultInstructionField - -// Multiply control -object MULHi extends XDefaultInstructionField -object MULSign1 extends XDefaultInstructionField -object MULSign2 extends XDefaultInstructionField -object MULSwapVdV2 extends NDefaultInstructionField -object MULAccumulate extends NDefaultInstructionField -object MULSub extends XDefaultInstructionField - -// FPFMA control -object FPAdd extends XDefaultInstructionField -object FPMul extends XDefaultInstructionField -object FPSwapVdV2 extends XDefaultInstructionField -object FPFMACmd extends XDefaultInstructionField { override val width = 2 } - -// FPComp control -object FPComp extends NDefaultInstructionField -object FPCompMin extends XDefaultInstructionField - -object FPMEQ extends XDefaultInstructionField -object FPMNE extends XDefaultInstructionField -object FPMLT extends XDefaultInstructionField -object FPMGT extends XDefaultInstructionField - -object FPSgnj extends NDefaultInstructionField -object FPSpecRM extends XDefaultInstructionField { override val width = 3 } diff --git a/arch/src/main/scala/framework/gendomain/insns/Decode.scala b/arch/src/main/scala/framework/gendomain/insns/Decode.scala deleted file mode 100644 index 776bba06..00000000 --- a/arch/src/main/scala/framework/gendomain/insns/Decode.scala +++ /dev/null @@ -1,46 +0,0 @@ -package framework.gendomain.insns - -import chisel3._ -import chisel3.util._ -import chisel3.util.experimental.decode._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.constants._ -import freechips.rocketchip.util._ - - -class VectorDecoder( - funct3: UInt, funct6: UInt, rs1: UInt, rs2: UInt, - insns: Seq[VectorInstruction], - fields: Seq[InstructionField]) { - - val index = Cat(rs1(4,0), rs2(4,0), funct3(2,0), funct6(5,0)) - val lookups = insns.map { i => i.lookup(RS1) ## i.lookup(RS2) ## i.lookup(F3) ## i.lookup(F6) } - val duplicates = lookups.diff(lookups.distinct).distinct - val table = insns.map { i => fields.map(f => i.lookup(f)) :+ BitPat(true.B) } - - val elementsGrouped = table.transpose - val defaults = fields.map(_.dontCare) :+ BitPat(false.B) - val elementWidths = elementsGrouped.zip(defaults).map { case (elts, default) => - require(elts.forall(_.getWidth == default.getWidth)) - default.getWidth - } - val resultWidth = elementWidths.sum - val elementIndices = elementWidths.scan(resultWidth-1) { case (l,r) => l - r } - val truthTable = TruthTable(lookups.zip(table).map { case (l,r) => (l, r.reduce(_ ## _)) }, defaults.reduce(_ ## _)) - val decode = chisel3.util.experimental.decode.decoder(index, truthTable) - val decoded = elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decode(msb, lsb+1) }.toSeq - - def uint(field: InstructionField): UInt = { - val index = fields.indexOf(field) - require(index >= 0, s"Field $field not found in this decoder") - decoded(index) - } - def bool(field: InstructionField): Bool = { - require(field.width == 1) - uint(field)(0) - } - def matched: Bool = decoded.last(0) -} diff --git a/arch/src/main/scala/framework/gendomain/insns/Instructions.scala b/arch/src/main/scala/framework/gendomain/insns/Instructions.scala deleted file mode 100644 index 05728239..00000000 --- a/arch/src/main/scala/framework/gendomain/insns/Instructions.scala +++ /dev/null @@ -1,233 +0,0 @@ -package framework.gendomain.insns - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.constants._ -import freechips.rocketchip.util._ -import framework.gendomain.common.{OPIFunct6, OPMFunct6, OPFFunct6, VectorConsts} - -class OPIVVInstruction(base: OPIInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPIVV), ReadsVS1.Y) -} -class OPIVXInstruction(base: OPIInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPIVX)) -} -class OPIVIInstruction(base: OPIInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPIVI)) -} -class OPMVVInstruction(base: OPMInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPMVV), ReadsVS1.Y) -} -class OPMVXInstruction(base: OPMInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPMVX)) -} -class OPFVVInstruction(base: OPFInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPFVV), ReadsVS1.Y) -} -class OPFVFInstruction(base: OPFInstruction) extends VectorInstruction { - val props = base.props ++ Seq(F3(VectorConsts.OPFVF)) -} - -trait OPIInstruction extends VectorInstruction { - def VV = new OPIVVInstruction(this) - def VX = new OPIVXInstruction(this) - def VI = new OPIVIInstruction(this) -} - -trait OPMInstruction extends VectorInstruction { - def VV = new OPMVVInstruction(this) - def VX = new OPMVXInstruction(this) -} - -trait OPFInstruction extends VectorInstruction { - def VV = new OPFVVInstruction(this) - def VF = new OPFVFInstruction(this) -} - -object ADD extends OPIInstruction { val props = Seq(F6(OPIFunct6.add) , DoSub.N, Averaging.N, CarryIn.N) } -object SUB extends OPIInstruction { val props = Seq(F6(OPIFunct6.sub) , DoSub.Y, Averaging.N, CarryIn.N) } -object RSUB extends OPIInstruction { val props = Seq(F6(OPIFunct6.rsub) , DoSub.Y, Averaging.N, CarryIn.N, Swap12.Y) } -object WADDU extends OPMInstruction { val props = Seq(F6(OPMFunct6.waddu) , DoSub.N, Averaging.N, CarryIn.N, WideningSext.N, Wide2VD.Y) } -object WADD extends OPMInstruction { val props = Seq(F6(OPMFunct6.wadd) , DoSub.N, Averaging.N, CarryIn.N, WideningSext.Y, Wide2VD.Y) } -object WSUBU extends OPMInstruction { val props = Seq(F6(OPMFunct6.wsubu) , DoSub.Y, Averaging.N, CarryIn.N, WideningSext.N, Wide2VD.Y) } -object WSUB extends OPMInstruction { val props = Seq(F6(OPMFunct6.wsub) , DoSub.Y, Averaging.N, CarryIn.N, WideningSext.Y, Wide2VD.Y) } -object WADDUW extends OPMInstruction { val props = Seq(F6(OPMFunct6.wadduw) , DoSub.N, Averaging.N, CarryIn.N, WideningSext.N, Wide2VD.Y, Wide2VS2.Y) } -object WADDW extends OPMInstruction { val props = Seq(F6(OPMFunct6.waddw) , DoSub.N, Averaging.N, CarryIn.N, WideningSext.Y, Wide2VD.Y, Wide2VS2.Y) } -object WSUBUW extends OPMInstruction { val props = Seq(F6(OPMFunct6.wsubuw) , DoSub.Y, Averaging.N, CarryIn.N, WideningSext.N, Wide2VD.Y, Wide2VS2.Y) } -object WSUBW extends OPMInstruction { val props = Seq(F6(OPMFunct6.wsubw) , DoSub.Y, Averaging.N, CarryIn.N, WideningSext.Y, Wide2VD.Y, Wide2VS2.Y) } -object ADC extends OPIInstruction { val props = Seq(F6(OPIFunct6.adc) , DoSub.N, Averaging.N, CarryIn.Y, AlwaysCarryIn.Y, SetsWMask.N) } -object MADC extends OPIInstruction { val props = Seq(F6(OPIFunct6.madc) , DoSub.N, Averaging.N, CarryIn.Y, AlwaysCarryIn.N, SetsWMask.N, WritesAsMask.Y) } -object SBC extends OPIInstruction { val props = Seq(F6(OPIFunct6.sbc) , DoSub.Y, Averaging.N, CarryIn.Y, AlwaysCarryIn.Y, SetsWMask.N) } -object MSBC extends OPIInstruction { val props = Seq(F6(OPIFunct6.msbc) , DoSub.Y, Averaging.N, CarryIn.Y, AlwaysCarryIn.N, SetsWMask.N, WritesAsMask.Y) } -object NEXT extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b00???")), UsesNarrowingSext.Y) } -object SLL extends OPIInstruction { val props = Seq(F6(OPIFunct6.sll) , UsesShift.Y, ShiftsLeft.Y, ScalingShift.N) } -object SRA extends OPIInstruction { val props = Seq(F6(OPIFunct6.sra) , UsesShift.Y, ShiftsLeft.N, ScalingShift.N) } -object SRL extends OPIInstruction { val props = Seq(F6(OPIFunct6.srl) , UsesShift.Y, ShiftsLeft.N, ScalingShift.N, ZextImm5.Y) } -object NSRA extends OPIInstruction { val props = Seq(F6(OPIFunct6.nsra) , UsesShift.Y, ShiftsLeft.N, ScalingShift.N, WideningSext.N, Wide2VS2.Y, ZextImm5.Y) } -object NSRL extends OPIInstruction { val props = Seq(F6(OPIFunct6.nsrl) , UsesShift.Y, ShiftsLeft.N, ScalingShift.N, WideningSext.N, Wide2VS2.Y, ZextImm5.Y) } -object MSEQ extends OPIInstruction { val props = Seq(F6(OPIFunct6.mseq) , WritesAsMask.Y, UsesCmp.Y, CmpLess.N) } -object MSNE extends OPIInstruction { val props = Seq(F6(OPIFunct6.msne) , WritesAsMask.Y, UsesCmp.Y, CmpLess.N) } -object MSLTU extends OPIInstruction { val props = Seq(F6(OPIFunct6.msltu) , WritesAsMask.Y, UsesCmp.Y, CmpLess.Y) } -object MSLT extends OPIInstruction { val props = Seq(F6(OPIFunct6.mslt) , WritesAsMask.Y, UsesCmp.Y, CmpLess.Y) } -object MSLEU extends OPIInstruction { val props = Seq(F6(OPIFunct6.msleu) , WritesAsMask.Y, UsesCmp.Y, CmpLess.Y) } -object MSLE extends OPIInstruction { val props = Seq(F6(OPIFunct6.msle) , WritesAsMask.Y, UsesCmp.Y, CmpLess.Y) } -object MSGTU extends OPIInstruction { val props = Seq(F6(OPIFunct6.msgtu) , WritesAsMask.Y, UsesCmp.Y, CmpLess.Y, Swap12.Y) } -object MSGT extends OPIInstruction { val props = Seq(F6(OPIFunct6.msgt) , WritesAsMask.Y, UsesCmp.Y, CmpLess.Y, Swap12.Y) } -object MINU extends OPIInstruction { val props = Seq(F6(OPIFunct6.minu) , UsesMinMax.Y, CmpLess.Y) } -object MIN extends OPIInstruction { val props = Seq(F6(OPIFunct6.min) , UsesMinMax.Y, CmpLess.Y) } -object MAXU extends OPIInstruction { val props = Seq(F6(OPIFunct6.maxu) , UsesMinMax.Y, CmpLess.Y, Swap12.Y) } -object MAX extends OPIInstruction { val props = Seq(F6(OPIFunct6.max) , UsesMinMax.Y, CmpLess.Y, Swap12.Y) } -object MERGE extends OPIInstruction { val props = Seq(F6(OPIFunct6.merge) , AlwaysReadsVM.Y, UsesMerge.Y, SetsWMask.N) } -object SADDU extends OPIInstruction { val props = Seq(F6(OPIFunct6.saddu) , DoSub.N, Averaging.N, CarryIn.N, UsesSat.Y) } -object SADD extends OPIInstruction { val props = Seq(F6(OPIFunct6.sadd) , DoSub.N, Averaging.N, CarryIn.N, UsesSat.Y) } -object SSUBU extends OPIInstruction { val props = Seq(F6(OPIFunct6.ssubu) , DoSub.Y, Averaging.N, CarryIn.N, UsesSat.Y) } -object SSUB extends OPIInstruction { val props = Seq(F6(OPIFunct6.ssub) , DoSub.Y, Averaging.N, CarryIn.N, UsesSat.Y) } -object AADDU extends OPMInstruction { val props = Seq(F6(OPMFunct6.aaddu) , DoSub.N, Averaging.Y, CarryIn.N) } -object AADD extends OPMInstruction { val props = Seq(F6(OPMFunct6.aadd) , DoSub.N, Averaging.Y, CarryIn.N) } -object ASUBU extends OPMInstruction { val props = Seq(F6(OPMFunct6.asubu) , DoSub.Y, Averaging.Y, CarryIn.N) } -object ASUB extends OPMInstruction { val props = Seq(F6(OPMFunct6.asub) , DoSub.Y, Averaging.Y, CarryIn.N) } -object SSRL extends OPIInstruction { val props = Seq(F6(OPIFunct6.ssrl) , UsesShift.Y, ShiftsLeft.N, ScalingShift.Y, ZextImm5.Y) } -object SSRA extends OPIInstruction { val props = Seq(F6(OPIFunct6.ssra) , UsesShift.Y, ShiftsLeft.N, ScalingShift.Y) } -object NCLIPU extends OPIInstruction { val props = Seq(F6(OPIFunct6.nclipu) , UsesShift.Y, ShiftsLeft.N, ScalingShift.Y, Wide2VS2.Y, ZextImm5.Y) } -object NCLIP extends OPIInstruction { val props = Seq(F6(OPIFunct6.nclip) , UsesShift.Y, ShiftsLeft.N, ScalingShift.Y, Wide2VS2.Y, ZextImm5.Y) } -object REDSUM extends OPMInstruction { val props = Seq(F6(OPMFunct6.redsum) , Reduction.Y, AccInitZeros.Y, DoSub.N, Averaging.N, CarryIn.N) } -object WREDSUM extends OPIInstruction { val props = Seq(F6(OPIFunct6.wredsum) , Reduction.Y, AccInitZeros.Y, DoSub.N, Averaging.N, CarryIn.N, WideningSext.Y, Wide2VD.Y) } -object WREDSUMU extends OPIInstruction { val props = Seq(F6(OPIFunct6.wredsumu), Reduction.Y, AccInitZeros.Y, DoSub.N, Averaging.N, CarryIn.N, WideningSext.N, Wide2VD.Y) } -object REDMINU extends OPMInstruction { val props = Seq(F6(OPMFunct6.redminu) , Reduction.Y, AccInitOnes.Y , UsesMinMax.Y, CmpLess.Y) } -object REDMIN extends OPMInstruction { val props = Seq(F6(OPMFunct6.redmin) , Reduction.Y, AccInitPos.Y , UsesMinMax.Y, CmpLess.Y) } -object REDMAXU extends OPMInstruction { val props = Seq(F6(OPMFunct6.redmaxu) , Reduction.Y, AccInitZeros.Y, UsesMinMax.Y, CmpLess.Y, Swap12.Y) } -object REDMAX extends OPMInstruction { val props = Seq(F6(OPMFunct6.redmax) , Reduction.Y, AccInitNeg.Y , UsesMinMax.Y, CmpLess.Y, Swap12.Y) } -object FMERGE extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmerge) , AlwaysReadsVM.Y, UsesMerge.Y, SetsWMask.N) } - - -object AND extends OPIInstruction { val props = Seq(F6(OPIFunct6.and) , BWAnd.Y) } -object OR extends OPIInstruction { val props = Seq(F6(OPIFunct6.or) , BWOr.Y) } -object XOR extends OPIInstruction { val props = Seq(F6(OPIFunct6.xor) , BWXor.Y) } -object MANDNOT extends OPMInstruction { val props = Seq(F6(OPMFunct6.mandnot) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWAnd.Y, BWInv1.Y) } -object MAND extends OPMInstruction { val props = Seq(F6(OPMFunct6.mand) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWAnd.Y) } -object MOR extends OPMInstruction { val props = Seq(F6(OPMFunct6.mor) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWOr.Y) } -object MXOR extends OPMInstruction { val props = Seq(F6(OPMFunct6.mxor) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWXor.Y) } -object MORNOT extends OPMInstruction { val props = Seq(F6(OPMFunct6.mornot) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWOr.Y, BWInv1.Y) } -object MNAND extends OPMInstruction { val props = Seq(F6(OPMFunct6.mnand) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWAnd.Y, BWInvOut.Y) } -object MNOR extends OPMInstruction { val props = Seq(F6(OPMFunct6.mnor) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWOr.Y, BWInvOut.Y) } -object MXNOR extends OPMInstruction { val props = Seq(F6(OPMFunct6.mxnor) , WritesAsMask.Y, ReadsVS1AsMask.Y, ReadsVS2AsMask.Y, BWXor.Y, BWInvOut.Y) } -object REDAND extends OPMInstruction { val props = Seq(F6(OPMFunct6.redand) , Reduction.Y, AccInitOnes.Y , BWAnd.Y) } -object REDOR extends OPMInstruction { val props = Seq(F6(OPMFunct6.redor) , Reduction.Y, AccInitZeros.Y, BWOr.Y) } -object REDXOR extends OPMInstruction { val props = Seq(F6(OPMFunct6.redxor) , Reduction.Y, AccInitZeros.Y, BWXor.Y) } - -object MUL extends OPMInstruction { val props = Seq(F6(OPMFunct6.mul) , MULHi.N) } -object MULH extends OPMInstruction { val props = Seq(F6(OPMFunct6.mulh) , MULHi.Y, MULSign1.Y, MULSign2.Y) } -object MULHU extends OPMInstruction { val props = Seq(F6(OPMFunct6.mulhu) , MULHi.Y, MULSign1.N, MULSign2.N) } -object MULHSU extends OPMInstruction { val props = Seq(F6(OPMFunct6.mulhsu) , MULHi.Y, MULSign1.N, MULSign2.Y) } -object WMUL extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmul) , MULHi.N, MULSign1.Y, MULSign2.Y, Wide2VD.Y) } -object WMULU extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmulu) , MULHi.N, MULSign1.N, MULSign2.N, Wide2VD.Y) } -object WMULSU extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmulsu) , MULHi.N, MULSign1.N, MULSign2.Y, Wide2VD.Y) } -object MACC extends OPMInstruction { val props = Seq(F6(OPMFunct6.macc) , MULHi.N, ReadsVD.Y, MULAccumulate.Y, MULSub.N) } -object NMSAC extends OPMInstruction { val props = Seq(F6(OPMFunct6.nmsac) , MULHi.N, ReadsVD.Y, MULAccumulate.Y, MULSub.Y) } -object MADD extends OPMInstruction { val props = Seq(F6(OPMFunct6.madd) , MULHi.N, ReadsVD.Y, MULAccumulate.Y, MULSub.N, MULSwapVdV2.Y) } -object NMSUB extends OPMInstruction { val props = Seq(F6(OPMFunct6.nmsub) , MULHi.N, ReadsVD.Y, MULAccumulate.Y, MULSub.Y, MULSwapVdV2.Y) } -object WMACC extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmacc) , MULHi.N, ReadsVD.Y, MULSign1.Y, MULSign2.Y, MULAccumulate.Y, MULSub.N, Wide2VD.Y) } -object WMACCU extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmaccu) , MULHi.N, ReadsVD.Y, MULSign1.N, MULSign2.N, MULAccumulate.Y, MULSub.N, Wide2VD.Y) } -object WMACCUS extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmaccus) , MULHi.N, ReadsVD.Y, MULSign1.N, MULSign2.Y, MULAccumulate.Y, MULSub.N, Wide2VD.Y) } -object WMACCSU extends OPMInstruction { val props = Seq(F6(OPMFunct6.wmaccsu) , MULHi.N, ReadsVD.Y, MULSign1.Y, MULSign2.N, MULAccumulate.Y, MULSub.N, Wide2VD.Y) } -object SMUL extends OPIInstruction { val props = Seq(F6(OPIFunct6.smul) , MULHi.N, MULSign1.Y, MULSign2.Y, MULSub.N) } - -object DIV extends OPMInstruction { val props = Seq(F6(OPMFunct6.div)) } -object DIVU extends OPMInstruction { val props = Seq(F6(OPMFunct6.divu)) } -object REM extends OPMInstruction { val props = Seq(F6(OPMFunct6.rem)) } -object REMU extends OPMInstruction { val props = Seq(F6(OPMFunct6.remu)) } - -object MV_S_X extends VectorInstruction { val props = Seq(F6(OPMFunct6.wrxunary0), F3(VectorConsts.OPMVX), RS2( 0.U(5.W)), ReadsVS2.N, VMBitReadsVM.N, ScalarToVD0.Y) } -object MV_X_S extends VectorInstruction { val props = Seq(F6(OPMFunct6.wrxunary0), F3(VectorConsts.OPMVV), RS1( 0.U(5.W)), ReadsVS2.Y, VMBitReadsVM.N, WritesScalar.Y, WritesVD.N) } -object POPC extends VectorInstruction { val props = Seq(F6(OPMFunct6.wrxunary0), F3(VectorConsts.OPMVV), RS1(16.U(5.W)), ReadsVS2.Y, VMBitReadsVM.Y, WritesScalar.Y, WritesVD.N, ReadsVS2AsMask.Y) } -object FIRST extends VectorInstruction { val props = Seq(F6(OPMFunct6.wrxunary0), F3(VectorConsts.OPMVV), RS1(17.U(5.W)), ReadsVS2.Y, VMBitReadsVM.Y, WritesScalar.Y, WritesVD.N, ReadsVS2AsMask.Y) } -object FMV_S_F extends VectorInstruction { val props = Seq(F6(OPFFunct6.wrfunary0), F3(VectorConsts.OPFVF), RS2( 0.U(5.W)), ReadsVS2.N, VMBitReadsVM.N, ScalarToVD0.Y) } -object FMV_F_S extends VectorInstruction { val props = Seq(F6(OPFFunct6.wrfunary0), F3(VectorConsts.OPFVV), RS1( 0.U(5.W)), ReadsVS2.Y, VMBitReadsVM.N, WritesScalar.Y, WritesVD.N) } -object MSBF extends VectorInstruction { val props = Seq(F6(OPMFunct6.munary0) , F3(VectorConsts.OPMVV), RS1( 1.U(5.W)), ReadsVS2AsMask.Y, WritesAsMask.Y) } -object MSOF extends VectorInstruction { val props = Seq(F6(OPMFunct6.munary0) , F3(VectorConsts.OPMVV), RS1( 2.U(5.W)), ReadsVS2AsMask.Y, WritesAsMask.Y) } -object MSIF extends VectorInstruction { val props = Seq(F6(OPMFunct6.munary0) , F3(VectorConsts.OPMVV), RS1( 3.U(5.W)), ReadsVS2AsMask.Y, WritesAsMask.Y) } -object IOTA extends VectorInstruction { val props = Seq(F6(OPMFunct6.munary0) , F3(VectorConsts.OPMVV), RS1(16.U(5.W)), ReadsVS2AsMask.Y) } -object ID extends VectorInstruction { val props = Seq(F6(OPMFunct6.munary0) , F3(VectorConsts.OPMVV), RS1(17.U(5.W)), ReadsVS2AsMask.Y, ReadsVS2.N) } - -object FADD extends OPFInstruction { val props = Seq(F6(OPFFunct6.fadd) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W))) } -object FSUB extends OPFInstruction { val props = Seq(F6(OPFFunct6.fsub) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(1.U(2.W))) } -object FRSUB extends OPFInstruction { val props = Seq(F6(OPFFunct6.frsub) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(2.U(2.W))) } -object FMUL extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmul) , FPAdd.N, FPMul.Y, FPSwapVdV2.N, FPFMACmd(0.U(2.W))) } -object FMACC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmacc) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), ReadsVD.Y) } -object FNMACC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fnmacc) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(3.U(2.W)), ReadsVD.Y) } -object FMSAC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmsac) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(1.U(2.W)), ReadsVD.Y) } -object FNMSAC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fnmsac) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(2.U(2.W)), ReadsVD.Y) } -object FMADD extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmadd) , FPAdd.Y, FPMul.Y, FPSwapVdV2.Y, FPFMACmd(0.U(2.W)), ReadsVD.Y) } -object FNMADD extends OPFInstruction { val props = Seq(F6(OPFFunct6.fnmadd) , FPAdd.Y, FPMul.Y, FPSwapVdV2.Y, FPFMACmd(3.U(2.W)), ReadsVD.Y) } -object FMSUB extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmsub) , FPAdd.Y, FPMul.Y, FPSwapVdV2.Y, FPFMACmd(1.U(2.W)), ReadsVD.Y) } -object FNMSUB extends OPFInstruction { val props = Seq(F6(OPFFunct6.fnmsub) , FPAdd.Y, FPMul.Y, FPSwapVdV2.Y, FPFMACmd(2.U(2.W)), ReadsVD.Y) } -object FWADD extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwadd) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Wide2VD.Y) } -object FWSUB extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwsub) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(1.U(2.W)), Wide2VD.Y) } -object FWADDW extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwaddw) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Wide2VD.Y, Wide2VS2.Y) } -object FWSUBW extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwsubw) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(1.U(2.W)), Wide2VD.Y, Wide2VS2.Y) } -object FWMUL extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwmul) , FPAdd.N, FPMul.Y, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Wide2VD.Y) } -object FWMACC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwmacc) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Wide2VD.Y, ReadsVD.Y) } -object FWNMACC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwnmacc) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(3.U(2.W)), Wide2VD.Y, ReadsVD.Y) } -object FWMSAC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwmsac) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(1.U(2.W)), Wide2VD.Y, ReadsVD.Y) } -object FWNMSAC extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwnmsac) , FPAdd.Y, FPMul.Y, FPSwapVdV2.N, FPFMACmd(2.U(2.W)), Wide2VD.Y, ReadsVD.Y) } -object FREDOSUM extends OPFInstruction { val props = Seq(F6(OPFFunct6.fredosum) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Reduction.Y, AccInitZeros.Y, Elementwise.Y) } -object FREDUSUM extends OPFInstruction { val props = Seq(F6(OPFFunct6.fredusum) , FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Reduction.Y, AccInitZeros.Y) } -object FWREDOSUM extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwredosum), FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Wide2VD.Y, Reduction.Y, AccInitZeros.Y, Elementwise.Y) } -object FWREDUSUM extends OPFInstruction { val props = Seq(F6(OPFFunct6.fwredusum), FPAdd.Y, FPMul.N, FPSwapVdV2.N, FPFMACmd(0.U(2.W)), Wide2VD.Y, Reduction.Y, AccInitZeros.Y) } - -object FDIV extends OPFInstruction { val props = Seq(F6(OPFFunct6.fdiv) , FPSwapVdV2.N, FPAdd.N, FPMul.N) } -object FRDIV extends OPFInstruction { val props = Seq(F6(OPFFunct6.frdiv) , FPSwapVdV2.Y, FPAdd.N, FPMul.N) } -object FSQRT_V extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary1) , F3(VectorConsts.OPFVV), RS1( 0.U(5.W)), FPSwapVdV2.N, FPAdd.N, FPMul.N) } -object FRSQRT7_V extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary1) , F3(VectorConsts.OPFVV), RS1( 4.U(5.W)), FPSwapVdV2.N) } -object FREC7_V extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary1) , F3(VectorConsts.OPFVV), RS1( 5.U(5.W)), FPSwapVdV2.N) } -object FCLASS_V extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary1) , F3(VectorConsts.OPFVV), RS1(16.U(5.W)), FPSwapVdV2.N, FPAdd.N, FPMul.N, FPSpecRM(1.U(3.W))) } - -object FMIN extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmin) , FPComp.Y, FPCompMin.Y, FPAdd.N, FPMul.N, FPSpecRM(0.U(3.W))) } -object FMAX extends OPFInstruction { val props = Seq(F6(OPFFunct6.fmax) , FPComp.Y, FPCompMin.N, FPAdd.N, FPMul.N, FPSpecRM(1.U(3.W))) } -object FSGNJ extends OPFInstruction { val props = Seq(F6(OPFFunct6.fsgnj) , FPSgnj.Y, FPAdd.N, FPMul.N, FPSpecRM(0.U(3.W))) } -object FSGNJN extends OPFInstruction { val props = Seq(F6(OPFFunct6.fsgnjn) , FPSgnj.Y, FPAdd.N, FPMul.N, FPSpecRM(1.U(2.W))) } -object FSGNJX extends OPFInstruction { val props = Seq(F6(OPFFunct6.fsgnjx) , FPSgnj.Y, FPAdd.N, FPMul.N, FPSpecRM(2.U(3.W))) } -object MFEQ extends OPFInstruction { val props = Seq(F6(OPFFunct6.mfeq) , WritesAsMask.Y, FPMEQ.Y, FPMNE.N, FPMLT.N, FPMGT.N, FPAdd.N, FPMul.N, FPSpecRM(2.U(3.W))) } -object MFNE extends OPFInstruction { val props = Seq(F6(OPFFunct6.mfne) , WritesAsMask.Y, FPMEQ.N, FPMNE.Y, FPMLT.N, FPMGT.N, FPAdd.N, FPMul.N, FPSpecRM(2.U(3.W))) } -object MFLT extends OPFInstruction { val props = Seq(F6(OPFFunct6.mflt) , WritesAsMask.Y, FPMEQ.N, FPMNE.N, FPMLT.Y, FPMGT.N, FPAdd.N, FPMul.N, FPSpecRM(1.U(3.W))) } -object MFLE extends OPFInstruction { val props = Seq(F6(OPFFunct6.mfle) , WritesAsMask.Y, FPMEQ.Y, FPMNE.N, FPMLT.Y, FPMGT.N, FPAdd.N, FPMul.N, FPSpecRM(0.U(3.W))) } -object MFGT extends OPFInstruction { val props = Seq(F6(OPFFunct6.mfgt) , WritesAsMask.Y, FPMEQ.N, FPMNE.N, FPMLT.N, FPMGT.Y, FPAdd.N, FPMul.N, FPSpecRM(0.U(3.W))) } -object MFGE extends OPFInstruction { val props = Seq(F6(OPFFunct6.mfge) , WritesAsMask.Y, FPMEQ.Y, FPMNE.N, FPMLT.N, FPMGT.Y, FPAdd.N, FPMul.N, FPSpecRM(1.U(3.W))) } -object FREDMIN extends OPFInstruction { val props = Seq(F6(OPFFunct6.fredmin) , FPComp.Y, FPCompMin.Y, Reduction.Y, FPAdd.N, FPMul.N, FPSpecRM(0.U(3.W))) } -object FREDMAX extends OPFInstruction { val props = Seq(F6(OPFFunct6.fredmax) , FPComp.Y, FPCompMin.N, Reduction.Y, FPAdd.N, FPMul.N, FPSpecRM(1.U(3.W))) } - -object FCVT_SGL extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b00???")), FPAdd.N, FPMul.N) } -object FCVT_WID extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b01???")), Wide2VD.Y, FPAdd.N, FPMul.N) } -object FCVT_NRW extends VectorInstruction { val props = Seq(F6(OPFFunct6.funary0), F3(VectorConsts.OPFVV), RS1(BitPat("b10???")), Wide2VD.N, Wide2VS2.Y, FPAdd.N, FPMul.N) } - -object SLIDEUP extends OPIInstruction { val props = Seq(F6(OPIFunct6.slideup) , UsesPermuteSeq.Y, ReadsVS2.N) } -object SLIDEDOWN extends OPIInstruction { val props = Seq(F6(OPIFunct6.slidedown) , UsesPermuteSeq.Y, ReadsVS2.N) } -object SLIDE1UP extends OPMInstruction { val props = Seq(F6(OPMFunct6.slide1up) , UsesPermuteSeq.Y, ReadsVS2.N) } -object SLIDE1DOWN extends OPMInstruction { val props = Seq(F6(OPMFunct6.slide1down) , UsesPermuteSeq.Y, ReadsVS2.N) } -object FSLIDE1UP extends OPFInstruction { val props = Seq(F6(OPFFunct6.fslide1up) , UsesPermuteSeq.Y, ReadsVS2.N) } -object FSLIDE1DOWN extends OPFInstruction { val props = Seq(F6(OPFFunct6.fslide1down), UsesPermuteSeq.Y, ReadsVS2.N) } - -object RGATHER_VX extends VectorInstruction { val props = Seq(F6(OPIFunct6.rgather) , F3(VectorConsts.OPIVX)) } -object RGATHER_VI extends VectorInstruction { val props = Seq(F6(OPIFunct6.rgather) , F3(VectorConsts.OPIVI)) } -object RGATHER_VV extends VectorInstruction { val props = Seq(F6(OPIFunct6.rgather) , F3(VectorConsts.OPIVV), UsesPermuteSeq.Y, Elementwise.Y) } -object RGATHEREI16 extends VectorInstruction { val props = Seq(F6(OPIFunct6.rgatherei16), F3(VectorConsts.OPIVV), UsesPermuteSeq.Y, Elementwise.Y) } -object COMPRESS extends OPMInstruction { val props = Seq(F6(OPMFunct6.compress) , ReadsVS1AsMask.Y, Elementwise.Y) } -object MVNRR extends VectorInstruction { val props = Seq(F6(OPIFunct6.mvnrr) , F3(VectorConsts.OPIVI)) } - - -// Zvbb instructions -object ANDN extends OPIInstruction { val props = Seq(F6(OPIFunct6.andn) , BWAnd.Y, BWInv1.Y) } -object BREV8 extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b01000")), UsesBitSwap.Y) } -object REV8 extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b01001")), UsesBitSwap.Y) } -object BREV extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b01010")), UsesBitSwap.Y) } -object CLZ extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b01100")), UsesCountZeros.Y) } -object CTZ extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b01101")), UsesCountZeros.Y) } -object CPOP extends OPMInstruction { val props = Seq(F6(OPMFunct6.xunary0) , RS1(BitPat("b01110")), UsesCountZeros.Y) } -object ROL extends OPIInstruction { val props = Seq(F6(OPIFunct6.rol) , UsesShift.Y, ShiftsLeft.Y, ScalingShift.N) } -object RORI extends OPIInstruction { val props = Seq(F6(OPIFunct6.rol) , UsesShift.Y, ShiftsLeft.Y, ScalingShift.N) } -object ROR extends OPIInstruction { val props = Seq(F6(OPIFunct6.ror) , UsesShift.Y, ShiftsLeft.N, ScalingShift.N) } -object WSLL extends OPIInstruction { val props = Seq(F6(OPIFunct6.wsll) , UsesShift.Y, ShiftsLeft.Y, ScalingShift.N, Wide2VD.Y, ZextImm5.Y) } diff --git a/arch/src/main/scala/framework/gendomain/mem/AddrGen.scala b/arch/src/main/scala/framework/gendomain/mem/AddrGen.scala deleted file mode 100644 index 84e0367a..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/AddrGen.scala +++ /dev/null @@ -1,127 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class AddrGen(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val valid = Input(Bool()) - val lsiq_id = Input(UInt(lsiqIdBits.W)) - val done = Output(Bool()) - val tag = Flipped(Decoupled(UInt(dmemTagBits.W))) - val op = Input(new VectorMemMacroOp) - val maskindex = new Bundle { - val index = Input(UInt(64.W)) - val mask = Input(Bool()) - val eew = Output(UInt(2.W)) - val needs_mask = Output(Bool()) - val needs_index = Output(Bool()) - val valid = Input(Bool()) - val ready = Output(Bool()) - } - val req = Decoupled(new MemRequest(dLenB, dmemTagBits)) - - val out = Decoupled(new IFQEntry) - }) - - def min(a: UInt, b: UInt) = Mux(a > b, b, a) - - def getElems(off: UInt, eew: UInt): UInt = { - (dLenB.U - off(dLenOffBits-1,0)) >> eew - } - - val r_eaddr = Reg(UInt(paddrBits.W)) - val r_saddr = Reg(UInt(paddrBits.W)) - val r_eidx = Reg(UInt((1+log2Ceil(8*maxVLMax)).W)) - val r_sidx = Reg(UInt(3.W)) - val r_head = RegInit(true.B) - - val fast_segmented = io.op.mop === mopUnit && io.op.segend === io.op.seg_nf && io.op.segstart === 0.U - val eidx = Mux(r_head, - io.op.vstart * (Mux(fast_segmented, io.op.seg_nf, 0.U) +& 1.U), - r_eidx) - val sidx = Mux(r_head, io.op.segstart , r_sidx) - val start_offset = (io.op.vstart * Mux(io.op.mop === mopStrided, - io.op.stride, - (io.op.seg_nf +& 1.U) << io.op.elem_size))(pgIdxBits-1,0) - val start_addr = io.op.base_offset + start_offset + (io.op.segstart << io.op.elem_size) - val index_offset = io.maskindex.index & eewBitMask(io.op.idx_size) - val eaddr = Mux(io.op.indexed, - io.op.base_offset + index_offset + Mux(r_head, io.op.segstart << io.op.elem_size, 0.U), - Mux(r_head, start_addr, r_eaddr)) - val saddr = Mux(io.op.seg_nf =/= 0.U && !fast_segmented, Mux(r_head, eaddr, r_saddr), eaddr) - - val mem_size = io.op.elem_size - val max_eidx = Mux(fast_segmented, - io.op.vl * (io.op.seg_nf +& 1.U), - io.op.vl) - - val next_max_elems = getElems(saddr, mem_size) - val next_contig_elems = Mux(fast_segmented, - max_eidx - eidx, - io.op.seg_nf +& 1.U - sidx) - val next_act_elems = min(next_contig_elems, next_max_elems)(dLenOffBits,0) - val next_act_bytes = next_act_elems << mem_size - - val next_sidx = sidx +& next_act_elems - val next_eidx = eidx +& Mux(fast_segmented, next_act_elems, 1.U) - - val next_eaddr = eaddr + Mux(io.op.mop === mopUnit, next_act_bytes, Mux(io.op.mop === mopStrided, io.op.stride, 0.U)) - val next_saddr = saddr + next_act_bytes - - val needs_mask = !io.op.vm && io.op.mop =/= mopUnit - val needs_index = io.op.mop(0) - val block_maskindex = (needs_mask || needs_index) && !io.maskindex.valid - - val masked = (needs_mask && !io.maskindex.mask) || (io.op.seg_nf > 0.U && sidx > io.op.segend) - val may_clear = (fast_segmented || next_sidx > io.op.seg_nf) && next_eidx >= max_eidx - - - io.done := false.B - io.maskindex.ready := false.B - io.maskindex.needs_mask := needs_mask - io.maskindex.needs_index := needs_index - io.maskindex.eew := io.op.idx_size - io.out.valid := io.valid && !block_maskindex && (masked || io.req.ready) && io.tag.valid - io.out.bits.head := saddr - io.out.bits.tail := saddr + next_act_bytes - io.out.bits.masked := masked - io.out.bits.last := may_clear - io.out.bits.lsiq_id := io.lsiq_id - io.out.bits.page_offset := saddr(pgIdxBits-1,0) - - io.req.valid := io.valid && io.out.ready && !block_maskindex && !masked && io.tag.valid - io.req.bits.addr := Cat(io.op.page, saddr(pgIdxBits-1,0)) - io.req.bits.data := DontCare - io.req.bits.mask := ((1.U << next_act_bytes) - 1.U) << saddr(dLenOffBits-1,0) - io.req.bits.tag := io.tag.bits - io.req.bits.store := DontCare - - io.tag.ready := io.valid && (io.req.ready || masked) && io.out.ready && !block_maskindex - - when (io.out.fire) { - when (next_sidx > io.op.seg_nf || fast_segmented) { - r_eaddr := next_eaddr - r_saddr := next_eaddr - r_eidx := next_eidx - r_sidx := 0.U - io.maskindex.ready := needs_mask || needs_index - } .otherwise { - r_eaddr := eaddr - r_saddr := next_saddr - r_eidx := io.op.vstart - r_sidx := next_sidx - } - r_head := false.B - when (may_clear) { - io.done := true.B - r_head := true.B - } - } - -} diff --git a/arch/src/main/scala/framework/gendomain/mem/LoadOrderBuffer.scala b/arch/src/main/scala/framework/gendomain/mem/LoadOrderBuffer.scala deleted file mode 100644 index d839ef92..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/LoadOrderBuffer.scala +++ /dev/null @@ -1,112 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import framework.gendomain.common._ - -object AgePriorityEncoder -{ - def apply(in: Seq[Bool], head: UInt): UInt = { - val n = in.size - val width = log2Ceil(in.size) - val n_padded = 1 << width - val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in - val idx = PriorityEncoder(temp_vec) - idx(width-1, 0) //discard msb - } -} - -class LoadOrderBuffer(nEntries: Int, nRobEntries: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - require(nEntries > 0, "Queue must have non-negative number of entries") - require(nRobEntries <= nEntries) - - val tagBits = log2Ceil(nEntries) - val io = IO(new Bundle { - val reserve = Decoupled(UInt(tagBits.W)) - val entry = Input(new IFQEntry) - val push = Input(Valid(new Bundle { - val data = UInt(dLen.W) - val tag = UInt(tagBits.W) - })) - - val replay_liq_id = Output(UInt(log2Ceil(vParams.vliqEntries).W)) - val replay = Decoupled(new MemRequest(dLenB, dmemTagBits)) - val deq = Decoupled(new IFQEntry) - val deq_data = Output(UInt(dLen.W)) - val busy = Output(Bool()) - }) - - val simpleRob = nEntries == nRobEntries - - val valids = RegInit(VecInit.fill(nEntries)(false.B)) - val must_replay = RegInit(VecInit.fill(nEntries)(false.B)) - val entries = Reg(Vec(nEntries, new IFQEntry)) - val rob_idxs = Reg(Vec(nEntries, UInt(log2Ceil(nRobEntries).W))) - val rob = Reg(Vec(nRobEntries, UInt(dLen.W))) - val rob_valids = RegInit(VecInit.fill(nRobEntries)(false.B)) - - val enq_ptr = Counter(nEntries) - val deq_ptr = Counter(nEntries) - val maybe_full = RegInit(false.B) - val has_replay = must_replay.orR - val rob_full = rob_valids.andR && (!simpleRob).B - val rob_next = PriorityEncoder(~rob_valids) - val ptr_match = enq_ptr.value === deq_ptr.value - val empty = ptr_match && !maybe_full - val full = ptr_match && maybe_full - - io.busy := !empty - io.reserve.valid := !full && !has_replay - io.reserve.bits := enq_ptr.value - when (io.reserve.fire) { - entries(enq_ptr.value) := io.entry - valids(enq_ptr.value) := io.entry.masked - enq_ptr.inc() - } - - io.deq.valid := !empty && (valids(deq_ptr.value) || (io.push.fire && io.push.bits.tag === deq_ptr.value)) - io.deq.bits := entries(deq_ptr.value) - val rob_deq_idx = if (simpleRob) deq_ptr.value else rob_idxs(deq_ptr.value) - io.deq_data := Mux(valids(deq_ptr.value), rob(rob_deq_idx), io.push.bits.data) - - val rob_push_idx = if (simpleRob) io.push.bits.tag else rob_next - when (io.push.valid && !(deq_ptr.value === io.push.bits.tag && io.deq.ready)) { - when (rob_full) { - must_replay(io.push.bits.tag) := true.B - } .otherwise { - valids(io.push.bits.tag) := true.B - rob_idxs(io.push.bits.tag) := rob_next - rob_valids(rob_push_idx) := true.B - rob(rob_push_idx) := io.push.bits.data - } - } - - when (io.deq.fire) { - deq_ptr.inc() - valids(deq_ptr.value) := false.B - when (valids(deq_ptr.value) && !entries(deq_ptr.value).masked) { - rob_valids(rob_deq_idx) := false.B - } - } - - val replay_valid = must_replay.orR - val next_replay = AgePriorityEncoder(must_replay, deq_ptr.value) - io.replay_liq_id := entries(next_replay).lsiq_id - io.replay.valid := replay_valid - io.replay.bits.addr := entries(next_replay).page_offset - io.replay.bits.data := DontCare - io.replay.bits.mask := ~(0.U(dLenB.W)) - io.replay.bits.tag := next_replay - io.replay.bits.store := false.B - - when (io.replay.fire) { - must_replay(next_replay) := false.B - } - - when (io.reserve.fire =/= io.deq.fire) { - maybe_full := io.reserve.fire - } -} diff --git a/arch/src/main/scala/framework/gendomain/mem/LoadSegmenter.scala b/arch/src/main/scala/framework/gendomain/mem/LoadSegmenter.scala deleted file mode 100644 index e8927faa..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/LoadSegmenter.scala +++ /dev/null @@ -1,93 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class LoadSegmenter(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val valid = Input(Bool()) - val done = Output(Bool()) - val op = Input(new VectorMemMacroOp) - - val compactor = Decoupled(new CompactorReq(dLenB)) - val compactor_data = Input(UInt(dLen.W)) - - val resp = Decoupled(new Bundle { - val data = UInt(dLen.W) - val debug_id = UInt(debugIdSz.W) - }) - }) - - val segbuf = Module(new LoadSegmentBuffer(vParams.doubleBufferSegments)) - - val r_eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val r_head = RegInit(true.B) - val r_sidx = Reg(UInt(3.W)) - val eidx = Mux(r_head, io.op.vstart, r_eidx) - val sidx = Mux(r_head, io.op.segstart, r_sidx) - - val mem_size = io.op.elem_size - val incr = (dLenB.U - (Mux(io.op.seg_nf === 0.U, eidx, sidx) << mem_size)(dLenOffBits-1,0)) >> mem_size - val eidx_incr = Mux(io.op.seg_nf =/= 0.U, 1.U, incr) - val sidx_incr = incr - val next_eidx = eidx +& eidx_incr - val next_sidx = sidx +& sidx_incr - - val sidx_tail = next_sidx > io.op.seg_nf - val eidx_tail = next_eidx >= io.op.vl - - when (io.op.seg_nf === 0.U) { - io.compactor.valid := io.valid && !segbuf.io.busy && io.resp.ready - io.compactor.bits.head := eidx << mem_size - io.compactor.bits.tail := Mux(eidx_tail, io.op.vl << mem_size, 0.U) - } .otherwise { - io.compactor.valid := io.valid && segbuf.io.in.ready - io.compactor.bits.head := sidx << mem_size - io.compactor.bits.tail := Mux(sidx_tail, (io.op.nf +& 1.U) << mem_size, 0.U) - } - - segbuf.io.in.valid := io.valid && io.op.seg_nf =/= 0.U && io.compactor.ready - segbuf.io.in.bits.eew := mem_size - segbuf.io.in.bits.nf := io.op.nf - segbuf.io.in.bits.data := io.compactor_data - segbuf.io.in.bits.eidx := eidx - segbuf.io.in.bits.sidx := sidx - segbuf.io.in.bits.sidx_tail := sidx_tail - segbuf.io.in.bits.tail := eidx_tail - segbuf.io.in.bits.segstart := io.op.segstart - segbuf.io.in.bits.debug_id := io.op.debug_id - - segbuf.io.out.ready := io.resp.ready - - io.resp.valid := Mux(segbuf.io.busy, - segbuf.io.out.valid, - io.compactor.ready && io.valid && io.op.seg_nf === 0.U) - io.resp.bits.data := Mux(segbuf.io.busy, segbuf.io.out.bits.data, io.compactor_data) - io.resp.bits.debug_id := Mux(segbuf.io.busy, segbuf.io.out.bits.debug_id, io.op.debug_id) - - - val seg_ready = Mux(io.op.seg_nf === 0.U, - !segbuf.io.busy && io.compactor.ready && io.resp.ready, - segbuf.io.in.ready && io.compactor.ready && sidx_tail) - - when (segbuf.io.in.fire) { - - r_head := false.B - when (r_head) { r_eidx := io.op.vstart } - r_sidx := next_sidx - when (next_sidx > io.op.nf) { - r_sidx := 0.U - } - } - io.done := false.B - when (seg_ready && io.valid) { - r_head := eidx_tail - r_eidx := next_eidx - io.done := eidx_tail - } -} diff --git a/arch/src/main/scala/framework/gendomain/mem/Mem.scala b/arch/src/main/scala/framework/gendomain/mem/Mem.scala deleted file mode 100644 index f158598f..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/Mem.scala +++ /dev/null @@ -1,402 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class LSIQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val op = new VectorMemMacroOp - def bound_all = op.mop =/= mopUnit - val bound_offset = UInt(pgIdxBits.W) - val ld_dep_mask = Vec(vParams.vliqEntries, Bool()) - val st_dep_mask = Vec(vParams.vsiqEntries, Bool()) - - def containsBlock(addr: UInt) = { - val cl = addr(pgIdxBits-1,lgCacheBlockBytes) - val base_cl = op.base_offset >> lgCacheBlockBytes - val bound_cl = bound_offset >> lgCacheBlockBytes - (((addr >> pgIdxBits) === op.page) && (base_cl <= cl && bound_cl >= cl)) || bound_all - - } - def overlaps(other: LSIQEntry) = { - (op.page === other.op.page) && (bound_all || other.bound_all || ( - (op.base_offset <= other.bound_offset && bound_offset >= other.op.base_offset) - )) - } -} - -class IFQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val head = UInt(log2Ceil(dLenB).W) - val tail = UInt(log2Ceil(dLenB).W) - val masked = Bool() - val last = Bool() - val lsiq_id = UInt(lsiqIdBits.W) - val page_offset = UInt(pgIdxBits.W) -} - -class MemRequest(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) { - val addr = UInt(coreMaxAddrBits.W) - val data = UInt((bytes*8).W) - val mask = UInt(bytes.W) - val tag = UInt(tagBits.W) - val store = Bool() -} - -class MemResponse(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) { - val data = UInt((bytes*8).W) - val tag = UInt(tagBits.W) -} - -class ScalarMemOrderCheckIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val addr = Input(UInt(coreMaxAddrBits.W)) - val size = Input(UInt(2.W)) - val store = Input(Bool()) - val conflict = Output(Bool()) -} - -class VectorMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val load_req = Decoupled(new MemRequest(dLenB, dmemTagBits)) - val load_resp = Input(Valid(new MemResponse(dLenB, dmemTagBits))) - val store_req = Decoupled(new MemRequest(dLenB, dmemTagBits)) - val store_ack = Input(Valid(new MemResponse(dLenB, dmemTagBits))) -} - -class VectorSGMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val req = Vec(vParams.vsgPorts, Decoupled(new MemRequest(1, sgmemTagBits))) - val resp = Vec(vParams.vsgPorts, Input(Valid(new MemResponse(1, sgmemTagBits)))) -} - -class VectorMemDatapathIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { - val lresp = Decoupled(new Bundle { - val data = UInt(dLen.W) - val debug_id = UInt(debugIdSz.W) - }) - val sdata = Flipped(Decoupled(new StoreDataMicroOp)) - - val mask_pop = Decoupled(new CompactorReq(dLenB)) - val mask_data = Input(Vec(dLenB, Bool())) - val index_pop = Decoupled(new CompactorReq(dLenB)) - val index_data = Input(Vec(dLenB, UInt(8.W))) -} - -class VectorMemUnit(sgSize: Option[BigInt] = None)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val enq = Flipped(Decoupled(new VectorMemMacroOp)) - - val dmem = new VectorMemIO - val sgmem = sgSize.map(_ => new VectorSGMemIO) - val scalar_check = new ScalarMemOrderCheckIO - - val vu = new VectorMemDatapathIO - - val busy = Output(Bool()) - }) - - def ptrIncr(u: UInt, sz: Int): Unit = { - val n = u +& 1.U - u := Mux(n === sz.U, 0.U, n) - } - - val sgas = sgSize.map { size => Module(new ScatterGatherAddrGen(size)) } - - val las = Module(new AddrGen) - val lifq = Module(new LoadOrderBuffer(vParams.vlifqEntries, vParams.vlrobEntries)) - val lcu = Module(new Compactor(dLenB, dLenB, UInt(8.W), true)) - val lss = Module(new LoadSegmenter) - - val scu = Module(new Compactor(dLenB, dLenB, new MaskedByte, false)) - val sss = Module(new StoreSegmenter) - val sas = Module(new AddrGen) - val sifq = Module(new DCEQueue(new IFQEntry, vParams.vsifqEntries)) - - val liq = Reg(Vec(vParams.vliqEntries, new LSIQEntry)) - val liq_valids = RegInit(VecInit.fill(vParams.vliqEntries)(false.B)) - val liq_las = RegInit(VecInit.fill(vParams.vliqEntries)(false.B)) - val liq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W)) - val liq_las_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W)) - val liq_lss_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W)) - - val liq_enq_fire = Wire(Bool()) - val liq_las_fire = Wire(Bool()) - val liq_lss_fire = Wire(Bool()) - - val liq_enq_ready = !liq_valids(liq_enq_ptr) - val liq_las_valid = !liq_las(liq_las_ptr) && liq_valids(liq_las_ptr) - val liq_lss_valid = liq_valids(liq_lss_ptr) - - val siq = Reg(Vec(vParams.vsiqEntries, new LSIQEntry)) - val siq_valids = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B)) - val siq_sss = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B)) - val siq_sas = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B)) - val siq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) - val siq_sss_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) - val siq_sas_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) - val siq_deq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) - - val siq_enq_fire = Wire(Bool()) - val siq_sss_fire = Wire(Bool()) - val siq_sas_fire = Wire(Bool()) - val siq_deq_fire = Wire(Bool()) - - val siq_enq_ready = !siq_valids(siq_enq_ptr) - val siq_sss_valid = !siq_sss(siq_sss_ptr) && siq_valids(siq_sss_ptr) - val siq_sas_valid = !siq_sas(siq_sas_ptr) && siq_valids(siq_sas_ptr) - - val enq_bound_max = (((io.enq.bits.nf +& 1.U) * io.enq.bits.vl) << io.enq.bits.elem_size) + io.enq.bits.base_offset - 1.U - val enq_bound = Mux((enq_bound_max >> pgIdxBits) =/= 0.U, ~(0.U(pgIdxBits.W)), enq_bound_max) - - when (liq_enq_fire) { - liq(liq_enq_ptr).op := io.enq.bits - liq(liq_enq_ptr).bound_offset := enq_bound - liq(liq_enq_ptr).st_dep_mask := siq_valids - liq_las(liq_enq_ptr) := false.B - ptrIncr(liq_enq_ptr, vParams.vliqEntries) - liq_valids(liq_enq_ptr) := true.B - } - when (liq_las_fire) { - ptrIncr(liq_las_ptr, vParams.vliqEntries) - liq_las(liq_las_ptr) := true.B - } - when (liq_lss_fire) { - ptrIncr(liq_lss_ptr, vParams.vliqEntries) - liq_valids(liq_lss_ptr) := false.B - assert(liq_las(liq_lss_ptr) || (liq_lss_ptr === liq_las_ptr && liq_las_fire)) - } - - when (siq_enq_fire) { - siq(siq_enq_ptr).op := io.enq.bits - siq(siq_enq_ptr).bound_offset := enq_bound - siq(siq_enq_ptr).ld_dep_mask := liq_valids - siq_sss(siq_enq_ptr) := false.B - siq_sas(siq_enq_ptr) := false.B - ptrIncr(siq_enq_ptr, vParams.vsiqEntries) - siq_valids(siq_enq_ptr) := true.B - } - when (siq_sss_fire) { - ptrIncr(siq_sss_ptr, vParams.vsiqEntries) - siq_sss(siq_sss_ptr) := true.B - } - when (siq_sas_fire) { - ptrIncr(siq_sas_ptr, vParams.vsiqEntries) - siq_sas(siq_sas_ptr) := true.B - assert(siq_sss(siq_sas_ptr) || (siq_sss_fire && siq_sss_ptr === siq_sas_ptr)) - } - when (siq_deq_fire) { - ptrIncr(siq_deq_ptr, vParams.vsiqEntries) - siq_valids(siq_deq_ptr) := false.B - assert(siq_sas(siq_deq_ptr) || (siq_sas_fire && siq_sas_ptr === siq_deq_ptr)) - } - - io.enq.ready := Mux(io.enq.bits.store, siq_enq_ready, liq_enq_ready) - liq_enq_fire := io.enq.valid && liq_enq_ready && !io.enq.bits.store - siq_enq_fire := io.enq.valid && siq_enq_ready && io.enq.bits.store - - when (liq_lss_fire) { siq.foreach(_.ld_dep_mask(liq_lss_ptr) := false.B) } - when (siq_deq_fire) { liq.foreach(_.st_dep_mask(siq_deq_ptr) := false.B) } - - val scalar_store_conflict = (0 until vParams.vsiqEntries).map { i => - siq_valids(i) && (siq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B) - }.orR - val scalar_load_conflict = (0 until vParams.vliqEntries).map { i => - liq_valids(i) && (liq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B) - }.orR - io.scalar_check.conflict := scalar_store_conflict || (scalar_load_conflict && io.scalar_check.store) - - // Send indices/masks to las/sas - - val las_older_than_sas = (liq_las_valid && !liq(liq_las_ptr).st_dep_mask(siq_sas_ptr)) || !siq_sas_valid - val maskindex_load = liq_las_valid && las_older_than_sas && !liq(liq_las_ptr).op.fast_sg - val maskindex_store = siq_sas_valid && !las_older_than_sas && !siq(siq_sas_ptr).op.fast_sg - val maskindex_gather = liq_las_valid && las_older_than_sas && liq(liq_las_ptr).op.fast_sg - val maskindex_scatter = siq_sas_valid && !las_older_than_sas && siq(siq_sas_ptr).op.fast_sg - las.io.maskindex.index := io.vu.index_data.asUInt - sas.io.maskindex.index := io.vu.index_data.asUInt - las.io.maskindex.mask := io.vu.mask_data(0) - sas.io.maskindex.mask := io.vu.mask_data(0) - io.vu.mask_pop.valid := false.B - io.vu.mask_pop.bits.head := 0.U - io.vu.mask_pop.bits.tail := 1.U - io.vu.index_pop.valid := false.B - io.vu.index_pop.bits.head := 0.U - io.vu.index_pop.bits.tail := 1.U - - when (maskindex_load) { - io.vu.mask_pop.valid := las.io.maskindex.needs_mask && las.io.maskindex.ready - io.vu.index_pop.valid := las.io.maskindex.needs_index && las.io.maskindex.ready - io.vu.index_pop.bits.tail := 1.U << las.io.maskindex.eew - } - when (maskindex_store) { - io.vu.mask_pop.valid := sas.io.maskindex.needs_mask && sas.io.maskindex.ready - io.vu.index_pop.valid := sas.io.maskindex.needs_index && sas.io.maskindex.ready - io.vu.index_pop.bits.tail := 1.U << sas.io.maskindex.eew - } - - // scatter/gather paths - sgas.foreach { sgas => - sgas.io.index_pop.ready := false.B - sgas.io.mask_pop.ready := false.B - when (maskindex_gather || maskindex_scatter) { - io.vu.mask_pop <> sgas.io.mask_pop - io.vu.index_pop <> sgas.io.index_pop - } - sgas.io.index_data := io.vu.index_data - sgas.io.mask_data := io.vu.mask_data - sgas.io.valid := maskindex_gather || maskindex_scatter - sgas.io.lsiq_id := Mux(maskindex_gather, liq_las_ptr, siq_sas_ptr) - sgas.io.op := Mux(maskindex_gather, liq(liq_las_ptr).op, siq(siq_sas_ptr).op) - sgas.io.req <> io.sgmem.get.req - sgas.io.resp <> io.sgmem.get.resp - } - - las.io.maskindex.valid := maskindex_load && (io.vu.mask_pop.ready || !las.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !las.io.maskindex.needs_index) - sas.io.maskindex.valid := !maskindex_load && (io.vu.mask_pop.ready || !sas.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !sas.io.maskindex.needs_index) - - // Load Addr Sequencing - val las_order_block = (0 until vParams.vsiqEntries).map { i => - val addr_conflict = siq(i).overlaps(liq(liq_las_ptr)) - siq_valids(i) && addr_conflict && liq(liq_las_ptr).st_dep_mask(i) - }.orR - val dae_block = !vParams.enableDAE.B && (!io.vu.lresp.ready || - io.vu.lresp.bits.debug_id =/= liq(liq_las_ptr).op.debug_id) - las.io.valid := liq_las_valid && !las_order_block && !liq(liq_las_ptr).op.fast_sg && !dae_block - las.io.lsiq_id := liq_las_ptr - las.io.op := liq(liq_las_ptr).op - liq_las_fire := Mux(liq(liq_las_ptr).op.fast_sg, - sgas.map(_.io.done && maskindex_gather).getOrElse(false.B), las.io.done) - - las.io.tag <> lifq.io.reserve - las.io.out.ready := lifq.io.reserve.valid - lifq.io.entry := las.io.out.bits - - lifq.io.push.valid := io.dmem.load_resp.valid - lifq.io.push.bits.data := io.dmem.load_resp.bits.data - lifq.io.push.bits.tag := io.dmem.load_resp.bits.tag - - val load_arb = Module(new Arbiter(new MemRequest(dLenB, dmemTagBits), 2)) - load_arb.io.in(1) <> las.io.req - load_arb.io.in(1).bits.store := false.B - load_arb.io.in(0) <> lifq.io.replay - load_arb.io.in(0).bits.addr := Cat(liq(lifq.io.replay_liq_id).op.page, lifq.io.replay.bits.addr(pgIdxBits-1,0)) - when (io.dmem.store_req.valid) { - load_arb.io.in(0).valid := false.B - lifq.io.replay.ready := false.B - } - - // Load compacting - lcu.io.push.valid := lifq.io.deq.valid - lcu.io.push.bits.head := lifq.io.deq.bits.head - lcu.io.push.bits.tail := lifq.io.deq.bits.tail - lcu.io.push_data := lifq.io.deq_data.asTypeOf(Vec(dLenB, UInt(8.W))) - lifq.io.deq.ready := lcu.io.push.ready - - sgas.foreach { sgas => - sgas.io.load_resp.ready := false.B - when (maskindex_gather && !lifq.io.busy) { - sgas.io.load_resp.ready := lcu.io.push.ready - lcu.io.push.valid := sgas.io.load_resp.valid - lcu.io.push.bits := sgas.io.load_resp.bits - lcu.io.push_data := sgas.io.load_data - } - } - - // Load segment sequencing - lss.io.valid := liq_lss_valid - lss.io.op := liq(liq_lss_ptr).op - lcu.io.pop <> lss.io.compactor - lss.io.compactor_data := lcu.io.pop_data.asUInt - io.vu.lresp <> lss.io.resp - liq_lss_fire := lss.io.done - - // Store segment sequencing - sss.io.valid := siq_sss_valid - sss.io.op := siq(siq_sss_ptr).op - scu.io.push <> sss.io.compactor - scu.io.push_data := sss.io.compactor_data - sss.io.stdata <> io.vu.sdata - siq_sss_fire := sss.io.done - - // Store address sequencing - val sas_order_block = (0 until vParams.vliqEntries).map { i => - val addr_conflict = liq(i).overlaps(siq(siq_sas_ptr)) - liq_valids(i) && addr_conflict && siq(siq_sas_ptr).ld_dep_mask(i) - }.orR - sas.io.valid := siq_sas_valid && !sas_order_block && !siq(siq_sas_ptr).op.fast_sg - sas.io.lsiq_id := siq_sas_ptr - sas.io.op := siq(siq_sas_ptr).op - siq_sas_fire := Mux(siq(siq_sas_ptr).op.fast_sg, sgas.map(_.io.done && maskindex_scatter).getOrElse(false.B), sas.io.done) - - val store_req_q = Module(new DCEQueue(new MemRequest(dLenB, dmemTagBits), 2)) - store_req_q.io.enq <> sas.io.req - store_req_q.io.enq.bits.store := true.B - store_req_q.io.enq.bits.data := VecInit(scu.io.pop_data.map(_.data)).asUInt - store_req_q.io.enq.bits.mask := VecInit(scu.io.pop_data.map(_.mask)).asUInt & sas.io.req.bits.mask - - val store_rob = Module(new ReorderBuffer(Bool(), vParams.vsifqEntries)) - sas.io.tag <> store_rob.io.reserve - store_rob.io.reserve.ready := sas.io.tag.ready && sas.io.req.valid - - sas.io.out.ready := sifq.io.enq.ready && scu.io.pop.ready - sifq.io.enq.valid := sas.io.out.valid && scu.io.pop.ready - sifq.io.enq.bits := sas.io.out.bits - scu.io.pop.valid := sas.io.out.valid && sifq.io.enq.ready - when (scu.io.pop.fire) { - for (i <- 0 until dLenB) { - assert(scu.io.pop_data(i).debug_id === sas.io.op.debug_id || - i.U < scu.io.pop.bits.head || - (i.U >= scu.io.pop.bits.tail && scu.io.pop.bits.tail =/= 0.U)) - } - } - - scu.io.pop.bits.head := sas.io.out.bits.head - scu.io.pop.bits.tail := sas.io.out.bits.tail - - sgas.foreach { sgas => - sgas.io.store_pop.ready := false.B - sgas.io.store_data := scu.io.pop_data.map(_.data) - when (maskindex_scatter && !store_rob.io.busy) { - sgas.io.store_pop.ready := scu.io.pop.ready - scu.io.pop.valid := sgas.io.store_pop.valid - scu.io.pop.bits := sgas.io.store_pop.bits - } - } - - store_rob.io.push.valid := io.dmem.store_ack.valid - store_rob.io.push.bits.tag := io.dmem.store_ack.bits.tag - store_rob.io.push.bits.data := DontCare - - sifq.io.deq.ready := sifq.io.deq.bits.masked || store_rob.io.deq.valid - store_rob.io.deq.ready := !sifq.io.deq.bits.masked && sifq.io.deq.valid - when (store_rob.io.deq.valid) { assert(sifq.io.deq.valid) } - siq_deq_fire := sifq.io.deq.fire && sifq.io.deq.bits.last - - sgas.foreach { sgas => - when (maskindex_scatter && sgas.io.valid && sgas.io.done) { siq_deq_fire := true.B } - } - - if (vParams.latencyInject) { - val latency = Wire(UInt(32.W)) - latency := PlusArg("saturn_mem_latency") - val delay_timer = RegInit(0.U(64.W)) - delay_timer := delay_timer + 1.U - val load_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64)) - val store_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64)) - load_delay.io.timer := delay_timer - store_delay.io.timer := delay_timer - load_delay.io.delay := latency - store_delay.io.delay := latency - load_delay.io.enq <> load_arb.io.out - store_delay.io.enq <> store_req_q.io.deq - io.dmem.load_req <> load_delay.io.deq - io.dmem.store_req <> store_delay.io.deq - } else { - io.dmem.load_req <> load_arb.io.out - io.dmem.store_req <> store_req_q.io.deq - } - io.dmem.load_req.bits.mask := ~(0.U(dLenB.W)) - - io.busy := liq_valids.orR || siq_valids.orR -} diff --git a/arch/src/main/scala/framework/gendomain/mem/SGAddrGen.scala b/arch/src/main/scala/framework/gendomain/mem/SGAddrGen.scala deleted file mode 100644 index ee19338b..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/SGAddrGen.scala +++ /dev/null @@ -1,140 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - - -class ScatterGatherAddrGen(sgSize: BigInt)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val sgPorts = vParams.vsgPorts - assert(sgPorts <= dLenB && sgPorts >= 8) - val io = IO(new Bundle { - val valid = Input(Bool()) - val lsiq_id = Input(UInt(lsiqIdBits.W)) - val done = Output(Bool()) - val op = Input(new VectorMemMacroOp) - val index_pop = Decoupled(new CompactorReq(dLenB)) - val index_data = Input(Vec(dLenB, UInt(8.W))) - val mask_pop = Decoupled(new CompactorReq(dLenB)) - val mask_data = Input(Vec(dLenB, Bool())) - val store_pop = Decoupled(new CompactorReq(dLenB)) - val store_data = Input(Vec(dLenB, UInt(8.W))) - - val req = Vec(sgPorts, Decoupled(new MemRequest(1, sgmemTagBits))) - val resp = Vec(sgPorts, Input(Valid(new MemResponse(1, sgmemTagBits)))) - - val load_resp = Decoupled(new CompactorReq(dLenB)) - val load_data = Output(Vec(dLenB, UInt(8.W))) - }) - val vsgifqEntries = vParams.vsgifqEntries - - def min(a: UInt, b: UInt) = Mux(a > b, b, a) - - val resp_buffer = Reg(Vec(vsgifqEntries, Vec(sgPorts, UInt(8.W)))) - val resp_busys = Reg(Vec(vsgifqEntries, Vec(sgPorts, Bool()))) - val resp_bytes = Reg(Vec(vsgifqEntries, UInt(log2Ceil(dLenB).W))) - val resp_valids = RegInit(VecInit.fill(vsgifqEntries)(false.B)) - val fired = RegInit(VecInit.fill(sgPorts)(false.B)) - - val r_eidx = Reg(UInt((1 + log2Ceil(8*maxVLMax)).W)) - val r_enq = RegInit(0.U(log2Ceil(vsgifqEntries).W)) - val r_deq = RegInit(0.U(log2Ceil(vsgifqEntries).W)) - val r_head = RegInit(true.B) - val r_done = RegInit(false.B) - - val eidx = Mux(r_head, io.op.vstart, r_eidx) - val idx_incr = dLenB.U >> io.op.idx_size - val elem_incr = sgPorts.U >> io.op.elem_size - val incr = min(idx_incr, elem_incr) - val next_act_elems = min(incr, io.op.vl - eidx) - val next_eidx = eidx +& incr - val next_row = Mux(r_enq +& 1.U === vsgifqEntries.U, 0.U, r_enq + 1.U) - val store = io.op.store - - val enq_stall = resp_valids(r_enq) - val port_stalls = Wire(Vec(sgPorts, Bool())) - val fire = io.valid && !port_stalls.orR && !enq_stall && io.index_pop.ready && (io.mask_pop.ready || io.op.vm) && !r_done && (io.store_pop.ready || !store) - - - val base = Cat(io.op.page, io.op.base_offset) - val addrs: Seq[Vec[UInt]] = (0 until 4).map { sew => - val offsets = io.index_data.asTypeOf(Vec(dLenB >> sew, UInt((8 << sew).W))) - VecInit(offsets.map(o => Cat(base >> log2Ceil(sgSize), (o +& base)(log2Ceil(sgSize)-1,0)))) - } - - - for (i <- 0 until sgPorts) { - val port_eidx_offset = (i.U >> io.op.elem_size) - val port_byte_offset = i.U & ((1.U << io.op.elem_size) - 1.U) - val port_eidx = eidx +& port_eidx_offset - val port_masked = !io.op.vm && !io.mask_data(port_eidx_offset) - val port_addr = VecInit((0 until 4).map { sew => addrs(sew)(port_eidx_offset) })(io.op.idx_size) - - val port_active = io.valid && !r_done && port_eidx < io.op.vl && !port_masked && !fired(i) - port_stalls(i) := port_active && !io.req(i).ready - - io.req(i).valid := port_active && !enq_stall && io.index_pop.ready && (io.mask_pop.ready || io.op.vm) && (io.store_pop.ready || !store) - io.req(i).bits.mask := true.B - io.req(i).bits.data := io.store_data(i) - io.req(i).bits.tag := r_enq - io.req(i).bits.addr := port_addr | port_byte_offset // this is broken if the addrs are misaligned - io.req(i).bits.store := io.op.store - - - when (io.req(i).fire) { - resp_busys(r_enq)(i) := true.B - fired(i) := true.B - } - } - - when (fire) { - r_head := false.B - r_eidx := next_eidx - r_enq := next_row - resp_valids(r_enq) := true.B - resp_bytes(r_enq) := next_act_elems << io.op.elem_size - fired := VecInit.fill(sgPorts)(false.B) - when (next_eidx >= io.op.vl) { - r_done := true.B - } - } - - io.index_pop.valid := io.valid && !r_done && !enq_stall && (io.mask_pop.ready || io.op.vm) && !port_stalls.orR && (io.store_pop.ready || !store) - io.index_pop.bits.head := 0.U - io.index_pop.bits.tail := next_act_elems << io.op.idx_size - - io.mask_pop.valid := io.valid && !r_done && !io.op.vm && io.index_pop.ready && !enq_stall && !port_stalls.orR && (io.store_pop.ready || !store) - io.mask_pop.bits.head := 0.U - io.mask_pop.bits.tail := next_act_elems - - io.store_pop.valid := io.valid && !r_done && (io.mask_pop.ready || io.op.vm) && io.index_pop.ready && !enq_stall && !port_stalls.orR - io.store_pop.bits.head := 0.U - io.store_pop.bits.tail := next_act_elems << io.op.elem_size - - for (i <- 0 until sgPorts) { - when (io.resp(i).valid) { - assert(resp_busys(io.resp(i).bits.tag)(i)) - resp_busys(io.resp(i).bits.tag)(i) := false.B - resp_buffer(io.resp(i).bits.tag)(i) := io.resp(i).bits.data - } - } - - val resp_fire = io.valid && resp_valids(r_deq) && !resp_busys(r_deq).orR && (store || io.load_resp.ready) - io.load_resp.valid := io.valid && resp_valids(r_deq) && !resp_busys(r_deq).orR && !store - io.load_resp.bits.head := 0.U - io.load_resp.bits.tail := Mux(resp_bytes(r_deq) === 0.U, sgSize.U, resp_bytes(r_deq)) - io.load_data := resp_buffer(r_deq).asUInt.asTypeOf(Vec(dLenB, UInt(8.W))) - - when (resp_fire) { - r_deq := Mux(r_deq === (sgSize-1).U, 0.U, r_deq + 1.U) - resp_valids(r_deq) := false.B - } - - io.done := r_done && resp_fire && (resp_valids.asUInt === UIntToOH(r_deq)) - when (io.done) { r_head := true.B; r_done := false.B } - -} diff --git a/arch/src/main/scala/framework/gendomain/mem/SGTLInterface.scala b/arch/src/main/scala/framework/gendomain/mem/SGTLInterface.scala deleted file mode 100644 index e4a256a8..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/SGTLInterface.scala +++ /dev/null @@ -1,38 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ - -class SGTLInterface(implicit p: Parameters) extends LazyModule()(p) with HasCoreParameters with HasVectorParams { - - require(vParams.vsgBuffers >= 2) - val accessors = Seq.tabulate(vParams.vsgPorts) { i => LazyModule(new TLInterface(sgmemTagBits)) } - val identityNode = TLEphemeralNode() - accessors.foreach { a => identityNode := TLBuffer(BufferParams(vParams.vsgBuffers), BufferParams.none) := a.node } - - def node = TLWidthWidget(1) :=* identityNode - - override lazy val module = new Impl - class Impl extends LazyModuleImp(this) { - val io = IO(new Bundle { - val vec = Flipped(new VectorSGMemIO) - val mem_busy = Output(Bool()) - }) - - io.vec.base := DontCare // this should be set outside - io.mem_busy := false.B - for (i <- 0 until vParams.vsgPorts) { - accessors(i).module.io.req <> io.vec.req(i) - accessors(i).module.io.resp <> io.vec.resp(i) - } - io.mem_busy := accessors.map(_.module.io.busy).orR - } -} diff --git a/arch/src/main/scala/framework/gendomain/mem/SegmentBuffer.scala b/arch/src/main/scala/framework/gendomain/mem/SegmentBuffer.scala deleted file mode 100644 index 59c8c102..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/SegmentBuffer.scala +++ /dev/null @@ -1,235 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class LoadSegmentBuffer(doubleBuffer: Boolean)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val in = Flipped(Decoupled(new Bundle { - val data = UInt(dLen.W) - val eew = UInt(2.W) - val nf = UInt(3.W) - val eidx = UInt(log2Ceil(maxVLMax).W) - val segstart = UInt(3.W) - val sidx = UInt(3.W) - val sidx_tail = Bool() - val tail = Bool() - val debug_id = UInt(debugIdSz.W) - })) - val out = Decoupled(new Bundle { - val data = UInt(dLen.W) - val debug_id = UInt(debugIdSz.W) - }) - val busy = Output(Bool()) - }) - - val nB = if (doubleBuffer) 2 else 1 - - val rows = 8 - val cols = dLenB - - val wdata = Wire(Vec(4, UInt((rows*8*8).W))) - val warr = wdata(io.in.bits.eew).asTypeOf(Vec(rows, Vec(8, UInt(8.W)))) - val wrow = WireInit(0.U(rows.W)) - val wcol = WireInit(0.U(cols.W)) - val wmode = Wire(Bool()) - val array = Seq.tabulate(rows, cols, nB) { case (_,_,_) => Reg(UInt(8.W)) } - - for (r <- 0 until 8) { - for (c <- 0 until cols) { - for (s <- 0 until nB) { - when (wrow(r) && wcol(c) && wmode === s.U) { - array(r)(c)(s) := warr(r)(c % 8) - } - } - } - } - - val modes = RegInit(VecInit.fill(nB)(false.B)) - val in_sel = RegInit(false.B) - val out_sel = RegInit(false.B) - val out_nf = Reg(Vec(nB, UInt(3.W))) - val out_row = Reg(Vec(nB, UInt(3.W))) - val out_id = Reg(Vec(nB, UInt(debugIdSz.W))) - - io.in.ready := !modes(in_sel) - io.out.valid := modes(out_sel) - io.out.bits.data := Mux1H(UIntToOH(out_row(out_sel)), array.map(row => VecInit(row.map(_(out_sel))).asUInt)) - io.out.bits.debug_id := out_id(out_sel) - - when (io.in.fire) { - wrow := ((1.U << (dLenB.U >> io.in.bits.eew)) - 1.U)(7,0) << io.in.bits.sidx - } - wcol := ((1.U << (1.U << io.in.bits.eew)) - 1.U)(7,0) << (io.in.bits.eidx(log2Ceil(dLenB)-1,0) << io.in.bits.eew)(log2Ceil(dLenB)-1,0) - wmode := in_sel - - for (eew <- 0 until 4) { - val in_rows = 8 min (dLenB >> eew) - val in_cols = 8 >> eew - val in_elems = dLenB >> eew - - val col = Wire(Vec(in_rows, UInt((8 << eew).W))) - val arr = Wire(Vec(in_rows, Vec(in_cols, UInt((8 << eew).W)))) - - col := io.in.bits.data.asTypeOf(Vec(in_rows, UInt((8 << eew).W))) - for (r <- 0 until in_rows) { - for (c <- 0 until in_cols) { - arr(r)(c) := col(r) - } - } - - wdata(eew) := Fill(8 / in_rows, arr.asUInt) - } - - when (io.in.fire && io.in.bits.sidx_tail && (wcol(cols-1) || io.in.bits.tail)) { - in_sel := (if (doubleBuffer) (!in_sel) else false.B) - modes(in_sel) := true.B - out_nf(in_sel) := io.in.bits.nf - out_row(in_sel) := io.in.bits.segstart - out_id(in_sel) := io.in.bits.debug_id - } - - when (io.out.fire) { - when (out_row(out_sel) === out_nf(out_sel)) { - out_sel := (if (doubleBuffer) (!out_sel) else false.B) - modes(out_sel) := false.B - } .otherwise { - out_row(out_sel) := out_row(out_sel) + 1.U - } - } - - io.busy := modes.orR -} - -class StoreSegmentBuffer(doubleBuffer: Boolean)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - - val io = IO(new Bundle { - val in = Flipped(Decoupled(new Bundle { - val data = UInt(dLen.W) - val mask = UInt(dLenB.W) - val debug_id = UInt(debugIdSz.W) - val eew = UInt(2.W) - val nf = UInt(3.W) - val rows = UInt(4.W) - val sidx = UInt(3.W) - val segstart = UInt(3.W) - val segend = UInt(3.W) - })) - - val out = Decoupled(new Bundle { - val data = new StoreDataMicroOp - val head = UInt(log2Ceil(dLenB).W) - val tail = UInt(log2Ceil(dLenB).W) - }) - val busy = Output(Bool()) - }) - - val nB = if (doubleBuffer) 2 else 1 - val rows = 8 - val cols = dLenB - - val wdata = Wire(Vec(4, UInt((rows*8*8).W))) - val warr = wdata(io.in.bits.eew).asTypeOf(Vec(rows, Vec(8, UInt(8.W)))) - val wrow = WireInit(0.U(rows.W)) - val wcol = WireInit(0.U(cols.W)) - val wmode = Wire(Bool()) - val array = Seq.tabulate(rows, cols, nB) { case (_,_,_) => Reg(UInt(8.W)) } - val mask = Seq.fill(nB) { Reg(UInt(dLenB.W)) } - - for (r <- 0 until 8) { - for (c <- 0 until cols) { - for (s <- 0 until nB) { - when (wrow(r) && wcol(c) && wmode === s.U) { - array(r)(c)(s) := warr(r)(c % 8) - } - } - } - } - val modes = RegInit(VecInit.fill(nB)(false.B)) - val in_sel = RegInit(false.B) - val out_sidx = Reg(Vec(nB, UInt(3.W))) - val out_row = RegInit(0.U(3.W)) - val out_sel = RegInit(false.B) - val out_nf = Reg(Vec(nB, UInt(3.W))) - val out_eew = Reg(Vec(nB, UInt(2.W))) - val out_rows = Reg(Vec(nB, UInt(4.W))) - val out_segstart = Reg(Vec(nB, UInt(3.W))) - val out_id = Reg(Vec(nB, UInt(debugIdSz.W))) - - - def sidxOff(sidx: UInt, eew: UInt) = sidx & ~((1.U << (log2Ceil(cols).U - eew)) - 1.U) - - io.in.ready := !modes(in_sel) - io.out.valid := modes(out_sel) - val row_sel = out_row + sidxOff(out_sidx(out_sel), out_eew(out_sel)) - io.out.bits.data.tail := DontCare - io.out.bits.data.vat := DontCare - io.out.bits.data.stdata := Mux1H(UIntToOH(row_sel), array.map(row => VecInit(row.map(_(out_sel))).asUInt)) - io.out.bits.data.stmask := Fill(dLenB, (Mux1H(UIntToOH(out_sel), mask) >> (out_row << out_eew(out_sel)))(0)) - io.out.bits.data.debug_id := out_id(out_sel) - io.out.bits.head := out_sidx(out_sel) << out_eew(out_sel) - val remaining_bytes = (out_nf(out_sel) +& 1.U - out_sidx(out_sel)) << out_eew(out_sel) - io.out.bits.tail := Mux((remaining_bytes +& io.out.bits.head) >= dLenB.U, dLenB.U, remaining_bytes + io.out.bits.head) - - when (io.in.fire) { - wrow := ((1.U << (1.U << (log2Ceil(cols).U - io.in.bits.eew))) - 1.U)(7,0) << sidxOff(io.in.bits.sidx, io.in.bits.eew) - for (s <- 0 until nB) { - when (wmode === s.U && io.in.bits.sidx === 0.U) { - mask(s) := io.in.bits.mask - } - } - } - wcol := ((1.U << (1.U << io.in.bits.eew)) - 1.U)(7,0) << (io.in.bits.sidx << io.in.bits.eew)(log2Ceil(cols)-1,0) - - wmode := in_sel - - for (eew <- 0 until 4) { - val in_rows = 8 min (dLenB >> eew) - val in_cols = 8 >> eew - val in_elems = cols >> eew - - val col = Wire(Vec(in_rows, UInt((8 << eew).W))) - val arr = Wire(Vec(in_rows, Vec(in_cols, UInt((8 << eew).W)))) - - col := io.in.bits.data.asTypeOf(Vec(in_rows, UInt((8 << eew).W))) - - for (r <- 0 until in_rows) { - for (c <- 0 until in_cols) { - arr(r)(c) := col(r) - } - } - wdata(eew) := Fill(8 / in_rows, arr.asUInt) - } - - when (io.in.fire && io.in.bits.sidx === io.in.bits.nf) { - in_sel := (if (doubleBuffer) (!in_sel) else false.B) - modes(in_sel) := true.B - out_sidx(in_sel) := io.in.bits.segstart - out_nf(in_sel) := io.in.bits.segend - out_eew(in_sel) := io.in.bits.eew - out_rows(in_sel) := io.in.bits.rows - out_segstart(in_sel) := io.in.bits.segstart - out_id(in_sel) := io.in.bits.debug_id - } - - when (io.out.fire) { - val sidx_tail = ((out_sidx(out_sel) +& (cols.U >> out_eew(out_sel))) > out_nf(out_sel)) - when ((out_row +& 1.U === out_rows(out_sel)) && sidx_tail) { - out_sel := (if (doubleBuffer) (!out_sel) else false.B) - out_row := 0.U - modes(out_sel) := false.B - } .elsewhen (sidx_tail) { - out_sidx(out_sel) := out_segstart(out_sel) - out_row := out_row + 1.U - } .otherwise { - out_sidx(out_sel) := out_sidx(out_sel) + (cols.U >> out_eew(out_sel)) - } - } - - io.busy := modes.orR -} diff --git a/arch/src/main/scala/framework/gendomain/mem/StoreSegmenter.scala b/arch/src/main/scala/framework/gendomain/mem/StoreSegmenter.scala deleted file mode 100644 index f0c4dcec..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/StoreSegmenter.scala +++ /dev/null @@ -1,85 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import framework.gendomain.common._ - -class StoreSegmenter(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val valid = Input(Bool()) - val done = Output(Bool()) - val op = Input(new VectorMemMacroOp) - - val compactor = Decoupled(new CompactorReq(dLenB)) - val compactor_data = Output(Vec(dLenB, new MaskedByte)) - val stdata = Flipped(Decoupled(new StoreDataMicroOp)) - }) - - val segbuf = Module(new StoreSegmentBuffer(vParams.doubleBufferSegments)) - - val r_eidx = Reg(UInt(log2Ceil(maxVLMax).W)) - val r_head = RegInit(true.B) - val r_sidx = Reg(UInt(3.W)) - val eidx = Mux(r_head, io.op.vstart, r_eidx) - val sidx = Mux(r_head, 0.U, r_sidx) - - val mem_size = io.op.elem_size - val sub_dlen = Mux(io.op.seg_nf =/= 0.U && (log2Ceil(dLenB).U > (3.U +& mem_size)), - log2Ceil(dLenB).U - 3.U - mem_size, - 0.U) - val eidx_incr = (dLenB.U - ((eidx << (mem_size +& sub_dlen))(dLenOffBits-1,0))) >> (mem_size +& sub_dlen) - val next_eidx = eidx +& eidx_incr - val next_sidx = sidx +& 1.U - - val sidx_tail = next_sidx > io.op.seg_nf - val eidx_tail = next_eidx >= io.op.vl - - when (io.valid && io.stdata.valid) { - assert(io.stdata.bits.debug_id === io.op.debug_id) - } - - io.stdata.ready := io.valid && Mux(io.op.seg_nf === 0.U, - !segbuf.io.busy && io.compactor.ready, - segbuf.io.in.ready) - - segbuf.io.in.valid := io.valid && io.op.seg_nf =/= 0.U && io.stdata.valid - segbuf.io.in.bits.data := io.stdata.bits.stdata >> ((eidx << mem_size)(dLenOffBits-1,0) << 3) - segbuf.io.in.bits.mask := io.stdata.bits.stmask >> (eidx << mem_size)(dLenOffBits-1,0) - segbuf.io.in.bits.eew := mem_size - segbuf.io.in.bits.nf := io.op.nf - segbuf.io.in.bits.rows := Mux(next_eidx >= io.op.vl, (io.op.vl - eidx), eidx_incr) - segbuf.io.in.bits.sidx := sidx - segbuf.io.in.bits.segstart := io.op.segstart - segbuf.io.in.bits.segend := io.op.seg_nf - segbuf.io.in.bits.debug_id := io.op.debug_id - - io.compactor.valid := Mux(segbuf.io.busy, - segbuf.io.out.valid, - io.stdata.valid && io.valid && io.op.seg_nf === 0.U) - io.compactor_data := Mux(segbuf.io.busy, - segbuf.io.out.bits.data, io.stdata.bits).asMaskedBytes - io.compactor.bits.head := Mux(segbuf.io.busy, - segbuf.io.out.bits.head, eidx << mem_size) - io.compactor.bits.tail := Mux(segbuf.io.busy, - segbuf.io.out.bits.tail, Mux(eidx_tail, io.op.vl << mem_size, 0.U)) - - segbuf.io.out.ready := io.compactor.ready - - io.done := false.B - when (io.stdata.fire) { - r_head := false.B - when (io.op.seg_nf =/= 0.U && !sidx_tail) { - when (r_head) { r_eidx := io.op.vstart } - r_sidx := next_sidx - } .otherwise { - r_eidx := next_eidx - r_sidx := 0.U - io.done := eidx_tail - r_head := eidx_tail - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/mem/TLInterface.scala b/arch/src/main/scala/framework/gendomain/mem/TLInterface.scala deleted file mode 100644 index 6fbe113b..00000000 --- a/arch/src/main/scala/framework/gendomain/mem/TLInterface.scala +++ /dev/null @@ -1,87 +0,0 @@ -package framework.gendomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ - -class TLInterface(tagBits: Int)(implicit p: Parameters) extends LazyModule()(p) with HasCoreParameters { - val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = s"Core ${tileId} Vector Load", - sourceId = IdRange(0, 1 << tagBits) - ))))) - override lazy val module = new Impl - class Impl extends LazyModuleImp(this) { - - val (out, edge) = node.out(0) - - val widthBytes = edge.slave.beatBytes - val offBits = log2Ceil(widthBytes) - - val io = IO(new Bundle { - val busy = Output(Bool()) - val req = Flipped(Decoupled(new MemRequest(widthBytes, tagBits))) - val resp = Valid(new MemResponse(widthBytes, tagBits)) - }) - - val inflights = RegInit(0.U(tagBits.W)) - when (out.a.fire || out.d.fire) { - inflights := inflights + out.a.fire - out.d.fire - } - io.busy := inflights =/= 0.U - - io.req.ready := out.a.ready - out.a.valid := io.req.valid - out.a.bits := Mux(io.req.bits.store, - edge.Put( - io.req.bits.tag, - (io.req.bits.addr >> offBits) << offBits, - log2Ceil(widthBytes).U, - io.req.bits.data, - io.req.bits.mask)._2, - edge.Get( - io.req.bits.tag, - (io.req.bits.addr >> offBits) << offBits, - log2Ceil(widthBytes).U)._2 - ) - - out.d.ready := true.B - io.resp.valid := out.d.valid - io.resp.bits.data := out.d.bits.data - io.resp.bits.tag := out.d.bits.source - } -} - - -class TLSplitInterface(implicit p: Parameters) extends LazyModule()(p) with HasCoreParameters with HasVectorParams { - - val reader = LazyModule(new TLInterface(dmemTagBits)) - val writer = LazyModule(new TLInterface(dmemTagBits)) - - val arb = LazyModule(new TLXbar) - def node = TLWidthWidget(dLenB) := arb.node - def edge = arb.node.edges.out(0) - - arb.node := reader.node - arb.node := writer.node - - override lazy val module = new Impl - class Impl extends LazyModuleImp(this) { - val io = IO(new Bundle { - val vec = Flipped(new VectorMemIO) - val mem_busy = Output(Bool()) - }) - - reader.module.io.req <> io.vec.load_req - io.vec.load_resp <> reader.module.io.resp - writer.module.io.req <> io.vec.store_req - io.vec.store_ack <> writer.module.io.resp - io.mem_busy := reader.module.io.busy || writer.module.io.busy - } -} diff --git a/arch/src/main/scala/framework/gendomain/rocket/Configs.scala b/arch/src/main/scala/framework/gendomain/rocket/Configs.scala deleted file mode 100644 index 3bf06704..00000000 --- a/arch/src/main/scala/framework/gendomain/rocket/Configs.scala +++ /dev/null @@ -1,83 +0,0 @@ -package framework.gendomain.rocket - -import chisel3._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.diplomacy._ -import framework.gendomain.common._ -import framework.gendomain.frontend.{EarlyVectorDecode} - -class WithRocketVectorUnit( - vLen: Int = 128, - dLen: Int = 64, - params: VectorParams = VectorParams(), - cores: Option[Seq[Int]] = None, - useL1DCache: Boolean = true) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: RocketTileAttachParams => { - val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) - if (buildVector) tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy( - vector = Some(RocketCoreVectorParams( - build = ((p: Parameters) => new SaturnRocketUnit()(p.alterPartial { - case VectorParamsKey => params.copy(dLen=dLen) - })), - vLen = vLen, - vfLen = 64, - vfh = true, - eLen = 64, - vMemDataBits = if (useL1DCache) dLen else 0, - decoder = ((p: Parameters) => { - val decoder = Module(new EarlyVectorDecode(params.supported_ex_insns)(p)) - decoder - }), - useDCache = true, - issueVConfig = false, - vExts = Seq("zvbb") - )), - fpu = (if (params.useScalarFPFMA || params.useScalarFPMisc) { tp.tileParams.core.fpu.map(_.copy( - sfmaLatency = params.fmaPipeDepth - 1, - dfmaLatency = params.fmaPipeDepth - 1, - ifpuLatency = params.fmaPipeDepth - 1, - fpmuLatency = params.fmaPipeDepth - 1, - )) } else { tp.tileParams.core.fpu }).map(_.copy(minFLen = 16)) - ), - dcache = if (useL1DCache) tp.tileParams.dcache.map(_.copy(rowBits = dLen)) else tp.tileParams.dcache - )) else tp - } - case tp: framework.rocket.RocketTileAttachParamsBB => { - val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) - if (buildVector) tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy( - vector = Some(RocketCoreVectorParams( - build = ((p: Parameters) => new SaturnRocketUnit()(p.alterPartial { - case VectorParamsKey => params.copy(dLen=dLen) - })), - vLen = vLen, - vfLen = 64, - vfh = true, - eLen = 64, - vMemDataBits = if (useL1DCache) dLen else 0, - decoder = ((p: Parameters) => { - val decoder = Module(new EarlyVectorDecode(params.supported_ex_insns)(p)) - decoder - }), - useDCache = true, - issueVConfig = false, - vExts = Seq("zvbb") - )), - fpu = (if (params.useScalarFPFMA || params.useScalarFPMisc) { tp.tileParams.core.fpu.map(_.copy( - sfmaLatency = params.fmaPipeDepth - 1, - dfmaLatency = params.fmaPipeDepth - 1, - ifpuLatency = params.fmaPipeDepth - 1, - fpmuLatency = params.fmaPipeDepth - 1, - )) } else { tp.tileParams.core.fpu }).map(_.copy(minFLen = 16)) - ), - dcache = if (useL1DCache) tp.tileParams.dcache.map(_.copy(rowBits = dLen)) else tp.tileParams.dcache - )) else tp - } - case other => other - } -}) diff --git a/arch/src/main/scala/framework/gendomain/rocket/Frontend.scala b/arch/src/main/scala/framework/gendomain/rocket/Frontend.scala deleted file mode 100644 index 5ad6c1f3..00000000 --- a/arch/src/main/scala/framework/gendomain/rocket/Frontend.scala +++ /dev/null @@ -1,94 +0,0 @@ -package framework.gendomain.rocket - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ -import framework.gendomain.backend.{VectorBackend} -import framework.gendomain.mem.{ScalarMemOrderCheckIO, TLSplitInterface} -import framework.gendomain.frontend.{EarlyTrapCheck, IterativeTrapCheck} - -class SaturnRocketFrontend(edge: TLEdge)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val core = new VectorCoreIO - val tlb = Flipped(new DCacheTLBPort) - - val issue = Decoupled(new VectorIssueInst) - - val index_access = Flipped(new VectorIndexAccessIO) - val mask_access = Flipped(new VectorMaskAccessIO) - - val scalar_check = Flipped(new ScalarMemOrderCheckIO) - }) - - val ptc = Module(new EarlyTrapCheck(edge, None)) - val itc = Module(new IterativeTrapCheck) - - ptc.io.sg_base := DontCare - ptc.io.s0.in.valid := io.core.ex.valid && !itc.io.busy - ptc.io.s0.in.bits.inst := io.core.ex.inst - ptc.io.s0.in.bits.pc := io.core.ex.pc - ptc.io.s0.in.bits.status := io.core.status - ptc.io.s0.in.bits.vconfig := io.core.ex.vconfig - ptc.io.s0.in.bits.vstart := io.core.ex.vstart - ptc.io.s0.in.bits.rs1 := io.core.ex.rs1 - ptc.io.s0.in.bits.rs2 := io.core.ex.rs2 - ptc.io.s0.in.bits.phys := false.B - io.core.ex.ready := !itc.io.busy - - ptc.io.s1.rs1.valid := ptc.io.s1.inst.isOpf && !ptc.io.s1.inst.vmu - ptc.io.s1.rs1.bits := io.core.mem.frs1 - ptc.io.s1.kill := io.core.killm - io.core.mem.block_all := itc.io.busy || ptc.io.s2.internal_replay.valid - io.core.mem.block_mem := (ptc.io.s2.inst.valid && ptc.io.s2.inst.bits.vmu) || io.scalar_check.conflict - - io.tlb.req.valid := Mux(itc.io.busy, itc.io.s0_tlb_req.valid, ptc.io.s0.tlb_req.valid) - io.tlb.req.bits := Mux(itc.io.busy, itc.io.s0_tlb_req.bits , ptc.io.s0.tlb_req.bits) - ptc.io.s1.tlb_resp := io.tlb.s1_resp - when (RegEnable(itc.io.busy || !io.tlb.req.ready, ptc.io.s0.tlb_req.valid)) { ptc.io.s1.tlb_resp.miss := true.B } - itc.io.tlb_resp := io.tlb.s1_resp - when (RegEnable(!io.tlb.req.ready, itc.io.s0_tlb_req.valid)) { itc.io.tlb_resp.miss := true.B } - io.tlb.s2_kill := false.B - - ptc.io.s2.scalar_store_pending := io.core.wb.store_pending - - io.core.wb.replay := ptc.io.s2.replay - io.core.wb.xcpt := Mux(itc.io.busy, itc.io.xcpt.valid , ptc.io.s2.xcpt.valid) - io.core.wb.cause := Mux(itc.io.busy, itc.io.xcpt.bits.cause, ptc.io.s2.xcpt.bits.cause) - io.core.wb.pc := Mux(itc.io.busy, itc.io.pc , ptc.io.s2.pc) - io.core.wb.retire := Mux(itc.io.busy, itc.io.retire , ptc.io.s2.retire) - io.core.wb.inst := Mux(itc.io.busy, itc.io.inst.bits , ptc.io.s2.inst.bits.bits) - io.core.wb.tval := Mux(itc.io.busy, itc.io.xcpt.bits.tval , ptc.io.s2.xcpt.bits.tval) - io.core.wb.rob_should_wb := Mux(itc.io.busy, itc.io.inst.writes_xrf, ptc.io.s2.inst.bits.writes_xrf) - io.core.wb.rob_should_wb_fp := Mux(itc.io.busy, itc.io.inst.writes_frf, ptc.io.s2.inst.bits.writes_frf) - io.core.set_vstart := Mux(itc.io.busy, itc.io.vstart , ptc.io.s2.vstart) - io.core.set_vconfig := itc.io.vconfig - ptc.io.s2.vxrm := io.core.wb.vxrm - ptc.io.s2.frm := io.core.wb.frm - itc.io.in := ptc.io.s2.internal_replay - - io.issue.valid := Mux(itc.io.busy, itc.io.issue.valid, ptc.io.s2.issue.valid) - io.issue.bits := Mux(itc.io.busy, itc.io.issue.bits , ptc.io.s2.issue.bits) - itc.io.issue.ready := io.issue.ready - ptc.io.s2.issue.ready := !itc.io.busy && io.issue.ready - - io.core.trap_check_busy := ptc.io.busy || itc.io.busy - - itc.io.status := io.core.status - itc.io.index_access <> io.index_access - itc.io.mask_access <> io.mask_access - io.scalar_check.addr := io.tlb.s1_resp.paddr - io.scalar_check.size := io.tlb.s1_resp.size - io.scalar_check.store := isWrite(io.tlb.s1_resp.cmd) - - io.core.backend_busy := false.B // set externally - io.core.set_vxsat := false.B // set externally - io.core.set_fflags := DontCare // set externally - io.core.resp := DontCare -} diff --git a/arch/src/main/scala/framework/gendomain/rocket/HellaInterface.scala b/arch/src/main/scala/framework/gendomain/rocket/HellaInterface.scala deleted file mode 100644 index 798b02f3..00000000 --- a/arch/src/main/scala/framework/gendomain/rocket/HellaInterface.scala +++ /dev/null @@ -1,94 +0,0 @@ -package framework.gendomain.rocket - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ -import framework.gendomain.common._ -import framework.gendomain.mem.{VectorMemIO} - -class HellaCacheInterface(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val status = Input(new MStatus) - val dmem = new HellaCacheIO - val vec = Flipped(new VectorMemIO) - val vec_busy = Input(Bool()) - val mem_busy = Output(Bool()) - }) - - val hella_simple = Module(new SimpleHellaCacheIF) - val hella_arb = Module(new HellaCacheArbiter(2)) - hella_simple.io.requestor <> hella_arb.io.mem - io.dmem <> hella_simple.io.cache - - val hella_load = hella_arb.io.requestor(1) - val hella_store = hella_arb.io.requestor(0) - - val hella_load_q = Module(new Queue(new HellaCacheReq, 2)) - hella_load.req <> hella_load_q.io.deq - val hella_store_q = Module(new Queue(new HellaCacheReq, 2)) - hella_store.req <> hella_store_q.io.deq - - hella_arb.io.requestor.foreach { h => - h.s1_kill := false.B - h.s1_data := DontCare - h.s2_kill := false.B - h.keep_clock_enabled := io.vec_busy - } - - val inflights = RegInit(0.U((1+dmemTagBits).W)) - - io.vec.load_req.ready := hella_load_q.io.enq.ready - hella_load_q.io.enq.valid := io.vec.load_req.valid - hella_load_q.io.enq.bits.addr := io.vec.load_req.bits.addr - hella_load_q.io.enq.bits.size := log2Ceil(dLenB).U - hella_load_q.io.enq.bits.tag := Cat(0.U, io.vec.load_req.bits.tag) - hella_load_q.io.enq.bits.cmd := M_XRD - hella_load_q.io.enq.bits.signed := false.B - hella_load_q.io.enq.bits.dprv := io.status.prv - hella_load_q.io.enq.bits.dv := io.status.dv - hella_load_q.io.enq.bits.data := DontCare - hella_load_q.io.enq.bits.mask := DontCare - hella_load_q.io.enq.bits.phys := false.B - hella_load_q.io.enq.bits.no_resp := false.B - hella_load_q.io.enq.bits.no_alloc := false.B - hella_load_q.io.enq.bits.no_xcpt := true.B - - io.vec.load_resp.valid := hella_load.resp.valid - io.vec.load_resp.bits.data := hella_load.resp.bits.data_raw - io.vec.load_resp.bits.tag := hella_load.resp.bits.tag - - io.vec.store_req.ready := hella_store_q.io.enq.ready - hella_store_q.io.enq.valid := io.vec.store_req.valid - hella_store_q.io.enq.bits.addr := io.vec.store_req.bits.addr - hella_store_q.io.enq.bits.tag := Cat(1.U, io.vec.store_req.bits.tag) - hella_store_q.io.enq.bits.cmd := M_PWR - hella_store_q.io.enq.bits.size := log2Ceil(dLenB).U - hella_store_q.io.enq.bits.signed := false.B - hella_store_q.io.enq.bits.dprv := io.status.prv - hella_store_q.io.enq.bits.dv := io.status.dv - hella_store_q.io.enq.bits.data := io.vec.store_req.bits.data - hella_store_q.io.enq.bits.mask := io.vec.store_req.bits.mask - hella_store_q.io.enq.bits.phys := false.B - hella_store_q.io.enq.bits.no_resp := false.B - hella_store_q.io.enq.bits.no_alloc := false.B - hella_store_q.io.enq.bits.no_xcpt := true.B - - io.vec.store_ack.valid := hella_store.resp.valid - io.vec.store_ack.bits.data := DontCare - io.vec.store_ack.bits.tag := hella_store.resp.bits.tag - - io.mem_busy := inflights =/= 0.U - - val load_enq = hella_load_q.io.enq.fire - val store_enq = hella_store_q.io.enq.fire - val load_deq = hella_load.resp.fire - val store_deq = hella_store.resp.fire - when (load_enq || store_enq || load_deq || store_deq) { - inflights := inflights + (load_enq +& store_enq) - (load_deq +& store_deq) - } -} diff --git a/arch/src/main/scala/framework/gendomain/rocket/Integration.scala b/arch/src/main/scala/framework/gendomain/rocket/Integration.scala deleted file mode 100644 index 13570524..00000000 --- a/arch/src/main/scala/framework/gendomain/rocket/Integration.scala +++ /dev/null @@ -1,119 +0,0 @@ -package framework.gendomain.rocket - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ -import framework.gendomain.backend.{VectorBackend} -import framework.gendomain.mem.{TLSplitInterface, VectorMemUnit} -import framework.gendomain.frontend.{VectorDispatcher} - -class SaturnRocketUnit(implicit p: Parameters) extends RocketVectorUnit()(p) with HasVectorParams with HasCoreParameters { - - if (vParams.useScalarFPFMA || vParams.useScalarFPMisc) { - require(coreParams.fpu.isDefined) - if (vParams.useScalarFPFMA) { - require(coreParams.fpu.get.sfmaLatency == vParams.fmaPipeDepth - 1) - require(coreParams.fpu.get.dfmaLatency == vParams.fmaPipeDepth - 1) - } - } - - val tl_if = LazyModule(new TLSplitInterface) - atlNode := TLBuffer(vParams.tlBuffer) := TLWidthWidget(dLen/8) := tl_if.node - - override lazy val module = new SaturnRocketImpl - class SaturnRocketImpl extends RocketVectorUnitModuleImp(this) with HasVectorParams with HasCoreParameters { - - val useL1DCache = dLen == vMemDataBits - - val dis = Module(new VectorDispatcher) - val vfu = Module(new SaturnRocketFrontend(tl_if.edge)) - val vu = Module(new VectorBackend) - val vmu = Module(new VectorMemUnit) - - val hella_if = Module(new HellaCacheInterface) - val scalar_arb = Module(new Arbiter(new ScalarWrite, 2)) - - dis.io.issue <> vfu.io.issue - - vfu.io.core <> io.core - vfu.io.tlb <> io.tlb - - vu.io.index_access <> vfu.io.index_access - vu.io.mask_access <> vfu.io.mask_access - vu.io.vmu <> vmu.io.vu - vu.io.vat_tail := dis.io.vat_tail - vu.io.vat_head := dis.io.vat_head - vu.io.dis <> dis.io.dis - dis.io.vat_release := vu.io.vat_release - vmu.io.enq <> dis.io.mem - - vmu.io.scalar_check <> vfu.io.scalar_check - - io.core.backend_busy := vu.io.busy || tl_if.module.io.mem_busy || hella_if.io.mem_busy || vmu.io.busy - io.core.set_vxsat := vu.io.set_vxsat - io.core.set_fflags := vu.io.set_fflags - - scalar_arb.io.in(0) <> vu.io.scalar_resp - scalar_arb.io.in(1) <> dis.io.scalar_resp - io.core.resp <> Queue(scalar_arb.io.out) - - io.fp_req <> vu.io.fp_req - vu.io.fp_resp.valid := io.fp_resp.valid - vu.io.fp_resp.bits := io.fp_resp.bits - io.fp_resp.ready := true.B - - io.dmem <> hella_if.io.dmem - hella_if.io.vec_busy := vu.io.busy || vmu.io.busy - hella_if.io.status := io.core.status - - def block[T <: Data](in: DecoupledIO[T], block: Bool): DecoupledIO[T] = { - val out = Wire(Decoupled(in.bits.cloneType)) - out.bits := in.bits - out.valid := in.valid && !block - in.ready := out.ready && !block - out - } - - val load_use_tl_reg = RegInit(true.B) - val store_use_tl_reg = RegInit(true.B) - - // virtually-addressed requests must go through L1 - val load_use_tl = load_use_tl_reg || !useL1DCache.B - val store_use_tl = store_use_tl_reg || !useL1DCache.B - - vmu.io.dmem.load_resp.valid := tl_if.module.io.vec.load_resp.valid || hella_if.io.vec.load_resp.valid - vmu.io.dmem.load_resp.bits := Mux1H( - Seq(tl_if.module.io.vec.load_resp.valid, hella_if.io.vec.load_resp.valid), - Seq(tl_if.module.io.vec.load_resp.bits , hella_if.io.vec.load_resp.bits)) - vmu.io.dmem.store_ack.valid := tl_if.module.io.vec.store_ack.valid || hella_if.io.vec.store_ack.valid - vmu.io.dmem.store_ack.bits := Mux1H( - Seq(tl_if.module.io.vec.store_ack.valid, hella_if.io.vec.store_ack.valid), - Seq(tl_if.module.io.vec.store_ack.bits , hella_if.io.vec.store_ack.bits)) - - when (load_use_tl) { - tl_if.module.io.vec.load_req <> block(vmu.io.dmem.load_req, hella_if.io.mem_busy) - hella_if.io.vec.load_req.valid := false.B - hella_if.io.vec.load_req.bits := DontCare - } .otherwise { - hella_if.io.vec.load_req <> block(vmu.io.dmem.load_req, tl_if.module.io.mem_busy) - tl_if.module.io.vec.load_req.valid := false.B - tl_if.module.io.vec.load_req.bits := DontCare - } - when (store_use_tl) { - tl_if.module.io.vec.store_req <> block(vmu.io.dmem.store_req, hella_if.io.mem_busy) - hella_if.io.vec.store_req.valid := false.B - hella_if.io.vec.store_req.bits := DontCare - } .otherwise { - hella_if.io.vec.store_req <> block(vmu.io.dmem.store_req, tl_if.module.io.mem_busy) - tl_if.module.io.vec.store_req.valid := false.B - tl_if.module.io.vec.store_req.bits := DontCare - } - } -} diff --git a/arch/src/main/scala/framework/gendomain/shuttle/Configs.scala b/arch/src/main/scala/framework/gendomain/shuttle/Configs.scala deleted file mode 100644 index 07e5e89a..00000000 --- a/arch/src/main/scala/framework/gendomain/shuttle/Configs.scala +++ /dev/null @@ -1,49 +0,0 @@ -package framework.gendomain.shuttle - -import chisel3._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.diplomacy._ -import framework.gendomain.common._ -import framework.gendomain.frontend.{EarlyVectorDecode} -import shuttle.common._ - -class WithShuttleVectorUnit( - vLen: Int = 128, - dLen: Int = 64, - params: VectorParams = VectorParams(), - cores: Option[Seq[Int]] = None, - location: HierarchicalLocation = InSubsystem -) extends Config((site, here, up) => { - case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { - case tp: ShuttleTileAttachParams => { - val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) - val vParams = params.copy( - dLen=dLen, - useScalarFPFMA = false, - useScalarFPMisc = false - ) - if (buildVector) tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy( - vector = Some(ShuttleCoreVectorParams( - build = ((p: Parameters) => new SaturnShuttleUnit()(p.alterPartial { - case VectorParamsKey => vParams - })), - vfLen = 64, - vfh = true, - vLen = vLen, - decoder = ((p: Parameters) => { - val decoder = Module(new EarlyVectorDecode(vParams.supported_ex_insns)(p)) - decoder - }), - issueVConfig = false, - vExts = Seq("zvbb") - )), - ) - )) else tp - } - case other => other - } -}) diff --git a/arch/src/main/scala/framework/gendomain/shuttle/Frontend.scala b/arch/src/main/scala/framework/gendomain/shuttle/Frontend.scala deleted file mode 100644 index f2bab271..00000000 --- a/arch/src/main/scala/framework/gendomain/shuttle/Frontend.scala +++ /dev/null @@ -1,112 +0,0 @@ -package framework.gendomain.shuttle - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ -import framework.gendomain.backend.{VectorBackend} -import framework.gendomain.mem.{ScalarMemOrderCheckIO, MemRequest, TLSplitInterface, SGTLInterface} -import framework.gendomain.frontend.{EarlyTrapCheck, IterativeTrapCheck} -import shuttle.common._ - - -class SaturnShuttleFrontend(sgSize: Option[BigInt], edge: TLEdge)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { - val io = IO(new Bundle { - val sg_base = Input(UInt(coreMaxAddrBits.W)) - val core = new ShuttleVectorCoreIO - - val issue = Decoupled(new VectorIssueInst) - - val index_access = Flipped(new VectorIndexAccessIO) - val mask_access = Flipped(new VectorMaskAccessIO) - - val scalar_check = Flipped(new ScalarMemOrderCheckIO) - }) - - val ptc = Module(new EarlyTrapCheck(edge, sgSize)) - val itc = Module(new IterativeTrapCheck) - - val replayed = RegInit(false.B) - - ptc.io.sg_base := io.sg_base - ptc.io.s0.in.valid := io.core.ex.valid && !itc.io.busy && !(replayed && !io.issue.ready) - ptc.io.s0.in.bits.inst := io.core.ex.uop.inst - ptc.io.s0.in.bits.pc := io.core.ex.uop.pc - ptc.io.s0.in.bits.status := io.core.status - ptc.io.s0.in.bits.vconfig := io.core.ex.vconfig - ptc.io.s0.in.bits.vstart := io.core.ex.vstart - ptc.io.s0.in.bits.rs1 := io.core.ex.uop.rs1_data - ptc.io.s0.in.bits.rs2 := io.core.ex.uop.rs2_data - ptc.io.s0.in.bits.phys := !(io.core.status.dprv <= PRV.S.U && io.core.satp.mode(io.core.satp.mode.getWidth-1)) - io.core.ex.ready := !itc.io.busy && !(replayed && !io.issue.ready) - - ptc.io.s1.rs1.valid := ptc.io.s1.inst.isOpf && !ptc.io.s1.inst.vmu - ptc.io.s1.rs1.bits := io.core.mem.frs1 - ptc.io.s1.kill := io.core.mem.kill || !RegEnable(io.core.ex.fire, io.core.ex.valid) - - io.core.mem.tlb_req.valid := Mux(itc.io.busy, itc.io.s1_tlb_req.valid, ptc.io.s1.tlb_req.valid) - io.core.mem.tlb_req.bits := Mux(itc.io.busy, itc.io.s1_tlb_req.bits, ptc.io.s1.tlb_req.bits) - val mem_tlb_resp = Wire(new TLBResp) - mem_tlb_resp.miss := io.core.mem.tlb_resp.miss || !io.core.mem.tlb_req.ready - mem_tlb_resp.paddr := io.core.mem.tlb_resp.paddr - mem_tlb_resp.pf := io.core.mem.tlb_resp.pf - mem_tlb_resp.ae := io.core.mem.tlb_resp.ae - mem_tlb_resp.ma := io.core.mem.tlb_resp.ma - mem_tlb_resp.gpa := DontCare - mem_tlb_resp.gpa_is_pte := DontCare - mem_tlb_resp.gf := 0.U.asTypeOf(new TLBExceptions) - mem_tlb_resp.cacheable := DontCare - mem_tlb_resp.must_alloc := DontCare - mem_tlb_resp.prefetchable := DontCare - mem_tlb_resp.size := DontCare - mem_tlb_resp.cmd := DontCare - ptc.io.s1.tlb_resp := mem_tlb_resp - itc.io.tlb_resp := mem_tlb_resp - - ptc.io.s2.scalar_store_pending := io.core.wb.store_pending - - io.core.wb.retire_late := itc.io.retire - io.core.wb.inst := Mux(itc.io.busy, itc.io.inst.bits , ptc.io.s2.inst.bits.bits) - io.core.wb.pc := Mux(itc.io.busy, itc.io.pc , ptc.io.s2.pc) - io.core.wb.xcpt := Mux(itc.io.busy, itc.io.xcpt.valid , ptc.io.s2.xcpt.valid) - io.core.wb.cause := Mux(itc.io.busy, itc.io.xcpt.bits.cause, ptc.io.s2.xcpt.bits.cause) - io.core.wb.tval := Mux(itc.io.busy, itc.io.xcpt.bits.tval , ptc.io.s2.xcpt.bits.tval) - io.core.wb.internal_replay := ptc.io.s2.internal_replay.valid - io.core.wb.block_all := itc.io.busy || (ptc.io.s2.inst.valid && !ptc.io.s2.retire && !ptc.io.s2.internal_replay.valid) - io.core.wb.rob_should_wb := Mux(itc.io.busy, itc.io.inst.writes_xrf, ptc.io.s2.inst.bits.writes_xrf) - io.core.wb.rob_should_wb_fp := Mux(itc.io.busy, itc.io.inst.writes_frf, ptc.io.s2.inst.bits.writes_frf) - io.core.set_vstart := Mux(itc.io.busy, itc.io.vstart, ptc.io.s2.vstart) - io.core.set_vconfig := itc.io.vconfig - ptc.io.s2.vxrm := io.core.wb.vxrm - ptc.io.s2.frm := io.core.wb.frm - itc.io.in := ptc.io.s2.internal_replay - - when (!io.issue.ready && ptc.io.s2.inst.valid) { replayed := true.B } - when (io.issue.ready) { replayed := false.B } - - io.issue.valid := Mux(itc.io.busy, itc.io.issue.valid, ptc.io.s2.issue.valid) - io.issue.bits := Mux(itc.io.busy, itc.io.issue.bits , ptc.io.s2.issue.bits) - itc.io.issue.ready := io.issue.ready - ptc.io.s2.issue.ready := !itc.io.busy && io.issue.ready - - io.core.trap_check_busy := ptc.io.busy || itc.io.busy - - itc.io.status := io.core.status - itc.io.index_access <> io.index_access - itc.io.mask_access <> io.mask_access - io.scalar_check.addr := io.core.wb.scalar_check.bits.addr - io.scalar_check.size := io.core.wb.scalar_check.bits.size - io.scalar_check.store := io.core.wb.scalar_check.bits.store - io.core.wb.scalar_check.ready := !io.scalar_check.conflict && !(ptc.io.s2.inst.valid && ptc.io.s2.inst.bits.vmu) - - io.core.backend_busy := false.B // set externally - io.core.set_vxsat := false.B // set externally - io.core.set_fflags := DontCare // set externally - io.core.resp := DontCare // set externally -} diff --git a/arch/src/main/scala/framework/gendomain/shuttle/Integration.scala b/arch/src/main/scala/framework/gendomain/shuttle/Integration.scala deleted file mode 100644 index bdc2b7c5..00000000 --- a/arch/src/main/scala/framework/gendomain/shuttle/Integration.scala +++ /dev/null @@ -1,77 +0,0 @@ -package framework.gendomain.shuttle - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ - -import framework.gendomain.common._ -import framework.gendomain.backend.{VectorBackend} -import framework.gendomain.mem.{TLSplitInterface, SGTLInterface, VectorMemUnit} -import framework.gendomain.frontend.{VectorDispatcher} -import shuttle.common._ - - -class SaturnShuttleUnit(implicit p: Parameters) extends ShuttleVectorUnit()(p) with HasVectorParams with HasCoreParameters { - assert(!vParams.useScalarFPFMA && !vParams.useScalarFPMisc) - if (vParams.useScalarFPFMA) { - require(coreParams.fpu.get.dfmaLatency == vParams.fmaPipeDepth - 1) - } - - val tl_if = LazyModule(new TLSplitInterface) - atlNode := TLBuffer(vParams.tlBuffer) := TLWidthWidget(dLenB) := tl_if.node - - val sg_if = sgNode.map { n => - val sg_if = LazyModule(new SGTLInterface) - n :=* sg_if.node - sg_if - } - - override lazy val module = new SaturnShuttleImpl - class SaturnShuttleImpl extends ShuttleVectorUnitModuleImp(this) with HasVectorParams with HasCoreParameters { - - val dis = Module(new VectorDispatcher) - val scalar_arb = Module(new Arbiter(new ScalarWrite, 2)) - val vfu = Module(new SaturnShuttleFrontend(sgSize, tl_if.edge)) - val vu = Module(new VectorBackend) - val vmu = Module(new VectorMemUnit(sgSize)) - - sg_if.foreach { sg => - sg.module.io.vec <> vmu.io.sgmem.get - } - - dis.io.issue <> vfu.io.issue - vfu.io.core <> io - vfu.io.sg_base := io_sg_base - - vu.io.index_access <> vfu.io.index_access - vu.io.mask_access <> vfu.io.mask_access - vu.io.vmu <> vmu.io.vu - vu.io.vat_tail := dis.io.vat_tail - vu.io.vat_head := dis.io.vat_head - vu.io.dis <> dis.io.dis - dis.io.vat_release := vu.io.vat_release - vmu.io.enq <> dis.io.mem - - vmu.io.scalar_check <> vfu.io.scalar_check - - io.backend_busy := vu.io.busy || tl_if.module.io.mem_busy || sg_if.map(_.module.io.mem_busy).getOrElse(false.B) || vmu.io.busy - io.set_vxsat := vu.io.set_vxsat - io.set_fflags := vu.io.set_fflags - - - scalar_arb.io.in(0) <> vu.io.scalar_resp - scalar_arb.io.in(1) <> dis.io.scalar_resp - io.resp <> Queue(scalar_arb.io.out) - - tl_if.module.io.vec <> vmu.io.dmem - - vu.io.fp_req.ready := false.B - vu.io.fp_resp.valid := false.B - vu.io.fp_resp.bits := DontCare - } -} diff --git a/arch/src/main/scala/sims/verilator/TargetConfig.scala b/arch/src/main/scala/sims/verilator/TargetConfig.scala index 39269e85..5666bf7c 100644 --- a/arch/src/main/scala/sims/verilator/TargetConfig.scala +++ b/arch/src/main/scala/sims/verilator/TargetConfig.scala @@ -20,10 +20,6 @@ class BuckyballToyVerilatorConfig extends Config( new WithCustomBootROM ++ new examples.toy.BuckyballToyConfig) -class BuckyballToyVectorVerilatorConfig extends Config( - new WithCustomBootROM ++ - new examples.toy.BuckyballToyVectorConfig) - class BuckyballGemminiVerilatorConfig extends Config( new WithCustomBootROM ++ new gemmini.DefaultGemminiConfig) diff --git a/arch/thirdparty/t1 b/arch/thirdparty/t1 new file mode 160000 index 00000000..07c71ebd --- /dev/null +++ b/arch/thirdparty/t1 @@ -0,0 +1 @@ +Subproject commit 07c71ebd150aa4cbcd5968a5949413829a7a3f71 From b9733627f298a1bdd69d4f75005b4c1667a3be9a Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 9 Dec 2025 22:47:31 +0800 Subject: [PATCH 005/238] [ci] fix: add missing dependency in doc.yml --- .github/workflows/doc.yml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.github/workflows/doc.yml b/.github/workflows/doc.yml index 484a1b30..617e0727 100644 --- a/.github/workflows/doc.yml +++ b/.github/workflows/doc.yml @@ -39,13 +39,9 @@ jobs: cargo install --version ${MDBOOK_VERSION} mdbook cargo install mdbook-linkcheck cargo install mdbook-pandoc - cargo install mdbook-toc - cargo install mdbook-mermaid - name: Setup Pages id: pages uses: actions/configure-pages@v4 - - name: Install mermaid.js - run: cd docs/bb-note && mdbook-mermaid install - name: Build with mdBook run: cd docs/bb-note && mdbook build - name: Upload artifact From 5e023aaf4e404e05980b561e46f04428a65d2b79 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 15 Dec 2025 06:10:15 +0800 Subject: [PATCH 006/238] [arch/core] feat: add usingRVVRoCC in rocket decoder, which would send RVV insts to RoCC [arch/gpdomain] feat: add General Purpose Domain [arch/frontend] feat: add domain id and docoder [doc] fix: remove files' deleted link [bb-tests/ctest] feat: add VSETVLI test (can be sent to gpdomain) --- .github/workflows/test.yml | 1 - arch/build.sc | 1 - .../scala/examples/toy/ToyBuckyBall.scala | 11 +- .../scala/examples/toy/balldomain/DISA.scala | 2 +- .../toy/balldomain/DomainDecoder.scala | 4 +- .../scala/framework/builtin/BaseConfigs.scala | 2 +- .../framework/frontend/decoder/GISA.scala | 8 + .../frontend/decoder/GobalDecoder.scala | 39 +- .../globalrs/GlobalReservationStation.scala | 45 +- .../main/scala/framework/gpdomain/DISA.scala | 85 + .../scala/framework/gpdomain/GPDomain.scala | 38 + .../main/scala/framework/gpdomain/LICENSE.t1 | 183 +++ .../framework/memdomain/DomainDecoder.scala | 4 +- .../scala/framework/memdomain/MemDomain.scala | 2 +- .../main/scala/framework/rocket/CSRBB.scala | 1450 ----------------- .../main/scala/framework/rocket/Configs.scala | 1 + .../src/main/scala/framework/rocket/README.md | 19 - .../framework/rocket/RoCCFragments.scala | 39 - .../scala/framework/rocket/RocketCoreBB.scala | 13 +- .../scala/framework/rocket/RocketTileBB.scala | 4 +- .../framework/rocket/id/RVVRoCCDecode.scala | 75 + .../workloads/src/CTest/toy/CMakeLists.txt | 2 + .../workloads/src/CTest/toy/test_vsetvli.c | 20 + docs/bb-note/src/SUMMARY.md | 1 - .../src/main/scala/framework/rocket/README.md | 1 - 25 files changed, 496 insertions(+), 1554 deletions(-) create mode 100644 arch/src/main/scala/framework/gpdomain/DISA.scala create mode 100644 arch/src/main/scala/framework/gpdomain/GPDomain.scala create mode 100644 arch/src/main/scala/framework/gpdomain/LICENSE.t1 delete mode 100644 arch/src/main/scala/framework/rocket/CSRBB.scala delete mode 100644 arch/src/main/scala/framework/rocket/README.md delete mode 100644 arch/src/main/scala/framework/rocket/RoCCFragments.scala create mode 100644 arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala create mode 100644 bb-tests/workloads/src/CTest/toy/test_vsetvli.c delete mode 120000 docs/bb-note/src/arch/src/main/scala/framework/rocket/README.md diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index d947f997..54932f56 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -20,7 +20,6 @@ jobs: run: | source ~/.zshrc buckyball_exec - setproxy git fetch origin main git clean -fd git reset --hard ${{ github.sha }} diff --git a/arch/build.sc b/arch/build.sc index ab437d61..dd0a9f97 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -8,7 +8,6 @@ import scalalib._ import mill.bsp._ - object buckyball extends SbtModule { m => override def millSourcePath = os.pwd override def scalaVersion = "2.13.12" diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 97a8c3a5..1f49b28e 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -8,7 +8,7 @@ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.tile._ +import freechips.rocketchip.tile.{TileKey, HasCoreParameters, LazyRoCC, LazyRoCCModuleImp} import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile.{LazyRoCC, LazyRoCCModuleImp} @@ -120,6 +120,15 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) outer.reader.module.io.flush := memDomain.io.tlbExp(0).flush() outer.writer.module.io.flush := memDomain.io.tlbExp(0).flush() +// ----------------------------------------------------------------------------- +// Backend: Gen Domain - General purpose domain (for T1 vector processor) +// ----------------------------------------------------------------------------- + val gpDomain = Module(new framework.gpdomain.GpDomain()(b, p)) + + // Global RS -> GpDomain + gpDomain.io.global_issue_i <> globalRs.io.gp_issue_o + globalRs.io.gp_complete_i <> gpDomain.io.global_complete_o + // ----------------------------------------------------------------------------- // Backend: Domain Bridge: BallDomain -> MemDomain // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 394294ad..6d7cefce 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -23,5 +23,5 @@ object DISA { val ABFT_SYSTOLIC = BitPat("b0101010") // 42 val CONV = BitPat("b0101011") // 43 val CIM = BitPat("b0101100") // 44 - val TRANSFER = BitPat("b0101101") // 45 + val TRANSFER = BitPat("b0101101") // 45 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 9fd970f5..ec544bea 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -2,7 +2,7 @@ package examples.toy.balldomain import chisel3._ import chisel3.util._ -import framework.frontend.decoder.PostGDCmd +import framework.frontend.decoder.{PostGDCmd, DomainId} import examples.BuckyballConfigs.CustomBuckyballConfig import examples.toy.balldomain.DISA._ import framework.memdomain.dma.LocalAddr @@ -107,7 +107,7 @@ class BallDomainDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extend // ----------------------------------------------------------------------------- // Output assignment // ----------------------------------------------------------------------------- - io.ball_decode_cmd_o.valid := io.raw_cmd_i.valid && io.raw_cmd_i.bits.is_ball + io.ball_decode_cmd_o.valid := io.raw_cmd_i.valid && (io.raw_cmd_i.bits.domain_id === DomainId.BALL) io.ball_decode_cmd_o.bits.bid := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) diff --git a/arch/src/main/scala/framework/builtin/BaseConfigs.scala b/arch/src/main/scala/framework/builtin/BaseConfigs.scala index 64298454..ab1df656 100644 --- a/arch/src/main/scala/framework/builtin/BaseConfigs.scala +++ b/arch/src/main/scala/framework/builtin/BaseConfigs.scala @@ -3,7 +3,7 @@ package framework.builtin import scala.math.{max, pow, sqrt} import chisel3._ import chisel3.util._ -import freechips.rocketchip.tile._ +import freechips.rocketchip.tile.OpcodeSet import org.chipsalliance.cde.config._ import framework.memdomain.dma.LocalAddr diff --git a/arch/src/main/scala/framework/frontend/decoder/GISA.scala b/arch/src/main/scala/framework/frontend/decoder/GISA.scala index d71436bf..8878a42c 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GISA.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GISA.scala @@ -6,3 +6,11 @@ import chisel3.util._ object GISA { val FENCE_BITPAT = BitPat("b0011111") // 31 (0x1F) } + +// Domain ID constants +object DomainId { + val FRONTEND = 0.U(4.W) // Frontend (fence), does not enter ROB queue + val MEM = 1.U(4.W) // Memory domain + val GP = 2.U(4.W) // General purpose domain (T1 vector processor) + val BALL = 3.U(4.W) // Ball domain +} diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index db909317..5a0564c8 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -7,24 +7,15 @@ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import freechips.rocketchip.tile._ import framework.memdomain.DISA._ +import framework.gpdomain.DISA._ import framework.frontend.decoder.GISA._ class BuckyballRawCmd(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand } - - class PostGDCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - // Instruction type determination - // Ball instruction (excluding FENCE) - val is_ball = Bool() - // Memory instruction (load/store) - val is_mem = Bool() - // Fence instruction - val is_fence = Bool() - - // Raw instruction information, passed to corresponding domain decoder + val domain_id = UInt(4.W) val raw_cmd = new RoCCCommand } @@ -40,17 +31,25 @@ class GlobalDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Mo io.id_i.ready := io.id_o.ready val func7 = io.id_i.bits.cmd.inst.funct - - // Instruction type determination: distinguish Ball, Mem, Fence instructions - val is_mem_instr = (func7 === MVIN_BITPAT) || (func7 === MVOUT_BITPAT) - val is_fence_instr = (func7 === FENCE_BITPAT) - val is_ball_instr = !is_mem_instr && !is_fence_instr + val opcode = io.id_i.bits.cmd.inst.opcode + + // Instruction type determination: distinguish Ball, Mem, Fence, GP (RVV) instructions + val is_mem_inst = (func7 === MVIN_BITPAT) || (func7 === MVOUT_BITPAT) + val is_frontend_inst = (func7 === FENCE_BITPAT) + // RVV instructions: opcode 0x57 (vector compute), 0x07 (vector load), 0x27 (vector store) + val is_gp_inst = (opcode === RVV_OPCODE_V) || (opcode === RVV_OPCODE_VL) || (opcode === RVV_OPCODE_VS) + val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_gp_inst + + // Encode domain ID + val domain_id = MuxCase(DomainId.BALL, Seq( + is_frontend_inst -> DomainId.FRONTEND, + is_mem_inst -> DomainId.MEM, + is_gp_inst -> DomainId.GP, + is_ball_inst -> DomainId.BALL + )) // Output control io.id_o.valid := io.id_i.valid - - io.id_o.bits.is_ball := is_ball_instr - io.id_o.bits.is_mem := is_mem_instr - io.id_o.bits.is_fence := is_fence_instr + io.id_o.bits.domain_id := domain_id io.id_o.bits.raw_cmd := io.id_i.bits.cmd } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 7a028fe2..853bc2e4 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -5,7 +5,8 @@ import chisel3.util._ import chisel3.experimental._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.frontend.decoder.PostGDCmd +import framework.frontend.decoder.{PostGDCmd, DomainId} +import framework.frontend.decoder.GISA._ import freechips.rocketchip.tile.RoCCResponse // Global ROB entry - only contains basic information, does not include specific instruction decoding @@ -36,12 +37,18 @@ class GlobalReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) // Global RS -> MemDomain (single channel) val mem_issue_o = Decoupled(new GlobalRsIssue) + // Global RS -> GpDomain (single channel) + val gp_issue_o = Decoupled(new GlobalRsIssue) + // BallDomain -> Global RS (single channel) val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete)) // MemDomain -> Global RS (single channel) val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete)) + // GpDomain -> Global RS (single channel) + val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete)) + // RoCC response val rs_rocc_o = new Bundle { val resp = new DecoupledIO(new RoCCResponse()(p)) @@ -52,11 +59,12 @@ class GlobalReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) val rob = Module(new GlobalROB) // ----------------------------------------------------------------------------- -// Fence handling +// Fence handling - fence instructions require ROB to be empty before execution // ----------------------------------------------------------------------------- val fenceActive = RegInit(false.B) // Cannot use fire, would form a loop - val isFenceCmd = io.global_decode_cmd_i.valid && io.global_decode_cmd_i.bits.is_fence + val func7 = io.global_decode_cmd_i.bits.raw_cmd.inst.funct + val isFenceCmd = io.global_decode_cmd_i.valid && (func7 === FENCE_BITPAT) val robEmpty = rob.io.empty // Fence state machine: only activate when fence instruction is accepted (fire) @@ -70,37 +78,46 @@ class GlobalReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) // ----------------------------------------------------------------------------- // Inbound - instruction allocation (Fence instructions do not enter ROB) // ----------------------------------------------------------------------------- - // Filter out fence instructions + // Filter out fence instructions (they don't need ROB tracking) rob.io.alloc.valid := io.global_decode_cmd_i.valid && !isFenceCmd rob.io.alloc.bits := io.global_decode_cmd_i.bits // Backpressure logic: // - Normal instructions: wait for ROB ready - // - Fence instructions: wait for ROB empty + // - Fence instructions: wait for ROB empty (to ensure ordering) io.global_decode_cmd_i.ready := Mux(isFenceCmd, robEmpty, rob.io.alloc.ready) // ----------------------------------------------------------------------------- -// Outbound - instruction issue (dispatch to corresponding domain based on is_ball/is_mem) +// Outbound - instruction issue (dispatch to corresponding domain based on domain_id) // ----------------------------------------------------------------------------- + val is_ball_domain = rob.io.issue.bits.cmd.domain_id === DomainId.BALL + val is_mem_domain = rob.io.issue.bits.cmd.domain_id === DomainId.MEM + val is_gp_domain = rob.io.issue.bits.cmd.domain_id === DomainId.GP + // Ball domain issue - io.ball_issue_o.valid := rob.io.issue.valid && rob.io.issue.bits.cmd.is_ball + io.ball_issue_o.valid := rob.io.issue.valid && is_ball_domain io.ball_issue_o.bits := rob.io.issue.bits // Mem domain issue - io.mem_issue_o.valid := rob.io.issue.valid && rob.io.issue.bits.cmd.is_mem + io.mem_issue_o.valid := rob.io.issue.valid && is_mem_domain io.mem_issue_o.bits := rob.io.issue.bits + // GP domain issue + io.gp_issue_o.valid := rob.io.issue.valid && is_gp_domain + io.gp_issue_o.bits := rob.io.issue.bits + // Set ROB ready signal - can only issue when target domain is ready rob.io.issue.ready := - (rob.io.issue.bits.cmd.is_ball && io.ball_issue_o.ready) || - (rob.io.issue.bits.cmd.is_mem && io.mem_issue_o.ready) + (is_ball_domain && io.ball_issue_o.ready) || + (is_mem_domain && io.mem_issue_o.ready) || + (is_gp_domain && io.gp_issue_o.ready) // ----------------------------------------------------------------------------- // Completion signal processing // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.rob_entries).W), 2)) + val completeArb = Module(new Arbiter(UInt(log2Up(b.rob_entries).W), 3)) - // Connect Ball and Mem domain completion signals to arbiter + // Connect Ball, Mem, and GP domain completion signals to arbiter completeArb.io.in(0).valid := io.ball_complete_i.valid completeArb.io.in(0).bits := io.ball_complete_i.bits.rob_id io.ball_complete_i.ready := completeArb.io.in(0).ready @@ -109,6 +126,10 @@ class GlobalReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) completeArb.io.in(1).bits := io.mem_complete_i.bits.rob_id io.mem_complete_i.ready := completeArb.io.in(1).ready + completeArb.io.in(2).valid := io.gp_complete_i.valid + completeArb.io.in(2).bits := io.gp_complete_i.bits.rob_id + io.gp_complete_i.ready := completeArb.io.in(2).ready + // Decide whether to filter completion signals based on configuration if (b.rs_out_of_order_response) { // Out-of-order mode: accept all completion signals, ROB commits out-of-order internally diff --git a/arch/src/main/scala/framework/gpdomain/DISA.scala b/arch/src/main/scala/framework/gpdomain/DISA.scala new file mode 100644 index 00000000..47891756 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/DISA.scala @@ -0,0 +1,85 @@ +package framework.gpdomain + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile._ + + +class BuckyballRawCmd(implicit p: Parameters) extends Bundle { + val cmd = new RoCCCommand +} + +object DISA { + // RVV Instruction Opcodes + val RVV_OPCODE_V = "b1010111".U // 0x57: OP-V (vector compute) + val RVV_OPCODE_VL = "b0000111".U // 0x07: LOAD-FP (vector load) + val RVV_OPCODE_VS = "b0100111".U // 0x27: STORE-FP (vector store) + + // RVV Vector Compute Instructions (opcode 0x57, func3=0-6) + // func7 field [31:25] for vector arithmetic instructions + val VADD_VV = BitPat("b0000000") // 0x00: vadd.vv + val VADD_VX = BitPat("b0000000") // 0x00: vadd.vx + val VADD_VI = BitPat("b0000000") // 0x00: vadd.vi + val VSUB_VV = BitPat("b0000010") // 0x02: vsub.vv + val VSUB_VX = BitPat("b0000010") // 0x02: vsub.vx + val VRSUB_VX = BitPat("b0000011") // 0x03: vrsub.vx + val VRSUB_VI = BitPat("b0000011") // 0x03: vrsub.vi + + val VMINU_VV = BitPat("b0000100") // 0x04: vminu.vv + val VMINU_VX = BitPat("b0000100") // 0x04: vminu.vx + val VMIN_VV = BitPat("b0000101") // 0x05: vmin.vv + val VMIN_VX = BitPat("b0000101") // 0x05: vmin.vx + val VMAXU_VV = BitPat("b0000110") // 0x06: vmaxu.vv + val VMAXU_VX = BitPat("b0000110") // 0x06: vmaxu.vx + val VMAX_VV = BitPat("b0000111") // 0x07: vmax.vv + val VMAX_VX = BitPat("b0000111") // 0x07: vmax.vx + + val VAND_VV = BitPat("b0001001") // 0x09: vand.vv + val VAND_VX = BitPat("b0001001") // 0x09: vand.vx + val VAND_VI = BitPat("b0001001") // 0x09: vand.vi + val VOR_VV = BitPat("b0001010") // 0x0A: vor.vv + val VOR_VX = BitPat("b0001010") // 0x0A: vor.vx + val VOR_VI = BitPat("b0001010") // 0x0A: vor.vi + val VXOR_VV = BitPat("b0001011") // 0x0B: vxor.vv + val VXOR_VX = BitPat("b0001011") // 0x0B: vxor.vx + val VXOR_VI = BitPat("b0001011") // 0x0B: vxor.vi + + val VSLL_VV = BitPat("b0010101") // 0x15: vsll.vv + val VSLL_VX = BitPat("b0010101") // 0x15: vsll.vx + val VSLL_VI = BitPat("b0010101") // 0x15: vsll.vi + val VSRL_VV = BitPat("b0010100") // 0x14: vsrl.vv + val VSRL_VX = BitPat("b0010100") // 0x14: vsrl.vx + val VSRL_VI = BitPat("b0010100") // 0x14: vsrl.vi + val VSRA_VV = BitPat("b0010101") // 0x15: vsra.vv + val VSRA_VX = BitPat("b0010101") // 0x15: vsra.vx + val VSRA_VI = BitPat("b0010101") // 0x15: vsra.vi + + val VMUL_VV = BitPat("b1001010") // 0x4A: vmul.vv + val VMUL_VX = BitPat("b1001010") // 0x4A: vmul.vx + val VMULH_VV = BitPat("b1001011") // 0x4B: vmulh.vv + val VMULH_VX = BitPat("b1001011") // 0x4B: vmulh.vx + val VMULHU_VV = BitPat("b1001000") // 0x48: vmulhu.vv + val VMULHU_VX = BitPat("b1001000") // 0x48: vmulhu.vx + val VMULHSU_VV = BitPat("b1001001") // 0x49: vmulhsu.vv + val VMULHSU_VX = BitPat("b1001001") // 0x49: vmulhsu.vx + + val VMACC_VV = BitPat("b1011010") // 0x5A: vmacc.vv + val VMACC_VX = BitPat("b1011010") // 0x5A: vmacc.vx + val VMADD_VV = BitPat("b1010010") // 0x52: vmadd.vv + val VMADD_VX = BitPat("b1010010") // 0x52: vmadd.vx + + // RVV Vector Load/Store Instructions + // mop field [27:26] for memory operations + val VLE_UNIT = BitPat("b00") // unit-stride load + val VLE_STRIDED = BitPat("b10") // strided load + val VLE_INDEXED = BitPat("b11") // indexed load + val VSE_UNIT = BitPat("b00") // unit-stride store + val VSE_STRIDED = BitPat("b10") // strided store + val VSE_INDEXED = BitPat("b11") // indexed store + + // Vector configuration instructions (vsetvl, vsetvli, vsetivli) + val VSETVLI = BitPat("b0000000") // vsetvli + val VSETIVLI = BitPat("b1100000") // vsetivli + val VSETVL = BitPat("b1000000") // vsetvl +} diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala new file mode 100644 index 00000000..5b0a6eb0 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -0,0 +1,38 @@ +package framework.gpdomain + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} +/** + * General Purpose Domain + */ +class GpDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { + // Receive instructions from GlobalRS + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) + + // Report completion to GlobalRS + val global_complete_o = Decoupled(new GlobalRsComplete) + + // Status signal + val busy = Output(Bool()) +} + +class GpDomain(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { + val io = IO(new GpDomainIO) + + // Placeholder implementation: accept instructions and immediately complete them + // This allows RVV instructions to pass through without blocking the pipeline + + // Accept all incoming instructions + io.global_issue_i.ready := io.global_complete_o.ready + + // Immediately complete accepted instructions (pass-through) + io.global_complete_o.valid := io.global_issue_i.valid + io.global_complete_o.bits.rob_id := io.global_issue_i.bits.rob_id + + io.busy := false.B + + override lazy val desiredName = "GpDomain" +} diff --git a/arch/src/main/scala/framework/gpdomain/LICENSE.t1 b/arch/src/main/scala/framework/gpdomain/LICENSE.t1 new file mode 100644 index 00000000..c6d9f269 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/LICENSE.t1 @@ -0,0 +1,183 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + ------------------------------------------------------------------------ + Note: + Individual files contain the following tag instead of the full license text. + + // SPDX-License-Identifier: Apache-2.0 diff --git a/arch/src/main/scala/framework/memdomain/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/DomainDecoder.scala index bdd56df2..10b92406 100644 --- a/arch/src/main/scala/framework/memdomain/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/DomainDecoder.scala @@ -2,7 +2,7 @@ package framework.memdomain import chisel3._ import chisel3.util._ -import framework.frontend.decoder.PostGDCmd +import framework.frontend.decoder.{PostGDCmd, DomainId} import examples.BuckyballConfigs.CustomBuckyballConfig import framework.memdomain.DISA._ import framework.memdomain.dma.LocalAddr @@ -77,7 +77,7 @@ class MemDomainDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends // ----------------------------------------------------------------------------- // Output assignment // ----------------------------------------------------------------------------- - io.mem_decode_cmd_o.valid := io.raw_cmd_i.valid && io.raw_cmd_i.bits.is_mem + io.mem_decode_cmd_o.valid := io.raw_cmd_i.valid && (io.raw_cmd_i.bits.domain_id === DomainId.MEM) io.mem_decode_cmd_o.bits.is_load := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.LD_EN.id).asBool, false.B) io.mem_decode_cmd_o.bits.is_store := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.ST_EN.id).asBool, false.B) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index f0fe2731..9d3e9ef5 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -129,7 +129,7 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu // ToPhysical interface // Ball Domain SRAM interface connected to MemController's Ball Domain interface val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) - + toPhysicalLines.io.sramRead_i <> io.ballDomain.sramRead toPhysicalLines.io.sramWrite_i <> io.ballDomain.sramWrite diff --git a/arch/src/main/scala/framework/rocket/CSRBB.scala b/arch/src/main/scala/framework/rocket/CSRBB.scala deleted file mode 100644 index 819c3279..00000000 --- a/arch/src/main/scala/framework/rocket/CSRBB.scala +++ /dev/null @@ -1,1450 +0,0 @@ -// See LICENSE.SiFive for license details. -// See LICENSE.Berkeley for license details. - -package framework.rocket - -import chisel3._ -import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.devices.debug.DebugModuleKey -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property - -import scala.collection.mutable.LinkedHashMap -import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.Instructions._ -import freechips.rocketchip.rocket.CustomInstructions._ - - -class CSRDecodeIOBB(implicit p: Parameters) extends CoreBundle { - val inst = Input(UInt(iLen.W)) - - def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) - - val fp_illegal = Output(Bool()) - val vector_illegal = Output(Bool()) - val fp_csr = Output(Bool()) - val vector_csr = Output(Bool()) - val rocc_illegal = Output(Bool()) - val read_illegal = Output(Bool()) - val write_illegal = Output(Bool()) - val write_flush = Output(Bool()) - val system_illegal = Output(Bool()) - val virtual_access_illegal = Output(Bool()) - val virtual_system_illegal = Output(Bool()) -} - -class CSRFileIOBB(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle - with HasCoreParameters { - val ungated_clock = Input(Clock()) - val interrupts = Input(new CoreInterrupts(hasBeu)) - val hartid = Input(UInt(hartIdLen.W)) - val rw = new Bundle { - val addr = Input(UInt(CSR.ADDRSZ.W)) - val cmd = Input(Bits(CSR.SZ.W)) - val rdata = Output(Bits(xLen.W)) - val wdata = Input(Bits(xLen.W)) - } - - val decode = Vec(decodeWidth, new CSRDecodeIOBB) - - val csr_stall = Output(Bool()) // stall retire for wfi - val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall - val eret = Output(Bool()) - val singleStep = Output(Bool()) - - val status = Output(new MStatus()) - val hstatus = Output(new HStatus()) - val gstatus = Output(new MStatus()) - val ptbr = Output(new PTBR()) - val hgatp = Output(new PTBR()) - val vsatp = Output(new PTBR()) - val evec = Output(UInt(vaddrBitsExtended.W)) - val exception = Input(Bool()) - val retire = Input(UInt(log2Up(1+retireWidth).W)) - val cause = Input(UInt(xLen.W)) - val pc = Input(UInt(vaddrBitsExtended.W)) - val tval = Input(UInt(vaddrBitsExtended.W)) - val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) - val mhtinst_read_pseudo = Input(Bool()) - val gva = Input(Bool()) - val time = Output(UInt(xLen.W)) - val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) - val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) - val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) - val rocc_interrupt = Input(Bool()) - val interrupt = Output(Bool()) - val interrupt_cause = Output(UInt(xLen.W)) - val bp = Output(Vec(nBreakpoints, new BP)) - val pmp = Output(Vec(nPMPs, new PMP)) - val counters = Vec(nPerfCounters, new PerfCounterIO) - val csrw_counter = Output(UInt(CSR.nCtr.W)) - val inhibit_cycle = Output(Bool()) - val inst = Input(Vec(retireWidth, UInt(iLen.W))) - val trace = Output(Vec(retireWidth, new TracedInstruction)) - val mcontext = Output(UInt(coreParams.mcontextWidth.W)) - val scontext = Output(UInt(coreParams.scontextWidth.W)) - val fiom = Output(Bool()) - - val vector = usingVector.option(new Bundle { - val vconfig = Output(new VConfig()) - val vstart = Output(UInt(maxVLMax.log2.W)) - val vxrm = Output(UInt(2.W)) - val set_vs_dirty = Input(Bool()) - val set_vconfig = Flipped(Valid(new VConfig)) - val set_vstart = Flipped(Valid(vstart)) - val set_vxsat = Input(Bool()) - }) -} - -class VConfig(implicit p: Parameters) extends CoreBundle { - val vl = UInt((maxVLMax.log2 + 1).W) - val vtype = new VType -} - -object VType { - def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { - val res = 0.U.asTypeOf(new VType) - val in = that.asTypeOf(res) - val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill - when (!vill || ignore_vill.B) { - res := in - res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) - } - res.reserved := 0.U - res.vill := vill - res - } - - def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = - VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) -} - -class VType(implicit p: Parameters) extends CoreBundle { - val vill = Bool() - val reserved = UInt((xLen - 9).W) - val vma = Bool() - val vta = Bool() - val vsew = UInt(3.W) - val vlmul_sign = Bool() - val vlmul_mag = UInt(2.W) - - def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt - - @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") - def vlmul: UInt = vlmul_mag - - def max_vsew = log2Ceil(eLen/8) - def max_vlmul = (1 << vlmul_mag.getWidth) - 1 - - def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) - - def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 - - def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) - - def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { - val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) - val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) - - val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR - val isZero = vill || useZero - Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) - } -} - -class CSRFileBB( - perfEventSets: EventSets = new EventSets(Seq()), - customCSRs: Seq[CustomCSR] = Nil, - roccCSRs: Seq[CustomCSR] = Nil, - hasBeu: Boolean = false)(implicit p: Parameters) - extends CoreModule()(p) - with HasCoreParameters { - val io = IO(new CSRFileIOBB(hasBeu) { - val customCSRs = Vec(CSRFileBB.this.customCSRs.size, new CustomCSRIO) - val roccCSRs = Vec(CSRFileBB.this.roccCSRs.size, new CustomCSRIO) - }) - - io.rw_stall := false.B - - val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) - reset_mstatus.mpp := PRV.M.U - reset_mstatus.prv := PRV.M.U - reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) - val reg_mstatus = RegInit(reset_mstatus) - - val new_prv = WireDefault(reg_mstatus.prv) - reg_mstatus.prv := legalizePrivilege(new_prv) - - val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) - reset_dcsr.xdebugver := 1.U - reset_dcsr.prv := PRV.M.U - val reg_dcsr = RegInit(reset_dcsr) - - val (supported_interrupts, delegable_interrupts) = { - val sup = Wire(new MIP) - sup.usip := false.B - sup.ssip := usingSupervisor.B - sup.vssip := usingHypervisor.B - sup.msip := true.B - sup.utip := false.B - sup.stip := usingSupervisor.B - sup.vstip := usingHypervisor.B - sup.mtip := true.B - sup.ueip := false.B - sup.seip := usingSupervisor.B - sup.vseip := usingHypervisor.B - sup.meip := true.B - sup.sgeip := false.B - sup.rocc := usingRoCC.B - sup.debug := false.B - sup.zero1 := false.B - sup.lip foreach { _ := true.B } - val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U - - val del = WireDefault(sup) - del.msip := false.B - del.mtip := false.B - del.meip := false.B - - (sup.asUInt | supported_high_interrupts, del.asUInt) - } - val delegable_base_exceptions = Seq( - Causes.misaligned_fetch, - Causes.fetch_page_fault, - Causes.breakpoint, - Causes.load_page_fault, - Causes.store_page_fault, - Causes.misaligned_load, - Causes.misaligned_store, - Causes.illegal_instruction, - Causes.user_ecall, - ) - val delegable_hypervisor_exceptions = Seq( - Causes.virtual_supervisor_ecall, - Causes.fetch_guest_page_fault, - Causes.load_guest_page_fault, - Causes.virtual_instruction, - Causes.store_guest_page_fault, - ) - val delegable_exceptions = ( - delegable_base_exceptions - ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) - ).map(1 << _).sum.U - - val hs_delegable_exceptions = Seq( - Causes.misaligned_fetch, - Causes.fetch_access, - Causes.illegal_instruction, - Causes.breakpoint, - Causes.misaligned_load, - Causes.load_access, - Causes.misaligned_store, - Causes.store_access, - Causes.user_ecall, - Causes.fetch_page_fault, - Causes.load_page_fault, - Causes.store_page_fault).map(1 << _).sum.U - - val (hs_delegable_interrupts, mideleg_always_hs) = { - val always = WireDefault(0.U.asTypeOf(new MIP())) - always.vssip := usingHypervisor.B - always.vstip := usingHypervisor.B - always.vseip := usingHypervisor.B - - val deleg = WireDefault(always) - deleg.lip.foreach { _ := usingHypervisor.B } - - (deleg.asUInt, always.asUInt) - } - - val reg_debug = RegInit(false.B) - val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) - val reg_dscratch0 = Reg(UInt(xLen.W)) - val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) - val reg_singleStepped = Reg(Bool()) - - val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) - val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) - - val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) - val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) - val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) - - val reg_mie = Reg(UInt(xLen.W)) - val (reg_mideleg, read_mideleg) = { - val reg = Reg(UInt(xLen.W)) - (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U)) - } - val (reg_medeleg, read_medeleg) = { - val reg = Reg(UInt(xLen.W)) - (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) - } - val reg_mip = Reg(new MIP) - val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) - val reg_mcause = RegInit(0.U(xLen.W)) - val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) - val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) - val reg_mscratch = Reg(Bits(xLen.W)) - val mtvecWidth = paddrBits min xLen - val reg_mtvec = mtvecInit match { - case Some(addr) => RegInit(addr.U(mtvecWidth.W)) - case None => Reg(UInt(mtvecWidth.W)) - } - - val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) - reset_mnstatus.mpp := PRV.M.U - val reg_mnscratch = Reg(Bits(xLen.W)) - val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) - val reg_mncause = RegInit(0.U(xLen.W)) - val reg_mnstatus = RegInit(reset_mnstatus) - val reg_rnmie = RegInit(true.B) - val nmie = reg_rnmie - - val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) - val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) - val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) - - val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U - val (reg_mcounteren, read_mcounteren) = { - val reg = Reg(UInt(32.W)) - (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) - } - val (reg_scounteren, read_scounteren) = { - val reg = Reg(UInt(32.W)) - (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) - } - - val (reg_hideleg, read_hideleg) = { - val reg = Reg(UInt(xLen.W)) - (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) - } - val (reg_hedeleg, read_hedeleg) = { - val reg = Reg(UInt(xLen.W)) - (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) - } - val hs_delegable_counters = delegable_counters - val (reg_hcounteren, read_hcounteren) = { - val reg = Reg(UInt(32.W)) - (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) - } - val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) - val reg_hgatp = Reg(new PTBR) - val reg_htval = Reg(reg_mtval2.cloneType) - val read_hvip = reg_mip.asUInt & hs_delegable_interrupts - val read_hie = reg_mie & hs_delegable_interrupts - - val (reg_vstvec, read_vstvec) = { - val reg = Reg(UInt(vaddrBitsExtended.W)) - (reg, formTVec(reg).sextTo(xLen)) - } - val reg_vsstatus = Reg(new MStatus) - val reg_vsscratch = Reg(Bits(xLen.W)) - val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) - val reg_vscause = Reg(Bits(xLen.W)) - val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) - val reg_vsatp = Reg(new PTBR) - - val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) - val reg_scause = Reg(Bits(xLen.W)) - val reg_stval = Reg(UInt(vaddrBitsExtended.W)) - val reg_sscratch = Reg(Bits(xLen.W)) - val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) - val reg_satp = Reg(new PTBR) - val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } - - val reg_fflags = Reg(UInt(5.W)) - val reg_frm = Reg(UInt(3.W)) - val reg_vconfig = usingVector.option(Reg(new VConfig)) - val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) - val reg_vxsat = usingVector.option(Reg(Bool())) - val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) - - val reg_mtinst_read_pseudo = Reg(Bool()) - val reg_htinst_read_pseudo = Reg(Bool()) - // XLEN=32: 0x00002000 - // XLEN=64: 0x00003000 - val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) - - val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) - io.inhibit_cycle := reg_mcountinhibit(0) - val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) - val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) - else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } - val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) - (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } - val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => - WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } - - val mip = WireDefault(reg_mip) - mip.lip := (io.interrupts.lip: Seq[Bool]) - mip.mtip := io.interrupts.mtip - mip.msip := io.interrupts.msip - mip.meip := io.interrupts.meip - // seip is the OR of reg_mip.seip and the actual line from the PLIC - io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ } - // Simimlar sort of thing would apply if the PLIC had a VSEIP line: - //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ } - mip.rocc := io.rocc_interrupt - val read_mip = mip.asUInt & supported_interrupts - val read_hip = read_mip & hs_delegable_interrupts - val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) - - val pending_interrupts = high_interrupts | (read_mip & reg_mie) - val d_interrupts = io.interrupts.debug << CSR.debugIntCause - val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => - (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) | - io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), - !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) - val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U) - val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) - val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) - val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) - val interruptMSB = BigInt(1) << (xLen-1) - val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt - io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease) - io.interrupt_cause := interruptCause - io.bp := reg_bp take nBreakpoints - io.mcontext := reg_mcontext.getOrElse(0.U) - io.scontext := reg_scontext.getOrElse(0.U) - io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom) - io.pmp := reg_pmp.map(PMP(_)) - - val isaMaskString = - (if (usingMulDiv) "M" else "") + - (if (usingAtomics) "A" else "") + - (if (fLen >= 32) "F" else "") + - (if (fLen >= 64) "D" else "") + - (if (coreParams.hasV) "V" else "") + - (if (usingCompressed) "C" else "") - val isaString = (if (coreParams.useRVE) "E" else "I") + - isaMaskString + - (if (customIsaExt.isDefined || usingRoCC) "X" else "") + - (if (usingSupervisor) "S" else "") + - (if (usingHypervisor) "H" else "") + - (if (usingUser) "U" else "") - val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString) - val reg_misa = RegInit(isaMax.U) - val read_mstatus = io.status.asUInt.extract(xLen-1,0) - val read_mtvec = formTVec(reg_mtvec).padTo(xLen) - val read_stvec = formTVec(reg_stvec).sextTo(xLen) - - val read_mapping = LinkedHashMap[Int,Bits]( - CSRs.tselect -> reg_tselect, - CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, - CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), - CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, - CSRs.misa -> reg_misa, - CSRs.mstatus -> read_mstatus, - CSRs.mtvec -> read_mtvec, - CSRs.mip -> read_mip, - CSRs.mie -> reg_mie, - CSRs.mscratch -> reg_mscratch, - CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), - CSRs.mtval -> reg_mtval.sextTo(xLen), - CSRs.mcause -> reg_mcause, - CSRs.mhartid -> io.hartid) - - val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( - CSRs.dcsr -> reg_dcsr.asUInt, - CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), - CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ - reg_dscratch1.map(r => CSRs.dscratch1 -> r) - - val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) - read_mnstatus.mpp := reg_mnstatus.mpp - read_mnstatus.mpv := reg_mnstatus.mpv - read_mnstatus.mie := reg_rnmie - val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( - CustomCSRs.mnscratch -> reg_mnscratch, - CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), - CustomCSRs.mncause -> reg_mncause, - CustomCSRs.mnstatus -> read_mnstatus.asUInt) - - val context_csrs = LinkedHashMap[Int,Bits]() ++ - reg_mcontext.map(r => CSRs.mcontext -> r) ++ - reg_scontext.map(r => CSRs.scontext -> r) - - val read_fcsr = Cat(reg_frm, reg_fflags) - val fp_csrs = LinkedHashMap[Int,Bits]() ++ - usingFPU.option(CSRs.fflags -> reg_fflags) ++ - usingFPU.option(CSRs.frm -> reg_frm) ++ - (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) - - val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) - val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( - CSRs.vxsat -> reg_vxsat.get, - CSRs.vxrm -> reg_vxrm.get, - CSRs.vcsr -> read_vcsr, - CSRs.vstart -> reg_vstart.get, - CSRs.vtype -> reg_vconfig.get.vtype.asUInt, - CSRs.vl -> reg_vconfig.get.vl, - CSRs.vlenb -> (vLen / 8).U) - - read_mapping ++= debug_csrs - read_mapping ++= nmi_csrs - read_mapping ++= context_csrs - read_mapping ++= fp_csrs - read_mapping ++= vector_csrs - - if (coreParams.haveBasicCounters) { - read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit - read_mapping += CSRs.mcycle -> reg_cycle - read_mapping += CSRs.minstret -> reg_instret - - for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) - zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { - read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN - read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN - read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN - if (xLen == 32) { - read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh - read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh - } - } - - if (usingUser) { - read_mapping += CSRs.mcounteren -> read_mcounteren - } - read_mapping += CSRs.cycle -> reg_cycle - read_mapping += CSRs.instret -> reg_instret - - if (xLen == 32) { - read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) - read_mapping += CSRs.minstreth -> (reg_instret >> 32) - read_mapping += CSRs.cycleh -> (reg_cycle >> 32) - read_mapping += CSRs.instreth -> (reg_instret >> 32) - } - } - - if (usingUser) { - read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt - if (xLen == 32) - read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) - } - - val sie_mask = { - val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) - sgeip_mask.sgeip := true.B - read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt) - } - if (usingSupervisor) { - val read_sie = reg_mie & sie_mask - val read_sip = read_mip & sie_mask - val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) - read_sstatus.sd := io.status.sd - read_sstatus.uxl := io.status.uxl - read_sstatus.sd_rv32 := io.status.sd_rv32 - read_sstatus.mxr := io.status.mxr - read_sstatus.sum := io.status.sum - read_sstatus.xs := io.status.xs - read_sstatus.fs := io.status.fs - read_sstatus.vs := io.status.vs - read_sstatus.spp := io.status.spp - read_sstatus.spie := io.status.spie - read_sstatus.sie := io.status.sie - - read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) - read_mapping += CSRs.sip -> read_sip.asUInt - read_mapping += CSRs.sie -> read_sie.asUInt - read_mapping += CSRs.sscratch -> reg_sscratch - read_mapping += CSRs.scause -> reg_scause - read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) - read_mapping += CSRs.satp -> reg_satp.asUInt - read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) - read_mapping += CSRs.stvec -> read_stvec - read_mapping += CSRs.scounteren -> read_scounteren - read_mapping += CSRs.mideleg -> read_mideleg - read_mapping += CSRs.medeleg -> read_medeleg - read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt - } - - val pmpCfgPerCSR = xLen / new PMPConfig().getWidth - def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) - if (reg_pmp.nonEmpty) { - require(reg_pmp.size <= CSR.maxPMPs) - val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) - for (i <- 0 until read_pmp.size by pmpCfgPerCSR) - read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt - for ((pmp, i) <- read_pmp.zipWithIndex) - read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr - } - - // implementation-defined CSRs - def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { - require(csr.mask >= 0 && csr.mask.bitLength <= xLen) - require(!read_mapping.contains(csr.id)) - val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) - val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U - csr_io.ren := read - when (read && csr_io.stall) { io.rw_stall := true.B } - read_mapping += csr.id -> reg - reg - } - val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) - val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) - - if (usingHypervisor) { - read_mapping += CSRs.mtinst -> read_mtinst - read_mapping += CSRs.mtval2 -> reg_mtval2 - - val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) - - read_mapping += CSRs.hstatus -> read_hstatus - read_mapping += CSRs.hedeleg -> read_hedeleg - read_mapping += CSRs.hideleg -> read_hideleg - read_mapping += CSRs.hcounteren-> read_hcounteren - read_mapping += CSRs.hgatp -> reg_hgatp.asUInt - read_mapping += CSRs.hip -> read_hip - read_mapping += CSRs.hie -> read_hie - read_mapping += CSRs.hvip -> read_hvip - read_mapping += CSRs.hgeie -> 0.U - read_mapping += CSRs.hgeip -> 0.U - read_mapping += CSRs.htval -> reg_htval - read_mapping += CSRs.htinst -> read_htinst - read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt - if (xLen == 32) - read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) - - val read_vsie = (read_hie & read_hideleg) >> 1 - val read_vsip = (read_hip & read_hideleg) >> 1 - val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) - val read_vstval = reg_vstval.sextTo(xLen) - val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) - - read_mapping += CSRs.vsstatus -> read_vsstatus - read_mapping += CSRs.vsip -> read_vsip - read_mapping += CSRs.vsie -> read_vsie - read_mapping += CSRs.vsscratch -> reg_vsscratch - read_mapping += CSRs.vscause -> reg_vscause - read_mapping += CSRs.vstval -> read_vstval - read_mapping += CSRs.vsatp -> reg_vsatp.asUInt - read_mapping += CSRs.vsepc -> read_vsepc - read_mapping += CSRs.vstvec -> read_vstvec - } - - // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs - Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) - - val decoded_addr = { - val addr = Cat(io.status.v, io.rw.addr) - val pats = for (((k, _), i) <- read_mapping.zipWithIndex) - yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) - val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) - val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap - - for ((k, v) <- unvirtualized_mapping) yield k -> { - val alt: Option[Bool] = CSR.mode(k) match { - // hcontext was assigned an unfortunate address; it lives where a - // hypothetical vscontext will live. Exclude them from the S/VS remapping. - // (on separate lines so scala-lint doesnt do something stupid) - case _ if k == CSRs.scontext => None - case _ if k == CSRs.hcontext => None - // When V=1, if a corresponding VS CSR exists, access it instead... - case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) - // ...and don't access the original S-mode version. - case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) - case _ => None - } - alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) - } - } - - val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) - - val system_insn = io.rw.cmd === CSR.I - val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) - val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), - EBREAK-> List(N,Y,N,N,N,N,N,N,N), - MRET-> List(N,N,Y,N,N,N,N,N,N), - CEASE-> List(N,N,N,Y,N,N,N,N,N), - WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ - usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ - usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ - coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ - usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ - usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ - usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ - usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ - (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) - val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { - val insn = ECALL.value.U | (io.rw.addr << 20) - DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) - } - - for (io_dec <- io.decode) { - val addr = io_dec.inst(31, 20) - - def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_) - def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) - - val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = - DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) - val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) - - val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw) - val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) - val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) - val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu) - val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) - val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) - val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) && - (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) && - (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr)) - io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a') - io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a') - io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) - io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) - io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a') - val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) || - usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U - val csr_exists = decodeAny(read_mapping) - io_dec.read_illegal := !csr_addr_legal || - !csr_exists || - ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) || - is_counter && !allow_counter || - decodeFast(debug_csrs.keys.toList) && !reg_debug || - decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal || - io_dec.fp_csr && io_dec.fp_illegal - io_dec.write_illegal := addr(11,10).andR - io_dec.write_flush := { - val addr_m = addr | (PRV.M.U << CSR.modeLSB) - !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) - } - io_dec.system_illegal := !csr_addr_legal && !is_hlsv || - is_wfi && !allow_wfi || - is_ret && !allow_sret || - is_ret && addr(10) && addr(7) && !reg_debug || - (is_sfence || is_hfence_gvma) && !allow_sfence_vma || - is_hfence_vvma && !allow_hfence_vvma || - is_hlsv && !allow_hlsv - - io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( - CSR.mode(addr) === PRV.H.U || - is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) || - CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) || - addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) - - io_dec.virtual_system_illegal := reg_mstatus.v && ( - is_hfence_vvma || - is_hfence_gvma || - is_hlsv || - is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) || - is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) || - is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm)) - } - - val cause = - Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), - Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) - val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) - val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) - val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U - val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U - val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) - val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) - val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) - val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) - val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) - val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) - val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) - def mtvecBaseAlign = 2 - def mtvecInterruptAlign = { - require(reg_mip.getWidth <= xLen) - log2Ceil(xLen) - } - val notDebugTVec = { - val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) - val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign - val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) - val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U - Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) - } - - val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U) - val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U - val causeIsNmi = causeIsRnmiInt - val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) - val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) - val trapToNmiInt = usingNMI.B && causeIsNmi - val trapToNmiXcpt = usingNMI.B && !nmie - val trapToNmi = trapToNmiInt || trapToNmiXcpt - val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 - - val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) - io.evec := tvec - io.ptbr := reg_satp - io.hgatp := reg_hgatp - io.vsatp := reg_vsatp - io.eret := insn_call || insn_break || insn_ret - io.singleStep := reg_dcsr.step && !reg_debug - io.status := reg_mstatus - io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR - io.status.debug := reg_debug - io.status.isa := reg_misa - io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U - io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U - io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) - io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) - io.status.sd_rv32 := (xLen == 32).B && io.status.sd - io.status.mpv := reg_mstatus.mpv - io.status.gva := reg_mstatus.gva - io.hstatus := reg_hstatus - io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U - io.gstatus := reg_vsstatus - io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR - io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U - io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd - - val exception = insn_call || insn_break || io.exception - assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") - - when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } - when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B } - io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) - - when (io.retire(0) || exception) { reg_singleStepped := true.B } - when (!io.singleStep) { reg_singleStepped := false.B } - assert(!io.singleStep || io.retire <= 1.U) - assert(!reg_singleStepped || io.retire === 0.U) - - val epc = formEPC(io.pc) - val tval = Mux(insn_break, epc, io.tval) - - when (exception) { - when (trapToDebug) { - when (!reg_debug) { - reg_mstatus.v := false.B - reg_debug := true.B - reg_dpc := epc - reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) - reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) - reg_dcsr.v := reg_mstatus.v - new_prv := PRV.M.U - } - }.elsewhen (trapToNmiInt) { - when (reg_rnmie) { - reg_mstatus.v := false.B - reg_mnstatus.mpv := reg_mstatus.v - reg_rnmie := false.B - reg_mnepc := epc - reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U) - reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) - new_prv := PRV.M.U - } - }.elsewhen (delegateVS && nmie) { - reg_mstatus.v := true.B - reg_vsstatus.spp := reg_mstatus.prv - reg_vsepc := epc - reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) - reg_vstval := tval - reg_vsstatus.spie := reg_vsstatus.sie - reg_vsstatus.sie := false.B - new_prv := PRV.S.U - }.elsewhen (delegate && nmie) { - reg_mstatus.v := false.B - reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) - reg_hstatus.gva := io.gva - reg_hstatus.spv := reg_mstatus.v - reg_sepc := epc - reg_scause := cause - reg_stval := tval - reg_htval := io.htval - reg_htinst_read_pseudo := io.mhtinst_read_pseudo - reg_mstatus.spie := reg_mstatus.sie - reg_mstatus.spp := reg_mstatus.prv - reg_mstatus.sie := false.B - new_prv := PRV.S.U - }.otherwise { - reg_mstatus.v := false.B - reg_mstatus.mpv := reg_mstatus.v - reg_mstatus.gva := io.gva - reg_mepc := epc - reg_mcause := cause - reg_mtval := tval - reg_mtval2 := io.htval - reg_mtinst_read_pseudo := io.mhtinst_read_pseudo - reg_mstatus.mpie := reg_mstatus.mie - reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) - reg_mstatus.mie := false.B - new_prv := PRV.M.U - } - } - - for (i <- 0 until supported_interrupts.getWidth) { - val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U - val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U - property.cover(en && !delegate, s"INTERRUPT_M_$i") - property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") - } - for (i <- 0 until xLen) { - val supported_exceptions: BigInt = 0x8fe | - (if (usingCompressed && !coreParams.misaWritable) 0 else 1) | - (if (usingUser) 0x100 else 0) | - (if (usingSupervisor) 0x200 else 0) | - (if (usingVM) 0xb000 else 0) - if (((supported_exceptions >> i) & 1) != 0) { - val en = exception && cause === i.U - val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U - property.cover(en && !delegate, s"EXCEPTION_M_$i") - property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") - } - } - - when (insn_ret) { - val ret_prv = WireInit(UInt(), DontCare) - when (usingSupervisor.B && !io.rw.addr(9)) { - when (!reg_mstatus.v) { - reg_mstatus.sie := reg_mstatus.spie - reg_mstatus.spie := true.B - reg_mstatus.spp := PRV.U.U - ret_prv := reg_mstatus.spp - reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv - io.evec := readEPC(reg_sepc) - reg_hstatus.spv := false.B - }.otherwise { - reg_vsstatus.sie := reg_vsstatus.spie - reg_vsstatus.spie := true.B - reg_vsstatus.spp := PRV.U.U - ret_prv := reg_vsstatus.spp - reg_mstatus.v := usingHypervisor.B - io.evec := readEPC(reg_vsepc) - } - }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { - ret_prv := reg_dcsr.prv - reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U - reg_debug := false.B - io.evec := readEPC(reg_dpc) - }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { - ret_prv := reg_mnstatus.mpp - reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U - reg_rnmie := true.B - io.evec := readEPC(reg_mnepc) - }.otherwise { - reg_mstatus.mie := reg_mstatus.mpie - reg_mstatus.mpie := true.B - reg_mstatus.mpp := legalizePrivilege(PRV.U.U) - reg_mstatus.mpv := false.B - ret_prv := reg_mstatus.mpp - reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U - io.evec := readEPC(reg_mepc) - } - - new_prv := ret_prv - when (usingUser.B && ret_prv <= PRV.S.U) { - reg_mstatus.mprv := false.B - } - } - - io.time := reg_cycle - io.csr_stall := reg_wfi || io.status.cease - io.status.cease := RegEnable(true.B, false.B, insn_cease) - io.status.wfi := reg_wfi - - for ((io, reg) <- io.customCSRs zip reg_custom) { - io.wen := false.B - io.wdata := wdata - io.value := reg - } - - for ((io, reg) <- io.roccCSRs zip reg_rocc) { - io.wen := false.B - io.wdata := wdata - io.value := reg - } - - io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) - - // cover access to register - val coverable_counters = read_mapping.filterNot { case (k, _) => - k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM - } - coverable_counters.foreach( {case (k, v) => { - when (!k.U(11,10).andR) { // Cover points for RW CSR registers - property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") - } .otherwise { // Cover points for RO CSR registers - property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") - } - }}) - - val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) - io.vector.foreach { vio => - when (set_vs_dirty) { - assert(reg_mstatus.vs > 0.U) - when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } - reg_mstatus.vs := 3.U - } - } - - val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) - if (coreParams.haveFSDirty) { - when (set_fs_dirty) { - assert(reg_mstatus.fs > 0.U) - when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } - reg_mstatus.fs := 3.U - } - } - - io.fcsr_rm := reg_frm - when (io.fcsr_flags.valid) { - reg_fflags := reg_fflags | io.fcsr_flags.bits - set_fs_dirty := true.B - } - - io.vector.foreach { vio => - when (vio.set_vxsat) { - reg_vxsat.get := true.B - set_vs_dirty := true.B - } - } - - val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall - io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) - when (csr_wen) { - val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */ - val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) - - when (decoded_addr(CSRs.mstatus)) { - val new_mstatus = wdata.asTypeOf(new MStatus()) - reg_mstatus.mie := new_mstatus.mie - reg_mstatus.mpie := new_mstatus.mpie - - if (usingUser) { - reg_mstatus.mprv := new_mstatus.mprv - reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) - if (usingSupervisor) { - reg_mstatus.spp := new_mstatus.spp - reg_mstatus.spie := new_mstatus.spie - reg_mstatus.sie := new_mstatus.sie - reg_mstatus.tw := new_mstatus.tw - reg_mstatus.tsr := new_mstatus.tsr - } - if (usingVM) { - reg_mstatus.mxr := new_mstatus.mxr - reg_mstatus.sum := new_mstatus.sum - reg_mstatus.tvm := new_mstatus.tvm - } - if (usingHypervisor) { - reg_mstatus.mpv := new_mstatus.mpv - reg_mstatus.gva := new_mstatus.gva - } - } - - if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) - reg_mstatus.vs := formVS(new_mstatus.vs) - } - when (decoded_addr(CSRs.misa)) { - val mask = isaStringToMask(isaMaskString).U(xLen.W) - val f = wdata('f' - 'a') - // suppress write if it would cause the next fetch to be misaligned - when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) { - if (coreParams.misaWritable) - reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask - } - } - when (decoded_addr(CSRs.mip)) { - // MIP should be modified based on the value in reg_mip, not the value - // in read_mip, since read_mip.seip is the OR of reg_mip.seip and - // io.interrupts.seip. We don't want the value on the PLIC line to - // inadvertently be OR'd into read_mip.seip. - val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) - if (usingSupervisor) { - reg_mip.ssip := new_mip.ssip - reg_mip.stip := new_mip.stip - reg_mip.seip := new_mip.seip - } - if (usingHypervisor) { - reg_mip.vssip := new_mip.vssip - } - } - when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } - when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } - when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } - if (mtvecWritable) - when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } - when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } - when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } - - if (usingNMI) { - val new_mnstatus = wdata.asTypeOf(new MNStatus()) - when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } - when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } - when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } - when (decoded_addr(CustomCSRs.mnstatus)) { - reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) - reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv - reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software - } - } - - for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { - writeCounter(i + CSR.firstMHPC, c, wdata) - when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } - } - if (coreParams.haveBasicCounters) { - when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero - writeCounter(CSRs.mcycle, reg_cycle, wdata) - writeCounter(CSRs.minstret, reg_instret, wdata) - } - - if (usingFPU) { - when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } - when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } - when (decoded_addr(CSRs.fcsr)) { - set_fs_dirty := true.B - reg_fflags := wdata - reg_frm := wdata >> reg_fflags.getWidth - } - } - if (usingDebug) { - when (decoded_addr(CSRs.dcsr)) { - val new_dcsr = wdata.asTypeOf(new DCSR()) - reg_dcsr.step := new_dcsr.step - reg_dcsr.ebreakm := new_dcsr.ebreakm - if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks - if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku - if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) - if (usingHypervisor) reg_dcsr.v := new_dcsr.v - } - when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } - when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } - reg_dscratch1.foreach { r => - when (decoded_addr(CSRs.dscratch1)) { r := wdata } - } - } - if (usingSupervisor) { - when (decoded_addr(CSRs.sstatus)) { - val new_sstatus = wdata.asTypeOf(new MStatus()) - reg_mstatus.sie := new_sstatus.sie - reg_mstatus.spie := new_sstatus.spie - reg_mstatus.spp := new_sstatus.spp - reg_mstatus.fs := formFS(new_sstatus.fs) - reg_mstatus.vs := formVS(new_sstatus.vs) - if (usingVM) { - reg_mstatus.mxr := new_sstatus.mxr - reg_mstatus.sum := new_sstatus.sum - } - } - when (decoded_addr(CSRs.sip)) { - val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP()) - reg_mip.ssip := new_sip.ssip - } - when (decoded_addr(CSRs.satp)) { - if (usingVM) { - val new_satp = wdata.asTypeOf(new PTBR()) - when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { - reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U - reg_satp.ppn := new_satp.ppn(ppnBits-1,0) - if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) - } - } - } - when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) } - when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } - when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } - when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } - when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } - when (decoded_addr(CSRs.stval)) { reg_stval := wdata } - when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } - when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } - when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } - when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } - } - - if (usingHypervisor) { - when (decoded_addr(CSRs.hstatus)) { - val new_hstatus = wdata.asTypeOf(new HStatus()) - reg_hstatus.gva := new_hstatus.gva - reg_hstatus.spv := new_hstatus.spv - reg_hstatus.spvp := new_hstatus.spvp - reg_hstatus.hu := new_hstatus.hu - reg_hstatus.vtvm := new_hstatus.vtvm - reg_hstatus.vtw := new_hstatus.vtw - reg_hstatus.vtsr := new_hstatus.vtsr - reg_hstatus.vsxl := new_hstatus.vsxl - } - when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } - when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } - when (decoded_addr(CSRs.hgatp)) { - val new_hgatp = wdata.asTypeOf(new PTBR()) - val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) - when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { - reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U - } - reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) - if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) - } - when (decoded_addr(CSRs.hip)) { - val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) - reg_mip.vssip := new_hip.vssip - } - when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) } - when (decoded_addr(CSRs.hvip)) { - val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) - reg_mip.vssip := new_sip.vssip - reg_mip.vstip := new_sip.vstip - reg_mip.vseip := new_sip.vseip - } - when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } - when (decoded_addr(CSRs.htval)) { reg_htval := wdata } - when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } - - val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) - when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } - when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } - - when (decoded_addr(CSRs.vsstatus)) { - val new_vsstatus = wdata.asTypeOf(new MStatus()) - reg_vsstatus.sie := new_vsstatus.sie - reg_vsstatus.spie := new_vsstatus.spie - reg_vsstatus.spp := new_vsstatus.spp - reg_vsstatus.mxr := new_vsstatus.mxr - reg_vsstatus.sum := new_vsstatus.sum - reg_vsstatus.fs := formFS(new_vsstatus.fs) - reg_vsstatus.vs := formVS(new_vsstatus.vs) - } - when (decoded_addr(CSRs.vsip)) { - val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) - reg_mip.vssip := new_vsip.vssip - } - when (decoded_addr(CSRs.vsatp)) { - val new_vsatp = wdata.asTypeOf(new PTBR()) - val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) - when (mode_ok) { - reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U - } - when (mode_ok || !reg_mstatus.v) { - reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) - if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) - } - } - when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) } - when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } - when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } - when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } - when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } - when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } - when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } - } - if (usingUser) { - when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } - when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } - } - if (nBreakpoints > 0) { - when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } - - for ((bp, i) <- reg_bp.zipWithIndex) { - when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) { - when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } - when (decoded_addr(CSRs.tdata3)) { - if (coreParams.mcontextWidth > 0) { - bp.textra.mselect := wdata(bp.textra.mselectPos) - bp.textra.mvalue := wdata >> bp.textra.mvaluePos - } - if (coreParams.scontextWidth > 0) { - bp.textra.sselect := wdata(bp.textra.sselectPos) - bp.textra.svalue := wdata >> bp.textra.svaluePos - } - } - when (decoded_addr(CSRs.tdata1)) { - bp.control := wdata.asTypeOf(bp.control) - - val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain - val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode - val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain - val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode - val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) - val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain) - bp.control.dmode := dMode - when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } - bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode) - } - } - } - } - reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} - reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} - if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { - require(xLen % pmp.cfg.getWidth == 0) - when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { - val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) - pmp.cfg := newCfg - // disallow unreadable but writable PMPs - pmp.cfg.w := newCfg.w && newCfg.r - // can't select a=NA4 with coarse-grained PMPs - if (pmpGranularity.log2 > PMP.lgAlign) - pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) - } - when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { - pmp.addr := wdata - } - } - def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { - val mask = csr.mask.U(xLen.W) - when (decoded_addr(csr.id)) { - reg := (wdata & mask) | (reg & ~mask) - io.wen := true.B - } - } - for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { - writeCustomCSR(io, csr, reg) - } - for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { - writeCustomCSR(io, csr, reg) - } - if (usingVector) { - when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } - when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } - when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } - when (decoded_addr(CSRs.vcsr)) { - set_vs_dirty := true.B - reg_vxsat.get := wdata - reg_vxrm.get := wdata >> 1 - } - } - } - - def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { - val mask = csr.mask.U(xLen.W) - when (io.set) { - reg := (io.sdata & mask) | (reg & ~mask) - } - } - for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { - setCustomCSR(io, csr, reg) - } - for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { - setCustomCSR(io, csr, reg) - } - - io.vector.map { vio => - when (vio.set_vconfig.valid) { - // user of CSRFileNpu is responsible for set_vs_dirty in this case - assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) - reg_vconfig.get := vio.set_vconfig.bits - } - when (vio.set_vstart.valid) { - set_vs_dirty := true.B - reg_vstart.get := vio.set_vstart.bits - } - vio.vstart := reg_vstart.get - vio.vconfig := reg_vconfig.get - vio.vxrm := reg_vxrm.get - - when (reset.asBool) { - reg_vconfig.get.vl := 0.U - reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) - reg_vconfig.get.vtype.vill := true.B - } - } - - when(reset.asBool) { - reg_satp.mode := 0.U - reg_vsatp.mode := 0.U - reg_hgatp.mode := 0.U - } - if (!usingVM) { - reg_satp.mode := 0.U - reg_satp.ppn := 0.U - reg_satp.asid := 0.U - } - if (!usingHypervisor) { - reg_vsatp.mode := 0.U - reg_vsatp.ppn := 0.U - reg_vsatp.asid := 0.U - reg_hgatp.mode := 0.U - reg_hgatp.ppn := 0.U - reg_hgatp.asid := 0.U - } - if (!(asIdBits > 0)) { - reg_satp.asid := 0.U - reg_vsatp.asid := 0.U - } - if (!(vmIdBits > 0)) { - reg_hgatp.asid := 0.U - } - reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) - - if (nBreakpoints <= 1) reg_tselect := 0.U - for (bpc <- reg_bp map {_.control}) { - bpc.ttype := bpc.tType.U - bpc.maskmax := bpc.maskMax.U - bpc.reserved := 0.U - bpc.zero := 0.U - bpc.h := false.B - if (!usingSupervisor) bpc.s := false.B - if (!usingUser) bpc.u := false.B - if (!usingSupervisor && !usingUser) bpc.m := true.B - when (reset.asBool) { - bpc.action := 0.U - bpc.dmode := false.B - bpc.chain := false.B - bpc.r := false.B - bpc.w := false.B - bpc.x := false.B - } - } - for (bpx <- reg_bp map {_.textra}) { - if (coreParams.mcontextWidth == 0) bpx.mselect := false.B - if (coreParams.scontextWidth == 0) bpx.sselect := false.B - } - for (bp <- reg_bp drop nBreakpoints) - bp := 0.U.asTypeOf(new BP()) - for (pmp <- reg_pmp) { - pmp.cfg.res := 0.U - when (reset.asBool) { pmp.reset() } - } - - for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { - t.exception := io.retire >= i.U && exception - t.valid := io.retire > i.U || t.exception - t.insn := insn - t.iaddr := io.pc - t.priv := Cat(reg_debug, reg_mstatus.prv) - t.cause := cause - t.interrupt := cause(xLen-1) - t.tval := io.tval - t.wdata.foreach(_ := DontCare) - } - - def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { - val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 - // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI - val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) - val priority = nonstandard ++ standard - val masks = masksIn.reverse - val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_) - val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) - (any, which) - } - - def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { - (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) - } - - def legalizePrivilege(priv: UInt): UInt = - if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) - else if (usingUser) Fill(2, priv(0)) - else PRV.M.U - - def trimPrivilege(priv: UInt): UInt = - if (usingSupervisor) priv - else legalizePrivilege(priv) - - def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { - if (xLen == 32) { - val hi = lo + CSRs.mcycleh - CSRs.mcycle - when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } - when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } - } else { - when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } - } - } - def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U)) - def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U)) - def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U) - def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) - def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) - def formVS(vs: UInt) = if (usingVector) vs else 0.U -} diff --git a/arch/src/main/scala/framework/rocket/Configs.scala b/arch/src/main/scala/framework/rocket/Configs.scala index 98f81003..47f466d4 100644 --- a/arch/src/main/scala/framework/rocket/Configs.scala +++ b/arch/src/main/scala/framework/rocket/Configs.scala @@ -23,6 +23,7 @@ class WithNBuckyballCores( val prev = up(TilesLocated(`location`), site) val idOffset = up(NumTiles) val big = RocketTileParamsBB( + usingRVVRoCC = true, core = RocketCoreParams( mulDiv = Some(MulDivParams( mulUnroll = 8, diff --git a/arch/src/main/scala/framework/rocket/README.md b/arch/src/main/scala/framework/rocket/README.md deleted file mode 100644 index 40b53a9b..00000000 --- a/arch/src/main/scala/framework/rocket/README.md +++ /dev/null @@ -1,19 +0,0 @@ -# Buckyball Rocket Core Framework - -This directory contains the customized Rocket core implementation in the Buckyball framework. The architecture is built on top of the Chipyard/Rocket-chip framework, with extensive extensions and modifications to support Buckyball's custom RoCC coprocessors. Buckyball's design philosophy is to maintain compatibility with upstream Rocket-chip while implementing functional extensions through parallel class hierarchies, thus avoiding maintenance issues from directly modifying upstream code while fully leveraging Rocket-chip's mature architecture. - -In Chipyard's hierarchy, the top level is the SoC subsystem, responsible for integrating multiple processor cores, cache subsystems, interconnect buses, memory controllers, and various peripherals. Buckyball defines its subsystem implementation through `RocketSubsystem.scala`, where the `RocketSubsystem` class extends Chipyard's `BaseSubsystem` and mixes in multiple traits to obtain necessary functional support. These traits include `InstantiatesHierarchicalElements` for managing hierarchical component instantiation, `HasTileNotificationSinks` and `HasTileInputConstants` for handling inter-tile communication, `CanHavePeripheryCLINT` and `CanHavePeripheryPLIC` for interrupt controller support, and `HasPeripheryDebug` for debug support. Through this multiple inheritance design pattern, Buckyball can reuse most of Chipyard's infrastructure while performing customized extensions where needed. Importantly, `RocketSubsystem` also defines `RocketTileAttachParamsBB` to describe how to connect Buckyball's version of Rocket tiles to the subsystem, with this parameter class specifying tile configuration parameters and cross-clock-domain connection methods. - -One level down is the tile level, where `RocketTileBB.scala` defines the complete implementation of a single Rocket tile. In Chipyard's design, a tile is a relatively independent processing unit containing the processor core, L1 instruction and data caches, optional vector units, RoCC coprocessor interface, and system bus connection interfaces. The `RocketTileBB` class obtains basic tile functionality by extending `BaseTile` while mixing in several key traits. `SinksExternalInterrupts` and `SourcesExternalNotifications` handle reception and transmission of external interrupts and notifications, `HasLazyRoCCBB` is a Buckyball-specific trait for supporting Buckyball's RoCC coprocessor framework, `HasHellaCache` provides the interface to L1 data cache, and `HasICacheFrontend` provides the instruction fetch frontend implementation. This multi-trait composition design allows `RocketTileBB` to obtain all necessary functionality while maintaining code modularity and maintainability. Notably, `RocketTileBB` defines its own parameter type `RocketTileParamsBB`, which contains all tile configuration information including core parameters, cache parameters, BTB parameters, and provides an instantiation interface through the `InstantiableTileParams` trait. - -Inside the tile, the most core component is the processor core itself, implemented by `RocketCoreBB.scala`. This file contains a reimplementation of the original Rocket core, where the `RocketBB` class extends `CoreModule` and mixes in `HasRocketCoreParameters` and `HasRocketCoreIOBB` traits. `CoreModule` provides the basic framework for core modules, `HasRocketCoreParameters` provides access interfaces to various core parameters, while `HasRocketCoreIOBB` defines Buckyball-specific core IO interfaces. The key difference of this IO interface from the standard Rocket core IO is using `RoCCCoreIOBB` instead of standard `RoCCCoreIO`, enabling support for Buckyball-specific RoCC interface extensions. In the core implementation, the most critical modification is instruction decode table handling. The original Rocket core decides whether to include RoCC instruction decode logic based on the `usingRoCC` parameter, but since Buckyball uses `BuildRoCCBB` instead of standard `BuildRoCC`, this causes `usingRoCC` to return false, preventing RoCC instructions from being properly decoded. To solve this problem, Buckyball forces inclusion of `RoCCDecode` in the decode table, ensuring custom instructions can be correctly recognized and processed. - -RoCC coprocessor support is implemented through `LazyRoCCBB.scala`, which defines Buckyball's RoCC framework. The `HasLazyRoCCBB` trait is the core of this framework, responsible for managing RoCC coprocessor instantiation and connections. This trait creates corresponding RoCC instances based on `BuildRoCCBB` configuration and allocates independent CSR address spaces for each RoCC. The `HasLazyRoCCModuleBB` trait handles RoCC connections at the module level, instantiating `RoccCommandRouterBB` for instruction routing. This router decides which specific RoCC instance to send instructions to based on instruction opcode, and also arbitrates responses from different RoCCs before returning them to the core. The router design considers concurrent instruction execution and response ordering, ensuring system correctness and performance. - -`CSRBB.scala` contains a reimplementation of the control and status register subsystem, which is one of the most complex parts of the Buckyball framework. The CSR subsystem handles all control and status register accesses, including standard RISC-V CSRs and Buckyball-specific extended CSRs. This implementation is based on the original Rocket CSR implementation but extended for Buckyball's needs, supporting more flexible CSR address allocation and more complex read/write logic. Particularly for RoCC-related CSRs, Buckyball implements a dynamic address allocation mechanism that allows different RoCC instances to have independent CSR spaces, avoiding address conflicts. - -`RoCCFragments.scala` defines Buckyball's RoCC interface data structures, which maintain compatibility with standard RoCC interfaces while providing additional extension capabilities. This includes extended command formats, response formats, and additional control signals. These interface definitions form the foundation of the entire Buckyball RoCC ecosystem, ensuring correct communication between different components. - -`Configs.scala` contains rich configuration definitions that specify various hardware parameters through Chipyard's configuration system. The configuration system uses functional programming concepts, building complex system configurations through composition of configuration functions. Buckyball's configuration defines how to integrate Buckyball-specific components into the entire system, including RoCC configuration, CSR configuration, and various performance parameter settings. - -The most critical design challenge in the entire architecture lies in parameter passing and configuration consistency. The Chipyard/Rocket-chip framework extensively uses Scala's implicit parameter mechanism and the `Parameters` configuration system, which allows configuration information to be passed and overridden throughout the hardware hierarchy. The main problem Buckyball faces is how to ensure its configuration information (especially RoCC configurations defined in `BuildRoCCBB`) can be correctly passed to all components that need it. Since the original Rocket core only recognizes `BuildRoCC` and is unaware of `BuildRoCCBB`, Buckyball adopts an elegant solution: when `RocketTileBB` creates a `RocketBB` core instance, it dynamically modifies the `Parameters` object passed to the core, merging the contents of `BuildRoCCBB` into `BuildRoCC`. From the core's perspective, Buckyball's RoCC appears just like a standard RoCC, and all logic based on `BuildRoCC` works correctly, including `usingRoCC` parameter calculation, port count calculation, and instruction decode table construction. This design maintains compatibility with upstream code while achieving the functional extensions required by Buckyball, exemplifying an elegant application of the adapter pattern in software engineering. diff --git a/arch/src/main/scala/framework/rocket/RoCCFragments.scala b/arch/src/main/scala/framework/rocket/RoCCFragments.scala deleted file mode 100644 index e5ba7fbe..00000000 --- a/arch/src/main/scala/framework/rocket/RoCCFragments.scala +++ /dev/null @@ -1,39 +0,0 @@ -package framework.rocket - -import chisel3._ - -import org.chipsalliance.cde.config.{Field, Parameters, Config} -import freechips.rocketchip.tile._ -import freechips.rocketchip.diplomacy._ -import framework.rocket.{LazyRoCCBB, BuildRoCCBB} - -import chipyard.{TestSuitesKey, TestSuiteHelper} - -/** - * Map from a tileId to a particular RoCC accelerator - */ -case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) -case object MultiRoCCKeyBB extends Field[Map[Int, Seq[Parameters => LazyRoCCBB]]](Map.empty[Int, Seq[Parameters => LazyRoCCBB]]) - -/** - * Config fragment to enable different RoCCs based on the tileId - */ -class WithMultiRoCC extends Config((site, here, up) => { - case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).tileId, Nil) -}) - -class WithMultiRoCCBB extends Config((site, here, up) => { - case BuildRoCCBB => site(MultiRoCCKeyBB).getOrElse(site(TileKey).tileId, Nil) -}) - - -/** - * Assigns what was previously in the BuildRoCC key to specific harts with MultiRoCCKey - * Must be paired with WithMultiRoCC - */ -class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => { - case BuildRoCC => Nil - case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => - (i -> up(BuildRoCC, site)) - } -}) diff --git a/arch/src/main/scala/framework/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/rocket/RocketCoreBB.scala index ab35490a..8c7e1774 100644 --- a/arch/src/main/scala/framework/rocket/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/rocket/RocketCoreBB.scala @@ -12,7 +12,9 @@ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer import freechips.rocketchip.rocket._ + import framework.rocket.RoCCCoreIOBB +import framework.rocket.id.RVVRoCCDecode trait HasRocketCoreIOBB extends HasRocketCoreParameters { @@ -103,6 +105,14 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) extends CoreModule()( val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen + + val usingRVVRoCC = tile.rocketParams.usingRVVRoCC + + // Ensure usingVector and usingRVVRoCC are mutually exclusive + require(!usingVector || !usingRVVRoCC, + "usingVector and usingRVVRoCC cannot both be enabled. " + + "Use usingVector for built-in vector unit, or usingRVVRoCC to route vector instructions to RoCC.") + val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: @@ -110,6 +120,7 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) extends CoreModule()( (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: + (usingRVVRoCC.option(new RVVRoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: @@ -226,7 +237,7 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) extends CoreModule()( val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt - val csr = Module(new CSRFileBB(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) + val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U diff --git a/arch/src/main/scala/framework/rocket/RocketTileBB.scala b/arch/src/main/scala/framework/rocket/RocketTileBB.scala index 346e6b19..26764db9 100644 --- a/arch/src/main/scala/framework/rocket/RocketTileBB.scala +++ b/arch/src/main/scala/framework/rocket/RocketTileBB.scala @@ -42,7 +42,9 @@ case class RocketTileParamsBB( beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), - boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None + boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None, + + usingRVVRoCC: Boolean = false ) extends InstantiableTileParams[RocketTileBB] { require(icache.isDefined) require(dcache.isDefined) diff --git a/arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala b/arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala new file mode 100644 index 00000000..b6f91ed4 --- /dev/null +++ b/arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala @@ -0,0 +1,75 @@ +// See LICENSE.Berkeley for license details. +// See LICENSE.SiFive for license details. + +package framework.rocket.id + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.rocket._ +import freechips.rocketchip.rocket.Instructions._ +import freechips.rocketchip.rocket.ALU._ +import freechips.rocketchip.rocket.constants.ScalarOpConstants +import freechips.rocketchip.rocket.constants.MemoryOpConstants +import freechips.rocketchip.util._ + +/** + * RVVRoCCDecode - Decoder for RVV (RISC-V Vector) instructions marked as RoCC + * + * This decoder takes standard RVV instructions and marks them as RoCC instructions, + * allowing them to be handled by a RoCC accelerator instead of the built-in vector unit. + * + * Usage: Enable by setting usingRVVRoCC parameter to true in RocketTileParamsBB + * Note: usingVector and usingRVVRoCC cannot both be true simultaneously + * + * This decoder uses opcode-based matching patterns instead of listing all 447 RVV instructions + * individually to avoid JVM method size limits and memory issues during decode minimization. + * + * RVV instruction opcodes: + * - 1010111 (0x57): V-type arithmetic/logic instructions, vector config + * - 0000111 (0x07): Vector load instructions (funct3 != 010) + * - 0100111 (0x27): Vector store instructions (funct3 != 010) + * + * Note: This decoder uses wildcard patterns that may match invalid encodings. + * The RoCC accelerator should validate instructions and handle illegal opcodes appropriately. + */ +class RVVRoCCDecode(implicit val p: Parameters) extends DecodeConstants with ScalarOpConstants with MemoryOpConstants +{ + import freechips.rocketchip.rocket.Instructions._ + + // Common decode signals for RVV instructions (rocc field set to Y) + // Most RVV instructions don't read scalar registers by default (overridden by specific patterns) + private val rvvRoCCBase: List[BitPat] = List(Y,N,Y,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N) + + // Vector configuration instructions need wxd=Y and may read rs1 + private val vcfgSigs: List[BitPat] = List(Y,N,Y,N,N,N,N,Y,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N) + private val vcfgImmSigs: List[BitPat] = List(Y,N,Y,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N) + + val table: Array[(BitPat, List[BitPat])] = Array( + // All V-type instructions (opcode = 1010111) + // This includes VSETVL, VSETVLI, VSETIVLI and all arithmetic/logic vector instructions + // Note: VSET* instructions should ideally have wxd=Y and rxs1=Y, but we use uniform + // decode signals here to avoid pattern overlap issues. The RoCC accelerator should + // handle the detailed decoding of vset instructions. + BitPat("b?????????????????????????????????1010111") -> rvvRoCCBase, + + // Vector load instructions (opcode = 0000111, funct3 = 000/101/110/111) + // funct3=101: VLE16, VLE256, etc. + // funct3=110: VLE32, VLE512, etc. + // funct3=111: VLE64, VLE1024, etc. + BitPat("b?????????????????000?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????101?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????110?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????111?????0000111") -> rvvRoCCBase, + + // Vector store instructions (opcode = 0100111, but NOT funct3=010 which is FP store) + // funct3=000: VSE8, VSE128, VS*R, etc. + // funct3=101: VSE16, VSE256, etc. + // funct3=110: VSE32, VSE512, etc. + // funct3=111: VSE64, VSE1024, etc. + BitPat("b?????????????????000?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????101?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????110?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????111?????0100111") -> rvvRoCCBase + ) +} diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 212ec222..06fd0226 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -133,6 +133,7 @@ add_cross_platform_test_target(ctest_abft_systolic_test abft_systolic_test.c) add_cross_platform_test_target(ctest_conv_test conv_test.c) add_cross_platform_test_target(ctest_cim_test cim_test.c) add_cross_platform_test_target(ctest_transfer_test transfer_test.c) +add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) # Create library dependency target to ensure all libraries are built first # add_custom_target(buckyball-libs-build @@ -173,5 +174,6 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_conv_test ctest_cim_test ctest_transfer_test + ctest_vsetvli COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/test_vsetvli.c b/bb-tests/workloads/src/CTest/toy/test_vsetvli.c new file mode 100644 index 00000000..1e1a94ef --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/test_vsetvli.c @@ -0,0 +1,20 @@ +#include + +int main() { + printf("Testing RVV RoCC decode with VSETVLI\n"); + + register unsigned long vl asm("a0"); + + // vsetvli a0, zero, e32, m1, ta, ma + // opcode=1010111, rd=a0(x10), funct3=111, rs1=x0, zimm=0x08 + // Encoding: 0000 0000 1000 00000 111 01010 1010111 + // = 0x0080d557 + asm volatile(".word 0x0080d557\n" // vsetvli a0, x0, 0x08 (e32, m1) + : "=r"(vl) + : + : "memory"); + + printf("VSETVLI executed, vl = %lu\n", vl); + printf("Test PASSED\n"); + return 0; +} diff --git a/docs/bb-note/src/SUMMARY.md b/docs/bb-note/src/SUMMARY.md index 1d3dc767..63297bfc 100644 --- a/docs/bb-note/src/SUMMARY.md +++ b/docs/bb-note/src/SUMMARY.md @@ -8,7 +8,6 @@ - [Scala Source Code](./arch/src/main/scala/README.md) - [Util](./arch/src/main/scala/Util/README.md) - [framework](./arch/src/main/scala/framework/README.md) - - [rocket](./arch/src/main/scala/framework/rocket/README.md) - [prototype](./arch/src/main/scala/prototype/README.md) - [format](./arch/src/main/scala/prototype/format/README.md) - [im2col](./arch/src/main/scala/prototype/im2col/README.md) diff --git a/docs/bb-note/src/arch/src/main/scala/framework/rocket/README.md b/docs/bb-note/src/arch/src/main/scala/framework/rocket/README.md deleted file mode 120000 index 72c54f5b..00000000 --- a/docs/bb-note/src/arch/src/main/scala/framework/rocket/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/framework/rocket/README.md \ No newline at end of file From 87667fe566928baff9f5f853d8277aaba1e3b032 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 15 Dec 2025 12:01:35 +0800 Subject: [PATCH 007/238] [arch/rocket] fix: add other insts' routing in RoCC CmdRouter --- .../scala/framework/rocket/LazyRoCCBB.scala | 38 ++++++++++++++----- .../scala/framework/rocket/RocketCoreBB.scala | 2 +- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala index 34643f95..e6192fbb 100644 --- a/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala +++ b/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala @@ -93,7 +93,9 @@ trait HasLazyRoCCModuleBB extends CanHavePTWModule val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) { val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) - val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p)) + // Get usingRVVRoCC from tile parameters + val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC + val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) outer.roccs.zipWithIndex.foreach { case (rocc, i) => rocc.module.io.ptw ++=: ptwPorts rocc.module.io.cmd <> cmdRouter.io.out(i) @@ -110,24 +112,40 @@ trait HasLazyRoCCModuleBB extends CanHavePTWModule } -class RoccCommandRouterBB(opcodes: Seq[OpcodeSet])(implicit p: Parameters) +class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { - val in = Flipped(Decoupled(new RoCCCommandBB)) - val out = Vec(opcodes.size, Decoupled(new RoCCCommandBB)) + val in = Flipped(Decoupled(new RoCCCommand)) + val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) val busy = Output(Bool()) }) val cmd = Queue(io.in) - val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) => - val me = opcode.matches(cmd.bits.inst.opcode) - out.valid := cmd.valid && me + + // Check which opcodes match + val opcodeMatches = opcodes.map(opcode => opcode.matches(cmd.bits.inst.opcode)) + val anyMatch = opcodeMatches.reduce(_ || _) + + val cmdReadys = io.out.zip(opcodeMatches).zipWithIndex.map { case ((out, matches), i) => + // In RVVRoCC mode: route unmatched opcodes to first RoCC (index 0) + // Otherwise: only route if opcode matches + val shouldRoute = if (usingRVVRoCC && i == 0) { + matches || !anyMatch // First RoCC gets matched opcodes OR unmatched opcodes + } else { + matches // Other RoCCs only get their matched opcodes + } + + out.valid := cmd.valid && shouldRoute out.bits := cmd.bits - out.ready && me + out.ready && shouldRoute } cmd.ready := cmdReadys.reduce(_ || _) io.busy := cmd.valid - assert(PopCount(cmdReadys) <= 1.U, - "Custom opcode matched for more than one accelerator") + // In RVVRoCC mode, allow unmatched opcodes to go to first RoCC + // Otherwise, assert that only one RoCC matches + if (!usingRVVRoCC) { + assert(PopCount(cmdReadys) <= 1.U, + "Custom opcode matched for more than one accelerator") + } } diff --git a/arch/src/main/scala/framework/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/rocket/RocketCoreBB.scala index 8c7e1774..304b3f8e 100644 --- a/arch/src/main/scala/framework/rocket/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/rocket/RocketCoreBB.scala @@ -116,11 +116,11 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) extends CoreModule()( val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: + (usingRVVRoCC.option(new RVVRoCCDecode)) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: - (usingRVVRoCC.option(new RVVRoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: From 6644183e9a4e62c77025622d06c7e3dbf2261b78 Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Tue, 16 Dec 2025 17:15:42 +0800 Subject: [PATCH 008/238] change the framework of memdomain for the preparation of virtualization (#18) --- .../framework/memdomain/MemController.scala | 139 +++++++++++++++--- .../scala/framework/memdomain/MemDomain.scala | 91 +++++------- .../framework/memdomain/Translator.scala | 31 ++++ 3 files changed, 183 insertions(+), 78 deletions(-) create mode 100644 arch/src/main/scala/framework/memdomain/Translator.scala diff --git a/arch/src/main/scala/framework/memdomain/MemController.scala b/arch/src/main/scala/framework/memdomain/MemController.scala index 891c802b..0ed8df63 100644 --- a/arch/src/main/scala/framework/memdomain/MemController.scala +++ b/arch/src/main/scala/framework/memdomain/MemController.scala @@ -4,42 +4,133 @@ import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.frontend.decoder.PostGDCmd +import freechips.rocketchip.tile._ +import framework.memdomain.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} import framework.memdomain.mem.{SramReadIO, SramWriteIO, Scratchpad} +import framework.memdomain.{MemLoader, MemStorer, MemController} +import framework.memdomain.rs.MemReservationStation +import framework.memdomain.tlb.{BBTLBCluster, BBTLBIO, BBTLBExceptionIO} +import framework.memdomain.pmc.MemCyclePMC +import freechips.rocketchip.tilelink.TLEdgeOut +import freechips.rocketchip.rocket.TLBPTWIO +import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} +import framework.switcher.{ToPhysicalLine, ToVirtualLine} /** * MemController: Controller that encapsulates scratchpad and accumulator * Provides DMA interface and Ball Domain interface */ -class MemController(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +class MemController(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOut) extends Module { + private val numBanks = b.sp_banks + b.acc_banks val io = IO(new Bundle { - // DMA interface - for MemLoader and MemStorer access - val dma = new Bundle { - val sramRead = Vec(b.sp_banks, new SramReadIO(b.spad_bank_entries, b.spad_w)) - val sramWrite = Vec(b.sp_banks, new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - val accRead = Vec(b.acc_banks, new SramReadIO(b.acc_bank_entries, b.acc_w)) - val accWrite = Vec(b.acc_banks, new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len)) + // Issue interface from global RS (single channel) + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) + + // Report completion to global RS (single channel) + val global_complete_o = Decoupled(new GlobalRsComplete) + + // SRAM read/write interface - used by load/store + val interdma = new Bundle { + val sramread = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) + val sramwrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + val accread = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) + val accwrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) } - // Ball Domain interface - for BallController access - val ballDomain = new Bundle { - val sramRead = Vec(b.sp_banks, new SramReadIO(b.spad_bank_entries, b.spad_w)) - val sramWrite = Vec(b.sp_banks, new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - val accRead = Vec(b.acc_banks, new SramReadIO(b.acc_bank_entries, b.acc_w)) - val accWrite = Vec(b.acc_banks, new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len)) + // DMA interface - used by Outer DRAM controller + val intradma = new Bundle { + val read = new Bundle { + val req = Decoupled(new BBReadRequest()) + val resp = Flipped(Decoupled(new BBReadResponse(b.spad_w))) + } + val write = new Bundle { + val req = Decoupled(new BBWriteRequest(b.spad_w)) + val resp = Flipped(Decoupled(new BBWriteResponse)) + } } + + // TLB interface - exposed externally for DMA use + val tlb = Vec(2, Flipped(new BBTLBIO)) + + // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) + val ptw = Vec(1, new TLBPTWIO) + + // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) + val tlbExp = Vec(1, new BBTLBExceptionIO) + + // Busy signal + val busy = Output(Bool()) }) - val spad = Module(new Scratchpad(b)) + val memDecoder = Module(new MemDomainDecoder) + val memRs = Module(new MemReservationStation) + val memLoader = Module(new MemLoader) + val memStorer = Module(new MemStorer) + // TLB cluster - use shared TLB like Gemmini + val tlbCluster = Module(new BBTLBCluster(2, b.tlb_size, b.dma_maxbytes, use_shared_tlb = true)) + +// ----------------------------------------------------------------------------- +// Global RS -> MemDecoder +// ----------------------------------------------------------------------------- + memDecoder.io.raw_cmd_i.valid := io.global_issue_i.valid + memDecoder.io.raw_cmd_i.bits := io.global_issue_i.bits.cmd + io.global_issue_i.ready := memDecoder.io.raw_cmd_i.ready + +// ----------------------------------------------------------------------------- +// MemDecoder -> MemReservationStation +// ----------------------------------------------------------------------------- + // Connect decoded instruction and global rob_id + memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid + memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits + memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id + memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready + +// ----------------------------------------------------------------------------- +// MemReservationStation -> MemLoader/MemStorer +// ----------------------------------------------------------------------------- + memLoader.io.cmdReq <> memRs.io.issue_o.ld + memStorer.io.cmdReq <> memRs.io.issue_o.st + memRs.io.commit_i.ld <> memLoader.io.cmdResp + memRs.io.commit_i.st <> memStorer.io.cmdResp + +//----------------------------------------------------------------------------- +// PMC - Performance Monitor Counter +// ----------------------------------------------------------------------------- + val pmc = Module(new MemCyclePMC) + pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire + pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits + pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire + pmc.io.stReq_i.bits := memRs.io.issue_o.st.bits + pmc.io.ldResp_o.valid := memLoader.io.cmdResp.fire + pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits + pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire + pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits +// + // Connect MemLoader and MemStorer to DMA + memLoader.io.dmaReq <> io.intradma.read.req + io.intradma.read.resp <> memLoader.io.dmaResp + memStorer.io.dmaReq <> io.intradma.write.req + io.intradma.write.resp <> memStorer.io.dmaResp + + // Connect TLB - now using internal BBTLBCluster + io.tlb <> tlbCluster.io.clients + io.ptw <> tlbCluster.io.ptw + + // Connect exception interface - note direction: internal TLB's exp is Output, external interface is Input + tlbCluster.io.exp <> io.tlbExp + + // Connect MemLoader and MemStorer to MemController's DMA interface + memLoader.io.sramWrite <> io.interdma.sramwrite + memLoader.io.accWrite <>io.interdma.accwrite + memStorer.io.sramRead <> io.interdma.sramread + memStorer.io.accRead <> io.interdma.accread - // Connect DMA interface to Scratchpad's DMA ports - io.dma.sramRead <> spad.io.dma.sramread - io.dma.sramWrite <> spad.io.dma.sramwrite - io.dma.accRead <> spad.io.dma.accread - io.dma.accWrite <> spad.io.dma.accwrite + // Completion signal connected to global RS + io.global_complete_o <> memRs.io.complete_o - // Connect Ball Domain interface to Scratchpad's execution ports - io.ballDomain.sramRead <> spad.io.exec.sramread - io.ballDomain.sramWrite <> spad.io.exec.sramwrite - io.ballDomain.accRead <> spad.io.exec.accread - io.ballDomain.accWrite <> spad.io.exec.accwrite + // Busy signal + // Simple busy signal + io.busy := !memRs.io.complete_o.ready } diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 9d3e9ef5..4881eb03 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -7,7 +7,7 @@ import examples.BuckyballConfigs.CustomBuckyballConfig import framework.frontend.decoder.PostGDCmd import freechips.rocketchip.tile._ import framework.memdomain.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} -import framework.memdomain.mem.{SramReadIO, SramWriteIO} +import framework.memdomain.mem.{SramReadIO, SramWriteIO, Scratchpad} import framework.memdomain.{MemLoader, MemStorer, MemController} import framework.memdomain.rs.MemReservationStation import framework.memdomain.tlb.{BBTLBCluster, BBTLBIO, BBTLBExceptionIO} @@ -58,73 +58,48 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu val busy = Output(Bool()) }) - val memDecoder = Module(new MemDomainDecoder) - val memRs = Module(new MemReservationStation) - val memLoader = Module(new MemLoader) - val memStorer = Module(new MemStorer) - - // Internal MemController (encapsulates spad and acc) val memController = Module(new MemController) - - // TLB cluster - use shared TLB like Gemmini - val tlbCluster = Module(new BBTLBCluster(2, b.tlb_size, b.dma_maxbytes, use_shared_tlb = true)) + val translator = Module(new Translator) + val spad = Module(new Scratchpad(b)) // ----------------------------------------------------------------------------- // Global RS -> MemDecoder // ----------------------------------------------------------------------------- - memDecoder.io.raw_cmd_i.valid := io.global_issue_i.valid - memDecoder.io.raw_cmd_i.bits := io.global_issue_i.bits.cmd - io.global_issue_i.ready := memDecoder.io.raw_cmd_i.ready + memController.io.global_issue_i.valid := io.global_issue_i.valid + memController.io.global_issue_i.bits.cmd := io.global_issue_i.bits.cmd + io.global_issue_i.ready := memController.io.global_issue_i.ready // ----------------------------------------------------------------------------- // MemDecoder -> MemReservationStation // ----------------------------------------------------------------------------- // Connect decoded instruction and global rob_id - memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid - memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits - memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id - memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready + memController.io.global_issue_i.bits.rob_id := io.global_issue_i.bits.rob_id -// ----------------------------------------------------------------------------- -// MemReservationStation -> MemLoader/MemStorer -// ----------------------------------------------------------------------------- - memLoader.io.cmdReq <> memRs.io.issue_o.ld - memStorer.io.cmdReq <> memRs.io.issue_o.st - memRs.io.commit_i.ld <> memLoader.io.cmdResp - memRs.io.commit_i.st <> memStorer.io.cmdResp - -// ----------------------------------------------------------------------------- -// PMC - Performance Monitor Counter -// ----------------------------------------------------------------------------- - val pmc = Module(new MemCyclePMC) - pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire - pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits - pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire - pmc.io.stReq_i.bits := memRs.io.issue_o.st.bits - pmc.io.ldResp_o.valid := memLoader.io.cmdResp.fire - pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits - pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire - pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits // Connect MemLoader and MemStorer to DMA - memLoader.io.dmaReq <> io.dma.read.req - io.dma.read.resp <> memLoader.io.dmaResp - memStorer.io.dmaReq <> io.dma.write.req - io.dma.write.resp <> memStorer.io.dmaResp + memController.io.intradma.read.req <> io.dma.read.req + io.dma.read.resp <> memController.io.intradma.read.resp + memController.io.intradma.write.req <> io.dma.write.req + io.dma.write.resp <> memController.io.intradma.write.resp // Connect TLB - now using internal BBTLBCluster - io.tlb <> tlbCluster.io.clients - io.ptw <> tlbCluster.io.ptw + io.tlb <> memController.io.tlb + io.ptw <> memController.io.ptw // Connect exception interface - note direction: internal TLB's exp is Output, external interface is Input - tlbCluster.io.exp <> io.tlbExp + memController.io.tlbExp <> io.tlbExp // Connect MemLoader and MemStorer to MemController's DMA interface - memLoader.io.sramWrite <> memController.io.dma.sramWrite - memLoader.io.accWrite <> memController.io.dma.accWrite - memStorer.io.sramRead <> memController.io.dma.sramRead - memStorer.io.accRead <> memController.io.dma.accRead + memController.io.interdma.sramwrite <> translator.io.dma_in.sramwrite + memController.io.interdma.accwrite <>translator.io.dma_in.accwrite + memController.io.interdma.sramread <> translator.io.dma_in.sramread + memController.io.interdma.accread <> translator.io.dma_in.accread + + translator.io.dma_out.sramwrite <> spad.io.dma.sramwrite + translator.io.dma_out.accwrite <> spad.io.dma.accwrite + translator.io.dma_out.sramread <> spad.io.dma.sramread + translator.io.dma_out.accread <> spad.io.dma.accread // ToPhysical interface // Ball Domain SRAM interface connected to MemController's Ball Domain interface @@ -133,15 +108,23 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu toPhysicalLines.io.sramRead_i <> io.ballDomain.sramRead toPhysicalLines.io.sramWrite_i <> io.ballDomain.sramWrite - toPhysicalLines.io.sramRead_o <> memController.io.ballDomain.sramRead - toPhysicalLines.io.sramWrite_o <> memController.io.ballDomain.sramWrite - toPhysicalLines.io.accRead_o <> memController.io.ballDomain.accRead - toPhysicalLines.io.accWrite_o <> memController.io.ballDomain.accWrite + toPhysicalLines.io.sramRead_o <> translator.io.exec_in.sramread + toPhysicalLines.io.sramWrite_o <> translator.io.exec_in.sramwrite + toPhysicalLines.io.accRead_o <> translator.io.exec_in.accread + toPhysicalLines.io.accWrite_o <> translator.io.exec_in.accwrite + + translator.io.exec_out.sramread <> spad.io.exec.sramread + translator.io.exec_out.sramwrite <> spad.io.exec.sramwrite + translator.io.exec_out.accread <> spad.io.exec.accread + translator.io.exec_out.accwrite <> spad.io.exec.accwrite + // translator.io.dma_return := DontCare + // translator.io.exec_return := DontCare + // Completion signal connected to global RS - io.global_complete_o <> memRs.io.complete_o + io.global_complete_o <> memController.io.global_complete_o // Busy signal // Simple busy signal - io.busy := !memRs.io.complete_o.ready + io.busy := memController.io.busy } diff --git a/arch/src/main/scala/framework/memdomain/Translator.scala b/arch/src/main/scala/framework/memdomain/Translator.scala new file mode 100644 index 00000000..e45cdf7f --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/Translator.scala @@ -0,0 +1,31 @@ +package framework.memdomain + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.mem.{SramReadIO, SramWriteIO} + +class Translator(implicit b: CustomBuckyballConfig, p: Parameters) extends Module{ + class BanksIO extends Bundle { + val sramread = Vec(b.sp_banks, new SramReadIO(b.spad_bank_entries, b.spad_w)) + val sramwrite = Vec(b.sp_banks, new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) + val accread = Vec(b.acc_banks, new SramReadIO(b.acc_bank_entries, b.acc_w)) + val accwrite = Vec(b.acc_banks, new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len)) + } + + val io = IO(new Bundle { + val dma_in = new BanksIO + // val dma_return = Flipped(new BanksIO) + val dma_out = Flipped(new BanksIO) + val exec_in = new BanksIO + // val exec_return = Flipped(new BanksIO) + val exec_out = Flipped(new BanksIO) + }) + + io.dma_out <> io.dma_in + // io.dma_return <> io.dma_in + io.exec_out <> io.exec_in + // io.exec_return <> io.exec_in +} + From 51013ee99491d3d29d1808fad75ffaa0bd1e8dbd Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 16 Dec 2025 17:28:20 +0800 Subject: [PATCH 009/238] [arch/gpdomain] feat: add rvv decoder in sequncer [compiler] update: bump to the latest version --- arch/build.sc | 45 -- .../frontend/decoder/GobalDecoder.scala | 13 +- .../main/scala/framework/gpdomain/DISA.scala | 85 --- .../scala/framework/gpdomain/GPDomain.scala | 14 +- .../gpdomain/sequencer/decoder/DISA.scala | 18 + .../gpdomain/sequencer/decoder/Decoder.scala | 538 ++++++++++++++++++ .../sequencer/decoder/DomainDecoder.scala | 54 ++ .../decoder/InstructionDatabase.scala | 357 ++++++++++++ .../decoder/InstructionDocumentation.scala | 465 +++++++++++++++ .../sequencer/decoder/T1DecodePattern.scala | 192 +++++++ .../sequencer/decoder/TableGenerator.scala | 180 ++++++ .../decoder/attribute/adderUop.scala | 185 ++++++ .../sequencer/decoder/attribute/divUop.scala | 64 +++ .../decoder/attribute/floatUop.scala | 178 ++++++ .../decoder/attribute/fpExecutionType.scala | 37 ++ .../sequencer/decoder/attribute/isAdder.scala | 124 ++++ .../decoder/attribute/isAverage.scala | 87 +++ .../decoder/attribute/isCompress.scala | 35 ++ .../decoder/attribute/isCrossread.scala | 72 +++ .../decoder/attribute/isCrosswrite.scala | 112 ++++ .../decoder/attribute/isDivider.scala | 46 ++ .../attribute/isDontneedexecuteinlane.scala | 150 +++++ .../decoder/attribute/isExtend.scala | 39 ++ .../decoder/attribute/isFcompare.scala | 49 ++ .../sequencer/decoder/attribute/isFfo.scala | 38 ++ .../decoder/attribute/isFirstwiden.scala | 69 +++ .../sequencer/decoder/attribute/isFloat.scala | 128 +++++ .../decoder/attribute/isFloatmul.scala | 38 ++ .../decoder/attribute/isFloattype.scala | 137 +++++ .../sequencer/decoder/attribute/isFma.scala | 58 ++ .../decoder/attribute/isFother.scala | 49 ++ .../decoder/attribute/isGather.scala | 38 ++ .../decoder/attribute/isGather16.scala | 35 ++ .../sequencer/decoder/attribute/isId.scala | 92 +++ .../decoder/attribute/isIndextype.scala | 65 +++ .../sequencer/decoder/attribute/isIota.scala | 35 ++ .../sequencer/decoder/attribute/isItype.scala | 70 +++ .../sequencer/decoder/attribute/isLogic.scala | 54 ++ .../decoder/attribute/isMaskPipeType.scala | 114 ++++ .../decoder/attribute/isMaskdestination.scala | 74 +++ .../decoder/attribute/isMasklogic.scala | 48 ++ .../decoder/attribute/isMasksource.scala | 57 ++ .../decoder/attribute/isMaskunit.scala | 94 +++ .../decoder/attribute/isMulticycle.scala | 137 +++++ .../decoder/attribute/isMultiplier.scala | 64 +++ .../sequencer/decoder/attribute/isMv.scala | 38 ++ .../decoder/attribute/isNarrow.scala | 46 ++ .../sequencer/decoder/attribute/isNr.scala | 38 ++ .../decoder/attribute/isOrderreduce.scala | 34 ++ .../sequencer/decoder/attribute/isOther.scala | 60 ++ .../decoder/attribute/isPopcount.scala | 35 ++ .../decoder/attribute/isReadonly.scala | 42 ++ .../sequencer/decoder/attribute/isRed.scala | 51 ++ .../decoder/attribute/isReverse.scala | 35 ++ .../decoder/attribute/isSaturate.scala | 97 ++++ .../decoder/attribute/isScheduler.scala | 277 +++++++++ .../sequencer/decoder/attribute/isShift.scala | 54 ++ .../sequencer/decoder/attribute/isSlid.scala | 42 ++ .../decoder/attribute/isSpecial.scala | 149 +++++ .../decoder/attribute/isSpecialslot.scala | 153 +++++ .../decoder/attribute/isSreadvd.scala | 310 ++++++++++ .../decoder/attribute/isSwrite.scala | 167 ++++++ .../decoder/attribute/isTargetrd.scala | 37 ++ .../decoder/attribute/isUnorderwrite.scala | 48 ++ .../decoder/attribute/isUnsigned0.scala | 171 ++++++ .../decoder/attribute/isUnsigned1.scala | 132 +++++ .../decoder/attribute/isVector.scala | 32 ++ .../sequencer/decoder/attribute/isVtype.scala | 202 +++++++ .../decoder/attribute/isVwmacc.scala | 41 ++ .../decoder/attribute/isWidenreduce.scala | 82 +++ .../decoder/attribute/isWriteCount.scala | 94 +++ .../sequencer/decoder/attribute/isZero.scala | 53 ++ .../sequencer/decoder/attribute/isZvbb.scala | 52 ++ .../sequencer/decoder/attribute/isZvma.scala | 55 ++ .../decoder/attribute/logicUop.scala | 93 +++ .../decoder/attribute/maskPipeOpcode.scala | 179 ++++++ .../sequencer/decoder/attribute/mulUop.scala | 94 +++ .../decoder/attribute/otherUop.scala | 114 ++++ .../sequencer/decoder/attribute/package.scala | 37 ++ .../decoder/attribute/shiftUop.scala | 77 +++ .../sequencer/decoder/attribute/topUop.scala | 297 ++++++++++ .../sequencer/decoder/attribute/uop.scala | 30 + .../sequencer/decoder/attribute/zeroUop.scala | 44 ++ .../sequencer/decoder/attribute/zvbbUop.scala | 103 ++++ compiler | 2 +- 85 files changed, 8188 insertions(+), 142 deletions(-) delete mode 100644 arch/src/main/scala/framework/gpdomain/DISA.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala diff --git a/arch/build.sc b/arch/build.sc index dd0a9f97..bd0857fe 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -7,7 +7,6 @@ import scalalib._ // support BSP import mill.bsp._ - object buckyball extends SbtModule { m => override def millSourcePath = os.pwd override def scalaVersion = "2.13.12" @@ -914,47 +913,3 @@ object palladium extends SbtModule { "-Ymacro-annotations" ) } - -// uvbb测试模块 -// object uvbb extends ScalaModule { -// override def millSourcePath = os.pwd / os.up / "bb-tests" / "uvbb" -// override def scalaVersion = "2.13.12" - -// override def scalacOptions = Seq( -// "-language:reflectiveCalls", -// "-deprecation", -// "-feature", -// "-Xcheckinit", -// "-Ymacro-annotations" -// ) - -// // 依赖buckyball模块 -// override def moduleDeps = Seq(buckyball) - -// override def ivyDeps = Agg( -// ivy"org.chipsalliance::chisel:6.5.0" -// ) - -// override def scalacPluginIvyDeps = Agg( -// ivy"org.chipsalliance:::chisel-plugin:6.5.0" -// ) - -// // 包含dut源码路径 -// override def sources = T.sources { -// super.sources() ++ Seq( -// PathRef(millSourcePath / "dut" / "src" / "main" / "scala") -// ) -// } - -// // 包含resources路径 -// override def resources = T.sources { -// super.resources() ++ Seq( -// PathRef(millSourcePath / "dut" / "src" / "main" / "resources") -// ) -// } - -// // 生成Verilog的任务 -// def elaborate = T { -// runMain("uvbb.Elaborate")() -// } -// } diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index 5a0564c8..d410f6e1 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -6,9 +6,10 @@ import chisel3.stage._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import freechips.rocketchip.tile._ -import framework.memdomain.DISA._ -import framework.gpdomain.DISA._ + import framework.frontend.decoder.GISA._ +import framework.memdomain.DISA._ +import framework.gpdomain.sequencer.decoder.DISA._ class BuckyballRawCmd(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand @@ -34,11 +35,11 @@ class GlobalDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Mo val opcode = io.id_i.bits.cmd.inst.opcode // Instruction type determination: distinguish Ball, Mem, Fence, GP (RVV) instructions - val is_mem_inst = (func7 === MVIN_BITPAT) || (func7 === MVOUT_BITPAT) - val is_frontend_inst = (func7 === FENCE_BITPAT) + val is_mem_inst = (func7 === MVIN_BITPAT) || (func7 === MVOUT_BITPAT) + val is_frontend_inst = (func7 === FENCE_BITPAT) // RVV instructions: opcode 0x57 (vector compute), 0x07 (vector load), 0x27 (vector store) - val is_gp_inst = (opcode === RVV_OPCODE_V) || (opcode === RVV_OPCODE_VL) || (opcode === RVV_OPCODE_VS) - val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_gp_inst + val is_gp_inst = (opcode === RVV_OPCODE_V) || (opcode === RVV_OPCODE_VL) || (opcode === RVV_OPCODE_VS) + val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_gp_inst // Encode domain ID val domain_id = MuxCase(DomainId.BALL, Seq( diff --git a/arch/src/main/scala/framework/gpdomain/DISA.scala b/arch/src/main/scala/framework/gpdomain/DISA.scala deleted file mode 100644 index 47891756..00000000 --- a/arch/src/main/scala/framework/gpdomain/DISA.scala +++ /dev/null @@ -1,85 +0,0 @@ -package framework.gpdomain - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ - - -class BuckyballRawCmd(implicit p: Parameters) extends Bundle { - val cmd = new RoCCCommand -} - -object DISA { - // RVV Instruction Opcodes - val RVV_OPCODE_V = "b1010111".U // 0x57: OP-V (vector compute) - val RVV_OPCODE_VL = "b0000111".U // 0x07: LOAD-FP (vector load) - val RVV_OPCODE_VS = "b0100111".U // 0x27: STORE-FP (vector store) - - // RVV Vector Compute Instructions (opcode 0x57, func3=0-6) - // func7 field [31:25] for vector arithmetic instructions - val VADD_VV = BitPat("b0000000") // 0x00: vadd.vv - val VADD_VX = BitPat("b0000000") // 0x00: vadd.vx - val VADD_VI = BitPat("b0000000") // 0x00: vadd.vi - val VSUB_VV = BitPat("b0000010") // 0x02: vsub.vv - val VSUB_VX = BitPat("b0000010") // 0x02: vsub.vx - val VRSUB_VX = BitPat("b0000011") // 0x03: vrsub.vx - val VRSUB_VI = BitPat("b0000011") // 0x03: vrsub.vi - - val VMINU_VV = BitPat("b0000100") // 0x04: vminu.vv - val VMINU_VX = BitPat("b0000100") // 0x04: vminu.vx - val VMIN_VV = BitPat("b0000101") // 0x05: vmin.vv - val VMIN_VX = BitPat("b0000101") // 0x05: vmin.vx - val VMAXU_VV = BitPat("b0000110") // 0x06: vmaxu.vv - val VMAXU_VX = BitPat("b0000110") // 0x06: vmaxu.vx - val VMAX_VV = BitPat("b0000111") // 0x07: vmax.vv - val VMAX_VX = BitPat("b0000111") // 0x07: vmax.vx - - val VAND_VV = BitPat("b0001001") // 0x09: vand.vv - val VAND_VX = BitPat("b0001001") // 0x09: vand.vx - val VAND_VI = BitPat("b0001001") // 0x09: vand.vi - val VOR_VV = BitPat("b0001010") // 0x0A: vor.vv - val VOR_VX = BitPat("b0001010") // 0x0A: vor.vx - val VOR_VI = BitPat("b0001010") // 0x0A: vor.vi - val VXOR_VV = BitPat("b0001011") // 0x0B: vxor.vv - val VXOR_VX = BitPat("b0001011") // 0x0B: vxor.vx - val VXOR_VI = BitPat("b0001011") // 0x0B: vxor.vi - - val VSLL_VV = BitPat("b0010101") // 0x15: vsll.vv - val VSLL_VX = BitPat("b0010101") // 0x15: vsll.vx - val VSLL_VI = BitPat("b0010101") // 0x15: vsll.vi - val VSRL_VV = BitPat("b0010100") // 0x14: vsrl.vv - val VSRL_VX = BitPat("b0010100") // 0x14: vsrl.vx - val VSRL_VI = BitPat("b0010100") // 0x14: vsrl.vi - val VSRA_VV = BitPat("b0010101") // 0x15: vsra.vv - val VSRA_VX = BitPat("b0010101") // 0x15: vsra.vx - val VSRA_VI = BitPat("b0010101") // 0x15: vsra.vi - - val VMUL_VV = BitPat("b1001010") // 0x4A: vmul.vv - val VMUL_VX = BitPat("b1001010") // 0x4A: vmul.vx - val VMULH_VV = BitPat("b1001011") // 0x4B: vmulh.vv - val VMULH_VX = BitPat("b1001011") // 0x4B: vmulh.vx - val VMULHU_VV = BitPat("b1001000") // 0x48: vmulhu.vv - val VMULHU_VX = BitPat("b1001000") // 0x48: vmulhu.vx - val VMULHSU_VV = BitPat("b1001001") // 0x49: vmulhsu.vv - val VMULHSU_VX = BitPat("b1001001") // 0x49: vmulhsu.vx - - val VMACC_VV = BitPat("b1011010") // 0x5A: vmacc.vv - val VMACC_VX = BitPat("b1011010") // 0x5A: vmacc.vx - val VMADD_VV = BitPat("b1010010") // 0x52: vmadd.vv - val VMADD_VX = BitPat("b1010010") // 0x52: vmadd.vx - - // RVV Vector Load/Store Instructions - // mop field [27:26] for memory operations - val VLE_UNIT = BitPat("b00") // unit-stride load - val VLE_STRIDED = BitPat("b10") // strided load - val VLE_INDEXED = BitPat("b11") // indexed load - val VSE_UNIT = BitPat("b00") // unit-stride store - val VSE_STRIDED = BitPat("b10") // strided store - val VSE_INDEXED = BitPat("b11") // indexed store - - // Vector configuration instructions (vsetvl, vsetvli, vsetivli) - val VSETVLI = BitPat("b0000000") // vsetvli - val VSETIVLI = BitPat("b1100000") // vsetivli - val VSETVL = BitPat("b1000000") // vsetvl -} diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index 5b0a6eb0..aef4f59d 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -5,6 +5,8 @@ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} +import framework.gpdomain.sequencer.decoder.DomainDecoder + /** * General Purpose Domain */ @@ -22,13 +24,15 @@ class GpDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundl class GpDomain(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val io = IO(new GpDomainIO) - // Placeholder implementation: accept instructions and immediately complete them - // This allows RVV instructions to pass through without blocking the pipeline - - // Accept all incoming instructions io.global_issue_i.ready := io.global_complete_o.ready - // Immediately complete accepted instructions (pass-through) +// ----------------------------------------------------------------------------- +// Decode Stage +// ----------------------------------------------------------------------------- + val decoder = Module(new DomainDecoder) + decoder.io.inst_i := io.global_issue_i.bits.cmd.raw_cmd + val decoded = decoder.io.decoded_o + io.global_complete_o.valid := io.global_issue_i.valid io.global_complete_o.bits.rob_id := io.global_issue_i.bits.rob_id diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala new file mode 100644 index 00000000..b1a8272d --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala @@ -0,0 +1,18 @@ +package framework.gpdomain.sequencer.decoder + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile._ + + +class BuckyballRawCmd(implicit p: Parameters) extends Bundle { + val cmd = new RoCCCommand +} + +object DISA { + // RVV Instruction Opcodes + val RVV_OPCODE_V = "b1010111".U // 0x57: OP-V (vector compute) + val RVV_OPCODE_VL = "b0000111".U // 0x07: LOAD-FP (vector load) + val RVV_OPCODE_VS = "b0100111".U // 0x27: STORE-FP (vector store) +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala new file mode 100644 index 00000000..da76280d --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import chisel3.util.BitPat +import chisel3.util.experimental.decode._ + +import framework.gpdomain.sequencer.decoder.InstructionEncoding.Instruction +import framework.gpdomain.sequencer.decoder.attribute._ + +object DecoderParam { + implicit def rwP: upickle.default.ReadWriter[DecoderParam] = upickle.default.macroRW +} + +case class DecoderParam(fpuEnable: Boolean, zvbbEnable: Boolean, useXsfmm: Boolean, allInstructions: Seq[Instruction]) + extends SerializableModuleParameter + +trait T1DecodeFiled[D <: Data] extends DecodeField[T1DecodePattern, D] with FieldName + +trait BoolField extends T1DecodeFiled[Bool] with BoolDecodeField[T1DecodePattern] { + def getTriState(pattern: T1DecodePattern): TriState + + override def genTable(pattern: T1DecodePattern): BitPat = + getTriState(pattern) match { + case attribute.Y => y + case attribute.N => n + case attribute.DC => dc + } +} + +trait T1UopField extends T1DecodeFiled[UInt] with FieldName { + def chiselType: UInt = UInt(4.W) +} + +trait T1TopUopField extends T1DecodeFiled[UInt] with FieldName { + def chiselType: UInt = UInt(5.W) +} + +trait T1fpExecutionTypeUopField extends T1DecodeFiled[UInt] with FieldName { + def chiselType: UInt = UInt(2.W) +} + +object Decoder { + object logic extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isLogic.value + } + + object adder extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isAdder.value + } + + object shift extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isShift.value + } + + object multiplier extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMultiplier.value + } + + object divider extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isDivider.value + } + + object multiCycle extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMulticycle.value + } + + object other extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isOther.value + } + + object unsigned0 extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isUnsigned0.value + } + + object unsigned1 extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isUnsigned1.value + } + + object itype extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isItype.value + } + + object nr extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isNr.value + } + + object red extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isRed.value + } + + object widenReduce extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isWidenreduce.value + } + + object targetRd extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isTargetrd.value + } + + object slid extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isSlid.value + } + + object gather extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isGather.value + } + + object gather16 extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isGather16.value + } + + object compress extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isCompress.value + } + + object unOrderWrite extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isUnorderwrite.value + } + + object extend extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isExtend.value + } + + object mv extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMv.value + } + + object iota extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isIota.value + } + + object maskLogic extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMasklogic.value + } + + object maskDestination extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMaskdestination.value + } + + object maskSource extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMasksource.value + } + + object readOnly extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isReadonly.value + } + + object vwmacc extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isVwmacc.value + } + + object saturate extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isSaturate.value + } + + object special extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isSpecial.value + } + + object maskUnit extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMaskunit.value + } + + object crossWrite extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isCrosswrite.value + } + + object crossRead extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isCrossread.value + } + + object sWrite extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isSwrite.value + } + + object vtype extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isVtype.value + } + + object sReadVD extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isSreadvd.value + } + + object scheduler extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isScheduler.value + } + + object dontNeedExecuteInLane extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isDontneedexecuteinlane.value + } + + object reverse extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isReverse.value + } + + object average extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isAverage.value + } + + object ffo extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isFfo.value + } + + object popCount extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isPopcount.value + } + + object specialSlot extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isSpecialslot.value + } + + object float extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isFloat.value + } + + object floatMul extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isFloatmul.value + } + + object orderReduce extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isOrderreduce.value + } + + object zvbb extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isZvbb.value + } + + object zvma extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isZvma.value + } + + object topUop extends T1TopUopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.topUop.value match { + case _: TopT0.type => BitPat("b00000") + case _: TopT1.type => BitPat("b00001") + case _: TopT2.type => BitPat("b00010") + case _: TopT3.type => BitPat("b00011") + case _: TopT4.type => BitPat("b00100") + case _: TopT5.type => BitPat("b00101") + case _: TopT6.type => BitPat("b00110") + case _: TopT7.type => BitPat("b00111") + case _: TopT8.type => BitPat("b01000") + case _: TopT9.type => BitPat("b01001") + case _: TopT10.type => BitPat("b01010") + case _: TopT11.type => BitPat("b01011") + case _: TopT12.type => BitPat("b01100") + case _: TopT13.type => BitPat("b01101") + case _: TopT14.type => BitPat("b01110") + case _: TopT15.type => BitPat("b01111") + case _: TopT16.type => BitPat("b10000") + case _: TopT17.type => BitPat("b10001") + case _: TopT18.type => BitPat("b10010") + case _: TopT19.type => BitPat("b10011") + case _: TopT20.type => BitPat("b10100") + case _: TopT21.type => BitPat("b10101") + case _: TopT22.type => BitPat("b10110") + case _: TopT23.type => BitPat("b10111") + case _: TopT24.type => BitPat("b11000") + case _: TopT25.type => BitPat("b11001") + case _: TopT26.type => BitPat("b11010") + case _: TopT27.type => BitPat("b11011") + case _: TopT28.type => BitPat("b11100") + case _: TopT29.type => BitPat("b11101") + case _: TopT30.type => BitPat("b11110") + case _: TopT31.type => BitPat("b11111") + case _ => BitPat.dontCare(5) + } + } + + object uop extends T1UopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.decoderUop.value match { + case addCase: AdderUOPType => + addCase match { + case _: addUop0.type => BitPat("b0000") + case _: addUop1.type => BitPat("b0001") + case _: addUop10.type => BitPat("b1010") + case _: addUop11.type => BitPat("b1011") + case _: addUop2.type => BitPat("b0010") + case _: addUop3.type => BitPat("b0011") + case _: addUop4.type => BitPat("b0100") + case _: addUop6.type => BitPat("b0110") + case _: addUop7.type => BitPat("b0111") + case _: addUop8.type => BitPat("b1000") + case _: addUop9.type => BitPat("b1001") + case _ => BitPat.dontCare(4) + } + case divCase: DivUOPType => + divCase match { + case _: divUop0.type => BitPat("b0000") + case _: divUop1.type => BitPat("b0001") + case _: divUop10.type => BitPat("b1010") + case _: divUop8.type => BitPat("b1000") + case _: divUop9.type => BitPat("b1001") + case _ => BitPat.dontCare(4) + } + case floatCase: FloatUopType => + floatCase match { + case _: FUT0.type => BitPat("b0000") + case _: FUT1.type => BitPat("b0001") + case _: FUT10.type => BitPat("b1010") + case _: FUT12.type => BitPat("b1100") + case _: FUT13.type => BitPat("b1101") + case _: FUT14.type => BitPat("b1110") + case _: FUT2.type => BitPat("b0010") + case _: FUT3.type => BitPat("b0011") + case _: FUT4.type => BitPat("b0100") + case _: FUT5.type => BitPat("b0101") + case _: FUT6.type => BitPat("b0110") + case _: FUT7.type => BitPat("b0111") + case _: FUT8.type => BitPat("b1000") + case _: FUT9.type => BitPat("b1001") + case _ => BitPat.dontCare(4) + } + case logicCase: LogicUopType => + logicCase match { + case _: logicUop0.type => BitPat("b0000") + case _: logicUop1.type => BitPat("b0001") + case _: logicUop2.type => BitPat("b0010") + case _: logicUop4.type => BitPat("b0100") + case _: logicUop5.type => BitPat("b0101") + case _: logicUop6.type => BitPat("b0110") + case _: logicUop8.type => BitPat("b1000") + case _: logicUop9.type => BitPat("b1001") + case _ => BitPat.dontCare(4) + } + case mulCase: MulUOPType => + mulCase match { + case _: mulUop0.type => BitPat("b0000") + case _: mulUop1.type => BitPat("b0001") + case _: mulUop10.type => BitPat("b1010") + case _: mulUop14.type => BitPat("b1110") + case _: mulUop3.type => BitPat("b0011") + case _: mulUop5.type => BitPat("b0101") + case _ => BitPat.dontCare(4) + } + case otherCase: OtherUopType => + otherCase match { + case _: otherUop0.type => BitPat("b0000") + case _: otherUop1.type => BitPat("b0001") + case _: otherUop2.type => BitPat("b0010") + case _: otherUop3.type => BitPat("b0011") + case _: otherUop4.type => BitPat("b0100") + case _: otherUop5.type => BitPat("b0101") + case _: otherUop6.type => BitPat("b0110") + case _: otherUop7.type => BitPat("b0111") + case _: otherUop8.type => BitPat("b1000") + case _: otherUop9.type => BitPat("b1001") + case _ => BitPat.dontCare(4) + } + case shiftCase: ShiftUopType => + shiftCase match { + case _: shiftUop0.type => BitPat("b0000") + case _: shiftUop1.type => BitPat("b0001") + case _: shiftUop2.type => BitPat("b0010") + case _: shiftUop4.type => BitPat("b0100") + case _: shiftUop6.type => BitPat("b0110") + case _ => BitPat.dontCare(4) + } + case zeroCase: ZeroUOPType => + zeroCase match { + case _: zeroUop0.type => BitPat("b0000") + case _ => BitPat.dontCare(4) + } + case zvbbCase: ZvbbUOPType => + zvbbCase match { + case _: zvbbUop0.type => BitPat("b0000") // brev + case _: zvbbUop1.type => BitPat("b0001") // brev8 + case _: zvbbUop2.type => BitPat("b0010") // rev8 + case _: zvbbUop3.type => BitPat("b0011") // clz + case _: zvbbUop4.type => BitPat("b0100") // ctz + case _: zvbbUop5.type => BitPat("b0101") // rol + case _: zvbbUop6.type => BitPat("b0110") // ror + case _: zvbbUop7.type => BitPat("b0111") // wsll + case _: zvbbUop8.type => BitPat("b1000") // andn + case _: zvbbUop9.type => BitPat("b1001") // pop + case _ => BitPat.dontCare(4) + } + case _ => BitPat.dontCare(4) + } + } + + object fpExecutionType extends T1fpExecutionTypeUopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.fpExecutionType match { + case FpExecutionType.Compare => BitPat("b10") + case FpExecutionType.MA => BitPat("b00") + case FpExecutionType.Other => BitPat("b11") + case FpExecutionType.Nil => BitPat.dontCare(2) + } + } + + object maskPipeType extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isMaskPip.value + } + + object writeCount extends BoolField { + override def getTriState(pattern: T1DecodePattern): TriState = pattern.isWriteCount.value + } + + object maskPipeUop extends T1TopUopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.maskPipeUop.value match { + case _: MaskUop0.type => BitPat("b00000") + case _: MaskUop1.type => BitPat("b00001") + case _: MaskUop2.type => BitPat("b00010") + case _: MaskUop3.type => BitPat("b00011") + case _: MaskUop4.type => BitPat("b00100") + case _: MaskUop5.type => BitPat("b00101") + case _: MaskUop6.type => BitPat("b00110") + case _: MaskUop7.type => BitPat("b00111") + case _: MaskUop8.type => BitPat("b01000") + case _: MaskUop9.type => BitPat("b01001") + case _: MaskUop10.type => BitPat("b01010") + case _: MaskUop11.type => BitPat("b01011") + case _ => BitPat.dontCare(chiselType.getWidth) + } + } + + def allFields(param: DecoderParam): Seq[T1DecodeFiled[_ >: Bool <: UInt]] = Seq( + logic, + adder, + shift, + multiplier, + divider, + multiCycle, + other, + maskPipeType, + unsigned0, + unsigned1, + itype, + nr, + red, + // top only + widenReduce, + targetRd, + slid, + gather, + gather16, + compress, + unOrderWrite, + // top uop + extend, // top uop + mv, // top uop + iota, // top uop + uop, + maskLogic, + maskDestination, + maskSource, + readOnly, + vwmacc, + saturate, + special, + maskUnit, + crossWrite, + crossRead, + // state + sWrite, + // sRead1 -> vType + vtype, + sReadVD, + scheduler, + dontNeedExecuteInLane, + reverse, // uop + average, // uop + ffo, // todo: add mask select -> top uop + popCount, // top uop add, red, uop popCount + topUop, + maskPipeUop, + writeCount, + specialSlot + ) ++ { + if (param.fpuEnable) + Seq( + float, + fpExecutionType, + floatMul, + orderReduce + ) + else Seq() + } ++ { + if (param.zvbbEnable) + Seq( + zvbb + ) + else Seq() + } ++ { + if (param.useXsfmm) + Seq( + zvma + ) + else Seq() + } + def allDecodePattern(param: DecoderParam): Seq[T1DecodePattern] = + param.allInstructions.map(T1DecodePattern(_, param)).toSeq.sortBy(_.instruction.name) + + def decodeTable(param: DecoderParam): DecodeTable[T1DecodePattern] = + new DecodeTable[T1DecodePattern](allDecodePattern(param), allFields(param)) + + def decode(param: DecoderParam): UInt => DecodeBundle = decodeTable(param).decode + def bundle(param: DecoderParam): DecodeBundle = decodeTable(param).bundle +} + +trait FieldName { + def name: String = this.getClass.getSimpleName.replace("$", "") +} + +case class SpecialAux(name: String, vs: Int, value: String) +case class SpecialMap(name: String, vs: Int, data: Map[String, String]) +case class SpecialAuxInstr(instrName: String, vs: Int, value: String, name: String) +case class Op( + tpe: String, + funct6: String, + tpeOp2: String, + funct3: String, + name: String, + special: Option[SpecialAux], + notLSU: Boolean, + vd: String, + opcode: String) + extends DecodePattern { + // include 32 bits: funct6 + vm + vs2 + vs1 + funct3 + vd + opcode + def bitPat: BitPat = BitPat( + "b" + + // funct6 + funct6 + + // ? for vm + "?" + + // vs2 + (if (special.isEmpty || special.get.vs == 1) "?????" else special.get.value) + + // vs1 + (if (special.isEmpty || special.get.vs == 2) "?????" else special.get.value) + + // funct3 + funct3 + + vd + + opcode + ) +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala new file mode 100644 index 00000000..4e69a68f --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala @@ -0,0 +1,54 @@ +package framework.gpdomain.sequencer.decoder + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.gpdomain.sequencer.decoder.{Decoder, DecoderParam} +import freechips.rocketchip.tile.RoCCCommand + +/** + * Domain Decoder Parameter Object + * Contains the configuration for RVV instruction decoding + */ +object DomainDecoderParameter { + // Get all RVV instructions from our local database + lazy val allInstructions: Seq[InstructionEncoding.Instruction] = { + RVVInstructions.allInstructions + } + + // Create decoder parameter using our local instruction types + lazy val decoderParam: DecoderParam = DecoderParam( + fpuEnable = true, // Enable floating-point vector instructions + zvbbEnable = true, // Enable vector bit manipulation + useXsfmm = false, // Disable xsfmm extension for now + allInstructions = allInstructions + ) +} + +/** + * Domain Decoder IO + */ +class DomainDecoderIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { + val inst_i = Input(new RoCCCommand) + val decoded_o = Decoder.bundle(DomainDecoderParameter.decoderParam).cloneType +} + +/** + * Domain Decoder Module + * Encapsulates the T1 decoder logic with local instruction database + */ +class DomainDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { + val io = IO(new DomainDecoderIO) + + import DomainDecoderParameter._ + + // Instantiate the T1 decoder with our local instructions + val decode = Decoder.decode(decoderParam) + + // Decode the incoming instruction + val inst = io.inst_i.inst.asUInt + io.decoded_o := decode(inst) + + override lazy val desiredName = "DomainDecoder" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala new file mode 100644 index 00000000..7273a6b0 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2024 Mio + +package framework.gpdomain.sequencer.decoder + +/** + * Local Instruction Database + * Provides instruction definitions without external dependencies + */ +object InstructionEncoding { + /** Like chisel3.BitPat, this stores the instruction encoding */ + case class Encoding(value: BigInt, mask: BigInt) { + def toBitMask(bit_pat: String) = + Seq.tabulate(32)(i => if (!mask.testBit(i)) bit_pat else if (value.testBit(i)) "1" else "0").reverse.mkString + override def toString: String = toBitMask("?") + } + + object Encoding { + implicit val rw: upickle.default.ReadWriter[Encoding] = upickle.default.macroRW + + def fromString(str: String): Encoding = { + require(str.length == 32, s"Encoding string must be 32 bits, got ${str.length}") + Encoding( + str.reverse.zipWithIndex.map { case (c, i) => + c match { + case '1' => BigInt(1) << i + case '0' => BigInt(0) + case '?' => BigInt(0) + case _ => throw new IllegalArgumentException(s"Invalid encoding character: $c") + } + }.sum, + str.reverse.zipWithIndex.map { case (c, i) => + c match { + case '1' => BigInt(1) << i + case '0' => BigInt(1) << i + case '?' => BigInt(0) + case _ => throw new IllegalArgumentException(s"Invalid encoding character: $c") + } + }.sum + ) + } + } + + case class Arg(name: String, msb: Int, lsb: Int) { + override def toString: String = name + } + + object Arg { + implicit val rw: upickle.default.ReadWriter[Arg] = upickle.default.macroRW + } + + case class InstructionSet(name: String) + + object InstructionSet { + implicit val rw: upickle.default.ReadWriter[InstructionSet] = upickle.default.macroRW + } + + case class Instruction( + name: String, + encoding: Encoding, + args: Seq[Arg], + instructionSets: Seq[InstructionSet], + pseudoFrom: Option[Instruction], + ratified: Boolean, + custom: Boolean + ) { + def instructionSet: InstructionSet = instructionSets.head + } + + object Instruction { + implicit val rw: upickle.default.ReadWriter[Instruction] = upickle.default.macroRW + } +} + +/** + * Manual RVV Instruction Database + * Contains commonly used RVV instructions with their encodings + */ +object RVVInstructions { + import InstructionEncoding._ + + // Common argument definitions + val vd = Arg("vd", 11, 7) + val vs1 = Arg("vs1", 19, 15) + val vs2 = Arg("vs2", 24, 20) + val vs3 = Arg("vs3", 11, 7) + val vm = Arg("vm", 25, 25) + val rs1 = Arg("rs1", 19, 15) + val rs2 = Arg("rs2", 24, 20) + val rd = Arg("rd", 11, 7) + val zimm5 = Arg("zimm5", 19, 15) + val zimm10 = Arg("zimm10", 29, 20) + val zimm11 = Arg("zimm11", 30, 20) + val simm5 = Arg("simm5", 19, 15) + val nf = Arg("nf", 31, 29) + + // Instruction set definitions + val rv_v = InstructionSet("rv_v") + val rv_zvbb = InstructionSet("rv_zvbb") + + /** + * Create all RVV instructions + * Returns a sequence of Instructions for the decoder + */ + def allInstructions: Seq[Instruction] = { + configInstructions ++ + integerArithmeticInstructions ++ + loadStoreInstructions ++ + maskInstructions ++ + permuteInstructions + } + + // ============================================================================ + // Vector Configuration Instructions + // ============================================================================ + def configInstructions: Seq[Instruction] = Seq( + Instruction( + name = "vsetvli", + encoding = Encoding.fromString("0????????????????111?????1010111"), // 31=0, zimm11(30..20), rs1(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) + args = Seq(rd, rs1, zimm11), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vsetivli", + encoding = Encoding.fromString("11???????????????111?????1010111"), // 31..30=11, zimm10(29..20), zimm5(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) + args = Seq(rd, zimm10, zimm5), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vsetvl", + encoding = Encoding.fromString("1000000??????????111?????1010111"), // 31=1, 30..25=000000, rs2(24..20), rs1(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) + args = Seq(rd, rs1, rs2), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ) + ) + + // ============================================================================ + // Integer Arithmetic Instructions (Common ones) + // ============================================================================ + def integerArithmeticInstructions: Seq[Instruction] = Seq( + // VADD variants + Instruction( + name = "vadd.vv", + encoding = Encoding.fromString("000000???????????000?????1010111"), // funct6=000000, funct3=000 (OPIVV) + args = Seq(vd, vs2, vs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vadd.vx", + encoding = Encoding.fromString("000000???????????100?????1010111"), // funct6=000000, funct3=100 (OPIVX) + args = Seq(vd, vs2, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vadd.vi", + encoding = Encoding.fromString("000000???????????011?????1010111"), // funct6=000000, funct3=011 (OPIVI) + args = Seq(vd, vs2, simm5, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + + // VSUB variants + Instruction( + name = "vsub.vv", + encoding = Encoding.fromString("000010???????????000?????1010111"), // funct6=000010, funct3=000 + args = Seq(vd, vs2, vs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vsub.vx", + encoding = Encoding.fromString("000010???????????100?????1010111"), // funct6=000010, funct3=100 + args = Seq(vd, vs2, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + + // VMUL variants + Instruction( + name = "vmul.vv", + encoding = Encoding.fromString("100101???????????010?????1010111"), // funct6=100101, funct3=010 (OPMVV) + args = Seq(vd, vs2, vs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vmul.vx", + encoding = Encoding.fromString("100101???????????110?????1010111"), // funct6=100101, funct3=110 (OPMVX) + args = Seq(vd, vs2, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ) + ) + + // ============================================================================ + // Load/Store Instructions + // ============================================================================ + def loadStoreInstructions: Seq[Instruction] = Seq( + // Unit-stride loads + Instruction( + name = "vle8.v", + encoding = Encoding.fromString("???000?00000?????000?????0000111"), // nf, mew=0, mop=00, lumop=00000, funct3=000, opcode=0000111 + args = Seq(vd, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vle16.v", + encoding = Encoding.fromString("???000?00000?????101?????0000111"), // funct3=101 + args = Seq(vd, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vle32.v", + encoding = Encoding.fromString("???000?00000?????110?????0000111"), // funct3=110 + args = Seq(vd, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vle64.v", + encoding = Encoding.fromString("???000?00000?????111?????0000111"), // funct3=111 + args = Seq(vd, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + + // Unit-stride stores + Instruction( + name = "vse8.v", + encoding = Encoding.fromString("???000?00000?????000?????0100111"), // opcode=0100111 (VS) + args = Seq(vs3, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vse16.v", + encoding = Encoding.fromString("???000?00000?????101?????0100111"), + args = Seq(vs3, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vse32.v", + encoding = Encoding.fromString("???000?00000?????110?????0100111"), + args = Seq(vs3, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vse64.v", + encoding = Encoding.fromString("???000?00000?????111?????0100111"), + args = Seq(vs3, rs1, vm), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ) + ) + + // ============================================================================ + // Mask Instructions + // ============================================================================ + def maskInstructions: Seq[Instruction] = Seq( + Instruction( + name = "vmand.mm", + encoding = Encoding.fromString("011001???????????010?????1010111"), // funct6=011001, funct3=010 + args = Seq(vd, vs2, vs1), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vmor.mm", + encoding = Encoding.fromString("011010???????????010?????1010111"), // funct6=011010, funct3=010 + args = Seq(vd, vs2, vs1), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ) + ) + + // ============================================================================ + // Permute Instructions + // ============================================================================ + def permuteInstructions: Seq[Instruction] = Seq( + Instruction( + name = "vmv.v.v", + encoding = Encoding.fromString("010111?00000?????000?????1010111"), // funct6=010111, vs2=00000, funct3=000 + args = Seq(vd, vs1), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vmv.v.x", + encoding = Encoding.fromString("010111?00000?????100?????1010111"), // funct6=010111, vs2=00000, funct3=100 + args = Seq(vd, rs1), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ), + Instruction( + name = "vmv.v.i", + encoding = Encoding.fromString("010111?00000?????011?????1010111"), // funct6=010111, vs2=00000, funct3=011 + args = Seq(vd, simm5), + instructionSets = Seq(rv_v), + pseudoFrom = None, + ratified = true, + custom = false + ) + ) +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala new file mode 100644 index 00000000..a2b366e2 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder + +import framework.gpdomain.sequencer.decoder.InstructionEncoding.Instruction + +/** Generate documentation for each instructions for T1. The documentation should contain the behavior for instruction + * in a specific configuration in T1. + * @todo + * should it be a post process at omreader? + */ +case class InstructionDocumentation(instruction: Instruction, param: DecoderParam) { + override def toString: String = instruction.name match { + case "vaadd.vv" => "TODO!" + case "vaadd.vx" => "TODO!" + case "vaaddu.vv" => "TODO!" + case "vaaddu.vx" => "TODO!" + case "vadc.vim" => "TODO!" + case "vadc.vvm" => "TODO!" + case "vadc.vxm" => "TODO!" + case "vadd.vi" => "TODO!" + case "vadd.vv" => "TODO!" + case "vadd.vx" => "TODO!" + case "vand.vi" => "TODO!" + case "vand.vv" => "TODO!" + case "vand.vx" => "TODO!" + case "vasub.vv" => "TODO!" + case "vasub.vx" => "TODO!" + case "vasubu.vv" => "TODO!" + case "vasubu.vx" => "TODO!" + case "vcompress.vm" => "TODO!" + case "vcpop.m" => "TODO!" + case "vdiv.vv" => "TODO!" + case "vdiv.vx" => "TODO!" + case "vdivu.vv" => "TODO!" + case "vdivu.vx" => "TODO!" + case "vfadd.vf" => "TODO!" + case "vfadd.vv" => "TODO!" + case "vfclass.v" => "TODO!" + case "vfcvt.f.x.v" => "TODO!" + case "vfcvt.f.xu.v" => "TODO!" + case "vfcvt.rtz.x.f.v" => "TODO!" + case "vfcvt.rtz.xu.f.v" => "TODO!" + case "vfcvt.x.f.v" => "TODO!" + case "vfcvt.xu.f.v" => "TODO!" + case "vfdiv.vf" => "TODO!" + case "vfdiv.vv" => "TODO!" + case "vfirst.m" => "TODO!" + case "vfmacc.vf" => "TODO!" + case "vfmacc.vv" => "TODO!" + case "vfmadd.vf" => "TODO!" + case "vfmadd.vv" => "TODO!" + case "vfmax.vf" => "TODO!" + case "vfmax.vv" => "TODO!" + case "vfmerge.vfm" => "TODO!" + case "vfmin.vf" => "TODO!" + case "vfmin.vv" => "TODO!" + case "vfmsac.vf" => "TODO!" + case "vfmsac.vv" => "TODO!" + case "vfmsub.vf" => "TODO!" + case "vfmsub.vv" => "TODO!" + case "vfmul.vf" => "TODO!" + case "vfmul.vv" => "TODO!" + case "vfmv.f.s" => "TODO!" + case "vfmv.s.f" => "TODO!" + case "vfmv.v.f" => "TODO!" + case "vfncvt.f.f.w" => "TODO!" + case "vfncvt.f.x.w" => "TODO!" + case "vfncvt.f.xu.w" => "TODO!" + case "vfncvt.rod.f.f.w" => "TODO!" + case "vfncvt.rtz.x.f.w" => "TODO!" + case "vfncvt.rtz.xu.f.w" => "TODO!" + case "vfncvt.x.f.w" => "TODO!" + case "vfncvt.xu.f.w" => "TODO!" + case "vfnmacc.vf" => "TODO!" + case "vfnmacc.vv" => "TODO!" + case "vfnmadd.vf" => "TODO!" + case "vfnmadd.vv" => "TODO!" + case "vfnmsac.vf" => "TODO!" + case "vfnmsac.vv" => "TODO!" + case "vfnmsub.vf" => "TODO!" + case "vfnmsub.vv" => "TODO!" + case "vfrdiv.vf" => "TODO!" + case "vfrec7.v" => "TODO!" + case "vfredmax.vs" => "TODO!" + case "vfredmin.vs" => "TODO!" + case "vfredosum.vs" => "TODO!" + case "vfredusum.vs" => "TODO!" + case "vfrsqrt7.v" => "TODO!" + case "vfrsub.vf" => "TODO!" + case "vfsgnj.vf" => "TODO!" + case "vfsgnj.vv" => "TODO!" + case "vfsgnjn.vf" => "TODO!" + case "vfsgnjn.vv" => "TODO!" + case "vfsgnjx.vf" => "TODO!" + case "vfsgnjx.vv" => "TODO!" + case "vfslide1down.vf" => "TODO!" + case "vfslide1up.vf" => "TODO!" + case "vfsqrt.v" => "TODO!" + case "vfsub.vf" => "TODO!" + case "vfsub.vv" => "TODO!" + case "vfwadd.vf" => "TODO!" + case "vfwadd.vv" => "TODO!" + case "vfwadd.wf" => "TODO!" + case "vfwadd.wv" => "TODO!" + case "vfwcvt.f.f.v" => "TODO!" + case "vfwcvt.f.x.v" => "TODO!" + case "vfwcvt.f.xu.v" => "TODO!" + case "vfwcvt.rtz.x.f.v" => "TODO!" + case "vfwcvt.rtz.xu.f.v" => "TODO!" + case "vfwcvt.x.f.v" => "TODO!" + case "vfwcvt.xu.f.v" => "TODO!" + case "vfwmacc.vf" => "TODO!" + case "vfwmacc.vv" => "TODO!" + case "vfwmsac.vf" => "TODO!" + case "vfwmsac.vv" => "TODO!" + case "vfwmul.vf" => "TODO!" + case "vfwmul.vv" => "TODO!" + case "vfwnmacc.vf" => "TODO!" + case "vfwnmacc.vv" => "TODO!" + case "vfwnmsac.vf" => "TODO!" + case "vfwnmsac.vv" => "TODO!" + case "vfwredosum.vs" => "TODO!" + case "vfwredusum.vs" => "TODO!" + case "vfwsub.vf" => "TODO!" + case "vfwsub.vv" => "TODO!" + case "vfwsub.wf" => "TODO!" + case "vfwsub.wv" => "TODO!" + case "vid.v" => "TODO!" + case "viota.m" => "TODO!" + case "vl1re16.v" => "TODO!" + case "vl1re32.v" => "TODO!" + case "vl1re64.v" => "TODO!" + case "vl1re8.v" => "TODO!" + case "vl2re16.v" => "TODO!" + case "vl2re32.v" => "TODO!" + case "vl2re64.v" => "TODO!" + case "vl2re8.v" => "TODO!" + case "vl4re16.v" => "TODO!" + case "vl4re32.v" => "TODO!" + case "vl4re64.v" => "TODO!" + case "vl4re8.v" => "TODO!" + case "vl8re16.v" => "TODO!" + case "vl8re32.v" => "TODO!" + case "vl8re64.v" => "TODO!" + case "vl8re8.v" => "TODO!" + case "vle1024.v" => "TODO!" + case "vle1024ff.v" => "TODO!" + case "vle128.v" => "TODO!" + case "vle128ff.v" => "TODO!" + case "vle16.v" => "TODO!" + case "vle16ff.v" => "TODO!" + case "vle256.v" => "TODO!" + case "vle256ff.v" => "TODO!" + case "vle32.v" => "TODO!" + case "vle32ff.v" => "TODO!" + case "vle512.v" => "TODO!" + case "vle512ff.v" => "TODO!" + case "vle64.v" => "TODO!" + case "vle64ff.v" => "TODO!" + case "vle8.v" => "TODO!" + case "vle8ff.v" => "TODO!" + case "vlm.v" => "TODO!" + case "vloxei1024.v" => "TODO!" + case "vloxei128.v" => "TODO!" + case "vloxei16.v" => "TODO!" + case "vloxei256.v" => "TODO!" + case "vloxei32.v" => "TODO!" + case "vloxei512.v" => "TODO!" + case "vloxei64.v" => "TODO!" + case "vloxei8.v" => "TODO!" + case "vlse1024.v" => "TODO!" + case "vlse128.v" => "TODO!" + case "vlse16.v" => "TODO!" + case "vlse256.v" => "TODO!" + case "vlse32.v" => "TODO!" + case "vlse512.v" => "TODO!" + case "vlse64.v" => "TODO!" + case "vlse8.v" => "TODO!" + case "vluxei1024.v" => "TODO!" + case "vluxei128.v" => "TODO!" + case "vluxei16.v" => "TODO!" + case "vluxei256.v" => "TODO!" + case "vluxei32.v" => "TODO!" + case "vluxei512.v" => "TODO!" + case "vluxei64.v" => "TODO!" + case "vluxei8.v" => "TODO!" + case "vmacc.vv" => "TODO!" + case "vmacc.vx" => "TODO!" + case "vmadc.vi" => "TODO!" + case "vmadc.vim" => "TODO!" + case "vmadc.vv" => "TODO!" + case "vmadc.vvm" => "TODO!" + case "vmadc.vx" => "TODO!" + case "vmadc.vxm" => "TODO!" + case "vmadd.vv" => "TODO!" + case "vmadd.vx" => "TODO!" + case "vmand.mm" => "TODO!" + case "vmandn.mm" => "TODO!" + case "vmax.vv" => "TODO!" + case "vmax.vx" => "TODO!" + case "vmaxu.vv" => "TODO!" + case "vmaxu.vx" => "TODO!" + case "vmerge.vim" => "TODO!" + case "vmerge.vvm" => "TODO!" + case "vmerge.vxm" => "TODO!" + case "vmfeq.vf" => "TODO!" + case "vmfeq.vv" => "TODO!" + case "vmfge.vf" => "TODO!" + case "vmfgt.vf" => "TODO!" + case "vmfle.vf" => "TODO!" + case "vmfle.vv" => "TODO!" + case "vmflt.vf" => "TODO!" + case "vmflt.vv" => "TODO!" + case "vmfne.vf" => "TODO!" + case "vmfne.vv" => "TODO!" + case "vmin.vv" => "TODO!" + case "vmin.vx" => "TODO!" + case "vminu.vv" => "TODO!" + case "vminu.vx" => "TODO!" + case "vmnand.mm" => "TODO!" + case "vmnor.mm" => "TODO!" + case "vmor.mm" => "TODO!" + case "vmorn.mm" => "TODO!" + case "vmsbc.vv" => "TODO!" + case "vmsbc.vvm" => "TODO!" + case "vmsbc.vx" => "TODO!" + case "vmsbc.vxm" => "TODO!" + case "vmsbf.m" => "TODO!" + case "vmseq.vi" => "TODO!" + case "vmseq.vv" => "TODO!" + case "vmseq.vx" => "TODO!" + case "vmsgt.vi" => "TODO!" + case "vmsgt.vx" => "TODO!" + case "vmsgtu.vi" => "TODO!" + case "vmsgtu.vx" => "TODO!" + case "vmsif.m" => "TODO!" + case "vmsle.vi" => "TODO!" + case "vmsle.vv" => "TODO!" + case "vmsle.vx" => "TODO!" + case "vmsleu.vi" => "TODO!" + case "vmsleu.vv" => "TODO!" + case "vmsleu.vx" => "TODO!" + case "vmslt.vv" => "TODO!" + case "vmslt.vx" => "TODO!" + case "vmsltu.vv" => "TODO!" + case "vmsltu.vx" => "TODO!" + case "vmsne.vi" => "TODO!" + case "vmsne.vv" => "TODO!" + case "vmsne.vx" => "TODO!" + case "vmsof.m" => "TODO!" + case "vmul.vv" => "TODO!" + case "vmul.vx" => "TODO!" + case "vmulh.vv" => "TODO!" + case "vmulh.vx" => "TODO!" + case "vmulhsu.vv" => "TODO!" + case "vmulhsu.vx" => "TODO!" + case "vmulhu.vv" => "TODO!" + case "vmulhu.vx" => "TODO!" + case "vmv.s.x" => "TODO!" + case "vmv.v.i" => "TODO!" + case "vmv.v.v" => "TODO!" + case "vmv.v.x" => "TODO!" + case "vmv.x.s" => "TODO!" + case "vmv1r.v" => "TODO!" + case "vmv2r.v" => "TODO!" + case "vmv4r.v" => "TODO!" + case "vmv8r.v" => "TODO!" + case "vmxnor.mm" => "TODO!" + case "vmxor.mm" => "TODO!" + case "vnclip.wi" => "TODO!" + case "vnclip.wv" => "TODO!" + case "vnclip.wx" => "TODO!" + case "vnclipu.wi" => "TODO!" + case "vnclipu.wv" => "TODO!" + case "vnclipu.wx" => "TODO!" + case "vnmsac.vv" => "TODO!" + case "vnmsac.vx" => "TODO!" + case "vnmsub.vv" => "TODO!" + case "vnmsub.vx" => "TODO!" + case "vnsra.wi" => "TODO!" + case "vnsra.wv" => "TODO!" + case "vnsra.wx" => "TODO!" + case "vnsrl.wi" => "TODO!" + case "vnsrl.wv" => "TODO!" + case "vnsrl.wx" => "TODO!" + case "vor.vi" => "TODO!" + case "vor.vv" => "TODO!" + case "vor.vx" => "TODO!" + case "vredand.vs" => "TODO!" + case "vredmax.vs" => "TODO!" + case "vredmaxu.vs" => "TODO!" + case "vredmin.vs" => "TODO!" + case "vredminu.vs" => "TODO!" + case "vredor.vs" => "TODO!" + case "vredsum.vs" => "TODO!" + case "vredxor.vs" => "TODO!" + case "vrem.vv" => "TODO!" + case "vrem.vx" => "TODO!" + case "vremu.vv" => "TODO!" + case "vremu.vx" => "TODO!" + case "vrgather.vi" => "TODO!" + case "vrgather.vv" => "TODO!" + case "vrgather.vx" => "TODO!" + case "vrgatherei16.vv" => "TODO!" + case "vrsub.vi" => "TODO!" + case "vrsub.vx" => "TODO!" + case "vs1r.v" => "TODO!" + case "vs2r.v" => "TODO!" + case "vs4r.v" => "TODO!" + case "vs8r.v" => "TODO!" + case "vsadd.vi" => "TODO!" + case "vsadd.vv" => "TODO!" + case "vsadd.vx" => "TODO!" + case "vsaddu.vi" => "TODO!" + case "vsaddu.vv" => "TODO!" + case "vsaddu.vx" => "TODO!" + case "vsbc.vvm" => "TODO!" + case "vsbc.vxm" => "TODO!" + case "vse1024.v" => "TODO!" + case "vse128.v" => "TODO!" + case "vse16.v" => "TODO!" + case "vse256.v" => "TODO!" + case "vse32.v" => "TODO!" + case "vse512.v" => "TODO!" + case "vse64.v" => "TODO!" + case "vse8.v" => "TODO!" + case "vsetivli" => "TODO!" + case "vsetvl" => "TODO!" + case "vsetvli" => "TODO!" + case "vsext.vf2" => "TODO!" + case "vsext.vf4" => "TODO!" + case "vsext.vf8" => "TODO!" + case "vslide1down.vx" => "TODO!" + case "vslide1up.vx" => "TODO!" + case "vslidedown.vi" => "TODO!" + case "vslidedown.vx" => "TODO!" + case "vslideup.vi" => "TODO!" + case "vslideup.vx" => "TODO!" + case "vsll.vi" => "TODO!" + case "vsll.vv" => "TODO!" + case "vsll.vx" => "TODO!" + case "vsm.v" => "TODO!" + case "vsmul.vv" => "TODO!" + case "vsmul.vx" => "TODO!" + case "vsoxei1024.v" => "TODO!" + case "vsoxei128.v" => "TODO!" + case "vsoxei16.v" => "TODO!" + case "vsoxei256.v" => "TODO!" + case "vsoxei32.v" => "TODO!" + case "vsoxei512.v" => "TODO!" + case "vsoxei64.v" => "TODO!" + case "vsoxei8.v" => "TODO!" + case "vsra.vi" => "TODO!" + case "vsra.vv" => "TODO!" + case "vsra.vx" => "TODO!" + case "vsrl.vi" => "TODO!" + case "vsrl.vv" => "TODO!" + case "vsrl.vx" => "TODO!" + case "vsse1024.v" => "TODO!" + case "vsse128.v" => "TODO!" + case "vsse16.v" => "TODO!" + case "vsse256.v" => "TODO!" + case "vsse32.v" => "TODO!" + case "vsse512.v" => "TODO!" + case "vsse64.v" => "TODO!" + case "vsse8.v" => "TODO!" + case "vssra.vi" => "TODO!" + case "vssra.vv" => "TODO!" + case "vssra.vx" => "TODO!" + case "vssrl.vi" => "TODO!" + case "vssrl.vv" => "TODO!" + case "vssrl.vx" => "TODO!" + case "vssub.vv" => "TODO!" + case "vssub.vx" => "TODO!" + case "vssubu.vv" => "TODO!" + case "vssubu.vx" => "TODO!" + case "vsub.vv" => "TODO!" + case "vsub.vx" => "TODO!" + case "vsuxei1024.v" => "TODO!" + case "vsuxei128.v" => "TODO!" + case "vsuxei16.v" => "TODO!" + case "vsuxei256.v" => "TODO!" + case "vsuxei32.v" => "TODO!" + case "vsuxei512.v" => "TODO!" + case "vsuxei64.v" => "TODO!" + case "vsuxei8.v" => "TODO!" + case "vwadd.vv" => "TODO!" + case "vwadd.vx" => "TODO!" + case "vwadd.wv" => "TODO!" + case "vwadd.wx" => "TODO!" + case "vwaddu.vv" => "TODO!" + case "vwaddu.vx" => "TODO!" + case "vwaddu.wv" => "TODO!" + case "vwaddu.wx" => "TODO!" + case "vwmacc.vv" => "TODO!" + case "vwmacc.vx" => "TODO!" + case "vwmaccsu.vv" => "TODO!" + case "vwmaccsu.vx" => "TODO!" + case "vwmaccu.vv" => "TODO!" + case "vwmaccu.vx" => "TODO!" + case "vwmaccus.vx" => "TODO!" + case "vwmul.vv" => "TODO!" + case "vwmul.vx" => "TODO!" + case "vwmulsu.vv" => "TODO!" + case "vwmulsu.vx" => "TODO!" + case "vwmulu.vv" => "TODO!" + case "vwmulu.vx" => "TODO!" + case "vwredsum.vs" => "TODO!" + case "vwredsumu.vs" => "TODO!" + case "vwsub.vv" => "TODO!" + case "vwsub.vx" => "TODO!" + case "vwsub.wv" => "TODO!" + case "vwsub.wx" => "TODO!" + case "vwsubu.vv" => "TODO!" + case "vwsubu.vx" => "TODO!" + case "vwsubu.wv" => "TODO!" + case "vwsubu.wx" => "TODO!" + case "vxor.vi" => "TODO!" + case "vxor.vv" => "TODO!" + case "vxor.vx" => "TODO!" + case "vzext.vf2" => "TODO!" + case "vzext.vf4" => "TODO!" + case "vzext.vf8" => "TODO!" + // rv_zvbb + case "vandn.vv" => "TODO!" + case "vandn.vx" => "TODO!" + case "vbrev.v" => "TODO!" + case "vbrev8.v" => "TODO!" + case "vrev8.v" => "TODO!" + case "vclz.v" => "TODO!" + case "vctz.v" => "TODO!" + case "vcpop.v" => "TODO!" + case "vrol.vv" => "TODO!" + case "vrol.vx" => "TODO!" + case "vror.vv" => "TODO!" + case "vror.vx" => "TODO!" + case "vror.vi" => "TODO!" + case "vwsll.vv" => "TODO!" + case "vwsll.vx" => "TODO!" + case "vwsll.vi" => "TODO!" + // + case "vlte8" => "TODO!" + case "vlte16" => "TODO!" + case "vlte32" => "TODO!" + case "vste8" => "TODO!" + case "vste16" => "TODO!" + case "vste32" => "TODO!" + case "vtmv.v.t" => "TODO!" + case "vtmv.t.v" => "TODO!" + case "mm.u.u" => "TODO!" + case "mm.u.s" => "TODO!" + case "mm.s.u" => "TODO!" + case "mm.s.s" => "TODO!" + case "mm.e5m2.e4m3" => "TODO!" + case "mm.e5m2.e5m2" => "TODO!" + case "mm.e4m3.e4m3" => "TODO!" + case "mm.e4m3.e5m2" => "TODO!" + case "vtzero.t" => "TODO!" + case "p2mm.f.f" => "TODO!" + case "vtdiscard" => "TODO!" + case _ => "TODO" + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala new file mode 100644 index 00000000..e4bf4f7b --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder + +import chisel3._ +import chisel3.experimental.hierarchy.core.Definition +import chisel3.experimental.hierarchy.{instantiable, public, Instantiate} +import chisel3.properties.{AnyClassType, Class, ClassType, Property} +import chisel3.util.BitPat +import chisel3.util.experimental.decode.DecodePattern +import framework.gpdomain.sequencer.decoder.InstructionEncoding.Instruction +import framework.gpdomain.sequencer.decoder.attribute._ + +@instantiable +class T1DecodeAttributeOM( + _identifier: String, + _description: String, + _value: String) + extends Class { + val identifier = IO(Output(Property[String]())) + val description = IO(Output(Property[String]())) + val value = IO(Output(Property[String]())) + identifier := Property(_identifier) + description := Property(_description) + value := Property(_value) +} + +@instantiable +class T1InstructionOM( + _instructionName: String, + _documentation: String, + _bitPat: String) + extends Class { + val instructionName = IO(Output(Property[String]())) + val documentation = IO(Output(Property[String]())) + val bitPat = IO(Output(Property[String]())) + val attributes = IO(Output(Property[Seq[AnyClassType]])) + @public + val attributesIn = IO(Input(Property[Seq[AnyClassType]])) + + instructionName := Property(_instructionName) + documentation := Property(_documentation) + bitPat := Property(_bitPat) + attributes := attributesIn +} + +/** A case class that should wrap all Vector Instructions. This is used to store the attribute for Vector Instruction + * under the T1 uArch. It generates [[chisel3.util.experimental.decode.TruthTable]], as well as documentation field. + */ +case class T1DecodePattern(instruction: Instruction, param: DecoderParam) extends DecodePattern { + override def bitPat: BitPat = BitPat("b" + instruction.encoding.toString) + + // use the attribute w/ [[isVector.value]] + def isVector: isVector = attribute.isVector(this) + def isAdder: isAdder = attribute.isAdder(this) + def isAverage: isAverage = attribute.isAverage(this) + def isCompress: isCompress = attribute.isCompress(this) + def isCrossread: isCrossread = attribute.isCrossread(this) + def isCrosswrite: isCrosswrite = attribute.isCrosswrite(this) + def isDivider: isDivider = attribute.isDivider(this) + def isDontneedexecuteinlane: isDontneedexecuteinlane = attribute.isDontneedexecuteinlane(this) + def isExtend: isExtend = attribute.isExtend(this) + def isFcompare: isFcompare = attribute.isFcompare(this) + def isFfo: isFfo = attribute.isFfo(this) + def isFirstwiden: isFirstwiden = attribute.isFirstwiden(this) + def isFloatmul: isFloatmul = attribute.isFloatmul(this) + def isFloat: isFloat = attribute.isFloat(this) + def isFloattype: isFloattype = attribute.isFloattype(this) + def isFma: isFma = attribute.isFma(this) + def isFother: isFother = attribute.isFother(this) + def isGather16: isGather16 = attribute.isGather16(this) + def isGather: isGather = attribute.isGather(this) + def isId: isId = attribute.isId(this) + def isIndextype: isIndextype = attribute.isIndextype(this) + def isIota: isIota = attribute.isIota(this) + def isItype: isItype = attribute.isItype(this) + def isLogic: isLogic = attribute.isLogic(this) + def isMaskdestination: isMaskdestination = attribute.isMaskdestination(this) + def isMasklogic: isMasklogic = attribute.isMasklogic(this) + def isMasksource: isMasksource = attribute.isMasksource(this) + def isMaskunit: isMaskunit = attribute.isMaskunit(this) + def isMulticycle: isMulticycle = attribute.isMulticycle(this) + def isMultiplier: isMultiplier = attribute.isMultiplier(this) + def isMv: isMv = attribute.isMv(this) + def isNarrow: isNarrow = attribute.isNarrow(this) + def isNr: isNr = attribute.isNr(this) + def isOrderreduce: isOrderreduce = attribute.isOrderreduce(this) + def isOther: isOther = attribute.isOther(this) + def isZero: isZero = attribute.isZero(this) + def isPopcount: isPopcount = attribute.isPopcount(this) + def isReadonly: isReadonly = attribute.isReadonly(this) + def isRed: isRed = attribute.isRed(this) + def isReverse: isReverse = attribute.isReverse(this) + def isSaturate: isSaturate = attribute.isSaturate(this) + def isScheduler: isScheduler = attribute.isScheduler(this) + def isShift: isShift = attribute.isShift(this) + def isSlid: isSlid = attribute.isSlid(this) + def isSpecial: isSpecial = attribute.isSpecial(this) + def isSpecialslot: isSpecialslot = attribute.isSpecialslot(this) + def isSreadvd: isSreadvd = attribute.isSreadvd(this) + def isSwrite: isSwrite = attribute.isSwrite(this) + def isTargetrd: isTargetrd = attribute.isTargetrd(this) + def isUnorderwrite: isUnorderwrite = attribute.isUnorderwrite(this) + def isUnsigned0: isUnsigned0 = attribute.isUnsigned0(this) + def isUnsigned1: isUnsigned1 = attribute.isUnsigned1(this) + def isVtype: isVtype = attribute.isVtype(this) + def isVwmacc: isVwmacc = attribute.isVwmacc(this) + def isWidenreduce: isWidenreduce = attribute.isWidenreduce(this) + def isZvbb: isZvbb = attribute.isZvbb(this) + def isZvma: isZvma = attribute.isZvma(this) + def isMaskPip: isMaskPipeType = attribute.isMaskPipeType(this) + def isWriteCount: isWriteCount = attribute.isWriteCount(this) + def fpExecutionType: FpExecutionType.Type = attribute.FpExecutionType(this) + def topUop: TopUop = attribute.TopUop(this) + def decoderUop: DecoderUop = attribute.DecoderUop(this) + def maskPipeUop: MaskPipeOpcode = attribute.MaskPipeOpcode(this) + + private def documentation: String = InstructionDocumentation(instruction, param).toString + + // This is the OM for this instruction + def om: Property[ClassType] = { + val obj = Instantiate( + new T1InstructionOM( + instruction.name, + bitPat.rawString, + documentation + ) + ) + // convert in-memory attributes to Chisel Property + // get type of [[T1DecodeAttributeOM]] + obj.attributesIn :#= Property( + Seq( + isVector, + isAdder, + isAverage, + isCompress, + isCrossread, + isCrosswrite, + isDivider, + isDontneedexecuteinlane, + isExtend, + isFcompare, + isFfo, + isFirstwiden, + isFloatmul, + isFloat, + isFloattype, + isFma, + isFother, + isGather16, + isGather, + isId, + isIndextype, + isIota, + isItype, + isLogic, + isMaskdestination, + isMasklogic, + isMasksource, + isMaskunit, + isMulticycle, + isMultiplier, + isMv, + isNarrow, + isNr, + isOrderreduce, + isOther, + isPopcount, + isReadonly, + isRed, + isReverse, + isSaturate, + isScheduler, + isShift, + isSlid, + isSpecial, + isSpecialslot, + isSreadvd, + isSwrite, + isTargetrd, + isUnorderwrite, + isUnsigned0, + isUnsigned1, + isVtype, + isVwmacc, + isWidenreduce + ).map(_.om.asAnyClassType) + ) + obj.getPropertyReference + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala new file mode 100644 index 00000000..603e049c --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder + +import chisel3.util._ +import chisel3.util.experimental.decode.TruthTable + +import scala.language.postfixOps + +object TableGenerator extends App { + implicit class CrossAble[X](xs: Traversable[X]) { + def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { + x <- xs + y <- ys + } yield (x, y) + } + implicit def bool2str(b: Boolean): String = if (b) "b1" else "b0" + + object LogicTable { + object LogicOpcode { + var index = 0 + } + + sealed trait LogicOpcode { + val value: Int = LogicOpcode.index + LogicOpcode.index = LogicOpcode.index + 1 + } + + trait Operand + + trait BinaryOperand extends Operand { + def op(op0: Boolean, op1: Boolean): Boolean + } + + case object and extends BinaryOperand with LogicOpcode { + override def op(op0: Boolean, op1: Boolean): Boolean = op0 && op1 + } + + case object or extends BinaryOperand with LogicOpcode { + override def op(op0: Boolean, op1: Boolean): Boolean = op0 || op1 + } + + case object xor extends BinaryOperand with LogicOpcode { + override def op(op0: Boolean, op1: Boolean): Boolean = op0 != op1 + } + + val opList: Seq[BinaryOperand with LogicOpcode] = Seq(and, or, xor) + val bitValue: Seq[Boolean] = Seq(true, false) + + val table: List[(BitPat, BitPat)] = bitValue + .cross(bitValue) + .cross(opList) + .map { case ((op0, op1), op) => + BitPat(toBinary(op.value)) ## BitPat(op0) ## BitPat(op1) -> BitPat(op.op(op0, op1)) + } + .toList + } + + object LaneDecodeTable { + object LaneUop { + var index = 0 + } + + sealed trait LaneUop { + val value: Int = LaneUop.index + LaneUop.index = LaneUop.index + 1 + } + + /*object SubUnitCode { + var index = 1 + } + + sealed trait SubUnitCode { + val value: Int = SubUnitCode.index + SubUnitCode.index = SubUnitCode.index << 1 + }*/ + trait BaseObject + trait SubUnit extends BaseObject + + trait LogicUnit extends SubUnit + trait Arithmetic extends SubUnit + trait Shift extends SubUnit + trait Mul extends SubUnit + trait Div extends SubUnit + trait PopCount extends SubUnit + trait FFO extends SubUnit + trait GetIndex extends SubUnit + trait DataProcess extends SubUnit + + def subUnitCode(in: SubUnit): Int = { + in match { + case unit: LogicUnit => 1 + case arithmetic: Arithmetic => 2 + case shift: Shift => 4 + case mul: Mul => 8 + case div: Div => 16 + case count: PopCount => 32 + case ffo: FFO => 64 + case index: GetIndex => 128 + case process: DataProcess => 256 + case _ => 0 + } + } + + case object and extends LogicUnit with LaneUop + case object nand extends LogicUnit with LaneUop + case object andn extends LogicUnit with LaneUop + case object or extends LogicUnit with LaneUop + case object nor extends LogicUnit with LaneUop + case object orn extends LogicUnit with LaneUop + case object xor extends LogicUnit with LaneUop + case object xnor extends LogicUnit with LaneUop + case object add extends Arithmetic with LaneUop + case object sub extends Arithmetic with LaneUop + case object adc extends Arithmetic with LaneUop + case object madc extends Arithmetic with LaneUop + case object sbc extends Arithmetic with LaneUop + case object msbc extends Arithmetic with LaneUop + case object slt extends Arithmetic with LaneUop + case object sltu extends Arithmetic with LaneUop + case object sle extends Arithmetic with LaneUop + case object sleu extends Arithmetic with LaneUop + case object sgt extends Arithmetic with LaneUop + case object sgtu extends Arithmetic with LaneUop + case object sge extends Arithmetic with LaneUop + case object sgeu extends Arithmetic with LaneUop + case object max extends Arithmetic with LaneUop + case object maxu extends Arithmetic with LaneUop + case object min extends Arithmetic with LaneUop + case object minu extends Arithmetic with LaneUop + case object sll extends Shift with LaneUop + case object srl extends Shift with LaneUop + case object sra extends Shift with LaneUop + case object ssrl extends Shift with LaneUop + case object ssra extends Shift with LaneUop + case object mul extends Mul with LaneUop + case object mulh extends Mul with LaneUop + case object mulhu extends Mul with LaneUop + case object mulhsu extends Mul with LaneUop + case object ma extends Mul with LaneUop + case object ms extends Mul with LaneUop + case object div extends Div with LaneUop + case object divu extends Div with LaneUop + case object rem extends Div with LaneUop + case object remu extends Div with LaneUop + case object popCount extends PopCount with LaneUop + case object ffo extends FFO with LaneUop + case object ffB extends FFO with LaneUop + case object ffInc extends FFO with LaneUop + case object ffID extends FFO with LaneUop + case object getID extends GetIndex with LaneUop + } + + object BankEnableTable { + // TODO + val maskList: Seq[Int] = Seq(1, 3, 15) + val maskSizeList: Seq[Int] = Seq(1, 2, 4) + var table: List[(BitPat, BitPat)] = List.empty + for { + eew <- 0 to 2 + vs <- 0 to 3 + groupId <- 0 to 3 + v <- Seq(true, false) + } { + var mask = if (v) maskList(eew) else 0 + val maskSize = maskSizeList(eew) + val index = (maskSize * (vs + groupId)) % 4 + mask <<= index + table :+= BitPat(v) ## BitPat(toBinary(eew, 2)) ## BitPat(toBinary(vs, 2)) ## BitPat( + toBinary(groupId, 2) + ) -> BitPat(toBinary(index, 2)) ## BitPat(toBinary(mask, 4)) + } + val res: TruthTable = TruthTable(table, BitPat.dontCare(6)) + } + + def toBinary(i: Int, digits: Int = 3): String = { + String.format("b%" + digits + "s", i.toBinaryString).replace(' ', '0') + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala new file mode 100644 index 00000000..4e722823 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait AdderUOPType extends Uop +object addUop0 extends AdderUOPType +object addUop1 extends AdderUOPType +object addUop2 extends AdderUOPType +object addUop3 extends AdderUOPType +object addUop4 extends AdderUOPType +object addUop6 extends AdderUOPType +object addUop7 extends AdderUOPType +object addUop8 extends AdderUOPType +object addUop9 extends AdderUOPType +object addUop10 extends AdderUOPType +object addUop11 extends AdderUOPType + +object AdderUOP { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> addUop0, + t1 _ -> addUop1, + t2 _ -> addUop2, + t3 _ -> addUop3, + t4 _ -> addUop4, + t6 _ -> addUop6, + t7 _ -> addUop7, + t8 _ -> addUop8, + t9 _ -> addUop9, + t10 _ -> addUop10, + t11 _ -> addUop11 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vredsum.vs", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwredsum.vs", + "vwredsumu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vrsub.vi", + "vrsub.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vredmax.vs", + "vredmaxu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vredmin.vs", + "vredminu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmseq.vi", + "vmseq.vv", + "vmseq.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsne.vi", + "vmsne.vv", + "vmsne.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vsbc.vvm", + "vsbc.vxm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala new file mode 100644 index 00000000..70bd21af --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait DivUOPType extends Uop +object divUop0 extends DivUOPType +object divUop1 extends DivUOPType +object divUop8 extends DivUOPType +object divUop9 extends DivUOPType +object divUop10 extends DivUOPType + +object DivUOP { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> divUop0, + t1 _ -> divUop1, + t8 _ -> divUop8, + t9 _ -> divUop9, + t10 _ -> divUop10 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfdiv.vf", + "vfdiv.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfsqrt.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfrdiv.vf" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala new file mode 100644 index 00000000..dc7649f1 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait FloatUopType extends Uop +object FUT0 extends FloatUopType +object FUT1 extends FloatUopType +object FUT2 extends FloatUopType +object FUT3 extends FloatUopType +object FUT4 extends FloatUopType +object FUT5 extends FloatUopType +object FUT6 extends FloatUopType +object FUT7 extends FloatUopType +object FUT8 extends FloatUopType +object FUT9 extends FloatUopType +object FUT10 extends FloatUopType +object FUT12 extends FloatUopType +object FUT13 extends FloatUopType +object FUT14 extends FloatUopType + +object FloatUop { + def apply(t1DecodePattern: T1DecodePattern) = { + Seq( + t0 _ -> FUT0, + t1 _ -> FUT1, + t2 _ -> FUT2, + t3 _ -> FUT3, + t4 _ -> FUT4, + t5 _ -> FUT5, + t6 _ -> FUT6, + t7 _ -> FUT7, + t8 _ -> FUT8, + t9 _ -> FUT9, + t10 _ -> FUT10, + t12 _ -> FUT12, + t13 _ -> FUT13, + t14 _ -> FUT14 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => + !(t1(t1DecodePattern) + || t2(t1DecodePattern) + || t3(t1DecodePattern) + || t4(t1DecodePattern) + || t5(t1DecodePattern) + || t6(t1DecodePattern) + || t7(t1DecodePattern) + || t8(t1DecodePattern) + || t9(t1DecodePattern) + || t10(t1DecodePattern) + || t12(t1DecodePattern) + || t13(t1DecodePattern) + || t14(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmsac.vf", + "vfmsac.vv", + "vfsgnj.vf", + "vfsgnj.vv", + "vmfeq.vf", + "vmfeq.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmsac.vf", + "vfnmsac.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vmflt.vf", + "vmflt.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmacc.vf", + "vfnmacc.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vmfle.vf", + "vmfle.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfclass.v", + "vfmadd.vf", + "vfmadd.vv", + "vmfgt.vf" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmsub.vf", + "vfmsub.vv", + "vmfge.vf" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmsub.vf", + "vfnmsub.vv", + "vfrec7.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmadd.vf", + "vfnmadd.vv", + "vfrsqrt7.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfadd.vf", + "vfadd.vv", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfmin.vf", + "vfmin.vv", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.xu.f.v", + "vfsub.vf", + "vfsub.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.x.f.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t12(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmax.vf", + "vfmax.vv", + "vfredmax.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t13(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.rtz.xu.f.v", + "vfrsub.vf" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t14(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.rtz.x.f.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala new file mode 100644 index 00000000..22312909 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object FpExecutionType { + trait Type extends Uop { + def apply(t1DecodePattern: T1DecodePattern): Boolean + } + case object Compare extends Type { + def apply(t1DecodePattern: T1DecodePattern): Boolean = isFcompare.y(t1DecodePattern) + } + case object Other extends Type { + def apply(t1DecodePattern: T1DecodePattern): Boolean = isFother.y(t1DecodePattern) + } + case object MA extends Type { + def apply(t1DecodePattern: T1DecodePattern): Boolean = + !(isFcompare.y(t1DecodePattern) || isFother.y(t1DecodePattern)) + } + case object Nil extends Type { + def apply(t1DecodePattern: T1DecodePattern): Boolean = { + require(requirement = false, "unreachable") + false + } + } + def apply(t1DecodePattern: T1DecodePattern): Type = { + val tpe = Seq(Compare, Other, MA).filter(tpe => tpe(t1DecodePattern)) + require(tpe.size <= 1) + tpe.headOption.getOrElse(Nil) + } +} + +case class FpExecutionType(value: FpExecutionType.Type) extends UopDecodeAttribute[FpExecutionType.Type] { + override val description: String = "float uop, goes to [[org.chipsalliance.t1.rtl.LaneFloatRequest.unitSelet]]" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala new file mode 100644 index 00000000..93cacd7b --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isAdder { + def apply(t1DecodePattern: T1DecodePattern): isAdder = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isAdder(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredsum.vs", + "vrsub.vi", + "vrsub.vx", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsbc.vvm", + "vsbc.vxm", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isAdder(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneAdder]]." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala new file mode 100644 index 00000000..73987b23 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isAverage { + def apply(t1DecodePattern: T1DecodePattern): isAverage = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isAverage(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class isAverage(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "For adder, does it need to take care of saturate. TODO: add to uop " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala new file mode 100644 index 00000000..75327c57 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isCompress { + def apply(t1DecodePattern: T1DecodePattern): isCompress = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isCompress(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isCompress(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "lane will read data from vs2, send to Sequencer. then Sequencer will read vs1 for mask. use mask to compress data in vs2. and write to vd at last. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala new file mode 100644 index 00000000..f70f5b41 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isCrossread { + def apply(t1DecodePattern: T1DecodePattern): isCrossread = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isCrossread(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.wv", + "vwsubu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isCrossread(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "Read vs2 or vd with cross read channel. crossRead -> narrow || firstWiden " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala new file mode 100644 index 00000000..ed17151c --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isCrosswrite { + def apply(t1DecodePattern: T1DecodePattern): isCrosswrite = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isCrosswrite(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + // rv_zvbb + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class isCrosswrite(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane should write to another lane" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala new file mode 100644 index 00000000..d2ff7438 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isDivider { + def apply(t1DecodePattern: T1DecodePattern): isDivider = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isDivider(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfdiv.vf", + "vfdiv.vv", + "vfrdiv.vf", + "vfsqrt.v", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isDivider(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "goes to [[org.chipsalliance.t1.rtl.LaneDiv]] or [[org.chipsalliance.t1.rtl.LaneDivFP]]. if FP exist, all div goes to [[org.chipsalliance.t1.rtl.LaneDivFP]]" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala new file mode 100644 index 00000000..3385935b --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isDontneedexecuteinlane { + def apply(t1DecodePattern: T1DecodePattern): isDontneedexecuteinlane = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isDontneedexecuteinlane(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfslide1down.vf", + "vfslide1up.vf", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vcompress.vm", + "viota.m", + "vl1re16.v", + "vl1re32.v", + "vl1re64.v", + "vl1re8.v", + "vl2re16.v", + "vl2re32.v", + "vl2re64.v", + "vl2re8.v", + "vl4re16.v", + "vl4re32.v", + "vl4re64.v", + "vl4re8.v", + "vl8re16.v", + "vl8re32.v", + "vl8re64.v", + "vl8re8.v", + "vle1024.v", + "vle1024ff.v", + "vle128.v", + "vle128ff.v", + "vle16.v", + "vle16ff.v", + "vle256.v", + "vle256ff.v", + "vle32.v", + "vle32ff.v", + "vle512.v", + "vle512ff.v", + "vle64.v", + "vle64ff.v", + "vle8.v", + "vle8ff.v", + "vlm.v", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vlse1024.v", + "vlse128.v", + "vlse16.v", + "vlse256.v", + "vlse32.v", + "vlse512.v", + "vlse64.v", + "vlse8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vrgather.vv", + "vrgatherei16.vv", + "vs1r.v", + "vs2r.v", + "vs4r.v", + "vs8r.v", + "vse1024.v", + "vse128.v", + "vse16.v", + "vse256.v", + "vse32.v", + "vse512.v", + "vse64.v", + "vse8.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsm.v", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsse1024.v", + "vsse128.v", + "vsse16.v", + "vsse256.v", + "vsse32.v", + "vsse512.v", + "vsse64.v", + "vsse8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isDontneedexecuteinlane(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "It is no longer executed in the execution unit, but it may pass through the pipe (expected to pass through the pipe in the future)" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala new file mode 100644 index 00000000..df57b48f --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isExtend { + def apply(t1DecodePattern: T1DecodePattern): isExtend = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isExtend(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isExtend(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "send element to MaskUnit at top, extend and broadcast to multiple Lanes." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala new file mode 100644 index 00000000..83cbbd1d --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFcompare { + def apply(t1DecodePattern: T1DecodePattern): isFcompare = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFcompare(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfmax.vf", + "vfmax.vv", + "vfmin.vf", + "vfmin.vv", + "vfredmax.vs", + "vfredmin.vs", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFcompare(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: remove it, but remains attribute." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala new file mode 100644 index 00000000..95ad026d --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFfo { + def apply(t1DecodePattern: T1DecodePattern): isFfo = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFfo(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfirst.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFfo(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "find first one, lane will report if 1 is found, Sequencer should decide which is exactly the first 1 in lanes. after 1 is found, tell each lane, 1 has been found at which the corresponding location. lane will stale at stage2. TODO: should split into lane control uop " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala new file mode 100644 index 00000000..c14dc3ee --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFirstwiden { + def apply(t1DecodePattern: T1DecodePattern): isFirstwiden = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFirstwiden(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wv", + "vnsrl.wx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.wv", + "vwsubu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFirstwiden(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "There are two types of widen: - vd -> widen. - vs2, vd -> widen. This op will widen vs2. TODO: remove it as attribute." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala new file mode 100644 index 00000000..48d776af --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFloat { + def apply(t1DecodePattern: T1DecodePattern): isFloat = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFloat(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = + if (t1DecodePattern.param.fpuEnable) + Seq( + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv" + ) + else Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFloat(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneFloat]]." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala new file mode 100644 index 00000000..d13574ab --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFloatmul { + def apply(t1DecodePattern: T1DecodePattern): isFloatmul = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFloatmul(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = + if (t1DecodePattern.param.fpuEnable) + Seq( + "vfmul.vf", + "vfmul.vv" + ) + else Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFloatmul(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: add op." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala new file mode 100644 index 00000000..c18a353d --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFloattype { + def apply(t1DecodePattern: T1DecodePattern): isFloattype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFloattype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = + if (t1DecodePattern.param.fpuEnable) + Seq( + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmv.v.f", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv" + ) + else Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFloattype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "is a float type. TODO: remove it." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala new file mode 100644 index 00000000..61dd3c8c --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFma { + def apply(t1DecodePattern: T1DecodePattern): isFma = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFma(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfadd.vf", + "vfadd.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfredosum.vs", + "vfredusum.vs", + "vfrsub.vf", + "vfsub.vf", + "vfsub.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFma(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "uop of FMA, goes to [[org.chipsalliance.t1.rtl.LaneFloat]] FMA unit." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala new file mode 100644 index 00000000..965c26c4 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isFother { + def apply(t1DecodePattern: T1DecodePattern): isFother = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFother(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfrec7.v", + "vfrsqrt7.v", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFother(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "designed for Other Unit in FP. goes to [[org.chipsalliance.t1.rtl.LaneFloat]] OtherUnit. TODO: perf it." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala new file mode 100644 index 00000000..83b6e01d --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isGather { + def apply(t1DecodePattern: T1DecodePattern): isGather = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isGather(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isGather(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "lane will read index from vs1, send to Sequencer. mask unit will calculate vrf address based on the vs1 from lane, and send read request to lanes, lanes should read it and send vs2 to Sequencer. Sequencer will write vd at last. address: 0 -> vlmax(sew decide address width.) " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala new file mode 100644 index 00000000..5552833c --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isGather16 { + def apply(t1DecodePattern: T1DecodePattern): isGather16 = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isGather16(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vrgatherei16.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isGather16(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "same with [[gather]] ignore sew, address width is fixed to 16. @note When SEW=8, vrgather.vv can only reference vector elements 0-255. The vrgatherei16 form can index 64K elements, and can also be used to reduce the register capacity needed to hold indices when SEW > 16. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala new file mode 100644 index 00000000..07349be3 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isId { + def apply(t1DecodePattern: T1DecodePattern): isId = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isId(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfdiv.vf", + "vfdiv.vv", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrdiv.vf", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "vid.v", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wv", + "vnsrl.wx", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.wv", + "vwsub.wx", + "vwsubu.wv", + "vwsubu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isId(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "write 0...vlmax to VRF. Lane other unit should handle it. TODO: remove it, it's a uop. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala new file mode 100644 index 00000000..cd4426fe --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isIndextype { + def apply(t1DecodePattern: T1DecodePattern): isIndextype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isIndextype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isIndextype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: remove it." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala new file mode 100644 index 00000000..c2dd11a6 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isIota { + def apply(t1DecodePattern: T1DecodePattern): isIota = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isIota(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "viota.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isIota(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "lane will read vs2 from VRF, send to Top. Top read v0(at register) calculate the result and write back to VRFs " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala new file mode 100644 index 00000000..f08b07f2 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isItype { + def apply(t1DecodePattern: T1DecodePattern): isItype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isItype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadd.vi", + "vand.vi", + "vmadc.vi", + "vmadc.vim", + "vmerge.vim", + "vmv.v.i", + "vmseq.vi", + "vmsgt.vi", + "vmsgtu.vi", + "vmsle.vi", + "vmsleu.vi", + "vmsne.vi", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vnclip.wi", + "vnclipu.wi", + "vnsra.wi", + "vnsrl.wi", + "vor.vi", + "vrgather.vi", + "vrsub.vi", + "vsadd.vi", + "vsaddu.vi", + "vslidedown.vi", + "vslideup.vi", + "vsll.vi", + "vsra.vi", + "vsrl.vi", + "vssra.vi", + "vssrl.vi", + "vxor.vi", + // rv_zvbb + "vror.vi", + "vwsll.vi" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isItype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "src is imm." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala new file mode 100644 index 00000000..0b4c45bb --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isLogic { + def apply(t1DecodePattern: T1DecodePattern): isLogic = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isLogic(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vand.vi", + "vand.vv", + "vand.vx", + "vmand.mm", + "vmandn.mm", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmxnor.mm", + "vmxor.mm", + "vor.vi", + "vor.vv", + "vor.vx", + "vredand.vs", + "vredor.vs", + "vredxor.vs", + "vxor.vi", + "vxor.vv", + "vxor.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isLogic(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "Instruction should use [[org.chipsalliance.t1.rtl.decoder.TableGenerator.LaneDecodeTable.LogicUnit]]." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala new file mode 100644 index 00000000..72ee2cbe --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMaskPipeType { + def apply(t1DecodePattern: T1DecodePattern): isMaskPipeType = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMaskPipeType(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val isExtend = Seq( + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + + val isCrossWrite = Seq( + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + // rv_zvbb + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + + val isSlide = Seq( + "vfslide1down.vf", + "vfslide1up.vf", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx" + ) + + val isGather = Seq( + "vrgather.vv", + "vrgatherei16.vv" + ) + + val isReduce = Seq( + "vcpop.m", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfwredosum.vs", + "vfwredusum.vs", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vwredsum.vs", + "vwredsumu.vs" + ) + + val allMatched = isExtend ++ isCrossWrite ++ isSlide ++ isGather ++ isReduce + + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMaskPipeType(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala new file mode 100644 index 00000000..f143ef20 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMaskdestination { + def apply(t1DecodePattern: T1DecodePattern): isMaskdestination = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMaskdestination(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMaskdestination(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "vd is mask format. execute at lane, send result to Sequencer, regroup it and write to vd. if datapath is unaligned, need to take care the tail. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala new file mode 100644 index 00000000..4469e9a4 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMasklogic { + def apply(t1DecodePattern: T1DecodePattern): isMasklogic = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMasklogic(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "viota.m", + "vmand.mm", + "vmandn.mm", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmxnor.mm", + "vmxor.mm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMasklogic(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "only one or two operators src is mask format(one element one bit). vl should align with src. if datapath is unaligned, need to take care the tail. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala new file mode 100644 index 00000000..27dada01 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMasksource { + def apply(t1DecodePattern: T1DecodePattern): isMasksource = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMasksource(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vfmerge.vfm", + "vfmv.v.f", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmerge.vim", + "vmv.v.i", + "vmerge.vvm", + "vmv.v.v", + "vmerge.vxm", + "vmv.v.x", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vsbc.vvm", + "vsbc.vxm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMasksource(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "three ops. these ops don't use mask. use v0 as third op, read it from duplicate V0. it will read use mask(v0) in mask format as source. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala new file mode 100644 index 00000000..e415460c --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMaskunit { + def apply(t1DecodePattern: T1DecodePattern): isMaskunit = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMaskunit(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val mvType = Seq( + "vfmv.f.s", + "vfmv.s.f", + "vmv.s.x", + "vmv.x.s" + ) + val compress = Seq( + "vcompress.vm", + "viota.m" + ) + val maskDestination = Seq( + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m" + ) + val isFFO = Seq( + "vfirst.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m" + ) + val allMatched = mvType ++ compress ++ maskDestination ++ isFFO + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMaskunit(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "mask unit -> red || compress || viota || ffo || slid || maskDestination || gather(v) || mv || popCount || extend all instruction in Sequencer mask unit. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala new file mode 100644 index 00000000..5825ac17 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMulticycle { + def apply(t1DecodePattern: T1DecodePattern): isMulticycle = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMulticycle(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMulticycle(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: remove? only Div or customer" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala new file mode 100644 index 00000000..bd0833ce --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMultiplier { + def apply(t1DecodePattern: T1DecodePattern): isMultiplier = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMultiplier(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vmacc.vv", + "vmacc.vx", + "vmadd.vv", + "vmadd.vx", + "vmul.vv", + "vmul.vx", + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vnmsac.vv", + "vnmsac.vx", + "vnmsub.vv", + "vnmsub.vx", + "vsmul.vv", + "vsmul.vx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMultiplier(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneMul]]. (only apply to int mul)" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala new file mode 100644 index 00000000..1704a7d6 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isMv { + def apply(t1DecodePattern: T1DecodePattern): isMv = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMv(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfmv.f.s", + "vfmv.s.f", + "vmv.s.x", + "vmv.x.s" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMv(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "move instruction, v->v s->v x->v, single element move. TODO: split them into multiple op since datapath differs " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala new file mode 100644 index 00000000..4c162533 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isNarrow { + def apply(t1DecodePattern: T1DecodePattern): isNarrow = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isNarrow(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isNarrow(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + " dual width of src will be convert to single width to dst. narrow can be the src of chain. as the dst of chain, only can be fed with Load. TODO: remove it as attribute. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala new file mode 100644 index 00000000..178bfa12 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isNr { + def apply(t1DecodePattern: T1DecodePattern): isNr = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isNr(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isNr(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "for vmvnr, move vreg group to another vreg group. it will ignore lmul, use from instr. chainable" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala new file mode 100644 index 00000000..34167406 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isOrderreduce { + def apply(t1DecodePattern: T1DecodePattern): isOrderreduce = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isOrderreduce(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfredosum.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isOrderreduce(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "don't use it, it's slow, lane read all elements from VRF, send to Top." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala new file mode 100644 index 00000000..63c3559e --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isOther { + def apply(t1DecodePattern: T1DecodePattern): isOther = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isOther(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "vfmerge.vfm", + "vfmv.v.f", + "vfmv.s.f", + "vid.v", + "vmerge.vim", + "vmv.v.i", + "vmerge.vvm", + "vmv.v.v", + "vmerge.vxm", + "vmv.v.x", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isOther(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.OtherUnit]]" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala new file mode 100644 index 00000000..fcf7e4a0 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isPopcount { + def apply(t1DecodePattern: T1DecodePattern): isPopcount = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isPopcount(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isPopcount(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + " count how many 1s in VS2. lane will use [[org.chipsalliance.t1.rtl.OtherUnit]] to how many 1s locally; use reduce datapath to accumulate, send total result to top top will send result to vd. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala new file mode 100644 index 00000000..0fd34132 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isReadonly { + def apply(t1DecodePattern: T1DecodePattern): isReadonly = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isReadonly(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "viota.m", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isReadonly(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "lane read only instructions. for these instructions lane will only read vrf and send data back to Sequencer. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala new file mode 100644 index 00000000..8f7e0ef1 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isRed { + def apply(t1DecodePattern: T1DecodePattern): isRed = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isRed(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfwredosum.vs", + "vfwredusum.vs", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vwredsum.vs", + "vwredsumu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isRed(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "do reduce in each lane. each element will sequentially executed in each lanes. after finishing, pop it to Top, and use ALU at top to get the final result and send to element0 TODO: better name. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala new file mode 100644 index 00000000..6f12d7e1 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isReverse { + def apply(t1DecodePattern: T1DecodePattern): isReverse = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isReverse(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vrsub.vi", + "vrsub.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isReverse(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "only instruction will switch src. TODO: send it to uop. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala new file mode 100644 index 00000000..dcef5855 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isSaturate { + def apply(t1DecodePattern: T1DecodePattern): isSaturate = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSaturate(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsmul.vv", + "vsmul.vx", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class isSaturate(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "For adder, does it need to take care of saturate. TODO: add to uop " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala new file mode 100644 index 00000000..6d3f1db9 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isScheduler { + def apply(t1DecodePattern: T1DecodePattern): isScheduler = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isScheduler(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vand.vi", + "vand.vv", + "vand.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmv.v.f", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vid.v", + "vmacc.vv", + "vmacc.vx", + "vmadd.vv", + "vmadd.vx", + "vmand.mm", + "vmandn.mm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmerge.vim", + "vmv.v.i", + "vmerge.vvm", + "vmv.v.v", + "vmerge.vxm", + "vmv.v.x", + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmul.vv", + "vmul.vx", + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnmsac.vv", + "vnmsac.vx", + "vnmsub.vv", + "vnmsub.vx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vor.vi", + "vor.vv", + "vor.vx", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vrgather.vi", + "vrgather.vx", + "vrsub.vi", + "vrsub.vx", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsbc.vvm", + "vsbc.vxm", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsmul.vv", + "vsmul.vx", + "vsra.vi", + "vsra.vv", + "vsra.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vxor.vi", + "vxor.vv", + "vxor.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isScheduler(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "lane will send request to Sequencer and wait ack from Sequencer. Instructions that will communicate with T1 top module.*/ " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala new file mode 100644 index 00000000..7fd1ba80 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isShift { + def apply(t1DecodePattern: T1DecodePattern): isShift = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isShift(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsra.vi", + "vsra.vv", + "vsra.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isShift(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneShifter]]." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala new file mode 100644 index 00000000..994693da --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isSlid { + def apply(t1DecodePattern: T1DecodePattern): isSlid = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSlid(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfslide1down.vf", + "vfslide1up.vf", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSlid(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "used in Sequencer mask unit, decide which vrf should be read. send read request to corresponding lane, lane will respond data to Sequencer. Sequencer will write data to VD. mask unit is work as the router here. TODO: opimize mask unit. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala new file mode 100644 index 00000000..37ac7f9e --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isSpecial { + def apply(t1DecodePattern: T1DecodePattern): isSpecial = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSpecial(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "vcpop.m", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfslide1down.vf", + "vfslide1up.vf", + "vfwredosum.vs", + "vfwredusum.vs", + "viota.m", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrgather.vv", + "vrgatherei16.vv", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vwredsum.vs", + "vwredsumu.vs", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSpecial(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "if Sequencer is the router for data from Lane to LSU or Sequencer mask unit. special -> maskUnit || index type load store " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala new file mode 100644 index 00000000..d54efaa4 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isSpecialslot { + def apply(t1DecodePattern: T1DecodePattern): isSpecialslot = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSpecialslot(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vcpop.m", + "vfirst.m", + "vfmerge.vfm", + "vfmv.v.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmand.mm", + "vmandn.mm", + "vmerge.vim", + "vmv.v.i", + "vmerge.vvm", + "vmv.v.v", + "vmerge.vxm", + "vmv.v.x", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vsbc.vvm", + "vsbc.vxm", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSpecialslot(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "special instructions schedule to slot0." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala new file mode 100644 index 00000000..2f9a2d4a --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isSreadvd { + def apply(t1DecodePattern: T1DecodePattern): isSreadvd = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSreadvd(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vand.vi", + "vand.vv", + "vand.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vcompress.vm", + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmv.v.f", + "vfmin.vf", + "vfmin.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vid.v", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmerge.vim", + "vmv.v.i", + "vmerge.vvm", + "vmv.v.v", + "vmerge.vxm", + "vmv.v.x", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmul.vv", + "vmul.vx", + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vor.vi", + "vor.vv", + "vor.vx", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv", + "vrsub.vi", + "vrsub.vx", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsbc.vvm", + "vsbc.vxm", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsmul.vv", + "vsmul.vx", + "vsra.vi", + "vsra.vv", + "vsra.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vxor.vi", + "vxor.vv", + "vxor.vx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSreadvd(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "sReadVD -> !(ma || maskLogic): instructions that need to read vd as the operator. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala new file mode 100644 index 00000000..48db0886 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isSwrite { + def apply(t1DecodePattern: T1DecodePattern): isSwrite = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSwrite(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "vfmv.f.s", + "vl1re16.v", + "vl1re32.v", + "vl1re64.v", + "vl1re8.v", + "vl2re16.v", + "vl2re32.v", + "vl2re64.v", + "vl2re8.v", + "vl4re16.v", + "vl4re32.v", + "vl4re64.v", + "vl4re8.v", + "vl8re16.v", + "vl8re32.v", + "vl8re64.v", + "vl8re8.v", + "vle1024.v", + "vle1024ff.v", + "vle128.v", + "vle128ff.v", + "vle16.v", + "vle16ff.v", + "vle256.v", + "vle256ff.v", + "vle32.v", + "vle32ff.v", + "vle512.v", + "vle512ff.v", + "vle64.v", + "vle64ff.v", + "vle8.v", + "vle8ff.v", + "vlm.v", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vlse1024.v", + "vlse128.v", + "vlse16.v", + "vlse256.v", + "vlse32.v", + "vlse512.v", + "vlse64.v", + "vlse8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmv.x.s", + "vs1r.v", + "vs2r.v", + "vs4r.v", + "vs8r.v", + "vse1024.v", + "vse128.v", + "vse16.v", + "vse256.v", + "vse32.v", + "vse512.v", + "vse64.v", + "vse8.v", + "vsm.v", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsse1024.v", + "vsse128.v", + "vsse16.v", + "vsse256.v", + "vsse32.v", + "vsse512.v", + "vsse64.v", + "vsse8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + // rv_zvbb + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSwrite(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "sWrite -> targetRd || readOnly || crossWrite || maskDestination || reduce || loadStore instruction will write vd or rd(scalar) from outside of lane. It will request vrf wait, and lane will not write. No write to vd when isSwrite is True!!!" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala new file mode 100644 index 00000000..f862fbf4 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isTargetrd { + def apply(t1DecodePattern: T1DecodePattern): isTargetrd = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isTargetrd(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "vfmv.f.s", + "vmv.x.s" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isTargetrd(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "write rd/fd at scalar core." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala new file mode 100644 index 00000000..828c1ace --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isUnorderwrite { + def apply(t1DecodePattern: T1DecodePattern): isUnorderwrite = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isUnorderwrite(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfmv.f.s", + "vfmv.s.f", + "vfredosum.vs", + "vfslide1down.vf", + "vfslide1up.vf", + "viota.m", + "vmv.s.x", + "vmv.x.s", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isUnorderwrite(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "unmanaged write for VRF. these instructions cannot be chain as source. TODO: add an attribute these instruction cannot be the source of chaining. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala new file mode 100644 index 00000000..ddedf7d8 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isUnsigned0 { + def apply(t1DecodePattern: T1DecodePattern): isUnsigned0 = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isUnsigned0(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaaddu.vv", + "vaaddu.vx", + "vasubu.vv", + "vasubu.vx", + "vcpop.m", + "vdivu.vv", + "vdivu.vx", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmaxu.vv", + "vmaxu.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsof.m", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vredmaxu.vs", + "vredminu.vs", + "vremu.vv", + "vremu.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssubu.vv", + "vssubu.vx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsumu.vs", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + // rv_zvbb + "vandn.vv", + "vandn.vx", + "vbrev.v", + "vbrev8.v", + "vrev8.v", + "vclz.v", + "vctz.v", + "vcpop.v", + "vrol.vv", + "vrol.vx", + "vror.vv", + "vror.vx", + "vror.vi", + "vwsll.vv", + "vwsll.vx", + "vwsll.vi", + "vfslide1down.vf", + "vfslide1up.vf", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isUnsigned0(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "is src0 unsigned? used everywhere in Lane and VFU. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala new file mode 100644 index 00000000..a9500f99 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isUnsigned1 { + def apply(t1DecodePattern: T1DecodePattern): isUnsigned1 = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isUnsigned1(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaaddu.vv", + "vaaddu.vx", + "vasubu.vv", + "vasubu.vx", + "vcpop.m", + "vdivu.vv", + "vdivu.vx", + "vfcvt.f.xu.v", + "vfcvt.rtz.xu.f.v", + "vfirst.m", + "vid.v", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmaxu.vv", + "vmaxu.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsof.m", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vredmaxu.vs", + "vredminu.vs", + "vremu.vv", + "vremu.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssubu.vv", + "vssubu.vx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsumu.vs", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + // rv_zvbb + "vandn.vv", + "vandn.vx", + "vbrev.v", + "vbrev8.v", + "vrev8.v", + "vclz.v", + "vctz.v", + "vcpop.v", + "vrol.vv", + "vrol.vx", + "vror.vv", + "vror.vx", + "vror.vi", + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isUnsigned1(value: TriState) extends BooleanDecodeAttribute { + override val description: String = " is src1 unsigned? used everywhere in Lane and VFU. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala new file mode 100644 index 00000000..159418a4 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isVector { + def apply(t1DecodePattern: T1DecodePattern): isVector = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isVector(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => i.instructionSet.name == "rv_v") + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isVector(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "This instruction should be decode by T1." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala new file mode 100644 index 00000000..c89df48e --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isVtype { + def apply(t1DecodePattern: T1DecodePattern): isVtype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isVtype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaaddu.vv", + "vadc.vvm", + "vadd.vv", + "vand.vv", + "vasub.vv", + "vasubu.vv", + "vcompress.vm", + "vcpop.m", + "vdiv.vv", + "vdivu.vv", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vv", + "vfirst.m", + "vfmacc.vv", + "vfmadd.vv", + "vfmax.vv", + "vfmin.vv", + "vfmsac.vv", + "vfmsub.vv", + "vfmul.vv", + "vfmv.f.s", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vv", + "vfnmadd.vv", + "vfnmsac.vv", + "vfnmsub.vv", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfsgnj.vv", + "vfsgnjn.vv", + "vfsgnjx.vv", + "vfsqrt.v", + "vfsub.vv", + "vfwadd.vv", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vv", + "vfwmsac.vv", + "vfwmul.vv", + "vfwnmacc.vv", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vv", + "vfwsub.wv", + "vid.v", + "viota.m", + "vmacc.vv", + "vmadc.vv", + "vmadc.vvm", + "vmadd.vv", + "vmand.mm", + "vmandn.mm", + "vmax.vv", + "vmaxu.vv", + "vmerge.vvm", + "vmv.v.v", + "vmfeq.vv", + "vmfle.vv", + "vmflt.vv", + "vmfne.vv", + "vmin.vv", + "vminu.vv", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbf.m", + "vmseq.vv", + "vmsif.m", + "vmsle.vv", + "vmsleu.vv", + "vmslt.vv", + "vmsltu.vv", + "vmsne.vv", + "vmsof.m", + "vmul.vv", + "vmulh.vv", + "vmulhsu.vv", + "vmulhu.vv", + "vmv.x.s", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wv", + "vnclipu.wv", + "vnmsac.vv", + "vnmsub.vv", + "vnsra.wv", + "vnsrl.wv", + "vor.vv", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrem.vv", + "vremu.vv", + "vrgather.vv", + "vrgatherei16.vv", + "vsadd.vv", + "vsaddu.vv", + "vsbc.vvm", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsll.vv", + "vsmul.vv", + "vsra.vv", + "vsrl.vv", + "vssra.vv", + "vssrl.vv", + "vssub.vv", + "vssubu.vv", + "vsub.vv", + "vwadd.vv", + "vwadd.wv", + "vwaddu.vv", + "vwaddu.wv", + "vwmacc.vv", + "vwmaccsu.vv", + "vwmaccu.vv", + "vwmul.vv", + "vwmulsu.vv", + "vwmulu.vv", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.wv", + "vwsubu.vv", + "vwsubu.wv", + "vxor.vv", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + // rv_zvbb + "vandn.vv", + "vrol.vv", + "vror.vv", + "vwsll.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isVtype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "src1 is vtype." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala new file mode 100644 index 00000000..c7e0676c --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isVwmacc { + def apply(t1DecodePattern: T1DecodePattern): isVwmacc = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isVwmacc(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isVwmacc(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "special MAC instruction, MAC use vd as source, it cross read vd. TODO: cross read vd + mac uop. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala new file mode 100644 index 00000000..0d160b88 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isWidenreduce { + def apply(t1DecodePattern: T1DecodePattern): isWidenreduce = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isWidenreduce(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vwredsum.vs", + "vwredsumu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class isWidenreduce(value: TriState) extends BooleanDecodeAttribute { + override val description: String = + "a special widen, only write dual vd from Top to element0 it doesn't cross. TODO: better name. " +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala new file mode 100644 index 00000000..bba534f1 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isWriteCount { + def apply(t1DecodePattern: T1DecodePattern): isWriteCount = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isWriteCount(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val isExtend = Seq( + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + + val isCrossWrite = Seq( + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + // rv_zvbb + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + + val isSlide = Seq( + "vfslide1down.vf", + "vfslide1up.vf", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx" + ) + + val isGather = Seq( + "vrgather.vv", + "vrgatherei16.vv" + ) + + val allMatched = isExtend ++ isCrossWrite ++ isSlide ++ isGather + + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isWriteCount(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala new file mode 100644 index 00000000..7436f37f --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isZero { + def apply(t1DecodePattern: T1DecodePattern): isZero = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isZero(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "vfslide1down.vf", + "vfslide1up.vf", + "viota.m", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isZero(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.OtherUnit]]" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala new file mode 100644 index 00000000..298784b9 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isZvbb { + def apply(t1DecodePattern: T1DecodePattern): isZvbb = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isZvbb(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = + if (t1DecodePattern.param.zvbbEnable) + Seq( + "vandn.vv", + "vandn.vx", + "vbrev.v", + "vbrev8.v", + "vrev8.v", + "vclz.v", + "vctz.v", + "vcpop.v", + "vrol.vv", + "vrol.vx", + "vror.vv", + "vror.vx", + "vror.vi", + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + else Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isZvbb(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneZvbb]]." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala new file mode 100644 index 00000000..f89e54af --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object isZvma { + def apply(t1DecodePattern: T1DecodePattern): isZvma = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isZvma(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = + if (t1DecodePattern.param.useXsfmm) + Seq( + "vlte8", + "vlte16", + "vlte32", + "vste8", + "vste16", + "vste32", + "vtmv.v.t", + "vtmv.t.v", + "mm.u.u", + "mm.u.s", + "mm.s.u", + "mm.s.s", + "mm.e5m2.e4m3", + "mm.e5m2.e5m2", + "mm.e4m3.e4m3", + "mm.e4m3.e5m2", + "vtzero.t", + "p2mm.f.f", + "vtdiscard" + ) + else Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isZvma(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneZvma]]." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala new file mode 100644 index 00000000..2345c8b7 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait LogicUopType extends Uop +object logicUop0 extends LogicUopType +object logicUop1 extends LogicUopType +object logicUop2 extends LogicUopType +object logicUop4 extends LogicUopType +object logicUop5 extends LogicUopType +object logicUop6 extends LogicUopType +object logicUop8 extends LogicUopType +object logicUop9 extends LogicUopType + +object LogicUop { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> logicUop0, + t1 _ -> logicUop1, + t2 _ -> logicUop2, + t4 _ -> logicUop4, + t5 _ -> logicUop5, + t6 _ -> logicUop6, + t8 _ -> logicUop8, + t9 _ -> logicUop9 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vand.vi", + "vand.vv", + "vand.vx", + "vmand.mm", + "vredand.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmor.mm", + "vor.vi", + "vor.vv", + "vor.vx", + "vredor.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmxor.mm", + "vredxor.vs", + "vxor.vi", + "vxor.vv", + "vxor.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmandn.mm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmorn.mm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmxnor.mm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmnand.mm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmnor.mm" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala new file mode 100644 index 00000000..d4b74867 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait MaskPipeUop extends Uop +object MaskUop0 extends MaskPipeUop +object MaskUop1 extends MaskPipeUop +object MaskUop2 extends MaskPipeUop +object MaskUop3 extends MaskPipeUop +object MaskUop4 extends MaskPipeUop +object MaskUop5 extends MaskPipeUop +object MaskUop6 extends MaskPipeUop +object MaskUop7 extends MaskPipeUop +object MaskUop8 extends MaskPipeUop +object MaskUop9 extends MaskPipeUop +object MaskUop10 extends MaskPipeUop +object MaskUop11 extends MaskPipeUop +// 0000 x => extend x?4:2 [0,1] +// 0001 x => gather x?16:sew [2,3] +// 001 xy => slide x?up:down y?s:1 [4,7] +// 010 xx => 0: add 1: logic 2: float 3: order [8,11] +object MaskPipeOpcode { + def apply(t1DecodePattern: T1DecodePattern): MaskPipeOpcode = { + Seq( + t0 _ -> MaskUop0, + t1 _ -> MaskUop1, + t2 _ -> MaskUop2, + t3 _ -> MaskUop3, + t4 _ -> MaskUop4, + t5 _ -> MaskUop5, + t6 _ -> MaskUop6, + t7 _ -> MaskUop7, + t8 _ -> MaskUop8, + t9 _ -> MaskUop9, + t10 _ -> MaskUop10, + t11 _ -> MaskUop11 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => MaskPipeOpcode(tpe) + }.getOrElse(MaskPipeOpcode(MaskUop0)) + } + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val isCrossWrite = Seq( + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + // rv_zvbb + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + val extend = Seq( + "vsext.vf2", + "vzext.vf2" + ) + val allMatched: Seq[String] = extend ++ isCrossWrite + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vsext.vf4", + "vzext.vf4" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrgather.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrgatherei16.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfslide1down.vf", + "vslide1down.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslidedown.vi", + "vslidedown.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfslide1up.vf", + "vslide1up.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslideup.vi", + "vslideup.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcpop.m", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredsum.vs", + "vwredsum.vs", + "vwredsumu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vredand.vs", + "vredor.vs", + "vredxor.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfredmax.vs", + "vfredmin.vs", + "vfredusum.vs", + "vfwredusum.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfredosum.vs", + "vfwredosum.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class MaskPipeOpcode(value: MaskPipeUop) extends UopDecodeAttribute[MaskPipeUop] { + override val description: String = "" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala new file mode 100644 index 00000000..788349ea --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait MulUOPType extends Uop +object mulUop0 extends MulUOPType +object mulUop1 extends MulUOPType +object mulUop3 extends MulUOPType +object mulUop5 extends MulUOPType +object mulUop10 extends MulUOPType +object mulUop14 extends MulUOPType + +object MulUOP { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> mulUop0, + t1 _ -> mulUop1, + t3 _ -> mulUop3, + t5 _ -> mulUop5, + t10 _ -> mulUop10, + t14 _ -> mulUop14 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmul.vv", + "vmul.vx", + "vsmul.vv", + "vsmul.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmadd.vv", + "vmadd.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmacc.vv", + "vmacc.vx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnmsub.vv", + "vnmsub.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t14(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnmsac.vv", + "vnmsac.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class MulUOP(value: MulUOPType) extends UopDecodeAttribute[MulUOPType] { + override val description: String = "" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala new file mode 100644 index 00000000..07d77dbb --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait OtherUopType extends Uop +object otherUop0 extends OtherUopType +object otherUop1 extends OtherUopType +object otherUop2 extends OtherUopType +object otherUop3 extends OtherUopType +object otherUop4 extends OtherUopType +object otherUop5 extends OtherUopType +object otherUop6 extends OtherUopType +object otherUop7 extends OtherUopType +object otherUop8 extends OtherUopType +object otherUop9 extends OtherUopType + +object OtherUop { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> otherUop0, + t1 _ -> otherUop1, + t2 _ -> otherUop2, + t3 _ -> otherUop3, + t4 _ -> otherUop4, + t5 _ -> otherUop5, + t6 _ -> otherUop6, + t7 _ -> otherUop7, + t8 _ -> otherUop8, + t9 _ -> otherUop9 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfirst.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsbf.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsof.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsif.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmerge.vfm", + "vfmv.v.f", + "vmerge.vim", + "vmv.v.i", + "vmerge.vvm", + "vmv.v.v", + "vmerge.vxm", + "vmv.v.x" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmv.s.f", + "vmv.s.x", + "vmv.x.s" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcpop.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vid.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala new file mode 100644 index 00000000..827a17ec --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder + +import chisel3.experimental.hierarchy.Instantiate +import chisel3.properties.{ClassType, Property} + +package object attribute { + + /** Attribute that will be encode the property of an instruction in the uarch and will be additional encode into the + * object module, which will be used to provide metadata for verifications. + */ + trait DecodeAttribute[T] { + val identifier: String = this.getClass.getSimpleName.replace("$", "") + val value: T + val description: String + // Property of this attribute + def om: Property[ClassType] = { + val obj = Instantiate(new T1DecodeAttributeOM(identifier, description, value.toString)) + obj.getPropertyReference + } + } + + sealed trait TriState + case object Y extends TriState + case object N extends TriState + case object DC extends TriState + + trait Uop + object UopDC extends Uop + trait UopDecodeAttribute[T <: Uop] extends DecodeAttribute[T] + + trait BooleanDecodeAttribute extends DecodeAttribute[TriState] + // TODO: we can add more scala type to avoid string type. + trait StringDecodeAttribute extends DecodeAttribute[String] +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala new file mode 100644 index 00000000..057be2d0 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait ShiftUopType extends Uop +object shiftUop0 extends ShiftUopType +object shiftUop1 extends ShiftUopType +object shiftUop2 extends ShiftUopType +object shiftUop4 extends ShiftUopType +object shiftUop6 extends ShiftUopType + +object ShiftUop { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> shiftUop0, + t1 _ -> shiftUop1, + t2 _ -> shiftUop2, + t4 _ -> shiftUop4, + t6 _ -> shiftUop6 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vsll.vi", + "vsll.vv", + "vsll.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vsra.vi", + "vsra.vv", + "vsra.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vssrl.vi", + "vssrl.vv", + "vssrl.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vssra.vi", + "vssra.vv", + "vssra.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class ShiftUop(value: ShiftUopType) extends UopDecodeAttribute[ShiftUopType] { + override val description: String = "" +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala new file mode 100644 index 00000000..6f5bb1aa --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait TopUopType extends Uop +object TopT0 extends TopUopType +object TopT1 extends TopUopType +object TopT2 extends TopUopType +object TopT3 extends TopUopType +object TopT4 extends TopUopType +object TopT5 extends TopUopType +object TopT6 extends TopUopType +object TopT7 extends TopUopType +object TopT8 extends TopUopType +object TopT9 extends TopUopType +object TopT10 extends TopUopType +object TopT11 extends TopUopType +object TopT12 extends TopUopType +object TopT13 extends TopUopType +object TopT14 extends TopUopType +object TopT15 extends TopUopType +object TopT16 extends TopUopType +object TopT17 extends TopUopType +object TopT18 extends TopUopType +object TopT19 extends TopUopType +object TopT20 extends TopUopType +object TopT21 extends TopUopType +object TopT22 extends TopUopType +object TopT23 extends TopUopType +object TopT24 extends TopUopType +object TopT25 extends TopUopType +object TopT26 extends TopUopType +object TopT27 extends TopUopType +object TopT28 extends TopUopType +object TopT29 extends TopUopType +object TopT30 extends TopUopType +object TopT31 extends TopUopType + +object TopUop { + def apply(t1DecodePattern: T1DecodePattern): TopUop = { + Seq( + t0 _ -> TopT0, + t1 _ -> TopT1, + t2 _ -> TopT2, + t3 _ -> TopT3, + t4 _ -> TopT4, + t5 _ -> TopT5, + t6 _ -> TopT6, + t7 _ -> TopT7, + t8 _ -> TopT8, + t9 _ -> TopT9, + t10 _ -> TopT10, + t11 _ -> TopT11, + t12 _ -> TopT12, + t13 _ -> TopT13, + t14 _ -> TopT14, + t15 _ -> TopT15, + t16 _ -> TopT16, + t17 _ -> TopT17, + t18 _ -> TopT18, + t19 _ -> TopT19, + t20 _ -> TopT20, + t21 _ -> TopT21, + t22 _ -> TopT22, + t23 _ -> TopT23, + t24 _ -> TopT24, + t25 _ -> TopT25, + t26 _ -> TopT26, + t27 _ -> TopT27, + t28 _ -> TopT28, + t29 _ -> TopT29, + t30 _ -> TopT30, + t31 _ -> TopT31 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => TopUop(tpe) + }.getOrElse(TopUop(TopT0)) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslidedown.vi", + "vslidedown.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslideup.vi", + "vslideup.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslide1down.vx", + "vfslide1down.vf" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslide1up.vx", + "vfslide1up.vf" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrgather.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrgatherei16.vv" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("viota.m") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vcompress.vm") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmv.s.f", + "vmv.s.x" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmv.f.s", + "vmv.x.s" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t12(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def t13(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def t14(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsbf.m", + "vmsif.m", + "vmsof.m" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t15(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vfirst.m") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t16(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcpop.m", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredsum.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t17(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vwredsum.vs", + "vwredsumu.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t18(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vredand.vs", + "vredor.vs", + "vredxor.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t19(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfredmax.vs", + "vfredmin.vs" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t20(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vfredusum.vs") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t21(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vfredosum.vs") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t22(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vfwredusum.vs") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t23(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vfwredosum.vs") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t24(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t25(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq() + allMatched.contains(t1DecodePattern.instruction.name) + } + def t26(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vzext.vf2") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t27(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vsext.vf2") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t28(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vzext.vf4") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t29(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vsext.vf4") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t30(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vzext.vf8") + allMatched.contains(t1DecodePattern.instruction.name) + } + def t31(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq("vsext.vf8") + allMatched.contains(t1DecodePattern.instruction.name) + } +} + +case class TopUop(value: TopUopType) extends UopDecodeAttribute[TopUopType] { + override val description: String = "uop for mask unit." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala new file mode 100644 index 00000000..e4f665e7 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +object DecoderUop { + def apply(t1DecodePattern: T1DecodePattern): DecoderUop = { + val tpe: Option[DecoderUop] = Seq( + isDivider.y(t1DecodePattern) -> DivUOP(t1DecodePattern), + isFloat.y(t1DecodePattern) -> FloatUop(t1DecodePattern), + isMultiplier.y(t1DecodePattern) -> MulUOP(t1DecodePattern), + isAdder.y(t1DecodePattern) -> AdderUOP(t1DecodePattern), + isLogic.y(t1DecodePattern) -> LogicUop(t1DecodePattern), + isShift.y(t1DecodePattern) -> ShiftUop(t1DecodePattern), + isOther.y(t1DecodePattern) -> OtherUop(t1DecodePattern), + isZero.y(t1DecodePattern) -> ZeroUOP(t1DecodePattern), + isZvbb.y(t1DecodePattern) -> ZvbbUOP(t1DecodePattern) + ).collectFirst { + case (fn, tpe) if fn => DecoderUop(tpe) + } + require(tpe.size <= 1) + tpe.getOrElse(DecoderUop(UopDC)) + } +} + +case class DecoderUop(value: Uop) extends UopDecodeAttribute[Uop] { + override val description: String = "uop for mask unit." +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala new file mode 100644 index 00000000..2a127c23 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait ZeroUOPType extends Uop +object zeroUop0 extends ZeroUOPType + +object ZeroUOP { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> zeroUop0 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcompress.vm", + "vfslide1down.vf", + "vfslide1up.vf", + "viota.m", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala new file mode 100644 index 00000000..5c20adec --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package framework.gpdomain.sequencer.decoder.attribute + +import framework.gpdomain.sequencer.decoder.T1DecodePattern + +trait ZvbbUOPType extends Uop +object zvbbUop0 extends ZvbbUOPType // brev +object zvbbUop1 extends ZvbbUOPType // brev8 +object zvbbUop2 extends ZvbbUOPType // rev8 +object zvbbUop3 extends ZvbbUOPType // clz +object zvbbUop4 extends ZvbbUOPType // ctz +object zvbbUop5 extends ZvbbUOPType // rol +object zvbbUop6 extends ZvbbUOPType // ror +object zvbbUop7 extends ZvbbUOPType // wsll +object zvbbUop8 extends ZvbbUOPType // andn +object zvbbUop9 extends ZvbbUOPType // pop + +object ZvbbUOP { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> zvbbUop0, + t1 _ -> zvbbUop1, + t2 _ -> zvbbUop2, + t3 _ -> zvbbUop3, + t4 _ -> zvbbUop4, + t5 _ -> zvbbUop5, + t6 _ -> zvbbUop6, + t7 _ -> zvbbUop7, + t8 _ -> zvbbUop8, + t9 _ -> zvbbUop9 + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vbrev.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vbrev8.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrev8.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vclz.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vctz.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrol.vv", + "vrol.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vror.vv", + "vror.vx", + "vror.vi" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vwsll.vv", + "vwsll.vx", + "vwsll.vi" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vandn.vv", + "vandn.vx" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcpop.v" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +} diff --git a/compiler b/compiler index 4ca70f74..aa00cfc3 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit 4ca70f74fef248bd8418fa1eb6231733175bad73 +Subproject commit aa00cfc3548a662a616a084341eb1aeb45f15eeb From 0a01adf05752175fc554104036325ddc688565d5 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 16 Dec 2025 17:29:58 +0800 Subject: [PATCH 010/238] [bb-test/ctest/rvv] del: remove staurn's rvv tests and add two base tests --- bb-tests/workloads/src/CTest/rvv/.gitignore | 1 - .../workloads/src/CTest/rvv/CMakeLists.txt | 255 +- bb-tests/workloads/src/CTest/rvv/Makefile | 133 - .../workloads/src/CTest/rvv/common/ara/exp.h | 99 - .../src/CTest/rvv/common/ara/fdotproduct.c | 346 -- .../src/CTest/rvv/common/ara/fdotproduct.h | 35 - .../workloads/src/CTest/rvv/common/ara/gemv.c | 248 - .../workloads/src/CTest/rvv/common/ara/gemv.h | 37 - .../rvv/common/ara/rivec/vector_defines.h | 138 - .../workloads/src/CTest/rvv/common/ara/spmv.c | 116 - .../workloads/src/CTest/rvv/common/ara/spmv.h | 30 - .../workloads/src/CTest/rvv/common/ara/util.c | 42 - .../workloads/src/CTest/rvv/common/ara/util.h | 58 - bb-tests/workloads/src/CTest/rvv/common/crt.S | 225 - .../workloads/src/CTest/rvv/common/syscalls.c | 472 -- .../workloads/src/CTest/rvv/common/test.ld | 65 - .../workloads/src/CTest/rvv/common/util.h | 115 - bb-tests/workloads/src/CTest/rvv/env/LICENSE | 24 - .../workloads/src/CTest/rvv/env/encoding.h | 5024 ----------------- .../workloads/src/CTest/rvv/env/p/link.ld | 16 - .../src/CTest/rvv/env/p/riscv_test.h | 297 - .../workloads/src/CTest/rvv/env/pm/link.ld | 1 - .../src/CTest/rvv/env/pm/riscv_test.h | 11 - .../workloads/src/CTest/rvv/env/pt/link.ld | 1 - .../src/CTest/rvv/env/pt/riscv_test.h | 69 - .../workloads/src/CTest/rvv/env/v/entry.S | 164 - .../workloads/src/CTest/rvv/env/v/link.ld | 1 - .../src/CTest/rvv/env/v/riscv_test.h | 101 - .../workloads/src/CTest/rvv/env/v/string.c | 108 - bb-tests/workloads/src/CTest/rvv/env/v/vm.c | 310 - .../workloads/src/CTest/rvv/utasks/utasks.h | 490 -- bb-tests/workloads/src/CTest/rvv/vadd_test.c | 40 + bb-tests/workloads/src/CTest/rvv/vdot_test.c | 39 + .../vec-conditional/conditional_gendata.pl | 142 - .../src/CTest/rvv/vec-conditional/dataset1.h | 250 - .../rvv/vec-conditional/vec-conditional.S | 23 - .../vec-conditional/vec-conditional_main.c | 60 - .../rvv/vec-conjugate-gradient/gen_data.py | 208 - .../CTest/rvv/vec-conjugate-gradient/main.c | 154 - .../src/CTest/rvv/vec-conv-3/dataset1.h | 1993 ------- .../src/CTest/rvv/vec-conv-3/gendata.py | 60 - .../src/CTest/rvv/vec-conv-3/vec-conv.S | 212 - .../src/CTest/rvv/vec-conv-3/vec-conv_main.c | 39 - .../workloads/src/CTest/rvv/vec-cos/cos.c | 56 - .../workloads/src/CTest/rvv/vec-cos/cos.h | 284 - .../src/CTest/rvv/vec-cos/gen_data.py | 71 - .../workloads/src/CTest/rvv/vec-cos/main.c | 190 - .../src/CTest/rvv/vec-div-approx/dataset1.h | 322 -- .../rvv/vec-div-approx/div_approx_gendata.pl | 135 - .../CTest/rvv/vec-div-approx/vec-div_approx.S | 26 - .../rvv/vec-div-approx/vec-div_approx_main.c | 48 - .../src/CTest/rvv/vec-dotprod/dotproduct.c | 299 - .../src/CTest/rvv/vec-dotprod/dotproduct.h | 37 - .../src/CTest/rvv/vec-dotprod/gen_data.py | 96 - .../src/CTest/rvv/vec-dotprod/main.c | 108 - .../src/CTest/rvv/vec-dropout/dropout.c | 61 - .../src/CTest/rvv/vec-dropout/dropout.h | 31 - .../src/CTest/rvv/vec-dropout/gen_data.py | 66 - .../src/CTest/rvv/vec-dropout/main.c | 66 - .../workloads/src/CTest/rvv/vec-exp/exp.c | 58 - .../src/CTest/rvv/vec-exp/gen_data.py | 71 - .../workloads/src/CTest/rvv/vec-exp/main.c | 174 - .../src/CTest/rvv/vec-fconv2d/fconv2d.h | 43 - .../src/CTest/rvv/vec-fconv2d/fconv2d_3x3.c | 334 -- .../src/CTest/rvv/vec-fconv2d/fconv2d_7x7.c | 636 --- .../src/CTest/rvv/vec-fconv2d/gen_data.py | 123 - .../src/CTest/rvv/vec-fconv2d/main.c | 103 - .../src/CTest/rvv/vec-fconv3d/fconv3d.h | 37 - .../src/CTest/rvv/vec-fconv3d/fconv3d_3x7x7.c | 894 --- .../src/CTest/rvv/vec-fconv3d/gen_data.py | 131 - .../src/CTest/rvv/vec-fconv3d/main.c | 101 - .../src/CTest/rvv/vec-fdotprod/gen_data.py | 85 - .../src/CTest/rvv/vec-fdotprod/main.c | 91 - .../src/CTest/rvv/vec-fft/dataset1.h | 4450 --------------- .../workloads/src/CTest/rvv/vec-fft/fft2.h | 11 - .../src/CTest/rvv/vec-fft/fft2_gendata.py | 71 - .../src/CTest/rvv/vec-fft/fft2_main.c | 54 - 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b/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt index 134263f6..bdbe515f 100644 --- a/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt @@ -1,229 +1,100 @@ set(ELF_CC "riscv64-unknown-elf-gcc") -set(ELF_CXX "riscv64-unknown-elf-g++") +set(LINUX_CC "riscv64-unknown-linux-gnu-g++") #------------------------------------------------------------------------------- -# Set baremetal compilation flags for RVV +# Set baremetal compilation flags with RVV support #------------------------------------------------------------------------------- -set(RVV_C_FLAGS -g -DPREALLOCATE=1 -DNR_LANES=64 -mcmodel=medany -static -O2 -ffast-math - -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns - -march=rv64gcv_zfh_zvfh -mabi=lp64d -std=gnu99 - -I${CTEST_RVV_WORKLOAD_DIR}/env - -I${CTEST_RVV_WORKLOAD_DIR}/common) - -set(RVV_CXX_FLAGS -g -DPREALLOCATE=1 -mcmodel=medany -static -O2 -ffast-math - -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns - -march=rv64gcv_zfh_zvfh -mabi=lp64d -std=c++17 - -specs=htif_nano.specs - -I${CTEST_RVV_WORKLOAD_DIR}/env - -I${CTEST_RVV_WORKLOAD_DIR}/common - -I${CTEST_RVV_WORKLOAD_DIR}/utasks) - -# Link options for baremetal -set(RVV_LINK_OPTS -static -nostdlib -nostartfiles -lm -lgcc - -T ${CTEST_RVV_WORKLOAD_DIR}/common/test.ld) - -# Common sources -file(GLOB RVV_COMMON_C_SRCS - ${CTEST_RVV_WORKLOAD_DIR}/common/*.c - ${CTEST_RVV_WORKLOAD_DIR}/common/ara/*.c) -file(GLOB RVV_COMMON_ASM_SRCS - ${CTEST_RVV_WORKLOAD_DIR}/common/*.S) -set(RVV_COMMON_SRCS ${RVV_COMMON_C_SRCS} ${RVV_COMMON_ASM_SRCS}) +set(C_FLAGS -g -fno-common -O1 -static -march=rv64gcv -mabi=lp64d -mcmodel=medany + -fno-builtin-printf -specs=htif_nano.specs) #------------------------------------------------------------------------------- -# Define compilation functions for RVV benchmarks +# Define common compilation step functions #------------------------------------------------------------------------------- -# Generate baremetal executable for C benchmarks -function(add_rvv_baremetal_test_target TEST_NAME) - set(EXECUTABLE "${TEST_NAME}-baremetal") - set(TEST_DIR "${CTEST_RVV_WORKLOAD_DIR}/${TEST_NAME}") - - # Find all C sources in the test directory - file(GLOB TEST_C_SRCS ${TEST_DIR}/*.c) - - # Check if there's a data generation script (only for tests that generate .S files) - # Exclude tests that generate C header files instead - set(GEN_SCRIPT "") - if(NOT TEST_NAME MATCHES "vec-conv-3|vec-sep-conv-3|vec-slide-conv|vec-sgemm|vec-sgemv|vec-transpose-load|vec-transpose-store") - file(GLOB GEN_SCRIPT ${TEST_DIR}/gen_data.py ${TEST_DIR}/*_gendata.py ${TEST_DIR}/gendata.py) - endif() - - # Find existing assembly sources (non-data files like vec-*.S) - file(GLOB TEST_ASM_SRCS ${TEST_DIR}/*.S) - list(FILTER TEST_ASM_SRCS EXCLUDE REGEX "data\\.S$") - - set(TEST_SRCS ${TEST_C_SRCS} ${TEST_ASM_SRCS}) - set(DATA_ASM_FILE "") - - # If there's a generation script, add command to generate data.S - if(GEN_SCRIPT) - set(DATA_ASM_FILE ${CMAKE_CURRENT_BINARY_DIR}/${TEST_NAME}_data.S) - - # Determine default arguments for each test - set(GEN_ARGS "") - if(TEST_NAME MATCHES "vec-cos|vec-exp|vec-log") - set(GEN_ARGS "64") # N_f64 - elseif(TEST_NAME MATCHES "vec-jacobi2d") - set(GEN_ARGS "16 16") # R C - elseif(TEST_NAME MATCHES "vec-pathfinder") - set(GEN_ARGS "10 20 30") # num_runs cols rows - elseif(TEST_NAME MATCHES "vec-conjugate-gradient|vec-spmv") - set(GEN_ARGS "16 16 0.5") # S N D - elseif(TEST_NAME MATCHES "vec-igemm") - set(GEN_ARGS "8 8 8") # M N P - elseif(TEST_NAME MATCHES "vec-softmax") - set(GEN_ARGS "8 8") # channels innerSize - elseif(TEST_NAME MATCHES "vec-dropout") - set(GEN_ARGS "1024") # N - elseif(TEST_NAME MATCHES "vec-fconv2d|vec-iconv2d") - set(GEN_ARGS "64 3") # matrix_width filter_size - elseif(TEST_NAME MATCHES "vec-fconv3d") - set(GEN_ARGS "16 3") # matrix_width filter_size - elseif(TEST_NAME MATCHES "vec-fdotprod|vec-dotprod") - set(GEN_ARGS "1024") # N - elseif(TEST_NAME MATCHES "vec-roi-align") - set(GEN_ARGS "2 3 16 16 4 8 8") # batch_size depth height width n_boxes crop_h crop_w - endif() - - # Convert space-separated args to list - string(REPLACE " " ";" GEN_ARGS_LIST "${GEN_ARGS}") - - add_custom_command( - OUTPUT ${DATA_ASM_FILE} - COMMAND ${CMAKE_COMMAND} -E env python3 ${GEN_SCRIPT} ${GEN_ARGS_LIST} > ${DATA_ASM_FILE} - DEPENDS ${GEN_SCRIPT} - COMMENT "Generating data for ${TEST_NAME} with args: ${GEN_ARGS}" - WORKING_DIRECTORY ${TEST_DIR} - ) - list(APPEND TEST_SRCS ${DATA_ASM_FILE}) - else() - # If no generation script, use existing data.S if present - file(GLOB DATA_S ${TEST_DIR}/data.S) - if(DATA_S) - list(APPEND TEST_SRCS ${DATA_S}) - endif() - endif() +#------------------------------------------------------------------------------- +# Generate executables for different platforms +#------------------------------------------------------------------------------- +set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") +set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-g++") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gcv") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gcv") + +# Generate Linux version executables +function(add_linux_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}-linux") + + add_executable(${EXECUTABLE} ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE}) + target_compile_options(${EXECUTABLE} PRIVATE -march=rv64gcv -mabi=lp64d) +endfunction() + +# Generate multicore baremetal version executables +function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}_multicore-baremetal") add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${RVV_C_FLAGS} - -I${TEST_DIR} - -o ${EXECUTABLE} - ${TEST_SRCS} - ${RVV_COMMON_SRCS} - ${RVV_LINK_OPTS} - DEPENDS ${TEST_SRCS} ${RVV_COMMON_SRCS} - COMMENT "Building RVV baremetal executable: ${EXECUTABLE}" + COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} ${CTEST_RVV_WORKLOAD_DIR}/start.S + -DMULTICORE=3 + ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} + DEPENDS ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_RVV_WORKLOAD_DIR}/start.S + COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) - add_custom_target(${TEST_NAME}_baremetal + add_custom_target(${TEST_NAME}_multicore_baremetal DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} ) endfunction() -# Generate baremetal executable for C++ benchmarks -# Note: C++ programs don't link common sources, they rely on htif_nano.specs -function(add_rvv_cpp_baremetal_test_target TEST_NAME) - set(EXECUTABLE "${TEST_NAME}-baremetal") - set(TEST_DIR "${CTEST_RVV_WORKLOAD_DIR}/${TEST_NAME}") - - # Find all C++ and assembly sources in the test directory - file(GLOB TEST_CPP_SRCS ${TEST_DIR}/*.cc) - file(GLOB TEST_ASM_SRCS ${TEST_DIR}/*.S) - set(TEST_SRCS ${TEST_CPP_SRCS} ${TEST_ASM_SRCS}) +# Generate singlecore baremetal version executables +function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}_singlecore-baremetal") add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CXX} ${RVV_CXX_FLAGS} - -I${TEST_DIR} - -o ${EXECUTABLE} - ${TEST_SRCS} - ${RVV_LINK_OPTS} - DEPENDS ${TEST_SRCS} ${CTEST_RVV_WORKLOAD_DIR}/utasks/utasks.h - COMMENT "Building RVV C++ baremetal executable: ${EXECUTABLE}" + COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} + ${CTEST_RVV_WORKLOAD_DIR}/start.S + ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} + DEPENDS ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_RVV_WORKLOAD_DIR}/start.S + COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) - add_custom_target(${TEST_NAME}_baremetal + add_custom_target(${TEST_NAME}_singlecore_baremetal DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} ) endfunction() +# Create cross-platform test targets +function(add_cross_platform_test_target TEST_NAME SOURCE_FILE) + add_linux_test_target(${TEST_NAME} ${SOURCE_FILE}) + add_multicore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) + add_singlecore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) + + # Create a master target that builds all platforms simultaneously + add_custom_target(${TEST_NAME} + DEPENDS ${TEST_NAME}-linux ${TEST_NAME}_multicore_baremetal ${TEST_NAME}_singlecore_baremetal + COMMENT "Building ${TEST_NAME} for all platforms" + ) +endfunction() + #------------------------------------------------------------------------------- -# Build list - C benchmarks (baremetal only) +# build linux version workload #------------------------------------------------------------------------------- -add_rvv_baremetal_test_target(vec-conditional) -add_rvv_baremetal_test_target(vec-conjugate-gradient) -add_rvv_baremetal_test_target(vec-conv-3) -add_rvv_baremetal_test_target(vec-cos) -add_rvv_baremetal_test_target(vec-div-approx) -add_rvv_baremetal_test_target(vec-dotprod) -add_rvv_baremetal_test_target(vec-dropout) -add_rvv_baremetal_test_target(vec-exp) -add_rvv_baremetal_test_target(vec-fconv2d) -add_rvv_baremetal_test_target(vec-fconv3d) -add_rvv_baremetal_test_target(vec-fdotprod) -add_rvv_baremetal_test_target(vec-iconv2d) -add_rvv_baremetal_test_target(vec-igemm) -add_rvv_baremetal_test_target(vec-jacobi2d) -add_rvv_baremetal_test_target(vec-log) -add_rvv_baremetal_test_target(vec-mixed_width_mask) -add_rvv_baremetal_test_target(vec-pathfinder) -add_rvv_baremetal_test_target(vec-roi-align) -add_rvv_baremetal_test_target(vec-sep-conv-3) -add_rvv_baremetal_test_target(vec-sgemm) -add_rvv_baremetal_test_target(vec-sgemm-v2) -add_rvv_baremetal_test_target(vec-sgemm-v3) -add_rvv_baremetal_test_target(vec-sgemv) -add_rvv_baremetal_test_target(vec-slide-conv) -add_rvv_baremetal_test_target(vec-softmax) -add_rvv_baremetal_test_target(vec-strlen) -add_rvv_baremetal_test_target(vec-spmv) -add_rvv_baremetal_test_target(vec-square-root-approx) -add_rvv_baremetal_test_target(vec-transpose-load) -add_rvv_baremetal_test_target(vec-transpose-store) +set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${LINK_FLAGS}") #------------------------------------------------------------------------------- -# Build list - C++ benchmarks +# Build list - use cross-platform function to generate all test targets #------------------------------------------------------------------------------- -# add_rvv_cpp_baremetal_test_target(vec-tasks) -# add_rvv_cpp_baremetal_test_target(vec-daxpy) +add_cross_platform_test_target(ctest_rvv_vadd vadd_test.c) +add_cross_platform_test_target(ctest_rvv_vdot vdot_test.c) -#------------------------------------------------------------------------------- # Create master build target -#------------------------------------------------------------------------------- add_custom_target(buckyball-rvv-build ALL DEPENDS - vec-conditional_baremetal - vec-conjugate-gradient_baremetal - vec-conv-3_baremetal - vec-cos_baremetal - vec-div-approx_baremetal - vec-dotprod_baremetal - vec-dropout_baremetal - vec-exp_baremetal - vec-fconv2d_baremetal - vec-fconv3d_baremetal - vec-fdotprod_baremetal - vec-iconv2d_baremetal - vec-igemm_baremetal - vec-jacobi2d_baremetal - vec-log_baremetal - vec-mixed_width_mask_baremetal - vec-pathfinder_baremetal - vec-roi-align_baremetal - vec-sep-conv-3_baremetal - vec-sgemm_baremetal - vec-sgemm-v2_baremetal - vec-sgemm-v3_baremetal - vec-sgemv_baremetal - vec-slide-conv_baremetal - vec-softmax_baremetal - vec-strlen_baremetal - vec-spmv_baremetal - vec-square-root-approx_baremetal - vec-transpose-load_baremetal - vec-transpose-store_baremetal - COMMENT "Building all RVV baremetal workloads for Buckyball" + ctest_rvv_vadd + ctest_rvv_vdot + COMMENT "Building all RVV workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/rvv/Makefile b/bb-tests/workloads/src/CTest/rvv/Makefile deleted file mode 100644 index 17417bdb..00000000 --- a/bb-tests/workloads/src/CTest/rvv/Makefile +++ /dev/null @@ -1,133 +0,0 @@ -#======================================================================= -# UCB VLSI FLOW: Makefile for riscv-bmarks -#----------------------------------------------------------------------- -# Yunsup Lee (yunsup@cs.berkeley.edu) -# - -XLEN ?= 64 - -default: all - -src_dir = . - -instname = riscv-bmarks -instbasedir = $(UCB_VLSI_HOME)/install - -#-------------------------------------------------------------------- -# Sources -#-------------------------------------------------------------------- - -bmarks = \ - vec-conditional \ - vec-conjugate-gradient \ - vec-conv-3 \ - vec-cos \ - vec-div-approx \ - vec-dotprod \ - vec-dropout \ - vec-exp \ - vec-fconv2d \ - vec-fconv3d \ - vec-fdotprod \ - vec-fft \ - vec-iconv2d \ - vec-igemm \ - vec-jacobi2d \ - vec-log \ - vec-mixed_width_mask \ - vec-pathfinder \ - vec-roi-align \ - vec-sep-conv-3 \ - vec-sgemm \ - vec-sgemm-v2 \ - vec-sgemm-v3 \ - vec-sgemv \ - vec-slide-conv \ - vec-softmax \ - vec-strlen \ - vec-spmv \ - vec-square-root-approx \ - vec-transpose-load \ - vec-transpose-store \ - -cpp_bmarks = \ - vec-tasks \ - vec-daxpy - -#-------------------------------------------------------------------- -# Build rules -#-------------------------------------------------------------------- - -RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- -RISCV_GCC ?= $(RISCV_PREFIX)gcc -RISCV_GXX ?= $(RISCV_PREFIX)g++ -RISCV_COMMON_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -O2 -g -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv$(XLEN)gcv_zfh_zvfh -mabi=lp64d -RISCV_GCC_OPTS ?= $(RISCV_COMMON_OPTS) -std=gnu99 -RISCV_GXX_OPTS ?= $(RISCV_COMMON_OPTS) -std=c++17 -specs=htif_nano.specs -RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs) -RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld -RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump -C -D -S --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data -RISCV_SIM ?= spike --isa=rv$(XLEN)gcv_zfh_zvfh -p4 -m0x70020000:0x20000,0x80000000:0x10000000 - -incs += -I$(src_dir)/env -I$(src_dir)/common $(addprefix -I$(src_dir)/, $(bmarks)) -objs := - -COMMON_SRCS = $(wildcard $(src_dir)/common/*.c) $(wildcard $(src_dir)/common/*.S) $(wildcard $(src_dir)/common/ara/*.c) - -define compile_template -$(1).riscv: $(wildcard $(src_dir)/$(1)/*) $(wildcard $(src_dir)/common/*) - $$(RISCV_GCC) $$(incs) $$(RISCV_GCC_OPTS) -o $$@ $(wildcard $(src_dir)/$(1)/*.c) $(wildcard $(src_dir)/$(1)/*.S) $(COMMON_SRCS) $$(RISCV_LINK_OPTS) -endef - -define compile_cpp_template -$(1).riscv: $(wildcard $(src_dir)/$(1)/*) $(src_dir)/utasks/utasks.h - $$(RISCV_GXX) $$(incs) $$(RISCV_GXX_OPTS) -I$(src_dir)/utasks -o $$@ $(wildcard $(src_dir)/$(1)/*.cc) $(wildcard $(src_dir)/$(1)/*.S) -endef - - -$(foreach bmark,$(bmarks),$(eval $(call compile_template,$(bmark)))) -$(foreach bmark,$(cpp_bmarks),$(eval $(call compile_cpp_template,$(bmark)))) - -#------------------------------------------------------------ -# Build and run benchmarks on riscv simulator - -bmarks_riscv_bin = $(addsuffix .riscv, $(bmarks) $(cpp_bmarks)) -bmarks_riscv_dump = $(addsuffix .riscv.dump, $(bmarks) $(cpp_bmarks)) -bmarks_riscv_out = $(addsuffix .riscv.out, $(bmarks) $(cpp_bmarks)) - -$(bmarks_riscv_dump): %.riscv.dump: %.riscv - $(RISCV_OBJDUMP) $< > $@ - -$(bmarks_riscv_out): %.riscv.out: %.riscv - $(RISCV_SIM) $< > $@ - -riscv: $(bmarks_riscv_dump) -run: $(bmarks_riscv_out) - -junk += $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(bmarks_riscv_hex) $(bmarks_riscv_out) - -#------------------------------------------------------------ -# Default - -all: riscv - -#------------------------------------------------------------ -# Install - -date_suffix = $(shell date +%Y-%m-%d_%H-%M) -install_dir = $(instbasedir)/$(instname)-$(date_suffix) -latest_install = $(shell ls -1 -d $(instbasedir)/$(instname)* | tail -n 1) - -install: - mkdir $(install_dir) - cp -r $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(install_dir) - -install-link: - rm -rf $(instbasedir)/$(instname) - ln -s $(latest_install) $(instbasedir)/$(instname) - -#------------------------------------------------------------ -# Clean up - -clean: - rm -rf $(objs) $(junk) diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/exp.h b/bb-tests/workloads/src/CTest/rvv/common/ara/exp.h deleted file mode 100644 index 1bdec349..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/exp.h +++ /dev/null @@ -1,99 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include -#include - -#include "riscv_vector.h" - -#define EXP_IMPL(t, w, l, b, c1, c2) \ - void exp_f##w##m##l##_bmark(t *exponents, t *results, size_t len); \ - inline vfloat##w##m##l##_t __exp_f##w##m##l(vfloat##w##m##l##_t x, \ - size_t gvl) { \ - t exp_hi = 88.3762626##w##7949; \ - t exp_lo = -88.3762626##w##7949; \ - \ - t cephes_LOG2EF = 1.44269504088896341; \ - t cephes_exp_C1 = 0.693359375; \ - t cephes_exp_C2 = -2.12194440e-4; \ - \ - t cephes_exp_p0 = 1.9875691500E-4; \ - t cephes_exp_p1 = 1.3981999507E-3; \ - t cephes_exp_p2 = 8.3334519073E-3; \ - t cephes_exp_p3 = 4.1665795894E-2; \ - t cephes_exp_p4 = 1.6666665459E-1; \ - t cephes_exp_p5 = 5.0000001201E-1; \ - vfloat##w##m##l##_t tmp; \ - vfloat##w##m##l##_t tmp2; \ - vfloat##w##m##l##_t tmp4; \ - vfloat##w##m##l##_t fx; \ - \ - vfloat##w##m##l##_t one = __riscv_vfmv_v_f_f##w##m##l(1.0, gvl); \ - vfloat##w##m##l##_t zero = __riscv_vfmv_v_f_f##w##m##l(0.0, gvl); \ - vfloat##w##m##l##_t z; \ - vfloat##w##m##l##_t y; \ - \ - vbool##b##_t mask; \ - vint##w##m##l##_t imm0; \ - vint##w##m##l##_t tmp3; \ - \ - x = __riscv_vfmin_vf_f##w##m##l(x, exp_hi, gvl); \ - x = __riscv_vfmax_vf_f##w##m##l(x, exp_lo, gvl); \ - \ - fx = __riscv_vfmv_v_f_f##w##m##l(0.5, gvl); \ - fx = __riscv_vfmacc_vf_f##w##m##l(fx, cephes_LOG2EF, x, gvl); \ - \ - tmp3 = __riscv_vfcvt_x_f_v_i##w##m##l(fx, gvl); \ - tmp = __riscv_vfcvt_f_x_v_f##w##m##l(tmp3, gvl); \ - \ - mask = __riscv_vmflt_vv_f##w##m##l##_b##b(fx, tmp, gvl); \ - tmp2 = __riscv_vmerge_vvm_f##w##m##l(zero, one, mask, gvl); \ - fx = __riscv_vfsub_vv_f##w##m##l(tmp, tmp2, gvl); \ - tmp = __riscv_vfmul_vf_f##w##m##l(fx, cephes_exp_C1, gvl); \ - z = __riscv_vfmul_vf_f##w##m##l(fx, cephes_exp_C2, gvl); \ - x = __riscv_vfsub_vv_f##w##m##l(x, tmp, gvl); \ - x = __riscv_vfsub_vv_f##w##m##l(x, z, gvl); \ - \ - z = __riscv_vfmul_vv_f##w##m##l(x, x, gvl); \ - \ - y = __riscv_vfmv_v_f_f##w##m##l(cephes_exp_p0, gvl); \ - y = __riscv_vfmadd_vf_f##w##m##l(y, cephes_exp_p1, x, gvl); \ - y = __riscv_vfmadd_vf_f##w##m##l(y, cephes_exp_p2, x, gvl); \ - y = __riscv_vfmadd_vf_f##w##m##l(y, cephes_exp_p3, x, gvl); \ - y = __riscv_vfmadd_vf_f##w##m##l(y, cephes_exp_p4, x, gvl); \ - y = __riscv_vfmadd_vf_f##w##m##l(y, cephes_exp_p5, x, gvl); \ - y = __riscv_vfmadd_vv_f##w##m##l(y, z, x, gvl); \ - y = __riscv_vfadd_vv_f##w##m##l(y, one, gvl); \ - \ - imm0 = __riscv_vfcvt_x_f_v_i##w##m##l(fx, gvl); \ - imm0 = __riscv_vadd_vv_i##w##m##l( \ - imm0, __riscv_vmv_v_x_i##w##m##l(c1, gvl), gvl); \ - imm0 = __riscv_vsll_vv_i##w##m##l( \ - imm0, __riscv_vmv_v_x_u##w##m##l(c2, gvl), gvl); \ - \ - tmp4 = __riscv_vreinterpret_v_i##w##m##l##_f##w##m##l(imm0); \ - y = __riscv_vfmul_vv_f##w##m##l(y, tmp4, gvl); \ - return y; \ - } - -EXP_IMPL(double, 64, 1, 64, 1023, 52); -EXP_IMPL(double, 64, 2, 32, 1023, 52); -EXP_IMPL(double, 64, 4, 16, 1023, 52); -EXP_IMPL(float, 32, 1, 32, 0x7f, 23); -EXP_IMPL(float, 32, 2, 16, 0x7f, 23); -EXP_IMPL(float, 32, 4, 8, 0x7f, 23); diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/fdotproduct.c b/bb-tests/workloads/src/CTest/rvv/common/ara/fdotproduct.c deleted file mode 100644 index 305ad6d9..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/fdotproduct.c +++ /dev/null @@ -1,346 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "fdotproduct.h" -#define INTRINSICS -// 64-bit dot-product: a * b -double fdotp_v64b(const double *a, const double *b, size_t avl) { -#ifdef INTRINSICS - - size_t orig_avl = avl; - size_t vl = __riscv_vsetvlmax_e64m8(); - - vfloat64m8_t acc, buf_a, buf_b; - vfloat64m1_t red; - - double *a_ = (double *)a; - double *b_ = (double *)b; - - // Clean the accumulator - acc = __riscv_vfmv_s_f_f64m8(0, vl); - red = __riscv_vfmv_s_f_f64m1(0, vl); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - vl = __riscv_vsetvl_e64m8(avl); - // Load chunk a and b - buf_a = __riscv_vle64_v_f64m8(a_, vl); - buf_b = __riscv_vle64_v_f64m8(b_, vl); - // Multiply and accumulate - acc = __riscv_vfmacc_vv_f64m8(acc, buf_a, buf_b, vl); - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - vl = __riscv_vsetvlmax_e64m8(); - red = __riscv_vfredusum_vs_f64m8_f64m1(acc, red, vl); - return __riscv_vfmv_f_s_f64m1_f64(red); - -#else - - size_t orig_avl = avl; - size_t vl; - asm volatile("vsetvli %0, %1, e64, m8, ta, ma" : "=r"(vl) : "r"(avl)); - - double red; - - double *a_ = (double *)a; - double *b_ = (double *)b; - - // Clean the accumulator - asm volatile("vmv.s.x v0, zero"); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - asm volatile("vsetvli %0, %1, e64, m8, ta, ma" : "=r"(vl) : "r"(avl)); - // Load chunk a and b - asm volatile("vle64.v v8, (%0)" ::"r"(a_)); - asm volatile("vle64.v v16, (%0)" ::"r"(b_)); - // Multiply and accumulate - if (avl == orig_avl) { - asm volatile("vfmul.vv v24, v8, v16"); - } else { - asm volatile("vfmacc.vv v24, v8, v16"); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; - -#endif -} - -// 32-bit dot-product: a * b -float fdotp_v32b(const float *a, const float *b, size_t avl) { -#ifdef INTRINSICS - - size_t orig_avl = avl; - size_t vl = __riscv_vsetvl_e32m8(avl); - - vfloat32m8_t acc, buf_a, buf_b; - vfloat32m1_t red; - - float *a_ = (float *)a; - float *b_ = (float *)b; - - // Clean the accumulator - acc = __riscv_vfmv_s_f_f32m8(0, vl); - red = __riscv_vfmv_s_f_f32m1(0, vl); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - vl = __riscv_vsetvl_e32m8(avl); - // Load chunk a and b - buf_a = __riscv_vle32_v_f32m8(a_, vl); - buf_b = __riscv_vle32_v_f32m8(b_, vl); - // Multiply and accumulate - acc = __riscv_vfmacc_vv_f32m8(acc, buf_a, buf_b, vl); - - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - vl = __riscv_vsetvlmax_e64m8(); - red = __riscv_vfredusum_vs_f32m8_f32m1(acc, red, vl); - return __riscv_vfmv_f_s_f32m1_f32(red); - -#else - - size_t orig_avl = avl; - size_t vl; - asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); - - float red; - - float *a_ = (float *)a; - float *b_ = (float *)b; - - // Clean the accumulator - asm volatile("vmv.s.x v0, zero"); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); - // Load chunk a and b - asm volatile("vle32.v v8, (%0)" ::"r"(a_)); - asm volatile("vle32.v v16, (%0)" ::"r"(b_)); - // Multiply and accumulate - if (avl == orig_avl) { - asm volatile("vfmul.vv v24, v8, v16"); - } else { - asm volatile("vfmacc.vv v24, v8, v16"); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; - -#endif -} - -// 16-bit dot-product: a * b -_Float16 fdotp_v16b(const _Float16 *a, const _Float16 *b, size_t avl) { - /* #ifdef INTRINSICS */ - - /* size_t orig_avl = avl; */ - /* size_t vl = __riscv_vsetvl_e16m8(avl); */ - - /* vfloat16m8_t acc, buf_a, buf_b; */ - /* vfloat16m1_t red; */ - - /* _Float16 *a_ = (_Float16 *)a; */ - /* _Float16 *b_ = (_Float16 *)b; */ - - /* // Clean the accumulator */ - /* red = __riscv_vfmv_s_f_f16m1(0, vl); */ - /* // Stripmine and accumulate a partial reduced vector */ - /* for (; avl > 0; avl -= vl) { */ - /* vl = __riscv_vsetvl_e16m8(avl); */ - /* // Load chunk a and b */ - /* buf_a = __riscv_vle16_v_f16m8(a_, vl); */ - /* buf_b = __riscv_vle16_v_f16m8(b_, vl); */ - /* // Multiply and accumulate */ - /* if (avl == orig_avl) { */ - /* acc = __riscv_vfmul_vv_f16m8(buf_a, buf_b, vl); */ - /* } else { */ - /* acc = __riscv_vfmacc_vv_f16m8(acc, buf_a, buf_b, vl); */ - /* } */ - /* // Bump pointers */ - /* a_ += vl; */ - /* b_ += vl; */ - /* } */ - - /* // Reduce and store */ - /* red = __riscv_vfredusum_vs_f16m8_f16m1(red, acc, red, vl); */ - /* return __riscv_vfmv_f_s_f16m1_f16(red); */ - - /* #else */ - - size_t orig_avl = avl; - size_t vl; - asm volatile("vsetvli %0, %1, e16, m8, ta, ma" : "=r"(vl) : "r"(avl)); - - _Float16 red; - - _Float16 *a_ = (_Float16 *)a; - _Float16 *b_ = (_Float16 *)b; - - // Clean the accumulator - asm volatile("vmv.s.x v0, zero"); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - asm volatile("vsetvli %0, %1, e16, m8, ta, ma" : "=r"(vl) : "r"(avl)); - // Load chunk a and b - asm volatile("vle16.v v8, (%0)" ::"r"(a_)); - asm volatile("vle16.v v16, (%0)" ::"r"(b_)); - // Multiply and accumulate - if (avl == orig_avl) { - asm volatile("vfmul.vv v24, v8, v16"); - } else { - asm volatile("vfmacc.vv v24, v8, v16"); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; - - /* #endif */ -} - -double fdotp_s64b(const double *a, const double *b, size_t avl) { - double acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} - -float fdotp_s32b(const float *a, const float *b, size_t avl) { - float acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} - -_Float16 fdotp_s16b(const _Float16 *a, const _Float16 *b, size_t avl) { - _Float16 acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/fdotproduct.h b/bb-tests/workloads/src/CTest/rvv/common/ara/fdotproduct.h deleted file mode 100644 index 4f5c3279..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/fdotproduct.h +++ /dev/null @@ -1,35 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef _FDOTPRODUCT_H_ -#define _FDOTPRODUCT_H_ - -#include -#include - -#include "riscv_vector.h" - -double fdotp_v64b(const double *a, const double *b, size_t avl); -float fdotp_v32b(const float *a, const float *b, size_t avl); -_Float16 fdotp_v16b(const _Float16 *a, const _Float16 *b, size_t avl); - -double fdotp_s64b(const double *a, const double *b, size_t avl); -float fdotp_s32b(const float *a, const float *b, size_t avl); -_Float16 fdotp_s16b(const _Float16 *a, const _Float16 *b, size_t avl); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/gemv.c b/bb-tests/workloads/src/CTest/rvv/common/ara/gemv.c deleted file mode 100644 index a1e13ad7..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/gemv.c +++ /dev/null @@ -1,248 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Chi Zhang, ETH Zurich - -#include "gemv.h" -#include "util.h" -#include -#include -#include -#include - -#include - -void init_gemv_data(const unsigned long int m_row, - const unsigned long int v_len, double *matrix, - double *vector, double a, double b, double c) { - // initialize matrix - for (uint64_t i = 0; i < m_row; ++i) { - for (uint64_t j = 0; j < v_len; ++j) { - matrix[i * v_len + j] = a * (double)i + b * (double)j + c; - } - } - - // initialize vector - for (uint64_t i = 0; i < v_len; ++i) { - vector[i] = a * (double)i + b; - } -} - -//=====================================// -//========= GEMV ROW WISE KERNEL ======// -//=====================================// - -#define SLICE_SIZE 128 - -void clear_reduction_register() { - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(SLICE_SIZE)); - asm volatile("vmv.v.i v16, 0"); - asm volatile("vmv.v.i v24, 0"); -} - -void store_slice_results(double *dest, const unsigned long int slice_height) { - double tmp; - // round slide - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_height)); - asm volatile("vfmv.f.s %0, v24" : "=f"(tmp)); - asm volatile("vfslide1down.vf v16, v24, %0" ::"f"(tmp)); - // store - asm volatile("vse64.v v16, (%0);" ::"r"(dest)); -} - -void gemv_rowwise_small_than_slice(const unsigned long int m_row, - const unsigned long int v_len, - double *matrix, double *vector, - double *dest) { - // setup - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(1)); - asm volatile("vmv.v.i v24, 0"); - asm volatile("vmv.v.i v16, 0"); - // load vector - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(v_len)); - asm volatile("vle64.v v0, (%0);" ::"r"(vector)); - for (uint64_t i = 0; i < m_row; ++i) { - double *_mat_ = matrix + i * v_len; - double *_dst_ = dest + i - 1; // delayed store - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(v_len)); - - if (i % 2 == 0) { - // load matrix slice row - asm volatile("vle64.v v4, (%0);" ::"r"(_mat_)); - // multiply with vector - asm volatile("vfmul.vv v8, v4, v0"); - // reduction - asm volatile("vfredsum.vs v16, v8, v16"); - // store previous data - if (i != 0) { - // asm volatile("vse64.v v24, (%0);" ::"r"(_dst_)); - double tmp; - asm volatile("vfmv.f.s %0, v24" : "=f"(tmp)); - *_dst_ = tmp; - // clear reduction register - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(1)); - asm volatile("vmv.v.i v24, 0"); - } - - } else { - // load matrix slice row - asm volatile("vle64.v v2, (%0);" ::"r"(_mat_)); - // multiply with vector - asm volatile("vfmul.vv v6, v2, v0"); - // reduction - asm volatile("vfredsum.vs v24, v6, v24"); - // store previous data - // asm volatile("vse64.v v16, (%0);" ::"r"(_dst_)); - double tmp; - asm volatile("vfmv.f.s %0, v16" : "=f"(tmp)); - *_dst_ = tmp; - // clear reduction register - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(1)); - asm volatile("vmv.v.i v16, 0"); - } - } - - // store the last value - double *_dst_ = dest + m_row - 1; - if (m_row % 2 == 0) // even - { - double tmp; - asm volatile("vfmv.f.s %0, v24" : "=f"(tmp)); - *_dst_ = tmp; - } else { // odd - double tmp; - asm volatile("vfmv.f.s %0, v16" : "=f"(tmp)); - *_dst_ = tmp; - } -} - -void gemv_rowwise_kernel_slice(const unsigned long int v_len, - const unsigned long int slice_width, - const unsigned long int slice_height, - double *matrix, double *vector) { - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_width)); - // load vector - asm volatile("vle64.v v0, (%0);" ::"r"(vector)); - - // for each row in slice - for (uint64_t i = 0; i < slice_height; ++i) { - double *_mat_ = matrix + i * v_len; - double tmp; // for round slice later - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_width)); - // load matrix slice row - asm volatile("vle64.v v4, (%0);" ::"r"(_mat_)); - // multiply with vector - asm volatile("vfmul.vv v8, v4, v0"); - if (i % 2 == 0) { - // round slide - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_height)); - asm volatile("vfmv.f.s %0, v24" : "=f"(tmp)); - asm volatile("vfslide1down.vf v16, v24, %0" ::"f"(tmp)); - // reduction - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_width)); - asm volatile("vfredsum.vs v16, v8, v16"); - } else { - // round slide - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_height)); - asm volatile("vfmv.f.s %0, v16" : "=f"(tmp)); - asm volatile("vfslide1down.vf v24, v16, %0" ::"f"(tmp)); - // reduction - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_width)); - asm volatile("vfredsum.vs v24, v8, v24"); - } - } - - if (slice_height % 2) { - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(slice_height)); - asm volatile("vmv.v.v v24, v16"); - } -} - -void gemv_rowwise(const unsigned long int m_row, const unsigned long int v_len, - double *matrix, double *vector, double *dest) { - // when matrix is samller than a slice - if (v_len <= SLICE_SIZE) { - gemv_rowwise_small_than_slice(m_row, v_len, matrix, vector, dest); - return; - } - - uint64_t num_slice_row = m_row / SLICE_SIZE; - uint64_t rest_row = m_row % SLICE_SIZE; - uint64_t num_slice_col = v_len / SLICE_SIZE; - uint64_t rest_col = v_len % SLICE_SIZE; - - // each slice row - for (uint64_t i = 0; i < num_slice_row; ++i) { - // clear reduction sum register file - clear_reduction_register(); - // each full slice - for (uint64_t j = 0; j < num_slice_col; ++j) { - double *_mat_ = matrix + i * SLICE_SIZE * v_len + j * SLICE_SIZE; - double *_vec_ = vector + j * SLICE_SIZE; - gemv_rowwise_kernel_slice(v_len, SLICE_SIZE, SLICE_SIZE, _mat_, _vec_); - } - // margin slice - if (rest_col > 0) { - double *_mat_ = - matrix + i * SLICE_SIZE * v_len + num_slice_col * SLICE_SIZE; - double *_vec_ = vector + num_slice_col * SLICE_SIZE; - gemv_rowwise_kernel_slice(v_len, rest_col, SLICE_SIZE, _mat_, _vec_); - } - // store dest vector value - double *_dst_ = dest + i * SLICE_SIZE; - store_slice_results(_dst_, SLICE_SIZE); - } - - // margin slice row - if (rest_row > 0) { - // clear reduction sum register file - clear_reduction_register(); - // each bottom slice - for (uint64_t j = 0; j < num_slice_col; ++j) { - double *_mat_ = - matrix + num_slice_row * SLICE_SIZE * v_len + j * SLICE_SIZE; - double *_vec_ = vector + j * SLICE_SIZE; - gemv_rowwise_kernel_slice(v_len, SLICE_SIZE, rest_row, _mat_, _vec_); - } - // margin slice - if (rest_col > 0) { - double *_mat_ = matrix + num_slice_row * SLICE_SIZE * v_len + - num_slice_col * SLICE_SIZE; - double *_vec_ = vector + num_slice_col * SLICE_SIZE; - gemv_rowwise_kernel_slice(v_len, rest_col, rest_row, _mat_, _vec_); - } - // store dest vector value - double *_dst_ = dest + num_slice_row * SLICE_SIZE; - store_slice_results(_dst_, rest_row); - } -} - -int gemv_verify(const unsigned long int m_row, const unsigned long int v_len, - double *matrix, double *vector, double *dest) { - for (uint64_t i = 0; i < m_row; ++i) { - double res = dest[i]; - double golden = 0; - for (uint64_t j = 0; j < v_len; ++j) { - golden = golden + matrix[i * v_len + j] * vector[j]; - } - if (golden != res) { - printf("Sorry, wrong value! at index %d, result = %f, golden = %f \n", i, - res, golden); - return i; - } - } - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/gemv.h b/bb-tests/workloads/src/CTest/rvv/common/ara/gemv.h deleted file mode 100644 index f38997c1..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/gemv.h +++ /dev/null @@ -1,37 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Chi Zhang, ETH Zurich - -#ifndef _GEMV_H -#define _GEMV_H - -void init_gemv_data(const unsigned long int m_row, - const unsigned long int v_len, double *matrix, - double *vector, double a, double b, double c); - -void gemv_rowwise(const unsigned long int m_row, const unsigned long int v_len, - double *matrix, double *vector, double *dest); - -void gemv_rowwise_small_than_slice(const unsigned long int m_row, - const unsigned long int v_len, - double *matrix, double *vector, - double *dest); - -int gemv_verify(const unsigned long int m_row, const unsigned long int v_len, - double *matrix, double *vector, double *dest); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/rivec/vector_defines.h b/bb-tests/workloads/src/CTest/rvv/common/ara/rivec/vector_defines.h deleted file mode 100644 index e525b51d..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/rivec/vector_defines.h +++ /dev/null @@ -1,138 +0,0 @@ -// Modified version of: -// vector_defines.h -// https://github.com/RALC88/riscv-vectorized-benchmark-suite/blob/rvv-1.0/common/vector_defines.h -// Find details on the original version below -// Author: Matteo Perotti - -// RISC-V VECTOR intrinsics mapping by Cristóbal Ramírez Lazo, "Barcelona 2019" - -#include "riscv_vector.h" - -/* - Data-Type Intrinsics -*/ - -#define _MMR_f64 vfloat64m1_t -#define _MMR_f32 vfloat32m1_t - -#define _MMR_i64 vint64m1_t -#define _MMR_i32 vint32m1_t - -#define _MMR_u64 vuint64m1_t -#define _MMR_u32 vuint32m1_t - -#define _MMR_MASK_i64 vbool64_t -#define _MMR_MASK_i32 vbool32_t - -/* - Reinterpret Intrinsics -*/ - -#define _MM_CAST_i32_u32(op1) __riscv_vreinterpret_v_u32m1_i32m1(op1) -#define _MM_CAST_u32_i32(op1) __riscv_vreinterpret_v_i32m1_u32m1(op1) -#define _MM_CAST_i64_u64(op1) __riscv_vreinterpret_v_u64m1_i64m1(op1) -#define _MM_CAST_u64_i64(op1) __riscv_vreinterpret_v_i64m1_u64m1(op1) - -#define _MM_CAST_i32_f32(op1) __riscv_vreinterpret_v_f32m1_i32m1(op1) -#define _MM_CAST_u32_f32(op1) __riscv_vreinterpret_v_f32m1_u32m1(op1) -#define _MM_CAST_f32_i32(op1) __riscv_vreinterpret_v_i32m1_f32m1(op1) -#define _MM_CAST_f32_u32(op1) __riscv_vreinterpret_v_u32m1_f32m1(op1) - -#define _MM_CAST_i64_f64(op1) __riscv_vreinterpret_v_f64m1_i64m1(op1) -#define _MM_CAST_u64_f64(op1) __riscv_vreinterpret_v_f64m1_u64m1(op1) -#define _MM_CAST_f64_i64(op1) __riscv_vreinterpret_v_i64m1_f64m1(op1) -#define _MM_CAST_f64_u64(op1) __riscv_vreinterpret_v_u64m1_f64m1(op1) - -/* - Integer Intrinsics -*/ - -#define _MM_SET_i64(op1, vl) __riscv_vmv_v_x_i64m1(op1, vl) -#define _MM_SET_i32(op1, vl) __riscv_vmv_v_x_i32m1(op1, vl) - -#define _MM_MERGE_i64(op1, op2, op3, vl) \ - __riscv_vmerge_vvm_i64m1(op1, op2, op3, vl) -#define _MM_MERGE_i32(op1, op2, op3, vl) \ - __riscv_vmerge_vvm_i32m1(op1, op2, op3, vl) - -#define _MM_AND_i64(op1, op2, vl) __riscv_vand_vv_i64m1(op1, op2, vl) -#define _MM_AND_i32(op1, op2, vl) __riscv_vand_vv_i32m1(op1, op2, vl) - -#define _MM_OR_i64(op1, op2, vl) __riscv_vor_vv_i64m1(op1, op2, vl) -#define _MM_OR_i32(op1, op2, vl) __riscv_vor_vv_i32m1(op1, op2, vl) - -#define _MM_XOR_i64(op1, op2, vl) __riscv_vxor_vv_i64m1(op1, op2, vl) -#define _MM_XOR_i32(op1, op2, vl) __riscv_vxor_vv_i32m1(op1, op2, vl) - -#define _MM_SLL_i64(op1, op2, vl) __riscv_vsll_vv_i64m1(op1, op2, vl) -#define _MM_SLL_i32(op1, op2, vl) __riscv_vsll_vv_i32m1(op1, op2, vl) - -#define _MM_SRL_i64(op1, op2, vl) __riscv_vsrl_vv_u64m1(op1, op2, vl) -#define _MM_SRL_i32(op1, op2, vl) __riscv_vsrl_vv_u32m1(op1, op2, vl) - -#define _MM_ADD_i64(op1, op2, vl) __riscv_vadd_vv_i64m1(op1, op2, vl) -#define _MM_ADD_i32(op1, op2, vl) __riscv_vadd_vv_i32m1(op1, op2, vl) - -#define _MM_SUB_i64(op1, op2, vl) __riscv_vsub_vv_i64m1(op1, op2, vl) -#define _MM_SUB_i32(op1, op2, vl) __riscv_vsub_vv_i32m1(op1, op2, vl) - -#define _MM_MUL_i64(op1, op2, vl) __riscv_vmul_vv_i64m1(op1, op2, vl) -#define _MM_MUL_i32(op1, op2, vl) __riscv_vmul_vv_i32m1(op1, op2, vl) - -#define _MM_VMSEQ_i64(op1, op2, vl) __riscv_vmseq_vv_i64m1_b64(op1, op2, vl) -#define _MM_VMSEQ_i32(op1, op2, vl) __riscv_vmseq_vv_i32m1_b32(op1, op2, vl) - -/* - Floating-Point Intrinsics -*/ - -#define _MM_SET_f64(op1, vl) __riscv_vfmv_v_f_f64m1(op1, vl) -#define _MM_SET_f32(op1, vl) __riscv_vfmv_v_f_f32m1(op1, vl) - -#define _MM_MERGE_f64(op1, op2, op3, vl) \ - __riscv_vmerge_vvm_f64m1(op1, op2, op3, vl) -#define _MM_MERGE_f32(op1, op2, op3, vl) \ - __riscv_vmerge_vvm_f32m1(op1, op2, op3, vl) - -#define _MM_MAX_f64(op1, op2, vl) __riscv_vfmax_vv_f64m1(op1, op2, vl) -#define _MM_MAX_f32(op1, op2, vl) __riscv_vfmax_vv_f32m1(op1, op2, vl) - -#define _MM_ADD_f64(op1, op2, vl) __riscv_vfadd_vv_f64m1(op1, op2, vl) -#define _MM_ADD_f32(op1, op2, vl) __riscv_vfadd_vv_f32m1(op1, op2, vl) - -#define _MM_SUB_f64(op1, op2, vl) __riscv_vfsub_vv_f64m1(op1, op2, vl) -#define _MM_SUB_f32(op1, op2, vl) __riscv_vfsub_vv_f32m1(op1, op2, vl) - -#define _MM_MUL_f64(op1, op2, vl) __riscv_vfmul_vv_f64m1(op1, op2, vl) -#define _MM_MUL_f32(op1, op2, vl) __riscv_vfmul_vv_f32m1(op1, op2, vl) - -#define _MM_MACC_f64(op1, op2, op3, vl) \ - __riscv_vfmacc_vv_f64m1(op1, op2, op3, vl) -#define _MM_MACC_f32(op1, op2, op3, vl) \ - __riscv_vfmacc_vv_f32m1(op1, op2, op3, vl) - -#define _MM_MADD_f64(op1, op2, op3, vl) \ - __riscv_vfmadd_vv_f64m1(op1, op2, op3, vl) -#define _MM_MADD_f32(op1, op2, op3, vl) \ - __riscv_vfmadd_vv_f32m1(op1, op2, op3, vl) - -#define _MM_VFCVT_F_X_f64(op1, vl) __riscv_vfcvt_f_x_v_f64m1(op1, vl) -#define _MM_VFCVT_F_X_f32(op1, vl) __riscv_vfcvt_f_x_v_f32m1(op1, vl) -#define _MM_VFCVT_X_F_i64(op1, vl) __riscv_vfcvt_x_f_v_i64m1(op1, vl) -#define _MM_VFCVT_X_F_i32(op1, vl) __riscv_vfcvt_x_f_v_i32m1(op1, vl) -#define _MM_VFWCVT_F_F_f64(op1, vl) __riscv_vfwcvt_f_f_v_f64m2(op1, vl) -#define _MM_VFNCVT_F_F_f32(op1, vl) __riscv_vfncvt_f_f_w_f32m1(op1, vl) -#define _MM_VFWCVT_F_X_f64(op1, vl) __riscv_vfwcvt_f_x_v_f64m2(op1, vl) -#define _MM_VFCVT_f32_i32(op1, vl) __riscv_vfcvt_f_x_v_f32m1(op1, vl) - -#define _MM_VFLE_f64(op1, op2, vl) __riscv_vmfle_vv_f64m1_b64(op1, op2, vl) -#define _MM_VFLE_f32(op1, op2, vl) __riscv_vmfle_vv_f32m1_b32(op1, op2, vl) - -#define _MM_VFLT_f64(op1, op2, vl) __riscv_vmflt_vv_f64m1_b64(op1, op2, vl) -#define _MM_VFLT_f32(op1, op2, vl) __riscv_vmflt_vv_f32m1_b32(op1, op2, vl) - -/* - Ancillary Defines -*/ - -#define FENCE() asm volatile("fence"); diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/spmv.c b/bb-tests/workloads/src/CTest/rvv/common/ara/spmv.c deleted file mode 100644 index af2e8187..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/spmv.c +++ /dev/null @@ -1,116 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Chi Zhang, ETH Zurich - -#include "spmv.h" -#include "util.h" -#include -#include -#include -#include -#include -#include -#include - -void spmv_csr_idx32(int32_t N_ROW, int32_t *CSR_PROW, int32_t *CSR_INDEX, - double *CSR_DATA, double *IN_VEC, double *OUT_VEC) { - /* printf("Do spmv\n"); */ - for (int i = 0; i < N_ROW; ++i) { - int32_t len = CSR_PROW[i + 1] - CSR_PROW[i]; - double *data = CSR_DATA + CSR_PROW[i]; - int32_t *index = CSR_INDEX + CSR_PROW[i]; - - // clear register file - - volatile size_t maxvl = __riscv_vsetvl_e64m8(len); - asm volatile("vmv.v.i v24, 0"); - - double dbg = 0; - while (len) { - volatile size_t slice_size = __riscv_vsetvl_e64m8(len); - asm volatile("vle64.v v8, (%0)" ::"r"(data)); // fetch entries - asm volatile("vle32.v v16, (%0)" ::"r"(index)); // fetch indices - asm volatile("vloxei32.v v0, (%0), v16" ::"r"(IN_VEC)); // load data - asm volatile("vfmacc.vv v24, v8, v0"); // vector multiply - /* if (i == 0) { */ - /* printf("slice=%ld\n", slice_size); */ - /* for (size_t j = 0; j < slice_size; j++) { */ - /* double t, u, v; */ - /* asm volatile("vrgather.vx v16, v12, %0" :: "r"(j)); */ - /* asm volatile("vfmv.f.s %0, v16" : "=f"(t)); */ - - /* asm volatile("vrgather.vx v16, v4, %0" :: "r"(j)); */ - /* asm volatile("vfmv.f.s %0, v16" : "=f"(u)); */ - - /* asm volatile("vrgather.vx v16, v0, %0" :: "r"(j)); */ - /* asm volatile("vfmv.f.s %0, v16" : "=f"(v)); */ - /* dbg += data[j] * IN_VEC[index[j]/sizeof(double)]; */ - /* printf("i=%ld j=%ld id=%ld data=%lx vec=%lx out=%lx - * vdata=\"%lx\" vvec=\"%lx\" vout=\"%lx\"\n", */ - /* i, j, index[j] / sizeof(double), */ - /* *(uint64_t*)(&data[j]), - * *(uint64_t*)(&IN_VEC[index[j]/sizeof(double)]), */ - /* *(uint64_t*)(&dbg), */ - /* *(uint64_t*)(&u), *(uint64_t*)(&v), *(uint64_t*)(&t) */ - /* ); */ - - /* } */ - /* } */ - - len = len - slice_size; - data = data + slice_size; - index = index + slice_size; - } - - double tmp; - asm volatile("vsetvli x0, %0, e64, m8, ta, ma" ::"r"(maxvl)); - asm volatile("vmv.v.i v8, 0"); - asm volatile("vfredusum.vs v24, v24, v8"); // reduction - asm volatile("vfmv.f.s %0, v24" : "=f"(tmp)); - OUT_VEC[i] = tmp; - } - /* printf("Verifying\n"); */ - // spmv_verify(N_ROW, CSR_PROW, CSR_INDEX, CSR_DATA, IN_VEC, OUT_VEC); -} - -int spmv_verify(int32_t N_ROW, int32_t *CSR_PROW, int32_t *CSR_INDEX, - double *CSR_DATA, double *IN_VEC, double *OUT_VEC) { - for (int32_t i = 0; i < N_ROW; ++i) { - double res = OUT_VEC[i]; - - int32_t len = CSR_PROW[i + 1] - CSR_PROW[i]; - double *data = CSR_DATA + CSR_PROW[i]; - int32_t *index = CSR_INDEX + CSR_PROW[i]; - - double golden = 0; - for (int32_t j = 0; j < len; ++j) { - int32_t idx = index[j] / sizeof(double); - double next = golden + data[j] * IN_VEC[idx]; - /* printf("index:%d, data: %lx, vec: %lx %lx\n", idx, - * *(uint64_t*)(&data[j]), *(uint64_t*)(&IN_VEC[idx]), */ - /* *(uint64_t*)(&next)); */ - golden = next; - } - if ((float)golden != (float)res) { - printf("Sorry, wrong value! at index %d, result = %lx, golden = %lx \n", - i, *(uint64_t *)(&res), *(uint64_t *)(&golden)); - exit(1); - return i; - } - } - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/spmv.h b/bb-tests/workloads/src/CTest/rvv/common/ara/spmv.h deleted file mode 100644 index 3a449966..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/spmv.h +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Chi Zhang, ETH Zurich - -#ifndef _SPMV_H -#define _SPMV_H - -#include - -void spmv_csr_idx32(int32_t N_ROW, int32_t *CSR_PROW, int32_t *CSR_INDEX, - double *CSR_DATA, double *IN_VEC, double *OUT_VEC); - -int spmv_verify(int32_t N_ROW, int32_t *CSR_PROW, int32_t *CSR_INDEX, - double *CSR_DATA, double *IN_VEC, double *OUT_VEC); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/util.c b/bb-tests/workloads/src/CTest/rvv/common/ara/util.c deleted file mode 100644 index ffaadb3a..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/util.c +++ /dev/null @@ -1,42 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti -// -// Utility functions for Ara software environment - -#include "util.h" - -int *__dummy__errno__ptr__; - -// Floating-point similarity check with threshold -int similarity_check(double a, double b, double threshold) { - double diff = a - b; - if (FABS(diff) > threshold) - return 0; - else - return 1; -} -int similarity_check_32b(float a, float b, float threshold) { - float diff = a - b; - if (FABS(diff) > threshold) - return 0; - else - return 1; -} - -// Dummy declaration for libm exp -int *__errno(void) { return __dummy__errno__ptr__; } diff --git a/bb-tests/workloads/src/CTest/rvv/common/ara/util.h b/bb-tests/workloads/src/CTest/rvv/common/ara/util.h deleted file mode 100644 index 7118a9b6..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/ara/util.h +++ /dev/null @@ -1,58 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti -// -// Utility functions for Ara software environment (header file) - -#ifndef __UTIL_H__ -#define __UTIL_H__ - -#ifdef GATE_SIM -#define NO_PRINTF -#endif - -#ifdef VCD_DUMP -#pragma message("VCD_DUMP successfully initialized") -#define NO_PRINTF -#define NO_TIMER -#endif - -// Don't measure performance -#ifdef NO_TIMER -#define start_timer() -#define stop_timer() -#define get_timer() 0 -#endif - -// Don't print anything -#ifdef NO_PRINTF -#define printf_(...) -#endif - -#define FABS(x) ((x < 0) ? -x : x) - -#define FABS(x) ((x < 0) ? -x : x) -#define MIN(a, b) ((a) <= (b) ? (a) : (b)) - -// Floating-point similarity check with threshold -int similarity_check(double a, double b, double threshold); -int similarity_check_32b(float a, float b, float threshold); - -// Dummy declaration for libm exp -int *__errno(void); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/common/crt.S b/bb-tests/workloads/src/CTest/rvv/common/crt.S deleted file mode 100644 index 3f5bb2c1..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/crt.S +++ /dev/null @@ -1,225 +0,0 @@ -# See LICENSE for license details. - -#include "encoding.h" - -#if __riscv_xlen == 64 -# define LREG ld -# define SREG sd -# define REGBYTES 8 -#else -# define LREG lw -# define SREG sw -# define REGBYTES 4 -#endif - - .section ".text.init" - .globl _start -_start: - li x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10,0 - li x11,0 - li x12,0 - li x13,0 - li x14,0 - li x15,0 - li x16,0 - li x17,0 - li x18,0 - li x19,0 - li x20,0 - li x21,0 - li x22,0 - li x23,0 - li x24,0 - li x25,0 - li x26,0 - li x27,0 - li x28,0 - li x29,0 - li x30,0 - li x31,0 - - # enable FPU, vector, and accelerator if present - li t0, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS - csrs mstatus, t0 - - # make sure XLEN agrees with compilation choice - li t0, 1 - slli t0, t0, 31 -#if __riscv_xlen == 64 - bgez t0, 1f -#else - bltz t0, 1f -#endif -2: - li a0, 1 - sw a0, tohost, t0 - j 2b -1: - -#ifdef __riscv_flen - # initialize FPU if we have one - la t0, 1f - csrw mtvec, t0 - - fssr x0 - fmv.s.x f0, x0 - fmv.s.x f1, x0 - fmv.s.x f2, x0 - fmv.s.x f3, x0 - fmv.s.x f4, x0 - fmv.s.x f5, x0 - fmv.s.x f6, x0 - fmv.s.x f7, x0 - fmv.s.x f8, x0 - fmv.s.x f9, x0 - fmv.s.x f10,x0 - fmv.s.x f11,x0 - fmv.s.x f12,x0 - fmv.s.x f13,x0 - fmv.s.x f14,x0 - fmv.s.x f15,x0 - fmv.s.x f16,x0 - fmv.s.x f17,x0 - fmv.s.x f18,x0 - fmv.s.x f19,x0 - fmv.s.x f20,x0 - fmv.s.x f21,x0 - fmv.s.x f22,x0 - fmv.s.x f23,x0 - fmv.s.x f24,x0 - fmv.s.x f25,x0 - fmv.s.x f26,x0 - fmv.s.x f27,x0 - fmv.s.x f28,x0 - fmv.s.x f29,x0 - fmv.s.x f30,x0 - fmv.s.x f31,x0 -1: -#endif - - # initialize trap vector - la t0, trap_entry - csrw mtvec, t0 - - # initialize global pointer -.option push -.option norelax - la gp, __global_pointer$ -.option pop - - la tp, _end + 63 - and tp, tp, -64 - - # get core id - csrr a0, mhartid - # for now, assume only 1 core - li a1, 1 -1:bgeu a0, a1, 1b - - # give each core 128KB of stack + TLS -#define STKSHIFT 17 - add sp, a0, 1 - sll sp, sp, STKSHIFT - add sp, sp, tp - sll a2, a0, STKSHIFT - add tp, tp, a2 - - j _init - - .align 2 -trap_entry: - addi sp, sp, -272 - - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - csrw mepc, a0 - - # Remain in M-mode after eret - li t0, MSTATUS_MPP - csrs mstatus, t0 - - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - - addi sp, sp, 272 - mret - -.section ".tohost","aw",@progbits -.align 6 -.globl tohost -tohost: .dword 0 -.align 6 -.globl fromhost -fromhost: .dword 0 diff --git a/bb-tests/workloads/src/CTest/rvv/common/syscalls.c b/bb-tests/workloads/src/CTest/rvv/common/syscalls.c deleted file mode 100644 index 24689182..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/syscalls.c +++ /dev/null @@ -1,472 +0,0 @@ -// See LICENSE for license details. - -#include "util.h" -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define SYS_write 64 - -#undef strcmp - -extern volatile uint64_t tohost; -extern volatile uint64_t fromhost; - -static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, - uint64_t arg2) { - volatile uint64_t magic_mem[8] __attribute__((aligned(64))); - magic_mem[0] = which; - magic_mem[1] = arg0; - magic_mem[2] = arg1; - magic_mem[3] = arg2; - __sync_synchronize(); - - tohost = (uintptr_t)magic_mem; - while (fromhost == 0) - ; - fromhost = 0; - - __sync_synchronize(); - return magic_mem[0]; -} - -#define NUM_COUNTERS 2 -static uintptr_t counters[NUM_COUNTERS]; -static const char *counter_names[NUM_COUNTERS]; - -void setStats(int enable) { - int i = 0; -#define READ_CTR(name) \ - do { \ - while (i >= NUM_COUNTERS) \ - ; \ - uintptr_t csr = read_csr(name); \ - if (!enable) { \ - csr -= counters[i]; \ - counter_names[i] = (const char *)#name; \ - } \ - counters[i++] = csr; \ - } while (0) - - READ_CTR(mcycle); - READ_CTR(minstret); - -#undef READ_CTR -} - -void __attribute__((noreturn)) tohost_exit(uintptr_t code) { - tohost = (code << 1) | 1; - while (1) - ; -} - -uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, - uintptr_t regs[32]) { - tohost_exit(1337); -} - -void exit(int code) { tohost_exit(code); } - -void abort() { exit(128 + SIGABRT); } - -void printstr(const char *s) { syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); } - -void __attribute__((weak)) thread_entry(int cid, int nc) { - // multi-threaded programs override this function. - // for the case of single-threaded programs, only let core 0 proceed. - while (cid != 0) - ; -} - -int __attribute__((weak)) main(int argc, char **argv) { - // single-threaded programs override this function. - printstr("Implement main(), foo!\n"); - return -1; -} - -static void init_tls() { - register void *thread_pointer asm("tp"); - extern char _tdata_begin, _tdata_end, _tbss_end; - size_t tdata_size = &_tdata_end - &_tdata_begin; - memcpy(thread_pointer, &_tdata_begin, tdata_size); - size_t tbss_size = &_tbss_end - &_tdata_end; - memset((char *)thread_pointer + tdata_size, 0, tbss_size); -} - -void _init(int cid, int nc) { - init_tls(); - thread_entry(cid, nc); - - // only single-threaded programs should ever get here. - int ret = main(0, 0); - - char buf[NUM_COUNTERS * 32] __attribute__((aligned(64))); - char *pbuf = buf; - for (int i = 0; i < NUM_COUNTERS; i++) - if (counters[i]) - pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]); - if (pbuf != buf) - printstr(buf); - - exit(ret); -} - -#undef putchar -int putchar(int ch) { - static __thread char buf[64] __attribute__((aligned(64))); - static __thread int buflen = 0; - - buf[buflen++] = ch; - - if (ch == '\n' || buflen == sizeof(buf)) { - syscall(SYS_write, 1, (uintptr_t)buf, buflen); - buflen = 0; - } - - return 0; -} - -void printhex(uint64_t x) { - char str[17]; - int i; - for (i = 0; i < 16; i++) { - str[15 - i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a' - 10); - x >>= 4; - } - str[16] = 0; - - printstr(str); -} - -static inline void printnum(void (*putch)(int, void **), void **putdat, - unsigned long long num, unsigned base, int width, - int padc) { - unsigned digs[sizeof(num) * CHAR_BIT]; - int pos = 0; - - while (1) { - digs[pos++] = num % base; - if (num < base) - break; - num /= base; - } - - while (width-- > pos) - putch(padc, putdat); - - while (pos-- > 0) - putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); -} - -static unsigned long long getuint(va_list *ap, int lflag) { - if (lflag >= 2) - return va_arg(*ap, unsigned long long); - else if (lflag) - return va_arg(*ap, unsigned long); - else - return va_arg(*ap, unsigned int); -} - -static long long getint(va_list *ap, int lflag) { - if (lflag >= 2) - return va_arg(*ap, long long); - else if (lflag) - return va_arg(*ap, long); - else - return va_arg(*ap, int); -} - -static void vprintfmt(void (*putch)(int, void **), void **putdat, - const char *fmt, va_list ap) { - const char *p; - const char *last_fmt; - unsigned long long num; - int ch, err; - int base, lflag, width, precision, altflag; - char padc; - - while (1) { - while ((ch = *(unsigned char *)fmt) != '%') { - if (ch == '\0') - return; - fmt++; - putch(ch, putdat); - } - fmt++; - - // Process a %-escape sequence - last_fmt = fmt; - padc = ' '; - width = -1; - precision = -1; - lflag = 0; - altflag = 0; - reswitch: - switch (ch = *(unsigned char *)fmt++) { - - // flag to pad on the right - case '-': - padc = '-'; - goto reswitch; - - // flag to pad with 0's instead of spaces - case '0': - padc = '0'; - goto reswitch; - - // width field - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - for (precision = 0;; ++fmt) { - precision = precision * 10 + ch - '0'; - ch = *fmt; - if (ch < '0' || ch > '9') - break; - } - goto process_precision; - - case '*': - precision = va_arg(ap, int); - goto process_precision; - - case '.': - if (width < 0) - width = 0; - goto reswitch; - - case '#': - altflag = 1; - goto reswitch; - - process_precision: - if (width < 0) - width = precision, precision = -1; - goto reswitch; - - // long flag (doubled for long long) - case 'l': - lflag++; - goto reswitch; - - // character - case 'c': - putch(va_arg(ap, int), putdat); - break; - - // string - case 's': - if ((p = va_arg(ap, char *)) == NULL) - p = "(null)"; - if (width > 0 && padc != '-') { - size_t slen = strlen(p); - if (precision >= 0 && (size_t)precision < slen) - slen = precision; - for (width -= slen; width > 0; width--) - putch(padc, putdat); - } - for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); - width--) { - putch(ch, putdat); - p++; - } - for (; width > 0; width--) - putch(' ', putdat); - break; - - // (signed) decimal - case 'd': - num = getint(&ap, lflag); - if ((long long)num < 0) { - putch('-', putdat); - num = -(long long)num; - } - base = 10; - goto signed_number; - - // unsigned decimal - case 'u': - base = 10; - goto unsigned_number; - - // (unsigned) octal - case 'o': - // should do something with padding so it's always 3 octits - base = 8; - goto unsigned_number; - - // pointer - case 'p': - static_assert(sizeof(long) == sizeof(void *)); - lflag = 1; - putch('0', putdat); - putch('x', putdat); - /* fall through to 'x' */ - - // (unsigned) hexadecimal - case 'x': - base = 16; - unsigned_number: - num = getuint(&ap, lflag); - signed_number: - printnum(putch, putdat, num, base, width, padc); - break; - - // escaped '%' character - case '%': - putch(ch, putdat); - break; - - // unrecognized escape sequence - just print it literally - default: - putch('%', putdat); - fmt = last_fmt; - break; - } - } -} - -int printf(const char *fmt, ...) { - va_list ap; - va_start(ap, fmt); - - vprintfmt((void (*)(int, void **))putchar, 0, fmt, ap); - - va_end(ap); - return 0; // incorrect return value, but who cares, anyway? -} - -static void sprintf_putch(int ch, void **data) { - char **pstr = (char **)data; - **pstr = ch; - (*pstr)++; -} - -int sprintf(char *str, const char *fmt, ...) { - va_list ap; - char *str0 = str; - va_start(ap, fmt); - - vprintfmt(sprintf_putch, (void **)&str, fmt, ap); - *str = 0; - - va_end(ap); - return str - str0; -} - -void *memcpy(void *dest, const void *src, size_t len) { - if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t) - 1)) == - 0) { - const uintptr_t *s = (const uintptr_t *)src; - uintptr_t *d = (uintptr_t *)dest; - uintptr_t *end = (uintptr_t *)((char *)dest + len); - while (d + 8 < end) { - uintptr_t reg[8] = {s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7]}; - d[0] = reg[0]; - d[1] = reg[1]; - d[2] = reg[2]; - d[3] = reg[3]; - d[4] = reg[4]; - d[5] = reg[5]; - d[6] = reg[6]; - d[7] = reg[7]; - d += 8; - s += 8; - } - while (d < end) - *d++ = *s++; - } else { - const char *s = (const char *)src; - char *d = (char *)dest; - while (d < (char *)dest + len) - *d++ = *s++; - } - return dest; -} - -void *memset(void *dest, int byte, size_t len) { - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t) - 1)) == 0) { - uintptr_t word = byte & 0xFF; - word |= word << 8; - word |= word << 16; - word |= word << 16 << 16; - - uintptr_t *d = (uintptr_t *)dest; - while (d < (uintptr_t *)((char *)dest + len)) - *d++ = word; - } else { - char *d = (char *)dest; - while (d < (char *)dest + len) - *d++ = byte; - } - return dest; -} - -size_t strlen(const char *s) { - const char *p = s; - while (*p) - p++; - return p - s; -} - -size_t strnlen(const char *s, size_t n) { - const char *p = s; - while (n-- && *p) - p++; - return p - s; -} - -int strcmp(const char *s1, const char *s2) { - unsigned char c1, c2; - - do { - c1 = *s1++; - c2 = *s2++; - } while (c1 != 0 && c1 == c2); - - return c1 - c2; -} - -char *strcpy(char *dest, const char *src) { - char *d = dest; - while ((*d++ = *src++)) - ; - return dest; -} - -long atol(const char *str) { - long res = 0; - int sign = 0; - - while (*str == ' ') - str++; - - if (*str == '-' || *str == '+') { - sign = *str == '-'; - str++; - } - - while (*str) { - res *= 10; - res += *str++ - '0'; - } - - return sign ? -res : res; -} - -#ifdef __cplusplus -} -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/common/test.ld b/bb-tests/workloads/src/CTest/rvv/common/test.ld deleted file mode 100644 index 08c6e819..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/test.ld +++ /dev/null @@ -1,65 +0,0 @@ -/*======================================================================*/ -/* Proxy kernel linker script */ -/*======================================================================*/ -/* This is the linker script used when building the proxy kernel. */ - -/*----------------------------------------------------------------------*/ -/* Setup */ -/*----------------------------------------------------------------------*/ - -/* The OUTPUT_ARCH command specifies the machine architecture where the - argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------*/ -/* Sections */ -/*----------------------------------------------------------------------*/ - -SECTIONS -{ - - /* text: test code section */ - . = 0x80000000; - .text.init : { *(.text.init) } - - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - - . = ALIGN(0x1000); - .text : { *(.text) } - - /* data segment */ - .data : { *(.data) } - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : { *(.bss) } - - /* thread-local data segment */ - .tdata : - { - _tdata_begin = .; - *(.tdata) - _tdata_end = .; - } - .tbss : - { - *(.tbss) - _tbss_end = .; - } - - /* End of uninitalized data segement */ - _end = .; -} diff --git a/bb-tests/workloads/src/CTest/rvv/common/util.h b/bb-tests/workloads/src/CTest/rvv/common/util.h deleted file mode 100644 index 1bebbd4e..00000000 --- a/bb-tests/workloads/src/CTest/rvv/common/util.h +++ /dev/null @@ -1,115 +0,0 @@ -// See LICENSE for license details. - -#ifndef __UTIL_H -#define __UTIL_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern void setStats(int enable); - -#include - -#define static_assert(cond) \ - switch (0) { \ - case 0: \ - case !!(long)(cond):; \ - } - -static int verify(int n, const volatile int *test, const int *verify) { - int i; - // Unrolled for faster verification - for (i = 0; i < n / 2 * 2; i += 2) { - int t0 = test[i], t1 = test[i + 1]; - int v0 = verify[i], v1 = verify[i + 1]; - if (t0 != v0) - return i + 1; - if (t1 != v1) - return i + 2; - } - if (n % 2 != 0 && test[n - 1] != verify[n - 1]) - return n; - return 0; -} - -static int verifyDouble(int n, const volatile double *test, - const double *verify) { - int i; - // Unrolled for faster verification - for (i = 0; i < n / 2 * 2; i += 2) { - double t0 = test[i], t1 = test[i + 1]; - double v0 = verify[i], v1 = verify[i + 1]; - int eq1 = t0 == v0, eq2 = t1 == v1; - if (!(eq1 & eq2)) - return i + 1 + eq1; - } - if (n % 2 != 0 && test[n - 1] != verify[n - 1]) - return n; - return 0; -} - -static int verifyFloat(int n, const volatile float *test, const float *verify) { - int i; - // Unrolled for faster verification - for (i = 0; i < n / 2 * 2; i += 2) { - float t0 = test[i], t1 = test[i + 1]; - float v0 = verify[i], v1 = verify[i + 1]; - int eq1 = t0 == v0, eq2 = t1 == v1; - if (!(eq1 & eq2)) - return i + 1 + eq1; - } - if (n % 2 != 0 && test[n - 1] != verify[n - 1]) - return n; - return 0; -} - -static void __attribute__((noinline)) barrier(int ncores) { - static volatile int sense; - static volatile int count; - static __thread int threadsense; - - __sync_synchronize(); - - threadsense = !threadsense; - if (__sync_fetch_and_add(&count, 1) == ncores - 1) { - count = 0; - sense = threadsense; - } else - while (sense != threadsense) - ; - - __sync_synchronize(); -} - -static uint64_t lfsr(uint64_t x) { - uint64_t bit = (x ^ (x >> 1)) & 1; - return (x >> 1) | (bit << 62); -} - -static uintptr_t insn_len(uintptr_t pc) { - return (*(unsigned short *)pc & 3) ? 4 : 2; -} - -#ifdef __riscv -#include "encoding.h" -#endif - -#define stringify_1(s) #s -#define stringify(s) stringify_1(s) -#define stats(code, iter) \ - do { \ - unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ - code; \ - _c += read_csr(mcycle), _i += read_csr(minstret); \ - if (cid == 0) \ - printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ - stringify(code), _c, _c / iter, 10 * _c / iter % 10, _c / _i, \ - 10 * _c / _i % 10); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif //__UTIL_H diff --git a/bb-tests/workloads/src/CTest/rvv/env/LICENSE b/bb-tests/workloads/src/CTest/rvv/env/LICENSE deleted file mode 100644 index 48fe522a..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/LICENSE +++ /dev/null @@ -1,24 +0,0 @@ -Copyright (c) 2012-2015, The Regents of the University of California (Regents). -All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. Neither the name of the Regents nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING -OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS -BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED -HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE -MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/bb-tests/workloads/src/CTest/rvv/env/encoding.h b/bb-tests/workloads/src/CTest/rvv/env/encoding.h deleted file mode 100644 index 2bef816d..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/encoding.h +++ /dev/null @@ -1,5024 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ - -/* Copyright (c) 2023 RISC-V International */ - -/* - * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (02b4866) - */ - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_UBE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS_SBE 0x0000001000000000 -#define MSTATUS_MBE 0x0000002000000000 -#define MSTATUS_GVA 0x0000004000000000 -#define MSTATUS_MPV 0x0000008000000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define MSTATUSH_SBE 0x00000010 -#define MSTATUSH_MBE 0x00000020 -#define MSTATUSH_GVA 0x00000040 -#define MSTATUSH_MPV 0x00000080 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_UBE 0x00000040 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define HSTATUS_VSXL 0x300000000 -#define HSTATUS_VTSR 0x00400000 -#define HSTATUS_VTW 0x00200000 -#define HSTATUS_VTVM 0x00100000 -#define HSTATUS_VGEIN 0x0003f000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_SPVP 0x00000100 -#define HSTATUS_SPV 0x00000080 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_VSBE 0x00000020 - -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 - -#define MNSTATUS_NMIE 0x00000008 -#define MNSTATUS_MNPP 0x00001800 -#define MNSTATUS_MNPV 0x00000080 - -#define DCSR_XDEBUGVER (3U << 30) -#define DCSR_NDRESET (1 << 29) -#define DCSR_FULLRESET (1 << 28) -#define DCSR_EBREAKM (1 << 15) -#define DCSR_EBREAKH (1 << 14) -#define DCSR_EBREAKS (1 << 13) -#define DCSR_EBREAKU (1 << 12) -#define DCSR_STOPCYCLE (1 << 10) -#define DCSR_STOPTIME (1 << 9) -#define DCSR_CAUSE (7 << 6) -#define DCSR_DEBUGINT (1 << 5) -#define DCSR_HALT (1 << 3) -#define DCSR_STEP (1 << 2) -#define DCSR_PRV (3 << 0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 -#define DCSR_CAUSE_GROUP 6 - -#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen) - 4)) -#define MCONTROL_DMODE(xlen) (1ULL << ((xlen) - 5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen) - 11)) - -#define MCONTROL_SELECT (1 << 19) -#define MCONTROL_TIMING (1 << 18) -#define MCONTROL_ACTION (0x3f << 12) -#define MCONTROL_CHAIN (1 << 11) -#define MCONTROL_MATCH (0xf << 7) -#define MCONTROL_M (1 << 6) -#define MCONTROL_H (1 << 5) -#define MCONTROL_S (1 << 4) -#define MCONTROL_U (1 << 3) -#define MCONTROL_EXECUTE (1 << 2) -#define MCONTROL_STORE (1 << 1) -#define MCONTROL_LOAD (1 << 0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_VSSIP (1 << IRQ_VS_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_VSTIP (1 << IRQ_VS_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_VSEIP (1 << IRQ_VS_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) -#define MIP_SGEIP (1 << IRQ_S_GEXT) -#define MIP_LCOFIP (1 << IRQ_LCOF) - -#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) -#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) -#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) - -#define MIDELEG_FORCED_MASK MIP_HS_MASK - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define MENVCFG_FIOM 0x00000001 -#define MENVCFG_CBIE 0x00000030 -#define MENVCFG_CBCFE 0x00000040 -#define MENVCFG_CBZE 0x00000080 -#define MENVCFG_HADE 0x2000000000000000 -#define MENVCFG_PBMTE 0x4000000000000000 -#define MENVCFG_STCE 0x8000000000000000 - -#define MENVCFGH_HADE 0x20000000 -#define MENVCFGH_PBMTE 0x40000000 -#define MENVCFGH_STCE 0x80000000 - -#define MSTATEEN0_CS 0x00000001 -#define MSTATEEN0_FCSR 0x00000002 -#define MSTATEEN0_JVT 0x00000004 -#define MSTATEEN0_HCONTEXT 0x0200000000000000 -#define MSTATEEN0_HENVCFG 0x4000000000000000 -#define MSTATEEN_HSTATEEN 0x8000000000000000 - -#define MSTATEEN0H_HCONTEXT 0x02000000 -#define MSTATEEN0H_HENVCFG 0x40000000 -#define MSTATEENH_HSTATEEN 0x80000000 - -#define MHPMEVENT_VUINH 0x0400000000000000 -#define MHPMEVENT_VSINH 0x0800000000000000 -#define MHPMEVENT_UINH 0x1000000000000000 -#define MHPMEVENT_SINH 0x2000000000000000 -#define MHPMEVENT_MINH 0x4000000000000000 -#define MHPMEVENT_OF 0x8000000000000000 - -#define MHPMEVENTH_VUINH 0x04000000 -#define MHPMEVENTH_VSINH 0x08000000 -#define MHPMEVENTH_UINH 0x10000000 -#define MHPMEVENTH_SINH 0x20000000 -#define MHPMEVENTH_MINH 0x40000000 -#define MHPMEVENTH_OF 0x80000000 - -#define HENVCFG_FIOM 0x00000001 -#define HENVCFG_CBIE 0x00000030 -#define HENVCFG_CBCFE 0x00000040 -#define HENVCFG_CBZE 0x00000080 -#define HENVCFG_HADE 0x2000000000000000 -#define HENVCFG_PBMTE 0x4000000000000000 -#define HENVCFG_STCE 0x8000000000000000 - -#define HENVCFGH_HADE 0x20000000 -#define HENVCFGH_PBMTE 0x40000000 -#define HENVCFGH_STCE 0x80000000 - -#define HSTATEEN0_CS 0x00000001 -#define HSTATEEN0_FCSR 0x00000002 -#define HSTATEEN0_JVT 0x00000004 -#define HSTATEEN0_SCONTEXT 0x0200000000000000 -#define HSTATEEN0_SENVCFG 0x4000000000000000 -#define HSTATEEN_SSTATEEN 0x8000000000000000 - -#define HSTATEEN0H_SCONTEXT 0x02000000 -#define HSTATEEN0H_SENVCFG 0x40000000 -#define HSTATEENH_SSTATEEN 0x80000000 - -#define SENVCFG_FIOM 0x00000001 -#define SENVCFG_CBIE 0x00000030 -#define SENVCFG_CBCFE 0x00000040 -#define SENVCFG_CBZE 0x00000080 - -#define SSTATEEN0_CS 0x00000001 -#define SSTATEEN0_FCSR 0x00000002 -#define SSTATEEN0_JVT 0x00000004 - -#define MSECCFG_MML 0x00000001 -#define MSECCFG_MMWP 0x00000002 -#define MSECCFG_RLB 0x00000004 -#define MSECCFG_USEED 0x00000100 -#define MSECCFG_SSEED 0x00000200 - -/* jvt fields */ -#define JVT_MODE 0x3F -#define JVT_BASE (~0x3F) - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_M 3 - -#define PRV_HS (PRV_S + 1) - -#define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF -#define SATP64_MODE 0xF000000000000000 -#define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF - -#define SATP_MODE_OFF 0 -#define SATP_MODE_SV32 1 -#define SATP_MODE_SV39 8 -#define SATP_MODE_SV48 9 -#define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 11 - -#define HGATP32_MODE 0x80000000 -#define HGATP32_VMID 0x1FC00000 -#define HGATP32_PPN 0x003FFFFF - -#define HGATP64_MODE 0xF000000000000000 -#define HGATP64_VMID 0x03FFF00000000000 -#define HGATP64_PPN 0x00000FFFFFFFFFFF - -#define HGATP_MODE_OFF 0 -#define HGATP_MODE_SV32X4 1 -#define HGATP_MODE_SV39X4 8 -#define HGATP_MODE_SV48X4 9 -#define HGATP_MODE_SV57X4 10 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_COP 12 -#define IRQ_LCOF 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -/* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ -#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ -#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ -#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -#define MSTATUS_SD MSTATUS64_SD -#define SSTATUS_SD SSTATUS64_SD -#define RISCV_PGLEVEL_BITS 9 -#define SATP_MODE SATP64_MODE -#else -#define MSTATUS_SD MSTATUS32_SD -#define SSTATUS_SD SSTATUS32_SD -#define RISCV_PGLEVEL_BITS 10 -#define SATP_MODE SATP32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; \ - }) - -#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); }) - -#define swap_csr(reg, val) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; \ - }) - -#define set_csr(reg, bit) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; \ - }) - -#define clear_csr(reg, bit) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; \ - }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif - -/* Automatically generated by parse_opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_ADD16 0x40000077 -#define MASK_ADD16 0xfe00707f -#define MATCH_ADD32 0x40002077 -#define MASK_ADD32 0xfe00707f -#define MATCH_ADD64 0xc0001077 -#define MASK_ADD64 0xfe00707f -#define MATCH_ADD8 0x48000077 -#define MASK_ADD8 0xfe00707f -#define MATCH_ADD_UW 0x800003b -#define MASK_ADD_UW 0xfe00707f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_AES32DSI 0x2a000033 -#define MASK_AES32DSI 0x3e00707f -#define MATCH_AES32DSMI 0x2e000033 -#define MASK_AES32DSMI 0x3e00707f -#define MATCH_AES32ESI 0x22000033 -#define MASK_AES32ESI 0x3e00707f -#define MATCH_AES32ESMI 0x26000033 -#define MASK_AES32ESMI 0x3e00707f -#define MATCH_AES64DS 0x3a000033 -#define MASK_AES64DS 0xfe00707f -#define MATCH_AES64DSM 0x3e000033 -#define MASK_AES64DSM 0xfe00707f -#define MATCH_AES64ES 0x32000033 -#define MASK_AES64ES 0xfe00707f -#define MATCH_AES64ESM 0x36000033 -#define MASK_AES64ESM 0xfe00707f -#define MATCH_AES64IM 0x30001013 -#define MASK_AES64IM 0xfff0707f -#define MATCH_AES64KS1I 0x31001013 -#define MASK_AES64KS1I 0xff00707f -#define MATCH_AES64KS2 0x7e000033 -#define MASK_AES64KS2 0xfe00707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ANDN 0x40007033 -#define MASK_ANDN 0xfe00707f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_AVE 0xe0000077 -#define MASK_AVE 0xfe00707f -#define MATCH_BCLR 0x48001033 -#define MASK_BCLR 0xfe00707f -#define MATCH_BCLRI 0x48001013 -#define MASK_BCLRI 0xfc00707f -#define MATCH_BCOMPRESS 0x8006033 -#define MASK_BCOMPRESS 0xfe00707f -#define MATCH_BCOMPRESSW 0x800603b -#define MASK_BCOMPRESSW 0xfe00707f -#define MATCH_BDECOMPRESS 0x48006033 -#define MASK_BDECOMPRESS 0xfe00707f -#define MATCH_BDECOMPRESSW 0x4800603b -#define MASK_BDECOMPRESSW 0xfe00707f -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BEXT 0x48005033 -#define MASK_BEXT 0xfe00707f -#define MATCH_BEXTI 0x48005013 -#define MASK_BEXTI 0xfc00707f -#define MATCH_BFP 0x48007033 -#define MASK_BFP 0xfe00707f -#define MATCH_BFPW 0x4800703b -#define MASK_BFPW 0xfe00707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_BINV 0x68001033 -#define MASK_BINV 0xfe00707f -#define MATCH_BINVI 0x68001013 -#define MASK_BINVI 0xfc00707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BMATFLIP 0x60301013 -#define MASK_BMATFLIP 0xfff0707f -#define MATCH_BMATOR 0x8003033 -#define MASK_BMATOR 0xfe00707f -#define MATCH_BMATXOR 0x48003033 -#define MASK_BMATXOR 0xfe00707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BSET 0x28001033 -#define MASK_BSET 0xfe00707f -#define MATCH_BSETI 0x28001013 -#define MASK_BSETI 0xfc00707f -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_LBU 0x8000 -#define MASK_C_LBU 0xfc03 -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_LH 0x8440 -#define MASK_C_LH 0xfc43 -#define MATCH_C_LHU 0x8400 -#define MASK_C_LHU 0xfc43 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_MUL 0x9c41 -#define MASK_C_MUL 0xfc63 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xef83 -#define MATCH_C_NOT 0x9c75 -#define MASK_C_NOT 0xfc7f -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_SB 0x8800 -#define MASK_C_SB 0xfc03 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_SEXT_B 0x9c65 -#define MASK_C_SEXT_B 0xfc7f -#define MATCH_C_SEXT_H 0x9c6d -#define MASK_C_SEXT_H 0xfc7f -#define MATCH_C_SH 0x8c00 -#define MASK_C_SH 0xfc43 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_ZEXT_B 0x9c61 -#define MASK_C_ZEXT_B 0xfc7f -#define MATCH_C_ZEXT_H 0x9c69 -#define MASK_C_ZEXT_H 0xfc7f -#define MATCH_C_ZEXT_W 0x9c71 -#define MASK_C_ZEXT_W 0xfc7f -#define MATCH_CBO_CLEAN 0x10200f -#define MASK_CBO_CLEAN 0xfff07fff -#define MATCH_CBO_FLUSH 0x20200f -#define MASK_CBO_FLUSH 0xfff07fff -#define MATCH_CBO_INVAL 0x200f -#define MASK_CBO_INVAL 0xfff07fff -#define MATCH_CBO_ZERO 0x40200f -#define MASK_CBO_ZERO 0xfff07fff -#define MATCH_CLMUL 0xa001033 -#define MASK_CLMUL 0xfe00707f -#define MATCH_CLMULH 0xa003033 -#define MASK_CLMULH 0xfe00707f -#define MATCH_CLMULR 0xa002033 -#define MASK_CLMULR 0xfe00707f -#define MATCH_CLRS16 0xae800077 -#define MASK_CLRS16 0xfff0707f -#define MATCH_CLRS32 0xaf800077 -#define MASK_CLRS32 0xfff0707f -#define MATCH_CLRS8 0xae000077 -#define MASK_CLRS8 0xfff0707f -#define MATCH_CLZ 0x60001013 -#define MASK_CLZ 0xfff0707f -#define MATCH_CLZ16 0xae900077 -#define MASK_CLZ16 0xfff0707f -#define MATCH_CLZ32 0xaf900077 -#define MASK_CLZ32 0xfff0707f -#define MATCH_CLZ8 0xae100077 -#define MASK_CLZ8 0xfff0707f -#define MATCH_CLZW 0x6000101b -#define MASK_CLZW 0xfff0707f -#define MATCH_CM_JALT 0xa002 -#define MASK_CM_JALT 0xfc03 -#define MATCH_CM_MVA01S 0xac62 -#define MASK_CM_MVA01S 0xfc63 -#define MATCH_CM_MVSA01 0xac22 -#define MASK_CM_MVSA01 0xfc63 -#define MATCH_CM_POP 0xba02 -#define MASK_CM_POP 0xff03 -#define MATCH_CM_POPRET 0xbe02 -#define MASK_CM_POPRET 0xff03 -#define MATCH_CM_POPRETZ 0xbc02 -#define MASK_CM_POPRETZ 0xff03 -#define MATCH_CM_PUSH 0xb802 -#define MASK_CM_PUSH 0xff03 -#define MATCH_CMIX 0x6001033 -#define MASK_CMIX 0x600707f -#define MATCH_CMOV 0x6005033 -#define MASK_CMOV 0x600707f -#define MATCH_CMPEQ16 0x4c000077 -#define MASK_CMPEQ16 0xfe00707f -#define MATCH_CMPEQ8 0x4e000077 -#define MASK_CMPEQ8 0xfe00707f -#define MATCH_CPOP 0x60201013 -#define MASK_CPOP 0xfff0707f -#define MATCH_CPOPW 0x6020101b -#define MASK_CPOPW 0xfff0707f -#define MATCH_CRAS16 0x44000077 -#define MASK_CRAS16 0xfe00707f -#define MATCH_CRAS32 0x44002077 -#define MASK_CRAS32 0xfe00707f -#define MATCH_CRC32_B 0x61001013 -#define MASK_CRC32_B 0xfff0707f -#define MATCH_CRC32_D 0x61301013 -#define MASK_CRC32_D 0xfff0707f -#define MATCH_CRC32_H 0x61101013 -#define MASK_CRC32_H 0xfff0707f -#define MATCH_CRC32_W 0x61201013 -#define MASK_CRC32_W 0xfff0707f -#define MATCH_CRC32C_B 0x61801013 -#define MASK_CRC32C_B 0xfff0707f -#define MATCH_CRC32C_D 0x61b01013 -#define MASK_CRC32C_D 0xfff0707f -#define MATCH_CRC32C_H 0x61901013 -#define MASK_CRC32C_H 0xfff0707f -#define MATCH_CRC32C_W 0x61a01013 -#define MASK_CRC32C_W 0xfff0707f -#define MATCH_CRSA16 0x46000077 -#define MASK_CRSA16 0xfe00707f -#define MATCH_CRSA32 0x46002077 -#define MASK_CRSA32 0xfe00707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CTZ 0x60101013 -#define MASK_CTZ 0xfff0707f -#define MATCH_CTZW 0x6010101b -#define MASK_CTZW 0xfff0707f -#define MATCH_CZERO_EQZ 0xe005033 -#define MASK_CZERO_EQZ 0xfe00707f -#define MATCH_CZERO_NEZ 0xe007033 -#define MASK_CZERO_NEZ 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCLASS_H 0xe4001053 -#define MASK_FCLASS_H 0xfff0707f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_D_H 0x42200053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_H_D 0x44100053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_FCVT_H_L 0xd4200053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_FCVT_H_LU 0xd4300053 -#define MASK_FCVT_H_LU 0xfff0007f -#define MATCH_FCVT_H_Q 0x44300053 -#define MASK_FCVT_H_Q 0xfff0007f -#define MATCH_FCVT_H_S 0x44000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_FCVT_H_W 0xd4000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_WU 0xd4100053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_L_H 0xc4200053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FCVT_LU_H 0xc4300053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FCVT_Q_H 0x46200053 -#define MASK_FCVT_Q_H 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_S_H 0x40200053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_W_H 0xc4000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_WU_H 0xc4100053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FEQ_H 0xa4002053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLE_H 0xa4000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FLT_H 0xa4001053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FMAX_H 0x2c001053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMIN_H 0x2c000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJ_H 0x24000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJN_H 0x24001053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FSGNJX_H 0x24002053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_FSL 0x4001033 -#define MASK_FSL 0x600707f -#define MATCH_FSLW 0x400103b -#define MASK_FSLW 0x600707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FSQRT_H 0x5c000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FSR 0x4005033 -#define MASK_FSR 0x600707f -#define MATCH_FSRI 0x4005013 -#define MASK_FSRI 0x400707f -#define MATCH_FSRIW 0x400501b -#define MASK_FSRIW 0x600707f -#define MATCH_FSRW 0x400503b -#define MASK_FSRW 0x600707f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_GORC 0x28005033 -#define MASK_GORC 0xfe00707f -#define MATCH_GORCI 0x28005013 -#define MASK_GORCI 0xfc00707f -#define MATCH_GORCIW 0x2800501b -#define MASK_GORCIW 0xfe00707f -#define MATCH_GORCW 0x2800503b -#define MASK_GORCW 0xfe00707f -#define MATCH_GREV 0x68005033 -#define MASK_GREV 0xfe00707f -#define MATCH_GREVI 0x68005013 -#define MASK_GREVI 0xfc00707f -#define MATCH_GREVIW 0x6800501b -#define MASK_GREVIW 0xfe00707f -#define MATCH_GREVW 0x6800503b -#define MASK_GREVW 0xfe00707f -#define MATCH_HFENCE_GVMA 0x62000073 -#define MASK_HFENCE_GVMA 0xfe007fff -#define MATCH_HFENCE_VVMA 0x22000073 -#define MASK_HFENCE_VVMA 0xfe007fff -#define MATCH_HINVAL_GVMA 0x66000073 -#define MASK_HINVAL_GVMA 0xfe007fff -#define MATCH_HINVAL_VVMA 0x26000073 -#define MASK_HINVAL_VVMA 0xfe007fff -#define MATCH_HLV_B 0x60004073 -#define MASK_HLV_B 0xfff0707f -#define MATCH_HLV_BU 0x60104073 -#define MASK_HLV_BU 0xfff0707f -#define MATCH_HLV_D 0x6c004073 -#define MASK_HLV_D 0xfff0707f -#define MATCH_HLV_H 0x64004073 -#define MASK_HLV_H 0xfff0707f -#define MATCH_HLV_HU 0x64104073 -#define MASK_HLV_HU 0xfff0707f -#define MATCH_HLV_W 0x68004073 -#define MASK_HLV_W 0xfff0707f -#define MATCH_HLV_WU 0x68104073 -#define MASK_HLV_WU 0xfff0707f -#define MATCH_HLVX_HU 0x64304073 -#define MASK_HLVX_HU 0xfff0707f -#define MATCH_HLVX_WU 0x68304073 -#define MASK_HLVX_WU 0xfff0707f -#define MATCH_HSV_B 0x62004073 -#define MASK_HSV_B 0xfe007fff -#define MATCH_HSV_D 0x6e004073 -#define MASK_HSV_D 0xfe007fff -#define MATCH_HSV_H 0x66004073 -#define MASK_HSV_H 0xfe007fff -#define MATCH_HSV_W 0x6a004073 -#define MASK_HSV_W 0xfe007fff -#define MATCH_INSB 0xac000077 -#define MASK_INSB 0xff80707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_KABS16 0xad100077 -#define MASK_KABS16 0xfff0707f -#define MATCH_KABS32 0xad200077 -#define MASK_KABS32 0xfff0707f -#define MATCH_KABS8 0xad000077 -#define MASK_KABS8 0xfff0707f -#define MATCH_KABSW 0xad400077 -#define MASK_KABSW 0xfff0707f -#define MATCH_KADD16 0x10000077 -#define MASK_KADD16 0xfe00707f -#define MATCH_KADD32 0x10002077 -#define MASK_KADD32 0xfe00707f -#define MATCH_KADD64 0x90001077 -#define MASK_KADD64 0xfe00707f -#define MATCH_KADD8 0x18000077 -#define MASK_KADD8 0xfe00707f -#define MATCH_KADDH 0x4001077 -#define MASK_KADDH 0xfe00707f -#define MATCH_KADDW 0x1077 -#define MASK_KADDW 0xfe00707f -#define MATCH_KCRAS16 0x14000077 -#define MASK_KCRAS16 0xfe00707f -#define MATCH_KCRAS32 0x14002077 -#define MASK_KCRAS32 0xfe00707f -#define MATCH_KCRSA16 0x16000077 -#define MASK_KCRSA16 0xfe00707f -#define MATCH_KCRSA32 0x16002077 -#define MASK_KCRSA32 0xfe00707f -#define MATCH_KDMABB 0xd2001077 -#define MASK_KDMABB 0xfe00707f -#define MATCH_KDMABB16 0xd8001077 -#define MASK_KDMABB16 0xfe00707f -#define MATCH_KDMABT 0xe2001077 -#define MASK_KDMABT 0xfe00707f -#define MATCH_KDMABT16 0xe8001077 -#define MASK_KDMABT16 0xfe00707f -#define MATCH_KDMATT 0xf2001077 -#define MASK_KDMATT 0xfe00707f -#define MATCH_KDMATT16 0xf8001077 -#define MASK_KDMATT16 0xfe00707f -#define MATCH_KDMBB 0xa001077 -#define MASK_KDMBB 0xfe00707f -#define MATCH_KDMBB16 0xda001077 -#define MASK_KDMBB16 0xfe00707f -#define MATCH_KDMBT 0x1a001077 -#define MASK_KDMBT 0xfe00707f -#define MATCH_KDMBT16 0xea001077 -#define MASK_KDMBT16 0xfe00707f -#define MATCH_KDMTT 0x2a001077 -#define MASK_KDMTT 0xfe00707f -#define MATCH_KDMTT16 0xfa001077 -#define MASK_KDMTT16 0xfe00707f -#define MATCH_KHM16 0x86000077 -#define MASK_KHM16 0xfe00707f -#define MATCH_KHM8 0x8e000077 -#define MASK_KHM8 0xfe00707f -#define MATCH_KHMBB 0xc001077 -#define MASK_KHMBB 0xfe00707f -#define MATCH_KHMBB16 0xdc001077 -#define MASK_KHMBB16 0xfe00707f -#define MATCH_KHMBT 0x1c001077 -#define MASK_KHMBT 0xfe00707f -#define MATCH_KHMBT16 0xec001077 -#define MASK_KHMBT16 0xfe00707f -#define MATCH_KHMTT 0x2c001077 -#define MASK_KHMTT 0xfe00707f -#define MATCH_KHMTT16 0xfc001077 -#define MASK_KHMTT16 0xfe00707f -#define MATCH_KHMX16 0x96000077 -#define MASK_KHMX16 0xfe00707f -#define MATCH_KHMX8 0x9e000077 -#define MASK_KHMX8 0xfe00707f -#define MATCH_KMABB 0x5a001077 -#define MASK_KMABB 0xfe00707f -#define MATCH_KMABB32 0x5a002077 -#define MASK_KMABB32 0xfe00707f -#define MATCH_KMABT 0x6a001077 -#define MASK_KMABT 0xfe00707f -#define MATCH_KMABT32 0x6a002077 -#define MASK_KMABT32 0xfe00707f -#define MATCH_KMADA 0x48001077 -#define MASK_KMADA 0xfe00707f -#define MATCH_KMADRS 0x6c001077 -#define MASK_KMADRS 0xfe00707f -#define MATCH_KMADRS32 0x6c002077 -#define MASK_KMADRS32 0xfe00707f -#define MATCH_KMADS 0x5c001077 -#define MASK_KMADS 0xfe00707f -#define MATCH_KMADS32 0x5c002077 -#define MASK_KMADS32 0xfe00707f -#define MATCH_KMAR64 0x94001077 -#define MASK_KMAR64 0xfe00707f -#define MATCH_KMATT 0x7a001077 -#define MASK_KMATT 0xfe00707f -#define MATCH_KMATT32 0x7a002077 -#define MASK_KMATT32 0xfe00707f -#define MATCH_KMAXDA 0x4a001077 -#define MASK_KMAXDA 0xfe00707f -#define MATCH_KMAXDA32 0x4a002077 -#define MASK_KMAXDA32 0xfe00707f -#define MATCH_KMAXDS 0x7c001077 -#define MASK_KMAXDS 0xfe00707f -#define MATCH_KMAXDS32 0x7c002077 -#define MASK_KMAXDS32 0xfe00707f -#define MATCH_KMDA 0x38001077 -#define MASK_KMDA 0xfe00707f -#define MATCH_KMDA32 0x38002077 -#define MASK_KMDA32 0xfe00707f -#define MATCH_KMMAC 0x60001077 -#define MASK_KMMAC 0xfe00707f -#define MATCH_KMMAC_U 0x70001077 -#define MASK_KMMAC_U 0xfe00707f -#define MATCH_KMMAWB 0x46001077 -#define MASK_KMMAWB 0xfe00707f -#define MATCH_KMMAWB2 0xce001077 -#define MASK_KMMAWB2 0xfe00707f -#define MATCH_KMMAWB2_U 0xde001077 -#define MASK_KMMAWB2_U 0xfe00707f -#define MATCH_KMMAWB_U 0x56001077 -#define MASK_KMMAWB_U 0xfe00707f -#define MATCH_KMMAWT 0x66001077 -#define MASK_KMMAWT 0xfe00707f -#define MATCH_KMMAWT2 0xee001077 -#define MASK_KMMAWT2 0xfe00707f -#define MATCH_KMMAWT2_U 0xfe001077 -#define MASK_KMMAWT2_U 0xfe00707f -#define MATCH_KMMAWT_U 0x76001077 -#define MASK_KMMAWT_U 0xfe00707f -#define MATCH_KMMSB 0x42001077 -#define MASK_KMMSB 0xfe00707f -#define MATCH_KMMSB_U 0x52001077 -#define MASK_KMMSB_U 0xfe00707f -#define MATCH_KMMWB2 0x8e001077 -#define MASK_KMMWB2 0xfe00707f -#define MATCH_KMMWB2_U 0x9e001077 -#define MASK_KMMWB2_U 0xfe00707f -#define MATCH_KMMWT2 0xae001077 -#define MASK_KMMWT2 0xfe00707f -#define MATCH_KMMWT2_U 0xbe001077 -#define MASK_KMMWT2_U 0xfe00707f -#define MATCH_KMSDA 0x4c001077 -#define MASK_KMSDA 0xfe00707f -#define MATCH_KMSDA32 0x4c002077 -#define MASK_KMSDA32 0xfe00707f -#define MATCH_KMSR64 0x96001077 -#define MASK_KMSR64 0xfe00707f -#define MATCH_KMSXDA 0x4e001077 -#define MASK_KMSXDA 0xfe00707f -#define MATCH_KMSXDA32 0x4e002077 -#define MASK_KMSXDA32 0xfe00707f -#define MATCH_KMXDA 0x3a001077 -#define MASK_KMXDA 0xfe00707f -#define MATCH_KMXDA32 0x3a002077 -#define MASK_KMXDA32 0xfe00707f -#define MATCH_KSLL16 0x64000077 -#define MASK_KSLL16 0xfe00707f -#define MATCH_KSLL32 0x64002077 -#define MASK_KSLL32 0xfe00707f -#define MATCH_KSLL8 0x6c000077 -#define MASK_KSLL8 0xfe00707f -#define MATCH_KSLLI16 0x75000077 -#define MASK_KSLLI16 0xff00707f -#define MATCH_KSLLI32 0x84002077 -#define MASK_KSLLI32 0xfe00707f -#define MATCH_KSLLI8 0x7c800077 -#define MASK_KSLLI8 0xff80707f -#define MATCH_KSLLIW 0x36001077 -#define MASK_KSLLIW 0xfe00707f -#define MATCH_KSLLW 0x26001077 -#define MASK_KSLLW 0xfe00707f -#define MATCH_KSLRA16 0x56000077 -#define MASK_KSLRA16 0xfe00707f -#define MATCH_KSLRA16_U 0x66000077 -#define MASK_KSLRA16_U 0xfe00707f -#define MATCH_KSLRA32 0x56002077 -#define MASK_KSLRA32 0xfe00707f -#define MATCH_KSLRA32_U 0x66002077 -#define MASK_KSLRA32_U 0xfe00707f -#define MATCH_KSLRA8 0x5e000077 -#define MASK_KSLRA8 0xfe00707f -#define MATCH_KSLRA8_U 0x6e000077 -#define MASK_KSLRA8_U 0xfe00707f -#define MATCH_KSLRAW 0x6e001077 -#define MASK_KSLRAW 0xfe00707f -#define MATCH_KSLRAW_U 0x7e001077 -#define MASK_KSLRAW_U 0xfe00707f -#define MATCH_KSTAS16 0xc4002077 -#define MASK_KSTAS16 0xfe00707f -#define MATCH_KSTAS32 0xc0002077 -#define MASK_KSTAS32 0xfe00707f -#define MATCH_KSTSA16 0xc6002077 -#define MASK_KSTSA16 0xfe00707f -#define MATCH_KSTSA32 0xc2002077 -#define MASK_KSTSA32 0xfe00707f -#define MATCH_KSUB16 0x12000077 -#define MASK_KSUB16 0xfe00707f -#define MATCH_KSUB32 0x12002077 -#define MASK_KSUB32 0xfe00707f -#define MATCH_KSUB64 0x92001077 -#define MASK_KSUB64 0xfe00707f -#define MATCH_KSUB8 0x1a000077 -#define MASK_KSUB8 0xfe00707f -#define MATCH_KSUBH 0x6001077 -#define MASK_KSUBH 0xfe00707f -#define MATCH_KSUBW 0x2001077 -#define MASK_KSUBW 0xfe00707f -#define MATCH_KWMMUL 0x62001077 -#define MASK_KWMMUL 0xfe00707f -#define MATCH_KWMMUL_U 0x72001077 -#define MASK_KWMMUL_U 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_MADDR32 0xc4001077 -#define MASK_MADDR32 0xfe00707f -#define MATCH_MAX 0xa006033 -#define MASK_MAX 0xfe00707f -#define MATCH_MAXU 0xa007033 -#define MASK_MAXU 0xfe00707f -#define MATCH_MIN 0xa004033 -#define MASK_MIN 0xfe00707f -#define MATCH_MINU 0xa005033 -#define MASK_MINU 0xfe00707f -#define MATCH_MNRET 0x70200073 -#define MASK_MNRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_MSUBR32 0xc6001077 -#define MASK_MSUBR32 0xfe00707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_MULR64 0xf0001077 -#define MASK_MULR64 0xfe00707f -#define MATCH_MULSR64 0xe0001077 -#define MASK_MULSR64 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ORN 0x40006033 -#define MASK_ORN 0xfe00707f -#define MATCH_PACK 0x8004033 -#define MASK_PACK 0xfe00707f -#define MATCH_PACKH 0x8007033 -#define MASK_PACKH 0xfe00707f -#define MATCH_PACKU 0x48004033 -#define MASK_PACKU 0xfe00707f -#define MATCH_PACKUW 0x4800403b -#define MASK_PACKUW 0xfe00707f -#define MATCH_PACKW 0x800403b -#define MASK_PACKW 0xfe00707f -#define MATCH_PAUSE 0x100000f -#define MASK_PAUSE 0xffffffff -#define MATCH_PBSAD 0xfc000077 -#define MASK_PBSAD 0xfe00707f -#define MATCH_PBSADA 0xfe000077 -#define MASK_PBSADA 0xfe00707f -#define MATCH_PKBB16 0xe001077 -#define MASK_PKBB16 0xfe00707f -#define MATCH_PKBT16 0x1e001077 -#define MASK_PKBT16 0xfe00707f -#define MATCH_PKBT32 0x1e002077 -#define MASK_PKBT32 0xfe00707f -#define MATCH_PKTB16 0x3e001077 -#define MASK_PKTB16 0xfe00707f -#define MATCH_PKTB32 0x3e002077 -#define MASK_PKTB32 0xfe00707f -#define MATCH_PKTT16 0x2e001077 -#define MASK_PKTT16 0xfe00707f -#define MATCH_PREFETCH_I 0x6013 -#define MASK_PREFETCH_I 0x1f07fff -#define MATCH_PREFETCH_R 0x106013 -#define MASK_PREFETCH_R 0x1f07fff -#define MATCH_PREFETCH_W 0x306013 -#define MASK_PREFETCH_W 0x1f07fff -#define MATCH_RADD16 0x77 -#define MASK_RADD16 0xfe00707f -#define MATCH_RADD32 0x2077 -#define MASK_RADD32 0xfe00707f -#define MATCH_RADD64 0x80001077 -#define MASK_RADD64 0xfe00707f -#define MATCH_RADD8 0x8000077 -#define MASK_RADD8 0xfe00707f -#define MATCH_RADDW 0x20001077 -#define MASK_RADDW 0xfe00707f -#define MATCH_RCRAS16 0x4000077 -#define MASK_RCRAS16 0xfe00707f -#define MATCH_RCRAS32 0x4002077 -#define MASK_RCRAS32 0xfe00707f -#define MATCH_RCRSA16 0x6000077 -#define MASK_RCRSA16 0xfe00707f -#define MATCH_RCRSA32 0x6002077 -#define MASK_RCRSA32 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_ROL 0x60001033 -#define MASK_ROL 0xfe00707f -#define MATCH_ROLW 0x6000103b -#define MASK_ROLW 0xfe00707f -#define MATCH_ROR 0x60005033 -#define MASK_ROR 0xfe00707f -#define MATCH_RORI 0x60005013 -#define MASK_RORI 0xfc00707f -#define MATCH_RORIW 0x6000501b -#define MASK_RORIW 0xfe00707f -#define MATCH_RORW 0x6000503b -#define MASK_RORW 0xfe00707f -#define MATCH_RSTAS16 0xb4002077 -#define MASK_RSTAS16 0xfe00707f -#define MATCH_RSTAS32 0xb0002077 -#define MASK_RSTAS32 0xfe00707f -#define MATCH_RSTSA16 0xb6002077 -#define MASK_RSTSA16 0xfe00707f -#define MATCH_RSTSA32 0xb2002077 -#define MASK_RSTSA32 0xfe00707f -#define MATCH_RSUB16 0x2000077 -#define MASK_RSUB16 0xfe00707f -#define MATCH_RSUB32 0x2002077 -#define MASK_RSUB32 0xfe00707f -#define MATCH_RSUB64 0x82001077 -#define MASK_RSUB64 0xfe00707f -#define MATCH_RSUB8 0xa000077 -#define MASK_RSUB8 0xfe00707f -#define MATCH_RSUBW 0x22001077 -#define MASK_RSUBW 0xfe00707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_SCLIP16 0x84000077 -#define MASK_SCLIP16 0xff00707f -#define MATCH_SCLIP32 0xe4000077 -#define MASK_SCLIP32 0xfe00707f -#define MATCH_SCLIP8 0x8c000077 -#define MASK_SCLIP8 0xff80707f -#define MATCH_SCMPLE16 0x1c000077 -#define MASK_SCMPLE16 0xfe00707f -#define MATCH_SCMPLE8 0x1e000077 -#define MASK_SCMPLE8 0xfe00707f -#define MATCH_SCMPLT16 0xc000077 -#define MASK_SCMPLT16 0xfe00707f -#define MATCH_SCMPLT8 0xe000077 -#define MASK_SCMPLT8 0xfe00707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_SEXT_B 0x60401013 -#define MASK_SEXT_B 0xfff0707f -#define MATCH_SEXT_H 0x60501013 -#define MASK_SEXT_H 0xfff0707f -#define MATCH_SFENCE_INVAL_IR 0x18100073 -#define MASK_SFENCE_INVAL_IR 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_SFENCE_W_INVAL 0x18000073 -#define MASK_SFENCE_W_INVAL 0xffffffff -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SH1ADD 0x20002033 -#define MASK_SH1ADD 0xfe00707f -#define MATCH_SH1ADD_UW 0x2000203b -#define MASK_SH1ADD_UW 0xfe00707f -#define MATCH_SH2ADD 0x20004033 -#define MASK_SH2ADD 0xfe00707f -#define MATCH_SH2ADD_UW 0x2000403b -#define MASK_SH2ADD_UW 0xfe00707f -#define MATCH_SH3ADD 0x20006033 -#define MASK_SH3ADD 0xfe00707f -#define MATCH_SH3ADD_UW 0x2000603b -#define MASK_SH3ADD_UW 0xfe00707f -#define MATCH_SHA256SIG0 0x10201013 -#define MASK_SHA256SIG0 0xfff0707f -#define MATCH_SHA256SIG1 0x10301013 -#define MASK_SHA256SIG1 0xfff0707f -#define MATCH_SHA256SUM0 0x10001013 -#define MASK_SHA256SUM0 0xfff0707f -#define MATCH_SHA256SUM1 0x10101013 -#define MASK_SHA256SUM1 0xfff0707f -#define MATCH_SHA512SIG0 0x10601013 -#define MASK_SHA512SIG0 0xfff0707f -#define MATCH_SHA512SIG0H 0x5c000033 -#define MASK_SHA512SIG0H 0xfe00707f -#define MATCH_SHA512SIG0L 0x54000033 -#define MASK_SHA512SIG0L 0xfe00707f -#define MATCH_SHA512SIG1 0x10701013 -#define MASK_SHA512SIG1 0xfff0707f -#define MATCH_SHA512SIG1H 0x5e000033 -#define MASK_SHA512SIG1H 0xfe00707f -#define MATCH_SHA512SIG1L 0x56000033 -#define MASK_SHA512SIG1L 0xfe00707f -#define MATCH_SHA512SUM0 0x10401013 -#define MASK_SHA512SUM0 0xfff0707f -#define MATCH_SHA512SUM0R 0x50000033 -#define MASK_SHA512SUM0R 0xfe00707f -#define MATCH_SHA512SUM1 0x10501013 -#define MASK_SHA512SUM1 0xfff0707f -#define MATCH_SHA512SUM1R 0x52000033 -#define MASK_SHA512SUM1R 0xfe00707f -#define MATCH_SHFL 0x8001033 -#define MASK_SHFL 0xfe00707f -#define MATCH_SHFLI 0x8001013 -#define MASK_SHFLI 0xfe00707f -#define MATCH_SHFLW 0x800103b -#define MASK_SHFLW 0xfe00707f -#define MATCH_SINVAL_VMA 0x16000073 -#define MASK_SINVAL_VMA 0xfe007fff -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLL16 0x54000077 -#define MASK_SLL16 0xfe00707f -#define MATCH_SLL32 0x54002077 -#define MASK_SLL32 0xfe00707f -#define MATCH_SLL8 0x5c000077 -#define MASK_SLL8 0xfe00707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLLI16 0x74000077 -#define MASK_SLLI16 0xff00707f -#define MATCH_SLLI32 0x74002077 -#define MASK_SLLI32 0xfe00707f -#define MATCH_SLLI8 0x7c000077 -#define MASK_SLLI8 0xff80707f -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f -#define MATCH_SLLI_UW 0x800101b -#define MASK_SLLI_UW 0xfc00707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SLO 0x20001033 -#define MASK_SLO 0xfe00707f -#define MATCH_SLOI 0x20001013 -#define MASK_SLOI 0xfc00707f -#define MATCH_SLOIW 0x2000101b -#define MASK_SLOIW 0xfe00707f -#define MATCH_SLOW 0x2000103b -#define MASK_SLOW 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_SM3P0 0x10801013 -#define MASK_SM3P0 0xfff0707f -#define MATCH_SM3P1 0x10901013 -#define MASK_SM3P1 0xfff0707f -#define MATCH_SM4ED 0x30000033 -#define MASK_SM4ED 0x3e00707f -#define MATCH_SM4KS 0x34000033 -#define MASK_SM4KS 0x3e00707f -#define MATCH_SMAL 0x5e001077 -#define MASK_SMAL 0xfe00707f -#define MATCH_SMALBB 0x88001077 -#define MASK_SMALBB 0xfe00707f -#define MATCH_SMALBT 0x98001077 -#define MASK_SMALBT 0xfe00707f -#define MATCH_SMALDA 0x8c001077 -#define MASK_SMALDA 0xfe00707f -#define MATCH_SMALDRS 0x9a001077 -#define MASK_SMALDRS 0xfe00707f -#define MATCH_SMALDS 0x8a001077 -#define MASK_SMALDS 0xfe00707f -#define MATCH_SMALTT 0xa8001077 -#define MASK_SMALTT 0xfe00707f -#define MATCH_SMALXDA 0x9c001077 -#define MASK_SMALXDA 0xfe00707f -#define MATCH_SMALXDS 0xaa001077 -#define MASK_SMALXDS 0xfe00707f -#define MATCH_SMAQA 0xc8000077 -#define MASK_SMAQA 0xfe00707f -#define MATCH_SMAQA_SU 0xca000077 -#define MASK_SMAQA_SU 0xfe00707f -#define MATCH_SMAR64 0x84001077 -#define MASK_SMAR64 0xfe00707f -#define MATCH_SMAX16 0x82000077 -#define MASK_SMAX16 0xfe00707f -#define MATCH_SMAX32 0x92002077 -#define MASK_SMAX32 0xfe00707f -#define MATCH_SMAX8 0x8a000077 -#define MASK_SMAX8 0xfe00707f -#define MATCH_SMBB16 0x8001077 -#define MASK_SMBB16 0xfe00707f -#define MATCH_SMBT16 0x18001077 -#define MASK_SMBT16 0xfe00707f -#define MATCH_SMBT32 0x18002077 -#define MASK_SMBT32 0xfe00707f -#define MATCH_SMDRS 0x68001077 -#define MASK_SMDRS 0xfe00707f -#define MATCH_SMDRS32 0x68002077 -#define MASK_SMDRS32 0xfe00707f -#define MATCH_SMDS 0x58001077 -#define MASK_SMDS 0xfe00707f -#define MATCH_SMDS32 0x58002077 -#define MASK_SMDS32 0xfe00707f -#define MATCH_SMIN16 0x80000077 -#define MASK_SMIN16 0xfe00707f -#define MATCH_SMIN32 0x90002077 -#define MASK_SMIN32 0xfe00707f -#define MATCH_SMIN8 0x88000077 -#define MASK_SMIN8 0xfe00707f -#define MATCH_SMMUL 0x40001077 -#define MASK_SMMUL 0xfe00707f -#define MATCH_SMMUL_U 0x50001077 -#define MASK_SMMUL_U 0xfe00707f -#define MATCH_SMMWB 0x44001077 -#define MASK_SMMWB 0xfe00707f -#define MATCH_SMMWB_U 0x54001077 -#define MASK_SMMWB_U 0xfe00707f -#define MATCH_SMMWT 0x64001077 -#define MASK_SMMWT 0xfe00707f -#define MATCH_SMMWT_U 0x74001077 -#define MASK_SMMWT_U 0xfe00707f -#define MATCH_SMSLDA 0xac001077 -#define MASK_SMSLDA 0xfe00707f -#define MATCH_SMSLXDA 0xbc001077 -#define MASK_SMSLXDA 0xfe00707f -#define MATCH_SMSR64 0x86001077 -#define MASK_SMSR64 0xfe00707f -#define MATCH_SMTT16 0x28001077 -#define MASK_SMTT16 0xfe00707f -#define MATCH_SMTT32 0x28002077 -#define MASK_SMTT32 0xfe00707f -#define MATCH_SMUL16 0xa0000077 -#define MASK_SMUL16 0xfe00707f -#define MATCH_SMUL8 0xa8000077 -#define MASK_SMUL8 0xfe00707f -#define MATCH_SMULX16 0xa2000077 -#define MASK_SMULX16 0xfe00707f -#define MATCH_SMULX8 0xaa000077 -#define MASK_SMULX8 0xfe00707f -#define MATCH_SMXDS 0x78001077 -#define MASK_SMXDS 0xfe00707f -#define MATCH_SMXDS32 0x78002077 -#define MASK_SMXDS32 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_SRA16 0x50000077 -#define MASK_SRA16 0xfe00707f -#define MATCH_SRA16_U 0x60000077 -#define MASK_SRA16_U 0xfe00707f -#define MATCH_SRA32 0x50002077 -#define MASK_SRA32 0xfe00707f -#define MATCH_SRA32_U 0x60002077 -#define MASK_SRA32_U 0xfe00707f -#define MATCH_SRA8 0x58000077 -#define MASK_SRA8 0xfe00707f -#define MATCH_SRA8_U 0x68000077 -#define MASK_SRA8_U 0xfe00707f -#define MATCH_SRA_U 0x24001077 -#define MASK_SRA_U 0xfe00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_SRAI16 0x70000077 -#define MASK_SRAI16 0xff00707f -#define MATCH_SRAI16_U 0x71000077 -#define MASK_SRAI16_U 0xff00707f -#define MATCH_SRAI32 0x70002077 -#define MASK_SRAI32 0xfe00707f -#define MATCH_SRAI32_U 0x80002077 -#define MASK_SRAI32_U 0xfe00707f -#define MATCH_SRAI8 0x78000077 -#define MASK_SRAI8 0xff80707f -#define MATCH_SRAI8_U 0x78800077 -#define MASK_SRAI8_U 0xff80707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f -#define MATCH_SRAI_U 0xd4001077 -#define MASK_SRAI_U 0xfc00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_SRAIW_U 0x34001077 -#define MASK_SRAIW_U 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRL16 0x52000077 -#define MASK_SRL16 0xfe00707f -#define MATCH_SRL16_U 0x62000077 -#define MASK_SRL16_U 0xfe00707f -#define MATCH_SRL32 0x52002077 -#define MASK_SRL32 0xfe00707f -#define MATCH_SRL32_U 0x62002077 -#define MASK_SRL32_U 0xfe00707f -#define MATCH_SRL8 0x5a000077 -#define MASK_SRL8 0xfe00707f -#define MATCH_SRL8_U 0x6a000077 -#define MASK_SRL8_U 0xfe00707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRLI16 0x72000077 -#define MASK_SRLI16 0xff00707f -#define MATCH_SRLI16_U 0x73000077 -#define MASK_SRLI16_U 0xff00707f -#define MATCH_SRLI32 0x72002077 -#define MASK_SRLI32 0xfe00707f -#define MATCH_SRLI32_U 0x82002077 -#define MASK_SRLI32_U 0xfe00707f -#define MATCH_SRLI8 0x7a000077 -#define MASK_SRLI8 0xff80707f -#define MATCH_SRLI8_U 0x7a800077 -#define MASK_SRLI8_U 0xff80707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRO 0x20005033 -#define MASK_SRO 0xfe00707f -#define MATCH_SROI 0x20005013 -#define MASK_SROI 0xfc00707f -#define MATCH_SROIW 0x2000501b -#define MASK_SROIW 0xfe00707f -#define MATCH_SROW 0x2000503b -#define MASK_SROW 0xfe00707f -#define MATCH_STAS16 0xf4002077 -#define MASK_STAS16 0xfe00707f -#define MATCH_STAS32 0xf0002077 -#define MASK_STAS32 0xfe00707f -#define MATCH_STSA16 0xf6002077 -#define MASK_STSA16 0xfe00707f -#define MATCH_STSA32 0xf2002077 -#define MASK_STSA32 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SUB16 0x42000077 -#define MASK_SUB16 0xfe00707f -#define MATCH_SUB32 0x42002077 -#define MASK_SUB32 0xfe00707f -#define MATCH_SUB64 0xc2001077 -#define MASK_SUB64 0xfe00707f -#define MATCH_SUB8 0x4a000077 -#define MASK_SUB8 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SUNPKD810 0xac800077 -#define MASK_SUNPKD810 0xfff0707f -#define MATCH_SUNPKD820 0xac900077 -#define MASK_SUNPKD820 0xfff0707f -#define MATCH_SUNPKD830 0xaca00077 -#define MASK_SUNPKD830 0xfff0707f -#define MATCH_SUNPKD831 0xacb00077 -#define MASK_SUNPKD831 0xfff0707f -#define MATCH_SUNPKD832 0xad300077 -#define MASK_SUNPKD832 0xfff0707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_UCLIP16 0x85000077 -#define MASK_UCLIP16 0xff00707f -#define MATCH_UCLIP32 0xf4000077 -#define MASK_UCLIP32 0xfe00707f -#define MATCH_UCLIP8 0x8d000077 -#define MASK_UCLIP8 0xff80707f -#define MATCH_UCMPLE16 0x3c000077 -#define MASK_UCMPLE16 0xfe00707f -#define MATCH_UCMPLE8 0x3e000077 -#define MASK_UCMPLE8 0xfe00707f -#define MATCH_UCMPLT16 0x2c000077 -#define MASK_UCMPLT16 0xfe00707f -#define MATCH_UCMPLT8 0x2e000077 -#define MASK_UCMPLT8 0xfe00707f -#define MATCH_UKADD16 0x30000077 -#define MASK_UKADD16 0xfe00707f -#define MATCH_UKADD32 0x30002077 -#define MASK_UKADD32 0xfe00707f -#define MATCH_UKADD64 0xb0001077 -#define MASK_UKADD64 0xfe00707f -#define MATCH_UKADD8 0x38000077 -#define MASK_UKADD8 0xfe00707f -#define MATCH_UKADDH 0x14001077 -#define MASK_UKADDH 0xfe00707f -#define MATCH_UKADDW 0x10001077 -#define MASK_UKADDW 0xfe00707f -#define MATCH_UKCRAS16 0x34000077 -#define MASK_UKCRAS16 0xfe00707f -#define MATCH_UKCRAS32 0x34002077 -#define MASK_UKCRAS32 0xfe00707f -#define MATCH_UKCRSA16 0x36000077 -#define MASK_UKCRSA16 0xfe00707f -#define MATCH_UKCRSA32 0x36002077 -#define MASK_UKCRSA32 0xfe00707f -#define MATCH_UKMAR64 0xb4001077 -#define MASK_UKMAR64 0xfe00707f -#define MATCH_UKMSR64 0xb6001077 -#define MASK_UKMSR64 0xfe00707f -#define MATCH_UKSTAS16 0xe4002077 -#define MASK_UKSTAS16 0xfe00707f -#define MATCH_UKSTAS32 0xe0002077 -#define MASK_UKSTAS32 0xfe00707f -#define MATCH_UKSTSA16 0xe6002077 -#define MASK_UKSTSA16 0xfe00707f -#define MATCH_UKSTSA32 0xe2002077 -#define MASK_UKSTSA32 0xfe00707f -#define MATCH_UKSUB16 0x32000077 -#define MASK_UKSUB16 0xfe00707f -#define MATCH_UKSUB32 0x32002077 -#define MASK_UKSUB32 0xfe00707f -#define MATCH_UKSUB64 0xb2001077 -#define MASK_UKSUB64 0xfe00707f -#define MATCH_UKSUB8 0x3a000077 -#define MASK_UKSUB8 0xfe00707f -#define MATCH_UKSUBH 0x16001077 -#define MASK_UKSUBH 0xfe00707f -#define MATCH_UKSUBW 0x12001077 -#define MASK_UKSUBW 0xfe00707f -#define MATCH_UMAQA 0xcc000077 -#define MASK_UMAQA 0xfe00707f -#define MATCH_UMAR64 0xa4001077 -#define MASK_UMAR64 0xfe00707f -#define MATCH_UMAX16 0x92000077 -#define MASK_UMAX16 0xfe00707f -#define MATCH_UMAX32 0xa2002077 -#define MASK_UMAX32 0xfe00707f -#define MATCH_UMAX8 0x9a000077 -#define MASK_UMAX8 0xfe00707f -#define MATCH_UMIN16 0x90000077 -#define MASK_UMIN16 0xfe00707f -#define MATCH_UMIN32 0xa0002077 -#define MASK_UMIN32 0xfe00707f -#define MATCH_UMIN8 0x98000077 -#define MASK_UMIN8 0xfe00707f -#define MATCH_UMSR64 0xa6001077 -#define MASK_UMSR64 0xfe00707f -#define MATCH_UMUL16 0xb0000077 -#define MASK_UMUL16 0xfe00707f -#define MATCH_UMUL8 0xb8000077 -#define MASK_UMUL8 0xfe00707f -#define MATCH_UMULX16 0xb2000077 -#define MASK_UMULX16 0xfe00707f -#define MATCH_UMULX8 0xba000077 -#define MASK_UMULX8 0xfe00707f -#define MATCH_UNSHFL 0x8005033 -#define MASK_UNSHFL 0xfe00707f -#define MATCH_UNSHFLI 0x8005013 -#define MASK_UNSHFLI 0xfe00707f -#define MATCH_UNSHFLW 0x800503b -#define MASK_UNSHFLW 0xfe00707f -#define MATCH_URADD16 0x20000077 -#define MASK_URADD16 0xfe00707f -#define MATCH_URADD32 0x20002077 -#define MASK_URADD32 0xfe00707f -#define MATCH_URADD64 0xa0001077 -#define MASK_URADD64 0xfe00707f -#define MATCH_URADD8 0x28000077 -#define MASK_URADD8 0xfe00707f -#define MATCH_URADDW 0x30001077 -#define MASK_URADDW 0xfe00707f -#define MATCH_URCRAS16 0x24000077 -#define MASK_URCRAS16 0xfe00707f -#define MATCH_URCRAS32 0x24002077 -#define MASK_URCRAS32 0xfe00707f -#define MATCH_URCRSA16 0x26000077 -#define MASK_URCRSA16 0xfe00707f -#define MATCH_URCRSA32 0x26002077 -#define MASK_URCRSA32 0xfe00707f -#define MATCH_URSTAS16 0xd4002077 -#define MASK_URSTAS16 0xfe00707f -#define MATCH_URSTAS32 0xd0002077 -#define MASK_URSTAS32 0xfe00707f -#define MATCH_URSTSA16 0xd6002077 -#define MASK_URSTSA16 0xfe00707f -#define MATCH_URSTSA32 0xd2002077 -#define MASK_URSTSA32 0xfe00707f -#define MATCH_URSUB16 0x22000077 -#define MASK_URSUB16 0xfe00707f -#define MATCH_URSUB32 0x22002077 -#define MASK_URSUB32 0xfe00707f -#define MATCH_URSUB64 0xa2001077 -#define MASK_URSUB64 0xfe00707f -#define MATCH_URSUB8 0x2a000077 -#define MASK_URSUB8 0xfe00707f -#define MATCH_URSUBW 0x32001077 -#define MASK_URSUBW 0xfe00707f -#define MATCH_VAADD_VV 0x24002057 -#define MASK_VAADD_VV 0xfc00707f -#define MATCH_VAADD_VX 0x24006057 -#define MASK_VAADD_VX 0xfc00707f -#define MATCH_VAADDU_VV 0x20002057 -#define MASK_VAADDU_VV 0xfc00707f -#define MATCH_VAADDU_VX 0x20006057 -#define MASK_VAADDU_VX 0xfc00707f -#define MATCH_VADC_VIM 0x40003057 -#define MASK_VADC_VIM 0xfe00707f -#define MATCH_VADC_VVM 0x40000057 -#define MASK_VADC_VVM 0xfe00707f -#define MATCH_VADC_VXM 0x40004057 -#define MASK_VADC_VXM 0xfe00707f -#define MATCH_VADD_VI 0x3057 -#define MASK_VADD_VI 0xfc00707f -#define MATCH_VADD_VV 0x57 -#define MASK_VADD_VV 0xfc00707f -#define MATCH_VADD_VX 0x4057 -#define MASK_VADD_VX 0xfc00707f -#define MATCH_VAMOADDEI16_V 0x502f -#define MASK_VAMOADDEI16_V 0xf800707f -#define MATCH_VAMOADDEI32_V 0x602f -#define MASK_VAMOADDEI32_V 0xf800707f -#define MATCH_VAMOADDEI64_V 0x702f -#define MASK_VAMOADDEI64_V 0xf800707f -#define MATCH_VAMOADDEI8_V 0x2f -#define MASK_VAMOADDEI8_V 0xf800707f -#define MATCH_VAMOANDEI16_V 0x6000502f -#define MASK_VAMOANDEI16_V 0xf800707f -#define MATCH_VAMOANDEI32_V 0x6000602f -#define MASK_VAMOANDEI32_V 0xf800707f -#define MATCH_VAMOANDEI64_V 0x6000702f -#define MASK_VAMOANDEI64_V 0xf800707f -#define MATCH_VAMOANDEI8_V 0x6000002f -#define MASK_VAMOANDEI8_V 0xf800707f -#define MATCH_VAMOMAXEI16_V 0xa000502f -#define MASK_VAMOMAXEI16_V 0xf800707f -#define MATCH_VAMOMAXEI32_V 0xa000602f -#define MASK_VAMOMAXEI32_V 0xf800707f -#define MATCH_VAMOMAXEI64_V 0xa000702f -#define MASK_VAMOMAXEI64_V 0xf800707f -#define MATCH_VAMOMAXEI8_V 0xa000002f -#define MASK_VAMOMAXEI8_V 0xf800707f -#define MATCH_VAMOMAXUEI16_V 0xe000502f -#define MASK_VAMOMAXUEI16_V 0xf800707f -#define MATCH_VAMOMAXUEI32_V 0xe000602f -#define MASK_VAMOMAXUEI32_V 0xf800707f -#define MATCH_VAMOMAXUEI64_V 0xe000702f -#define MASK_VAMOMAXUEI64_V 0xf800707f -#define MATCH_VAMOMAXUEI8_V 0xe000002f -#define MASK_VAMOMAXUEI8_V 0xf800707f -#define MATCH_VAMOMINEI16_V 0x8000502f -#define MASK_VAMOMINEI16_V 0xf800707f -#define MATCH_VAMOMINEI32_V 0x8000602f -#define MASK_VAMOMINEI32_V 0xf800707f -#define MATCH_VAMOMINEI64_V 0x8000702f -#define MASK_VAMOMINEI64_V 0xf800707f -#define MATCH_VAMOMINEI8_V 0x8000002f -#define MASK_VAMOMINEI8_V 0xf800707f -#define MATCH_VAMOMINUEI16_V 0xc000502f -#define MASK_VAMOMINUEI16_V 0xf800707f -#define MATCH_VAMOMINUEI32_V 0xc000602f -#define MASK_VAMOMINUEI32_V 0xf800707f -#define MATCH_VAMOMINUEI64_V 0xc000702f -#define MASK_VAMOMINUEI64_V 0xf800707f -#define MATCH_VAMOMINUEI8_V 0xc000002f -#define MASK_VAMOMINUEI8_V 0xf800707f -#define MATCH_VAMOOREI16_V 0x4000502f -#define MASK_VAMOOREI16_V 0xf800707f -#define MATCH_VAMOOREI32_V 0x4000602f -#define MASK_VAMOOREI32_V 0xf800707f -#define MATCH_VAMOOREI64_V 0x4000702f -#define MASK_VAMOOREI64_V 0xf800707f -#define MATCH_VAMOOREI8_V 0x4000002f -#define MASK_VAMOOREI8_V 0xf800707f -#define MATCH_VAMOSWAPEI16_V 0x800502f -#define MASK_VAMOSWAPEI16_V 0xf800707f -#define MATCH_VAMOSWAPEI32_V 0x800602f -#define MASK_VAMOSWAPEI32_V 0xf800707f -#define MATCH_VAMOSWAPEI64_V 0x800702f -#define MASK_VAMOSWAPEI64_V 0xf800707f -#define MATCH_VAMOSWAPEI8_V 0x800002f -#define MASK_VAMOSWAPEI8_V 0xf800707f -#define MATCH_VAMOXOREI16_V 0x2000502f -#define MASK_VAMOXOREI16_V 0xf800707f -#define MATCH_VAMOXOREI32_V 0x2000602f -#define MASK_VAMOXOREI32_V 0xf800707f -#define MATCH_VAMOXOREI64_V 0x2000702f -#define MASK_VAMOXOREI64_V 0xf800707f -#define MATCH_VAMOXOREI8_V 0x2000002f -#define MASK_VAMOXOREI8_V 0xf800707f -#define MATCH_VAND_VI 0x24003057 -#define MASK_VAND_VI 0xfc00707f -#define MATCH_VAND_VV 0x24000057 -#define MASK_VAND_VV 0xfc00707f -#define MATCH_VAND_VX 0x24004057 -#define MASK_VAND_VX 0xfc00707f -#define MATCH_VASUB_VV 0x2c002057 -#define MASK_VASUB_VV 0xfc00707f -#define MATCH_VASUB_VX 0x2c006057 -#define MASK_VASUB_VX 0xfc00707f -#define MATCH_VASUBU_VV 0x28002057 -#define MASK_VASUBU_VV 0xfc00707f -#define MATCH_VASUBU_VX 0x28006057 -#define MASK_VASUBU_VX 0xfc00707f -#define MATCH_VCOMPRESS_VM 0x5e002057 -#define MASK_VCOMPRESS_VM 0xfe00707f -#define MATCH_VCPOP_M 0x40082057 -#define MASK_VCPOP_M 0xfc0ff07f -#define MATCH_VDIV_VV 0x84002057 -#define MASK_VDIV_VV 0xfc00707f -#define MATCH_VDIV_VX 0x84006057 -#define MASK_VDIV_VX 0xfc00707f -#define MATCH_VDIVU_VV 0x80002057 -#define MASK_VDIVU_VV 0xfc00707f -#define MATCH_VDIVU_VX 0x80006057 -#define MASK_VDIVU_VX 0xfc00707f -#define MATCH_VFADD_VF 0x5057 -#define MASK_VFADD_VF 0xfc00707f -#define MATCH_VFADD_VV 0x1057 -#define MASK_VFADD_VV 0xfc00707f -#define MATCH_VFCLASS_V 0x4c081057 -#define MASK_VFCLASS_V 0xfc0ff07f -#define MATCH_VFCVT_F_X_V 0x48019057 -#define MASK_VFCVT_F_X_V 0xfc0ff07f -#define MATCH_VFCVT_F_XU_V 0x48011057 -#define MASK_VFCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 -#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 -#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFCVT_X_F_V 0x48009057 -#define MASK_VFCVT_X_F_V 0xfc0ff07f -#define MATCH_VFCVT_XU_F_V 0x48001057 -#define MASK_VFCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFDIV_VF 0x80005057 -#define MASK_VFDIV_VF 0xfc00707f -#define MATCH_VFDIV_VV 0x80001057 -#define MASK_VFDIV_VV 0xfc00707f -#define MATCH_VFIRST_M 0x4008a057 -#define MASK_VFIRST_M 0xfc0ff07f -#define MATCH_VFMACC_VF 0xb0005057 -#define MASK_VFMACC_VF 0xfc00707f -#define MATCH_VFMACC_VV 0xb0001057 -#define MASK_VFMACC_VV 0xfc00707f -#define MATCH_VFMADD_VF 0xa0005057 -#define MASK_VFMADD_VF 0xfc00707f -#define MATCH_VFMADD_VV 0xa0001057 -#define MASK_VFMADD_VV 0xfc00707f -#define MATCH_VFMAX_VF 0x18005057 -#define MASK_VFMAX_VF 0xfc00707f -#define MATCH_VFMAX_VV 0x18001057 -#define MASK_VFMAX_VV 0xfc00707f -#define MATCH_VFMERGE_VFM 0x5c005057 -#define MASK_VFMERGE_VFM 0xfe00707f -#define MATCH_VFMIN_VF 0x10005057 -#define MASK_VFMIN_VF 0xfc00707f -#define MATCH_VFMIN_VV 0x10001057 -#define MASK_VFMIN_VV 0xfc00707f -#define MATCH_VFMSAC_VF 0xb8005057 -#define MASK_VFMSAC_VF 0xfc00707f -#define MATCH_VFMSAC_VV 0xb8001057 -#define MASK_VFMSAC_VV 0xfc00707f -#define MATCH_VFMSUB_VF 0xa8005057 -#define MASK_VFMSUB_VF 0xfc00707f -#define MATCH_VFMSUB_VV 0xa8001057 -#define MASK_VFMSUB_VV 0xfc00707f -#define MATCH_VFMUL_VF 0x90005057 -#define MASK_VFMUL_VF 0xfc00707f -#define MATCH_VFMUL_VV 0x90001057 -#define MASK_VFMUL_VV 0xfc00707f -#define MATCH_VFMV_F_S 0x42001057 -#define MASK_VFMV_F_S 0xfe0ff07f -#define MATCH_VFMV_S_F 0x42005057 -#define MASK_VFMV_S_F 0xfff0707f -#define MATCH_VFMV_V_F 0x5e005057 -#define MASK_VFMV_V_F 0xfff0707f -#define MATCH_VFNCVT_F_F_W 0x480a1057 -#define MASK_VFNCVT_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_F_X_W 0x48099057 -#define MASK_VFNCVT_F_X_W 0xfc0ff07f -#define MATCH_VFNCVT_F_XU_W 0x48091057 -#define MASK_VFNCVT_F_XU_W 0xfc0ff07f -#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 -#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 -#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f -#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 -#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f -#define MATCH_VFNCVT_X_F_W 0x48089057 -#define MASK_VFNCVT_X_F_W 0xfc0ff07f -#define MATCH_VFNCVT_XU_F_W 0x48081057 -#define MASK_VFNCVT_XU_F_W 0xfc0ff07f -#define MATCH_VFNMACC_VF 0xb4005057 -#define MASK_VFNMACC_VF 0xfc00707f -#define MATCH_VFNMACC_VV 0xb4001057 -#define MASK_VFNMACC_VV 0xfc00707f -#define MATCH_VFNMADD_VF 0xa4005057 -#define MASK_VFNMADD_VF 0xfc00707f -#define MATCH_VFNMADD_VV 0xa4001057 -#define MASK_VFNMADD_VV 0xfc00707f -#define MATCH_VFNMSAC_VF 0xbc005057 -#define MASK_VFNMSAC_VF 0xfc00707f -#define MATCH_VFNMSAC_VV 0xbc001057 -#define MASK_VFNMSAC_VV 0xfc00707f -#define MATCH_VFNMSUB_VF 0xac005057 -#define MASK_VFNMSUB_VF 0xfc00707f -#define MATCH_VFNMSUB_VV 0xac001057 -#define MASK_VFNMSUB_VV 0xfc00707f -#define MATCH_VFRDIV_VF 0x84005057 -#define MASK_VFRDIV_VF 0xfc00707f -#define MATCH_VFREC7_V 0x4c029057 -#define MASK_VFREC7_V 0xfc0ff07f -#define MATCH_VFREDMAX_VS 0x1c001057 -#define MASK_VFREDMAX_VS 0xfc00707f -#define MATCH_VFREDMIN_VS 0x14001057 -#define MASK_VFREDMIN_VS 0xfc00707f -#define MATCH_VFREDOSUM_VS 0xc001057 -#define MASK_VFREDOSUM_VS 0xfc00707f -#define MATCH_VFREDUSUM_VS 0x4001057 -#define MASK_VFREDUSUM_VS 0xfc00707f -#define MATCH_VFRSQRT7_V 0x4c021057 -#define MASK_VFRSQRT7_V 0xfc0ff07f -#define MATCH_VFRSUB_VF 0x9c005057 -#define MASK_VFRSUB_VF 0xfc00707f -#define MATCH_VFSGNJ_VF 0x20005057 -#define MASK_VFSGNJ_VF 0xfc00707f -#define MATCH_VFSGNJ_VV 0x20001057 -#define MASK_VFSGNJ_VV 0xfc00707f -#define MATCH_VFSGNJN_VF 0x24005057 -#define MASK_VFSGNJN_VF 0xfc00707f -#define MATCH_VFSGNJN_VV 0x24001057 -#define MASK_VFSGNJN_VV 0xfc00707f -#define MATCH_VFSGNJX_VF 0x28005057 -#define MASK_VFSGNJX_VF 0xfc00707f -#define MATCH_VFSGNJX_VV 0x28001057 -#define MASK_VFSGNJX_VV 0xfc00707f -#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 -#define MASK_VFSLIDE1DOWN_VF 0xfc00707f -#define MATCH_VFSLIDE1UP_VF 0x38005057 -#define MASK_VFSLIDE1UP_VF 0xfc00707f -#define MATCH_VFSQRT_V 0x4c001057 -#define MASK_VFSQRT_V 0xfc0ff07f -#define MATCH_VFSUB_VF 0x8005057 -#define MASK_VFSUB_VF 0xfc00707f -#define MATCH_VFSUB_VV 0x8001057 -#define MASK_VFSUB_VV 0xfc00707f -#define MATCH_VFWADD_VF 0xc0005057 -#define MASK_VFWADD_VF 0xfc00707f -#define MATCH_VFWADD_VV 0xc0001057 -#define MASK_VFWADD_VV 0xfc00707f -#define MATCH_VFWADD_WF 0xd0005057 -#define MASK_VFWADD_WF 0xfc00707f -#define MATCH_VFWADD_WV 0xd0001057 -#define MASK_VFWADD_WV 0xfc00707f -#define MATCH_VFWCVT_F_F_V 0x48061057 -#define MASK_VFWCVT_F_F_V 0xfc0ff07f -#define MATCH_VFWCVT_F_X_V 0x48059057 -#define MASK_VFWCVT_F_X_V 0xfc0ff07f -#define MATCH_VFWCVT_F_XU_V 0x48051057 -#define MASK_VFWCVT_F_XU_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 -#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 -#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f -#define MATCH_VFWCVT_X_F_V 0x48049057 -#define MASK_VFWCVT_X_F_V 0xfc0ff07f -#define MATCH_VFWCVT_XU_F_V 0x48041057 -#define MASK_VFWCVT_XU_F_V 0xfc0ff07f -#define MATCH_VFWMACC_VF 0xf0005057 -#define MASK_VFWMACC_VF 0xfc00707f -#define MATCH_VFWMACC_VV 0xf0001057 -#define MASK_VFWMACC_VV 0xfc00707f -#define MATCH_VFWMSAC_VF 0xf8005057 -#define MASK_VFWMSAC_VF 0xfc00707f -#define MATCH_VFWMSAC_VV 0xf8001057 -#define MASK_VFWMSAC_VV 0xfc00707f -#define MATCH_VFWMUL_VF 0xe0005057 -#define MASK_VFWMUL_VF 0xfc00707f -#define MATCH_VFWMUL_VV 0xe0001057 -#define MASK_VFWMUL_VV 0xfc00707f -#define MATCH_VFWNMACC_VF 0xf4005057 -#define MASK_VFWNMACC_VF 0xfc00707f -#define MATCH_VFWNMACC_VV 0xf4001057 -#define MASK_VFWNMACC_VV 0xfc00707f -#define MATCH_VFWNMSAC_VF 0xfc005057 -#define MASK_VFWNMSAC_VF 0xfc00707f -#define MATCH_VFWNMSAC_VV 0xfc001057 -#define MASK_VFWNMSAC_VV 0xfc00707f -#define MATCH_VFWREDOSUM_VS 0xcc001057 -#define MASK_VFWREDOSUM_VS 0xfc00707f -#define MATCH_VFWREDUSUM_VS 0xc4001057 -#define MASK_VFWREDUSUM_VS 0xfc00707f -#define MATCH_VFWSUB_VF 0xc8005057 -#define MASK_VFWSUB_VF 0xfc00707f -#define MATCH_VFWSUB_VV 0xc8001057 -#define MASK_VFWSUB_VV 0xfc00707f -#define MATCH_VFWSUB_WF 0xd8005057 -#define MASK_VFWSUB_WF 0xfc00707f -#define MATCH_VFWSUB_WV 0xd8001057 -#define MASK_VFWSUB_WV 0xfc00707f -#define MATCH_VID_V 0x5008a057 -#define MASK_VID_V 0xfdfff07f -#define MATCH_VIOTA_M 0x50082057 -#define MASK_VIOTA_M 0xfc0ff07f -#define MATCH_VL1RE16_V 0x2805007 -#define MASK_VL1RE16_V 0xfff0707f -#define MATCH_VL1RE32_V 0x2806007 -#define MASK_VL1RE32_V 0xfff0707f -#define MATCH_VL1RE64_V 0x2807007 -#define MASK_VL1RE64_V 0xfff0707f -#define MATCH_VL1RE8_V 0x2800007 -#define MASK_VL1RE8_V 0xfff0707f -#define MATCH_VL2RE16_V 0x22805007 -#define MASK_VL2RE16_V 0xfff0707f -#define MATCH_VL2RE32_V 0x22806007 -#define MASK_VL2RE32_V 0xfff0707f -#define MATCH_VL2RE64_V 0x22807007 -#define MASK_VL2RE64_V 0xfff0707f -#define MATCH_VL2RE8_V 0x22800007 -#define MASK_VL2RE8_V 0xfff0707f -#define MATCH_VL4RE16_V 0x62805007 -#define MASK_VL4RE16_V 0xfff0707f -#define MATCH_VL4RE32_V 0x62806007 -#define MASK_VL4RE32_V 0xfff0707f -#define MATCH_VL4RE64_V 0x62807007 -#define MASK_VL4RE64_V 0xfff0707f -#define MATCH_VL4RE8_V 0x62800007 -#define MASK_VL4RE8_V 0xfff0707f -#define MATCH_VL8RE16_V 0xe2805007 -#define MASK_VL8RE16_V 0xfff0707f -#define MATCH_VL8RE32_V 0xe2806007 -#define MASK_VL8RE32_V 0xfff0707f -#define MATCH_VL8RE64_V 0xe2807007 -#define MASK_VL8RE64_V 0xfff0707f -#define MATCH_VL8RE8_V 0xe2800007 -#define MASK_VL8RE8_V 0xfff0707f -#define MATCH_VLE1024_V 0x10007007 -#define MASK_VLE1024_V 0x1df0707f -#define MATCH_VLE1024FF_V 0x11007007 -#define MASK_VLE1024FF_V 0x1df0707f -#define MATCH_VLE128_V 0x10000007 -#define MASK_VLE128_V 0x1df0707f -#define MATCH_VLE128FF_V 0x11000007 -#define MASK_VLE128FF_V 0x1df0707f -#define MATCH_VLE16_V 0x5007 -#define MASK_VLE16_V 0x1df0707f -#define MATCH_VLE16FF_V 0x1005007 -#define MASK_VLE16FF_V 0x1df0707f -#define MATCH_VLE256_V 0x10005007 -#define MASK_VLE256_V 0x1df0707f -#define MATCH_VLE256FF_V 0x11005007 -#define MASK_VLE256FF_V 0x1df0707f -#define MATCH_VLE32_V 0x6007 -#define MASK_VLE32_V 0x1df0707f -#define MATCH_VLE32FF_V 0x1006007 -#define MASK_VLE32FF_V 0x1df0707f -#define MATCH_VLE512_V 0x10006007 -#define MASK_VLE512_V 0x1df0707f -#define MATCH_VLE512FF_V 0x11006007 -#define MASK_VLE512FF_V 0x1df0707f -#define MATCH_VLE64_V 0x7007 -#define MASK_VLE64_V 0x1df0707f -#define MATCH_VLE64FF_V 0x1007007 -#define MASK_VLE64FF_V 0x1df0707f -#define MATCH_VLE8_V 0x7 -#define MASK_VLE8_V 0x1df0707f -#define MATCH_VLE8FF_V 0x1000007 -#define MASK_VLE8FF_V 0x1df0707f -#define MATCH_VLM_V 0x2b00007 -#define MASK_VLM_V 0xfff0707f -#define MATCH_VLOXEI1024_V 0x1c007007 -#define MASK_VLOXEI1024_V 0x1c00707f -#define MATCH_VLOXEI128_V 0x1c000007 -#define MASK_VLOXEI128_V 0x1c00707f -#define MATCH_VLOXEI16_V 0xc005007 -#define MASK_VLOXEI16_V 0x1c00707f -#define MATCH_VLOXEI256_V 0x1c005007 -#define MASK_VLOXEI256_V 0x1c00707f -#define MATCH_VLOXEI32_V 0xc006007 -#define MASK_VLOXEI32_V 0x1c00707f -#define MATCH_VLOXEI512_V 0x1c006007 -#define MASK_VLOXEI512_V 0x1c00707f -#define MATCH_VLOXEI64_V 0xc007007 -#define MASK_VLOXEI64_V 0x1c00707f -#define MATCH_VLOXEI8_V 0xc000007 -#define MASK_VLOXEI8_V 0x1c00707f -#define MATCH_VLSE1024_V 0x18007007 -#define MASK_VLSE1024_V 0x1c00707f -#define MATCH_VLSE128_V 0x18000007 -#define MASK_VLSE128_V 0x1c00707f -#define MATCH_VLSE16_V 0x8005007 -#define MASK_VLSE16_V 0x1c00707f -#define MATCH_VLSE256_V 0x18005007 -#define MASK_VLSE256_V 0x1c00707f -#define MATCH_VLSE32_V 0x8006007 -#define MASK_VLSE32_V 0x1c00707f -#define MATCH_VLSE512_V 0x18006007 -#define MASK_VLSE512_V 0x1c00707f -#define MATCH_VLSE64_V 0x8007007 -#define MASK_VLSE64_V 0x1c00707f -#define MATCH_VLSE8_V 0x8000007 -#define MASK_VLSE8_V 0x1c00707f -#define MATCH_VLUXEI1024_V 0x14007007 -#define MASK_VLUXEI1024_V 0x1c00707f -#define MATCH_VLUXEI128_V 0x14000007 -#define MASK_VLUXEI128_V 0x1c00707f -#define MATCH_VLUXEI16_V 0x4005007 -#define MASK_VLUXEI16_V 0x1c00707f -#define MATCH_VLUXEI256_V 0x14005007 -#define MASK_VLUXEI256_V 0x1c00707f -#define MATCH_VLUXEI32_V 0x4006007 -#define MASK_VLUXEI32_V 0x1c00707f -#define MATCH_VLUXEI512_V 0x14006007 -#define MASK_VLUXEI512_V 0x1c00707f -#define MATCH_VLUXEI64_V 0x4007007 -#define MASK_VLUXEI64_V 0x1c00707f -#define MATCH_VLUXEI8_V 0x4000007 -#define MASK_VLUXEI8_V 0x1c00707f -#define MATCH_VMACC_VV 0xb4002057 -#define MASK_VMACC_VV 0xfc00707f -#define MATCH_VMACC_VX 0xb4006057 -#define MASK_VMACC_VX 0xfc00707f -#define MATCH_VMADC_VI 0x46003057 -#define MASK_VMADC_VI 0xfe00707f -#define MATCH_VMADC_VIM 0x44003057 -#define MASK_VMADC_VIM 0xfe00707f -#define MATCH_VMADC_VV 0x46000057 -#define MASK_VMADC_VV 0xfe00707f -#define MATCH_VMADC_VVM 0x44000057 -#define MASK_VMADC_VVM 0xfe00707f -#define MATCH_VMADC_VX 0x46004057 -#define MASK_VMADC_VX 0xfe00707f -#define MATCH_VMADC_VXM 0x44004057 -#define MASK_VMADC_VXM 0xfe00707f -#define MATCH_VMADD_VV 0xa4002057 -#define MASK_VMADD_VV 0xfc00707f -#define MATCH_VMADD_VX 0xa4006057 -#define MASK_VMADD_VX 0xfc00707f -#define MATCH_VMAND_MM 0x64002057 -#define MASK_VMAND_MM 0xfc00707f -#define MATCH_VMANDN_MM 0x60002057 -#define MASK_VMANDN_MM 0xfc00707f -#define MATCH_VMAX_VV 0x1c000057 -#define MASK_VMAX_VV 0xfc00707f -#define MATCH_VMAX_VX 0x1c004057 -#define MASK_VMAX_VX 0xfc00707f -#define MATCH_VMAXU_VV 0x18000057 -#define MASK_VMAXU_VV 0xfc00707f -#define MATCH_VMAXU_VX 0x18004057 -#define MASK_VMAXU_VX 0xfc00707f -#define MATCH_VMERGE_VIM 0x5c003057 -#define MASK_VMERGE_VIM 0xfe00707f -#define MATCH_VMERGE_VVM 0x5c000057 -#define MASK_VMERGE_VVM 0xfe00707f -#define MATCH_VMERGE_VXM 0x5c004057 -#define MASK_VMERGE_VXM 0xfe00707f -#define MATCH_VMFEQ_VF 0x60005057 -#define MASK_VMFEQ_VF 0xfc00707f -#define MATCH_VMFEQ_VV 0x60001057 -#define MASK_VMFEQ_VV 0xfc00707f -#define MATCH_VMFGE_VF 0x7c005057 -#define MASK_VMFGE_VF 0xfc00707f -#define MATCH_VMFGT_VF 0x74005057 -#define MASK_VMFGT_VF 0xfc00707f -#define MATCH_VMFLE_VF 0x64005057 -#define MASK_VMFLE_VF 0xfc00707f -#define MATCH_VMFLE_VV 0x64001057 -#define MASK_VMFLE_VV 0xfc00707f -#define MATCH_VMFLT_VF 0x6c005057 -#define MASK_VMFLT_VF 0xfc00707f -#define MATCH_VMFLT_VV 0x6c001057 -#define MASK_VMFLT_VV 0xfc00707f -#define MATCH_VMFNE_VF 0x70005057 -#define MASK_VMFNE_VF 0xfc00707f -#define MATCH_VMFNE_VV 0x70001057 -#define MASK_VMFNE_VV 0xfc00707f -#define MATCH_VMIN_VV 0x14000057 -#define MASK_VMIN_VV 0xfc00707f -#define MATCH_VMIN_VX 0x14004057 -#define MASK_VMIN_VX 0xfc00707f -#define MATCH_VMINU_VV 0x10000057 -#define MASK_VMINU_VV 0xfc00707f -#define MATCH_VMINU_VX 0x10004057 -#define MASK_VMINU_VX 0xfc00707f -#define MATCH_VMNAND_MM 0x74002057 -#define MASK_VMNAND_MM 0xfc00707f -#define MATCH_VMNOR_MM 0x78002057 -#define MASK_VMNOR_MM 0xfc00707f -#define MATCH_VMOR_MM 0x68002057 -#define MASK_VMOR_MM 0xfc00707f -#define MATCH_VMORN_MM 0x70002057 -#define MASK_VMORN_MM 0xfc00707f -#define MATCH_VMSBC_VV 0x4e000057 -#define MASK_VMSBC_VV 0xfe00707f -#define MATCH_VMSBC_VVM 0x4c000057 -#define MASK_VMSBC_VVM 0xfe00707f -#define MATCH_VMSBC_VX 0x4e004057 -#define MASK_VMSBC_VX 0xfe00707f -#define MATCH_VMSBC_VXM 0x4c004057 -#define MASK_VMSBC_VXM 0xfe00707f -#define MATCH_VMSBF_M 0x5000a057 -#define MASK_VMSBF_M 0xfc0ff07f -#define MATCH_VMSEQ_VI 0x60003057 -#define MASK_VMSEQ_VI 0xfc00707f -#define MATCH_VMSEQ_VV 0x60000057 -#define MASK_VMSEQ_VV 0xfc00707f -#define MATCH_VMSEQ_VX 0x60004057 -#define MASK_VMSEQ_VX 0xfc00707f -#define MATCH_VMSGT_VI 0x7c003057 -#define MASK_VMSGT_VI 0xfc00707f -#define MATCH_VMSGT_VX 0x7c004057 -#define MASK_VMSGT_VX 0xfc00707f -#define MATCH_VMSGTU_VI 0x78003057 -#define MASK_VMSGTU_VI 0xfc00707f -#define MATCH_VMSGTU_VX 0x78004057 -#define MASK_VMSGTU_VX 0xfc00707f -#define MATCH_VMSIF_M 0x5001a057 -#define MASK_VMSIF_M 0xfc0ff07f -#define MATCH_VMSLE_VI 0x74003057 -#define MASK_VMSLE_VI 0xfc00707f -#define MATCH_VMSLE_VV 0x74000057 -#define MASK_VMSLE_VV 0xfc00707f -#define MATCH_VMSLE_VX 0x74004057 -#define MASK_VMSLE_VX 0xfc00707f -#define MATCH_VMSLEU_VI 0x70003057 -#define MASK_VMSLEU_VI 0xfc00707f -#define MATCH_VMSLEU_VV 0x70000057 -#define MASK_VMSLEU_VV 0xfc00707f -#define MATCH_VMSLEU_VX 0x70004057 -#define MASK_VMSLEU_VX 0xfc00707f -#define MATCH_VMSLT_VV 0x6c000057 -#define MASK_VMSLT_VV 0xfc00707f -#define MATCH_VMSLT_VX 0x6c004057 -#define MASK_VMSLT_VX 0xfc00707f -#define MATCH_VMSLTU_VV 0x68000057 -#define MASK_VMSLTU_VV 0xfc00707f -#define MATCH_VMSLTU_VX 0x68004057 -#define MASK_VMSLTU_VX 0xfc00707f -#define MATCH_VMSNE_VI 0x64003057 -#define MASK_VMSNE_VI 0xfc00707f -#define MATCH_VMSNE_VV 0x64000057 -#define MASK_VMSNE_VV 0xfc00707f -#define MATCH_VMSNE_VX 0x64004057 -#define MASK_VMSNE_VX 0xfc00707f -#define MATCH_VMSOF_M 0x50012057 -#define MASK_VMSOF_M 0xfc0ff07f -#define MATCH_VMUL_VV 0x94002057 -#define MASK_VMUL_VV 0xfc00707f -#define MATCH_VMUL_VX 0x94006057 -#define MASK_VMUL_VX 0xfc00707f -#define MATCH_VMULH_VV 0x9c002057 -#define MASK_VMULH_VV 0xfc00707f -#define MATCH_VMULH_VX 0x9c006057 -#define MASK_VMULH_VX 0xfc00707f -#define MATCH_VMULHSU_VV 0x98002057 -#define MASK_VMULHSU_VV 0xfc00707f -#define MATCH_VMULHSU_VX 0x98006057 -#define MASK_VMULHSU_VX 0xfc00707f -#define MATCH_VMULHU_VV 0x90002057 -#define MASK_VMULHU_VV 0xfc00707f -#define MATCH_VMULHU_VX 0x90006057 -#define MASK_VMULHU_VX 0xfc00707f -#define MATCH_VMV1R_V 0x9e003057 -#define MASK_VMV1R_V 0xfe0ff07f -#define MATCH_VMV2R_V 0x9e00b057 -#define MASK_VMV2R_V 0xfe0ff07f -#define MATCH_VMV4R_V 0x9e01b057 -#define MASK_VMV4R_V 0xfe0ff07f -#define MATCH_VMV8R_V 0x9e03b057 -#define MASK_VMV8R_V 0xfe0ff07f -#define MATCH_VMV_S_X 0x42006057 -#define MASK_VMV_S_X 0xfff0707f -#define MATCH_VMV_V_I 0x5e003057 -#define MASK_VMV_V_I 0xfff0707f -#define MATCH_VMV_V_V 0x5e000057 -#define MASK_VMV_V_V 0xfff0707f -#define MATCH_VMV_V_X 0x5e004057 -#define MASK_VMV_V_X 0xfff0707f -#define MATCH_VMV_X_S 0x42002057 -#define MASK_VMV_X_S 0xfe0ff07f -#define MATCH_VMXNOR_MM 0x7c002057 -#define MASK_VMXNOR_MM 0xfc00707f -#define MATCH_VMXOR_MM 0x6c002057 -#define MASK_VMXOR_MM 0xfc00707f -#define MATCH_VNCLIP_WI 0xbc003057 -#define MASK_VNCLIP_WI 0xfc00707f -#define MATCH_VNCLIP_WV 0xbc000057 -#define MASK_VNCLIP_WV 0xfc00707f -#define MATCH_VNCLIP_WX 0xbc004057 -#define MASK_VNCLIP_WX 0xfc00707f -#define MATCH_VNCLIPU_WI 0xb8003057 -#define MASK_VNCLIPU_WI 0xfc00707f -#define MATCH_VNCLIPU_WV 0xb8000057 -#define MASK_VNCLIPU_WV 0xfc00707f -#define MATCH_VNCLIPU_WX 0xb8004057 -#define MASK_VNCLIPU_WX 0xfc00707f -#define MATCH_VNMSAC_VV 0xbc002057 -#define MASK_VNMSAC_VV 0xfc00707f -#define MATCH_VNMSAC_VX 0xbc006057 -#define MASK_VNMSAC_VX 0xfc00707f -#define MATCH_VNMSUB_VV 0xac002057 -#define MASK_VNMSUB_VV 0xfc00707f -#define MATCH_VNMSUB_VX 0xac006057 -#define MASK_VNMSUB_VX 0xfc00707f -#define MATCH_VNSRA_WI 0xb4003057 -#define MASK_VNSRA_WI 0xfc00707f -#define MATCH_VNSRA_WV 0xb4000057 -#define MASK_VNSRA_WV 0xfc00707f -#define MATCH_VNSRA_WX 0xb4004057 -#define MASK_VNSRA_WX 0xfc00707f -#define MATCH_VNSRL_WI 0xb0003057 -#define MASK_VNSRL_WI 0xfc00707f -#define MATCH_VNSRL_WV 0xb0000057 -#define MASK_VNSRL_WV 0xfc00707f -#define MATCH_VNSRL_WX 0xb0004057 -#define MASK_VNSRL_WX 0xfc00707f -#define MATCH_VOR_VI 0x28003057 -#define MASK_VOR_VI 0xfc00707f -#define MATCH_VOR_VV 0x28000057 -#define MASK_VOR_VV 0xfc00707f -#define MATCH_VOR_VX 0x28004057 -#define MASK_VOR_VX 0xfc00707f -#define MATCH_VREDAND_VS 0x4002057 -#define MASK_VREDAND_VS 0xfc00707f -#define MATCH_VREDMAX_VS 0x1c002057 -#define MASK_VREDMAX_VS 0xfc00707f -#define MATCH_VREDMAXU_VS 0x18002057 -#define MASK_VREDMAXU_VS 0xfc00707f -#define MATCH_VREDMIN_VS 0x14002057 -#define MASK_VREDMIN_VS 0xfc00707f -#define MATCH_VREDMINU_VS 0x10002057 -#define MASK_VREDMINU_VS 0xfc00707f -#define MATCH_VREDOR_VS 0x8002057 -#define MASK_VREDOR_VS 0xfc00707f -#define MATCH_VREDSUM_VS 0x2057 -#define MASK_VREDSUM_VS 0xfc00707f -#define MATCH_VREDXOR_VS 0xc002057 -#define MASK_VREDXOR_VS 0xfc00707f -#define MATCH_VREM_VV 0x8c002057 -#define MASK_VREM_VV 0xfc00707f -#define MATCH_VREM_VX 0x8c006057 -#define MASK_VREM_VX 0xfc00707f -#define MATCH_VREMU_VV 0x88002057 -#define MASK_VREMU_VV 0xfc00707f -#define MATCH_VREMU_VX 0x88006057 -#define MASK_VREMU_VX 0xfc00707f -#define MATCH_VRGATHER_VI 0x30003057 -#define MASK_VRGATHER_VI 0xfc00707f -#define MATCH_VRGATHER_VV 0x30000057 -#define MASK_VRGATHER_VV 0xfc00707f -#define MATCH_VRGATHER_VX 0x30004057 -#define MASK_VRGATHER_VX 0xfc00707f -#define MATCH_VRGATHEREI16_VV 0x38000057 -#define MASK_VRGATHEREI16_VV 0xfc00707f -#define MATCH_VRSUB_VI 0xc003057 -#define MASK_VRSUB_VI 0xfc00707f -#define MATCH_VRSUB_VX 0xc004057 -#define MASK_VRSUB_VX 0xfc00707f -#define MATCH_VS1R_V 0x2800027 -#define MASK_VS1R_V 0xfff0707f -#define MATCH_VS2R_V 0x22800027 -#define MASK_VS2R_V 0xfff0707f -#define MATCH_VS4R_V 0x62800027 -#define MASK_VS4R_V 0xfff0707f -#define MATCH_VS8R_V 0xe2800027 -#define MASK_VS8R_V 0xfff0707f -#define MATCH_VSADD_VI 0x84003057 -#define MASK_VSADD_VI 0xfc00707f -#define MATCH_VSADD_VV 0x84000057 -#define MASK_VSADD_VV 0xfc00707f -#define MATCH_VSADD_VX 0x84004057 -#define MASK_VSADD_VX 0xfc00707f -#define MATCH_VSADDU_VI 0x80003057 -#define MASK_VSADDU_VI 0xfc00707f -#define MATCH_VSADDU_VV 0x80000057 -#define MASK_VSADDU_VV 0xfc00707f -#define MATCH_VSADDU_VX 0x80004057 -#define MASK_VSADDU_VX 0xfc00707f -#define MATCH_VSBC_VVM 0x48000057 -#define MASK_VSBC_VVM 0xfe00707f -#define MATCH_VSBC_VXM 0x48004057 -#define MASK_VSBC_VXM 0xfe00707f -#define MATCH_VSE1024_V 0x10007027 -#define MASK_VSE1024_V 0x1df0707f -#define MATCH_VSE128_V 0x10000027 -#define MASK_VSE128_V 0x1df0707f -#define MATCH_VSE16_V 0x5027 -#define MASK_VSE16_V 0x1df0707f -#define MATCH_VSE256_V 0x10005027 -#define MASK_VSE256_V 0x1df0707f -#define MATCH_VSE32_V 0x6027 -#define MASK_VSE32_V 0x1df0707f -#define MATCH_VSE512_V 0x10006027 -#define MASK_VSE512_V 0x1df0707f -#define MATCH_VSE64_V 0x7027 -#define MASK_VSE64_V 0x1df0707f -#define MATCH_VSE8_V 0x27 -#define MASK_VSE8_V 0x1df0707f -#define MATCH_VSETIVLI 0xc0007057 -#define MASK_VSETIVLI 0xc000707f -#define MATCH_VSETVL 0x80007057 -#define MASK_VSETVL 0xfe00707f -#define MATCH_VSETVLI 0x7057 -#define MASK_VSETVLI 0x8000707f -#define MATCH_VSEXT_VF2 0x4803a057 -#define MASK_VSEXT_VF2 0xfc0ff07f -#define MATCH_VSEXT_VF4 0x4802a057 -#define MASK_VSEXT_VF4 0xfc0ff07f -#define MATCH_VSEXT_VF8 0x4801a057 -#define MASK_VSEXT_VF8 0xfc0ff07f -#define MATCH_VSLIDE1DOWN_VX 0x3c006057 -#define MASK_VSLIDE1DOWN_VX 0xfc00707f -#define MATCH_VSLIDE1UP_VX 0x38006057 -#define MASK_VSLIDE1UP_VX 0xfc00707f -#define MATCH_VSLIDEDOWN_VI 0x3c003057 -#define MASK_VSLIDEDOWN_VI 0xfc00707f -#define MATCH_VSLIDEDOWN_VX 0x3c004057 -#define MASK_VSLIDEDOWN_VX 0xfc00707f -#define MATCH_VSLIDEUP_VI 0x38003057 -#define MASK_VSLIDEUP_VI 0xfc00707f -#define MATCH_VSLIDEUP_VX 0x38004057 -#define MASK_VSLIDEUP_VX 0xfc00707f -#define MATCH_VSLL_VI 0x94003057 -#define MASK_VSLL_VI 0xfc00707f -#define MATCH_VSLL_VV 0x94000057 -#define MASK_VSLL_VV 0xfc00707f -#define MATCH_VSLL_VX 0x94004057 -#define MASK_VSLL_VX 0xfc00707f -#define MATCH_VSM_V 0x2b00027 -#define MASK_VSM_V 0xfff0707f -#define MATCH_VSMUL_VV 0x9c000057 -#define MASK_VSMUL_VV 0xfc00707f -#define MATCH_VSMUL_VX 0x9c004057 -#define MASK_VSMUL_VX 0xfc00707f -#define MATCH_VSOXEI1024_V 0x1c007027 -#define MASK_VSOXEI1024_V 0x1c00707f -#define MATCH_VSOXEI128_V 0x1c000027 -#define MASK_VSOXEI128_V 0x1c00707f -#define MATCH_VSOXEI16_V 0xc005027 -#define MASK_VSOXEI16_V 0x1c00707f -#define MATCH_VSOXEI256_V 0x1c005027 -#define MASK_VSOXEI256_V 0x1c00707f -#define MATCH_VSOXEI32_V 0xc006027 -#define MASK_VSOXEI32_V 0x1c00707f -#define MATCH_VSOXEI512_V 0x1c006027 -#define MASK_VSOXEI512_V 0x1c00707f -#define MATCH_VSOXEI64_V 0xc007027 -#define MASK_VSOXEI64_V 0x1c00707f -#define MATCH_VSOXEI8_V 0xc000027 -#define MASK_VSOXEI8_V 0x1c00707f -#define MATCH_VSRA_VI 0xa4003057 -#define MASK_VSRA_VI 0xfc00707f -#define MATCH_VSRA_VV 0xa4000057 -#define MASK_VSRA_VV 0xfc00707f -#define MATCH_VSRA_VX 0xa4004057 -#define MASK_VSRA_VX 0xfc00707f -#define MATCH_VSRL_VI 0xa0003057 -#define MASK_VSRL_VI 0xfc00707f -#define MATCH_VSRL_VV 0xa0000057 -#define MASK_VSRL_VV 0xfc00707f -#define MATCH_VSRL_VX 0xa0004057 -#define MASK_VSRL_VX 0xfc00707f -#define MATCH_VSSE1024_V 0x18007027 -#define MASK_VSSE1024_V 0x1c00707f -#define MATCH_VSSE128_V 0x18000027 -#define MASK_VSSE128_V 0x1c00707f -#define MATCH_VSSE16_V 0x8005027 -#define MASK_VSSE16_V 0x1c00707f -#define MATCH_VSSE256_V 0x18005027 -#define MASK_VSSE256_V 0x1c00707f -#define MATCH_VSSE32_V 0x8006027 -#define MASK_VSSE32_V 0x1c00707f -#define MATCH_VSSE512_V 0x18006027 -#define MASK_VSSE512_V 0x1c00707f -#define MATCH_VSSE64_V 0x8007027 -#define MASK_VSSE64_V 0x1c00707f -#define MATCH_VSSE8_V 0x8000027 -#define MASK_VSSE8_V 0x1c00707f -#define MATCH_VSSRA_VI 0xac003057 -#define MASK_VSSRA_VI 0xfc00707f -#define MATCH_VSSRA_VV 0xac000057 -#define MASK_VSSRA_VV 0xfc00707f -#define MATCH_VSSRA_VX 0xac004057 -#define MASK_VSSRA_VX 0xfc00707f -#define MATCH_VSSRL_VI 0xa8003057 -#define MASK_VSSRL_VI 0xfc00707f -#define MATCH_VSSRL_VV 0xa8000057 -#define MASK_VSSRL_VV 0xfc00707f -#define MATCH_VSSRL_VX 0xa8004057 -#define MASK_VSSRL_VX 0xfc00707f -#define MATCH_VSSUB_VV 0x8c000057 -#define MASK_VSSUB_VV 0xfc00707f -#define MATCH_VSSUB_VX 0x8c004057 -#define MASK_VSSUB_VX 0xfc00707f -#define MATCH_VSSUBU_VV 0x88000057 -#define MASK_VSSUBU_VV 0xfc00707f -#define MATCH_VSSUBU_VX 0x88004057 -#define MASK_VSSUBU_VX 0xfc00707f -#define MATCH_VSUB_VV 0x8000057 -#define MASK_VSUB_VV 0xfc00707f -#define MATCH_VSUB_VX 0x8004057 -#define MASK_VSUB_VX 0xfc00707f -#define MATCH_VSUXEI1024_V 0x14007027 -#define MASK_VSUXEI1024_V 0x1c00707f -#define MATCH_VSUXEI128_V 0x14000027 -#define MASK_VSUXEI128_V 0x1c00707f -#define MATCH_VSUXEI16_V 0x4005027 -#define MASK_VSUXEI16_V 0x1c00707f -#define MATCH_VSUXEI256_V 0x14005027 -#define MASK_VSUXEI256_V 0x1c00707f -#define MATCH_VSUXEI32_V 0x4006027 -#define MASK_VSUXEI32_V 0x1c00707f -#define MATCH_VSUXEI512_V 0x14006027 -#define MASK_VSUXEI512_V 0x1c00707f -#define MATCH_VSUXEI64_V 0x4007027 -#define MASK_VSUXEI64_V 0x1c00707f -#define MATCH_VSUXEI8_V 0x4000027 -#define MASK_VSUXEI8_V 0x1c00707f -#define MATCH_VWADD_VV 0xc4002057 -#define MASK_VWADD_VV 0xfc00707f -#define MATCH_VWADD_VX 0xc4006057 -#define MASK_VWADD_VX 0xfc00707f -#define MATCH_VWADD_WV 0xd4002057 -#define MASK_VWADD_WV 0xfc00707f -#define MATCH_VWADD_WX 0xd4006057 -#define MASK_VWADD_WX 0xfc00707f -#define MATCH_VWADDU_VV 0xc0002057 -#define MASK_VWADDU_VV 0xfc00707f -#define MATCH_VWADDU_VX 0xc0006057 -#define MASK_VWADDU_VX 0xfc00707f -#define MATCH_VWADDU_WV 0xd0002057 -#define MASK_VWADDU_WV 0xfc00707f -#define MATCH_VWADDU_WX 0xd0006057 -#define MASK_VWADDU_WX 0xfc00707f -#define MATCH_VWMACC_VV 0xf4002057 -#define MASK_VWMACC_VV 0xfc00707f -#define MATCH_VWMACC_VX 0xf4006057 -#define MASK_VWMACC_VX 0xfc00707f -#define MATCH_VWMACCSU_VV 0xfc002057 -#define MASK_VWMACCSU_VV 0xfc00707f -#define MATCH_VWMACCSU_VX 0xfc006057 -#define MASK_VWMACCSU_VX 0xfc00707f -#define MATCH_VWMACCU_VV 0xf0002057 -#define MASK_VWMACCU_VV 0xfc00707f -#define MATCH_VWMACCU_VX 0xf0006057 -#define MASK_VWMACCU_VX 0xfc00707f -#define MATCH_VWMACCUS_VX 0xf8006057 -#define MASK_VWMACCUS_VX 0xfc00707f -#define MATCH_VWMUL_VV 0xec002057 -#define MASK_VWMUL_VV 0xfc00707f -#define MATCH_VWMUL_VX 0xec006057 -#define MASK_VWMUL_VX 0xfc00707f -#define MATCH_VWMULSU_VV 0xe8002057 -#define MASK_VWMULSU_VV 0xfc00707f -#define MATCH_VWMULSU_VX 0xe8006057 -#define MASK_VWMULSU_VX 0xfc00707f -#define MATCH_VWMULU_VV 0xe0002057 -#define MASK_VWMULU_VV 0xfc00707f -#define MATCH_VWMULU_VX 0xe0006057 -#define MASK_VWMULU_VX 0xfc00707f -#define MATCH_VWREDSUM_VS 0xc4000057 -#define MASK_VWREDSUM_VS 0xfc00707f -#define MATCH_VWREDSUMU_VS 0xc0000057 -#define MASK_VWREDSUMU_VS 0xfc00707f -#define MATCH_VWSUB_VV 0xcc002057 -#define MASK_VWSUB_VV 0xfc00707f -#define MATCH_VWSUB_VX 0xcc006057 -#define MASK_VWSUB_VX 0xfc00707f -#define MATCH_VWSUB_WV 0xdc002057 -#define MASK_VWSUB_WV 0xfc00707f -#define MATCH_VWSUB_WX 0xdc006057 -#define MASK_VWSUB_WX 0xfc00707f -#define MATCH_VWSUBU_VV 0xc8002057 -#define MASK_VWSUBU_VV 0xfc00707f -#define MATCH_VWSUBU_VX 0xc8006057 -#define MASK_VWSUBU_VX 0xfc00707f -#define MATCH_VWSUBU_WV 0xd8002057 -#define MASK_VWSUBU_WV 0xfc00707f -#define MATCH_VWSUBU_WX 0xd8006057 -#define MASK_VWSUBU_WX 0xfc00707f -#define MATCH_VXOR_VI 0x2c003057 -#define MASK_VXOR_VI 0xfc00707f -#define MATCH_VXOR_VV 0x2c000057 -#define MASK_VXOR_VV 0xfc00707f -#define MATCH_VXOR_VX 0x2c004057 -#define MASK_VXOR_VX 0xfc00707f -#define MATCH_VZEXT_VF2 0x48032057 -#define MASK_VZEXT_VF2 0xfc0ff07f -#define MATCH_VZEXT_VF4 0x48022057 -#define MASK_VZEXT_VF4 0xfc0ff07f -#define MATCH_VZEXT_VF8 0x48012057 -#define MASK_VZEXT_VF8 0xfc0ff07f -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_WRS_NTO 0xd00073 -#define MASK_WRS_NTO 0xffffffff -#define MATCH_WRS_STO 0x1d00073 -#define MASK_WRS_STO 0xffffffff -#define MATCH_XNOR 0x40004033 -#define MASK_XNOR 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_XPERM16 0x28006033 -#define MASK_XPERM16 0xfe00707f -#define MATCH_XPERM32 0x28000033 -#define MASK_XPERM32 0xfe00707f -#define MATCH_XPERM4 0x28002033 -#define MASK_XPERM4 0xfe00707f -#define MATCH_XPERM8 0x28004033 -#define MASK_XPERM8 0xfe00707f -#define MATCH_ZUNPKD810 0xacc00077 -#define MASK_ZUNPKD810 0xfff0707f -#define MATCH_ZUNPKD820 0xacd00077 -#define MASK_ZUNPKD820 0xfff0707f -#define MATCH_ZUNPKD830 0xace00077 -#define MASK_ZUNPKD830 0xfff0707f -#define MATCH_ZUNPKD831 0xacf00077 -#define MASK_ZUNPKD831 0xfff0707f -#define MATCH_ZUNPKD832 0xad700077 -#define MASK_ZUNPKD832 0xfff0707f - -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_VSTART 0x8 -#define CSR_VXSAT 0x9 -#define CSR_VXRM 0xa -#define CSR_VCSR 0xf -#define CSR_SEED 0x15 -#define CSR_JVT 0x17 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_VL 0xc20 -#define CSR_VTYPE 0xc21 -#define CSR_VLENB 0xc22 -#define CSR_SSTATUS 0x100 -#define CSR_SEDELEG 0x102 -#define CSR_SIDELEG 0x103 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SENVCFG 0x10a -#define CSR_SSTATEEN0 0x10c -#define CSR_SSTATEEN1 0x10d -#define CSR_SSTATEEN2 0x10e -#define CSR_SSTATEEN3 0x10f -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 -#define CSR_STIMECMP 0x14d -#define CSR_SISELECT 0x150 -#define CSR_SIREG 0x151 -#define CSR_STOPEI 0x15c -#define CSR_SATP 0x180 -#define CSR_SCONTEXT 0x5a8 -#define CSR_VSSTATUS 0x200 -#define CSR_VSIE 0x204 -#define CSR_VSTVEC 0x205 -#define CSR_VSSCRATCH 0x240 -#define CSR_VSEPC 0x241 -#define CSR_VSCAUSE 0x242 -#define CSR_VSTVAL 0x243 -#define CSR_VSIP 0x244 -#define CSR_VSTIMECMP 0x24d -#define CSR_VSISELECT 0x250 -#define CSR_VSIREG 0x251 -#define CSR_VSTOPEI 0x25c -#define CSR_VSATP 0x280 -#define CSR_HSTATUS 0x600 -#define CSR_HEDELEG 0x602 -#define CSR_HIDELEG 0x603 -#define CSR_HIE 0x604 -#define CSR_HTIMEDELTA 0x605 -#define CSR_HCOUNTEREN 0x606 -#define CSR_HGEIE 0x607 -#define CSR_HVIEN 0x608 -#define CSR_HVICTL 0x609 -#define CSR_HENVCFG 0x60a -#define CSR_HSTATEEN0 0x60c -#define CSR_HSTATEEN1 0x60d -#define CSR_HSTATEEN2 0x60e -#define CSR_HSTATEEN3 0x60f -#define CSR_HTVAL 0x643 -#define CSR_HIP 0x644 -#define CSR_HVIP 0x645 -#define CSR_HVIPRIO1 0x646 -#define CSR_HVIPRIO2 0x647 -#define CSR_HTINST 0x64a -#define CSR_HGATP 0x680 -#define CSR_HCONTEXT 0x6a8 -#define CSR_HGEIP 0xe12 -#define CSR_VSTOPI 0xeb0 -#define CSR_SCOUNTOVF 0xda0 -#define CSR_STOPI 0xdb0 -#define CSR_UTVT 0x7 -#define CSR_UNXTI 0x45 -#define CSR_UINTSTATUS 0x46 -#define CSR_USCRATCHCSW 0x48 -#define CSR_USCRATCHCSWL 0x49 -#define CSR_STVT 0x107 -#define CSR_SNXTI 0x145 -#define CSR_SINTSTATUS 0x146 -#define CSR_SSCRATCHCSW 0x148 -#define CSR_SSCRATCHCSWL 0x149 -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 -#define CSR_MINTSTATUS 0x346 -#define CSR_MSCRATCHCSW 0x348 -#define CSR_MSCRATCHCSWL 0x349 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MVIEN 0x308 -#define CSR_MVIP 0x309 -#define CSR_MENVCFG 0x30a -#define CSR_MSTATEEN0 0x30c -#define CSR_MSTATEEN1 0x30d -#define CSR_MSTATEEN2 0x30e -#define CSR_MSTATEEN3 0x30f -#define CSR_MCOUNTINHIBIT 0x320 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_MTINST 0x34a -#define CSR_MTVAL2 0x34b -#define CSR_MISELECT 0x350 -#define CSR_MIREG 0x351 -#define CSR_MTOPEI 0x35c -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPCFG4 0x3a4 -#define CSR_PMPCFG5 0x3a5 -#define CSR_PMPCFG6 0x3a6 -#define CSR_PMPCFG7 0x3a7 -#define CSR_PMPCFG8 0x3a8 -#define CSR_PMPCFG9 0x3a9 -#define CSR_PMPCFG10 0x3aa -#define CSR_PMPCFG11 0x3ab -#define CSR_PMPCFG12 0x3ac -#define CSR_PMPCFG13 0x3ad -#define CSR_PMPCFG14 0x3ae -#define CSR_PMPCFG15 0x3af -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_PMPADDR16 0x3c0 -#define CSR_PMPADDR17 0x3c1 -#define CSR_PMPADDR18 0x3c2 -#define CSR_PMPADDR19 0x3c3 -#define CSR_PMPADDR20 0x3c4 -#define CSR_PMPADDR21 0x3c5 -#define CSR_PMPADDR22 0x3c6 -#define CSR_PMPADDR23 0x3c7 -#define CSR_PMPADDR24 0x3c8 -#define CSR_PMPADDR25 0x3c9 -#define CSR_PMPADDR26 0x3ca -#define CSR_PMPADDR27 0x3cb -#define CSR_PMPADDR28 0x3cc -#define CSR_PMPADDR29 0x3cd -#define CSR_PMPADDR30 0x3ce -#define CSR_PMPADDR31 0x3cf -#define CSR_PMPADDR32 0x3d0 -#define CSR_PMPADDR33 0x3d1 -#define CSR_PMPADDR34 0x3d2 -#define CSR_PMPADDR35 0x3d3 -#define CSR_PMPADDR36 0x3d4 -#define CSR_PMPADDR37 0x3d5 -#define CSR_PMPADDR38 0x3d6 -#define CSR_PMPADDR39 0x3d7 -#define CSR_PMPADDR40 0x3d8 -#define CSR_PMPADDR41 0x3d9 -#define CSR_PMPADDR42 0x3da -#define CSR_PMPADDR43 0x3db -#define CSR_PMPADDR44 0x3dc -#define CSR_PMPADDR45 0x3dd -#define CSR_PMPADDR46 0x3de -#define CSR_PMPADDR47 0x3df -#define CSR_PMPADDR48 0x3e0 -#define CSR_PMPADDR49 0x3e1 -#define CSR_PMPADDR50 0x3e2 -#define CSR_PMPADDR51 0x3e3 -#define CSR_PMPADDR52 0x3e4 -#define CSR_PMPADDR53 0x3e5 -#define CSR_PMPADDR54 0x3e6 -#define CSR_PMPADDR55 0x3e7 -#define CSR_PMPADDR56 0x3e8 -#define CSR_PMPADDR57 0x3e9 -#define CSR_PMPADDR58 0x3ea -#define CSR_PMPADDR59 0x3eb -#define CSR_PMPADDR60 0x3ec -#define CSR_PMPADDR61 0x3ed -#define CSR_PMPADDR62 0x3ee -#define CSR_PMPADDR63 0x3ef -#define CSR_MSECCFG 0x747 -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_TINFO 0x7a4 -#define CSR_TCONTROL 0x7a5 -#define CSR_MCONTEXT 0x7a8 -#define CSR_MSCONTEXT 0x7aa -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH0 0x7b2 -#define CSR_DSCRATCH1 0x7b3 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_MCONFIGPTR 0xf15 -#define CSR_MTOPI 0xfb0 -#define CSR_SIEH 0x114 -#define CSR_SIPH 0x154 -#define CSR_STIMECMPH 0x15d -#define CSR_VSIEH 0x214 -#define CSR_VSIPH 0x254 -#define CSR_VSTIMECMPH 0x25d -#define CSR_HTIMEDELTAH 0x615 -#define CSR_HIDELEGH 0x613 -#define CSR_HVIENH 0x618 -#define CSR_HENVCFGH 0x61a -#define CSR_HVIPH 0x655 -#define CSR_HVIPRIO1H 0x656 -#define CSR_HVIPRIO2H 0x657 -#define CSR_HSTATEEN0H 0x61c -#define CSR_HSTATEEN1H 0x61d -#define CSR_HSTATEEN2H 0x61e -#define CSR_HSTATEEN3H 0x61f -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MSTATUSH 0x310 -#define CSR_MIDELEGH 0x313 -#define CSR_MIEH 0x314 -#define CSR_MVIENH 0x318 -#define CSR_MVIPH 0x319 -#define CSR_MENVCFGH 0x31a -#define CSR_MSTATEEN0H 0x31c -#define CSR_MSTATEEN1H 0x31d -#define CSR_MSTATEEN2H 0x31e -#define CSR_MSTATEEN3H 0x31f -#define CSR_MIPH 0x354 -#define CSR_MHPMEVENT3H 0x723 -#define CSR_MHPMEVENT4H 0x724 -#define CSR_MHPMEVENT5H 0x725 -#define CSR_MHPMEVENT6H 0x726 -#define CSR_MHPMEVENT7H 0x727 -#define CSR_MHPMEVENT8H 0x728 -#define CSR_MHPMEVENT9H 0x729 -#define CSR_MHPMEVENT10H 0x72a -#define CSR_MHPMEVENT11H 0x72b -#define CSR_MHPMEVENT12H 0x72c -#define CSR_MHPMEVENT13H 0x72d -#define CSR_MHPMEVENT14H 0x72e -#define CSR_MHPMEVENT15H 0x72f -#define CSR_MHPMEVENT16H 0x730 -#define CSR_MHPMEVENT17H 0x731 -#define CSR_MHPMEVENT18H 0x732 -#define CSR_MHPMEVENT19H 0x733 -#define CSR_MHPMEVENT20H 0x734 -#define CSR_MHPMEVENT21H 0x735 -#define CSR_MHPMEVENT22H 0x736 -#define CSR_MHPMEVENT23H 0x737 -#define CSR_MHPMEVENT24H 0x738 -#define CSR_MHPMEVENT25H 0x739 -#define CSR_MHPMEVENT26H 0x73a -#define CSR_MHPMEVENT27H 0x73b -#define CSR_MHPMEVENT28H 0x73c -#define CSR_MHPMEVENT29H 0x73d -#define CSR_MHPMEVENT30H 0x73e -#define CSR_MHPMEVENT31H 0x73f -#define CSR_MNSCRATCH 0x740 -#define CSR_MNEPC 0x741 -#define CSR_MNCAUSE 0x742 -#define CSR_MNSTATUS 0x744 -#define CSR_MSECCFGH 0x757 -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f - -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 -#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 -#define CAUSE_VIRTUAL_INSTRUCTION 0x16 -#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 - -#define INSN_FIELD_RD 0xf80 -#define INSN_FIELD_RT 0xf8000 -#define INSN_FIELD_RS1 0xf8000 -#define INSN_FIELD_RS2 0x1f00000 -#define INSN_FIELD_RS3 0xf8000000 -#define INSN_FIELD_AQRL 0x6000000 -#define INSN_FIELD_AQ 0x4000000 -#define INSN_FIELD_RL 0x2000000 -#define INSN_FIELD_FM 0xf0000000 -#define INSN_FIELD_PRED 0xf000000 -#define INSN_FIELD_SUCC 0xf00000 -#define INSN_FIELD_RM 0x7000 -#define INSN_FIELD_FUNCT3 0x7000 -#define INSN_FIELD_FUNCT2 0x6000000 -#define INSN_FIELD_IMM20 0xfffff000 -#define INSN_FIELD_JIMM20 0xfffff000 -#define INSN_FIELD_IMM12 0xfff00000 -#define INSN_FIELD_CSR 0xfff00000 -#define INSN_FIELD_IMM12HI 0xfe000000 -#define INSN_FIELD_BIMM12HI 0xfe000000 -#define INSN_FIELD_IMM12LO 0xf80 -#define INSN_FIELD_BIMM12LO 0xf80 -#define INSN_FIELD_ZIMM 0xf8000 -#define INSN_FIELD_SHAMTQ 0x7f00000 -#define INSN_FIELD_SHAMTW 0x1f00000 -#define INSN_FIELD_SHAMTW4 0xf00000 -#define INSN_FIELD_SHAMTD 0x3f00000 -#define INSN_FIELD_BS 0xc0000000 -#define INSN_FIELD_RNUM 0xf00000 -#define INSN_FIELD_RC 0x3e000000 -#define INSN_FIELD_IMM2 0x300000 -#define INSN_FIELD_IMM3 0x700000 -#define INSN_FIELD_IMM4 0xf00000 -#define INSN_FIELD_IMM5 0x1f00000 -#define INSN_FIELD_IMM6 0x3f00000 -#define INSN_FIELD_OPCODE 0x7f -#define INSN_FIELD_FUNCT7 0xfe000000 -#define INSN_FIELD_VD 0xf80 -#define INSN_FIELD_VS3 0xf80 -#define INSN_FIELD_VS1 0xf8000 -#define INSN_FIELD_VS2 0x1f00000 -#define INSN_FIELD_VM 0x2000000 -#define INSN_FIELD_WD 0x4000000 -#define INSN_FIELD_AMOOP 0xf8000000 -#define INSN_FIELD_NF 0xe0000000 -#define INSN_FIELD_SIMM5 0xf8000 -#define INSN_FIELD_ZIMM10 0x3ff00000 -#define INSN_FIELD_ZIMM11 0x7ff00000 -#define INSN_FIELD_C_NZUIMM10 0x1fe0 -#define INSN_FIELD_C_UIMM7LO 0x60 -#define INSN_FIELD_C_UIMM7HI 0x1c00 -#define INSN_FIELD_C_UIMM8LO 0x60 -#define INSN_FIELD_C_UIMM8HI 0x1c00 -#define INSN_FIELD_C_UIMM9LO 0x60 -#define INSN_FIELD_C_UIMM9HI 0x1c00 -#define INSN_FIELD_C_NZIMM6LO 0x7c -#define INSN_FIELD_C_NZIMM6HI 0x1000 -#define INSN_FIELD_C_IMM6LO 0x7c -#define INSN_FIELD_C_IMM6HI 0x1000 -#define INSN_FIELD_C_NZIMM10HI 0x1000 -#define INSN_FIELD_C_NZIMM10LO 0x7c -#define INSN_FIELD_C_NZIMM18HI 0x1000 -#define INSN_FIELD_C_NZIMM18LO 0x7c -#define INSN_FIELD_C_IMM12 0x1ffc -#define INSN_FIELD_C_BIMM9LO 0x7c -#define INSN_FIELD_C_BIMM9HI 0x1c00 -#define INSN_FIELD_C_NZUIMM5 0x7c -#define INSN_FIELD_C_NZUIMM6LO 0x7c -#define INSN_FIELD_C_NZUIMM6HI 0x1000 -#define INSN_FIELD_C_UIMM8SPLO 0x7c -#define INSN_FIELD_C_UIMM8SPHI 0x1000 -#define INSN_FIELD_C_UIMM8SP_S 0x1f80 -#define INSN_FIELD_C_UIMM10SPLO 0x7c -#define INSN_FIELD_C_UIMM10SPHI 0x1000 -#define INSN_FIELD_C_UIMM9SPLO 0x7c -#define INSN_FIELD_C_UIMM9SPHI 0x1000 -#define INSN_FIELD_C_UIMM10SP_S 0x1f80 -#define INSN_FIELD_C_UIMM9SP_S 0x1f80 -#define INSN_FIELD_C_UIMM2 0x60 -#define INSN_FIELD_C_UIMM1 0x20 -#define INSN_FIELD_C_RLIST 0xf0 -#define INSN_FIELD_C_SPIMM 0xc -#define INSN_FIELD_C_INDEX 0x3fc -#define INSN_FIELD_RS1_P 0x380 -#define INSN_FIELD_RS2_P 0x1c -#define INSN_FIELD_RD_P 0x1c -#define INSN_FIELD_RD_RS1_N0 0xf80 -#define INSN_FIELD_RD_RS1_P 0x380 -#define INSN_FIELD_RD_RS1 0xf80 -#define INSN_FIELD_RD_N2 0xf80 -#define INSN_FIELD_RD_N0 0xf80 -#define INSN_FIELD_RS1_N0 0xf80 -#define INSN_FIELD_C_RS2_N0 0x7c -#define INSN_FIELD_C_RS1_N0 0xf80 -#define INSN_FIELD_C_RS2 0x7c -#define INSN_FIELD_C_SREG1 0x380 -#define INSN_FIELD_C_SREG2 0x1c -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) -DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) -DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) -DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) -DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) -DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) -DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) -DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) -DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) -DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) -DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) -DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) -DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) -DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) -DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) -DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) -DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) -DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) -DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) -DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) -DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) -DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) -DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) -DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) -DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) -DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) -DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) -DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) -DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) -DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) -DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) -DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) -DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) -DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN) -DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH) -DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL) -DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) -DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) -DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) -DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) -DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) -DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) -DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) -DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) -DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) -DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) -DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) -DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) -DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT) -DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S) -DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01) -DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) -DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) -DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) -DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) -DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) -DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) -DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) -DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) -DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) -DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) -DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) -DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) -DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) -DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) -DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) -DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) -DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) -DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) -DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) -DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) -DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) -DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) -DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) -DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ) -DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) -DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) -DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) -DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) -DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) -DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) -DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) -DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) -DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) -DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) -DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) -DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) -DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) -DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) -DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) -DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) -DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) -DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) -DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) -DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) -DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) -DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) -DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) -DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) -DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) -DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) -DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) -DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) -DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) -DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) -DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) -DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) -DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) -DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) -DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) -DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) -DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) -DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) -DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) -DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) -DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) -DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) -DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) -DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) -DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) -DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) -DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) -DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) -DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) -DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) -DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) -DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) -DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) -DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) -DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) -DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) -DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) -DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) -DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) -DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) -DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) -DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) -DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) -DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) -DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) -DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) -DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) -DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) -DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) -DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) -DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) -DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) -DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB) -DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) -DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT) -DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) -DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) -DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) -DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) -DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) -DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) -DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) -DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) -DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) -DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) -DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) -DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) -DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) -DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) -DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) -DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) -DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) -DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) -DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) -DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) -DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) -DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) -DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) -DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) -DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) -DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) -DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) -DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) -DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) -DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) -DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) -DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) -DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) -DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) -DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) -DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) -DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) -DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) -DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) -DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) -DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) -DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) -DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) -DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) -DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) -DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) -DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) -DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) -DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) -DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) -DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) -DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) -DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) -DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) -DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) -DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) -DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) -DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) -DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) -DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) -DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) -DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) -DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) -DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) -DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) -DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) -DECLARE_INSN(max, MATCH_MAX, MASK_MAX) -DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) -DECLARE_INSN(min, MATCH_MIN, MASK_MIN) -DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) -DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) -DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) -DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) -DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) -DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) -DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) -DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) -DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) -DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) -DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) -DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) -DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) -DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) -DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) -DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) -DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) -DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) -DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) -DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) -DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) -DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) -DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) -DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) -DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) -DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) -DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) -DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) -DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) -DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) -DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) -DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) -DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) -DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) -DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) -DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) -DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) -DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) -DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) -DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) -DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) -DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) -DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) -DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) -DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) -DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) -DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) -DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) -DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) -DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) -DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) -DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) -DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) -DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) -DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) -DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) -DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) -DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) -DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) -DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) -DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) -DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) -DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) -DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) -DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) -DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) -DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) -DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) -DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) -DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) -DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) -DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) -DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) -DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) -DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) -DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) -DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) -DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) -DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) -DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) -DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) -DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) -DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) -DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) -DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) -DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) -DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) -DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) -DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) -DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) -DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) -DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) -DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) -DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) -DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) -DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) -DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) -DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) -DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) -DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) -DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) -DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) -DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) -DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) -DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) -DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) -DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) -DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) -DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) -DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) -DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) -DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) -DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U) -DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT) -DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) -DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA) -DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) -DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) -DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) -DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) -DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) -DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) -DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) -DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) -DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) -DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) -DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) -DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) -DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) -DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) -DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) -DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) -DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) -DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) -DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) -DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) -DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) -DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) -DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) -DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) -DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) -DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) -DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) -DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) -DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) -DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) -DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) -DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) -DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) -DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) -DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) -DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) -DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) -DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) -DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) -DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) -DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) -DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) -DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) -DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) -DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) -DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) -DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) -DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) -DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) -DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) -DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) -DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) -DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) -DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) -DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) -DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) -DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) -DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) -DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) -DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) -DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) -DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) -DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) -DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) -DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) -DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) -DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) -DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) -DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) -DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) -DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) -DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) -DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) -DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) -DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) -DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) -DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) -DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) -DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) -DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) -DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) -DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) -DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) -DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) -DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) -DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) -DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) -DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) -DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) -DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) -DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) -DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) -DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) -DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) -DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) -DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) -DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) -DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) -DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) -DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) -DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) -DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) -DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) -DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) -DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) -DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) -DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) -DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) -DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) -DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) -DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) -DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) -DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) -DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) -DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) -DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) -DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) -DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) -DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) -DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) -DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) -DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) -DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) -DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) -DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) -DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) -DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) -DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) -DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) -DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) -DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) -DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) -DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) -DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) -DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) -DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) -DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) -DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) -DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) -DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) -DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) -DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) -DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) -DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) -DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) -DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) -DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) -DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) -DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) -DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) -DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) -DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) -DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) -DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) -DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) -DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) -DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) -DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) -DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) -DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) -DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) -DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) -DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) -DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) -DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) -DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) -DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) -DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) -DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) -DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) -DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) -DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) -DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) -DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) -DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) -DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) -DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) -DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) -DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) -DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) -DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) -DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) -DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) -DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) -DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) -DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) -DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) -DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) -DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) -DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) -DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) -DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) -DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) -DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) -DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) -DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) -DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) -DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) -DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) -DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) -DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) -DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) -DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) -DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) -DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) -DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) -DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) -DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) -DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) -DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) -DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) -DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) -DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) -DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) -DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) -DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) -DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) -DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) -DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) -DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) -DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) -DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) -DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) -DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) -DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) -DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) -DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) -DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) -DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) -DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) -DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) -DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) -DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) -DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) -DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) -DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) -DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) -DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) -DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) -DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) -DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) -DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) -DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) -DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) -DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) -DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) -DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) -DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) -DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) -DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) -DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) -DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) -DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) -DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) -DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) -DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) -DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) -DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) -DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) -DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) -DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) -DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) -DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) -DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) -DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) -DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) -DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) -DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) -DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) -DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) -DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) -DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) -DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) -DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) -DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) -DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) -DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) -DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) -DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) -DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) -DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) -DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) -DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) -DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) -DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) -DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) -DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) -DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) -DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) -DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) -DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) -DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) -DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) -DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) -DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) -DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) -DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) -DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) -DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) -DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) -DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) -DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) -DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) -DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) -DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) -DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) -DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) -DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) -DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) -DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) -DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) -DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) -DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) -DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) -DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) -DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) -DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) -DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) -DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) -DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) -DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) -DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) -DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) -DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) -DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) -DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) -DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) -DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) -DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) -DECLARE_INSN(vmandn_mm, MATCH_VMANDN_MM, MASK_VMANDN_MM) -DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) -DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) -DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) -DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) -DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) -DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) -DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) -DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) -DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) -DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) -DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) -DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) -DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) -DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) -DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) -DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) -DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) -DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) -DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) -DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) -DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) -DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) -DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) -DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) -DECLARE_INSN(vmorn_mm, MATCH_VMORN_MM, MASK_VMORN_MM) -DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) -DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) -DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) -DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) -DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) -DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) -DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) -DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) -DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) -DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) -DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) -DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) -DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) -DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) -DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) -DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) -DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) -DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) -DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) -DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) -DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) -DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) -DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) -DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) -DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) -DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) -DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) -DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) -DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) -DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) -DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) -DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) -DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) -DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) -DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) -DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) -DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) -DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) -DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) -DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) -DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) -DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) -DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) -DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) -DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) -DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) -DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) -DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) -DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) -DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) -DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) -DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) -DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) -DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) -DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) -DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) -DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) -DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) -DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) -DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) -DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) -DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) -DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) -DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) -DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) -DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) -DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) -DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) -DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) -DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) -DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) -DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) -DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) -DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) -DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) -DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) -DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) -DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) -DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) -DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) -DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) -DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) -DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) -DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) -DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) -DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) -DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) -DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) -DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) -DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) -DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) -DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) -DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) -DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) -DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) -DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) -DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) -DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) -DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) -DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) -DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) -DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) -DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) -DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) -DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) -DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) -DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) -DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) -DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) -DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) -DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) -DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) -DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) -DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) -DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) -DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) -DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) -DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) -DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) -DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) -DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) -DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) -DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) -DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) -DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) -DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) -DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) -DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) -DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) -DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) -DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) -DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) -DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) -DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) -DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) -DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) -DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) -DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) -DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) -DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) -DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) -DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) -DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) -DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) -DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) -DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) -DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) -DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) -DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) -DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) -DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) -DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) -DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) -DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) -DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) -DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) -DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) -DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) -DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) -DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) -DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) -DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) -DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) -DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) -DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) -DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) -DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) -DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) -DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) -DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) -DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) -DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) -DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) -DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) -DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) -DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) -DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) -DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) -DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) -DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) -DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) -DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) -DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) -DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) -DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) -DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) -DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) -DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) -DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) -DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) -DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) -DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) -DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) -DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) -DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) -DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) -DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) -DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) -DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) -DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) -DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) -DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16) -DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32) -DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) -DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) -DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) -DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) -DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) -DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) -DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(vstart, CSR_VSTART) -DECLARE_CSR(vxsat, CSR_VXSAT) -DECLARE_CSR(vxrm, CSR_VXRM) -DECLARE_CSR(vcsr, CSR_VCSR) -DECLARE_CSR(seed, CSR_SEED) -DECLARE_CSR(jvt, CSR_JVT) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(vl, CSR_VL) -DECLARE_CSR(vtype, CSR_VTYPE) -DECLARE_CSR(vlenb, CSR_VLENB) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sedeleg, CSR_SEDELEG) -DECLARE_CSR(sideleg, CSR_SIDELEG) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(senvcfg, CSR_SENVCFG) -DECLARE_CSR(sstateen0, CSR_SSTATEEN0) -DECLARE_CSR(sstateen1, CSR_SSTATEEN1) -DECLARE_CSR(sstateen2, CSR_SSTATEEN2) -DECLARE_CSR(sstateen3, CSR_SSTATEEN3) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(stval, CSR_STVAL) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(stimecmp, CSR_STIMECMP) -DECLARE_CSR(siselect, CSR_SISELECT) -DECLARE_CSR(sireg, CSR_SIREG) -DECLARE_CSR(stopei, CSR_STOPEI) -DECLARE_CSR(satp, CSR_SATP) -DECLARE_CSR(scontext, CSR_SCONTEXT) -DECLARE_CSR(vsstatus, CSR_VSSTATUS) -DECLARE_CSR(vsie, CSR_VSIE) -DECLARE_CSR(vstvec, CSR_VSTVEC) -DECLARE_CSR(vsscratch, CSR_VSSCRATCH) -DECLARE_CSR(vsepc, CSR_VSEPC) -DECLARE_CSR(vscause, CSR_VSCAUSE) -DECLARE_CSR(vstval, CSR_VSTVAL) -DECLARE_CSR(vsip, CSR_VSIP) -DECLARE_CSR(vstimecmp, CSR_VSTIMECMP) -DECLARE_CSR(vsiselect, CSR_VSISELECT) -DECLARE_CSR(vsireg, CSR_VSIREG) -DECLARE_CSR(vstopei, CSR_VSTOPEI) -DECLARE_CSR(vsatp, CSR_VSATP) -DECLARE_CSR(hstatus, CSR_HSTATUS) -DECLARE_CSR(hedeleg, CSR_HEDELEG) -DECLARE_CSR(hideleg, CSR_HIDELEG) -DECLARE_CSR(hie, CSR_HIE) -DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) -DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) -DECLARE_CSR(hgeie, CSR_HGEIE) -DECLARE_CSR(hvien, CSR_HVIEN) -DECLARE_CSR(hvictl, CSR_HVICTL) -DECLARE_CSR(henvcfg, CSR_HENVCFG) -DECLARE_CSR(hstateen0, CSR_HSTATEEN0) -DECLARE_CSR(hstateen1, CSR_HSTATEEN1) -DECLARE_CSR(hstateen2, CSR_HSTATEEN2) -DECLARE_CSR(hstateen3, CSR_HSTATEEN3) -DECLARE_CSR(htval, CSR_HTVAL) -DECLARE_CSR(hip, CSR_HIP) -DECLARE_CSR(hvip, CSR_HVIP) -DECLARE_CSR(hviprio1, CSR_HVIPRIO1) -DECLARE_CSR(hviprio2, CSR_HVIPRIO2) -DECLARE_CSR(htinst, CSR_HTINST) -DECLARE_CSR(hgatp, CSR_HGATP) -DECLARE_CSR(hcontext, CSR_HCONTEXT) -DECLARE_CSR(hgeip, CSR_HGEIP) -DECLARE_CSR(vstopi, CSR_VSTOPI) -DECLARE_CSR(scountovf, CSR_SCOUNTOVF) -DECLARE_CSR(stopi, CSR_STOPI) -DECLARE_CSR(utvt, CSR_UTVT) -DECLARE_CSR(unxti, CSR_UNXTI) -DECLARE_CSR(uintstatus, CSR_UINTSTATUS) -DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) -DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) -DECLARE_CSR(stvt, CSR_STVT) -DECLARE_CSR(snxti, CSR_SNXTI) -DECLARE_CSR(sintstatus, CSR_SINTSTATUS) -DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) -DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) -DECLARE_CSR(mtvt, CSR_MTVT) -DECLARE_CSR(mnxti, CSR_MNXTI) -DECLARE_CSR(mintstatus, CSR_MINTSTATUS) -DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) -DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mvien, CSR_MVIEN) -DECLARE_CSR(mvip, CSR_MVIP) -DECLARE_CSR(menvcfg, CSR_MENVCFG) -DECLARE_CSR(mstateen0, CSR_MSTATEEN0) -DECLARE_CSR(mstateen1, CSR_MSTATEEN1) -DECLARE_CSR(mstateen2, CSR_MSTATEEN2) -DECLARE_CSR(mstateen3, CSR_MSTATEEN3) -DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mtval, CSR_MTVAL) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(mtinst, CSR_MTINST) -DECLARE_CSR(mtval2, CSR_MTVAL2) -DECLARE_CSR(miselect, CSR_MISELECT) -DECLARE_CSR(mireg, CSR_MIREG) -DECLARE_CSR(mtopei, CSR_MTOPEI) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpcfg4, CSR_PMPCFG4) -DECLARE_CSR(pmpcfg5, CSR_PMPCFG5) -DECLARE_CSR(pmpcfg6, CSR_PMPCFG6) -DECLARE_CSR(pmpcfg7, CSR_PMPCFG7) -DECLARE_CSR(pmpcfg8, CSR_PMPCFG8) -DECLARE_CSR(pmpcfg9, CSR_PMPCFG9) -DECLARE_CSR(pmpcfg10, CSR_PMPCFG10) -DECLARE_CSR(pmpcfg11, CSR_PMPCFG11) -DECLARE_CSR(pmpcfg12, CSR_PMPCFG12) -DECLARE_CSR(pmpcfg13, CSR_PMPCFG13) -DECLARE_CSR(pmpcfg14, CSR_PMPCFG14) -DECLARE_CSR(pmpcfg15, CSR_PMPCFG15) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(pmpaddr16, CSR_PMPADDR16) -DECLARE_CSR(pmpaddr17, CSR_PMPADDR17) -DECLARE_CSR(pmpaddr18, CSR_PMPADDR18) -DECLARE_CSR(pmpaddr19, CSR_PMPADDR19) -DECLARE_CSR(pmpaddr20, CSR_PMPADDR20) -DECLARE_CSR(pmpaddr21, CSR_PMPADDR21) -DECLARE_CSR(pmpaddr22, CSR_PMPADDR22) -DECLARE_CSR(pmpaddr23, CSR_PMPADDR23) -DECLARE_CSR(pmpaddr24, CSR_PMPADDR24) -DECLARE_CSR(pmpaddr25, CSR_PMPADDR25) -DECLARE_CSR(pmpaddr26, CSR_PMPADDR26) -DECLARE_CSR(pmpaddr27, CSR_PMPADDR27) -DECLARE_CSR(pmpaddr28, CSR_PMPADDR28) -DECLARE_CSR(pmpaddr29, CSR_PMPADDR29) -DECLARE_CSR(pmpaddr30, CSR_PMPADDR30) -DECLARE_CSR(pmpaddr31, CSR_PMPADDR31) -DECLARE_CSR(pmpaddr32, CSR_PMPADDR32) -DECLARE_CSR(pmpaddr33, CSR_PMPADDR33) -DECLARE_CSR(pmpaddr34, CSR_PMPADDR34) -DECLARE_CSR(pmpaddr35, CSR_PMPADDR35) -DECLARE_CSR(pmpaddr36, CSR_PMPADDR36) -DECLARE_CSR(pmpaddr37, CSR_PMPADDR37) -DECLARE_CSR(pmpaddr38, CSR_PMPADDR38) -DECLARE_CSR(pmpaddr39, CSR_PMPADDR39) -DECLARE_CSR(pmpaddr40, CSR_PMPADDR40) -DECLARE_CSR(pmpaddr41, CSR_PMPADDR41) -DECLARE_CSR(pmpaddr42, CSR_PMPADDR42) -DECLARE_CSR(pmpaddr43, CSR_PMPADDR43) -DECLARE_CSR(pmpaddr44, CSR_PMPADDR44) -DECLARE_CSR(pmpaddr45, CSR_PMPADDR45) -DECLARE_CSR(pmpaddr46, CSR_PMPADDR46) -DECLARE_CSR(pmpaddr47, CSR_PMPADDR47) -DECLARE_CSR(pmpaddr48, CSR_PMPADDR48) -DECLARE_CSR(pmpaddr49, CSR_PMPADDR49) -DECLARE_CSR(pmpaddr50, CSR_PMPADDR50) -DECLARE_CSR(pmpaddr51, CSR_PMPADDR51) -DECLARE_CSR(pmpaddr52, CSR_PMPADDR52) -DECLARE_CSR(pmpaddr53, CSR_PMPADDR53) -DECLARE_CSR(pmpaddr54, CSR_PMPADDR54) -DECLARE_CSR(pmpaddr55, CSR_PMPADDR55) -DECLARE_CSR(pmpaddr56, CSR_PMPADDR56) -DECLARE_CSR(pmpaddr57, CSR_PMPADDR57) -DECLARE_CSR(pmpaddr58, CSR_PMPADDR58) -DECLARE_CSR(pmpaddr59, CSR_PMPADDR59) -DECLARE_CSR(pmpaddr60, CSR_PMPADDR60) -DECLARE_CSR(pmpaddr61, CSR_PMPADDR61) -DECLARE_CSR(pmpaddr62, CSR_PMPADDR62) -DECLARE_CSR(pmpaddr63, CSR_PMPADDR63) -DECLARE_CSR(mseccfg, CSR_MSECCFG) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(tinfo, CSR_TINFO) -DECLARE_CSR(tcontrol, CSR_TCONTROL) -DECLARE_CSR(mcontext, CSR_MCONTEXT) -DECLARE_CSR(mscontext, CSR_MSCONTEXT) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch0, CSR_DSCRATCH0) -DECLARE_CSR(dscratch1, CSR_DSCRATCH1) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR) -DECLARE_CSR(mtopi, CSR_MTOPI) -DECLARE_CSR(sieh, CSR_SIEH) -DECLARE_CSR(siph, CSR_SIPH) -DECLARE_CSR(stimecmph, CSR_STIMECMPH) -DECLARE_CSR(vsieh, CSR_VSIEH) -DECLARE_CSR(vsiph, CSR_VSIPH) -DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH) -DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) -DECLARE_CSR(hidelegh, CSR_HIDELEGH) -DECLARE_CSR(hvienh, CSR_HVIENH) -DECLARE_CSR(henvcfgh, CSR_HENVCFGH) -DECLARE_CSR(hviph, CSR_HVIPH) -DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H) -DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H) -DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H) -DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H) -DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H) -DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mstatush, CSR_MSTATUSH) -DECLARE_CSR(midelegh, CSR_MIDELEGH) -DECLARE_CSR(mieh, CSR_MIEH) -DECLARE_CSR(mvienh, CSR_MVIENH) -DECLARE_CSR(mviph, CSR_MVIPH) -DECLARE_CSR(menvcfgh, CSR_MENVCFGH) -DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H) -DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H) -DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H) -DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H) -DECLARE_CSR(miph, CSR_MIPH) -DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H) -DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H) -DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H) -DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H) -DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H) -DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H) -DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H) -DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H) -DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H) -DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H) -DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H) -DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H) -DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H) -DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H) -DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H) -DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H) -DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H) -DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H) -DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H) -DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H) -DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H) -DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H) -DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H) -DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H) -DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H) -DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H) -DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H) -DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H) -DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H) -DECLARE_CSR(mnscratch, CSR_MNSCRATCH) -DECLARE_CSR(mnepc, CSR_MNEPC) -DECLARE_CSR(mncause, CSR_MNCAUSE) -DECLARE_CSR(mnstatus, CSR_MNSTATUS) -DECLARE_CSR(mseccfgh, CSR_MSECCFGH) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) -DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) -DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) -DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) -DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) -DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/env/p/link.ld b/bb-tests/workloads/src/CTest/rvv/env/p/link.ld deleted file mode 100644 index a64fffb6..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/p/link.ld +++ /dev/null @@ -1,16 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} diff --git a/bb-tests/workloads/src/CTest/rvv/env/p/riscv_test.h b/bb-tests/workloads/src/CTest/rvv/env/p/riscv_test.h deleted file mode 100644 index 8dd32ed8..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/p/riscv_test.h +++ /dev/null @@ -1,297 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_H -#define _ENV_PHYSICAL_SINGLE_CORE_H - -#include "../encoding.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#define RVTEST_RV64U \ - .macro init; \ - .endm - -#define RVTEST_RV64UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV64UV \ - .macro init; \ - RVTEST_VECTOR_ENABLE; \ - .endm - -#define RVTEST_RV32U \ - .macro init; \ - .endm - -#define RVTEST_RV32UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV32UV \ - .macro init; \ - RVTEST_VECTOR_ENABLE; \ - .endm - -#define RVTEST_RV64M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV64S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#define RVTEST_RV32M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV32S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#if __riscv_xlen == 64 -#define CHECK_XLEN \ - li a0, 1; \ - slli a0, a0, 31; \ - bgez a0, 1f; \ - RVTEST_PASS; \ - 1: -#else -#define CHECK_XLEN \ - li a0, 1; \ - slli a0, a0, 31; \ - bltz a0, 1f; \ - RVTEST_PASS; \ - 1: -#endif - -#define INIT_XREG \ - li x1, 0; \ - li x2, 0; \ - li x3, 0; \ - li x4, 0; \ - li x5, 0; \ - li x6, 0; \ - li x7, 0; \ - li x8, 0; \ - li x9, 0; \ - li x10, 0; \ - li x11, 0; \ - li x12, 0; \ - li x13, 0; \ - li x14, 0; \ - li x15, 0; \ - li x16, 0; \ - li x17, 0; \ - li x18, 0; \ - li x19, 0; \ - li x20, 0; \ - li x21, 0; \ - li x22, 0; \ - li x23, 0; \ - li x24, 0; \ - li x25, 0; \ - li x26, 0; \ - li x27, 0; \ - li x28, 0; \ - li x29, 0; \ - li x30, 0; \ - li x31, 0; - -#define INIT_PMP \ - la t0, 1f; \ - csrw mtvec, t0; \ - /* Set up a PMP to permit all accesses */ \ - li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \ - csrw pmpaddr0, t0; \ - li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ - csrw pmpcfg0, t0; \ - .align 2; \ - 1: - -#define INIT_RNMI \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi CSR_MNSTATUS, MNSTATUS_NMIE; \ - .align 2; \ - 1: - -#define INIT_SATP \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi satp, 0; \ - .align 2; \ - 1: - -#define DELEGATE_NO_TRAPS \ - csrwi mie, 0; \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi medeleg, 0; \ - csrwi mideleg, 0; \ - .align 2; \ - 1: - -#define RVTEST_ENABLE_SUPERVISOR \ - li a0, MSTATUS_MPP &(MSTATUS_MPP >> 1); \ - csrs mstatus, a0; \ - li a0, SIP_SSIP | SIP_STIP; \ - csrs mideleg, a0; - -#define RVTEST_ENABLE_MACHINE \ - li a0, MSTATUS_MPP; \ - csrs mstatus, a0; - -#define RVTEST_FP_ENABLE \ - li a0, MSTATUS_FS &(MSTATUS_FS >> 1); \ - csrs mstatus, a0; \ - csrwi fcsr, 0 - -#define RVTEST_VECTOR_ENABLE \ - li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1)); \ - csrs mstatus, a0; \ - csrwi fcsr, 0; \ - csrwi vcsr, 0; - -#define RISCV_MULTICORE_DISABLE \ - csrr a0, mhartid; \ - 1 : bnez a0, 1b - -#define EXTRA_TVEC_USER -#define EXTRA_TVEC_MACHINE -#define EXTRA_INIT -#define EXTRA_INIT_TIMER -#define FILTER_TRAP -#define FILTER_PAGE_FAULT - -#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ - -#define RVTEST_CODE_BEGIN \ - .section.text.init; \ - .align 6; \ - .weak stvec_handler; \ - .weak mtvec_handler; \ - .globl _start; \ - _start: \ - /* reset vector */ \ - j reset_vector; \ - .align 2; \ - trap_vector: \ - /* test whether the test came from pass/fail */ \ - csrr t5, mcause; \ - li t6, CAUSE_USER_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_SUPERVISOR_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_MACHINE_ECALL; \ - beq t5, t6, write_tohost; \ - /* if an mtvec_handler is defined, jump to it */ \ - la t5, mtvec_handler; \ - beqz t5, 1f; \ - jr t5; \ - /* was it an interrupt or an exception? */ \ - 1 : csrr t5, mcause; \ - bgez t5, handle_exception; \ - INTERRUPT_HANDLER; \ - handle_exception: \ - /* we don't know how to handle whatever the exception was */ \ - other_exception: \ - /* some unhandlable exception occurred */ \ - 1 : ori TESTNUM, TESTNUM, 1337; \ - write_tohost: \ - sw TESTNUM, tohost, t5; \ - sw zero, tohost + 4, t5; \ - j write_tohost; \ - reset_vector: \ - INIT_XREG; \ - RISCV_MULTICORE_DISABLE; \ - INIT_RNMI; \ - INIT_SATP; \ - INIT_PMP; \ - DELEGATE_NO_TRAPS; \ - li TESTNUM, 0; \ - la t0, trap_vector; \ - csrw mtvec, t0; \ - CHECK_XLEN; \ - /* if an stvec_handler is defined, delegate exceptions to it */ \ - la t0, stvec_handler; \ - beqz t0, 1f; \ - csrw stvec, t0; \ - li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT) | \ - (1 << CAUSE_FETCH_PAGE_FAULT) | (1 << CAUSE_MISALIGNED_FETCH) | \ - (1 << CAUSE_USER_ECALL) | (1 << CAUSE_BREAKPOINT); \ - csrw medeleg, t0; \ - 1 : csrwi mstatus, 0; \ - init; \ - EXTRA_INIT; \ - EXTRA_INIT_TIMER; \ - la t0, 1f; \ - csrw mepc, t0; \ - csrr a0, mhartid; \ - mret; \ - 1: - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -#define RVTEST_CODE_END unimp - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#define RVTEST_PASS \ - fence; \ - li TESTNUM, 1; \ - li a7, 93; \ - li a0, 0; \ - ecall - -#define TESTNUM gp -#define RVTEST_FAIL \ - fence; \ - 1 : beqz TESTNUM, 1b; \ - sll TESTNUM, TESTNUM, 1; \ - or TESTNUM, TESTNUM, 1; \ - li a7, 93; \ - addi a0, TESTNUM, 0; \ - ecall - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN \ - EXTRA_DATA.pushsection.tohost, "aw", @progbits; \ - .align 6; \ - .global tohost; \ - tohost: \ - .dword 0; \ - .size tohost, 8; \ - .align 6; \ - .global fromhost; \ - fromhost: \ - .dword 0; \ - .size fromhost, 8; \ - .popsection; \ - .align 4; \ - .global begin_signature; \ - begin_signature: - -#define RVTEST_DATA_END \ - .align 4; \ - .global end_signature; \ - end_signature: - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/env/pm/link.ld b/bb-tests/workloads/src/CTest/rvv/env/pm/link.ld deleted file mode 120000 index 86b45f9f..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/pm/link.ld +++ /dev/null @@ -1 +0,0 @@ -../p/link.ld \ No newline at end of file diff --git a/bb-tests/workloads/src/CTest/rvv/env/pm/riscv_test.h b/bb-tests/workloads/src/CTest/rvv/env/pm/riscv_test.h deleted file mode 100644 index 38a0e86b..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/pm/riscv_test.h +++ /dev/null @@ -1,11 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_MULTI_CORE_H -#define _ENV_PHYSICAL_MULTI_CORE_H - -#include "../p/riscv_test.h" - -#undef RISCV_MULTICORE_DISABLE -#define RISCV_MULTICORE_DISABLE - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/env/pt/link.ld b/bb-tests/workloads/src/CTest/rvv/env/pt/link.ld deleted file mode 120000 index 86b45f9f..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/pt/link.ld +++ /dev/null @@ -1 +0,0 @@ -../p/link.ld \ No newline at end of file diff --git a/bb-tests/workloads/src/CTest/rvv/env/pt/riscv_test.h b/bb-tests/workloads/src/CTest/rvv/env/pt/riscv_test.h deleted file mode 100644 index 378406d7..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/pt/riscv_test.h +++ /dev/null @@ -1,69 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H -#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H - -#include "../p/riscv_test.h" - -#define TIMER_INTERVAL 2 - -#undef EXTRA_INIT_TIMER -#define EXTRA_INIT_TIMER \ - li a0, MIP_MTIP; \ - csrs mie, a0; \ - csrr a0, mtime; \ - addi a0, a0, TIMER_INTERVAL; \ - csrw mtimecmp, a0; - -#if SSTATUS_XS != 0x18000 -#error -#endif -#define XS_SHIFT 15 - -#undef INTERRUPT_HANDLER -#define INTERRUPT_HANDLER \ - slli t5, t5, 1; \ - srli t5, t5, 1; \ - add t5, t5, -IRQ_M_TIMER; \ - bnez t5, other_exception; /* other interrups shouldn't happen */ \ - csrr t5, mtime; \ - addi t5, t5, TIMER_INTERVAL; \ - csrw mtimecmp, t5; \ - mret; - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#undef EXTRA_DATA -#define EXTRA_DATA \ - .align 3; \ - regspill: \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - evac: \ - .skip 32768; - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/env/v/entry.S b/bb-tests/workloads/src/CTest/rvv/env/v/entry.S deleted file mode 100644 index 13d46a34..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/v/entry.S +++ /dev/null @@ -1,164 +0,0 @@ -#include "riscv_test.h" - -#if __riscv_xlen == 64 -# define STORE sd -# define LOAD ld -# define REGBYTES 8 -#else -# define STORE sw -# define LOAD lw -# define REGBYTES 4 -#endif - -#define STACK_TOP (_end + RISCV_PGSIZE * 4) - - .section ".text.init","ax",@progbits - .globl _start - .align 2 -_start: - j handle_reset - - /* NMI vector */ - .align 2 -nmi_vector: - j wtf - - .align 2 -trap_vector: - j wtf - -handle_reset: - li x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - INIT_RNMI - - la t0, trap_vector - csrw mtvec, t0 - la sp, STACK_TOP - SIZEOF_TRAPFRAME_T - csrr t0, mhartid - slli t0, t0, 12 - add sp, sp, t0 - csrw mscratch, sp - call extra_boot - la a0, userstart - j vm_boot - - .globl pop_tf -pop_tf: - LOAD t0,33*REGBYTES(a0) - csrw sepc,t0 - LOAD x1,1*REGBYTES(a0) - LOAD x2,2*REGBYTES(a0) - LOAD x3,3*REGBYTES(a0) - LOAD x4,4*REGBYTES(a0) - LOAD x5,5*REGBYTES(a0) - LOAD x6,6*REGBYTES(a0) - LOAD x7,7*REGBYTES(a0) - LOAD x8,8*REGBYTES(a0) - LOAD x9,9*REGBYTES(a0) - LOAD x11,11*REGBYTES(a0) - LOAD x12,12*REGBYTES(a0) - LOAD x13,13*REGBYTES(a0) - LOAD x14,14*REGBYTES(a0) - LOAD x15,15*REGBYTES(a0) - LOAD x16,16*REGBYTES(a0) - LOAD x17,17*REGBYTES(a0) - LOAD x18,18*REGBYTES(a0) - LOAD x19,19*REGBYTES(a0) - LOAD x20,20*REGBYTES(a0) - LOAD x21,21*REGBYTES(a0) - LOAD x22,22*REGBYTES(a0) - LOAD x23,23*REGBYTES(a0) - LOAD x24,24*REGBYTES(a0) - LOAD x25,25*REGBYTES(a0) - LOAD x26,26*REGBYTES(a0) - LOAD x27,27*REGBYTES(a0) - LOAD x28,28*REGBYTES(a0) - LOAD x29,29*REGBYTES(a0) - LOAD x30,30*REGBYTES(a0) - LOAD x31,31*REGBYTES(a0) - LOAD a0,10*REGBYTES(a0) - sret - - .global trap_entry - .align 2 -trap_entry: - csrrw sp, sscratch, sp - - # save gprs - STORE x1,1*REGBYTES(sp) - STORE x3,3*REGBYTES(sp) - STORE x4,4*REGBYTES(sp) - STORE x5,5*REGBYTES(sp) - STORE x6,6*REGBYTES(sp) - STORE x7,7*REGBYTES(sp) - STORE x8,8*REGBYTES(sp) - STORE x9,9*REGBYTES(sp) - STORE x10,10*REGBYTES(sp) - STORE x11,11*REGBYTES(sp) - STORE x12,12*REGBYTES(sp) - STORE x13,13*REGBYTES(sp) - STORE x14,14*REGBYTES(sp) - STORE x15,15*REGBYTES(sp) - STORE x16,16*REGBYTES(sp) - STORE x17,17*REGBYTES(sp) - STORE x18,18*REGBYTES(sp) - STORE x19,19*REGBYTES(sp) - STORE x20,20*REGBYTES(sp) - STORE x21,21*REGBYTES(sp) - STORE x22,22*REGBYTES(sp) - STORE x23,23*REGBYTES(sp) - STORE x24,24*REGBYTES(sp) - STORE x25,25*REGBYTES(sp) - STORE x26,26*REGBYTES(sp) - STORE x27,27*REGBYTES(sp) - STORE x28,28*REGBYTES(sp) - STORE x29,29*REGBYTES(sp) - STORE x30,30*REGBYTES(sp) - STORE x31,31*REGBYTES(sp) - - csrrw t0,sscratch,sp - STORE t0,2*REGBYTES(sp) - - # get sr, epc, badvaddr, cause - csrr t0,sstatus - STORE t0,32*REGBYTES(sp) - csrr t0,sepc - STORE t0,33*REGBYTES(sp) - csrr t0,stval - STORE t0,34*REGBYTES(sp) - csrr t0,scause - STORE t0,35*REGBYTES(sp) - - move a0, sp - j handle_trap diff --git a/bb-tests/workloads/src/CTest/rvv/env/v/link.ld b/bb-tests/workloads/src/CTest/rvv/env/v/link.ld deleted file mode 120000 index 86b45f9f..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/v/link.ld +++ /dev/null @@ -1 +0,0 @@ -../p/link.ld \ No newline at end of file diff --git a/bb-tests/workloads/src/CTest/rvv/env/v/riscv_test.h b/bb-tests/workloads/src/CTest/rvv/env/v/riscv_test.h deleted file mode 100644 index 39b98b8e..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/v/riscv_test.h +++ /dev/null @@ -1,101 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_VIRTUAL_SINGLE_CORE_H -#define _ENV_VIRTUAL_SINGLE_CORE_H - -#include "../p/riscv_test.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#undef RVTEST_FP_ENABLE -#define RVTEST_FP_ENABLE fssr x0 - -#undef RVTEST_VECTOR_ENABLE -#define RVTEST_VECTOR_ENABLE \ - csrwi fcsr, 0; \ - csrwi vcsr, 0; - -#undef RVTEST_CODE_BEGIN -#define RVTEST_CODE_BEGIN \ - .text; \ - .global extra_boot; \ - extra_boot: \ - EXTRA_INIT \ - ret; \ - .global trap_filter; \ - trap_filter: \ - FILTER_TRAP \ - li a0, 0; \ - ret; \ - .global pf_filter; \ - pf_filter: \ - FILTER_PAGE_FAULT \ - li a0, 0; \ - ret; \ - .global userstart; \ - userstart: \ - init - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#undef RVTEST_PASS -#define RVTEST_PASS \ - li a0, 1; \ - scall - -#undef RVTEST_FAIL -#define RVTEST_FAIL \ - sll a0, TESTNUM, 1; \ - 1 : beqz a0, 1b; \ - or a0, a0, 1; \ - scall; - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#undef RVTEST_DATA_END -#define RVTEST_DATA_END - -//----------------------------------------------------------------------- -// Supervisor mode definitions and macros -//----------------------------------------------------------------------- - -#ifndef LFSR_BITS -#define LFSR_BITS 6 -#endif - -#define MAX_TEST_PAGES \ - ((1 << LFSR_BITS) - 1) // this must be the period of the LFSR below -#define LFSR_NEXT(x) \ - (((((x) ^ ((x) >> 1)) & 1) << (LFSR_BITS - 1)) | ((x) >> 1)) - -#define PGSHIFT 12 -#define PGSIZE (1UL << PGSHIFT) - -#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36) - -#ifndef __ASSEMBLER__ - -typedef unsigned long pte_t; -#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2) -#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2)) -#define VPN_BITS (PTIDXBITS * LEVELS) -#define VA_BITS (VPN_BITS + PGSHIFT) -#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS) -#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE) - -typedef struct { - long gpr[32]; - long sr; - long epc; - long badvaddr; - long cause; -} trapframe_t; -#endif - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/env/v/string.c b/bb-tests/workloads/src/CTest/rvv/env/v/string.c deleted file mode 100644 index f934b194..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/v/string.c +++ /dev/null @@ -1,108 +0,0 @@ -#include -#include -#include - -void *memcpy(void *dest, const void *src, size_t len) { - if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t) - 1)) == - 0) { - const uintptr_t *s = src; - uintptr_t *d = dest; - while (d < (uintptr_t *)(dest + len)) - *d++ = *s++; - } else { - const char *s = src; - char *d = dest; - while (d < (char *)(dest + len)) - *d++ = *s++; - } - return dest; -} - -void *memset(void *dest, int byte, size_t len) { - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t) - 1)) == 0) { - uintptr_t word = byte & 0xFF; - word |= word << 8; - word |= word << 16; - word |= word << 16 << 16; - - uintptr_t *d = dest; - while (d < (uintptr_t *)(dest + len)) - *d++ = word; - } else { - char *d = dest; - while (d < (char *)(dest + len)) - *d++ = byte; - } - return dest; -} - -size_t strlen(const char *s) { - const char *p = s; - while (*p) - p++; - return p - s; -} - -int strcmp(const char *s1, const char *s2) { - unsigned char c1, c2; - - do { - c1 = *s1++; - c2 = *s2++; - } while (c1 != 0 && c1 == c2); - - return c1 - c2; -} - -int memcmp(const void *s1, const void *s2, size_t n) { - if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t) - 1)) == 0) { - const uintptr_t *u1 = s1; - const uintptr_t *u2 = s2; - const uintptr_t *end = u1 + (n / sizeof(uintptr_t)); - while (u1 < end) { - if (*u1 != *u2) - break; - u1++; - u2++; - } - n -= (const void *)u1 - s1; - s1 = u1; - s2 = u2; - } - - while (n--) { - unsigned char c1 = *(const unsigned char *)s1++; - unsigned char c2 = *(const unsigned char *)s2++; - if (c1 != c2) - return c1 - c2; - } - - return 0; -} - -char *strcpy(char *dest, const char *src) { - char *d = dest; - while ((*d++ = *src++)) - ; - return dest; -} - -long atol(const char *str) { - long res = 0; - int sign = 0; - - while (*str == ' ') - str++; - - if (*str == '-' || *str == '+') { - sign = *str == '-'; - str++; - } - - while (*str) { - res *= 10; - res += *str++ - '0'; - } - - return sign ? -res : res; -} diff --git a/bb-tests/workloads/src/CTest/rvv/env/v/vm.c b/bb-tests/workloads/src/CTest/rvv/env/v/vm.c deleted file mode 100644 index a26781f4..00000000 --- a/bb-tests/workloads/src/CTest/rvv/env/v/vm.c +++ /dev/null @@ -1,310 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include - -#include "riscv_test.h" - -#if __riscv_xlen == 32 -#define SATP_MODE_CHOICE SATP_MODE_SV32 -#elif defined(Sv48) -#define SATP_MODE_CHOICE SATP_MODE_SV48 -#else -#define SATP_MODE_CHOICE SATP_MODE_SV39 -#endif - -void trap_entry(); -void pop_tf(trapframe_t *); - -extern volatile uint64_t tohost; -extern volatile uint64_t fromhost; - -static void do_tohost(uint64_t tohost_value) { - while (tohost) - fromhost = 0; - tohost = tohost_value; -} - -#define pa2kva(pa) ((void *)(pa) - DRAM_BASE - MEGAPAGE_SIZE) -#define uva2kva(pa) ((void *)(pa) - MEGAPAGE_SIZE) - -#define flush_page(addr) asm volatile("sfence.vma %0" : : "r"(addr) : "memory") - -static uint64_t lfsr63(uint64_t x) { - uint64_t bit = (x ^ (x >> 1)) & 1; - return (x >> 1) | (bit << 62); -} - -static void cputchar(int x) { - do_tohost(0x0101000000000000 | (unsigned char)x); -} - -static void cputstring(const char *s) { - while (*s) - cputchar(*s++); -} - -static void terminate(int code) { - do_tohost(code); - while (1) - ; -} - -void wtf() { terminate(841); } - -#define stringify1(x) #x -#define stringify(x) stringify1(x) -#define assert(x) \ - do { \ - if (x) \ - break; \ - cputstring("Assertion failed: " stringify(x) "\n"); \ - terminate(3); \ - } while (0) - -#define l1pt pt[0] -#define user_l2pt pt[1] -#if SATP_MODE_CHOICE == SATP_MODE_SV48 -#define NPT 6 -#define kernel_l2pt pt[2] -#define kernel_l3pt pt[3] -#define user_l3pt pt[4] -#define user_llpt pt[5] -#elif SATP_MODE_CHOICE == SATP_MODE_SV39 -#define NPT 4 -#define kernel_l2pt pt[2] -#define user_llpt pt[3] -#elif SATP_MODE_CHOICE == SATP_MODE_SV32 -#define NPT 2 -#define user_llpt user_l2pt -#else -#error Unknown SATP_MODE_CHOICE -#endif -pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE))); - -typedef struct { - pte_t addr; - void *next; -} freelist_t; - -freelist_t user_mapping[MAX_TEST_PAGES]; -freelist_t freelist_nodes[MAX_TEST_PAGES]; -freelist_t *freelist_head, *freelist_tail; - -void printhex(uint64_t x) { - char str[17]; - for (int i = 0; i < 16; i++) { - str[15 - i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a' - 10); - x >>= 4; - } - str[16] = 0; - - cputstring(str); -} - -static void evict(unsigned long addr) { - assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); - addr = addr / PGSIZE * PGSIZE; - - freelist_t *node = &user_mapping[addr / PGSIZE]; - if (node->addr) { - // check accessed and dirty bits - assert(user_llpt[addr / PGSIZE] & PTE_A); - uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); - if (memcmp((void *)addr, uva2kva(addr), PGSIZE)) { - assert(user_llpt[addr / PGSIZE] & PTE_D); - memcpy(uva2kva(addr), (void *)addr, PGSIZE); - } - write_csr(sstatus, sstatus); - - user_mapping[addr / PGSIZE].addr = 0; - - if (freelist_tail == 0) - freelist_head = freelist_tail = node; - else { - freelist_tail->next = node; - freelist_tail = node; - } - } -} - -extern int pf_filter(uintptr_t addr, uintptr_t *pte, int *copy); -extern int trap_filter(trapframe_t *tf); - -void handle_fault(uintptr_t addr, uintptr_t cause) { - uintptr_t filter_encodings = 0; - int copy_page = 1; - - assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); - addr = addr / PGSIZE * PGSIZE; - - if (user_llpt[addr / PGSIZE]) { - if (!(user_llpt[addr / PGSIZE] & PTE_A)) { - user_llpt[addr / PGSIZE] |= PTE_A; - } else { - assert(!(user_llpt[addr / PGSIZE] & PTE_D) && - cause == CAUSE_STORE_PAGE_FAULT); - user_llpt[addr / PGSIZE] |= PTE_D; - } - flush_page(addr); - return; - } - - freelist_t *node = freelist_head; - assert(node); - freelist_head = node->next; - if (freelist_head == freelist_tail) - freelist_tail = 0; - - uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | - PTE_R | PTE_W | PTE_X; - - if (pf_filter(addr, &filter_encodings, ©_page)) { - new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | filter_encodings; - } - - user_llpt[addr / PGSIZE] = new_pte | PTE_A | PTE_D; - flush_page(addr); - - assert(user_mapping[addr / PGSIZE].addr == 0); - user_mapping[addr / PGSIZE] = *node; - - uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); - memcpy((void *)addr, uva2kva(addr), PGSIZE); - write_csr(sstatus, sstatus); - - user_llpt[addr / PGSIZE] = new_pte; - flush_page(addr); - - asm volatile("fence.i"); -} - -void handle_trap(trapframe_t *tf) { - if (trap_filter(tf)) { - pop_tf(tf); - } - - if (tf->cause == CAUSE_USER_ECALL) { - int n = tf->gpr[10]; - - for (long i = 1; i < MAX_TEST_PAGES; i++) - evict(i * PGSIZE); - - terminate(n); - } else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) { - assert(tf->epc % 4 == 0); - - int *fssr; - asm("jal %0, 1f; fssr x0; 1:" : "=r"(fssr)); - - if (*(int *)tf->epc == *fssr) - terminate(1); // FP test on non-FP hardware. "succeed." - else - assert(!"illegal instruction"); - tf->epc += 4; - } else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || - tf->cause == CAUSE_LOAD_PAGE_FAULT || - tf->cause == CAUSE_STORE_PAGE_FAULT) - handle_fault(tf->badvaddr, tf->cause); - else - assert(!"unexpected exception"); - - pop_tf(tf); -} - -static void coherence_torture() { - // cause coherence misses without affecting program semantics - uint64_t random = ENTROPY; - while (1) { - uintptr_t paddr = - DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4); -#ifdef __riscv_atomic - if (random & 1) // perform a no-op write - asm volatile("amoadd.w zero, zero, (%0)" ::"r"(paddr)); - else // perform a read -#endif - asm volatile("lw zero, (%0)" ::"r"(paddr)); - random = lfsr63(random); - } -} - -void vm_boot(uintptr_t test_addr) { - uint64_t random = ENTROPY; - if (read_csr(mhartid) > 0) - coherence_torture(); - - _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???"); - -#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0 -#error -#endif - // map user to lowermost megapage - l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - // map kernel to uppermost megapage -#if SATP_MODE_CHOICE == SATP_MODE_SV48 - l1pt[PTES_PER_PT - 1] = - ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - kernel_l2pt[PTES_PER_PT - 1] = - ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - kernel_l3pt[PTES_PER_PT - 1] = (DRAM_BASE / RISCV_PGSIZE << PTE_PPN_SHIFT) | - PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; - user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - user_l3pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; -#elif SATP_MODE_CHOICE == SATP_MODE_SV39 - l1pt[PTES_PER_PT - 1] = - ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - kernel_l2pt[PTES_PER_PT - 1] = (DRAM_BASE / RISCV_PGSIZE << PTE_PPN_SHIFT) | - PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; - user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; -#elif SATP_MODE_CHOICE == SATP_MODE_SV32 - l1pt[PTES_PER_PT - 1] = (DRAM_BASE / RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | - PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; -#else -#error -#endif - uintptr_t vm_choice = SATP_MODE_CHOICE; - uintptr_t satp_value = ((uintptr_t)l1pt >> PGSHIFT) | - (vm_choice * (SATP_MODE & ~(SATP_MODE << 1))); - write_csr(satp, satp_value); - if (read_csr(satp) != satp_value) - assert(!"unsupported satp mode"); - - // Set up PMPs if present, ignoring illegal instruction trap if not. - uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; - uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1; - asm volatile("la t0, 1f\n\t" - "csrrw t0, mtvec, t0\n\t" - "csrw pmpaddr0, %1\n\t" - "csrw pmpcfg0, %0\n\t" - ".align 2\n\t" - "1: csrw mtvec, t0" - : - : "r"(pmpc), "r"(pmpa) - : "t0"); - - // set up supervisor trap handling - write_csr(stvec, pa2kva(trap_entry)); - write_csr(sscratch, pa2kva(read_csr(mscratch))); - write_csr(medeleg, (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) | - (1 << CAUSE_LOAD_PAGE_FAULT) | - (1 << CAUSE_STORE_PAGE_FAULT)); - // FPU on; accelerator on; vector unit on - write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS); - write_csr(mie, 0); - - random = 1 + (random % MAX_TEST_PAGES); - freelist_head = pa2kva((void *)&freelist_nodes[0]); - freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES - 1]); - for (long i = 0; i < MAX_TEST_PAGES; i++) { - freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random) * PGSIZE; - freelist_nodes[i].next = pa2kva(&freelist_nodes[i + 1]); - random = LFSR_NEXT(random); - } - freelist_nodes[MAX_TEST_PAGES - 1].next = 0; - - trapframe_t tf; - memset(&tf, 0, sizeof(tf)); - tf.epc = test_addr - DRAM_BASE; - pop_tf(&tf); -} diff --git a/bb-tests/workloads/src/CTest/rvv/utasks/utasks.h b/bb-tests/workloads/src/CTest/rvv/utasks/utasks.h deleted file mode 100644 index 80936ddd..00000000 --- a/bb-tests/workloads/src/CTest/rvv/utasks/utasks.h +++ /dev/null @@ -1,490 +0,0 @@ -#ifndef UTASKS_H -#define UTASKS_H - -#include "util.h" -#include -#include -#include -#include -#include -#include -#include - -class runner_t; - -class mutex_t { // can't use std::mutex if we don't have pthreads -public: - mutex_t() : next_ticket(0), now_serving(0) {} - void lock() { - size_t my_ticket = next_ticket.fetch_add(1, std::memory_order_relaxed); - while (my_ticket != now_serving.load(std::memory_order_acquire)) { - } - } - void unlock() { now_serving.fetch_add(1, std::memory_order_release); } - -private: - std::atomic next_ticket; - std::atomic now_serving; -}; - -mutex_t printf_lock; - -#define PRINTF(...) \ - ({ \ - printf_lock.lock(); \ - printf("hart %ld: ", read_csr(mhartid)); \ - printf(__VA_ARGS__); \ - printf_lock.unlock(); \ - }) - -class allocator_t { -public: - virtual void *allocate(size_t n) = 0; - virtual void deallocate(void *buf) = 0; -}; - -mutex_t heap_allocator_lock; -class heap_allocator_t : public allocator_t { -public: - void *allocate(size_t n) { - heap_allocator_lock.lock(); - void *buf = malloc(n); - heap_allocator_lock.unlock(); - return buf; - } - void deallocate(void *buf) { - heap_allocator_lock.lock(); - free(buf); - heap_allocator_lock.unlock(); - } -}; - -class region_allocator_t : public allocator_t { -public: - region_allocator_t(void *base, size_t size) - : base(base), size(size), tail(0) {} - void *allocate(size_t n) { - lock.lock(); - if (tail + n > size) { - lock.unlock(); - PRINTF("illegal allocation size %ld\n", size); - exit(1); - } - void *r = (uint8_t *)base + tail; - tail += n; - lock.unlock(); - return r; - } - void deallocate(void *buf) {} - -private: - mutex_t lock; - void *base; - size_t size; - size_t tail; -}; - -class alignas(64) task_t { - friend class runner_t; - -public: - task_t() : may_finish(false) {} - void set_may_finish() { may_finish = true; } - bool __attribute__((noinline)) is_finished() { - return may_finish && !has_work(); - } - void wait_for_finished() { - while (!this->is_finished()) { - }; - } - virtual void propagate_finished() = 0; - virtual void assign_runner(runner_t *runner) {}; - -private: - virtual void run() = 0; - virtual bool has_work() = 0; - -protected: - bool may_finish; -}; - -class circular_buffer_pointers_t { -public: - circular_buffer_pointers_t() : head_wide(0), tail_wide(0), size(0) {} - size_t head_wide; - size_t tail_wide; - size_t size; -}; - -template class alignas(64) circular_buffer_t { -public: - circular_buffer_t(size_t capacity, void *buffer, - circular_buffer_pointers_t *pointers) - : buffer((T *)buffer), capacity(capacity), pointers(pointers) { - if (capacity < 4 || (capacity & (capacity - 1)) != 0) { - PRINTF("Illegal capacity %ld\n", capacity); - exit(1); - } - mask = capacity - 1; - } - ~circular_buffer_t() { delete[] buffer; } - - std::pair push(size_t n) { - size_t tail_wide_read, size_read; - size_t mask = this->mask; - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(tail_wide_read) - : [incr] "r"(n), [addr] "r"(&pointers->tail_wide)); - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(size_read) - : [incr] "r"(n), [addr] "r"(&pointers->size)); - tail_wide_read += n; - size_read += n; - size_t tail = tail_wide_read & mask; - size_t head = pointers->head_wide & mask; - size_t remaining_capacity = capacity - size_read; - size_t limit = ((head > tail) ? head : capacity) - tail; - size_t r = (remaining_capacity > limit) ? limit : remaining_capacity; - return std::make_pair(buffer + tail, r); - } - - std::pair pop(size_t n) { - size_t head_wide_read, size_read; - size_t mask = this->mask; - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(head_wide_read) - : [incr] "r"(n), [addr] "r"(&pointers->head_wide)); - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(size_read) - : [incr] "r"((~n) + 1), [addr] "r"(&pointers->size)); - head_wide_read += n; - size_read -= n; - size_t head = head_wide_read & mask; - size_t tail = pointers->tail_wide & mask; - size_t limit = ((tail > head) ? tail : capacity) - head; - size_t r = (size_read > limit) ? limit : size_read; - return std::make_pair(buffer + head, r); - } - - bool busy() { return pointers->size != 0; } - - T *buffer; - size_t mask; - size_t capacity; - circular_buffer_pointers_t *pointers; -}; - -template class circular_buffer_helper_t { -public: - static std::tuple - push_pop(circular_buffer_t *const source, - circular_buffer_pointers_t *source_pointers, - circular_buffer_t *const sink, - circular_buffer_pointers_t *sink_pointers, size_t n) { - size_t sink_tail_wide_read, sink_size_read; - size_t source_head_wide_read, source_size_read; - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(sink_tail_wide_read) - : [incr] "r"(n), [addr] "r"(&sink_pointers->tail_wide)); - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(source_head_wide_read) - : [incr] "r"(n), [addr] "r"(&source_pointers->head_wide)); - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(sink_size_read) - : [incr] "r"(n), [addr] "r"(&sink_pointers->size)); - asm volatile("amoadd.d %[rd], %[incr], (%[addr])\n" - : [rd] "=r"(source_size_read) - : [incr] "r"((~n) + 1), [addr] "r"(&source_pointers->size)); - size_t sink_head_wide = sink_pointers->head_wide; - size_t source_tail_wide = source_pointers->tail_wide; - - asm volatile("\n"); - size_t sink_mask = sink->mask; - size_t source_mask = source->mask; - size_t sink_capacity = sink->capacity; - size_t source_capacity = source->capacity; - - asm volatile("add %[rd], %[src], %[incr]\n" - : [rd] "=r"(sink_tail_wide_read) - : [src] "r"(sink_tail_wide_read), [incr] "r"(n)); - asm volatile("add %[rd], %[src], %[incr]\n" - : [rd] "=r"(source_head_wide_read) - : [src] "r"(source_head_wide_read), [incr] "r"(n)); - asm volatile("add %[rd], %[src], %[incr]\n" - : [rd] "=r"(sink_size_read) - : [src] "r"(sink_size_read), [incr] "r"(n)); - asm volatile("sub %[rd], %[src], %[incr]\n" - : [rd] "=r"(source_size_read) - : [src] "r"(source_size_read), [incr] "r"(n)); - - T *source_buffer = source->buffer; - U *sink_buffer = sink->buffer; - size_t remaining_capacity = sink_capacity - sink_size_read; - size_t sink_tail = sink_tail_wide_read & sink_mask; - size_t sink_head = sink_head_wide & sink_mask; - size_t sink_limit = - ((sink_head > sink_tail) ? sink_head : sink_capacity) - sink_tail; - size_t sink_r = - (remaining_capacity > sink_limit) ? sink_limit : remaining_capacity; - - size_t source_head = source_head_wide_read & source_mask; - size_t source_tail = source_tail_wide & source_mask; - size_t source_limit = - ((source_tail > source_head) ? source_tail : source_capacity) - - source_head; - size_t source_r = - (source_size_read > source_limit) ? source_limit : source_size_read; - - size_t r = (sink_r > source_r) ? source_r : sink_r; - return std::make_tuple(source_buffer + source_head, sink_buffer + sink_tail, - r); - } -}; - -template class sink_t; -template class source_t; - -class runner_t { -public: - runner_t(size_t id, allocator_t *allocator) - : id(id), task_count(0), allocator(allocator) {}; - void run() { - while (1) { - task_t *scheduled_task = schedule_task(); - if (scheduled_task) { - scheduled_task->run(); - } - } - } - - void add_task(task_t *task) { - task->assign_runner(this); - task_lock.lock(); - tasks.push_back(task); - task_count++; - task_lock.unlock(); - } - - bool idle() { return task_count.load() == 0; } - - allocator_t *get_allocator() { return allocator; } - -private: - task_t *schedule_task() { - task_lock.lock(); - for (auto &t : tasks) { - if (t->has_work()) { - task_lock.unlock(); - return t; - } - } - std::list::iterator it = tasks.begin(); - while (it != tasks.end()) { - if ((*it)->is_finished()) { - (*it)->propagate_finished(); - it = tasks.erase(it); - task_count--; - } - it++; - } - task_lock.unlock(); - return nullptr; - } - - size_t id; - mutex_t task_lock; - std::atomic task_count; - std::list tasks; - allocator_t *allocator; -}; - -template class sink_t : virtual public task_t { - friend class source_t; - -public: - sink_t(size_t buffer_size) : buffer_size(buffer_size), buffer(nullptr) {} - ~sink_t() { - runner->get_allocator()->deallocate(buffer_data); - runner->get_allocator()->deallocate(buffer); - } - void assign_runner(runner_t *runner) { - this->runner = runner; - void *pointers_buff = - runner->get_allocator()->allocate(sizeof(circular_buffer_pointers_t)); - circular_buffer_pointers_t *pointers = - new (pointers_buff) circular_buffer_pointers_t; - buffer_data = runner->get_allocator()->allocate(buffer_size * sizeof(T)); - buffer = new circular_buffer_t(buffer_size, buffer_data, pointers); - } - size_t buffer_size; - alignas(64) circular_buffer_t *buffer; - -private: - runner_t *runner; - void *buffer_data; -}; - -template class source_t : virtual public task_t { -public: - source_t() : next(nullptr), output(nullptr) {} - void chain(sink_t *next) { - if (this->next) { - PRINTF("Failed chain\n"); - exit(1); - } - this->next = next; - } - void terminate(T *out) { - if (this->next) { - PRINTF("Failed chain\n"); - exit(1); - } - output = out; - } - void propagate_finished() { - if (this->next) { - this->next->set_may_finish(); - } - } - -protected: - sink_t *next; - alignas(64) T *output; -}; - -template -class pipe_task_t : public source_t, public sink_t { -public: - pipe_task_t(size_t buffer_size, size_t max_chunk) - : max_chunk(max_chunk), sink_t(buffer_size) {} - bool has_work() { return this->buffer->busy(); } - virtual size_t kernel(T *in, U *out, size_t n) = 0; - -private: - void run() { - bool has_next = this->next != nullptr; - circular_buffer_t *next_buffer = has_next ? this->next->buffer : nullptr; - size_t max_chunk = this->max_chunk; - circular_buffer_t *buffer = this->buffer; - if (has_next) { - circular_buffer_pointers_t *source_pointers = buffer->pointers; - circular_buffer_pointers_t *next_pointers = next_buffer->pointers; - std::tuple r = circular_buffer_helper_t::push_pop( - buffer, source_pointers, next_buffer, next_pointers, 0); - T *input = std::get<0>(r); - T *output = std::get<1>(r); - size_t n = std::get<2>(r); - while (n > 0) { - size_t completed = 0; - while (completed < max_chunk && n > 0) { - size_t finished = kernel(input, output, n); - n -= finished; - completed += finished; - input += finished; - output += finished; - } - asm volatile("fence"); - r = circular_buffer_helper_t::push_pop( - buffer, source_pointers, next_buffer, next_pointers, completed); - input = std::get<0>(r); - output = std::get<1>(r); - n = std::get<2>(r); - if (completed == 0) - break; - } - } else { - std::pair pop = buffer->pop(0); - T *input = pop.first; - size_t n = pop.second; - while (n > 0) { - size_t completed = 0; - while (completed < max_chunk && n > 0) { - size_t finished = kernel(input, this->output, n); - n -= finished; - completed += finished; - input += finished; - this->output += finished; - } - asm volatile("fence"); - pop = buffer->pop(completed); - input = pop.first; - n = pop.second; - if (completed == 0) - break; - } - } - } - size_t max_chunk; -}; - -template class source_task_t : public source_t { -public: - source_task_t(size_t max_chunk) : max_chunk(max_chunk) {} - virtual size_t kernel(T *out, size_t n) = 0; - virtual bool has_work() = 0; - -private: - void run() { - bool has_next = this->next != nullptr; - assert(has_next); - circular_buffer_t *next_buffer = has_next ? this->next->buffer : nullptr; - size_t max_chunk = this->max_chunk; - - std::pair push = next_buffer->push(0); - T *output = push.first; - size_t n = push.second; - while (n > 0) { - size_t completed = 0; - while (completed < max_chunk && n > 0) { - size_t finished = kernel(output, n); - n -= finished; - completed += finished; - output += finished; - if (finished == 0) - break; - } - asm volatile("fence"); - push = next_buffer->push(completed); - output = push.first; - n = push.second; - if (completed == 0) - break; - } - } - size_t max_chunk; -}; - -template class sink_task_t : public sink_t { -public: - sink_task_t(size_t buffer_size, size_t max_chunk) - : max_chunk(max_chunk), sink_t(buffer_size) {} - bool has_work() { return this->buffer->busy(); } - virtual size_t kernel(T *in, size_t n) = 0; - -private: - void run() { - size_t max_chunk = this->max_chunk; - circular_buffer_t buffer = this->buffer; - std::pair pop = buffer->pop(0); - T *input = pop.first; - size_t n = pop.second; - while (n > 0) { - size_t completed = 0; - while (completed < max_chunk && n > 0) { - size_t finished = kernel(input, n); - n -= finished; - completed += finished; - input += finished; - } - asm volatile("fence"); - pop = buffer->pop(completed); - input = pop.first; - n = pop.second; - if (completed == 0) - break; - } - } - size_t max_chunk; -}; - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vadd_test.c b/bb-tests/workloads/src/CTest/rvv/vadd_test.c new file mode 100644 index 00000000..dbb22d04 --- /dev/null +++ b/bb-tests/workloads/src/CTest/rvv/vadd_test.c @@ -0,0 +1,40 @@ +#include +#include + +int main() { + printf("Testing RVV vector addition with intrinsics\n"); + + // Test parameters + const int n = 16; + int a[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + int b[16] = {16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}; + int c[16] = {0}; + int expected[16] = {17, 17, 17, 17, 17, 17, 17, 17, + 17, 17, 17, 17, 17, 17, 17, 17}; + + // Perform vector addition using RVV intrinsics + size_t vl; + for (size_t i = 0; i < n;) { + vl = __riscv_vsetvl_e32m1(n - i); // Set vector length + vint32m1_t va = __riscv_vle32_v_i32m1(&a[i], vl); // Load vector a + vint32m1_t vb = __riscv_vle32_v_i32m1(&b[i], vl); // Load vector b + vint32m1_t vc = __riscv_vadd_vv_i32m1(va, vb, vl); // Vector add + __riscv_vse32_v_i32m1(&c[i], vc, vl); // Store result + i += vl; + } + + // Verify results + int passed = 1; + for (int i = 0; i < n; i++) { + if (c[i] != expected[i]) { + printf("FAILED at index %d: expected %d, got %d\n", i, expected[i], c[i]); + passed = 0; + } + } + + if (passed) { + printf("Test PASSED - Vector addition works correctly!\n"); + } + + return passed ? 0 : 1; +} diff --git a/bb-tests/workloads/src/CTest/rvv/vdot_test.c b/bb-tests/workloads/src/CTest/rvv/vdot_test.c new file mode 100644 index 00000000..480af9d3 --- /dev/null +++ b/bb-tests/workloads/src/CTest/rvv/vdot_test.c @@ -0,0 +1,39 @@ +#include +#include + +int main() { + printf("Testing RVV vector dot product with intrinsics\n"); + + // Test parameters + const int n = 8; + int a[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + int b[8] = {8, 7, 6, 5, 4, 3, 2, 1}; + int result = 0; + // Expected: 1*8 + 2*7 + 3*6 + 4*5 + 5*4 + 6*3 + 7*2 + 8*1 + // = 8 + 14 + 18 + 20 + 20 + 18 + 14 + 8 = 120 + int expected = 120; + + // Perform vector dot product using RVV intrinsics + size_t vl = __riscv_vsetvl_e32m1(n); // Set vector length for entire array + + vint32m1_t va = __riscv_vle32_v_i32m1(a, vl); // Load vector a + vint32m1_t vb = __riscv_vle32_v_i32m1(b, vl); // Load vector b + vint32m1_t vmul = __riscv_vmul_vv_i32m1(va, vb, vl); // Element-wise multiply + + // Manual reduction: store to temp array and sum + int temp[8]; + __riscv_vse32_v_i32m1(temp, vmul, vl); + + for (int i = 0; i < n; i++) { + result += temp[i]; + } + + // Verify result + if (result == expected) { + printf("Test PASSED - Dot product result: %d\n", result); + return 0; + } else { + printf("Test FAILED - Expected %d, got %d\n", expected, result); + return 1; + } +} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conditional/conditional_gendata.pl b/bb-tests/workloads/src/CTest/rvv/vec-conditional/conditional_gendata.pl deleted file mode 100755 index bf29e81c..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conditional/conditional_gendata.pl +++ /dev/null @@ -1,142 +0,0 @@ -#!/usr/bin/perl -w -#========================================================================== -# conditional_gendata.pl -# -# Author: Generated -# Date: Today -# -(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm; -# -# Simple script which creates an input data set and the reference data -# for the given conditional operation. -# -ENDMSG - -use strict "vars"; -use warnings; -no warnings("once"); -use Getopt::Long; - -#-------------------------------------------------------------------------- -# Command line processing -#-------------------------------------------------------------------------- - -our %opts; - -sub usage() -{ - - print "\n"; - print " Usage: conditional_gendata.pl [options] \n"; - print "\n"; - print " Options:\n"; - print " --help print this message\n"; - print " --size size of input data [1000]\n"; - print " --seed random seed [1]\n"; - print "$usageMsg"; - - exit(); -} - -sub processCommandLine() -{ - - $opts{"help"} = 0; - $opts{"size"} = 1000; - $opts{"seed"} = 1; - Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage(); - $opts{"help"} and usage(); - -} - -#-------------------------------------------------------------------------- -# Helper Functions -#-------------------------------------------------------------------------- -sub printArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - my $type = $_[2]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print $type." ".$arrayName."[DATA_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3d",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - my @input1_data; # x - my @input2_data; # a - my @input3_data; # b - my @verify_data; # z - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - my $valueX = int(rand(10)); # x - my $valueA = int(rand(999)); # a - my $valueB = int(rand(999)); # b - - push( @input1_data, $valueX ); - push( @input2_data, $valueA ); - push( @input3_data, $valueB ); - push( @verify_data, ($valueX < 5) ? $valueA : $valueB ); - } - - print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n"; - printArray( "input1_data", \@input1_data, "int8_t" ); # x - printArray( "input2_data", \@input2_data, "int16_t" ); # a - printArray( "input3_data", \@input3_data, "int16_t" ); # b - printArray( "verify_data", \@verify_data, "int16_t" ); # z - -} - -main(); diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conditional/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-conditional/dataset1.h deleted file mode 100644 index 5cfbc028..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conditional/dataset1.h +++ /dev/null @@ -1,250 +0,0 @@ -#define DATA_SIZE 1000 - -int8_t input1_data[DATA_SIZE] = { - 0, 3, 1, 3, 1, 1, 8, 2, 9, 5, 6, 0, 1, 6, 3, 7, 3, 1, 3, 2, 5, 5, 2, 6, 5, - 9, 0, 9, 3, 6, 2, 3, 9, 3, 9, 9, 6, 0, 1, 6, 2, 9, 9, 4, 5, 7, 2, 1, 4, 4, - 7, 6, 2, 5, 1, 5, 3, 8, 2, 7, 5, 2, 4, 5, 5, 2, 2, 6, 1, 3, 9, 4, 5, 7, 9, - 6, 0, 8, 4, 0, 3, 0, 9, 2, 4, 1, 3, 9, 5, 6, 3, 1, 0, 3, 4, 7, 0, 6, 0, 8, - 8, 1, 3, 1, 8, 5, 2, 3, 8, 8, 6, 1, 5, 6, 5, 7, 2, 0, 7, 1, 3, 9, 9, 8, 0, - 6, 1, 1, 8, 2, 1, 9, 9, 3, 7, 6, 5, 6, 0, 5, 7, 6, 0, 3, 8, 2, 2, 6, 3, 3, - 5, 1, 7, 4, 0, 4, 2, 1, 7, 0, 9, 1, 4, 8, 2, 6, 8, 8, 2, 2, 5, 2, 8, 7, 0, - 7, 7, 7, 2, 0, 7, 7, 7, 7, 0, 6, 9, 1, 7, 9, 4, 3, 3, 1, 2, 1, 7, 4, 8, 1, - 6, 7, 1, 1, 3, 8, 1, 0, 7, 6, 5, 8, 1, 4, 7, 4, 0, 7, 5, 0, 0, 0, 1, 4, 6, - 9, 2, 5, 5, 3, 9, 0, 4, 4, 9, 6, 3, 1, 6, 4, 6, 6, 3, 1, 3, 0, 1, 7, 7, 4, - 1, 0, 0, 0, 1, 3, 1, 3, 4, 3, 8, 3, 3, 3, 8, 3, 4, 2, 5, 9, 7, 5, 8, 9, 4, - 9, 1, 6, 7, 9, 7, 3, 7, 1, 9, 8, 5, 7, 7, 5, 7, 5, 1, 8, 8, 7, 7, 9, 4, 0, - 7, 7, 3, 4, 9, 9, 8, 3, 8, 3, 0, 1, 7, 6, 7, 7, 3, 2, 5, 8, 9, 6, 9, 0, 5, - 9, 2, 9, 9, 4, 2, 9, 1, 5, 0, 8, 2, 6, 6, 2, 9, 1, 9, 2, 1, 5, 7, 7, 5, 7, - 2, 0, 4, 5, 2, 6, 6, 2, 4, 2, 0, 8, 8, 5, 7, 4, 3, 0, 4, 9, 3, 8, 4, 2, 9, - 8, 0, 9, 8, 2, 2, 4, 0, 9, 4, 5, 3, 4, 7, 7, 5, 0, 8, 0, 4, 0, 5, 0, 8, 7, - 1, 2, 9, 0, 8, 8, 5, 4, 1, 8, 9, 3, 4, 0, 1, 4, 3, 2, 0, 2, 1, 7, 3, 1, 9, - 2, 3, 1, 2, 6, 8, 4, 1, 2, 8, 8, 4, 9, 2, 5, 0, 7, 0, 2, 8, 1, 7, 7, 2, 6, - 1, 1, 9, 0, 6, 7, 1, 9, 7, 6, 0, 7, 9, 0, 9, 3, 5, 5, 5, 5, 8, 4, 4, 8, 2, - 4, 3, 3, 1, 7, 8, 3, 3, 4, 6, 4, 9, 4, 9, 3, 7, 8, 5, 8, 3, 1, 1, 1, 1, 2, - 4, 6, 4, 8, 4, 8, 4, 3, 0, 5, 1, 9, 5, 8, 3, 4, 2, 8, 4, 6, 5, 3, 3, 5, 5, - 5, 7, 7, 0, 7, 0, 6, 3, 0, 1, 9, 7, 0, 9, 8, 9, 3, 7, 1, 6, 7, 8, 2, 1, 3, - 8, 7, 6, 1, 9, 3, 4, 2, 1, 5, 3, 0, 3, 4, 0, 4, 5, 3, 7, 4, 8, 2, 0, 1, 2, - 5, 3, 7, 0, 0, 5, 3, 3, 0, 4, 7, 3, 2, 1, 8, 9, 4, 9, 4, 3, 1, 2, 6, 9, 7, - 3, 1, 0, 6, 9, 9, 6, 4, 6, 7, 3, 0, 7, 1, 8, 8, 7, 0, 5, 5, 8, 1, 8, 2, 8, - 1, 6, 3, 7, 5, 0, 0, 6, 5, 2, 8, 5, 8, 7, 7, 9, 3, 7, 7, 2, 6, 4, 0, 0, 5, - 7, 8, 6, 3, 3, 8, 1, 9, 7, 6, 6, 5, 2, 4, 8, 8, 9, 5, 7, 4, 4, 6, 0, 2, 7, - 4, 8, 4, 2, 9, 9, 4, 4, 7, 6, 0, 2, 3, 8, 5, 4, 4, 2, 7, 2, 4, 5, 1, 3, 7, - 3, 4, 1, 1, 5, 4, 8, 2, 2, 5, 1, 1, 8, 4, 0, 4, 9, 3, 1, 8, 0, 7, 8, 0, 3, - 4, 4, 4, 6, 1, 2, 0, 2, 9, 4, 1, 2, 7, 7, 1, 8, 6, 7, 0, 9, 5, 5, 0, 2, 1, - 1, 8, 4, 2, 6, 0, 8, 3, 8, 9, 9, 3, 8, 4, 7, 3, 9, 0, 0, 5, 8, 1, 4, 7, 0, - 5, 5, 2, 8, 7, 3, 5, 5, 5, 4, 4, 1, 2, 0, 4, 2, 5, 4, 8, 7, 8, 2, 2, 6, 0, - 7, 8, 1, 3, 1, 2, 2, 9, 1, 1, 7, 5, 8, 3, 4, 2, 4, 4, 0, 2, 9, 1, 7, 7, 4, - 9, 2, 3, 7, 1, 8, 7, 4, 4, 8, 4, 8, 5, 9, 9, 1, 9, 2, 7, 6, 2, 3, 9, 6, 3, - 5, 2, 2, 1, 7, 9, 3, 8, 7, 4, 4, 7, 1, 3, 8, 8, 3, 9, 1, 3, 3, 6, 1, 6, 6, - 4, 6, 4, 4, 9, 8, 8, 2, 5, 1, 1, 4, 8, 5, 8, 7, 5, 9, 9, 3, 2, 1, 1, 7, 1, - 5, 8, 0, 6, 2, 0, 6, 7, 5, 0, 6, 3, 2, 4, 3, 7, 4, 0, 1, 5, 6, 8, 8, 5, 1, - 9, 9, 9, 6, 6, 0, 8, 4, 5, 0, 8, 6, 9, 3, 8, 7, 7, 6, 6, 4, 0, 7, 1, 4, 3, - 3, 1, 8, 6, 3, 2, 3, 9, 0, 9, 5, 5, 5, 1, 5, 8, 7, 0, 5, 9, 5, 4, 6, 8, 8, - 3, 2, 4, 5, 5, 0, 0, 2, 6, 8, 2, 6, 5, 6, 4, 5, 3, 4, 7, 5, 2, 7, 8, 4, 5}; - -int16_t input2_data[DATA_SIZE] = { - 454, 564, 989, 350, 64, 584, 140, 6, 339, 392, 228, 110, 750, 426, 436, - 774, 981, 875, 564, 938, 647, 203, 703, 606, 551, 195, 569, 229, 584, 902, - 489, 826, 592, 195, 649, 350, 814, 181, 998, 65, 704, 141, 715, 264, 538, - 761, 494, 499, 693, 444, 285, 317, 351, 288, 169, 606, 796, 455, 758, 358, - 989, 985, 788, 517, 461, 775, 332, 598, 446, 125, 557, 799, 925, 648, 891, - 19, 557, 95, 440, 614, 396, 808, 170, 344, 536, 965, 539, 882, 54, 701, - 479, 891, 641, 665, 95, 158, 395, 247, 476, 792, 265, 414, 214, 518, 503, - 284, 643, 290, 68, 731, 619, 786, 828, 528, 487, 947, 626, 304, 403, 959, - 818, 294, 874, 748, 60, 105, 153, 651, 412, 356, 423, 140, 621, 533, 715, - 837, 886, 173, 493, 133, 969, 951, 415, 110, 860, 255, 988, 628, 990, 753, - 633, 19, 452, 777, 988, 81, 483, 153, 390, 943, 601, 496, 121, 641, 870, - 113, 871, 275, 404, 784, 526, 803, 226, 280, 726, 454, 54, 41, 397, 508, - 416, 480, 478, 709, 482, 873, 173, 526, 1, 232, 464, 30, 233, 350, 779, - 784, 743, 823, 403, 160, 289, 202, 636, 90, 70, 855, 954, 6, 698, 194, - 598, 526, 746, 698, 534, 49, 732, 893, 547, 492, 215, 83, 59, 921, 96, - 834, 966, 114, 625, 10, 409, 387, 305, 559, 592, 409, 497, 427, 995, 521, - 822, 185, 14, 274, 185, 486, 96, 899, 814, 80, 37, 946, 935, 870, 441, - 62, 554, 845, 639, 211, 249, 562, 974, 495, 470, 159, 419, 180, 542, 458, - 729, 795, 671, 104, 670, 984, 745, 584, 385, 528, 457, 378, 477, 236, 416, - 165, 270, 704, 825, 303, 623, 560, 294, 532, 398, 584, 375, 767, 589, 958, - 845, 837, 522, 824, 165, 171, 461, 155, 376, 694, 158, 747, 193, 124, 274, - 425, 619, 269, 156, 752, 987, 1, 32, 809, 399, 972, 554, 558, 600, 579, - 540, 849, 995, 716, 224, 181, 820, 793, 96, 320, 238, 754, 191, 142, 884, - 165, 140, 646, 23, 422, 480, 542, 201, 745, 119, 932, 81, 533, 880, 203, - 735, 365, 1, 680, 169, 947, 177, 101, 654, 679, 242, 471, 641, 713, 151, - 870, 601, 907, 397, 979, 454, 365, 962, 98, 655, 315, 90, 774, 70, 282, - 494, 594, 488, 290, 639, 449, 539, 644, 723, 767, 552, 491, 362, 617, 144, - 282, 335, 560, 343, 782, 339, 344, 465, 759, 485, 333, 746, 699, 336, 503, - 546, 268, 943, 345, 396, 908, 523, 545, 990, 351, 719, 312, 616, 567, 737, - 989, 316, 182, 796, 771, 115, 644, 165, 911, 742, 983, 671, 719, 962, 154, - 620, 447, 796, 325, 80, 175, 637, 838, 898, 230, 601, 324, 553, 17, 978, - 177, 185, 393, 651, 377, 349, 553, 844, 593, 980, 544, 50, 781, 716, 896, - 6, 548, 703, 829, 771, 613, 559, 313, 434, 607, 784, 896, 415, 431, 162, - 224, 595, 834, 964, 201, 154, 797, 943, 574, 652, 721, 362, 744, 206, 277, - 973, 757, 627, 517, 910, 904, 63, 394, 482, 244, 557, 172, 884, 594, 6, - 159, 562, 454, 506, 167, 382, 494, 72, 52, 932, 342, 961, 287, 985, 626, - 600, 860, 793, 478, 689, 914, 139, 974, 780, 548, 653, 270, 428, 626, 315, - 323, 317, 239, 377, 231, 70, 825, 576, 848, 303, 616, 708, 2, 967, 815, - 831, 410, 741, 422, 117, 9, 952, 64, 804, 811, 846, 335, 971, 415, 318, - 565, 647, 597, 294, 383, 866, 115, 673, 952, 5, 257, 948, 35, 222, 213, - 943, 621, 444, 934, 340, 462, 321, 522, 78, 313, 238, 972, 201, 879, 450, - 163, 143, 643, 771, 781, 797, 630, 966, 435, 413, 696, 116, 710, 538, 581, - 874, 615, 898, 261, 764, 686, 432, 560, 825, 317, 359, 386, 11, 504, 408, - 907, 368, 516, 359, 797, 69, 692, 300, 815, 829, 247, 243, 281, 713, 909, - 406, 932, 304, 373, 86, 412, 28, 850, 28, 707, 941, 682, 672, 43, 713, - 549, 186, 214, 44, 898, 456, 651, 408, 970, 877, 642, 368, 972, 109, 121, - 516, 631, 736, 315, 530, 296, 854, 668, 228, 881, 808, 0, 483, 212, 154, - 528, 668, 338, 334, 374, 746, 385, 545, 587, 456, 729, 971, 871, 304, 269, - 538, 491, 404, 231, 758, 644, 992, 57, 352, 776, 648, 95, 345, 198, 632, - 86, 95, 337, 87, 86, 580, 187, 230, 759, 547, 10, 798, 957, 450, 128, - 220, 590, 217, 249, 858, 799, 610, 157, 963, 974, 571, 783, 955, 772, 361, - 650, 552, 798, 563, 761, 167, 277, 829, 361, 397, 914, 478, 264, 390, 208, - 443, 813, 118, 964, 30, 101, 92, 453, 361, 23, 839, 890, 246, 622, 366, - 296, 529, 80, 260, 851, 243, 760, 631, 843, 333, 936, 594, 75, 329, 751, - 805, 48, 473, 638, 973, 474, 82, 923, 371, 280, 686, 451, 810, 620, 98, - 611, 376, 791, 298, 726, 249, 898, 5, 607, 208, 741, 258, 950, 31, 353, - 50, 700, 821, 774, 361, 263, 810, 940, 180, 639, 33, 418, 716, 786, 408, - 494, 925, 391, 552, 798, 262, 367, 373, 850, 688, 857, 555, 422, 172, 830, - 834, 144, 126, 134, 804, 913, 424, 555, 756, 325, 302, 134, 683, 791, 533, - 86, 440, 471, 47, 777, 900, 459, 559, 685, 470, 437, 616, 106, 121, 694, - 937, 39, 229, 843, 252, 492, 419, 970, 456, 955, 623, 325, 527, 732, 104, - 980, 830, 689, 790, 343, 580, 48, 292, 724, 805, 510, 258, 723, 328, 48, - 450, 485, 515, 441, 346, 405, 609, 446, 154, 965, 993, 467, 480, 687, 942, - 725, 330, 741, 241, 279, 607, 517, 87, 146, 457, 78, 73, 423, 967, 87, - 33, 342, 430, 990, 178, 928, 160, 224, 234, 382, 163, 231, 366, 746, 733, - 722, 26, 440, 435, 667, 813, 924, 373, 877, 47, 321, 49, 286, 385, 215, - 238, 146, 289, 774, 977, 726, 637, 767, 55, 858}; - -int16_t input3_data[DATA_SIZE] = { - 833, 1, 749, 572, 949, 216, 621, 572, 890, 898, 961, 883, 296, 500, 659, - 812, 678, 696, 474, 258, 569, 88, 759, 375, 657, 592, 267, 800, 944, 368, - 913, 313, 985, 543, 566, 997, 657, 208, 859, 847, 349, 253, 886, 415, 979, - 4, 478, 864, 222, 296, 676, 78, 937, 646, 615, 289, 351, 720, 367, 92, - 62, 853, 346, 222, 908, 358, 778, 740, 33, 743, 933, 557, 431, 357, 287, - 514, 86, 853, 587, 678, 280, 17, 819, 380, 512, 917, 808, 887, 946, 951, - 567, 7, 568, 730, 434, 280, 84, 911, 435, 729, 486, 236, 548, 6, 682, - 173, 499, 599, 215, 658, 251, 131, 302, 433, 322, 125, 824, 10, 733, 703, - 722, 406, 653, 86, 378, 667, 381, 98, 840, 12, 54, 216, 343, 921, 521, - 299, 13, 36, 121, 537, 372, 434, 129, 438, 437, 478, 409, 719, 549, 450, - 171, 646, 501, 509, 753, 12, 853, 339, 357, 171, 328, 968, 516, 81, 786, - 603, 907, 610, 32, 745, 357, 441, 751, 943, 458, 201, 459, 53, 377, 141, - 860, 219, 499, 180, 371, 725, 992, 914, 435, 247, 697, 521, 250, 40, 573, - 161, 502, 355, 170, 633, 32, 320, 853, 852, 107, 388, 157, 16, 204, 677, - 218, 824, 239, 511, 706, 428, 799, 702, 373, 798, 621, 651, 794, 657, 880, - 659, 462, 62, 529, 714, 904, 728, 105, 901, 512, 796, 202, 940, 359, 158, - 22, 680, 107, 797, 242, 718, 698, 739, 644, 326, 407, 605, 768, 88, 148, - 344, 838, 954, 141, 991, 821, 832, 615, 266, 916, 336, 803, 215, 840, 636, - 872, 820, 758, 418, 254, 568, 729, 139, 414, 173, 554, 183, 977, 399, 229, - 996, 105, 696, 140, 50, 635, 87, 8, 110, 37, 646, 619, 897, 57, 288, - 985, 99, 67, 432, 749, 28, 621, 272, 43, 898, 236, 443, 265, 935, 941, - 185, 320, 933, 763, 88, 14, 649, 995, 744, 873, 791, 509, 530, 405, 683, - 251, 120, 452, 622, 678, 530, 335, 226, 1, 569, 646, 610, 203, 796, 299, - 108, 974, 852, 619, 890, 565, 372, 991, 408, 372, 464, 34, 52, 908, 744, - 214, 167, 781, 321, 688, 101, 50, 708, 399, 625, 952, 795, 725, 245, 529, - 333, 545, 775, 143, 755, 105, 210, 54, 923, 764, 595, 697, 685, 324, 32, - 622, 389, 75, 409, 726, 950, 135, 303, 290, 125, 415, 107, 116, 869, 235, - 724, 913, 263, 242, 677, 728, 410, 613, 590, 309, 993, 310, 525, 487, 134, - 393, 367, 75, 629, 600, 429, 92, 355, 668, 991, 863, 84, 532, 707, 370, - 452, 912, 746, 160, 618, 854, 226, 779, 830, 137, 705, 565, 886, 785, 293, - 253, 173, 5, 678, 309, 685, 123, 241, 550, 372, 627, 398, 103, 174, 159, - 558, 372, 859, 745, 321, 591, 890, 345, 933, 908, 989, 456, 900, 495, 444, - 700, 285, 29, 652, 546, 534, 116, 507, 971, 42, 169, 421, 916, 539, 147, - 481, 580, 350, 948, 232, 396, 539, 769, 121, 339, 747, 821, 910, 594, 505, - 680, 354, 847, 971, 505, 770, 243, 396, 214, 646, 399, 67, 620, 972, 698, - 882, 809, 366, 93, 831, 853, 452, 78, 59, 10, 924, 680, 797, 92, 885, - 616, 232, 744, 773, 508, 494, 288, 431, 581, 22, 981, 815, 653, 603, 386, - 889, 164, 861, 865, 304, 152, 854, 390, 326, 402, 813, 206, 962, 890, 49, - 665, 321, 246, 176, 675, 764, 426, 531, 758, 611, 437, 854, 237, 639, 684, - 662, 449, 158, 882, 734, 268, 296, 50, 439, 397, 506, 667, 445, 443, 349, - 13, 366, 612, 720, 828, 911, 812, 50, 57, 950, 55, 226, 416, 877, 572, - 99, 12, 812, 968, 488, 242, 293, 795, 345, 599, 386, 93, 680, 112, 960, - 923, 506, 359, 495, 609, 286, 118, 192, 20, 586, 573, 746, 663, 5, 888, - 441, 737, 169, 219, 672, 452, 298, 459, 923, 612, 497, 352, 917, 290, 503, - 625, 108, 685, 954, 646, 446, 664, 655, 392, 735, 523, 451, 156, 766, 124, - 869, 251, 568, 572, 139, 608, 566, 906, 573, 687, 506, 271, 950, 824, 856, - 468, 793, 416, 978, 626, 548, 28, 786, 578, 265, 415, 623, 934, 545, 40, - 712, 349, 307, 872, 225, 996, 136, 487, 837, 487, 114, 688, 667, 624, 729, - 250, 838, 213, 471, 132, 327, 327, 651, 519, 354, 647, 842, 713, 781, 943, - 615, 843, 942, 53, 263, 269, 68, 538, 330, 606, 320, 122, 646, 604, 880, - 175, 425, 346, 63, 514, 766, 939, 120, 172, 755, 323, 866, 100, 530, 696, - 69, 192, 91, 654, 544, 801, 25, 967, 168, 928, 336, 243, 477, 640, 328, - 295, 914, 345, 508, 606, 71, 435, 161, 70, 804, 276, 36, 542, 953, 773, - 133, 104, 462, 815, 237, 393, 196, 168, 613, 589, 197, 232, 306, 424, 690, - 876, 122, 770, 125, 176, 693, 606, 70, 632, 604, 300, 795, 711, 357, 789, - 93, 530, 1, 289, 834, 172, 123, 942, 322, 503, 183, 633, 594, 40, 213, - 794, 217, 267, 554, 199, 99, 946, 891, 834, 286, 256, 467, 918, 695, 529, - 207, 195, 951, 912, 33, 826, 835, 233, 910, 551, 24, 822, 917, 470, 208, - 206, 823, 638, 307, 439, 349, 996, 144, 226, 207, 535, 849, 695, 763, 623, - 724, 92, 86, 303, 652, 530, 321, 963, 369, 164, 957, 2, 296, 304, 935, - 40, 899, 637, 866, 531, 969, 278, 442, 503, 129, 842, 515, 84, 724, 703, - 109, 892, 884, 196, 828, 367, 435, 696, 908, 392, 163, 569, 232, 49, 35, - 900, 700, 759, 631, 637, 885, 147, 919, 995, 875, 734, 163, 293, 104, 363, - 163, 370, 952, 309, 336, 503, 368, 539, 233, 789, 192, 856, 945, 921, 553, - 628, 326, 563, 429, 139, 518, 291, 297, 704, 163, 675, 70, 722, 635, 59, - 874, 677, 204, 474, 548, 333, 508, 769, 448, 452, 665, 866, 442, 101, 713, - 659, 142, 340, 518, 579, 7, 597, 358, 415, 120}; - -int16_t verify_data[DATA_SIZE] = { - 454, 564, 989, 350, 64, 584, 621, 6, 890, 898, 961, 110, 750, 500, 436, - 812, 981, 875, 564, 938, 569, 88, 703, 375, 657, 592, 569, 800, 584, 368, - 489, 826, 985, 195, 566, 997, 657, 181, 998, 847, 704, 253, 886, 264, 979, - 4, 494, 499, 693, 444, 676, 78, 351, 646, 169, 289, 796, 720, 758, 92, - 62, 985, 788, 222, 908, 775, 332, 740, 446, 125, 933, 799, 431, 357, 287, - 514, 557, 853, 440, 614, 396, 808, 819, 344, 536, 965, 539, 887, 946, 951, - 479, 891, 641, 665, 95, 280, 395, 911, 476, 729, 486, 414, 214, 518, 682, - 173, 643, 290, 215, 658, 251, 786, 302, 433, 322, 125, 626, 304, 733, 959, - 818, 406, 653, 86, 60, 667, 153, 651, 840, 356, 423, 216, 343, 533, 521, - 299, 13, 36, 493, 537, 372, 434, 415, 110, 437, 255, 988, 719, 990, 753, - 171, 19, 501, 777, 988, 81, 483, 153, 357, 943, 328, 496, 121, 81, 870, - 603, 907, 610, 404, 784, 357, 803, 751, 943, 726, 201, 459, 53, 397, 508, - 860, 219, 499, 180, 482, 725, 992, 526, 435, 247, 464, 30, 233, 350, 779, - 784, 502, 823, 170, 160, 32, 320, 636, 90, 70, 388, 954, 6, 204, 677, - 218, 824, 746, 698, 706, 49, 732, 702, 373, 492, 215, 83, 59, 921, 880, - 659, 966, 62, 529, 10, 904, 387, 305, 559, 512, 796, 497, 427, 359, 521, - 22, 680, 14, 274, 185, 486, 96, 739, 644, 80, 37, 946, 935, 870, 441, - 62, 554, 845, 639, 211, 821, 562, 974, 495, 916, 159, 419, 180, 840, 636, - 872, 820, 758, 418, 670, 568, 745, 139, 414, 173, 554, 378, 977, 236, 229, - 996, 105, 696, 140, 50, 635, 87, 294, 110, 37, 646, 619, 897, 589, 958, - 985, 99, 522, 824, 749, 28, 621, 155, 43, 694, 158, 747, 265, 935, 941, - 185, 619, 269, 763, 88, 14, 649, 995, 809, 873, 791, 554, 530, 405, 579, - 540, 120, 995, 622, 224, 530, 820, 226, 1, 320, 646, 754, 203, 142, 884, - 108, 974, 852, 619, 890, 480, 542, 201, 408, 119, 464, 34, 533, 880, 203, - 735, 167, 781, 321, 688, 947, 177, 101, 654, 625, 242, 795, 641, 713, 529, - 333, 601, 775, 143, 979, 454, 365, 962, 923, 655, 595, 90, 774, 324, 32, - 622, 594, 75, 290, 639, 449, 135, 644, 290, 125, 552, 491, 116, 617, 235, - 724, 913, 560, 343, 677, 728, 344, 465, 759, 485, 333, 746, 699, 336, 503, - 546, 367, 943, 345, 600, 908, 523, 545, 990, 991, 863, 312, 616, 567, 370, - 452, 316, 746, 796, 618, 115, 226, 165, 911, 137, 983, 565, 886, 962, 293, - 620, 447, 5, 325, 309, 685, 637, 241, 550, 372, 601, 398, 103, 17, 159, - 177, 372, 859, 745, 321, 591, 553, 844, 933, 980, 544, 50, 781, 716, 444, - 700, 548, 703, 829, 546, 613, 116, 313, 971, 607, 169, 421, 916, 539, 162, - 224, 595, 834, 964, 201, 154, 539, 943, 121, 652, 747, 362, 744, 206, 505, - 973, 354, 847, 971, 910, 904, 63, 396, 482, 646, 399, 172, 884, 972, 698, - 882, 809, 366, 506, 831, 382, 452, 72, 52, 932, 924, 680, 287, 92, 885, - 616, 860, 744, 478, 508, 494, 288, 974, 780, 548, 981, 815, 653, 626, 386, - 323, 317, 239, 377, 304, 70, 825, 576, 848, 303, 616, 206, 2, 890, 815, - 665, 410, 741, 422, 117, 764, 952, 531, 804, 811, 437, 335, 971, 415, 318, - 662, 647, 597, 294, 734, 268, 115, 50, 952, 5, 257, 948, 445, 443, 349, - 943, 621, 444, 720, 828, 911, 812, 522, 57, 950, 238, 972, 416, 879, 572, - 99, 12, 643, 968, 488, 242, 630, 795, 435, 599, 696, 93, 710, 112, 960, - 874, 615, 359, 495, 764, 286, 118, 192, 20, 586, 573, 386, 663, 5, 408, - 441, 368, 516, 359, 672, 452, 298, 459, 815, 829, 497, 243, 917, 290, 503, - 625, 108, 304, 373, 646, 446, 664, 655, 392, 707, 941, 451, 672, 43, 124, - 549, 251, 214, 44, 139, 608, 651, 408, 573, 687, 642, 368, 972, 824, 856, - 516, 631, 736, 978, 530, 296, 28, 668, 228, 265, 808, 0, 483, 212, 40, - 528, 349, 338, 334, 225, 746, 385, 487, 587, 456, 729, 688, 871, 304, 729, - 538, 838, 213, 231, 758, 644, 992, 57, 519, 776, 648, 95, 345, 781, 632, - 86, 95, 942, 53, 86, 269, 68, 538, 759, 606, 320, 122, 957, 450, 128, - 220, 425, 217, 249, 514, 799, 939, 157, 172, 755, 323, 783, 100, 772, 696, - 650, 192, 798, 563, 544, 801, 277, 829, 168, 397, 336, 243, 264, 640, 328, - 443, 914, 345, 508, 30, 101, 92, 453, 361, 23, 839, 36, 246, 953, 773, - 133, 529, 80, 815, 851, 393, 196, 631, 843, 333, 936, 594, 306, 329, 751, - 876, 122, 770, 638, 973, 474, 82, 923, 371, 280, 300, 451, 711, 357, 98, - 93, 376, 791, 289, 726, 172, 123, 5, 607, 503, 741, 633, 594, 40, 213, - 50, 217, 821, 554, 199, 263, 810, 891, 834, 639, 256, 418, 716, 786, 529, - 207, 925, 951, 912, 798, 262, 835, 373, 850, 551, 24, 555, 917, 172, 830, - 834, 823, 126, 307, 439, 913, 996, 555, 756, 207, 535, 849, 683, 763, 533, - 86, 440, 86, 303, 652, 530, 321, 963, 369, 470, 437, 616, 106, 304, 694, - 40, 899, 229, 866, 252, 492, 278, 442, 503, 955, 842, 325, 527, 732, 104, - 109, 830, 689, 790, 828, 367, 435, 696, 908, 805, 163, 569, 232, 49, 35, - 450, 700, 515, 631, 346, 885, 147, 919, 154, 875, 734, 163, 293, 104, 942, - 725, 370, 741, 241, 279, 607, 517, 539, 233, 457, 78, 73, 945, 967, 553, - 628, 326, 563, 990, 139, 518, 291, 224, 704, 163, 675, 231, 722, 635, 59, - 722, 26, 440, 474, 548, 813, 924, 373, 448, 452, 321, 866, 442, 101, 215, - 659, 146, 289, 518, 579, 726, 597, 358, 55, 120}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conditional/vec-conditional.S b/bb-tests/workloads/src/CTest/rvv/vec-conditional/vec-conditional.S deleted file mode 100644 index 7b7cefc1..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conditional/vec-conditional.S +++ /dev/null @@ -1,23 +0,0 @@ - .text - .balign 4 - .global vec_conditional - -# (int16) z[i] = ((int8) x[i] < 5) ? (int16) a[i] : (int16) b[i]; -# -vec_conditional: - vsetvli t0, a0, e8, m1, ta, ma # Use 8b elements. - vle8.v v0, (a1) # Get x[i] - sub a0, a0, t0 # Decrement element count - add a1, a1, t0 # x[i] Bump pointer - vmslt.vi v0, v0, 5 # Set mask in v0 - vsetvli x0, x0, e16, m2, ta, mu # Use 16b elements. - slli t0, t0, 1 # Multiply by 2 bytes - vle16.v v2, (a2), v0.t # z[i] = a[i] case - vmnot.m v0, v0 # Invert v0 - add a2, a2, t0 # a[i] bump pointer - vle16.v v2, (a3), v0.t # z[i] = b[i] case - add a3, a3, t0 # b[i] bump pointer - vse16.v v2, (a4) # Store z - add a4, a4, t0 # z[i] bump pointer - bnez a0, vec_conditional # Any more? - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conditional/vec-conditional_main.c b/bb-tests/workloads/src/CTest/rvv/vec-conditional/vec-conditional_main.c deleted file mode 100644 index 4b0c903f..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conditional/vec-conditional_main.c +++ /dev/null @@ -1,60 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Conditional benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized conditional implementation. -// The input data (and reference data) should be generated using -// the conditional_gendata.pl perl script and dumped to a file named -// dataset1.h. - -#include "util.h" -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" -#include - -//-------------------------------------------------------------------------- -// Main - -static int verify_short(int n, const volatile int16_t *test, - const int16_t *verify) { - int i; - // Unrolled for faster verification - for (i = 0; i < n / 2 * 2; i += 2) { - int t0 = test[i], t1 = test[i + 1]; - int v0 = verify[i], v1 = verify[i + 1]; - if (t0 != v0) - return i + 1; - if (t1 != v1) - return i + 2; - } - if (n % 2 != 0 && test[n - 1] != verify[n - 1]) - return n; - return 0; -} - -void vec_conditional(size_t n, int8_t x[], int16_t a[], int16_t b[], - int16_t z[]); - -int main(int argc, char *argv[]) { - int16_t results_data[DATA_SIZE]; - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_conditional(DATA_SIZE, input1_data, input2_data, input3_data, - results_data); -#endif - - // Do the conditional - setStats(1); - vec_conditional(DATA_SIZE, input1_data, input2_data, input3_data, - results_data); - setStats(0); - - return verify_short(DATA_SIZE, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conjugate-gradient/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-conjugate-gradient/gen_data.py deleted file mode 100644 index bb55ba65..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conjugate-gradient/gen_data.py +++ /dev/null @@ -1,208 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# // Author: Chi Zhang, ETH Zurich - -# arg1: size, arg2: steps, arg3: sparse density - -import random -import numpy as np -import sys -from sklearn.datasets import make_spd_matrix -from sklearn.datasets import make_sparse_spd_matrix - - -# fun for froming file -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -def genSymetricPositveDenseMatrix(size, data_type): - A = make_spd_matrix(size) - M = np.array(A, dtype=data_type) - return M - pass - - -def genSymetricPositveSparseMatrix(size, data_type, idx_type, density, element_byte): - alpha = 1.0 - density - M = make_sparse_spd_matrix(size) - M = np.array(M, dtype=data_type) - insert_list = list(np.flatnonzero(M)) - non_zero = len(insert_list) - sparsity = float(non_zero) / float(size * size) - num_row = size - num_col = size - - # nz_coo = np.nonzero(M) - # nz_coo_row = nz_coo[0] - # nz_coo_col = nz_coo[1] - - coo = np.transpose(np.nonzero(M)) - - # generate data - data_list = [] - for x in range(non_zero): - # data_list.append(random.random()) - a = coo[x][0] - b = coo[x][1] - data_list.append(M[a][b]) - pass - - # Count for p_row - p_row = [] - p_row.append(0) - acc_bar = num_col - acc_cnt = 0 - for x in range(non_zero): - if insert_list[x] >= acc_bar: - p_row.append(x) - acc_bar = acc_bar + num_col - acc_cnt = acc_cnt + 1 - while insert_list[x] >= acc_bar: - p_row.append(x) - acc_bar = acc_bar + num_col - acc_cnt = acc_cnt + 1 - pass - pass - pass - for x in range(num_row - acc_cnt): - p_row.append(non_zero) - pass - - # generate indicies - index_list = [] - for x in range(non_zero): - idx = insert_list[x] - max_idx = num_col - while idx >= max_idx: - idx = idx - max_idx - pass - index_list.append(idx * element_byte) - pass - - # form an equvelant dense matrix - A = np.zeros([size, size], dtype=data_type) - cnt = 0 - for x in range(size): - row_len = p_row[x + 1] - p_row[x] - for y in range(row_len): - if cnt != y + p_row[x]: - print("Error. paralyze sparse matrix wrong") - sys.exit() - pass - idx = int((index_list[cnt]) / element_byte) - A[x][idx] = data_list[cnt] - cnt = cnt + 1 - pass - pass - - # check dialog elements - for x in range(size): - if A[x][x] == 0: - print("Error. paralyze dialog wrong") - sys.exit() - pass - pass - - # check symetric - for x in range(size): - for y in range(size): - if A[x][y] != A[y][x]: - print("Error. paralyze dialog wrong") - sys.exit() - pass - pass - pass - - # check transform correctness - for x in range(size): - for y in range(size): - if A[x][y] != M[x][y]: - print("Error. CSR transform wrong") - sys.exit() - pass - pass - pass - - # Form numpy data - A_PROW = np.array(p_row, dtype=idx_type) - A_IDX = np.array(index_list, dtype=idx_type) - A_DATA = np.array(data_list, dtype=data_type) - - return A_PROW, A_IDX, A_DATA, sparsity - pass - - -def genRandomVector(size, data_type): - v = np.zeros([size], dtype=data_type) - for x in range(size): - v[x] = random.random() - pass - return v - pass - - -# SCRIPT - - -if len(sys.argv) == 4: - S = int(sys.argv[1]) - N = int(sys.argv[2]) - D = float(sys.argv[3]) -else: - print("Error. Give me one argument: the number of vector elements.") - sys.exit() - -data_type = np.float64 -idx_type = np.int32 -element_byte = 8 - -A = genSymetricPositveDenseMatrix(S, data_type) -A_PROW, A_IDX, A_DATA, sparsity = genSymetricPositveSparseMatrix( - S, data_type, idx_type, D, element_byte -) -b = genRandomVector(S, data_type) -x = np.zeros([S], dtype=data_type) -r = np.zeros([S], dtype=data_type) -p = np.zeros([S], dtype=data_type) -Ax = np.zeros([S, S], dtype=data_type) -Ap = np.zeros([S, S], dtype=data_type) - - -print('.section .data,"aw",@progbits') -emit("size", np.array(S, dtype=np.uint64)) -emit("step", np.array(N, dtype=np.uint64)) -emit("sparsity", np.array(sparsity, dtype=np.float64)) -emit("A", A, "NR_LANES*4") -emit("b", b, "NR_LANES*4") -emit("x", x, "NR_LANES*4") -emit("r", r, "NR_LANES*4") -emit("p", p, "NR_LANES*4") -emit("Ax", Ax, "NR_LANES*4") -emit("Ap", Ap, "NR_LANES*4") -emit("A_PROW", A_PROW, "NR_LANES*4") -emit("A_IDX", A_IDX, "NR_LANES*4") -emit("A_DATA", A_DATA, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conjugate-gradient/main.c b/bb-tests/workloads/src/CTest/rvv/vec-conjugate-gradient/main.c deleted file mode 100644 index 1e66b4dc..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conjugate-gradient/main.c +++ /dev/null @@ -1,154 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Chi Zhang, ETH Zurich - -#include -#include - -#include "ara/fdotproduct.h" -#include "ara/spmv.h" -#include "util.h" - -#include - -#define MIN_LOSS 0.005 -#define MAX_ITERS 10 -#define abs(x) (x < 0 ? -x : x) - -extern uint64_t size; -extern uint64_t step; -extern double sparsity; - -extern double A[] __attribute__((aligned(16))); -extern double Ax[] __attribute__((aligned(16))); -extern double x[] __attribute__((aligned(16))); -extern double b[] __attribute__((aligned(16))); -extern double r[] __attribute__((aligned(16))); -extern double p[] __attribute__((aligned(16))); -extern double Ap[] __attribute__((aligned(16))); -extern int32_t A_PROW[] __attribute__((aligned(16))); -extern int32_t A_IDX[] __attribute__((aligned(16))); -extern double A_DATA[] __attribute__((aligned(16))); - -void daxpy(double *x, double a, double *y, double *dest, uint64_t len) { - while (len) { - size_t vl = __riscv_vsetvl_e64m8(len); - asm volatile("vle64.v v0, (%0);" ::"r"(x)); - asm volatile("vle64.v v8, (%0);" ::"r"(y)); - asm volatile("vfmacc.vf v8, %0, v0" ::"f"(a)); - asm volatile("vse64.v v8, (%0);" ::"r"(dest)); - x = x + vl; - y = y + vl; - dest = dest + vl; - len = len - vl; - } -} - -double CG_iteration_spmv(int32_t *A_PROW, int32_t *A_IDX, double *A_DATA, - double *x, double *b, double *r, double *p, double *Ap, - uint64_t size) { - /* - Calculate step length alpha - */ - double rk_norm = fdotp_v64b(r, r, size); - spmv_csr_idx32(size, A_PROW, A_IDX, A_DATA, p, Ap); - double pAp = fdotp_v64b(p, Ap, size); - // printf("pAp: %f\n", pAp); - if (abs(pAp) < MIN_LOSS) { - return rk_norm; - } - double alpha = rk_norm / pAp; - - /* - update x - */ - daxpy(p, alpha, x, x, size); - - /* - update loss r - */ - daxpy(Ap, (-1.0) * alpha, r, r, size); - - /* - calculate beta - */ - double rk_norm_new = fdotp_v64b(r, r, size); - double beta = rk_norm_new / rk_norm; - - /* - update p - */ - daxpy(p, beta, r, p, size); - - /* - return loss - */ - return rk_norm_new; -} - -int main() { - printf("Conjugate Gradient\n"); - printf("Solving a Ax=b equation with (%d x %d) Matrix size...\n", size, size); - printf("Sparse Matrix in CSR format, with %ld nonzeros per row\n", - (size_t)(sparsity * size)); - - printf("Initializing CGM parameters...\n"); - spmv_csr_idx32(size, A_PROW, A_IDX, A_DATA, x, Ax); - daxpy(Ax, -1.0, b, r, size); - daxpy(Ax, -1.0, b, p, size); - - printf("Start CGM ...\n"); - - // Start instruction and cycles count of the region of interest - unsigned long cycles1, cycles2, instr2, instr1; - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - uint64_t i = 0; - while (1) { - if (step > 0 && i >= step) { - break; - } - double loss = - CG_iteration_spmv(A_PROW, A_IDX, A_DATA, x, b, r, p, Ap, size); - if (loss < MIN_LOSS || i > MAX_ITERS) { - break; - } - i++; - } - - asm volatile("fence"); - - // End instruction and cycles count of the region of interest - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - size_t rk_norm_ops = size; - size_t spmv_ops = sparsity * size * size; - size_t pAp_ops = size; - size_t daxpy_ops = size * 3; - size_t rk_norm_new_ops = size; - - size_t operations = - i * (rk_norm_ops + spmv_ops + pAp_ops + daxpy_ops + rk_norm_new_ops); - - // Instruction and cycles count of the region of interest - printf("NUMBER OF OPERATIONS %lu\n", operations); - printf("NUMBER OF EXEC CYCLES :%lu\n", cycles2 - cycles1); - printf("NUMBER OF INSTRUCTIONS EXECUTED :%lu\n", instr2 - instr1); - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-conv-3/dataset1.h deleted file mode 100644 index 7c766b9e..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/dataset1.h +++ /dev/null @@ -1,1993 +0,0 @@ -#define K_DIM 3 -#define IH 100 -#define IW 100 -#define I_SIZE 10000 -#define OH 98 -#define OW 98 -#define O_SIZE 9604 - -float input_k[K_DIM * K_DIM] = { - 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, -}; -float input_image[I_SIZE] = { - 20.0, 29.0, 16.0, 10.0, 44.0, 6.0, 2.0, 0.0, 4.0, 12.0, 30.0, - 44.0, 96.0, 20.0, 28.0, 384.0, 3.0, 184.0, 62.0, 20.0, 464.0, 60.0, - 62.0, 216.0, 14.0, 76.0, 304.0, 480.0, 16.0, 192.0, 44.0, 112.0, 2.0, - 27.0, 256.0, 5.0, 52.0, 124.0, 160.0, 112.0, 42.0, 64.0, 16.0, 27.0, - 26.0, 38.0, 23.0, 152.0, 60.0, 184.0, 232.0, 40.0, 176.0, 64.0, 248.0, - 3.0, 176.0, 208.0, 56.0, 31.0, 384.0, 48.0, 108.0, 0.0, 8.0, 48.0, - 26.0, 216.0, 8.0, 20.0, 8.0, 160.0, 336.0, 112.0, 42.0, 12.0, 9.0, - 28.0, 192.0, 112.0, 84.0, 17.0, 288.0, 120.0, 48.0, 28.0, 16.0, 23.0, - 256.0, 112.0, 208.0, 16.0, 8.0, 320.0, 80.0, 116.0, 50.0, 256.0, 16.0, - 248.0, 160.0, 448.0, 100.0, 4.0, 224.0, 54.0, 32.0, 76.0, 16.0, 240.0, - 2.0, 168.0, 32.0, 4.0, 20.0, 26.0, 18.0, 160.0, 4.0, 8.0, 28.0, - 30.0, 240.0, 6.0, 42.0, 24.0, 30.0, 26.0, 64.0, 16.0, 48.0, 320.0, - 6.0, 27.0, 80.0, 54.0, 40.0, 104.0, 3.0, 32.0, 4.0, 168.0, 12.0, - 17.0, 32.0, 112.0, 14.0, 22.0, 11.0, 336.0, 136.0, 68.0, 200.0, 12.0, - 0.0, 1.0, 40.0, 40.0, 0.0, 76.0, 16.0, 384.0, 0.0, 48.0, 240.0, - 144.0, 30.0, 12.0, 27.0, 1.0, 184.0, 192.0, 9.0, 104.0, 16.0, 62.0, - 2.0, 208.0, 32.0, 32.0, 160.0, 52.0, 44.0, 10.0, 100.0, 96.0, 52.0, - 26.0, 64.0, 6.0, 40.0, 30.0, 48.0, 184.0, 14.0, 320.0, 176.0, 2.0, - 84.0, 400.0, 32.0, 52.0, 48.0, 60.0, 208.0, 11.0, 464.0, 26.0, 36.0, - 304.0, 152.0, 64.0, 208.0, 0.0, 80.0, 416.0, 26.0, 44.0, 108.0, 18.0, - 272.0, 64.0, 56.0, 17.0, 60.0, 8.0, 160.0, 320.0, 92.0, 32.0, 12.0, - 160.0, 224.0, 128.0, 0.0, 4.0, 88.0, 13.0, 40.0, 13.0, 6.0, 16.0, - 25.0, 5.0, 11.0, 232.0, 64.0, 336.0, 17.0, 56.0, 128.0, 48.0, 29.0, - 22.0, 18.0, 200.0, 4.0, 28.0, 432.0, 15.0, 416.0, 320.0, 6.0, 272.0, - 12.0, 8.0, 28.0, 480.0, 14.0, 104.0, 64.0, 28.0, 240.0, 20.0, 0.0, - 40.0, 248.0, 112.0, 62.0, 100.0, 136.0, 58.0, 272.0, 24.0, 44.0, 52.0, - 28.0, 64.0, 32.0, 496.0, 0.0, 124.0, 152.0, 40.0, 184.0, 38.0, 10.0, - 24.0, 432.0, 208.0, 48.0, 304.0, 26.0, 7.0, 336.0, 18.0, 112.0, 272.0, - 20.0, 144.0, 192.0, 304.0, 16.0, 34.0, 84.0, 416.0, 240.0, 4.0, 26.0, - 56.0, 23.0, 384.0, 12.0, 36.0, 184.0, 496.0, 10.0, 40.0, 128.0, 112.0, - 108.0, 248.0, 8.0, 0.0, 96.0, 18.0, 168.0, 72.0, 44.0, 176.0, 48.0, - 272.0, 192.0, 216.0, 88.0, 128.0, 32.0, 36.0, 104.0, 27.0, 50.0, 24.0, - 304.0, 31.0, 0.0, 60.0, 232.0, 23.0, 62.0, 0.0, 200.0, 20.0, 6.0, - 12.0, 176.0, 20.0, 432.0, 9.0, 60.0, 30.0, 80.0, 8.0, 24.0, 108.0, - 14.0, 4.0, 232.0, 12.0, 0.0, 224.0, 8.0, 18.0, 72.0, 25.0, 18.0, - 96.0, 32.0, 28.0, 32.0, 240.0, 21.0, 400.0, 0.0, 240.0, 184.0, 24.0, - 13.0, 40.0, 400.0, 432.0, 32.0, 240.0, 3.0, 16.0, 104.0, 22.0, 4.0, - 16.0, 14.0, 480.0, 38.0, 88.0, 58.0, 40.0, 32.0, 24.0, 288.0, 27.0, - 464.0, 38.0, 272.0, 12.0, 64.0, 56.0, 28.0, 144.0, 54.0, 232.0, 19.0, - 28.0, 272.0, 108.0, 496.0, 288.0, 60.0, 8.0, 0.0, 52.0, 60.0, 384.0, - 176.0, 17.0, 52.0, 224.0, 224.0, 12.0, 9.0, 52.0, 0.0, 38.0, 224.0, - 52.0, 480.0, 272.0, 24.0, 29.0, 0.0, 288.0, 4.0, 0.0, 32.0, 136.0, - 400.0, 56.0, 48.0, 30.0, 128.0, 88.0, 29.0, 8.0, 104.0, 29.0, 40.0, - 18.0, 116.0, 52.0, 16.0, 16.0, 26.0, 168.0, 64.0, 104.0, 34.0, 400.0, - 184.0, 72.0, 248.0, 15.0, 44.0, 32.0, 52.0, 46.0, 0.0, 320.0, 64.0, - 40.0, 62.0, 28.0, 112.0, 40.0, 184.0, 60.0, 28.0, 15.0, 416.0, 28.0, - 31.0, 192.0, 48.0, 272.0, 18.0, 44.0, 24.0, 56.0, 48.0, 76.0, 96.0, - 44.0, 62.0, 160.0, 96.0, 128.0, 20.0, 42.0, 240.0, 15.0, 32.0, 216.0, - 0.0, 84.0, 20.0, 25.0, 4.0, 56.0, 84.0, 464.0, 88.0, 16.0, 38.0, - 19.0, 48.0, 26.0, 64.0, 8.0, 448.0, 88.0, 176.0, 6.0, 80.0, 18.0, - 100.0, 160.0, 32.0, 96.0, 16.0, 208.0, 48.0, 52.0, 54.0, 8.0, 29.0, - 464.0, 104.0, 160.0, 21.0, 34.0, 152.0, 112.0, 16.0, 7.0, 216.0, 144.0, - 56.0, 2.0, 14.0, 12.0, 240.0, 6.0, 8.0, 112.0, 80.0, 2.0, 0.0, - 13.0, 25.0, 416.0, 48.0, 240.0, 104.0, 240.0, 84.0, 240.0, 240.0, 48.0, - 152.0, 10.0, 13.0, 176.0, 192.0, 76.0, 8.0, 160.0, 72.0, 32.0, 104.0, - 60.0, 58.0, 464.0, 4.0, 4.0, 248.0, 18.0, 9.0, 176.0, 256.0, 112.0, - 80.0, 4.0, 48.0, 1.0, 14.0, 8.0, 32.0, 92.0, 208.0, 256.0, 23.0, - 168.0, 16.0, 176.0, 76.0, 48.0, 20.0, 28.0, 16.0, 8.0, 64.0, 10.0, - 42.0, 58.0, 48.0, 120.0, 56.0, 19.0, 120.0, 12.0, 108.0, 42.0, 3.0, - 32.0, 32.0, 184.0, 104.0, 96.0, 32.0, 240.0, 208.0, 24.0, 62.0, 320.0, - 30.0, 24.0, 14.0, 44.0, 21.0, 10.0, 58.0, 152.0, 64.0, 240.0, 28.0, - 8.0, 12.0, 60.0, 31.0, 1.0, 56.0, 1.0, 6.0, 8.0, 8.0, 40.0, - 176.0, 160.0, 60.0, 216.0, 25.0, 16.0, 80.0, 208.0, 6.0, 248.0, 1.0, - 16.0, 30.0, 26.0, 14.0, 200.0, 184.0, 184.0, 496.0, 124.0, 12.0, 13.0, - 8.0, 496.0, 1.0, 38.0, 24.0, 288.0, 48.0, 9.0, 22.0, 24.0, 9.0, - 192.0, 38.0, 8.0, 224.0, 160.0, 22.0, 48.0, 42.0, 256.0, 352.0, 64.0, - 16.0, 25.0, 25.0, 6.0, 40.0, 20.0, 256.0, 58.0, 42.0, 30.0, 104.0, - 1.0, 52.0, 136.0, 21.0, 256.0, 50.0, 12.0, 432.0, 72.0, 20.0, 40.0, - 13.0, 30.0, 108.0, 1.0, 40.0, 224.0, 3.0, 24.0, 108.0, 32.0, 76.0, - 24.0, 16.0, 216.0, 96.0, 168.0, 64.0, 16.0, 34.0, 31.0, 48.0, 384.0, - 208.0, 21.0, 30.0, 88.0, 128.0, 52.0, 112.0, 46.0, 16.0, 56.0, 50.0, - 16.0, 152.0, 28.0, 36.0, 14.0, 128.0, 80.0, 92.0, 128.0, 6.0, 28.0, - 22.0, 136.0, 48.0, 104.0, 496.0, 224.0, 136.0, 54.0, 14.0, 42.0, 58.0, - 48.0, 14.0, 2.0, 176.0, 48.0, 304.0, 124.0, 112.0, 60.0, 68.0, 0.0, - 480.0, 48.0, 32.0, 62.0, 64.0, 44.0, 22.0, 16.0, 88.0, 4.0, 22.0, - 272.0, 60.0, 0.0, 96.0, 32.0, 25.0, 29.0, 96.0, 40.0, 56.0, 32.0, - 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846.0, 992.0, 985.0, 756.0, 517.0, 564.0, 499.0, 632.0, 539.0, - 817.0, 641.0, 1041.0, 727.0, 667.0, 282.0, 284.0, 189.0, 302.0, - 361.0, 312.0, 186.0, 150.0, 332.0, 567.0, 900.0, 841.0, 599.0, - 479.0, 831.0, 749.0, 302.0, 473.0, 667.0, 866.0, 688.0, 638.0, - 445.0, 620.0, 481.0, 544.0, 1101.0, 1104.0, 1270.0, 484.0, 418.0, - 722.0, 807.0, 915.0, 375.0, 1018.0, 1378.0, 1748.0, 1634.0, 1186.0, - 907.0, 352.0, 582.0, 747.0, 838.0, 1023.0, 778.0, 854.0, 387.0, - 638.0, 536.0, 700.0, 484.0, 699.0, 762.0, 788.0, 809.0, 724.0, - 778.0, 812.0, 821.0, 713.0, 661.0, 593.0, 665.0, 922.0, 943.0, - 1269.0, 742.0, 1214.0, 1423.0, 2013.0, 1797.0, 1592.0, 1374.0, 1498.0, - 1333.0, 1050.0, 592.0, 413.0, 305.0, 761.0, 966.0, 928.0, 1162.0, - 1234.0, 1193.0, 522.0, 494.0, 470.0, 490.0, 177.0, 200.0, 427.0, - 505.0, 901.0, 611.0, 947.0, 556.0, 742.0, 323.0, 777.0, 642.0, - 997.0, 556.0, 546.0, 228.0, 407.0, 680.0, 759.0, 653.0, 372.0, - 825.0, 851.0, 582.0, 489.0, 560.0, 651.0, 663.0, 565.0, 318.0, - 505.0, 485.0, 610.0, 1493.0, 1416.0, 1326.0, 514.0, 508.0, 956.0, - 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697.0, 562.0, 822.0, 873.0, 1069.0, 1253.0, 1072.0, 896.0, 532.0, - 610.0, 879.0, 1245.0, 1047.0, 750.0, 612.0, 661.0, 835.0, 693.0, - 828.0, 688.0, 774.0, 681.0, 1031.0, 1283.0, 1152.0, 1214.0, 723.0, - 809.0, 792.0, 959.0, 1655.0, 1584.0, 1412.0, 604.0, 296.0, 908.0, - 1100.0, 1324.0, 694.0, 670.0, 374.0, 776.0, 780.0, 751.0, 753.0, - 607.0, 588.0, 222.0, 408.0, 527.0, 971.0, 1105.0, 1002.0, 788.0, - 714.0, 758.0, 642.0, 451.0, 513.0, 763.0, 836.0, 1377.0, 1053.0, - 1337.0, 850.0, 1172.0, 1082.0, 1197.0, 1210.0, 980.0, 565.0, 599.0, - 269.0, 208.0, 450.0, 850.0, 984.0, 847.0, 585.0, 456.0, 755.0, - 951.0, 1214.0, 914.0, 631.0, 341.0, 478.0, 447.0, 777.0, 733.0, - 979.0, 839.0, 698.0, 592.0, 514.0, 638.0, 716.0, 679.0, 1195.0, - 1259.0, 1484.0, 799.0, 787.0, 893.0, 990.0, 1176.0, 800.0, 1248.0, - 1184.0, 1714.0, 1302.0, 1222.0, 982.0, 886.0, 786.0, 658.0, 744.0, - 678.0, 760.0, 994.0, 1716.0, 2424.0, 2037.0, 1657.0, 726.0, 757.0, - 764.0, 917.0, 2049.0, 1956.0, 1955.0, 1025.0, 735.0, 724.0, 458.0, - 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735.0, 929.0, 1248.0, 1251.0, 1419.0, 1060.0, 1044.0, 561.0, 710.0, - 572.0, 518.0, 614.0, 698.0, 831.0, 873.0, 997.0, 1001.0, 785.0, - 1040.0, 931.0, 867.0, 443.0, 538.0, 618.0, 1066.0, 1318.0, 1265.0, - 691.0, 789.0, 777.0, 1311.0, 1171.0, 1217.0, 1069.0, 715.0, 724.0, - 380.0, 649.0, 607.0, 789.0, 954.0, 1078.0, 962.0, 926.0, 1034.0, - 1676.0, 1904.0, 2146.0, 1492.0, 1132.0, 1124.0, 965.0, 1139.0, 903.0, - 1724.0, 1740.0, 1908.0, 1436.0, 1131.0, 843.0, 1043.0, 868.0, 725.0, - 317.0, 317.0, 1022.0, 968.0, 1075.0, 875.0, 951.0, 1338.0, 918.0, - 848.0, 344.0, 724.0, 1012.0, 1137.0, 888.0, 504.0, 381.0, 886.0, - 1074.0, 1361.0, 1565.0, 1377.0, 1085.0, 477.0, 685.0, 893.0, 573.0, - 569.0, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-conv-3/gendata.py deleted file mode 100755 index ef83ab20..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/gendata.py +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env python3 - -import numpy as np - -K_DIM = 3 -IH = 100 -IW = 100 -OH = IH - K_DIM + 1 -OW = IW - K_DIM + 1 - -info = np.finfo(np.float32) -nmant = 5 # Limit precision to avoid rounding errors -maxmant = 1 << nmant -minexp = 0 -maxexp = 5 - - -# Generate floating-point values with exact mantissa and exponent -def randf(n): - return np.ldexp( - np.random.randint(maxmant, size=n), np.random.randint(minexp, maxexp, size=n) - ) - - -inputs = randf((IH, IW)).astype(np.float32) -weights = np.ones((K_DIM, K_DIM), dtype=np.float32) -outputs = np.full((OH, OW), np.float32(0.0)) - -# Convolution -for kh in range(K_DIM): - for kw in range(K_DIM): - outputs += inputs[kh : (kh + OH), kw : (kw + OW)] * weights[kh][kw] - -print( - """#define K_DIM {} -#define IH {} -#define IW {} -#define I_SIZE {} -#define OH {} -#define OW {} -#define O_SIZE {} - -""".format( - K_DIM, IH, IW, IH * IW, OH, OW, OH * OW - ) -) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=10): - print("{} {}[{}] = {{".format(data_type, name, data_size)) - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print_array("input_k", weights.flatten(), "K_DIM*K_DIM") -print_array("input_image", inputs.flatten(), "I_SIZE") -print_array("verify_data", outputs.flatten(), "O_SIZE") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/vec-conv.S b/bb-tests/workloads/src/CTest/rvv/vec-conv-3/vec-conv.S deleted file mode 100644 index c2e987a8..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/vec-conv.S +++ /dev/null @@ -1,212 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vectorized 2D 3x3 convolution -//-------------------------------------------------------------------------- - - .text - .balign 4 - - .global vec_conv -/* - * Calling convention: - * a0: size_t rows - * a1: size_t cols - * a2: size_t a_stride - * a3: size_t b_stride - * a4: const float *k - * a5: const float *a - * a6: float *b - */ - -#define rows a0 -#define cols a1 -#define a_stride a2 -#define b_stride a3 -#define k a4 -#define a a5 -#define b a6 - -#define ap t0 -#define bp t1 -#define vlen t2 -#define row_count t3 -#define VLEN_stride t4 -#define ap_4 t5 -#define ap_8 t6 - -#define row_check s0 -#define rows_odd s1 - -#define k0 ft0 -#define k1 ft1 -#define k2 ft2 -#define k3 ft3 -#define k4 ft4 -#define k5 ft5 -#define k6 ft6 -#define k7 ft7 -#define k8 ft8 - -#define vload0 v0 -#define vload1 v4 -#define vload2 v8 -#define vrow0 v16 -#define vrow1 v20 - -#define FRAMESIZE 32 - -vec_conv: - addi sp, sp, -FRAMESIZE - sd s0, 0(sp) - sd s1, 8(sp) - - # load the kernel into scalar registers - flw k0, 0(k) - flw k1, 4(k) - flw k2, 8(k) - flw k3, 12(k) - flw k4, 16(k) - flw k5, 20(k) - flw k6, 24(k) - flw k7, 28(k) - flw k8, 32(k) - - slli a_stride, a_stride, 2 - slli b_stride, b_stride, 2 - - mv row_check, rows - addi row_check, row_check, -2 - - andi rows_odd, rows, 1 - -# Prolog -loop_prolog: - mv ap, a - addi ap_4, ap, 4 - addi ap_8, ap, 8 - mv bp, b - mv row_count, row_check - - vsetvli vlen, cols, e32, m4, ta, ma - slli VLEN_stride, vlen, 2 - - # Load the first row and compute horizontal - vle32.v vload0, (ap) - vfmul.vf vrow0, vload0, k0 - vle32.v vload1, (ap_4) - vfmacc.vf vrow0, k1, vload1 - vle32.v vload2, (ap_8) - vfmacc.vf vrow0, k2, vload2 - - add ap, ap, a_stride - addi ap_4, ap, 4 - addi ap_8, ap, 8 - - # Load the second row and compute horizontal - vle32.v vload0, (ap) - vfmacc.vf vrow0, k3, vload0 - vle32.v vload1, (ap_4) - vfmacc.vf vrow0, k4, vload1 - vle32.v vload2, (ap_8) - vfmacc.vf vrow0, k5, vload2 - add ap, ap, a_stride - - # Load the third row - vfmul.vf vrow1, vload0, k0 - vle32.v vload0, (ap) - addi ap_4, ap, 4 - vfmacc.vf vrow1, k1, vload1 - vle32.v vload1, (ap_4) - vfmacc.vf vrow1, k2, vload2 - addi ap_8, ap, 8 - vle32.v vload2, (ap_8) - -# Main Loop -conv_loop: - vfmacc.vf vrow0, k6, vload0 - add ap, ap, a_stride - vfmacc.vf vrow0, k7, vload1 - addi ap_4, ap, 4 - vfmacc.vf vrow0, k8, vload2 - addi ap_8, ap, 8 - - vse32.v vrow0, (bp) - - vfmacc.vf vrow1, k3, vload0 - vfmacc.vf vrow1, k4, vload1 - vfmacc.vf vrow1, k5, vload2 - - vfmul.vf vrow0, vload0, k0 - vle32.v vload0, (ap) - vfmacc.vf vrow0, k1, vload1 - vle32.v vload1, (ap_4) - add bp, bp, b_stride - vfmacc.vf vrow0, k2, vload2 - - vle32.v vload2, (ap_8) - - vfmacc.vf vrow1, k6, vload0 - add ap, ap, a_stride - vfmacc.vf vrow1, k7, vload1 - addi ap_4, ap, 4 - vfmacc.vf vrow1, k8, vload2 - addi ap_8, ap, 8 - - vfmacc.vf vrow0, k3, vload0 - vfmacc.vf vrow0, k4, vload1 - vfmacc.vf vrow0, k5, vload2 - - vse32.v vrow1, (bp) - - vfmul.vf vrow1, vload0, k0 - vle32.v vload0, (ap) - vfmacc.vf vrow1, k1, vload1 - vle32.v vload1, (ap_4) - vfmacc.vf vrow1, k2, vload2 - vle32.v vload2, (ap_8) - - add bp, bp, b_stride - addi row_count, row_count, -2 - - bgtz row_count, conv_loop - -epilog: - vfmacc.vf vrow0, k6, vload0 - vfmacc.vf vrow0, k7, vload1 - vfmacc.vf vrow0, k8, vload2 - vse32.v vrow0, (bp) - - bnez rows_odd, row_loop_complete - - vfmacc.vf vrow1, k3, vload0 - vfmacc.vf vrow1, k4, vload1 - vfmacc.vf vrow1, k5, vload2 - - add ap, ap, a_stride - addi ap_4, ap, 4 - addi ap_8, ap, 8 - add bp, bp, b_stride - - vle32.v vload0, (ap) - vfmacc.vf vrow1, k6, vload0 - vle32.v vload1, (ap_4) - vfmacc.vf vrow1, k7, vload1 - vle32.v vload2, (ap_8) - vfmacc.vf vrow1, k8, vload2 - - vse32.v vrow1, (bp) - -row_loop_complete: - add a, a, VLEN_stride - add b, b, VLEN_stride - - sub cols, cols, vlen - bnez cols, loop_prolog - -exit: - ld s0, 0(sp) - ld s1, 8(sp) - addi sp, sp, FRAMESIZE - - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/vec-conv_main.c b/bb-tests/workloads/src/CTest/rvv/vec-conv-3/vec-conv_main.c deleted file mode 100644 index 619f0d00..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-conv-3/vec-conv_main.c +++ /dev/null @@ -1,39 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// 3x3 2D Convolution Benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized 2D 3x3 convolution implementation. - -#include "util.h" -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_conv(size_t, size_t, size_t, size_t, const float *, const float *, - float *); - -int main(int argc, char *argv[]) { - float results_data[O_SIZE] = {0}; - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_conv(OH, OW, IW, OW, input_k, input_image, results_data); - memset(results_data, 0, sizeof(results_data)); -#endif - - // Do the convolution - setStats(1); - vec_conv(OH, OW, IW, OW, input_k, input_image, results_data); - setStats(0); - - // Check the results - return verifyFloat(O_SIZE, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-cos/cos.c b/bb-tests/workloads/src/CTest/rvv/vec-cos/cos.c deleted file mode 100644 index a79a0405..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-cos/cos.c +++ /dev/null @@ -1,56 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include "cos.h" - -#define COS64_IMPL(m) \ - void cos_f64m##m##_bmark(double *angles, double *results, size_t len) { \ - size_t avl = len; \ - vfloat64m##m##_t cos_vec, res_vec; \ - \ - for (size_t vl = __riscv_vsetvl_e64m##m(avl); avl > 0; avl -= vl) { \ - vl = __riscv_vsetvl_e64m##m(avl); \ - cos_vec = __riscv_vle64_v_f64m##m(angles, vl); \ - res_vec = __cos_f64m##m(cos_vec, vl); \ - __riscv_vse64_v_f64m##m(results, res_vec, vl); \ - angles += vl; \ - results += vl; \ - } \ - } - -#define COS32_IMPL(m) \ - void cos_f32m##m##_bmark(float *angles, float *results, size_t len) { \ - size_t avl = len; \ - vfloat32m##m##_t cos_vec, res_vec; \ - \ - for (size_t vl = __riscv_vsetvl_e32m##m(avl); avl > 0; avl -= vl) { \ - vl = __riscv_vsetvl_e32m##m(avl); \ - cos_vec = __riscv_vle32_v_f32m##m(angles, vl); \ - res_vec = __cos_f32m##m(cos_vec, vl); \ - __riscv_vse32_v_f32m##m(results, res_vec, vl); \ - angles += vl; \ - results += vl; \ - } \ - } - -COS64_IMPL(1) -COS64_IMPL(2) -COS64_IMPL(4) -COS32_IMPL(1) -COS32_IMPL(2) -COS32_IMPL(4) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-cos/cos.h b/bb-tests/workloads/src/CTest/rvv/vec-cos/cos.h deleted file mode 100644 index a2839eda..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-cos/cos.h +++ /dev/null @@ -1,284 +0,0 @@ -// Modified version of: -// "RISC-V VECTOR COS FUNCTION Version by Cristóbal Ramírez Lazo, "Barcelona -// 2019"" Find details on the original version below Author: Matteo Perotti -// - -// RISC-V VECTOR COS FUNCTION Version by Cristóbal Ramírez Lazo, "Barcelona -// 2019" This RISC-V Vector implementation is based on the original code -// presented by Julien Pommier - -/* - AVX implementation of sin, cos, sincos, exp and log - Based on "sse_mathfun.h", by Julien Pommier - http://gruntthepeon.free.fr/ssemath/ - Copyright (C) 2012 Giovanni Garberoglio - Interdisciplinary Laboratory for Computational Science (LISC) - Fondazione Bruno Kessler and University of Trento - via Sommarive, 18 - I-38123 Trento (Italy) - This software is provided 'as-is', without any express or implied - warranty. In no event will the authors be held liable for any damages - arising from the use of this software. - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software - in a product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not be - misrepresented as being the original software. - 3. This notice may not be removed or altered from any source distribution. - (this is the zlib license) -*/ - -#include -#include -#include - -#define COS64_INLINE(m, md) \ - void cos_f64m##m##_bmark(double *angles, double *results, size_t len); \ - static inline vfloat64m##m##_t __cos_f64m##m(vfloat64m##m##_t x, \ - size_t gvl) { \ - int64_t _ps_inv_sign_mask = ~0x8000000000000000; \ - double _ps_cephes_FOPI = 1.27323954473516; /* 4 / M_PI */ \ - int64_t _pi32_1 = 1; \ - int64_t _pi32_inv1 = ~0x0000000000000001; \ - int64_t _pi32_2 = 2; \ - int64_t _pi32_4 = 4; \ - int64_t _Zero = 0; \ - \ - vfloat64m##m##_t xmm2; \ - vfloat64m##m##_t xmm1; \ - vfloat64m##m##_t xmm3; \ - vfloat64m##m##_t y; \ - \ - vint64m##m##_t emm0; \ - vint64m##m##_t emm2; \ - \ - vbool##md##_t xMask; \ - /* take the absolute value */ \ - vint64m##m##_t xf = __riscv_vreinterpret_v_f64m##m##_i64m##m(x); \ - vint64m##m##_t xa = __riscv_vand_vx_i64m##m(xf, _ps_inv_sign_mask, gvl); \ - x = __riscv_vreinterpret_v_i64m##m##_f64m##m(xa); \ - \ - /* scale by 4/Pi */ \ - y = __riscv_vfmul_vf_f64m##m(x, _ps_cephes_FOPI, gvl); \ - \ - /* store the integer part of y in mm0 */ \ - emm2 = __riscv_vfcvt_x_f_v_i64m##m(y, gvl); \ - \ - /* j=(j+1) & (~1) (see the cephes sources) */ \ - emm2 = __riscv_vadd_vx_i64m##m(emm2, _pi32_1, gvl); \ - emm2 = __riscv_vand_vx_i64m##m(emm2, _pi32_inv1, gvl); \ - y = __riscv_vfcvt_f_x_v_f64m##m(emm2, gvl); \ - \ - emm2 = __riscv_vsub_vx_i64m##m(emm2, _pi32_2, gvl); \ - \ - /* get the swap sign flag */ \ - emm0 = __riscv_vxor_vx_i64m##m(emm2, 0xffffffffffffffff, gvl); \ - emm0 = __riscv_vand_vx_i64m##m(emm0, _pi32_4, gvl); \ - \ - emm0 = __riscv_vsll_vx_i64m##m(emm0, 61, gvl); \ - \ - /* get the polynom selection mask */ \ - emm2 = __riscv_vand_vx_i64m##m(emm2, _pi32_2, gvl); \ - xMask = __riscv_vmseq_vx_i64m##m##_b##md(emm2, _Zero, gvl); \ - vint64m##m##_t zv = __riscv_vmv_v_x_i64m##m(_Zero, gvl); \ - emm2 = __riscv_vmerge_vxm_i64m##m(zv, 0xffffffffffffffff, xMask, gvl); \ - \ - vfloat64m##m##_t sign_bit = \ - __riscv_vreinterpret_v_i64m##m##_f64m##m(emm0); \ - vfloat64m##m##_t poly_mask = \ - __riscv_vreinterpret_v_i64m##m##_f64m##m(emm2); \ - \ - /* The magic pass: "Extended precision modular arithmetic" \ - x = ((x - y * DP1) - y * DP2) - y * DP3; */ \ - \ - double _ps_minus_cephes_DP1 = -0.78515625; \ - double _ps_minus_cephes_DP2 = -2.4187564849853515625E-4; \ - double _ps_minus_cephes_DP3 = -3.77489497744594108E-8; \ - \ - x = __riscv_vfmacc_vf_f64m##m(x, _ps_minus_cephes_DP1, y, gvl); \ - x = __riscv_vfmacc_vf_f64m##m(x, _ps_minus_cephes_DP2, y, gvl); \ - x = __riscv_vfmacc_vf_f64m##m(x, _ps_minus_cephes_DP3, y, gvl); \ - \ - /* Evaluate the first polynom (0 <= x <= Pi/4) */ \ - double _ps_coscof_p0 = 2.443315711809948E-005; \ - double _ps_coscof_p1 = -1.388731625493765E-003; \ - double _ps_coscof_p2 = 4.166664568298827E-002; \ - double _ps_0p5 = 0.5f; \ - \ - vfloat64m##m##_t z; \ - vfloat64m##m##_t tmp; \ - \ - z = __riscv_vfmul_vv_f64m##m(x, x, gvl); \ - \ - vfloat64m##m##_t vcp1 = __riscv_vfmv_v_f_f64m##m(_ps_coscof_p1, gvl); \ - vfloat64m##m##_t vcp2 = __riscv_vfmv_v_f_f64m##m(_ps_coscof_p2, gvl); \ - y = __riscv_vfmacc_vf_f64m##m(vcp1, _ps_coscof_p0, y, gvl); \ - y = __riscv_vfmacc_vv_f64m##m(vcp2, z, y, gvl); \ - y = __riscv_vfmul_vv_f64m##m(y, z, gvl); \ - y = __riscv_vfmul_vv_f64m##m(y, z, gvl); \ - y = __riscv_vfnmsub_vf_f64m##m(y, _ps_0p5, z, gvl); \ - y = __riscv_vfadd_vf_f64m##m(y, 1.0, gvl); \ - \ - /* Evaluate the second polynom (Pi/4 <= x <= 0) */ \ - double _ps_sincof_p0 = -1.9515295891E-4; \ - double _ps_sincof_p1 = 8.3321608736E-3; \ - double _ps_sincof_p2 = -1.6666654611E-1; \ - vfloat64m##m##_t y2; \ - \ - vfloat64m##m##_t vsp1 = __riscv_vfmv_v_f_f64m##m(_ps_sincof_p1, gvl); \ - vfloat64m##m##_t vsp2 = __riscv_vfmv_v_f_f64m##m(_ps_sincof_p2, gvl); \ - y2 = __riscv_vfmacc_vf_f64m##m(vsp1, _ps_sincof_p0, z, gvl); \ - y2 = __riscv_vfmacc_vv_f64m##m(vsp2, z, y2, gvl); \ - y2 = __riscv_vfmul_vv_f64m##m(y2, z, gvl); \ - y2 = __riscv_vfmacc_vv_f64m##m(x, y2, x, gvl); \ - \ - /* select the correct result from the two polynoms */ \ - xmm3 = poly_mask; \ - vint64m##m##_t t1 = __riscv_vreinterpret_v_f64m##m##_i64m##m(xmm3); \ - vint64m##m##_t t2 = __riscv_vreinterpret_v_f64m##m##_i64m##m(y2); \ - vint64m##m##_t t3 = __riscv_vreinterpret_v_f64m##m##_i64m##m(y); \ - vint64m##m##_t t4 = __riscv_vxor_vx_i64m##m(t1, 0xffffffffffffffff, gvl); \ - vint64m##m##_t at1t2 = __riscv_vand_vv_i64m##m(t1, t2, gvl); \ - vint64m##m##_t at3t4 = __riscv_vand_vv_i64m##m(t3, t4, gvl); \ - y2 = __riscv_vreinterpret_v_i64m##m##_f64m##m(at1t2); \ - y = __riscv_vreinterpret_v_i64m##m##_f64m##m(at3t4); \ - y = __riscv_vfadd_vv_f64m##m(y, y2, gvl); \ - /* update the sign */ \ - t1 = __riscv_vreinterpret_v_f64m##m##_i64m##m(y); \ - t2 = __riscv_vreinterpret_v_f64m##m##_i64m##m(sign_bit); \ - vint64m##m##_t xt1t2 = __riscv_vxor_vv_i64m##m(t1, t2, gvl); \ - y = __riscv_vreinterpret_v_i64m##m##_f64m##m(xt1t2); \ - \ - return y; \ - } - -#define COS32_INLINE(m, md) \ - void cos_f32m##m##_bmark(float *angles, float *results, size_t len); \ - static inline vfloat32m##m##_t __cos_f32m##m(vfloat32m##m##_t x, \ - size_t gvl) { \ - int32_t _ps_inv_sign_mask = ~0x80000000; \ - float _ps_cephes_FOPI = 1.27323954473516; /* 4 / M_PI */ \ - int32_t _pi32_1 = 1; \ - int32_t _pi32_inv1 = ~0x00000001; \ - int32_t _pi32_2 = 2; \ - int32_t _pi32_4 = 4; \ - int32_t _Zero = 0; \ - \ - vfloat32m##m##_t xmm2; \ - vfloat32m##m##_t xmm1; \ - vfloat32m##m##_t xmm3; \ - vfloat32m##m##_t y; \ - \ - vint32m##m##_t emm0; \ - vint32m##m##_t emm2; \ - \ - vbool##md##_t xMask; \ - /* take the absolute value */ \ - vint32m##m##_t xf = __riscv_vreinterpret_v_f32m##m##_i32m##m(x); \ - vint32m##m##_t xa = __riscv_vand_vx_i32m##m(xf, _ps_inv_sign_mask, gvl); \ - x = __riscv_vreinterpret_v_i32m##m##_f32m##m(xa); \ - \ - /* scale by 4/Pi */ \ - y = __riscv_vfmul_vf_f32m##m(x, _ps_cephes_FOPI, gvl); \ - \ - /* store the integer part of y in mm0 */ \ - emm2 = __riscv_vfcvt_x_f_v_i32m##m(y, gvl); \ - \ - /* j=(j+1) & (~1) (see the cephes sources) */ \ - emm2 = __riscv_vadd_vx_i32m##m(emm2, _pi32_1, gvl); \ - emm2 = __riscv_vand_vx_i32m##m(emm2, _pi32_inv1, gvl); \ - y = __riscv_vfcvt_f_x_v_f32m##m(emm2, gvl); \ - \ - emm2 = __riscv_vsub_vx_i32m##m(emm2, _pi32_2, gvl); \ - \ - /* get the swap sign flag */ \ - emm0 = __riscv_vxor_vx_i32m##m(emm2, 0xffffffff, gvl); \ - emm0 = __riscv_vand_vx_i32m##m(emm0, _pi32_4, gvl); \ - \ - emm0 = __riscv_vsll_vx_i32m##m(emm0, 61, gvl); \ - \ - /* get the polynom selection mask */ \ - emm2 = __riscv_vand_vx_i32m##m(emm2, _pi32_2, gvl); \ - xMask = __riscv_vmseq_vx_i32m##m##_b##md(emm2, _Zero, gvl); \ - vint32m##m##_t zv = __riscv_vmv_v_x_i32m##m(_Zero, gvl); \ - emm2 = __riscv_vmerge_vxm_i32m##m(zv, 0xffffffff, xMask, gvl); \ - \ - vfloat32m##m##_t sign_bit = \ - __riscv_vreinterpret_v_i32m##m##_f32m##m(emm0); \ - vfloat32m##m##_t poly_mask = \ - __riscv_vreinterpret_v_i32m##m##_f32m##m(emm2); \ - \ - /* The magic pass: "Extended precision modular arithmetic" \ - x = ((x - y * DP1) - y * DP2) - y * DP3; */ \ - \ - float _ps_minus_cephes_DP1 = -0.78515625; \ - float _ps_minus_cephes_DP2 = -2.4187532849853515625E-4; \ - float _ps_minus_cephes_DP3 = -3.77489497744594108E-8; \ - \ - x = __riscv_vfmacc_vf_f32m##m(x, _ps_minus_cephes_DP1, y, gvl); \ - x = __riscv_vfmacc_vf_f32m##m(x, _ps_minus_cephes_DP2, y, gvl); \ - x = __riscv_vfmacc_vf_f32m##m(x, _ps_minus_cephes_DP3, y, gvl); \ - \ - /* Evaluate the first polynom (0 <= x <= Pi/4) */ \ - float _ps_coscof_p0 = 2.443315711809948E-005; \ - float _ps_coscof_p1 = -1.388731625493765E-003; \ - float _ps_coscof_p2 = 4.166632568298827E-002; \ - float _ps_0p5 = 0.5f; \ - \ - vfloat32m##m##_t z; \ - vfloat32m##m##_t tmp; \ - \ - z = __riscv_vfmul_vv_f32m##m(x, x, gvl); \ - \ - vfloat32m##m##_t vcp1 = __riscv_vfmv_v_f_f32m##m(_ps_coscof_p1, gvl); \ - vfloat32m##m##_t vcp2 = __riscv_vfmv_v_f_f32m##m(_ps_coscof_p2, gvl); \ - y = __riscv_vfmacc_vf_f32m##m(vcp1, _ps_coscof_p0, y, gvl); \ - y = __riscv_vfmacc_vv_f32m##m(vcp2, z, y, gvl); \ - y = __riscv_vfmul_vv_f32m##m(y, z, gvl); \ - y = __riscv_vfmul_vv_f32m##m(y, z, gvl); \ - y = __riscv_vfnmsub_vf_f32m##m(y, _ps_0p5, z, gvl); \ - y = __riscv_vfadd_vf_f32m##m(y, 1.0, gvl); \ - \ - /* Evaluate the second polynom (Pi/4 <= x <= 0) */ \ - float _ps_sincof_p0 = -1.9515295891E-4; \ - float _ps_sincof_p1 = 8.3321608736E-3; \ - float _ps_sincof_p2 = -1.6666654611E-1; \ - vfloat32m##m##_t y2; \ - \ - vfloat32m##m##_t vsp1 = __riscv_vfmv_v_f_f32m##m(_ps_sincof_p1, gvl); \ - vfloat32m##m##_t vsp2 = __riscv_vfmv_v_f_f32m##m(_ps_sincof_p2, gvl); \ - y2 = __riscv_vfmacc_vf_f32m##m(vsp1, _ps_sincof_p0, z, gvl); \ - y2 = __riscv_vfmacc_vv_f32m##m(vsp2, z, y2, gvl); \ - y2 = __riscv_vfmul_vv_f32m##m(y2, z, gvl); \ - y2 = __riscv_vfmacc_vv_f32m##m(x, y2, x, gvl); \ - \ - /* select the correct result from the two polynoms */ \ - xmm3 = poly_mask; \ - vint32m##m##_t t1 = __riscv_vreinterpret_v_f32m##m##_i32m##m(xmm3); \ - vint32m##m##_t t2 = __riscv_vreinterpret_v_f32m##m##_i32m##m(y2); \ - vint32m##m##_t t3 = __riscv_vreinterpret_v_f32m##m##_i32m##m(y); \ - vint32m##m##_t t4 = __riscv_vxor_vx_i32m##m(t1, 0xffffffff, gvl); \ - vint32m##m##_t at1t2 = __riscv_vand_vv_i32m##m(t1, t2, gvl); \ - vint32m##m##_t at3t4 = __riscv_vand_vv_i32m##m(t3, t4, gvl); \ - y2 = __riscv_vreinterpret_v_i32m##m##_f32m##m(at1t2); \ - y = __riscv_vreinterpret_v_i32m##m##_f32m##m(at3t4); \ - y = __riscv_vfadd_vv_f32m##m(y, y2, gvl); \ - /* update the sign */ \ - t1 = __riscv_vreinterpret_v_f32m##m##_i32m##m(y); \ - t2 = __riscv_vreinterpret_v_f32m##m##_i32m##m(sign_bit); \ - vint32m##m##_t xt1t2 = __riscv_vxor_vv_i32m##m(t1, t2, gvl); \ - y = __riscv_vreinterpret_v_i32m##m##_f32m##m(xt1t2); \ - \ - return y; \ - } - -COS64_INLINE(1, 64) -COS64_INLINE(2, 32) -COS64_INLINE(4, 16) -COS32_INLINE(1, 32) -COS32_INLINE(2, 16) -COS32_INLINE(4, 8) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-cos/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-cos/gen_data.py deleted file mode 100644 index 82914e15..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-cos/gen_data.py +++ /dev/null @@ -1,71 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: vector size, arg2: filter size - -import random as rand -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -def rand_matrix(N, dtype): - return np.random.rand(N).astype(dtype) - - -# SCRIPT - -if len(sys.argv) == 2: - N_f64 = int(sys.argv[1]) - N_f32 = 2 * N_f64 -else: - print("Error. Give me one argument: the number of vector elements.") - sys.exit() - -# Vector of samples -angles_f64 = rand_matrix(N_f64, np.float64).astype(np.float64) -angles_f32 = rand_matrix(N_f32, np.float32).astype(np.float32) - -# Results buffer -results_f64 = np.zeros(N_f64, dtype=np.float64) -results_f32 = np.zeros(N_f32, dtype=np.float32) - -# Gold results -gold_results_f64 = np.cos(angles_f64, dtype=np.float64) -gold_results_f32 = np.cos(angles_f32, dtype=np.float32) - -# Create the file -print('.section .data,"aw",@progbits') -emit("N_f64", np.array(N_f64, dtype=np.uint64)) -emit("angles_f64", angles_f64, "32") -emit("results_f64", results_f64, "32") -emit("gold_results_f64", gold_results_f64, "32") -emit("N_f32", np.array(N_f32, dtype=np.uint32)) -emit("angles_f32", angles_f32, "32") -emit("results_f32", results_f32, "32") -emit("gold_results_f32", gold_results_f32, "32") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-cos/main.c b/bb-tests/workloads/src/CTest/rvv/vec-cos/main.c deleted file mode 100644 index b3cba5e2..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-cos/main.c +++ /dev/null @@ -1,190 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include -#include -#include - -#include "ara/util.h" -#include "cos.h" -#include "util.h" - -#define N_F64 (512) -extern size_t N_f64; -extern double angles_f64[] __attribute__((aligned(16))); -extern double results_f64[] __attribute__((aligned(16))); -extern double gold_results_f64[] __attribute__((aligned(16))); -double results_f64m1[N_F64] __attribute__((aligned(16))); -double results_f64m2[N_F64] __attribute__((aligned(16))); -double results_f64m4[N_F64] __attribute__((aligned(16))); - -#define N_F32 (1024) -extern size_t N_f32; -extern float angles_f32[] __attribute__((aligned(16))); -extern float results_f32[] __attribute__((aligned(16))); -extern float gold_results_f32[] __attribute__((aligned(16))); -float results_f32m1[N_F32] __attribute__((aligned(16))); -float results_f32m2[N_F32] __attribute__((aligned(16))); -float results_f32m4[N_F32] __attribute__((aligned(16))); - -#define THRESHOLD 0.3 - -int check64(double *results) { - int error = 0; - for (uint64_t i = 0; i < N_f64; ++i) { - if (!similarity_check(results[i], gold_results_f64[i], THRESHOLD)) { - error = 1; - printf("64-bit error at index %d. %lx != %lx\n", i, - *(uint64_t *)(&results[i]), *(uint64_t *)(&gold_results_f64[i])); - } - } - return error; -} - -int check32(float *results) { - int error = 0; - for (uint64_t i = 0; i < N_f32; ++i) { - if (!similarity_check(results[i], gold_results_f32[i], THRESHOLD)) { - error = 1; - printf("32-bit error at index %d. %x != %x\n", i, - *(uint32_t *)(&results[i]), *(uint32_t *)(&gold_results_f32[i])); - } - } - return error; -} - -int main() { - if (N_F64 != N_f64 || N_F32 != N_f32) - exit(1); - - printf("FCOS\n"); - - int error = 0; - unsigned long cycles1, cycles2, instr2, instr1; - - if (N_f32 >= 256) { - for (size_t t = 8; t <= 256; t += 31) { - /* cycles1 = read_csr(mcycle); */ - /* cos_f32m1_bmark(angles_f32, results_f32m1, t); */ - /* asm volatile("fence"); */ - /* cycles2 = read_csr(mcycle); */ - /* printf("32b LMUL=1 n=%ld cycles=%ld\n", t, cycles2 - cycles1); */ - - cycles1 = read_csr(mcycle); - cos_f32m2_bmark(angles_f32, results_f32m2, t); - asm volatile("fence"); - cycles2 = read_csr(mcycle); - printf("32b LMUL=2 n=%ld cycles=%ld\n", t, cycles2 - cycles1); - - /* cycles1 = read_csr(mcycle); */ - /* cos_f32m4_bmark(angles_f32, results_f32m4, t); */ - /* asm volatile("fence"); */ - /* cycles2 = read_csr(mcycle); */ - /* printf("32b LMUL=4 n=%ld cycles=%ld\n", t, cycles2 - cycles1); */ - } - } - - printf("Executing cosine on %d 64-bit data LMUL1...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - cos_f64m1_bmark(angles_f64, results_f64m1, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles %ld instructions.\n", cycles2 - cycles1, - instr2 - instr1); - - printf("Executing cosine on %d 64-bit data LMUL2...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - cos_f64m2_bmark(angles_f64, results_f64m2, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles %ld instructions.\n", cycles2 - cycles1, - instr2 - instr1); - - printf("Executing cosine on %d 64-bit data LMUL4...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - cos_f64m4_bmark(angles_f64, results_f64m4, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles %ld instructions.\n", cycles2 - cycles1, - instr2 - instr1); - - printf("Executing cosine on %d 32-bit data LMUL1...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - cos_f32m1_bmark(angles_f32, results_f32m1, N_f32); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles %ld instructions.\n", cycles2 - cycles1, - instr2 - instr1); - - printf("Executing cosine on %d 32-bit data LMUL2...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - cos_f32m2_bmark(angles_f32, results_f32m2, N_f32); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles %ld instructions.\n", cycles2 - cycles1, - instr2 - instr1); - - printf("Executing cosine on %d 32-bit data LMUL4...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - cos_f32m4_bmark(angles_f32, results_f32m4, N_f32); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles %ld instructions.\n", cycles2 - cycles1, - instr2 - instr1); - - printf("Checking results:\n"); - - error = check64(results_f64m1); - if (error) { - return error; - } - error = check64(results_f64m2); - if (error) { - return error; - } - error = check64(results_f64m4); - if (error) { - return error; - } - error = check32(results_f32m1); - if (error) { - return error; - } - error = check32(results_f32m2); - if (error) { - return error; - } - error = check32(results_f32m4); - if (error) { - return error; - } - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-div-approx/dataset1.h deleted file mode 100644 index 6f0afd6a..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/dataset1.h +++ /dev/null @@ -1,322 +0,0 @@ - -#define DATA_SIZE 3000 - -float input1_data[DATA_SIZE] = { - 2, 41, 28, 9, 37, 17, 6, 47, 29, 40, 31, 0, 46, 44, 19, 34, 48, 5, 5, - 14, 21, 15, 33, 38, 15, 33, 43, 18, 23, 46, 27, 28, 10, 14, 37, 30, 25, 32, - 9, 4, 13, 11, 16, 47, 45, 12, 45, 41, 46, 49, 9, 48, 28, 17, 32, 32, 9, - 5, 42, 3, 14, 17, 7, 45, 44, 13, 28, 49, 38, 12, 23, 25, 20, 11, 22, 36, - 33, 15, 11, 46, 14, 5, 30, 30, 19, 17, 22, 13, 18, 17, 29, 3, 49, 20, 17, - 25, 27, 45, 38, 12, 38, 29, 7, 1, 6, 47, 46, 40, 27, 21, 32, 47, 14, 0, - 2, 4, 4, 22, 29, 30, 19, 14, 40, 48, 41, 17, 22, 25, 48, 17, 40, 44, 26, - 47, 35, 17, 28, 44, 1, 28, 33, 21, 21, 7, 0, 4, 12, 2, 21, 39, 43, 24, - 20, 18, 27, 25, 44, 34, 14, 13, 24, 14, 44, 10, 36, 34, 12, 39, 27, 15, 26, - 27, 16, 47, 14, 41, 15, 39, 36, 48, 18, 36, 14, 48, 32, 37, 4, 18, 5, 5, - 19, 32, 41, 42, 17, 7, 2, 7, 47, 17, 26, 37, 26, 41, 29, 0, 8, 3, 6, - 6, 37, 18, 47, 1, 6, 5, 42, 21, 12, 13, 20, 31, 19, 27, 37, 28, 8, 0, - 36, 25, 38, 2, 37, 4, 10, 42, 7, 38, 17, 47, 46, 16, 24, 22, 25, 32, 13, - 39, 5, 42, 45, 13, 11, 1, 39, 28, 17, 40, 40, 37, 14, 4, 22, 22, 35, 22, - 2, 12, 18, 25, 35, 43, 24, 37, 25, 35, 2, 18, 43, 47, 49, 26, 36, 21, 11, - 24, 34, 1, 17, 12, 17, 12, 28, 39, 37, 25, 41, 41, 8, 8, 33, 1, 10, 7, - 42, 4, 19, 5, 42, 5, 7, 0, 38, 10, 9, 28, 10, 26, 8, 11, 34, 37, 35, - 2, 4, 40, 44, 25, 18, 24, 0, 31, 4, 5, 39, 46, 32, 44, 41, 12, 23, 5, - 28, 26, 0, 49, 45, 19, 20, 5, 27, 46, 25, 20, 15, 10, 21, 30, 17, 26, 34, - 1, 9, 15, 5, 13, 19, 12, 24, 5, 34, 45, 38, 32, 4, 8, 20, 47, 1, 38, - 43, 5, 7, 3, 7, 41, 42, 21, 7, 10, 40, 41, 28, 18, 30, 24, 40, 45, 7, - 21, 40, 9, 27, 42, 22, 39, 43, 39, 40, 37, 5, 20, 12, 49, 6, 36, 29, 39, - 20, 26, 35, 27, 18, 38, 48, 11, 47, 11, 8, 25, 5, 35, 39, 7, 15, 39, 31, - 28, 5, 0, 26, 40, 1, 29, 37, 30, 38, 23, 2, 47, 39, 49, 41, 15, 3, 41, - 49, 37, 8, 41, 31, 7, 41, 2, 34, 4, 11, 37, 37, 13, 6, 36, 47, 21, 18, - 16, 13, 27, 38, 37, 45, 0, 0, 45, 49, 40, 28, 43, 48, 14, 25, 27, 48, 20, - 29, 14, 12, 42, 6, 22, 35, 4, 33, 9, 12, 16, 39, 32, 0, 16, 49, 32, 37, - 47, 10, 7, 9, 15, 8, 38, 48, 32, 28, 31, 21, 13, 28, 27, 24, 49, 37, 10, - 18, 46, 33, 1, 26, 23, 45, 10, 1, 10, 18, 44, 39, 34, 35, 34, 47, 19, 2, - 5, 23, 19, 33, 16, 47, 23, 23, 36, 35, 46, 26, 43, 3, 27, 45, 42, 7, 49, - 11, 5, 18, 4, 2, 4, 22, 38, 15, 16, 34, 38, 36, 16, 14, 26, 31, 29, 44, - 3, 14, 24, 36, 22, 27, 6, 32, 41, 14, 38, 8, 20, 24, 49, 5, 30, 43, 11, - 14, 28, 45, 28, 9, 12, 39, 49, 36, 17, 21, 30, 38, 8, 15, 16, 17, 15, 35, - 2, 24, 25, 5, 19, 13, 15, 3, 17, 49, 30, 45, 19, 4, 27, 13, 33, 17, 42, - 43, 15, 5, 26, 28, 41, 18, 49, 23, 45, 9, 13, 8, 38, 1, 42, 32, 0, 39, - 45, 42, 6, 49, 35, 28, 35, 12, 39, 7, 9, 12, 22, 45, 0, 16, 30, 15, 8, - 8, 6, 41, 35, 27, 11, 4, 31, 16, 46, 5, 0, 48, 7, 8, 29, 18, 19, 29, - 37, 18, 43, 29, 27, 22, 17, 29, 14, 45, 27, 18, 22, 39, 5, 24, 44, 40, 35, - 27, 17, 1, 41, 31, 27, 30, 48, 5, 15, 45, 48, 30, 39, 8, 44, 25, 45, 21, - 17, 7, 11, 5, 29, 41, 6, 47, 10, 24, 19, 39, 23, 38, 28, 24, 16, 36, 22, - 41, 37, 0, 29, 13, 6, 34, 37, 27, 42, 25, 18, 25, 45, 12, 12, 19, 21, 10, - 12, 26, 20, 8, 15, 31, 29, 26, 34, 7, 37, 40, 22, 3, 4, 8, 0, 42, 24, - 16, 3, 2, 5, 0, 17, 36, 34, 14, 48, 4, 31, 45, 30, 43, 37, 37, 23, 30, - 25, 45, 40, 14, 48, 6, 29, 27, 43, 49, 13, 31, 32, 31, 49, 19, 16, 23, 8, - 12, 9, 43, 11, 17, 7, 41, 16, 19, 42, 1, 20, 30, 27, 10, 0, 39, 44, 40, - 41, 33, 20, 4, 12, 21, 10, 33, 0, 18, 21, 3, 2, 37, 40, 25, 21, 16, 16, - 11, 20, 23, 34, 28, 15, 22, 29, 6, 44, 19, 46, 13, 5, 45, 2, 47, 18, 19, - 12, 11, 33, 1, 49, 22, 10, 19, 0, 31, 2, 30, 46, 47, 41, 23, 31, 40, 26, - 33, 2, 15, 17, 2, 48, 37, 20, 44, 43, 28, 8, 36, 0, 32, 25, 48, 39, 42, - 12, 31, 40, 39, 21, 44, 30, 34, 32, 4, 35, 39, 5, 29, 0, 46, 30, 32, 18, - 13, 11, 30, 34, 27, 5, 28, 37, 1, 15, 48, 28, 19, 38, 33, 25, 10, 44, 45, - 21, 36, 25, 1, 11, 39, 35, 22, 34, 34, 23, 40, 16, 30, 12, 5, 17, 14, 36, - 14, 45, 32, 31, 46, 11, 34, 18, 43, 32, 20, 47, 33, 42, 39, 19, 35, 21, 26, - 34, 1, 7, 2, 38, 6, 27, 40, 12, 10, 10, 28, 44, 47, 30, 32, 21, 45, 48, - 32, 34, 32, 13, 13, 48, 40, 41, 6, 23, 23, 31, 14, 20, 15, 11, 31, 14, 25, - 1, 33, 16, 28, 44, 15, 20, 0, 9, 46, 10, 26, 2, 26, 41, 17, 16, 11, 43, - 18, 7, 49, 19, 42, 24, 29, 0, 24, 36, 47, 34, 43, 7, 31, 13, 2, 12, 24, - 44, 10, 11, 16, 6, 32, 21, 16, 2, 33, 25, 38, 11, 32, 4, 13, 35, 9, 24, - 47, 4, 11, 42, 16, 37, 2, 4, 44, 13, 9, 36, 26, 38, 48, 30, 0, 28, 6, - 47, 14, 30, 6, 5, 8, 29, 20, 17, 12, 31, 25, 40, 44, 47, 7, 44, 8, 48, - 46, 16, 39, 41, 5, 38, 37, 34, 32, 49, 9, 39, 1, 32, 38, 44, 40, 13, 22, - 48, 18, 3, 46, 45, 26, 12, 13, 44, 32, 10, 15, 14, 40, 28, 17, 48, 24, 30, - 5, 6, 21, 22, 1, 3, 1, 12, 13, 44, 21, 27, 31, 35, 38, 14, 13, 5, 4, - 31, 40, 42, 36, 19, 38, 6, 8, 42, 9, 29, 46, 12, 11, 3, 9, 21, 37, 37, - 43, 2, 42, 38, 31, 24, 8, 23, 23, 30, 46, 0, 31, 14, 46, 15, 22, 35, 35, - 31, 22, 39, 30, 11, 26, 39, 36, 14, 36, 40, 8, 44, 22, 47, 30, 40, 25, 37, - 40, 31, 47, 47, 2, 17, 9, 39, 35, 14, 13, 38, 32, 10, 13, 15, 47, 47, 30, - 41, 31, 26, 12, 20, 13, 45, 39, 39, 26, 24, 15, 9, 19, 36, 45, 39, 23, 41, - 18, 5, 11, 42, 42, 27, 42, 15, 41, 21, 8, 23, 41, 15, 10, 7, 5, 31, 6, - 31, 21, 45, 30, 49, 27, 24, 11, 16, 42, 26, 6, 10, 34, 39, 8, 31, 4, 24, - 4, 23, 26, 15, 38, 35, 26, 23, 45, 48, 34, 16, 8, 21, 7, 0, 5, 37, 15, - 34, 25, 2, 1, 3, 31, 42, 12, 26, 24, 34, 13, 48, 27, 25, 47, 34, 42, 16, - 11, 4, 36, 16, 35, 49, 22, 44, 34, 5, 9, 17, 31, 18, 2, 43, 34, 36, 9, - 19, 25, 48, 28, 36, 34, 2, 2, 4, 45, 24, 21, 38, 22, 2, 31, 20, 31, 7, - 22, 18, 49, 48, 36, 36, 23, 34, 14, 34, 21, 18, 36, 36, 18, 37, 22, 15, 13, - 16, 25, 25, 44, 27, 7, 16, 39, 3, 18, 42, 21, 4, 46, 4, 26, 31, 17, 28, - 28, 49, 25, 6, 46, 38, 14, 11, 28, 35, 19, 29, 33, 11, 30, 36, 37, 41, 2, - 36, 12, 33, 22, 29, 23, 33, 4, 16, 46, 10, 38, 43, 41, 22, 16, 30, 43, 14, - 34, 5, 10, 27, 33, 7, 22, 17, 38, 27, 28, 36, 37, 29, 38, 23, 20, 42, 42, - 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26, 33, 30, 44, 38, 6, 24, 1, 44, 11, 1, 48, 43, 15, 8, 39, 9, 26, 11, - 23, 18, 24, 24, 21, 8, 15, 11, 42, 22, 10, 17, 37, 12, 46, 4, 38, 34, 30, - 15, 20, 19, 26, 39, 22, 14, 16, 17, 7, 49, 37, 40, 8, 42, 33, 19, 7, 7, - 3, 34, 5, 38, 31, 31, 12, 3, 5, 47, 3, 23, 34, 43, 11, 34, 14, 12, 40, - 22, 14, 2, 44, 17, 21, 44, 9, 19, 34, 42, 2, 27, 37, 34, 17, 1, 25, 4, - 46, 44, 44, 47, 20, 26, 47, 11, 39, 32, 1, 13, 35, 26, 43, 8, 17, 43, 15, - 0, 14, 4, 47, 4, 27, 28, 49, 6, 11, 10, 28, 18, 41, 38, 15, 12, 16, 35, - 27, 22, 39, 14, 31, 27, 34, 28, 9, 9, 45, 19, 33, 28, 33, 2, 47, 26, 45, - 1, 27, 6, 6, 7, 15, 40, 28, 2, 15, 3, 35, 13, 35, 33, 19, 29, 0, 10, - 46, 13, 36, 10, 21, 35, 15, 7, 4, 46, 32, 24, 42, 39, 27, 14, 18, 39, 23, - 1, 19, 19, 22, 37, 26, 45, 35, 34, 32, 23, 8, 34, 16, 37, 22, 5, 42, 14, - 49, 9, 7, 29, 42, 16, 28, 20, 8, 5, 41, 39, 43, 39, 20, 16, 40, 3, 30, - 6, 41, 26, 46, 2, 23, 34, 25, 41, 13, 3, 4, 19, 45, 44, 37, 2, 48, 36, - 42, 48, 28, 33, 42, 10, 21, 8, 4, 46, 10, 34, 44, 41, 43, 19, 41, 7, 5, - 33, 24, 16, 35, 17, 5, 17, 31, 18, 45, 40, 2, 10, 27, 10, 47, 32, 13, 29, - 24, 42, 1, 35, 32, 0, 38, 9, 31, 41, 5, 4, 46, 16, 14, 42, 41, 10, 17, - 8, 0, 49, 40, 11, 45, 48, 12, 49, 1, 23, 37, 14, 17, 37, 44, 42, 0, 2, - 37, 34, 43, 10, 7, 31, 19, 22, 43, 30, 16, 11, 14, 17, 36, 4, 4, 15, 34, - 47, 10, 39, 29, 40, 21, 45, 1, 46, 35, 32, 2, 46, 21, 28, 14, 15, 20, 11, - 42, 0, 23, 31, 5, 36, 19, 44, 31, 42, 13, 30, 29, 3, 28, 35, 22, 13, 35, - 11, 18, 33, 18, 9, 25, 8, 27, 15, 1, 18, 14, 30, 4, 26, 47, 4, 36, 25, - 7, 33, 37, 21, 33, 27, 39, 41, 36, 26, 26, 20, 17, 2, 12, 40, 18, 14, 33, - 31, 21, 30, 8, 6, 5, 23, 2, 28, 28, 4, 28, 45, 26, 49, 13, 16, 16, 40, - 36, 5, 3, 4, 14, 41, 41, 35, 12, 23, 38, 35, 49, 21, 34, 16, 31, 18, 28, - 23, 42, 33, 46, 25, 39, 48, 27, 22, 43, 4, 16, 5, 30, 11, 44, 47, 16, 35, - 48, 20, 14, 37, 24, 27, 2, 13, 0, 48, 13, 24, 6, 27, 4, 17, 11, 5, 43, - 47, 6, 43, 18, 10, 16, 4, 1, 10, 30, 14, 17, 25, 33, 5, 40, 49, 38, 1, - 37, 44, 23, 12, 13, 26, 48, 17, 13, 25, 32, 2, 13, 3, 13, 38, 21, 8, 17, - 35, 5, 19, 6, 48, 8, 47, 6, 29, 48, 4, 47, 17, 42, 47, 38, 44, 33, 14, - 46, 3, 33, 47, 9, 25, 14, 27, 20, 42, 36, 0, 37, 25, 30, 5, 30, 46, 10, - 8, 3, 30, 13, 3, 23, 44, 27, 47, 0, 36, 14, 37, 46, 17, 14, 12, 24, 28, - 12, 35, 0, 41, 12, 38, 28, 26, 19, 46, 15, 44, 6, 8, 21, 30, 14, 49, 1, - 34, 23, 26, 26, 8, 41, 39, 22, 32, 5, 41, 9, 19, 1, 32, 23, 24, 43, 28, - 0, 4, 15, 39, 44, 6, 30, 30, 5, 18, 36, 4, 12, 7, 46, 49, 5, 31, 9, - 5, 17, 32, 31, 14, 14, 30, 25, 39, 10, 1, 6, 31, 11, 11, 49, 31, 36, 35, - 32, 35, 6, 3, 37, 3, 11, 45, 15, 5, 15, 25, 5, 16, 48, 3, 30, 48, 44, - 4, 36, 0, 5, 30, 21, 35, 19, 47, 11, 8, 34, 38, 42, 20, 47, 32, 24, 38, - 36, 4, 38, 4, 9, 11, 0, 26, 21, 33, 7, 42, 9, 35, 45, 42, 1, 8, 10, - 39, 46, 8, 18, 0, 48, 10, 1, 46, 2, 12, 43, 49, 12, 36, 10, 42, 8, 29, - 5, 43, 5, 23, 41, 28, 34, 27, 43, 47, 39, 26, 32, 45, 1, 25, 4, 40, 21, - 28, 9, 21, 39, 2, 29, 34, 31, 23, 24, 29, 9, 17, 38, 23, 30, 14, 16, 37, - 31, 20, 40, 41, 10, 31, 19, 16, 24, 29, 16, 0, 41, 5, 32, 46, 25, 14, 24, - 11, 39, 25, 43, 24, 7, 8, 4, 35, 31, 23, 7, 32, 36, 14, 4, 44, 25, 9, - 34, 46, 34, 26, 28, 24, 35, 14, 16, 29, 41, 28, 2, 3, 35, 37, 33, 40, 24, - 27, 40, 25, 21, 46, 31, 45, 9, 25, 26, 31, 48, 23, 35, 44, 44, 33, 16, 34, - 9, 13, 25, 5, 12, 17, 11, 31, 30, 16, 13, 4, 7, 16, 18, 7, 17, 16, 9, - 35, 39, 34, 34, 6, 36, 17, 4, 25, 38, 23, 40, 44, 11, 44, 34, 23, 0, 40, - 21, 16, 30, 10, 14, 34, 37, 10, 14, 4, 27, 34, 43, 4, 26, 11, 32, 40, 48, - 32, 39, 21, 9, 40, 49, 38, 49, 37, 32, 43, 10, 39, 43, 4, 15, 9, 2, 31, - 44, 30, 37, 8, 7, 3, 5, 24, 7, 1, 46, 20, 12, 34, 7, 48, 10, 21, 38, - 11, 30, 31, 46, 46, 4, 8, 5, 40, 44, 4, 12, 24, 45, 39, 25, 3}; - -float input2_data[DATA_SIZE] = { - 23, 17, 1, 50, 19, 29, 4, 8, 11, 8, 11, 29, 18, 30, 45, 12, 1, 45, 38, - 33, 26, 22, 36, 41, 50, 8, 35, 29, 14, 13, 33, 26, 5, 36, 34, 19, 28, 47, - 30, 29, 48, 41, 30, 33, 19, 25, 17, 16, 30, 20, 28, 33, 50, 50, 41, 4, 11, - 50, 32, 43, 36, 50, 13, 36, 22, 21, 27, 36, 1, 25, 6, 44, 35, 21, 15, 15, - 32, 4, 18, 28, 33, 9, 27, 15, 40, 41, 37, 38, 38, 5, 50, 14, 43, 40, 27, - 12, 24, 13, 18, 17, 35, 38, 23, 16, 38, 28, 24, 28, 47, 40, 18, 45, 34, 26, - 28, 44, 43, 23, 4, 34, 20, 1, 1, 9, 15, 20, 27, 10, 46, 28, 50, 45, 3, - 31, 48, 25, 8, 1, 33, 17, 37, 5, 37, 15, 20, 35, 46, 24, 41, 37, 14, 7, - 12, 11, 10, 1, 26, 30, 9, 33, 18, 31, 4, 43, 33, 32, 7, 7, 42, 34, 22, - 25, 38, 7, 32, 1, 1, 21, 6, 36, 41, 49, 21, 44, 43, 5, 4, 34, 34, 8, - 7, 5, 21, 12, 1, 22, 49, 11, 32, 19, 47, 36, 33, 16, 45, 35, 2, 25, 28, - 27, 49, 33, 22, 21, 16, 22, 44, 11, 24, 50, 34, 36, 50, 17, 23, 32, 8, 33, - 23, 22, 26, 50, 22, 1, 25, 8, 18, 20, 3, 9, 31, 6, 49, 7, 45, 5, 44, - 31, 31, 44, 45, 31, 21, 12, 38, 27, 14, 23, 12, 38, 48, 37, 36, 11, 3, 38, - 3, 20, 3, 8, 21, 38, 12, 24, 39, 10, 25, 35, 37, 9, 10, 46, 1, 49, 13, - 24, 19, 27, 12, 7, 3, 40, 10, 9, 38, 22, 18, 21, 8, 32, 15, 40, 17, 32, - 6, 43, 4, 41, 20, 48, 2, 1, 35, 35, 34, 30, 45, 42, 38, 24, 26, 27, 23, - 22, 37, 37, 36, 28, 5, 40, 11, 2, 33, 3, 22, 33, 5, 49, 34, 49, 27, 4, - 32, 16, 36, 21, 3, 37, 16, 22, 46, 30, 35, 40, 25, 9, 48, 50, 25, 8, 42, - 31, 35, 1, 6, 40, 10, 1, 36, 5, 38, 37, 41, 22, 17, 2, 2, 31, 47, 2, - 5, 23, 17, 18, 28, 19, 48, 32, 20, 50, 13, 17, 42, 49, 20, 14, 24, 18, 17, - 21, 13, 11, 28, 46, 32, 37, 30, 42, 34, 50, 21, 34, 47, 29, 38, 34, 7, 20, - 47, 9, 23, 16, 10, 24, 10, 21, 21, 41, 50, 14, 37, 35, 42, 27, 3, 32, 27, - 5, 15, 44, 6, 20, 40, 33, 19, 48, 45, 30, 3, 15, 43, 38, 5, 27, 23, 22, - 9, 47, 2, 24, 17, 14, 19, 18, 45, 8, 9, 23, 10, 32, 47, 14, 40, 10, 32, - 15, 47, 8, 42, 5, 50, 32, 33, 2, 1, 38, 20, 46, 40, 28, 50, 27, 31, 21, - 35, 28, 46, 7, 50, 27, 32, 12, 45, 27, 42, 33, 12, 5, 14, 29, 12, 7, 31, - 10, 12, 40, 45, 29, 6, 8, 40, 43, 2, 36, 45, 25, 3, 19, 11, 28, 21, 7, - 33, 24, 5, 15, 3, 45, 12, 38, 37, 45, 9, 1, 27, 17, 9, 25, 6, 9, 3, - 36, 33, 46, 32, 13, 42, 40, 33, 13, 13, 8, 44, 17, 31, 47, 39, 20, 12, 38, - 23, 22, 11, 49, 46, 47, 33, 27, 30, 5, 24, 35, 4, 38, 2, 25, 2, 20, 25, - 2, 21, 33, 2, 48, 28, 5, 16, 37, 37, 7, 28, 13, 6, 19, 3, 44, 8, 43, - 37, 17, 24, 14, 18, 41, 34, 17, 17, 21, 24, 3, 30, 25, 21, 50, 38, 12, 27, - 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39, 36, 38, 12, 29, 36, 21, 10, 41, 38, 31, 16, 8, 25, 22, 20, 37, 30, 20, - 18, 10, 32, 5, 20, 11, 35, 13, 21, 27, 22, 48, 39, 11, 19, 6, 30, 39, 10, - 36, 50, 38, 18, 39, 9, 14, 19, 28, 49, 9, 47, 6, 11, 17, 9, 45, 13, 26, - 16, 34, 26, 10, 18, 24, 48, 10, 44, 46, 19, 49, 13, 41, 8, 32, 21, 9, 36, - 28, 13, 8, 9, 40, 26, 40, 31, 14, 35, 47, 49, 27, 46, 48, 42, 46, 29, 49, - 34, 23, 13, 29, 20, 6, 7, 3, 44, 39, 29, 46, 7, 15, 13, 35, 14, 37, 27, - 42, 34, 46, 27, 5, 44, 26, 13, 2, 11, 26, 1, 40, 27, 45, 13, 21, 24, 30, - 12, 10, 42, 29, 30, 35, 6, 40, 3, 20, 36, 35, 34, 32, 40, 31, 14, 31, 39, - 50, 3, 40, 48, 31, 10, 16, 35, 40, 1, 23, 11, 47, 26, 46, 11, 21, 8, 14, - 39, 31, 10, 23, 48, 11, 6, 29, 43, 50, 15, 42, 48, 39, 1, 33, 44, 1, 40, - 19, 5, 20, 11, 23, 13, 28, 47, 34, 39, 40, 50, 48, 3, 44, 36, 19, 44, 21, - 30, 7, 21, 38, 22, 7, 29, 3, 47, 20, 39, 4, 22, 32, 34, 35, 15, 10, 36, - 42, 19, 42, 22, 29, 10, 32, 2, 47, 50, 38, 12, 47, 42, 18, 11, 3, 44, 10, - 10, 3, 18, 48, 1, 30, 28, 25, 6, 26, 47, 10, 36, 24, 32, 1, 45, 36, 41, - 37, 37, 12, 47, 2, 18, 5, 11, 29, 5, 41, 16, 23, 32, 33, 3, 45, 14, 39, - 41, 4, 37, 38, 46, 16, 25, 5, 37, 32, 28, 2, 34, 38, 4, 28, 12, 40, 15, - 14, 32, 15, 44, 25, 25, 40, 49, 22, 8, 39, 39, 24, 22, 24, 28, 49, 3, 50, - 19, 49, 25, 41, 39, 19, 24, 39, 6, 12, 6, 3, 46, 32, 35, 21, 41, 2, 40, - 28, 47, 43, 15, 48, 26, 39, 2, 18, 36, 8, 29, 23, 17, 12, 17, 21, 15, 50, - 7, 21, 27, 50, 4, 3, 27, 4, 4, 33, 1, 2, 8, 37, 23, 40, 4, 27, 1, - 35, 30, 33, 6, 43, 28, 16, 30, 8, 16, 22, 47, 3, 21, 43, 16, 34, 7, 50, - 31, 13, 11, 11, 14, 15, 17, 24, 24, 14, 41, 36, 2, 11, 34, 36, 17, 16, 36, - 21, 26, 33, 23, 29, 26, 33, 31, 19, 40, 26, 3, 18, 41, 12, 6, 41, 4, 21, - 14, 38, 1, 21, 22, 9, 37, 31, 49, 23, 32, 10, 24, 42, 43, 11, 15, 6, 6, - 40, 44, 41, 42, 21, 7, 10, 11, 48, 34, 38, 50, 38, 40, 19, 26, 34, 38, 45, - 2, 45, 1, 1, 27, 13, 10, 11, 2, 49, 34, 46, 23, 39, 15, 27, 15, 33, 44, - 43, 42, 13, 44, 21, 5, 36, 27, 10, 21, 20, 44, 9, 12, 29, 9, 21, 13, 25, - 36, 19, 1, 47, 40, 44, 31, 44, 35, 28, 42, 39, 15, 43, 19, 3, 30, 48, 41, - 9, 6, 26, 48, 24, 1, 41, 40, 38, 43, 35, 37, 16, 7, 3, 48, 36, 31, 26, - 49, 5, 18, 43, 40, 36, 7, 4, 14, 37, 21, 14, 47, 6, 31, 49, 11, 18, 14, - 34, 25, 15, 5, 9, 36, 12, 41, 1, 32, 11, 11, 37, 22, 20, 5, 5, 25, 10, - 31, 7, 47, 41, 41, 4, 50, 32, 10, 16, 25, 14, 4, 20, 41, 21, 12, 47, 7, - 28, 35, 20, 32, 40, 41, 49, 43, 48, 35, 21, 32, 18, 9, 50, 11, 45, 27, 25, - 32, 11, 3, 37, 44, 40, 21, 21, 22, 22, 44, 31, 37, 23, 39, 7, 10, 30, 33, - 28, 36, 42, 20, 30, 8, 34, 35, 2, 11, 42, 13, 30, 31, 2, 31, 17, 50, 22, - 38, 12, 9, 39, 12, 26, 50, 15, 44, 50, 2, 2, 22, 13, 6, 41, 40, 24, 4, - 4, 41, 50, 16, 8, 26, 23, 32, 38, 47, 40, 10, 39, 42, 43, 6, 10, 28, 39, - 9, 9, 38, 20, 24, 40, 39, 9, 46, 25, 45, 22, 39, 18, 28, 29, 16, 36, 41, - 15, 40, 24, 22, 21, 38, 28, 50, 31, 42, 21, 41, 49, 42, 36, 13, 46, 50, 36, - 4, 41, 11, 36, 23, 24, 25, 39, 8, 48, 7, 32, 50, 45, 3, 49, 38, 12, 26, - 15, 30, 5, 6, 39, 43, 45, 19, 4, 47, 38, 37, 13, 27, 23, 5, 6, 29, 8, - 2, 1, 15, 39, 18, 24, 49, 16, 1, 2, 50, 30, 37, 49, 34, 25, 41, 14, 24, - 30, 45, 17, 39, 29, 26, 3, 26, 33, 23, 48, 27, 6, 37, 13, 18, 13, 22, 33, - 31, 43, 1, 14, 6, 42, 3, 50, 1, 1, 41, 46, 3, 29, 21, 47, 12, 28, 50, - 34, 1, 11, 15, 17, 45, 29, 37, 32, 3, 33, 40, 8, 40, 9, 18, 4, 33, 11, - 45, 21, 14, 33, 29, 4, 8, 23, 11, 28, 27, 37, 2, 41, 28, 12, 7, 23, 41, - 15, 20, 40, 20, 42, 23, 19, 45, 40, 45, 35, 31, 11, 4, 26, 27, 11, 29, 22, - 34, 32, 23, 8, 8, 28, 22, 26, 9, 20, 36, 15, 32, 36, 3, 45, 33, 13, 35, - 17, 24, 38, 41, 45, 32, 46, 25, 21, 43, 29, 14, 45, 49, 21, 4, 11, 31, 32, - 38, 41, 39, 32, 46, 21, 36, 13, 2, 32, 44, 8, 7, 8, 2, 28, 32, 22, 25, - 40, 17, 8, 21, 7, 7, 42, 18, 11, 46, 18, 26, 45, 28, 27, 31, 48, 50, 6, - 29, 50, 41, 37, 21, 40, 49, 33, 15, 19, 28, 12, 37, 34, 14, 45, 32, 30, 1, - 34, 47, 10, 7, 3, 40, 43, 40, 21, 12, 27, 2, 38, 7, 26, 27, 27, 41, 16, - 24, 14, 29, 24, 48, 21, 29, 45, 10, 19, 30, 50, 40, 34, 27, 45, 42, 41, 12, - 10, 25, 18, 20, 1, 30, 22, 19, 5, 37, 44, 49, 25, 37, 16, 18, 44, 11, 42, - 7, 42, 44, 34, 45, 45, 9, 41, 44, 20, 44, 17, 16, 27, 32, 5, 22, 10, 34, - 37, 7, 49, 17, 15, 21, 2, 38, 16, 16, 16, 37, 38, 44, 33, 4, 13, 21, 46, - 41, 12, 13, 28, 6, 6, 8, 28, 18, 48, 40, 40, 48, 48, 13, 5, 40, 18, 1, - 42, 28, 35, 16, 25, 10, 44, 11, 9, 48, 3, 37, 25, 33, 31, 5, 27, 37, 14, - 39, 14, 16, 49, 45, 30, 9, 21, 43, 44, 36, 17, 40, 36, 43, 38, 50, 20, 9, - 21, 27, 9, 27, 7, 21, 43, 29, 1, 2, 28, 43, 29, 37, 30, 21, 10, 5, 37, - 44, 50, 46, 22, 22, 3, 5, 19, 36, 40, 11, 4, 45, 32, 14, 43, 31, 14, 43, - 17, 8, 44, 9, 1, 24, 35, 40, 10, 34, 16, 4, 18, 17, 9, 9, 45, 6, 5, - 45, 23, 28, 27, 7, 28, 11, 28, 24, 25, 39, 3, 7, 38, 45, 12, 27, 34, 28, - 42, 49, 24, 22, 21, 18, 22, 38, 49, 8, 2, 45, 10, 21, 49, 24, 41, 12, 50, - 2, 45, 19, 26, 33, 3, 15, 16, 24, 19, 41, 13, 22, 23, 43, 50, 37, 5, 6, - 43, 35, 19, 28, 8, 19, 38, 4, 1, 37, 26, 40, 9, 36, 14, 16, 32, 35, 18, - 42, 24, 20, 21, 19, 10, 23, 18, 2, 48, 49, 43, 11, 39, 42, 48, 40, 12, 21, - 47, 28, 33, 23, 35, 26, 9, 47, 31, 3, 17, 39, 11, 15, 14, 40, 23}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/div_approx_gendata.pl b/bb-tests/workloads/src/CTest/rvv/vec-div-approx/div_approx_gendata.pl deleted file mode 100755 index 5ee73828..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/div_approx_gendata.pl +++ /dev/null @@ -1,135 +0,0 @@ -#!/usr/bin/perl -w -#========================================================================== -# div_approx.pl -# -# Author: Generated -# Date: Today -# -(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm; -# -# Simple script which creates an input data set and the reference data -# for the given conditional operation. -# -ENDMSG - -use strict "vars"; -use warnings; -no warnings("once"); -use Getopt::Long; - -#-------------------------------------------------------------------------- -# Command line processing -#-------------------------------------------------------------------------- - -our %opts; - -sub usage() -{ - - print "\n"; - print " Usage: conditional_gendata.pl [options] \n"; - print "\n"; - print " Options:\n"; - print " --help print this message\n"; - print " --size size of input data [1000]\n"; - print " --seed random seed [1]\n"; - print "$usageMsg"; - - exit(); -} - -sub processCommandLine() -{ - - $opts{"help"} = 0; - $opts{"size"} = 300; - $opts{"seed"} = 1; - Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage(); - $opts{"help"} and usage(); - -} - -#-------------------------------------------------------------------------- -# Helper Functions -#-------------------------------------------------------------------------- -sub printArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - my $type = $_[2]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print $type." ".$arrayName."[DATA_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3d",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - my @input1_data; # x - my @input2_data; # y - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - my $valueX = int(rand(50)); # x - my $valueY = 1 + int(rand(50)); # y - - - push( @input1_data, $valueX ); - push( @input2_data, $valueY ); - } - - print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n"; - printArray( "input1_data", \@input1_data, "float" ); # x - printArray( "input2_data", \@input2_data, "float" ); # y -} - -main(); diff --git a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/vec-div_approx.S b/bb-tests/workloads/src/CTest/rvv/vec-div-approx/vec-div_approx.S deleted file mode 100644 index 2281e1b9..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/vec-div_approx.S +++ /dev/null @@ -1,26 +0,0 @@ - .text - .balign 4 - .global vec_div_approx - -# v1 = v1 / v2 to almost 23 bits of precision. - -vec_div_approx: - vsetvli t1, a0, e32, m4, ta, mu - vle32.v v4, (a1) # load x values - vle32.v v8, (a2) # load y values - sub a0, a0, t1 - slli t1, t1, 2 - vfrec7.v v12, v8 # Estimate 1/v2 - li t0, 0x40000000 - vmv.v.x v16, t0 # Splat 2.0 - vfnmsac.vv v16, v8, v12 # 2.0 - v2 * est(1/v2) - vfmul.vv v12, v12, v16 # Better estimate of 1/v2 - vmv.v.x v16, t0 # Splat 2.0 - vfnmsac.vv v16, v8, v12 # 2.0 - v2 * est(1/v2) - vfmul.vv v12, v12, v16 # Better estimate of 1/v2 - vfmul.vv v4, v4, v12 # Estimate of v1/v2 - vse32.v v4, (a1) - add a2, a2, t1 # Bump pointer - add a1, a1, t1 # Bump pointer - bnez a0, vec_div_approx - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/vec-div_approx_main.c b/bb-tests/workloads/src/CTest/rvv/vec-div-approx/vec-div_approx_main.c deleted file mode 100644 index 416ef7ef..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-div-approx/vec-div_approx_main.c +++ /dev/null @@ -1,48 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// division approximation benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized conditional implementation. -// The input data (and reference data) should be generated using -// the div_approx_gendata.pl perl script and dumped to a file named -// dataset1.h. - -#include "util.h" -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" -#include - -//-------------------------------------------------------------------------- -// Main - -void vec_div_approx(size_t n, float x[], float y[]); - -int main(int argc, char *argv[]) { - printf("Div approx size = %ld\n", DATA_SIZE); -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_div_approx(DATA_SIZE, input1_data, input2_data); -#endif - - // Do the division - setStats(1); - vec_div_approx(DATA_SIZE, input1_data, input2_data); - setStats(0); - - // int i; - // // Unrolled for faster verification - // for (i = 0; i < 17/2*2; i+=2) - // { - // float t0 = input1_data[i], t1 = input1_data[i+1]; - // printf("test_val: %.2f\n", t0); - // printf("test_val: %.2f\n", t1); - // } - // if (17 % 2 != 0) printf("test_val: %.2f\n\n", input1_data[17-1]); - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/dotproduct.c b/bb-tests/workloads/src/CTest/rvv/vec-dotprod/dotproduct.c deleted file mode 100644 index 7b976a11..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/dotproduct.c +++ /dev/null @@ -1,299 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "dotproduct.h" - -int64_t dotp_v64b(int64_t *a, int64_t *b, uint64_t avl) { - size_t orig_avl = avl; - size_t vl = __riscv_vsetvl_e64m8(avl); - - vint64m8_t acc, buf_a, buf_b; - vint64m1_t red; - - int64_t *a_ = (int64_t *)a; - int64_t *b_ = (int64_t *)b; - - // Clean the accumulator - red = __riscv_vmv_s_x_i64m1(0, vl); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - vl = __riscv_vsetvl_e64m8(avl); - // Load chunk a and b - buf_a = __riscv_vle64_v_i64m8(a_, vl); - buf_b = __riscv_vle64_v_i64m8(b_, vl); - // Multiply and accumulate - if (avl == orig_avl) { - acc = __riscv_vmul_vv_i64m8(buf_a, buf_b, vl); - } else { - acc = __riscv_vmacc_vv_i64m8(acc, buf_a, buf_b, vl); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - red = __riscv_vredsum_vs_i64m8_i64m1(acc, red, vl); - return __riscv_vmv_x_s_i64m1_i64(red); -} - -int32_t dotp_v32b(int32_t *a, int32_t *b, uint64_t avl) { - size_t orig_avl = avl; - size_t vl = __riscv_vsetvl_e32m8(avl); - - vint32m8_t acc, buf_a, buf_b; - vint32m1_t red; - - int32_t *a_ = (int32_t *)a; - int32_t *b_ = (int32_t *)b; - - // Clean the accumulator - red = __riscv_vmv_s_x_i32m1(0, vl); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - vl = __riscv_vsetvl_e32m8(avl); - // Load chunk a and b - buf_a = __riscv_vle32_v_i32m8(a_, vl); - buf_b = __riscv_vle32_v_i32m8(b_, vl); - // Multiply and accumulate - if (avl == orig_avl) { - acc = __riscv_vmul_vv_i32m8(buf_a, buf_b, vl); - } else { - acc = __riscv_vmacc_vv_i32m8(acc, buf_a, buf_b, vl); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and return - red = __riscv_vredsum_vs_i32m8_i32m1(acc, red, vl); - return __riscv_vmv_x_s_i32m1_i32(red); -} - -int16_t dotp_v16b(int16_t *a, int16_t *b, uint64_t avl) { - size_t orig_avl = avl; - size_t vl = __riscv_vsetvl_e16m8(avl); - - vint16m8_t acc, buf_a, buf_b; - vint16m1_t red; - - int16_t *a_ = (int16_t *)a; - int16_t *b_ = (int16_t *)b; - - // Clean the accumulator - red = __riscv_vmv_s_x_i16m1(0, vl); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - vl = __riscv_vsetvl_e16m8(avl); - // Load chunk a and b - buf_a = __riscv_vle16_v_i16m8(a_, vl); - buf_b = __riscv_vle16_v_i16m8(b_, vl); - // Multiply and accumulate - if (avl == orig_avl) { - acc = __riscv_vmul_vv_i16m8(buf_a, buf_b, vl); - } else { - acc = __riscv_vmacc_vv_i16m8(acc, buf_a, buf_b, vl); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and store - red = __riscv_vredsum_vs_i16m8_i16m1(acc, red, vl); - return __riscv_vmv_x_s_i16m1_i16(red); -} - -int8_t dotp_v8b(int8_t *a, int8_t *b, uint64_t avl) { - size_t orig_avl = avl; - size_t vl = __riscv_vsetvl_e8m8(avl); - - vint8m8_t acc, buf_a, buf_b; - vint8m1_t red; - - int8_t *a_ = (int8_t *)a; - int8_t *b_ = (int8_t *)b; - - // Clean the accumulator - red = __riscv_vmv_s_x_i8m1(0, vl); - // Stripmine and accumulate a partial reduced vector - for (; avl > 0; avl -= vl) { - vl = __riscv_vsetvl_e8m8(avl); - // Load chunk a and b - buf_a = __riscv_vle8_v_i8m8(a_, vl); - buf_b = __riscv_vle8_v_i8m8(b_, vl); - // Multiply and accumulate - if (avl == orig_avl) { - acc = __riscv_vmul_vv_i8m8(buf_a, buf_b, vl); - } else { - acc = __riscv_vmacc_vv_i8m8(acc, buf_a, buf_b, vl); - } - // Bump pointers - a_ += vl; - b_ += vl; - } - - // Reduce and store - red = __riscv_vredsum_vs_i8m8_i8m1(acc, red, vl); - return __riscv_vmv_x_s_i8m1_i8(red); -} - -int64_t dotp_s64b(int64_t *a, int64_t *b, uint64_t avl) { - int64_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} - -int32_t dotp_s32b(int32_t *a, int32_t *b, uint64_t avl) { - int32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} - -int16_t dotp_s16b(int16_t *a, int16_t *b, uint64_t avl) { - int16_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} - -int8_t dotp_s8b(int8_t *a, int8_t *b, uint64_t avl) { - int8_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; - - acc0 = 0; - acc1 = 0; - acc2 = 0; - acc3 = 0; - acc4 = 0; - acc5 = 0; - acc6 = 0; - acc7 = 0; - - for (uint64_t i = 0; i < avl; i += 8) { - acc0 += a[i + 0] * b[i + 0]; - acc1 += a[i + 1] * b[i + 1]; - acc2 += a[i + 2] * b[i + 2]; - acc3 += a[i + 3] * b[i + 3]; - acc4 += a[i + 4] * b[i + 4]; - acc5 += a[i + 5] * b[i + 5]; - acc6 += a[i + 6] * b[i + 6]; - acc7 += a[i + 7] * b[i + 7]; - } - - acc0 += acc1; - acc2 += acc3; - acc4 += acc5; - acc6 += acc7; - - acc0 += acc2; - acc4 += acc6; - - acc0 += acc4; - - return acc0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/dotproduct.h b/bb-tests/workloads/src/CTest/rvv/vec-dotprod/dotproduct.h deleted file mode 100644 index 7139417c..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/dotproduct.h +++ /dev/null @@ -1,37 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef _DOTPRODUCT_H_ -#define _DOTPRODUCT_H_ - -#include -#include - -#include - -int64_t dotp_v64b(int64_t *a, int64_t *b, uint64_t avl); -int32_t dotp_v32b(int32_t *a, int32_t *b, uint64_t avl); -int16_t dotp_v16b(int16_t *a, int16_t *b, uint64_t avl); -int8_t dotp_v8b(int8_t *a, int8_t *b, uint64_t avl); - -int64_t dotp_s64b(int64_t *a, int64_t *b, uint64_t avl); -int32_t dotp_s32b(int32_t *a, int32_t *b, uint64_t avl); -int16_t dotp_s16b(int16_t *a, int16_t *b, uint64_t avl); -int8_t dotp_s8b(int8_t *a, int8_t *b, uint64_t avl); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-dotprod/gen_data.py deleted file mode 100755 index 2a29ca53..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/gen_data.py +++ /dev/null @@ -1,96 +0,0 @@ -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Generate input data for fdotp benchmark -# arg: #elements per vector - -import numpy as np -import random -from functools import reduce -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# Vector length -if len(sys.argv) > 1: - vsize = int(sys.argv[1]) -else: - # Default: no stripmine - vsize = 64 - -avl64 = int(vsize) -avl32 = int(vsize) -avl16 = int(vsize) -avl8 = int(vsize) - -# Create the vectors -v64a = np.random.randint(-(2 ** (50)), high=2 ** (50) - 1, size=avl64, dtype=np.int64) -v64b = np.random.randint(-(2 ** (50)), high=2 ** (50) - 1, size=avl64, dtype=np.int64) -v32a = np.random.randint(-(2 ** (20)), high=2 ** (20) - 1, size=avl32, dtype=np.int32) -v32b = np.random.randint(-(2 ** (20)), high=2 ** (20) - 1, size=avl32, dtype=np.int32) -v16a = np.random.randint(-(2 ** (10)), high=2 ** (10) - 1, size=avl16, dtype=np.int16) -v16b = np.random.randint(-(2 ** (10)), high=2 ** (10) - 1, size=avl16, dtype=np.int16) -v8a = np.random.randint(-(2 ** (2)), high=2 ** (2) - 1, size=avl8, dtype=np.int8) -v8b = np.random.randint(-(2 ** (2)), high=2 ** (2) - 1, size=avl8, dtype=np.int8) - -# Create the golden output -gold64 = reduce(lambda a, b: a + b, np.multiply(v64a, v64b)) -gold32 = reduce(lambda a, b: a + b, np.multiply(v32a, v32b)) -gold16 = reduce(lambda a, b: a + b, np.multiply(v16a, v16b)) -gold16 = np.array([gold16, gold16]) -gold8 = reduce(lambda a, b: a + b, np.multiply(v8a, v8b)) -gold8 = np.array([gold8, gold8, gold8, gold8]) - -# Create the empty result vectors -res64 = 0 -res32 = 0 -res16 = 0 -res8 = 0 - -# Print information on file -print('.section .data,"aw",@progbits') -emit("vsize", np.array(vsize, dtype=np.uint64)) -emit("v64a", v64a, "32") -emit("v64b", v64b, "32") -emit("v32a", v32a, "32") -emit("v32b", v32b, "32") -emit("v16a", v16a, "32") -emit("v16b", v16b, "32") -emit("v8a", v8a, "32") -emit("v8b", v8b, "32") -# emit("gold64", np.array(gold64, dtype=np.int64)); -# emit("gold32", np.array(gold32, dtype=np.int32)); -# emit("gold16", gold16, '32'); -# emit("gold8", gold8, '32'); -emit("res64_v", np.array(res64, dtype=np.int64)) -emit("res32_v", np.array(res32, dtype=np.int32)) -emit("res16_v", np.array(res16, dtype=np.int32)) -emit("res8_v", np.array(res8, dtype=np.int32)) -emit("res64_s", np.array(res64, dtype=np.int64)) -emit("res32_s", np.array(res32, dtype=np.int32)) -emit("res16_s", np.array(res16, dtype=np.int32)) -emit("res8_s", np.array(res8, dtype=np.int32)) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/main.c b/bb-tests/workloads/src/CTest/rvv/vec-dotprod/main.c deleted file mode 100644 index c33e18ad..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dotprod/main.c +++ /dev/null @@ -1,108 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "dotproduct.h" -#include "util.h" -#include -#include -#include - -// Run also the scalar benchmark -#define SCALAR 1 - -// Check the vector results against golden vectors -#define CHECK 1 - -// Vector size (Byte) -extern uint64_t vsize; -// Vectors for benchmarks -extern int64_t v64a[] __attribute__((aligned(256), section(".l2"))); -extern int64_t v64b[] __attribute__((aligned(256), section(".l2"))); -extern int32_t v32a[] __attribute__((aligned(256), section(".l2"))); -extern int32_t v32b[] __attribute__((aligned(256), section(".l2"))); -extern int16_t v16a[] __attribute__((aligned(256), section(".l2"))); -extern int16_t v16b[] __attribute__((aligned(256), section(".l2"))); -extern int8_t v8a[] __attribute__((aligned(256), section(".l2"))); -extern int8_t v8b[] __attribute__((aligned(256), section(".l2"))); -// Output vectors -extern int64_t res64_v, res64_s; -extern int32_t res32_v, res32_s; -extern int16_t res16_v, res16_s; -extern int8_t res8_v, res8_s; - -int main() { - printf("DOTP %ld\n", vsize); - - unsigned long cycles1, cycles2, instr2, instr1; - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - // Dotp - printf("Calulating 64b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res64_v = dotp_v64b(v64a, v64b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector cycles: %ld instructions: %ld\n", cycles2 - cycles1, - instr2 - instr1); - } - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - // Dotp - printf("Calulating 32b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res32_v = dotp_v32b(v32a, v32b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector cycles: %ld instructions: %ld\n", cycles2 - cycles1, - instr2 - instr1); - } - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - // Dotp - printf("Calulating 16b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res16_v = dotp_v16b(v16a, v16b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector cycles: %ld instructions: %ld\n", cycles2 - cycles1, - instr2 - instr1); - } - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - // Dotp - printf("Calulating 8b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res8_v = dotp_v8b(v8a, v8b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector cycles: %ld instructions: %ld\n", cycles2 - cycles1, - instr2 - instr1); - } - - printf("SUCCESS.\n"); - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dropout/dropout.c b/bb-tests/workloads/src/CTest/rvv/vec-dropout/dropout.c deleted file mode 100644 index 8a1ec7b6..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dropout/dropout.c +++ /dev/null @@ -1,61 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include "dropout.h" - -// Scalar dropout -void dropout_gold(const unsigned int n, const float *i, const float scale, - const uint8_t *sel_ptr, float *o) { - uint8_t buf_sel, sel; - for (unsigned int k = 0; k < n; ++k) { - if (!(k % 8)) - buf_sel = sel_ptr[k >> 3]; - sel = buf_sel & 0x01; - o[k] = sel ? (i[k] * scale) : 0; - buf_sel >>= 1; - } -} - -void dropout_vec(const unsigned int n, const float *i, const float scale, - const uint8_t *sel_ptr, float *o) { - unsigned int vl; - - asm volatile("vsetvli %[vl], %[n], e32, m8, ta, ma" - : [vl] "=r"(vl) - : [n] "r"(n)); - - for (unsigned int avl = n; avl > 0; avl -= vl) { - // Find next vl - asm volatile("vsetvli %[vl], %[avl], e32, m8, ta, ma" - : [vl] "=r"(vl) - : [avl] "r"(avl)); - // Load the mask vector (1 = keep, 0 = drop) - asm volatile("vlm.v v0, (%[sel_ptr])" ::[sel_ptr] "r"(sel_ptr)); - // Initialize output vector with zeroes - asm volatile("vmv.v.i v24, 0"); - // Load input vector - asm volatile("vle32.v v8, (%[i])" ::[i] "r"(i)); - // Calculate output vector - asm volatile("vfmul.vf v24, v8, %[scale], v0.t" ::[scale] "f"(scale)); - asm volatile("vse32.v v24, (%[o])" ::[o] "r"(o)); - // Bump pointers - i += vl; - sel_ptr += vl >> 3; - o += vl; - } -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dropout/dropout.h b/bb-tests/workloads/src/CTest/rvv/vec-dropout/dropout.h deleted file mode 100644 index 812b7080..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dropout/dropout.h +++ /dev/null @@ -1,31 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef _DROPOUT_H_ -#define _DROPOUT_H_ - -#include - -#include - -void dropout_gold(const unsigned int n, const float *i, const float scale, - const uint8_t *sel_ptr, float *o); -void dropout_vec(const unsigned int n, const float *i, const float scale, - const uint8_t *sel_ptr, float *o); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dropout/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-dropout/gen_data.py deleted file mode 100644 index 1abdf9e4..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dropout/gen_data.py +++ /dev/null @@ -1,66 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: image size, arg2: filter size - -import numpy as np -import random -import sys - - -def rand_array(N, dtype): - return np.random.rand(N).astype(dtype) - - -def rand_sel(N, dtype): - return np.random.randint(0, 256, N, dtype) - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -if len(sys.argv) > 1: - N = int(sys.argv[1]) -else: - N = 1024 - -# Generate inputs -input_array = rand_array(N, np.float32) -SCALE = rand_array(1, np.float32)[0] -SEL = rand_sel(N, np.uint8) - -# Create the empty o matrix -o = np.zeros(N).astype(np.float32) -o_gold = o - -# Print information on file -print('.section .data,"aw",@progbits') -emit("N", np.array(N, dtype=np.uint64)) -emit("SCALE", np.array(SCALE, dtype=np.float32)) -emit("I", input_array, "NR_LANES*4") -emit("SEL", SEL, "NR_LANES*4") -emit("o", o, "NR_LANES*4") -emit("o_gold", o_gold, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-dropout/main.c b/bb-tests/workloads/src/CTest/rvv/vec-dropout/main.c deleted file mode 100644 index 94fcd334..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-dropout/main.c +++ /dev/null @@ -1,66 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -// Include to use vector intrinsics -// Documentation: https://github.com/riscv/rvv-intrinsic-doc -// Compiler support: -// https://github.com/riscv/riscv-gnu-toolchain/tree/rvv-intrinsic - -#include "dropout.h" -#include "util.h" - -extern const unsigned int N; -extern const float SCALE; -extern const float I[] __attribute__((aligned(16))); -extern const uint8_t SEL[] __attribute__((aligned(16))); -extern float o[] __attribute__((aligned(16))); -extern float o_gold[] __attribute__((aligned(16))); - -int main() { - printf("DROPOU\n"); - unsigned long cycles1, cycles2, instr2, instr1; - - printf("Running Dropout with %d elements.\n", N); - - // Call the main kernel, and measure cycles - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - dropout_vec(N, I, SCALE, SEL, o); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - // Only count effective SPFLOP/cycle - float performance = (float)N / (cycles2 - cycles1); - printf("The execution took %ld cycles.\n", cycles2 - cycles1); - printf("The execution performed %d SFLOPs per 1000 cycles\n", - (int)(performance * 1000)); - - // Verify correctness - dropout_gold(N, I, SCALE, SEL, o_gold); - - for (unsigned int k = 0; k < N; ++k) { - if (o[k] != o_gold[k]) { - printf("Error: o[%d] = %f != %f\n", k, o[k], o_gold[k]); - return k ? k : -1; - } - } - printf("Passed.\n"); - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-exp/exp.c b/bb-tests/workloads/src/CTest/rvv/vec-exp/exp.c deleted file mode 100644 index 6fb2e277..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-exp/exp.c +++ /dev/null @@ -1,58 +0,0 @@ -// Modified version of: -// "RISC-V VECTOR EXP FUNCTION Version by Cristóbal Ramírez Lazo, "Barcelona -// 2019"" Find details on the original version below Author: Matteo Perotti -// - -// -// RISC-V VECTOR EXP FUNCTION Version by Cristóbal Ramírez Lazo, "Barcelona -// 2019" This RISC-V Vector implementation is based on the original code -// presented by Julien Pommier - -/* - AVX implementation of sin, cos, sincos, exp and log - Based on "sse_mathfun.h", by Julien Pommier - http://gruntthepeon.free.fr/ssemath/ - Copyright (C) 2012 Giovanni Garberoglio - Interdisciplinary Laboratory for Computational Science (LISC) - Fondazione Bruno Kessler and University of Trento - via Sommarive, 18 - I-38123 Trento (Italy) - This software is provided 'as-is', without any express or implied - warranty. In no event will the authors be held liable for any damages - arising from the use of this software. - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software - in a product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not be - misrepresented as being the original software. - 3. This notice may not be removed or altered from any source distribution. - (this is the zlib license) -*/ - -#include "ara/exp.h" - -#define EXP_BMARK(t, w, l) \ - void exp_f##w##m##l##_bmark(t *exponents, t *results, size_t len) { \ - size_t avl = len; \ - vfloat##w##m##l##_t exp_vec, res_vec; \ - \ - for (size_t vl = __riscv_vsetvl_e##w##m##l(avl); avl > 0; avl -= vl) { \ - vl = __riscv_vsetvl_e##w##m##l(avl); \ - exp_vec = __riscv_vle##w##_v_f##w##m##l(exponents, vl); \ - res_vec = __exp_f##w##m##l(exp_vec, vl); \ - __riscv_vse##w##_v_f##w##m##l(results, res_vec, vl); \ - exponents += vl; \ - results += vl; \ - } \ - } - -EXP_BMARK(double, 64, 1) -EXP_BMARK(double, 64, 2) -EXP_BMARK(double, 64, 4) -EXP_BMARK(float, 32, 1) -EXP_BMARK(float, 32, 2) -EXP_BMARK(float, 32, 4) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-exp/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-exp/gen_data.py deleted file mode 100644 index 0532139a..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-exp/gen_data.py +++ /dev/null @@ -1,71 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: vector size, arg2: filter size - -import random as rand -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -def rand_matrix(N, dtype): - return np.random.rand(N).astype(dtype) - - -# SCRIPT - -if len(sys.argv) == 2: - N_f64 = int(sys.argv[1]) - N_f32 = 2 * N_f64 -else: - print("Error. Give me one argument: the number of vector elements.") - sys.exit() - -# Vector of samples -exponents_f64 = rand_matrix(N_f64, np.float64).astype(np.float64) -exponents_f32 = rand_matrix(N_f32, np.float32).astype(np.float32) - -# Results buffer -results_f64 = np.zeros(N_f64, dtype=np.float64) -results_f32 = np.zeros(N_f32, dtype=np.float32) - -# Gold results -gold_results_f64 = np.exp(exponents_f64, dtype=np.float64) -gold_results_f32 = np.exp(exponents_f32, dtype=np.float32) - -# Create the file -print('.section .data,"aw",@progbits') -emit("N_f64", np.array(N_f64, dtype=np.uint64)) -emit("exponents_f64", exponents_f64, "32") -emit("results_f64", results_f64, "32") -emit("gold_results_f64", gold_results_f64, "32") -emit("N_f32", np.array(N_f32, dtype=np.uint32)) -emit("exponents_f32", exponents_f32, "32") -emit("results_f32", results_f32, "32") -emit("gold_results_f32", gold_results_f32, "32") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-exp/main.c b/bb-tests/workloads/src/CTest/rvv/vec-exp/main.c deleted file mode 100644 index a84f85bb..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-exp/main.c +++ /dev/null @@ -1,174 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include -#include - -#include "ara/exp.h" -#include "ara/util.h" -#include "util.h" -#include - -#define N_F64 512 -#define N_F32 1024 - -extern size_t N_f64; -extern double exponents_f64[] __attribute__((aligned(32))); -extern double results_f64[] __attribute__((aligned(32))); -extern double gold_results_f64[] __attribute__((aligned(32))); - -extern size_t N_f32; -extern float exponents_f32[] __attribute__((aligned(32))); -extern float results_f32[] __attribute__((aligned(32))); -extern float gold_results_f32[] __attribute__((aligned(32))); - -double results_f64m1[N_F64] __attribute__((aligned(32))); -double results_f64m2[N_F64] __attribute__((aligned(32))); -double results_f64m4[N_F64] __attribute__((aligned(32))); -float results_f32m1[N_F32] __attribute__((aligned(32))); -float results_f32m2[N_F32] __attribute__((aligned(32))); -float results_f32m4[N_F32] __attribute__((aligned(32))); - -#define THRESHOLD 1.0 - -int check64(double *results) { - int error = 0; - for (uint64_t i = 0; i < N_f64; ++i) { - if (!similarity_check(results[i], gold_results_f64[i], THRESHOLD)) { - error = 1; - printf("64-bit error at index %d. %lx != %lx\n", i, - *(uint64_t *)(&results[i]), *(uint64_t *)(&gold_results_f64[i])); - } - } - return error; -} - -int check32(float *results) { - int error = 0; - for (uint64_t i = 0; i < N_f32; ++i) { - if (!similarity_check(results[i], gold_results_f32[i], THRESHOLD)) { - error = 1; - printf("32-bit error at index %d. %x != %x\n", i, - *(uint32_t *)(&results[i]), *(uint32_t *)(&gold_results_f32[i])); - } - } - return error; -} - -int main() { - printf("FEXP N_64=%ld N_32=%ld\n", N_f64, N_f32); - - if (N_F64 != N_f64 || N_F32 != N_f32) - return 1; - - int error = 0; - unsigned long cycles1, cycles2, instr2, instr1; - - if (N_f32 >= 256) { - for (size_t t = 8; t <= 256; t += 31) { - cycles1 = read_csr(mcycle); - exp_f32m4_bmark(exponents_f32, results_f32m2, t); - asm volatile("fence"); - cycles2 = read_csr(mcycle); - printf("32b LMUL=4 n=%ld cycles=%ld\n", t, cycles2 - cycles1); - } - } - - printf("Executing exponential on %d 64-bit data LMUL=1...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - exp_f64m1_bmark(exponents_f64, results_f64m1, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %d cycles.\n", cycles2 - cycles1); - - printf("Executing exponential on %d 64-bit data LMUL=2...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - exp_f64m2_bmark(exponents_f64, results_f64m2, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %d cycles.\n", cycles2 - cycles1); - - printf("Executing exponential on %d 64-bit data LMUL=4...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - exp_f64m4_bmark(exponents_f64, results_f64m4, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %d cycles.\n", cycles2 - cycles1); - - printf("Executing exponential on %d 32-bit data LMUL=1...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - exp_f32m1_bmark(exponents_f32, results_f32m1, N_f32); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %d cycles.\n", cycles2 - cycles1); - - printf("Executing exponential on %d 32-bit data LMUL=2...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - exp_f32m2_bmark(exponents_f32, results_f32m2, N_f32); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %d cycles.\n", cycles2 - cycles1); - - printf("Executing exponential on %d 32-bit data LMUL=4...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - exp_f32m4_bmark(exponents_f32, results_f32m4, N_f32); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("The execution took %d cycles.\n", cycles2 - cycles1); - - printf("Checking results:\n"); - - error = check64(results_f64m1); - if (error) { - return error; - } - error = check64(results_f64m2); - if (error) { - return error; - } - error = check64(results_f64m4); - if (error) { - return error; - } - error = check32(results_f32m1); - if (error) { - return error; - } - error = check32(results_f32m2); - if (error) { - return error; - } - error = check32(results_f32m4); - if (error) { - return error; - } - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d.h b/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d.h deleted file mode 100644 index 888d93a2..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d.h +++ /dev/null @@ -1,43 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef FCONV2D_H -#define FCONV2D_H - -#include -#include - -void fconv2d_3x3(double *o, double *i, double *f, int64_t R, int64_t C, - int64_t F); -void fconv2d_vec_4xC_slice_init_3x3(double *o, int64_t C); -void fconv2d_vec_4xC_slice_preload_3x3(double *i, int64_t C, int64_t F); -void fconv2d_vec_4xC_slice_move_3x3(int64_t C, int64_t F); -void fconv2d_vec_4xC_3x3(double *o, double *i, double *f, int64_t C, int64_t F); - -void fconv2d_7x7(double *o, double *i, double *f, int64_t R, int64_t C, - int64_t F); -void fconv2d_7x7_block(double *o, double *i, double *f, int64_t R, int64_t C, - int64_t n_, int64_t F); - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -// Threshold for FP numbers comparison during the final check -#define THRESHOLD 0.000000000001 -// #define THRESHOLD 0 - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d_3x3.c b/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d_3x3.c deleted file mode 100644 index f4e614e2..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d_3x3.c +++ /dev/null @@ -1,334 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "fconv2d.h" - -void fconv2d_3x3(double *o, double *i, double *f, int64_t R, int64_t C, - int64_t F) { - // We work on 4 rows of the output matrix at once - int64_t block_size_o = 4; - // We work on block_size_o + F - 1 rows of the input matrix at once - - // First iteration round, r = 0 - double *i_ = i; - double *o_ = o; - - // Preload the first two input rows -> This is not needed in the other rounds - fconv2d_vec_4xC_slice_preload_3x3(i_, C, F); - // The first F-1 rows have already been loaded by - // fconv2d_vec_4xC_slice_preload_3x3() - double *i__ = i_ + (F - 1) * (C + F - 1); - fconv2d_vec_4xC_3x3(o_, i__, f, C, F); - // Re-use some of the already-loaded input rows - fconv2d_vec_4xC_slice_move_3x3(C, F); - - i_ = i + block_size_o * (C + F - 1); - i__ = i_ + (F - 1) * (C + F - 1); - - int64_t ldi = (C + F - 1) << 3; - int64_t ldf = F << 3; - - // Temporary variables - double t0, t1, t2; - // Helper variables - double *f_; - f_ = f; - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t0) - : "r"(ldf)); - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t1) - : "r"(ldf)); - asm volatile("fld %1, (%0);" : "+&r"(f_), "=&f"(t2)); - - // Iterate over the output rows - for (int64_t r = block_size_o; r < R; r += block_size_o) { - - // The first F-1 rows have already been loaded by - // fconv2d_vec_4xC_slice_init() - - double t3, t4, t5; - - // Fetch C + F - 1 elements (padding included) - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - f_ = f; - - // Fetch the first column of the filter, and start calculating its - // contribution on the four output rows (v0, v2, v4, v6) - - // Fetch 4 + F - 1 - 2 rows of the input matrix - // Compute on C + F - 1 elements, instead of C elements, to cover the - // latency of the load instructions - asm volatile("vmv.v.v v8, v16"); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - asm volatile("vfmul.vf v0, v8, %0" ::"f"(t0)); - - asm volatile("vmv.v.v v10, v18"); - asm volatile("vfmul.vf v2, v10, %0" ::"f"(t0)); - asm volatile("vle64.v v14, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - asm volatile("vfmacc.vf v0, %0, v10" ::"f"(t1)); - - asm volatile("vfmacc.vf v2, %0, v12" ::"f"(t1)); - asm volatile("vle64.v v16, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - asm volatile("vfmacc.vf v0, %0, v12" ::"f"(t2)); - asm volatile("vslidedown.vi v20, v8, 1"); - asm volatile("vfmul.vf v4, v12, %0" ::"f"(t0)); - - asm volatile("vle64.v v18, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C)); - - asm volatile("vfmul.vf v6, v14, %0" ::"f"(t0)); - asm volatile("vslidedown.vi v22, v10, 1"); - asm volatile("vfmacc.vf v4, %0, v14" ::"f"(t1)); - asm volatile("vfmacc.vf v2, %0, v14" ::"f"(t2)); - asm volatile("vslidedown.vi v24, v12, 1"); - - asm volatile("vfmacc.vf v6, %0, v16" ::"f"(t1)); - asm volatile("vfmacc.vf v4, %0, v16" ::"f"(t2)); - - asm volatile("vslidedown.vi v26, v14, 1"); - - asm volatile("vfmacc.vf v6, %0, v18" ::"f"(t2)); - - f_ = f + 1; - // Fetch the middle column of the filter, and start calculating its - // contributions on the output rows To do so, slide down the input rows by - // one - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t3) - : "r"(ldf)); - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t4) - : "r"(ldf)); - asm volatile("fld %1, (%0);" : "+&r"(f_), "=&f"(t5)); - - asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t3)); - - asm volatile("vfmacc.vf v0, %0, v22" ::"f"(t4)); - asm volatile("vslidedown.vi v28, v16, 1"); - asm volatile("vfmacc.vf v2, %0, v22" ::"f"(t3)); - - i_ = i + (r + block_size_o) * (C + F - 1); - asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t5)); - asm volatile("vslidedown.vi v30, v18, 1"); - asm volatile("vfmacc.vf v2, %0, v24" ::"f"(t4)); - asm volatile("vfmacc.vf v4, %0, v24" ::"f"(t3)); - asm volatile("vslidedown.vi v20, v8, 2"); - - asm volatile("vfmacc.vf v2, %0, v26" ::"f"(t5)); - asm volatile("vfmacc.vf v4, %0, v26" ::"f"(t4)); - asm volatile("vslidedown.vi v22, v10, 2"); - asm volatile("vfmacc.vf v6, %0, v26" ::"f"(t3)); - i__ = i_ + (F - 1) * (C + F - 1); - - asm volatile("vfmacc.vf v4, %0, v28" ::"f"(t5)); - f_ = f + 2; - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t3) - : "r"(ldf)); - asm volatile("vfmacc.vf v6, %0, v28" ::"f"(t4)); - asm volatile("vslidedown.vi v24, v12, 2"); - - asm volatile("vfmacc.vf v6, %0, v30" ::"f"(t5)); - asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t3)); - asm volatile("vslidedown.vi v26, v14, 2"); - - // Repeat for the last filter column, and then store the output rows - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t4) - : "r"(ldf)); - asm volatile("fld %1, (%0);" : "+&r"(f_), "=&f"(t5)); - - asm volatile("vfmacc.vf v0, %0, v22" ::"f"(t4)); - o_ = o + r * C; - - // Compute on C elements - int64_t ldo = C << 3; - asm volatile("vfmacc.vf v2, %0, v22" ::"f"(t3)); - asm volatile("vslidedown.vi v28, v16, 2"); - - asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t5)); - asm volatile("vfmacc.vf v2, %0, v24" ::"f"(t4)); - asm volatile("vslidedown.vi v30, v18, 2"); - asm volatile("vse64.v v0, (%0); add %0, %0, %1" : "+&r"(o_) : "r"(ldo)); - asm volatile("vfmacc.vf v4, %0, v24" ::"f"(t3)); - - asm volatile("vfmacc.vf v2, %0, v26" ::"f"(t5)); - asm volatile("vse64.v v2, (%0); add %0, %0, %1" : "+&r"(o_) : "r"(ldo)); - asm volatile("vfmacc.vf v4, %0, v26" ::"f"(t4)); - asm volatile("vfmacc.vf v6, %0, v26" ::"f"(t3)); - - asm volatile("vfmacc.vf v4, %0, v28" ::"f"(t5)); - asm volatile("vse64.v v4, (%0); add %0, %0, %1" : "+&r"(o_) : "r"(ldo)); - asm volatile("vfmacc.vf v6, %0, v28" ::"f"(t4)); - - asm volatile("vfmacc.vf v6, %0, v30" ::"f"(t5)); - asm volatile("vse64.v v6, (%0);" : "+r"(o_)); - } -} - -// Load 4 rows of the output matrix -void fconv2d_vec_4xC_slice_preload_3x3(double *i, int64_t C, int64_t F) { - // Helper variables - int64_t ldi = (C + F - 1) << 3; - - // Set the vector configuration - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Fetch the first floor(F/2) + 1 input rows - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+r"(i)); -} - -// Calculate 4 output matrix rows -void fconv2d_vec_4xC_3x3(double *o, double *i, double *f, int64_t C, - int64_t F) { - - // Temporary variables - double t0, t1, t2; - - // Helper variables - int64_t ldo = C << 3; - int64_t ldi = (C + F - 1) << 3; - int64_t ldf = F << 3; - double *f_; - - // Fetch C + F - 1 elements (padding included) - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - f_ = f; - // Fetch the first column of the filter, and start calculating its - // contribution on the four output rows (v0, v2, v4, v6) - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t0) - : "r"(ldf)); - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t1) - : "r"(ldf)); - asm volatile("fld %1, (%0);" : "+&r"(f_), "=&f"(t2)); - - // Fetch 4 + F - 1 - 2 rows of the input matrix - // Compute on C + F - 1 elements, instead of C elements, to cover the latency - // of the load instructions - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vfmul.vf v0, v8, %0" ::"f"(t0)); - - asm volatile("vfmul.vf v2, v10, %0" ::"f"(t0)); - asm volatile("vle64.v v14, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vfmacc.vf v0, %0, v10" ::"f"(t1)); - - asm volatile("vfmacc.vf v2, %0, v12" ::"f"(t1)); - asm volatile("vle64.v v16, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vfmacc.vf v0, %0, v12" ::"f"(t2)); - asm volatile("vslidedown.vi v20, v8, 1"); - asm volatile("vfmul.vf v4, v12, %0" ::"f"(t0)); - - asm volatile("vle64.v v18, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C)); - - asm volatile("vfmul.vf v6, v14, %0" ::"f"(t0)); - asm volatile("vfmacc.vf v4, %0, v14" ::"f"(t1)); - asm volatile("vslidedown.vi v22, v10, 1"); - asm volatile("vfmacc.vf v2, %0, v14" ::"f"(t2)); - - asm volatile("vfmacc.vf v6, %0, v16" ::"f"(t1)); - asm volatile("vfmacc.vf v4, %0, v16" ::"f"(t2)); - - asm volatile("vslidedown.vi v24, v12, 1"); - asm volatile("vfmacc.vf v6, %0, v18" ::"f"(t2)); - - f_ = f + 1; - // Fetch the middle column of the filter, and start calculating its - // contributions on the output rows To do so, slide down the input rows by one - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t0) - : "r"(ldf)); - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t1) - : "r"(ldf)); - asm volatile("fld %1, (%0);" : "+&r"(f_), "=&f"(t2)); - - asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); - - asm volatile("vfmacc.vf v0, %0, v22" ::"f"(t1)); - asm volatile("vslidedown.vi v26, v14, 1"); - asm volatile("vfmacc.vf v2, %0, v22" ::"f"(t0)); - - asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t2)); - asm volatile("vfmacc.vf v2, %0, v24" ::"f"(t1)); - asm volatile("vslidedown.vi v28, v16, 1"); - asm volatile("vfmacc.vf v4, %0, v24" ::"f"(t0)); - - asm volatile("vfmacc.vf v2, %0, v26" ::"f"(t2)); - asm volatile("vfmacc.vf v4, %0, v26" ::"f"(t1)); - asm volatile("vslidedown.vi v30, v18, 1"); - asm volatile("vfmacc.vf v6, %0, v26" ::"f"(t0)); - - asm volatile("vfmacc.vf v4, %0, v28" ::"f"(t2)); - asm volatile("vslidedown.vi v20, v8, 2"); - asm volatile("vfmacc.vf v6, %0, v28" ::"f"(t1)); - - asm volatile("vfmacc.vf v6, %0, v30" ::"f"(t2)); - asm volatile("vslidedown.vi v22, v10, 2"); - - f_ = f + 2; - // Repeat for the last filter column, and then store the output rows - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t0) - : "r"(ldf)); - asm volatile("fld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&f"(t1) - : "r"(ldf)); - asm volatile("fld %1, (%0);" : "+&r"(f_), "=&f"(t2)); - - asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); - - asm volatile("vfmacc.vf v0, %0, v22" ::"f"(t1)); - asm volatile("vslidedown.vi v24, v12, 2"); - asm volatile("vfmacc.vf v2, %0, v22" ::"f"(t0)); - - // Compute on C elements - - asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t2)); - asm volatile("vse64.v v0, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vslidedown.vi v26, v14, 2"); - asm volatile("vfmacc.vf v2, %0, v24" ::"f"(t1)); - asm volatile("vfmacc.vf v4, %0, v24" ::"f"(t0)); - - asm volatile("vfmacc.vf v2, %0, v26" ::"f"(t2)); - asm volatile("vse64.v v2, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vslidedown.vi v28, v16, 2"); - asm volatile("vfmacc.vf v4, %0, v26" ::"f"(t1)); - asm volatile("vfmacc.vf v6, %0, v26" ::"f"(t0)); - - asm volatile("vfmacc.vf v4, %0, v28" ::"f"(t2)); - asm volatile("vslidedown.vi v30, v18, 2"); - asm volatile("vse64.v v4, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v6, %0, v28" ::"f"(t1)); - - asm volatile("vfmacc.vf v6, %0, v30" ::"f"(t2)); - asm volatile("vse64.v v6, (%0);" : "+r"(o)); -} - -void fconv2d_vec_4xC_slice_move_3x3(int64_t C, int64_t F) { - // Move C+F-1 elements - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Move the last floor(F/2) + 1 input rows - asm volatile("vmv.v.v v8, v16"); - asm volatile("vmv.v.v v10, v18"); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d_7x7.c b/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d_7x7.c deleted file mode 100644 index 6b69f3de..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/fconv2d_7x7.c +++ /dev/null @@ -1,636 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -/* - Optimized convolution for Ara - The code is long only because of: - 1) Special cases related to the first/last 7 rows - 2) Unrolling of the loops to hide the latency of the moves, slides, mem ops - - At the end of the file, you can find the not-unrolled main loop in a comment, - without the edge-code. - - Algorithm: - a) Load the next input row - b) Calculate its contributions to the F = 7 output rows using one column of - the filter c) Slide down the input row by 1, injecting the next input scalar - element in the tail d) Repeat from b), taking the next colum of the filter, - until the last column is fetched e) Store the first output row, the one that - is complete f) Move all the output rows up by one register, to restore the - initial condition g) Repeat from a) - - Every time a new input row is loaded, a new output row is created. - - The first 6 rows and the last 6 rows do not follow this pattern, thus we wrote - dedicated code. Because of the unrolling, we counted for this the first and - last 7 rows, instead of 6 - - This algorithm helps in minimizing the data dependencies, as every input rows - is used To calculate 7 different output rows. -*/ - -#include "fconv2d.h" - -void fconv2d_7x7(double *o, double *i, double *f, int64_t M, int64_t N, - int64_t F) { - - unsigned long int block_size_n; - - // Set the vector configuration - asm volatile("vsetvli %0, %1, e64, m2, ta, ma" : "=r"(block_size_n) : "r"(N)); - - // Slice the matrix into a manageable number of columns n_ - for (unsigned long int n = 0; n < N; n += block_size_n) { - // Set the vector length - const unsigned long int n_ = MIN(N - n, block_size_n); - - // Find pointers to the submatrices - const double *i_ = i + n; - double *o_ = o + n; - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(n_)); - - fconv2d_7x7_block(o_, i_, f, M, N, n_, F); - } -} -void fconv2d_7x7_block(double *o, double *i, double *f, int64_t R, int64_t C, - int64_t n_, int64_t F) { - - // Helper variables - int64_t ldo = C << 3; - int64_t ldi_pad = (C + F - 1) << 3; - - double *i_ = i; - - double f6, f13, f20, f27, f34, f41, f48; - - double *i_slide_ptr_0; - double *i_slide_ptr_1; - double *i_slide_ptr_2; - double *i_slide_ptr_3; - - // Buffer some of the filter coefficients not to lose efficiency after a - // vector store (CVA6 cannot issue memory operations if there is a pending - // store!) - f6 = f[6]; - f13 = f[13]; - f20 = f[20]; - f27 = f[27]; - f34 = f[34]; - f41 = f[41]; - f48 = f[48]; - - // Point to the scalar elements to insert during a slide - i_slide_ptr_0 = i_ + n_ + 0 * (C + F - 1); - i_slide_ptr_1 = i_ + n_ + 1 * (C + F - 1); - i_slide_ptr_2 = i_ + n_ + 2 * (C + F - 1); - i_slide_ptr_3 = i_ + n_ + 3 * (C + F - 1); - - //////////////// - // Row 0 -> 3 // - //////////////// - - // Load one input row - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vle64.v v4, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - if (k == 0) - asm volatile("vfmul.vf v16, v0, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[0 + (2 * k)])); - if (k == 0) - asm volatile("vfmul.vf v18, v4, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[0 + (2 * k)])); - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v4" ::"f"(f[7 + (2 * k)])); - if (k == 0) - asm volatile("vfmul.vf v22, v12, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f[0 + (2 * k)])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v18, %0, v8" ::"f"(f[7 + (2 * k)])); - asm volatile("vfmacc.vf v16, %0, v8" ::"f"(f[14 + (2 * k)])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - if (k == 0) - asm volatile("vfmul.vf v20, v8, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[0 + (2 * k)])); - asm volatile("vfmacc.vf v18, %0, v12" ::"f"(f[14 + (2 * k)])); - asm volatile("vfmacc.vf v16, %0, v12" ::"f"(f[21 + (2 * k)])); - asm volatile("vfslide1down.vf v14, v12, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v20, %0, v12" ::"f"(f[7 + (2 * k)])); - - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(f[7 + (2 * k + 1)])); - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(f[7 + (2 * k + 1)])); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfmacc.vf v18, %0, v14" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v22, %0, v14" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfmacc.vf v16, %0, v14" ::"f"(f[21 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v12, v14, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v20, %0, v14" ::"f"(f[7 + (2 * k + 1)])); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i_ + n_ + 0 * (C + F - 1); - i_slide_ptr_1 = i_ + n_ + 1 * (C + F - 1); - i_slide_ptr_2 = i_ + n_ + 2 * (C + F - 1); - - // Main kernel, last iteration with filter coefficients reuse - // Start loading next rows, from 4 to 6 - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f6)); - asm volatile("vle64.v v2, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f6)); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f6)); - asm volatile("vfmacc.vf v16, %0, v4" ::"f"(f13)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vfmacc.vf v18, %0, v8" ::"f"(f13)); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f6)); - asm volatile("vfmacc.vf v16, %0, v8" ::"f"(f20)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vfmacc.vf v18, %0, v12" ::"f"(f20)); - asm volatile("vfmacc.vf v20, %0, v12" ::"f"(f13)); - asm volatile("vfmacc.vf v16, %0, v12" ::"f"(f27)); - - //////////////// - // Row 4 -> 6 // - //////////////// - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f[21 + (2 * k)])); - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(f[35 + (2 * k)])); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(f[42 + (2 * k)])); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(f[35 + (2 * k)])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f[14 + (2 * k)])); - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(f[21 + (2 * k)])); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[28 + (2 * k)])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f[7 + (2 * k)])); - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(f[14 + (2 * k)])); - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(f[21 + (2 * k)])); - - if (k == 0) - asm volatile("vfmul.vf v24, v2, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[0 + (2 * k)])); - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(f[7 + (2 * k)])); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(f[14 + (2 * k)])); - - if (k == 0) - asm volatile("vfmul.vf v26, v6, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[0 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(f[7 + (2 * k)])); - - if (k == 0) - asm volatile("vfmul.vf v28, v10, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[0 + (2 * k)])); - - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v16, %0, v4" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfmacc.vf v16, %0, v8" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f[21 + (2 * k + 1)])); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v18, %0, v8" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(f[21 + (2 * k + 1)])); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f[7 + (2 * k + 1)])); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(f[21 + (2 * k + 1)])); - - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(f[7 + (2 * k + 1)])); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(f[14 + (2 * k + 1)])); - - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(f[7 + (2 * k + 1)])); - - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[0 + (2 * k + 1)])); - } - - // Main kernel, last iteration with filter coefficients reuse - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f34)); - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(f41)); - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(f48)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f27)); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f34)); - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(f41)); - asm volatile("vmv.v.v v16, v18"); - - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f20)); - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(f27)); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f34)); - asm volatile("vmv.v.v v18, v20"); - - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f13)); - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(f20)); - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(f27)); - asm volatile("vmv.v.v v20, v22"); - - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f6)); - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(f13)); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(f20)); - asm volatile("vmv.v.v v22, v24"); - - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f6)); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(f13)); - asm volatile("vmv.v.v v24, v26"); - - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f6)); - asm volatile("vmv.v.v v26, v28"); - - //////////// - // REGIME // - //////////// - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i_ + n_; - - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - - // The following loop is unrolled by 2 - // The input matrix has R + F - 1 rows - // We have computed F input rows already - // Compute now until only F input rows are left - // (The last F-1 rows do not contribute to F output rows each, so keep them - // outside of this loop) (We keep F rows outside because of the unrolling by - // 2, just for easeness) - for (int j = 0; j < ((R + F - 1) - 2 * F) / 2; ++j) { - // Work on F output rows - - ////////////// - // UNROLL 0 // - ////////////// - - // Main loop - for (int k = 0; k < F / 2; ++k) { - double f42, f35, f28, f21, f14, f7, f0, fs; - f42 = f[42 + (2 * k)]; - f35 = f[35 + (2 * k)]; - f28 = f[28 + (2 * k)]; - f21 = f[21 + (2 * k)]; - f14 = f[14 + (2 * k)]; - f7 = f[7 + (2 * k)]; - f0 = f[0 + (2 * k)]; - fs = *i_slide_ptr_0++; - asm volatile("" ::: "memory"); - // Calculate F contributions of the input rows, on F different output rows - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f42)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f35)); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f28)); - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(fs)); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f21)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f14)); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f7)); - if (k == 0) - asm volatile("vfmul.vf v28, v0, %0" ::"f"(f0)); - else - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f0)); - - f42 = f[42 + (2 * k + 1)]; - f35 = f[35 + (2 * k + 1)]; - f28 = f[28 + (2 * k + 1)]; - f21 = f[21 + (2 * k + 1)]; - f14 = f[14 + (2 * k + 1)]; - f7 = f[7 + (2 * k + 1)]; - f0 = f[0 + (2 * k + 1)]; - fs = *i_slide_ptr_0++; - asm volatile("" ::: "memory"); - // Calculate F contributions of the input rows, on F different output rows - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f42)); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f35)); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f28)); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(fs)); - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f21)); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f14)); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f7)); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f0)); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_1 = i_ + n_; - - // The last iteration is used to mask the latency of the store and the moves - // Use buffered coefficients not to stall CVA6 for coherency - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f48)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f41)); - asm volatile("vmv.v.v v16, v18"); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f34)); - asm volatile("vle64.v v2, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vmv.v.v v18, v20"); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f27)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f20)); - asm volatile("vmv.v.v v20, v22"); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f13)); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f6)); - asm volatile("vmv.v.v v22, v24"); - - ////////////// - // UNROLL 1 // - ////////////// - - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[42])); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f[35])); - asm volatile("vmv.v.v v24, v26"); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f[28])); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f[21])); - asm volatile("vmv.v.v v26, v28"); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[14])); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f[7])); - asm volatile("vfmul.vf v28, v2, %0" ::"f"(f[0])); - - for (int k = 1; k < F; k += 2) { - double f42, f35, f28, f21, f14, f7, f0, fs; - f42 = f[42 + k]; - f35 = f[35 + k]; - f28 = f[28 + k]; - f21 = f[21 + k]; - f14 = f[14 + k]; - f7 = f[7 + k]; - f0 = f[0 + k]; - fs = *i_slide_ptr_1++; - asm volatile("" ::: "memory"); - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f42)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f35)); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f28)); - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(fs)); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f21)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f14)); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f7)); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f0)); - - if (k == F - 2) - break; - - f42 = f[42 + k + 1]; - f35 = f[35 + k + 1]; - f28 = f[28 + k + 1]; - f21 = f[21 + k + 1]; - f14 = f[14 + k + 1]; - f7 = f[7 + k + 1]; - f0 = f[0 + k + 1]; - fs = *i_slide_ptr_1++; - asm volatile("" ::: "memory"); - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f42)); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f35)); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f28)); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(fs)); - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f21)); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f14)); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f7)); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f0)); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i_ + n_; - - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f48)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f41)); - asm volatile("vmv.v.v v16, v18"); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f34)); - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vmv.v.v v18, v20"); - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f27)); - asm volatile("vmv.v.v v20, v22"); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f20)); - asm volatile("vmv.v.v v22, v24"); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f13)); - asm volatile("vmv.v.v v24, v26"); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f6)); - asm volatile("vmv.v.v v26, v28"); - } - - //////////////////////// - // Row I-F -> (I-1)-3 // - //////////////////////// - - // Point to the scalar elements to insert during a slide - // i_slide_ptr_0 has already been computed - i_slide_ptr_1 = i_ + n_ + 0 * (C + F - 1); - i_slide_ptr_2 = i_ + n_ + 1 * (C + F - 1); - i_slide_ptr_3 = i_ + n_ + 2 * (C + F - 1); - - // Load other three input rows (one was already loaded) - asm volatile("vle64.v v4, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - // Process 4 input rows - for (int k = 0; k < F / 2; ++k) { - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[42 + (2 * k)])); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f[35 + (2 * k)])); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f[21 + (2 * k)])); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[14 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f[7 + (2 * k)])); - if (k == 0) - asm volatile("vfmul.vf v28, v0, %0" ::"f"(f[0 + (2 * k)])); - else - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f[0 + (2 * k)])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[42 + (2 * k)])); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(f[35 + (2 * k)])); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(f[21 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[14 + (2 * k)])); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(f[7 + (2 * k)])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[42 + (2 * k)])); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(f[35 + (2 * k)])); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(f[21 + (2 * k)])); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[14 + (2 * k)])); - asm volatile("vfslide1down.vf v14, v12, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f[42 + (2 * k)])); - asm volatile("vfmacc.vf v24, %0, v12" ::"f"(f[35 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v12" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v28, %0, v12" ::"f"(f[21 + (2 * k)])); - - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f[21 + (2 * k + 1)])); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f[7 + (2 * k + 1)])); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f[0 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(f[21 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(f[7 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(f[21 + (2 * k + 1)])); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[14 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v12, v14, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v22, %0, v14" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfmacc.vf v24, %0, v14" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v14" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v28, %0, v14" ::"f"(f[21 + (2 * k + 1)])); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i_ + n_ + 0 * (C + F - 1); - i_slide_ptr_1 = i_ + n_ + 1 * (C + F - 1); - i_slide_ptr_2 = i_ + n_ + 2 * (C + F - 1); - - asm volatile("vle64.v v2, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f48)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f41)); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f34)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f27)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f20)); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f13)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f6)); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f48)); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(f41)); - asm volatile("vse64.v v18, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(f34)); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(f27)); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f20)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+&r"(i_) : "r"(ldi_pad)); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(f13)); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f48)); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(f41)); - asm volatile("vse64.v v20, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(f34)); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(f27)); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f20)); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f48)); - asm volatile("vse64.v v22, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v24, %0, v12" ::"f"(f41)); - asm volatile("vfmacc.vf v26, %0, v12" ::"f"(f34)); - asm volatile("vfmacc.vf v28, %0, v12" ::"f"(f27)); - - ////////////////////////// - // Row (I-1)-3 -> (I-1) // - ////////////////////////// - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[42 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f[35 + (2 * k)])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f[28 + (2 * k)])); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[42 + (2 * k)])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(f[35 + (2 * k)])); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[42 + (2 * k)])); - - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f[28 + (2 * k + 1)])); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[42 + (2 * k + 1)])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(f[35 + (2 * k + 1)])); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[42 + (2 * k + 1)])); - } - - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f48)); - asm volatile("vse64.v v24, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f41)); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f34)); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f48)); - asm volatile("vse64.v v26, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(f41)); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f48)); - asm volatile("vse64.v v28, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); -} - -/* - //////////////////// - // MAIN ALGORITHM // - //////////////////// - - // Start calculating the pointer to the next element to be slided in - i_slide_ptr_0 = i + C; - - // Load one input row - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - - // Kernel - for (int k = 0; k < F; ++k) { - // Calculate F*F contributions of the input rows, on F different output rows - // v28 should be initialized during the first iteration - asm volatile("vfmacc.vf v16, %0, v0" :: "f"(f[42 + (2*k)])); - asm volatile("vfmacc.vf v18, %0, v0" :: "f"(f[35 + (2*k)])); - asm volatile("vfmacc.vf v20, %0, v0" :: "f"(f[28 + (2*k)])); - asm volatile("vfmacc.vf v22, %0, v0" :: "f"(f[21 + (2*k)])); - asm volatile("vfmacc.vf v24, %0, v0" :: "f"(f[14 + (2*k)])); - asm volatile("vfmacc.vf v26, %0, v0" :: "f"(f[7 + (2*k)])); - if (k == 0) - asm volatile("vfmul.vf v28, v0, %0" :: "f"(f[0 + (2*k)])); - else - asm volatile("vfmacc.vf v28, %0, v0" :: "f"(f[0 + (2*k)])); - - // Slide the input row by one, and inject the next scalar element of the row - asm volatile("vfslide1down.vf v0, v0, %0" :: "f"(*i_slide_ptr_0++)); - } - - // Store one output row - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - - // Move all the input rows to return to the initial situation - // To avoid these operations, unroll the loop via software, renaming the - registers manually asm volatile("vmv.v.v v16, v18"); asm volatile("vmv.v.v - v18, v20"); asm volatile("vmv.v.v v20, v22"); asm volatile("vmv.v.v v22, - v24"); asm volatile("vmv.v.v v24, v26"); asm volatile("vmv.v.v v26, v28"); -*/ diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/gen_data.py deleted file mode 100755 index 9bf90b96..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/gen_data.py +++ /dev/null @@ -1,123 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: image size, arg2: filter size - -import numpy as np -import sys - - -def convolve2D(kernel, image, padding): - # Default stride - strides = 1 - - # Gather Shapes of Kernel + Image + Padding - xKernShape = kernel.shape[0] - yKernShape = kernel.shape[1] - xImgShape = image.shape[0] - yImgShape = image.shape[1] - - # Shape of Output Convolution - xOutput = xImgShape - xKernShape + 1 - yOutput = yImgShape - yKernShape + 1 - output = np.zeros((xOutput, yOutput)) - - # Iterate through image - for y in range(image.shape[1]): - # Exit Convolution - if y > image.shape[1] - yKernShape: - break - # Only Convolve if y has gone down by the specified Strides - if y % strides == 0: - for x in range(image.shape[0]): - # Go to next row once kernel is out of bounds - if x > image.shape[0] - xKernShape: - break - try: - # Only Convolve if x has moved by the specified Strides - if x % strides == 0: - output[x, y] = ( - kernel * image[x : x + xKernShape, y : y + yKernShape] - ).sum() - except Exception: - break - - return output - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# Define the filter size and the matrix dimension (max, for now, is 128 64-bit elements) -if len(sys.argv) > 1: - matrix_width = int(sys.argv[1]) - assert ( - matrix_width <= 128 - ), "The width of the image cannot be greater than 128 64-bit \ - elements. If this is not enough, modify the algorithm." - f = int(sys.argv[2]) - # Filter size must be odd - assert f % 2 == 1, "The filter size must be an odd integer number" -else: - matrix_width = 64 - f = 3 - -dtype = np.float64 - -# Input image. Take a square image -M = matrix_width -N = matrix_width -padding = int(f / 2) -M_pad = M + 2 * padding -N_pad = N + 2 * padding -assert ( - M % 4 == 0 -), "Output image dimension must be divisible by 4, pad the input image accordingly" -assert ( - N % 4 == 0 -), "Output image dimension must be divisible by 4, pad the input image accordingly" - -# Generate a random float64 input padded image -image = np.random.rand(M_pad, N_pad).astype(dtype) - -# Generate a random float64 filter -gen_filter = np.random.rand(f, f).astype(dtype) - -# Create the empty o matrix -empty_o = np.zeros((M, N)).astype(dtype) - -# Calculate the output matrix -result = convolve2D(gen_filter, image, padding).astype(dtype) - -# Print information on file -print('.section .data,"aw",@progbits') -emit("M", np.array(M, dtype=np.uint64)) -emit("N", np.array(N, dtype=np.uint64)) -emit("F", np.array(f, dtype=np.uint64)) -emit("i", image, "NR_LANES*4") -emit("f", gen_filter, "NR_LANES*4") -emit("o", empty_o, "NR_LANES*4") -emit("golden_o", result, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/main.c b/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/main.c deleted file mode 100644 index 026f1a73..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv2d/main.c +++ /dev/null @@ -1,103 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include -#include -#include - -#include "ara/util.h" -#include "fconv2d.h" -#include "util.h" - -// Define Matrix dimensions: -// o = i ° f, with i=[MxN], f=[FxF], o=[MxN] -// The filter is a square matrix, and F is odd - -// Matrices defined in data.S -extern double i[] - __attribute__((aligned(32))); // [ (M+floor(F/2)) * (N+floor(F/2)) ] -extern double f[] __attribute__((aligned(32))); // [ F*F ] -extern double o[] __attribute__((aligned(32))); // [ M*N ] -extern double golden_o[] __attribute__((aligned(32))); // [ M*N ] -// M, N, F defined in data.S -extern int64_t M; -extern int64_t N; -extern int64_t F; - -// Verify the matrices -int verify_matrix(double *matrix, double *golden_matrix, int64_t R, int64_t C, - double threshold) { - for (int r = 0; r < R; ++r) - for (int c = 0; c < C; ++c) - if (!similarity_check(matrix[c + C * r], golden_matrix[c + C * r], - threshold)) { - printf("Error: o[%d][%d] = %lf, instead of %lf\n", r, c, - matrix[c + C * r], golden_matrix[c + C * r]); - return 1; - } - return 0; -} - -int main() { - printf("FCONV2D M=%ld N=%ld F=%ld\n", M, N, F); - -#if PREALLOCATE - if (F == 3) - fconv2d_3x3(o, i, f, M, N, F); - else if (F == 7) - fconv2d_7x7(o, i, f, M, N, F); - else - printf("Error: the filter size is different from 3 or 5 or 7.\n"); -#endif - - unsigned long cycles1, cycles2, instr2, instr1; - - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - - // Call the main kernel, and measure cycles - if (F == 3) - fconv2d_3x3(o, i, f, M, N, F); - else if (F == 7) - fconv2d_7x7(o, i, f, M, N, F); - else - printf("Error: the filter size is different from 3 or 5 or 7.\n"); - - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - // Performance metrics - int64_t runtime = cycles2 - cycles1; - float performance = 2.0 * F * F * M * N / runtime; - printf("operations: %d\n", F * F * M * N); - printf("The execution took %d cycles.\n", runtime); - printf("The performance is %ld DPFLOP/1000 cycles.\n", - (uint64_t)(1000.0 * performance)); - - // Verify correctness - printf("Verifying result...\n"); - int error = verify_matrix(o, golden_o, M, N, THRESHOLD); - if (error != 0) { - printf("Fail.\n"); - } else { - printf("Passed.\n"); - } - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/fconv3d.h b/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/fconv3d.h deleted file mode 100644 index 386e5506..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/fconv3d.h +++ /dev/null @@ -1,37 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef FCONV3D_H -#define FCONV3D_H - -#include -#include - -void fconv3d_CHx7x7(double *o, double *i, double *f, int64_t M, int64_t N, - int64_t C, int64_t F); - -void fconv3d_CHx7x7_block(double *o, double *i, double *f, int64_t M, int64_t N, - int64_t n_, int64_t C, int64_t F); - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -// Threshold for FP numbers comparison during the final check -#define THRESHOLD 0.000000000001 -// #define THRESHOLD 0 - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/fconv3d_3x7x7.c b/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/fconv3d_3x7x7.c deleted file mode 100644 index 422f04a8..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/fconv3d_3x7x7.c +++ /dev/null @@ -1,894 +0,0 @@ -// Nopyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LINENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WAMMANTIES OM NONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -/* - Optimized convolution for Ara - The code is long only because of: - 1) Special cases related to the first/last 7 rows - 2) Unrolling of the loops to hide the latency of the moves, slides, mem ops - - At the end of the file, you can find the not-unrolled main loop in a comment, - without the edge-code. - - Algorithm: - a) Load the next input row - b) Calculate its contributions to the F = 7 output rows using one column of - the filter - c) Slide down the input row by 1, injecting the next input scalar - element in the tail - d) Repeat from b), taking the next colum of the filter, - until the last column is fetched - d2) Repeat from a) for all the channels - e) Store the first output row, the one that is complete - f) Move all the output rows up by one register, to restore the initial - condition g) Repeat from a) - - Every time a new input row is loaded, a new output row is created. - - The first 6 rows and the last 6 rows do not follow this pattern, thus we wrote - dedicated code. Because of the unrolling, we counted for this the first and - last 7 rows, instead of 6 - - This algorithm helps in minimizing the data dependencies, as every input rows - is used To calculate 7 different output rows. -*/ - -#include "fconv3d.h" - -extern int64_t event_trigger; - -void fconv3d_CHx7x7(double *o, double *i, double *f, int64_t M, int64_t N, - int64_t C, int64_t F) { - - unsigned long int block_size_n; - - // Set the vector configuration - asm volatile("vsetvli %0, %1, e64, m2, ta, ma" : "=r"(block_size_n) : "r"(N)); - - // Slice the matrix into a manageable number of columns n_ - for (unsigned long int n = 0; n < N; n += block_size_n) { - // Set the vector length - const unsigned long int n_ = MIN(N - n, block_size_n); - - // Find pointers to the submatrices - const double *i_ = i + n; - double *o_ = o + n; - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(n_)); - - fconv3d_CHx7x7_block(o_, i_, f, M, N, n_, C, F); - } -} - -void fconv3d_CHx7x7_block(double *o, double *i, double *f, int64_t M, int64_t N, - int64_t n_, int64_t C, int64_t F) { - - // Helper variables - int64_t ldo = N << 3; - int64_t ldi_pad = (N + F - 1) << 3; - - // Number of elements that separates two adjacent channels - int64_t ich_len = (M + F - 1) * (N + F - 1); - int64_t fch_len = F * F; - - double *i_ = i; - double *i__ = i; - - // Very last column of coefficients - double fl0, fl1, fl2, fl3, fl4, fl5, fl6; - // Buffers for coefficients preloading (solve 16-lane starvation problem) - double f0_buf, f1_buf, f2_buf, f3_buf, f4_buf, f5_buf, f6_buf; - - double *i_slide_ptr_0; - double *i_slide_ptr_1; - double *i_slide_ptr_2; - double *i_slide_ptr_3; - - // Buffer some of the filter coefficients not to lose efficiency after a - // vector store (CVA6 cannot issue memory operations if there is a pending - // store!) - int64_t last_f_column = (C - 1) * fch_len + F - 1; - - fl0 = f[last_f_column + 0 * F]; - fl1 = f[last_f_column + 1 * F]; - fl2 = f[last_f_column + 2 * F]; - fl3 = f[last_f_column + 3 * F]; - fl4 = f[last_f_column + 4 * F]; - fl5 = f[last_f_column + 5 * F]; - fl6 = f[last_f_column + 6 * F]; - - //////////////// - // Row 0 -> 3 // - //////////////// - - // Loop on the channels - for (int ch = 0; ch < C; ++ch) { - - // Point to the first element of the channel ch - i__ = i_ + ch * ich_len; - - // Point to the scalar elements to insert during a slide - i_slide_ptr_0 = i__ + n_ + 0 * (N + F - 1); - i_slide_ptr_1 = i__ + n_ + 1 * (N + F - 1); - i_slide_ptr_2 = i__ + n_ + 2 * (N + F - 1); - i_slide_ptr_3 = i__ + n_ + 3 * (N + F - 1); - - // Load four input rows belonging to channel ch - asm volatile("vle64.v v0, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v4, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - // Unrolled because of double buffering - // With HW renaming, this unroll is not needed - for (int64_t k = 0; k < F / 2; ++k) { - // Two base indexes because of the unrolling - // Point to the first element of the current column (k) of the current - // channel (ch) of the filter (f) - int64_t base_idx_0 = (2 * k) + (ch * fch_len); - // Point to the first element of the current column (k+1) of the current - // channel (ch) of the filter (f) - int64_t base_idx_1 = (2 * k + 1) + (ch * fch_len); - - if ((k | ch) == 0) - asm volatile("vfmul.vf v16, v0, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[0 + base_idx_0])); - if ((k | ch) == 0) - asm volatile("vfmul.vf v18, v4, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[0 + base_idx_0])); - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v4" ::"f"(f[7 + base_idx_0])); - if ((k | ch) == 0) - asm volatile("vfmul.vf v22, v12, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f[0 + base_idx_0])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v18, %0, v8" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v8" ::"f"(f[14 + base_idx_0])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - if ((k | ch) == 0) - asm volatile("vfmul.vf v20, v8, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v12" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v12" ::"f"(f[21 + base_idx_0])); - asm volatile("vfslide1down.vf v14, v12, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v20, %0, v12" ::"f"(f[7 + base_idx_0])); - - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[0 + base_idx_1])); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[0 + base_idx_1])); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(f[7 + base_idx_1])); - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(f[7 + base_idx_1])); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[0 + base_idx_1])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(f[14 + base_idx_1])); - asm volatile("vfmacc.vf v18, %0, v14" ::"f"(f[14 + base_idx_1])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v22, %0, v14" ::"f"(f[0 + base_idx_1])); - asm volatile("vfmacc.vf v16, %0, v14" ::"f"(f[21 + base_idx_1])); - asm volatile("vfslide1down.vf v12, v14, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v20, %0, v14" ::"f"(f[7 + base_idx_1])); - } - - int64_t base_idx_0 = (F - 1) + (ch * fch_len); - - // Don't slide during the last iteration - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v4" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v8" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v8" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v12" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v12" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v12" ::"f"(f[21 + base_idx_0])); - } - - // Bump the input ptr - i_ += 4 * (N + F - 1); - - //////////////// - // Row 4 -> 6 // - //////////////// - - // Loop on the channels - for (int ch = 0; ch < C; ++ch) { - - // Point to the first element of the channel ch - i__ = i_ + ch * ich_len; - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i__ + n_ + 0 * (N + F - 1); - i_slide_ptr_1 = i__ + n_ + 1 * (N + F - 1); - i_slide_ptr_2 = i__ + n_ + 2 * (N + F - 1); - - asm volatile("vle64.v v2, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - // Two base indexes because of the unrolling - // Point to the first element of the current column (k) of the current - // channel (ch) of the filter (f) - int64_t base_idx_0 = (2 * k) + (ch * fch_len); - // Point to the first element of the current column (k+1) of the current - // channel (ch) of the filter (f) - int64_t base_idx_1 = (2 * k + 1) + (ch * fch_len); - - // Unroll 0 - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(f[42 + base_idx_0])); - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(f[35 + base_idx_0])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[28 + base_idx_0])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(f[21 + base_idx_0])); - - if ((k | ch) == 0) - asm volatile("vfmul.vf v24, v2, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(f[14 + base_idx_0])); - - if ((k | ch) == 0) - asm volatile("vfmul.vf v26, v6, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(f[7 + base_idx_0])); - - if ((k | ch) == 0) - asm volatile("vfmul.vf v28, v10, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[0 + base_idx_0])); - - // Unroll 1 - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v16, %0, v4" ::"f"(f[35 + base_idx_1])); - asm volatile("vfmacc.vf v16, %0, v8" ::"f"(f[42 + base_idx_1])); - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f[21 + base_idx_1])); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v18, %0, v8" ::"f"(f[35 + base_idx_1])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f[14 + base_idx_1])); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(f[21 + base_idx_1])); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[28 + base_idx_1])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f[7 + base_idx_1])); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(f[14 + base_idx_1])); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(f[21 + base_idx_1])); - - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[0 + base_idx_1])); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(f[7 + base_idx_1])); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(f[14 + base_idx_1])); - - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[0 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(f[7 + base_idx_1])); - - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[0 + base_idx_1])); - } - - // The very last iterations require mixing the instructions with the store - // and the moves - if (ch != C - 1) { - // Point to the first element of the current column (k) of the current - // channel (ch) of the filter (f) - int64_t base_idx_0 = (F - 1) + (ch * fch_len); - - // Don't slide the elements here - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(f[42 + base_idx_0])); - - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(f[35 + base_idx_0])); - - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[28 + base_idx_0])); - - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(f[21 + base_idx_0])); - - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(f[14 + base_idx_0])); - - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(f[7 + base_idx_0])); - - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[0 + base_idx_0])); - } - } - - // Reuse preloaded coefficients - // Buffer the next coefficients for faster use - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(fl4)); - f6_buf = f[42]; - asm volatile("vfmacc.vf v16, %0, v6" ::"f"(fl5)); - f5_buf = f[35]; - asm volatile("vfmacc.vf v16, %0, v10" ::"f"(fl6)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(fl3)); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(fl4)); - asm volatile("vfmacc.vf v18, %0, v10" ::"f"(fl5)); - asm volatile("vmv.v.v v16, v18"); - - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(fl2)); - f4_buf = f[28]; - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(fl3)); - f3_buf = f[21]; - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(fl4)); - asm volatile("vmv.v.v v18, v20"); - - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(fl1)); - f2_buf = f[14]; - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(fl2)); - f1_buf = f[7]; - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(fl3)); - asm volatile("vmv.v.v v20, v22"); - - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(fl0)); - f0_buf = f[0]; - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(fl1)); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(fl2)); - asm volatile("vmv.v.v v22, v24"); - - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(fl0)); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(fl1)); - asm volatile("vmv.v.v v24, v26"); - - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(fl0)); - asm volatile("vmv.v.v v26, v28"); - - // Bump the input ptr - i_ += 3 * (N + F - 1); - - //////////// - // REGIME // - //////////// - - // The following loop is unrolled by 2 - // The input matrix has M + F - 1 rows - // We have computed F input rows already - // Nompute now until only F input rows are left - // (The last F-1 rows do not contribute to F output rows each, so keep them - // outside of this loop) (We keep F rows outside because of the unrolling by - // 2, just for easeness) - for (int j = 0; j < ((M + F - 1) - 2 * F) / 2; ++j) { -#ifdef VCD_DUMP - // Start dumping VCD - event_trigger = +1; -#endif - - // Work on F output rows - - // Loop on the channels - for (int ch = 0; ch < C; ++ch) { - // Point to the first element of the channel ch - i__ = i_ + ch * ich_len; - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i__ + n_; - - asm volatile("vle64.v v0, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - - ////////////// - // UNROLL 0 // - ////////////// - - // Main loop - // Use double buffering on the filter coefficients for 16-lanes config - // The computation is too fast, and every coefficient belongs to a - // different $line At every fld, CVA6 misses, and until it does not get - // the new coefficient, it cannot dispatch the next V instruction - for (int k = 0; k < F / 2; ++k) { - // Two base indexes because of the unrolling - // Look ahead to the first element of the current column (k+2) of the - // current channel (ch) of the filter (f) - int64_t base_idx_0 = (2 * k + 2) + (ch * fch_len); - // Point to the first element of the current column (k+1) of the current - // channel (ch) of the filter (f) - int64_t base_idx_1 = (2 * k + 1) + (ch * fch_len); - double fs; - fs = *i_slide_ptr_0++; - asm volatile("" ::: "memory"); - - // Calculate F contributions of the input rows, on F different output - // rows - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f6_buf)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f5_buf)); - f6_buf = f[42 + base_idx_1]; - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f4_buf)); - f5_buf = f[35 + base_idx_1]; - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(fs)); - f4_buf = f[28 + base_idx_1]; - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f3_buf)); - f3_buf = f[21 + base_idx_1]; - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f2_buf)); - f2_buf = f[14 + base_idx_1]; - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f1_buf)); - f1_buf = f[7 + base_idx_1]; - if ((k | ch) == 0) - asm volatile("vfmul.vf v28, v0, %0" ::"f"(f0_buf)); - else - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f0_buf)); - f0_buf = f[0 + base_idx_1]; - - fs = *i_slide_ptr_0++; - asm volatile("" ::: "memory"); - - // Nalculate F contributions of the input rows, on F different output - // rows - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f6_buf)); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f5_buf)); - f6_buf = f[42 + base_idx_0]; - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f4_buf)); - f5_buf = f[35 + base_idx_0]; - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(fs)); - f4_buf = f[28 + base_idx_0]; - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f3_buf)); - f3_buf = f[21 + base_idx_0]; - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f2_buf)); - f2_buf = f[14 + base_idx_0]; - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f1_buf)); - f1_buf = f[7 + base_idx_0]; - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f0_buf)); - f0_buf = f[0 + base_idx_0]; - } - - if (ch != C - 1) { - int64_t base_idx_0 = (ch + 1) * fch_len; - - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f6_buf)); - f6_buf = f[42 + base_idx_0]; - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f5_buf)); - f5_buf = f[35 + base_idx_0]; - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f4_buf)); - f4_buf = f[28 + base_idx_0]; - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f3_buf)); - f3_buf = f[21 + base_idx_0]; - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f2_buf)); - f2_buf = f[14 + base_idx_0]; - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f1_buf)); - f1_buf = f[7 + base_idx_0]; - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f0_buf)); - f0_buf = f[0 + base_idx_0]; - } - } - - // The last iteration is used to mask the latency of the store and the moves - // Use buffered coefficients not to stall NVA6 for coherency - f6_buf = f[42]; - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(fl6)); - f5_buf = f[35]; - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(fl5)); - asm volatile("vmv.v.v v16, v18"); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(fl4)); - asm volatile("vmv.v.v v18, v20"); - f4_buf = f[28]; - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(fl3)); - asm volatile("vmv.v.v v20, v22"); - f3_buf = f[21]; - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(fl2)); - asm volatile("vmv.v.v v22, v24"); - f2_buf = f[14]; - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(fl1)); - asm volatile("vmv.v.v v24, v26"); - f1_buf = f[7]; - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(fl0)); - asm volatile("vmv.v.v v26, v28"); - f0_buf = f[0]; - - // Bump the input ptr - i_ += N + F - 1; - -#ifdef VCD_DUMP - // Stop dumping VCD - event_trigger = -1; -#endif - - ////////////// - // UNROLL 1 // - ////////////// - - // Loop on the channels - for (int ch = 0; ch < C; ++ch) { - - // Point to the first element of the channel ch - i__ = i_ + ch * ich_len; - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_1 = i__ + n_; - - asm volatile("vle64.v v2, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - - for (int k = 0; k < F / 2; ++k) { - // Two base indexes because of the unrolling - // Point to the first element of the current column (k) of the current - // channel (ch) of the filter (f) - int64_t base_idx_0 = (2 * k + 2) + (ch * fch_len); - // Point to the first element of the current column (k+1) of the current - // channel (ch) of the filter (f) - int64_t base_idx_1 = (2 * k + 1) + (ch * fch_len); - double fs; - fs = *i_slide_ptr_1++; - asm volatile("" ::: "memory"); - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f6_buf)); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f5_buf)); - f6_buf = f[42 + base_idx_1]; - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f4_buf)); - f5_buf = f[35 + base_idx_1]; - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(fs)); - f4_buf = f[28 + base_idx_1]; - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f3_buf)); - f3_buf = f[21 + base_idx_1]; - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f2_buf)); - f2_buf = f[14 + base_idx_1]; - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f1_buf)); - f1_buf = f[7 + base_idx_1]; - if ((k | ch) == 0) - asm volatile("vfmul.vf v28, v2, %0" ::"f"(f0_buf)); - else - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f0_buf)); - f0_buf = f[0 + base_idx_1]; - - fs = *i_slide_ptr_1++; - asm volatile("" ::: "memory"); - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f6_buf)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f5_buf)); - f6_buf = f[42 + base_idx_0]; - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f4_buf)); - f5_buf = f[35 + base_idx_0]; - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(fs)); - f4_buf = f[28 + base_idx_0]; - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f3_buf)); - f3_buf = f[21 + base_idx_0]; - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f2_buf)); - f2_buf = f[14 + base_idx_0]; - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f1_buf)); - f1_buf = f[7 + base_idx_0]; - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f0_buf)); - f0_buf = f[0 + base_idx_0]; - } - - if (ch != C - 1) { - int64_t base_idx_0 = (ch + 1) * fch_len; - - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f6_buf)); - f6_buf = f[42 + base_idx_0]; - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f5_buf)); - f5_buf = f[35 + base_idx_0]; - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f4_buf)); - f4_buf = f[28 + base_idx_0]; - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f3_buf)); - f3_buf = f[21 + base_idx_0]; - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f2_buf)); - f2_buf = f[14 + base_idx_0]; - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f1_buf)); - f1_buf = f[7 + base_idx_0]; - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f0_buf)); - f0_buf = f[0 + base_idx_0]; - } - } - - // The last iteration is used to mask the latency of the store and the moves - // Use buffered coefficients not to stall CVA6 for coherency - f6_buf = f[42]; - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(fl6)); - f5_buf = f[35]; - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(fl5)); - asm volatile("vmv.v.v v16, v18"); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(fl4)); - asm volatile("vmv.v.v v18, v20"); - f4_buf = f[28]; - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(fl3)); - asm volatile("vmv.v.v v20, v22"); - f3_buf = f[21]; - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(fl2)); - asm volatile("vmv.v.v v22, v24"); - f2_buf = f[14]; - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(fl1)); - asm volatile("vmv.v.v v24, v26"); - f1_buf = f[7]; - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(fl0)); - asm volatile("vmv.v.v v26, v28"); - f0_buf = f[0]; - - // Bump the input ptr - i_ += N + F - 1; - } - - //////////////////////// - // Row I-F -> (I-1)-3 // - //////////////////////// - - for (int64_t ch = 0; ch < C; ++ch) { - - // Point to the first element of the channel ch - i__ = i_ + ch * ich_len; - - // Point to the scalar elements to insert during a slide - // i_slide_ptr_0 has already been computed - i_slide_ptr_0 = i__ + n_ + 0 * (N + F - 1); - i_slide_ptr_1 = i__ + n_ + 1 * (N + F - 1); - i_slide_ptr_2 = i__ + n_ + 2 * (N + F - 1); - i_slide_ptr_3 = i__ + n_ + 3 * (N + F - 1); - - // Load other three input rows (one was already loaded) - asm volatile("vle64.v v0, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v4, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - // Process 4 input rows - for (int k = 0; k < F / 2; ++k) { - // Two base indexes because of the unrolling - // Point to the first element of the current column (k) of the current - // channel (ch) of the filter (f) - int64_t base_idx_0 = (2 * k) + (ch * fch_len); - // Point to the first element of the current column (k+1) of the current - // channel (ch) of the filter (f) - int64_t base_idx_1 = (2 * k + 1) + (ch * fch_len); - - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f[7 + base_idx_0])); - if ((k | ch) == 0) - asm volatile("vfmul.vf v28, v0, %0" ::"f"(f[0 + base_idx_0])); - else - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f[0 + base_idx_0])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(f[7 + base_idx_0])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[14 + base_idx_0])); - asm volatile("vfslide1down.vf v14, v12, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v12" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v12" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v12" ::"f"(f[21 + base_idx_0])); - - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v16, %0, v2" ::"f"(f[42 + base_idx_1])); - asm volatile("vfmacc.vf v18, %0, v2" ::"f"(f[35 + base_idx_1])); - asm volatile("vfmacc.vf v20, %0, v2" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v22, %0, v2" ::"f"(f[21 + base_idx_1])); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[14 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f[7 + base_idx_1])); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f[0 + base_idx_1])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v18, %0, v6" ::"f"(f[42 + base_idx_1])); - asm volatile("vfmacc.vf v20, %0, v6" ::"f"(f[35 + base_idx_1])); - asm volatile("vfmacc.vf v22, %0, v6" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v24, %0, v6" ::"f"(f[21 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[14 + base_idx_1])); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(f[7 + base_idx_1])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v20, %0, v10" ::"f"(f[42 + base_idx_1])); - asm volatile("vfmacc.vf v22, %0, v10" ::"f"(f[35 + base_idx_1])); - asm volatile("vfmacc.vf v24, %0, v10" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v10" ::"f"(f[21 + base_idx_1])); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[14 + base_idx_1])); - asm volatile("vfslide1down.vf v12, v14, %0" ::"f"(*i_slide_ptr_3++)); - asm volatile("vfmacc.vf v22, %0, v14" ::"f"(f[42 + base_idx_1])); - asm volatile("vfmacc.vf v24, %0, v14" ::"f"(f[35 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v14" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v28, %0, v14" ::"f"(f[21 + base_idx_1])); - } - - if (ch != C - 1) { - int64_t base_idx_0 = (F - 1) + (ch * fch_len); - - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f[0 + base_idx_0])); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(f[7 + base_idx_0])); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(f[21 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[14 + base_idx_0])); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v24, %0, v12" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v12" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v12" ::"f"(f[21 + base_idx_0])); - } - } - - asm volatile("vfmacc.vf v16, %0, v0" ::"f"(fl6)); - asm volatile("vfmacc.vf v18, %0, v0" ::"f"(fl5)); - asm volatile("vfmacc.vf v20, %0, v0" ::"f"(fl4)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v22, %0, v0" ::"f"(fl3)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(fl2)); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(fl1)); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(fl0)); - asm volatile("vfmacc.vf v18, %0, v4" ::"f"(fl6)); - asm volatile("vfmacc.vf v20, %0, v4" ::"f"(fl5)); - asm volatile("vse64.v v18, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v22, %0, v4" ::"f"(fl4)); - asm volatile("vfmacc.vf v24, %0, v4" ::"f"(fl3)); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(fl2)); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(fl1)); - asm volatile("vfmacc.vf v20, %0, v8" ::"f"(fl6)); - asm volatile("vfmacc.vf v22, %0, v8" ::"f"(fl5)); - asm volatile("vse64.v v20, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v24, %0, v8" ::"f"(fl4)); - asm volatile("vfmacc.vf v26, %0, v8" ::"f"(fl3)); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(fl2)); - asm volatile("vfmacc.vf v22, %0, v12" ::"f"(fl6)); - asm volatile("vse64.v v22, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v24, %0, v12" ::"f"(fl5)); - asm volatile("vfmacc.vf v26, %0, v12" ::"f"(fl4)); - asm volatile("vfmacc.vf v28, %0, v12" ::"f"(fl3)); - - // Bump the input ptr - i_ += 4 * (N + F - 1); - - ////////////////////////// - // Row (I-1)-3 -> (I-1) // - ////////////////////////// - - for (int64_t ch = 0; ch < C; ++ch) { - - // Point to the first element of the channel ch - i__ = i_ + ch * ich_len; - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i__ + n_ + 0 * (N + F - 1); - i_slide_ptr_1 = i__ + n_ + 1 * (N + F - 1); - i_slide_ptr_2 = i__ + n_ + 2 * (N + F - 1); - - asm volatile("vle64.v v2, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" - : "+&r"(i__) - : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - // Two base indexes because of the unrolling - // Point to the first element of the current column (k) of the current - // channel (ch) of the filter (f) - int64_t base_idx_0 = (2 * k) + (ch * fch_len); - // Point to the first element of the current column (k+1) of the current - // channel (ch) of the filter (f) - int64_t base_idx_1 = (2 * k + 1) + (ch * fch_len); - - asm volatile("vfslide1down.vf v0, v2, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f[35 + base_idx_0])); - asm volatile("vfslide1down.vf v4, v6, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[42 + base_idx_0])); - asm volatile("vfslide1down.vf v8, v10, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[42 + base_idx_0])); - - asm volatile("vfslide1down.vf v2, v0, %0" ::"f"(*i_slide_ptr_0++)); - asm volatile("vfmacc.vf v24, %0, v0" ::"f"(f[42 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v0" ::"f"(f[35 + base_idx_1])); - asm volatile("vfslide1down.vf v6, v4, %0" ::"f"(*i_slide_ptr_1++)); - asm volatile("vfmacc.vf v28, %0, v0" ::"f"(f[28 + base_idx_1])); - asm volatile("vfmacc.vf v26, %0, v4" ::"f"(f[42 + base_idx_1])); - asm volatile("vfslide1down.vf v10, v8, %0" ::"f"(*i_slide_ptr_2++)); - asm volatile("vfmacc.vf v28, %0, v4" ::"f"(f[35 + base_idx_1])); - asm volatile("vfmacc.vf v28, %0, v8" ::"f"(f[42 + base_idx_1])); - } - - if (ch != C - 1) { - int64_t base_idx_0 = (F - 1) + (ch * fch_len); - - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(f[28 + base_idx_0])); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(f[42 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(f[35 + base_idx_0])); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(f[42 + base_idx_0])); - } - } - - asm volatile("vfmacc.vf v24, %0, v2" ::"f"(fl6)); - asm volatile("vse64.v v24, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v26, %0, v2" ::"f"(fl5)); - asm volatile("vfmacc.vf v28, %0, v2" ::"f"(fl4)); - asm volatile("vfmacc.vf v26, %0, v6" ::"f"(fl6)); - asm volatile("vse64.v v26, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vfmacc.vf v28, %0, v6" ::"f"(fl5)); - asm volatile("vfmacc.vf v28, %0, v10" ::"f"(fl6)); - asm volatile("vse64.v v28, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/gen_data.py deleted file mode 100755 index ae7d6274..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/gen_data.py +++ /dev/null @@ -1,131 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: image size, arg2: filter size - -import numpy as np -import sys - - -def convolve2D(kernel, image, padding): - # Default stride - strides = 1 - - # Gather Shapes of Kernel + Image + Padding - xKernShape = kernel.shape[0] - yKernShape = kernel.shape[1] - xImgShape = image.shape[0] - yImgShape = image.shape[1] - - # Shape of Output Convolution - xOutput = xImgShape - xKernShape + 1 - yOutput = yImgShape - yKernShape + 1 - output = np.zeros((xOutput, yOutput)) - - # Iterate through image - for y in range(image.shape[1]): - # Exit Convolution - if y > image.shape[1] - yKernShape: - break - # Only Convolve if y has gone down by the specified Strides - if y % strides == 0: - for x in range(image.shape[0]): - # Go to next row once kernel is out of bounds - if x > image.shape[0] - xKernShape: - break - try: - # Only Convolve if x has moved by the specified Strides - if x % strides == 0: - output[x, y] = ( - kernel * image[x : x + xKernShape, y : y + yKernShape] - ).sum() - except Exception: - break - - return output - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# Define the filter size and the matrix dimension (max, for now, is 128 64-bit elements) -if len(sys.argv) > 1: - matrix_width = int(sys.argv[1]) - # assert(matrix_width <= 128), "The width of the image cannot be greater than 128 64-bit \ - # elements. If this is not enough, modify the algorithm." - F = int(sys.argv[2]) - # Filter size must be odd - assert F % 2 == 1, "The filter size must be an odd integer number" -else: - matrix_width = 64 - F = 3 - -# 64-bit data -dtype = np.float64 - -# Input image. Take a square image -M = matrix_width -N = matrix_width -# 3 Channels -CH = 3 -padding = int(F / 2) -M_pad = M + 2 * padding -N_pad = N + 2 * padding -assert ( - M % 4 == 0 -), "Output image dimension must be divisible by 4, pad the input image accordingly" -assert ( - N % 4 == 0 -), "Output image dimension must be divisible by 4, pad the input image accordingly" - -image = list() -# Generate a random float64 input padded image -for ch in range(CH): - image += [np.random.rand(M_pad, N_pad).astype(dtype)] - -gen_filter = list() -# Generate a random float64 filter -for ch in range(CH): - gen_filter += [np.random.rand(F, F).astype(dtype)] - -# Create the empty o matrix -empty_o = np.zeros((M, N)).astype(dtype) - -# Calculate the output matrix -result = np.zeros((M, N)).astype(dtype) -for ch in range(CH): - result += convolve2D(gen_filter[ch], image[ch], padding).astype(dtype) - -# Print information on file -print('.section .data,"aw",@progbits') -emit("M", np.array(M, dtype=np.uint64)) -emit("N", np.array(N, dtype=np.uint64)) -emit("F", np.array(F, dtype=np.uint64)) -emit("CH", np.array(CH, dtype=np.uint64)) -emit("i", np.concatenate(image), "NR_LANES*4") -emit("f", np.concatenate(gen_filter), "NR_LANES*4") -emit("o", empty_o, "NR_LANES*4") -emit("golden_o", result, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/main.c b/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/main.c deleted file mode 100644 index eec76a4d..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fconv3d/main.c +++ /dev/null @@ -1,101 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include -#include -#include - -#include "ara/util.h" -#include "fconv3d.h" -#include "util.h" - -// Define Matrix dimensions: -// o = i ° f, with i=[(M+F-1)x(N+f-1)xCH], f=[FxFxCH], o=[MxN] -// The filter is a square matrix, and F is odd - -// Matrices defined in data.S -extern double i[] - __attribute__((aligned(32))); // [ (M+floor(F/2)) * (N+floor(F/2)) * CH ] -extern double f[] __attribute__((aligned(32))); // [ F*F*CH ] -extern double o[] __attribute__((aligned(32))); // [ M*N ] -extern double golden_o[] __attribute__((aligned(32))); // [ M*N ] -// M, N, F defined in data.S -extern int64_t M; -extern int64_t N; -extern int64_t CH; -extern int64_t F; - -// Verify the matrices -int verify_matrix(double *matrix, double *golden_matrix, int64_t R, int64_t C, - double threshold) { - for (int r = 0; r < R; ++r) - for (int c = 0; c < C; ++c) - if (!similarity_check(matrix[c + C * r], golden_matrix[c + C * r], - threshold)) { - printf("Error: o[%d][%d] = %lf, instead of %lf\n", r, c, - matrix[c + C * r], golden_matrix[c + C * r]); - return 1; - } - return 0; -} - -int main() { - printf("FCONV3D float64\n"); - printf("Input Mtx size: %dx%d\n", M + F - 1, N + F - 1); - printf("Output Mtx size: %dx%d\n", M, N); - printf("Filter size: %dx%d\n", F, F); - printf("Channels: %d\n", CH); - -#if PREALLOCATE - if (F == 7) - fconv3d_CHx7x7(o, i, f, M, N, CH, F); - else - printf("Error: the filter size is different from 7.\n"); -#endif - - unsigned long cycles1, cycles2, instr2, instr1; - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - // Call the main kernel, and measure cycles - if (F == 7) - fconv3d_CHx7x7(o, i, f, M, N, CH, F); - else - printf("Error: the filter size is different from 7.\n"); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - // Performance metrics - int64_t runtime = cycles2 - cycles1; - float performance = 2.0 * CH * F * F * M * N / runtime; - printf("Operations: %ld\n", CH * F * F * M * N); - printf("The execution took %d cycles.\n", runtime); - printf("The performance is %ld DPFLOP/1000 cycles.\n", - (uint64_t)(1000.0 * performance)); - - // Verify correctness - printf("Verifying result...\n"); - int error = verify_matrix(o, golden_o, M, N, THRESHOLD); - if (error != 0) { - printf("Fail.\n"); - } else { - printf("Passed.\n"); - } - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fdotprod/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-fdotprod/gen_data.py deleted file mode 100755 index 8c2f4b48..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fdotprod/gen_data.py +++ /dev/null @@ -1,85 +0,0 @@ -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Generate input data for fdotp benchmark -# arg: #elements per vector - -import numpy as np -import random -from functools import reduce -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# Vector length -if len(sys.argv) > 1: - vsize = int(sys.argv[1]) -else: - # Default: no stripmine - vsize = 64 - -avl64 = int(vsize) -avl32 = int(vsize) -avl16 = int(vsize) - -# Create the vectors -v64a = np.random.rand(avl64).astype(np.float64) -v64b = np.random.rand(avl64).astype(np.float64) -v32a = np.random.rand(avl32).astype(np.float32) -v32b = np.random.rand(avl32).astype(np.float32) -v16a = np.random.rand(avl16).astype(np.float16) -v16b = np.random.rand(avl16).astype(np.float16) - -# Create the golden output -gold64 = reduce(lambda a, b: a + b, np.multiply(v64a, v64b)) -gold32 = reduce(lambda a, b: a + b, np.multiply(v32a, v32b)) -gold16 = reduce(lambda a, b: a + b, np.multiply(v16a, v16b)) -gold16 = np.array([gold16, gold16]) - -# Create the empty result vectors -res64 = 0 -res32 = 0 -res16 = 0 - -# Print information on file -print('.section .data,"aw",@progbits') -emit("vsize", np.array(vsize, dtype=np.uint64)) -emit("v64a", v64a, "32") -emit("v64b", v64b, "32") -emit("v32a", v32a, "32") -emit("v32b", v32b, "32") -emit("v16a", v16a, "32") -emit("v16b", v16b, "32") -emit("gold64", np.array(gold64, dtype=np.float64)) -emit("gold32", np.array(gold32, dtype=np.float32)) -emit("gold16", gold16, "32") -emit("res64_v", np.array(res64, dtype=np.float64)) -emit("res32_v", np.array(res32, dtype=np.float32)) -emit("res16_v", np.array(res16, dtype=np.float32)) -emit("res64_s", np.array(res64, dtype=np.float64)) -emit("res32_s", np.array(res32, dtype=np.float32)) -emit("res16_s", np.array(res16, dtype=np.float32)) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fdotprod/main.c b/bb-tests/workloads/src/CTest/rvv/vec-fdotprod/main.c deleted file mode 100644 index 4e18c7fc..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fdotprod/main.c +++ /dev/null @@ -1,91 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "util.h" -#include -#include - -#include "ara/fdotproduct.h" -#include "ara/util.h" -#include - -// Threshold for FP comparisons -#define THRESHOLD_64b 0.0000000001 -#define THRESHOLD_32b 0.0001 -#define THRESHOLD_16b 1 - -// Vector size (Byte) -extern uint64_t vsize; -// Input vectors -extern double v64a[] __attribute__((aligned(256))); -extern double v64b[] __attribute__((aligned(256))); -extern float v32a[] __attribute__((aligned(256))); -extern float v32b[] __attribute__((aligned(256))); -extern _Float16 v16a[] __attribute__((aligned(256))); -extern _Float16 v16b[] __attribute__((aligned(256))); -// Golden outputs -extern double gold64; -extern float gold32; -extern _Float16 gold16; -// Output vectors -extern double res64_v, res64_s; -extern float res32_v, res32_s; -extern _Float16 res16_v, res16_s; - -int main() { - printf("FDOTP\n"); - - unsigned long cycles1, cycles2, instr2, instr1; - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - printf("Calulating 64b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res64_v = fdotp_v64b(v64a, v64b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector runtime: %ld\n", cycles2 - cycles1); - } - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - printf("Calulating 32b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res32_v = fdotp_v32b(v32a, v32b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector runtime: %ld\n", cycles2 - cycles1); - } - - for (uint64_t avl = 8; avl <= vsize; avl *= 8) { - printf("Calulating 16b dotp with vectors with length = %lu\n", avl); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - res16_v = fdotp_v16b(v16a, v16b, avl); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Vector runtime: %ld\n", cycles2 - cycles1); - } - - printf("SUCCESS.\n"); - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fft/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-fft/dataset1.h deleted file mode 100644 index e24c6c7c..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fft/dataset1.h +++ /dev/null @@ -1,4450 +0,0 @@ -#define LOG2_DATA_SIZE 10 -#define DATA_SIZE 1024 -float input_Xr[DATA_SIZE] = { - 0.171875f, 1.21875f, 0.765625f, 6.625f, 0.0f, 2.40625f, - 12.8125f, 0.265625f, 1.15625f, 0.125f, 6.625f, 0.0f, - 1.640625f, 4.3125f, 0.515625f, 3.09375f, 4.40625f, 3.8125f, - 7.875f, 1.890625f, 2.703125f, 14.0f, 4.75f, 3.203125f, - 3.0f, 6.0f, 3.6875f, 7.03125f, 0.328125f, 2.25f, - 1.6640625f, 14.375f, 7.5f, 0.4375f, 0.953125f, 3.40625f, - 0.8359375f, 1.5625f, 12.0f, 15.4375f, 1.21875f, 0.1640625f, - 0.90625f, 12.125f, 1.9765625f, 5.0f, 2.453125f, 1.796875f, - 2.03125f, 0.3671875f, 0.453125f, 3.15625f, 1.1875f, 0.0625f, - 1.1484375f, 0.265625f, 1.21875f, 0.34375f, 5.625f, 0.328125f, - 3.921875f, 9.25f, 2.21875f, 5.0f, 5.625f, 0.125f, - 12.8125f, 0.3125f, 11.4375f, 1.6484375f, 7.4375f, 0.7734375f, - 3.15625f, 5.9375f, 0.5625f, 5.1875f, 3.75f, 0.421875f, - 15.875f, 4.75f, 6.0625f, 3.90625f, 7.8125f, 5.71875f, - 0.3125f, 5.9375f, 1.7578125f, 2.875f, 0.1328125f, 0.953125f, - 1.453125f, 3.34375f, 13.3125f, 0.015625f, 7.8125f, 4.9375f, - 0.59375f, 0.5f, 1.21875f, 12.9375f, 0.78125f, 9.9375f, - 0.203125f, 0.4375f, 3.625f, 6.875f, 1.6796875f, 0.609375f, - 0.046875f, 1.703125f, 1.765625f, 4.3125f, 1.1015625f, 1.03125f, - 4.4375f, 0.625f, 11.6875f, 1.5859375f, 3.421875f, 9.1875f, - 7.4375f, 0.5703125f, 6.9375f, 1.2734375f, 5.25f, 1.1484375f, - 2.46875f, 1.25f, 4.59375f, 0.40625f, 0.703125f, 1.609375f, - 1.8046875f, 4.40625f, 11.5f, 4.5f, 0.734375f, 3.3125f, - 3.734375f, 1.125f, 0.75f, 2.28125f, 5.40625f, 0.1875f, - 0.4375f, 7.0625f, 1.8359375f, 1.625f, 1.3984375f, 3.75f, - 3.40625f, 1.921875f, 2.5f, 3.578125f, 0.5390625f, 3.875f, - 7.8125f, 12.8125f, 2.1875f, 0.0f, 3.28125f, 3.0625f, - 0.6953125f, 1.1171875f, 0.8125f, 2.6875f, 1.171875f, 1.3359375f, - 7.75f, 0.8125f, 0.3203125f, 0.03125f, 0.8125f, 7.0f, - 1.125f, 0.796875f, 1.640625f, 3.03125f, 2.78125f, 0.484375f, - 1.828125f, 3.25f, 2.6875f, 7.625f, 0.890625f, 15.625f, - 1.609375f, 2.84375f, 0.6953125f, 1.203125f, 3.515625f, 0.703125f, - 1.9375f, 10.9375f, 0.1796875f, 3.0625f, 1.640625f, 1.625f, - 3.015625f, 1.828125f, 3.0625f, 0.984375f, 0.5234375f, 0.34375f, - 4.5f, 7.46875f, 3.9375f, 0.78125f, 0.59375f, 1.6015625f, - 12.0625f, 3.96875f, 2.53125f, 4.0625f, 0.4609375f, 12.375f, - 1.03125f, 1.953125f, 1.875f, 3.0f, 1.3515625f, 3.46875f, - 0.8125f, 1.953125f, 10.9375f, 0.109375f, 3.375f, 1.5f, - 1.8046875f, 1.8125f, 1.09375f, 3.84375f, 0.8671875f, 15.375f, - 1.03125f, 2.1875f, 3.875f, 4.375f, 3.515625f, 3.640625f, - 7.65625f, 2.875f, 1.4375f, 6.65625f, 1.6875f, 0.0625f, - 1.34375f, 0.9375f, 1.84375f, 2.375f, 0.5f, 2.625f, - 10.3125f, 0.53125f, 3.6875f, 0.25f, 3.65625f, 7.40625f, - 1.375f, 7.375f, 3.8125f, 4.0f, 0.953125f, 1.0546875f, - 0.1171875f, 2.65625f, 3.40625f, 3.59375f, 0.90625f, 3.96875f, - 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-import numpy -import argparse - -parser = argparse.ArgumentParser(description="Generate fft2 dataset") -parser.add_argument( - "log2size", metavar="M", type=int, nargs="?", default=6, help="log2(FFT size)" -) -args = parser.parse_args() - -M = args.log2size -N = 1 << M - -dtype = numpy.float32 -info = numpy.finfo(dtype) -nmant = 8 # Limit precision to avoid rounding errors -maxmant = 1 << nmant -minexp = 1 - nmant # info.minexp / 2 -maxexp = -3 # (info.maxexp / 2) - nmant - - -# Generate floating-point values with exact mantissa and exponent -def randf(n): - return numpy.ldexp( - numpy.random.randint(maxmant, size=n), - numpy.random.randint(minexp, maxexp, size=n), - ) - - -Xr = randf(N).astype(dtype) -Xi = randf(N).astype(dtype) -X = Xr.astype(numpy.complex128 if dtype == numpy.float64 else numpy.complex64) -X.imag = Xi -Y = numpy.fft.fft(X) - -# Precompute "long weight vector" (Baily 1987), which stores twiddle -# factors for each stage separately to enable unit-stride access -# -# for stage p = 1 to M -# for k = 0 to N/(2^p) - 1 -# A = k * 2^{p-1} -# W = e^{-j 2\pi A / N} = e^{-j \pi k 2^p / N} -# -# Omit final two stages (i = 1, 0) with trivial twiddle factor -# components {-1, 0, 1} -angles = [] -for i in range(M - 1, -1, -1): - size = 1 << i # N / 2^p - for k in range(0, size): - angles.append((-k / size) * numpy.pi) - -Wr = numpy.cos(angles).astype(dtype) -Wi = numpy.sin(angles).astype(dtype) - - -def print_array(name, data, data_size="DATA_SIZE", fold=10): - print("float {}[{}] = {{".format(name, data_size)) - for i in range(0, len(data), fold): - print(" ", ", ".join("{}f".format(x) for x in data[i : i + fold]), ",", sep="") - print("};") - - -print("#define LOG2_DATA_SIZE {}".format(M)) -print("#define DATA_SIZE {}".format(N)) -print_array("input_Xr", Xr) -print_array("input_Xi", Xi) -print_array("input_Wr", Wr, "DATA_SIZE-1") -print_array("input_Wi", Wi, "DATA_SIZE-1") -print_array("verify_Xr", Y.real.astype(dtype)) -print_array("verify_Xi", Y.imag.astype(dtype)) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fft/fft2_main.c b/bb-tests/workloads/src/CTest/rvv/vec-fft/fft2_main.c deleted file mode 100644 index 1567c577..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fft/fft2_main.c +++ /dev/null @@ -1,54 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// fft2 benchmark -//-------------------------------------------------------------------------- -// - -#include "fft2.h" -#include "util.h" - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -int main(int argc, char *argv[]) { -#if PREALLOCATE - for (size_t i = 0; i < DATA_SIZE - 1; i++) { - volatile float tmp; - tmp = input_Xr[i]; - tmp = input_Xi[i]; - tmp = input_Wr[i]; - tmp = input_Wi[i]; - } -#endif - - // Do the FFT - setStats(1); - fft2(input_Xr, input_Xi, input_Wr, input_Wi, DATA_SIZE, LOG2_DATA_SIZE); - setStats(0); - -#define VERIFY -#ifdef VERIFY -#define FFT_MAX_ERROR (10e-8f) - // Check the results - { - size_t i; - for (i = 0; i < DATA_SIZE; i++) { - float rdiff, idiff, err; - rdiff = input_Xr[i] - verify_Xr[i]; - idiff = input_Xi[i] - verify_Xi[i]; - - err = (rdiff * rdiff) + (idiff * idiff); - if (err > FFT_MAX_ERROR) { - return (i + 1); - } - } - } -#endif - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-fft/vec-fft2.c b/bb-tests/workloads/src/CTest/rvv/vec-fft/vec-fft2.c deleted file mode 100644 index b93aeae3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-fft/vec-fft2.c +++ /dev/null @@ -1,225 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vectorized decimation-in-frequency radix-2 FFT -//-------------------------------------------------------------------------- -#include "fft2.h" - -void fft2(float Xr[], float Xi[], const float Wr[], const float Wi[], size_t N, - size_t M) { - { - size_t N1, N2; - float *end; - - end = Xr + N; - - for (N1 = N; N1 > 4;) { - float *Xr0; - float *Xi0; - float *Xr1; - float *Xi1; - const float *wr; - const float *wi; - - N2 = N1 / 2; - - Xr0 = Xr; // Lower half - Xi0 = Xi; - Xr1 = Xr + N2; // Upper half - Xi1 = Xi + N2; - - // Iterate over butterfly groups - do { - size_t n; - - n = N2; - wr = Wr; - wi = Wi; - // Iterate over butterflies in group - do { - size_t vl; - __asm__ __volatile__("vsetvli %0, %1, e32, m4, ta, ma" - "\n\t" - : "=r"(vl) - : "r"(n)); - - __asm__ __volatile__("vle32.v v8, %0" - "\n\t" // ar - "vle32.v v12, %1" - "\n\t" // br - "vle32.v v16, %2" - "\n\t" // ai - "vle32.v v20, %3" - "\n\t" // bi - - "vfsub.vv v24, v8, v12" - "\n\t" // ar - br - "vle32.v v4, %5" - "\n\t" // Wi - "vfsub.vv v28, v16, v20" - "\n\t" // ai - bi - "vle32.v v0, %4" - "\n\t" // Wr - "vfadd.vv v16, v16, v20" - "\n\t" // ai' = ai + bi - "vfmul.vv v20, v24, v4" - "\n\t" // Wi * (ar - br) - "vfmul.vv v4, v28, v4" - "\n\t" // Wi * (ai - bi) - "vfadd.vv v8, v8, v12" - "\n\t" // ar' = ar + br - - "vse32.v v16, %2" - "\n\t" // ai' - - "vfmadd.vv v28, v0, v20" - "\n\t" // bi' = Wr * (ai - bi) + Wi * (ar - br) - "vfmsub.vv v24, v0, v4" - "\n\t" // br' = Wr * (ar - br) - Wi * (ai - bi) - - "vse32.v v8, %0" - "\n\t" // ar' - "vse32.v v28, %3" - "\n\t" // bi' - "vse32.v v24, %1" - "\n\t" // br' - - : - : "A"(*Xr0), "A"(*Xr1), "A"(*Xi0), "A"(*Xi1), - "A"(*wr), "A"(*wi)); - - n -= vl; - wr += vl; - wi += vl; - Xr0 += vl; - Xi0 += vl; - Xr1 += vl; - Xi1 += vl; - - } while (n > 0); - - Xr0 = Xr1; - Xi0 = Xi1; - Xr1 += N2; - Xi1 += N2; - - } while (Xr1 < end); - - Wr = wr; - Wi = wi; - N1 = N2; - } - } - - { - float *xr; - float *xi; - size_t n; - - /* Stage M-2 */ - xr = Xr; - xi = Xi; - n = N / 4; - do { - size_t vl; - __asm__ __volatile__("vsetvli %0, %1, e32, m2, ta, ma" - "\n\t" - : "=r"(vl) - : "r"(n)); - - __asm__ __volatile__("vlseg4e32.v v0, %0" - "\n\t" - "vlseg4e32.v v8, %1" - "\n\t" - - "vfadd.vv v16, v0, v4" - "\n\t" // xr[0] + xr[2] - "vfadd.vv v18, v2, v6" - "\n\t" // xr[1] + xr[3] - "vfsub.vv v20, v0, v4" - "\n\t" // xr[0] - xr[2] - "vfsub.vv v22, v10, v14" - "\n\t" // xi[1] - xi[3] - - "vfsub.vv v30, v6, v2" - "\n\t" // xr[3] - xr[1] - "vfadd.vv v24, v8, v12" - "\n\t" // xi[0] + xi[2] - "vfadd.vv v26, v10, v14" - "\n\t" // xi[1] + xi[3] - "vfsub.vv v28, v8, v12" - "\n\t" // xi[0] - xi[2] - - "vsseg4e32.v v16, %0" - "\n\t" - "vsseg4e32.v v24, %1" - "\n\t" - : - : "A"(*xr), "A"(*xi)); - - n -= vl; - xr += 4 * vl; - xi += 4 * vl; - } while (n > 0); - - /* Stage M-1 */ - xr = Xr; - xi = Xi; - n = N / 2; - do { - size_t vl; - __asm__ __volatile__("vsetvli %0, %1, e32, m4, ta, ma" - "\n\t" - : "=r"(vl) - : "r"(n)); - - __asm__ __volatile__("vlseg2e32.v v0, %0" - "\n\t" - "vlseg2e32.v v8, %1" - "\n\t" - - "vfadd.vv v16, v0, v4" - "\n\t" // xr[0] + xr[1] - "vfsub.vv v20, v0, v4" - "\n\t" // xr[0] - xr[1] - "vfadd.vv v24, v8, v12" - "\n\t" // xi[0] + xi[1] - "vfsub.vv v28, v8, v12" - "\n\t" // xi[0] - xi[1] - - "vsseg2e32.v v16, %0" - "\n\t" - "vsseg2e32.v v24, %1" - "\n\t" - : - : "A"(*xr), "A"(*xi)); - - n -= vl; - xr += 2 * vl; - xi += 2 * vl; - } while (n > 0); - } - - /* Bit-reversal unscrambler */ - { - size_t i, j, b; - size_t N1, N2; - N1 = N - 1; - N2 = N >> 1; - for (i = 0, j = 0; i < N1; i++) { - if (i < j) { - float z; - z = Xr[j]; - Xr[j] = Xr[i]; - Xr[i] = z; - - z = Xi[j]; - Xi[j] = Xi[i]; - Xi[i] = z; - } - b = ~i & (i + 1); - b = N2 / b; - j ^= N1 & ~(b - 1); - } - } -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/gen_data.py deleted file mode 100644 index 9f43f697..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/gen_data.py +++ /dev/null @@ -1,127 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: image size, arg2: filter size - -import numpy as np -import sys - - -def convolve2D(kernel, image, padding): - # Default stride - strides = 1 - - # Gather Shapes of Kernel + Image + Padding - xKernShape = kernel.shape[0] - yKernShape = kernel.shape[1] - xImgShape = image.shape[0] - yImgShape = image.shape[1] - - # Shape of Output Convolution - xOutput = xImgShape - xKernShape + 1 - yOutput = yImgShape - yKernShape + 1 - output = np.zeros((xOutput, yOutput)) - - # Iterate through image - for y in range(image.shape[1]): - # Exit Convolution - if y > image.shape[1] - yKernShape: - break - # Only Convolve if y has gone down by the specified Strides - if y % strides == 0: - for x in range(image.shape[0]): - # Go to next row once kernel is out of bounds - if x > image.shape[0] - xKernShape: - break - try: - # Only Convolve if x has moved by the specified Strides - if x % strides == 0: - output[x, y] = ( - kernel * image[x : x + xKernShape, y : y + yKernShape] - ).sum() - except Exception: - break - - return output - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# Define the filter size and the matrix dimension (max, for now, is 128 64-bit elements) -if len(sys.argv) > 1: - matrix_width = int(sys.argv[1]) - assert ( - matrix_width <= 128 - ), "The width of the image cannot be greater than 128 64-bit \ - elements. If this is not enough, modify the algorithm." - F = int(sys.argv[2]) - # Filter size must be odd - assert F % 2 == 1, "The filter size must be an odd integer number" -else: - matrix_width = 64 - F = 3 - -dtype = np.int64 -MIN_DTYPE = -(2**20) -MAX_DTYPE = +(2**20) - -# Input image. Take a square image -M = matrix_width -N = matrix_width -padding = int(F / 2) -M_pad = M + 2 * padding -N_pad = N + 2 * padding -assert ( - M % 4 == 0 -), "Output image dimension must be divisible by 4, pad the input image accordingly" -assert ( - N % 4 == 0 -), "Output image dimension must be divisible by 4, pad the input image accordingly" - -# Generate a random int64 input padded image -image = np.random.randint(MIN_DTYPE, MAX_DTYPE, M_pad * N_pad, dtype).reshape( - M_pad, N_pad -) - -# Generate a random int64 filter -gen_filter = np.random.randint(MIN_DTYPE, MAX_DTYPE, F * F, dtype).reshape(F, F) - -# Create the empty o matrix -empty_o = np.zeros((M, N)).astype(np.int64) - -# Calculate the output matrix -result = np.around(convolve2D(gen_filter, image, padding)).astype(np.int64) - -# Print information on file -print('.section .data,"aw",@progbits') -emit("M", np.array(M, dtype=np.uint64)) -emit("N", np.array(N, dtype=np.uint64)) -emit("F", np.array(F, dtype=np.uint64)) -emit("i", image, "NR_LANES*4") -emit("f", gen_filter, "NR_LANES*4") -emit("o", empty_o, "NR_LANES*4") -emit("golden_o", result, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d.h b/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d.h deleted file mode 100644 index 1234e3ff..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d.h +++ /dev/null @@ -1,47 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef ICONV2D_H -#define ICONV2D_H - -#include - -void iconv2d_3x3(int64_t *o, int64_t *i, int64_t *f, int64_t R, int64_t C, - int64_t F); -void iconv2d_vec_4xC_slice_init_3x3(int64_t *o, int64_t C); -void iconv2d_vec_4xC_slice_preload_3x3(int64_t *i, int64_t C, int64_t F); -void iconv2d_vec_4xC_slice_move_3x3(int64_t C, int64_t F); -void iconv2d_vec_4xC_3x3(int64_t *o, int64_t *i, int64_t *f, int64_t C, - int64_t F); - -void iconv2d_5x5(int64_t *o, int64_t *i, int64_t *f, int64_t R, int64_t C, - int64_t F); -void iconv2d_vec_4xC_slice_init_5x5(int64_t *o, int64_t C); -void iconv2d_vec_4xC_slice_preload_5x5(int64_t *i, int64_t C, int64_t F); -void iconv2d_vec_4xC_slice_move_5x5(int64_t C, int64_t F); -void iconv2d_vec_4xC_5x5(int64_t *o, int64_t *i, int64_t *f, int64_t C, - int64_t F); - -void iconv2d_7x7(int64_t *o, int64_t *i, int64_t *f, int64_t M, int64_t N, - int64_t F); -void iconv2d_7x7_block(int64_t *o, int64_t *i, int64_t *f, int64_t R, int64_t C, - int64_t n_, int64_t F); - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_3x3.c b/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_3x3.c deleted file mode 100644 index f8176fee..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_3x3.c +++ /dev/null @@ -1,321 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "iconv2d.h" -#include - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -void iconv2d_3x3(int64_t *o, int64_t *i, int64_t *f, int64_t R, int64_t C, - int64_t F) { - // We work on 4 rows of the output matrix at once - int64_t block_size_o = 4; - // We work on block_size_o + F - 1 rows of the input matrix at once - - // First iteration round, r = 0 - int64_t *i_ = i; - int64_t *o_ = o; - - // Preload the first two input rows -> This is not needed in the other rounds - iconv2d_vec_4xC_slice_preload_3x3(i_, C, F); - // The first F-1 rows have already been loaded by - // iconv2d_vec_4xC_slice_preload_3x3() - int64_t *i__ = i_ + (F - 1) * (C + F - 1); - iconv2d_vec_4xC_3x3(o_, i__, f, C, F); - // Re-use some of the already-loaded input rows - iconv2d_vec_4xC_slice_move_3x3(C, F); - - i_ = i + block_size_o * (C + F - 1); - i__ = i_ + (F - 1) * (C + F - 1); - - int64_t ldi = (C + F - 1) << 3; - int64_t ldf = F << 3; - - // Temporary variables - int64_t t0, t1, t2; - // Helper variables - int64_t *f_; - f_ = f; - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t0) : "r"(ldf)); - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t1) : "r"(ldf)); - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t2)); - - // Iterate over the output rows - for (int64_t r = block_size_o; r < R; r += block_size_o) { - - // The first F-1 rows have already been loaded by - // iconv2d_vec_4xC_slice_init() - - int64_t t3, t4, t5; - - // Fetch C + F - 1 elements (padding included) - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - f_ = f; - - // Fetch the first column of the filter, and start calculating its - // contribution on the four output rows (v0, v2, v4, v6) - - // Fetch 4 + F - 1 - 2 rows of the input matrix - // Compute on C + F - 1 elements, instead of C elements, to cover the - // latency of the load instructions - asm volatile("vmv.v.v v8, v16"); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - asm volatile("vmul.vx v0, v8, %0" ::"r"(t0)); - - asm volatile("vmv.v.v v10, v18"); - asm volatile("vmul.vx v2, v10, %0" ::"r"(t0)); - asm volatile("vle64.v v14, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - asm volatile("vmacc.vx v0, %0, v10" ::"r"(t1)); - - asm volatile("vmacc.vx v2, %0, v12" ::"r"(t1)); - asm volatile("vle64.v v16, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - asm volatile("vmacc.vx v0, %0, v12" ::"r"(t2)); - asm volatile("vslidedown.vi v20, v8, 1"); - asm volatile("vmul.vx v4, v12, %0" ::"r"(t0)); - - asm volatile("vle64.v v18, (%0); add %0, %0, %1" : "+&r"(i__) : "r"(ldi)); - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C)); - - asm volatile("vmul.vx v6, v14, %0" ::"r"(t0)); - asm volatile("vslidedown.vi v22, v10, 1"); - asm volatile("vmacc.vx v4, %0, v14" ::"r"(t1)); - asm volatile("vmacc.vx v2, %0, v14" ::"r"(t2)); - asm volatile("vslidedown.vi v24, v12, 1"); - - asm volatile("vmacc.vx v6, %0, v16" ::"r"(t1)); - asm volatile("vmacc.vx v4, %0, v16" ::"r"(t2)); - - asm volatile("vslidedown.vi v26, v14, 1"); - - asm volatile("vmacc.vx v6, %0, v18" ::"r"(t2)); - - f_ = f + 1; - // Fetch the middle column of the filter, and start calculating its - // contributions on the output rows To do so, slide down the input rows by - // one - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t3) - : "r"(ldf)); - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t4) - : "r"(ldf)); - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t5)); - - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t3)); - - asm volatile("vmacc.vx v0, %0, v22" ::"r"(t4)); - asm volatile("vslidedown.vi v28, v16, 1"); - asm volatile("vmacc.vx v2, %0, v22" ::"r"(t3)); - - i_ = i + (r + block_size_o) * (C + F - 1); - asm volatile("vmacc.vx v0, %0, v24" ::"r"(t5)); - asm volatile("vslidedown.vi v30, v18, 1"); - asm volatile("vmacc.vx v2, %0, v24" ::"r"(t4)); - asm volatile("vmacc.vx v4, %0, v24" ::"r"(t3)); - asm volatile("vslidedown.vi v20, v8, 2"); - - asm volatile("vmacc.vx v2, %0, v26" ::"r"(t5)); - asm volatile("vmacc.vx v4, %0, v26" ::"r"(t4)); - asm volatile("vslidedown.vi v22, v10, 2"); - asm volatile("vmacc.vx v6, %0, v26" ::"r"(t3)); - i__ = i_ + (F - 1) * (C + F - 1); - - asm volatile("vmacc.vx v4, %0, v28" ::"r"(t5)); - f_ = f + 2; - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t3) - : "r"(ldf)); - asm volatile("vmacc.vx v6, %0, v28" ::"r"(t4)); - asm volatile("vslidedown.vi v24, v12, 2"); - - asm volatile("vmacc.vx v6, %0, v30" ::"r"(t5)); - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t3)); - asm volatile("vslidedown.vi v26, v14, 2"); - - // Repeat for the last filter column, and then store the output rows - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t4) - : "r"(ldf)); - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t5)); - - asm volatile("vmacc.vx v0, %0, v22" ::"r"(t4)); - o_ = o + r * C; - - // Compute on C elements - int64_t ldo = C << 3; - asm volatile("vmacc.vx v2, %0, v22" ::"r"(t3)); - asm volatile("vslidedown.vi v28, v16, 2"); - - asm volatile("vmacc.vx v0, %0, v24" ::"r"(t5)); - asm volatile("vmacc.vx v2, %0, v24" ::"r"(t4)); - asm volatile("vslidedown.vi v30, v18, 2"); - asm volatile("vse64.v v0, (%0); add %0, %0, %1" : "+&r"(o_) : "r"(ldo)); - asm volatile("vmacc.vx v4, %0, v24" ::"r"(t3)); - - asm volatile("vmacc.vx v2, %0, v26" ::"r"(t5)); - asm volatile("vse64.v v2, (%0); add %0, %0, %1" : "+&r"(o_) : "r"(ldo)); - asm volatile("vmacc.vx v4, %0, v26" ::"r"(t4)); - asm volatile("vmacc.vx v6, %0, v26" ::"r"(t3)); - - asm volatile("vmacc.vx v4, %0, v28" ::"r"(t5)); - asm volatile("vse64.v v4, (%0); add %0, %0, %1" : "+&r"(o_) : "r"(ldo)); - asm volatile("vmacc.vx v6, %0, v28" ::"r"(t4)); - - asm volatile("vmacc.vx v6, %0, v30" ::"r"(t5)); - asm volatile("vse64.v v6, (%0);" : "+r"(o_)); - } -} - -// Load 4 rows of the output matrix -void iconv2d_vec_4xC_slice_preload_3x3(int64_t *i, int64_t C, int64_t F) { - // Helper variables - int64_t ldi = (C + F - 1) << 3; - - // Set the vector configuration - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Fetch the first floor(F/2) + 1 input rows - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+r"(i)); -} - -// Calculate 4 output matrix rows -void iconv2d_vec_4xC_3x3(int64_t *o, int64_t *i, int64_t *f, int64_t C, - int64_t F) { - - // Temporary variables - int64_t t0, t1, t2; - - // Helper variables - int64_t ldo = C << 3; - int64_t ldi = (C + F - 1) << 3; - int64_t ldf = F << 3; - int64_t *f_; - - // Fetch C + F - 1 elements (padding included) - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - f_ = f; - // Fetch the first column of the filter, and start calculating its - // contribution on the four output rows (v0, v2, v4, v6) - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t0) : "r"(ldf)); - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t1) : "r"(ldf)); - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t2)); - - // Fetch 4 + F - 1 - 2 rows of the input matrix - // Compute on C + F - 1 elements, instead of C elements, to cover the latency - // of the load instructions - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vmul.vx v0, v8, %0" ::"r"(t0)); - - asm volatile("vmul.vx v2, v10, %0" ::"r"(t0)); - asm volatile("vle64.v v14, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vmacc.vx v0, %0, v10" ::"r"(t1)); - - asm volatile("vmacc.vx v2, %0, v12" ::"r"(t1)); - asm volatile("vle64.v v16, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vmacc.vx v0, %0, v12" ::"r"(t2)); - asm volatile("vslidedown.vi v20, v8, 1"); - asm volatile("vmul.vx v4, v12, %0" ::"r"(t0)); - - asm volatile("vle64.v v18, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C)); - - asm volatile("vmul.vx v6, v14, %0" ::"r"(t0)); - asm volatile("vmacc.vx v4, %0, v14" ::"r"(t1)); - asm volatile("vslidedown.vi v22, v10, 1"); - asm volatile("vmacc.vx v2, %0, v14" ::"r"(t2)); - - asm volatile("vmacc.vx v6, %0, v16" ::"r"(t1)); - asm volatile("vmacc.vx v4, %0, v16" ::"r"(t2)); - - asm volatile("vslidedown.vi v24, v12, 1"); - asm volatile("vmacc.vx v6, %0, v18" ::"r"(t2)); - - f_ = f + 1; - // Fetch the middle column of the filter, and start calculating its - // contributions on the output rows To do so, slide down the input rows by one - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t0) : "r"(ldf)); - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t1) : "r"(ldf)); - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t2)); - - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t0)); - - asm volatile("vmacc.vx v0, %0, v22" ::"r"(t1)); - asm volatile("vslidedown.vi v26, v14, 1"); - asm volatile("vmacc.vx v2, %0, v22" ::"r"(t0)); - - asm volatile("vmacc.vx v0, %0, v24" ::"r"(t2)); - asm volatile("vmacc.vx v2, %0, v24" ::"r"(t1)); - asm volatile("vslidedown.vi v28, v16, 1"); - asm volatile("vmacc.vx v4, %0, v24" ::"r"(t0)); - - asm volatile("vmacc.vx v2, %0, v26" ::"r"(t2)); - asm volatile("vmacc.vx v4, %0, v26" ::"r"(t1)); - asm volatile("vslidedown.vi v30, v18, 1"); - asm volatile("vmacc.vx v6, %0, v26" ::"r"(t0)); - - asm volatile("vmacc.vx v4, %0, v28" ::"r"(t2)); - asm volatile("vslidedown.vi v20, v8, 2"); - asm volatile("vmacc.vx v6, %0, v28" ::"r"(t1)); - - asm volatile("vmacc.vx v6, %0, v30" ::"r"(t2)); - asm volatile("vslidedown.vi v22, v10, 2"); - - f_ = f + 2; - // Repeat for the last filter column, and then store the output rows - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t0) : "r"(ldf)); - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t1) : "r"(ldf)); - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t2)); - - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t0)); - - asm volatile("vmacc.vx v0, %0, v22" ::"r"(t1)); - asm volatile("vslidedown.vi v24, v12, 2"); - asm volatile("vmacc.vx v2, %0, v22" ::"r"(t0)); - - // Compute on C elements - - asm volatile("vmacc.vx v0, %0, v24" ::"r"(t2)); - asm volatile("vse64.v v0, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vslidedown.vi v26, v14, 2"); - asm volatile("vmacc.vx v2, %0, v24" ::"r"(t1)); - asm volatile("vmacc.vx v4, %0, v24" ::"r"(t0)); - - asm volatile("vmacc.vx v2, %0, v26" ::"r"(t2)); - asm volatile("vse64.v v2, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vslidedown.vi v28, v16, 2"); - asm volatile("vmacc.vx v4, %0, v26" ::"r"(t1)); - asm volatile("vmacc.vx v6, %0, v26" ::"r"(t0)); - - asm volatile("vmacc.vx v4, %0, v28" ::"r"(t2)); - asm volatile("vslidedown.vi v30, v18, 2"); - asm volatile("vse64.v v4, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v6, %0, v28" ::"r"(t1)); - - asm volatile("vmacc.vx v6, %0, v30" ::"r"(t2)); - asm volatile("vse64.v v6, (%0);" : "+r"(o)); -} - -void iconv2d_vec_4xC_slice_move_3x3(int64_t C, int64_t F) { - // Move C+F-1 elements - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Move the last floor(F/2) + 1 input rows - asm volatile("vmv.v.v v8, v16"); - asm volatile("vmv.v.v v10, v18"); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_5x5.c b/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_5x5.c deleted file mode 100644 index 07735a8b..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_5x5.c +++ /dev/null @@ -1,216 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "iconv2d.h" -#include - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -void iconv2d_5x5(int64_t *o, int64_t *i, int64_t *f, int64_t R, int64_t C, - int64_t F) { - // We work on 2 rows of the output matrix at once - int64_t block_size_o = 2; - // We work on block_size_o + F - 1 rows of the input matrix at once - - // First iteration round, r = 0 - int64_t *i_ = i; - int64_t *o_ = o; - - // For simplicity, compute over the padding rows as well - iconv2d_vec_4xC_slice_init_5x5(o_, C); - // Preload the first two input rows -> This is not needed in the other rounds - iconv2d_vec_4xC_slice_preload_5x5(i_, C, F); - // The first (floor(F/2) + 1 = 2) rows have already been loaded by - // iconv2d_vec_4xC_slice_init() - int64_t *i__ = i_ + (F - 1) * (C + F - 1); - iconv2d_vec_4xC_5x5(o_, i__, f, C, F); - // Re-use some of the already-loaded input rows - iconv2d_vec_4xC_slice_move_5x5(C, F); - - // Iterate over the output rows - for (int64_t r = block_size_o; r < R; r += block_size_o) { - i_ = i + r * (C + F - 1); - o_ = o + r * C; - - // For simplicity, compute over the padding rows as well - iconv2d_vec_4xC_slice_init_5x5(o_, C); - // The first F-1 rows have already been loaded by - // iconv2d_vec_4xC_slice_init() - i__ = i_ + (F - 1) * (C + F - 1); - iconv2d_vec_4xC_5x5(o_, i__, f, C, F); - // Re-use some of the already-loaded input rows - iconv2d_vec_4xC_slice_move_5x5(C, F); - } -} - -// Load 4 rows of the output matrix -void iconv2d_vec_4xC_slice_init_5x5(int64_t *o, int64_t C) { - // Helper variables - int64_t ldo = C << 3; - - // Set the vector configuration - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C)); - // Fetch 2 output rows - asm volatile("vmv.v.i v0, 0; add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmv.v.i v2, 0;" : "+r"(o)); -} - -// Load 4 rows of the output matrix -void iconv2d_vec_4xC_slice_preload_5x5(int64_t *i, int64_t C, int64_t F) { - // Helper variables - int64_t ldi = (C + F - 1) << 3; - - // Set the vector configuration - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Fetch the first F-1 = 4 input rows - asm volatile("vle64.v v4, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+r"(i)); -} - -// Calculate 4 output matrix rows -void iconv2d_vec_4xC_5x5(int64_t *o, int64_t *i, int64_t *f, int64_t C, - int64_t F) { - - // Temporary variables (one filter column) - int64_t t0, t1, t2, t3, t4; - int64_t slamt; - - // Helper variables - int64_t ldo = C << 3; - int64_t ldi = (C + F - 1) << 3; - int64_t ldf = F << 3; - int64_t *f_; - - // Compute on C elements - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Fetch other 2 rows of the input matrix - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - asm volatile("vle64.v v14, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi)); - - // Compute on C elements - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C)); - f_ = f; - // Fetch the first column of the filter, and start calculating its - // contribution on the two output rows (v0, v2) - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t0) : "r"(ldf)); - asm volatile("vmacc.vx v0, %0, v4" ::"r"(t0)); - asm volatile("vmacc.vx v2, %0, v6" ::"r"(t0)); - - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t1) : "r"(ldf)); - asm volatile("vmacc.vx v0, %0, v6" ::"r"(t1)); - asm volatile("vmacc.vx v2, %0, v8" ::"r"(t1)); - - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t2) : "r"(ldf)); - asm volatile("vmacc.vx v0, %0, v8" ::"r"(t2)); - asm volatile("vmacc.vx v2, %0, v10" ::"r"(t2)); - - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t3) : "r"(ldf)); - asm volatile("vmacc.vx v0, %0, v10" ::"r"(t3)); - asm volatile("vmacc.vx v2, %0, v12" ::"r"(t3)); - - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t4)); - asm volatile("vmacc.vx v0, %0, v12" ::"r"(t4)); - asm volatile("vmacc.vx v2, %0, v14" ::"r"(t4)); - - for (int64_t idx = 1; idx < F - 1; ++idx) { - // Adjust filter mtx pointer and slide-amount - f_ = f + idx; - slamt = idx; - // Fetch the other columns of the filter (except for the last one), and - // start calculating their contributions on the two output rows (v0, v2) To - // do so, at each iteration slide down the input rows by one - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t0) - : "r"(ldf)); - asm volatile("vslidedown.vx v16, v4, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v16" ::"r"(t0)); - - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t1) - : "r"(ldf)); - asm volatile("vslidedown.vx v18, v6, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v18" ::"r"(t1)); - asm volatile("vmacc.vx v2, %0, v18" ::"r"(t0)); - - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t2) - : "r"(ldf)); - asm volatile("vslidedown.vx v20, v8, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t2)); - asm volatile("vmacc.vx v2, %0, v20" ::"r"(t1)); - - asm volatile("ld %1, (%0); add %0, %0, %2" - : "+&r"(f_), "=&r"(t3) - : "r"(ldf)); - asm volatile("vslidedown.vx v22, v10, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v22" ::"r"(t3)); - asm volatile("vmacc.vx v2, %0, v22" ::"r"(t2)); - - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t4)); - asm volatile("vslidedown.vx v24, v12, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v24" ::"r"(t4)); - asm volatile("vmacc.vx v2, %0, v24" ::"r"(t3)); - - asm volatile("vslidedown.vx v26, v14, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v2, %0, v26" ::"r"(t4)); - } - - f_ = f + (F - 1); - slamt = (F - 1); - // Repeat for the last filter column, and then store the output rows - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t0) : "r"(ldf)); - asm volatile("vslidedown.vx v16, v4, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v16" ::"r"(t0)); - - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t1) : "r"(ldf)); - asm volatile("vslidedown.vx v18, v6, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v18" ::"r"(t1)); - asm volatile("vmacc.vx v2, %0, v18" ::"r"(t0)); - - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t2) : "r"(ldf)); - asm volatile("vslidedown.vx v20, v8, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t2)); - asm volatile("vmacc.vx v2, %0, v20" ::"r"(t1)); - - asm volatile("ld %1, (%0); add %0, %0, %2" : "+&r"(f_), "=&r"(t3) : "r"(ldf)); - asm volatile("vslidedown.vx v22, v10, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v22" ::"r"(t3)); - asm volatile("vmacc.vx v2, %0, v22" ::"r"(t2)); - - asm volatile("ld %1, (%0);" : "+&r"(f_), "=&r"(t4)); - asm volatile("vslidedown.vx v24, v12, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v0, %0, v24" ::"r"(t4)); - asm volatile("vse64.v v0, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v2, %0, v24" ::"r"(t3)); - - asm volatile("vslidedown.vx v26, v14, %0" ::"r"(slamt)); - asm volatile("vmacc.vx v2, %0, v26" ::"r"(t4)); - asm volatile("vse64.v v2, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); -} - -void iconv2d_vec_4xC_slice_move_5x5(int64_t C, int64_t F) { - // Move C+F-1 elements - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(C + F - 1)); - // Move the last floor(F/2) + 1 input rows - asm volatile("vmv.v.v v4, v8"); - asm volatile("vmv.v.v v6, v10"); - asm volatile("vmv.v.v v8, v12"); - asm volatile("vmv.v.v v10, v14"); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_7x7.c b/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_7x7.c deleted file mode 100644 index 019b6540..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/iconv2d_7x7.c +++ /dev/null @@ -1,599 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -/* - Optimized convolution for Ara - The code is long only because of: - 1) Special cases related to the first/last 7 rows - 2) Unrolling of the loops to hide the latency of the moves, slides, mem ops - - At the end of the file, you can find the not-unrolled main loop in a comment, - without the edge-code. - - Algorithm: - a) Load the next input row - b) Calculate its contributions to the F = 7 output rows using one column of - the filter c) Slide down the input row by 1, injecting the next input scalar - element in the tail d) Repeat from b), taking the next colum of the filter, - until the last column is fetched e) Store the first output row, the one that - is complete f) Move all the output rows up by one register, to restore the - initial condition g) Repeat from a) - - Every time a new input row is loaded, a new output row is created. - - The first 6 rows and the last 6 rows do not follow this pattern, thus we wrote - dedicated code. Because of the unrolling, we counted for this the first and - last 7 rows, instead of 6 - - This algorithm helps in minimizing the data dependencies, as every input rows - is used To calculate 7 different output rows. -*/ - -#include "iconv2d.h" - -void iconv2d_7x7(int64_t *o, int64_t *i, int64_t *f, int64_t M, int64_t N, - int64_t F) { - - unsigned long int block_size_n; - - // Set the vector configuration - asm volatile("vsetvli %0, %1, e64, m2, ta, ma" : "=r"(block_size_n) : "r"(N)); - - // Slice the matrix into a manageable number of columns n_ - for (unsigned long int n = 0; n < N; n += block_size_n) { - // Set the vector length - const unsigned long int n_ = MIN(N - n, block_size_n); - - // Find pointers to the submatrices - const int64_t *i_ = i + n; - int64_t *o_ = o + n; - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(n_)); - - iconv2d_7x7_block(o_, i_, f, M, N, n_, F); - } -} - -void iconv2d_7x7_block(int64_t *o, int64_t *i, int64_t *f, int64_t R, int64_t C, - int64_t n_, int64_t F) { - - // Helper variables - int64_t ldo = C << 3; - int64_t ldi_pad = (C + F - 1) << 3; - - int64_t *i_ = i; - - int64_t t6, t13, t20, t27, t34, t41, t48; - - int64_t *i_slide_ptr_0; - int64_t *i_slide_ptr_1; - int64_t *i_slide_ptr_2; - int64_t *i_slide_ptr_3; - - // Buffer some of the filter coefficients not to lose efficiency after a - // vector store (CVA6 cannot issue memory operations if there is a pending - // store!) - t6 = f[6]; - t13 = f[13]; - t20 = f[20]; - t27 = f[27]; - t34 = f[34]; - t41 = f[41]; - t48 = f[48]; - - // Point to the scalar elements to insert during a slide - i_slide_ptr_0 = i + n_ + 0 * (C + F - 1); - i_slide_ptr_1 = i + n_ + 1 * (C + F - 1); - i_slide_ptr_2 = i + n_ + 2 * (C + F - 1); - i_slide_ptr_3 = i + n_ + 3 * (C + F - 1); - - //////////////// - // Row 0 -> 3 // - //////////////// - - // Load one input row - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vle64.v v4, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - if (k == 0) - asm volatile("vmul.vx v16, v0, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v16, %0, v0" ::"r"(f[0 + (2 * k)])); - if (k == 0) - asm volatile("vmul.vx v18, v4, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v18, %0, v4" ::"r"(f[0 + (2 * k)])); - asm volatile("vslide1down.vx v2, v0, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v16, %0, v4" ::"r"(f[7 + (2 * k)])); - if (k == 0) - asm volatile("vmul.vx v22, v12, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v22, %0, v12" ::"r"(f[0 + (2 * k)])); - asm volatile("vslide1down.vx v6, v4, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v18, %0, v8" ::"r"(f[7 + (2 * k)])); - asm volatile("vmacc.vx v16, %0, v8" ::"r"(f[14 + (2 * k)])); - asm volatile("vslide1down.vx v10, v8, %0" ::"r"(*i_slide_ptr_2++)); - if (k == 0) - asm volatile("vmul.vx v20, v8, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v20, %0, v8" ::"r"(f[0 + (2 * k)])); - asm volatile("vmacc.vx v18, %0, v12" ::"r"(f[14 + (2 * k)])); - asm volatile("vmacc.vx v16, %0, v12" ::"r"(f[21 + (2 * k)])); - asm volatile("vslide1down.vx v14, v12, %0" ::"r"(*i_slide_ptr_3++)); - asm volatile("vmacc.vx v20, %0, v12" ::"r"(f[7 + (2 * k)])); - - asm volatile("vmacc.vx v16, %0, v2" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v6" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v16, %0, v6" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v10" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vmacc.vx v20, %0, v10" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vslide1down.vx v4, v6, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v16, %0, v10" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v14" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vslide1down.vx v8, v10, %0" ::"r"(*i_slide_ptr_2++)); - asm volatile("vmacc.vx v22, %0, v14" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vmacc.vx v16, %0, v14" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vslide1down.vx v12, v14, %0" ::"r"(*i_slide_ptr_3++)); - asm volatile("vmacc.vx v20, %0, v14" ::"r"(f[7 + (2 * k + 1)])); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i + n_ + 0 * (C + F - 1); - i_slide_ptr_1 = i + n_ + 1 * (C + F - 1); - i_slide_ptr_2 = i + n_ + 2 * (C + F - 1); - - // Main kernel, last iteration with filter coefficients reuse - // Start loading next rows, from 4 to 6 - asm volatile("vmacc.vx v16, %0, v0" ::"r"(t6)); - asm volatile("vle64.v v2, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmacc.vx v18, %0, v4" ::"r"(t6)); - asm volatile("vmacc.vx v22, %0, v12" ::"r"(t6)); - asm volatile("vmacc.vx v16, %0, v4" ::"r"(t13)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmacc.vx v18, %0, v8" ::"r"(t13)); - asm volatile("vmacc.vx v20, %0, v8" ::"r"(t6)); - asm volatile("vmacc.vx v16, %0, v8" ::"r"(t20)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmacc.vx v18, %0, v12" ::"r"(t20)); - asm volatile("vmacc.vx v20, %0, v12" ::"r"(t13)); - asm volatile("vmacc.vx v16, %0, v12" ::"r"(t27)); - - //////////////// - // Row 4 -> 6 // - //////////////// - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - asm volatile("vmacc.vx v16, %0, v2" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v18, %0, v2" ::"r"(f[21 + (2 * k)])); - asm volatile("vmacc.vx v16, %0, v6" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v18, %0, v6" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v16, %0, v10" ::"r"(f[42 + (2 * k)])); - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_0++)); - - asm volatile("vmacc.vx v18, %0, v10" ::"r"(f[35 + (2 * k)])); - asm volatile("vslide1down.vx v4, v6, %0" ::"r"(*i_slide_ptr_1++)); - - asm volatile("vmacc.vx v20, %0, v2" ::"r"(f[14 + (2 * k)])); - asm volatile("vmacc.vx v20, %0, v6" ::"r"(f[21 + (2 * k)])); - asm volatile("vmacc.vx v20, %0, v10" ::"r"(f[28 + (2 * k)])); - asm volatile("vslide1down.vx v8, v10, %0" ::"r"(*i_slide_ptr_2++)); - - asm volatile("vmacc.vx v22, %0, v2" ::"r"(f[7 + (2 * k)])); - asm volatile("vmacc.vx v22, %0, v6" ::"r"(f[14 + (2 * k)])); - asm volatile("vmacc.vx v22, %0, v10" ::"r"(f[21 + (2 * k)])); - - if (k == 0) - asm volatile("vmul.vx v24, v2, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v24, %0, v2" ::"r"(f[0 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v6" ::"r"(f[7 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v10" ::"r"(f[14 + (2 * k)])); - - if (k == 0) - asm volatile("vmul.vx v26, v6, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v26, %0, v6" ::"r"(f[0 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v10" ::"r"(f[7 + (2 * k)])); - - if (k == 0) - asm volatile("vmul.vx v28, v10, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v28, %0, v10" ::"r"(f[0 + (2 * k)])); - - asm volatile("vmacc.vx v16, %0, v0" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v16, %0, v4" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v16, %0, v8" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vslide1down.vx v2, v0, %0" ::"r"(*i_slide_ptr_0++)); - - asm volatile("vmacc.vx v18, %0, v0" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v4" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v8" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vslide1down.vx v6, v4, %0" ::"r"(*i_slide_ptr_1++)); - - asm volatile("vmacc.vx v20, %0, v0" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vmacc.vx v20, %0, v4" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vmacc.vx v20, %0, v8" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vslide1down.vx v10, v8, %0" ::"r"(*i_slide_ptr_2++)); - - asm volatile("vmacc.vx v22, %0, v0" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vmacc.vx v22, %0, v4" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vmacc.vx v22, %0, v8" ::"r"(f[21 + (2 * k + 1)])); - - asm volatile("vmacc.vx v24, %0, v0" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v4" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v8" ::"r"(f[14 + (2 * k + 1)])); - - asm volatile("vmacc.vx v26, %0, v4" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v8" ::"r"(f[7 + (2 * k + 1)])); - - asm volatile("vmacc.vx v28, %0, v8" ::"r"(f[0 + (2 * k + 1)])); - } - - // Main kernel, last iteration with filter coefficients reuse - asm volatile("vmacc.vx v16, %0, v2" ::"r"(t34)); - asm volatile("vmacc.vx v16, %0, v6" ::"r"(t41)); - asm volatile("vmacc.vx v16, %0, v10" ::"r"(t48)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - - asm volatile("vmacc.vx v18, %0, v2" ::"r"(t27)); - asm volatile("vmacc.vx v18, %0, v6" ::"r"(t34)); - asm volatile("vmacc.vx v18, %0, v10" ::"r"(t41)); - asm volatile("vmv.v.v v16, v18"); - - asm volatile("vmacc.vx v20, %0, v2" ::"r"(t20)); - asm volatile("vmacc.vx v20, %0, v6" ::"r"(t27)); - asm volatile("vmacc.vx v20, %0, v10" ::"r"(t34)); - asm volatile("vmv.v.v v18, v20"); - - asm volatile("vmacc.vx v22, %0, v2" ::"r"(t13)); - asm volatile("vmacc.vx v22, %0, v6" ::"r"(t20)); - asm volatile("vmacc.vx v22, %0, v10" ::"r"(t27)); - asm volatile("vmv.v.v v20, v22"); - - asm volatile("vmacc.vx v24, %0, v2" ::"r"(t6)); - asm volatile("vmacc.vx v24, %0, v6" ::"r"(t13)); - asm volatile("vmacc.vx v24, %0, v10" ::"r"(t20)); - asm volatile("vmv.v.v v22, v24"); - - asm volatile("vmacc.vx v26, %0, v6" ::"r"(t6)); - asm volatile("vmacc.vx v26, %0, v10" ::"r"(t13)); - asm volatile("vmv.v.v v24, v26"); - - asm volatile("vmacc.vx v28, %0, v10" ::"r"(t6)); - asm volatile("vmv.v.v v26, v28"); - - //////////// - // REGIME // - //////////// - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i + n_; - - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - - // The following loop is unrolled by 2 - // The input matrix has R + F - 1 rows - // We have computed F input rows already - // Compute now until only F input rows are left - // (The last F-1 rows do not contribute to F output rows each, so keep them - // outside of this loop) (We keep F rows outside because of the unrolling by - // 2, just for easeness) - for (int j = 0; j < ((R + F - 1) - 2 * F) / 2; ++j) { - // Work on F output rows - - ////////////// - // UNROLL 0 // - ////////////// - - // Main loop - for (int k = 0; k < F / 2; ++k) { - // Calculate F contributions of the input rows, on F different output rows - asm volatile("vmacc.vx v16, %0, v0" ::"r"(f[42 + (2 * k)])); - asm volatile("vmacc.vx v18, %0, v0" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v20, %0, v0" ::"r"(f[28 + (2 * k)])); - asm volatile("vslide1down.vx v2, v0, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v22, %0, v0" ::"r"(f[21 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v0" ::"r"(f[14 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v0" ::"r"(f[7 + (2 * k)])); - if (k == 0) - asm volatile("vmul.vx v28, v0, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v28, %0, v0" ::"r"(f[0 + (2 * k)])); - - // Calculate F contributions of the input rows, on F different output rows - asm volatile("vmacc.vx v16, %0, v2" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v2" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v20, %0, v2" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v22, %0, v2" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v2" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vmacc.vx v28, %0, v2" ::"r"(f[0 + (2 * k + 1)])); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_1 = i + n_; - - // The last iteration is used to mask the latency of the store and the moves - // Use buffered coefficients not to stall CVA6 for coherency - asm volatile("vmacc.vx v16, %0, v0" ::"r"(t48)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v18, %0, v0" ::"r"(t41)); - asm volatile("vmv.v.v v16, v18"); - asm volatile("vmacc.vx v20, %0, v0" ::"r"(t34)); - asm volatile("vle64.v v2, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmv.v.v v18, v20"); - asm volatile("vmacc.vx v22, %0, v0" ::"r"(t27)); - asm volatile("vmacc.vx v24, %0, v0" ::"r"(t20)); - asm volatile("vmv.v.v v20, v22"); - asm volatile("vmacc.vx v26, %0, v0" ::"r"(t13)); - asm volatile("vmacc.vx v28, %0, v0" ::"r"(t6)); - asm volatile("vmv.v.v v22, v24"); - - ////////////// - // UNROLL 1 // - ////////////// - - asm volatile("vmacc.vx v16, %0, v2" ::"r"(f[42])); - asm volatile("vmacc.vx v18, %0, v2" ::"r"(f[35])); - asm volatile("vmv.v.v v24, v26"); - asm volatile("vmacc.vx v20, %0, v2" ::"r"(f[28])); - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v22, %0, v2" ::"r"(f[21])); - asm volatile("vmv.v.v v26, v28"); - asm volatile("vmacc.vx v24, %0, v2" ::"r"(f[14])); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(f[7])); - asm volatile("vmul.vx v28, v2, %0" ::"r"(f[0])); - - for (int k = 1; k < F; k += 2) { - asm volatile("vmacc.vx v16, %0, v0" ::"r"(f[42 + k])); - asm volatile("vmacc.vx v18, %0, v0" ::"r"(f[35 + k])); - asm volatile("vmacc.vx v20, %0, v0" ::"r"(f[28 + k])); - asm volatile("vslide1down.vx v2, v0, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v22, %0, v0" ::"r"(f[21 + k])); - asm volatile("vmacc.vx v24, %0, v0" ::"r"(f[14 + k])); - asm volatile("vmacc.vx v26, %0, v0" ::"r"(f[7 + k])); - asm volatile("vmacc.vx v28, %0, v0" ::"r"(f[0 + k])); - - if (k == F - 2) - break; - - asm volatile("vmacc.vx v16, %0, v2" ::"r"(f[42 + (k + 1)])); - asm volatile("vmacc.vx v18, %0, v2" ::"r"(f[35 + (k + 1)])); - asm volatile("vmacc.vx v20, %0, v2" ::"r"(f[28 + (k + 1)])); - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v22, %0, v2" ::"r"(f[21 + (k + 1)])); - asm volatile("vmacc.vx v24, %0, v2" ::"r"(f[14 + (k + 1)])); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(f[7 + (k + 1)])); - asm volatile("vmacc.vx v28, %0, v2" ::"r"(f[0 + (k + 1)])); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i + n_; - - asm volatile("vmacc.vx v16, %0, v2" ::"r"(t48)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v18, %0, v2" ::"r"(t41)); - asm volatile("vmv.v.v v16, v18"); - asm volatile("vmacc.vx v20, %0, v2" ::"r"(t34)); - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmv.v.v v18, v20"); - asm volatile("vmacc.vx v22, %0, v2" ::"r"(t27)); - asm volatile("vmv.v.v v20, v22"); - asm volatile("vmacc.vx v24, %0, v2" ::"r"(t20)); - asm volatile("vmv.v.v v22, v24"); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(t13)); - asm volatile("vmv.v.v v24, v26"); - asm volatile("vmacc.vx v28, %0, v2" ::"r"(t6)); - asm volatile("vmv.v.v v26, v28"); - } - - //////////////////////// - // Row I-F -> (I-1)-3 // - //////////////////////// - - // Point to the scalar elements to insert during a slide - // i_slide_ptr_0 has already been computed - i_slide_ptr_1 = i + n_ + 0 * (C + F - 1); - i_slide_ptr_2 = i + n_ + 1 * (C + F - 1); - i_slide_ptr_3 = i + n_ + 2 * (C + F - 1); - - // Load other three input rows (one was already loaded) - asm volatile("vle64.v v4, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vle64.v v8, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vle64.v v12, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - - // Main kernel, unrolled by 2 - // Process 4 input rows - for (int k = 0; k < F / 2; ++k) { - asm volatile("vslide1down.vx v2, v0, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v16, %0, v0" ::"r"(f[42 + (2 * k)])); - asm volatile("vmacc.vx v18, %0, v0" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v20, %0, v0" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v22, %0, v0" ::"r"(f[21 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v0" ::"r"(f[14 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v0" ::"r"(f[7 + (2 * k)])); - if (k == 0) - asm volatile("vmul.vx v28, v0, %0" ::"r"(f[0 + (2 * k)])); - else - asm volatile("vmacc.vx v28, %0, v0" ::"r"(f[0 + (2 * k)])); - asm volatile("vslide1down.vx v6, v4, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v18, %0, v4" ::"r"(f[42 + (2 * k)])); - asm volatile("vmacc.vx v20, %0, v4" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v22, %0, v4" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v4" ::"r"(f[21 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v4" ::"r"(f[14 + (2 * k)])); - asm volatile("vmacc.vx v28, %0, v4" ::"r"(f[7 + (2 * k)])); - asm volatile("vslide1down.vx v10, v8, %0" ::"r"(*i_slide_ptr_2++)); - asm volatile("vmacc.vx v20, %0, v8" ::"r"(f[42 + (2 * k)])); - asm volatile("vmacc.vx v22, %0, v8" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v8" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v8" ::"r"(f[21 + (2 * k)])); - asm volatile("vmacc.vx v28, %0, v8" ::"r"(f[14 + (2 * k)])); - asm volatile("vslide1down.vx v14, v12, %0" ::"r"(*i_slide_ptr_3++)); - asm volatile("vmacc.vx v22, %0, v12" ::"r"(f[42 + (2 * k)])); - asm volatile("vmacc.vx v24, %0, v12" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v12" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v28, %0, v12" ::"r"(f[21 + (2 * k)])); - - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v16, %0, v2" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vmacc.vx v18, %0, v2" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v20, %0, v2" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v22, %0, v2" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v2" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vmacc.vx v28, %0, v2" ::"r"(f[0 + (2 * k + 1)])); - asm volatile("vslide1down.vx v4, v6, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v18, %0, v6" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vmacc.vx v20, %0, v6" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v22, %0, v6" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v6" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v6" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vmacc.vx v28, %0, v6" ::"r"(f[7 + (2 * k + 1)])); - asm volatile("vslide1down.vx v8, v10, %0" ::"r"(*i_slide_ptr_2++)); - asm volatile("vmacc.vx v20, %0, v10" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vmacc.vx v22, %0, v10" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v10" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v10" ::"r"(f[21 + (2 * k + 1)])); - asm volatile("vmacc.vx v28, %0, v10" ::"r"(f[14 + (2 * k + 1)])); - asm volatile("vslide1down.vx v12, v14, %0" ::"r"(*i_slide_ptr_3++)); - asm volatile("vmacc.vx v22, %0, v14" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vmacc.vx v24, %0, v14" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v14" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v28, %0, v14" ::"r"(f[21 + (2 * k + 1)])); - } - - // Start calculating the next pointers to the elements to be slided in - i_slide_ptr_0 = i + n_ + 0 * (C + F - 1); - i_slide_ptr_1 = i + n_ + 1 * (C + F - 1); - i_slide_ptr_2 = i + n_ + 2 * (C + F - 1); - - asm volatile("vle64.v v2, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmacc.vx v16, %0, v0" ::"r"(t48)); - asm volatile("vmacc.vx v18, %0, v0" ::"r"(t41)); - asm volatile("vmacc.vx v20, %0, v0" ::"r"(t34)); - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v22, %0, v0" ::"r"(t27)); - asm volatile("vmacc.vx v24, %0, v0" ::"r"(t20)); - asm volatile("vmacc.vx v26, %0, v0" ::"r"(t13)); - asm volatile("vle64.v v6, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmacc.vx v28, %0, v0" ::"r"(t6)); - asm volatile("vmacc.vx v18, %0, v4" ::"r"(t48)); - asm volatile("vmacc.vx v20, %0, v4" ::"r"(t41)); - asm volatile("vse64.v v18, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v22, %0, v4" ::"r"(t34)); - asm volatile("vmacc.vx v24, %0, v4" ::"r"(t27)); - asm volatile("vmacc.vx v26, %0, v4" ::"r"(t20)); - asm volatile("vle64.v v10, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - asm volatile("vmacc.vx v28, %0, v4" ::"r"(t13)); - asm volatile("vmacc.vx v20, %0, v8" ::"r"(t48)); - asm volatile("vmacc.vx v22, %0, v8" ::"r"(t41)); - asm volatile("vse64.v v20, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v24, %0, v8" ::"r"(t34)); - asm volatile("vmacc.vx v26, %0, v8" ::"r"(t27)); - asm volatile("vmacc.vx v28, %0, v8" ::"r"(t20)); - asm volatile("vmacc.vx v22, %0, v12" ::"r"(t48)); - asm volatile("vse64.v v22, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v24, %0, v12" ::"r"(t41)); - asm volatile("vmacc.vx v26, %0, v12" ::"r"(t34)); - asm volatile("vmacc.vx v28, %0, v12" ::"r"(t27)); - - ////////////////////////// - // Row (I-1)-3 -> (I-1) // - ////////////////////////// - - // Main kernel, unrolled by 2 - for (int k = 0; k < F / 2; ++k) { - asm volatile("vslide1down.vx v0, v2, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v24, %0, v2" ::"r"(f[42 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(f[35 + (2 * k)])); - asm volatile("vslide1down.vx v4, v6, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v28, %0, v2" ::"r"(f[28 + (2 * k)])); - asm volatile("vmacc.vx v26, %0, v6" ::"r"(f[42 + (2 * k)])); - asm volatile("vslide1down.vx v8, v10, %0" ::"r"(*i_slide_ptr_2++)); - asm volatile("vmacc.vx v28, %0, v6" ::"r"(f[35 + (2 * k)])); - asm volatile("vmacc.vx v28, %0, v10" ::"r"(f[42 + (2 * k)])); - - asm volatile("vslide1down.vx v2, v0, %0" ::"r"(*i_slide_ptr_0++)); - asm volatile("vmacc.vx v24, %0, v0" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v0" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vslide1down.vx v6, v4, %0" ::"r"(*i_slide_ptr_1++)); - asm volatile("vmacc.vx v28, %0, v0" ::"r"(f[28 + (2 * k + 1)])); - asm volatile("vmacc.vx v26, %0, v4" ::"r"(f[42 + (2 * k + 1)])); - asm volatile("vslide1down.vx v10, v8, %0" ::"r"(*i_slide_ptr_2++)); - asm volatile("vmacc.vx v28, %0, v4" ::"r"(f[35 + (2 * k + 1)])); - asm volatile("vmacc.vx v28, %0, v8" ::"r"(f[42 + (2 * k + 1)])); - } - - asm volatile("vmacc.vx v24, %0, v2" ::"r"(t48)); - asm volatile("vse64.v v24, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v26, %0, v2" ::"r"(t41)); - asm volatile("vmacc.vx v28, %0, v2" ::"r"(t34)); - asm volatile("vmacc.vx v26, %0, v6" ::"r"(t48)); - asm volatile("vse64.v v26, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - asm volatile("vmacc.vx v28, %0, v6" ::"r"(t41)); - asm volatile("vmacc.vx v28, %0, v10" ::"r"(t48)); - asm volatile("vse64.v v28, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); -} - -/* - //////////////////// - // MAIN ALGORITHM // - //////////////////// - - // Start calculating the pointer to the next element to be slided in - i_slide_ptr_0 = i + C; - - // Load one input row - asm volatile("vle64.v v0, (%0); add %0, %0, %1" : "+&r"(i) : "r"(ldi_pad)); - - // Kernel - for (int k = 0; k < F; ++k) { - // Calculate F*F contributions of the input rows, on F different output rows - // v28 should be initialized during the first iteration - asm volatile("vmacc.vx v16, %0, v0" :: "r"(f[42 + (2*k)])); - asm volatile("vmacc.vx v18, %0, v0" :: "r"(f[35 + (2*k)])); - asm volatile("vmacc.vx v20, %0, v0" :: "r"(f[28 + (2*k)])); - asm volatile("vmacc.vx v22, %0, v0" :: "r"(f[21 + (2*k)])); - asm volatile("vmacc.vx v24, %0, v0" :: "r"(f[14 + (2*k)])); - asm volatile("vmacc.vx v26, %0, v0" :: "r"(f[7 + (2*k)])); - if (k == 0) - asm volatile("vmul.vx v28, v0, %0" :: "r"(f[0 + (2*k)])); - else - asm volatile("vmacc.vx v28, %0, v0" :: "r"(f[0 + (2*k)])); - - // Slide the input row by one, and inject the next scalar element of the row - asm volatile("vslide1down.vx v0, v0, %0" :: "r"(*i_slide_ptr_0++)); - } - - // Store one output row - asm volatile("vse64.v v16, (%0); add %0, %0, %1" : "+&r"(o) : "r"(ldo)); - - // Move all the input rows to return to the initial situation - // To avoid these operations, unroll the loop via software, renaming the - registers manually asm volatile("vmv.v.v v16, v18"); asm volatile("vmv.v.v - v18, v20"); asm volatile("vmv.v.v v20, v22"); asm volatile("vmv.v.v v22, - v24"); asm volatile("vmv.v.v v24, v26"); asm volatile("vmv.v.v v26, v28"); -*/ diff --git a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/main.c b/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/main.c deleted file mode 100644 index 09b075b5..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-iconv2d/main.c +++ /dev/null @@ -1,91 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include -#include -#include - -#include "iconv2d.h" -#include "util.h" - -// Define Matrix dimensions: -// o = i ° f, with i=[MxN], f=[FxF], o=[MxN] -// The filter is a square matrix, and F is odd - -// Matrices defined in data.S -extern int64_t i[] - __attribute__((aligned(32))); // [ (M+floor(F/2)) * (N+floor(F/2)) ] -extern int64_t f[] __attribute__((aligned(32))); // [ F*F ] -extern int64_t o[] __attribute__((aligned(32))); // [ M*N ] -extern int64_t golden_o[] __attribute__((aligned(32))); // [ M*N ] -// M, N, F defined in data.S -extern int64_t M; -extern int64_t N; -extern int64_t F; - -// Verify the matrices -int verify_matrix(int64_t *matrix, int64_t *golden_matrix, int64_t R, - int64_t C) { - for (int r = 0; r < R; ++r) - for (int c = 0; c < C; ++c) - if (matrix[c + C * r] != golden_matrix[c + C * r]) { - printf("Error: o[%d][%d] = %ld, instead of %ld\n", r, c, - matrix[c + C * r], golden_matrix[c + C * r]); - return 1; - } - return 0; -} - -int main() { - printf("ICONV2D M=%ld N=%ld F=%ld\n", M, N, F); - - unsigned long cycles1, cycles2, instr2, instr1; - // Call the main kernel, and measure cycles - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - if (F == 3) - iconv2d_3x3(o, i, f, M, N, F); - else if (F == 5) - iconv2d_5x5(o, i, f, M, N, F); - else if (F == 7) - iconv2d_7x7(o, i, f, M, N, F); - else - printf("Error: the filter size is different from 3 or 5 or 7.\n"); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - // Performance metrics - int64_t runtime = cycles2 - cycles1; - float performance = 2.0 * F * F * M * N / runtime; - printf("operations %ld\n", F * F * M * N); - printf("The execution took %d cycles.\n", runtime); - printf("The performance is %ld OPs/1000 cycles\n", - (uint64_t)(1000.0 * performance)); - - // Verify correctness - printf("Verifying result...\n"); - int error = verify_matrix(o, golden_o, M, N); - if (error != 0) { - printf("Fail.\n"); - } else { - printf("Passed.\n"); - } - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-igemm/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-igemm/gen_data.py deleted file mode 100644 index 8f073ad3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-igemm/gen_data.py +++ /dev/null @@ -1,71 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2022 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# Author: Matteo Perotti - -# C = AB with A=[MxN], B=[NxP], C=[MxP] -# arg1, arg2, arg3: M, N, P - -import random as rand -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# SCRIPT - -if len(sys.argv) == 4: - M = int(sys.argv[1]) - N = int(sys.argv[2]) - P = int(sys.argv[3]) -else: - print("Error. Give me three argument: M, N, P.") - print("C = AB with A=[MxN], B=[NxP], C=[MxP]") - sys.exit() - -dtype = np.int64 - -UPPER_LIMIT = 10000 -LOWER_LIMIT = -10000 - -# Matrices and results -A = np.random.randint(LOWER_LIMIT, UPPER_LIMIT, size=(M, N)).astype(dtype) -B = np.random.randint(LOWER_LIMIT, UPPER_LIMIT, size=(N, P)).astype(dtype) -C = np.zeros([M, P], dtype=dtype) -# Golden result matrix -G = np.matmul(A, B).astype(dtype) - -# Create the file -print('.section .data,"aw",@progbits') -emit("M", np.array(M, dtype=np.uint64)) -emit("N", np.array(N, dtype=np.uint64)) -emit("P", np.array(P, dtype=np.uint64)) -emit("a", A, "32") -emit("b", B, "32") -emit("c", C, "32") -emit("g", G, "32") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-igemm/imatmul.c b/bb-tests/workloads/src/CTest/rvv/vec-igemm/imatmul.c deleted file mode 100644 index 2be76e72..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-igemm/imatmul.c +++ /dev/null @@ -1,324 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matheus Cavalcante, ETH Zurich -// Samuel Riedel, ETH Zurich - -#include "imatmul.h" - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -void imatmul(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int M, const unsigned long int N, - const unsigned long int P) { - if (M <= 4) { - imatmul_4x4(c, a, b, M, N, P); - } else if (M <= 128) { - imatmul_8x8(c, a, b, M, N, P); - } else { - // Vector length is 64 elements. With an 4x4 matmul, - // we can use LMUL=4, having a vl of 256. - imatmul_4x4(c, a, b, M, N, P); - } -} - -// --------------- -// 4x4 -// --------------- - -void imatmul_4x4(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int M, const unsigned long int N, - const unsigned long int P) { - // We work on 4 rows of the matrix at once - const unsigned long int block_size = 4; - unsigned long int block_size_p; - - // Set the vector configuration - asm volatile("vsetvli %0, %1, e64, m4, ta, ma" : "=r"(block_size_p) : "r"(P)); - - // Slice the matrix into a manageable number of columns p_ - for (unsigned long int p = 0; p < P; p += block_size_p) { - // Set the vector length - const unsigned long int p_ = MIN(P - p, block_size_p); - - // Find pointers to the submatrices - const int64_t *b_ = b + p; - int64_t *c_ = c + p; - - asm volatile("vsetvli zero, %0, e64, m4, ta, ma" ::"r"(p_)); - - // Iterate over the rows - for (unsigned long int m = 0; m < M; m += block_size) { - // Find pointer to the submatrices - const int64_t *a_ = a + m * N; - int64_t *c__ = c_ + m * P; - - imatmul_vec_4x4_slice_init(); - imatmul_vec_4x4(c__, a_, b_, N, P); - } - } -} - -void imatmul_vec_4x4_slice_init() { - asm volatile("vmv.v.i v0, 0"); - asm volatile("vmv.v.i v4, 0"); - asm volatile("vmv.v.i v8, 0"); - asm volatile("vmv.v.i v12, 0"); -} - -void imatmul_vec_4x4(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int N, const unsigned long int P) { - // Temporary variables - int64_t t0, t1, t2, t3; - - // Original pointer - const int64_t *a_ = a; - - // Prefetch one row of matrix B - asm volatile("vle64.v v16, (%0);" ::"r"(b)); - b += P; - - // Prefetch one row of scalar values - t0 = *a, a += N; - t1 = *a, a += N; - t2 = *a, a += N; - t3 = *a; - - // Compute the multiplication - unsigned long int n = 0; - - while (n < N) { -#ifdef VCD_DUMP - // Start dumping VCD - if (n == 8) - event_trigger = +1; - // Stop dumping VCD - if (n == 12) - event_trigger = -1; -#endif - - // Calculate pointer to the matrix A - a = a_ + ++n; - - asm volatile("vmacc.vx v0, %0, v16" ::"r"(t0)); - t0 = *a, a += N; - - // Load one row of B - asm volatile("vle64.v v20, (%0);" ::"r"(b)); - b += P; - - asm volatile("vmacc.vx v4, %0, v16" ::"r"(t1)); - t1 = *a, a += N; - asm volatile("vmacc.vx v8, %0, v16" ::"r"(t2)); - t2 = *a, a += N; - asm volatile("vmacc.vx v12, %0, v16" ::"r"(t3)); - t3 = *a; - - a = a_ + ++n; - - if (n == N) - break; - - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t0)); - t0 = *a, a += N; - - // Load one row of B - asm volatile("vle64.v v16, (%0);" ::"r"(b)); - b += P; - - asm volatile("vmacc.vx v4, %0, v20" ::"r"(t1)); - t1 = *a, a += N; - asm volatile("vmacc.vx v8, %0, v20" ::"r"(t2)); - t2 = *a, a += N; - asm volatile("vmacc.vx v12, %0, v20" ::"r"(t3)); - t3 = *a; - } - - // Last iteration: store results - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t0)); - asm volatile("vse64.v v0, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v4, %0, v20" ::"r"(t1)); - asm volatile("vse64.v v4, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v8, %0, v20" ::"r"(t2)); - asm volatile("vse64.v v8, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v12, %0, v20" ::"r"(t3)); - asm volatile("vse64.v v12, (%0);" ::"r"(c)); -} - -// --------------- -// 8x8 -// --------------- - -void imatmul_8x8(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int M, const unsigned long int N, - const unsigned long int P) { - // We work on 4 rows of the matrix at once - const unsigned long int block_size = 8; - unsigned long int block_size_p; - - // Set the vector configuration - asm volatile("vsetvli %0, %1, e64, m2, ta, ma" : "=r"(block_size_p) : "r"(P)); - - // Slice the matrix into a manageable number of columns p_ - for (unsigned long int p = 0; p < P; p += block_size_p) { - // Set the vector length - const unsigned long int p_ = MIN(P - p, block_size_p); - - // Find pointers to the submatrices - const int64_t *b_ = b + p; - int64_t *c_ = c + p; - - asm volatile("vsetvli zero, %0, e64, m2, ta, ma" ::"r"(p_)); - - // Iterate over the rows - for (unsigned long int m = 0; m < M; m += block_size) { - // Find pointer to the submatrices - const int64_t *a_ = a + m * N; - int64_t *c__ = c_ + m * P; - - imatmul_vec_8x8_slice_init(); - imatmul_vec_8x8(c__, a_, b_, N, P); - } - } -} - -void imatmul_vec_8x8_slice_init() { - asm volatile("vmv.v.i v0, 0"); - asm volatile("vmv.v.i v2, 0"); - asm volatile("vmv.v.i v4, 0"); - asm volatile("vmv.v.i v6, 0"); - asm volatile("vmv.v.i v8, 0"); - asm volatile("vmv.v.i v10, 0"); - asm volatile("vmv.v.i v12, 0"); - asm volatile("vmv.v.i v14, 0"); -} - -void imatmul_vec_8x8(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int N, const unsigned long int P) { - // Temporary variables - int64_t t0, t1, t2, t3, t4, t5, t6, t7; - - // Original pointer - const int64_t *a_ = a; - - // Prefetch one row of matrix B - asm volatile("vle64.v v18, (%0);" ::"r"(b)); - b += P; - - // Prefetch one row of scalar values - t0 = *a, a += N; - t1 = *a, a += N; - t2 = *a, a += N; - t3 = *a, a += N; - t4 = *a, a += N; - t5 = *a, a += N; - t6 = *a, a += N; - t7 = *a; - - // Compute the multiplication - unsigned long int n = 0; - - while (n < N) { -#ifdef VCD_DUMP - // Start dumping VCD - if (n == 8) - event_trigger = +1; - // Stop dumping VCD - if (n == 12) - event_trigger = -1; -#endif - - // Calculate pointer to the matrix A - a = a_ + ++n; - - asm volatile("vmacc.vx v0, %0, v18" ::"r"(t0)); - t0 = *a, a += N; - - // Load one row of B - asm volatile("vle64.v v20, (%0);" ::"r"(b)); - b += P; - - asm volatile("vmacc.vx v2, %0, v18" ::"r"(t1)); - t1 = *a, a += N; - asm volatile("vmacc.vx v4, %0, v18" ::"r"(t2)); - t2 = *a, a += N; - asm volatile("vmacc.vx v6, %0, v18" ::"r"(t3)); - t3 = *a, a += N; - asm volatile("vmacc.vx v8, %0, v18" ::"r"(t4)); - t4 = *a, a += N; - asm volatile("vmacc.vx v10, %0, v18" ::"r"(t5)); - t5 = *a, a += N; - asm volatile("vmacc.vx v12, %0, v18" ::"r"(t6)); - t6 = *a, a += N; - asm volatile("vmacc.vx v14, %0, v18" ::"r"(t7)); - t7 = *a; - - a = a_ + ++n; - - if (n == N) - break; - - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t0)); - t0 = *a, a += N; - - // Load one row of B - asm volatile("vle64.v v18, (%0);" ::"r"(b)); - b += P; - - asm volatile("vmacc.vx v2, %0, v20" ::"r"(t1)); - t1 = *a, a += N; - asm volatile("vmacc.vx v4, %0, v20" ::"r"(t2)); - t2 = *a, a += N; - asm volatile("vmacc.vx v6, %0, v20" ::"r"(t3)); - t3 = *a, a += N; - asm volatile("vmacc.vx v8, %0, v20" ::"r"(t4)); - t4 = *a, a += N; - asm volatile("vmacc.vx v10, %0, v20" ::"r"(t5)); - t5 = *a, a += N; - asm volatile("vmacc.vx v12, %0, v20" ::"r"(t6)); - t6 = *a, a += N; - asm volatile("vmacc.vx v14, %0, v20" ::"r"(t7)); - t7 = *a; - } - - // Last iteration: store results - asm volatile("vmacc.vx v0, %0, v20" ::"r"(t0)); - asm volatile("vse64.v v0, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v2, %0, v20" ::"r"(t1)); - asm volatile("vse64.v v2, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v4, %0, v20" ::"r"(t2)); - asm volatile("vse64.v v4, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v6, %0, v20" ::"r"(t3)); - asm volatile("vse64.v v6, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v8, %0, v20" ::"r"(t4)); - asm volatile("vse64.v v8, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v10, %0, v20" ::"r"(t5)); - asm volatile("vse64.v v10, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v12, %0, v20" ::"r"(t6)); - asm volatile("vse64.v v12, (%0);" ::"r"(c)); - c += P; - asm volatile("vmacc.vx v14, %0, v20" ::"r"(t7)); - asm volatile("vse64.v v14, (%0);" ::"r"(c)); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-igemm/imatmul.h b/bb-tests/workloads/src/CTest/rvv/vec-igemm/imatmul.h deleted file mode 100644 index 145b498d..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-igemm/imatmul.h +++ /dev/null @@ -1,45 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matheus Cavalcante, ETH Zurich -// Samuel Riedel, ETH Zurich - -#ifndef IMATMUL_H -#define IMATMUL_H - -#include - -void imatmul(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int m, const unsigned long int n, - const unsigned long int p); - -void imatmul_4x4(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int m, const unsigned long int n, - const unsigned long int p); -void imatmul_vec_4x4_slice_init(); -void imatmul_vec_4x4(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int n, const unsigned long int p); - -void imatmul_8x8(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int m, const unsigned long int n, - const unsigned long int p); -void imatmul_vec_8x8_slice_init(); -void imatmul_vec_8x8(int64_t *c, const int64_t *a, const int64_t *b, - const unsigned long int n, const unsigned long int p); - -extern int64_t event_trigger; - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-igemm/main.c b/bb-tests/workloads/src/CTest/rvv/vec-igemm/main.c deleted file mode 100644 index 01d51fb8..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-igemm/main.c +++ /dev/null @@ -1,93 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matheus Cavalcante, ETH Zurich -// Samuel Riedel, ETH Zurich - -#include -#include -#include - -#include "imatmul.h" -#include "util.h" - -// Define Matrix dimensions: -// C = AB with A=[MxN], B=[NxP], C=[MxP] -extern uint64_t M; -extern uint64_t N; -extern uint64_t P; - -extern int64_t a[] __attribute__((aligned(256))); -extern int64_t b[] __attribute__((aligned(256))); -extern int64_t c[] __attribute__((aligned(256))); -// Gold results -extern int64_t g[] __attribute__((aligned(256))); - -// Verify the matrix -int verify_matrix(int64_t *result, int64_t *gold, size_t R, size_t C) { - for (uint64_t i = 0; i < R; ++i) { - for (uint64_t j = 0; j < C; ++j) { - uint64_t idx = i * C + j; - if (result[idx] != gold[idx]) { - return (i + j) == 0 ? -1 : idx; - } - } - } - return 0; -} - -int main() { - printf("IMATMUL\n"); - unsigned long cycles1, cycles2, instr2, instr1; - - for (int s = 4; s <= M; s *= 2) { - printf("Calculating a (%d x %d) x (%d x %d) matrix multiplication...\n", s, - s, s, s); - - // Matrices are initialized --> Start calculating - printf("Calculating imatmul...\n"); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - imatmul(c, a, b, s, s, s); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - // Metrics - int64_t runtime = cycles2 - cycles1; - float performance = 2.0 * s * s * s / runtime; - - printf("The execution took %d cycles.\n", runtime); - printf("The performance is %ld OPs/1000 cycles.\n", - (uint64_t)(1000.0 * performance)); - - // Verify the result only for s == M (to keep it simple) - if (s == M) { - // Verify the result - printf("Verifying result...\n"); - int error = verify_matrix(c, g, s, s); - if (error != 0) { - printf("Error code %d\n", error); - printf("c[%d]=%d\n", error, c[error]); - return error; - } else { - printf("Passed.\n"); - } - } - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/gen_data.py deleted file mode 100755 index e0774213..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/gen_data.py +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: vector size, arg2: filter size - -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# SCRIPT - -if len(sys.argv) == 3: - R = int(sys.argv[1]) - C = int(sys.argv[2]) -else: - print("Error. Give me one argument: the number of vector elements.") - sys.exit() - -dtype = np.float64 - -TSTEPS = 1 - -# Fill in the extra data to align the matrices to 4*NrLanes in SW -maxNrLanes = 16 -maxAlignment = 4 * maxNrLanes # [B] -sizeOfDType = np.dtype(dtype).itemsize # [B] -R_ext = int(R + (maxAlignment / sizeOfDType)) -C_ext = int(C + (maxAlignment / sizeOfDType)) - -# Vector of samples (padding is random since it does not impact performance) -A = np.random.rand(R_ext, C_ext).astype(dtype) -B = np.zeros([R_ext, C_ext], dtype=dtype) - -# Create the file -print('.section .data,"aw",@progbits') -emit("R", np.array(R, dtype=np.uint64)) -emit("C", np.array(C, dtype=np.uint64)) -emit("TSTEPS", np.array(TSTEPS, dtype=np.uint64)) -emit("A_v", A, "NR_LANES*4") -emit("B_v", B, "NR_LANES*4") -emit("A_s", A, "NR_LANES*4") -emit("B_s", B, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/jacobi2d.c b/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/jacobi2d.c deleted file mode 100644 index 50d4a646..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/jacobi2d.c +++ /dev/null @@ -1,146 +0,0 @@ -/* -OHIO STATE UNIVERSITY SOFTWARE DISTRIBUTION LICENSE - -PolyBench/C, a collection of benchmarks containing static control -parts (the "Software") -Copyright (c) 2010-2016, Ohio State University. All rights reserved. - -The Software is available for download and use subject to the terms -and conditions of this License. Access or use of the Software -constitutes acceptance and agreement to the terms and conditions of -this License. Redistribution and use of the Software in source and -binary forms, with or without modification, are permitted provided -that the following conditions are met: - -1. Redistributions of source code must retain the above copyright -notice, this list of conditions and the capitalized paragraph below. - -2. Redistributions in binary form must reproduce the above copyright -notice, this list of conditions and the capitalized paragraph below in -the documentation and/or other materials provided with the -distribution. - -3. The name of Ohio State University, or its faculty, staff or -students may not be used to endorse or promote products derived from -the Software without specific prior written permission. - -This software was produced with support from the U.S. Defense Advanced -Research Projects Agency (DARPA), the U.S. Department of Energy (DoE) -and the U.S. National Science Foundation. Nothing in this work should -be construed as reflecting the official policy or position of the -Defense Department, the United States government or Ohio State -University. - -THIS SOFTWARE HAS BEEN APPROVED FOR PUBLIC RELEASE, UNLIMITED -DISTRIBUTION. THE SOFTWARE IS PROVIDED ?AS IS? AND WITHOUT ANY -EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED -TO, WARRANTIES OF ACCURACY, COMPLETENESS, NONINFRINGEMENT, -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -ACCESS OR USE OF THE SOFTWARE IS ENTIRELY AT THE USER?S RISK. IN NO -EVENT SHALL OHIO STATE UNIVERSITY OR ITS FACULTY, STAFF OR STUDENTS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE USER SHALL -INDEMNIFY, DEFEND AND HOLD HARMLESS OHIO STATE UNIVERSITY AND ITS -FACULTY, STAFF AND STUDENTS FROM ANY AND ALL CLAIMS, ACTIONS, DAMAGES, -LOSSES, LIABILITIES, COSTS AND EXPENSES, INCLUDING ATTORNEYS? FEES AND -COURT COSTS, DIRECTLY OR INDIRECTLY ARISING OUT OF OR IN CONNECTION -WITH ACCESS OR USE OF THE SOFTWARE. -*/ - -/** - * This version is stamped on May 10, 2016 - * - * Contact: - * Louis-Noel Pouchet - * Tomofumi Yuki - * - * Web address: http://polybench.sourceforge.net - */ -/* jacobi-2d.c: this file is part of PolyBench/C */ - -/************************************************************************* - * RISC-V Vectorized Version - * Author: Cristóbal Ramírez Lazo - * email: cristobal.ramirez@bsc.es - * Barcelona Supercomputing Center (2020) - *************************************************************************/ - -// Porting to Ara SW environment and Optimization -// Author: Matteo Perotti, ETH Zurich, - -#include "jacobi2d.h" -#define DOUBLE_BUFFERING - -void j2d_s(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B, - uint64_t tsteps) { - for (uint32_t t = 0; t < tsteps; t++) { - for (uint32_t i = 1; i < r - 1; i++) - for (uint32_t j = 1; j < c - 1; j++) - B[i * c + j] = - (0.2) * (A[i * c + j] + A[i * c + j - 1] + A[i * c + j + 1] + - A[(i + 1) * c + j] + A[(i - 1) * c + j]); -#ifdef DOUBLE_BUFFERING - for (uint32_t i = 1; i < r - 1; i++) - for (uint32_t j = 1; j < c - 1; j++) - A[i * c + j] = - (0.2) * (B[i * c + j] + B[i * c + j - 1] + B[i * c + j + 1] + - B[(i + 1) * c + j] + B[(i - 1) * c + j]); -#endif - } -} - -void j2d_v(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B, - uint64_t tsteps) { - for (uint32_t t = 0; t < tsteps; t++) { - j2d_kernel_v(r, c, B, A); - } -} - -void j2d_kernel_v(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B) { - vfloat64m4_t xU; - vfloat64m4_t xUtmp; - vfloat64m4_t xUleft; - vfloat64m4_t xUright; - vfloat64m4_t xUtop; - vfloat64m4_t xUbottom; - - DATA_TYPE izq, der; - uint32_t size_x = c - 2; - uint32_t size_y = r - 2; - - size_t gvl = __riscv_vsetvl_e64m4(size_x); - - for (uint32_t j = 1; j <= size_x; j = j + gvl) { - gvl = __riscv_vsetvl_e64m4(size_x - j + 1); - xU = __riscv_vle64_v_f64m4(&A[1 * c + j], gvl); - xUtop = __riscv_vle64_v_f64m4(&A[0 * c + j], gvl); - xUbottom = __riscv_vle64_v_f64m4(&A[2 * c + j], gvl); - - for (uint32_t i = 1; i <= size_y; i++) { - if (i != 1) { - xUtop = xU; - xU = xUbottom; - xUbottom = __riscv_vle64_v_f64m4(&A[(i + 1) * c + j], gvl); - } - izq = A[i * c + j - 1]; - der = A[i * c + j + gvl]; - if (i != size_y) { - asm volatile("ld x0, 0(%0)" : : "r"(A + (i + 1) * c + j - 1)); - asm volatile("ld x0, 0(%0)" : : "r"(A + (i + 1) * c + j + gvl)); - } - xUleft = __riscv_vfslide1up_vf_f64m4(xU, izq, gvl); - xUright = __riscv_vfslide1down_vf_f64m4(xU, der, gvl); - xUtmp = __riscv_vfadd_vv_f64m4(xUleft, xUright, gvl); - xUtmp = __riscv_vfadd_vv_f64m4(xUtmp, xUtop, gvl); - xUtmp = __riscv_vfadd_vv_f64m4(xUtmp, xUbottom, gvl); - xUtmp = __riscv_vfadd_vv_f64m4(xUtmp, xU, gvl); - xUtmp = __riscv_vfmul_vf_f64m4(xUtmp, (float)0.2, gvl); - __riscv_vse64_v_f64m4(&B[i * c + j], xUtmp, gvl); - } - } -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/jacobi2d.h b/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/jacobi2d.h deleted file mode 100644 index 3c029375..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/jacobi2d.h +++ /dev/null @@ -1,108 +0,0 @@ -/* -OHIO STATE UNIVERSITY SOFTWARE DISTRIBUTION LICENSE - -PolyBench/C, a collection of benchmarks containing static control -parts (the "Software") -Copyright (c) 2010-2016, Ohio State University. All rights reserved. - -The Software is available for download and use subject to the terms -and conditions of this License. Access or use of the Software -constitutes acceptance and agreement to the terms and conditions of -this License. Redistribution and use of the Software in source and -binary forms, with or without modification, are permitted provided -that the following conditions are met: - -1. Redistributions of source code must retain the above copyright -notice, this list of conditions and the capitalized paragraph below. - -2. Redistributions in binary form must reproduce the above copyright -notice, this list of conditions and the capitalized paragraph below in -the documentation and/or other materials provided with the -distribution. - -3. The name of Ohio State University, or its faculty, staff or -students may not be used to endorse or promote products derived from -the Software without specific prior written permission. - -This software was produced with support from the U.S. Defense Advanced -Research Projects Agency (DARPA), the U.S. Department of Energy (DoE) -and the U.S. National Science Foundation. Nothing in this work should -be construed as reflecting the official policy or position of the -Defense Department, the United States government or Ohio State -University. - -THIS SOFTWARE HAS BEEN APPROVED FOR PUBLIC RELEASE, UNLIMITED -DISTRIBUTION. THE SOFTWARE IS PROVIDED ?AS IS? AND WITHOUT ANY -EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED -TO, WARRANTIES OF ACCURACY, COMPLETENESS, NONINFRINGEMENT, -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -ACCESS OR USE OF THE SOFTWARE IS ENTIRELY AT THE USER?S RISK. IN NO -EVENT SHALL OHIO STATE UNIVERSITY OR ITS FACULTY, STAFF OR STUDENTS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE USER SHALL -INDEMNIFY, DEFEND AND HOLD HARMLESS OHIO STATE UNIVERSITY AND ITS -FACULTY, STAFF AND STUDENTS FROM ANY AND ALL CLAIMS, ACTIONS, DAMAGES, -LOSSES, LIABILITIES, COSTS AND EXPENSES, INCLUDING ATTORNEYS? FEES AND -COURT COSTS, DIRECTLY OR INDIRECTLY ARISING OUT OF OR IN CONNECTION -WITH ACCESS OR USE OF THE SOFTWARE. -*/ - -/** - * This version is stamped on May 10, 2016 - * - * Contact: - * Louis-Noel Pouchet - * Tomofumi Yuki - * - * Web address: http://polybench.sourceforge.net - */ -/* jacobi-2d.c: this file is part of PolyBench/C */ - -/************************************************************************* - * RISC-V Vectorized Version - * Author: Cristóbal Ramírez Lazo - * email: cristobal.ramirez@bsc.es - * Barcelona Supercomputing Center (2020) - *************************************************************************/ - -// Porting to Ara SW environment -// Author: Matteo Perotti, ETH Zurich, - -#ifndef _JACOBI2D_H_ - -#define _JACOBI2D_H_ - -#include -#include -#include - -#include - -#include "util.h" - -// The vector algorithm seems not to be parametrized on the data type -// So, don't change this parameter if also the vector implementation is used -#define DATA_TYPE double - -// Threshold for FP numbers comparison during the final check -#define THRESHOLD 0.000001 - -// #define SOURCE_PRINT -// #define RESULT_PRINT - -void j2d_s(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B, uint64_t tsteps); -void j2d_v(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B, uint64_t tsteps); -void j2d_kernel_v(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B); -void j2d_kernel_opt_v(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B); -void j2d_kernel_asm_v(uint64_t r, uint64_t c, DATA_TYPE *A, DATA_TYPE *B); - -int check_result(uint64_t r, uint64_t c, DATA_TYPE *A_s, DATA_TYPE *B_s, - DATA_TYPE *A_v, DATA_TYPE *B_v); -void output_printfile(uint64_t r, uint64_t c, DATA_TYPE *A); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/main.c b/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/main.c deleted file mode 100644 index 7fbefbad..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-jacobi2d/main.c +++ /dev/null @@ -1,124 +0,0 @@ -/* -OHIO STATE UNIVERSITY SOFTWARE DISTRIBUTION LICENSE - -PolyBench/C, a collection of benchmarks containing static control -parts (the "Software") -Copyright (c) 2010-2016, Ohio State University. All rights reserved. - -The Software is available for download and use subject to the terms -and conditions of this License. Access or use of the Software -constitutes acceptance and agreement to the terms and conditions of -this License. Redistribution and use of the Software in source and -binary forms, with or without modification, are permitted provided -that the following conditions are met: - -1. Redistributions of source code must retain the above copyright -notice, this list of conditions and the capitalized paragraph below. - -2. Redistributions in binary form must reproduce the above copyright -notice, this list of conditions and the capitalized paragraph below in -the documentation and/or other materials provided with the -distribution. - -3. The name of Ohio State University, or its faculty, staff or -students may not be used to endorse or promote products derived from -the Software without specific prior written permission. - -This software was produced with support from the U.S. Defense Advanced -Research Projects Agency (DARPA), the U.S. Department of Energy (DoE) -and the U.S. National Science Foundation. Nothing in this work should -be construed as reflecting the official policy or position of the -Defense Department, the United States government or Ohio State -University. - -THIS SOFTWARE HAS BEEN APPROVED FOR PUBLIC RELEASE, UNLIMITED -DISTRIBUTION. THE SOFTWARE IS PROVIDED ?AS IS? AND WITHOUT ANY -EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED -TO, WARRANTIES OF ACCURACY, COMPLETENESS, NONINFRINGEMENT, -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -ACCESS OR USE OF THE SOFTWARE IS ENTIRELY AT THE USER?S RISK. IN NO -EVENT SHALL OHIO STATE UNIVERSITY OR ITS FACULTY, STAFF OR STUDENTS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE USER SHALL -INDEMNIFY, DEFEND AND HOLD HARMLESS OHIO STATE UNIVERSITY AND ITS -FACULTY, STAFF AND STUDENTS FROM ANY AND ALL CLAIMS, ACTIONS, DAMAGES, -LOSSES, LIABILITIES, COSTS AND EXPENSES, INCLUDING ATTORNEYS? FEES AND -COURT COSTS, DIRECTLY OR INDIRECTLY ARISING OUT OF OR IN CONNECTION -WITH ACCESS OR USE OF THE SOFTWARE. -*/ - -/** - * This version is stamped on May 10, 2016 - * - * Contact: - * Louis-Noel Pouchet - * Tomofumi Yuki - * - * Web address: http://polybench.sourceforge.net - */ -/* jacobi-2d.c: this file is part of PolyBench/C */ - -/************************************************************************* - * RISC-V Vectorized Version - * Author: Cristóbal Ramírez Lazo - * email: cristobal.ramirez@bsc.es - * Barcelona Supercomputing Center (2020) - *************************************************************************/ - -// Porting to Ara SW environment -// Author: Matteo Perotti, ETH Zurich, - -#include -#include - -#include "ara/util.h" -#include "jacobi2d.h" -#include "util.h" - -// The padded matrices should be aligned in SW not on the padding, -// but on the actual data. -// R and C contain the padding as well. -extern uint64_t R; -extern uint64_t C; - -extern uint64_t TSTEPS; - -extern DATA_TYPE A_s[] __attribute__((aligned(32), section(".l2"))); -extern DATA_TYPE B_s[] __attribute__((aligned(32), section(".l2"))); -extern DATA_TYPE A_v[] __attribute__((aligned(32), section(".l2"))); -extern DATA_TYPE B_v[] __attribute__((aligned(32), section(".l2"))); - -int main() { - printf("JACOBI2D\n"); - - int error = 0; - unsigned long cycles1, cycles2, instr2, instr1; - -#if PREALLOCATE - j2d_v(R, C, A_v, B_v, TSTEPS); -#endif - - // Measure vector kernel execution - printf("Processing the vector benchmark\n"); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - j2d_v(R, C, A_v, B_v, TSTEPS); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - int64_t runtime = cycles2 - cycles1; - // 2* since we have 2 jacobi kernels, one on A_fixed_v, one on B_fixed_v - // TSTEPS*5*N*N is the number of DPFLOP to compute - float performance = (2.0 * TSTEPS * 5.0 * (R - 1) * (C - 1) / runtime); - printf("operations = %ld\n", (size_t)(TSTEPS * 5.0 * (R - 1) * (C - 1))); - printf("Vector jacobi2d (R=%ld C=%ld) cycle count: %d\n", R, C, runtime); - printf("The performance is %ld DPFLOP/1000 cycles\n", - (uint64_t)(1000.0 * performance)); - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-log/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-log/gen_data.py deleted file mode 100644 index 0c7f239f..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-log/gen_data.py +++ /dev/null @@ -1,71 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: vector size, arg2: filter size - -import random as rand -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -def rand_matrix(N, dtype): - return np.random.rand(N).astype(dtype) - - -# SCRIPT - -if len(sys.argv) == 2: - N_f64 = int(sys.argv[1]) - N_f32 = 2 * N_f64 -else: - print("Error. Give me one argument: the number of vector elements.") - sys.exit() - -# Vector of samples -args_f64 = rand_matrix(N_f64, np.float64).astype(np.float64) -args_f32 = rand_matrix(N_f32, np.float32).astype(np.float32) - -# Results buffer -results_f64 = np.zeros(N_f64, dtype=np.float64) -results_f32 = np.zeros(N_f32, dtype=np.float32) - -# Gold results -gold_results_f64 = np.log(args_f64, dtype=np.float64) -gold_results_f32 = np.log(args_f32, dtype=np.float32) - -# Create the file -print('.section .data,"aw",@progbits') -emit("N_f64", np.array(N_f64, dtype=np.uint64)) -emit("args_f64", args_f64, "NR_LANES*4") -emit("results_f64", results_f64, "NR_LANES*4") -emit("gold_results_f64", gold_results_f64, "NR_LANES*4") -emit("N_f32", np.array(N_f32, dtype=np.uint32)) -emit("args_f32", args_f32, "NR_LANES*4") -emit("results_f32", results_f32, "NR_LANES*4") -emit("gold_results_f32", gold_results_f32, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-log/log.c b/bb-tests/workloads/src/CTest/rvv/vec-log/log.c deleted file mode 100644 index a6253160..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-log/log.c +++ /dev/null @@ -1,59 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include "log.h" - -void log_1xf64_bmark(double *args, double *results, size_t len) { - - size_t avl = len; - vfloat64m1_t log_vec, res_vec; - - for (size_t vl = __riscv_vsetvl_e64m1(avl); avl > 0; avl -= vl) { - // Strip-mine - vl = __riscv_vsetvl_e64m1(avl); - // Load vector - log_vec = __riscv_vle64_v_f64m1(args, vl); - // Compute - res_vec = __log_1xf64(log_vec, vl); - // Store - __riscv_vse64_v_f64m1(results, res_vec, vl); - // Bump pointers - args += vl; - results += vl; - } -} - -void log_2xf32_bmark(float *args, float *results, size_t len) { - - size_t avl = len; - vfloat32m1_t log_vec, res_vec; - - for (size_t vl = __riscv_vsetvl_e32m1(avl); avl > 0; avl -= vl) { - // Strip-mine - vl = __riscv_vsetvl_e32m1(avl); - // Load vector - log_vec = __riscv_vle32_v_f32m1(args, vl); - // Compute - res_vec = __log_2xf32(log_vec, vl); - // Store - __riscv_vse32_v_f32m1(results, res_vec, vl); - // Bump pointers - args += vl; - results += vl; - } -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-log/log.h b/bb-tests/workloads/src/CTest/rvv/vec-log/log.h deleted file mode 100644 index af6685a6..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-log/log.h +++ /dev/null @@ -1,157 +0,0 @@ -// Modified version of: -// "RISC-V VECTOR LOG FUNCTION Version by Cristóbal Ramírez Lazo, "Barcelona -// 2019"" Find details on the original version below Author: Matteo Perotti -// - -// RISC-V VECTOR LOG FUNCTION Version by Cristóbal Ramírez Lazo, "Barcelona -// 2019" This RISC-V Vector implementation is based on the original code -// presented by Julien Pommier - -/* - AVX implementation of sin, cos, sincos, exp and log - Based on "sse_mathfun.h", by Julien Pommier - http://gruntthepeon.free.fr/ssemath/ - Copyright (C) 2012 Giovanni Garberoglio - Interdisciplinary Laboratory for Computational Science (LISC) - Fondazione Bruno Kessler and University of Trento - via Sommarive, 18 - I-38123 Trento (Italy) - This software is provided 'as-is', without any express or implied - warranty. In no event will the authors be held liable for any damages - arising from the use of this software. - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software - in a product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not be - misrepresented as being the original software. - 3. This notice may not be removed or altered from any source distribution. - (this is the zlib license) -*/ - -#include -#include - -#include "ara/rivec/vector_defines.h" - -void log_1xf64_bmark(double *args, double *results, size_t len); -void log_2xf32_bmark(float *args, float *results, size_t len); - -inline _MMR_f64 __log_1xf64(_MMR_f64 x, unsigned long int gvl) { - - _MMR_i64 _x_i; - _MMR_u64 imm0_u; - _MMR_i64 imm0; - _MMR_f64 e; - _MMR_MASK_i64 invalid_mask = _MM_VFLE_f64(x, _MM_SET_f64(0.0f, gvl), gvl); - - x = _MM_MAX_f64(x, _MM_CAST_f64_i64(_MM_SET_i64(0x0010000000000000, gvl)), - gvl); /* cut off denormalized stuff */ - imm0_u = _MM_SRL_i64(_MM_CAST_u64_f64(x), - _MM_CAST_u64_i64(_MM_SET_i64(52, gvl)), gvl); - imm0 = _MM_CAST_i64_u64(imm0_u); - /* keep only the fractional part */ - _x_i = _MM_AND_i64(_MM_CAST_i64_f64(x), _MM_SET_i64(~0x7ff0000000000000, gvl), - gvl); - _x_i = _MM_OR_i64(_x_i, _MM_CAST_i64_f64(_MM_SET_f64(0.5f, gvl)), gvl); - x = _MM_CAST_f64_i64(_x_i); - imm0 = _MM_SUB_i64(imm0, _MM_SET_i64(1023, gvl), gvl); - e = _MM_VFCVT_F_X_f64(imm0, gvl); - e = _MM_ADD_f64(e, _MM_SET_f64(1.0f, gvl), gvl); - - _MMR_MASK_i64 mask = - _MM_VFLT_f64(x, _MM_SET_f64(0.707106781186547524, gvl), gvl); - _MMR_f64 tmp = _MM_MERGE_f64(_MM_SET_f64(0.0f, gvl), x, mask, gvl); - - x = _MM_SUB_f64(x, _MM_SET_f64(1.0f, gvl), gvl); - e = _MM_SUB_f64( - e, - _MM_MERGE_f64(_MM_SET_f64(0.0f, gvl), _MM_SET_f64(1.0f, gvl), mask, gvl), - gvl); - x = _MM_ADD_f64(x, tmp, gvl); - - _MMR_f64 z = _MM_MUL_f64(x, x, gvl); - _MMR_f64 y; - - y = _MM_MADD_f64(_MM_SET_f64(7.0376836292E-2, gvl), x, - _MM_SET_f64(-1.1514610310E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(1.1676998740E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(-1.2420140846E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(1.4249322787E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(-1.6668057665E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(2.0000714765E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(-2.4999993993E-1, gvl), gvl); - y = _MM_MADD_f64(y, x, _MM_SET_f64(3.3333331174E-1, gvl), gvl); - y = _MM_MUL_f64(y, z, gvl); - y = _MM_MACC_f64(y, e, _MM_SET_f64(-2.12194440e-4, gvl), gvl); - tmp = _MM_MUL_f64(z, _MM_SET_f64(0.5f, gvl), gvl); - y = _MM_SUB_f64(y, tmp, gvl); - tmp = _MM_MUL_f64(e, _MM_SET_f64(0.693359375, gvl), gvl); - x = _MM_ADD_f64(x, y, gvl); - x = _MM_ADD_f64(x, tmp, gvl); - x = _MM_MERGE_f64(x, _MM_CAST_f64_i64(_MM_SET_i64(0xffffffffffffffff, gvl)), - invalid_mask, gvl); - - return x; -} - -inline _MMR_f32 __log_2xf32(_MMR_f32 x, unsigned long int gvl) { - - _MMR_i32 _x_i; - _MMR_u32 imm0_u; - _MMR_i32 imm0; - _MMR_f32 e; - - _MMR_MASK_i32 invalid_mask = _MM_VFLE_f32(x, _MM_SET_f32(0.0f, gvl), gvl); - - x = _MM_MAX_f32(x, _MM_CAST_f32_i32(_MM_SET_i32(0x00800000, gvl)), - gvl); /* cut off denormalized stuff */ - imm0_u = _MM_SRL_i32(_MM_CAST_u32_f32(x), - _MM_CAST_u32_i32(_MM_SET_i32(23, gvl)), gvl); - imm0 = _MM_CAST_i32_u32(imm0_u); - /* keep only the fractional part */ - _x_i = _MM_AND_i32(_MM_CAST_i32_f32(x), _MM_SET_i32(~0x7f800000, gvl), gvl); - _x_i = _MM_OR_i32(_x_i, _MM_CAST_i32_f32(_MM_SET_f32(0.5f, gvl)), gvl); - x = _MM_CAST_f32_i32(_x_i); - imm0 = _MM_SUB_i32(imm0, _MM_SET_i32(0x7f, gvl), gvl); - e = _MM_VFCVT_F_X_f32(imm0, gvl); - e = _MM_ADD_f32(e, _MM_SET_f32(1.0f, gvl), gvl); - - _MMR_MASK_i32 mask = - _MM_VFLT_f32(x, _MM_SET_f32(0.707106781186547524, gvl), gvl); - _MMR_f32 tmp = _MM_MERGE_f32(_MM_SET_f32(0.0f, gvl), x, mask, gvl); - - x = _MM_SUB_f32(x, _MM_SET_f32(1.0f, gvl), gvl); - e = _MM_SUB_f32( - e, - _MM_MERGE_f32(_MM_SET_f32(0.0f, gvl), _MM_SET_f32(1.0f, gvl), mask, gvl), - gvl); - x = _MM_ADD_f32(x, tmp, gvl); - - _MMR_f32 z = _MM_MUL_f32(x, x, gvl); - _MMR_f32 y; - - y = _MM_MADD_f32(_MM_SET_f32(7.0376836292E-2, gvl), x, - _MM_SET_f32(-1.1514610310E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(1.1676998740E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(-1.2420140846E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(1.4249322787E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(-1.6668057665E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(2.0000714765E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(-2.4999993993E-1, gvl), gvl); - y = _MM_MADD_f32(y, x, _MM_SET_f32(3.3333331174E-1, gvl), gvl); - y = _MM_MUL_f32(y, z, gvl); - y = _MM_MACC_f32(y, e, _MM_SET_f32(-2.12194440e-4, gvl), gvl); - tmp = _MM_MUL_f32(z, _MM_SET_f32(0.5f, gvl), gvl); - y = _MM_SUB_f32(y, tmp, gvl); - tmp = _MM_MUL_f32(e, _MM_SET_f32(0.693359375, gvl), gvl); - x = _MM_ADD_f32(x, y, gvl); - x = _MM_ADD_f32(x, tmp, gvl); - x = _MM_MERGE_f32(x, _MM_CAST_f32_i32(_MM_SET_i32(0xffffffff, gvl)), - invalid_mask, gvl); - - return x; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-log/main.c b/bb-tests/workloads/src/CTest/rvv/vec-log/main.c deleted file mode 100644 index 30cf36a0..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-log/main.c +++ /dev/null @@ -1,87 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include -#include - -#include "ara/util.h" -#include "log.h" -#include "util.h" - -#define THRESHOLD 0.1 - -#define CHECK - -extern size_t N_f64; -extern double args_f64[] __attribute__((aligned(16))); -extern double results_f64[] __attribute__((aligned(16))); -extern double gold_results_f64[] __attribute__((aligned(16))); - -extern size_t N_f32; -extern float args_f32[] __attribute__((aligned(16))); -extern float results_f32[] __attribute__((aligned(16))); -extern float gold_results_f32[] __attribute__((aligned(16))); - -// Natural logarithm (base e) -int main() { - printf("FLOG\n"); - unsigned long cycles1, cycles2, instr2, instr1; - - int error = 0; - int64_t runtime; - - printf("Executing natural log (base e) on %d 64-bit data...\n", N_f64); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - log_1xf64_bmark(args_f64, results_f64, N_f64); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - runtime = cycles2 = cycles1; - printf("The execution took %d cycles.\n", runtime); - - printf("Executing natural log (base e) on %d 32-bit data...\n", N_f32); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - log_2xf32_bmark(args_f32, results_f32, N_f32); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - runtime = cycles2 = cycles1; - printf("The execution took %d cycles.\n", runtime); - -#ifdef CHECK - printf("Checking results:\n"); - - for (uint64_t i = 0; i < N_f64; ++i) { - if (!similarity_check(results_f64[i], gold_results_f64[i], THRESHOLD)) { - error = 1; - printf("64-bit error at index %d. %f != %f\n", i, results_f64[i], - gold_results_f64[i]); - } - } - for (uint64_t i = 0; i < N_f32; ++i) { - if (!similarity_check(results_f32[i], gold_results_f32[i], THRESHOLD)) { - error = 1; - printf("32-bit error at index %d. %f != %f\n", i, results_f32[i], - gold_results_f32[i]); - } - } -#endif - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/dataset1.h deleted file mode 100644 index d93de1e0..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/dataset1.h +++ /dev/null @@ -1,181 +0,0 @@ -#define DATA_SIZE 1000 - -int8_t input1_data[DATA_SIZE] = { - 0, 8, 5, 1, 7, 3, 1, 9, 5, 8, 6, 0, 9, 8, 3, 6, 9, 1, 1, 2, 4, 3, 6, 7, 3, - 6, 8, 3, 4, 9, 5, 5, 2, 2, 7, 6, 5, 6, 1, 0, 2, 2, 3, 9, 9, 2, 9, 8, 9, 9, - 1, 9, 5, 3, 6, 6, 1, 1, 8, 0, 2, 3, 1, 9, 8, 2, 5, 9, 7, 2, 4, 5, 4, 2, 4, - 7, 6, 3, 2, 9, 2, 1, 6, 6, 3, 3, 4, 2, 3, 3, 5, 0, 9, 4, 3, 5, 5, 9, 7, 2, - 7, 5, 1, 0, 1, 9, 9, 8, 5, 4, 6, 9, 2, 0, 0, 0, 0, 4, 5, 6, 3, 2, 8, 9, 8, - 3, 4, 5, 9, 3, 8, 8, 5, 9, 7, 3, 5, 8, 0, 5, 6, 4, 4, 1, 0, 0, 2, 0, 4, 7, - 8, 4, 4, 3, 5, 5, 8, 6, 2, 2, 4, 2, 8, 2, 7, 6, 2, 7, 5, 3, 5, 5, 3, 9, 2, - 8, 3, 7, 7, 9, 3, 7, 2, 9, 6, 7, 0, 3, 1, 1, 3, 6, 8, 8, 3, 1, 0, 1, 9, 3, - 5, 7, 5, 8, 5, 0, 1, 0, 1, 1, 7, 3, 9, 0, 1, 1, 8, 4, 2, 2, 4, 6, 3, 5, 7, - 5, 1, 0, 7, 5, 7, 0, 7, 0, 2, 8, 1, 7, 3, 9, 9, 3, 4, 4, 5, 6, 2, 7, 1, 8, - 9, 2, 2, 0, 7, 5, 3, 8, 8, 7, 2, 0, 4, 4, 7, 4, 0, 2, 3, 5, 7, 8, 4, 7, 5, - 7, 0, 3, 8, 9, 9, 5, 7, 4, 2, 4, 6, 0, 3, 2, 3, 2, 5, 7, 7, 5, 8, 8, 1, 1, - 6, 0, 2, 1, 8, 0, 3, 1, 8, 1, 1, 0, 7, 2, 1, 5, 2, 5, 1, 2, 6, 7, 7, 0, 0, - 8, 8, 5, 3, 4, 0, 6, 0, 1, 7, 9, 6, 8, 8, 2, 4, 1, 5, 5, 0, 9, 9, 3, 4, 1, - 5, 9, 5, 4, 3, 2, 4, 6, 3, 5, 6, 0, 1, 3, 1, 2, 3, 2, 4, 1, 6, 9, 7, 6, 0, - 1, 4, 9, 0, 7, 8, 1, 1, 0, 1, 8, 8, 4, 1, 2, 8, 8, 5, 3, 6, 4, 8, 9, 1, 4, - 8, 1, 5, 8, 4, 7, 8, 7, 8, 7, 1, 4, 2, 9, 1, 7, 5, 7, 4, 5, 7, 5, 3, 7, 9, - 2, 9, 2, 1, 5, 1, 7, 7, 1, 3, 7, 6, 5, 1, 0, 5, 8, 0, 5, 7, 6, 7, 4, 0, 9, - 7, 9, 8, 3, 0, 8, 9, 7, 1, 8, 6, 1, 8, 0, 6, 0, 2, 7, 7, 2, 1, 7, 9, 4, 3, - 3, 2, 5, 7, 7, 9, 0, 0, 9, 9, 8, 5, 8, 9, 2, 5, 5, 9, 4, 5, 2, 2, 8, 1, 4, - 7, 0, 6, 1, 2, 3, 7, 6, 0, 3, 9, 6, 7, 9, 2, 1, 1, 3, 1, 7, 9, 6, 5, 6, 4, - 2, 5, 5, 4, 9, 7, 2, 3, 9, 6, 0, 5, 4, 9, 2, 0, 2, 3, 8, 7, 6, 7, 6, 9, 3, - 0, 1, 4, 3, 6, 3, 9, 4, 4, 7, 7, 9, 5, 8, 0, 5, 9, 8, 1, 9, 2, 1, 3, 0, 0, - 0, 4, 7, 3, 3, 6, 7, 7, 3, 2, 5, 6, 5, 8, 0, 2, 4, 7, 4, 5, 1, 6, 8, 2, 7, - 1, 4, 4, 9, 1, 6, 8, 2, 2, 5, 9, 5, 1, 2, 7, 9, 7, 3, 4, 6, 7, 1, 3, 3, 3, - 3, 7, 0, 4, 5, 1, 3, 2, 3, 0, 3, 9, 6, 9, 3, 0, 5, 2, 6, 3, 8, 8, 3, 1, 5, - 5, 8, 3, 9, 4, 9, 1, 2, 1, 7, 0, 8, 6, 0, 7, 9, 8, 1, 9, 7, 5, 7, 2, 7, 1, - 1, 2, 4, 9, 0, 3, 6, 3, 1, 1, 1, 8, 7, 5, 2, 0, 6, 3, 9, 1, 0, 9, 1, 1, 5, - 3, 3, 5, 7, 3, 8, 5, 5, 4, 3, 5, 2, 9, 5, 3, 4, 7, 1, 4, 8, 8, 7, 5, 3, 0, - 8, 6, 5, 6, 9, 1, 3, 9, 9, 6, 7, 1, 8, 5, 9, 4, 3, 1, 2, 1, 5, 8, 1, 9, 2, - 4, 3, 7, 4, 7, 5, 4, 3, 7, 4, 8, 7, 0, 5, 2, 1, 6, 7, 5, 8, 5, 3, 5, 9, 2, - 2, 3, 4, 2, 2, 5, 4, 1, 3, 6, 5, 5, 6, 1, 7, 8, 4, 0, 0, 1, 0, 8, 4, 3, 0, - 0, 1, 0, 3, 7, 6, 2, 9, 0, 6, 9, 6, 8, 7, 7, 4, 6, 5, 9, 8, 2, 9, 1, 5, 5, - 8, 9, 2, 6, 6, 6, 9, 3, 3, 4, 1, 2, 1, 8, 2, 3, 1, 8, 3, 3, 8, 0, 4, 6, 5, - 2, 0, 7, 8, 8, 8, 6, 4, 0, 2, 4, 2, 6, 0, 3, 4, 0, 0, 7, 8, 5, 4, 3, 3, 2, - 4, 4, 6, 5, 3, 4, 5, 1, 8, 3, 9, 2, 1, 9, 0, 9, 3, 3, 2, 2, 6, 0, 9, 4, 2, - 3, 0, 6, 0, 6, 9, 9, 8, 4, 6, 8, 5, 6, 0, 3, 3, 0, 9, 7, 4, 8, 8, 5, 1, 7, - 0, 6, 5, 9, 7, 8, 2, 6, 8, 7, 4, 8, 6, 6, 6, 0, 7, 7, 1, 5, 0, 9, 6, 6, 3, - 2, 2, 6, 6, 5, 1, 5, 7, 0, 3, 9, 5, 3, 7, 6, 5, 2, 8, 9, 4, 7, 5, 0, 2, 7, - 7, 4, 6, 6, 4, 8, 3, 6, 2, 1, 3, 2, 7, 2, 9, 6, 6, 9, 2, 6, 3, 8, 6, 4, 9}; - -int input2_data[DATA_SIZE] = { - 454, 335, 1, 989, 365, 572, 64, 153, 216, 140, 210, 572, 339, 593, 898, - 228, 12, 883, 750, 646, 500, 436, 701, 812, 981, 150, 696, 564, 272, 258, - 647, 509, 88, 703, 669, 375, 551, 936, 592, 569, 952, 800, 584, 643, 368, - 489, 328, 313, 592, 388, 543, 649, 979, 997, 814, 79, 208, 998, 629, 847, - 704, 997, 253, 715, 430, 415, 538, 700, 4, 494, 100, 864, 693, 416, 296, - 285, 620, 78, 351, 540, 646, 169, 527, 289, 796, 801, 720, 758, 745, 92, - 989, 271, 853, 788, 531, 222, 461, 241, 358, 332, 684, 740, 446, 311, 743, - 557, 479, 557, 925, 796, 357, 891, 666, 514, 557, 870, 853, 440, 61, 678, - 396, 9, 17, 170, 291, 380, 536, 185, 917, 539, 983, 887, 54, 612, 951, - 479, 151, 7, 641, 335, 730, 95, 728, 280, 395, 688, 911, 476, 815, 729, - 265, 127, 236, 214, 180, 6, 503, 596, 173, 643, 346, 599, 68, 849, 658, - 619, 121, 131, 828, 667, 433, 487, 753, 125, 626, 14, 10, 403, 106, 703, - 818, 964, 406, 874, 856, 86, 60, 660, 667, 153, 121, 98, 412, 236, 12, - 423, 965, 216, 621, 361, 921, 715, 647, 299, 886, 682, 36, 493, 551, 537, - 969, 643, 434, 415, 303, 438, 860, 203, 478, 988, 675, 719, 990, 338, 450, - 633, 155, 646, 452, 427, 509, 988, 426, 12, 483, 142, 339, 390, 50, 171, - 601, 105, 968, 121, 879, 81, 870, 600, 603, 871, 887, 610, 404, 234, 745, - 526, 275, 441, 226, 752, 943, 726, 709, 201, 54, 758, 53, 397, 41, 141, - 416, 747, 219, 478, 770, 180, 482, 691, 725, 173, 186, 914, 1, 963, 247, - 464, 362, 521, 233, 120, 40, 779, 195, 161, 743, 439, 355, 403, 141, 633, - 289, 782, 320, 636, 118, 852, 70, 816, 388, 954, 36, 16, 698, 695, 677, - 598, 883, 824, 746, 462, 511, 534, 440, 428, 732, 726, 702, 547, 86, 798, - 215, 21, 651, 59, 429, 657, 96, 973, 659, 966, 524, 62, 625, 303, 714, - 409, 55, 728, 305, 436, 901, 592, 691, 796, 497, 177, 940, 995, 480, 158, - 822, 611, 680, 14, 111, 797, 185, 0, 718, 96, 749, 739, 814, 435, 326, - 37, 33, 605, 935, 27, 88, 441, 339, 344, 554, 365, 954, 639, 396, 991, - 249, 338, 832, 974, 393, 266, 470, 348, 336, 419, 249, 215, 542, 903, 636, - 729, 581, 820, 671, 979, 418, 670, 920, 568, 745, 662, 139, 385, 927, 173, - 457, 316, 183, 477, 196, 399, 416, 805, 996, 270, 735, 696, 825, 528, 50, - 623, 537, 87, 294, 867, 110, 398, 781, 646, 375, 943, 897, 589, 44, 288, - 845, 742, 99, 522, 443, 432, 165, 930, 28, 461, 323, 272, 376, 340, 898, - 158, 168, 443, 193, 631, 935, 274, 781, 185, 619, 292, 933, 156, 827, 88, - 987, 629, 649, 32, 1, 744, 399, 915, 791, 554, 984, 530, 600, 401, 683, - 540, 903, 120, 995, 521, 622, 224, 895, 530, 820, 651, 226, 96, 262, 569, - 238, 126, 610, 191, 238, 796, 884, 573, 108, 140, 789, 852, 23, 704, 890, - 480, 52, 372, 201, 546, 408, 119, 645, 464, 81, 293, 52, 880, 224, 744, - 735, 886, 167, 1, 532, 321, 169, 485, 101, 177, 42, 708, 654, 915, 625, - 242, 822, 795, 641, 252, 245, 151, 876, 333, 601, 938, 775, 397, 233, 755, - 454, 424, 210, 962, 900, 923, 655, 529, 595, 90, 464, 685, 70, 754, 32, - 494, 25, 389, 488, 37, 409, 639, 27, 950, 539, 80, 303, 723, 734, 125, - 552, 248, 107, 362, 48, 869, 144, 841, 724, 335, 470, 263, 343, 809, 677, - 339, 336, 410, 465, 56, 590, 485, 406, 993, 746, 238, 525, 336, 256, 134, - 546, 722, 367, 943, 106, 629, 396, 208, 429, 523, 130, 355, 990, 673, 991, - 719, 449, 84, 616, 211, 707, 737, 847, 452, 316, 974, 746, 796, 522, 618, - 115, 727, 226, 165, 200, 830, 742, 187, 705, 671, 785, 886, 962, 657, 293, - 620, 144, 173, 796, 72, 678, 80, 793, 685, 637, 967, 241, 898, 693, 372, - 601, 721, 398, 553, 72, 174, 978, 325, 558, 185, 505, 859, 651, 573, 321, - 349, 400, 890, 844, 885, 933, 980, 448, 989, 50, 332, 900, 716, 747, 444, - 6, 394, 285, 703, 450, 652, 771, 485, 534, 559, 481, 507, 434, 343, 42, - 784, 865, 421, 415, 871, 539, 162, 105, 481, 595, 115, 350, 964, 287, 232, - 154, 602, 539, 943, 872, 121, 652, 811, 747, 362, 340, 910, 206, 572, 505, - 973, 961, 354, 627, 849, 971, 910, 410, 770, 63, 874, 396, 482, 619, 646, - 557, 328, 67, 884, 512, 972, 6, 513, 882, 562, 764, 366, 506, 786, 831, - 382, 638, 452, 72, 83, 59, 932, 929, 924, 961, 69, 797, 985, 854, 885, - 600, 389, 232, 793, 179, 773, 689, 775, 494, 139, 234, 431, 780, 371, 22, - 653, 741, 815, 428, 139, 603, 315, 344, 889, 317, 260, 861, 377, 511, 304, - 70, 35, 854, 576, 490, 326, 303, 431, 813, 708, 388, 962, 967, 442, 49, - 831, 251, 321, 741, 179, 176, 117, 523, 764, 952, 704, 531, 804, 23, 611, - 846, 375, 854, 971, 24, 639, 318, 723, 662, 647, 281, 158, 294, 885, 734, - 866, 471, 296, 673, 472, 439, 5, 155, 506, 948, 600, 445, 222, 784, 349, - 943, 150, 366, 444, 604, 720, 340, 972, 911, 321, 435, 50, 78, 761, 950, - 238, 27, 226, 201, 176, 877, 450, 879, 99, 143, 31, 812, 771, 527, 488, - 797, 194, 293, 966, 276, 345, 413, 197, 386, 116, 322, 680, 538, 553, 960, - 874, 48, 506, 898, 539, 495, 764, 805, 286, 432, 836, 192, 825, 778, 586, - 359, 352, 746, 11, 749, 5, 408, 643, 441, 368, 97, 169, 359, 527, 672, - 69, 880, 298, 300, 327, 923, 829, 816, 497, 243, 981, 917, 713, 653, 503, - 406, 543, 108, 304, 464, 954, 86, 802, 446, 28}; - -int verify_data[DATA_SIZE] = { - 454, 1, 1, 989, 1, 572, 64, 1, 1, 1, 1, 572, 1, 1, 898, - 1, 1, 883, 750, 646, 500, 436, 1, 1, 981, 1, 1, 564, 272, 1, - 1, 1, 88, 703, 1, 1, 1, 1, 592, 569, 952, 800, 584, 1, 1, - 489, 1, 1, 1, 1, 543, 1, 1, 997, 1, 1, 208, 998, 1, 847, - 704, 997, 253, 1, 1, 415, 1, 1, 1, 494, 100, 1, 693, 416, 296, - 1, 1, 78, 351, 1, 646, 169, 1, 1, 796, 801, 720, 758, 745, 92, - 1, 271, 1, 788, 531, 1, 1, 1, 1, 332, 1, 1, 446, 311, 743, - 1, 1, 1, 1, 796, 1, 1, 666, 514, 557, 870, 853, 440, 1, 1, - 396, 9, 1, 1, 1, 380, 536, 1, 1, 539, 1, 1, 1, 1, 1, - 479, 1, 1, 641, 1, 1, 95, 728, 280, 395, 688, 911, 476, 815, 1, - 1, 127, 236, 214, 1, 1, 1, 1, 173, 643, 346, 599, 1, 849, 1, - 1, 121, 1, 1, 667, 1, 1, 753, 1, 626, 1, 10, 1, 1, 1, - 818, 1, 406, 1, 1, 1, 60, 660, 667, 153, 121, 1, 1, 1, 12, - 423, 965, 216, 1, 361, 1, 1, 1, 1, 1, 682, 36, 493, 551, 537, - 1, 643, 1, 415, 303, 438, 1, 203, 478, 988, 675, 1, 990, 1, 1, - 1, 155, 646, 1, 1, 1, 988, 1, 12, 483, 1, 339, 1, 50, 1, - 1, 105, 968, 121, 1, 1, 870, 1, 603, 1, 1, 610, 404, 234, 1, - 1, 275, 1, 1, 1, 943, 726, 709, 201, 1, 758, 53, 397, 41, 1, - 1, 1, 219, 1, 1, 1, 482, 691, 1, 1, 1, 1, 1, 963, 247, - 464, 1, 521, 233, 120, 40, 779, 1, 1, 1, 1, 1, 1, 141, 633, - 1, 782, 320, 636, 1, 852, 70, 816, 1, 954, 36, 16, 1, 695, 677, - 1, 883, 1, 746, 462, 1, 1, 1, 428, 732, 1, 1, 1, 86, 798, - 215, 1, 651, 59, 1, 1, 1, 1, 1, 966, 524, 62, 1, 1, 714, - 1, 1, 728, 305, 436, 1, 1, 1, 796, 497, 177, 940, 1, 480, 1, - 1, 611, 680, 14, 111, 797, 185, 0, 718, 96, 1, 1, 1, 1, 326, - 37, 33, 1, 935, 1, 1, 441, 339, 344, 554, 1, 1, 639, 396, 991, - 1, 1, 1, 974, 1, 266, 1, 1, 336, 419, 1, 215, 1, 1, 636, - 1, 1, 1, 1, 1, 418, 670, 920, 1, 745, 1, 1, 1, 927, 1, - 1, 1, 183, 1, 1, 399, 1, 805, 996, 1, 735, 1, 1, 528, 50, - 1, 1, 1, 294, 867, 1, 1, 781, 1, 1, 1, 1, 589, 44, 1, - 1, 1, 1, 522, 443, 1, 1, 1, 28, 1, 1, 272, 1, 340, 1, - 158, 168, 1, 1, 631, 935, 1, 1, 185, 619, 292, 933, 1, 1, 1, - 1, 629, 649, 1, 1, 1, 1, 1, 1, 554, 1, 1, 1, 401, 1, - 540, 903, 1, 995, 521, 1, 224, 1, 530, 820, 651, 1, 1, 262, 569, - 1, 1, 1, 1, 238, 796, 884, 573, 108, 1, 1, 1, 1, 1, 890, - 480, 1, 1, 201, 1, 1, 119, 645, 1, 1, 293, 1, 880, 1, 744, - 735, 886, 167, 1, 1, 1, 1, 1, 1, 177, 42, 708, 654, 915, 1, - 242, 1, 795, 641, 1, 1, 1, 1, 1, 601, 1, 1, 1, 233, 1, - 454, 424, 210, 962, 900, 923, 655, 1, 595, 90, 1, 1, 1, 754, 32, - 1, 1, 1, 1, 37, 409, 639, 1, 950, 1, 80, 1, 1, 734, 1, - 552, 248, 107, 1, 48, 1, 1, 841, 724, 1, 1, 1, 343, 809, 1, - 1, 1, 410, 465, 1, 1, 485, 406, 993, 746, 238, 1, 336, 256, 1, - 546, 722, 367, 943, 106, 629, 1, 1, 1, 523, 130, 1, 990, 1, 991, - 1, 1, 84, 616, 1, 1, 1, 847, 1, 316, 1, 746, 796, 522, 1, - 115, 1, 1, 165, 1, 1, 1, 187, 1, 1, 1, 1, 962, 1, 293, - 620, 144, 173, 1, 72, 678, 1, 793, 685, 637, 967, 1, 1, 1, 372, - 601, 1, 398, 1, 72, 174, 1, 325, 558, 1, 505, 859, 1, 1, 321, - 1, 1, 1, 844, 885, 1, 980, 1, 1, 50, 332, 1, 716, 747, 1, - 1, 1, 1, 703, 450, 1, 1, 1, 1, 1, 481, 507, 1, 1, 1, - 1, 865, 1, 1, 1, 539, 162, 105, 481, 595, 1, 1, 964, 1, 232, - 154, 602, 1, 943, 1, 1, 652, 811, 1, 362, 1, 1, 206, 1, 505, - 973, 1, 1, 1, 1, 1, 910, 1, 1, 63, 874, 396, 482, 619, 646, - 1, 328, 67, 884, 1, 1, 1, 1, 882, 1, 1, 366, 506, 786, 831, - 382, 1, 452, 72, 83, 59, 932, 929, 924, 1, 1, 797, 1, 854, 1, - 1, 1, 1, 1, 1, 773, 1, 1, 1, 1, 234, 1, 780, 1, 1, - 1, 1, 815, 1, 1, 1, 1, 344, 889, 317, 260, 861, 377, 1, 304, - 70, 35, 1, 576, 490, 1, 303, 431, 1, 1, 388, 962, 1, 1, 1, - 1, 1, 321, 741, 179, 176, 117, 1, 764, 952, 704, 531, 804, 1, 1, - 1, 375, 854, 971, 24, 639, 318, 1, 1, 647, 281, 1, 294, 1, 734, - 1, 471, 296, 1, 472, 1, 5, 155, 506, 948, 1, 445, 1, 784, 349, - 943, 150, 1, 444, 1, 1, 1, 1, 911, 1, 1, 1, 1, 761, 950, - 238, 27, 1, 1, 176, 1, 1, 1, 99, 1, 31, 1, 1, 1, 1, - 1, 194, 1, 1, 1, 345, 1, 1, 1, 1, 322, 1, 1, 553, 1, - 874, 1, 1, 1, 539, 495, 764, 1, 1, 1, 836, 1, 1, 778, 586, - 1, 1, 746, 1, 1, 1, 408, 1, 1, 368, 1, 1, 359, 527, 1, - 1, 880, 1, 1, 327, 1, 829, 1, 497, 243, 981, 917, 1, 653, 1, - 1, 1, 1, 304, 1, 954, 1, 1, 446, 1}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/mixed_with_mask_gendata.pl b/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/mixed_with_mask_gendata.pl deleted file mode 100755 index dc9aa1a2..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/mixed_with_mask_gendata.pl +++ /dev/null @@ -1,191 +0,0 @@ -#!/usr/bin/perl -w -#========================================================================== -# conditional_gendata.pl -# -# Author: Generated -# Date: Today -# -(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm; -# -# Simple script which creates an input data set and the reference data -# for the given conditional operation. -# -ENDMSG - -use strict "vars"; -use warnings; -no warnings("once"); -use Getopt::Long; - -#-------------------------------------------------------------------------- -# Command line processing -#-------------------------------------------------------------------------- - -our %opts; - -sub usage() -{ - - print "\n"; - print " Usage: conditional_gendata.pl [options] \n"; - print "\n"; - print " Options:\n"; - print " --help print this message\n"; - print " --size size of input data [1000]\n"; - print " --seed random seed [1]\n"; - print "$usageMsg"; - - exit(); -} - -sub processCommandLine() -{ - - $opts{"help"} = 0; - $opts{"size"} = 1000; - $opts{"seed"} = 1; - Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage(); - $opts{"help"} and usage(); - -} - -#-------------------------------------------------------------------------- -# Helper Functions -#-------------------------------------------------------------------------- - -sub printArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print "int ".$arrayName."[DATA_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3d",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - -sub print8bitArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print "int8_t ".$arrayName."[DATA_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3d",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - my @input1_data; - my @input2_data; - my @verify_data; - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - my $valueA = int(rand(10)); # Ensure fluctuation around 5 - my $valueC = int(rand(999)); - - push( @input1_data, $valueA ); - push( @input2_data, $valueC ); - push( @verify_data, ($valueA < 5) ? $valueC : 1 ); - } - - print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n"; - print8bitArray( "input1_data", \@input1_data ); - printArray( "input2_data", \@input2_data ); - printArray( "verify_data", \@verify_data ); - -} - -main(); diff --git a/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/vec-mixed_width_mask.S b/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/vec-mixed_width_mask.S deleted file mode 100644 index 8af7edae..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-mixed_width_mask/vec-mixed_width_mask.S +++ /dev/null @@ -1,25 +0,0 @@ - .text - .balign 4 - .global vec_mixed_width_mask - -# Code using one width for predicate and different width for masked -# compute. -# int8_t a[]; int32_t b[], c[]; -# for (i=0; i - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void vec_mixed_width_mask(size_t n, int8_t x[], int y[], int z[]); - -int main(int argc, char *argv[]) { - int results_data[DATA_SIZE]; - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_mixed_width_mask(DATA_SIZE, input1_data, results_data, input2_data); -#endif - - // Do the compute - setStats(1); - vec_mixed_width_mask(DATA_SIZE, input1_data, results_data, input2_data); - setStats(0); - - // Check the results - return verify(DATA_SIZE, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/LICENSE_0 b/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/LICENSE_0 deleted file mode 100644 index a7393e56..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/LICENSE_0 +++ /dev/null @@ -1,41 +0,0 @@ -Pathfinder is derived by RODINIA. -Original RODINIA License: - -LICENSE TERMS - -Copyright (c)2008-2011 University of Virginia -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, are permitted without royalty fees or other restrictions, provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the name of the University of Virginia, the Dept. of Computer Science, nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF VIRGINIA OR THE SOFTWARE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -If you use this software or a modified version of it, please cite the most relevant among the following papers: - -- M. A. Goodrum, M. J. Trotter, A. Aksel, S. T. Acton, and K. Skadron. Parallelization of Particle Filter Algorithms. In Proceedings -of the 3rd Workshop on Emerging Applications and Many-core Architecture (EAMA), in conjunction with the IEEE/ACM International -Symposium on Computer Architecture (ISCA), June 2010. - -- S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, Sang-Ha Lee and K. Skadron. -"Rodinia: A Benchmark Suite for Heterogeneous Computing". IEEE International Symposium -on Workload Characterization, Oct 2009. - -- J. Meng and K. Skadron. "Performance Modeling and Automatic Ghost Zone Optimization -for Iterative Stencil Loops on GPUs." In Proceedings of the 23rd Annual ACM International -Conference on Supercomputing (ICS), June 2009. - -- L.G. Szafaryn, K. Skadron and J. Saucerman. "Experiences Accelerating MATLAB Systems -Biology Applications." in Workshop on Biomedicine in Computing (BiC) at the International -Symposium on Computer Architecture (ISCA), June 2009. - -- M. Boyer, D. Tarjan, S. T. Acton, and K. Skadron. "Accelerating Leukocyte Tracking using CUDA: -A Case Study in Leveraging Manycore Coprocessors." In Proceedings of the International Parallel -and Distributed Processing Symposium (IPDPS), May 2009. - -- S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron. "A Performance -Study of General Purpose Applications on Graphics Processors using CUDA" Journal of -Parallel and Distributed Computing, Elsevier, June 2008. diff --git a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/LICENSE_1 b/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/LICENSE_1 deleted file mode 100644 index 107b78e1..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/LICENSE_1 +++ /dev/null @@ -1,28 +0,0 @@ -The vectorized RODINIA comes from RiVEC Benchmark Suite. -RiVEC License: - -Copyright (c) 2020, Barcelona Supercomputing Center -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met: redistributions of source code must retain the above copyright -notice, this list of conditions and the following disclaimer; -redistributions in binary form must reproduce the above copyright -notice, this list of conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution; -neither the name of the copyright holders nor the names of its -contributors may be used to endorse or promote products derived from -this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/gen_data.py deleted file mode 100644 index 13741047..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/gen_data.py +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: vector size, arg2: filter size - -import random as rand -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -def rand_matrix(N, dtype): - return np.random.rand(N).astype(dtype) - - -# SCRIPT - -if len(sys.argv) == 4: - num_runs = int(sys.argv[1]) - cols = int(sys.argv[2]) - rows = int(sys.argv[3]) -else: - print("Error. Give me three arguments: num_runs, cols, and rows.") - sys.exit() - -dtype = np.int32 -dmax = np.iinfo(dtype).max - -# Vector of samples -wall = np.random.randint(10, size=rows * cols, dtype=dtype) - -# Buffers -result_s = np.zeros(cols, dtype=dtype) -result_v = np.zeros(cols, dtype=dtype) -src = np.zeros(cols, dtype=dtype) - -# Create the file -print('.section .data,"aw",@progbits') -emit("num_runs", np.array(num_runs, dtype=np.uint32)) -emit("rows", np.array(rows, dtype=np.uint32)) -emit("cols", np.array(cols, dtype=np.uint32)) -emit("wall", wall, "NR_LANES*4") -emit("result_s", result_s, "NR_LANES*4") -emit("result_v", result_v, "NR_LANES*4") -emit("src", src, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/main.c b/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/main.c deleted file mode 100644 index 60a19193..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/main.c +++ /dev/null @@ -1,89 +0,0 @@ -// Modified version of pathfinder from RODINIA and then RiVEC, adapted to Ara -// environment. Author: Matteo Perotti Check LICENSE_0 -// and LICENCE_1 for additional information - -/************************************************************************* - * RISC-V Vectorized Version - * Author: Cristóbal Ramírez Lazo - * email: cristobal.ramirez@bsc.es - * Barcelona Supercomputing Center (2020) - *************************************************************************/ - -#include -#include - -#include "pathfinder.h" -#include "util.h" -#include - -// #define CHECK - -extern int32_t num_runs; -extern int32_t rows; -extern int32_t cols; -extern int src[] __attribute__((aligned(32), section(".l2"))); -extern int wall[] __attribute__((aligned(32), section(".l2"))); -extern int result_v[] __attribute__((aligned(32), section(".l2"))); -extern int result_s[] __attribute__((aligned(32), section(".l2"))); - -int verify_result(int *result_s, int *result_v, uint32_t cols) { -#ifdef CHECK - // Check vector with scalar result - for (uint32_t i = 0; i < cols; i++) { - if (result_v[i] != result_s[i]) { - printf("Error. result_v[%d]=%d != result_s[%d]=%d \n", i, result_v[i], i, - result_s[i]); - return 1; - } - } - - printf("Test result: PASS. No errors found.\n"); -#else - volatile uint32_t x; - for (uint32_t i = 0; i < cols; i++) { - x = result_v[i]; - } -#endif - return 0; -} - -int main() { - printf("PATHFINDER\n"); - - int error; - int *s_ptr; - unsigned long cycles1, cycles2, instr2, instr1; - - printf("Number of runs: %d\n", num_runs); - printf("rows=%ld cols=%ld\n", rows, cols); - printf("operations=%ld\n", num_runs * cols * rows * 3); - -#ifdef CHECK - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - s_ptr = run(wall, result_s, src, cols, rows, num_runs); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - printf("Scalar code cycles: %d\n", cycles2 - cycles1); -#endif - -#define TEST(l) \ - instr1 = read_csr(minstret); \ - cycles1 = read_csr(mcycle); \ - run_vectorm##l(wall, result_v, cols, rows, num_runs); \ - asm volatile("fence"); \ - instr2 = read_csr(minstret); \ - cycles2 = read_csr(mcycle); \ - printf("Vector code LMUL=%d, cycles: %d\n", l, cycles2 - cycles1); \ - error = verify_result(s_ptr, result_v, cols); \ - if (error) \ - return error; - - TEST(1); - TEST(2); - TEST(4); - TEST(8); - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/pathfinder.c b/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/pathfinder.c deleted file mode 100644 index 8cae18b8..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/pathfinder.c +++ /dev/null @@ -1,100 +0,0 @@ -// Modified version of pathfinder from RODINIA and then RiVEC, adapted to Ara -// environment. Author: Matteo Perotti Check LICENSE_0 -// and LICENCE_1 for additional information - -/************************************************************************* - * RISC-V Vectorized Version - * Author: Cristóbal Ramírez Lazo - * email: cristobal.ramirez@bsc.es - * Barcelona Supercomputing Center (2020) - *************************************************************************/ - -#include "pathfinder.h" - -#define MIN(a, b) ((a < b) ? a : b) - -int *run(int *wall, int *result_s, int *src, uint32_t cols, uint32_t rows, - uint32_t num_runs) { - int min; - int *temp; - int *dst; - - for (uint32_t j = 0; j < num_runs; j++) { - for (uint32_t x = 0; x < cols; x++) { - result_s[x] = wall[x]; - } - - dst = result_s; - - for (uint32_t t = 0; t < rows - 1; t++) { - temp = src; - src = dst; - dst = temp; - for (uint32_t n = 0; n < cols; n++) { - min = src[n]; - if (n > 0) - min = MIN(min, src[n - 1]); - if (n < cols - 1) - min = MIN(min, src[n + 1]); - dst[n] = wall[(t + 1) * cols + n] + min; - } - } - // Reset the pointer not to lose it - src = temp; - } - return dst; -} - -#define IMPL(l) \ - void run_vectorm##l(int *wall, int *result_v, uint32_t cols, uint32_t rows, \ - uint32_t num_runs) { \ - \ - size_t gvl; \ - \ - vint32m##l##_t temp; \ - vint32m##l##_t xSrc_slideup; \ - vint32m##l##_t xSrc_slidedown; \ - vint32m##l##_t xSrc; \ - vint32m##l##_t xNextrow; \ - \ - int aux, aux2; \ - int *dst; \ - \ - for (uint32_t j = 0; j < num_runs; j++) { \ - for (uint32_t n = 0; n < cols; n += gvl) { \ - gvl = __riscv_vsetvl_e32m##l(cols); \ - temp = __riscv_vle32_v_i32m##l(&wall[n], gvl); \ - __riscv_vse32_v_i32m##l(&result_v[n], temp, gvl); \ - } \ - dst = result_v; \ - \ - gvl = __riscv_vsetvl_e32m##l(cols); \ - \ - for (uint32_t t = 0; t < rows - 1; t++) { \ - aux = dst[0]; \ - for (uint32_t n = 0; n < cols; n = n + gvl) { \ - gvl = __riscv_vsetvl_e32m##l(cols - n); \ - xNextrow = __riscv_vle32_v_i32m##l(&dst[n], gvl); \ - \ - xSrc = xNextrow; \ - aux2 = (n + gvl >= cols) ? dst[n + gvl - 1] : dst[n + gvl]; \ - xSrc_slideup = __riscv_vslide1up_vx_i32m##l(xSrc, aux, gvl); \ - xSrc_slidedown = __riscv_vslide1down_vx_i32m##l(xSrc, aux2, gvl); \ - \ - xSrc = __riscv_vmin_vv_i32m##l(xSrc, xSrc_slideup, gvl); \ - xSrc = __riscv_vmin_vv_i32m##l(xSrc, xSrc_slidedown, gvl); \ - \ - xNextrow = __riscv_vle32_v_i32m##l(&wall[(t + 1) * cols + n], gvl); \ - xNextrow = __riscv_vadd_vv_i32m##l(xNextrow, xSrc, gvl); \ - \ - aux = dst[n + gvl - 1]; \ - __riscv_vse32_v_i32m##l(&dst[n], xNextrow, gvl); \ - } \ - } \ - } \ - } - -IMPL(1) -IMPL(2) -IMPL(4) -IMPL(8) diff --git a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/pathfinder.h b/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/pathfinder.h deleted file mode 100644 index b1524b32..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-pathfinder/pathfinder.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _PATHFINDER_H_ -#define _PATHFINDER_H_ - -#include -#include -#include - -int *run(int *wall, int *result_s, int *src, uint32_t cols, uint32_t rows, - uint32_t num_runs); - -#define DECLARE(l) \ - void run_vectorm##l(int *wall, int *result_v, uint32_t cols, uint32_t rows, \ - uint32_t num_runs); - -DECLARE(1) -DECLARE(2) -DECLARE(4) -DECLARE(8) -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-roi-align/gen_data.py deleted file mode 100755 index c403e2b4..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/gen_data.py +++ /dev/null @@ -1,96 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: image size, arg2: filter size - -import numpy as np -import sys - - -# Batch * Depth * Height * Width -def rand_matrix(dims): - mtx = np.random.rand(*dims).astype(dtype=np.float32) - return mtx - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# Define the filter size and the matrix dimension (max, for now, is 128 64-bit elements) -if len(sys.argv) > 1: - batch_size = int(sys.argv[1]) - depth = int(sys.argv[2]) - height = int(sys.argv[3]) - width = int(sys.argv[4]) - n_boxes = int(sys.argv[5]) - crop_h = int(sys.argv[6]) - crop_w = int(sys.argv[7]) -else: - print( - "Give me 7 arguments. Batch_size, depth, height, width, n_boxes (in total), crop_h, crop_w." - ) - sys.exit(-1) - -# Generate a random batch of feature maps -image_data = np.random.rand(batch_size, depth, height, width).astype(np.float32) - -# Generate random coordinates for the boxes -xs = np.random.uniform(0, width, size=(n_boxes, 2)) -ys = np.random.uniform(0, height, size=(n_boxes, 2)) - -xs /= height - 1 -ys /= width - 1 - -xs.sort(axis=1) -ys.sort(axis=1) - -boxes_data = np.stack((ys[:, 0], xs[:, 0], ys[:, 1], xs[:, 1]), axis=-1).astype( - np.float32 -) - -# Generate box indexes -box_index_data = np.random.randint(0, batch_size, size=n_boxes, dtype=np.int32) - -# Generate mem space for output crops -# Randomize to enhance verification -dims = (n_boxes, depth, crop_h, crop_w) -crops_data = rand_matrix(dims) -crops_data_vec = rand_matrix(dims) - -# Print information on file -print('.section .data,"aw",@progbits') -emit("BATCH_SIZE", np.array(batch_size, dtype=np.uint64)) -emit("DEPTH", np.array(depth, dtype=np.uint64)) -emit("IMAGE_HEIGHT", np.array(height, dtype=np.uint64)) -emit("IMAGE_WIDTH", np.array(width, dtype=np.uint64)) -emit("N_BOXES", np.array(n_boxes, dtype=np.uint64)) -emit("CROP_HEIGHT", np.array(crop_h, dtype=np.uint64)) -emit("CROP_WIDTH", np.array(crop_w, dtype=np.uint64)) -emit("image_data", np.concatenate(image_data), "NR_LANES*4") -emit("boxes_data", boxes_data, "NR_LANES*4") -emit("box_index_data", box_index_data, "NR_LANES*4") -emit("crops_data", np.concatenate(crops_data), "NR_LANES*4") -emit("crops_data_vec", np.concatenate(crops_data_vec), "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/main.c b/bb-tests/workloads/src/CTest/rvv/vec-roi-align/main.c deleted file mode 100644 index 74727413..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/main.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - Original implementation taken from - https://github.com/longcw/RoIAlign.pytorch No license found on the website. - A question about the license was made here - https://github.com/longcw/RoIAlign.pytorch/issues/48 Following the answer to - this question, a correct header will be added also here - Adaptation by: Matteo Perotti, ETH Zurich, -*/ - -#include -#include - -#include "ara/util.h" -#include "roi_align.h" -#include "util.h" -#include - -#define EXTRAPOLATION_VALUE 0 - -extern uint64_t BATCH_SIZE; -extern uint64_t DEPTH; -extern uint64_t IMAGE_HEIGHT; -extern uint64_t IMAGE_WIDTH; -extern uint64_t N_BOXES; -extern uint64_t CROP_HEIGHT; -extern uint64_t CROP_WIDTH; - -extern float image_data[]; -extern float boxes_data[]; -extern int box_index_data[]; -extern float crops_data[]; -extern float crops_data_vec[]; - -// Compare the vector and scalar implementation. -// Return 0 if no error is found -// Return -1 if we have an error on the first element -// A positive return value indicates the index of the faulty element -int verify_result(float *s_crops_data, float *v_crops_data, size_t size, - float delta) { - int ret; - - for (unsigned long int i = 0; i < size; ++i) { - if (!similarity_check_32b(s_crops_data[i], v_crops_data[i], delta)) { - ret = (!i) ? -1 : i; - return ret; - } - } - - return 0; -} - -int main() { - printf("RoI Align\n"); - - int64_t err; - unsigned long cycles1, cycles2, instr2, instr1; - uint64_t runtime_s, runtime_v; - uint64_t result_size = N_BOXES * DEPTH * CROP_HEIGHT * CROP_WIDTH; - - // Parameters - printf("BATCH_SIZE = %ld\nDEPTH = %ld\nIMAGE_HEIGHT = %ld\nIMAGE_WIDTH = " - "%ld\nN_BOXES = %ld\nCROP_HEIGHT = %ld\nCROP_WIDTH = " - "%ld\nEXTRAPOLATION_VALUE = %ld\n", - BATCH_SIZE, DEPTH, IMAGE_HEIGHT, IMAGE_WIDTH, N_BOXES, CROP_HEIGHT, - CROP_WIDTH, EXTRAPOLATION_VALUE); - - // Scalar benchmark - printf("Starting scalar benchmark...\n"); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - CropAndResizePerBox(image_data, BATCH_SIZE, DEPTH, IMAGE_HEIGHT, IMAGE_WIDTH, - boxes_data, box_index_data, 0, N_BOXES, crops_data, - CROP_HEIGHT, CROP_WIDTH, EXTRAPOLATION_VALUE); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - runtime_s = cycles2 - cycles1; - printf("Scalar benchmark complete.\n"); - printf("Cycles: %d\n", runtime_s); - - // Vector benchmark - printf("Starting vector benchmark...\n"); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - CropAndResizePerBox_BCHW_vec(image_data, BATCH_SIZE, DEPTH, IMAGE_HEIGHT, - IMAGE_WIDTH, boxes_data, box_index_data, 0, - N_BOXES, crops_data_vec, CROP_HEIGHT, CROP_WIDTH, - EXTRAPOLATION_VALUE); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - runtime_v = cycles2 - cycles1; - printf("Vector benchmark complete.\n"); - printf("Cycles: %d\n", runtime_v); - printf("Operations: %ld\n", N_BOXES * CROP_WIDTH * CROP_HEIGHT * DEPTH * 6); - printf("Loads: %ld\n", N_BOXES * CROP_WIDTH * CROP_HEIGHT * DEPTH * 4); - printf("Stores: %ld\n", N_BOXES * CROP_WIDTH * CROP_HEIGHT * DEPTH); - - // Check for errors - err = verify_result(crops_data, crops_data_vec, result_size, DELTA); - - if (err != 0) { - // Fix return code to match the index of the faulty element - err = (err == -1) ? 0 : err; - printf("Failed. Index %d: %x != %x\n", err, *((uint32_t *)&crops_data[err]), - *((uint32_t *)&crops_data_vec[err])); - return err; - } else { - printf("Passed.\n"); - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/roi_align.c b/bb-tests/workloads/src/CTest/rvv/vec-roi-align/roi_align.c deleted file mode 100644 index c58099a3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/roi_align.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - Original implementation taken from - https://github.com/longcw/RoIAlign.pytorch No license found on the website. - A question about the license was made here - https://github.com/longcw/RoIAlign.pytorch/issues/48 Following the answer to - this question, a correct header will be added also here - Adaptation by: Matteo Perotti, ETH Zurich, -*/ - -#include "roi_align.h" - -void printf_fx(float num) { printf("%x\n", *((uint32_t *)&num)); } - -int64_t CropAndResizePerBox(const float *image_data, const int batch_size, - const int depth, const int image_height, - const int image_width, - - const float *boxes_data, const int *box_index_data, - const int start_box, const int limit_box, - - float *crops_data, const int crop_height, - const int crop_width, - const float extrapolation_value) { - - const int image_channel_elements = image_height * image_width; - const int image_elements = depth * image_channel_elements; - - const int channel_elements = crop_height * crop_width; - const int crop_elements = depth * channel_elements; - - int b; - // #pragma omp parallel for - - for (b = start_box; b < limit_box; ++b) { - const float *box = boxes_data + b * 4; - const float y1 = box[0]; - const float x1 = box[1]; - const float y2 = box[2]; - const float x2 = box[3]; - - const int b_in = box_index_data[b]; - if (b_in < 0 || b_in >= batch_size) { - printf("Error: batch_index %d out of range [0, %d)\n", b_in, batch_size); - return -1; - } -#ifdef PRINTF - printf("box = %d; y1, x1, y2, x2 --------------------------:\n", b); - printf_fx(y1); - printf_fx(x1); - printf_fx(y2); - printf_fx(y2); -#endif - - const float height_scale = - (crop_height > 1) ? (y2 - y1) * (image_height - 1) / (crop_height - 1) - : 0; - const float width_scale = - (crop_width > 1) ? (x2 - x1) * (image_width - 1) / (crop_width - 1) : 0; - -#ifdef PRINTF - printf("h_scale, w_scale:\n"); - printf_fx(height_scale); - printf_fx(width_scale); -#endif - for (int y = 0; y < crop_height; ++y) { - const float in_y = (crop_height > 1) - ? y1 * (image_height - 1) + y * height_scale - : 0.5 * (y1 + y2) * (image_height - 1); - - if (in_y < 0 || in_y > image_height - 1) { - for (int x = 0; x < crop_width; ++x) { - for (int d = 0; d < depth; ++d) { - // crops(b, y, x, d) = extrapolation_value; - crops_data[crop_elements * b + channel_elements * d + - y * crop_width + x] = extrapolation_value; - } - } - continue; - } - - const int top_y_index = floorf(in_y); - const int bottom_y_index = ceilf(in_y); - const float y_lerp = in_y - top_y_index; - -#ifdef PRINTF - printf("in_y, top_y_idx, bottom_y_idx, y_lerp\n"); - printf_fx(in_y); - printf("%d\n", top_y_index); - printf("%d\n", bottom_y_index); - printf_fx(y_lerp); -#endif - - for (int x = 0; x < crop_width; ++x) { - const float in_x = (crop_width > 1) - ? x1 * (image_width - 1) + x * width_scale - : 0.5 * (x1 + x2) * (image_width - 1); - if (in_x < 0 || in_x > image_width - 1) { - for (int d = 0; d < depth; ++d) { - crops_data[crop_elements * b + channel_elements * d + - y * crop_width + x] = extrapolation_value; - } - continue; - } - const int left_x_index = floorf(in_x); - const int right_x_index = ceilf(in_x); - const float x_lerp = in_x - left_x_index; - -#ifdef PRINTF - printf("in_x, left_x_idx, right_x_idx, x_lerp\n"); - printf_fx(in_x); - printf("%d\n", left_x_index); - printf("%d\n", right_x_index); - printf_fx(x_lerp); -#endif - for (int d = 0; d < depth; ++d) { - const float *pimage = - image_data + b_in * image_elements + d * image_channel_elements; - - const float top_left = - pimage[top_y_index * image_width + left_x_index]; - const float top_right = - pimage[top_y_index * image_width + right_x_index]; - const float bottom_left = - pimage[bottom_y_index * image_width + left_x_index]; - const float bottom_right = - pimage[bottom_y_index * image_width + right_x_index]; - - const float top = top_left + (top_right - top_left) * x_lerp; - const float bottom = - bottom_left + (bottom_right - bottom_left) * x_lerp; - - crops_data[crop_elements * b + channel_elements * d + y * crop_width + - x] = top + (bottom - top) * y_lerp; - } - } // end for x - } // end for y - } // end for b -#ifdef PRINTF - printf("End of the scalar function\n"); -#endif - return 0; -} - -int64_t CropAndResizePerBox_BCHW_vec( - const float *image_data, const int batch_size, const int depth, - const int image_height, const int image_width, - - const float *boxes_data, const int *box_index_data, const int start_box, - const int limit_box, - - float *crops_data, const int crop_height, const int crop_width, - const float extrapolation_value) { - - const int image_channel_elements = image_height * image_width; - const int image_elements = depth * image_channel_elements; - - const int channel_elements = crop_height * crop_width; - const int crop_elements = depth * channel_elements; - - float *prev_pimage; - float *prev_crops_data = crops_data; - - int b; - // #pragma omp parallel for - for (b = start_box; b < limit_box; ++b) { - const float *box = boxes_data + b * 4; - const float y1 = box[0]; - const float x1 = box[1]; - const float y2 = box[2]; - const float x2 = box[3]; - - const int b_in = box_index_data[b]; - if (b_in < 0 || b_in >= batch_size) { - printf("Error: batch_index %d out of range [0, %d)\n", b_in, batch_size); - return -1; - } - const float *pimage = image_data + b_in * image_elements; - const float *prev_pimage = pimage; - - const float height_scale = - (crop_height > 1) ? (y2 - y1) * (image_height - 1) / (crop_height - 1) - : 0; - const float width_scale = - (crop_width > 1) ? (x2 - x1) * (image_width - 1) / (crop_width - 1) : 0; - - for (int y = 0; y < crop_height; ++y) { - const float in_y = (crop_height > 1) - ? y1 * (image_height - 1) + y * height_scale - : 0.5 * (y1 + y2) * (image_height - 1); - - if (in_y < 0 || in_y > image_height - 1) { - for (int x = 0; x < crop_width; ++x) { - for (int d = 0; d < depth; ++d) { - // crops(b, y, x, d) = extrapolation_value; - crops_data[crop_elements * b + channel_elements * d + - y * crop_width + x] = extrapolation_value; - } - } - continue; - } - - const int top_y_index = floorf(in_y); - const int bottom_y_index = ceilf(in_y); - const float y_lerp = in_y - top_y_index; - - for (int x = 0; x < crop_width; ++x) { - const float in_x = (crop_width > 1) - ? x1 * (image_width - 1) + x * width_scale - : 0.5 * (x1 + x2) * (image_width - 1); - if (in_x < 0 || in_x > image_width - 1) { - for (int d = 0; d < depth; ++d) { - crops_data[crop_elements * b + channel_elements * d + - y * crop_width + x] = extrapolation_value; - } - continue; - } - - const int left_x_index = floorf(in_x); - const int right_x_index = ceilf(in_x); - const float x_lerp = in_x - left_x_index; - - // Load the elements that belong to the same channel - vfloat32m1_t top_left, top_right, bottom_left, bottom_right, top, - bottom, result; - ptrdiff_t cstride_pimage = image_channel_elements * sizeof(pimage[0]); - ptrdiff_t cstride_crops = channel_elements * sizeof(crops_data[0]); - size_t avl, vl; - - avl = depth; -#ifdef INTRINSICS - vl = vsetvl_e32m1(avl); - - for (avl = depth; avl > 0; avl -= vl) { - vl = vsetvl_e32m1(avl); - top_left = - vlse32_v_f32m1(&pimage[top_y_index * image_width + left_x_index], - cstride_pimage, vl); - top_right = - vlse32_v_f32m1(&pimage[top_y_index * image_width + right_x_index], - cstride_pimage, vl); - - top = vfsub_vv_f32m1(top_right, top_left, vl); - top = vfmadd_vf_f32m1(top, x_lerp, top_left, vl); - - bottom_left = vlse32_v_f32m1( - &pimage[bottom_y_index * image_width + left_x_index], - cstride_pimage, vl); - bottom_right = vlse32_v_f32m1( - &pimage[bottom_y_index * image_width + right_x_index], - cstride_pimage, vl); - - bottom = vfsub_vv_f32m1(bottom_right, bottom_left, vl); - bottom = vfmadd_vf_f32m1(bottom, x_lerp, bottom_left, vl); - - result = vfsub_vv_f32m1(bottom, top, vl); - result = vfmadd_vf_f32m1(result, y_lerp, top, vl); - - vsse32_v_f32m1(&crops_data[crop_elements * b + y * crop_width + x], - cstride_crops, result, vl); - - // Bump pointers - pimage += vl * image_channel_elements; - crops_data += vl * channel_elements; - } -#else - asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(avl)); - - for (avl = depth; avl > 0; avl -= vl) { - asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(avl)); - asm volatile("vlse32.v v0, (%0), %1" ::"r"( - &pimage[top_y_index * image_width + left_x_index]), - "r"(cstride_pimage) - : "v0"); // top left - asm volatile("vlse32.v v1, (%0), %1" ::"r"( - &pimage[top_y_index * image_width + right_x_index]), - "r"(cstride_pimage) - : "v1"); // top right - - asm volatile("vfsub.vv v2, v1, v0"); // top - asm volatile("vfmadd.vf v2, %0, v0" ::"f"(x_lerp)); // top - - asm volatile( - "vlse32.v v3, (%0), %1" ::"r"( - &pimage[bottom_y_index * image_width + left_x_index]), - "r"(cstride_pimage) - : "v3"); // bottom left - asm volatile( - "vlse32.v v4, (%0), %1" ::"r"( - &pimage[bottom_y_index * image_width + right_x_index]), - "r"(cstride_pimage) - : "v4"); // bottom right - - asm volatile("vfsub.vv v5, v4, v3"); // bottom - asm volatile("vfmadd.vf v5, %0, v3" ::"f"(x_lerp)); // bottom - - asm volatile("vfsub.vv v6, v5, v2"); // bottom - asm volatile("vfmadd.vf v6, %0, v2" ::"f"(y_lerp)); // bottom - - asm volatile("vsse32.v v6, (%0), %1" ::"r"( - &crops_data[crop_elements * b + y * crop_width + x]), - "r"(cstride_crops)); - - // Bump pointers - pimage += vl * image_channel_elements; - crops_data += vl * channel_elements; - } -#endif - pimage = prev_pimage; - - crops_data = prev_crops_data; - } // end for x - } // end for y - } // end for b - return 0; -} - -int64_t CropAndResizePerBox_BHWC_vec( - const float *image_data, const int batch_size, const int depth, - const int image_height, const int image_width, - - const float *boxes_data, const int *box_index_data, const int start_box, - const int limit_box, - - float *crops_data, const int crop_height, const int crop_width, - const float extrapolation_value) { - - const int image_channel_elements = image_height * image_width; - const int image_elements = depth * image_channel_elements; - - const int channel_elements = crop_height * crop_width; - const int crop_elements = depth * channel_elements; - - float *prev_pimage; - float *prev_crops_data = crops_data; - - int b; - // #pragma omp parallel for - for (b = start_box; b < limit_box; ++b) { - const float *box = boxes_data + b * 4; - const float y1 = box[0]; - const float x1 = box[1]; - const float y2 = box[2]; - const float x2 = box[3]; - - const int b_in = box_index_data[b]; - if (b_in < 0 || b_in >= batch_size) { - printf("Error: batch_index %d out of range [0, %d)\n", b_in, batch_size); - return -1; - } - const float *pimage = image_data + b_in * image_elements; - const float *prev_pimage = pimage; - - const float height_scale = - (crop_height > 1) ? (y2 - y1) * (image_height - 1) / (crop_height - 1) - : 0; - const float width_scale = - (crop_width > 1) ? (x2 - x1) * (image_width - 1) / (crop_width - 1) : 0; - - for (int y = 0; y < crop_height; ++y) { - const float in_y = (crop_height > 1) - ? y1 * (image_height - 1) + y * height_scale - : 0.5 * (y1 + y2) * (image_height - 1); - - if (in_y < 0 || in_y > image_height - 1) { - for (int x = 0; x < crop_width; ++x) { - for (int d = 0; d < depth; ++d) { - // crops(b, y, x, d) = extrapolation_value; - crops_data[crop_elements * b + y * crop_width * depth + x * depth + - d] = extrapolation_value; - } - } - continue; - } - - const int top_y_index = floorf(in_y); - const int bottom_y_index = ceilf(in_y); - const float y_lerp = in_y - top_y_index; - - for (int x = 0; x < crop_width; ++x) { - const float in_x = (crop_width > 1) - ? x1 * (image_width - 1) + x * width_scale - : 0.5 * (x1 + x2) * (image_width - 1); - if (in_x < 0 || in_x > image_width - 1) { - for (int d = 0; d < depth; ++d) { - crops_data[crop_elements * b + y * crop_width * depth + x * depth + - d] = extrapolation_value; - } - continue; - } - - const int left_x_index = floorf(in_x); - const int right_x_index = ceilf(in_x); - const float x_lerp = in_x - left_x_index; - - // Load the elements that belong to the same channel - vfloat32m1_t top_left, top_right, bottom_left, bottom_right, top, - bottom, result; - size_t avl, vl; - - avl = depth; - -#ifdef INTRINSICS - vl = vsetvl_e32m1(avl); - - for (avl = depth; avl > 0; avl -= vl) { - vl = vsetvl_e32m1(avl); - top_left = vle32_v_f32m1( - &pimage[depth * (top_y_index * image_width + left_x_index)], vl); - top_right = vle32_v_f32m1( - &pimage[depth * (top_y_index * image_width + right_x_index)], vl); - - top = vfsub_vv_f32m1(top_right, top_left, vl); - top = vfmadd_vf_f32m1(top, x_lerp, top_left, vl); - - bottom_left = vle32_v_f32m1( - &pimage[depth * (bottom_y_index * image_width + left_x_index)], - vl); - bottom_right = vle32_v_f32m1( - &pimage[depth * (bottom_y_index * image_width + right_x_index)], - vl); - - bottom = vfsub_vv_f32m1(bottom_right, bottom_left, vl); - bottom = vfmadd_vf_f32m1(bottom, x_lerp, bottom_left, vl); - - result = vfsub_vv_f32m1(bottom, top, vl); - result = vfmadd_vf_f32m1(result, y_lerp, top, vl); - - vse32_v_f32m1(&crops_data[crop_elements * b + y * crop_width * depth + - x * depth], - result, vl); - - // Bump pointers - pimage += vl; - crops_data += vl; - } -#else - asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(avl)); - - for (avl = depth; avl > 0; avl -= vl) { - asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(avl)); - asm volatile("vle32.v v0, (%0)" ::"r"( - &pimage[top_y_index * image_width + left_x_index]) - : "v0"); // top left - asm volatile("vle32.v v1, (%0)" ::"r"( - &pimage[top_y_index * image_width + right_x_index]) - : "v1"); // top right - - asm volatile("vfsub.vv v2, v1, v0"); // top - asm volatile("vfmadd.vf v2, %0, v0" ::"f"(x_lerp)); // top - - asm volatile("vle32.v v3, (%0)" ::"r"( - &pimage[bottom_y_index * image_width + left_x_index]) - : "v3"); // bottom left - asm volatile( - "vle32.v v4, (%0)" ::"r"( - &pimage[bottom_y_index * image_width + right_x_index]) - : "v4"); // bottom right - - asm volatile("vfsub.vv v5, v4, v3"); // bottom - asm volatile("vfmadd.vf v5, %0, v3" ::"f"(x_lerp)); // bottom - - asm volatile("vfsub.vv v6, v5, v2"); // bottom - asm volatile("vfmadd.vf v6, %0, v2" ::"f"(y_lerp)); // bottom - - asm volatile("vse32.v v6, (%0)" ::"r"( - &crops_data[crop_elements * b + y * crop_width + x])); - - // Bump pointers - pimage += vl * image_channel_elements; - crops_data += vl * channel_elements; - } -#endif - pimage = prev_pimage; - - crops_data = prev_crops_data; - } // end for x - } // end for y - } // end for b - return 0; -} - -// Normalized image -void init_image(float *vec, size_t size) { - for (unsigned long int i = 0; i < size; ++i) - vec[i] = (float)((i + 5) % size) / size; -} - -// Boxes must have meaningful coordinates -void init_boxes(float *vec, size_t size) { - // 4 coordinates per box: y1 x1 y2 x2 - for (unsigned long int i = 0; i < size; i += 4) { - vec[i] = 3; // y1 - vec[i + 1] = 7; // x1 - vec[i + 2] = 35; // y2 - vec[i + 3] = 39; // x2 - } -} - -// Each box can belong to one of the #BATCH_SIZE images -void init_boxes_idx(int *vec, size_t size, uint64_t batch_size) { - for (unsigned long int i = 0; i < size; ++i) - vec[i] = i % batch_size; -} - -// Crops initialized to zero -void init_crops(float *vec, size_t size) { - for (unsigned long int i = 0; i < size; ++i) - vec[i] = 0; -} - -// Roi Align vector kernel -// Fake just for timing measurements and comparison with Ideal Dispatcher -void roi_align_fake_kernel_asm(float *pimage, float *crops_data, - int left_x_index, int right_x_index, int b, - int y, size_t depth) { - - volatile float x_lerp = 0.14135; - volatile float y_lerp = 0.4363; - volatile int image_channel_elements = 64; - volatile int channel_elements = 32; - volatile int crop_elements = 5; - volatile int crop_width = 3; - volatile int tyiw = 9; - volatile int byiw = 7; - volatile int x = 11; - volatile int k = 0; - volatile int z = 0; - - size_t vl; - size_t avl = depth; - - asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(avl)); - - for (avl = depth; avl > 0; avl -= vl) { - asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(avl)); - asm volatile("vle32.v v0, (%0)" ::"r"(&pimage[tyiw + left_x_index]) - : "v0"); // top left - asm volatile("vle32.v v8, (%0)" ::"r"(&pimage[tyiw + right_x_index]) - : "v8"); // top right - - asm volatile("vfsub.vv v12, v8, v0"); // top - asm volatile("vfmadd.vf v12, %0, v0" ::"f"(x_lerp)); // top - - asm volatile("vle32.v v16, (%0)" ::"r"(&pimage[byiw + left_x_index]) - : "v16"); // bottom left - asm volatile("vle32.v v20, (%0)" ::"r"(&pimage[byiw + right_x_index]) - : "v20"); // bottom right - - asm volatile("vfsub.vv v24, v20, v16"); // bottom - asm volatile("vfmadd.vf v24, %0, v16" ::"f"(x_lerp)); // bottom - - asm volatile("vfsub.vv v28, v24, v12"); // bottom - asm volatile("vfmadd.vf v28, %0, v12" ::"f"(y_lerp)); // bottom - - asm volatile("vse32.v v28, (%0)" ::"r"( - &crops_data[crop_elements * b + y * crop_width + x])); - - // Bump pointers - k += vl * image_channel_elements; - z += vl * channel_elements; - } -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/roi_align.h b/bb-tests/workloads/src/CTest/rvv/vec-roi-align/roi_align.h deleted file mode 100644 index 8a843663..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-roi-align/roi_align.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - Original implementation taken from - https://github.com/longcw/RoIAlign.pytorch No license found on the website. - A question about the license was made here - https://github.com/longcw/RoIAlign.pytorch/issues/48 Following the answer to - this question, a correct header will be added also here - Adaptation by: Matteo Perotti, ETH Zurich, -*/ - -#ifndef _ROI_ALIGN_H_ -#define _ROI_ALIGN_H_ - -#include - -#include "util.h" -#include -#include - -#define DELTA 0.0001 - -void printf_fx(float num); - -int64_t CropAndResizePerBox(const float *image_data, const int batch_size, - const int depth, const int image_height, - const int image_width, - - const float *boxes_data, const int *box_index_data, - const int start_box, const int limit_box, - - float *crops_data, const int crop_height, - const int crop_width, - const float extrapolation_value); - -int64_t CropAndResizePerBox_BCHW_vec( - const float *image_data, const int batch_size, const int depth, - const int image_height, const int image_width, - - const float *boxes_data, const int *box_index_data, const int start_box, - const int limit_box, - - float *crops_data, const int crop_height, const int crop_width, - const float extrapolation_value); - -int64_t CropAndResizePerBox_BHWC_vec( - const float *image_data, const int batch_size, const int depth, - const int image_height, const int image_width, - - const float *boxes_data, const int *box_index_data, const int start_box, - const int limit_box, - - float *crops_data, const int crop_height, const int crop_width, - const float extrapolation_value); - -void roi_align_fake_kernel_asm(float *pimage, float *crops_data, - int left_x_index, int right_x_index, int b, - int y, size_t depth); - -// Normalized image -void init_image(float *vec, size_t size); - -// Boxes must have meaningful coordinates -void init_boxes(float *vec, size_t size); - -// Each box can belong to one of the #BATCH_SIZE images -void init_boxes_idx(int *vec, size_t size, uint64_t batch_size); - -// Crops initialized to zero -void init_crops(float *vec, size_t size); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/dataset1.h deleted file mode 100644 index 90d2eca1..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/dataset1.h +++ /dev/null @@ -1,2928 +0,0 @@ -#define KH 3 -#define KW 3 -#define IH 121 -#define IW 121 -#define I_SIZE 14641 -#define OH 119 -#define OW 119 -#define O_SIZE 14161 - -float input_k1[IW] = { - 1.0, - 1.0, - 1.0, -}; -float input_k2[IH] = { - 1.0, - 1.0, - 1.0, -}; -float input_image[I_SIZE] = { - 92.0, 28.0, 120.0, 18.0, 20.0, 12.0, 88.0, 112.0, 56.0, 32.0, 9.0, - 48.0, 216.0, 240.0, 96.0, 4.0, 20.0, 20.0, 4.0, 168.0, 4.0, 28.0, - 22.0, 6.0, 3.0, 64.0, 216.0, 20.0, 48.0, 8.0, 56.0, 208.0, 52.0, - 64.0, 44.0, 176.0, 240.0, 96.0, 24.0, 12.0, 32.0, 464.0, 76.0, 32.0, - 88.0, 32.0, 8.0, 496.0, 4.0, 9.0, 352.0, 4.0, 76.0, 16.0, 20.0, - 12.0, 480.0, 480.0, 208.0, 60.0, 224.0, 96.0, 416.0, 320.0, 24.0, 24.0, - 112.0, 16.0, 15.0, 200.0, 72.0, 3.0, 160.0, 96.0, 24.0, 31.0, 480.0, - 208.0, 52.0, 19.0, 104.0, 448.0, 248.0, 8.0, 42.0, 108.0, 12.0, 4.0, - 38.0, 0.0, 22.0, 288.0, 100.0, 40.0, 15.0, 48.0, 8.0, 16.0, 448.0, - 52.0, 56.0, 27.0, 24.0, 24.0, 84.0, 248.0, 128.0, 16.0, 112.0, 3.0, - 72.0, 12.0, 240.0, 124.0, 200.0, 12.0, 120.0, 104.0, 40.0, 240.0, 32.0, - 192.0, 31.0, 200.0, 336.0, 48.0, 96.0, 14.0, 4.0, 96.0, 112.0, 216.0, - 136.0, 152.0, 9.0, 96.0, 24.0, 50.0, 144.0, 400.0, 25.0, 32.0, 68.0, - 14.0, 48.0, 1.0, 320.0, 46.0, 0.0, 24.0, 92.0, 46.0, 240.0, 28.0, - 224.0, 2.0, 0.0, 88.0, 100.0, 26.0, 20.0, 56.0, 400.0, 48.0, 22.0, - 128.0, 14.0, 64.0, 176.0, 120.0, 168.0, 16.0, 32.0, 128.0, 176.0, 80.0, - 116.0, 4.0, 88.0, 84.0, 304.0, 48.0, 112.0, 464.0, 32.0, 168.0, 192.0, - 56.0, 432.0, 40.0, 16.0, 36.0, 176.0, 112.0, 60.0, 56.0, 14.0, 46.0, - 112.0, 2.0, 48.0, 92.0, 60.0, 76.0, 2.0, 112.0, 30.0, 464.0, 11.0, - 28.0, 20.0, 2.0, 48.0, 240.0, 32.0, 200.0, 20.0, 20.0, 124.0, 24.0, - 128.0, 304.0, 14.0, 288.0, 192.0, 0.0, 304.0, 14.0, 176.0, 28.0, 24.0, - 20.0, 3.0, 14.0, 29.0, 29.0, 368.0, 496.0, 16.0, 32.0, 15.0, 10.0, - 112.0, 54.0, 2.0, 80.0, 26.0, 240.0, 46.0, 232.0, 416.0, 23.0, 40.0, - 72.0, 64.0, 88.0, 12.0, 6.0, 22.0, 184.0, 29.0, 36.0, 256.0, 80.0, - 62.0, 76.0, 96.0, 8.0, 136.0, 224.0, 7.0, 31.0, 0.0, 464.0, 1.0, - 22.0, 76.0, 464.0, 2.0, 50.0, 31.0, 8.0, 32.0, 48.0, 24.0, 60.0, - 13.0, 2.0, 160.0, 16.0, 84.0, 96.0, 80.0, 22.0, 176.0, 72.0, 14.0, - 30.0, 88.0, 92.0, 24.0, 4.0, 72.0, 120.0, 40.0, 29.0, 15.0, 152.0, - 28.0, 240.0, 28.0, 7.0, 32.0, 16.0, 176.0, 6.0, 26.0, 4.0, 36.0, - 112.0, 52.0, 25.0, 136.0, 31.0, 16.0, 480.0, 104.0, 232.0, 28.0, 20.0, - 20.0, 6.0, 8.0, 24.0, 120.0, 13.0, 38.0, 240.0, 208.0, 34.0, 28.0, - 60.0, 112.0, 16.0, 224.0, 54.0, 29.0, 192.0, 9.0, 384.0, 46.0, 54.0, - 208.0, 232.0, 13.0, 80.0, 96.0, 72.0, 0.0, 72.0, 40.0, 80.0, 200.0, - 128.0, 32.0, 72.0, 24.0, 384.0, 62.0, 12.0, 256.0, 200.0, 52.0, 432.0, - 54.0, 116.0, 11.0, 20.0, 56.0, 160.0, 120.0, 80.0, 2.0, 64.0, 96.0, - 128.0, 52.0, 192.0, 24.0, 38.0, 30.0, 76.0, 192.0, 26.0, 384.0, 112.0, - 24.0, 288.0, 240.0, 144.0, 0.0, 24.0, 84.0, 16.0, 2.0, 0.0, 12.0, - 28.0, 32.0, 80.0, 10.0, 16.0, 304.0, 136.0, 40.0, 40.0, 32.0, 13.0, - 18.0, 2.0, 112.0, 10.0, 416.0, 432.0, 0.0, 3.0, 304.0, 0.0, 24.0, - 40.0, 88.0, 64.0, 21.0, 32.0, 64.0, 64.0, 13.0, 120.0, 80.0, 8.0, - 13.0, 248.0, 52.0, 80.0, 18.0, 56.0, 14.0, 17.0, 38.0, 26.0, 64.0, - 80.0, 62.0, 224.0, 432.0, 320.0, 144.0, 48.0, 0.0, 16.0, 232.0, 48.0, - 13.0, 112.0, 232.0, 432.0, 32.0, 32.0, 23.0, 20.0, 42.0, 76.0, 200.0, - 40.0, 13.0, 432.0, 352.0, 6.0, 496.0, 136.0, 20.0, 160.0, 96.0, 72.0, - 16.0, 40.0, 116.0, 15.0, 0.0, 12.0, 60.0, 6.0, 28.0, 84.0, 18.0, - 160.0, 21.0, 20.0, 31.0, 216.0, 20.0, 21.0, 224.0, 64.0, 192.0, 48.0, - 0.0, 128.0, 20.0, 5.0, 44.0, 48.0, 200.0, 0.0, 25.0, 0.0, 176.0, - 22.0, 13.0, 136.0, 22.0, 448.0, 160.0, 104.0, 52.0, 16.0, 11.0, 112.0, - 128.0, 0.0, 64.0, 352.0, 18.0, 208.0, 1.0, 32.0, 28.0, 104.0, 1.0, - 15.0, 64.0, 19.0, 48.0, 40.0, 352.0, 48.0, 224.0, 240.0, 62.0, 26.0, - 64.0, 0.0, 80.0, 80.0, 56.0, 480.0, 416.0, 4.0, 192.0, 24.0, 384.0, - 38.0, 88.0, 32.0, 176.0, 26.0, 144.0, 48.0, 168.0, 8.0, 136.0, 1.0, - 32.0, 64.0, 384.0, 92.0, 8.0, 0.0, 36.0, 68.0, 64.0, 56.0, 8.0, - 25.0, 48.0, 23.0, 2.0, 128.0, 112.0, 240.0, 128.0, 16.0, 60.0, 64.0, - 128.0, 36.0, 29.0, 62.0, 42.0, 88.0, 8.0, 60.0, 4.0, 20.0, 320.0, - 168.0, 16.0, 4.0, 20.0, 16.0, 8.0, 0.0, 32.0, 256.0, 448.0, 38.0, - 92.0, 3.0, 54.0, 62.0, 62.0, 2.0, 40.0, 3.0, 368.0, 160.0, 8.0, - 80.0, 12.0, 400.0, 29.0, 48.0, 480.0, 12.0, 19.0, 16.0, 64.0, 240.0, - 62.0, 288.0, 368.0, 52.0, 22.0, 128.0, 0.0, 15.0, 72.0, 12.0, 6.0, - 8.0, 12.0, 9.0, 25.0, 104.0, 3.0, 36.0, 16.0, 208.0, 54.0, 17.0, - 27.0, 176.0, 384.0, 2.0, 168.0, 38.0, 40.0, 11.0, 50.0, 80.0, 336.0, - 96.0, 2.0, 2.0, 240.0, 4.0, 26.0, 6.0, 160.0, 400.0, 120.0, 72.0, - 9.0, 64.0, 54.0, 40.0, 21.0, 20.0, 120.0, 2.0, 44.0, 18.0, 16.0, - 176.0, 128.0, 30.0, 16.0, 32.0, 96.0, 272.0, 12.0, 26.0, 54.0, 100.0, - 384.0, 144.0, 160.0, 0.0, 56.0, 5.0, 40.0, 5.0, 60.0, 144.0, 48.0, - 11.0, 17.0, 15.0, 52.0, 16.0, 2.0, 352.0, 14.0, 48.0, 184.0, 104.0, - 0.0, 448.0, 72.0, 13.0, 14.0, 1.0, 368.0, 100.0, 28.0, 216.0, 17.0, - 112.0, 36.0, 64.0, 288.0, 104.0, 0.0, 368.0, 16.0, 28.0, 136.0, 17.0, - 14.0, 22.0, 200.0, 16.0, 8.0, 176.0, 0.0, 464.0, 88.0, 176.0, 64.0, - 224.0, 22.0, 192.0, 42.0, 32.0, 3.0, 304.0, 128.0, 72.0, 112.0, 208.0, - 19.0, 16.0, 20.0, 20.0, 29.0, 100.0, 12.0, 448.0, 92.0, 200.0, 30.0, - 0.0, 16.0, 208.0, 32.0, 8.0, 20.0, 72.0, 34.0, 52.0, 26.0, 112.0, - 240.0, 144.0, 17.0, 12.0, 192.0, 40.0, 64.0, 200.0, 96.0, 12.0, 224.0, - 24.0, 304.0, 18.0, 4.0, 144.0, 4.0, 38.0, 2.0, 8.0, 100.0, 7.0, - 24.0, 256.0, 16.0, 8.0, 384.0, 20.0, 52.0, 464.0, 124.0, 24.0, 60.0, - 224.0, 20.0, 14.0, 144.0, 0.0, 10.0, 22.0, 368.0, 64.0, 0.0, 24.0, - 208.0, 26.0, 24.0, 192.0, 416.0, 120.0, 13.0, 2.0, 16.0, 9.0, 352.0, - 27.0, 248.0, 22.0, 160.0, 432.0, 25.0, 50.0, 36.0, 27.0, 224.0, 96.0, - 2.0, 416.0, 64.0, 60.0, 76.0, 92.0, 16.0, 0.0, 88.0, 304.0, 40.0, - 3.0, 108.0, 124.0, 19.0, 56.0, 22.0, 88.0, 44.0, 116.0, 448.0, 38.0, - 72.0, 56.0, 8.0, 44.0, 48.0, 64.0, 100.0, 240.0, 11.0, 48.0, 248.0, - 23.0, 27.0, 14.0, 4.0, 16.0, 64.0, 128.0, 12.0, 30.0, 3.0, 60.0, - 42.0, 352.0, 152.0, 64.0, 124.0, 0.0, 112.0, 34.0, 14.0, 12.0, 8.0, - 40.0, 7.0, 352.0, 272.0, 368.0, 40.0, 120.0, 38.0, 40.0, 4.0, 208.0, - 2.0, 160.0, 32.0, 28.0, 40.0, 42.0, 16.0, 4.0, 15.0, 464.0, 96.0, - 50.0, 4.0, 0.0, 58.0, 22.0, 112.0, 52.0, 64.0, 26.0, 104.0, 400.0, - 26.0, 112.0, 224.0, 152.0, 96.0, 9.0, 72.0, 8.0, 184.0, 29.0, 30.0, - 27.0, 72.0, 100.0, 36.0, 200.0, 48.0, 60.0, 248.0, 112.0, 224.0, 24.0, - 240.0, 26.0, 64.0, 272.0, 16.0, 128.0, 31.0, 54.0, 192.0, 3.0, 40.0, - 136.0, 184.0, 6.0, 44.0, 23.0, 52.0, 56.0, 416.0, 496.0, 50.0, 176.0, - 176.0, 304.0, 96.0, 54.0, 96.0, 80.0, 104.0, 16.0, 0.0, 80.0, 28.0, - 26.0, 30.0, 28.0, 21.0, 224.0, 36.0, 100.0, 336.0, 448.0, 24.0, 40.0, - 0.0, 22.0, 248.0, 26.0, 0.0, 104.0, 464.0, 28.0, 368.0, 184.0, 124.0, - 18.0, 48.0, 54.0, 21.0, 184.0, 20.0, 20.0, 72.0, 336.0, 0.0, 12.0, - 16.0, 2.0, 104.0, 24.0, 40.0, 24.0, 15.0, 26.0, 176.0, 72.0, 160.0, - 56.0, 88.0, 36.0, 20.0, 16.0, 208.0, 20.0, 60.0, 56.0, 3.0, 64.0, - 496.0, 448.0, 2.0, 80.0, 0.0, 4.0, 64.0, 128.0, 176.0, 104.0, 52.0, - 96.0, 72.0, 16.0, 144.0, 31.0, 17.0, 184.0, 128.0, 88.0, 108.0, 0.0, - 32.0, 192.0, 76.0, 14.0, 112.0, 104.0, 26.0, 384.0, 176.0, 12.0, 232.0, - 8.0, 5.0, 208.0, 208.0, 184.0, 12.0, 48.0, 192.0, 304.0, 72.0, 22.0, - 116.0, 4.0, 40.0, 44.0, 54.0, 96.0, 68.0, 19.0, 48.0, 72.0, 52.0, - 28.0, 40.0, 96.0, 16.0, 56.0, 5.0, 80.0, 48.0, 40.0, 152.0, 448.0, - 480.0, 368.0, 19.0, 64.0, 1.0, 10.0, 8.0, 352.0, 336.0, 8.0, 25.0, - 80.0, 23.0, 56.0, 40.0, 14.0, 272.0, 40.0, 80.0, 5.0, 3.0, 12.0, - 5.0, 56.0, 256.0, 176.0, 24.0, 22.0, 8.0, 56.0, 58.0, 14.0, 16.0, - 62.0, 56.0, 10.0, 1.0, 116.0, 16.0, 30.0, 232.0, 44.0, 24.0, 5.0, - 56.0, 192.0, 2.0, 72.0, 2.0, 60.0, 8.0, 7.0, 68.0, 56.0, 0.0, - 12.0, 224.0, 160.0, 224.0, 25.0, 224.0, 5.0, 80.0, 10.0, 20.0, 56.0, - 25.0, 16.0, 432.0, 6.0, 336.0, 368.0, 17.0, 4.0, 112.0, 352.0, 496.0, - 36.0, 16.0, 432.0, 80.0, 116.0, 11.0, 176.0, 15.0, 80.0, 256.0, 144.0, - 0.0, 26.0, 176.0, 62.0, 80.0, 12.0, 336.0, 7.0, 16.0, 120.0, 12.0, - 56.0, 2.0, 352.0, 44.0, 52.0, 72.0, 88.0, 28.0, 96.0, 320.0, 8.0, - 232.0, 0.0, 31.0, 14.0, 368.0, 368.0, 64.0, 20.0, 120.0, 12.0, 62.0, - 232.0, 26.0, 32.0, 24.0, 21.0, 11.0, 80.0, 72.0, 14.0, 48.0, 80.0, - 80.0, 16.0, 56.0, 28.0, 240.0, 16.0, 14.0, 76.0, 92.0, 384.0, 1.0, - 15.0, 48.0, 16.0, 160.0, 9.0, 24.0, 22.0, 240.0, 38.0, 92.0, 72.0, - 112.0, 144.0, 34.0, 6.0, 68.0, 32.0, 144.0, 160.0, 112.0, 84.0, 16.0, - 80.0, 232.0, 10.0, 320.0, 108.0, 16.0, 13.0, 80.0, 60.0, 6.0, 16.0, - 64.0, 224.0, 4.0, 56.0, 20.0, 32.0, 400.0, 40.0, 304.0, 400.0, 2.0, - 116.0, 23.0, 72.0, 54.0, 32.0, 464.0, 0.0, 56.0, 16.0, 232.0, 152.0, - 124.0, 16.0, 72.0, 36.0, 16.0, 56.0, 240.0, 12.0, 18.0, 12.0, 26.0, - 112.0, 21.0, 46.0, 0.0, 30.0, 192.0, 68.0, 168.0, 16.0, 104.0, 25.0, - 17.0, 56.0, 68.0, 32.0, 256.0, 16.0, 36.0, 34.0, 16.0, 12.0, 136.0, - 29.0, 152.0, 48.0, 168.0, 22.0, 24.0, 304.0, 56.0, 28.0, 40.0, 480.0, - 56.0, 336.0, 52.0, 1.0, 64.0, 16.0, 11.0, 208.0, 20.0, 128.0, 38.0, - 152.0, 240.0, 32.0, 240.0, 104.0, 15.0, 8.0, 352.0, 116.0, 36.0, 496.0, - 0.0, 116.0, 496.0, 34.0, 10.0, 44.0, 32.0, 62.0, 60.0, 44.0, 96.0, - 26.0, 21.0, 18.0, 200.0, 40.0, 176.0, 176.0, 18.0, 24.0, 4.0, 16.0, - 12.0, 10.0, 160.0, 448.0, 50.0, 21.0, 64.0, 2.0, 24.0, 26.0, 368.0, - 464.0, 104.0, 128.0, 136.0, 100.0, 38.0, 2.0, 30.0, 112.0, 448.0, 6.0, - 192.0, 25.0, 168.0, 10.0, 224.0, 2.0, 25.0, 88.0, 160.0, 40.0, 0.0, - 12.0, 116.0, 168.0, 0.0, 3.0, 32.0, 72.0, 7.0, 26.0, 96.0, 176.0, - 5.0, 112.0, 120.0, 29.0, 32.0, 200.0, 112.0, 108.0, 16.0, 24.0, 46.0, - 22.0, 2.0, 80.0, 18.0, 144.0, 208.0, 128.0, 216.0, 76.0, 16.0, 32.0, - 0.0, 52.0, 36.0, 3.0, 3.0, 100.0, 0.0, 32.0, 32.0, 6.0, 28.0, - 6.0, 72.0, 144.0, 16.0, 64.0, 0.0, 0.0, 34.0, 6.0, 200.0, 72.0, - 208.0, 10.0, 14.0, 16.0, 256.0, 128.0, 24.0, 80.0, 304.0, 27.0, 18.0, - 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631.0, 569.0, 857.0, 887.0, 507.0, 523.0, 564.0, 673.0, 678.0, - 727.0, 829.0, 604.0, 706.0, 544.0, 490.0, 400.0, 399.0, 724.0, - 619.0, 618.0, 457.0, 447.0, 446.0, 488.0, 607.0, 756.0, 732.0, - 698.0, 685.0, 446.0, 588.0, 619.0, 792.0, 976.0, 1462.0, 1448.0, - 1281.0, 671.0, 590.0, 908.0, 932.0, 1108.0, 962.0, 1082.0, 1065.0, - 856.0, 1068.0, 897.0, 628.0, 354.0, 387.0, 457.0, 331.0, 367.0, - 399.0, 463.0, 831.0, 1065.0, 964.0, 573.0, 368.0, 735.0, 774.0, - 733.0, 525.0, 615.0, 778.0, 667.0, 461.0, 745.0, 809.0, 1035.0, - 1405.0, 1194.0, 1424.0, 764.0, 692.0, 575.0, 883.0, 1111.0, 995.0, - 784.0, 566.0, 907.0, 1202.0, 1302.0, 1338.0, 948.0, 1004.0, 467.0, - 509.0, 722.0, 777.0, 719.0, 1040.0, 1408.0, 1590.0, 1050.0, 870.0, - 676.0, 476.0, 394.0, 520.0, 524.0, 756.0, 832.0, 778.0, 826.0, - 802.0, 885.0, 599.0, 333.0, 406.0, 856.0, 1188.0, 1117.0, 928.0, - 1286.0, 1275.0, 900.0, 620.0, 688.0, 936.0, 577.0, 741.0, 600.0, - 672.0, 761.0, 754.0, 755.0, 490.0, 650.0, 606.0, 534.0, 368.0, - 483.0, 800.0, 740.0, 675.0, 828.0, 825.0, 841.0, 719.0, 864.0, - 796.0, 948.0, 846.0, 1004.0, 447.0, 409.0, 625.0, 1072.0, 1488.0, - 1638.0, 1278.0, 1029.0, 503.0, 469.0, 1082.0, 1066.0, 1269.0, 429.0, - 1065.0, 1098.0, 1426.0, 1184.0, 928.0, 654.0, 418.0, 506.0, 503.0, - 349.0, 481.0, 666.0, 714.0, 997.0, 1188.0, 1127.0, 669.0, 416.0, - 705.0, 769.0, 720.0, 560.0, 691.0, 622.0, 555.0, 593.0, 617.0, - 563.0, 729.0, 937.0, 966.0, 831.0, 623.0, 436.0, 583.0, 1227.0, - 1476.0, 1251.0, 528.0, 310.0, 633.0, 972.0, 918.0, 1056.0, 758.0, - 958.0, 759.0, 833.0, 1309.0, 1063.0, 1257.0, 1155.0, 1506.0, 1724.0, - 1504.0, 1212.0, 796.0, 572.0, 1040.0, 1021.0, 965.0, 773.0, 772.0, - 720.0, 780.0, 772.0, 1044.0, 712.0, 590.0, 426.0, 737.0, 937.0, - 867.0, 820.0, 1135.0, 1217.0, 1023.0, 670.0, 1110.0, 1416.0, 1300.0, - 960.0, 652.0, 585.0, 446.0, 281.0, 307.0, 288.0, 445.0, 430.0, - 336.0, 250.0, 543.0, 784.0, 722.0, 495.0, 816.0, 887.0, 1113.0, - 767.0, 729.0, 459.0, 1107.0, 1110.0, 1244.0, 401.0, 489.0, 697.0, - 1524.0, 2252.0, 2408.0, 1633.0, 976.0, 546.0, 519.0, 705.0, 569.0, - 606.0, 322.0, 805.0, 1006.0, 1269.0, 1406.0, 1338.0, 1093.0, 607.0, - 535.0, 512.0, 424.0, 616.0, 701.0, 733.0, 1178.0, 1468.0, 1453.0, - 722.0, 365.0, 327.0, 446.0, 510.0, 653.0, 984.0, 910.0, 1032.0, - 829.0, 785.0, 706.0, 965.0, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/gendata.py deleted file mode 100755 index 35427826..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/gendata.py +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env python3 - -import numpy as np - -KH = 3 -KW = 3 -IH = 260 -IW = 260 -OH = IH - KH + 1 -OW = IW - KW + 1 - -info = np.finfo(np.float32) -nmant = 5 # Limit precision to avoid rounding errors -maxmant = 1 << nmant -minexp = 0 -maxexp = 5 - - -# Generate floating-point values with exact mantissa and exponent -def randf(n): - return np.ldexp( - np.random.randint(maxmant, size=n), np.random.randint(minexp, maxexp, size=n) - ) - - -inputs = randf((IH, IW)).astype(np.float32) -weights = np.ones((KH, KW), dtype=np.float32) -weights_1 = np.ones(KW, dtype=np.float32) -weights_2 = np.ones(KH, dtype=np.float32) -outputs = np.full((OH, OW), np.float32(0.0)) - -# Convolution -for kh in range(KH): - for kw in range(KW): - outputs += inputs[kh : (kh + OH), kw : (kw + OW)] * weights[kh][kw] - -print( - """#define KH {} -#define KW {} -#define IH {} -#define IW {} -#define I_SIZE {} -#define OH {} -#define OW {} -#define O_SIZE {} - -""".format( - KH, KW, IH, IW, IH * IW, OH, OW, OH * OW - ) -) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=10): - print("{} {}[{}] = {{".format(data_type, name, data_size)) - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print_array("input_k1", weights_1, "IW") -print_array("input_k2", weights_2, "IH") -print_array("input_image", inputs.flatten(), "I_SIZE") -print_array("verify_data", outputs.flatten(), "O_SIZE") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/vec-sep-conv.S b/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/vec-sep-conv.S deleted file mode 100644 index 0d4f874d..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/vec-sep-conv.S +++ /dev/null @@ -1,205 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vectorized 2D separable convolution -//-------------------------------------------------------------------------- - - .text - .balign 4 - - .global vec_sep_conv -/* - * Calling convention: - * a0: size_t rows - * a1: size_t cols - * a2: size_t a_stride - * a3: size_t b_stride - * a4: const float *kw - * a5: const float *kh - * a6: const float *a - * a7: float *b - */ - -#define rows a0 -#define cols a1 -#define a_stride a2 -#define b_stride a3 -#define kw a4 -#define kh a5 -#define a a6 -#define b a7 - -#define ap t0 -#define bp t1 -#define vlen t2 -#define row_count t3 -#define VLEN_stride t4 -#define ap_4 t5 -#define ap_8 t6 - -#define row_check s0 -#define rows_odd s1 - -#define kw0 ft0 -#define kw1 ft1 -#define kw2 ft2 -#define kh0 ft3 -#define kh1 ft4 -#define kh2 ft5 - -#define vload0 v0 -#define vload1 v4 -#define vload2 v8 -#define vrow0 v16 -#define vrow1 v20 -#define vtmp v24 - -#define FRAMESIZE 32 - -vec_sep_conv: - addi sp, sp, -FRAMESIZE - sd s0, 0(sp) - sd s1, 8(sp) - - # load the kernel into scalar registers - flw kw0, 0(kw) - flw kw1, 4(kw) - flw kw2, 8(kw) - flw kh0, 0(kh) - flw kh1, 4(kh) - flw kh2, 8(kh) - - slli a_stride, a_stride, 2 - slli b_stride, b_stride, 2 - - mv row_check, rows - addi row_check, row_check, -2 - - andi rows_odd, rows, 1 - -# Prolog -loop_prolog: - mv ap, a - addi ap_4, ap, 4 - addi ap_8, ap, 8 - mv bp, b - mv row_count, row_check - - vsetvli vlen, cols, e32, m4, ta, ma - slli VLEN_stride, vlen, 2 - - # Load the first row and compute horizontal - vle32.v vload0, (ap) - vfmul.vf vrow0, vload0, kw0 - vle32.v vload1, (ap_4) - vfmacc.vf vrow0, kw1, vload1 - vle32.v vload2, (ap_8) - vfmacc.vf vrow0, kw2, vload2 - - add ap, ap, a_stride - addi ap_4, ap, 4 - addi ap_8, ap, 8 - - # Load the second row and compute horizontal - vle32.v vload0, (ap) - vfmul.vf vrow1, vload0, kw0 - vle32.v vload1, (ap_4) - vfmacc.vf vrow1, kw1, vload1 - vle32.v vload2, (ap_8) - vfmacc.vf vrow1, kw2, vload2 - - add ap, ap, a_stride - addi ap_4, ap, 4 - addi ap_8, ap, 8 - - # Begin the vertical computation with the first and second rows - vfmul.vf vrow0, vrow0, kh0 - vfmacc.vf vrow0, kh1, vrow1 - vfmul.vf vrow1, vrow1, kh0 - - # Load the third row and compute horizontal - vle32.v vload0, (ap) - vfmul.vf vtmp, vload0, kw0 - vle32.v vload1, (ap_4) - vfmacc.vf vtmp, kw1, vload1 - vle32.v vload2, (ap_8) - vfmacc.vf vtmp, kw2, vload2 - -# Main Loop -conv_loop: - - add ap, ap, a_stride - addi ap_4, ap, 4 - addi ap_8, ap, 8 - - vle32.v vload0, (ap) - vfmacc.vf vrow0, kh2, vtmp - vle32.v vload1, (ap_4) - vse32.v vrow0, (bp) - vle32.v vload2, (ap_8) - - vfmacc.vf vrow1, kh1, vtmp - vfmul.vf vrow0, vtmp, kh0 - - add ap, ap, a_stride - vfmul.vf vtmp, vload0, kw0 - addi ap_4, ap, 4 - vle32.v vload0, (ap) - vfmacc.vf vtmp, kw1, vload1 - addi ap_8, ap, 8 - vle32.v vload1, (ap_4) - vfmacc.vf vtmp, kw2, vload2 - vle32.v vload2, (ap_8) - add bp, bp, b_stride - - vfmacc.vf vrow1, kh2, vtmp - vfmacc.vf vrow0, kh1, vtmp - vse32.v vrow1, (bp) - vfmul.vf vrow1, vtmp, kh0 - - vfmul.vf vtmp, vload0, kw0 - add bp, bp, b_stride - vfmacc.vf vtmp, kw1, vload1 - addi row_count, row_count, -2 - vfmacc.vf vtmp, kw2, vload2 - - - bgtz row_count, conv_loop - -epilog: - vfmacc.vf vrow0, kh2, vtmp - vse32.v vrow0, (bp) - - bnez rows_odd, row_loop_complete - - vfmacc.vf vrow1, kh1, vtmp - - add ap, ap, a_stride - addi ap_4, ap, 4 - addi ap_8, ap, 8 - add bp, bp, b_stride - - vle32.v vload0, (ap) - vle32.v vload1, (ap_4) - vle32.v vload2, (ap_8) - - vfmul.vf vtmp, vload0, kw0 - vfmacc.vf vtmp, kw1, vload1 - vfmacc.vf vtmp, kw2, vload2 - - vfmacc.vf vrow1, kh2, vtmp - vse32.v vrow1, (bp) - -row_loop_complete: - add a, a, VLEN_stride - add b, b, VLEN_stride - - sub cols, cols, vlen - bnez cols, loop_prolog - -exit: - ld s0, 0(sp) - ld s1, 8(sp) - addi sp, sp, FRAMESIZE - - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/vec-sep-conv_main.c b/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/vec-sep-conv_main.c deleted file mode 100644 index 8b3ea262..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sep-conv-3/vec-sep-conv_main.c +++ /dev/null @@ -1,42 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Separable Convolution Benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized 2D separable convolution implementation. - -#include "util.h" -#include -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_sep_conv(size_t, size_t, size_t, size_t, const float *, const float *, - const float *, float *); - -int main(int argc, char *argv[]) { - float results_data[O_SIZE] = {0}; - printf("2dsepconv (OH,OW,KH,KW,IH,IW) = (%ld, %ld, %ld, %ld, %ld, %ld)\n", OH, - OW, KH, KW, IH, IW); - printf("operations = %ld\n", (IW - KW + 1) * (IH - KH + 1) * (KW + KH)); -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_sep_conv(OH, OW, IW, OW, input_k1, input_k2, input_image, results_data); - memset(results_data, 0, sizeof(results_data)); -#endif - - // Do the convolution - setStats(1); - vec_sep_conv(OH, OW, IW, OW, input_k1, input_k2, input_image, results_data); - setStats(0); - - // Check the results - return verifyFloat(O_SIZE, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/dataset1.h deleted file mode 100644 index 39867b05..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/dataset1.h +++ /dev/null @@ -1,28 +0,0 @@ -#define M_DIM 6 -#define K_DIM 6 -#define N_DIM 6 - -typedef float data_t; - -static data_t a_matrix[M_DIM * K_DIM] = { - -9.0, -144.0, 8.0, 168.0, 96.0, -144.0, 52.0, -32.0, 160.0, - -6.0, -0.90625, 0.625, 3.25, 13.0, 0.0, 9.5, 104.0, -288.0, - -480.0, 480.0, -24.0, -48.0, -5.75, 40.0, -24.0, 2.875, 0.90625, - 2.0, -0.5625, -1.0, -2.625, -54.0, 176.0, -32.0, -15.5, 208.0, -}; -static data_t b_matrix[K_DIM * N_DIM] = { - -2.625, 0.75, 0.5, -432.0, 400.0, -3.75, 25.0, 29.0, -2.75, - 1.0, 368.0, -2.5, -8.0, 11.0, -2.25, 256.0, -13.0, -0.84375, - -8.0, 2.0, 0.71875, 168.0, 2.0, 64.0, 16.0, -1.375, -1.625, - -3.0, 7.0, 10.0, -0.375, 0.25, -6.0, -3.5, -4.0, 0.4375, -}; -static data_t verify_data[M_DIM * N_DIM] = { - -3394.375, -3926.75, 1202.25, 34232.0, -55112.0, - 12036.0, -2183.234375, 860.40234375, -252.58984375, 17456.53125, - 6923.15625, -642.7890625, 2012.46875, 183.4375, 1531.703125, - 901.0, 7983.0, 1477.3125, 13729.0, 13217.90625, - -1771.15625, 193509.25, -15344.25, -2491.75, 103.0, - 79.8671875, -13.59375, 10944.0625, -8549.71875, 203.9853515625, - -2821.109375, 377.34375, -1494.625, 40078.5, -24214.5, - -2115.65625, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/gendata.py deleted file mode 120000 index ecf1d19c..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/gendata.py +++ /dev/null @@ -1 +0,0 @@ -../vec-sgemm/gendata.py \ No newline at end of file diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/vec-sgemm.S b/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/vec-sgemm.S deleted file mode 100644 index c4270edb..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/vec-sgemm.S +++ /dev/null @@ -1,317 +0,0 @@ - .text - .balign 4 - .global vec_sgemm_nn - .type vec_sgemm_nn,@function -# -# void -# vec_sgemm_nn(size_t n, -# size_t m, -# size_t k, -# const float*a, // m * k matrix -# size_t lda, -# const float*b, // k * n matrix -# size_t ldb, -# float*c, // m * n matrix -# size_t ldc) -# -# c += a*b (alpha=1, no transpose on input matrices) -# matrices stored in C row-major order - - - -# With LMUL=4, load 4 rows of C and 4 rows of B -# Load 16 scalars from A into FP registers - -#define n a0 -#define m a1 -#define k a2 -#define ap a3 -#define astride a4 -#define bp a5 -#define bstride a6 -#define cp a7 -#define cstride t0 -#define kt t1 -#define nt t2 -#define bnp t3 -#define cnp t4 -#define akp t5 -#define bkp s0 -#define nvl s1 -#define ccp s2 -#define amp s3 - -#define a00 ft0 -#define a10 ft1 -#define a20 ft2 -#define a30 ft3 -#define a01 ft4 -#define a11 ft5 -#define a21 ft6 -#define a31 ft7 -#define a02 fa0 -#define a12 fa1 -#define a22 fa2 -#define a32 fa3 -#define a03 fa4 -#define a13 fa5 -#define a23 fa6 -#define a33 fa7 - -#define FRAMESIZE 32 - -vec_sgemm_nn: - ld cstride, 0(sp) # Get arg from stack frame - addi sp, sp, -FRAMESIZE - sd s0, 0(sp) - sd s1, 8(sp) - sd s2, 16(sp) - sd s3, 24(sp) - - # Check for zero size matrices - beqz n, exit - beqz m, exit - beqz k, exit - - # Convert elements strides to byte strides. - slli astride, astride, 2 - slli bstride, bstride, 2 - slli cstride, cstride, 2 - - slti t6, m, 4 - bnez t6, m_remainder_m_loop - -c_row_loop: # Loop across rows of C blocks - mv nt, n # Initialize n counter for next row of C blocks - mv bnp, bp # Initialize B n-loop pointer to start - mv cnp, cp # Initialize C n-loop pointer - -c_col_loop: # Loop across columns of C - vsetvli nvl, nt, e32, m4, ta, ma # 32-bit vectors, LMUL=4 - - # Not enough remaining k elements to unroll by 4 - mv kt, k # Initialize inner loop counter - slti t6, kt, 4 - bnez t6, k_loop_remainder - - mv akp, ap # reset pointer into A to beginning - mv bkp, bnp # step to next column in B matrix - - # Initalize current C submatrix block from memory. - vle32.v v0, (cnp); add ccp, cnp, cstride; - flw a00, (akp); add amp, akp, astride; - flw a10, (amp); add amp, amp, astride; - vle32.v v4, (ccp); add ccp, ccp, cstride; - flw a20, (amp); add amp, amp, astride; - flw a30, (amp); add akp, akp, 4 - vle32.v v8, (ccp); add ccp, ccp, cstride; - flw a01, (akp); add amp, akp, astride; - flw a11, (amp); add amp, amp, astride; - vle32.v v12, (ccp); - flw a21, (amp); add amp, amp, astride; - flw a31, (amp); add akp, akp, 4 - - # Get vector from B matrix - vle32.v v16, (bkp); add bkp, bkp, bstride - flw a02, (akp); add amp, akp, astride; - flw a12, (amp); add amp, amp, astride; - vle32.v v20, (bkp); add bkp, bkp, bstride - flw a22, (amp); add amp, amp, astride; - flw a32, (amp); add akp, akp, 4 - vle32.v v24, (bkp); add bkp, bkp, bstride - flw a03, (akp); add amp, akp, astride; - flw a13, (amp); add amp, amp, astride; - vle32.v v28, (bkp); add bkp, bkp, bstride - flw a23, (amp); add amp, amp, astride; - flw a33, (amp); add akp, akp, 4 - - addi kt, kt, -4 - -k_loop: - # Compute current block of FMAs - vfmacc.vf v0, a00, v16 - vfmacc.vf v0, a01, v20 - vfmacc.vf v0, a02, v24 - vfmacc.vf v0, a03, v28 - - vfmacc.vf v4, a10, v16 - vfmacc.vf v4, a11, v20 - vfmacc.vf v4, a12, v24 - vfmacc.vf v4, a13, v28 - - vfmacc.vf v8, a20, v16 - vfmacc.vf v8, a21, v20 - vfmacc.vf v8, a22, v24 - vfmacc.vf v8, a23, v28 - - vfmacc.vf v12, a30, v16 - vfmacc.vf v12, a31, v20 - vfmacc.vf v12, a32, v24 - vfmacc.vf v12, a33, v28 - - addi kt, kt, -4 - blez kt, k_loop_remainder - - # Load values from A for the next iteration - flw a00, (akp); add amp, akp, astride; - flw a10, (amp); add amp, amp, astride; - flw a20, (amp); add amp, amp, astride; - flw a30, (amp); add akp, akp, 4 - flw a01, (akp); add amp, akp, astride; - flw a11, (amp); add amp, amp, astride; - flw a21, (amp); add amp, amp, astride; - flw a31, (amp); add akp, akp, 4 - flw a02, (akp); add amp, akp, astride; - flw a12, (amp); add amp, amp, astride; - flw a22, (amp); add amp, amp, astride; - flw a32, (amp); add akp, akp, 4 - flw a03, (akp); add amp, akp, astride; - flw a13, (amp); add amp, amp, astride; - flw a23, (amp); add amp, amp, astride; - flw a33, (amp); add akp, akp, 4 - - vle32.v v16, (bkp); add bkp, bkp, bstride - vle32.v v20, (bkp); add bkp, bkp, bstride - vle32.v v24, (bkp); add bkp, bkp, bstride - vle32.v v28, (bkp); add bkp, bkp, bstride - - j k_loop - -k_loop_remainder: - beqz kt, 1f - addi kt, kt, 4 - -k_loop_remainder_loop: - # Proceed at one k element per loop - addi kt, kt, -1 - vle32.v v16, (bkp) - flw a00, (akp); add amp, akp, astride; - flw a10, (amp); add amp, amp, astride; - flw a20, (amp); add amp, amp, astride; - flw a30, (amp) - - vfmacc.vf v0, a00, v16 - vfmacc.vf v4, a10, v16 - vfmacc.vf v8, a20, v16 - vfmacc.vf v12, a30, v16 - - addi akp, akp, 4 - add bkp, bkp, bstride - - bnez kt, k_loop_remainder_loop - -1: vse32.v v0, (cnp); add ccp, cnp, cstride; - vse32.v v4, (ccp); add ccp, ccp, cstride; - vse32.v v8, (ccp); add ccp, ccp, cstride; - vse32.v v12, (ccp) - - slli t6, nvl, 2 - add cnp, cnp, t6 - add bnp, bnp, t6 - sub nt, nt, nvl # Decrement element count in n dimension - bnez nt, c_col_loop - - # Move to the next set of rows - addi m, m, -4 - - slli t6, astride, 2 # Multiply astride by 4 - add ap, ap, t6 # Move A matrix pointer down 4 rows - slli t6, cstride, 2 # Multiply cstride by 4 - add cp, cp, t6 # Move C matrix pointer down 4 rows - - slti t6, m, 4 - beqz t6, c_row_loop - - beqz m, exit - -m_remainder_m_loop: - mv cnp, cp - mv bnp, bp - mv nt, n - -m_remainder_n_loop: - vsetvli nvl, nt, e32, m4, ta, ma # 32-bit vectors, LMUL=4 - - # Not enough remaining k elements to unroll by 4 - mv kt, k # Initialize inner loop counter - slti t6, kt, 4 - bnez t6, m_remainder_k_loop_remainder - - mv akp, ap # reset pointer into A to beginning - mv bkp, bnp # step to next column in B matrix - - vle32.v v0, (cnp) - - # Get vectors from B matrix - vle32.v v16, (bkp); add bkp, bkp, bstride - vle32.v v20, (bkp); add bkp, bkp, bstride - vle32.v v24, (bkp); add bkp, bkp, bstride - vle32.v v28, (bkp); add bkp, bkp, bstride - - # Inner loop scheduled assuming 4-clock occupancy of vfmacc instruction and single-issue pipeline - # Software pipeline loads - flw a00, (akp); addi akp, akp, 4 - flw a01, (akp); addi akp, akp, 4 - flw a02, (akp); addi akp, akp, 4 - flw a03, (akp); addi akp, akp, 4 - - addi kt, kt, -4 - -m_remainder_k_loop: - vfmacc.vf v0, a00, v16 - vfmacc.vf v0, a01, v20 - vfmacc.vf v0, a02, v24 - vfmacc.vf v0, a03, v28 - - addi kt, kt, -4 - blez kt, m_remainder_k_loop_remainder - - flw a00, (akp); addi akp, akp, 4 - flw a01, (akp); addi akp, akp, 4 - flw a02, (akp); addi akp, akp, 4 - flw a03, (akp); addi akp, akp, 4 - - vle32.v v16, (bkp); add bkp, bkp, bstride - vle32.v v20, (bkp); add bkp, bkp, bstride - vle32.v v24, (bkp); add bkp, bkp, bstride - vle32.v v28, (bkp); add bkp, bkp, bstride - - j m_remainder_k_loop - -m_remainder_k_loop_remainder: - addi kt, kt, 4 - beqz kt, 1f - -m_remainder_k_loop_remainder_loop: - addi kt, kt, -1 - vle32.v v16, (bkp) - flw a00, (akp) - - vfmacc.vf v0, a00, v16 - - addi akp, akp, 4 - add bkp, bkp, bstride - - bnez kt, m_remainder_k_loop_remainder_loop - -1: vse32.v v0, (cnp) - - slli t6, nvl, 2 - add cnp, cnp, t6 - add bnp, bnp, t6 - sub nt, nt, nvl - bnez nt, m_remainder_n_loop - - addi m, m, -1 - add ap, ap, astride - add cp, cp, cstride - - bnez m, m_remainder_m_loop - -exit: - ld s0, 0(sp) - ld s1, 8(sp) - ld s2, 16(sp) - ld s3, 24(sp) - addi sp, sp, FRAMESIZE - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/vec-sgemm_main.c b/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/vec-sgemm_main.c deleted file mode 100644 index e9a81ecc..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v2/vec-sgemm_main.c +++ /dev/null @@ -1,43 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// SGEMM benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized sgemm implementation. - -#include "util.h" -#include -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_sgemm_nn(size_t, size_t, size_t, const float *, size_t, const float *, - size_t, float *, size_t); - -int main(int argc, char *argv[]) { - float results_data[M_DIM * N_DIM] = {0}; - printf("sgemm M,N,K = %ld,%ld,%ld\n", M_DIM, N_DIM, K_DIM); - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_sgemm_nn(N_DIM, M_DIM, K_DIM, a_matrix, K_DIM, b_matrix, N_DIM, - results_data, N_DIM); - memset(results_data, 0, sizeof(results_data)); -#endif - - // Do the sgemm - setStats(1); - vec_sgemm_nn(N_DIM, M_DIM, K_DIM, a_matrix, K_DIM, b_matrix, N_DIM, - results_data, N_DIM); - setStats(0); - - // Check the results - return verifyFloat(M_DIM * N_DIM, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v3/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v3/dataset1.h deleted file mode 100644 index 37351254..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v3/dataset1.h +++ /dev/null @@ -1,4429 +0,0 @@ -#define M_DIM 87 -#define K_DIM 87 -#define N_DIM 87 - -typedef float data_t; - -static data_t a_matrix[M_DIM * K_DIM] = { - 48.0, 1.0, 0.75, 1.125, -12.0, 4.0, -0.75, 48.0, - -16.0, 40.0, -4.0, 4.0, 0.0, -18.0, 12.0, 1.75, - -7.0, 0.9375, -1.0, -0.75, 0.25, 60.0, 24.0, 0.4375, - 8.0, 0.625, -2.5, 30.0, 6.5, 9.0, -12.0, -2.0, - -9.0, 80.0, -5.0, -24.0, -28.0, 56.0, 3.5, -0.625, - 4.0, -1.625, -32.0, 56.0, 0.125, 2.0, 0.1875, 16.0, - -36.0, -6.0, 0.0625, -40.0, -10.0, 7.0, -40.0, 12.0, - 5.0, 4.0, 48.0, -1.25, -64.0, 0.75, -28.0, 1.5, - -0.375, 3.25, 0.6875, 2.75, 120.0, -3.25, 2.0, 120.0, - -5.0, 72.0, 14.0, 15.0, 0.5, 3.75, -0.375, 11.0, - 0.25, 22.0, -0.25, 0.8125, 1.0, 0.75, -0.1875, -11.0, - 72.0, -0.5, -2.0, 0.75, -7.0, -104.0, -1.5, 12.0, - -3.5, 24.0, -3.75, 7.5, -16.0, 2.0, 3.0, 24.0, - 0.5, 40.0, -1.0, 0.0, 8.0, -10.0, 9.0, -8.0, - -56.0, 2.25, 2.0, -28.0, 0.125, 1.75, -0.25, 0.375, - 1.125, 10.0, -7.0, 24.0, -30.0, 1.0, -0.125, 104.0, - 16.0, 2.5, 24.0, -12.0, 1.125, 15.0, -0.625, 0.0, - -5.0, -5.0, -44.0, 48.0, 112.0, -1.125, 3.5, -104.0, - -1.25, 18.0, 3.5, 1.875, -32.0, 96.0, 0.75, 4.0, - 8.0, -1.0, 112.0, -6.0, 6.5, -1.5, 9.0, 12.0, - -8.0, 14.0, -4.5, -104.0, 11.0, 48.0, -22.0, -72.0, - 2.5, -1.25, 24.0, 1.0, -5.5, -56.0, 12.0, 6.5, - 12.0, -1.0, 0.4375, 0.0, -3.75, 48.0, -0.75, -1.25, - -0.1875, 48.0, 1.5, -14.0, -2.0, -32.0, -0.1875, 1.5, - 0.125, -52.0, -8.0, 40.0, -2.0, -16.0, -3.5, -28.0, - -1.25, -5.0, -112.0, 104.0, -0.5, -0.9375, 0.5, 60.0, - 6.0, 18.0, -7.0, -24.0, 1.5, -15.0, -24.0, -6.0, - -0.25, -2.0, 0.0, -22.0, 6.0, 3.5, 14.0, 7.0, - 2.0, 0.375, -80.0, 5.5, -1.75, 24.0, 10.0, -36.0, - -8.0, 104.0, -15.0, 0.9375, 64.0, 6.0, 0.0625, 1.0, - -48.0, 48.0, 30.0, -1.0, -3.5, -64.0, 6.0, -0.875, - 0.875, 8.0, -8.0, 5.0, 12.0, -80.0, 1.0, 2.0, - -0.5, 40.0, 0.0625, 0.625, -64.0, -24.0, -1.0, -4.0, - -0.25, -4.5, 22.0, 0.375, -2.0, 1.75, 0.75, 0.125, - 1.5, -3.0, -30.0, 5.0, -9.0, -3.0, -1.0, 0.25, - -0.0625, -0.3125, -2.0, 16.0, -0.5, -0.875, -0.4375, -1.75, - 1.0, -0.8125, 26.0, 20.0, -4.5, -48.0, 1.375, -1.5, - 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.text - .balign 4 - .global vec_sgemm_nn - .type vec_sgemm_nn,@function -# -# void -# vec_sgemm_nn(size_t n, -# size_t m, -# size_t k, -# const float*a, // m * k matrix -# size_t lda, -# const float*b, // k * n matrix -# size_t ldb, -# float*c, // m * n matrix -# size_t ldc) -# -# c += a*b (alpha=1, no transpose on input matrices) -# matrices stored in C row-major order - -# With LMUL=4, load 4 rows of C and 4 rows of B -# Load 16 scalars from A into FP registers - -#define n a0 -#define m a1 -#define k a2 -#define ap a3 -#define astride a4 -#define bp a5 -#define bstride a6 -#define cp a7 -#define cstride t0 -#define kt t1 -#define nt t2 -#define bnp t3 -#define cnp t4 -#define akp t5 -#define bkp s0 -#define nvl s1 -#define ccp s2 -#define amp s3 - -#define a00 ft0 -#define a10 ft1 -#define a20 ft2 -#define a30 ft3 -#define a01 ft4 -#define a11 ft5 -#define a21 ft6 -#define a31 ft7 -#define a02 fa0 -#define a12 fa1 -#define a22 fa2 -#define a32 fa3 -#define a03 fa4 -#define a13 fa5 -#define a23 fa6 -#define a33 fa7 - -#define FRAMESIZE 32 - -vec_sgemm_nn: - ld cstride, 0(sp) # Get arg from stack frame - addi sp, sp, -FRAMESIZE - sd s0, 0(sp) - sd s1, 8(sp) - sd s2, 16(sp) - sd s3, 24(sp) - - # Check for zero size matrices - beqz n, exit - beqz m, exit - beqz k, exit - - # Convert elements strides to byte strides. - slli astride, astride, 2 - slli bstride, bstride, 2 - slli cstride, cstride, 2 - - slti t6, m, 4 - bnez t6, m_remainder_m_loop - -c_row_loop: # Loop across rows of C blocks - mv nt, n # Initialize n counter for next row of C blocks - mv bnp, bp # Initialize B n-loop pointer to start - mv cnp, cp # Initialize C n-loop pointer - -c_col_loop: # Loop across columns of C - vsetvli nvl, nt, e32, m4, ta, ma # 32-bit vectors, LMUL=4 - - # Not enough remaining k elements to unroll by 4 - mv kt, k # Initialize inner loop counter - slti t6, kt, 4 - bnez t6, k_loop_remainder - - mv akp, ap # reset pointer into A to beginning - mv bkp, bnp # step to next column in B matrix - - # Initalize current C submatrix block from memory. - vle32.v v0, (cnp); add ccp, cnp, cstride; - flw a00, (akp); add amp, akp, astride; - flw a10, (amp); add amp, amp, astride; - vle32.v v4, (ccp); add ccp, ccp, cstride; - flw a20, (amp); add amp, amp, astride; - flw a30, (amp); addi akp, akp, 4 - vle32.v v8, (ccp); add ccp, ccp, cstride; - flw a01, (akp); add amp, akp, astride; - flw a11, (amp); add amp, amp, astride; - vle32.v v12, (ccp); - flw a21, (amp); add amp, amp, astride; - flw a31, (amp); addi akp, akp, 4 - - # Get vector from B matrix - vle32.v v16, (bkp); add bkp, bkp, bstride - flw a02, (akp); add amp, akp, astride; - flw a12, (amp); add amp, amp, astride; - vle32.v v20, (bkp); add bkp, bkp, bstride - flw a22, (amp); add amp, amp, astride; - flw a32, (amp); addi akp, akp, 4 - vle32.v v24, (bkp); add bkp, bkp, bstride - flw a03, (akp); add amp, akp, astride; - flw a13, (amp); add amp, amp, astride; - vle32.v v28, (bkp); add bkp, bkp, bstride - flw a23, (amp); add amp, amp, astride; - flw a33, (amp); addi akp, akp, 4 - - # Inner loop scheduled assuming 4-clock occupancy of vfmacc instruction and single-issue pipeline - # Software pipeline loads - - addi kt, kt, -4 - -k_loop: - - slti t6, kt, 4 - bnez t6, k_loop_remainder - - # Compute current block of FMAs - vfmacc.vf v0, a00, v16 - flw a00, (akp); add amp, akp, astride; - vfmacc.vf v4, a10, v16 - flw a10, (amp); add amp, amp, astride; - vfmacc.vf v8, a20, v16 - flw a20, (amp); add amp, amp, astride; - vfmacc.vf v12, a30, v16 - flw a30, (amp); add akp, akp, 4 - vle32.v v16, (bkp); add bkp, bkp, bstride - - vfmacc.vf v0, a01, v20 - flw a01, (akp); add amp, akp, astride; - vfmacc.vf v4, a11, v20 - flw a11, (amp); add amp, amp, astride; - vfmacc.vf v8, a21, v20 - flw a21, (amp); add amp, amp, astride; - vfmacc.vf v12, a31, v20 - flw a31, (amp); add akp, akp, 4 - vle32.v v20, (bkp); add bkp, bkp, bstride - - vfmacc.vf v0, a02, v24 - flw a02, (akp); add amp, akp, astride; - vfmacc.vf v4, a12, v24 - flw a12, (amp); add amp, amp, astride; - vfmacc.vf v8, a22, v24 - flw a22, (amp); add amp, amp, astride; - vfmacc.vf v12, a32, v24 - flw a32, (amp); add akp, akp, 4 - vle32.v v24, (bkp); add bkp, bkp, bstride - - vfmacc.vf v0, a03, v28 - flw a03, (akp); add amp, akp, astride; - vfmacc.vf v4, a13, v28 - flw a13, (amp); add amp, amp, astride; - vfmacc.vf v8, a23, v28 - flw a23, (amp); add amp, amp, astride; - vfmacc.vf v12, a33, v28 - flw a33, (amp); add akp, akp, 4 - vle32.v v28, (bkp); add bkp, bkp, bstride - - addi kt, kt, -4 - - j k_loop - -k_loop_remainder: - vfmacc.vf v0, a00, v16 - vfmacc.vf v4, a10, v16 - vfmacc.vf v8, a20, v16 - vfmacc.vf v12, a30, v16 - vfmacc.vf v0, a01, v20 - vfmacc.vf v4, a11, v20 - vfmacc.vf v8, a21, v20 - vfmacc.vf v12, a31, v20 - vfmacc.vf v0, a02, v24 - vfmacc.vf v4, a12, v24 - vfmacc.vf v8, a22, v24 - vfmacc.vf v12, a32, v24 - vfmacc.vf v0, a03, v28 - vfmacc.vf v4, a13, v28 - vfmacc.vf v8, a23, v28 - vfmacc.vf v12, a33, v28 - - beqz kt, 1f - -k_loop_remainder_loop: - # Proceed at one k element per loop - addi kt, kt, -1 - vle32.v v16, (bkp) - flw a00, (akp); add amp, akp, astride; - flw a10, (amp); add amp, amp, astride; - flw a20, (amp); add amp, amp, astride; - flw a30, (amp) - - vfmacc.vf v0, a00, v16 - vfmacc.vf v4, a10, v16 - vfmacc.vf v8, a20, v16 - vfmacc.vf v12, a30, v16 - - addi akp, akp, 4 - add bkp, bkp, bstride - - bnez kt, k_loop_remainder_loop - -1: vse32.v v0, (cnp); add ccp, cnp, cstride; - vse32.v v4, (ccp); add ccp, ccp, cstride; - vse32.v v8, (ccp); add ccp, ccp, cstride; - vse32.v v12, (ccp) - - slli t6, nvl, 2 - add cnp, cnp, t6 - add bnp, bnp, t6 - sub nt, nt, nvl # Decrement element count in n dimension - bnez nt, c_col_loop - - # Move to the next set of rows - addi m, m, -4 - - slli t6, astride, 2 # Multiply astride by 4 - add ap, ap, t6 # Move A matrix pointer down 4 rows - slli t6, cstride, 2 # Multiply cstride by 4 - add cp, cp, t6 # Move C matrix pointer down 4 rows - - slti t6, m, 4 - beqz t6, c_row_loop - - beqz m, exit - -m_remainder_m_loop: - mv cnp, cp - mv bnp, bp - mv nt, n - -m_remainder_n_loop: - vsetvli nvl, nt, e32, m4, ta, ma # 32-bit vectors, LMUL=4 - - # Not enough remaining k elements to unroll by 4 - mv kt, k # Initialize inner loop counter - slti t6, kt, 4 - bnez t6, m_remainder_k_loop_remainder - - mv akp, ap # reset pointer into A to beginning - mv bkp, bnp # step to next column in B matrix - - vle32.v v0, (cnp) - - # Get vectors from B matrix - vle32.v v16, (bkp); add bkp, bkp, bstride - vle32.v v20, (bkp); add bkp, bkp, bstride - vle32.v v24, (bkp); add bkp, bkp, bstride - vle32.v v28, (bkp); add bkp, bkp, bstride - - # Inner loop scheduled assuming 4-clock occupancy of vfmacc instruction and single-issue pipeline - # Software pipeline loads - flw a00, (akp); addi akp, akp, 4 - flw a01, (akp); addi akp, akp, 4 - flw a02, (akp); addi akp, akp, 4 - flw a03, (akp); addi akp, akp, 4 - - addi kt, kt, -4 - -m_remainder_k_loop: - vfmacc.vf v0, a00, v16 - vfmacc.vf v0, a01, v20 - vfmacc.vf v0, a02, v24 - vfmacc.vf v0, a03, v28 - - addi kt, kt, -4 - blez kt, m_remainder_k_loop_remainder - - flw a00, (akp); addi akp, akp, 4 - flw a01, (akp); addi akp, akp, 4 - flw a02, (akp); addi akp, akp, 4 - flw a03, (akp); addi akp, akp, 4 - - vle32.v v16, (bkp); add bkp, bkp, bstride - vle32.v v20, (bkp); add bkp, bkp, bstride - vle32.v v24, (bkp); add bkp, bkp, bstride - vle32.v v28, (bkp); add bkp, bkp, bstride - - j m_remainder_k_loop - -m_remainder_k_loop_remainder: - addi kt, kt, 4 - beqz kt, 1f - -m_remainder_k_loop_remainder_loop: - - addi kt, kt, -1 - vle32.v v16, (bkp) - flw a00, (akp); add amp, akp, astride; - - vfmacc.vf v0, a00, v16 - - addi akp, akp, 4 - add bkp, bkp, bstride - - bnez kt, m_remainder_k_loop_remainder_loop - -1: vse32.v v0, (cnp) - - slli t6, nvl, 2 - add cnp, cnp, t6 - add bnp, bnp, t6 - sub nt, nt, nvl - bnez nt, m_remainder_n_loop - - addi m, m, -1 - add ap, ap, astride - add cp, cp, cstride - - bnez m, m_remainder_m_loop - -exit: - ld s0, 0(sp) - ld s1, 8(sp) - ld s2, 16(sp) - ld s3, 24(sp) - addi sp, sp, FRAMESIZE - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v3/vec-sgemm_main.c b/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v3/vec-sgemm_main.c deleted file mode 100644 index 252319db..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm-v3/vec-sgemm_main.c +++ /dev/null @@ -1,56 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// SGEMM benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized sgemm implementation. - -#include "util.h" -#include -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_sgemm_nn(size_t, size_t, size_t, const float *, size_t, const float *, - size_t, float *, size_t); - -int main(int argc, char *argv[]) { - float results_data[M_DIM * N_DIM] = {0}; - printf("sgemm M,N,K = %ld,%ld,%ld\n", M_DIM, N_DIM, K_DIM); - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_sgemm_nn(N_DIM, M_DIM, K_DIM, a_matrix, K_DIM, b_matrix, N_DIM, - results_data, N_DIM); -#endif - - // Do the size sweeps -#define MAXSZ 85 - if (M_DIM >= MAXSZ && N_DIM >= MAXSZ && K_DIM >= MAXSZ) { - for (size_t t = 8; t <= MAXSZ; t += 7) { - size_t start, end; - start = read_csr(mcycle); - vec_sgemm_nn(t, t, t, a_matrix, t, b_matrix, t, results_data, t); - asm volatile("fence"); - end = read_csr(mcycle); - printf("size %ld cycles = %ld\n", t, end - start); - } - } - - // Do the sgemm - memset(results_data, 0, sizeof(results_data)); - setStats(1); - vec_sgemm_nn(N_DIM, M_DIM, K_DIM, a_matrix, K_DIM, b_matrix, N_DIM, - results_data, N_DIM); - setStats(0); - - // Check the results - return verifyFloat(M_DIM * N_DIM, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-sgemm/dataset1.h deleted file mode 100644 index 29a30cd7..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm/dataset1.h +++ /dev/null @@ -1,2535 +0,0 @@ -#define M_DIM 71 -#define K_DIM 71 -#define N_DIM 71 - -typedef float data_t; - -static data_t a_matrix[M_DIM * K_DIM] = { - -112.0, -1.875, -20.0, 28.0, -0.125, -40.0, 60.0, -1.625, - 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-import numpy as np -import argparse - - -m_dim = 71 -k_dim = 71 -n_dim = 71 - -parser = argparse.ArgumentParser( - description="A script to generate input data for an SGEMM kernel." -) - -parser.add_argument("--mdim", type=int, help="M dimension of inputs") -parser.add_argument("--kdim", type=int, help="K dimension of inputs") -parser.add_argument("--ndim", type=int, help="N dimension of inputs") -parser.add_argument("--size", type=int, help="Dimensions of NxN inputs") - -args = parser.parse_args() - -if args.size: - m_dim = args.size - k_dim = args.size - n_dim = args.size -else: - if args.mdim: - m_dim = args.mdim - if args.kdim: - k_dim = args.kdim - if args.ndim: - n_dim = args.ndim - -a_array_size = m_dim * k_dim -b_array_size = k_dim * n_dim -c_array_size = m_dim * n_dim - -info = np.finfo(np.float32) -maxmant = 1 << 4 -minexp = -4 -maxexp = 4 - - -# Generate floating-point values with exact mantissa and exponent -def randf(n): - return np.ldexp( - np.random.randint(-1 * maxmant, maxmant, size=n), - np.random.randint(minexp, maxexp, size=n), - ) - - -a_matrix = randf((m_dim, k_dim)).astype(np.float32) -b_matrix = randf((k_dim, n_dim)).astype(np.float32) - -c_matrix = np.dot(a_matrix, b_matrix) - -print( - f"""#define M_DIM {m_dim} -#define K_DIM {k_dim} -#define N_DIM {n_dim} - -typedef float data_t; - -""" -) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=10): - print(f"{name} [{data_size}] = {{") - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print_array("static data_t a_matrix", a_matrix.flatten(), "M_DIM*K_DIM") -print_array("static data_t b_matrix", b_matrix.flatten(), "K_DIM*N_DIM") -print_array("static data_t verify_data", c_matrix.flatten(), "M_DIM*N_DIM") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm/vec-sgemm.S b/bb-tests/workloads/src/CTest/rvv/vec-sgemm/vec-sgemm.S deleted file mode 100644 index 1c43bede..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm/vec-sgemm.S +++ /dev/null @@ -1,200 +0,0 @@ - .text - .balign 4 - .global vec_sgemm_nn -# RV64IDV system -# -# void -# vec_sgemm_nn(size_t n, -# size_t m, -# size_t k, -# const float*a, // m * k matrix -# size_t lda, -# const float*b, // k * n matrix -# size_t ldb, -# float*c, // m * n matrix -# size_t ldc) -# -# c += a*b (alpha=1, no transpose on input matrices) -# matrices stored in C row-major order - -#define n a0 -#define m a1 -#define k a2 -#define ap a3 -#define astride a4 -#define bp a5 -#define bstride a6 -#define cp a7 -#define cstride t0 -#define kt t1 -#define nt t2 -#define bnp t3 -#define cnp t4 -#define akp t5 -#define bkp s0 -#define nvl s1 -#define ccp s2 -#define amp s3 - -# Use args as additional temporaries -#define ft12 fa0 -#define ft13 fa1 -#define ft14 fa2 -#define ft15 fa3 - -#define FRAMESIZE 32 - -# This version holds a 4*VLMAX*4 block of C matrix in vector registers -# in inner loop, but otherwise does not cache or TLB tiling. - -vec_sgemm_nn: - ld cstride, 0(sp) # Get arg from stack frame - addi sp, sp, -FRAMESIZE - sd s0, 0(sp) - sd s1, 8(sp) - sd s2, 16(sp) - sd s3, 24(sp) - - # Check for zero size matrices - beqz n, exit - beqz m, exit - beqz k, exit - - # Convert elements strides to byte strides. - slli astride, astride, 2 - slli bstride, bstride, 2 - slli cstride, cstride, 2 - - slti t6, m, 4 - bnez t6, end_rows - -c_row_loop: # Loop across rows of C blocks - - mv nt, n # Initialize n counter for next row of C blocks - - mv bnp, bp # Initialize B n-loop pointer to start - mv cnp, cp # Initialize C n-loop pointer - -c_col_loop: # Loop across one row of C blocks - vsetvli nvl, nt, e32, m4, ta, ma # 32-bit vectors, LMUL=4 - - # Initalize current C submatrix block from memory. - vle32.v v0, (cnp); add ccp, cnp, cstride; - mv akp, ap # reset pointer into A to beginning - vle32.v v4, (ccp); add ccp, ccp, cstride; - mv bkp, bnp # step to next column in B matrix - vle32.v v8, (ccp); add ccp, ccp, cstride; - vle32.v v12, (ccp); - - # Get vector from B matrix - vle32.v v16, (bkp) - mv kt, k # Initialize inner loop counter - - # Inner loop scheduled assuming 4-clock occupancy of vfmacc instruction and single-issue pipeline - # Software pipeline loads - flw ft0, (akp); add amp, akp, astride; - flw ft1, (amp); add amp, amp, astride; - flw ft2, (amp); add amp, amp, astride; - flw ft3, (amp); add amp, amp, astride; - - # Loop on inner dimension for current C block -k_loop: - vfmacc.vf v0, ft0, v16 - add bkp, bkp, bstride - addi kt, kt, -1 # Decrement k counter - addi akp, akp, 4 - beqz kt, 1f - flw ft0, (akp) - add amp, akp, astride -1: vfmacc.vf v4, ft1, v16 - beqz kt, 1f - flw ft1, (amp) - add amp, amp, astride -1: vfmacc.vf v8, ft2, v16 - beqz kt, 1f - flw ft2, (amp) - add amp, amp, astride -1: vfmacc.vf v12, ft3, v16 - beqz kt, 1f # Exit the loop - flw ft3, (amp) - add amp, amp, astride - vle32.v v16, (bkp) # Get next vector from B matrix, overlap loads with jump stalls - j k_loop - -1: vse32.v v0, (cnp); add ccp, cnp, cstride; - slli t6, nvl, 2 - vse32.v v4, (ccp); add ccp, ccp, cstride; - add cnp, cnp, t6 # Move C block pointer over - vse32.v v8, (ccp); add ccp, ccp, cstride; - add bnp, bnp, t6 # Move B block pointer over - sub nt, nt, nvl # Decrement element count in n dimension - vse32.v v12, (ccp); - - # Following tail instructions should be scheduled earlier in free slots during C block save. - # Leaving here for clarity. - - # Bump pointers for loop across blocks in one row - bnez nt, c_col_loop # Any more to do? - - # Move to next set of rows - addi m, m, -4 # Did 4 rows above - slli t6, astride, 2 # Multiply astride by 4 - add ap, ap, t6 # Move A matrix pointer down 4 rows - slli t6, cstride, 2 # Multiply cstride by 4 - add cp, cp, t6 # Move C matrix pointer down 4 rows - - slti t6, m, 4 - beqz t6, c_row_loop - - # Handle end of matrix with fewer than 4 rows. - # Can use smaller versions of above decreasing in powers-of-2 depending on code-size concerns. -end_rows: - beqz m, exit - -end_rows_row_loop: - mv nt, n # Initialize n counter for next row of C blocks - mv bnp, bp # Initialize B n-loop pointer to start - mv cnp, cp # Initialize C n-loop pointer - -end_rows_col_loop: - vsetvli nvl, nt, e32, m4, ta, ma # 32-bit vectors, LMUL=4 - vle32.v v0, (cnp) - mv akp, ap # reset pointer into A to beginning - mv bkp, bnp # step to next column in B matrix - vle32.v v16, (bkp) - flw ft0, (akp) - mv kt, k # Initialize inner loop counter - -end_rows_k_loop: - vfmacc.vf v0, ft0, v16 - addi akp, akp, 4 - addi kt, kt, -1 - add bkp, bkp, bstride - - beqz kt, 1f - - flw ft0, (akp) - vle32.v v16, (bkp) - j end_rows_k_loop - -1: vse32.v v0, (cnp) - slli t6, nvl, 2 - add cnp, cnp, t6 - add bnp, bnp, t6 - sub nt, nt, nvl - - bnez nt, end_rows_col_loop - - addi m, m, -1 - add ap, ap, astride - add cp, cp, cstride - - bnez m, end_rows_row_loop - -exit: - ld s0, 0(sp) - ld s1, 8(sp) - ld s2, 16(sp) - ld s3, 24(sp) - addi sp, sp, FRAMESIZE - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemm/vec-sgemm_main.c b/bb-tests/workloads/src/CTest/rvv/vec-sgemm/vec-sgemm_main.c deleted file mode 100644 index e9a81ecc..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemm/vec-sgemm_main.c +++ /dev/null @@ -1,43 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// SGEMM benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized sgemm implementation. - -#include "util.h" -#include -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_sgemm_nn(size_t, size_t, size_t, const float *, size_t, const float *, - size_t, float *, size_t); - -int main(int argc, char *argv[]) { - float results_data[M_DIM * N_DIM] = {0}; - printf("sgemm M,N,K = %ld,%ld,%ld\n", M_DIM, N_DIM, K_DIM); - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_sgemm_nn(N_DIM, M_DIM, K_DIM, a_matrix, K_DIM, b_matrix, N_DIM, - results_data, N_DIM); - memset(results_data, 0, sizeof(results_data)); -#endif - - // Do the sgemm - setStats(1); - vec_sgemm_nn(N_DIM, M_DIM, K_DIM, a_matrix, K_DIM, b_matrix, N_DIM, - results_data, N_DIM); - setStats(0); - - // Check the results - return verifyFloat(M_DIM * N_DIM, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-sgemv/dataset1.h deleted file mode 100644 index 0a7ef5f9..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/dataset1.h +++ /dev/null @@ -1,1123 +0,0 @@ -#define M_DIM 128 -#define N_DIM 128 -#define DIM_SIZE 16384 -float input_data_A[M_DIM * N_DIM] = { - 0.0, 0.0, 0.0, 0.0, 1.0, 2.0, 0.0, 1.0, 2.0, 4.0, 0.0, 2.0, 4.0, 0.0, 0.0, - 0.0, 2.0, 0.0, 1.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 4.0, 0.0, - 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 4.0, 2.0, 0.0, 2.0, - 0.0, 0.0, 0.0, 0.0, 4.0, 4.0, 4.0, 1.0, 2.0, 4.0, 0.0, 4.0, 4.0, 2.0, 2.0, - 0.0, 2.0, 0.0, 0.0, 2.0, 2.0, 1.0, 1.0, 0.0, 4.0, 2.0, 4.0, 2.0, 0.0, 4.0, - 0.0, 2.0, 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, 1.0, 2.0, 1.0, - 2.0, 0.0, 4.0, 1.0, 0.0, 0.0, 1.0, 1.0, 0.0, 2.0, 0.0, 0.0, 0.0, 1.0, 0.0, - 4.0, 2.0, 1.0, 0.0, 1.0, 0.0, 4.0, 0.0, 1.0, 4.0, 4.0, 0.0, 0.0, 0.0, 0.0, - 0.0, 0.0, 0.0, 0.0, 4.0, 0.0, 2.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 2.0, 4.0, - 1.0, 0.0, 2.0, 1.0, 1.0, 0.0, 1.0, 0.0, 0.0, 4.0, 0.0, 4.0, 0.0, 0.0, 4.0, - 1.0, 0.0, 0.0, 4.0, 0.0, 0.0, 4.0, 0.0, 2.0, 2.0, 0.0, 4.0, 0.0, 0.0, 2.0, - 2.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 2.0, 0.0, 1.0, 4.0, 0.0, 0.0, 1.0, 0.0, - 1.0, 4.0, 0.0, 1.0, 0.0, 1.0, 1.0, 2.0, 1.0, 1.0, 4.0, 0.0, 2.0, 4.0, 4.0, - 1.0, 0.0, 0.0, 0.0, 0.0, 4.0, 0.0, 1.0, 2.0, 2.0, 0.0, 0.0, 2.0, 0.0, 1.0, - 2.0, 0.0, 2.0, 0.0, 0.0, 4.0, 0.0, 0.0, 2.0, 2.0, 0.0, 2.0, 0.0, 2.0, 0.0, - 1.0, 0.0, 1.0, 2.0, 1.0, 0.0, 4.0, 1.0, 1.0, 4.0, 4.0, 0.0, 2.0, 0.0, 2.0, - 0.0, 4.0, 0.0, 4.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 2.0, 4.0, 0.0, 0.0, 0.0, - 0.0, 4.0, 4.0, 2.0, 4.0, 0.0, 2.0, 1.0, 4.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, - 0.0, 4.0, 2.0, 0.0, 0.0, 0.0, 4.0, 1.0, 2.0, 0.0, 4.0, 0.0, 2.0, 4.0, 0.0, - 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0.0, 2.0, 2.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0, 0.0, 1.0, 0.0, 4.0, 0.0, 4.0, - 1.0, 0.0, 2.0, 1.0, 0.0, 4.0, 4.0, 2.0, 4.0, 0.0, 0.0, 0.0, 0.0, 0.0, 4.0, - 0.0, 2.0, 4.0, 4.0, 2.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, - 0.0, 0.0, 1.0, 1.0, 0.0, 2.0, 1.0, 1.0, 0.0, 0.0, 0.0, 1.0, 4.0, 0.0, 0.0, - 0.0, 2.0, 2.0, 0.0, 4.0, 0.0, 4.0, 4.0, 0.0, 0.0, 2.0, 0.0, 4.0, 0.0, 4.0, - 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 4.0, 1.0, 0.0, 1.0, 0.0, 2.0, 0.0, 4.0, 1.0, - 2.0, 0.0, 0.0, 4.0, 1.0, 2.0, 2.0, 1.0, 0.0, 0.0, 0.0, 4.0, 4.0, 1.0, 0.0, - 0.0, 4.0, 0.0, 0.0, -}; -float input_data_x[M_DIM] = { - 0.0, 2.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 4.0, 1.0, 0.0, 4.0, 4.0, 4.0, 0.0, - 2.0, 4.0, 2.0, 0.0, 1.0, 2.0, 2.0, 0.0, 0.0, 1.0, 2.0, 0.0, 0.0, 0.0, 1.0, - 1.0, 1.0, 4.0, 1.0, 0.0, 2.0, 1.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, - 0.0, 2.0, 0.0, 2.0, 0.0, 0.0, 0.0, 4.0, 2.0, 2.0, 2.0, 0.0, 0.0, 2.0, 0.0, - 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 4.0, 1.0, 0.0, 0.0, 2.0, 0.0, 1.0, 2.0, 4.0, - 0.0, 2.0, 1.0, 0.0, 2.0, 4.0, 4.0, 1.0, 4.0, 0.0, 0.0, 2.0, 0.0, 1.0, 0.0, - 2.0, 2.0, 4.0, 2.0, 4.0, 4.0, 0.0, 2.0, 2.0, 0.0, 2.0, 4.0, 0.0, 0.0, 1.0, - 0.0, 0.0, 2.0, 0.0, 4.0, 4.0, 1.0, 0.0, 1.0, 4.0, 4.0, 0.0, 0.0, 4.0, 0.0, - 2.0, 1.0, 0.0, 1.0, 0.0, 4.0, 1.0, 0.0, -}; -float verify_data[N_DIM] = { - 147.0, 219.0, 230.0, 268.0, 177.0, 160.0, 245.0, 180.0, 194.0, 235.0, 232.0, - 210.0, 237.0, 228.0, 192.0, 198.0, 179.0, 107.0, 160.0, 151.0, 171.0, 157.0, - 209.0, 132.0, 231.0, 213.0, 202.0, 229.0, 168.0, 207.0, 150.0, 239.0, 197.0, - 189.0, 153.0, 268.0, 199.0, 213.0, 149.0, 192.0, 205.0, 172.0, 156.0, 211.0, - 173.0, 167.0, 161.0, 256.0, 203.0, 212.0, 137.0, 226.0, 186.0, 236.0, 186.0, - 185.0, 202.0, 174.0, 185.0, 235.0, 184.0, 227.0, 268.0, 172.0, 190.0, 236.0, - 203.0, 183.0, 186.0, 210.0, 219.0, 165.0, 219.0, 212.0, 205.0, 178.0, 216.0, - 206.0, 188.0, 174.0, 155.0, 266.0, 192.0, 218.0, 166.0, 173.0, 142.0, 202.0, - 188.0, 147.0, 148.0, 230.0, 249.0, 202.0, 219.0, 191.0, 182.0, 182.0, 179.0, - 236.0, 220.0, 213.0, 159.0, 160.0, 201.0, 238.0, 175.0, 186.0, 160.0, 190.0, - 136.0, 144.0, 119.0, 169.0, 199.0, 175.0, 174.0, 186.0, 168.0, 184.0, 227.0, - 221.0, 246.0, 165.0, 188.0, 178.0, 189.0, 178.0, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-sgemv/gendata.py deleted file mode 100755 index 3c21ca42..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/gendata.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python3 - -import numpy - -M_DIM = 128 -N_DIM = 128 - -info = numpy.finfo(numpy.float64) -nmant = 1 # Limit precision to avoid rounding errors -maxmant = 1 << nmant -minexp = 0 -maxexp = 3 - - -# Generate floating-point values with exact mantissa and exponent -def randf(n): - return numpy.ldexp( - numpy.random.randint(maxmant, size=n), - numpy.random.randint(minexp, maxexp, size=n), - ) - - -A = randf((M_DIM, N_DIM)).astype(numpy.float64) -x = randf(M_DIM).astype(numpy.float64) -result = numpy.dot(numpy.transpose(x), A) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=8): - print("{} {}[{}] = {{".format(data_type, name, data_size)) - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print("#define M_DIM {}".format(M_DIM)) -print("#define N_DIM {}".format(N_DIM)) -print("#define DIM_SIZE {}".format(M_DIM * N_DIM)) - -print_array("input_data_A", A.flatten(), "M_DIM * N_DIM") -print_array("input_data_x", x, "M_DIM") -print_array("verify_data", result, "N_DIM") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/vec-sgemv.S b/bb-tests/workloads/src/CTest/rvv/vec-sgemv/vec-sgemv.S deleted file mode 100644 index 9b590563..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/vec-sgemv.S +++ /dev/null @@ -1,94 +0,0 @@ - .text - .balign 4 - .global vec_sgemv -# RV64IDV system -# -# void -# vec_sgemv(size_t m, -# size_t n, -# const float* v, // m-length vector -# const float* m, // m * n matrix -# float*c) // m-length vector -# -# c += a*b (V^T * M) -# matrix stored in row-major order - -#define m a0 -#define n a1 -#define vp a2 -#define mp a3 -#define cp a4 - -#define vt t1 -#define mpm t2 -#define nvl t3 -#define nstride t4 -#define mt t5 -#define nvlb t6 - - -vec_sgemv: - # Check for zero size matrices - beqz m, exit - beqz n, exit - - # Convert elements strides to byte strides. - slli nstride, n, 2 - - slti mt, mp, 2 - bnez mt, exit - -c_col_loop: - vsetvli nvl, n, e32, m8, ta, ma # 32-bit vectors, LMUL=8 - - mv mt, m # reset the row pointer - mv vt, vp # reset the vector pointer - - # Load vector from the C matrix - vle32.v v16, (cp) - - vle32.v v0, (mp) - add mpm, mp, nstride - vle32.v v8, (mpm) - add mpm, mpm, nstride - - flw ft0, (vp) - flw ft1, 4(vp) - addi vt, vp, 8 - -m_loop: - vfmacc.vf v16, ft0, v0 # Compute the first FMA of the loop against V scalar - vle32.v v0, (mpm) # Load the next row of the matrix - flw ft0, (vt) # Load the next scalar from V - add mpm, mpm, nstride # Bump the M pointer for the next M vector load - addi mt, mt, -2 # Completing two rows of M in this loop - vfmacc.vf v16, ft1, v8 # Compute the second FMA of the loop - vle32.v v8, (mpm) # Load the next row of the matrix - add mpm, mpm, nstride # Bump the M pointer - flw ft1, 4(vt) # Load the next V scalar - addi vt, vt, 8 # Bump the pointer for the next scalar load - slti t0, mt, 4 - bnez t0, 1f - j m_loop - -1: vfmacc.vf v16, ft0, v0 - addi mt, mt, -2 - vfmacc.vf v16, ft1, v8 - - beqz mt, 1f - - vle32.v v0, (mpm) - flw ft0, (vt) - vfmacc.vf v16, ft0, v0 - -1: vse32.v v16, (cp) # Store the vector of results - - slli nvlb, nvl, 2 # Current vl in bytes - add cp, cp, nvlb # Bump the output pointer - add mp, mp, nvlb # Bump the matrix pointer to the next set of columns - - sub n, n, nvl # Track how much of output we've computed - bnez n, c_col_loop # Done with entire computation? - -exit: - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/vec-sgemv_main.c b/bb-tests/workloads/src/CTest/rvv/vec-sgemv/vec-sgemv_main.c deleted file mode 100644 index 4dc55c68..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-sgemv/vec-sgemv_main.c +++ /dev/null @@ -1,40 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// SGEMV benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized sgemm implementation. - -#include "util.h" -#include -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_sgemv(size_t, size_t, const float *, const float *, float *); - -int main(int argc, char *argv[]) { - float results_data[N_DIM] = {0}; - - printf("sgemv M,N = %ld,%ld\n", M_DIM, N_DIM); -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_sgemv(M_DIM, N_DIM, input_data_x, input_data_A, results_data); - memset(results_data, 0, sizeof(results_data)); -#endif - - // Do the sgemv - setStats(1); - vec_sgemv(M_DIM, N_DIM, input_data_x, input_data_A, results_data); - setStats(0); - - // Check the results - return verifyFloat(N_DIM, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/dataset1.h deleted file mode 100644 index 67db4dcf..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/dataset1.h +++ /dev/null @@ -1,1040 +0,0 @@ -#define KH 3 -#define KW 3 -#define IH 72 -#define IW 72 -#define I_SIZE 5184 -#define OH 70 -#define OW 70 -#define O_SIZE 4900 - -float input_k1[IW] = { - 1.0, - 1.0, - 1.0, -}; -float input_k2[IH] = { - 1.0, - 1.0, - 1.0, -}; -float input_image[I_SIZE] = { - 2.0, 0.0, 0.0, 6.0, 80.0, 64.0, 184.0, 26.0, 4.0, 128.0, 26.0, - 30.0, 208.0, 16.0, 384.0, 32.0, 52.0, 40.0, 42.0, 19.0, 36.0, 18.0, - 12.0, 80.0, 32.0, 30.0, 400.0, 22.0, 104.0, 432.0, 80.0, 400.0, 56.0, - 184.0, 56.0, 4.0, 224.0, 8.0, 28.0, 40.0, 2.0, 288.0, 208.0, 108.0, - 32.0, 5.0, 18.0, 36.0, 60.0, 10.0, 88.0, 108.0, 368.0, 20.0, 28.0, - 108.0, 26.0, 23.0, 28.0, 32.0, 28.0, 176.0, 34.0, 96.0, 168.0, 4.0, - 16.0, 248.0, 416.0, 108.0, 4.0, 6.0, 0.0, 192.0, 248.0, 22.0, 72.0, - 32.0, 176.0, 144.0, 46.0, 12.0, 88.0, 128.0, 26.0, 22.0, 12.0, 124.0, - 36.0, 48.0, 18.0, 50.0, 22.0, 112.0, 10.0, 4.0, 288.0, 36.0, 96.0, - 120.0, 16.0, 92.0, 46.0, 40.0, 100.0, 31.0, 24.0, 240.0, 224.0, 496.0, - 124.0, 56.0, 248.0, 18.0, 26.0, 416.0, 232.0, 20.0, 31.0, 20.0, 96.0, - 26.0, 36.0, 88.0, 88.0, 48.0, 28.0, 16.0, 96.0, 80.0, 48.0, 6.0, - 64.0, 160.0, 10.0, 32.0, 56.0, 224.0, 224.0, 248.0, 144.0, 24.0, 52.0, - 64.0, 100.0, 21.0, 416.0, 64.0, 62.0, 18.0, 46.0, 16.0, 20.0, 12.0, - 224.0, 30.0, 50.0, 27.0, 76.0, 23.0, 16.0, 16.0, 208.0, 44.0, 31.0, - 256.0, 50.0, 19.0, 42.0, 80.0, 2.0, 48.0, 8.0, 336.0, 56.0, 32.0, - 24.0, 60.0, 8.0, 48.0, 9.0, 56.0, 12.0, 80.0, 64.0, 104.0, 10.0, - 32.0, 58.0, 200.0, 76.0, 100.0, 56.0, 68.0, 152.0, 0.0, 18.0, 208.0, - 60.0, 88.0, 116.0, 96.0, 432.0, 6.0, 68.0, 72.0, 52.0, 104.0, 128.0, - 54.0, 2.0, 160.0, 96.0, 24.0, 15.0, 56.0, 192.0, 480.0, 12.0, 88.0, - 48.0, 9.0, 12.0, 18.0, 20.0, 2.0, 320.0, 192.0, 54.0, 16.0, 13.0, - 208.0, 160.0, 40.0, 272.0, 80.0, 480.0, 25.0, 448.0, 40.0, 13.0, 48.0, - 23.0, 480.0, 92.0, 6.0, 72.0, 8.0, 248.0, 288.0, 60.0, 44.0, 80.0, - 56.0, 124.0, 256.0, 208.0, 58.0, 22.0, 112.0, 208.0, 48.0, 60.0, 64.0, - 232.0, 14.0, 224.0, 20.0, 248.0, 12.0, 184.0, 88.0, 168.0, 288.0, 38.0, - 400.0, 50.0, 192.0, 34.0, 0.0, 400.0, 464.0, 10.0, 30.0, 1.0, 144.0, - 24.0, 44.0, 8.0, 7.0, 0.0, 272.0, 240.0, 18.0, 160.0, 26.0, 104.0, - 2.0, 80.0, 496.0, 56.0, 208.0, 176.0, 18.0, 88.0, 32.0, 48.0, 10.0, - 24.0, 7.0, 4.0, 72.0, 34.0, 352.0, 88.0, 120.0, 84.0, 128.0, 24.0, - 30.0, 416.0, 288.0, 16.0, 7.0, 72.0, 100.0, 56.0, 208.0, 48.0, 72.0, - 28.0, 52.0, 32.0, 88.0, 7.0, 5.0, 18.0, 10.0, 25.0, 40.0, 14.0, - 24.0, 38.0, 30.0, 48.0, 30.0, 6.0, 28.0, 48.0, 42.0, 72.0, 2.0, - 100.0, 56.0, 160.0, 24.0, 56.0, 1.0, 4.0, 128.0, 31.0, 116.0, 92.0, - 88.0, 11.0, 26.0, 40.0, 80.0, 16.0, 80.0, 80.0, 28.0, 26.0, 112.0, - 216.0, 76.0, 368.0, 2.0, 50.0, 136.0, 3.0, 176.0, 480.0, 168.0, 64.0, - 2.0, 56.0, 96.0, 112.0, 320.0, 24.0, 8.0, 56.0, 96.0, 224.0, 26.0, - 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104.0, 240.0, 184.0, -}; -float verify_data[O_SIZE] = { - 979.0, 969.0, 970.0, 420.0, 734.0, 706.0, 662.0, 408.0, 560.0, - 678.0, 810.0, 537.0, 821.0, 716.0, 755.0, 387.0, 476.0, 485.0, - 470.0, 588.0, 547.0, 561.0, 537.0, 611.0, 1006.0, 834.0, 816.0, - 1178.0, 1170.0, 1514.0, 834.0, 927.0, 543.0, 655.0, 837.0, 1309.0, - 1181.0, 900.0, 654.0, 900.0, 968.0, 1210.0, 1122.0, 1103.0, 672.0, - 506.0, 493.0, 472.0, 592.0, 576.0, 946.0, 946.0, 866.0, 604.0, - 566.0, 649.0, 945.0, 751.0, 712.0, 612.0, 664.0, 736.0, 680.0, - 866.0, 876.0, 1180.0, 1554.0, 1468.0, 883.0, 353.0, 1661.0, 1543.0, - 1032.0, 415.0, 475.0, 471.0, 498.0, 290.0, 744.0, 1008.0, 1112.0, - 545.0, 296.0, 521.0, 668.0, 671.0, 814.0, 776.0, 1205.0, 1100.0, - 1434.0, 964.0, 914.0, 570.0, 628.0, 933.0, 885.0, 1198.0, 724.0, - 688.0, 626.0, 831.0, 843.0, 803.0, 737.0, 1253.0, 1181.0, 1260.0, - 1172.0, 1092.0, 758.0, 798.0, 1116.0, 1326.0, 933.0, 619.0, 735.0, - 676.0, 904.0, 628.0, 874.0, 730.0, 894.0, 732.0, 844.0, 1036.0, - 1362.0, 1394.0, 1112.0, 1018.0, 702.0, 656.0, 816.0, 1462.0, 1562.0, - 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237.0, 439.0, 627.0, 1004.0, 1426.0, 1236.0, 1070.0, 1032.0, 1010.0, - 651.0, 785.0, 778.0, 881.0, 311.0, 632.0, 578.0, 1136.0, 1230.0, - 1964.0, 1597.0, 1337.0, 883.0, 770.0, 1058.0, 734.0, 896.0, 876.0, - 1082.0, 1532.0, 1325.0, 1461.0, 1661.0, 1367.0, 1060.0, 148.0, 259.0, - 294.0, 551.0, 757.0, 997.0, 1318.0, 1010.0, 1238.0, 1172.0, 1222.0, - 934.0, 590.0, 1268.0, 1224.0, 1094.0, 672.0, 512.0, 623.0, 403.0, - 449.0, 430.0, 882.0, 816.0, 935.0, 535.0, 1215.0, 1009.0, 1041.0, - 421.0, 852.0, 719.0, 691.0, 665.0, 698.0, 774.0, 836.0, 1190.0, - 508.0, 772.0, 1184.0, 1434.0, 1250.0, 1576.0, 1294.0, 1206.0, 1094.0, - 907.0, 875.0, 597.0, 1178.0, 1309.0, 1475.0, 1173.0, 1685.0, 1335.0, - 1045.0, 679.0, 1001.0, 1515.0, 1184.0, 972.0, 862.0, 1080.0, 1100.0, - 1087.0, 1185.0, 1597.0, 1140.0, 858.0, 131.0, 256.0, 348.0, 601.0, - 808.0, 982.0, 1234.0, 944.0, 1120.0, 1062.0, 1086.0, 958.0, 742.0, - 1312.0, 1264.0, 1276.0, 874.0, 810.0, 871.0, 923.0, 751.0, 528.0, - 696.0, 636.0, 821.0, 469.0, 1409.0, 1202.0, 1234.0, 582.0, 611.0, - 579.0, 345.0, 710.0, 653.0, 707.0, 779.0, 974.0, 501.0, 699.0, - 698.0, 922.0, 836.0, 1444.0, 1162.0, 1539.0, 1387.0, 1370.0, 913.0, - 815.0, 1658.0, 1788.0, 2102.0, 1259.0, 1550.0, 1031.0, 824.0, 376.0, - 663.0, 853.0, 848.0, 686.0, 952.0, 1054.0, 796.0, 798.0, 1072.0, - 1314.0, 812.0, 466.0, 215.0, 264.0, 292.0, 543.0, 688.0, 916.0, - 1008.0, 1046.0, 1264.0, 1254.0, 1104.0, 848.0, 577.0, 1109.0, 1249.0, - 1384.0, 1058.0, 846.0, 942.0, 918.0, 828.0, 540.0, 622.0, 516.0, - 735.0, 479.0, 1515.0, 1292.0, 1460.0, 988.0, 1023.0, 849.0, 467.0, - 482.0, 523.0, 493.0, 911.0, 988.0, 373.0, 350.0, 504.0, 1100.0, - 940.0, 1345.0, 1159.0, 1639.0, 1459.0, 1669.0, 1373.0, 1382.0, 1442.0, - 1369.0, 1385.0, 695.0, 703.0, 622.0, 938.0, 1032.0, 1205.0, 1021.0, - 799.0, 381.0, 335.0, 662.0, 686.0, 1014.0, 888.0, 1282.0, 864.0, - 657.0, 215.0, 187.0, 266.0, 290.0, 568.0, 576.0, 860.0, 812.0, - 826.0, 546.0, 366.0, 476.0, 469.0, 611.0, 709.0, 864.0, 1028.0, - 890.0, 974.0, 832.0, 826.0, 534.0, 740.0, 570.0, 811.0, 453.0, - 1105.0, 988.0, 1168.0, 1028.0, 892.0, 816.0, 455.0, 639.0, 566.0, - 479.0, 383.0, 484.0, 445.0, 410.0, 560.0, 876.0, 704.0, 819.0, - 689.0, 1189.0, 1029.0, 1343.0, 1091.0, 1020.0, 909.0, 656.0, 1015.0, - 542.0, 813.0, 1150.0, 1451.0, 1416.0, 954.0, 740.0, 514.0, 378.0, - 449.0, 798.0, 780.0, 870.0, 716.0, 1042.0, 798.0, 625.0, 249.0, - 444.0, 897.0, 923.0, 917.0, 496.0, 532.0, 921.0, 960.0, 921.0, - 337.0, 369.0, 293.0, 641.0, 693.0, 788.0, 788.0, 698.0, 695.0, - 387.0, 581.0, 524.0, 506.0, 284.0, 837.0, 1169.0, 1333.0, 837.0, - 601.0, 677.0, 1013.0, 1449.0, 1276.0, 1027.0, 554.0, 509.0, 337.0, - 420.0, 828.0, 627.0, 634.0, 934.0, 686.0, 871.0, 791.0, 951.0, - 655.0, 759.0, 851.0, 852.0, 448.0, 210.0, 155.0, 119.0, 255.0, - 1194.0, 1567.0, 1630.0, 932.0, 574.0, 522.0, 398.0, 925.0, 1538.0, - 1490.0, 1160.0, 486.0, 992.0, 1251.0, 1175.0, 787.0, 577.0, 1137.0, - 1105.0, 985.0, 622.0, 522.0, 795.0, 1072.0, 1233.0, 805.0, 353.0, - 148.0, 716.0, 770.0, 867.0, 357.0, 433.0, 401.0, 405.0, 697.0, - 728.0, 918.0, 782.0, 1175.0, 1433.0, 1261.0, 1253.0, 1201.0, 1069.0, - 1038.0, 1418.0, 1441.0, 1101.0, 436.0, 527.0, 461.0, 480.0, 616.0, - 675.0, 616.0, 1118.0, 880.0, 1104.0, 728.0, 878.0, 608.0, 438.0, - 438.0, 416.0, 426.0, 507.0, 500.0, 475.0, 434.0, 1015.0, 1029.0, - 870.0, 662.0, 786.0, 825.0, 509.0, 874.0, 1180.0, 1094.0, 628.0, - 362.0, 503.0, 1090.0, 942.0, 994.0, 897.0, 1441.0, 1456.0, 1079.0, - 704.0, 506.0, 736.0, 1091.0, 1210.0, 971.0, 565.0, 439.0, 887.0, - 915.0, 989.0, 376.0, 358.0, 287.0, 316.0, 474.0, 554.0, 724.0, - 715.0, 1471.0, 1809.0, 2004.0, 1773.0, 1682.0, 1286.0, 1446.0, 1745.0, - 1795.0, 1066.0, 503.0, 469.0, 475.0, 254.0, 591.0, 453.0, 410.0, - 784.0, 824.0, 1072.0, 808.0, 830.0, 620.0, 970.0, 1038.0, 1104.0, - 641.0, 744.0, 622.0, 804.0, 747.0, 867.0, 766.0, 666.0, 1084.0, - 1108.0, 1058.0, 434.0, 720.0, 1000.0, 982.0, 551.0, 501.0, 656.0, - 1665.0, 1322.0, 1441.0, 807.0, 1034.0, 954.0, 1104.0, 1012.0, 831.0, - 304.0, 699.0, 1150.0, 1505.0, 1062.0, 725.0, 817.0, 815.0, 695.0, - 302.0, 256.0, 290.0, 217.0, 459.0, 480.0, 714.0, 889.0, 1373.0, - 1372.0, 1329.0, 1569.0, 1871.0, 1534.0, 1067.0, 824.0, 1087.0, 822.0, - 862.0, 684.0, 914.0, 746.0, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/gendata.py deleted file mode 100755 index 6957e0e9..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/gendata.py +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env python3 - -import numpy as np - -KH = 3 -KW = 3 -IH = 72 -IW = 72 -OH = IH - KH + 1 -OW = IW - KW + 1 - -info = np.finfo(np.float32) -nmant = 5 # Limit precision to avoid rounding errors -maxmant = 1 << nmant -minexp = 0 -maxexp = 5 - - -# Generate floating-point values with exact mantissa and exponent -def randf(n): - return np.ldexp( - np.random.randint(maxmant, size=n), np.random.randint(minexp, maxexp, size=n) - ) - - -inputs = randf((IH, IW)).astype(np.float32) -weights = np.ones((KH, KW), dtype=np.float32) -weights_1 = np.ones(KW, dtype=np.float32) -weights_2 = np.ones(KH, dtype=np.float32) -outputs = np.full((OH, OW), np.float32(0.0)) - -# Convolution -for kh in range(KH): - for kw in range(KW): - outputs += inputs[kh : (kh + OH), kw : (kw + OW)] * weights[kh][kw] - -print( - """#define KH {} -#define KW {} -#define IH {} -#define IW {} -#define I_SIZE {} -#define OH {} -#define OW {} -#define O_SIZE {} - -""".format( - KH, KW, IH, IW, IH * IW, OH, OW, OH * OW - ) -) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=10): - print("{} {}[{}] = {{".format(data_type, name, data_size)) - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print_array("input_k1", weights_1, "IW") -print_array("input_k2", weights_2, "IH") -print_array("input_image", inputs.flatten(), "I_SIZE") -print_array("verify_data", outputs.flatten(), "O_SIZE") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/vec-slide-conv.S b/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/vec-slide-conv.S deleted file mode 100644 index df139ab3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/vec-slide-conv.S +++ /dev/null @@ -1,217 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vectorized 2D separable convolution -//-------------------------------------------------------------------------- - - .text - .balign 4 - - .global vec_sep_conv -/* - * Calling convention: - * a0: size_t rows - * a1: size_t cols - * a2: size_t a_stride - * a3: size_t b_stride - * a4: const float *kw - * a5: const float *kh - * a6: const float *a - * a7: float *b - */ - -#define rows a0 -#define cols a1 -#define a_stride a2 -#define b_stride a3 -#define kw a4 -#define kh a5 -#define a a6 -#define b a7 - -#define ap t0 -#define bp t1 -#define vlen t2 -#define row_count t3 -#define VLEN_stride t4 -#define ap_4 t5 -#define ap_8 t6 - -#define row_check s0 -#define rows_odd s1 -#define slide_ptr s2 - -#define kw0 ft0 -#define kw1 ft1 -#define kw2 ft2 -#define kh0 ft3 -#define kh1 ft4 -#define kh2 ft5 - -#define vload0 v0 -#define vload1 v4 -#define vload2 v8 -#define vrow0 v16 -#define vrow1 v20 -#define vtmp v24 - -#define FRAMESIZE 32 - -vec_sep_conv: - addi sp, sp, -FRAMESIZE - sd s0, 0(sp) - sd s1, 8(sp) - sd s2, 16(sp) - - # load the kernel into scalar registers - flw kw0, 0(kw) - flw kw1, 4(kw) - flw kw2, 8(kw) - flw kh0, 0(kh) - flw kh1, 4(kh) - flw kh2, 8(kh) - - slli a_stride, a_stride, 2 - slli b_stride, b_stride, 2 - - mv row_check, rows - addi row_check, row_check, -2 - - andi rows_odd, rows, 1 - -# Prolog -loop_prolog: - mv ap, a - mv bp, b - mv row_count, row_check - - vsetvli vlen, cols, e32, m4, ta, ma - slli VLEN_stride, vlen, 2 - - # Load the first row and compute horizontal - vle32.v vload0, (ap) - add slide_ptr, ap, VLEN_stride # Bump slide_ptr to the n+1 element - flw ft6, (slide_ptr) - vfmul.vf vrow0, vload0, kw0 - vfslide1down.vf vload1, vload0, ft6 - flw ft7, 4(slide_ptr) - vfmacc.vf vrow0, kw1, vload1 - vfslide1down.vf vload2, vload1, ft7 - vfmacc.vf vrow0, kw2, vload2 - - add ap, ap, a_stride - add slide_ptr, ap, VLEN_stride - - # Load the second row and compute horizontal - vle32.v vload0, (ap) - flw ft6, (slide_ptr) - vfmul.vf vrow1, vload0, kw0 - vfslide1down.vf vload1, vload0, ft6 - flw ft7, 4(slide_ptr) - vfmacc.vf vrow1, kw1, vload1 - vfslide1down.vf vload2, vload1, ft7 - vfmacc.vf vrow1, kw2, vload2 - - add ap, ap, a_stride - add slide_ptr, ap, VLEN_stride - - # Begin the vertical computation with the first and second rows - vfmul.vf vrow0, vrow0, kh0 - vfmacc.vf vrow0, kh1, vrow1 - vfmul.vf vrow1, vrow1, kh0 - - # Load the third row and compute horizontal - vle32.v vload0, (ap) - flw ft6, (slide_ptr) - vfmul.vf vtmp, vload0, kw0 - vfslide1down.vf vload1, vload0, ft6 - flw ft7, 4(slide_ptr) - vfmacc.vf vtmp, kw1, vload1 - vfslide1down.vf vload2, vload1, ft7 - vfmacc.vf vtmp, kw2, vload2 - -# Main Loop -conv_loop: - add ap, ap, a_stride - add slide_ptr, ap, VLEN_stride - - vle32.v vload0, (ap) - flw ft6, (slide_ptr) - - vfmacc.vf vrow0, kh2, vtmp - - vfslide1down.vf vload1, vload0, ft6 - - vse32.v vrow0, (bp) - - flw ft7, 4(slide_ptr) - vfslide1down.vf vload2, vload1, ft7 - - vfmacc.vf vrow1, kh1, vtmp - vfmul.vf vrow0, vtmp, kh0 - - add ap, ap, a_stride - vfmul.vf vtmp, vload0, kw0 - add slide_ptr, ap, VLEN_stride - vle32.v vload0, (ap) - flw ft6, (slide_ptr) - vfmacc.vf vtmp, kw1, vload1 - vfslide1down.vf vload1, vload0, ft6 - flw ft7, 4(slide_ptr) - vfmacc.vf vtmp, kw2, vload2 - vfslide1down.vf vload2, vload1, ft7 - add bp, bp, b_stride - - vfmacc.vf vrow1, kh2, vtmp - vfmacc.vf vrow0, kh1, vtmp - vse32.v vrow1, (bp) - vfmul.vf vrow1, vtmp, kh0 - - vfmul.vf vtmp, vload0, kw0 - add bp, bp, b_stride - vfmacc.vf vtmp, kw1, vload1 - addi row_count, row_count, -2 - vfmacc.vf vtmp, kw2, vload2 - - - bgtz row_count, conv_loop - -epilog: - vfmacc.vf vrow0, kh2, vtmp - vse32.v vrow0, (bp) - - bnez rows_odd, row_loop_complete - - vfmacc.vf vrow1, kh1, vtmp - - add ap, ap, a_stride - add slide_ptr, ap, VLEN_stride - add bp, bp, b_stride - - vle32.v vload0, (ap) - flw ft6, (slide_ptr) - vfslide1down.vf vload1, vload0, ft6 - flw ft7, 4(slide_ptr) - vfslide1down.vf vload2, vload1, ft7 - - vfmul.vf vtmp, vload0, kw0 - vfmacc.vf vtmp, kw1, vload1 - vfmacc.vf vtmp, kw2, vload2 - - vfmacc.vf vrow1, kh2, vtmp - vse32.v vrow1, (bp) - -row_loop_complete: - add a, a, VLEN_stride - add b, b, VLEN_stride - - sub cols, cols, vlen - bnez cols, loop_prolog - -exit: - ld s0, 0(sp) - ld s1, 8(sp) - ld s2, 16(sp) - addi sp, sp, FRAMESIZE - - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/vec-slide-conv_main.c b/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/vec-slide-conv_main.c deleted file mode 100644 index a6a9ea70..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-slide-conv/vec-slide-conv_main.c +++ /dev/null @@ -1,42 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Separable Convolution Benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized 2D separable convolution implementation. - -#include "util.h" -#include -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_sep_conv(size_t, size_t, size_t, size_t, const float *, const float *, - const float *, float *); - -int main(int argc, char *argv[]) { - float results_data[O_SIZE] = {0}; - printf("slideconv OH,OW,KH,KW,IH,IW = %ld,%ld,%ld,%ld,%ld,%ld\n", OH, OW, KH, - KW, IH, IW); - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_sep_conv(OH, OW, IW, OW, input_k1, input_k2, input_image, results_data); - memset(results_data, 0, sizeof(results_data)); -#endif - - // Do the convolution - setStats(1); - vec_sep_conv(OH, OW, IW, OW, input_k1, input_k2, input_image, results_data); - setStats(0); - - // Check the results - return verifyFloat(O_SIZE, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-softmax/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-softmax/gen_data.py deleted file mode 100644 index df20a8d6..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-softmax/gen_data.py +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# arg1: vector size, arg2: filter size - -import random as rand -import numpy as np -import sys - - -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -def rand_matrix(N, dtype): - return np.random.rand(N).astype(dtype) - - -# SCRIPT - -if len(sys.argv) == 3: - channels = int(sys.argv[1]) - innerSize = int(sys.argv[2]) -else: - print("Error. Give me two arguments: the number of channels and the inner size.") - sys.exit() - -# Vector of samples -i = rand_matrix(channels * innerSize, np.float32).astype(np.float32) - -# Results buffer -buf = np.zeros(channels * innerSize, dtype=np.float32) -o_s = np.zeros(channels * innerSize, dtype=np.float32) -o_g = np.zeros(channels * innerSize, dtype=np.float32) - -# Create the file -print('.section .data,"aw",@progbits') -emit("channels", np.array(channels, dtype=np.uint64)) -emit("innerSize", np.array(innerSize, dtype=np.uint64)) -emit("i", i, "NR_LANES*4") -emit("buf", i, "NR_LANES*4") -emit("o_s", i, "NR_LANES*4") -emit("o_v", i, "NR_LANES*4") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-softmax/main.c b/bb-tests/workloads/src/CTest/rvv/vec-softmax/main.c deleted file mode 100644 index a4d95b69..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-softmax/main.c +++ /dev/null @@ -1,85 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include -#include - -#include "ara/util.h" -#include "softmax.h" -#include "util.h" -#include - -// Check the results using a threshold -#define CHECK - -// Sanity check to see that there are some precision differences -// between the two algorithms -// #define SANITY_CHECK - -// Sanity check to see the results -// #define PRINT_RESULTS - -#define THRESHOLD 0.1 - -extern uint64_t channels; -extern uint64_t innerSize; -extern float i[] __attribute__((aligned(32))); -extern float buf[] __attribute__((aligned(32))); -extern float o_s[] __attribute__((aligned(32))); -extern float o_v[] __attribute__((aligned(32))); - -int main() { - printf("SOFTMAX\n"); - printf("Channels: %lu\nInner Size: %lu\n", channels, innerSize); - - int64_t runtime; - int error = 0; - unsigned long cycles1, cycles2, instr2, instr1; - - printf("Scalar Softmax...\n"); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - softmax(i, o_s, buf, channels, innerSize); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - runtime = cycles2 - cycles1; - printf("The scalar SOFTMAX execution took %d cycles.\n", runtime); - - printf("Vector Softmax...\n"); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - softmax_vec(i, o_v, channels, innerSize); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - runtime = cycles2 - cycles1; - printf("The vector Softmax execution took %d cycles.\n", runtime); - - for (uint64_t k = 0; k < channels * innerSize; ++k) { - if (!similarity_check(o_s[k], o_v[k], THRESHOLD)) { - error = 1; - printf("Error at index %d. %x != %x\n", k, *(uint32_t *)(&o_v[k]), - *(uint32_t *)(&o_s[k])); - } - } - if (!error) - printf("Check okay. No errors.\n"); - - return error; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-softmax/softmax.c b/bb-tests/workloads/src/CTest/rvv/vec-softmax/softmax.c deleted file mode 100644 index 37a86196..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-softmax/softmax.c +++ /dev/null @@ -1,213 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#include -#include - -#include "riscv_vector.h" - -#include "ara/exp.h" - -// Our fdiv cannot receive any X in input -// The following macro is just a trick and should NOT be used -#define RESET_VREGS - -// Scalar implmentation inspired by OpenCV softmax: -// https://github.com/opencv/opencv/blob/master/modules/dnn/src/layers/softmax_layer.cpp -void softmax(const float *i, const float *o, const float *buf, - uint64_t channels, uint64_t innerSize) { - - // OpenCV names - float *srcPtr = (float *)i; - float *bufPtr = (float *)buf; - float *dstPtr = (float *)o; - - // Batch size == 1 - size_t outerSize = 1; - - // Steps - size_t outerStep = channels * innerSize; - size_t cnStep = innerSize; - - // Compute max along axis - for (size_t outerDim = 0; outerDim < outerSize; outerDim++) { - - size_t srcOffset = outerDim * outerStep; - size_t bufOffset = outerDim * cnStep; - - memcpy(bufPtr + bufOffset, srcPtr + srcOffset, innerSize * sizeof(float)); - - for (size_t cnDim = 1; cnDim < channels; cnDim++) { - for (size_t i = 0; i < innerSize; i++) { - bufPtr[bufOffset + i] = - fmax(bufPtr[bufOffset + i], srcPtr[srcOffset + cnDim * cnStep + i]); - } - } - - // Subtract max - for (size_t outerDim = 0; outerDim < outerSize; outerDim++) { - size_t srcOffset = outerDim * outerStep; - size_t bufOffset = outerDim * cnStep; - - for (size_t cnDim = 0; cnDim < channels; cnDim++) { - const int offset = srcOffset + cnDim * cnStep; - for (size_t i = 0; i < innerSize; i++) - dstPtr[offset + i] = srcPtr[offset + i] - bufPtr[bufOffset + i]; - } - } - - // Exponentiate - for (size_t outerDim = 0; outerDim < outerSize; outerDim++) { - size_t srcOffset = outerDim * outerStep; - - for (size_t cnDim = 0; cnDim < channels; cnDim++) { - const int offset = srcOffset + cnDim * cnStep; - for (size_t i = 0; i < innerSize; i++) - dstPtr[offset + i] = exp(dstPtr[offset + i]); - } - } - - // Sum exps and divide - for (size_t outerDim = 0; outerDim < outerSize; outerDim++) { - size_t srcOffset = outerDim * outerStep; - size_t bufOffset = outerDim * cnStep; - - // Sum exp along axis - for (size_t i = 0; i < innerSize; i++) - bufPtr[bufOffset + i] = 0.f; - - for (size_t cnDim = 0; cnDim < channels; cnDim++) { - const int offset = srcOffset + cnDim * cnStep; - for (size_t i = 0; i < innerSize; i++) - bufPtr[bufOffset + i] += dstPtr[offset + i]; - } - - // Divide by computed sum - for (size_t cnDim = 0; cnDim < channels; cnDim++) { - const int offset = srcOffset + cnDim * cnStep; - for (size_t i = 0; i < innerSize; i++) - dstPtr[offset + i] /= bufPtr[bufOffset + i]; - } - } - } -} - -void softmax_vec(const float *i, const float *o, uint64_t channels, - uint64_t innerSize) { - - /* ONLY FOR DEBUGGING PURPOSE. DELETE THE FOLLOWING ASM LINES - */ - // Clean the regs from Xes -#ifdef RESET_VREGS - volatile int temp; - asm volatile("vsetvli %0, zero, e32, m8, ta, ma" : "=r"(temp)); - - asm volatile("vmv.v.i v0, 0"); - asm volatile("vmv.v.i v8, 0"); - asm volatile("vmv.v.i v16, 0"); - asm volatile("vmv.v.i v24, 0"); -#endif - - size_t avl = innerSize; - size_t vl; - - // Stripmining pointers - float *_i = (float *)i; - float *_o = (float *)o; - // Channel pointers - float *__i = (float *)i; - float *__o = (float *)o; - - // Vector registers - vfloat32m1_t max_chunk_v; - vfloat32m1_t buf_chunk_v; - vfloat32m1_t num_chunk_v; - vfloat32m1_t den_chunk_v; - vfloat32m1_t res_chunk_v; - - // Stripmine on innerSize - for (vl = __riscv_vsetvl_e32m1(avl); avl > 0; avl -= vl) { - - vl = __riscv_vsetvl_e32m1(avl); - - /* - Calculate the maximum along the channel dimension - */ - - // Initialize the max vector - max_chunk_v = __riscv_vle32_v_f32m1(__i, vl); - // Bump the pointer - __i += innerSize; - for (uint64_t ch = 1; ch < channels; ++ch) { - // Load a chunk of the input vector - buf_chunk_v = __riscv_vle32_v_f32m1(__i, vl); - // Bump the channel pointer - __i += innerSize; - // Calculate the elm-wise maximum between the two chunks - max_chunk_v = __riscv_vfmax_vv_f32m1(max_chunk_v, buf_chunk_v, vl); - } - // Restore the channel pointer - __i = _i; - - /* - Fetch, subtract, exponentiate along the channel dimension - */ - - // Initialize accumulator - den_chunk_v = __riscv_vfmv_v_f_f32m1(0, vl); - for (uint64_t ch = 0; ch < channels; ++ch) { - // Fetch one chunk from channel ch - buf_chunk_v = __riscv_vle32_v_f32m1(__i, vl); - // Subtract the maximum - buf_chunk_v = __riscv_vfsub_vv_f32m1(buf_chunk_v, max_chunk_v, vl); - // Exponentiate - buf_chunk_v = __exp_f32m1(buf_chunk_v, vl); - // Store the numerator to memory - __riscv_vse32_v_f32m1(__o, buf_chunk_v, vl); - // Accumulate - den_chunk_v = __riscv_vfadd_vv_f32m1(den_chunk_v, buf_chunk_v, vl); - // Bump channel pointers - __i += innerSize; - __o += innerSize; - } - // Restore the pointers - __i = _i; - __o = _o; - - /* - Divide by the computed sum - */ - - for (uint64_t ch = 0; ch < channels; ++ch) { - // Load numerator from memory - num_chunk_v = __riscv_vle32_v_f32m1(__o, vl); - // Divide - res_chunk_v = __riscv_vfdiv_vv_f32m1(num_chunk_v, den_chunk_v, vl); - // Store the result to memory - __riscv_vse32_v_f32m1(__o, res_chunk_v, vl); - // Bump channel pointers - __o += innerSize; - } - // Bump stripmining pointers - _i += vl; - _o += vl; - // Reset channel pointers - __i = _i; - __o = _o; - } -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-softmax/softmax.h b/bb-tests/workloads/src/CTest/rvv/vec-softmax/softmax.h deleted file mode 100644 index 65c5beb9..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-softmax/softmax.h +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// Author: Matteo Perotti - -#ifndef _SOFTMAX_H_ -#define _SOFTMAX_H_ - -void softmax(const float *i, const float *o, const float *buf, - uint64_t channels, uint64_t innerSize); - -void softmax_vec(const float *i, const float *o, uint64_t channels, - uint64_t innerSize); - -#endif diff --git a/bb-tests/workloads/src/CTest/rvv/vec-spmv/gen_data.py b/bb-tests/workloads/src/CTest/rvv/vec-spmv/gen_data.py deleted file mode 100644 index 9fff2b32..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-spmv/gen_data.py +++ /dev/null @@ -1,174 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2021 ETH Zurich and University of Bologna. -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# // Author: Chi Zhang, ETH Zurich - - -# arg1: row, arg2: column, arg3: density -# default configuration: -# # INT32 idx -# # FP64 data - -import random -import numpy as np -import sys - - -# fun for froming file -def emit(name, array, alignment="8"): - print(".global %s" % name) - print(".balign " + alignment) - print("%s:" % name) - bs = array.tobytes() - for i in range(0, len(bs), 4): - s = "" - for n in range(4): - s += "%02x" % bs[i + 3 - n] - print(" .word 0x%s" % s) - - -# generate random CSR format sparse matrix -def randomCSR(num_row, num_col, density, element_byte): - non_zero = int(num_row * num_col * density) - # print("non_zero="+str(non_zero)) - # random insert - insert_list = [] - pool = list(range(num_row * num_col)) - for x in range(non_zero): - insert = random.choice(pool) - pool.remove(insert) - # print(insert) - insert_list.append(insert) - # print("inseting: "+str(x)+"/"+str(non_zero), end="\r") - pass - insert_list.sort() - # print(insert_list) - - # Count for p_row - p_row = [] - p_row.append(0) - acc_bar = num_col - acc_cnt = 0 - for x in range(non_zero): - # print("generate p_row: "+str(x)+"/"+str(non_zero), end="\r") - if insert_list[x] >= acc_bar: - p_row.append(x) - acc_bar = acc_bar + num_col - acc_cnt = acc_cnt + 1 - while insert_list[x] >= acc_bar: - p_row.append(x) - acc_bar = acc_bar + num_col - acc_cnt = acc_cnt + 1 - pass - pass - pass - for x in range(num_row - acc_cnt): - p_row.append(non_zero) - pass - # print(p_row) - - # generate indicies - index_list = [] - for x in range(num_row): - # print("generate index: "+str(x)+"/"+str(num_row), end="\r") - length = p_row[x + 1] - p_row[x] - row_idx_list = [] - pool = list(range(0, num_col * element_byte, element_byte)) - for x in range(length): - index = random.choice(pool) - pool.remove(index) - row_idx_list.append(index) - pass - row_idx_list.sort() - index_list = index_list + row_idx_list - pass - - # generate data - # print("start generate data") - data_list = [] - for x in range(non_zero): - # data_list.append(random.random()) - data_list.append(x) - pass - - # generate vector - # print("start generate vector") - vector_list = [] - for x in range(num_col): - vector_list.append(random.random()) - # vector_list.append(x) - pass - - return non_zero, p_row, index_list, data_list, vector_list - - pass - - -# SCRIPT - - -if len(sys.argv) == 4: - R = int(sys.argv[1]) - C = int(sys.argv[2]) - D = float(sys.argv[3]) -else: - print("Error. Give me one argument: the number of vector elements.") - sys.exit() - -data_type = np.float64 -idx_type = np.int32 -element_byte = 8 -idx_byte = 4 - -# generate sparse matrix -non_zero, p_row, index_list, data_list, vector_list = randomCSR(R, C, D, element_byte) - -# Create the file -print('.section .data,"aw",@progbits') -emit("R", np.array(R, dtype=np.uint64)) -emit("C", np.array(C, dtype=np.uint64)) -emit("NZ", np.array(non_zero, dtype=np.uint64)) -emit("CSR_PROW", np.array(p_row, dtype=idx_type), "NR_LANES*4") -emit("CSR_INDEX", np.array(index_list, dtype=idx_type), "NR_LANES*4") -emit("CSR_DATA", np.array(data_list, dtype=data_type), "NR_LANES*4") -emit("CSR_IN_VECTOR", np.array(vector_list, dtype=data_type), "NR_LANES*4") -emit("CSR_OUT_VECTOR", np.zeros([C], dtype=data_type), "NR_LANES*4") - - -# TSTEPS = 1 - -# # Fill in the extra data to align the matrices to 4*NrLanes in SW -# maxNrLanes = 16 -# maxAlignment = 4*maxNrLanes # [B] -# sizeOfDType = np.dtype(dtype).itemsize # [B] -# R_ext = int(R + (maxAlignment / sizeOfDType)) -# C_ext = int(C + (maxAlignment / sizeOfDType)) - -# # Vector of samples (padding is random since it does not impact performance) -# A = np.random.rand(R_ext, C_ext).astype(dtype) -# B = np.zeros([R_ext, C_ext], dtype=dtype) - -# Create the file -# print(".section .data,\"aw\",@progbits") -# emit("R", np.array(R, dtype=np.uint64)) -# emit("C", np.array(C, dtype=np.uint64)) -# emit("TSTEPS", np.array(TSTEPS, dtype=np.uint64)) -# emit("A_v", A, 'NR_LANES*4') -# emit("B_v", B, 'NR_LANES*4') -# if not OnlyVec: -# emit("A_s", A, 'NR_LANES*4') -# emit("B_s", B, 'NR_LANES*4') diff --git a/bb-tests/workloads/src/CTest/rvv/vec-spmv/main.c b/bb-tests/workloads/src/CTest/rvv/vec-spmv/main.c deleted file mode 100644 index 5565b212..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-spmv/main.c +++ /dev/null @@ -1,78 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Chi Zhang, ETH Zurich - -#include -#include - -#include "ara/spmv.h" -#include "util.h" -#include - -extern uint64_t R; -extern uint64_t C; -extern uint64_t NZ; - -extern int32_t CSR_PROW[] __attribute__((aligned(32), section(".l2"))); -extern int32_t CSR_INDEX[] __attribute__((aligned(32), section(".l2"))); -extern double CSR_DATA[] __attribute__((aligned(32), section(".l2"))); -extern double CSR_IN_VECTOR[] __attribute__((aligned(32), section(".l2"))); -extern double CSR_OUT_VECTOR[] __attribute__((aligned(32), section(".l2"))); - -int main() { - printf("SpMV\n"); - - unsigned long cycles1, cycles2, instr2, instr1; - double density = ((double)NZ) / (R * C); - double nz_per_row = ((double)NZ) / R; - -#if PREALLOCATE - spmv_csr_idx32(R, CSR_PROW, CSR_INDEX, CSR_DATA, CSR_IN_VECTOR, - CSR_OUT_VECTOR); -#endif - - printf( - "Calculating a (%d x %d) x %d sparse matrix vector multiplication...\n", - R, C, C); - printf("CSR format with %d nozeros: %ld nonzeros per 1000 elements, %ld " - "nonzeros per row \n", - NZ, (uint64_t)(density * 1000.0), (uint64_t)nz_per_row); - instr1 = read_csr(minstret); - cycles1 = read_csr(mcycle); - spmv_csr_idx32(R, CSR_PROW, CSR_INDEX, CSR_DATA, CSR_IN_VECTOR, - CSR_OUT_VECTOR); - asm volatile("fence"); - instr2 = read_csr(minstret); - cycles2 = read_csr(mcycle); - - // Metrics - int64_t runtime = cycles2 - cycles1; - float performance = 2.0 * NZ / runtime; - - printf("The execution took %d cycles.\n", runtime); - printf("The performance is %ld FLOPs/1000 cycles.\n", - (uint64_t)(1000.0 * performance)); - - printf("Verifying ...\n"); - if (spmv_verify(R, CSR_PROW, CSR_INDEX, CSR_DATA, CSR_IN_VECTOR, - CSR_OUT_VECTOR)) { - return 1; - } else { - printf("Passed.\n"); - } - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/dataset1.h deleted file mode 100644 index b195bf11..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/dataset1.h +++ /dev/null @@ -1,19 +0,0 @@ -#define DATA_SIZE 300 - -float input1_data[DATA_SIZE] = { - 2, 22, 41, 16, 28, 0, 9, 49, 37, 18, 17, 28, 6, 3, 47, 7, 29, 10, 40, - 7, 31, 10, 0, 28, 46, 17, 44, 29, 19, 44, 34, 11, 48, 0, 5, 44, 5, 37, - 14, 32, 21, 25, 15, 21, 33, 35, 38, 40, 15, 49, 33, 7, 43, 34, 18, 28, 23, - 13, 46, 12, 27, 32, 28, 25, 10, 4, 14, 35, 37, 33, 30, 18, 25, 27, 32, 46, - 9, 29, 4, 28, 13, 47, 11, 40, 16, 29, 47, 32, 45, 18, 12, 24, 45, 16, 41, - 15, 46, 29, 49, 19, 9, 27, 48, 32, 28, 49, 17, 49, 32, 40, 32, 3, 9, 10, - 5, 49, 42, 31, 3, 42, 14, 35, 17, 49, 7, 12, 45, 35, 44, 21, 13, 20, 28, - 26, 49, 35, 38, 0, 12, 24, 23, 5, 25, 43, 20, 34, 11, 20, 22, 14, 36, 14, - 33, 31, 15, 3, 11, 17, 46, 27, 14, 32, 5, 8, 30, 26, 30, 14, 19, 39, 17, - 40, 22, 36, 13, 37, 18, 37, 17, 4, 29, 49, 3, 13, 49, 42, 20, 39, 17, 26, - 25, 11, 27, 23, 45, 12, 38, 17, 12, 16, 38, 34, 29, 37, 7, 22, 1, 15, 6, - 37, 47, 27, 46, 23, 40, 27, 27, 46, 21, 39, 32, 17, 47, 44, 14, 33, 0, 25, - 2, 27, 4, 43, 4, 42, 22, 22, 29, 3, 30, 33, 19, 19, 14, 0, 40, 0, 48, - 8, 41, 14, 17, 19, 22, 26, 25, 9, 48, 45, 17, 27, 40, 49, 44, 44, 26, 2, - 47, 30, 35, 47, 17, 24, 28, 7, 44, 0, 1, 32, 28, 16, 33, 36, 21, 4, 21, - 36, 7, 14, 0, 19, 4, 34, 12, 45, 2, 23, 21, 40, 39, 36}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/root_approx_gendata.pl b/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/root_approx_gendata.pl deleted file mode 100755 index 646862de..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/root_approx_gendata.pl +++ /dev/null @@ -1,131 +0,0 @@ -#!/usr/bin/perl -w -#========================================================================== -# root_approx.pl -# -# Author: Generated -# Date: Today -# -(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm; -# -# Simple script which creates an input data set and the reference data -# for the given conditional operation. -# -ENDMSG - -use strict "vars"; -use warnings; -no warnings("once"); -use Getopt::Long; - -#-------------------------------------------------------------------------- -# Command line processing -#-------------------------------------------------------------------------- - -our %opts; - -sub usage() -{ - - print "\n"; - print " Usage: conditional_gendata.pl [options] \n"; - print "\n"; - print " Options:\n"; - print " --help print this message\n"; - print " --size size of input data [1000]\n"; - print " --seed random seed [1]\n"; - print "$usageMsg"; - - exit(); -} - -sub processCommandLine() -{ - - $opts{"help"} = 0; - $opts{"size"} = 300; - $opts{"seed"} = 1; - Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage(); - $opts{"help"} and usage(); - -} - -#-------------------------------------------------------------------------- -# Helper Functions -#-------------------------------------------------------------------------- -sub printArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - my $type = $_[2]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print $type." ".$arrayName."[DATA_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3d",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3d",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - my @input1_data; # x - my @input2_data; # y - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - my $valueX = int(rand(50)); # x - - push( @input1_data, $valueX ); - } - - print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n"; - printArray( "input1_data", \@input1_data, "float" ); # x -} - -main(); diff --git a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/vec-square_root.S b/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/vec-square_root.S deleted file mode 100644 index ad3ad4b7..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/vec-square_root.S +++ /dev/null @@ -1,32 +0,0 @@ - .text - .balign 4 - .global vec_root_approx - -# v1 = sqrt(v1) to almost 23 bits of precision. - -vec_root_approx: - vsetvli t1, a0, e32, m1, ta, mu - vle32.v v1, (a1) # load x values - sub a0, a0, t1 - slli t1, t1, 2 - fmv.w.x ft0, x0 # Mask off zero inputs - vmfne.vf v0, v1, ft0 # to avoid div by zero - vfrsqrt7.v v2, v1, v0.t # Estimate 1/sqrt(x) - vmfne.vf v0, v2, ft0, v0.t # Additionally mask off +inf inputs - li t0, 0x40400000 - vmv.v.x v4, t0 # Splat 3.0 - vfmul.vv v3, v1, v2, v0.t # x * est - vfnmsub.vv v3, v2, v4, v0.t # - x * est * est + 3 - vfmul.vv v3, v3, v2, v0.t # est * (-x * est * est + 3) - li t0, 0x3f000000 - fmv.w.x ft0, t0 # 0.5 - vfmul.vf v2, v3, ft0, v0.t # Estimate to 14 bits - vfmul.vv v3, v1, v2, v0.t # x * est - vfnmsub.vv v3, v2, v4, v0.t # - x * est * est + 3 - vfmul.vv v3, v3, v2, v0.t # est * (-x * est * est + 3) - vfmul.vf v2, v3, ft0, v0.t # Estimate to 23 bits - vfmul.vv v1, v2, v1, v0.t # x * 1/sqrt(x) - vse32.v v1, (a1) - add a1, a1, t1 # Bump pointer - bnez a0, vec_root_approx # Any more? - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/vec-square_root_main.c b/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/vec-square_root_main.c deleted file mode 100644 index f3e74eff..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-square-root-approx/vec-square_root_main.c +++ /dev/null @@ -1,37 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// square root approximation benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized conditional implementation. -// The input data (and reference data) should be generated using -// the root_approx_gendata.pl perl script and dumped to a file named -// dataset1.h. - -#include "util.h" -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" -#include - -//-------------------------------------------------------------------------- -// Main - -void vec_root_approx(size_t n, float x[]); - -int main(int argc, char *argv[]) { - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_root_approx(DATA_SIZE, input1_data); -#endif - - // Do the root - setStats(1); - vec_root_approx(DATA_SIZE, input1_data); - setStats(0); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-strlen/main.c b/bb-tests/workloads/src/CTest/rvv/vec-strlen/main.c deleted file mode 100644 index de4aa346..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-strlen/main.c +++ /dev/null @@ -1,32 +0,0 @@ -#include "util.h" -#include -#include -#include - -const char *input = - "Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod " - "tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim " - "veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea " - "commodo consequat. Duis aute irure dolor in reprehenderit in voluptate " - "velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint " - "occaecat cupidatat non proident, sunt in culpa qui officia deserunt " - "mollit anim id est laborum"; - -size_t strlen_rvv(const char *s); - -int main() { - size_t cycles1, cycles2; - size_t max = strlen(input); - printf("Performing strlen with max len = %ld\n", max); - - cycles1 = read_csr(mcycle); - for (size_t i = 0; i < max; i += 15) { - size_t r = strlen_rvv(input + i); - if (r != max - i) { - return 1; - } - } - cycles2 = read_csr(mcycle); - printf("The execution took %ld cycles.\n", cycles2 - cycles1); - return 0; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-strlen/vec_strlen.S b/bb-tests/workloads/src/CTest/rvv/vec-strlen/vec_strlen.S deleted file mode 100644 index 5b323815..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-strlen/vec_strlen.S +++ /dev/null @@ -1,17 +0,0 @@ -.text -.balign 4 -.global strlen_rvv -strlen_rvv: - mv a3, a0 -loop: - vsetvli a1, x0, e8, m8, ta, ma - vle8ff.v v8, (a3) - csrr a1, vl - vmseq.vi v0, v8, 0 - vfirst.m a2, v0 - add a3, a3, a1 - bltz a2, loop - add a0, a0, a1 - add a3, a3, a2 - sub a0, a3, a0 - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/dataset1.h deleted file mode 100644 index ffeebcdd..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/dataset1.h +++ /dev/null @@ -1,116 +0,0 @@ -#define DIM_M 32 -#define DIM_N 32 -#define ARRAY_SIZE 1024 - -float input_matrix[ARRAY_SIZE] = { - 94, 91, 7, 31, 65, 87, 56, 25, 45, 24, 22, 28, 8, 18, 79, 25, 41, 73, 91, - 80, 23, 34, 73, 42, 36, 51, 79, 30, 47, 81, 50, 41, 68, 79, 3, 47, 52, 91, - 17, 11, 66, 8, 11, 33, 82, 7, 67, 95, 20, 15, 80, 19, 64, 81, 57, 14, 50, - 31, 55, 80, 26, 54, 67, 31, 64, 25, 38, 53, 32, 93, 97, 35, 44, 71, 22, 93, - 58, 70, 56, 70, 98, 14, 10, 52, 14, 8, 17, 78, 78, 18, 16, 91, 65, 70, 74, - 81, 32, 3, 60, 37, 53, 82, 24, 46, 22, 96, 71, 44, 50, 98, 7, 24, 74, 13, - 62, 25, 96, 97, 90, 29, 27, 20, 84, 60, 28, 95, 81, 94, 24, 21, 40, 84, 88, - 66, 1, 81, 76, 18, 56, 47, 73, 25, 66, 44, 59, 26, 78, 2, 87, 10, 65, 16, - 44, 92, 53, 56, 29, 86, 31, 99, 54, 39, 76, 40, 26, 22, 85, 9, 11, 12, 73, - 18, 8, 27, 14, 61, 6, 4, 99, 44, 27, 75, 77, 4, 74, 30, 79, 55, 42, 72, - 25, 92, 54, 18, 95, 7, 71, 33, 98, 99, 63, 35, 85, 81, 29, 17, 33, 49, 36, - 88, 41, 27, 84, 42, 31, 53, 98, 19, 1, 56, 43, 43, 63, 47, 6, 89, 42, 58, - 74, 90, 7, 59, 98, 7, 31, 89, 45, 86, 47, 61, 72, 47, 20, 34, 91, 1, 6, - 12, 35, 70, 90, 13, 24, 93, 30, 7, 61, 29, 66, 86, 87, 27, 78, 36, 9, 6, - 79, 88, 49, 94, 75, 46, 93, 19, 64, 65, 46, 30, 28, 75, 39, 16, 38, 39, 82, - 48, 9, 3, 32, 15, 71, 55, 3, 73, 28, 92, 22, 59, 73, 19, 9, 80, 50, 60, - 37, 11, 69, 5, 78, 98, 34, 48, 37, 14, 34, 5, 10, 72, 15, 6, 81, 33, 88, - 74, 9, 16, 8, 64, 39, 40, 62, 63, 67, 63, 16, 61, 10, 14, 17, 43, 65, 40, - 41, 10, 34, 46, 63, 87, 5, 81, 26, 61, 76, 70, 44, 77, 31, 91, 3, 5, 9, - 53, 40, 31, 41, 71, 62, 31, 68, 62, 76, 2, 17, 12, 48, 5, 76, 26, 78, 79, - 16, 34, 6, 54, 7, 78, 4, 99, 77, 70, 99, 69, 83, 4, 98, 39, 28, 35, 16, - 7, 43, 13, 71, 56, 79, 38, 44, 29, 94, 96, 93, 53, 48, 27, 10, 74, 6, 80, - 74, 60, 40, 84, 22, 67, 47, 3, 27, 81, 62, 94, 32, 95, 48, 84, 70, 15, 83, - 96, 23, 37, 39, 62, 51, 31, 52, 95, 24, 35, 67, 80, 16, 74, 82, 1, 88, 42, - 51, 88, 70, 90, 19, 18, 25, 97, 40, 20, 65, 63, 81, 62, 73, 5, 35, 39, 17, - 66, 85, 51, 14, 87, 30, 27, 58, 3, 89, 43, 38, 6, 53, 43, 72, 83, 91, 11, - 73, 69, 6, 91, 67, 34, 18, 31, 5, 28, 74, 4, 8, 5, 39, 39, 21, 41, 6, - 13, 60, 74, 53, 41, 6, 90, 80, 30, 71, 35, 94, 29, 17, 30, 7, 57, 66, 59, - 7, 0, 74, 13, 25, 62, 93, 73, 12, 20, 79, 11, 15, 84, 0, 72, 73, 96, 96, - 19, 42, 67, 4, 25, 49, 1, 60, 93, 10, 46, 63, 2, 67, 70, 28, 88, 9, 44, - 14, 55, 18, 99, 64, 46, 40, 72, 84, 37, 59, 44, 23, 31, 14, 12, 74, 29, 64, - 54, 95, 94, 50, 25, 81, 15, 27, 27, 13, 11, 31, 76, 87, 59, 35, 76, 91, 61, - 64, 31, 22, 37, 56, 2, 66, 65, 90, 61, 17, 52, 69, 80, 49, 98, 61, 16, 58, - 54, 0, 59, 39, 76, 21, 83, 59, 3, 84, 75, 90, 59, 56, 2, 28, 5, 9, 7, - 40, 72, 23, 39, 86, 35, 36, 91, 17, 92, 17, 16, 27, 2, 74, 67, 92, 95, 22, - 7, 50, 92, 97, 8, 71, 33, 32, 51, 78, 72, 33, 8, 70, 66, 5, 7, 35, 21, - 59, 85, 69, 87, 3, 17, 53, 59, 80, 73, 15, 51, 25, 49, 57, 19, 25, 86, 29, - 20, 78, 65, 53, 7, 16, 48, 45, 50, 18, 80, 4, 64, 16, 88, 30, 72, 43, 19, - 36, 77, 48, 9, 65, 91, 94, 54, 1, 73, 83, 32, 12, 61, 79, 6, 9, 5, 56, - 74, 38, 56, 32, 68, 7, 68, 63, 57, 79, 49, 93, 40, 6, 13, 37, 62, 99, 58, - 78, 35, 86, 65, 93, 43, 55, 11, 30, 22, 79, 3, 33, 93, 71, 19, 11, 78, 60, - 51, 57, 72, 45, 61, 14, 21, 51, 0, 58, 1, 70, 7, 94, 50, 35, 12, 38, 24, - 47, 9, 91, 12, 73, 56, 58, 28, 46, 98, 99, 84, 89, 29, 74, 22, 66, 83, 26, - 83, 73, 5, 80, 84, 71, 57, 54, 56, 8, 26, 57, 56, 4, 12, 7, 40, 41, 47, - 68, 88, 44, 6, 9, 74, 75, 16, 20, 6, 48, 0, 11, 56, 19, 13, 4, 23, 62, - 40, 45, 15, 81, 38, 7, 30, 76, 87, 43, 85, 41, 10, 60, 65, 95, 51, 90, 21, - 37, 22, 26, 45, 89, 59, 81, 93, 87, 87, 49, 20, 39, 82, 99, 16, 14, 23, 63, - 80, 71, 7, 10, 31, 12, 65, 28, 5, 28, 38, 30, 19, 46, 94, 4, 8, 51, 7, - 60, 9, 89, 10, 57, 94, 56, 0, 42, 88, 25, 82, 18, 8, 93, 47, 15, 74, 70, - 51, 86, 84, 42, 13, 74, 97, 2, 57, 58, 7, 77, 11, 14, 58, 42, 95, 43, 85, - 53, 74, 9, 42, 52, 49, 52, 7, 38, 72, 9, 73, 99, 9, 20, 19, 69, 53, 67, - 96, 70, 1, 11, 20, 36, 44, 10, 68, 50, 22, 71, 28, 90, 84, 45, 4, 36, 96, - 86, 33, 56, 0, 8, 99, 24, 82, 52, 35, 96, 17, 80, 74, 0, 26, 50, 13, 47, - 83, 78, 56, 91, 38, 47, 51, 78, 6, 75, 51, 96, 76, 8, 81, 38, 37, -}; -float verify_data[ARRAY_SIZE] = { - 94, 68, 64, 32, 24, 54, 54, 6, 61, 32, 81, 76, 7, 6, 67, 30, 6, 15, 40, - 64, 56, 32, 78, 79, 30, 91, 7, 43, 10, 15, 9, 8, 91, 79, 25, 3, 21, 39, - 18, 89, 29, 15, 33, 70, 78, 80, 80, 27, 13, 84, 72, 31, 2, 51, 65, 6, 22, - 12, 40, 85, 31, 74, 73, 99, 7, 3, 38, 60, 40, 76, 95, 42, 66, 71, 88, 44, - 4, 74, 16, 58, 60, 0, 84, 22, 28, 78, 53, 9, 79, 73, 41, 41, 12, 70, 99, - 24, 31, 47, 53, 37, 84, 40, 7, 58, 86, 55, 74, 77, 99, 60, 74, 3, 74, 72, - 37, 37, 5, 72, 7, 5, 3, 56, 47, 10, 65, 51, 9, 82, 65, 52, 32, 53, 88, - 26, 71, 74, 87, 3, 9, 31, 77, 40, 82, 89, 53, 73, 59, 56, 9, 33, 16, 56, - 33, 58, 68, 60, 28, 86, 20, 52, 87, 91, 93, 82, 66, 22, 33, 90, 27, 73, 16, - 91, 70, 84, 1, 43, 41, 96, 44, 2, 7, 8, 48, 74, 93, 28, 88, 65, 5, 84, - 19, 35, 56, 17, 97, 24, 1, 85, 98, 7, 78, 28, 8, 3, 99, 22, 88, 38, 6, - 96, 23, 66, 40, 70, 45, 38, 71, 46, 44, 95, 28, 42, 69, 96, 25, 11, 35, 46, - 81, 9, 99, 59, 36, 92, 64, 5, 69, 67, 42, 6, 90, 19, 31, 65, 72, 66, 50, - 56, 19, 98, 6, 51, 38, 13, 53, 17, 45, 66, 44, 22, 76, 11, 63, 98, 9, 22, - 39, 9, 83, 47, 51, 53, 80, 42, 14, 90, 23, 5, 18, 32, 11, 99, 9, 90, 30, - 74, 67, 80, 24, 8, 71, 96, 18, 12, 35, 7, 6, 59, 40, 53, 4, 3, 88, 43, - 30, 67, 12, 61, 39, 7, 80, 68, 78, 84, 74, 21, 19, 97, 96, 74, 22, 11, 22, - 71, 56, 73, 85, 31, 79, 73, 62, 40, 98, 27, 70, 72, 71, 4, 74, 17, 86, 35, - 4, 7, 60, 89, 75, 37, 46, 2, 70, 0, 28, 33, 93, 44, 47, 18, 81, 89, 88, - 19, 63, 31, 39, 81, 90, 83, 35, 25, 29, 52, 35, 21, 64, 68, 51, 29, 16, 22, - 94, 57, 1, 26, 8, 82, 58, 50, 73, 8, 29, 45, 49, 9, 67, 41, 28, 62, 19, - 91, 94, 49, 64, 69, 36, 59, 16, 63, 57, 74, 20, 26, 4, 58, 11, 50, 18, 7, - 70, 98, 25, 27, 17, 86, 94, 80, 63, 71, 35, 94, 18, 11, 29, 1, 54, 80, 91, - 85, 88, 57, 72, 22, 6, 45, 8, 7, 20, 13, 79, 67, 56, 7, 66, 14, 33, 47, - 75, 50, 16, 62, 16, 32, 25, 73, 17, 60, 95, 49, 17, 69, 30, 79, 45, 66, 48, - 89, 51, 77, 36, 47, 25, 95, 70, 24, 44, 61, 49, 61, 46, 60, 61, 31, 7, 95, - 97, 69, 30, 93, 94, 98, 92, 87, 72, 49, 61, 83, 0, 59, 7, 11, 44, 83, 41, - 20, 98, 74, 59, 6, 36, 72, 93, 37, 10, 68, 43, 48, 40, 6, 7, 10, 50, 61, - 17, 3, 43, 93, 14, 26, 11, 81, 60, 14, 10, 78, 73, 15, 14, 13, 26, 4, 88, - 47, 19, 11, 14, 62, 13, 84, 20, 91, 57, 46, 25, 16, 16, 17, 19, 40, 21, 83, - 56, 93, 9, 58, 68, 56, 91, 80, 10, 62, 78, 99, 41, 20, 64, 69, 17, 76, 71, - 70, 65, 67, 66, 63, 81, 58, 27, 53, 36, 6, 51, 73, 19, 87, 89, 42, 50, 91, - 80, 19, 52, 25, 2, 44, 27, 34, 65, 5, 43, 2, 56, 15, 63, 34, 59, 2, 15, - 54, 2, 59, 77, 13, 0, 5, 13, 87, 10, 95, 22, 38, 23, 64, 14, 96, 87, 27, - 84, 91, 46, 78, 65, 17, 79, 83, 81, 18, 7, 67, 27, 0, 74, 80, 48, 37, 58, - 80, 4, 49, 57, 43, 71, 47, 34, 81, 8, 97, 10, 75, 42, 1, 30, 98, 40, 12, - 38, 96, 62, 31, 0, 70, 27, 59, 67, 73, 9, 62, 1, 84, 23, 20, 94, 85, 28, - 51, 73, 57, 17, 90, 65, 77, 31, 6, 28, 34, 41, 48, 44, 23, 73, 5, 74, 28, - 13, 39, 92, 15, 65, 99, 70, 71, 62, 39, 56, 53, 90, 78, 42, 14, 78, 29, 16, - 4, 53, 12, 75, 48, 10, 5, 29, 37, 5, 28, 13, 88, 11, 76, 95, 51, 91, 58, - 7, 57, 40, 82, 0, 74, 84, 6, 36, 50, 78, 27, 44, 74, 98, 35, 39, 37, 34, - 76, 94, 39, 35, 74, 25, 9, 31, 21, 22, 25, 94, 78, 94, 54, 45, 99, 42, 9, - 45, 75, 51, 31, 18, 20, 92, 30, 19, 70, 16, 14, 46, 26, 96, 62, 39, 4, 62, - 44, 76, 83, 7, 49, 54, 35, 50, 56, 15, 16, 88, 42, 4, 51, 79, 55, 16, 84, - 53, 79, 1, 90, 38, 34, 63, 78, 93, 51, 17, 8, 93, 14, 87, 59, 50, 57, 1, - 86, 35, 8, 81, 14, 25, 52, 36, 96, 30, 80, 91, 60, 56, 55, 56, 13, 39, 5, - 87, 79, 53, 31, 66, 5, 73, 55, 59, 3, 92, 19, 73, 65, 12, 26, 38, 23, 82, - 49, 96, 76, 47, 26, 65, 28, 29, 42, 43, 24, 82, 10, 5, 16, 48, 52, 85, 39, - 12, 18, 35, 84, 97, 25, 83, 93, 38, 57, 7, 63, 18, 52, 86, 8, 81, 54, 70, - 95, 86, 72, 43, 93, 48, 72, 81, 34, 27, 95, 51, 39, 20, 99, 76, 75, 8, 86, - 32, 43, 24, 56, 30, 80, 8, 7, 33, 81, 50, 67, 74, 81, 31, 25, 63, 30, 9, - 15, 26, 6, 10, 24, 14, 21, 79, 64, 91, 90, 71, 29, 12, 55, 47, 4, 76, 71, - 93, 38, 56, 38, 41, 31, 81, 94, 99, 92, 47, 7, 3, 6, 61, 54, 74, 35, 87, - 41, 11, 46, 61, 59, 33, 20, 61, 11, 9, 12, 87, 7, 47, 72, 0, 37, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/gendata.py deleted file mode 100755 index 54bde6c3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/gendata.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 - -# Script for generating a basic transpose test case - -import numpy as np - -dim_m = 32 -dim_n = 32 - -input_matrix = np.random.randint(0, 100, size=(dim_m, dim_n), dtype=np.int32) -transpose_matrix = input_matrix.T - -print( - """#define DIM_M {} -#define DIM_N {} -#define ARRAY_SIZE {} - -""".format( - dim_m, dim_n, dim_m * dim_n - ) -) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=8): - print("{} {}[{}] = {{".format(data_type, name, data_size)) - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print_array("input_matrix", input_matrix.flatten(), "ARRAY_SIZE") -print_array("verify_data", input_matrix.T.flatten(), "ARRAY_SIZE") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/vec-transpose.S b/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/vec-transpose.S deleted file mode 100644 index d7402c04..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/vec-transpose.S +++ /dev/null @@ -1,89 +0,0 @@ - .text - .balign 4 - .global vec_transpose -# RV64IDV system -# -# void -# vec_transpose(size_t n, -# size_t m, -# const float*a, // m * n matrix -# float*b, // n * m matrix -# - -############### UNOPTIMIZED ###################### - -#define n a0 -#define m a1 -#define ap a2 -#define bp a3 - -#define astride t0 -#define bstride t1 -#define nvl t2 -#define amp t3 -#define bmp t4 -#define mt t5 -#define nt t6 - -#define bnp a4 - - -vec_transpose: - # Check for zero size matrices - beqz n, exit - beqz m, exit - - # Convert elements strides to byte strides. - slli astride, n, 2 - slli bstride, m, 2 - - slti t6, m, 4 - bnez t6, end_rows - -a_row_loop: - mv mt, m - - mv amp, ap - mv bmp, bp - -a_col_loop: - vsetvli nvl, mt, e32, m1, ta, ma - - mv bnp, bmp - - // Load the input matrix using strided segment loads - vlsseg4e32.v v0, (amp), astride - - // Store the transposed output matrix using unit stride stores - vse32.v v0, (bnp) - add bnp, bnp, bstride - vse32.v v1, (bnp) - add bnp, bnp, bstride - vse32.v v2, (bnp) - add bnp, bnp, bstride - vse32.v v3, (bnp) - - slli a5, nvl, 2 - add bmp, bmp, a5 - - mul a5, astride, nvl - add amp, amp, a5 - - sub mt, mt, nvl - - bnez mt, a_col_loop - - addi n, n, -4 - - slli a5, bstride, 2 - add bp, bp, a5 - - addi ap, ap, 16 - - bnez n, a_row_loop - - -end_rows: - -exit: - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/vec-transpose_main.c b/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/vec-transpose_main.c deleted file mode 100644 index 61fbcb3e..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-load/vec-transpose_main.c +++ /dev/null @@ -1,37 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Transpose benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized matrix transpose implementation. - -#include "util.h" -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_transpose(size_t, size_t, const float *, float *); - -int main(int argc, char *argv[]) { - float results_data[ARRAY_SIZE] = {0}; - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_transpose(DIM_N, DIM_M, input_matrix, results_data); - memset(results_data, 0, sizeof(results_data)); -#endif - - setStats(1); - vec_transpose(DIM_N, DIM_M, input_matrix, results_data); - setStats(0); - - // Check the results - return verifyFloat(ARRAY_SIZE, results_data, verify_data); -} diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/dataset1.h b/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/dataset1.h deleted file mode 100644 index 39ec76e8..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/dataset1.h +++ /dev/null @@ -1,116 +0,0 @@ -#define DIM_M 32 -#define DIM_N 32 -#define ARRAY_SIZE 1024 - -float input_matrix[ARRAY_SIZE] = { - 44, 76, 26, 36, 98, 42, 0, 26, 30, 53, 44, 9, 72, 4, 58, 54, 28, 78, 47, - 42, 64, 93, 96, 44, 67, 53, 82, 21, 78, 84, 12, 95, 60, 3, 42, 54, 79, 74, - 48, 81, 41, 51, 13, 86, 16, 4, 8, 69, 71, 44, 19, 11, 53, 49, 97, 35, 93, - 87, 4, 87, 36, 54, 2, 70, 33, 34, 33, 5, 18, 33, 76, 12, 90, 61, 38, 49, - 85, 86, 62, 0, 23, 33, 70, 79, 93, 28, 36, 54, 35, 98, 95, 51, 41, 81, 45, - 21, 17, 4, 80, 85, 14, 99, 83, 78, 69, 42, 90, 25, 46, 93, 74, 78, 17, 64, - 51, 89, 42, 77, 1, 46, 65, 85, 28, 81, 0, 87, 22, 9, 72, 55, 27, 17, 86, - 68, 96, 85, 91, 44, 20, 29, 87, 44, 98, 81, 85, 38, 4, 70, 72, 79, 99, 38, - 45, 43, 0, 11, 99, 81, 36, 58, 61, 63, 44, 72, 33, 25, 15, 51, 85, 66, 47, - 57, 21, 82, 6, 59, 6, 60, 80, 66, 89, 21, 92, 36, 5, 87, 51, 24, 96, 43, - 9, 55, 85, 26, 19, 97, 10, 19, 58, 33, 28, 9, 47, 35, 36, 0, 30, 45, 37, - 61, 76, 41, 69, 67, 35, 90, 16, 43, 41, 10, 3, 55, 30, 90, 22, 57, 12, 31, - 85, 16, 76, 72, 8, 55, 38, 92, 33, 71, 66, 7, 82, 27, 77, 88, 67, 20, 11, - 37, 70, 74, 19, 39, 87, 61, 7, 57, 36, 86, 73, 99, 25, 82, 82, 10, 9, 61, - 96, 89, 76, 33, 3, 48, 12, 69, 53, 46, 85, 35, 73, 99, 51, 8, 12, 95, 39, - 23, 79, 97, 6, 10, 2, 98, 90, 51, 19, 29, 12, 24, 2, 6, 80, 46, 67, 16, - 43, 42, 82, 56, 24, 84, 88, 55, 63, 79, 21, 83, 51, 68, 67, 17, 89, 99, 26, - 20, 27, 0, 52, 21, 26, 25, 71, 83, 44, 28, 46, 89, 63, 40, 77, 93, 31, 77, - 48, 96, 79, 69, 0, 15, 69, 21, 17, 58, 87, 21, 2, 15, 56, 32, 60, 17, 86, - 94, 3, 75, 57, 83, 31, 21, 93, 89, 83, 74, 17, 24, 21, 43, 6, 18, 56, 2, - 93, 87, 85, 78, 80, 11, 93, 24, 97, 58, 2, 38, 67, 57, 13, 96, 69, 28, 23, - 13, 76, 86, 27, 82, 62, 26, 74, 42, 8, 14, 34, 71, 61, 68, 47, 25, 26, 58, - 90, 8, 23, 77, 83, 49, 91, 28, 61, 57, 2, 3, 39, 54, 23, 57, 99, 53, 48, - 11, 53, 97, 56, 3, 53, 46, 22, 16, 56, 25, 41, 6, 67, 61, 15, 82, 12, 44, - 52, 85, 86, 4, 51, 23, 96, 36, 43, 53, 71, 17, 26, 43, 58, 90, 24, 65, 56, - 93, 32, 52, 75, 20, 53, 24, 78, 2, 72, 43, 92, 67, 28, 93, 55, 60, 10, 21, - 10, 65, 89, 10, 46, 54, 13, 19, 91, 39, 4, 41, 93, 23, 4, 36, 26, 49, 71, - 64, 77, 69, 63, 38, 56, 84, 98, 94, 75, 53, 45, 93, 61, 33, 34, 31, 25, 34, - 37, 13, 11, 48, 89, 52, 27, 39, 84, 34, 81, 81, 47, 83, 54, 35, 78, 62, 30, - 84, 16, 4, 81, 29, 24, 55, 57, 29, 1, 90, 10, 28, 22, 69, 37, 15, 53, 90, - 69, 54, 58, 88, 38, 12, 16, 35, 88, 86, 13, 16, 27, 28, 93, 12, 49, 63, 92, - 65, 40, 73, 50, 8, 16, 37, 13, 98, 38, 2, 80, 39, 75, 56, 28, 47, 94, 33, - 81, 79, 48, 41, 20, 0, 47, 57, 52, 36, 42, 4, 9, 86, 73, 3, 73, 87, 48, - 94, 0, 36, 75, 20, 17, 76, 99, 18, 61, 50, 77, 8, 72, 18, 83, 33, 29, 98, - 17, 21, 62, 17, 36, 30, 87, 4, 65, 89, 10, 85, 31, 42, 34, 10, 19, 28, 31, - 48, 94, 61, 83, 36, 35, 0, 5, 90, 62, 58, 6, 98, 66, 60, 27, 5, 15, 51, - 64, 1, 51, 86, 5, 18, 53, 23, 45, 46, 7, 47, 97, 0, 10, 51, 64, 42, 46, - 1, 11, 37, 90, 22, 21, 92, 72, 55, 62, 57, 24, 84, 26, 21, 6, 39, 35, 48, - 70, 89, 46, 83, 40, 79, 31, 89, 55, 8, 85, 83, 81, 73, 22, 62, 73, 9, 35, - 78, 84, 77, 89, 42, 67, 55, 82, 74, 78, 66, 92, 78, 56, 53, 86, 97, 33, 68, - 56, 23, 7, 17, 14, 20, 20, 14, 53, 87, 4, 47, 18, 36, 10, 80, 63, 88, 49, - 81, 46, 5, 11, 80, 39, 54, 28, 98, 47, 76, 34, 81, 5, 55, 25, 78, 56, 40, - 17, 14, 59, 54, 39, 87, 16, 53, 25, 82, 68, 83, 67, 92, 83, 7, 77, 20, 68, - 33, 15, 14, 32, 99, 43, 55, 18, 50, 57, 35, 99, 49, 46, 4, 86, 19, 54, 64, - 93, 6, 59, 50, 36, 88, 33, 41, 6, 25, 67, 17, 13, 56, 47, 84, 93, 72, 47, - 3, 39, 60, 75, 56, 26, 32, 21, 26, 88, 26, 75, 95, 85, 55, 0, 5, 27, 10, - 89, 63, 38, 39, 65, 10, 74, 13, 72, 17, 28, 39, 4, 52, 67, 62, 22, 69, 70, - 17, 79, 20, 14, 91, 68, 80, 77, 54, 90, 31, 75, 89, 29, 85, 74, 50, 0, 19, - 35, 84, 38, 88, 91, 80, 33, 86, 46, 48, 91, 53, 7, 24, 74, 74, 80, 33, 16, - 40, 61, 58, 73, 2, 8, 81, 46, 19, 77, 10, 43, 85, 14, 86, 63, 51, 26, 76, - 1, 12, 66, 48, 70, 12, 79, 24, 66, 11, 14, 77, 10, 94, 53, 34, 20, 62, 33, - 64, 73, 77, 53, 39, 60, 11, 20, 90, 30, 55, 83, 47, 88, 26, 34, 4, 60, 15, - 19, 61, 87, 64, 9, 21, 17, 57, 16, 79, 22, 70, 11, 16, 24, 85, 89, 74, 37, - 40, 45, 54, 60, 44, 59, 52, 40, 21, 64, 59, 39, 95, 87, 44, 48, 1, -}; -float verify_data[ARRAY_SIZE] = { - 44, 60, 33, 17, 72, 61, 85, 22, 36, 6, 89, 87, 80, 26, 41, 53, 71, 47, 16, - 81, 72, 5, 11, 22, 53, 59, 86, 88, 14, 80, 14, 9, 76, 3, 34, 4, 55, 63, - 26, 57, 86, 10, 99, 21, 11, 58, 6, 24, 64, 83, 35, 79, 18, 90, 37, 62, 87, - 54, 19, 26, 91, 33, 77, 21, 26, 42, 33, 80, 27, 44, 19, 12, 73, 2, 26, 2, - 93, 90, 67, 78, 77, 54, 88, 48, 83, 62, 90, 73, 4, 39, 54, 75, 68, 16, 10, - 17, 36, 54, 5, 85, 17, 72, 97, 31, 99, 98, 20, 15, 24, 8, 61, 2, 69, 35, - 86, 41, 33, 58, 22, 9, 47, 87, 64, 95, 80, 40, 94, 57, 98, 79, 18, 14, 86, - 33, 10, 85, 25, 90, 27, 56, 97, 23, 15, 72, 63, 78, 13, 20, 29, 6, 21, 35, - 18, 16, 93, 85, 77, 61, 53, 16, 42, 74, 33, 99, 68, 25, 19, 16, 82, 51, 0, - 32, 58, 77, 82, 43, 38, 62, 16, 0, 98, 98, 92, 78, 36, 53, 6, 55, 54, 58, - 34, 79, 0, 48, 76, 83, 96, 15, 58, 76, 82, 19, 52, 60, 2, 83, 12, 92, 56, - 30, 27, 47, 17, 66, 72, 84, 10, 25, 59, 0, 90, 73, 20, 22, 26, 81, 12, 78, - 85, 51, 33, 72, 10, 29, 21, 17, 38, 49, 44, 67, 84, 84, 28, 57, 21, 60, 55, - 77, 80, 82, 50, 5, 31, 2, 62, 70, 30, 41, 90, 69, 91, 85, 28, 8, 9, 12, - 26, 86, 67, 91, 52, 28, 98, 16, 93, 52, 62, 27, 62, 89, 63, 68, 36, 27, 75, - 8, 33, 11, 53, 51, 61, 42, 44, 66, 9, 55, 61, 24, 25, 94, 57, 28, 85, 93, - 94, 4, 12, 36, 17, 5, 57, 42, 88, 83, 88, 10, 89, 81, 64, 16, 44, 13, 38, - 90, 20, 47, 47, 38, 96, 2, 71, 3, 13, 61, 86, 55, 75, 81, 49, 42, 36, 15, - 24, 67, 49, 67, 33, 89, 29, 46, 73, 24, 9, 86, 49, 25, 29, 57, 35, 92, 89, - 6, 83, 75, 96, 57, 4, 60, 53, 29, 63, 4, 30, 51, 84, 55, 81, 92, 41, 63, - 85, 19, 77, 85, 72, 16, 85, 46, 87, 21, 36, 33, 76, 80, 44, 57, 69, 2, 51, - 10, 45, 24, 92, 9, 87, 64, 26, 82, 46, 83, 6, 38, 74, 77, 53, 89, 4, 4, - 86, 93, 44, 82, 0, 71, 33, 46, 28, 83, 28, 3, 23, 21, 93, 55, 65, 86, 4, - 1, 21, 74, 5, 7, 25, 39, 50, 10, 39, 74, 58, 8, 62, 74, 98, 6, 30, 66, - 3, 67, 46, 31, 23, 39, 96, 10, 61, 57, 40, 73, 65, 51, 6, 78, 11, 77, 67, - 65, 0, 43, 60, 37, 54, 69, 0, 78, 81, 59, 45, 7, 48, 16, 89, 21, 13, 54, - 36, 65, 33, 29, 73, 3, 89, 86, 39, 66, 80, 20, 17, 10, 19, 85, 11, 40, 28, - 71, 23, 17, 85, 6, 37, 82, 12, 43, 63, 93, 76, 23, 43, 89, 34, 1, 50, 73, - 10, 5, 35, 92, 39, 68, 13, 74, 35, 14, 20, 45, 78, 44, 33, 64, 38, 60, 61, - 27, 69, 42, 40, 89, 86, 57, 53, 10, 31, 90, 8, 87, 85, 18, 48, 78, 54, 33, - 56, 13, 84, 86, 90, 54, 47, 19, 70, 51, 4, 80, 76, 77, 53, 82, 77, 83, 27, - 99, 71, 46, 25, 10, 16, 48, 31, 53, 70, 56, 28, 15, 47, 72, 38, 63, 30, 60, - 42, 11, 79, 89, 70, 66, 41, 88, 46, 56, 93, 74, 82, 53, 17, 54, 34, 28, 37, - 94, 42, 23, 89, 53, 98, 14, 84, 17, 88, 51, 55, 44, 64, 53, 93, 42, 72, 89, - 69, 67, 85, 24, 31, 17, 62, 48, 26, 13, 37, 22, 13, 0, 34, 45, 46, 86, 47, - 32, 93, 28, 91, 26, 83, 59, 93, 49, 28, 77, 79, 21, 67, 20, 35, 84, 77, 24, - 26, 11, 43, 19, 13, 69, 98, 36, 10, 46, 83, 97, 76, 99, 72, 39, 80, 76, 47, - 52, 96, 97, 36, 1, 99, 92, 35, 11, 73, 88, 48, 21, 74, 53, 58, 91, 11, 37, - 38, 75, 19, 7, 40, 33, 34, 43, 47, 4, 33, 1, 88, 40, 44, 35, 54, 46, 38, - 36, 90, 37, 99, 55, 96, 43, 42, 97, 90, 39, 48, 15, 2, 20, 28, 47, 79, 68, - 81, 55, 3, 52, 86, 12, 26, 21, 67, 93, 35, 65, 45, 5, 16, 70, 51, 63, 79, - 6, 8, 56, 24, 4, 89, 53, 80, 17, 31, 97, 31, 56, 5, 18, 39, 67, 46, 66, - 34, 64, 53, 87, 98, 85, 43, 87, 43, 74, 8, 79, 69, 18, 14, 3, 65, 41, 52, - 90, 39, 76, 48, 0, 89, 23, 55, 50, 60, 62, 48, 48, 4, 59, 82, 4, 95, 28, - 0, 51, 41, 19, 12, 21, 0, 56, 34, 53, 56, 93, 27, 69, 75, 99, 94, 10, 55, - 7, 25, 57, 75, 22, 91, 70, 60, 39, 21, 87, 51, 81, 11, 24, 10, 39, 95, 83, - 15, 2, 71, 46, 93, 23, 39, 54, 56, 18, 61, 51, 8, 17, 78, 35, 56, 69, 53, - 12, 15, 95, 78, 36, 41, 0, 99, 96, 3, 87, 39, 51, 69, 93, 61, 22, 32, 4, - 84, 58, 28, 61, 83, 64, 85, 14, 56, 99, 26, 70, 7, 79, 19, 87, 84, 54, 81, - 87, 81, 43, 55, 61, 23, 68, 21, 87, 68, 16, 52, 36, 34, 88, 47, 50, 36, 42, - 83, 20, 40, 49, 32, 17, 24, 24, 61, 44, 12, 2, 45, 22, 36, 9, 30, 7, 79, - 67, 17, 85, 47, 56, 75, 26, 81, 38, 94, 77, 35, 46, 81, 20, 17, 46, 21, 79, - 74, 66, 87, 48, 95, 70, 21, 9, 58, 55, 90, 57, 97, 17, 58, 78, 25, 25, 20, - 49, 81, 12, 33, 8, 0, 1, 73, 14, 14, 4, 26, 20, 74, 11, 64, 1, -}; diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/gendata.py b/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/gendata.py deleted file mode 100755 index 54bde6c3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/gendata.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 - -# Script for generating a basic transpose test case - -import numpy as np - -dim_m = 32 -dim_n = 32 - -input_matrix = np.random.randint(0, 100, size=(dim_m, dim_n), dtype=np.int32) -transpose_matrix = input_matrix.T - -print( - """#define DIM_M {} -#define DIM_N {} -#define ARRAY_SIZE {} - -""".format( - dim_m, dim_n, dim_m * dim_n - ) -) - - -def print_array(name, data, data_size, data_type="float", data_fmt="{}", fold=8): - print("{} {}[{}] = {{".format(data_type, name, data_size)) - for i in range(0, len(data), fold): - print( - " ", ", ".join(data_fmt.format(x) for x in data[i : i + fold]), ",", sep="" - ) - print("};") - - -print_array("input_matrix", input_matrix.flatten(), "ARRAY_SIZE") -print_array("verify_data", input_matrix.T.flatten(), "ARRAY_SIZE") diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/vec-transpose.S b/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/vec-transpose.S deleted file mode 100644 index e560b9a1..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/vec-transpose.S +++ /dev/null @@ -1,90 +0,0 @@ - .text - .balign 4 - .global vec_transpose -# RV64IDV system -# -# void -# vec_transpose(size_t n, -# size_t m, -# const float*a, // m * n matrix -# float*b, // n * m matrix -# - -############### UNOPTIMIZED ###################### - -#define n a0 -#define m a1 -#define ap a2 -#define bp a3 - -#define astride t0 -#define bstride t1 -#define nvl t2 -#define amp t3 -#define bnp t4 -#define mt t5 -#define nt t6 -#define anp a4 - - -vec_transpose: - # Check for zero size matrices - beqz n, exit - beqz m, exit - - # Convert elements strides to byte strides. - slli astride, n, 2 - slli bstride, m, 2 - - slti t6, m, 4 - bnez t6, end_rows - -a_row_loop: - mv nt, n - - mv anp, ap - mv bnp, bp - -a_col_loop: - vsetvli nvl, nt, e32, m1, ta, ma - - mv amp, anp - - // Load the input matrix with unit stride - vle32.v v0, (amp) - add amp, amp, astride - vle32.v v1, (amp) - add amp, amp, astride - vle32.v v2, (amp) - add amp, amp, astride - vle32.v v3, (amp) - - // Output the transpose using strided segment store - vssseg4e32.v v0, (bnp), bstride - - slli a5, nvl, 2 - add anp, anp, a5 - - mul a5, bstride, nvl - add bnp, bnp, a5 - - sub nt, nt, nvl - - bnez nt, a_col_loop - - mv nt, n - addi m, m, -4 - - slli a5, astride, 2 - add ap, ap, a5 - - addi bp, bp, 16 - - bnez m, a_row_loop - - -end_rows: - # Not done - -exit: - ret diff --git a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/vec-transpose_main.c b/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/vec-transpose_main.c deleted file mode 100644 index 61fbcb3e..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vec-transpose-store/vec-transpose_main.c +++ /dev/null @@ -1,37 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Transpose benchmark -//-------------------------------------------------------------------------- -// -// This benchmark tests a vectorized matrix transpose implementation. - -#include "util.h" -#include - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "dataset1.h" - -//-------------------------------------------------------------------------- -// Main - -void *vec_transpose(size_t, size_t, const float *, float *); - -int main(int argc, char *argv[]) { - float results_data[ARRAY_SIZE] = {0}; - -#if PREALLOCATE - // If needed we preallocate everything in the caches - vec_transpose(DIM_N, DIM_M, input_matrix, results_data); - memset(results_data, 0, sizeof(results_data)); -#endif - - setStats(1); - vec_transpose(DIM_N, DIM_M, input_matrix, results_data); - setStats(0); - - // Check the results - return verifyFloat(ARRAY_SIZE, results_data, verify_data); -} From e67d6f8f67a6b48e2c7b7fde81a2b8ae376471bf Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Thu, 18 Dec 2025 13:01:39 +0800 Subject: [PATCH 011/238] [arch/memdomain] refactor: made some adjustments to the architecture details to prepare for backend virtualization. (#19) --- .../framework/memdomain/DomainDecoder.scala | 3 +- .../framework/memdomain/MemController.scala | 10 ++-- .../scala/framework/memdomain/MemDomain.scala | 47 +++++++++++-------- .../scala/framework/memdomain/MemLoader.scala | 43 +++++++++-------- .../scala/framework/memdomain/MemStorer.scala | 47 ++++++++++--------- .../framework/memdomain/Translator.scala | 8 ++-- 6 files changed, 89 insertions(+), 69 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/DomainDecoder.scala index 10b92406..3d9878de 100644 --- a/arch/src/main/scala/framework/memdomain/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/DomainDecoder.scala @@ -11,6 +11,7 @@ import org.chipsalliance.cde.config.Parameters // Detailed decode output for Mem domain class MemDecodeCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { + private val numBanks = b.sp_banks + b.acc_banks val is_load = Bool() val is_store = Bool() @@ -22,7 +23,7 @@ class MemDecodeCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bun // Scratchpad address and bank information // 3 bits, supports 8 banks (SPAD+ACC) - val sp_bank = UInt(log2Up(b.sp_banks + b.acc_banks).W) + val sp_bank = UInt(log2Up(numBanks).W) // 12 bits, uses SPAD row count (sufficient to accommodate ACC's 10-bit address) val sp_bank_addr = UInt(log2Up(b.spad_bank_entries).W) diff --git a/arch/src/main/scala/framework/memdomain/MemController.scala b/arch/src/main/scala/framework/memdomain/MemController.scala index 0ed8df63..e7122058 100644 --- a/arch/src/main/scala/framework/memdomain/MemController.scala +++ b/arch/src/main/scala/framework/memdomain/MemController.scala @@ -15,7 +15,7 @@ import framework.memdomain.pmc.MemCyclePMC import freechips.rocketchip.tilelink.TLEdgeOut import freechips.rocketchip.rocket.TLBPTWIO import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} +import framework.balldomain.blink.{SramReadWithRobId, SramWriteWithRobId, SramReadWithInfo, SramWriteWithInfo} import framework.switcher.{ToPhysicalLine, ToVirtualLine} /** @@ -33,10 +33,10 @@ class MemController(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEd // SRAM read/write interface - used by load/store val interdma = new Bundle { - val sramread = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val sramwrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accread = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accwrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val sramread = Vec(b.sp_banks, Flipped(new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) + val sramwrite = Vec(b.sp_banks, Flipped(new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + val accread = Vec(b.acc_banks, Flipped(new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) + val accwrite = Vec(b.acc_banks, Flipped(new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) } // DMA interface - used by Outer DRAM controller diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 4881eb03..b36723fa 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -90,33 +90,42 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu memController.io.tlbExp <> io.tlbExp // Connect MemLoader and MemStorer to MemController's DMA interface + + val toVirtualLines0 = Module(new ToVirtualLine()(b, p)) + val toPhysicalLines0 = Module(new ToPhysicalLine()(b, p)) - memController.io.interdma.sramwrite <> translator.io.dma_in.sramwrite - memController.io.interdma.accwrite <>translator.io.dma_in.accwrite - memController.io.interdma.sramread <> translator.io.dma_in.sramread - memController.io.interdma.accread <> translator.io.dma_in.accread + memController.io.interdma.sramwrite <> toVirtualLines0.io.sramWrite_i + memController.io.interdma.accwrite <> toVirtualLines0.io.accWrite_i + memController.io.interdma.sramread <> toVirtualLines0.io.sramRead_i + memController.io.interdma.accread <> toVirtualLines0.io.accRead_i - translator.io.dma_out.sramwrite <> spad.io.dma.sramwrite - translator.io.dma_out.accwrite <> spad.io.dma.accwrite - translator.io.dma_out.sramread <> spad.io.dma.sramread - translator.io.dma_out.accread <> spad.io.dma.accread + translator.io.dma_in.sramread <> toVirtualLines0.io.sramRead_o + translator.io.dma_in.sramwrite <> toVirtualLines0.io.sramWrite_o + + translator.io.dma_out.sramread <> toPhysicalLines0.io.sramRead_i + translator.io.dma_out.sramwrite <> toPhysicalLines0.io.sramWrite_i + + toPhysicalLines0.io.sramRead_o <> spad.io.dma.sramread + toPhysicalLines0.io.sramWrite_o <> spad.io.dma.sramwrite + toPhysicalLines0.io.accRead_o <> spad.io.dma.accread + toPhysicalLines0.io.accWrite_o <> spad.io.dma.accwrite // ToPhysical interface // Ball Domain SRAM interface connected to MemController's Ball Domain interface - val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) + val toPhysicalLines1 = Module(new ToPhysicalLine()(b, p)) + + translator.io.exec_in.sramread <> io.ballDomain.sramRead + translator.io.exec_in.sramwrite <> io.ballDomain.sramWrite + + translator.io.exec_out.sramread <> toPhysicalLines1.io.sramRead_i + translator.io.exec_out.sramwrite <> toPhysicalLines1.io.sramWrite_i - toPhysicalLines.io.sramRead_i <> io.ballDomain.sramRead - toPhysicalLines.io.sramWrite_i <> io.ballDomain.sramWrite + toPhysicalLines1.io.sramRead_o <> spad.io.exec.sramread + toPhysicalLines1.io.sramWrite_o <> spad.io.exec.sramwrite + toPhysicalLines1.io.accRead_o <> spad.io.exec.accread + toPhysicalLines1.io.accWrite_o <> spad.io.exec.accwrite - toPhysicalLines.io.sramRead_o <> translator.io.exec_in.sramread - toPhysicalLines.io.sramWrite_o <> translator.io.exec_in.sramwrite - toPhysicalLines.io.accRead_o <> translator.io.exec_in.accread - toPhysicalLines.io.accWrite_o <> translator.io.exec_in.accwrite - translator.io.exec_out.sramread <> spad.io.exec.sramread - translator.io.exec_out.sramwrite <> spad.io.exec.sramwrite - translator.io.exec_out.accread <> spad.io.exec.accread - translator.io.exec_out.accwrite <> spad.io.exec.accwrite // translator.io.dma_return := DontCare // translator.io.exec_return := DontCare diff --git a/arch/src/main/scala/framework/memdomain/MemLoader.scala b/arch/src/main/scala/framework/memdomain/MemLoader.scala index c55b63ff..a01f76e5 100644 --- a/arch/src/main/scala/framework/memdomain/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/MemLoader.scala @@ -8,10 +8,11 @@ import framework.memdomain.rs.{MemRsIssue, MemRsComplete} import framework.memdomain.mem.SramWriteIO import framework.memdomain.dma.{BBReadRequest, BBReadResponse, LocalAddr} import freechips.rocketchip.rocket.MStatus +import framework.balldomain.blink.{SramWriteWithRobId, SramWriteWithInfo} class MemLoader(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val rob_id_width = log2Up(b.rob_entries) - + val numBanks = b.sp_banks + b.acc_banks val io = IO(new Bundle { // Load instruction from ReservationStation val cmdReq = Flipped(Decoupled(new MemRsIssue)) @@ -21,8 +22,8 @@ class MemLoader(implicit b: CustomBuckyballConfig, p: Parameters) extends Module val dmaReq = Decoupled(new BBReadRequest()) val dmaResp = Flipped(Decoupled(new BBReadResponse(b.spad_w))) // Connected to Scratchpad SRAM write interface - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + val accWrite = Vec(b.acc_banks, Flipped(new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) }) val s_idle :: s_dma_req :: s_dma_wait :: Nil = Enum(3) @@ -95,31 +96,35 @@ class MemLoader(implicit b: CustomBuckyballConfig, p: Parameters) extends Module val target_row = current_bank_addr for (i <- 0 until b.sp_banks) { - io.sramWrite(i).req.valid := io.dmaResp.fire && (target_bank === i.U) - io.sramWrite(i).req.bits.addr := target_row - io.sramWrite(i).req.bits.data := io.dmaResp.bits.data - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(true.B)) + io.sramWrite(i).io.req.valid := io.dmaResp.fire && (target_bank === i.U) + io.sramWrite(i).io.req.bits.addr := target_row + io.sramWrite(i).io.req.bits.data := io.dmaResp.bits.data + io.sramWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(true.B)) + io.sramWrite(i).rob_id := rob_id_reg } // Default assignment for (i <- 0 until b.acc_banks) { - io.accWrite(i).req.valid := false.B - io.accWrite(i).req.bits.addr := 0.U - io.accWrite(i).req.bits.data := 0.U - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(false.B)) + io.accWrite(i).io.req.valid := false.B + io.accWrite(i).io.req.bits.addr := 0.U + io.accWrite(i).io.req.bits.data := 0.U + io.accWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(false.B)) + io.accWrite(i).rob_id := 0.U } for (i <- 0 until b.acc_banks/2) { when(io.dmaResp.fire && is_acc_reg){ when(io.dmaResp.bits.addrcounter(2)){ - io.accWrite(i).req.valid := target_row(log2Ceil(b.acc_banks/2) - 1, 0) === i.U - io.accWrite(i).req.bits.addr := wr_bank_addr_reg + (io.dmaResp.bits.addrcounter >> (log2Ceil(b.acc_banks/2) + 1)) - io.accWrite(i).req.bits.data := io.dmaResp.bits.data - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + io.accWrite(i).io.req.valid := target_row(log2Ceil(b.acc_banks/2) - 1, 0) === i.U + io.accWrite(i).io.req.bits.addr := wr_bank_addr_reg + (io.dmaResp.bits.addrcounter >> (log2Ceil(b.acc_banks/2) + 1)) + io.accWrite(i).io.req.bits.data := io.dmaResp.bits.data + io.accWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + io.accWrite(i).rob_id := rob_id_reg }.otherwise{ - io.accWrite(i + b.acc_banks/2).req.valid := target_row(log2Ceil(b.acc_banks/2) - 1, 0) === i.U - io.accWrite(i + b.acc_banks/2).req.bits.addr := wr_bank_addr_reg + (io.dmaResp.bits.addrcounter >> (log2Ceil(b.acc_banks/2) + 1)) - io.accWrite(i + b.acc_banks/2).req.bits.data := io.dmaResp.bits.data - io.accWrite(i + b.acc_banks/2).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + io.accWrite(i + b.acc_banks/2).io.req.valid := target_row(log2Ceil(b.acc_banks/2) - 1, 0) === i.U + io.accWrite(i + b.acc_banks/2).io.req.bits.addr := wr_bank_addr_reg + (io.dmaResp.bits.addrcounter >> (log2Ceil(b.acc_banks/2) + 1)) + io.accWrite(i + b.acc_banks/2).io.req.bits.data := io.dmaResp.bits.data + io.accWrite(i + b.acc_banks/2).io.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + io.accWrite(i + b.acc_banks/2).rob_id := rob_id_reg } } } diff --git a/arch/src/main/scala/framework/memdomain/MemStorer.scala b/arch/src/main/scala/framework/memdomain/MemStorer.scala index fb3c5a61..a4a5f60b 100644 --- a/arch/src/main/scala/framework/memdomain/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/MemStorer.scala @@ -8,6 +8,7 @@ import framework.memdomain.rs.{MemRsIssue, MemRsComplete} import freechips.rocketchip.rocket.MStatus import framework.memdomain.mem.SramReadIO import framework.memdomain.dma.{BBWriteRequest, BBWriteResponse, LocalAddr} +import framework.balldomain.blink.{SramReadWithRobId, SramReadWithInfo} class MemStorer(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val rob_id_width = log2Up(b.rob_entries) @@ -25,8 +26,8 @@ class MemStorer(implicit b: CustomBuckyballConfig, p: Parameters) extends Module val dmaReq = Decoupled(new BBWriteRequest(b.spad_w)) val dmaResp = Flipped(Decoupled(new BBWriteResponse)) // Connected to Scratchpad SRAM read interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) + val sramRead = Vec(b.sp_banks, Flipped(new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) + val accRead = Vec(b.acc_banks, Flipped(new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) }) val s_idle :: s_sram_req :: s_dma_wait :: Nil = Enum(3) @@ -83,37 +84,41 @@ class MemStorer(implicit b: CustomBuckyballConfig, p: Parameters) extends Module val target_row = current_bank_addr for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := (state === s_sram_req) && (target_bank === i.U) && !acc_reg - io.sramRead(i).req.bits.addr := target_row - io.sramRead(i).req.bits.fromDMA := true.B + io.sramRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) && !acc_reg + io.sramRead(i).io.req.bits.addr := target_row + io.sramRead(i).io.req.bits.fromDMA := true.B + io.sramRead(i).rob_id := rob_id_reg } // Default assignment for (i <- 0 until b.acc_banks) { - io.accRead(i).req.valid := false.B - io.accRead(i).req.bits.addr := 0.U - io.accRead(i).req.bits.fromDMA := true.B + io.accRead(i).io.req.valid := false.B + io.accRead(i).io.req.bits.addr := 0.U + io.accRead(i).io.req.bits.fromDMA := true.B + io.accRead(i).rob_id := 0.U } for (i <- 0 until b.acc_banks/2){ when((state === s_sram_req) && acc_reg){ when(sram_count(2) === 0.U){ - io.accRead(i).req.valid := i.U === target_row(log2Ceil(b.acc_banks/2) - 1, 0) - io.accRead(i).req.bits.addr := rd_bank_addr_reg + (sram_count >> (log2Ceil(b.acc_banks/2) + 1)) - io.accRead(i).req.bits.fromDMA := true.B + io.accRead(i).io.req.valid := i.U === target_row(log2Ceil(b.acc_banks/2) - 1, 0) + io.accRead(i).io.req.bits.addr := rd_bank_addr_reg + (sram_count >> (log2Ceil(b.acc_banks/2) + 1)) + io.accRead(i).io.req.bits.fromDMA := true.B + io.accRead(i).rob_id := rob_id_reg }.otherwise{ - io.accRead(i + b.acc_banks/2).req.valid := i.U === target_row(log2Ceil(b.acc_banks/2) - 1, 0) - io.accRead(i + b.acc_banks/2).req.bits.addr := rd_bank_addr_reg + (sram_count >> (log2Ceil(b.acc_banks/2) + 1)) - io.accRead(i + b.acc_banks/2).req.bits.fromDMA := true.B + io.accRead(i + b.acc_banks/2).io.req.valid := i.U === target_row(log2Ceil(b.acc_banks/2) - 1, 0) + io.accRead(i + b.acc_banks/2).io.req.bits.addr := rd_bank_addr_reg + (sram_count >> (log2Ceil(b.acc_banks/2) + 1)) + io.accRead(i + b.acc_banks/2).io.req.bits.fromDMA := true.B + io.accRead(i + b.acc_banks/2).rob_id := rob_id_reg } } } // SRAM response processing - val sram_resp_valid = io.sramRead.map(_.resp.valid).reduce(_ || _) - val sram_resp_data = Mux1H(io.sramRead.map(_.resp.valid), io.sramRead.map(_.resp.bits.data)) - val acc_resp_valid = io.accRead.map(_.resp.valid).reduce(_ || _) - val acc_resp_data = Mux1H(io.accRead.map(_.resp.valid), io.accRead.map(_.resp.bits.data)) + val sram_resp_valid = io.sramRead.map(_.io.resp.valid).reduce(_ || _) + val sram_resp_data = Mux1H(io.sramRead.map(_.io.resp.valid), io.sramRead.map(_.io.resp.bits.data)) + val acc_resp_valid = io.accRead.map(_.io.resp.valid).reduce(_ || _) + val acc_resp_data = Mux1H(io.accRead.map(_.io.resp.valid), io.accRead.map(_.io.resp.bits.data)) // Calculate memory address corresponding to current row val current_mem_addr = mem_addr_reg + sram_count(1,0) * line_bytes.U + ((sram_count >> 2) << 2) * stride_reg * line_bytes.U @@ -230,10 +235,10 @@ class MemStorer(implicit b: CustomBuckyballConfig, p: Parameters) extends Module io.dmaReq.bits.status := dma_req_status_reg // Connect SRAM response ready signal - based on DMA ready state - io.sramRead.foreach(_.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) - io.accRead.foreach(_.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) + io.sramRead.foreach(_.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) + io.accRead.foreach(_.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) // State transition and counter update - when (io.sramRead.map(_.req.fire).reduce(_ || _)) { + when (io.sramRead.map(_.io.req.fire).reduce(_ || _)) { state := s_dma_wait } diff --git a/arch/src/main/scala/framework/memdomain/Translator.scala b/arch/src/main/scala/framework/memdomain/Translator.scala index e45cdf7f..aed404cd 100644 --- a/arch/src/main/scala/framework/memdomain/Translator.scala +++ b/arch/src/main/scala/framework/memdomain/Translator.scala @@ -5,13 +5,13 @@ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.memdomain.mem.{SramReadIO, SramWriteIO} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} class Translator(implicit b: CustomBuckyballConfig, p: Parameters) extends Module{ + val numBanks = b.sp_banks + b.acc_banks class BanksIO extends Bundle { - val sramread = Vec(b.sp_banks, new SramReadIO(b.spad_bank_entries, b.spad_w)) - val sramwrite = Vec(b.sp_banks, new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - val accread = Vec(b.acc_banks, new SramReadIO(b.acc_bank_entries, b.acc_w)) - val accwrite = Vec(b.acc_banks, new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len)) + val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) + val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) } val io = IO(new Bundle { From 987f7c6ca686cb87dbb0f66ebe64c7089fb6c027 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 18 Dec 2025 15:21:49 +0800 Subject: [PATCH 012/238] [compiler] fix: specify 'llvm' in git submodule update for compiler installation script --- scripts/install-compiler.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/install-compiler.sh b/scripts/install-compiler.sh index 2a5e11eb..72e728c4 100755 --- a/scripts/install-compiler.sh +++ b/scripts/install-compiler.sh @@ -14,7 +14,7 @@ source ${BBDIR}/env.sh pip install -r ${BUDDY_MLIR_DIR}/requirements.txt cd ${BUDDY_MLIR_DIR} -git submodule update --init +git submodule update --init llvm mkdir -p llvm/build && cd llvm/build cmake -G Ninja ../llvm \ From c8ca4976365c8f84cced58a1d23a6fde8df1605d Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Thu, 18 Dec 2025 16:37:26 +0800 Subject: [PATCH 013/238] [arch/memdomain] refractor: finish the back-end arch unification (#20) --- .../framework/memdomain/MemController.scala | 2 +- .../scala/framework/memdomain/MemDomain.scala | 24 +-- .../framework/memdomain/mem/AccBank.scala | 142 --------------- .../framework/memdomain/mem/AccMonitor.scala | 165 ++++++++++++++++++ .../scala/framework/memdomain/mem/README.md | 151 ++++++++-------- .../framework/memdomain/mem/Scratchpad.scala | 157 ++++++----------- 6 files changed, 304 insertions(+), 337 deletions(-) delete mode 100644 arch/src/main/scala/framework/memdomain/mem/AccBank.scala create mode 100644 arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala diff --git a/arch/src/main/scala/framework/memdomain/MemController.scala b/arch/src/main/scala/framework/memdomain/MemController.scala index e7122058..312dff1a 100644 --- a/arch/src/main/scala/framework/memdomain/MemController.scala +++ b/arch/src/main/scala/framework/memdomain/MemController.scala @@ -8,7 +8,7 @@ import framework.frontend.decoder.PostGDCmd import freechips.rocketchip.tile._ import framework.memdomain.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} import framework.memdomain.mem.{SramReadIO, SramWriteIO, Scratchpad} -import framework.memdomain.{MemLoader, MemStorer, MemController} +import framework.memdomain.{MemLoader, MemStorer} import framework.memdomain.rs.MemReservationStation import framework.memdomain.tlb.{BBTLBCluster, BBTLBIO, BBTLBExceptionIO} import framework.memdomain.pmc.MemCyclePMC diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index b36723fa..17c04ded 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -60,7 +60,7 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu val memController = Module(new MemController) val translator = Module(new Translator) - val spad = Module(new Scratchpad(b)) + val spad = Module(new Scratchpad()) // ----------------------------------------------------------------------------- // Global RS -> MemDecoder @@ -92,7 +92,6 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu // Connect MemLoader and MemStorer to MemController's DMA interface val toVirtualLines0 = Module(new ToVirtualLine()(b, p)) - val toPhysicalLines0 = Module(new ToPhysicalLine()(b, p)) memController.io.interdma.sramwrite <> toVirtualLines0.io.sramWrite_i memController.io.interdma.accwrite <> toVirtualLines0.io.accWrite_i @@ -102,30 +101,17 @@ class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOu translator.io.dma_in.sramread <> toVirtualLines0.io.sramRead_o translator.io.dma_in.sramwrite <> toVirtualLines0.io.sramWrite_o - translator.io.dma_out.sramread <> toPhysicalLines0.io.sramRead_i - translator.io.dma_out.sramwrite <> toPhysicalLines0.io.sramWrite_i - - toPhysicalLines0.io.sramRead_o <> spad.io.dma.sramread - toPhysicalLines0.io.sramWrite_o <> spad.io.dma.sramwrite - toPhysicalLines0.io.accRead_o <> spad.io.dma.accread - toPhysicalLines0.io.accWrite_o <> spad.io.dma.accwrite + translator.io.dma_out.sramread <> spad.io.dma.sramread + translator.io.dma_out.sramwrite <> spad.io.dma.sramwrite // ToPhysical interface // Ball Domain SRAM interface connected to MemController's Ball Domain interface - val toPhysicalLines1 = Module(new ToPhysicalLine()(b, p)) translator.io.exec_in.sramread <> io.ballDomain.sramRead translator.io.exec_in.sramwrite <> io.ballDomain.sramWrite - translator.io.exec_out.sramread <> toPhysicalLines1.io.sramRead_i - translator.io.exec_out.sramwrite <> toPhysicalLines1.io.sramWrite_i - - toPhysicalLines1.io.sramRead_o <> spad.io.exec.sramread - toPhysicalLines1.io.sramWrite_o <> spad.io.exec.sramwrite - toPhysicalLines1.io.accRead_o <> spad.io.exec.accread - toPhysicalLines1.io.accWrite_o <> spad.io.exec.accwrite - - + translator.io.exec_out.sramread <> spad.io.exec.sramread + translator.io.exec_out.sramwrite <> spad.io.exec.sramwrite // translator.io.dma_return := DontCare // translator.io.exec_return := DontCare diff --git a/arch/src/main/scala/framework/memdomain/mem/AccBank.scala b/arch/src/main/scala/framework/memdomain/mem/AccBank.scala deleted file mode 100644 index 9ea71afe..00000000 --- a/arch/src/main/scala/framework/memdomain/mem/AccBank.scala +++ /dev/null @@ -1,142 +0,0 @@ -package framework.memdomain.mem - -import chisel3._ -import chisel3.util._ - -import framework.builtin.util.Util._ - -class AccWriteIO(n: Int, w: Int, mask_len: Int) extends SramWriteIO(n, w, mask_len) { - val is_acc = Input(Bool()) -} - -class AccPipe(val n: Int, val w: Int, val mask_len: Int) extends Module { - val io = IO(new Bundle { - val write_in = new AccWriteIO(n, w, mask_len) // outer —> Acc - val read = Flipped(new SramReadIO(n, w)) // Acc <—> SramBank - val write_out = Flipped(new SramWriteIO(n, w, mask_len)) // Acc —> SramBank - }) - - // Pipeline registers - val valid_reg = RegInit(false.B) - val addr_reg = RegInit(0.U(log2Ceil(n).W)) - val data_reg = RegInit(0.U(w.W)) - val mask_reg = RegInit(VecInit(Seq.fill(mask_len)(false.B))) - - when (io.write_in.is_acc || RegNext(io.write_in.is_acc)) { -// ----------------------------------------------------------------------------- -// exec->AccPipe->SramBank -// ----------------------------------------------------------------------------- - // Stage 1: Read request - io.read.req.valid := io.write_in.req.valid - io.read.req.bits.addr := io.write_in.req.bits.addr - // AccPipe read is not from DMA - io.read.req.bits.fromDMA := false.B - valid_reg := io.write_in.req.valid - addr_reg := io.write_in.req.bits.addr - data_reg := io.write_in.req.bits.data - mask_reg := io.write_in.req.bits.mask - - // Stage 2: Accumulate (when read data is ready) - val acc_data = WireDefault(0.U(w.W)) - when (valid_reg && io.read.resp.valid) { - acc_data := data_reg + io.read.resp.bits.data - }.otherwise { - acc_data := data_reg - } - - // Stage 3: Write back - io.write_out.req.valid := valid_reg && io.read.resp.valid - io.write_out.req.bits.addr := addr_reg - io.write_out.req.bits.data := acc_data - io.write_out.req.bits.mask := mask_reg - - // Backpressure - io.write_in.req.ready := io.read.req.ready - io.read.resp.ready := io.write_out.req.ready - }.otherwise { -// ----------------------------------------------------------------------------- -// main->SramBank -// ----------------------------------------------------------------------------- - io.read.req.valid := false.B - io.read.req.bits.addr := 0.U(log2Ceil(n).W) - io.read.req.bits.fromDMA := false.B - - io.write_out.req.valid := io.write_in.req.valid - io.write_out.req.bits.addr := io.write_in.req.bits.addr - io.write_out.req.bits.data := io.write_in.req.bits.data - io.write_out.req.bits.mask := io.write_in.req.bits.mask - - io.write_in.req.ready := io.write_out.req.ready - io.read.resp.ready := false.B - } -} - - -class AccReadRouter(val n: Int, val w: Int) extends Module { - val io = IO(new Bundle { - val read_in1 = new SramReadIO(n, w) - val read_in2 = new SramReadIO(n, w) - val read_out = Flipped(new SramReadIO(n, w)) - }) - -// ----------------------------------------------------------------------------- -// Arbiter - use two Arbiters to handle req and resp separately -// ----------------------------------------------------------------------------- - // Priority arbiter, read_in2 has index 0 for higher priority - val req_arbiter = Module(new Arbiter(new SramReadReq(n), 2)) - req_arbiter.io.in(0) <> io.read_in2.req - req_arbiter.io.in(1) <> io.read_in1.req - io.read_out.req <> req_arbiter.io.out - - // Response distributor: record which input initiated the request - val resp_to_in1 = RegNext(req_arbiter.io.chosen === 1.U && req_arbiter.io.out.fire, false.B) - val resp_to_in2 = RegNext(req_arbiter.io.chosen === 0.U && req_arbiter.io.out.fire, false.B) - - // Response distribution - io.read_in1.resp.valid := io.read_out.resp.valid && resp_to_in1 - io.read_in1.resp.bits := io.read_out.resp.bits - io.read_in2.resp.valid := io.read_out.resp.valid && resp_to_in2 - io.read_in2.resp.bits := io.read_out.resp.bits - - // Response ready signal - io.read_out.resp.ready := - (resp_to_in1 && io.read_in1.resp.ready) || - (resp_to_in2 && io.read_in2.resp.ready) - - assert(!(io.read_in1.req.valid && io.read_in2.req.valid), "[AccBank Router]: Read requests is not allowed at the same time") -} - - -class AccBank(n: Int, w: Int, aligned_to: Int, single_ported: Boolean) extends Module { - val mask_len = (w / (aligned_to * 8)) max 1 - val mask_elem = UInt((w min (aligned_to * 8)).W) - - val io = IO(new Bundle { - val read = new SramReadIO(n, w) - val write = new AccWriteIO(n, w, mask_len) - }) - - val sram = Module(new SramBank(n, w, aligned_to, single_ported)) - val pipe = Module(new AccPipe(n, w, mask_len)) - val read_router = Module(new AccReadRouter(n, w)) - -// ----------------------------------------------------------------------------- -// Write request enters pipeline -// ----------------------------------------------------------------------------- - pipe.io.write_in <> io.write - -// ----------------------------------------------------------------------------- -// Read request arbitration -// ----------------------------------------------------------------------------- - read_router.io.read_in1 <> pipe.io.read - read_router.io.read_in2 <> io.read - - // Connect AccRouter output to SramBank - sram.io.read <> read_router.io.read_out - -// ----------------------------------------------------------------------------- -// Pipeline output connected to underlying SRAM write port -// ----------------------------------------------------------------------------- - sram.io.write <> pipe.io.write_out - -} diff --git a/arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala b/arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala new file mode 100644 index 00000000..dff1124c --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala @@ -0,0 +1,165 @@ +package framework.memdomain.mem + +import chisel3._ +import chisel3.util._ + +import framework.builtin.util.Util._ + +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.mem.{SramReadIO, SramWriteIO} +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} + +class AccMonitorWriteIO(n: Int, w: Int, mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters)extends Bundle { + val io = new SramWriteIO(n, w, mask_len) + + val rob_id = Input(UInt(log2Up(b.rob_entries).W)) + val is_acc = Input(Bool()) + val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) +} + +class AccMonitorReadIO(n: Int, w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle{ + val io = new SramReadIO(n, w) + + val rob_id = Input(UInt(log2Up(b.rob_entries).W)) + val is_acc = Input(Bool()) + val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) +} + +class AccPipe(val n: Int, val w: Int, val mask_len: Int) (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { + val io = IO(new Bundle { + val write_in = new AccMonitorWriteIO(n, w, mask_len) // outer —> Acc + val read = Flipped(new AccMonitorReadIO(n, w)) // Acc <—> SramBank + val write_out = Flipped(new SramWriteIO(n, w, mask_len)) // Acc —> SramBank + }) + + // Pipeline registers + val valid_reg = RegInit(false.B) + val addr_reg = RegInit(0.U(log2Ceil(n).W)) + val data_reg = RegInit(0.U(w.W)) + val mask_reg = RegInit(VecInit(Seq.fill(mask_len)(false.B))) + + // Default/forward metadata (so it's always driven) + io.read.rob_id := io.write_in.rob_id + io.read.is_acc := io.write_in.is_acc + io.read.bank_id := io.write_in.bank_id + + + when (io.write_in.is_acc || RegNext(io.write_in.is_acc)) { +// ----------------------------------------------------------------------------- +// exec->AccPipe->SramBank +// ----------------------------------------------------------------------------- + // Stage 1: Read request + io.read.io.req.valid := io.write_in.io.req.valid + io.read.io.req.bits.addr := io.write_in.io.req.bits.addr + // AccPipe read is not from DMA + io.read.io.req.bits.fromDMA := false.B + valid_reg := io.write_in.io.req.valid + addr_reg := io.write_in.io.req.bits.addr + data_reg := io.write_in.io.req.bits.data + mask_reg := io.write_in.io.req.bits.mask + + // Stage 2: Accumulate (when read data is ready) + val acc_data = WireDefault(0.U(w.W)) + when (valid_reg && io.read.io.resp.valid) { + acc_data := data_reg + io.read.io.resp.bits.data + }.otherwise { + acc_data := data_reg + } + + // Stage 3: Write back + io.write_out.req.valid := valid_reg && io.read.io.resp.valid + io.write_out.req.bits.addr := addr_reg + io.write_out.req.bits.data := acc_data + io.write_out.req.bits.mask := mask_reg + + // Backpressure + io.write_in.io.req.ready := io.read.io.req.ready + io.read.io.resp.ready := io.write_out.req.ready + }.otherwise { +// ----------------------------------------------------------------------------- +// main->SramBank +// ----------------------------------------------------------------------------- + io.read.io.req.valid := false.B + io.read.io.req.bits.addr := 0.U(log2Ceil(n).W) + io.read.io.req.bits.fromDMA := false.B + + io.write_out.req.valid := io.write_in.io.req.valid + io.write_out.req.bits.addr := io.write_in.io.req.bits.addr + io.write_out.req.bits.data := io.write_in.io.req.bits.data + io.write_out.req.bits.mask := io.write_in.io.req.bits.mask + + io.write_in.io.req.ready := io.write_out.req.ready + io.read.io.resp.ready := false.B + } +} + + +class AccReadRouter(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { + val io = IO(new Bundle { + val read_in1 = new AccMonitorReadIO(n, w) + val read_in2 = new AccMonitorReadIO(n, w) + val read_out = Flipped(new SramReadIO(n, w)) + }) + +// ----------------------------------------------------------------------------- +// Arbiter - use two Arbiters to handle req and resp separately +// ----------------------------------------------------------------------------- + // Priority arbiter, read_in2 has index 0 for higher priority + val req_arbiter = Module(new Arbiter(new SramReadReq(n), 2)) + req_arbiter.io.in(0) <> io.read_in2.io.req + req_arbiter.io.in(1) <> io.read_in1.io.req + io.read_out.req <> req_arbiter.io.out + + // Response distributor: record which input initiated the request + val resp_to_in1 = RegNext(req_arbiter.io.chosen === 1.U && req_arbiter.io.out.fire, false.B) + val resp_to_in2 = RegNext(req_arbiter.io.chosen === 0.U && req_arbiter.io.out.fire, false.B) + + // Response distribution + io.read_in1.io.resp.valid := io.read_out.resp.valid && resp_to_in1 + io.read_in1.io.resp.bits := io.read_out.resp.bits + io.read_in2.io.resp.valid := io.read_out.resp.valid && resp_to_in2 + io.read_in2.io.resp.bits := io.read_out.resp.bits + + // Response ready signal + io.read_out.resp.ready := + (resp_to_in1 && io.read_in1.io.resp.ready) || + (resp_to_in2 && io.read_in2.io.resp.ready) + + assert(!(io.read_in1.io.req.valid && io.read_in2.io.req.valid), "[AccBank Router]: Read requests is not allowed at the same time") +} + + +class AccMonitor(n: Int, w: Int, aligned_to: Int, single_ported: Boolean) (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { + val mask_len = (w / (aligned_to * 8)) max 1 + val mask_elem = UInt((w min (aligned_to * 8)).W) + + val io = IO(new Bundle { + val read = new AccMonitorReadIO(n, w) + val write = new AccMonitorWriteIO(n, w, mask_len) + }) + + val sram = Module(new SramBank(n, w, aligned_to, single_ported)) + val pipe = Module(new AccPipe(n, w, mask_len)) + val read_router = Module(new AccReadRouter(n, w)) + +// ----------------------------------------------------------------------------- +// Write request enters pipeline +// ----------------------------------------------------------------------------- + pipe.io.write_in <> io.write + +// ----------------------------------------------------------------------------- +// Read request arbitration +// ----------------------------------------------------------------------------- + read_router.io.read_in1 <> pipe.io.read + read_router.io.read_in2 <> io.read + + // Connect AccRouter output to SramBank + sram.io.read <> read_router.io.read_out + +// ----------------------------------------------------------------------------- +// Pipeline output connected to underlying SRAM write port +// ----------------------------------------------------------------------------- + sram.io.write <> pipe.io.write_out + +} diff --git a/arch/src/main/scala/framework/memdomain/mem/README.md b/arch/src/main/scala/framework/memdomain/mem/README.md index cecedcf6..3678ed63 100644 --- a/arch/src/main/scala/framework/memdomain/mem/README.md +++ b/arch/src/main/scala/framework/memdomain/mem/README.md @@ -1,30 +1,46 @@ -# Memory Bank Implementation +# Memory Domain Modules -## Overview +Core memory building blocks for Buckyball, located at `arch/src/main/scala/framework/memdomain/mem`. This directory provides single-ported SRAM banks, an accumulation monitor around the bank, and a multi-bank scratchpad with request arbitration. -Core storage units for Buckyball's memory domain, located at `arch/src/main/scala/framework/builtin/memdomain/mem`. Provides high-performance on-chip memory components. +## Modules -Components: -- **SramBank**: Basic SRAM storage bank with synchronous read/write -- **AccBank**: Accumulator storage bank with read-modify-write support -- **Scratchpad**: Scratchpad module managing multiple memory banks with arbitration +- **SramBank**: Single-ported synchronous SRAM bank with 1-cycle read latency and write-ready arbitration. +- **AccMonitor**: Wraps a `SramBank` with an accumulation pipeline (`AccPipe`) and a read router (`AccReadRouter`). Supports read-modify-write when `is_acc` is asserted. +- **Scratchpad**: Instantiates one `AccMonitor` per bank and arbitrates between DMA and execution-unit (exec) traffic. -## File Structure +## File Layout ``` mem/ -├── SramBank.scala - Basic SRAM bank implementation -├── AccBank.scala - Accumulator bank implementation -└── Scratchpad.scala - Scratchpad management module +├── SramBank.scala # Basic single-ported SRAM bank +├── AccMonitor.scala # Accumulate pipeline + read router around SRAM +└── Scratchpad.scala # Multi-bank manager and request arbitration ``` -## SramBank.scala +## Configuration -### Interface Definition +All modules are parameterized via `examples.BuckyballConfigs.CustomBuckyballConfig` and `org.chipsalliance.cde.config.Parameters`: + +- Bank count: `b.sp_banks`, `b.acc_banks` +- Entries per bank: `b.spad_bank_entries` +- Data width: `b.spad_w` +- Alignment: `b.aligned_to` +- Single-ported banks: `b.sp_singleported` (must be true; enforced by assertion in `Scratchpad`) + +--- + +## SramBank + +### Interface ```scala class SramReadReq(val n: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) + val addr = UInt(log2Ceil(n).W) + val fromDMA = Bool() +} + +class SramReadResp(val w: Int) extends Bundle { + val data = UInt(w.W) val fromDMA = Bool() } @@ -35,80 +51,71 @@ class SramWriteReq(val n: Int, val w: Int, val mask_len: Int) extends Bundle { } ``` -### Core Logic +### Behavior -```scala -val mem = SyncReadMem(n, Vec(mask_len, mask_elem)) +- Single-ported arbitration: `assert(!(io.read.req.valid && io.write.req.valid))` forbids same-cycle read+write. +- Handshake: `io.read.req.ready := !io.write.req.valid`, `io.write.req.ready := !io.read.req.valid`. +- Read latency: 1 cycle; `resp.valid := RegNext(io.read.req.fire)`, `resp.bits.data := mem.read(addr, ren).asUInt`. +- Write: stores `data` as a `Vec(mask_len, mask_elem)`. Current implementation writes all lanes; per-bit mask can be added in future. -// Read/write conflict arbitration -assert(!(io.read.req.valid && io.write.req.valid), - "SramBank: Read and write requests is not allowed at the same time") +--- -io.read.req.ready := !io.write.req.valid -io.write.req.ready := !io.read.req.valid -``` +## AccMonitor -**Constraint**: No simultaneous read/write to same bank in same cycle +`AccMonitor(n, w, aligned_to, single_ported)` composes: -## AccBank.scala +- `SramBank`: underlying single-ported storage. +- `AccPipe`: 3-stage read–accumulate–write pipeline when `is_acc` is asserted. +- `AccReadRouter`: 2-input arbiter for read requests and response distribution. -### Accumulation Pipeline (AccPipe) +### AccPipe -```scala -when (io.write_in.is_acc || RegNext(io.write_in.is_acc)) { - // Stage 1: Read request - io.read.req.valid := io.write_in.req.valid +- Trigger: pipeline active when `io.write_in.is_acc || RegNext(io.write_in.is_acc)`. +- Stage 1 (Read issue): forwards `addr` and sets `fromDMA := false.B`. +- Stage 2 (Accumulate): if `valid_reg && io.read.io.resp.valid`, compute `acc_data := data_reg + resp.data`; otherwise pass through `data_reg`. +- Stage 3 (Write back): issues write with `acc_data`, preserving `addr` and `mask`. +- Bypass: if not accumulating, write requests pass through directly to SRAM. +- Backpressure: `write_in.ready` mirrors `read.req.ready`; `read.resp.ready` mirrors `write_out.req.ready`. - // Stage 2: Accumulate - val acc_data = data_reg + io.read.resp.bits.data +### AccReadRouter - // Stage 3: Write back - io.write_out.req.bits.data := acc_data -} -``` - -### Read Request Router (AccReadRouter) - -```scala -val req_arbiter = Module(new Arbiter(new SramReadReq(n), 2)) -req_arbiter.io.in(0) <> io.read_in2.req // Higher priority -req_arbiter.io.in(1) <> io.read_in1.req // Lower priority +- Request arbitration: 2-way `Arbiter[SramReadReq]`, with input 0 (second client) prioritized. +- Response routing: captures `req_arbiter.io.chosen` to send `resp` to the initiating client. +- Ready: `read_out.resp.ready` is high when the selected client is ready. +- Safety: `assert(!(io.read_in1.io.req.valid && io.read_in2.io.req.valid))`. -// Response distribution -val resp_to_in1 = RegNext(req_arbiter.io.chosen === 1.U && req_arbiter.io.out.fire) -``` +--- -## Scratchpad.scala +## Scratchpad -### Bank Instantiation +- Banks: `numBanks = b.sp_banks + b.acc_banks`; instantiates `AccMonitor` per bank. +- Read arbitration per bank: priority `exec` > `dma`. + - Select: `exec_read_sel = exec_read_req.valid`; `main_read_sel = main_read_req.valid && !exec_read_sel`. + - Response distribution: records which client fired, then forwards `resp` accordingly. + - Ready: bank `resp.ready` is the OR of the selected client's ready. +- Write arbitration per bank: priority `exec` > `dma`; muxes `addr`, `data`, `mask` and metadata (`is_acc`, `bank_id`, `rob_id`). +- Metadata: read-side metadata is tied off (`rob_id := 0.U`, `is_acc := false.B`, `bank_id := i.U`). +- Assertions: + - `assert(b.sp_singleported)` — Scratchpad expects single-ported SRAM. + - `assert(!(exec_read_req.valid && exec_write.io.req.valid))` — exec read and write cannot target the same bank simultaneously. -```scala -val spad_mems = Seq.fill(sp_banks) { Module(new SramBank( - spad_bank_entries, spad_w, aligned_to, sp_singleported -)) } +--- -val acc_mems = Seq.fill(acc_banks) { Module(new AccBank( - acc_bank_entries, acc_w, aligned_to, sp_singleported -)) } -``` +## Key Guarantees & Notes -### Request Arbitration +1. **Single-Port Discipline**: No same-cycle read/write in `SramBank`; higher layers arbitrate accordingly. +2. **Priority Policy**: `exec` traffic wins over `dma` for both reads and writes; `AccReadRouter` prioritizes its second input. +3. **Accumulation Semantics**: When `is_acc` is asserted, writes become read-modify-write with `+` over the fetched word. +4. **Masking**: Write requests carry a mask vector; current `SramBank` implementation writes all lanes and can be extended to honor per-bit masks. +5. **Latency**: Reads have 1-cycle latency from `req.fire` to `resp.valid`; accumulation path adds pipeline staging. +6. **Parameterization**: Widths, depths, and counts come from config; ensure `w` and `aligned_to` satisfy `require(w % aligned_to == 0 || w < aligned_to)`. -```scala -// Read arbitration: priority exec > dma -val exec_read_sel = exec_read_req.valid -val main_read_sel = main_read_req.valid && !exec_read_sel +--- -// Response distribution -val resp_to_main = RegNext(main_read_sel && bank.io.read.req.fire) -val resp_to_exec = RegNext(exec_read_sel && bank.io.read.req.fire) -``` +## Where to Look -## Important Notes +- Bank implementation: `SramBank.scala` +- Accumulate pipeline & router: `AccMonitor.scala` +- Multi-bank arbitration & top-level wiring: `Scratchpad.scala` -1. **Single Port Limitation**: Configuration enforces single-port SRAM (`sp_singleported = true`), no same-cycle read/write -2. **Arbitration Priority**: Execution unit (exec) requests have higher priority than DMA requests in all modules -3. **Pipeline Design**: AccBank uses 3-stage pipeline (read-accumulate-write), requires careful data dependency handling -4. **Parameterized Configuration**: All modules support configuration through BaseConfig (bank count, capacity, data width) -5. **Assertions**: Code includes runtime assertions for detecting illegal concurrent access and configuration errors -6. **Mask Support**: Byte-granularity write mask operations, mask length calculated from data width and alignment +These modules are designed to be composed cleanly with Chisel handshakes and explicit assertions to catch illegal concurrent accesses. diff --git a/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala b/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala index 08d20c2f..5921181b 100644 --- a/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala +++ b/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala @@ -8,29 +8,30 @@ import freechips.rocketchip.tile._ import framework.builtin.util.Util._ import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.mem.AccWriteIO +import framework.memdomain.mem.AccMonitor +import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} -class Scratchpad(config: CustomBuckyballConfig)(implicit val p: Parameters) extends Module with HasCoreParameters { - import config._ +class Scratchpad(implicit b: CustomBuckyballConfig, implicit val p: Parameters) + extends Module with HasCoreParameters { // Assertion: ensure configuration consistency - assert(sp_singleported, "Scratchpad expects single-ported SRAM banks") - + assert(b.sp_singleported, "Scratchpad expects single-ported SRAM banks") + private val numBanks = b.sp_banks + b.acc_banks val io = IO(new Bundle { // SRAM read/write interface - used by load/store val dma = new Bundle { - val sramread = Vec(sp_banks, new SramReadIO(spad_bank_entries, spad_w)) - val sramwrite = Vec(sp_banks, new SramWriteIO(spad_bank_entries, spad_w, spad_mask_len)) - val accread = Vec(acc_banks, new SramReadIO(acc_bank_entries, acc_w)) - val accwrite = Vec(acc_banks, new SramWriteIO(acc_bank_entries, acc_w, acc_mask_len)) + val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) + val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) + // val accread = Vec(acc_banks, new SramReadIO(acc_bank_entries, acc_w)) + // val accwrite = Vec(acc_banks, new SramWriteIO(acc_bank_entries, acc_w, acc_mask_len)) } // Execution unit read/write interface - one read and write per bank, OpA and OpB guaranteed to access different banks val exec = new Bundle { - val sramread = Vec(sp_banks, new SramReadIO(spad_bank_entries, spad_w)) - val sramwrite = Vec(sp_banks, new SramWriteIO(spad_bank_entries, spad_w, spad_mask_len)) - val accread = Vec(acc_banks, new SramReadIO(acc_bank_entries, acc_w)) - val accwrite = Vec(acc_banks, new SramWriteIO(acc_bank_entries, acc_w, acc_mask_len)) + val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) + val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) + // val accread = Vec(acc_banks, new SramReadIO(acc_bank_entries, acc_w)) + // val accwrite = Vec(acc_banks, new SramWriteIO(acc_bank_entries, acc_w, acc_mask_len)) } }) @@ -39,25 +40,25 @@ class Scratchpad(config: CustomBuckyballConfig)(implicit val p: Parameters) exte // ----------------------------------------------------------------------------- // SRAM banks - each bank has only one port, supports simultaneous read and write - val spad_mems = Seq.fill(sp_banks) { Module(new SramBank( - spad_bank_entries, spad_w, + val spad_mems = Seq.fill(numBanks) { Module(new AccMonitor( + b.spad_bank_entries, b.spad_w, // Use configuration parameters - aligned_to, sp_singleported + b.aligned_to, b.sp_singleported )) } // Request arbitration and connection for each bank spad_mems.zipWithIndex.foreach { case (bank, i) => // All read request sources - val main_read_req = io.dma.sramread(i).req - val exec_read_req = io.exec.sramread(i).req + val main_read_req = io.dma.sramread(i).io.req + val exec_read_req = io.exec.sramread(i).io.req // All write request sources val main_write = io.dma.sramwrite(i) val exec_write = io.exec.sramwrite(i) // Assertion: OpA and OpB should not access the same bank simultaneously - assert(!(exec_read_req.valid && exec_write.req.valid), + assert(!(exec_read_req.valid && exec_write.io.req.valid), s"Bank ${i}: exec and write cannot access the same bank simultaneously") // Read request arbitration: priority exec > main @@ -65,107 +66,57 @@ class Scratchpad(config: CustomBuckyballConfig)(implicit val p: Parameters) exte val main_read_sel = main_read_req.valid && !exec_read_sel // Write request arbitration: exec has higher priority - val exec_write_sel = exec_write.req.valid + val exec_write_sel = exec_write.io.req.valid - // Connect read request to SramBank - bank.io.read.req.valid := exec_read_sel || main_read_sel - bank.io.read.req.bits := Mux(exec_read_sel, exec_read_req.bits, main_read_req.bits) + val main_isacc_sel = main_write.is_acc + val exec_isacc_sel = exec_write.is_acc - // Read request ready reverse connection - main_read_req.ready := main_read_sel && bank.io.read.req.ready - exec_read_req.ready := exec_read_sel && bank.io.read.req.ready - - // Record which client initiated read request (for response distribution) - val resp_to_main = RegNext(main_read_sel && bank.io.read.req.fire, false.B) - val resp_to_exec = RegNext(exec_read_sel && bank.io.read.req.fire, false.B) + val main_bankid = main_write.bank_id + val exec_bankid = exec_write.bank_id - // Read response distribution - io.dma.sramread(i).resp.valid := bank.io.read.resp.valid && resp_to_main - io.dma.sramread(i).resp.bits := bank.io.read.resp.bits - - io.exec.sramread(i).resp.valid := bank.io.read.resp.valid && resp_to_exec - io.exec.sramread(i).resp.bits := bank.io.read.resp.bits - - // Read response ready signal: either client ready is sufficient - bank.io.read.resp.ready := - (resp_to_main && io.dma.sramread(i).resp.ready) || - (resp_to_exec && io.exec.sramread(i).resp.ready) - - // Connect write request to SramBank - bank.io.write.req.valid := Mux(exec_write_sel, exec_write.req.valid, main_write.req.valid) - bank.io.write.req.bits.addr := Mux(exec_write_sel, exec_write.req.bits.addr, main_write.req.bits.addr) - bank.io.write.req.bits.data := Mux(exec_write_sel, exec_write.req.bits.data, main_write.req.bits.data) - bank.io.write.req.bits.mask := Mux(exec_write_sel, exec_write.req.bits.mask, main_write.req.bits.mask) - - // Write request ready reverse connection - main_write.req.ready := !exec_write_sel && bank.io.write.req.ready - exec_write.req.ready := exec_write_sel && bank.io.write.req.ready - } - -// ----------------------------------------------------------------------------- -// Accumulator -// ----------------------------------------------------------------------------- - - val acc_mems = Seq.fill(acc_banks) { Module(new AccBank( - acc_bank_entries, acc_w, - // Use configuration parameters - aligned_to, sp_singleported - )) } - - // Request arbitration and connection for each acc bank - acc_mems.zipWithIndex.foreach { case (bank, i) => - // All read request sources - val main_read_req = io.dma.accread(i).req - val exec_read_req = io.exec.accread(i).req - - // All write request sources - val main_write = io.dma.accwrite(i) - val exec_write = io.exec.accwrite(i) - - // Assertion: OpA and OpB should not access the same bank simultaneously - assert(!(exec_read_req.valid && exec_write.req.valid), - s"Bank ${i}: exec and write cannot access the same bank simultaneously") - - // Read request arbitration: priority exec > main - val exec_read_sel = exec_read_req.valid - val main_read_sel = main_read_req.valid && !exec_read_sel - - // Write request arbitration: exec has higher priority - val exec_write_sel = exec_write.req.valid + val main_robid = main_write.rob_id + val exec_robid = exec_write.rob_id // Connect read request to SramBank - bank.io.read.req.valid := exec_read_sel || main_read_sel - bank.io.read.req.bits := Mux(exec_read_sel, exec_read_req.bits, main_read_req.bits) + bank.io.read.io.req.valid := exec_read_sel || main_read_sel + bank.io.read.io.req.bits := Mux(exec_read_sel, exec_read_req.bits, main_read_req.bits) // Read request ready reverse connection - main_read_req.ready := main_read_sel && bank.io.read.req.ready - exec_read_req.ready := exec_read_sel && bank.io.read.req.ready + main_read_req.ready := main_read_sel && bank.io.read.io.req.ready + exec_read_req.ready := exec_read_sel && bank.io.read.io.req.ready // Record which client initiated read request (for response distribution) - val resp_to_main = RegNext(main_read_sel && bank.io.read.req.fire, false.B) - val resp_to_exec = RegNext(exec_read_sel && bank.io.read.req.fire, false.B) + val resp_to_main = RegNext(main_read_sel && bank.io.read.io.req.fire, false.B) + val resp_to_exec = RegNext(exec_read_sel && bank.io.read.io.req.fire, false.B) // Read response distribution - io.dma.accread(i).resp.valid := bank.io.read.resp.valid && resp_to_main - io.dma.accread(i).resp.bits := bank.io.read.resp.bits + io.dma.sramread(i).io.resp.valid := bank.io.read.io.resp.valid && resp_to_main + io.dma.sramread(i).io.resp.bits := bank.io.read.io.resp.bits - io.exec.accread(i).resp.valid := bank.io.read.resp.valid && resp_to_exec - io.exec.accread(i).resp.bits := bank.io.read.resp.bits + io.exec.sramread(i).io.resp.valid := bank.io.read.io.resp.valid && resp_to_exec + io.exec.sramread(i).io.resp.bits := bank.io.read.io.resp.bits // Read response ready signal: either client ready is sufficient - bank.io.read.resp.ready := - (resp_to_main && io.dma.accread(i).resp.ready) || - (resp_to_exec && io.exec.accread(i).resp.ready) + bank.io.read.io.resp.ready := + (resp_to_main && io.dma.sramread(i).io.resp.ready) || + (resp_to_exec && io.exec.sramread(i).io.resp.ready) // Connect write request to SramBank - bank.io.write.req.valid := Mux(exec_write_sel, exec_write.req.valid, main_write.req.valid) - bank.io.write.req.bits.addr := Mux(exec_write_sel, exec_write.req.bits.addr, main_write.req.bits.addr) - bank.io.write.req.bits.data := Mux(exec_write_sel, exec_write.req.bits.data, main_write.req.bits.data) - bank.io.write.req.bits.mask := Mux(exec_write_sel, exec_write.req.bits.mask, main_write.req.bits.mask) - bank.io.write.is_acc := Mux(exec_write_sel, true.B, false.B) + bank.io.write.io.req.valid := Mux(exec_write_sel, exec_write.io.req.valid, main_write.io.req.valid) + bank.io.write.io.req.bits.addr := Mux(exec_write_sel, exec_write.io.req.bits.addr, main_write.io.req.bits.addr) + bank.io.write.io.req.bits.data := Mux(exec_write_sel, exec_write.io.req.bits.data, main_write.io.req.bits.data) + bank.io.write.io.req.bits.mask := Mux(exec_write_sel, exec_write.io.req.bits.mask, main_write.io.req.bits.mask) + bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, main_isacc_sel) + bank.io.write.bank_id := Mux(exec_write_sel, exec_bankid, main_bankid) + bank.io.write.rob_id := Mux(exec_write_sel, exec_robid, main_robid) // Write request ready reverse connection - main_write.req.ready := !exec_write_sel && bank.io.write.req.ready - exec_write.req.ready := exec_write_sel && bank.io.write.req.ready + main_write.io.req.ready := !exec_write_sel && bank.io.write.io.req.ready + exec_write.io.req.ready := exec_write_sel && bank.io.write.io.req.ready + + // Tie-off read metadata (unused for now) + bank.io.read.rob_id := 0.U + bank.io.read.is_acc := false.B + bank.io.read.bank_id := i.U } } From 1101258f22b9dc538af52c319030e81f2707b38b Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 18 Dec 2025 17:04:22 +0800 Subject: [PATCH 014/238] [submodules] update: bump submodule versions for compiler and palladium [arch/palladium] feat: add 256CoreCrossBarConfig --- .../scala/examples/toy/CustomConfigs.scala | 40 ++++++++++--------- .../scala/sims/palladium/TargetConfigs.scala | 7 ++++ compiler | 2 +- tools/palladium | 2 +- 4 files changed, 31 insertions(+), 20 deletions(-) diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 8d636077..abd2a5b9 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -4,17 +4,12 @@ import org.chipsalliance.cde.config.{Config, Parameters, Field} import chisel3._ import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.subsystem.SystemBusKey -// import freechips.rocketchip.tile.{BuildRoCC, OpcodeSet} import freechips.rocketchip.tile._ import examples.toy.ToyBuckyball import framework.builtin.BaseConfig import examples.BuckyballConfigs.CustomBuckyballConfig import examples.CustomBuckyballConfig -// Use standard BuildRoCC instead of BuildRoCCBB -// import framework.rocket.BuildRoCCBB -// import framework.rocket.MultiRoCCKeyBB - object BuckyballToyConfig { val defaultConfig = new BaseConfig( inputType = UInt(8.W), @@ -36,19 +31,6 @@ class BuckyballCustomConfig( ) }) -// class WithMultiRoCCToyBuckyball(harts: Int*)( -// buckyballConfig: CustomBuckyballConfig = CustomBuckyballConfig() -// ) extends Config((site, here, up) => { -// case MultiRoCCKeyBB => up(MultiRoCCKeyBB, site) ++ harts.distinct.map { i => -// (i -> Seq((p: Parameters) => { -// implicit val q = p -// val buckyball = LazyModule(new ToyBuckyball(buckyballConfig)) -// buckyball -// })) -// } -// }) - - class BuckyballToyConfig extends Config( new BuckyballCustomConfig ++ new framework.rocket.WithNBuckyballCores(1) ++ @@ -162,3 +144,25 @@ class BuckyballToy256Config extends Config( new freechips.rocketchip.subsystem.WithNBanks(32) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) + +class BuckyballToy256CBConfig extends Config( + new WithLargeBootROM(0x80000, 0x80000) ++ // 512KB BootROM at 0x80000 (for 1024 cores) + new BuckyballCustomConfig ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(7)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(6)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(5)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(4)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(3)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(2)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(1)) ++ + new framework.rocket.WithNBuckyballCores(32, location=InCluster(0)) ++ + new freechips.rocketchip.subsystem.WithCluster(7) ++ + new freechips.rocketchip.subsystem.WithCluster(6) ++ + new freechips.rocketchip.subsystem.WithCluster(5) ++ + new freechips.rocketchip.subsystem.WithCluster(4) ++ + new freechips.rocketchip.subsystem.WithCluster(3) ++ + new freechips.rocketchip.subsystem.WithCluster(2) ++ + new freechips.rocketchip.subsystem.WithCluster(1) ++ + new freechips.rocketchip.subsystem.WithCluster(0) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig) diff --git a/arch/src/main/scala/sims/palladium/TargetConfigs.scala b/arch/src/main/scala/sims/palladium/TargetConfigs.scala index 21ec9a89..e2bbcfb7 100644 --- a/arch/src/main/scala/sims/palladium/TargetConfigs.scala +++ b/arch/src/main/scala/sims/palladium/TargetConfigs.scala @@ -8,3 +8,10 @@ class BuckyballToyP2EConfig extends Config( new palladium.fpga.WithVCU19PTweaks ++ new examples.toy.BuckyballToy256Config // Test with 256 cores + 8 L2 banks ) + +// Cross-bar config +class BuckyballToyP2ECBConfig extends Config( + new palladium.fpga.WithFPGAFrequency(50) ++ + new palladium.fpga.WithVCU19PTweaks ++ + new examples.toy.BuckyballToy256CBConfig +) diff --git a/compiler b/compiler index aa00cfc3..b709653f 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit aa00cfc3548a662a616a084341eb1aeb45f15eeb +Subproject commit b709653f56d2aec77491f74be5f485cb912c80bb diff --git a/tools/palladium b/tools/palladium index 5334475a..3990e3ed 160000 --- a/tools/palladium +++ b/tools/palladium @@ -1 +1 @@ -Subproject commit 5334475ace67b2ac6dd08d09e7de0ddccb777364 +Subproject commit 3990e3edfc5176599d7789bd357ae17c2c6163cc From d4c5ad678380ddf99ee6f54745a1527f7f7314c1 Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Fri, 19 Dec 2025 12:10:05 +0800 Subject: [PATCH 015/238] [arch/memdomain] fix: resolve ther bug of CI TEST (#21) --- .../src/main/scala/framework/memdomain/mem/Scratchpad.scala | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala b/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala index 5921181b..f7d6a13f 100644 --- a/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala +++ b/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala @@ -23,15 +23,11 @@ class Scratchpad(implicit b: CustomBuckyballConfig, implicit val p: Parameters) val dma = new Bundle { val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - // val accread = Vec(acc_banks, new SramReadIO(acc_bank_entries, acc_w)) - // val accwrite = Vec(acc_banks, new SramWriteIO(acc_bank_entries, acc_w, acc_mask_len)) } // Execution unit read/write interface - one read and write per bank, OpA and OpB guaranteed to access different banks val exec = new Bundle { val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - // val accread = Vec(acc_banks, new SramReadIO(acc_bank_entries, acc_w)) - // val accwrite = Vec(acc_banks, new SramWriteIO(acc_bank_entries, acc_w, acc_mask_len)) } }) @@ -106,7 +102,7 @@ class Scratchpad(implicit b: CustomBuckyballConfig, implicit val p: Parameters) bank.io.write.io.req.bits.addr := Mux(exec_write_sel, exec_write.io.req.bits.addr, main_write.io.req.bits.addr) bank.io.write.io.req.bits.data := Mux(exec_write_sel, exec_write.io.req.bits.data, main_write.io.req.bits.data) bank.io.write.io.req.bits.mask := Mux(exec_write_sel, exec_write.io.req.bits.mask, main_write.io.req.bits.mask) - bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, main_isacc_sel) + bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, false.B) bank.io.write.bank_id := Mux(exec_write_sel, exec_bankid, main_bankid) bank.io.write.rob_id := Mux(exec_write_sel, exec_robid, main_robid) From 8789836b87e7aab821f20d077a58410889318f40 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 21 Dec 2025 02:38:16 +0800 Subject: [PATCH 016/238] [bb-test] refactor: Update memory management in sw and ISA integration --- bb-tests/sardine/package-lock.json | 9 +- bb-tests/sardine/package.json | 2 +- bb-tests/workloads/lib/bbhw/CMakeLists.txt | 35 +--- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 18 ++ bb-tests/workloads/lib/bbhw/isa/24_mvin.c | 42 +---- bb-tests/workloads/lib/bbhw/isa/25_mvout.c | 42 +---- bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c | 41 +--- .../workloads/lib/bbhw/isa/27_matmul_ws.c | 45 +---- bb-tests/workloads/lib/bbhw/isa/31_fence.c | 22 +-- .../workloads/lib/bbhw/isa/32_mul_warp16.c | 45 +---- bb-tests/workloads/lib/bbhw/isa/33_im2col.c | 54 ++---- .../workloads/lib/bbhw/isa/34_transpose.c | 41 +--- bb-tests/workloads/lib/bbhw/isa/38_relu.c | 36 +--- .../workloads/lib/bbhw/isa/39_bbus_config.c | 41 +--- bb-tests/workloads/lib/bbhw/isa/40_nnlut.c | 36 +--- bb-tests/workloads/lib/bbhw/isa/41_snn.c | 44 ++--- .../workloads/lib/bbhw/isa/42_abft_systolic.c | 42 +---- bb-tests/workloads/lib/bbhw/isa/43_conv.c | 66 ++----- bb-tests/workloads/lib/bbhw/isa/44_cim.c | 59 ++---- bb-tests/workloads/lib/bbhw/isa/45_transfer.c | 38 +--- bb-tests/workloads/lib/bbhw/isa/7_flush.c | 20 +- .../workloads/lib/bbhw/isa/CMakeLists.txt | 176 +++--------------- bb-tests/workloads/lib/bbhw/isa/README.md | 79 -------- bb-tests/workloads/lib/bbhw/isa/isa.c | 91 --------- bb-tests/workloads/lib/bbhw/isa/isa.h | 119 ++++-------- .../workloads/lib/bbhw/mem/CMakeLists.txt | 51 +++-- bb-tests/workloads/lib/bbhw/mem/bank.c | 19 -- bb-tests/workloads/lib/bbhw/mem/bank.h | 55 ------ bb-tests/workloads/lib/bbhw/mem/dma.h | 19 -- bb-tests/workloads/lib/bbhw/mem/mem.h | 6 + bb-tests/workloads/lib/bbhw/mem/params.h | 11 ++ bb-tests/workloads/lib/bbhw/mem/spad.c | 60 ------ bb-tests/workloads/lib/bbhw/mem/spad.h | 17 -- .../workloads/src/CTest/toy/CMakeLists.txt | 8 +- .../src/CTest/toy/abft_systolic_test.c | 20 +- .../workloads/src/CTest/toy/aligned_matmul.c | 22 ++- .../src/CTest/toy/bbfp_matmul_random1.c | 26 +-- .../src/CTest/toy/bbfp_matmul_random2.c | 26 +-- .../src/CTest/toy/bbfp_matmul_random3.c | 22 +-- bb-tests/workloads/src/CTest/toy/bbfpmatmul.c | 21 +-- bb-tests/workloads/src/CTest/toy/bbfptest.c | 25 ++- bb-tests/workloads/src/CTest/toy/buckyball.c | 4 +- bb-tests/workloads/src/CTest/toy/buckyball.h | 1 + bb-tests/workloads/src/CTest/toy/cim_test.c | 26 +-- bb-tests/workloads/src/CTest/toy/conv_test.c | 30 +-- .../workloads/src/CTest/toy/im2col_test.c | 21 ++- .../src/CTest/toy/mvin_mvout_acc_test.c | 12 +- .../workloads/src/CTest/toy/mvin_mvout_test.c | 11 +- bb-tests/workloads/src/CTest/toy/nnlut_test.c | 17 +- bb-tests/workloads/src/CTest/toy/relu_test.c | 18 +- bb-tests/workloads/src/CTest/toy/snn_test.c | 16 +- .../workloads/src/CTest/toy/tiled_matmul.c | 91 +++------ .../workloads/src/CTest/toy/transfer_test.c | 15 +- .../src/CTest/toy/transpose_matmul.c | 21 ++- .../workloads/src/CTest/toy/transpose_test.c | 12 +- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 18 +- .../CTest/toy/vecunit_matmul_16xn_random1.c | 22 +-- .../CTest/toy/vecunit_matmul_16xn_random2.c | 18 +- .../CTest/toy/vecunit_matmul_16xn_random3.c | 18 +- .../toy/vecunit_matmul_16xn_zero_random.c | 18 +- .../CTest/toy/vecunit_matmul_col_row_vector.c | 18 +- .../toy/vecunit_matmul_identity_random.c | 18 +- .../src/CTest/toy/vecunit_matmul_ones.c | 18 +- .../src/CTest/toy/vecunit_matmul_random1.c | 18 +- .../src/CTest/toy/vecunit_matmul_random2.c | 18 +- .../src/CTest/toy/vecunit_matmul_random3.c | 18 +- .../CTest/toy/vecunit_matmul_row_col_vector.c | 18 +- .../CTest/toy/vecunit_matmul_zero_random.c | 18 +- .../toy/vecunit_simple_nn_forward_pass_test.c | 20 +- 69 files changed, 665 insertions(+), 1539 deletions(-) create mode 100644 bb-tests/workloads/lib/bbhw/isa/23_mset.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/README.md delete mode 100644 bb-tests/workloads/lib/bbhw/mem/bank.c delete mode 100644 bb-tests/workloads/lib/bbhw/mem/bank.h delete mode 100644 bb-tests/workloads/lib/bbhw/mem/dma.h create mode 100644 bb-tests/workloads/lib/bbhw/mem/mem.h create mode 100644 bb-tests/workloads/lib/bbhw/mem/params.h delete mode 100644 bb-tests/workloads/lib/bbhw/mem/spad.c delete mode 100644 bb-tests/workloads/lib/bbhw/mem/spad.h diff --git a/bb-tests/sardine/package-lock.json b/bb-tests/sardine/package-lock.json index c2f45d29..7ab7d6c7 100644 --- a/bb-tests/sardine/package-lock.json +++ b/bb-tests/sardine/package-lock.json @@ -5,15 +5,14 @@ "packages": { "": { "dependencies": { - "allure-commandline": "^2.34.1", + "allure-commandline": "^2.36.0", "httpx": "^3.0.1" } }, "node_modules/allure-commandline": { - "version": "2.34.1", - "resolved": "https://registry.npmjs.org/allure-commandline/-/allure-commandline-2.34.1.tgz", - "integrity": "sha512-l42csZ2bz7FdtJI1t5zA3IXtOZ0YJaP/+JMRC9gt6aBHRVUIu+6r+3F7KRyshQ79osLz9/MHlGqAjBPRqH0QFw==", - "license": "Apache-2.0", + "version": "2.36.0", + "resolved": "https://registry.npmjs.org/allure-commandline/-/allure-commandline-2.36.0.tgz", + "integrity": "sha512-ls/4fk2Psv2Tu2PbWFrQPmUnm3gmmO9MBan4MuPWwqdkJPEmln2KRwtvtWYr9Av+e5AnFK1fGXWVyxqJIPiPwA==", "bin": { "allure": "bin/allure" } diff --git a/bb-tests/sardine/package.json b/bb-tests/sardine/package.json index 3c6abc82..5d71a221 100644 --- a/bb-tests/sardine/package.json +++ b/bb-tests/sardine/package.json @@ -1,6 +1,6 @@ { "dependencies": { - "allure-commandline": "^2.34.1", + "allure-commandline": "^2.36.0", "httpx": "^3.0.1" } } diff --git a/bb-tests/workloads/lib/bbhw/CMakeLists.txt b/bb-tests/workloads/lib/bbhw/CMakeLists.txt index 32b5a090..90e67f68 100644 --- a/bb-tests/workloads/lib/bbhw/CMakeLists.txt +++ b/bb-tests/workloads/lib/bbhw/CMakeLists.txt @@ -1,8 +1,5 @@ -set(ELF_CC "riscv64-unknown-elf-gcc") -set(LINUX_CC "riscv64-unknown-linux-gnu-gcc") - #------------------------------------------------------------------------------- -# Add subdirectories, each compiles three versions +# Add subdirectories #------------------------------------------------------------------------------- add_subdirectory(mem) add_subdirectory(isa) @@ -10,8 +7,6 @@ add_subdirectory(isa) #------------------------------------------------------------------------------- # Combine final library - only responsible for linking submodules #------------------------------------------------------------------------------- -set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-gcc") # 1. Linux version - merge Linux versions of submodules add_custom_command( @@ -29,34 +24,6 @@ add_custom_command( add_custom_target(bbhw-linux ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-linux.a) -#------------------------------------------------------------------------------- -# build linux version library -#------------------------------------------------------------------------------- -set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") - -#------------------------------------------------------------------------------- -# Generate x86_64 version library (for toy project) -#------------------------------------------------------------------------------- -# 3. x86 version - combine x86 versions of submodules -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-x86.a - COMMAND ${CMAKE_COMMAND} -E make_directory temp_extract - COMMAND ${CMAKE_COMMAND} -E chdir temp_extract ar x ../mem/libbbmem-x86.a - COMMAND ${CMAKE_COMMAND} -E chdir temp_extract ar x ../isa/libbbisa-x86.a - COMMAND ar rcs libbbhw-x86.a temp_extract/*.o - COMMAND ranlib libbbhw-x86.a - COMMAND ${CMAKE_COMMAND} -E remove_directory temp_extract - DEPENDS bbisa-x86-build bbmem-x86-build - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Combining x86_64 version of bbhw library" -) - -add_custom_target(bbhw-x86 ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-x86.a) - -#------------------------------------------------------------------------------- -# Set baremetal compilation flags -#------------------------------------------------------------------------------- - # 2. Baremetal version - merge Baremetal versions of submodules add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-baremetal.a diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c new file mode 100644 index 00000000..d1600937 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -0,0 +1,18 @@ +#ifndef _BB_MSET_H_ +#define _BB_MSET_H_ + +#include "isa.h" + +#define BB_MSET_FUNC7 23 + +#define bb_mset(relase_en, bank_id, alloc_en, bank_num, row, col) \ + ({ \ + BUCKYBALL_INSTRUCTION_R_R((FIELD(alloc_en, 0, 0) | FIELD(bank_id, 1, 13)), \ + (FIELD(relase_en, 0, 0) | \ + FIELD(bank_num, 1, 5) | FIELD(row, 6, 9) | \ + FIELD(col, 10, 17)), \ + BB_MSET_FUNC7); \ + (bank_id); \ + }) + +#endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c index 1e2dae37..19c1ffc8 100644 --- a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c @@ -1,36 +1,14 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig mvin_config = { - .rs1_fields = (BitFieldConfig[]){{"base_dram_addr", 0, 31}, {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"base_sp_addr", 0, 14}, - {"iter", 15, 24}, - {"stride", 24, 33}, - {NULL, 0, 0}}}; +#ifndef _BB_MVIN_H_ +#define _BB_MVIN_H_ -// =========================== for CTest =========================== -#define MVIN_ENCODE_RS1(dram_addr) ENCODE_FIELD(dram_addr, 0, 32) +#include "isa.h" -#define MVIN_ENCODE_RS2(sp_addr, iter, stride) \ - (ENCODE_FIELD(sp_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(stride, 25, 10)) +#define BB_MVIN_FUNC7 24 -// MVIN instruction low-level implementation -#ifndef __x86_64__ -#define MVIN_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 24, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define MVIN_RAW(rs1, rs2) -#endif +#define bb_mvin(mem_addr, bank_id, depth, stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + FIELD(mem_addr, 0, 14), \ + (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 31)), \ + BB_MVIN_FUNC7) -// MVIN instruction high-level API implementation -void bb_mvin(uint64_t mem_addr, uint32_t sp_addr, uint32_t iter, - uint32_t stride) { - uint64_t rs1_val = MVIN_ENCODE_RS1(mem_addr); - uint64_t rs2_val = MVIN_ENCODE_RS2(sp_addr, iter, stride); - MVIN_RAW(rs1_val, rs2_val); -} +#endif // _BB_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c index fe44d0f0..03c5b450 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c @@ -1,36 +1,14 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig mvout_config = { - .rs1_fields = (BitFieldConfig[]){{"base_dram_addr", 0, 31}, {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"base_sp_addr", 0, 14}, - {"iter", 15, 24}, - {"stride", 24, 33}, - {NULL, 0, 0}}}; +#ifndef _BB_MVOUT_H_ +#define _BB_MVOUT_H_ -// =========================== for CTest =========================== -#define MVOUT_ENCODE_RS1(dram_addr) ENCODE_FIELD(dram_addr, 0, 32) +#include "isa.h" -#define MVOUT_ENCODE_RS2(sp_addr, iter, stride) \ - (ENCODE_FIELD(sp_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(stride, 25, 10)) +#define BB_MVOUT_FUNC7 25 -// MVOUT instruction low-level implementation -#ifndef __x86_64__ -#define MVOUT_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 25, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define MVOUT_RAW(rs1, rs2) -#endif +#define bb_mvout(mem_addr, bank_id, depth, stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + FIELD(mem_addr, 0, 14), \ + (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 31)), \ + BB_MVOUT_FUNC7) -// MVOUT instruction high-level API implementation -void bb_mvout(uint64_t mem_addr, uint32_t sp_addr, uint32_t iter, - uint32_t stride) { - uint64_t rs1_val = MVOUT_ENCODE_RS1(mem_addr); - uint64_t rs2_val = MVOUT_ENCODE_RS2(sp_addr, iter, stride); - MVOUT_RAW(rs1_val, rs2_val); -} +#endif // _BB_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c b/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c index 0d61ddb1..1456c9db 100644 --- a/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c +++ b/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c @@ -1,36 +1,13 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig bbfp_mul_config = { - .rs1_fields = (BitFieldConfig[]){{"op1_spaddr", 0, 14}, - {"op2_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"wr_spaddr", 0, 14}, {"iter", 15, 24}, {NULL, 0, 0}}}; +#ifndef _BBFP_MUL_H_ +#define _BBFP_MUL_H_ -// =========================== for CTest =========================== -#define BBFP_MUL_ENCODE_RS1(op1_addr, op2_addr) \ - (ENCODE_FIELD(op1_addr, 0, 15) | ENCODE_FIELD(op2_addr, 15, 15)) +#include "isa.h" -#define BBFP_MUL_ENCODE_RS2(wr_addr, iter) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10)) +#define BB_BBFP_MUL_FUNC7 26 -// BBFP_MUL instruction low-level implementation -#ifndef __x86_64__ -#define BBFP_MUL_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 26, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define BBFP_MUL_RAW(rs1, rs2) -#endif +#define bb_bbfp_mul(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(wr_bank_id, 16, 23) | FIELD(iter, 24, 33)), BB_BBFP_MUL_FUNC7) -// BBFP_MUL instruction high-level API implementation -void bb_bbfp_mul(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter) { - uint64_t rs1_val = BBFP_MUL_ENCODE_RS1(op1_addr, op2_addr); - uint64_t rs2_val = BBFP_MUL_ENCODE_RS2(wr_addr, iter); - BBFP_MUL_RAW(rs1_val, rs2_val); -} +#endif // _BBFP_MUL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c index 13f7ecf6..64ef6f56 100644 --- a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c +++ b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c @@ -1,39 +1,14 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig matmul_ws_config = { - .rs1_fields = (BitFieldConfig[]){{"op1_spaddr", 0, 14}, - {"op2_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"wr_spaddr", 0, 14}, - {"iter", 15, 24}, - {"ws_flag", 25, 25}, - {NULL, 0, 0}}}; +#ifndef _MATMUL_WS_H_ +#define _MATMUL_WS_H_ -// =========================== for CTest =========================== -#define MATMUL_WS_ENCODE_RS1(op1_addr, op2_addr) \ - (ENCODE_FIELD(op1_addr, 0, 15) | ENCODE_FIELD(op2_addr, 15, 15)) +#include "isa.h" -#define MATMUL_WS_ENCODE_RS2(wr_addr, iter, ws_flag) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(ws_flag, 25, 1)) +#define BB_MATMUL_WS_FUNC7 27 -// MATMUL_WS instruction low-level implementation -#ifndef __x86_64__ -#define MATMUL_WS_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 27, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define MATMUL_WS_RAW(rs1, rs2) -#endif +#define bb_matmul_ws(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(wr_bank_id, 16, 23) | FIELD(iter, 24, 33) | FIELD(1, 34, 34)), \ + BB_MATMUL_WS_FUNC7) -// MATMUL_WS instruction high-level API implementation -void bb_matmul_ws(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter) { - uint64_t rs1_val = MATMUL_WS_ENCODE_RS1(op1_addr, op2_addr); - uint64_t rs2_val = MATMUL_WS_ENCODE_RS2(wr_addr, iter, 1); - MATMUL_WS_RAW(rs1_val, rs2_val); -} +#endif // _MATMUL_WS_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/31_fence.c b/bb-tests/workloads/lib/bbhw/isa/31_fence.c index dc6ada62..46fb4878 100644 --- a/bb-tests/workloads/lib/bbhw/isa/31_fence.c +++ b/bb-tests/workloads/lib/bbhw/isa/31_fence.c @@ -1,20 +1,10 @@ +#ifndef _BB_FENCE_H_ +#define _BB_FENCE_H_ + #include "isa.h" -// =========================== for CTest =========================== -// FENCE instruction has no parameters, define assembly macro directly +#define BB_FENCE_FUNC7 31 -// FENCE instruction low-level implementation -#ifndef __x86_64__ -#define FENCE_RAW() \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 31, x0, x0, x0" \ - : \ - : \ - : "memor" \ - "y") -#else -// Do not execute RISC-V instructions on x86 platform -#define FENCE_RAW() -#endif +#define bb_fence() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7) -// FENCE instruction high-level API implementation -void bb_fence(void) { FENCE_RAW(); } +#endif // _BB_FENCE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c index 406ec367..2de6c03a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c @@ -1,39 +1,14 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig mul_warp16_config = { - .rs1_fields = (BitFieldConfig[]){{"op1_spaddr", 0, 14}, - {"op2_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"wr_spaddr", 0, 14}, - {"iter", 15, 24}, - {"mode", 25, 25}, - {NULL, 0, 0}}}; +#ifndef _BB_MUL_WARP16_H_ +#define _BB_MUL_WARP16_H_ -// =========================== for CTest =========================== -#define MUL_WARP16_ENCODE_RS1(op1_addr, op2_addr) \ - (ENCODE_FIELD(op1_addr, 0, 15) | ENCODE_FIELD(op2_addr, 15, 15)) +#include "isa.h" -#define MUL_WARP16_ENCODE_RS2(wr_addr, iter, mode) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(mode, 25, 1)) +#define BB_MUL_WARP16_FUNC7 32 -// MUL_WARP16 instruction low-level implementation -#ifndef __x86_64__ -#define MUL_WARP16_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 32, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define MUL_WARP16_RAW(rs1, rs2) -#endif +#define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(wr_bank_id, 16, 23) | FIELD(iter, 24, 33) | FIELD(mode, 34, 34)), \ + BB_MUL_WARP16_FUNC7) -// MUL_WARP16 instruction high-level API implementation -void bb_mul_warp16(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter, uint32_t mode) { - uint64_t rs1_val = MUL_WARP16_ENCODE_RS1(op1_addr, op2_addr); - uint64_t rs2_val = MUL_WARP16_ENCODE_RS2(wr_addr, iter, mode); - MUL_WARP16_RAW(rs1_val, rs2_val); -} +#endif // _BB_MUL_WARP16_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c index 34508494..1eac76bc 100644 --- a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c +++ b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c @@ -1,45 +1,17 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig im2col_config = { - .rs1_fields = (BitFieldConfig[]){{"op_spaddr", 0, 14}, - {"wr_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"kcol", 26, 29}, - {"krow", 30, 33}, - {"incol", 34, 38}, - {"inrow", 39, 43}, - {"startcol", 49, 53}, - {"startrow", 54, 58}, - {NULL, 0, 0}}}; +#ifndef _BB_IM2COL_H_ +#define _BB_IM2COL_H_ -// =========================== for CTest =========================== -#define IM2COL_ENCODE_RS1(op_addr, wr_addr) \ - (ENCODE_FIELD(op_addr, 0, 15) | ENCODE_FIELD(wr_addr, 15, 15)) +#include "isa.h" -#define IM2COL_ENCODE_RS2(krow, kcol, inrow, incol, startrow, startcol) \ - (ENCODE_FIELD(kcol, 26, 4) | ENCODE_FIELD(krow, 30, 4) | \ - ENCODE_FIELD(incol, 34, 5) | ENCODE_FIELD(inrow, 39, 5) | \ - ENCODE_FIELD(startcol, 49, 5) | ENCODE_FIELD(startrow, 54, 5)) +#define BB_IM2COL_FUNC7 33 -// IM2COL instruction low-level implementation -#ifndef __x86_64__ -#define IM2COL_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 33, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define IM2COL_RAW(rs1, rs2) -#endif +#define bb_im2col(op1_bank_id, wr_bank_id, krow, kcol, inrow, incol, startrow, \ + startcol) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ + (FIELD(kcol, 26, 29) | FIELD(krow, 30, 33) | FIELD(incol, 34, 38) | \ + FIELD(inrow, 39, 43) | FIELD(startcol, 49, 53) | \ + FIELD(startrow, 54, 58)), \ + BB_IM2COL_FUNC7) -// IM2COL instruction high-level API implementation -void bb_im2col(uint32_t op1_addr, uint32_t wr_addr, uint32_t krow, - uint32_t kcol, uint32_t inrow, uint32_t incol, uint32_t startrow, - uint32_t startcol) { - uint64_t rs1_val = IM2COL_ENCODE_RS1(op1_addr, wr_addr); - uint64_t rs2_val = - IM2COL_ENCODE_RS2(krow, kcol, inrow, incol, startrow, startcol); - IM2COL_RAW(rs1_val, rs2_val); -} +#endif // _BB_IM2COL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c index f2c8d492..6b7aefae 100644 --- a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c +++ b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c @@ -1,36 +1,13 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig transpose_config = { - .rs1_fields = (BitFieldConfig[]){{"op_spaddr", 0, 14}, - {"wr_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = - (BitFieldConfig[]){{"mode", 25, 25}, {"iter", 15, 24}, {NULL, 0, 0}}}; +#ifndef _BB_TRANSPOSE_H_ +#define _BB_TRANSPOSE_H_ -// =========================== for CTest =========================== -#define TRANSPOSE_ENCODE_RS1(op_addr, wr_addr) \ - (ENCODE_FIELD(op_addr, 0, 15) | ENCODE_FIELD(wr_addr, 15, 15)) +#include "isa.h" -#define TRANSPOSE_ENCODE_RS2(iter, mode) \ - (ENCODE_FIELD(iter, 15, 10) | ENCODE_FIELD(mode, 25, 1)) +#define BB_TRANSPOSE_FUNC7 34 -// TRANSPOSE instruction low-level implementation -#ifndef __x86_64__ -#define TRANSPOSE_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 34, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define TRANSPOSE_RAW(rs1, rs2) -#endif +#define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ + (FIELD(iter, 15, 24) | FIELD(mode, 25, 25)), BB_TRANSPOSE_FUNC7) -// TRANSPOSE instruction high-level API implementation -void bb_transpose(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter, - uint32_t mode) { - uint64_t rs1_val = TRANSPOSE_ENCODE_RS1(op1_addr, wr_addr); - uint64_t rs2_val = TRANSPOSE_ENCODE_RS2(iter, mode); - TRANSPOSE_RAW(rs1_val, rs2_val); -} +#endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/38_relu.c b/bb-tests/workloads/lib/bbhw/isa/38_relu.c index e829d4ad..02a91d7f 100644 --- a/bb-tests/workloads/lib/bbhw/isa/38_relu.c +++ b/bb-tests/workloads/lib/bbhw/isa/38_relu.c @@ -1,31 +1,13 @@ -#include "isa.h" +#ifndef _BB_RELU_H_ +#define _BB_RELU_H_ -// =========================== for simulator =========================== -const InstructionConfig relu_config = { - .rs1_fields = (BitFieldConfig[]){{"op_spaddr", 0, 14}, {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"wr_spaddr", 0, 14}, {"iter", 15, 24}, {NULL, 0, 0}}}; +#include "isa.h" -// =========================== for CTest =========================== -#define RELU_ENCODE_RS1(op_addr) (ENCODE_FIELD(op_addr, 0, 15)) -#define RELU_ENCODE_RS2(wr_addr, iter) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10)) +#define BB_RELU_FUNC7 38 -// RELU instruction low-level implementation -#ifndef __x86_64__ -#define RELU_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 38, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define RELU_RAW(rs1, rs2) -#endif +#define bb_relu(bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(bank_id, 0, 7), \ + FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 17), \ + BB_RELU_FUNC7) -// RELU instruction high-level API implementation -void bb_relu(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter) { - uint64_t rs1_val = RELU_ENCODE_RS1(op1_addr); - uint64_t rs2_val = RELU_ENCODE_RS2(wr_addr, iter); - RELU_RAW(rs1_val, rs2_val); -} +#endif // _BB_RELU_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c index 7cab7796..b214dc27 100644 --- a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c +++ b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c @@ -1,35 +1,14 @@ +#ifndef _BB_BBUS_CONFIG_H_ +#define _BB_BBUS_CONFIG_H_ + #include "isa.h" -#include -#include -// =========================== for simulator =========================== -const InstructionConfig bbus_config_config = { - .rs1_fields = (BitFieldConfig[]){{NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"src_bid", 25, 30}, - {"dst_bid", 31, 36}, - {"enable", 37, 37}, - {NULL, 0, 0}}}; -// =========================== for CTest =========================== -#define bbus_config_ENCODE_RS1(op_addr) (0) -#define bbus_config_ENCODE_RS2(src_bid, dst_bid, enable) \ - (ENCODE_FIELD(src_bid, 25, 6) | ENCODE_FIELD(dst_bid, 31, 6) | \ - ENCODE_FIELD(enable, 37, 1)) +#define BB_BBUS_CONFIG_FUNC7 39 -// bbus_config instruction low-level implementation -#ifndef __x86_64__ -#define bbus_config_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 39, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define bbus_config_RAW(rs1, rs2) -#endif +#define bb_bbus_config(src_bid, dst_bid, enable) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(src_bid, 25, 30) | FIELD(dst_bid, 31, 36) | \ + FIELD(enable, 37, 37)), \ + BB_BBUS_CONFIG_FUNC7) -// bbus_config instruction high-level API implementation -void bb_bbus_config(uint32_t src_bid, uint32_t dst_bid, uint64_t enable) { - uint64_t rs1_val = bbus_config_ENCODE_RS1(0); - uint64_t rs2_val = bbus_config_ENCODE_RS2(src_bid, dst_bid, enable); - bbus_config_RAW(rs1_val, rs2_val); -} +#endif // _BB_BBUS_CONFIG_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c index b20bc8cb..a6b174ff 100644 --- a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c +++ b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c @@ -1,31 +1,13 @@ -#include "isa.h" +#ifndef _BB_NNLUT_H_ +#define _BB_NNLUT_H_ -// =========================== for simulator =========================== -const InstructionConfig nnlut_config = { - .rs1_fields = (BitFieldConfig[]){{"op_spaddr", 0, 14}, {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"wr_spaddr", 0, 14}, {"iter", 15, 24}, {NULL, 0, 0}}}; +#include "isa.h" -// =========================== for CTest =========================== -#define NNLUT_ENCODE_RS1(op_addr) (ENCODE_FIELD(op_addr, 0, 15)) -#define NNLUT_ENCODE_RS2(wr_addr, iter) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10)) +#define BB_NNLUT_FUNC7 40 -// NNLUT instruction low-level implementation -#ifndef __x86_64__ -#define NNLUT_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 40, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define NNLUT_RAW(rs1, rs2) -#endif +#define bb_nnlut(op1_addr, wr_addr, iter) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_addr, 0, 14), \ + (FIELD(wr_addr, 0, 14) | FIELD(iter, 15, 24)), \ + BB_NNLUT_FUNC7) -// NNLUT instruction high-level API implementation -void bb_nnlut(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter) { - uint64_t rs1_val = NNLUT_ENCODE_RS1(op1_addr); - uint64_t rs2_val = NNLUT_ENCODE_RS2(wr_addr, iter); - NNLUT_RAW(rs1_val, rs2_val); -} +#endif // _BB_NNLUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_snn.c b/bb-tests/workloads/lib/bbhw/isa/41_snn.c index 2e4980d3..f52e52aa 100644 --- a/bb-tests/workloads/lib/bbhw/isa/41_snn.c +++ b/bb-tests/workloads/lib/bbhw/isa/41_snn.c @@ -1,36 +1,14 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig snn_config = { - .rs1_fields = (BitFieldConfig[]){{"op_spaddr", 0, 14}, {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){{"wr_spaddr", 0, 14}, - {"iter", 15, 24}, - {"threshold", 25, 32}, - {"leak_factor", 33, 40}, - {NULL, 0, 0}}}; +#ifndef _BB_SNN_H_ +#define _BB_SNN_H_ -// =========================== for CTest =========================== -#define SNN_ENCODE_RS1(op_addr) (ENCODE_FIELD(op_addr, 0, 15)) -#define SNN_ENCODE_RS2(wr_addr, iter, threshold, leak_factor) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(threshold, 25, 8) | ENCODE_FIELD(leak_factor, 33, 8)) +#include "isa.h" -// SNN instruction low-level implementation -#ifndef __x86_64__ -#define SNN_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 41, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define SNN_RAW(rs1, rs2) -#endif +#define BB_SNN_FUNC7 41 +#define bb_snn(op1_addr, wr_addr, iter, threshold, leak_factor) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_addr, 0, 14), \ + (FIELD(wr_addr, 0, 14) | FIELD(iter, 15, 24) | \ + FIELD(threshold, 25, 32) | \ + FIELD(leak_factor, 33, 40)), \ + BB_SNN_FUNC7) -// SNN instruction high-level API implementation -void bb_snn(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter, - uint32_t threshold, uint32_t leak_factor) { - uint64_t rs1_val = SNN_ENCODE_RS1(op1_addr); - uint64_t rs2_val = SNN_ENCODE_RS2(wr_addr, iter, threshold, leak_factor); - SNN_RAW(rs1_val, rs2_val); -} +#endif // _BB_SNN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c index d6e806d5..f9bf354a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c +++ b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c @@ -1,36 +1,12 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig abft_systolic_config = { - .rs1_fields = (BitFieldConfig[]){{"op1_spaddr", 0, 14}, - {"op2_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"wr_spaddr", 0, 14}, {"iter", 15, 24}, {NULL, 0, 0}}}; +#ifndef _BB_ABFT_SYSTOLIC_H_ +#define _BB_ABFT_SYSTOLIC_H_ -// =========================== for CTest =========================== -#define ABFT_SYSTOLIC_ENCODE_RS1(op1_addr, op2_addr) \ - (ENCODE_FIELD(op1_addr, 0, 15) | ENCODE_FIELD(op2_addr, 15, 15)) - -#define ABFT_SYSTOLIC_ENCODE_RS2(wr_addr, iter) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10)) +#include "isa.h" -// ABFT_SYSTOLIC instruction low-level implementation -#ifndef __x86_64__ -#define ABFT_SYSTOLIC_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 42, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define ABFT_SYSTOLIC_RAW(rs1, rs2) -#endif +#define BB_ABFT_SYSTOLIC_FUNC7 42 +#define bb_abft_systolic(op1_addr, op2_addr, wr_addr, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_addr, 0, 14) | FIELD(op2_addr, 15, 29)), \ + (FIELD(wr_addr, 0, 14) | FIELD(iter, 15, 24)), BB_ABFT_SYSTOLIC_FUNC7) -// ABFT_SYSTOLIC instruction high-level API implementation -void bb_abft_systolic(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter) { - uint64_t rs1_val = ABFT_SYSTOLIC_ENCODE_RS1(op1_addr, op2_addr); - uint64_t rs2_val = ABFT_SYSTOLIC_ENCODE_RS2(wr_addr, iter); - ABFT_SYSTOLIC_RAW(rs1_val, rs2_val); -} +#endif // _BB_ABFT_SYSTOLIC_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_conv.c b/bb-tests/workloads/lib/bbhw/isa/43_conv.c index 47261d3d..e8bfa393 100644 --- a/bb-tests/workloads/lib/bbhw/isa/43_conv.c +++ b/bb-tests/workloads/lib/bbhw/isa/43_conv.c @@ -1,57 +1,17 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig conv_config = { - .rs1_fields = (BitFieldConfig[]){{"ifmap_spaddr", 0, 14}, - {"weight_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"ofmap_spaddr", 0, 14}, - {"iter", 15, 24}, - // special field is 40 bits: rs2(63, spAddrLen + 10) = rs2(63, 24) = 40 - // bits Encode: in_height[15:0], in_width[31:16], kernel_h[39:32], - // kernel_w[47:40] but only 40 bits available Adjust: use - // in_height[15:0], in_width[31:16], kernel_h[39:32], kernel_w same as - // kernel_h - {"in_height", 25, 40}, - {"in_width", 41, 56}, - {"kernel_h", 57, 64}, - {NULL, 0, 0}}}; +#ifndef _BB_CONV_H_ +#define _BB_CONV_H_ -// =========================== for CTest =========================== -#define CONV_ENCODE_RS1(ifmap_addr, weight_addr) \ - (ENCODE_FIELD(ifmap_addr, 0, 15) | ENCODE_FIELD(weight_addr, 15, 15)) +#include "isa.h" -// Note: special field is only 40 bits (rs2[63:24]) -// DomainDecoder extracts rs2(63, spAddrLen + 10) = rs2(63, 24) for special -// So special[39:0] = rs2[63:24] -// Encode in special: in_height[15:0] = special[15:0], in_width[15:0] = -// special[31:16], kernel_h[7:0] = special[39:32] kernel_w is assumed to equal -// kernel_h for simplicity -#define CONV_ENCODE_RS2(ofmap_addr, iter, in_height, in_width, kernel_h, \ - kernel_w) \ - (ENCODE_FIELD(ofmap_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(in_height, 24, 16) | ENCODE_FIELD(in_width, 40, 16) | \ - ENCODE_FIELD(kernel_h, 56, 8)) +#define BB_CONV_FUNC7 43 -// CONV instruction low-level implementation -#ifndef __x86_64__ -#define CONV_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 43, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define CONV_RAW(rs1, rs2) -#endif +#define bb_conv(ifmap_addr, weight_addr, ofmap_addr, iter, in_height, \ + in_width, kernel_h, kernel_w) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(ifmap_addr, 0, 14) | FIELD(weight_addr, 15, 29)), \ + (FIELD(ofmap_addr, 0, 14) | FIELD(iter, 15, 24) | \ + FIELD(in_height, 25, 40) | FIELD(in_width, 41, 56) | \ + FIELD(kernel_h, 57, 64)), \ + BB_CONV_FUNC7) -// CONV instruction high-level API implementation -void bb_conv(uint32_t ifmap_addr, uint32_t weight_addr, uint32_t ofmap_addr, - uint32_t iter, uint32_t in_height, uint32_t in_width, - uint32_t kernel_h, uint32_t kernel_w) { - uint64_t rs1_val = CONV_ENCODE_RS1(ifmap_addr, weight_addr); - uint64_t rs2_val = CONV_ENCODE_RS2(ofmap_addr, iter, in_height, in_width, - kernel_h, kernel_w); - CONV_RAW(rs1_val, rs2_val); -} +#endif // _BB_CONV_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/44_cim.c b/bb-tests/workloads/lib/bbhw/isa/44_cim.c index fb12e53d..0986110e 100644 --- a/bb-tests/workloads/lib/bbhw/isa/44_cim.c +++ b/bb-tests/workloads/lib/bbhw/isa/44_cim.c @@ -1,51 +1,14 @@ -#include "isa.h" - -// =========================== for simulator =========================== -const InstructionConfig cim_config = { - .rs1_fields = (BitFieldConfig[]){{"op1_spaddr", 0, 14}, - {"op2_spaddr", 15, 29}, - {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"result_spaddr", 0, 14}, - {"iter", 15, 24}, - // special field is 40 bits: rs2(63, spAddrLen + 10) = rs2(63, 24) = 40 - // bits Encode: rows[15:0], cols[31:16], op_type[35:32] - {"rows", 25, 40}, - {"cols", 41, 56}, - {"op_type", 57, 60}, - {NULL, 0, 0}}}; +#ifndef _BB_CIM_H_ +#define _BB_CIM_H_ -// =========================== for CTest =========================== -#define CIM_ENCODE_RS1(op1_addr, op2_addr) \ - (ENCODE_FIELD(op1_addr, 0, 15) | ENCODE_FIELD(op2_addr, 15, 15)) - -// Note: special field is only 40 bits (rs2[63:24]) -// DomainDecoder extracts rs2(63, spAddrLen + 10) = rs2(63, 24) for special -// So special[39:0] = rs2[63:24] -// Encode in special: rows[15:0] = special[15:0], cols[15:0] = special[31:16], -// op_type[3:0] = special[35:32] In rs2: rows in rs2[39:24], cols in rs2[55:40], -// op_type in rs2[59:56] -#define CIM_ENCODE_RS2(result_addr, iter, rows, cols, op_type) \ - (ENCODE_FIELD(result_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10) | \ - ENCODE_FIELD(rows, 24, 16) | ENCODE_FIELD(cols, 40, 16) | \ - ENCODE_FIELD(op_type, 56, 4)) +#include "isa.h" -// CIM instruction low-level implementation -#ifndef __x86_64__ -#define CIM_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 44, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define CIM_RAW(rs1, rs2) -#endif +#define BB_CIM_FUNC7 44 +#define bb_cim(op1_addr, op2_addr, result_addr, iter, rows, cols, op_type) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_addr, 0, 14) | FIELD(op2_addr, 15, 29)), \ + (FIELD(result_addr, 0, 14) | FIELD(iter, 15, 24) | FIELD(rows, 25, 40) | \ + FIELD(cols, 41, 56) | FIELD(op_type, 57, 60)), \ + BB_CIM_FUNC7) -// CIM instruction high-level API implementation -void bb_cim(uint32_t op1_addr, uint32_t op2_addr, uint32_t result_addr, - uint32_t iter, uint32_t rows, uint32_t cols, uint32_t op_type) { - uint64_t rs1_val = CIM_ENCODE_RS1(op1_addr, op2_addr); - uint64_t rs2_val = CIM_ENCODE_RS2(result_addr, iter, rows, cols, op_type); - CIM_RAW(rs1_val, rs2_val); -} +#endif // _BB_CIM_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c index 241f7605..23afd483 100644 --- a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c +++ b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c @@ -1,32 +1,14 @@ -#include "isa.h" +#ifndef _BB_TRANSFER_H_ +#define _BB_TRANSFER_H_ -// =========================== for simulator =========================== -const InstructionConfig transfer_config = { - .rs1_fields = (BitFieldConfig[]){{"op1_spaddr", 0, 14}, {NULL, 0, 0}}, - .rs2_fields = (BitFieldConfig[]){ - {"wr_spaddr", 0, 14}, {"iter", 15, 24}, {NULL, 0, 0}}}; +#include "isa.h" -// =========================== for CTest =========================== -#define TRANSFER_ENCODE_RS1(op1_addr) (ENCODE_FIELD(op1_addr, 0, 15)) -#define TRANSFER_ENCODE_RS2(wr_addr, iter) \ - (ENCODE_FIELD(wr_addr, 0, 15) | ENCODE_FIELD(iter, 15, 10)) +#define BB_TRANSFER_FUNC7 45 -// TRANSFER instruction low-level implementation -#ifndef __x86_64__ -#define TRANSFER_RAW(rs1, rs2) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 45, x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2) \ - : "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define TRANSFER_RAW(rs1, rs2) -#endif +#define bb_transfer(op1_addr, wr_addr, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + FIELD(op1_addr, 0, 14), \ + (FIELD(wr_addr, 0, 14) | FIELD((iter > 1023 ? 1023 : iter), 15, 24)), \ + BB_TRANSFER_FUNC7) -// TRANSFER instruction high-level API implementation -void bb_transfer(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter) { - if (iter > 1023) iter = 1023; - uint64_t rs1_val = TRANSFER_ENCODE_RS1(op1_addr); - uint64_t rs2_val = TRANSFER_ENCODE_RS2(wr_addr, iter); - TRANSFER_RAW(rs1_val, rs2_val); -} +#endif // _BB_TRANSFER_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/7_flush.c b/bb-tests/workloads/lib/bbhw/isa/7_flush.c index 4d37a88d..3be03848 100644 --- a/bb-tests/workloads/lib/bbhw/isa/7_flush.c +++ b/bb-tests/workloads/lib/bbhw/isa/7_flush.c @@ -1,14 +1,10 @@ +#ifndef _BB_FLUSH_H_ +#define _BB_FLUSH_H_ + #include "isa.h" -// =========================== for CTest =========================== -// FLUSH instruction low-level implementation -#ifndef __x86_64__ -#define FLUSH_RAW() \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 7, x0, x0, x0" ::: "memory") -#else -// Do not execute RISC-V instructions on x86 platform -#define FLUSH_RAW() -#endif - -// FLUSH instruction high-level API implementation -void bb_flush(void) { FLUSH_RAW(); } +#define BB_FLUSH_FUNC7 7 + +#define bb_flush() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FLUSH_FUNC7) + +#endif // _BB_FLUSH_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt b/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt index 33122850..46351c67 100644 --- a/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt +++ b/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt @@ -1,70 +1,28 @@ # ISA submodule library -set(ISA_SOURCES - isa.c - 24_mvin.c - 25_mvout.c - 31_fence.c - 32_mul_warp16.c - 26_bbfp_mul.c - 27_matmul_ws.c - 33_im2col.c - 34_transpose.c - 38_relu.c - 39_bbus_config.c - 40_nnlut.c - 41_snn.c - 42_abft_systolic.c - 43_conv.c - 44_cim.c - 45_transfer.c - 7_flush.c -) +file(GLOB ISA_C_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/*.c") # 1. Linux version add_library(bbisa-linux STATIC IMPORTED) set_target_properties(bbisa-linux PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a) +set(LINUX_OBJS "") +foreach(src ${ISA_C_SOURCES}) + get_filename_component(name ${src} NAME_WE) + set(obj "${CMAKE_CURRENT_BINARY_DIR}/linux-${name}.o") + list(APPEND LINUX_OBJS ${obj}) + add_custom_command( + OUTPUT ${obj} + COMMAND riscv64-unknown-linux-gnu-gcc -c ${src} -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../mem -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} + DEPENDS ${src} + COMMENT "Compiling ${name}.c for Linux" + ) +endforeach() + add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a - COMMAND riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/isa.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-isa.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/24_mvin.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-24_mvin.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/25_mvout.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-25_mvout.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/31_fence.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-31_fence.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/32_mul_warp16.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-32_mul_warp16.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/26_bbfp_mul.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-26_bbfp_mul.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/27_matmul_ws.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-27_matmul_ws.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/33_im2col.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-33_im2col.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/34_transpose.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-34_transpose.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/38_relu.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-38_relu.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/39_bbus_config.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-39_bbus_config.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/40_nnlut.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-40_nnlut.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/41_snn.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-41_snn.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/42_abft_systolic.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-42_abft_systolic.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/43_conv.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-43_conv.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/44_cim.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-44_cim.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/45_transfer.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-45_transfer.o - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/7_flush.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-7_flush.o - && ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a - linux-isa.o - linux-24_mvin.o - linux-25_mvout.o - linux-31_fence.o - linux-32_mul_warp16.o - linux-26_bbfp_mul.o - linux-27_matmul_ws.o - linux-33_im2col.o - linux-34_transpose.o - linux-38_relu.o - linux-39_bbus_config.o - linux-40_nnlut.o - linux-41_snn.o - linux-42_abft_systolic.o - linux-43_conv.o - linux-44_cim.o - linux-45_transfer.o - linux-7_flush.o - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND riscv64-unknown-linux-gnu-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a ${LINUX_OBJS} + DEPENDS ${LINUX_OBJS} COMMENT "Building RISC-V Linux version of ISA library" ) add_custom_target(bbisa-linux-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a) @@ -73,95 +31,23 @@ add_custom_target(bbisa-linux-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libb add_library(bbisa-baremetal STATIC IMPORTED) set_target_properties(bbisa-baremetal PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a) +set(BAREMETAL_OBJS "") +foreach(src ${ISA_C_SOURCES}) + get_filename_component(name ${src} NAME_WE) + set(obj "${CMAKE_CURRENT_BINARY_DIR}/baremetal-${name}.o") + list(APPEND BAREMETAL_OBJS ${obj}) + add_custom_command( + OUTPUT ${obj} + COMMAND riscv64-unknown-elf-gcc -c ${src} -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../mem -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} + DEPENDS ${src} + COMMENT "Compiling ${name}.c for Baremetal" + ) +endforeach() + add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a - COMMAND riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/isa.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-isa.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/24_mvin.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-24_mvin.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/25_mvout.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-25_mvout.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/31_fence.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-31_fence.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/32_mul_warp16.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-32_mul_warp16.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/26_bbfp_mul.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-26_bbfp_mul.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/27_matmul_ws.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-27_matmul_ws.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/33_im2col.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-33_im2col.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/34_transpose.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-34_transpose.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/38_relu.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-38_relu.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/39_bbus_config.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-39_bbus_config.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/40_nnlut.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-40_nnlut.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/41_snn.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-41_snn.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/42_abft_systolic.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-42_abft_systolic.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/43_conv.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-43_conv.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/44_cim.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-44_cim.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/45_transfer.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-45_transfer.o - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/7_flush.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-7_flush.o - && ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a - baremetal-isa.o - baremetal-24_mvin.o - baremetal-25_mvout.o - baremetal-31_fence.o - baremetal-32_mul_warp16.o - baremetal-26_bbfp_mul.o - baremetal-27_matmul_ws.o - baremetal-33_im2col.o - baremetal-34_transpose.o - baremetal-38_relu.o - baremetal-39_bbus_config.o - baremetal-40_nnlut.o - baremetal-41_snn.o - baremetal-42_abft_systolic.o - baremetal-43_conv.o - baremetal-44_cim.o - baremetal-45_transfer.o - baremetal-7_flush.o - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND riscv64-unknown-elf-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a ${BAREMETAL_OBJS} + DEPENDS ${BAREMETAL_OBJS} COMMENT "Building RISC-V Baremetal version of ISA library" ) add_custom_target(bbisa-baremetal-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a) - -# 3. x86 version -add_library(bbisa-x86 STATIC IMPORTED) -set_target_properties(bbisa-x86 PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-x86.a) - -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-x86.a - COMMAND gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/isa.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-isa.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/24_mvin.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-24_mvin.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/25_mvout.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-25_mvout.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/31_fence.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-31_fence.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/32_mul_warp16.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-32_mul_warp16.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/26_bbfp_mul.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-26_bbfp_mul.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/27_matmul_ws.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-27_matmul_ws.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/33_im2col.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-33_im2col.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/34_transpose.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-34_transpose.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/38_relu.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-38_relu.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/39_bbus_config.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-39_bbus_config.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/40_nnlut.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-40_nnlut.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/41_snn.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-41_snn.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/42_abft_systolic.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-42_abft_systolic.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/43_conv.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-43_conv.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/44_cim.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-44_cim.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/45_transfer.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-45_transfer.o - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/7_flush.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-7_flush.o - && ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-x86.a - x86-isa.o - x86-24_mvin.o - x86-25_mvout.o - x86-31_fence.o - x86-32_mul_warp16.o - x86-26_bbfp_mul.o - x86-27_matmul_ws.o - x86-33_im2col.o - x86-34_transpose.o - x86-38_relu.o - x86-39_bbus_config.o - x86-40_nnlut.o - x86-41_snn.o - x86-42_abft_systolic.o - x86-43_conv.o - x86-44_cim.o - x86-45_transfer.o - x86-7_flush.o - && ranlib ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-x86.a - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Building x86_64 version of ISA library" -) -add_custom_target(bbisa-x86-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-x86.a) diff --git a/bb-tests/workloads/lib/bbhw/isa/README.md b/bb-tests/workloads/lib/bbhw/isa/README.md deleted file mode 100644 index f7e15684..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/README.md +++ /dev/null @@ -1,79 +0,0 @@ -# Buckyball ISA Instruction Registration Mechanism - -## Overview - -This ISA library now supports a dynamic instruction registration mechanism, allowing you to easily add new custom instructions without modifying core code. - -## How to Add New Instructions - -### 1. Define New Instruction Type in Header File - -Add new instructions to the `InstructionType` enum in `isa.h`: - -```c -typedef enum { - // Existing instructions... - CUSTOM_ADD_FUNC7 = 50, // New custom addition instruction - CUSTOM_SUB_FUNC7 = 51, // New custom subtraction instruction -} InstructionType; -``` - -### 2. Implement Instruction Execution Function - -Create a new .c file or add to existing file: - -```c -#ifndef __x86_64__ -static void execute_custom_add(uint32_t rs1_val, uint32_t rs2_val) { - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, 50, x0, %0, %1" - : : "r"(rs1_val), "r"(rs2_val) : "memory"); -} -#else -static void execute_custom_add_nop(uint32_t rs1_val, uint32_t rs2_val) { - // No-op implementation on x86 platform -} -#endif -``` - -### 3. Register Instruction - -Register new instruction in initialization code: - -```c -void init_custom_instructions(void) { -#ifndef __x86_64__ - register_instruction(CUSTOM_ADD_FUNC7, execute_custom_add); -#else - register_instruction(CUSTOM_ADD_FUNC7, execute_custom_add_nop); -#endif -} -``` - -### 4. Use Instruction - -```c -BuckyballInstruction inst = build_instruction(CUSTOM_ADD_FUNC7); -InstructionBuilder builder = create_builder(&inst, CUSTOM_ADD_FUNC7); - -// Set parameters -builder.set.rs1(builder.set.builder_ptr, "field_name", value1); -builder.set.rs2(builder.set.builder_ptr, "field_name", value2); - -// Execute instruction -execute_builder(builder); -``` - -## Advantages - -1. **Modularity**: New instructions can be implemented in separate files -2. **Extensibility**: Add new instructions without modifying core code -3. **Platform Compatibility**: Automatically handles differences between x86 and RISC-V platforms -4. **Type Safety**: Compile-time checking of instruction types -5. **Performance**: Minimal runtime lookup overhead - -## Notes - -- func7 values must be in the range 0-127 -- Each instruction type can only be registered once -- Supports up to 16 instructions (can be adjusted by modifying MAX_INSTRUCTIONS) -- On RISC-V platforms, func7 values in inline assembly must be compile-time constants diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.c b/bb-tests/workloads/lib/bbhw/isa/isa.c index 065ec429..28315640 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.c +++ b/bb-tests/workloads/lib/bbhw/isa/isa.c @@ -1,92 +1 @@ #include "isa.h" -#include - -// =========================== for simulator =========================== -uint32_t get_bbinst_field(uint64_t value, const char *field_name, - const BitFieldConfig *config) { - for (int i = 0; config[i].name != NULL; i++) { - if (strcmp(config[i].name, field_name) == 0) { - uint32_t bit_width = config[i].end_bit - config[i].start_bit + 1; - uint64_t mask = ((1ULL << bit_width) - 1); - return (value >> config[i].start_bit) & mask; - } - } - // Field not found - return 0; -} - -void set_bbinst_field(uint64_t *value, const char *field_name, - uint32_t field_value, const BitFieldConfig *config) { - for (int i = 0; config[i].name != NULL; i++) { - if (strcmp(config[i].name, field_name) == 0) { - uint32_t bit_width = config[i].end_bit - config[i].start_bit + 1; - uint64_t mask = ((1ULL << bit_width) - 1); - // Clear original value - *value &= ~(mask << config[i].start_bit); - // Set new value - *value |= ((uint64_t)(field_value & mask) << config[i].start_bit); - return; - } - } -} - -// External configuration declarations - defined in individual instruction files -extern const InstructionConfig mvin_config; -extern const InstructionConfig mvout_config; -extern const InstructionConfig mul_warp16_config; -extern const InstructionConfig bbfp_mul_config; -extern const InstructionConfig matmul_ws_config; -extern const InstructionConfig im2col_config; -extern const InstructionConfig transpose_config; -extern const InstructionConfig relu_config; -extern const InstructionConfig bbus_config_config; -extern const InstructionConfig nnlut_config; -extern const InstructionConfig snn_config; -extern const InstructionConfig abft_systolic_config; -extern const InstructionConfig conv_config; -extern const InstructionConfig cim_config; -extern const InstructionConfig transfer_config; - -// Get instruction configuration by func7 -const InstructionConfig *config(InstructionType func7) { - switch (func7) { - case MVIN_FUNC7: - return &mvin_config; - case MVOUT_FUNC7: - return &mvout_config; - case MUL_WARP16_FUNC7: - return &mul_warp16_config; - case BBFP_MUL_FUNC7: - return &bbfp_mul_config; - case MATMUL_WS_FUNC7: - return &matmul_ws_config; - case IM2COL_FUNC7: - return &im2col_config; - case TRANSPOSE_FUNC7: - return &transpose_config; - case RELU_FUNC7: - return &relu_config; - case BBUS_CONFIG_FUNC7: - return &bbus_config_config; - case NNLUT_FUNC7: - return &nnlut_config; - case SNN_FUNC7: - return &snn_config; - case ABFT_SYSTOLIC_FUNC7: - return &abft_systolic_config; - case CONV_FUNC7: - return &conv_config; - case CIM_FUNC7: - return &cim_config; - case TRANSFER_FUNC7: - return &transfer_config; - case FENCE_FUNC7: - // FENCE instruction has no parameters, no configuration needed - return NULL; - case FLUSH_FUNC7: - // FLUSH instruction has no parameters, no configuration needed - return NULL; - default: - return NULL; - } -} diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index a3a17af1..ae7eddfa 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -4,103 +4,48 @@ #include #include -/* Pure C implementation - no C++ linkage needed */ - // Data type for matrix elements typedef int8_t elem_t; typedef int32_t result_t; // Custom instruction opcodes #define CUSTOM_3 0x7b -// String macros (from xcustom.h) + +// String macros #define STR1(x) #x #ifndef STR #define STR(x) STR1(x) #endif -// Generic field encoding macro -#define ENCODE_FIELD(value, start_bit, width) \ - (((value) & ((1ULL << (width)) - 1)) << (start_bit)) - -// Bit field configuration structure -typedef struct { - const char *name; // Field name (NULL indicates end of array) - uint32_t start_bit; // Start bit - uint32_t end_bit; // End bit (inclusive) -} BitFieldConfig; - -// Instruction type enum - directly uses func7 values -typedef enum { - MVIN_FUNC7 = 24, // 0x18 - Move in function code - MVOUT_FUNC7 = 25, // 0x19 - Move out function code - FENCE_FUNC7 = 31, // 0x1F - Fence function code - MUL_WARP16_FUNC7 = 32, // 0x20 - Matrix multiply function code - IM2COL_FUNC7 = 33, // 0x21 - Matrix im2col function code - TRANSPOSE_FUNC7 = 34, // 0x22 - Matrix transpose function code - FLUSH_FUNC7 = 7, // 0x07 - Flush function code - BBFP_MUL_FUNC7 = 26, // 0x1A - BBFP matrix multiply function code - MATMUL_WS_FUNC7 = 27, // 0x1B - Matrix multiply with warp16 function code - RELU_FUNC7 = 38, // 0x26 - ReLU activation function code - BBUS_CONFIG_FUNC7 = 39, // 0x27 - BBUS configuration function code - NNLUT_FUNC7 = 40, // 0x28 - NN-LUT lookup function code - SNN_FUNC7 = 41, // 0x29 - SNN spiking neural network function code - ABFT_SYSTOLIC_FUNC7 = 42, // 0x2A - ABFT systolic array function code - CONV_FUNC7 = 43, // 0x2B - CONV convolution function code - CIM_FUNC7 = 44, // 0x2C - CIM compute-in-memory function code - TRANSFER_FUNC7 = 45 // 0x2D - Transfer function code -} InstructionType; - -// Instruction configuration structure (for simulator) -typedef struct { - // Field configuration for rs1 register (terminated by NULL name) - const BitFieldConfig *rs1_fields; - // Field configuration for rs2 register (terminated by NULL name) - const BitFieldConfig *rs2_fields; -} InstructionConfig; - -// Generic field access functions (for simulator) -uint32_t get_bbinst_field(uint64_t value, const char *field_name, - const BitFieldConfig *config); -void set_bbinst_field(uint64_t *value, const char *field_name, - uint32_t field_value, const BitFieldConfig *config); - -// High-level API (for CTest) - -void bb_mvin(uint64_t mem_addr, uint32_t sp_addr, uint32_t iter, - uint32_t col_stride); -void bb_mvout(uint64_t mem_addr, uint32_t sp_addr, uint32_t iter, - uint32_t stride); -void bb_fence(void); -void bb_mul_warp16(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter, uint32_t mode); -void bb_bbfp_mul(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter); -void bb_matmul_ws(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter); -void bb_im2col(uint32_t op1_addr, uint32_t wr_addr, uint32_t krow, - uint32_t kcol, uint32_t inrow, uint32_t incol, uint32_t startrow, - uint32_t startcol); -void bb_transpose(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter, - uint32_t mode); -void bb_relu(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter); -void bb_bbus_config(uint32_t src_bid, uint32_t dst_bid, uint64_t enable); -void bb_nnlut(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter); -void bb_snn(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter, - uint32_t threshold, uint32_t leak_factor); -void bb_abft_systolic(uint32_t op1_addr, uint32_t op2_addr, uint32_t wr_addr, - uint32_t iter); -void bb_conv(uint32_t ifmap_addr, uint32_t weight_addr, uint32_t ofmap_addr, - uint32_t iter, uint32_t in_height, uint32_t in_width, - uint32_t kernel_h, uint32_t kernel_w); -void bb_cim(uint32_t op1_addr, uint32_t op2_addr, uint32_t result_addr, - uint32_t iter, uint32_t rows, uint32_t cols, uint32_t op_type); -void bb_transfer(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter); - -void bb_flush(void); - -// Get instruction configuration by func7 -const InstructionConfig *config(InstructionType func7); - -/* End of pure C header */ +// Field encoding macro with start and end bit +#define FIELD(val, start_bit, end_bit) \ + (((val) & ((1UL << ((end_bit) - (start_bit) + 1)) - 1)) << (start_bit)) + +// Generic RISC-V custom instruction macro +#define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ + asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c2, x0, %0, %1" \ + : \ + : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ + : "memory") + +// Include all instruction definitions +#include "23_mset.c" +#include "24_mvin.c" +#include "25_mvout.c" +#include "26_bbfp_mul.c" +#include "27_matmul_ws.c" +#include "31_fence.c" +#include "32_mul_warp16.c" +#include "33_im2col.c" +#include "34_transpose.c" +#include "38_relu.c" +#include "39_bbus_config.c" +#include "40_nnlut.c" +#include "41_snn.c" +#include "42_abft_systolic.c" +#include "43_conv.c" +#include "44_cim.c" +#include "45_transfer.c" +#include "7_flush.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt b/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt index 983452b2..4057b4aa 100644 --- a/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt +++ b/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt @@ -1,18 +1,28 @@ # MEM submodule library -set(MEM_SOURCES - bank.c - spad.c -) +file(GLOB MEM_C_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/*.c") # 1. Linux version add_library(bbmem-linux STATIC IMPORTED) set_target_properties(bbmem-linux PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a) +set(LINUX_OBJS "") +foreach(src ${MEM_C_SOURCES}) + get_filename_component(name ${src} NAME_WE) + set(obj "${CMAKE_CURRENT_BINARY_DIR}/linux-${name}.o") + list(APPEND LINUX_OBJS ${obj}) + add_custom_command( + OUTPUT ${obj} + COMMAND riscv64-unknown-linux-gnu-gcc -c ${src} -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../isa -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} + DEPENDS ${src} + COMMENT "Compiling ${name}.c for Linux" + ) +endforeach() + add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a - COMMAND riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/bank.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-bank.o && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/spad.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-spad.o && ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a linux-bank.o linux-spad.o - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND riscv64-unknown-linux-gnu-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a ${LINUX_OBJS} + DEPENDS ${LINUX_OBJS} COMMENT "Building RISC-V Linux version of MEM library" ) add_custom_target(bbmem-linux-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a) @@ -21,22 +31,23 @@ add_custom_target(bbmem-linux-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libb add_library(bbmem-baremetal STATIC IMPORTED) set_target_properties(bbmem-baremetal PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a) +set(BAREMETAL_OBJS "") +foreach(src ${MEM_C_SOURCES}) + get_filename_component(name ${src} NAME_WE) + set(obj "${CMAKE_CURRENT_BINARY_DIR}/baremetal-${name}.o") + list(APPEND BAREMETAL_OBJS ${obj}) + add_custom_command( + OUTPUT ${obj} + COMMAND riscv64-unknown-elf-gcc -c ${src} -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../isa -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} + DEPENDS ${src} + COMMENT "Compiling ${name}.c for Baremetal" + ) +endforeach() + add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a - COMMAND riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/bank.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-bank.o && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/spad.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-spad.o && ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a baremetal-bank.o baremetal-spad.o - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND riscv64-unknown-elf-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a ${BAREMETAL_OBJS} + DEPENDS ${BAREMETAL_OBJS} COMMENT "Building RISC-V Baremetal version of MEM library" ) add_custom_target(bbmem-baremetal-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a) - -# 3. x86 version -add_library(bbmem-x86 STATIC IMPORTED) -set_target_properties(bbmem-x86 PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-x86.a) - -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-x86.a - COMMAND gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/bank.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-bank.o && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/spad.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-spad.o && ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-x86.a x86-bank.o x86-spad.o && ranlib ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-x86.a - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Building x86_64 version of MEM library" -) -add_custom_target(bbmem-x86-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-x86.a) diff --git a/bb-tests/workloads/lib/bbhw/mem/bank.c b/bb-tests/workloads/lib/bbhw/mem/bank.c deleted file mode 100644 index 109bcb8c..00000000 --- a/bb-tests/workloads/lib/bbhw/mem/bank.c +++ /dev/null @@ -1,19 +0,0 @@ -#include "bank.h" - -const BankConfig bank_configs[BANK_NUM] = { - // SPAD area: bank 0-3, address 0-16383 - // bank 0: SPAD0, rows 0-4095 - {"spad0", 0, 4096, 16, 8}, - // bank 1: SPAD1, rows 4096-8191 - {"spad1", 4096, 4096, 16, 8}, - // bank 2: SPAD2, rows 8192-12287 - {"spad2", 8192, 4096, 16, 8}, - // bank 3: SPAD3, rows 12288-16383 - {"spad3", 12288, 4096, 16, 8}, - - // ACC area: bank 4+, starting at address 16384 - // (each ACC bank actually has 1024 rows, but address is aligned to 4096) - // bank 4: ACC0, rows 16384-17407 (uses first 1024 rows), accumulator uses - // 32 bits - {"acc0", 16384, 1024, 16, 32}, -}; diff --git a/bb-tests/workloads/lib/bbhw/mem/bank.h b/bb-tests/workloads/lib/bbhw/mem/bank.h deleted file mode 100644 index 8b313a1e..00000000 --- a/bb-tests/workloads/lib/bbhw/mem/bank.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef _BANK_H_ -#define _BANK_H_ - -#include - -/* Pure C implementation - no C++ linkage needed */ - -typedef struct { - const char *name_; - uint32_t base_addr_; - uint32_t row_num_; - uint32_t elem_num_; - uint32_t elem_width_; -} BankConfig; - -static inline const char *bank_name(const BankConfig *config) { - return config->name_; -} -static inline uint32_t bank_base_addr(const BankConfig *config) { - return config->base_addr_; -} -static inline uint32_t bank_row_num(const BankConfig *config) { - return config->row_num_; -} -static inline uint32_t bank_elem_num(const BankConfig *config) { - return config->elem_num_; -} -static inline uint32_t bank_elem_width(const BankConfig *config) { - return config->elem_width_; -} - -static inline uint32_t bank_row_width(const BankConfig *config) { - return config->elem_num_ * config->elem_width_; -} - -static inline uint32_t bank_row_bytes(const BankConfig *config) { - return bank_row_width(config) / 8; -} - -static inline uint32_t bank_total_size(const BankConfig *config) { - return config->row_num_ * bank_row_bytes(config); -} - -static inline uint32_t bank_addr(const BankConfig *config, uint32_t row) { - return config->base_addr_ + row; -} - -#define BANK_NUM 5 -#define DIM 16 - -extern const BankConfig bank_configs[BANK_NUM]; - -/* End of pure C header */ - -#endif // _BANK_H_ diff --git a/bb-tests/workloads/lib/bbhw/mem/dma.h b/bb-tests/workloads/lib/bbhw/mem/dma.h deleted file mode 100644 index 8203b6b7..00000000 --- a/bb-tests/workloads/lib/bbhw/mem/dma.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _DMA_H_ -#define _DMA_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define DMA_BANDWIDTH 128 - -// Get DMA row width (bytes) -static inline uint32_t dma_row_bytes() { return DMA_BANDWIDTH / 8; } - -#ifdef __cplusplus -} -#endif - -#endif // _DMA_H_ diff --git a/bb-tests/workloads/lib/bbhw/mem/mem.h b/bb-tests/workloads/lib/bbhw/mem/mem.h new file mode 100644 index 00000000..5c40881a --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/mem/mem.h @@ -0,0 +1,6 @@ +#ifndef _MEM_H_ +#define _MEM_H_ + +#include "params.h" + +#endif // _MEM_H_ diff --git a/bb-tests/workloads/lib/bbhw/mem/params.h b/bb-tests/workloads/lib/bbhw/mem/params.h new file mode 100644 index 00000000..4d6e7986 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/mem/params.h @@ -0,0 +1,11 @@ +#ifndef _PARAMS_H_ +#define _PARAMS_H_ + +// number of virtual banks +#define BANK_NUM 16 +// bank width in bits +#define BANK_WIDTH 128 +// number of lines in a bank (16KB) +#define BANK_LINES 1024 + +#endif // _PARAMS_H_ diff --git a/bb-tests/workloads/lib/bbhw/mem/spad.c b/bb-tests/workloads/lib/bbhw/mem/spad.c deleted file mode 100644 index 437fbe1d..00000000 --- a/bb-tests/workloads/lib/bbhw/mem/spad.c +++ /dev/null @@ -1,60 +0,0 @@ -#include "spad.h" - -/** - * SPAD (Scratchpad) memory address management library - * - * Provides conversion from bank and row to physical address - */ - -// Runtime interface - pure C implementation -uint32_t spad_addr(uint32_t bank, uint32_t row) { - return (bank < BANK_NUM) ? bank_addr(&bank_configs[bank], row) : -1; -} - -// Get bank number from spad address -uint32_t spad_get_bank(uint32_t addr) { - for (uint32_t bank = 0; bank < BANK_NUM; bank++) { - uint32_t base = bank_configs[bank].base_addr_; - uint32_t size = bank_configs[bank].row_num_; - if (addr >= base && addr < base + size) { - return bank; - } - } - // Bank not found - return -1; -} - -// Get offset (row) within bank from spad address -uint32_t spad_get_offset(uint32_t addr) { - for (uint32_t bank = 0; bank < BANK_NUM; bank++) { - uint32_t base = bank_configs[bank].base_addr_; - uint32_t size = bank_configs[bank].row_num_; - if (addr >= base && addr < base + size) { - return addr - base; - } - } - // Bank not found - return -1; -} - -// Get both bank and offset from spad address -void spad_get_bank_offset(uint32_t addr, uint32_t *bank, uint32_t *offset) { - for (uint32_t i = 0; i < BANK_NUM; i++) { - uint32_t base = bank_configs[i].base_addr_; - uint32_t size = bank_configs[i].row_num_; - if (addr >= base && addr < base + size) { - *bank = i; - *offset = addr - base; - return; - } - } - *bank = -1; - *offset = -1; -} - -// Get row width (bytes) of specified bank -uint32_t spad_get_bank_row_bytes(uint32_t bank) { - if (bank >= BANK_NUM) - return 0; - return bank_configs[bank].elem_num_ * bank_configs[bank].elem_width_ / 8; -} diff --git a/bb-tests/workloads/lib/bbhw/mem/spad.h b/bb-tests/workloads/lib/bbhw/mem/spad.h deleted file mode 100644 index 82015d73..00000000 --- a/bb-tests/workloads/lib/bbhw/mem/spad.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef SPAD_H -#define SPAD_H - -#include "bank.h" -#include - -/* Pure C implementation - no C++ linkage needed */ - -uint32_t spad_addr(uint32_t bank, uint32_t row); -uint32_t spad_get_bank(uint32_t addr); -uint32_t spad_get_offset(uint32_t addr); -void spad_get_bank_offset(uint32_t addr, uint32_t *bank, uint32_t *offset); -uint32_t spad_get_bank_row_bytes(uint32_t bank); - -/* End of pure C header */ - -#endif // SPAD_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 06fd0226..db1c5816 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -4,7 +4,7 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") #------------------------------------------------------------------------------- # Set baremetal compilation flags #------------------------------------------------------------------------------- -set(C_FLAGS -g -fno-common -O1 -static -march=rv64gc -mcmodel=medany +set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -specs=htif_nano.specs -I${CTEST_TOY_WORKLOAD_DIR}) #------------------------------------------------------------------------------- @@ -135,12 +135,6 @@ add_cross_platform_test_target(ctest_cim_test cim_test.c) add_cross_platform_test_target(ctest_transfer_test transfer_test.c) add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) -# Create library dependency target to ensure all libraries are built first -# add_custom_target(buckyball-libs-build -# DEPENDS bbmem-linux-build bbisa-linux-build bbmem-baremetal-build bbisa-baremetal-build -# COMMENT "Building all required libraries" -# ) - # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_mvin_mvout_acc_test diff --git a/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c b/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c index 92dcbf1d..1815c449 100644 --- a/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c +++ b/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix_c[DIM * DIM] __attribute__((aligned(64))); @@ -34,18 +36,18 @@ int abft_systolic_cpu_reference(elem_t *a, elem_t *b, elem_t *c, int size) { void hw_abft_systolic(const char *test_name, elem_t *a, elem_t *b, elem_t *c, int size) { // Matrix A in spad bank 0, Matrix B in spad bank 1, result in spad bank 2 - uint32_t op1_addr = spad_addr(0, 0); - uint32_t op2_addr = spad_addr(1, 0); - uint32_t wr_addr = spad_addr(2, 0); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + uint32_t wr_bank_id = 2; // Move input matrices into scratchpad - bb_mvin((uintptr_t)a, op1_addr, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); // Call ABFT systolic array instruction - bb_abft_systolic(op1_addr, op2_addr, wr_addr, size); + bb_abft_systolic(op1_bank_id, op2_bank_id, wr_bank_id, size); bb_fence(); // Result will be moved back in run_test for verification @@ -59,8 +61,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, elem_t *c, int size) { hw_abft_systolic(test_name, a, b, c, size); // Move result back from scratchpad for verification - uint32_t wr_addr = spad_addr(2, 0); - bb_mvout((uintptr_t)output_matrix_c, wr_addr, size, 1); + uint32_t wr_bank_id = 2; + bb_mvout((uintptr_t)output_matrix_c, wr_bank_id, size, 1); bb_fence(); // Verify results diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index ec3fdbe8..6a69b237 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + // Column count n for 16xn matrix multiplication #define MATMUL_COL 50 // 16-byte alignment of n @@ -18,23 +20,23 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); uint32_t col_stride = (size + DIM - 1) / DIM; for (int i = 0; i < col_stride; i++) { - bb_mvin((uintptr_t)a + i * DIM, op2_addr + size + i * DIM, DIM, col_stride); + bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } - bb_mvin((uintptr_t)b, op2_addr, size, 1); - bb_mvin((uintptr_t)c, wr_addr, DIM << 2, 1); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_mvin((uintptr_t)c, op2_bank_id, DIM << 2, 1); bb_fence(); - bb_transpose(op2_addr + size, op1_addr, size, 0); + bb_transpose(op2_bank_id, op1_bank_id, size, 0); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, op2_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c index 5740649f..6daaf06e 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -11,23 +13,15 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); - - printf("op1_addr: %d\n", op1_addr); - printf("op2_addr: %d\n", op2_addr); - printf("wr_addr: %d\n", wr_addr); - - bb_mvin((uintptr_t)a, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_bbfp_mul(op1_addr, op2_addr, wr_addr, size); + bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, size); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, op2_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c index 1447b373..566a0e30 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -11,23 +13,15 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); - - printf("op1_addr: %d\n", op1_addr); - printf("op2_addr: %d\n", op2_addr); - printf("wr_addr: %d\n", wr_addr); - - bb_mvin((uintptr_t)a, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_bbfp_mul(op1_addr, op2_addr, wr_addr, size); + bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, size); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, op2_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c index 064a4466..24b8b574 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -11,19 +13,15 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); - - bb_mvin((uintptr_t)a, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_bbfp_mul(op1_addr, op2_addr, wr_addr, size); + bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, size); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, op2_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c index c2a00a4c..5d629872 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c +++ b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c @@ -1,11 +1,13 @@ #include "buckyball.h" #include -#include +#include #include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + void init_matrix(elem_t *matrix, int rows, int cols, int seed) { srand(seed); for (int i = 0; i < rows * cols; i++) { @@ -45,20 +47,17 @@ int main() { // print_matrix("Input", input_matrix, DIM, DIM); // Move input to scratchpad - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)weight_matrix, op1_addr, DIM, 1); - bb_mvin((uintptr_t)input_matrix, op2_addr, DIM, 1); + bb_mvin((uintptr_t)weight_matrix, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)input_matrix, op2_bank_id, DIM, 1); bb_fence(); - bb_bbfp_mul(op1_addr, op2_addr, wr_addr, DIM); + bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, DIM); bb_fence(); // Move back from scratchpad to output - bb_mvout((uintptr_t)output_matrix, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)output_matrix, op2_bank_id, DIM << 2, 1); bb_fence(); if (compare_u32_matrices(output_matrix, expected_output_matrix, DIM, DIM)) { printf("Test passed!\n"); diff --git a/bb-tests/workloads/src/CTest/toy/bbfptest.c b/bb-tests/workloads/src/CTest/toy/bbfptest.c index 5f4e37ff..87a87e2b 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfptest.c +++ b/bb-tests/workloads/src/CTest/toy/bbfptest.c @@ -1,11 +1,13 @@ #include "buckyball.h" #include -#include +#include #include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + // Test matrices static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))); static elem_t weight_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -53,24 +55,21 @@ int main() { // print_matrix("Input", input_matrix, DIM, DIM); // Move input to scratchpad - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)input_matrix, op1_addr, DIM, 1); - bb_mvin((uintptr_t)weight_matrix, op2_addr, DIM, 1); + bb_mvin((uintptr_t)input_matrix, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)weight_matrix, op2_bank_id, DIM, 1); printf("Perform Matmul\n"); - bb_bbfp_mul(op1_addr, op2_addr, wr_addr, DIM); + bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, DIM); printf("change"); - bb_matmul_ws(wr_addr, op2_addr, wr_addr, 16); + bb_matmul_ws(acc_bank_id, op2_bank_id, acc_bank_id, 16); init_matrixv2(input_matrix, 16, 16, 42, 4); - bb_matmul_ws(wr_addr, op2_addr, wr_addr, 16); + bb_matmul_ws(acc_bank_id, op2_bank_id, acc_bank_id, 16); printf("Matmul Done\n"); - bb_mvout(((uintptr_t)output_matrix), wr_addr, DIM << 2, 1); + bb_mvout(((uintptr_t)output_matrix), op2_bank_id, DIM << 2, 1); print_result_matrix("Output", output_matrix, DIM, DIM); diff --git a/bb-tests/workloads/src/CTest/toy/buckyball.c b/bb-tests/workloads/src/CTest/toy/buckyball.c index d8a61d26..3376770e 100644 --- a/bb-tests/workloads/src/CTest/toy/buckyball.c +++ b/bb-tests/workloads/src/CTest/toy/buckyball.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + /* Read cycle counter (rdcycle) helper. Works on RV64 with a single rdcycle. On RV32 we read low/high and detect rollover to produce a 64-bit value. */ unsigned long long read_rdcycle(void) { diff --git a/bb-tests/workloads/src/CTest/toy/buckyball.h b/bb-tests/workloads/src/CTest/toy/buckyball.h index a3449960..129f7a4b 100644 --- a/bb-tests/workloads/src/CTest/toy/buckyball.h +++ b/bb-tests/workloads/src/CTest/toy/buckyball.h @@ -77,4 +77,5 @@ void cpu_relu(elem_t *a, elem_t *matrix, int rows, int cols); void cpu_transfer(elem_t *src, elem_t *dst, int rows, int cols); unsigned long long read_cycle(void); + #endif diff --git a/bb-tests/workloads/src/CTest/toy/cim_test.c b/bb-tests/workloads/src/CTest/toy/cim_test.c index 430bc2d0..98706480 100644 --- a/bb-tests/workloads/src/CTest/toy/cim_test.c +++ b/bb-tests/workloads/src/CTest/toy/cim_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + #define OP1_SIZE 64 #define OP2_SIZE 64 #define RESULT_SIZE 64 @@ -66,24 +68,22 @@ int cim_cpu_reference(elem_t *op1, elem_t *op2, elem_t *result, int rows, } void hw_cim(const char *test_name, elem_t *op1, elem_t *op2, elem_t *result, - int rows, int cols, int op_type) { + int rows, int cols, int op_type, int acc_bank_id) { // Operand 1 in spad bank 0, operand 2 in spad bank 1, result in spad bank 2 - uint32_t op1_addr = spad_addr(0, 0); - uint32_t op2_addr = spad_addr(1, 0); - uint32_t result_addr = spad_addr(2, 0); - + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; // Move operand 1 into scratchpad - bb_mvin((uintptr_t)op1, op1_addr, OP1_SIZE, 1); + bb_mvin((uintptr_t)op1, op1_bank_id, OP1_SIZE, 1); bb_fence(); // Move operand 2 into scratchpad - bb_mvin((uintptr_t)op2, op2_addr, OP2_SIZE, 1); + bb_mvin((uintptr_t)op2, op2_bank_id, OP2_SIZE, 1); bb_fence(); // Call CIM instruction // iter is the number of iterations (simplified: use rows*cols for now) uint32_t iter = rows * cols; - bb_cim(op1_addr, op2_addr, result_addr, iter, rows, cols, op_type); + bb_cim(op1_bank_id, op2_bank_id, acc_bank_id, iter, rows, cols, op_type); bb_fence(); // Result will be moved back in run_test for verification @@ -94,12 +94,14 @@ int run_test(const char *test_name, elem_t *op1, elem_t *op2, elem_t *result, // CPU reference computation cim_cpu_reference(op1, op2, expected_result, rows, cols, op_type); + // Allocate accumulator bank + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + // Hardware computation - hw_cim(test_name, op1, op2, result, rows, cols, op_type); + hw_cim(test_name, op1, op2, result, rows, cols, op_type, acc_bank_id); // Move result back from scratchpad for verification - uint32_t result_addr = spad_addr(2, 0); - bb_mvout((uintptr_t)result, result_addr, RESULT_SIZE, 1); + bb_mvout((uintptr_t)result, acc_bank_id, RESULT_SIZE, 1); bb_fence(); // Verify results diff --git a/bb-tests/workloads/src/CTest/toy/conv_test.c b/bb-tests/workloads/src/CTest/toy/conv_test.c index 785cce12..49beed30 100644 --- a/bb-tests/workloads/src/CTest/toy/conv_test.c +++ b/bb-tests/workloads/src/CTest/toy/conv_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + #define IFMAP_SIZE 64 #define WEIGHT_SIZE 16 #define OFMAP_SIZE 16 @@ -46,26 +48,25 @@ int conv_cpu_reference(elem_t *ifmap, elem_t *weight, elem_t *ofmap, int in_h, } void hw_conv(const char *test_name, elem_t *ifmap, elem_t *weight, - elem_t *ofmap, int in_h, int in_w, int kernel_h, int kernel_w) { + elem_t *ofmap, int in_h, int in_w, int kernel_h, int kernel_w, + uint32_t ofmap_bank_id) { // Input feature map in spad bank 0, weights in spad bank 1, output in spad // bank 2 - uint32_t ifmap_addr = spad_addr(0, 0); - uint32_t weight_addr = spad_addr(1, 0); - uint32_t ofmap_addr = spad_addr(2, 0); - + uint32_t ifmap_bank_id = 0; + uint32_t weight_bank_id = 1; // Move input feature map into scratchpad - bb_mvin((uintptr_t)ifmap, ifmap_addr, IFMAP_SIZE, 1); + bb_mvin((uintptr_t)ifmap, ifmap_bank_id, IFMAP_SIZE, 1); bb_fence(); // Move weights into scratchpad - bb_mvin((uintptr_t)weight, weight_addr, WEIGHT_SIZE, 1); + bb_mvin((uintptr_t)weight, weight_bank_id, WEIGHT_SIZE, 1); bb_fence(); // Call CONV instruction // iter is the number of iterations (simplified: use 1 for now) uint32_t iter = 1; - bb_conv(ifmap_addr, weight_addr, ofmap_addr, iter, in_h, in_w, kernel_h, - kernel_w); + bb_conv(ifmap_bank_id, weight_bank_id, ofmap_bank_id, iter, in_h, in_w, + kernel_h, kernel_w); bb_fence(); // Result will be moved back in run_test for verification @@ -76,12 +77,15 @@ int run_test(const char *test_name, elem_t *ifmap, elem_t *weight, // CPU reference computation conv_cpu_reference(ifmap, weight, ofmap, in_h, in_w, kernel_h, kernel_w); + // Output feature map in spad bank 2 + uint32_t ofmap_bank_id = 2; + // Hardware computation - hw_conv(test_name, ifmap, weight, ofmap, in_h, in_w, kernel_h, kernel_w); + hw_conv(test_name, ifmap, weight, ofmap, in_h, in_w, kernel_h, kernel_w, + ofmap_bank_id); // Move result back from scratchpad for verification - uint32_t ofmap_addr = spad_addr(2, 0); - bb_mvout((uintptr_t)output_feature_map, ofmap_addr, OFMAP_SIZE, 1); + bb_mvout((uintptr_t)output_feature_map, ofmap_bank_id, OFMAP_SIZE, 1); bb_fence(); // Verify results diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 18641ef9..59351bc1 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -1,19 +1,21 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - - bb_mvin((uintptr_t)a, op1_addr, size, 1); + uint32_t op2_bank_id = 1; + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); uint64_t krow = 4; uint64_t kcol = 1; @@ -21,8 +23,13 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { uint64_t incol = 16; uint64_t startrow = 1; uint64_t startcol = 1; - // bb_im2col(op1_addr, op2_addr, krow, kcol, inrow, incol, startrow, - // startcol); bb_fence(); + // bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, + // startcol); + bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, + startcol); + bb_fence(); + bb_mvout((uintptr_t)b, op2_bank_id, size, 1); + bb_fence(); } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index c829ce82..fefae780 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + // Test matrices static elem_t input_matrix_a[DIM * 1024] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * 1024] __attribute__((aligned(64))); @@ -16,13 +18,13 @@ int acc_mvin_mvout_pressure_test() { for (int i = 0; i < 4; i++) { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); - uint32_t wr_addr = spad_addr(4, i); - bb_mvin((uintptr_t)expected_matrix, wr_addr, DIM << 2, 1); + uint32_t acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM << 2, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); - wr_addr = spad_addr(4, i); - bb_mvout((uintptr_t)output_matrix, wr_addr, DIM << 2, 1); + acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM << 2, 1); bb_fence(); if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test ACC mvin/mvout pressure %d FAILED\n", i); diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index 84dc9d96..d9af25c7 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + // Test matrices static elem_t input_matrix_a[DIM * 1024] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * 1024] __attribute__((aligned(64))); @@ -15,10 +17,11 @@ static elem_t a_transposed[DIM * 1024] __attribute__((aligned(64))); int alternately_mvin_mvout_pressure_test() { for (int i = 0; i < 4; i++) { init_u8_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); - uint32_t wr_addr = spad_addr(0, i); - bb_mvin((uintptr_t)expected_matrix, wr_addr, DIM, 1); + uint32_t acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM, 1); clear_u32_matrix(output_matrix, DIM, DIM); - bb_mvout((uintptr_t)output_matrix, wr_addr, DIM, 1); + acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); bb_fence(); if (!compare_u8_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test mvin/mvout pressure %d FAILED\n", i); diff --git a/bb-tests/workloads/src/CTest/toy/nnlut_test.c b/bb-tests/workloads/src/CTest/toy/nnlut_test.c index 59359c3e..677bde12 100644 --- a/bb-tests/workloads/src/CTest/toy/nnlut_test.c +++ b/bb-tests/workloads/src/CTest/toy/nnlut_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); @@ -28,15 +30,14 @@ void init_lut() { void hw_nnlut(const char *test_name, elem_t *a, elem_t *b, int size) { // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_addr = spad_addr(0, 0); - uint32_t wr_addr = spad_addr(1, 0); - + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; // Move input into scratchpad bank0, starting at offset 0, iterate size times // row-wise - bb_mvin((uintptr_t)a, op1_addr, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); // Call NN-LUT instruction - bb_nnlut(op1_addr, wr_addr, size); + bb_nnlut(op1_bank_id, wr_bank_id, size); bb_fence(); // Result will be moved back in run_test for verification @@ -50,8 +51,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { hw_nnlut(test_name, a, b, size); // Move result back from scratchpad for verification - uint32_t wr_addr = spad_addr(1, 0); - bb_mvout((uintptr_t)output_matrix_b, wr_addr, size, 1); + uint32_t wr_bank_id = 1; + bb_mvout((uintptr_t)output_matrix_b, wr_bank_id, size, 1); bb_fence(); // Verify results diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index 607b3db1..eb9ab523 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -16,26 +18,26 @@ static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); // bb_relu(op1_addr, wr_addr, iter) wrapper in bbhw implementation // (func7=RELU_FUNC7). -void hw_relu(const char *test_name, elem_t *a, result_t*b, int size) { +void hw_relu(const char *test_name, elem_t *a, result_t *b, int size) { // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_addr = spad_addr(0, 0); - uint32_t wr_addr = spad_addr(1, 0); + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; // Move input into scratchpad bank0, starting at offset 0, iterate size times // row-wise - bb_mvin((uintptr_t)a, op1_addr, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); // Call ReLU instruction - bb_relu(op1_addr, wr_addr, size); + bb_relu(op1_bank_id, wr_bank_id, size); bb_fence(); - bb_mvout((uintptr_t)b, wr_addr, size, 1); + bb_mvout((uintptr_t)b, wr_bank_id, size, 1); } int run_test(const char *test_name, elem_t *a, int size) { clear_i8_matrix(output_matrix, size, size); cpu_relu(a, expected_matrix, size, size); hw_relu(test_name, a, output_matrix, size); - if(compare_i8_matrices(output_matrix, expected_matrix, size, size)) { + if (compare_i8_matrices(output_matrix, expected_matrix, size, size)) { printf("%s compare test PASSED\n", test_name); return 1; } else { diff --git a/bb-tests/workloads/src/CTest/toy/snn_test.c b/bb-tests/workloads/src/CTest/toy/snn_test.c index 9c3f8c1e..9c6d9ef4 100644 --- a/bb-tests/workloads/src/CTest/toy/snn_test.c +++ b/bb-tests/workloads/src/CTest/toy/snn_test.c @@ -1,10 +1,12 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * DIM] __attribute__((aligned(64))); @@ -35,15 +37,15 @@ int snn_cpu_reference(elem_t *input, elem_t *output, int size, void hw_snn(const char *test_name, elem_t *a, elem_t *b, int size, uint8_t threshold, uint8_t leak_factor) { // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_addr = spad_addr(0, 0); - uint32_t wr_addr = spad_addr(1, 0); + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; // Move input into scratchpad bank0, starting at offset 0, iterate size times // row-wise - bb_mvin((uintptr_t)a, op1_addr, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); // Call SNN instruction - bb_snn(op1_addr, wr_addr, size, threshold, leak_factor); + bb_snn(op1_bank_id, wr_bank_id, size, threshold, leak_factor); bb_fence(); // Result will be moved back in run_test for verification @@ -58,8 +60,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size, hw_snn(test_name, a, b, size, threshold, leak_factor); // Move result back from scratchpad for verification - uint32_t wr_addr = spad_addr(1, 0); - bb_mvout((uintptr_t)output_matrix_b, wr_addr, size, 1); + uint32_t wr_bank_id = 1; + bb_mvout((uintptr_t)output_matrix_b, wr_bank_id, size, 1); bb_fence(); // Verify results diff --git a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c index 074fe64c..a359f906 100644 --- a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + #define DIM_I 32 #define DIM_J 32 #define DIM_K 32 @@ -13,54 +15,15 @@ static elem_t input_b[DIM_J * DIM_K] __attribute__((aligned(16))); static result_t output_c[DIM_I * DIM_K] __attribute__((aligned(64))); static result_t expected_c[DIM_I * DIM_K] __attribute__((aligned(64))); static result_t c_zero[DIM * DIM] __attribute__((aligned(64))); -/** -void tiled_matmul(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c, result_t *zero_c) { - int row_iter = dim_i / DIM; - int col_iter = dim_k / DIM; - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); - uint32_t j_stride = dim_j / DIM; - uint32_t k_stride = dim_k / DIM; - unsigned long long start_compute, end_compute; - start_compute = read_cycle(); - for (int i = 0; i < row_iter; i++) { - for (int k = 0; k < k_stride; k++) { - if(k == 0){ - for(int j = 0; j < j_stride; j++) - bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, op2_addr + -dim_j + j * DIM, DIM, j_stride); - } - bb_mvin((uintptr_t)b + k * DIM, op2_addr, dim_k, k_stride); - bb_mvin((uintptr_t)zero_c, wr_addr, DIM << 2, 1); - bb_fence(); - if(k == 0){ - bb_transpose(op2_addr + dim_j, op1_addr, dim_j, 0); - bb_fence(); - } - bb_mul_warp16(op1_addr, op2_addr, wr_addr, dim_j, 0); - bb_fence(); - bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, wr_addr, -DIM << 2, k_stride); bb_fence(); - } - } - bb_fence(); - end_compute = read_cycle(); - printf("Cycles for matmul: %d\n", end_compute - start_compute); -} -*/ + void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, elem_t *a, elem_t *b, result_t *c) { // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -73,21 +36,22 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, for (int i = 0; i < i_stride; i++) { for (int j = 0; j < j_stride; j++) { bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, - op1_addr + dim_j * k_stride + dim_j * i + j * DIM, DIM, j_stride); + op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, + j_stride); } } // mvin matrix b for (int k = 0; k < k_stride; k++) { - bb_mvin((uintptr_t)b + k * DIM, op2_addr + dim_j * k, dim_j, k_stride); + bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); } bb_fence(); // perform matmul for (int i = 0; i < i_stride; i++) { for (int k = 0; k < k_stride; k++) { - bb_mul_warp16(op1_addr + dim_j * i, op2_addr + dim_j * k, - wr_addr + i * dim_k / 2 + k * DIM / 2, dim_j, 1); - bb_transpose((uintptr_t)op1_addr + dim_j * k_stride + dim_j * i, - op1_addr + dim_j * i, dim_j, 1); + bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, + acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 1); + bb_transpose((uintptr_t)op1_bank_id + dim_j * k_stride + dim_j * i, + op1_bank_id + dim_j * i, dim_j, 1); } } bb_fence(); @@ -95,7 +59,7 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, for (int i = 0; i < i_stride; i++) { for (int k = 0; k < k_stride; k++) { bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, - wr_addr + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); + acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); bb_fence(); } } @@ -107,11 +71,11 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, elem_t *a, elem_t *b, result_t *c) { // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -123,27 +87,28 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, for (int i = 0; i < i_stride; i++) { for (int j = 0; j < j_stride; j++) { bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, - op2_addr + dim_j * k_stride + dim_j * i + j * DIM, DIM, j_stride); + op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, + j_stride); } } // mvin matrix b for (int k = 0; k < k_stride; k++) { - bb_mvin((uintptr_t)b + k * DIM, op2_addr + dim_j * k, dim_j, k_stride); + bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); } bb_fence(); // transpose matrix a for (int i = 0; i < i_stride; i++) { - bb_transpose((uintptr_t)op2_addr + dim_j * k_stride + dim_j * i, - op1_addr + dim_j * i, dim_j, 0); + bb_transpose((uintptr_t)op2_bank_id + dim_j * k_stride + dim_j * i, + op1_bank_id + dim_j * i, dim_j, 0); } bb_fence(); // perform matmul for (int i = 0; i < i_stride; i++) { for (int k = 0; k < k_stride; k++) { - bb_mul_warp16(op1_addr + dim_j * i, op2_addr + dim_j * k, - wr_addr + i * dim_k / 2 + k * DIM / 2, dim_j, 0); + bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, + acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 0); bb_fence(); } } @@ -152,7 +117,7 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, for (int i = 0; i < i_stride; i++) { for (int k = 0; k < k_stride; k++) { bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, - wr_addr + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); + acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); bb_fence(); } } @@ -174,9 +139,9 @@ int run_test(const char *test_name) { clear_u32_matrix(output_c, DIM_I, DIM_K); // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); // TODO: ACC overwrite write can skip this step - bb_mvin((uintptr_t)output_c, wr_addr, DIM_I * DIM_K * 4 / DIM, 1); + bb_mvin((uintptr_t)output_c, acc_bank_id, DIM_I * DIM_K * 4 / DIM, 1); tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { printf("Test Normal Mode %s PASSED\n", test_name); diff --git a/bb-tests/workloads/src/CTest/toy/transfer_test.c b/bb-tests/workloads/src/CTest/toy/transfer_test.c index c2c6a69f..7f27bdb6 100644 --- a/bb-tests/workloads/src/CTest/toy/transfer_test.c +++ b/bb-tests/workloads/src/CTest/toy/transfer_test.c @@ -1,33 +1,34 @@ #include "buckyball.h" #include -#include +#include #include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * DIM] __attribute__((aligned(64))); static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); // static elem_t probe_matrix[DIM * DIM] __attribute__((aligned(64))); // Used to verify content in SPAD after MVIN - // bb_transfer(op1_addr, wr_addr, iter) wrapper in bbhw implementation // (func7=TRANSFER_FUNC7). void hw_transfer(const char *test_name, elem_t *a, elem_t *b, int size) { // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_addr = spad_addr(0, 0); - uint32_t wr_addr = spad_addr(1, 0); + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; // Move input into scratchpad bank0, starting at offset 0, iterate size times // row-wise - bb_mvin((uintptr_t)a, op1_addr, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); // Call Transfer instruction - bb_transfer(op1_addr, wr_addr, size); + bb_transfer(op1_bank_id, wr_bank_id, size); bb_fence(); - bb_mvout((uintptr_t)b, wr_addr, size, 1); + bb_mvout((uintptr_t)b, wr_bank_id, size, 1); } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index a96da9e8..0a49d6f3 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + // Column count n for 16xn matrix multiplication #define MATMUL_COL 50 // 16-byte alignment of n @@ -18,22 +20,23 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); uint32_t col_stride = (size + DIM - 1) / DIM; for (int i = 0; i < col_stride; i++) { - bb_mvin((uintptr_t)a + i * DIM, op2_addr + size + i * DIM, DIM, col_stride); + bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, + col_stride); } - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_transpose(op2_addr + size, op1_addr, size, 0); + bb_transpose(op2_bank_id + size, op1_bank_id, size, 0); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index a79a69c0..c6e4c305 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -1,21 +1,23 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; - bb_mvin((uintptr_t)a, op1_addr, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); - bb_transpose(op1_addr, op2_addr, size, 0); + bb_transpose(op1_bank_id, op2_bank_id, size, 0); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index 4634c17d..4a13661d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(16))); static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(16))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 32); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index eb644a7b..3d48e92c 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(16))); static elem_t input_matrix_b[64 * DIM] __attribute__((aligned(16))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -13,19 +15,15 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { static elem_t a_transposed[64 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 64); - // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); - // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); - // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); - - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 9c0eb366..4e16546f 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(16))); static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(16))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 32); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index a55ced5f..9174666e 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * 48] __attribute__((aligned(16))); static elem_t input_matrix_b[48 * DIM] __attribute__((aligned(16))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[48 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 48); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 68e291bd..be8938f2 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(16))); static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(16))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 32); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index 78071ec3..f13868e1 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -1,8 +1,10 @@ #include "buckyball.h" #include -#include +#include #include #include + +#define DIM (BANK_WIDTH / sizeof(elem_t)) #include static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); @@ -15,19 +17,19 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 14301583..0139d6ab 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,19 +16,19 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 4a2ab8e3..dd86eae6 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,19 +16,19 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index c8b3b0df..4aa03053 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 9a627dac..10352d1f 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 01f209e7..c6ac9b3d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,18 +16,18 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index 581afbcd..e2e949ee 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,19 +16,19 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index 99718c73..77400b1a 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -14,19 +16,19 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index 608f0067..5c3132a7 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -1,9 +1,11 @@ #include "buckyball.h" #include -#include +#include #include #include +#define DIM (BANK_WIDTH / sizeof(elem_t)) + // Define neural network parameters #define INPUT_SIZE DIM #define HIDDEN_SIZE DIM @@ -57,23 +59,23 @@ void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { // Move matrices to scratchpad // spad0: operand A, offset 0 - uint32_t op1_addr = spad_addr(0, 0); + uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 - uint32_t op2_addr = spad_addr(1, 0); + uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - uint32_t wr_addr = spad_addr(4, 0); + int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_addr, size, 1); - bb_mvin((uintptr_t)b, op2_addr, size, 1); - bb_mvin((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_mvin((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); // Execute matrix multiplication - bb_mul_warp16(op1_addr, op2_addr, wr_addr, size, 0); + bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); // Move result back - bb_mvout((uintptr_t)c, wr_addr, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } From ecfe3a037bbbff2e0f041b84aed46723398e6bef Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 22 Dec 2025 17:09:14 +0800 Subject: [PATCH 017/238] [arch] feat: update config with Serializable feat: update Module initialisation with instantiable wip: replace spad and acc with banks [pre-commit] feat: add scalafmt --- .pre-commit-config.yaml | 18 +- arch/.scalafmt.conf | 6 +- arch/build.sbt | 22 +- arch/build.sc | 134 +- arch/project/plugins.sbt | 2 +- arch/src/main/scala/Util/Pipeline.scala | 57 +- .../main/scala/examples/BuckyBallConfig.scala | 40 +- .../scala/examples/toy/CustomConfigs.scala | 274 ++-- arch/src/main/scala/examples/toy/README.md | 2 +- .../scala/examples/toy/ToyBuckyBall.scala | 158 +- .../examples/toy/balldomain/BallDomain.scala | 140 +- .../scala/examples/toy/balldomain/DISA.scala | 1 - .../toy/balldomain/DomainDecoder.scala | 209 +-- .../toy/balldomain/bbus/busRegister.scala | 43 +- .../toy/balldomain/configs/default.json | 9 + .../toy/balldomain/emptyball/EmptyBall.scala | 81 +- .../toy/balldomain/rs/rsRegister.scala | 31 +- .../framework/balldomain/bbus/bbus.scala | 117 +- .../bbus/cmdrouter/CmdReqRouter.scala | 18 +- .../bbus/cmdrouter/CmdRespRouter.scala | 14 +- .../balldomain/bbus/cmdrouter/CmdRouter.scala | 34 +- .../bbus/memrouter/SramIOAdapter.scala | 31 - .../balldomain/bbus/memrouter/memRouter.scala | 134 +- .../balldomain/bbus/pmc/BallCyclePMC.scala | 17 +- .../framework/balldomain/blink/baseball.scala | 2 +- .../framework/balldomain/blink/blink.scala | 99 +- .../balldomain/rs/reservationStation.scala | 97 +- .../scala/framework/balldomain/rs/rob.scala | 127 +- .../scala/framework/builtin/BaseConfigs.scala | 105 +- .../framework/builtin/configs/default.json | 21 + .../scala/framework/builtin/util/Util.scala | 113 +- .../scala/framework/core/rocket/Configs.scala | 275 ++++ .../framework/core/rocket/LazyRoCCBB.scala | 161 ++ .../framework/core/rocket/RocketCoreBB.scala | 1454 +++++++++++++++++ .../{ => core}/rocket/RocketSubsystem.scala | 41 +- .../{ => core}/rocket/RocketTileBB.scala | 238 +-- .../{ => core}/rocket/id/RVVRoCCDecode.scala | 33 +- .../scala/framework/frontend/Frontend.scala | 80 + .../framework/frontend/FrontendParam.scala | 8 + .../framework/frontend/decoder/GISA.scala | 2 +- .../frontend/decoder/GobalDecoder.scala | 52 +- .../frontend/globalrs/GlobalROB.scala | 111 +- .../globalrs/GlobalReservationStation.scala | 99 +- .../scala/framework/gpdomain/GPDomain.scala | 63 +- .../framework/gpdomain/configs/default.json | 3 + .../gpdomain/sequencer/decoder/DISA.scala | 7 +- .../gpdomain/sequencer/decoder/Decoder.scala | 31 +- .../sequencer/decoder/DomainDecoder.scala | 22 +- .../decoder/InstructionDatabase.scala | 104 +- .../decoder/InstructionDocumentation.scala | 13 +- .../sequencer/decoder/T1DecodePattern.scala | 8 +- .../sequencer/decoder/TableGenerator.scala | 28 +- .../decoder/attribute/adderUop.scala | 37 +- .../sequencer/decoder/attribute/divUop.scala | 19 +- .../decoder/attribute/floatUop.scala | 16 + .../decoder/attribute/fpExecutionType.scala | 17 +- .../sequencer/decoder/attribute/isAdder.scala | 2 + .../decoder/attribute/isAverage.scala | 3 + .../decoder/attribute/isCompress.scala | 2 + .../decoder/attribute/isCrossread.scala | 2 + .../decoder/attribute/isCrosswrite.scala | 3 + .../decoder/attribute/isDivider.scala | 2 + .../attribute/isDontneedexecuteinlane.scala | 2 + .../decoder/attribute/isExtend.scala | 2 + .../decoder/attribute/isFcompare.scala | 2 + .../sequencer/decoder/attribute/isFfo.scala | 2 + .../decoder/attribute/isFirstwiden.scala | 2 + .../sequencer/decoder/attribute/isFloat.scala | 2 + .../decoder/attribute/isFloatmul.scala | 2 + .../decoder/attribute/isFloattype.scala | 2 + .../sequencer/decoder/attribute/isFma.scala | 2 + .../decoder/attribute/isFother.scala | 2 + .../decoder/attribute/isGather.scala | 2 + .../decoder/attribute/isGather16.scala | 2 + .../sequencer/decoder/attribute/isId.scala | 2 + .../decoder/attribute/isIndextype.scala | 2 + .../sequencer/decoder/attribute/isIota.scala | 2 + .../sequencer/decoder/attribute/isItype.scala | 2 + .../sequencer/decoder/attribute/isLogic.scala | 2 + .../decoder/attribute/isMaskPipeType.scala | 2 + .../decoder/attribute/isMaskdestination.scala | 2 + .../decoder/attribute/isMasklogic.scala | 2 + .../decoder/attribute/isMasksource.scala | 2 + .../decoder/attribute/isMaskunit.scala | 2 + .../decoder/attribute/isMulticycle.scala | 2 + .../decoder/attribute/isMultiplier.scala | 2 + .../sequencer/decoder/attribute/isMv.scala | 2 + .../decoder/attribute/isNarrow.scala | 2 + .../sequencer/decoder/attribute/isNr.scala | 2 + .../decoder/attribute/isOrderreduce.scala | 2 + .../sequencer/decoder/attribute/isOther.scala | 2 + .../decoder/attribute/isPopcount.scala | 2 + .../decoder/attribute/isReadonly.scala | 2 + .../sequencer/decoder/attribute/isRed.scala | 2 + .../decoder/attribute/isReverse.scala | 2 + .../decoder/attribute/isSaturate.scala | 3 + .../decoder/attribute/isScheduler.scala | 2 + .../sequencer/decoder/attribute/isShift.scala | 2 + .../sequencer/decoder/attribute/isSlid.scala | 2 + .../decoder/attribute/isSpecial.scala | 2 + .../decoder/attribute/isSpecialslot.scala | 2 + .../decoder/attribute/isSreadvd.scala | 2 + .../decoder/attribute/isSwrite.scala | 2 + .../decoder/attribute/isTargetrd.scala | 2 + .../decoder/attribute/isUnorderwrite.scala | 2 + .../decoder/attribute/isUnsigned0.scala | 2 + .../decoder/attribute/isUnsigned1.scala | 2 + .../decoder/attribute/isVector.scala | 2 + .../sequencer/decoder/attribute/isVtype.scala | 2 + .../decoder/attribute/isVwmacc.scala | 2 + .../decoder/attribute/isWidenreduce.scala | 3 + .../decoder/attribute/isWriteCount.scala | 2 + .../sequencer/decoder/attribute/isZero.scala | 2 + .../sequencer/decoder/attribute/isZvbb.scala | 2 + .../sequencer/decoder/attribute/isZvma.scala | 2 + .../decoder/attribute/logicUop.scala | 28 +- .../decoder/attribute/maskPipeOpcode.scala | 23 +- .../sequencer/decoder/attribute/mulUop.scala | 22 +- .../decoder/attribute/otherUop.scala | 34 +- .../sequencer/decoder/attribute/package.scala | 9 +- .../decoder/attribute/shiftUop.scala | 19 +- .../sequencer/decoder/attribute/topUop.scala | 100 +- .../sequencer/decoder/attribute/uop.scala | 2 + .../sequencer/decoder/attribute/zeroUop.scala | 7 +- .../sequencer/decoder/attribute/zvbbUop.scala | 34 +- .../framework/memdomain/DomainDecoder.scala | 96 -- .../framework/memdomain/MemController.scala | 136 -- .../scala/framework/memdomain/MemDomain.scala | 243 +-- .../scala/framework/memdomain/MemLoader.scala | 135 -- .../scala/framework/memdomain/MemStorer.scala | 313 ---- .../framework/memdomain/Translator.scala | 31 - .../memdomain/backend/MemManager.scala | 116 ++ .../memdomain/backend/accpipe/AccPipe.scala | 159 ++ .../memdomain/backend/accpipe/BankPipe.scala | 62 + .../memdomain/backend/banks/SramBank.scala | 59 + .../memdomain/backend/banks/SramIO.scala | 38 + .../framework/memdomain/configs/default.json | 10 + .../framework/memdomain/dma/LocalAddr.scala | 147 -- .../memdomain/frontend/MemController.scala | 168 ++ .../cmd_channel/decoder}/DISA.scala | 8 +- .../cmd_channel/decoder/DomainDecoder.scala | 143 ++ .../{ => frontend/cmd_channel}/rs/README.md | 0 .../cmd_channel/rs/reservationStation.scala | 111 ++ .../cmd_channel}/rs/ringFifo.scala | 19 +- .../{ => frontend/cmd_channel}/rs/rob.scala | 38 +- .../frontend/outside_channel/MemLoader.scala | 118 ++ .../frontend/outside_channel/MemStorer.scala | 289 ++++ .../outside_channel}/dma/DMA.scala | 214 +-- .../outside_channel}/dma/README.md | 0 .../outside_channel}/tlb/BBTLB.scala | 38 +- .../outside_channel}/tlb/README.md | 0 .../outside_channel/tlb/TLBCluster.scala | 89 + .../outside_channel}/tlb/spec-BBTLB.md | 0 .../outside_channel}/tlb/spec-BBTLBCluster.md | 0 .../framework/memdomain/mem/AccMonitor.scala | 165 -- .../scala/framework/memdomain/mem/README.md | 121 -- .../framework/memdomain/mem/Scratchpad.scala | 118 -- .../framework/memdomain/mem/SramBank.scala | 83 - .../memdomain/midend/MemScheduler.scala | 102 ++ .../framework/memdomain/midend/bmt/bmt.scala | 1 + .../memdomain/rs/reservationStation.scala | 99 -- .../framework/memdomain/tlb/TLBCluster.scala | 81 - .../{ => utils}/pmc/MemCyclePMC.scala | 29 +- .../main/scala/framework/rocket/Configs.scala | 194 --- .../scala/framework/rocket/LazyRoCCBB.scala | 151 -- .../scala/framework/rocket/RocketCoreBB.scala | 1256 -------------- .../main/scala/framework/switcher/README.md | 69 - .../framework/switcher/ToPhysicalLine.scala | 141 -- .../framework/switcher/ToVirtuaLine.scala | 167 -- .../prototype/abft/ABFTSystolicArray.scala | 303 ++-- .../abft/ABFTSystolicArrayBall.scala | 54 +- .../prototype/abft/configs/ABFTConfig.scala | 61 + .../scala/prototype/abft/configs/default.json | 10 + arch/src/main/scala/prototype/conv/Conv.scala | 335 ++-- .../main/scala/prototype/conv/ConvBall.scala | 54 +- .../prototype/conv/configs/ConvConfig.scala | 61 + .../scala/prototype/conv/configs/default.json | 10 + .../scala/prototype/format/Arithmetic.scala | 6 +- .../scala/prototype/format/Dataformat.scala | 36 +- .../scala/prototype/ibuki/matmul/LIF.scala | 163 +- .../ibuki/matmul/LIFMatmulBall.scala | 45 +- .../scala/prototype/im2col/Im2colBall.scala | 52 +- .../im2col/configs/Im2colConfig.scala | 62 + .../prototype/im2col/configs/default.json | 10 + .../main/scala/prototype/im2col/im2col.scala | 193 ++- .../scala/prototype/matrix/MatrixBall.scala | 56 +- .../prototype/matrix/bbfpIns_decode.scala | 72 +- .../scala/prototype/matrix/bbfp_buffer.scala | 71 +- .../scala/prototype/matrix/bbfp_control.scala | 74 +- .../main/scala/prototype/matrix/bbfp_ex.scala | 366 +++-- .../scala/prototype/matrix/bbfp_load.scala | 67 +- .../main/scala/prototype/matrix/bbfp_pe.scala | 371 ++--- .../matrix/configs/MatrixConfig.scala | 62 + .../prototype/matrix/configs/default.json | 10 + .../scala/prototype/nagisa/matmul/Macro.scala | 361 ++-- .../nagisa/matmul/MacroMatmulBall.scala | 50 +- .../main/scala/prototype/nnlut/NNLut.scala | 173 +- .../scala/prototype/nnlut/NNLutBall.scala | 48 +- .../prototype/nnlut/configs/NNLutConfig.scala | 61 + .../prototype/nnlut/configs/default.json | 10 + arch/src/main/scala/prototype/relu/Relu.scala | 195 +-- .../main/scala/prototype/relu/ReluBall.scala | 60 +- .../prototype/relu/configs/ReluConfig.scala | 62 + .../scala/prototype/relu/configs/default.json | 10 + .../scala/prototype/transfer/Transfer.scala | 187 ++- .../prototype/transfer/TransferBall.scala | 49 +- .../transfer/configs/TransferConfig.scala | 62 + .../prototype/transfer/configs/default.json | 10 + .../scala/prototype/transpose/Transpose.scala | 190 ++- .../prototype/transpose/TransposeBall.scala | 52 +- .../transpose/configs/TransposeConfig.scala | 62 + .../prototype/transpose/configs/default.json | 10 + .../main/scala/prototype/vector/VecBall.scala | 55 +- .../scala/prototype/vector/VecCtrlUnit.scala | 118 +- .../scala/prototype/vector/VecEXUnit.scala | 94 +- .../scala/prototype/vector/VecLoadUnit.scala | 230 +-- .../scala/prototype/vector/VecStoreUnit.scala | 151 +- .../main/scala/prototype/vector/VecUnit.scala | 93 +- .../prototype/vector/bond/BondWrapper.scala | 10 +- .../scala/prototype/vector/bond/vvv.scala | 10 +- .../prototype/vector/configs/VecConfig.scala | 62 + .../prototype/vector/configs/default.json | 10 + .../scala/prototype/vector/op/cascade.scala | 28 +- .../main/scala/prototype/vector/op/mul.scala | 23 +- .../prototype/vector/thread/BaseThread.scala | 25 +- .../prototype/vector/thread/CasThread.scala | 8 +- .../prototype/vector/thread/MulThread.scala | 8 +- .../prototype/vector/warp/MeshWarp.scala | 61 +- .../scala/prototype/vector/warp/VecBall.scala | 50 +- .../scala/sims/firesim/TargetConfigs.scala | 54 +- .../scala/sims/palladium/TargetConfigs.scala | 22 +- .../main/scala/sims/verify/TargetConfig.scala | 92 +- .../scala/sims/verilator/TargetConfig.scala | 61 +- .../workloads/lib/bbhw/isa/32_mul_warp16.c | 2 +- scripts/init.sh | 12 +- scripts/install-scalafmt.sh | 25 + 236 files changed, 9041 insertions(+), 7554 deletions(-) create mode 100644 arch/src/main/scala/examples/toy/balldomain/configs/default.json delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala create mode 100644 arch/src/main/scala/framework/builtin/configs/default.json create mode 100644 arch/src/main/scala/framework/core/rocket/Configs.scala create mode 100644 arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala create mode 100644 arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala rename arch/src/main/scala/framework/{ => core}/rocket/RocketSubsystem.scala (58%) rename arch/src/main/scala/framework/{ => core}/rocket/RocketTileBB.scala (55%) rename arch/src/main/scala/framework/{ => core}/rocket/id/RVVRoCCDecode.scala (71%) create mode 100644 arch/src/main/scala/framework/frontend/Frontend.scala create mode 100644 arch/src/main/scala/framework/frontend/FrontendParam.scala create mode 100644 arch/src/main/scala/framework/gpdomain/configs/default.json delete mode 100644 arch/src/main/scala/framework/memdomain/DomainDecoder.scala delete mode 100644 arch/src/main/scala/framework/memdomain/MemController.scala delete mode 100644 arch/src/main/scala/framework/memdomain/MemLoader.scala delete mode 100644 arch/src/main/scala/framework/memdomain/MemStorer.scala delete mode 100644 arch/src/main/scala/framework/memdomain/Translator.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/MemManager.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala create mode 100644 arch/src/main/scala/framework/memdomain/configs/default.json delete mode 100644 arch/src/main/scala/framework/memdomain/dma/LocalAddr.scala create mode 100644 arch/src/main/scala/framework/memdomain/frontend/MemController.scala rename arch/src/main/scala/framework/memdomain/{ => frontend/cmd_channel/decoder}/DISA.scala (59%) create mode 100644 arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala rename arch/src/main/scala/framework/memdomain/{ => frontend/cmd_channel}/rs/README.md (100%) create mode 100644 arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala rename arch/src/main/scala/framework/memdomain/{ => frontend/cmd_channel}/rs/ringFifo.scala (82%) rename arch/src/main/scala/framework/memdomain/{ => frontend/cmd_channel}/rs/rob.scala (67%) create mode 100644 arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala create mode 100644 arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala rename arch/src/main/scala/framework/memdomain/{ => frontend/outside_channel}/dma/DMA.scala (56%) rename arch/src/main/scala/framework/memdomain/{ => frontend/outside_channel}/dma/README.md (100%) rename arch/src/main/scala/framework/memdomain/{ => frontend/outside_channel}/tlb/BBTLB.scala (61%) rename arch/src/main/scala/framework/memdomain/{ => frontend/outside_channel}/tlb/README.md (100%) create mode 100644 arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala rename arch/src/main/scala/framework/memdomain/{ => frontend/outside_channel}/tlb/spec-BBTLB.md (100%) rename arch/src/main/scala/framework/memdomain/{ => frontend/outside_channel}/tlb/spec-BBTLBCluster.md (100%) delete mode 100644 arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala delete mode 100644 arch/src/main/scala/framework/memdomain/mem/README.md delete mode 100644 arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala delete mode 100644 arch/src/main/scala/framework/memdomain/mem/SramBank.scala create mode 100644 arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala create mode 100644 arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala delete mode 100644 arch/src/main/scala/framework/memdomain/rs/reservationStation.scala delete mode 100644 arch/src/main/scala/framework/memdomain/tlb/TLBCluster.scala rename arch/src/main/scala/framework/memdomain/{ => utils}/pmc/MemCyclePMC.scala (53%) delete mode 100644 arch/src/main/scala/framework/rocket/Configs.scala delete mode 100644 arch/src/main/scala/framework/rocket/LazyRoCCBB.scala delete mode 100644 arch/src/main/scala/framework/rocket/RocketCoreBB.scala delete mode 100644 arch/src/main/scala/framework/switcher/README.md delete mode 100644 arch/src/main/scala/framework/switcher/ToPhysicalLine.scala delete mode 100644 arch/src/main/scala/framework/switcher/ToVirtuaLine.scala create mode 100644 arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala create mode 100644 arch/src/main/scala/prototype/abft/configs/default.json create mode 100644 arch/src/main/scala/prototype/conv/configs/ConvConfig.scala create mode 100644 arch/src/main/scala/prototype/conv/configs/default.json create mode 100644 arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala create mode 100644 arch/src/main/scala/prototype/im2col/configs/default.json create mode 100644 arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala create mode 100644 arch/src/main/scala/prototype/matrix/configs/default.json create mode 100644 arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala create mode 100644 arch/src/main/scala/prototype/nnlut/configs/default.json create mode 100644 arch/src/main/scala/prototype/relu/configs/ReluConfig.scala create mode 100644 arch/src/main/scala/prototype/relu/configs/default.json create mode 100644 arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala create mode 100644 arch/src/main/scala/prototype/transfer/configs/default.json create mode 100644 arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala create mode 100644 arch/src/main/scala/prototype/transpose/configs/default.json create mode 100644 arch/src/main/scala/prototype/vector/configs/VecConfig.scala create mode 100644 arch/src/main/scala/prototype/vector/configs/default.json create mode 100755 scripts/install-scalafmt.sh diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 601bf685..46a33fc6 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -45,12 +45,12 @@ repos: - id: check-yaml - id: check-added-large-files - # # Scala formatting with scalafmt - # - repo: local - # hooks: - # - id: scalafmt-check - # name: Check Scala formatting with scalafmt - # entry: bash -c 'cd arch && scalafmt --test' - # language: system - # files: ^arch/.*\.scala$ - # pass_filenames: false + # Scala formatting with scalafmt + - repo: local + hooks: + - id: scalafmt + name: Format Scala code with scalafmt + entry: bash -c 'cd arch && source ../env.sh && scalafmt --config .scalafmt.conf src/main/scala' + language: system + files: ^arch/src/main/scala/.*\.scala$ + pass_filenames: false diff --git a/arch/.scalafmt.conf b/arch/.scalafmt.conf index 46935cc9..68e263b3 100644 --- a/arch/.scalafmt.conf +++ b/arch/.scalafmt.conf @@ -1,8 +1,8 @@ version = 2.6.4 -# Exclude thirdparty directory from formatting -project.excludeFilters = [ - "thirdparty" +# Only format src/main/scala directory +project.includeFilters = [ + "src/main/scala/.*\\.scala$" ] # Basic formatting diff --git a/arch/build.sbt b/arch/build.sbt index 93f38dbb..f657b8c8 100644 --- a/arch/build.sbt +++ b/arch/build.sbt @@ -1,7 +1,7 @@ // See README.md for license details. -val chisel6Version = "6.5.0" -val chiselTestVersion = "6.0.0" +val chisel6Version = "6.5.0" +val chiselTestVersion = "6.0.0" val scalaVersionFromChisel = "2.13.12" // Fix for scalafix undefined setting @@ -19,11 +19,11 @@ lazy val chisel6Settings = Seq( lazy val chiselSettings = chisel6Settings ++ Seq( libraryDependencies ++= Seq( "org.apache.commons" % "commons-lang3" % "3.12.0", - "org.apache.commons" % "commons-text" % "1.9" + "org.apache.commons" % "commons-text" % "1.9" ) ) -lazy val scalaTestSettings = Seq( +lazy val scalaTestSettings = Seq( libraryDependencies ++= Seq( "org.scalatest" %% "scalatest" % "3.2.+" % "test" ) @@ -44,9 +44,9 @@ lazy val palladium = ProjectRef(file("../tools/palladium"), "palladium") lazy val buckyball = (project in file(".")) .dependsOn(chipyard, firechip, palladium) .settings( - name := "buckyball", + name := "buckyball", organization := "com.buckyball", - version := "1.0.0", + version := "1.0.0", scalaVersion := scalaVersionFromChisel, scalacOptions ++= Seq( "-deprecation", @@ -58,10 +58,10 @@ lazy val buckyball = (project in file(".")) Resolver.sonatypeRepo("releases") ), chisel6Settings ++ - scalaTestSettings ++ - Seq( - libraryDependencies ++= Seq( - "edu.berkeley.cs" %% "rocketchip" % "1.6" + scalaTestSettings ++ + Seq( + libraryDependencies ++= Seq( + "edu.berkeley.cs" %% "rocketchip" % "1.6" + ) ) - ) ) diff --git a/arch/build.sc b/arch/build.sc index bd0857fe..2b772c37 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -9,7 +9,8 @@ import mill.bsp._ object buckyball extends SbtModule { m => override def millSourcePath = os.pwd - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" + override def scalacOptions = Seq( "-language:reflectiveCalls", "-deprecation", @@ -44,18 +45,21 @@ object buckyball extends SbtModule { m => object test extends ScalaModule with TestModule.ScalaTest { override def scalaVersion = T("2.13.12") - override def moduleDeps = Seq(m) + override def moduleDeps = Seq(m) + override def ivyDeps = Agg( ivy"org.scalatest::scalatest::3.2.19" // ivy"org.scalatest::scalatest:3.2.16" ) + } + } // Define cde module - must be compiled first object cde extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "cde" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Override sources to match freshProject behavior override def sources = T.sources { @@ -69,12 +73,13 @@ object cde extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define hardfloat module - depends on cde object hardfloat extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "hardfloat" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add cde dependency override def moduleDeps = Seq( @@ -93,12 +98,14 @@ object hardfloat extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define midas_target_utils module object midas_target_utils extends SbtModule { - override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "sims" / "firesim" / "sim" / "midas" / "targetutils" - override def scalaVersion = "2.13.12" + override def millSourcePath = + os.pwd / "thirdparty" / "chipyard" / "sims" / "firesim" / "sim" / "midas" / "targetutils" + override def scalaVersion = "2.13.12" override def ivyDeps = Agg( ivy"org.chipsalliance::chisel:6.5.0" @@ -107,12 +114,13 @@ object midas_target_utils extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define diplomacy module - depends on cde object diplomacy extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "diplomacy" / "diplomacy" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add cde dependency first override def moduleDeps = Seq( @@ -132,12 +140,13 @@ object diplomacy extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define rocket-chip module with proper dependencies object rocketchip extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "rocket-chip" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add required dependencies for rocket-chip override def moduleDeps = Seq( @@ -157,12 +166,13 @@ object rocketchip extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define chipyard module object chipyard extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Override sources to include tools/stage, generators/chipyard, and harness directories (as per build.sbt) override def sources = T.sources { @@ -211,12 +221,13 @@ object chipyard extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define testchipip module object testchipip extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "testchipip" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip and rocket-chip-blocks as dependencies override def moduleDeps = Seq( @@ -231,12 +242,13 @@ object testchipip extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define rocket-chip-blocks module (contains sifive package) object rocket_chip_blocks extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "rocket-chip-blocks" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -250,12 +262,13 @@ object rocket_chip_blocks extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define icenet module object icenet extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "icenet" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -269,12 +282,13 @@ object icenet extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define nvdla module object nvdla extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "nvdla" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -288,12 +302,13 @@ object nvdla extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define fft_generator module object fft_generator extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "fft-generator" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip and rocket-dsp-utils as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -308,12 +323,13 @@ object fft_generator extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define constellation module object constellation extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "constellation" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -327,12 +343,13 @@ object constellation extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define boom module object boom extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "boom" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -346,12 +363,13 @@ object boom extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define tracegen module object tracegen extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "tracegen" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add testchipip, rocket-chip, rocketchip_inclusive_cache, and boom as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -368,12 +386,13 @@ object tracegen extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define shuttle module object shuttle extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "shuttle" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -387,12 +406,13 @@ object shuttle extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define rocketchip_inclusive_cache module object rocketchip_inclusive_cache extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "rocket-chip-inclusive-cache" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Override sources to match build.sbt behavior - point to design/craft directory override def sources = T.sources { @@ -411,12 +431,13 @@ object rocketchip_inclusive_cache extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define saturn module object saturn extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "saturn" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip and shuttle as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -431,12 +452,13 @@ object saturn extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define gemmini module object gemmini extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "gemmini" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -450,12 +472,13 @@ object gemmini extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define sodor module object sodor extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "riscv-sodor" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -469,12 +492,13 @@ object sodor extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define vexiiriscv module object vexiiriscv extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "vexiiriscv" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -488,12 +512,13 @@ object vexiiriscv extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define ibex module object ibex extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "ibex" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -507,12 +532,13 @@ object ibex extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define cva6 module object cva6 extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "cva6" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -526,12 +552,13 @@ object cva6 extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define ara module object ara extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "ara" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip and shuttle as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -546,12 +573,13 @@ object ara extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define rerocc module object rerocc extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "rerocc" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip, constellation, boom, and shuttle as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -568,12 +596,13 @@ object rerocc extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define rocket-dsp-utils module object rocket_dsp_utils extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "rocket-dsp-utils" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip, cde, and dsptools as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -589,12 +618,13 @@ object rocket_dsp_utils extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define dsptools module object dsptools extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "dsptools" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip and fixedpoint as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -612,12 +642,13 @@ object dsptools extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define fixedpoint module object fixedpoint extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "fixedpoint" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -631,12 +662,13 @@ object fixedpoint extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define compressacc module object compressacc extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "compress-acc" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -650,12 +682,13 @@ object compressacc extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define mempress module object mempress extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "mempress" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -669,12 +702,13 @@ object mempress extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define barf module object barf extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "bar-fetchers" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -688,12 +722,13 @@ object barf extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define caliptra_aes module object caliptra_aes extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "caliptra-aes-acc" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip, rocc_acc_utils, and testchipip as dependencies (as per build.sbt) override def moduleDeps = Seq( @@ -709,12 +744,13 @@ object caliptra_aes extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define rocc_acc_utils module object rocc_acc_utils extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "rocc-acc-utils" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocket-chip as a dependency override def moduleDeps = Seq( @@ -728,16 +764,17 @@ object rocc_acc_utils extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define firrtl2 module object firrtl2 extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "firrtl2" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Override sources to include generated ANTLR sources and BuildInfo override def sources = T.sources { - val baseSources = super.sources() + val baseSources = super.sources() // Include pre-generated sources from target directory val generatedDir = millSourcePath / "src" / "target" / "scala-2.13" / "src_managed" / "main" if (os.exists(generatedDir)) { @@ -768,12 +805,13 @@ object firrtl2 extends SbtModule { "-language:existentials", "-language:implicitConversions" ) + } // Define firrtl2_bridge module object firrtl2_bridge extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "firrtl2" / "bridge" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add firrtl2 as a dependency override def moduleDeps = Seq( @@ -787,12 +825,12 @@ object firrtl2_bridge extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) -} +} object firesim_lib extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "sims" / "firesim" / "sim" / "firesim-lib" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add midas_target_utils as a dependency override def moduleDeps = Seq( @@ -806,6 +844,7 @@ object firesim_lib extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Interfaces for target-specific bridges shared with FireSim. @@ -813,7 +852,7 @@ object firesim_lib extends SbtModule { // This is copied to FireSim's GoldenGate compiler. object firechip_bridgeinterfaces extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "firechip" / "bridgeinterfaces" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" override def ivyDeps = Agg( ivy"org.chipsalliance::chisel:6.5.0" @@ -822,13 +861,14 @@ object firechip_bridgeinterfaces extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Target-side bridge definitions, CC files, etc used for FireSim. // This only compiled with Chipyard. object firechip_bridgestubs extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "firechip" / "bridgestubs" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add chipyard, firesim_lib, and firechip_bridgeinterfaces as dependencies override def moduleDeps = Seq( @@ -844,12 +884,13 @@ object firechip_bridgestubs extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // FireSim top-level project that includes the FireSim harness, CC files, etc needed for FireSim. object firechip extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "generators" / "firechip" / "chip" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add chipyard, firesim_lib, firechip_bridgestubs, and firechip_bridgeinterfaces as dependencies override def moduleDeps = Seq( @@ -866,12 +907,13 @@ object firechip extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Define fpga_shells module object fpga_shells extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "fpga" / "fpga-shells" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add rocketchip and rocket_chip_blocks as dependencies override def moduleDeps = Seq( @@ -886,12 +928,13 @@ object fpga_shells extends SbtModule { override def scalacPluginIvyDeps = Agg( ivy"org.chipsalliance:::chisel-plugin:6.5.0" ) + } // Palladium FPGA subproject (external reference) object palladium extends SbtModule { override def millSourcePath = os.pwd / os.up / "tools" / "palladium" - override def scalaVersion = "2.13.12" + override def scalaVersion = "2.13.12" // Add chipyard and fpga_shells as dependencies override def moduleDeps = Seq( @@ -912,4 +955,5 @@ object palladium extends SbtModule { "-unchecked", "-Ymacro-annotations" ) + } diff --git a/arch/project/plugins.sbt b/arch/project/plugins.sbt index 87f092c7..1dd5989c 100644 --- a/arch/project/plugins.sbt +++ b/arch/project/plugins.sbt @@ -1,2 +1,2 @@ -addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1") +addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4") diff --git a/arch/src/main/scala/Util/Pipeline.scala b/arch/src/main/scala/Util/Pipeline.scala index 714b00ed..55b0aded 100644 --- a/arch/src/main/scala/Util/Pipeline.scala +++ b/arch/src/main/scala/Util/Pipeline.scala @@ -3,31 +3,33 @@ package Util import chisel3._ import chisel3.util._ -class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { +class Pipeline[T <: Data](gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency + 1)((x: T) => x)) extends Module { + val io = IO(new Bundle { - val in = Flipped(Decoupled(gen)) - val out = Decoupled(gen) + val in = Flipped(Decoupled(gen)) + val out = Decoupled(gen) val busy = Output(Bool()) }) - require(comb.size == latency+1, "length of combinational is incorrect") + require(comb.size == latency + 1, "length of combinational is incorrect") if (latency == 0) { - io.in.ready := io.out.ready + io.in.ready := io.out.ready io.out.valid := io.in.valid - io.out.bits := comb.head(io.in.bits) - io.busy := io.in.valid + io.out.bits := comb.head(io.in.bits) + io.busy := io.in.valid } else { - val stages = Reg(Vec(latency, gen)) - val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) + val stages = Reg(Vec(latency, gen)) + val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) - io.busy := io.in.valid || valids.reduce(_||_) + io.busy := io.in.valid || valids.reduce(_ || _) // Stall signals - io.in.ready := !stalling.head + io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready - (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => - s1 := v1 && s2 + (stalling.init, stalling.tail, valids.init).zipped.foreach { + case (s1, s2, v1) => + s1 := v1 && s2 } // Valid signals @@ -36,19 +38,21 @@ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(la when(io.out.ready) { valids.last := false.B } - (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => - when(!s2) { - v1 := false.B - } + (valids.init, stalling.tail).zipped.foreach { + case (v1, s2) => + when(!s2) { + v1 := false.B + } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } - (valids.tail, valids.init).zipped.foreach { case (v2, v1) => - when(v1) { - v2 := true.B - } + (valids.tail, valids.init).zipped.foreach { + case (v2, v1) => + when(v1) { + v2 := true.B + } } // Stages @@ -56,15 +60,17 @@ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(la stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) - ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => - when(!s2) { - st2 := c1(st1) - } + ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { + case ((st2, st1), (s2, c1)) => + when(!s2) { + st2 := c1(st1) + } } } } object Pipeline { + def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in @@ -76,4 +82,5 @@ object Pipeline { p.io.in <> in p.io.out } + } diff --git a/arch/src/main/scala/examples/BuckyBallConfig.scala b/arch/src/main/scala/examples/BuckyBallConfig.scala index 3b87a774..8e3ce957 100644 --- a/arch/src/main/scala/examples/BuckyBallConfig.scala +++ b/arch/src/main/scala/examples/BuckyBallConfig.scala @@ -3,20 +3,54 @@ package examples import chisel3._ import framework.builtin.BaseConfig import examples.toy.BuckyballToyConfig +import scala.io.Source +import upickle.default._ object BuckyballConfigs { - val defaultConfig = BaseConfig - val toyConfig = BuckyballToyConfig.defaultConfig + val defaultConfig = BaseConfig() + val toyConfig = BuckyballToyConfig.defaultConfig // Actually used configuration val customConfig = toyConfig type CustomBuckyballConfig = BaseConfig -} + /** + * Load global config from JSON file + * Usage: BuckyballConfigs.fromJson("path/to/config.json") + */ + def fromJson(path: String): BaseConfig = { + val jsonStr = Source.fromFile(path).mkString + read[BaseConfig](jsonStr) + } + + /** + * Load global config from JSON string + */ + def fromJsonString(json: String): BaseConfig = + read[BaseConfig](json) + + /** + * Save global config to JSON file + */ + def toJsonFile(config: BaseConfig, path: String): Unit = { + val jsonStr = write(config, indent = 2) + java.nio.file.Files.write( + java.nio.file.Paths.get(path), + jsonStr.getBytes + ) + } + +} // Get currently selected configuration object CustomBuckyballConfig { import BuckyballConfigs._ def apply(): CustomBuckyballConfig = BuckyballConfigs.customConfig + + /** + * Create config from JSON file + * Usage: CustomBuckyballConfig.fromJson("configs/my_config.json") + */ + def fromJson(path: String): CustomBuckyballConfig = BuckyballConfigs.fromJson(path) } diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index abd2a5b9..840cfd4f 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -1,6 +1,6 @@ package examples.toy -import org.chipsalliance.cde.config.{Config, Parameters, Field} +import org.chipsalliance.cde.config.{Config, Field, Parameters} import chisel3._ import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.subsystem.SystemBusKey @@ -11,34 +11,34 @@ import examples.BuckyballConfigs.CustomBuckyballConfig import examples.CustomBuckyballConfig object BuckyballToyConfig { + val defaultConfig = new BaseConfig( - inputType = UInt(8.W), - accType = UInt(32.W), - sp_banks = 4, - acc_banks = 8 + bankNum = 32 ) + } class BuckyballCustomConfig( - buckyballConfig: CustomBuckyballConfig = CustomBuckyballConfig() -) extends Config((site, here, up) => { - case BuildRoCC => up(BuildRoCC) ++ Seq( - (p: Parameters) => { - implicit val q = p - val buckyball = LazyModule(new ToyBuckyball(buckyballConfig)) - buckyball - } - ) -}) + buckyballConfig: CustomBuckyballConfig = CustomBuckyballConfig()) + extends Config((site, here, up) => { + case BuildRoCC => up(BuildRoCC) ++ Seq { + (p: Parameters) => + implicit val q = p + val buckyball = LazyModule(new ToyBuckyball(buckyballConfig)(q)) + buckyball + } + }) -class BuckyballToyConfig extends Config( - new BuckyballCustomConfig ++ - new framework.rocket.WithNBuckyballCores(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) +class BuckyballToyConfig + extends Config( + new BuckyballCustomConfig ++ + new framework.core.rocket.WithNBuckyballCores(1) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) -import freechips.rocketchip.subsystem.{InCluster, InSubsystem, SBUS, MBUS} -import freechips.rocketchip.devices.tilelink.{BootROMParams, BootROMLocated} +import freechips.rocketchip.subsystem.{InCluster, InSubsystem, MBUS, SBUS} +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import constellation.channel._ import constellation.routing._ import constellation.router._ @@ -50,119 +50,131 @@ import scala.collection.immutable.ListMap // Note: For AddressSet(base, size-1), we need (base & (size-1)) == 0 // This means base must be aligned to size (size must be power of 2) // For 256 cores (8 clusters × 32 cores), 512KB should be sufficient -class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) extends Config((site, here, up) => { - case BootROMLocated(InSubsystem) => { - up(BootROMLocated(InSubsystem)).map(_.copy(address = address, size = size)) - } -}) +class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) + extends Config((site, here, up) => { + case BootROMLocated(InSubsystem) => { + up(BootROMLocated(InSubsystem)).map(_.copy(address = address, size = size)) + } + }) // 4-core test configuration to understand NoC mapping -class BuckyballToy4Config extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( - constellation.protocol.DiplomaticNetworkNodeMapping( - inNodeMapping = ListMap( - "serial_tl" -> 0, - "Core 0 " -> 1, // Space after number for precise matching - "Core 1 " -> 2, - "Core 2 " -> 3, - "Core 3 " -> 4, - "debug" -> 5, - // buckyball-stream ports appear together, map them to same node - "buckyball-stream-reader[0],buckyball-stream-writer[0]" -> 6, - "buckyball-stream-reader[1],buckyball-stream-writer[1]" -> 7, - "buckyball-stream-reader[2],buckyball-stream-writer[2]" -> 8, - "buckyball-stream-reader[3],buckyball-stream-writer[3]" -> 9 - ), - outNodeMapping = ListMap( - "pbus" -> 10, - "system[0]" -> 11, - "system[1]" -> 12, - "system[2]" -> 13, - "system[3]" -> 14 - ) - ), - NoCParams( - topology = TerminalRouter(Mesh2D(4, 4)), // 4x4 mesh = 16 nodes (enough for 10 inputs + 5 outputs) - channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }), - routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1)) - )) ++ - new BuckyballCustomConfig ++ - new framework.rocket.WithNBuckyballCores(4) ++ - new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) +class BuckyballToy4Config + extends Config( + new WithLargeBootROM(0x80000, 0x80000) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "serial_tl" -> 0, + "Core 0 " -> 1, // Space after number for precise matching + "Core 1 " -> 2, + "Core 2 " -> 3, + "Core 3 " -> 4, + "debug" -> 5, + // buckyball-stream ports appear together, map them to same node + "buckyball-stream-reader[0],buckyball-stream-writer[0]" -> 6, + "buckyball-stream-reader[1],buckyball-stream-writer[1]" -> 7, + "buckyball-stream-reader[2],buckyball-stream-writer[2]" -> 8, + "buckyball-stream-reader[3],buckyball-stream-writer[3]" -> 9 + ), + outNodeMapping = ListMap( + "pbus" -> 10, + "system[0]" -> 11, + "system[1]" -> 12, + "system[2]" -> 13, + "system[3]" -> 14 + ) + ), + NoCParams( + topology = TerminalRouter(Mesh2D(4, 4)), // 4x4 mesh = 16 nodes (enough for 10 inputs + 5 outputs) + channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), + routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) + ) + )) ++ + new BuckyballCustomConfig ++ + new framework.core.rocket.WithNBuckyballCores(4) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) // 64-core test configuration with 2 L2 banks -class BuckyballToy64Config extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( - constellation.protocol.DiplomaticNetworkNodeMapping( - inNodeMapping = ListMap( - "serial_tl" -> 0, - "debug" -> 1 - ) ++ (0 until 64).map(i => s"Core $i " -> (2 + i)).toMap // Note the space after number! - ++ (0 until 64).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (66 + i)).toMap, - outNodeMapping = ListMap( - "pbus" -> 130 - ) ++ (0 until 2).map(i => s"system[$i]" -> (131 + i)).toMap - ), - NoCParams( - // 12x12 mesh = 144 nodes (enough for 130 inputs + 3 outputs) - topology = TerminalRouter(Mesh2D(12, 12)), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }), - routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1)) - )) ++ - new BuckyballCustomConfig ++ - new framework.rocket.WithNBuckyballCores(64) ++ - new freechips.rocketchip.subsystem.WithNBanks(2) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) +class BuckyballToy64Config + extends Config( + new WithLargeBootROM(0x80000, 0x80000) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "serial_tl" -> 0, + "debug" -> 1 + ) ++ (0 until 64).map(i => s"Core $i " -> (2 + i)).toMap // Note the space after number! + ++ (0 until 64).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (66 + i)).toMap, + outNodeMapping = ListMap( + "pbus" -> 130 + ) ++ (0 until 2).map(i => s"system[$i]" -> (131 + i)).toMap + ), + NoCParams( + // 12x12 mesh = 144 nodes (enough for 130 inputs + 3 outputs) + topology = TerminalRouter(Mesh2D(12, 12)), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), + routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) + ) + )) ++ + new BuckyballCustomConfig ++ + new framework.core.rocket.WithNBuckyballCores(64) ++ + new freechips.rocketchip.subsystem.WithNBanks(2) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) // 256-core test configuration with 32 L2 banks -class BuckyballToy256Config extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( - constellation.protocol.DiplomaticNetworkNodeMapping( - inNodeMapping = ListMap( - "serial_tl" -> 0, - "debug" -> 1 - ) ++ (0 until 256).map(i => s"Core $i " -> (2 + i)).toMap // Note the space after number! - ++ (0 until 256).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (258 + i)).toMap, - outNodeMapping = ListMap( - "pbus" -> 514 - ) ++ (0 until 32).map(i => s"system[$i]" -> (515 + i)).toMap - ), - NoCParams( - // 24x24 mesh = 576 nodes (enough for 514 inputs + 33 outputs) - topology = TerminalRouter(Mesh2D(24, 24)), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }), - routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1)) - )) ++ - new BuckyballCustomConfig ++ - new framework.rocket.WithNBuckyballCores(256) ++ - new freechips.rocketchip.subsystem.WithNBanks(32) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) +class BuckyballToy256Config + extends Config( + new WithLargeBootROM(0x80000, 0x80000) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "serial_tl" -> 0, + "debug" -> 1 + ) ++ (0 until 256).map(i => s"Core $i " -> (2 + i)).toMap // Note the space after number! + ++ (0 until 256).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (258 + i)).toMap, + outNodeMapping = ListMap( + "pbus" -> 514 + ) ++ (0 until 32).map(i => s"system[$i]" -> (515 + i)).toMap + ), + NoCParams( + // 24x24 mesh = 576 nodes (enough for 514 inputs + 33 outputs) + topology = TerminalRouter(Mesh2D(24, 24)), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), + routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) + ) + )) ++ + new BuckyballCustomConfig ++ + new framework.core.rocket.WithNBuckyballCores(256) ++ + new freechips.rocketchip.subsystem.WithNBanks(32) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) -class BuckyballToy256CBConfig extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ // 512KB BootROM at 0x80000 (for 1024 cores) - new BuckyballCustomConfig ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(7)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(6)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(5)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(4)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(3)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(2)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(1)) ++ - new framework.rocket.WithNBuckyballCores(32, location=InCluster(0)) ++ - new freechips.rocketchip.subsystem.WithCluster(7) ++ - new freechips.rocketchip.subsystem.WithCluster(6) ++ - new freechips.rocketchip.subsystem.WithCluster(5) ++ - new freechips.rocketchip.subsystem.WithCluster(4) ++ - new freechips.rocketchip.subsystem.WithCluster(3) ++ - new freechips.rocketchip.subsystem.WithCluster(2) ++ - new freechips.rocketchip.subsystem.WithCluster(1) ++ - new freechips.rocketchip.subsystem.WithCluster(0) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) +class BuckyballToy256CBConfig + extends Config( + new WithLargeBootROM(0x80000, 0x80000) ++ // 512KB BootROM at 0x80000 (for 1024 cores) + new BuckyballCustomConfig ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(7)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(6)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(5)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(4)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(3)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(2)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(1)) ++ + new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(0)) ++ + new freechips.rocketchip.subsystem.WithCluster(7) ++ + new freechips.rocketchip.subsystem.WithCluster(6) ++ + new freechips.rocketchip.subsystem.WithCluster(5) ++ + new freechips.rocketchip.subsystem.WithCluster(4) ++ + new freechips.rocketchip.subsystem.WithCluster(3) ++ + new freechips.rocketchip.subsystem.WithCluster(2) ++ + new freechips.rocketchip.subsystem.WithCluster(1) ++ + new freechips.rocketchip.subsystem.WithCluster(0) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) diff --git a/arch/src/main/scala/examples/toy/README.md b/arch/src/main/scala/examples/toy/README.md index ecf88766..2ded842b 100644 --- a/arch/src/main/scala/examples/toy/README.md +++ b/arch/src/main/scala/examples/toy/README.md @@ -100,7 +100,7 @@ class BuckyballCustomConfig( **System configuration**: ```scala class BuckyballToyConfig extends Config( - new framework.rocket.WithNBuckyballCores(1) ++ + new framework.core.rocket.WithNBuckyballCores(1) ++ new BuckyballCustomConfig(CustomBuckyballConfig()) ++ new chipyard.config.WithSystemBusWidth(128) ++ new WithCustomBootROM ++ diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 1f49b28e..1d06cf67 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -8,35 +8,35 @@ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.tile.{TileKey, HasCoreParameters, LazyRoCC, LazyRoCCModuleImp} +import freechips.rocketchip.tile.{HasCoreParameters, LazyRoCC, LazyRoCCModuleImp, OpcodeSet, TileKey} import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile.{LazyRoCC, LazyRoCCModuleImp} -import framework.frontend.decoder.GlobalDecoder -import framework.memdomain.dma.{BBStreamReader, BBStreamWriter} -import framework.memdomain.MemDomain -import examples.toy.balldomain.BallDomain +import chisel3.experimental.hierarchy.{Instance, Instantiate} +import framework.frontend.{Frontend, FrontendParam} +import framework.memdomain.{MemDomain, MemDomainParam} +import framework.gpdomain.{GpDomain, GpDomainParam} +import framework.memdomain.frontend.outside_channel.dma.{BBStreamReader, BBStreamWriter} +import examples.toy.balldomain.{BallDomain, BallDomainParam} import examples.BuckyballConfigs.CustomBuckyballConfig - class ToyBuckyball(val b: CustomBuckyballConfig)(implicit p: Parameters) - extends LazyRoCC (opcodes = b.opcodes, nPTWPorts = 1) { + extends LazyRoCC(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { - val xLen = p(TileKey).core.xLen // the width of core's register file + val xLen = p(TileKey).core.xLen // the width of core's register file - val id_node = TLIdentityNode() + val id_node = TLIdentityNode() val xbar_node = TLXbar() - val spad_w = b.inputType.getWidth * b.veclane - val reader = LazyModule(new BBStreamReader(b.max_in_flight_mem_reqs, b.dma_buswidth, b.dma_maxbytes, spad_w)) - val writer = LazyModule(new BBStreamWriter(b.max_in_flight_mem_reqs, b.dma_buswidth, b.dma_maxbytes, spad_w)) + val reader = LazyModule(new BBStreamReader(b.max_in_flight_mem_reqs, b.dma_buswidth, b.dma_maxbytes, b.bankWidth)(p)) + val writer = LazyModule(new BBStreamWriter(b.max_in_flight_mem_reqs, b.dma_buswidth, b.dma_maxbytes, b.bankWidth)(p)) // Note: BallDomain is now a regular Module, no longer a LazyModule // Will be instantiated in module - xbar_node := TLBuffer() := reader.node - xbar_node := TLBuffer() := writer.node - id_node := TLWidthWidget(b.dma_buswidth/8) := TLBuffer() := xbar_node + xbar_node := TLBuffer() := reader.node + xbar_node := TLBuffer() := writer.node + id_node := TLWidthWidget(b.dma_buswidth / 8) := TLBuffer() := xbar_node override lazy val module = new ToyBuckyballModule(this) @@ -44,13 +44,12 @@ class ToyBuckyball(val b: CustomBuckyballConfig)(implicit p: Parameters) // atlNode connects into a tile-local arbiter along with the backside of the L1 instruction cache. // tlNode connects directly to the L1-L2 crossbar. // The corresponding Tilelink ports in the module implementation's IO bundle are atl and tl, respectively. - override val tlNode = id_node + override val tlNode = id_node override val atlNode = TLIdentityNode() - val node = tlNode + val node = tlNode } -class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) - with HasCoreParameters { +class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) with HasCoreParameters { import outer.b._ val tagWidth = 32 @@ -58,46 +57,84 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) // ----------------------------------------------------------------------------- // Frontend: TLB moved inside MemDomain // ----------------------------------------------------------------------------- - implicit val edge: TLEdgeOut = outer.id_node.edges.out.head + val edge: TLEdgeOut = outer.id_node.edges.out.head // ----------------------------------------------------------------------------- // Frontend: Global Decoder + Global Reservation Station // ----------------------------------------------------------------------------- - implicit val b: CustomBuckyballConfig = outer.b - - val gDecoder = Module(new GlobalDecoder) - gDecoder.io.id_i.valid := io.cmd.valid - gDecoder.io.id_i.bits.cmd := io.cmd.bits - io.cmd.ready := gDecoder.io.id_i.ready - - // Global reservation station - val globalRs = Module(new framework.frontend.globalrs.GlobalReservationStation) - globalRs.io.global_decode_cmd_i <> gDecoder.io.id_o + val b: CustomBuckyballConfig = outer.b + // Frontend parameter + val frontendParam = FrontendParam( + rob_entries = b.rob_entries, + rs_out_of_order_response = b.rs_out_of_order_response + ) - -// ----------------------------------------------------------------------------- -// Backend: Ball Domain -// ----------------------------------------------------------------------------- - // BallDomain is now a regular Module, instantiate directly - val ballDomain = Module(new BallDomain()(b, p)) - - // Global RS -> BallDomain - ballDomain.io.global_issue_i <> globalRs.io.ball_issue_o - globalRs.io.ball_complete_i <> ballDomain.io.global_complete_o + val frontend: Instance[Frontend] = Instantiate(new Frontend(frontendParam)) + frontend.io.cmd.valid := io.cmd.valid + frontend.io.cmd.bits.cmd := io.cmd.bits + io.cmd.ready := frontend.io.cmd.ready // ----------------------------------------------------------------------------- // Backend: Mem Domain - complete domain containing DMA+TLB+SRAM // ----------------------------------------------------------------------------- - val memDomain = Module(new MemDomain) - - // Global RS -> MemDomain - memDomain.io.global_issue_i <> globalRs.io.mem_issue_o - globalRs.io.mem_complete_i <> memDomain.io.global_complete_o + // Load MemDomain config: try JSON file first, fallback to global config + val memDomainParam = + try { + MemDomainParam.fromJson("arch/src/main/scala/framework/memdomain/configs/default.json") + } catch { + case _: Exception => MemDomainParam.fromGlobal(b) + } // ----------------------------------------------------------------------------- -// Backend: MemDomain Connections +// Backend: Ball Domain // ----------------------------------------------------------------------------- + // Load BallDomain config: try JSON file first, fallback to global config + val ballDomainParam = + try { + BallDomainParam.fromJson("arch/src/main/scala/examples/toy/balldomain/configs/default.json") + } catch { + case _: Exception => BallDomainParam.fromGlobal(b) + } + + // Require parameter matching between BallDomain and MemDomain + require( + ballDomainParam.bbusChannel == memDomainParam.bankChannel, + s"BallDomain bbusChannel (${ballDomainParam.bbusChannel}) must equal MemDomain bankChannel (${memDomainParam.bankChannel})" + ) + require( + ballDomainParam.numBanks == memDomainParam.bankNum, + s"BallDomain numBanks (${ballDomainParam.numBanks}) must equal MemDomain bankNum (${memDomainParam.bankNum})" + ) + require( + ballDomainParam.bankEntries == memDomainParam.bankEntries, + s"BallDomain bankEntries (${ballDomainParam.bankEntries}) must equal MemDomain bankEntries (${memDomainParam.bankEntries})" + ) + require( + ballDomainParam.bankWidth == memDomainParam.bankWidth, + s"BallDomain bankWidth (${ballDomainParam.bankWidth}) must equal MemDomain bankWidth (${memDomainParam.bankWidth})" + ) + require( + ballDomainParam.bankMaskLen == memDomainParam.bankMaskLen, + s"BallDomain bankMaskLen (${ballDomainParam.bankMaskLen}) must equal MemDomain bankMaskLen (${memDomainParam.bankMaskLen})" + ) + require( + ballDomainParam.rob_entries == memDomainParam.rob_entries, + s"BallDomain rob_entries (${ballDomainParam.rob_entries}) must equal MemDomain rob_entries (${memDomainParam.rob_entries})" + ) + + val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(ballDomainParam)(outer.p)) + + // Frontend -> BallDomain + ballDomain.global_issue_i <> frontend.io.ball_issue_o + frontend.io.ball_complete_i <> ballDomain.global_complete_o + + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(memDomainParam)(edge)) + + // Frontend -> MemDomain + memDomain.io.global_issue_i <> frontend.io.mem_issue_o + frontend.io.mem_complete_i <> memDomain.io.global_complete_o + // MemDomain -> DMA memDomain.io.dma.read.req <> outer.reader.module.io.req outer.reader.module.io.resp <> memDomain.io.dma.read.resp @@ -113,7 +150,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) // TLB exception handling - shared TLB has only 1 exception interface // Set flush input signals - memDomain.io.tlbExp(0).flush_skip := false.B + memDomain.io.tlbExp(0).flush_skip := false.B memDomain.io.tlbExp(0).flush_retry := false.B // Flush signals to DMA components (obtained from MemDomain's TLB exceptions) @@ -123,30 +160,39 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) // ----------------------------------------------------------------------------- // Backend: Gen Domain - General purpose domain (for T1 vector processor) // ----------------------------------------------------------------------------- - val gpDomain = Module(new framework.gpdomain.GpDomain()(b, p)) + // Load GpDomain config: try JSON file first, fallback to global config + val gpDomainParam = + try { + GpDomainParam.fromJson("arch/src/main/scala/framework/gpdomain/configs/default.json") + } catch { + case _: Exception => GpDomainParam.fromGlobal(b) + } + + val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(gpDomainParam)(outer.p)) - // Global RS -> GpDomain - gpDomain.io.global_issue_i <> globalRs.io.gp_issue_o - globalRs.io.gp_complete_i <> gpDomain.io.global_complete_o + // Frontend -> GpDomain + gpDomain.io.global_issue_i <> frontend.io.gp_issue_o + frontend.io.gp_complete_i <> gpDomain.io.global_complete_o // ----------------------------------------------------------------------------- // Backend: Domain Bridge: BallDomain -> MemDomain // ----------------------------------------------------------------------------- - ballDomain.io.sramRead <> memDomain.io.ballDomain.sramRead - ballDomain.io.sramWrite <> memDomain.io.ballDomain.sramWrite + ballDomain.bankRead <> memDomain.io.ballDomain.bankRead + ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite // --------------------------------------------------------------------------- // RoCC response and status signals // --------------------------------------------------------------------------- - io.resp <> globalRs.io.rs_rocc_o.resp - io.busy := globalRs.io.rs_rocc_o.busy + + io.resp <> frontend.io.resp + io.busy := frontend.io.busy io.interrupt := memDomain.io.tlbExp(0).interrupt // --------------------------------------------------------------------------- // Busy counter to prevent long simulation stalls // --------------------------------------------------------------------------- val busy_counter = RegInit(0.U(32.W)) - busy_counter := Mux(globalRs.io.rs_rocc_o.busy, busy_counter + 1.U, 0.U) + busy_counter := Mux(frontend.io.busy, busy_counter + 1.U, 0.U) assert(busy_counter < 10000.U, "ToyBuckyball: busy for too long!") } diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 034ddc2b..069518c1 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -2,78 +2,142 @@ package examples.toy.balldomain import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import framework.memdomain.mem.{SramReadIO, SramWriteIO} import examples.BuckyballConfigs.CustomBuckyballConfig import examples.toy.balldomain.rs.BallRSModule import examples.toy.balldomain.bbus.BBusModule -import framework.frontend.globalrs.GlobalRsIssue -import framework.frontend.globalrs.GlobalRsComplete -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} - -// Ball Domain input/output interface -class BallDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - private val numBanks = b.sp_banks + b.acc_banks - // Issue interface from global RS (single channel) - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) - - // Report completion to global RS (single channel) - val global_complete_o = Decoupled(new GlobalRsComplete) - - // Execution interface connected to Scratchpad - val sramRead = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) - val sramWrite = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - // val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - // val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) +import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.balldomain.blink.{BankRead, BankWrite} + +object BallDomainParam { + implicit def rw: upickle.default.ReadWriter[BallDomainParam] = upickle.default.macroRW + + /** + * Load from JSON file + */ + def fromJson(path: String): BallDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[BallDomainParam](jsonStr) + } + + /** + * Generate from global config + */ + def fromGlobal(global: framework.builtin.BaseConfig): BallDomainParam = { + BallDomainParam( + rob_entries = global.rob_entries, + numBanks = global.bankNum, + bbusChannel = global.bankChannel, + bankEntries = global.bankEntries, + bankWidth = global.bankWidth, + bankMaskLen = global.bankMaskLen, + emptyBallid = global.emptyBallid + ) + } + } -// Ball Domain top level - uses new simplified BBus architecture -class BallDomain(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +case class BallDomainParam( + rob_entries: Int, + numBanks: Int, + bbusChannel: Int, + bankEntries: Int, + bankWidth: Int, + bankMaskLen: Int, + emptyBallid: Int = 5) + extends SerializableModuleParameter { + override def toString: String = + s"""BallDomainParam + | ROB entries: $rob_entries + | Num banks: $numBanks + | BBus channel: $bbusChannel + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | Empty Ball ID: $emptyBallid + |""".stripMargin +} + +/** + * Ball Domain top level - uses new simplified BBus architecture + */ +@instantiable +class BallDomain(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + + @public + val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries)))) + + @public + val global_complete_o = IO(Decoupled(new GlobalRsComplete(parameter.rob_entries))) + + @public + val bankRead = IO(Vec( + parameter.numBanks, + Flipped(new BankRead( + parameter.bankEntries, + parameter.bankWidth, + parameter.rob_entries, + parameter.numBanks + )) + )) - val io = IO(new BallDomainIO) + @public + val bankWrite = IO(Vec( + parameter.numBanks, + Flipped(new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.numBanks + )) + )) // Create new BBus module - val bbus = Module(new BBusModule) + val bbus: Instance[BBusModule] = Instantiate(new BBusModule(parameter)) //--------------------------------------------------------------------------- // Global RS -> Decoder (receive global issue and construct PostGDCmd) //--------------------------------------------------------------------------- - val ballDecoder = Module(new BallDomainDecoder) + val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(parameter)(p)) // Convert global RS issue to Decoder input format - ballDecoder.io.raw_cmd_i.valid := io.global_issue_i.valid - ballDecoder.io.raw_cmd_i.bits := io.global_issue_i.bits.cmd - io.global_issue_i.ready := ballDecoder.io.raw_cmd_i.ready + ballDecoder.raw_cmd_i.valid := global_issue_i.valid + ballDecoder.raw_cmd_i.bits := global_issue_i.bits.cmd + global_issue_i.ready := ballDecoder.raw_cmd_i.ready //--------------------------------------------------------------------------- // Decoder -> Local BallRS (multi-channel issue to each Ball device) //--------------------------------------------------------------------------- - val ballRs = Module(new BallRSModule) + val ballRs: Instance[BallRSModule] = Instantiate(new BallRSModule(parameter)) // Connect decoded instruction and global rob_id - ballRs.io.ball_decode_cmd_i.valid := ballDecoder.io.ball_decode_cmd_o.valid - ballRs.io.ball_decode_cmd_i.bits.cmd := ballDecoder.io.ball_decode_cmd_o.bits - ballRs.io.ball_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id - ballDecoder.io.ball_decode_cmd_o.ready := ballRs.io.ball_decode_cmd_i.ready + ballRs.ball_decode_cmd_i.valid := ballDecoder.ball_decode_cmd_o.valid + ballRs.ball_decode_cmd_i.bits.cmd := ballDecoder.ball_decode_cmd_o.bits + ballRs.ball_decode_cmd_i.bits.rob_id := global_issue_i.bits.rob_id + ballDecoder.ball_decode_cmd_o.ready := ballRs.ball_decode_cmd_i.ready //--------------------------------------------------------------------------- // Local BallRS -> BBus (multi-channel) //--------------------------------------------------------------------------- - bbus.io.cmdReq <> ballRs.io.issue_o.balls - ballRs.io.commit_i.balls <> bbus.io.cmdResp + bbus.cmdReq <> ballRs.issue_o.balls + ballRs.commit_i.balls <> bbus.cmdResp //--------------------------------------------------------------------------- // BBus -> Mem Domain //--------------------------------------------------------------------------- - bbus.io.sramRead <> io.sramRead - bbus.io.sramWrite <> io.sramWrite + bbus.bankRead <> bankRead + bbus.bankWrite <> bankWrite //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) //--------------------------------------------------------------------------- - io.global_complete_o <> ballRs.io.complete_o + global_complete_o <> ballRs.complete_o override lazy val desiredName = "BallDomain" } diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 6d7cefce..433fc46a 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -5,7 +5,6 @@ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ - class BuckyballRawCmd(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index ec544bea..d1d5f739 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -2,20 +2,18 @@ package examples.toy.balldomain import chisel3._ import chisel3.util._ -import framework.frontend.decoder.{PostGDCmd, DomainId} -import examples.BuckyballConfigs.CustomBuckyballConfig -import examples.toy.balldomain.DISA._ -import framework.memdomain.dma.LocalAddr -import freechips.rocketchip.tile._ +import chisel3.experimental.hierarchy.{instantiable, public} import org.chipsalliance.cde.config.Parameters +import framework.frontend.decoder.{DomainId, PostGDCmd} +import examples.toy.balldomain.DISA._ // Detailed decode output for Ball domain -class BallDecodeCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { +class BallDecodeCmd(parameter: BallDomainParam) extends Bundle { // Ball ID val bid = UInt(5.W) // Iteration count - val iter = UInt(10.W) + val iter = UInt(10.W) // Ball-specific fields val op1_en = Bool() @@ -26,23 +24,10 @@ class BallDecodeCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bu // Instruction-specific subfield val special = UInt(40.W) - // Ball operand addresses - // 3 bits, supports 8 banks - val op1_bank = UInt(log2Up(b.sp_banks + b.acc_banks).W) - // 12 bits, uses SPAD row count - val op1_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - // 3 bits, supports 8 banks - val op2_bank = UInt(log2Up(b.sp_banks + b.acc_banks).W) - // 12 bits, uses SPAD row count - val op2_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - - // Write address and bank information - // 3 bits, supports 8 banks - val wr_bank = UInt(log2Up(b.sp_banks + b.acc_banks).W) - // 12 bits, uses SPAD row count - val wr_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - // Whether this is an acc bank operation - val is_acc = Bool() + // Ball operand bank IDs (now directly from rs1/rs2) + val op1_bank = UInt(log2Up(parameter.numBanks).W) + val op2_bank = UInt(log2Up(parameter.numBanks).W) + val wr_bank = UInt(log2Up(parameter.numBanks).W) val rs1 = UInt(64.W) val rs2 = UInt(64.W) @@ -51,101 +36,133 @@ class BallDecodeCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bu // Ball decode fields object BallDecodeFields extends Enumeration { type Field = Value - val OP1_EN, OP2_EN, WR_SPAD, OP1_FROM_SPAD, OP2_FROM_SPAD, - OP1_SPADDR, OP2_SPADDR, WR_SPADDR, ITER, BID, SPECIAL = Value + val OP1_EN, OP2_EN, WR_SPAD, OP1_FROM_SPAD, OP2_FROM_SPAD, OP1_SPADDR, OP2_SPADDR, WR_SPADDR, ITER, BID, SPECIAL = + Value } - - // Default constants for EX decoder object BallDefaultConstants { - val Y = true.B - val N = false.B - val DADDR = 0.U(14.W) - val DITER = 0.U(10.W) - val DBID = 0.U(5.W) + val Y = true.B + val N = false.B + val DADDR = 0.U(14.W) + val DITER = 0.U(10.W) + val DBID = 0.U(5.W) val DSPECIAL = 0.U(40.W) } -class BallDomainDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class BallDomainDecoder(val parameter: BallDomainParam)(implicit p: Parameters) extends Module { import BallDefaultConstants._ - val io = IO(new Bundle { - val raw_cmd_i = Flipped(Decoupled(new PostGDCmd)) - val ball_decode_cmd_o = Decoupled(new BallDecodeCmd) - }) + @public + val raw_cmd_i = IO(Flipped(Decoupled(new PostGDCmd))) + + @public + val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(parameter))) - val spAddrLen = b.spAddrLen + val spAddrLen = 14 // b.spAddrLen replaced with constant // Only process ball instructions - io.raw_cmd_i.ready := io.ball_decode_cmd_o.ready + raw_cmd_i.ready := ball_decode_cmd_o.ready - val func7 = io.raw_cmd_i.bits.raw_cmd.inst.funct - val rs1 = io.raw_cmd_i.bits.raw_cmd.rs1 - val rs2 = io.raw_cmd_i.bits.raw_cmd.rs2 + val func7 = raw_cmd_i.bits.raw_cmd.inst.funct + val rs1 = raw_cmd_i.bits.raw_cmd.rs1 + val rs2 = raw_cmd_i.bits.raw_cmd.rs2 - // Ball instruction decoding + // Ball instruction decoding - now directly use rs1/rs2 as bank IDs import BallDecodeFields._ - val ball_default_decode = List(N,N,N,N,N,DADDR,DADDR,DADDR,DITER,DBID,DSPECIAL) - val ball_decode_list = ListLookup(func7, ball_default_decode, Array( - MATMUL_WARP16_BITPAT -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),0.U,rs2(63,spAddrLen + 10)), - BB_BBFP_MUL -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),1.U,rs2(63,spAddrLen + 10)), - MATMUL_WS -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),1.U,rs2(63,spAddrLen + 10)), - IM2COL -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),2.U,rs2(63,spAddrLen + 10)), - TRANSPOSE -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),3.U,rs2(63,spAddrLen + 10)), - RELU -> List(Y,N,Y,Y,N, rs1(spAddrLen-1,0), DADDR, rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),4.U,rs2(63,spAddrLen + 10)), - BBUS_CONFIG -> List(Y,N,Y,Y,N, rs1(spAddrLen-1,0), DADDR, rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),5.U,rs2(63,spAddrLen + 10)), - NNLUT -> List(Y,N,Y,Y,N, rs1(spAddrLen-1,0), DADDR, rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),31.U,rs2(63,spAddrLen + 10)), - SNN -> List(Y,N,Y,Y,N, rs1(spAddrLen-1,0), DADDR, rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),7.U,rs2(63,spAddrLen + 10)), - ABFT_SYSTOLIC -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),8.U,rs2(63,spAddrLen + 10)), - CONV -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),9.U,rs2(63,spAddrLen + 10)), - CIM -> List(Y,Y,Y,Y,Y, rs1(spAddrLen-1,0), rs1(2*spAddrLen - 1,spAddrLen), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),10.U,rs2(63,spAddrLen + 10)), - TRANSFER -> List(Y,N,Y,Y,N, rs1(spAddrLen-1,0), DADDR, rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen),6.U,rs2(63,spAddrLen + 10)) - )) - + val ball_default_decode = List(N, N, N, N, N, 0.U, 0.U, 0.U, DITER, DBID, DSPECIAL) + + val ball_decode_list = ListLookup( + func7, + ball_default_decode, + Array( + MATMUL_WARP16_BITPAT -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), + BB_BBFP_MUL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 1.U, rs2(63, 16)), + MATMUL_WS -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 1.U, rs2(63, 16)), + IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), + TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), + RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 4.U, rs2(63, 16)), + BBUS_CONFIG -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), + NNLUT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 31.U, rs2(63, 16)), + SNN -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 7.U, rs2(63, 16)), + ABFT_SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 8.U, rs2(63, 16)), + CONV -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 9.U, rs2(63, 16)), + CIM -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 10.U, rs2(63, 16)), + TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) + ) + ) // ----------------------------------------------------------------------------- // Output assignment // ----------------------------------------------------------------------------- - io.ball_decode_cmd_o.valid := io.raw_cmd_i.valid && (io.raw_cmd_i.bits.domain_id === DomainId.BALL) - - io.ball_decode_cmd_o.bits.bid := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) - - io.ball_decode_cmd_o.bits.iter := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.ITER.id).asUInt, 0.U(10.W)) - io.ball_decode_cmd_o.bits.special := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.SPECIAL.id).asUInt, DSPECIAL) - io.ball_decode_cmd_o.bits.op1_en := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.OP1_EN.id).asBool, false.B) - io.ball_decode_cmd_o.bits.op2_en := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.OP2_EN.id).asBool, false.B) - io.ball_decode_cmd_o.bits.wr_spad_en := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.WR_SPAD.id).asBool, false.B) - io.ball_decode_cmd_o.bits.op1_from_spad := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.OP1_FROM_SPAD.id).asBool, false.B) - io.ball_decode_cmd_o.bits.op2_from_spad := Mux(io.ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.OP2_FROM_SPAD.id).asBool, false.B) - - // Address parsing - val op1_spaddr = ball_decode_list(BallDecodeFields.OP1_SPADDR.id).asUInt - val op2_spaddr = ball_decode_list(BallDecodeFields.OP2_SPADDR.id).asUInt - val wr_spaddr = ball_decode_list(BallDecodeFields.WR_SPADDR.id).asUInt - - val op1_laddr = LocalAddr.cast_to_sp_addr(b.local_addr_t, op1_spaddr) - val op2_laddr = LocalAddr.cast_to_sp_addr(b.local_addr_t, op2_spaddr) - val wr_laddr = LocalAddr.cast_to_sp_addr(b.local_addr_t, wr_spaddr) - - // Use mem_bank() and mem_row() to support ACC banks (bank 4+) - io.ball_decode_cmd_o.bits.op1_bank := Mux(io.ball_decode_cmd_o.valid, op1_laddr.mem_bank(), 0.U(log2Up(b.sp_banks + b.acc_banks).W)) - io.ball_decode_cmd_o.bits.op1_bank_addr := Mux(io.ball_decode_cmd_o.valid, op1_laddr.mem_row(), 0.U(log2Up(b.spad_bank_entries).W)) - io.ball_decode_cmd_o.bits.op2_bank := Mux(io.ball_decode_cmd_o.valid, op2_laddr.mem_bank(), 0.U(log2Up(b.sp_banks + b.acc_banks).W)) - io.ball_decode_cmd_o.bits.op2_bank_addr := Mux(io.ball_decode_cmd_o.valid, op2_laddr.mem_row(), 0.U(log2Up(b.spad_bank_entries).W)) - - io.ball_decode_cmd_o.bits.wr_bank := Mux(io.ball_decode_cmd_o.valid, wr_laddr.mem_bank(), 0.U(log2Up(b.sp_banks + b.acc_banks).W)) - io.ball_decode_cmd_o.bits.wr_bank_addr := Mux(io.ball_decode_cmd_o.valid, wr_laddr.mem_row(), 0.U(log2Up(b.spad_bank_entries).W)) - io.ball_decode_cmd_o.bits.is_acc := Mux(io.ball_decode_cmd_o.valid, (io.ball_decode_cmd_o.bits.wr_bank >= b.sp_banks.U), false.B) + ball_decode_cmd_o.valid := raw_cmd_i.valid && (raw_cmd_i.bits.domain_id === DomainId.BALL) + + ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) + + ball_decode_cmd_o.bits.iter := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.ITER.id).asUInt, + 0.U(10.W) + ) + ball_decode_cmd_o.bits.special := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.SPECIAL.id).asUInt, + DSPECIAL + ) + ball_decode_cmd_o.bits.op1_en := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.OP1_EN.id).asBool, + false.B + ) + ball_decode_cmd_o.bits.op2_en := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.OP2_EN.id).asBool, + false.B + ) + ball_decode_cmd_o.bits.wr_spad_en := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.WR_SPAD.id).asBool, + false.B + ) + ball_decode_cmd_o.bits.op1_from_spad := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.OP1_FROM_SPAD.id).asBool, + false.B + ) + ball_decode_cmd_o.bits.op2_from_spad := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.OP2_FROM_SPAD.id).asBool, + false.B + ) + + // Directly assign bank IDs from decoded values + ball_decode_cmd_o.bits.op1_bank := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.OP1_SPADDR.id).asUInt, + 0.U + ) + ball_decode_cmd_o.bits.op2_bank := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.OP2_SPADDR.id).asUInt, + 0.U + ) + ball_decode_cmd_o.bits.wr_bank := Mux( + ball_decode_cmd_o.valid, + ball_decode_list(BallDecodeFields.WR_SPADDR.id).asUInt, + 0.U + ) // Assertion: OpA and OpB in execution instructions must access different banks - assert(!(io.ball_decode_cmd_o.valid && io.ball_decode_cmd_o.bits.op1_en && io.ball_decode_cmd_o.bits.op2_en && - io.ball_decode_cmd_o.bits.op1_bank === io.ball_decode_cmd_o.bits.op2_bank), - "BallDomainDecoder: Ball instruction OpA and OpB cannot access the same bank") + assert( + !(ball_decode_cmd_o.valid && ball_decode_cmd_o.bits.op1_en && ball_decode_cmd_o.bits.op2_en && + ball_decode_cmd_o.bits.op1_bank === ball_decode_cmd_o.bits.op2_bank), + "BallDomainDecoder: Ball instruction OpA and OpB cannot access the same bank" + ) // ----------------------------------------------------------------------------- // Continue passing rs1 and rs2 // ----------------------------------------------------------------------------- - io.ball_decode_cmd_o.bits.rs1 := rs1 - io.ball_decode_cmd_o.bits.rs2 := rs2 + ball_decode_cmd_o.bits.rs1 := rs1 + ball_decode_cmd_o.bits.rs2 := rs2 } diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index a0af441d..dc6721fe 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -2,24 +2,41 @@ package examples.toy.balldomain.bbus import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.instantiable import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import examples.toy.balldomain.BallDomainParam import framework.balldomain.bbus.BBus +import prototype.vector.configs.VecConfig +import prototype.matrix.configs.MatrixConfig +import prototype.im2col.configs.Im2colConfig +import prototype.transpose.configs.TransposeConfig +import prototype.relu.configs.ReluConfig +import prototype.transfer.configs.TransferConfig /** * BBusModule - Ball bus module that directly extends BBus */ -class BBusModule(implicit b: CustomBuckyballConfig, p: Parameters) extends BBus ( - // Define Ball device generators to register - Seq( - () => new prototype.vector.VecBall(0), - () => new prototype.matrix.MatrixBall(1), - () => new prototype.im2col.Im2colBall(2), - () => new prototype.transpose.TransposeBall(3), - () => new prototype.relu.ReluBall(4), - () => new examples.toy.balldomain.emptyball.EmptyBall(5), - () => new prototype.transfer.TransferBall(6) - ) -) { +@instantiable +class BBusModule(parameter: BallDomainParam)(implicit p: Parameters) + extends BBus( + parameter, + // Define Ball device generators to register + Seq( + () => new prototype.vector.VecBall(VecConfig.fromBallDomain(parameter), 0), + () => new prototype.matrix.MatrixBall(MatrixConfig.fromBallDomain(parameter), 1), + () => new prototype.im2col.Im2colBall(Im2colConfig.fromBallDomain(parameter), 2), + () => new prototype.transpose.TransposeBall(TransposeConfig.fromBallDomain(parameter), 3), + () => new prototype.relu.ReluBall(ReluConfig.fromBallDomain(parameter), 4), + () => + new examples.toy.balldomain.emptyball.EmptyBall( + parameter, + 5, + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen + ), + () => new prototype.transfer.TransferBall(TransferConfig.fromBallDomain(parameter), 6) + ) + ) { override lazy val desiredName = "BBusModule" } diff --git a/arch/src/main/scala/examples/toy/balldomain/configs/default.json b/arch/src/main/scala/examples/toy/balldomain/configs/default.json new file mode 100644 index 00000000..000d56bb --- /dev/null +++ b/arch/src/main/scala/examples/toy/balldomain/configs/default.json @@ -0,0 +1,9 @@ +{ + "rob_entries": 16, + "numBanks": 32, + "bbusChannel": 8, + "bankEntries": 128, + "bankWidth": 128, + "bankMaskLen": 16, + "emptyBallid": 5 +} diff --git a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala index 5abcc76f..3354fb1e 100644 --- a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala +++ b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala @@ -2,56 +2,51 @@ package examples.toy.balldomain.emptyball import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} - -class EmptyBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module with BallRegist { - val io = IO(new Blink) +import chisel3.experimental.hierarchy.{instantiable, public} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} + +@instantiable +class EmptyBall( + parameter: BallDomainParam, + id: Int, + bankEntries: Int, + bankWidth: Int, + bankMaskLen: Int) + extends Module + with BallRegist { + @public + val io = IO(new Blink(parameter, bankEntries, bankWidth, bankMaskLen)) val ballId = id.U def Blink: Blink = io - io.cmdResp.valid := RegNext(io.cmdReq.valid) + io.cmdResp.valid := RegNext(io.cmdReq.valid) io.cmdResp.bits.rob_id := RegNext(io.cmdReq.bits.rob_id) - io.cmdReq.ready := true.B - - for (i <- 0 until b.sp_banks) { - io.sramRead(i).io.req.valid := false.B - io.sramRead(i).io.req.bits.addr := 0.U - io.sramRead(i).io.req.bits.fromDMA := false.B - io.sramRead(i).io.resp.ready := false.B - io.sramRead(i).rob_id := 0.U - - io.sramWrite(i).io.req.valid := false.B - io.sramWrite(i).io.req.bits.addr := 0.U - io.sramWrite(i).io.req.bits.data := 0.U - io.sramWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) - io.sramWrite(i).rob_id := 0.U - } - - // Handle Accumulator read interface - EmptyBall does not read accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramReadIO), we need to drive req.valid, req.bits (outputs) and resp.ready (output) - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } - - // Handle Accumulator write interface - EmptyBall does not write accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramWriteIO), we need to drive req.valid and req.bits (outputs) - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + io.cmdReq.ready := true.B + + for (i <- 0 until parameter.numBanks) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.req.bits.fromDMA := false.B + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).rob_id := 0.U + io.bankRead(i).bank_id := 0.U + + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(bankMaskLen)(0.U(1.W))) + io.bankWrite(i).rob_id := 0.U + io.bankWrite(i).bank_id := 0.U + io.bankWrite(i).io.req.bits.wmode := false.B } io.status.ready := true.B - io.status.valid := io.cmdResp.valid - io.status.idle := false.B - io.status.init := false.B - io.status.running := false.B - io.status.iter := 0.U + io.status.valid := io.cmdResp.valid + io.status.idle := false.B + io.status.init := false.B + io.status.running := false.B + io.status.iter := 0.U io.status.complete := io.cmdResp.valid } diff --git a/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala b/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala index da797fc3..39e80f15 100644 --- a/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala @@ -2,24 +2,27 @@ package examples.toy.balldomain.rs import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import chisel3.experimental.hierarchy.instantiable +import examples.toy.balldomain.BallDomainParam import framework.balldomain.rs.{BallReservationStation, BallRsRegist} /** * Ball RS module - references BBus mechanism, manages Ball device registration and connections */ -class BallRSModule(implicit b: CustomBuckyballConfig, p: Parameters) extends BallReservationStation( - // Define Ball device information to register - Seq( - BallRsRegist(ballId = 0, ballName = "VecBall"), - BallRsRegist(ballId = 1, ballName = "MatrixBall"), - BallRsRegist(ballId = 2, ballName = "Im2colBall"), - BallRsRegist(ballId = 3, ballName = "TransposeBall"), - BallRsRegist(ballId = 4, ballName = "ReluBall"), - BallRsRegist(ballId = 5, ballName = "EmptyBall"), - BallRsRegist(ballId = 6, ballName = "TransferBall") - ) -) { +@instantiable +class BallRSModule(parameter: BallDomainParam) + extends BallReservationStation( + parameter, + // Define Ball device information to register + Seq( + BallRsRegist(ballId = 0, ballName = "VecBall"), + BallRsRegist(ballId = 1, ballName = "MatrixBall"), + BallRsRegist(ballId = 2, ballName = "Im2colBall"), + BallRsRegist(ballId = 3, ballName = "TransposeBall"), + BallRsRegist(ballId = 4, ballName = "ReluBall"), + BallRsRegist(ballId = 5, ballName = "EmptyBall"), + BallRsRegist(ballId = 6, ballName = "TransferBall") + ) + ) { override lazy val desiredName = "BallRSModule" } diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index db08c4fa..db2a2a58 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -2,59 +2,70 @@ package framework.balldomain.bbus import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import framework.memdomain.mem.{SramReadIO, SramWriteIO} +import chisel3.experimental.hierarchy.{instantiable, public} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.blink.BallRegist import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter -import framework.switcher.{ToPhysicalLine, ToVirtualLine} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} +import framework.balldomain.blink.{BankRead, BankWrite} - -class BBusConfigIO(numBalls: Int)extends Bundle { +class BBusConfigIO(numBalls: Int) extends Bundle { val src_bid = UInt(log2Ceil(numBalls).W) val dst_bid = UInt(log2Ceil(numBalls).W) val set = Bool() } + /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices */ -class BBus(ballGenerators: Seq[() => BallRegist with Module]) - (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class BBus(val parameter: BallDomainParam, ballGenerators: Seq[() => BallRegist with Module]) extends Module { val numBalls = ballGenerators.length - private val numBanks = b.sp_banks + b.acc_banks - val io = IO(new Bundle { - val cmdReq = Vec(numBalls, Flipped(Decoupled(new BallRsIssue))) - val cmdResp = Vec(numBalls, Decoupled(new BallRsComplete)) - val sramRead = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) - val sramWrite = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - // val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - // val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) - }) + @public + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(parameter))))) + + @public + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(parameter)))) + + @public + val bankRead = IO(Vec( + parameter.numBanks, + Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.numBanks)) + )) + + @public + val bankWrite = IO(Vec( + parameter.numBanks, + Flipped(new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.numBanks + )) + )) // Instantiate all registered Balls val balls = ballGenerators.map(gen => Module(gen())) - // ----------------------------------------------------------------------------- // cmd router // ----------------------------------------------------------------------------- - val cmdRouter = Module(new CmdRouter(numBalls)) + val cmdRouter = Module(new CmdRouter(parameter, numBalls)) val idle_ball = Wire(Vec(numBalls, Bool())) for (i <- 0 until numBalls) { idle_ball(i) := balls(i).Blink.cmdReq.ready } - cmdRouter.io.cmdReq_i <> io.cmdReq + cmdRouter.io.cmdReq_i <> cmdReq cmdRouter.io.ballIdle := idle_ball for (i <- 0 until numBalls) { balls(i).Blink.cmdReq.valid := cmdRouter.io.cmdReq_o.valid && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) - balls(i).Blink.cmdReq.bits := cmdRouter.io.cmdReq_o.bits + balls(i).Blink.cmdReq.bits := cmdRouter.io.cmdReq_o.bits } cmdRouter.io.cmdReq_o.ready := VecInit((0 until numBalls).map(i => @@ -65,59 +76,37 @@ class BBus(ballGenerators: Seq[() => BallRegist with Module]) cmdRouter.io.cmdResp_i(i) <> balls(i).Blink.cmdResp } - io.cmdResp <> cmdRouter.io.cmdResp_o - -// ----------------------------------------------------------------------------- -// bus router -// ----------------------------------------------------------------------------- - + cmdResp <> cmdRouter.io.cmdResp_o // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- - val memoryrouter = Module(new MemRouter(numBalls)(b, p)) + val memoryrouter = Module(new MemRouter(parameter, numBalls, parameter.bbusChannel)) memoryrouter.io.bbusConfig_i <> cmdRouter.io.bbusConfig_o - io.sramRead <> memoryrouter.io.sramRead_o - io.sramWrite <> memoryrouter.io.sramWrite_o -// ----------------------------------------------------------------------------- -// PMC - Performance Monitor Counter -// ----------------------------------------------------------------------------- - val pmc = Module(new BallCyclePMC(numBalls)) - - for (i <- 0 until numBalls) { - pmc.io.cmdReq_i(i).valid := cmdRouter.io.cmdReq_i(i).fire - pmc.io.cmdReq_i(i).bits := cmdRouter.io.cmdReq_i(i).bits - // Remove delay caused by RoB blocking preventing commit - pmc.io.cmdResp_o(i).valid := cmdRouter.io.cmdResp_o(i).valid - pmc.io.cmdResp_o(i).bits := cmdRouter.io.cmdResp_o(i).bits - } -//----------------------------------------------------------------------------- -// ToVirtualLine - per-ball address to virtual line conversion -// ----------------------------------------------------------------------------- - - val toVirtualLines = Seq.fill(numBalls){ Module(new ToVirtualLine()(b, p)) } + // Direct connection from balls to memory router (no ToVirtualLine) for (i <- 0 until numBalls) { - toVirtualLines(i).io.sramRead_i <> balls(i).Blink.sramRead - toVirtualLines(i).io.sramWrite_i <> balls(i).Blink.sramWrite - toVirtualLines(i).io.accRead_i <> balls(i).Blink.accRead - toVirtualLines(i).io.accWrite_i <> balls(i).Blink.accWrite + for (j <- 0 until parameter.numBanks) { + memoryrouter.io.bankRead_i(i)(j) <> balls(i).Blink.bankRead(j) + memoryrouter.io.bankWrite_i(i)(j) <> balls(i).Blink.bankWrite(j) + } } - for(i <- 0 until numBalls){ - memoryrouter.io.sramRead_i(i) <> toVirtualLines(i).io.sramRead_o - memoryrouter.io.sramWrite_i(i) <> toVirtualLines(i).io.sramWrite_o - } + bankRead <> memoryrouter.io.bankRead_o + bankWrite <> memoryrouter.io.bankWrite_o // ----------------------------------------------------------------------------- -// ToPhysicalLine - per-ball conversion from virtual to physical line +// PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- + val pmc = Module(new BallCyclePMC(parameter, numBalls)) - // val toPhysicalLines = Module(new ToPhysicalLine()(b, p)) - - // toPhysicalLines.io.sramRead_i <> memoryrouter.io.sramRead_o - // toPhysicalLines.io.sramWrite_i <> memoryrouter.io.sramWrite_o - + for (i <- 0 until numBalls) { + pmc.io.cmdReq_i(i).valid := cmdRouter.io.cmdReq_i(i).fire + pmc.io.cmdReq_i(i).bits := cmdRouter.io.cmdReq_i(i).bits + // Remove delay caused by RoB blocking preventing commit + pmc.io.cmdResp_o(i).valid := cmdRouter.io.cmdResp_o(i).valid + pmc.io.cmdResp_o(i).bits := cmdRouter.io.cmdResp_o(i).bits + } override lazy val desiredName = "BBus" -} \ No newline at end of file +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala index a0b7388d..913e59c4 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala @@ -2,23 +2,23 @@ package framework.balldomain.bbus.cmdrouter import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.BallRsIssue + +class CmdReqRouter(val parameter: BallDomainParam, val numBalls: Int) extends Module { -class CmdReqRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val io = IO(new Bundle { - val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue))) + val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(parameter)))) val ballIdle = Input(Vec(numBalls, Bool())) - val cmdReq_o = Decoupled(new BallRsIssue) + val cmdReq_o = Decoupled(new BallRsIssue(parameter)) }) - val arbiter = Module(new RRArbiter(new BallRsIssue, numBalls)) + val arbiter = Module(new RRArbiter(new BallRsIssue(parameter), numBalls)) for (i <- 0 until numBalls) { arbiter.io.in(i).valid := io.cmdReq_i(i).valid && io.ballIdle(i) - arbiter.io.in(i).bits := io.cmdReq_i(i).bits - io.cmdReq_i(i).ready := arbiter.io.in(i).ready && io.ballIdle(i) + arbiter.io.in(i).bits := io.cmdReq_i(i).bits + io.cmdReq_i(i).ready := arbiter.io.in(i).ready && io.ballIdle(i) } io.cmdReq_o <> arbiter.io.out diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala index 1534418e..0d649b81 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala @@ -2,17 +2,17 @@ package framework.balldomain.bbus.cmdrouter import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.BallRsComplete + +class CmdRespRouter(val parameter: BallDomainParam, val numBalls: Int) extends Module { -class CmdRespRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val io = IO(new Bundle { - val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete))) - val cmdResp_o = Decoupled(new BallRsComplete) + val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(parameter)))) + val cmdResp_o = Decoupled(new BallRsComplete(parameter)) }) - val arbiter = Module(new RRArbiter(new BallRsComplete, numBalls)) + val arbiter = Module(new RRArbiter(new BallRsComplete(parameter), numBalls)) for (i <- 0 until numBalls) { arbiter.io.in(i) <> io.cmdResp_i(i) diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala index 3bb11d4b..f7779260 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala @@ -2,22 +2,22 @@ package framework.balldomain.bbus.cmdrouter import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.bbus.BBusConfigIO -class CmdRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +class CmdRouter(val parameter: BallDomainParam, val numBalls: Int) extends Module { + val io = IO(new Bundle { - val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue))) - val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete))) - val ballIdle = Input(Vec(numBalls, Bool())) - val cmdReq_o = Decoupled(new BallRsIssue) - val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete)) + val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(parameter)))) + val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(parameter)))) + val ballIdle = Input(Vec(numBalls, Bool())) + val cmdReq_o = Decoupled(new BallRsIssue(parameter)) + val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete(parameter))) val bbusConfig_o = Decoupled(new BBusConfigIO(numBalls)) }) - val reqRouter = Module(new CmdReqRouter(numBalls)) + val reqRouter = Module(new CmdReqRouter(parameter, numBalls)) reqRouter.io.cmdReq_i <> io.cmdReq_i reqRouter.io.ballIdle := io.ballIdle @@ -26,15 +26,15 @@ class CmdRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) for (i <- 0 until numBalls) { io.cmdResp_o(i) <> io.cmdResp_i(i) } - io.bbusConfig_o.valid := false.B + io.bbusConfig_o.valid := false.B io.bbusConfig_o.bits.src_bid := 0.U io.bbusConfig_o.bits.dst_bid := 0.U - io.bbusConfig_o.bits.set := false.B - when(io.cmdReq_i(b.emptyBallid).valid){ - io.bbusConfig_o.valid := true.B - io.bbusConfig_o.bits.src_bid := io.cmdReq_i(b.emptyBallid).bits.cmd.special(5,0) - io.bbusConfig_o.bits.dst_bid := io.cmdReq_i(b.emptyBallid).bits.cmd.special(11,6) - io.bbusConfig_o.bits.set := io.cmdReq_i(b.emptyBallid).bits.cmd.special(12,12) + io.bbusConfig_o.bits.set := false.B + when(io.cmdReq_i(parameter.emptyBallid).valid) { + io.bbusConfig_o.valid := true.B + io.bbusConfig_o.bits.src_bid := io.cmdReq_i(parameter.emptyBallid).bits.cmd.special(5, 0) + io.bbusConfig_o.bits.dst_bid := io.cmdReq_i(parameter.emptyBallid).bits.cmd.special(11, 6) + io.bbusConfig_o.bits.set := io.cmdReq_i(parameter.emptyBallid).bits.cmd.special(12, 12) } override lazy val desiredName = "CmdRouter" } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala deleted file mode 100644 index f7556bd8..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/SramIOAdapter.scala +++ /dev/null @@ -1,31 +0,0 @@ -package framework.balldomain.bbus.memrouter - - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq, SramReadResp, SramWriteReq} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} - -class SramIOAdapter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new Bundle { - val sramWrite_i = new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len) - val sramRead_o = new SramReadWithInfo(b.spad_bank_entries, b.spad_w) - }) - - val read_o = Wire(new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) - - read_o.io.req.ready := true.B - io.sramWrite_i.io.req.ready := read_o.io.resp.ready - read_o.io.resp.valid := io.sramWrite_i.io.req.valid - read_o.io.resp.bits.data := io.sramWrite_i.io.req.bits.data - read_o.io.resp.bits.fromDMA := false.B - - read_o.rob_id := io.sramWrite_i.rob_id - read_o.is_acc := io.sramWrite_i.is_acc - read_o.bank_id := io.sramWrite_i.bank_id - - io.sramRead_o <> read_o -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index c702cced..01f43aad 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -2,97 +2,63 @@ package framework.balldomain.bbus.memrouter import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq, SramReadResp, SramWriteReq} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.memdomain.backend.banks.{SramReadIO, SramReadReq, SramReadResp, SramWriteIO, SramWriteReq} +import framework.balldomain.blink.{BankRead, BankWrite} import framework.balldomain.bbus.BBusConfigIO +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -class MemRouter(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - private val numBanks = b.sp_banks + b.acc_banks - val io = IO(new Bundle { - val sramRead_i = Vec(numBalls, Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) - val sramWrite_i = Vec(numBalls, Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - - val bbusConfig_i = Flipped(Decoupled(new BBusConfigIO(numBalls))) - - val sramRead_o = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) - val sramWrite_o = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - - }) - - val list_valid = RegInit(VecInit(Seq.fill(numBalls)(false.B))) - val list_dst_bid = RegInit(VecInit(Seq.fill(numBalls)(0.U(log2Ceil(numBalls).W)))) - - // Explicitly initialize to false - val memReq = WireInit(VecInit(Seq.fill(numBalls)(false.B))) +@instantiable +class MemRouter(val parameter: BallDomainParam, val numBalls: Int, val bbusChannel: Int) + extends Module + with SerializableModule[BallDomainParam] { + @public + val io = IO(new Bundle { - // Default assignment - io.sramRead_o := DontCare - io.sramWrite_o := DontCare + val bankRead_i = Vec( + numBalls, + Vec( + parameter.numBanks, + new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.numBanks) + ) + ) - for (i <- 0 until numBalls) { - io.sramRead_i(i).foreach(_.io.req.ready := false.B) - io.sramRead_i(i).foreach(_.io.resp.valid := false.B) - io.sramRead_i(i).foreach(_.io.resp.bits := DontCare) - io.sramWrite_i(i).foreach(_.io.req.ready := false.B) - } + val bankWrite_i = Vec( + numBalls, + Vec( + parameter.numBanks, + new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.numBanks + ) + ) + ) - // Routing selection - for (i <- 0 until numBalls) { -/* - memReq(i) := io.sramRead_i(i).map(_.io.req.valid).reduce(_||_) || - io.sramWrite_i(i).map(_.io.req.valid).reduce(_||_) || - io.accRead_i(i).map(_.io.req.valid).reduce(_||_) || - io.accWrite_i(i).map(_.io.req.valid).reduce(_||_) + val bbusConfig_i = Flipped(Decoupled(new BBusConfigIO(numBalls))) - when (memReq(i)) { - io.sramRead_o <> io.sramRead_i(i).io - io.sramWrite_o <> io.sramWrite_i(i).io - io.accRead_o <> io.accRead_i(i).io - io.accWrite_o <> io.accWrite_i(i).io - } - */ + // Output: bbusChannel channels to MemDomain frontend + val bankRead_o = Vec( + bbusChannel, + Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.numBanks)) + ) - for(j <- 0 until numBanks){ - when(io.sramRead_i(i)(j).io.req.valid){ - io.sramRead_o(j).io.req <> io.sramRead_i(i)(j).io.req - } - } - for(j <- 0 until numBanks){ - when(io.sramRead_o(j).io.resp.valid){ - io.sramRead_i(i)(j).io.resp <> io.sramRead_o(j).io.resp - } - } + val bankWrite_o = Vec( + bbusChannel, + Flipped(new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.numBanks + )) + ) - for(j <- 0 until numBanks){ - when(io.sramWrite_i(i)(j).io.req.valid){ - io.sramWrite_o(j)<> io.sramWrite_i(i)(j) - } - } - } - io.bbusConfig_i.ready := true.B - when (io.bbusConfig_i.valid) { - when(io.bbusConfig_i.bits.set === 1.U){ - list_valid(io.bbusConfig_i.bits.src_bid) := true.B - list_dst_bid(io.bbusConfig_i.bits.src_bid) := io.bbusConfig_i.bits.dst_bid - }.otherwise{ - list_valid(io.bbusConfig_i.bits.src_bid) := false.B - list_dst_bid(io.bbusConfig_i.bits.src_bid) := 0.U - } - } + }) - for(i <- 0 until numBalls){ - when(list_valid(i)){ - val sramIOadapter = Module(new SramIOAdapter(numBalls)(b, p)) - val dst_bid = list_dst_bid(i) - sramIOadapter.io.sramWrite_i <> io.sramWrite_i(i)(0) - io.sramRead_i(dst_bid)(0) <> sramIOadapter.io.sramRead_o - io.sramWrite_o(0).io.req.valid := false.B - io.sramWrite_o(0).io.req.bits := DontCare - } - } - override lazy val desiredName = "MemRouter" -} \ No newline at end of file +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala index bef6b307..f0b12a68 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala @@ -2,21 +2,22 @@ package framework.balldomain.bbus.pmc import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.BallRsIssue +import framework.balldomain.rs.BallRsComplete + +class BallCyclePMC(val parameter: BallDomainParam, val numBalls: Int) extends Module { -class BallCyclePMC(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { val io = IO(new Bundle { - val cmdReq_i = Input(Vec(numBalls, Valid(new BallRsIssue))) - val cmdResp_o = Input(Vec(numBalls, Valid(new BallRsComplete))) + val cmdReq_i = Input(Vec(numBalls, Valid(new BallRsIssue(parameter)))) + val cmdResp_o = Input(Vec(numBalls, Valid(new BallRsComplete(parameter)))) val totalCycles = Output(Vec(numBalls, UInt(64.W))) }) val cycleCounter = RegInit(0.U(64.W)) cycleCounter := cycleCounter + 1.U - val startTime = Reg(Vec(b.rob_entries, UInt(64.W))) + val startTime = Reg(Vec(parameter.rob_entries, UInt(64.W))) val ballTotalCycles = RegInit(VecInit(Seq.fill(numBalls)(0.U(64.W)))) for (i <- 0 until numBalls) { @@ -27,7 +28,7 @@ class BallCyclePMC(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Paramete for (i <- 0 until numBalls) { when(io.cmdResp_o(i).valid) { - val robId = io.cmdResp_o(i).bits.rob_id + val robId = io.cmdResp_o(i).bits.rob_id val elapsed = cycleCounter - startTime(robId) ballTotalCycles(i) := ballTotalCycles(i) + elapsed printf("[PMC] Ball %d completed task, elapsed: %d cycles\n", i.U, elapsed) diff --git a/arch/src/main/scala/framework/balldomain/blink/baseball.scala b/arch/src/main/scala/framework/balldomain/blink/baseball.scala index 365cdc22..25c0ce2f 100644 --- a/arch/src/main/scala/framework/balldomain/blink/baseball.scala +++ b/arch/src/main/scala/framework/balldomain/blink/baseball.scala @@ -6,6 +6,6 @@ import org.chipsalliance.cde.config.Parameters // Base trait for Ball devices trait BallRegist { - def Blink: Blink + def Blink: Blink def ballId: UInt } diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index d5b127aa..349e3d1f 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -2,72 +2,67 @@ package framework.balldomain.blink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import framework.memdomain.mem.{SramReadIO, SramWriteIO} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} // Ball device status bundle class Status extends Bundle { - // device is ready to accept new input - val ready = Output(Bool()) - // device has valid output - val valid = Output(Bool()) - // no input and no output - val idle = Output(Bool()) - // has input but no output - val init = Output(Bool()) - // started producing output - val running = Output(Bool()) - // fully finished current batch + val ready = Output(Bool()) + val valid = Output(Bool()) + val idle = Output(Bool()) + val init = Output(Bool()) + val running = Output(Bool()) val complete = Output(Bool()) - // current batch iteration - val iter = Output(UInt(32.W)) + val iter = Output(UInt(32.W)) } - -// SramReadIO with rob_id -class SramReadWithRobId(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val io = new SramReadIO(n, w) +// BankRead with rob_id, bank_id +class BankRead( + val n: Int, + val w: Int, + rob_entries: Int, + total_banks: Int) + extends Bundle { + val io = new SramReadIO(n, w) // Input because the outer layer has Flipped - val rob_id = Input(UInt(log2Up(b.rob_entries).W)) -} - -// SramWriteIO with rob_id -class SramWriteWithRobId(val n: Int, val w: Int, val mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val io = new SramWriteIO(n, w, mask_len) - // Input because theSramWriteIO outer layer has Flipped - val rob_id = Input(UInt(log2Up(b.rob_entries).W)) + val rob_id = Input(UInt(log2Up(rob_entries).W)) + val bank_id = Input(UInt(log2Up(total_banks).W)) } -// SramReadIO with rob_id, is_acc, bank_id -class SramReadWithInfo(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val io = new SramReadIO(n, w) +// BankWrite with rob_id, bank_id +// wmode is in SramWriteIO.io.req.bits.wmode: true = accumulate (累加), false = overwrite (覆盖) +class BankWrite( + val n: Int, + val w: Int, + val mask_len: Int, + rob_entries: Int, + total_banks: Int) + extends Bundle { + val io = new SramWriteIO(n, w, mask_len) // Input because the outer layer has Flipped - val rob_id = Input(UInt(log2Up(b.rob_entries).W)) - val is_acc = Input(Bool()) - val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) + val rob_id = Input(UInt(log2Up(rob_entries).W)) + val bank_id = Input(UInt(log2Up(total_banks).W)) } -// SramWriteIO with rob_id, is_acc, bank_id -class SramWriteWithInfo(val n: Int, val w: Int, val mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val io = new SramWriteIO(n, w, mask_len) - // Input because theSramWriteIO outer layer has Flipped - val rob_id = Input(UInt(log2Up(b.rob_entries).W)) - val is_acc = Input(Bool()) - val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) -} - - // Standard interface for Ball devices -class Blink(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) +// bankEntries, bankWidth, bankMaskLen come from MemDomain, not BallDomain +class Blink( + parameter: BallDomainParam, + bankEntries: Int, + bankWidth: Int, + bankMaskLen: Int) + extends Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val cmdResp = Decoupled(new BallRsComplete(parameter)) + + val bankRead = + Vec(parameter.numBanks, Flipped(new BankRead(bankEntries, bankWidth, parameter.rob_entries, parameter.numBanks))) - val sramRead = Vec(b.sp_banks, Flipped(new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + val bankWrite = Vec( + parameter.numBanks, + Flipped(new BankWrite(bankEntries, bankWidth, bankMaskLen, parameter.rob_entries, parameter.numBanks)) + ) val status = new Status } diff --git a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala index f461309f..07482e5a 100644 --- a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala @@ -2,72 +2,74 @@ package framework.balldomain.rs import chisel3._ import chisel3.util._ -import chisel3.experimental._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import chisel3.experimental.hierarchy.{instantiable, public} import examples.toy.balldomain._ import framework.balldomain.blink.BallRegist // Ball device information - configuration information for registering Ball devices case class BallRsRegist( - ballId: Int, - ballName: String -) + ballId: Int, + ballName: String) // Ball domain issue interface - includes global rob_id -class BallRsIssue(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val cmd = new BallDecodeCmd +class BallRsIssue(parameter: BallDomainParam) extends Bundle { + val cmd = new BallDecodeCmd(parameter) // Global ROB ID - val rob_id = UInt(log2Up(b.rob_entries).W) + val rob_id = UInt(log2Up(parameter.rob_entries).W) } // Ball domain completion interface -class BallRsComplete(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val rob_id = UInt(log2Up(b.rob_entries).W) +class BallRsComplete(parameter: BallDomainParam) extends Bundle { + val rob_id = UInt(log2Up(parameter.rob_entries).W) } // Generic Ball domain issue interface - supports dynamic number of Ball devices -class BallIssueInterface(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val balls = Vec(numBalls, Decoupled(new BallRsIssue)) +class BallIssueInterface(numBalls: Int, parameter: BallDomainParam) extends Bundle { + val balls = Vec(numBalls, Decoupled(new BallRsIssue(parameter))) } // Generic Ball domain completion interface - supports dynamic number of Ball devices -class BallCommitInterface(numBalls: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val balls = Vec(numBalls, Flipped(Decoupled(new BallRsComplete))) +class BallCommitInterface(numBalls: Int, parameter: BallDomainParam) extends Bundle { + val balls = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(parameter)))) } // Local Ball reservation station - simple FIFO scheduler -class BallReservationStation(BallRsRegists: Seq[BallRsRegist]) - (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class BallReservationStation(val parameter: BallDomainParam, BallRsRegists: Seq[BallRsRegist]) extends Module { val numBalls = BallRsRegists.length - val io = IO(new Bundle { - // Decoded instruction input (with global rob_id) - val ball_decode_cmd_i = Flipped(new DecoupledIO(new Bundle { - val cmd = new BallDecodeCmd - // Global ROB ID - val rob_id = UInt(log2Up(b.rob_entries).W) - })) + @public + val ball_decode_cmd_i = IO(Flipped(new DecoupledIO(new Bundle { + val cmd = new BallDecodeCmd(parameter) + // Global ROB ID + val rob_id = UInt(log2Up(parameter.rob_entries).W) + }))) - // Rs -> BallController (multi-channel issue) - val issue_o = new BallIssueInterface(numBalls) - val commit_i = new BallCommitInterface(numBalls) + // Rs -> BallController (multi-channel issue) + @public + val issue_o = IO(new BallIssueInterface(numBalls, parameter)) - // Output completion signal (with global rob_id, single channel) - val complete_o = Decoupled(new BallRsComplete) - }) + @public + val commit_i = IO(new BallCommitInterface(numBalls, parameter)) + + // Output completion signal (with global rob_id, single channel) + @public + val complete_o = IO(Decoupled(new BallRsComplete(parameter))) // Simple FIFO queue, only for buffering - val fifo = Module(new Queue(new Bundle { - val cmd = new BallDecodeCmd - val rob_id = UInt(log2Up(b.rob_entries).W) - }, entries = 4)) // Small buffer is sufficient + val fifo = Module(new Queue( + new Bundle { + val cmd = new BallDecodeCmd(parameter) + val rob_id = UInt(log2Up(parameter.rob_entries).W) + }, + entries = 4 + )) // Small buffer is sufficient // ----------------------------------------------------------------------------- // Inbound - FIFO enqueue // ----------------------------------------------------------------------------- - fifo.io.enq <> io.ball_decode_cmd_i + fifo.io.enq <> ball_decode_cmd_i // ----------------------------------------------------------------------------- // Outbound - instruction issue (dispatch to corresponding Ball device based on bid) @@ -77,32 +79,33 @@ class BallReservationStation(BallRsRegists: Seq[BallRsRegist]) // Set issue signals for each Ball device for (i <- 0 until numBalls) { val ballId = BallRsRegists(i).ballId.U - io.issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === ballId - io.issue_o.balls(i).bits.cmd := headEntry.cmd - io.issue_o.balls(i).bits.rob_id := headEntry.rob_id + issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === ballId + issue_o.balls(i).bits.cmd := headEntry.cmd + issue_o.balls(i).bits.rob_id := headEntry.rob_id } // FIFO deq.ready - can only dequeue when target Ball device is ready fifo.io.deq.ready := VecInit( - BallRsRegists.zipWithIndex.map { case (info, idx) => - (headEntry.cmd.bid === info.ballId.U) && io.issue_o.balls(idx).ready + BallRsRegists.zipWithIndex.map { + case (info, idx) => + (headEntry.cmd.bid === info.ballId.U) && issue_o.balls(idx).ready } ).asUInt.orR // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.rob_entries).W), numBalls)) + val completeArb = Module(new Arbiter(UInt(log2Up(parameter.rob_entries).W), numBalls)) // Connect completion signals from all Ball devices to arbiter for (i <- 0 until numBalls) { - completeArb.io.in(i).valid := io.commit_i.balls(i).valid - completeArb.io.in(i).bits := io.commit_i.balls(i).bits.rob_id - io.commit_i.balls(i).ready := completeArb.io.in(i).ready + completeArb.io.in(i).valid := commit_i.balls(i).valid + completeArb.io.in(i).bits := commit_i.balls(i).bits.rob_id + commit_i.balls(i).ready := completeArb.io.in(i).ready } // Forward completion signal (with global rob_id) - io.complete_o.valid := completeArb.io.out.valid - io.complete_o.bits.rob_id := completeArb.io.out.bits - completeArb.io.out.ready := io.complete_o.ready + complete_o.valid := completeArb.io.out.valid + complete_o.bits.rob_id := completeArb.io.out.bits + completeArb.io.out.ready := complete_o.ready } diff --git a/arch/src/main/scala/framework/balldomain/rs/rob.scala b/arch/src/main/scala/framework/balldomain/rs/rob.scala index 25f7bff6..6e7e8b6a 100644 --- a/arch/src/main/scala/framework/balldomain/rs/rob.scala +++ b/arch/src/main/scala/framework/balldomain/rs/rob.scala @@ -2,75 +2,77 @@ package framework.balldomain.rs import chisel3._ import chisel3.util._ -import chisel3.experimental._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import examples.toy.balldomain.BallDomainParam import examples.toy.balldomain.BallDecodeCmd // ROB entry data structure - preserves ROB ID to support out-of-order completion -class RobEntry(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val cmd = new BallDecodeCmd - val rob_id = UInt(log2Up(b.rob_entries).W) +class RobEntry(val parameter: BallDomainParam) extends Bundle { + val cmd = new BallDecodeCmd(parameter) + val rob_id = UInt(log2Up(parameter.rob_entries).W) } -class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +class ROB(val parameter: BallDomainParam) extends Module { + val io = IO(new Bundle { // Allocation interface - val alloc = Flipped(new DecoupledIO(new BallDecodeCmd)) + val alloc = Flipped(new DecoupledIO(new BallDecodeCmd(parameter))) // Externally specified rob_id - val alloc_rob_id = Input(UInt(log2Up(b.rob_entries).W)) + val alloc_rob_id = Input(UInt(log2Up(parameter.rob_entries).W)) // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new RobEntry) + val issue = new DecoupledIO(new RobEntry(parameter)) // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(b.rob_entries).W))) + val complete = Flipped(new DecoupledIO(UInt(log2Up(parameter.rob_entries).W))) // Commit interface - commit completed head instruction // val commit = new DecoupledIO(new RobEntry) // Status signals - exposed to reservation station for decision making - val empty = Output(Bool()) - val full = Output(Bool()) + val empty = Output(Bool()) + val full = Output(Bool()) // head pointer position - val head_ptr = Output(UInt(log2Up(b.rob_entries).W)) + val head_ptr = Output(UInt(log2Up(parameter.rob_entries).W)) // Number of issued but uncompleted instructions - val issued_count = Output(UInt(log2Up(b.rob_entries + 1).W)) + val issued_count = Output(UInt(log2Up(parameter.rob_entries + 1).W)) // Whether each entry is valid - val entry_valid = Output(Vec(b.rob_entries, Bool())) + val entry_valid = Output(Vec(parameter.rob_entries, Bool())) // Whether each entry is complete - val entry_complete = Output(Vec(b.rob_entries, Bool())) + val entry_complete = Output(Vec(parameter.rob_entries, Bool())) }) // Circular ROB structure // Initialize to zero to avoid X states in FPGA - val robEntries = RegInit(VecInit(Seq.fill(b.rob_entries)(0.U.asTypeOf(new RobEntry)))) + val robEntries = RegInit(VecInit(Seq.fill(parameter.rob_entries)(0.U.asTypeOf(new RobEntry(parameter))))) // Whether entry is valid - val robValid = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robValid = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Whether entry is issued - val robIssued = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Whether entry is complete - val robComplete = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Circular queue pointers // Points to oldest uncommitted instruction - val headPtr = RegInit(0.U(log2Up(b.rob_entries).W)) + val headPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) // Points to next position to allocate - val tailPtr = RegInit(0.U(log2Up(b.rob_entries).W)) + val tailPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) // ROB ID circular counter - val robIdCounter = RegInit(0.U(log2Up(b.rob_entries).W)) + val robIdCounter = RegInit(0.U(log2Up(parameter.rob_entries).W)) // Number of issued but uncompleted instructions (used to limit issue) - val issuedCount = RegInit(0.U(log2Up(b.rob_entries + 1).W)) + val issuedCount = RegInit(0.U(log2Up(parameter.rob_entries + 1).W)) // Maximum issue limit: half of ROB depth - val maxIssueLimit = (b.rob_entries / 2).U + val maxIssueLimit = (parameter.rob_entries / 2).U // Queue status val isEmpty = headPtr === tailPtr && !robValid(headPtr) val isFull = headPtr === tailPtr && robValid(headPtr) - val count = Mux(isFull, b.rob_entries.U, - Mux(tailPtr >= headPtr, tailPtr - headPtr, - b.rob_entries.U + tailPtr - headPtr)) + + val count = Mux( + isFull, + parameter.rob_entries.U, + Mux(tailPtr >= headPtr, tailPtr - headPtr, parameter.rob_entries.U + tailPtr - headPtr) + ) // ----------------------------------------------------------------------------- // Inbound - instruction allocation @@ -80,13 +82,13 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { when(io.alloc.fire) { robEntries(tailPtr).cmd := io.alloc.bits robEntries(tailPtr).rob_id := robIdCounter - robValid(tailPtr) := true.B - robIssued(tailPtr) := false.B - robComplete(tailPtr) := false.B + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B // Update tail pointer and rob_id counter (circular) - tailPtr := Mux(tailPtr === (b.rob_entries - 1).U, 0.U, tailPtr + 1.U) - robIdCounter := Mux(robIdCounter === (b.rob_entries - 1).U, 0.U, robIdCounter + 1.U) + tailPtr := Mux(tailPtr === (parameter.rob_entries - 1).U, 0.U, tailPtr + 1.U) + robIdCounter := Mux(robIdCounter === (parameter.rob_entries - 1).U, 0.U, robIdCounter + 1.U) } // ----------------------------------------------------------------------------- @@ -107,28 +109,28 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // ----------------------------------------------------------------------------- // Find first valid and unissued instruction starting from head val canIssue = Wire(Bool()) - val issuePtr = Wire(UInt(log2Up(b.rob_entries).W)) + val issuePtr = Wire(UInt(log2Up(parameter.rob_entries).W)) // Default values canIssue := false.B issuePtr := headPtr // Scan from head to find first issuable instruction - val scanValid = Wire(Vec(b.rob_entries, Bool())) - for (i <- 0 until b.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.rob_entries.U, - headPtr + i.U - b.rob_entries.U, - headPtr + i.U) + val scanValid = Wire(Vec(parameter.rob_entries, Bool())) + for (i <- 0 until parameter.rob_entries) { + val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) } // Find first issuable position val firstValid = PriorityEncoder(scanValid.asUInt) - val hasValid = scanValid.asUInt.orR + val hasValid = scanValid.asUInt.orR - val actualIssuePtr = Mux(headPtr + firstValid >= b.rob_entries.U, - headPtr + firstValid - b.rob_entries.U, - headPtr + firstValid) + val actualIssuePtr = Mux( + headPtr + firstValid >= parameter.rob_entries.U, + headPtr + firstValid - parameter.rob_entries.U, + headPtr + firstValid + ) // Can only issue if issue limit is not reached val canIssueMore = issuedCount < maxIssueLimit @@ -140,7 +142,7 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { when(io.issue.fire) { robIssued(issuePtr) := true.B - issuedCount := issuedCount + 1.U + issuedCount := issuedCount + 1.U } // ----------------------------------------------------------------------------- @@ -151,34 +153,35 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // robValid(headPtr) := false.B // robIssued(headPtr) := false.B // robComplete(headPtr) := false.B - // headPtr := Mux(headPtr === (b.rob_entries - 1).U, 0.U, headPtr + 1.U) + // headPtr := Mux(tailPtr === (parameter.rob_entries - 1).U, 0.U, tailPtr + 1.U) // } // Sequential commit version // Commit all completed instructions - for (i <- 0 until b.rob_entries) { + for (i <- 0 until parameter.rob_entries) { when(robValid(i.U) && robComplete(i.U)) { - robValid(i.U) := false.B - robIssued(i.U) := false.B + robValid(i.U) := false.B + robIssued(i.U) := false.B robComplete(i.U) := false.B } } // Update head pointer: skip all completed (about to be cleared) positions // Find first "valid and incomplete" instruction position starting from head - val nextHeadCandidates = Wire(Vec(b.rob_entries, Bool())) - for (i <- 0 until b.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.rob_entries.U, - headPtr + i.U - b.rob_entries.U, - headPtr + i.U) + val nextHeadCandidates = Wire(Vec(parameter.rob_entries, Bool())) + for (i <- 0 until parameter.rob_entries) { + val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) // Entry is valid and incomplete (will not be committed) nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) } val hasUncommitted = nextHeadCandidates.asUInt.orR val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) - val nextHeadPtr = Mux(headPtr + nextHeadOffset >= b.rob_entries.U, - headPtr + nextHeadOffset - b.rob_entries.U, - headPtr + nextHeadOffset) + + val nextHeadPtr = Mux( + headPtr + nextHeadOffset >= parameter.rob_entries.U, + headPtr + nextHeadOffset - parameter.rob_entries.U, + headPtr + nextHeadOffset + ) // Update head pointer: // - If there are uncompleted instructions, move head to first uncompleted position @@ -188,10 +191,10 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // ----------------------------------------------------------------------------- // Status signals - exposed to reservation station // ----------------------------------------------------------------------------- - io.empty := isEmpty - io.full := isFull - io.head_ptr := headPtr - io.issued_count := issuedCount - io.entry_valid := robValid + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid io.entry_complete := robComplete } diff --git a/arch/src/main/scala/framework/builtin/BaseConfigs.scala b/arch/src/main/scala/framework/builtin/BaseConfigs.scala index ab1df656..c3c8fccd 100644 --- a/arch/src/main/scala/framework/builtin/BaseConfigs.scala +++ b/arch/src/main/scala/framework/builtin/BaseConfigs.scala @@ -3,77 +3,80 @@ package framework.builtin import scala.math.{max, pow, sqrt} import chisel3._ import chisel3.util._ +import chisel3.experimental.SerializableModuleParameter import freechips.rocketchip.tile.OpcodeSet import org.chipsalliance.cde.config._ -import framework.memdomain.dma.LocalAddr - sealed abstract trait BuckyballMemCapacity case class CapacityInKilobytes(kilobytes: Int) extends BuckyballMemCapacity case class CapacityInVectors(vectors: Int) extends BuckyballMemCapacity // case class CapacityInMatrices(matrices: Int) extends BuckyballMemCapacity -case class BaseConfig( - opcodes: OpcodeSet = OpcodeSet.custom3, +object BaseConfig { - inputType: Data, - accType: Data, + // upickle support for BuckyballMemCapacity + implicit def memCapacityRW: upickle.default.ReadWriter[BuckyballMemCapacity] = + upickle.default.ReadWriter.merge( + upickle.default.macroRW[CapacityInKilobytes], + upickle.default.macroRW[CapacityInVectors] + ) - veclane: Int = 16, - accveclane: Int = 4, + // upickle support for BaseConfig + implicit def rw: upickle.default.ReadWriter[BaseConfig] = upickle.default.macroRW +} - tlb_size: Int = 4, +case class BaseConfig( + tlb_size: Int = 4, // Number of RoB entries - rob_entries: Int = 16, + rob_entries: Int = 16, // Whether reservation station responds out-of-order (false = wait for ROB to be empty before responding) rs_out_of_order_response: Boolean = true, - // Unused - dma_maxbytes: Int = 64, - dma_buswidth: Int = 128, - - sp_banks: Int = 4, - acc_banks: Int = 8, - - sp_singleported: Boolean = true, - - sp_capacity: BuckyballMemCapacity = CapacityInKilobytes(256), - acc_capacity: BuckyballMemCapacity = CapacityInKilobytes(64), - - max_in_flight_mem_reqs: Int = 16, // Unused - aligned_to: Int = 1, - spad_read_delay: Int = 0, - + dma_maxbytes: Int = 64, + dma_buswidth: Int = 128, + bankNum: Int = 32, + // bit + bankWidth: Int = 128, + bankCapacity: BuckyballMemCapacity = CapacityInKilobytes(16), + sp_singleported: Boolean = true, + max_in_flight_mem_reqs: Int = 16, // Unused + aligned_to: Int = 1, + spad_read_delay: Int = 0, // Index length supporting SPAD (16384 rows) + ACC (4096 rows) - spAddrLen: Int = 15, + // spAddrLen: Int = 15, // Index length for 4GB - memAddrLen: Int = 32, - + memAddrLen: Int = 32, // Number of vector PEs per thread - numVecPE: Int = 16, + numVecPE: Int = 16, // Number of vector threads per thread - numVecThread: Int = 16, - + numVecThread: Int = 16, // Empty ball id - emptyBallid: Int = 5, - -) { - val spad_w = veclane * inputType.getWidth - val spad_mask_len = (spad_w / (aligned_to * 8)) max 1 - val spad_bank_entries = sp_capacity match { - case CapacityInKilobytes(kb) => kb * 1024 * 8 / (sp_banks * spad_w) - case CapacityInVectors(vs) => vs * veclane / sp_banks - } - val acc_w = accveclane * accType.getWidth - val acc_mask_len = (acc_w / (aligned_to * 8)) max 1 - val acc_bank_entries = acc_capacity match { - case CapacityInKilobytes(kb) => kb * 1024 * 8 / (acc_banks * acc_w) - case CapacityInVectors(vs) => vs * accveclane / acc_banks + emptyBallid: Int = 5, + // Bank channel (BBus bandwidth, same as MemDomain bankChannel) + bankChannel: Int = 8) + extends SerializableModuleParameter { + // Fixed data widths + val inputWidth: Int = 8 // UInt8 + val accWidth: Int = 32 // UInt32 + + val bankMaskLen = (bankWidth / (aligned_to * 8)) max 1 + + val bankEntries = bankCapacity match { + case CapacityInKilobytes(kb) => kb * 1024 * 8 / (bankNum * bankWidth) } - - val local_addr_t = new LocalAddr(sp_banks, spad_bank_entries, acc_banks, acc_bank_entries) - - - + // Helper methods to get Data types + def inputType: Data = UInt(inputWidth.W) + def accType: Data = UInt(accWidth.W) + + override def toString: String = + s"""BuckyballConfig + | ROB entries: $rob_entries + | Bank num: $bankNum + | Bank width: $bankWidth bits + | Bank entries: $bankEntries + | Bank capacity: $bankCapacity + | TLB size: $tlb_size + | DMA max bytes: $dma_maxbytes + |""".stripMargin } diff --git a/arch/src/main/scala/framework/builtin/configs/default.json b/arch/src/main/scala/framework/builtin/configs/default.json new file mode 100644 index 00000000..51371b5a --- /dev/null +++ b/arch/src/main/scala/framework/builtin/configs/default.json @@ -0,0 +1,21 @@ +{ + "tlb_size": 4, + "rob_entries": 16, + "rs_out_of_order_response": true, + "dma_maxbytes": 64, + "dma_buswidth": 128, + "bankNum": 32, + "bankWidth": 128, + "bankCapacity": { + "$type": "framework.builtin.CapacityInKilobytes", + "kilobytes": 16 + }, + "sp_singleported": true, + "max_in_flight_mem_reqs": 16, + "aligned_to": 1, + "spad_read_delay": 0, + "memAddrLen": 32, + "numVecPE": 16, + "numVecThread": 16, + "emptyBallid": 5 +} diff --git a/arch/src/main/scala/framework/builtin/util/Util.scala b/arch/src/main/scala/framework/builtin/util/Util.scala index 513b5b1a..a13ad6f7 100644 --- a/arch/src/main/scala/framework/builtin/util/Util.scala +++ b/arch/src/main/scala/framework/builtin/util/Util.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.util._ object Util { + def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { @@ -14,71 +15,97 @@ object Util { } } - def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { + def wrappingAdd( + u: UInt, + n: UInt, + max_plus_one: UInt, + en: Bool = true.B + ): UInt = { val max = max_plus_one - 1.U assert(n <= max || max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") - /* - Mux(!en, u, - Mux (max === 0.U, 0.U, - Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) - */ - - MuxCase(u + n, Seq( - (!en) -> u, - (max === 0.U) -> 0.U, - (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) - )) + /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) */ + + MuxCase( + u + n, + Seq( + (!en) -> u, + (max === 0.U) -> 0.U, + (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) + ) + ) } - def satAdd(u: UInt, v: UInt, max: UInt): UInt = { + def satAdd(u: UInt, v: UInt, max: UInt): UInt = Mux(u +& v > max, max, u + v) - } - def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { + def floorAdd( + u: UInt, + n: UInt, + max_plus_one: UInt, + en: Bool = true.B + ): UInt = { val max = max_plus_one - 1.U - MuxCase(u + n, Seq( - (!en) -> u, - ((u +& n) > max) -> 0.U - )) - } - - def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { + MuxCase( + u + n, + Seq( + (!en) -> u, + ((u +& n) > max) -> 0.U + ) + ) + } + + def sFloorAdd( + s: SInt, + n: UInt, + max_plus_one: SInt, + min: SInt, + en: Bool = true.B + ): SInt = { val max = max_plus_one - 1.S - MuxCase(s + n.zext, Seq( - (!en) -> s, - ((s +& n.zext) > max) -> min - )) + MuxCase( + s + n.zext, + Seq( + (!en) -> s, + ((s +& n.zext) > max) -> min + ) + ) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") - Mux(u < n, max.U - (n-u) + 1.U, u - n) + Mux(u < n, max.U - (n - u) + 1.U, u - n) } - def ceilingDivide(numer: Int, denom: Int): Int = { + def ceilingDivide(numer: Int, denom: Int): Int = if (numer % denom == 0) { numer / denom } - else { numer / denom + 1} - } + else { numer / denom + 1 } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? - val exp = u.asBools.zipWithIndex.map { case (b, i) => + val exp = u.asBools.zipWithIndex.map { + case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } - def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { + def closestAlignedLowerPowerOf2( + u: UInt, + addr: UInt, + stride: UInt, + rowBytes: Int + ): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? - val exp = u.asBools.zipWithIndex.map { case (b, i) => - Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) + val exp = u.asBools.zipWithIndex.map { + case (b, i) => + Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt @@ -96,18 +123,16 @@ object Util { Mux(enable, next, buf) } - def maxOf(u1: UInt, u2: UInt): UInt = { + def maxOf(u1: UInt, u2: UInt): UInt = Mux(u1 > u2, u1, u2) - } // def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { // import ev._ // Mux(x > y, x, y) // } - def minOf(u1: UInt, u2: UInt): UInt = { + def minOf(u1: UInt, u2: UInt): UInt = Mux(u1 < u2, u1, u2) - } // def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { def accumulateTree(xs: Seq[UInt]): UInt = { @@ -118,9 +143,9 @@ object Util { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) - val upperRow = xs.padTo(upperRowLen, 0.U(xs.head.getWidth.W)) - val pairs = upperRow.grouped(2) - val lowerRow = pairs.map { case Seq(a, b) => a + b } + val upperRow = xs.padTo(upperRowLen, 0.U(xs.head.getWidth.W)) + val pairs = upperRow.grouped(2) + val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } @@ -128,11 +153,11 @@ object Util { // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() - val bits = t.cloneType + val bits = t.cloneType def push(b: T): Unit = { valid := true.B - bits := b + bits := b } def pop(dummy: Int = 0): T = { @@ -149,7 +174,7 @@ object Util { // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) - val reg = RegNext(wire) + val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } diff --git a/arch/src/main/scala/framework/core/rocket/Configs.scala b/arch/src/main/scala/framework/core/rocket/Configs.scala new file mode 100644 index 00000000..e938d71c --- /dev/null +++ b/arch/src/main/scala/framework/core/rocket/Configs.scala @@ -0,0 +1,275 @@ +package framework.core.rocket + +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.rocket._ +import freechips.rocketchip.prci.{AsynchronousCrossing, ClockCrossingType, RationalCrossing, SynchronousCrossing} +import freechips.rocketchip.subsystem.{ + CBUS, + CCBUS, + CacheBlockBytes, + CloneTileAttachParams, + ClustersLocated, + HierarchicalElementMasterPortParams, + HierarchicalElementSlavePortParams, + HierarchicalLocation, + InCluster, + InSubsystem, + NumTiles, + RocketCrossingParams, + RocketTileAttachParams, + SystemBusKey, + TileAttachConfig, + TilesLocated +} +import freechips.rocketchip.tile.{FPUParams, RocketTileBoundaryBufferParams, RocketTileParams} +import scala.reflect.ClassTag + +import framework.core.rocket.{RocketCrossingParamsBB, RocketTileParamsBB} + +class WithNBuckyballCores( + n: Int, + location: HierarchicalLocation, + crossing: RocketCrossingParams) + extends Config((site, here, up) => { + case TilesLocated(`location`) => { + val prev = up(TilesLocated(`location`), site) + val idOffset = up(NumTiles) + val big = RocketTileParamsBB( + usingRVVRoCC = true, + core = RocketCoreParams( + mulDiv = Some(MulDivParams( + mulUnroll = 8, + mulEarlyOut = true, + divEarlyOut = true + )), + useZba = true, + useZbb = true, + useZbs = true, + fpu = Some(FPUParams(minFLen = 16)) + ), + dcache = Some(DCacheParams( + nSets = 64, + nWays = 8, + rowBits = site(SystemBusKey).beatBits, + nMSHRs = 0, + blockBytes = site(CacheBlockBytes) + )), + icache = Some(ICacheParams( + nSets = 64, + nWays = 8, + rowBits = site(SystemBusKey).beatBits, + blockBytes = site(CacheBlockBytes) + )) + ) + List.tabulate(n)(i => + RocketTileAttachParamsBB( + big.copy(tileId = i + idOffset), + crossing + ) + ) ++ prev + } + case NumTiles => up(NumTiles) + n + }) { + def this(n: Int, location: HierarchicalLocation = InSubsystem) = this( + n, + location, + RocketCrossingParams( + master = HierarchicalElementMasterPortParams.locationDefault(location), + slave = HierarchicalElementSlavePortParams.locationDefault(location), + mmioBaseAddressPrefixWhere = location match { + case InSubsystem => CBUS + case InCluster(clusterId) => CCBUS(clusterId) + } + ) + ) +} + +class RocketTileAttachConfig(f: RocketTileAttachParams => RocketTileAttachParams) + extends TileAttachConfig[RocketTileAttachParams](f) + +class RocketTileConfig(f: RocketTileParams => RocketTileParams) + extends RocketTileAttachConfig(tp => + tp.copy( + tileParams = f(tp.tileParams) + ) + ) + +class RocketCrossingConfig(f: RocketCrossingParams => RocketCrossingParams) + extends RocketTileAttachConfig(tp => + tp.copy( + crossingParams = f(tp.crossingParams) + ) + ) + +class RocketCoreConfig(f: RocketCoreParams => RocketCoreParams) + extends RocketTileConfig(tp => + tp.copy( + core = f(tp.core) + ) + ) + +class RocketICacheConfig(f: ICacheParams => ICacheParams) + extends RocketTileConfig(tp => + tp.copy( + icache = tp.icache.map(ic => f(ic)) + ) + ) + +class RocketDCacheConfig(f: DCacheParams => DCacheParams) + extends RocketTileConfig(tp => + tp.copy( + dcache = tp.dcache.map(dc => f(dc)) + ) + ) + +class WithL1ICacheSets(sets: Int) extends RocketICacheConfig(_.copy(nSets = sets)) +class WithL1ICacheWays(ways: Int) extends RocketICacheConfig(_.copy(nWays = ways)) +class WithL1ICacheECC(dataECC: String, tagECC: String) + extends RocketICacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC))) +class WithL1ICacheRowBits(n: Int) extends RocketICacheConfig(_.copy(rowBits = n)) +class WithL1ICacheTLBSets(sets: Int) extends RocketICacheConfig(_.copy(nTLBSets = sets)) +class WithL1ICacheTLBWays(ways: Int) extends RocketICacheConfig(_.copy(nTLBWays = ways)) +class WithL1ICacheTLBBasePageSectors(sectors: Int) extends RocketICacheConfig(_.copy(nTLBBasePageSectors = sectors)) +class WithL1ICacheTLBSuperpages(superpages: Int) extends RocketICacheConfig(_.copy(nTLBSuperpages = superpages)) +class WithL1ICacheBlockBytes(bytes: Int = 64) extends RocketICacheConfig(_.copy(blockBytes = bytes)) + +class WithL1DCacheSets(sets: Int) extends RocketDCacheConfig(_.copy(nSets = sets)) +class WithL1DCacheWays(ways: Int) extends RocketDCacheConfig(_.copy(nWays = ways)) +class WithL1DCacheECC(dataECC: String, tagECC: String) + extends RocketDCacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC))) +class WithL1DCacheRowBits(n: Int) extends RocketDCacheConfig(_.copy(rowBits = n)) +class WithL1DCacheTLBSets(sets: Int) extends RocketDCacheConfig(_.copy(nTLBSets = sets)) +class WithL1DCacheTLBWays(ways: Int) extends RocketDCacheConfig(_.copy(nTLBWays = ways)) +class WithL1DCacheTLBBasePageSectors(sectors: Int) extends RocketDCacheConfig(_.copy(nTLBBasePageSectors = sectors)) +class WithL1DCacheTLBSuperpages(superpages: Int) extends RocketDCacheConfig(_.copy(nTLBSuperpages = superpages)) +class WithL1DCacheBlockBytes(bytes: Int = 64) extends RocketDCacheConfig(_.copy(blockBytes = bytes)) +class WithL1DCacheNonblocking(nMSHRs: Int) extends RocketDCacheConfig(_.copy(nMSHRs = nMSHRs)) +class WithL1DCacheClockGating extends RocketDCacheConfig(_.copy(clockGate = true)) +class WithL1DCacheDTIMAddress(address: BigInt) extends RocketDCacheConfig(_.copy(scratch = Some(address))) + +class WithScratchpadsOnly + extends RocketTileConfig(tp => + tp.copy( + core = tp.core.copy(useVM = false), + dcache = tp.dcache.map(_.copy( + nSets = 256, // 16Kb scratchpad + nWays = 1, + scratch = Some(0x80000000L) + )) + ) + ) + +class WithCacheRowBits(n: Int) + extends RocketTileConfig(tp => + tp.copy( + dcache = tp.dcache.map(_.copy(rowBits = n)), + icache = tp.icache.map(_.copy(rowBits = n)) + ) + ) + +class WithBEU(addr: BigInt) extends RocketTileConfig(_.copy(beuAddr = Some(addr))) +class WithBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) + extends RocketTileConfig(_.copy(boundaryBuffers = buffers)) + +class WithRV32 + extends RocketCoreConfig(c => + c.copy( + xLen = 32, + pgLevels = 2, // sv32 + fpu = c.fpu.map(_.copy(fLen = 32)), + mulDiv = Some(MulDivParams(mulUnroll = 8)) + ) + ) + +class WithoutVM extends RocketCoreConfig(_.copy(useVM = false)) +class WithCFlushEnabled extends RocketCoreConfig(_.copy(haveCFlush = true)) +class WithNBreakpoints(hwbp: Int) extends RocketCoreConfig(_.copy(nBreakpoints = hwbp)) +class WithHypervisor(hext: Boolean = true) extends RocketCoreConfig(_.copy(useHypervisor = hext)) +class WithCease(enable: Boolean = true) extends RocketCoreConfig(_.copy(haveCease = enable)) +class WithCoreClockGatingEnabled extends RocketCoreConfig(_.copy(clockGate = true)) +class WithPgLevels(n: Int) extends RocketCoreConfig(_.copy(pgLevels = n)) +class WithZba extends RocketCoreConfig(_.copy(useZba = true)) +class WithZbb extends RocketCoreConfig(_.copy(useZbb = true)) +class WithZbs extends RocketCoreConfig(_.copy(useZbs = true)) +class WithB extends RocketCoreConfig(_.copy(useZba = true, useZbb = true, useZbs = true)) +class WithSV48 extends WithPgLevels(4) +class WithSV39 extends WithPgLevels(3) + +// Simulation-only configs +class WithNoSimulationTimeout extends RocketCoreConfig(_.copy(haveSimTimeout = false)) +class WithDebugROB(enable: Boolean = true, size: Int = 0) + extends RocketCoreConfig(_.copy(debugROB = Option.when(enable)(DebugROBParams(size)))) + +// FPU configs +class WithoutFPU extends RocketCoreConfig(_.copy(fpu = None)) +class WithFP16 extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(minFLen = 16)))) +class WithFPUWithoutDivSqrt extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(divSqrt = false)))) + +// mul-div configs +class WithFastMulDiv + extends RocketCoreConfig(c => + c.copy(mulDiv = + Some( + MulDivParams(mulUnroll = 8, mulEarlyOut = c.xLen > 32, divEarlyOut = true) + ) + ) + ) + +class WithCustomFastMulDiv( + mUnroll: Int = 8, + mEarlyOut: Boolean = true, + dUnroll: Int = 1, + dEarlyOut: Boolean = true, + dEarlyOutGranularity: Int = 1) + extends RocketCoreConfig(_.copy(mulDiv = + Some( + MulDivParams( + mulUnroll = mUnroll, + mulEarlyOut = mEarlyOut, + divUnroll = dUnroll, + divEarlyOut = dEarlyOut, + divEarlyOutGranularity = dEarlyOutGranularity + ) + ) + )) + +class WithoutMulDiv extends RocketCoreConfig(_.copy(mulDiv = None)) + +// Branch-prediction configs +class WithDefaultBtb extends RocketTileConfig(t => t.copy(btb = Some(BTBParams()))) +class WithNoBtb extends RocketTileConfig(_.copy(btb = None)) + +// Tile CDC configs +class WithCDC(crossingType: ClockCrossingType = SynchronousCrossing()) + extends RocketCrossingConfig(_.copy(crossingType = crossingType)) +class WithSeperateClockReset extends RocketCrossingConfig(_.copy(forceSeparateClockReset = true)) +class WithSynchronousCDCs extends WithCDC(SynchronousCrossing()) +class WithAsynchronousCDCs(depth: Int, sync: Int) extends WithCDC(AsynchronousCrossing(depth, sync)) +class WithRationalCDCs extends WithCDC(RationalCrossing()) + +class WithCloneRocketTiles( + n: Int = 1, + cloneTileId: Int = 0, + location: HierarchicalLocation = InSubsystem, + cloneLocation: HierarchicalLocation = InSubsystem) + extends Config((site, here, up) => { + case TilesLocated(`location`) => { + val prev = up(TilesLocated(location), site) + val idOffset = up(NumTiles) + val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId) + .get.asInstanceOf[RocketTileAttachParams] + (0 until n).map { i => + CloneTileAttachParams( + cloneTileId, + tileAttachParams.copy( + tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset) + ) + ) + } ++ prev + } + case NumTiles => up(NumTiles) + n + }) diff --git a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala new file mode 100644 index 00000000..471822cc --- /dev/null +++ b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala @@ -0,0 +1,161 @@ +// See LICENSE.Berkeley for license details. +// See LICENSE.SiFive for license details. + +package framework.core.rocket + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.IntParam + +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.rocket.{ + CanHavePTW, + CanHavePTWModule, + HellaCacheIO, + MStatus, + M_SZ, + M_XRD, + PRV, + PTE, + SimpleHellaCacheIF, + TLBPTWIO +} +import freechips.rocketchip.tilelink.{TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters, TLNode} +import freechips.rocketchip.util.InOrderArbiter + +case object BuildRoCCBB extends Field[Seq[Parameters => LazyRoCCBB]](Nil) + +class RoCCCommandBB(implicit p: Parameters) extends CoreBundle()(p) { + val inst = new RoCCInstruction + val rs1 = Bits(xLen.W) + val rs2 = Bits(xLen.W) + val status = new MStatus +} + +class RoCCResponseBB(implicit p: Parameters) extends CoreBundle()(p) { + val rd = Bits(5.W) + val data = Bits(xLen.W) +} + +class RoCCCoreIOBB(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { + val cmd = Flipped(Decoupled(new RoCCCommandBB)) + val resp = Decoupled(new RoCCResponseBB) + val mem = new HellaCacheIO + val busy = Output(Bool()) + val interrupt = Output(Bool()) + val exception = Input(Bool()) + val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) +} + +class RoCCIOBB(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIOBB(nRoCCCSRs)(p) { + val ptw = Vec(nPTWPorts, new TLBPTWIO) + val fpu_req = Decoupled(new FPInput) + val fpu_resp = Flipped(Decoupled(new FPResult)) +} + +/** Base classes for Diplomatic TL2 RoCC units * */ +abstract class LazyRoCCBB( + val opcodes: OpcodeSet, + val nPTWPorts: Int = 0, + val usesFPU: Boolean = false, + val roccCSRs: Seq[CustomCSR] = Nil +)( + implicit p: Parameters) + extends LazyModule { + val module: LazyRoCCModuleImpBB + require(roccCSRs.map(_.id).toSet.size == roccCSRs.size) + val atlNode: TLNode = TLIdentityNode() + val tlNode: TLNode = TLIdentityNode() + val stlNode: TLNode = TLIdentityNode() +} + +class LazyRoCCModuleImpBB(outer: LazyRoCCBB) extends LazyModuleImp(outer) { + val io = IO(new RoCCIOBB(outer.nPTWPorts, outer.roccCSRs.size)) + io := DontCare +} + +/** Mixins for including RoCC * */ + +trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => + val roccs = p(BuildRoCCBB).map(_(p)) + val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs + require( + roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, + "LazyRoCC instantiations require overlapping CSRs" + ) + roccs.map(_.atlNode).foreach(atl => tlMasterXbar.node :=* atl) + roccs.map(_.tlNode).foreach(tl => tlOtherMastersNode :=* tl) + roccs.map(_.stlNode).foreach(stl => stl :*= tlSlaveXbar.node) + + nPTWPorts += roccs.map(_.nPTWPorts).sum + nDCachePorts += roccs.size +} + +trait HasLazyRoCCModuleBB extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImpBB => + + val (respArb, cmdRouter) = if (outer.roccs.nonEmpty) { + val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) + // Get usingRVVRoCC from tile parameters + val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC + val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) + outer.roccs.zipWithIndex.foreach { + case (rocc, i) => + rocc.module.io.ptw ++=: ptwPorts + rocc.module.io.cmd <> cmdRouter.io.out(i) + val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) + dcIF.io.requestor <> rocc.module.io.mem + dcachePorts += dcIF.io.cache + respArb.io.in(i) <> Queue(rocc.module.io.resp) + } + (Some(respArb), Some(cmdRouter)) + } else { + (None, None) + } + + val roccCSRIOs = outer.roccs.map(_.module.io.csrs) +} + +class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implicit p: Parameters) + extends CoreModule()(p) { + + val io = IO(new Bundle { + val in = Flipped(Decoupled(new RoCCCommand)) + val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) + val busy = Output(Bool()) + }) + + val cmd = Queue(io.in) + + // Check which opcodes match + val opcodeMatches = opcodes.map(opcode => opcode.matches(cmd.bits.inst.opcode)) + val anyMatch = opcodeMatches.reduce(_ || _) + + val cmdReadys = io.out.zip(opcodeMatches).zipWithIndex.map { + case ((out, matches), i) => + // In RVVRoCC mode: route unmatched opcodes to first RoCC (index 0) + // Otherwise: only route if opcode matches + val shouldRoute = if (usingRVVRoCC && i == 0) { + matches || !anyMatch // First RoCC gets matched opcodes OR unmatched opcodes + } else { + matches // Other RoCCs only get their matched opcodes + } + + out.valid := cmd.valid && shouldRoute + out.bits := cmd.bits + out.ready && shouldRoute + } + + cmd.ready := cmdReadys.reduce(_ || _) + io.busy := cmd.valid + + // In RVVRoCC mode, allow unmatched opcodes to go to first RoCC + // Otherwise, assert that only one RoCC matches + if (!usingRVVRoCC) { + assert(PopCount(cmdReadys) <= 1.U, "Custom opcode matched for more than one accelerator") + } +} diff --git a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala new file mode 100644 index 00000000..d8954479 --- /dev/null +++ b/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala @@ -0,0 +1,1454 @@ +// See LICENSE.Berkeley for license details. +// See LICENSE.SiFive for license details. + +package framework.core.rocket + +import chisel3._ +import chisel3.util._ +import chisel3.withClock +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile._ +import freechips.rocketchip.util._ +import freechips.rocketchip.util.property +import scala.collection.mutable.ArrayBuffer +import freechips.rocketchip.rocket._ + +import framework.core.rocket.RoCCCoreIOBB +import framework.core.rocket.id.RVVRoCCDecode + +trait HasRocketCoreIOBB extends HasRocketCoreParameters { + implicit val p: Parameters + def nTotalRoCCCSRs: Int + + val io = IO(new CoreBundle()(p) { + val hartid = Input(UInt(hartIdLen.W)) + val reset_vector = Input(UInt(resetVectorLen.W)) + val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParamsBB].beuAddr.isDefined)) + val imem = new FrontendIO + val dmem = new HellaCacheIO + val ptw = Flipped(new DatapathPTWIO()) + val fpu = Flipped(new FPUCoreIO()) + val rocc = Flipped(new RoCCCoreIOBB(nTotalRoCCCSRs)) + val trace = Output(new TraceBundle) + val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) + val cease = Output(Bool()) + val wfi = Output(Bool()) + val traceStall = Input(Bool()) + val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None + }) + +} + +class RocketBB(tile: RocketTileBB)(implicit p: Parameters) + extends CoreModule()(p) + with HasRocketCoreParameters + with HasRocketCoreIOBB { + def nTotalRoCCCSRs = tile.roccCSRs.flatten.size + import ALU._ + + val clock_en_reg = RegInit(true.B) + val long_latency_stall = Reg(Bool()) + val id_reg_pause = Reg(Bool()) + val imem_might_request_reg = Reg(Bool()) + val clock_en = WireDefault(true.B) + + val gated_clock = + if (!rocketParams.clockGate) clock + else ClockGate(clock, clock_en, "rocket_clock_gate") + + class RocketImpl { // entering gated-clock domain + + // performance counters + def pipelineIDToWB[T <: Data](x: T): T = + RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) + + val perfEvents = new EventSets(Seq( + new EventSet( + (mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), + Seq( + ("exception", () => false.B), + ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), + ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), + ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), + ("system", () => id_ctrl.csr =/= CSR.N), + ( + "arith", + () => + id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N) + ), + ("branch", () => id_ctrl.branch), + ("jal", () => id_ctrl.jal), + ("jalr", () => id_ctrl.jalr) + ) + ++ (if (!usingMulDiv) Seq() + else + Seq( + ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), + ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV) + )) + ++ (if (!usingFPU) Seq() + else + Seq( + ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), + ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), + ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), + ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), + ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), + ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)), + ( + "fp other", + () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt) + ) + )) + ), + new EventSet( + (mask, hits) => (mask & hits).orR, + Seq( + ( + "load-use interlock", + () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem + ), + ("long-latency interlock", () => id_sboard_hazard), + ( + "csr interlock", + () => + id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N + ), + ("I$ blocked", () => icache_blocked), + ("D$ blocked", () => id_ctrl.mem && dcache_blocked), + ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), + ( + "control-flow target misprediction", + () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked + ), + ("flush", () => wb_reg_flush_pipe), + ("replay", () => replay_wb) + ) + ++ (if (!usingMulDiv) Seq() + else + Seq( + ( + "mul/div interlock", + () => + id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div + ) + )) + ++ (if (!usingFPU) Seq() + else + Seq( + ( + "fp interlock", + () => + id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu + ) + )) + ), + new EventSet( + (mask, hits) => (mask & hits).orR, + Seq( + ("I$ miss", () => io.imem.perf.acquire), + ("D$ miss", () => io.dmem.perf.acquire), + ("D$ release", () => io.dmem.perf.release), + ("ITLB miss", () => io.imem.perf.tlbMiss), + ("DTLB miss", () => io.dmem.perf.tlbMiss), + ("L2 TLB miss", () => io.ptw.perf.l2miss) + ) + ) + )) + + val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen + + val usingRVVRoCC = tile.rocketParams.usingRVVRoCC + + // Ensure usingVector and usingRVVRoCC are mutually exclusive + require( + !usingVector || !usingRVVRoCC, + "usingVector and usingRVVRoCC cannot both be enabled. " + + "Use usingVector for built-in vector unit, or usingRVVRoCC to route vector instructions to RoCC." + ) + + val decode_table = { + (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: + (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: + (usingRVVRoCC.option(new RVVRoCCDecode)) ++: + (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: + (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: + (if (minFLen == 16) + new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq + else Nil) ++: + (usingRoCC.option(new RoCCDecode)) ++: + (if (xLen == 32) new I32Decode else new I64Decode) +: + (usingVM.option(new SVMDecode)) ++: + (usingSupervisor.option(new SDecode)) ++: + (usingHypervisor.option(new HypervisorDecode)) ++: + ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: + (usingDebug.option(new DebugDecode)) ++: + (usingNMI.option(new NMIDecode)) ++: + (usingConditionalZero.option(new ConditionalZeroDecode)) ++: + Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: + coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: + rocketParams.haveCease.option(new CeaseDecode) ++: + usingVector.option(new VCFGDecode) ++: + (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: + (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: + coreParams.useZbs.option(new ZbsDecode) ++: + Seq(new IDecode) + } flatMap (_.table) + + val ex_ctrl = Reg(new IntCtrlSigs) + val mem_ctrl = Reg(new IntCtrlSigs) + val wb_ctrl = Reg(new IntCtrlSigs) + + val ex_reg_xcpt_interrupt = Reg(Bool()) + val ex_reg_valid = Reg(Bool()) + val ex_reg_rvc = Reg(Bool()) + val ex_reg_btb_resp = Reg(new BTBResp) + val ex_reg_xcpt = Reg(Bool()) + val ex_reg_flush_pipe = Reg(Bool()) + val ex_reg_load_use = Reg(Bool()) + val ex_reg_cause = Reg(UInt()) + val ex_reg_replay = Reg(Bool()) + val ex_reg_pc = Reg(UInt()) + val ex_reg_mem_size = Reg(UInt()) + val ex_reg_hls = Reg(Bool()) + val ex_reg_inst = Reg(Bits()) + val ex_reg_raw_inst = Reg(UInt()) + val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) + val ex_reg_set_vconfig = Reg(Bool()) + + val mem_reg_xcpt_interrupt = Reg(Bool()) + val mem_reg_valid = Reg(Bool()) + val mem_reg_rvc = Reg(Bool()) + val mem_reg_btb_resp = Reg(new BTBResp) + val mem_reg_xcpt = Reg(Bool()) + val mem_reg_replay = Reg(Bool()) + val mem_reg_flush_pipe = Reg(Bool()) + val mem_reg_cause = Reg(UInt()) + val mem_reg_slow_bypass = Reg(Bool()) + val mem_reg_load = Reg(Bool()) + val mem_reg_store = Reg(Bool()) + val mem_reg_set_vconfig = Reg(Bool()) + val mem_reg_sfence = Reg(Bool()) + val mem_reg_pc = Reg(UInt()) + val mem_reg_inst = Reg(Bits()) + val mem_reg_mem_size = Reg(UInt()) + val mem_reg_hls_or_dv = Reg(Bool()) + val mem_reg_raw_inst = Reg(UInt()) + val mem_reg_wdata = Reg(Bits()) + val mem_reg_rs2 = Reg(Bits()) + val mem_br_taken = Reg(Bool()) + val take_pc_mem = Wire(Bool()) + val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) + + val wb_reg_valid = Reg(Bool()) + val wb_reg_xcpt = Reg(Bool()) + val wb_reg_replay = Reg(Bool()) + val wb_reg_flush_pipe = Reg(Bool()) + val wb_reg_cause = Reg(UInt()) + val wb_reg_set_vconfig = Reg(Bool()) + val wb_reg_sfence = Reg(Bool()) + val wb_reg_pc = Reg(UInt()) + val wb_reg_mem_size = Reg(UInt()) + val wb_reg_hls_or_dv = Reg(Bool()) + val wb_reg_hfence_v = Reg(Bool()) + val wb_reg_hfence_g = Reg(Bool()) + val wb_reg_inst = Reg(Bits()) + val wb_reg_raw_inst = Reg(UInt()) + val wb_reg_wdata = Reg(Bits()) + val wb_reg_rs2 = Reg(Bits()) + val take_pc_wb = Wire(Bool()) + val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) + + val take_pc_mem_wb = take_pc_wb || take_pc_mem + val take_pc = take_pc_mem_wb + + // decode stage + val ibuf = Module(new IBuf) + val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) + val id_raw_inst = ibuf.io.inst.map(_.bits.raw) + val id_inst = id_expanded_inst.map(_.bits) + ibuf.io.imem <> io.imem.resp + ibuf.io.kill := take_pc + + require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) + require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") + require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") + val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) + + val lgNXRegs = if (coreParams.useRVE) 4 else 5 + val regAddrMask = (1 << lgNXRegs) - 1 + + def decodeReg(x: UInt) = (x.extract(x.getWidth - 1, lgNXRegs).asBool, x(lgNXRegs - 1, 0)) + val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) + val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) + val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) + val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) + + val id_load_use = Wire(Bool()) + val id_reg_fence = RegInit(false.B) + val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) + val id_raddr = IndexedSeq(id_raddr1, id_raddr2) + val rf = new RegFile(regAddrMask, xLen) + val id_rs = id_raddr.map(rf.read _) + val ctrl_killd = Wire(Bool()) + val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt + + val csr = Module(new CSRFile( + perfEvents, + coreParams.customCSRs.decls, + tile.roccCSRs.flatten, + tile.rocketParams.beuAddr.isDefined + )) + + val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) + val id_system_insn = id_ctrl.csr === CSR.I + val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U + val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) + val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) + val id_set_vconfig = + Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B + + id_ctrl.vec := false.B + if (usingVector) { + val v_decode = rocketParams.vector.get.decoder(p) + v_decode.io.inst := id_inst(0) + v_decode.io.vconfig := csr.io.vector.get.vconfig + when(v_decode.io.legal) { + id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill + id_ctrl.fp := v_decode.io.fp + id_ctrl.rocc := false.B + id_ctrl.branch := false.B + id_ctrl.jal := false.B + id_ctrl.jalr := false.B + id_ctrl.rxs2 := v_decode.io.read_rs2 + id_ctrl.rxs1 := v_decode.io.read_rs1 + id_ctrl.mem := false.B + id_ctrl.rfs1 := v_decode.io.read_frs1 + id_ctrl.rfs2 := false.B + id_ctrl.rfs3 := false.B + id_ctrl.wfd := v_decode.io.write_frd + id_ctrl.mul := false.B + id_ctrl.div := false.B + id_ctrl.wxd := v_decode.io.write_rd + id_ctrl.csr := CSR.N + id_ctrl.fence_i := false.B + id_ctrl.fence := false.B + id_ctrl.amo := false.B + id_ctrl.dp := false.B + id_ctrl.vec := true.B + } + } + + val id_illegal_insn = !id_ctrl.legal || + (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m' - 'a') || + id_ctrl.amo && !csr.io.status.isa('a' - 'a') || + id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) || + (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse( + false.B + )) || + id_ctrl.dp && !csr.io.status.isa('d' - 'a') || + ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c' - 'a') || + id_raddr2_illegal && id_ctrl.rxs2 || + id_raddr1_illegal && id_ctrl.rxs1 || + id_waddr_illegal && id_ctrl.wxd || + id_ctrl.rocc && csr.io.decode(0).rocc_illegal || + id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) || + !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) + + val id_virtual_insn = id_ctrl.legal && + ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) || + (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) + + // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) + val id_amo_aq = id_inst(0)(26) + val id_amo_rl = id_inst(0)(25) + val id_fence_pred = id_inst(0)(27, 24) + val id_fence_succ = id_inst(0)(23, 20) + val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq + val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid + when(!id_mem_busy)(id_reg_fence := false.B) + + val id_rocc_busy = usingRoCC.B && + (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || + mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) + + val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31, 20)).orR && id_csr_en && !id_csr_ren + val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B) + + val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) || + id_vec_busy && id_ctrl.fence || + id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))) + + val bpu = Module(new BreakpointUnit(nBreakpoints)) + bpu.io.status := csr.io.status + bpu.io.bp := csr.io.bp + bpu.io.pc := ibuf.io.pc + bpu.io.ea := mem_reg_wdata + bpu.io.mcontext := csr.io.mcontext + bpu.io.scontext := csr.io.scontext + + val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 + val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 + + val (id_xcpt, id_cause) = checkExceptions(List( + (csr.io.interrupt, csr.io.interrupt_cause), + (bpu.io.debug_if, CSR.debugTriggerCause.U), + (bpu.io.xcpt_if, Causes.breakpoint.U), + (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), + (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), + (id_xcpt0.ae.inst, Causes.fetch_access.U), + (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), + (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), + (id_xcpt1.ae.inst, Causes.fetch_access.U), + (id_virtual_insn, Causes.virtual_instruction.U), + (id_illegal_insn, Causes.illegal_instruction.U) + )) + + val idCoverCauses = List( + (CSR.debugTriggerCause, "DEBUG_TRIGGER"), + (Causes.breakpoint, "BREAKPOINT"), + (Causes.fetch_access, "FETCH_ACCESS"), + (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") + ) ++ (if (usingVM) + List( + (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") + ) + else Nil) + + coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) + + val dcache_bypass_data = + if (fastLoadByte) io.dmem.resp.bits.data(xLen - 1, 0) + else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen - 1, 0) + else wb_reg_wdata + + // detect bypass opportunities + val ex_waddr = ex_reg_inst(11, 7) & regAddrMask.U + val mem_waddr = mem_reg_inst(11, 7) & regAddrMask.U + val wb_waddr = wb_reg_inst(11, 7) & regAddrMask.U + + val bypass_sources = IndexedSeq( + (true.B, 0.U, 0.U), // treat reading x0 as a bypass + (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), + (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), + (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data) + ) + + val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) + + // execute stage + val bypass_mux = bypass_sources.map(_._3) + val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) + val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) + val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) + + val ex_rs = + for (i <- 0 until id_raddr.size) + yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) + + val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) + val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31, 0), ex_rs(0)) << ex_reg_inst(14, 13) + + val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( + A1_RS1 -> ex_rs(0).asSInt, + A1_PC -> ex_reg_pc.asSInt, + A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) + )) + + val ex_op2_oh = + UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen) - 1, 0)).asSInt + + val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( + A2_RS2 -> ex_rs(1).asSInt, + A2_IMM -> ex_imm, + A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S) + ) ++ (if (coreParams.useZbs) + Seq( + A2_RS2OH -> ex_op2_oh, + A2_IMMOH -> ex_op2_oh + ) + else Nil)) + + val (ex_new_vl, ex_new_vconfig) = if (usingVector) { + val ex_new_vtype = VType.fromUInt(MuxCase( + ex_rs(1), + Seq( + ex_reg_inst(31, 30).andR -> ex_reg_inst(29, 20), + !ex_reg_inst(31) -> ex_reg_inst(30, 20) + ) + )) + val ex_avl = Mux( + ex_ctrl.rxs1, + Mux( + ex_reg_inst(19, 15) === 0.U, + Mux(ex_reg_inst(11, 7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), + ex_rs(0) + ), + ex_reg_inst(19, 15) + ) + val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) + val ex_new_vconfig = Wire(new VConfig) + ex_new_vconfig.vtype := ex_new_vtype + ex_new_vconfig.vl := ex_new_vl + (Some(ex_new_vl), Some(ex_new_vconfig)) + } else { (None, None) } + + val alu = Module(new ALU) + alu.io.dw := ex_ctrl.alu_dw + alu.io.fn := ex_ctrl.alu_fn + alu.io.in2 := ex_op2.asUInt + alu.io.in1 := ex_op1.asUInt + + // multiplier and divider + val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) + div.io.req.valid := ex_reg_valid && ex_ctrl.div + div.io.req.bits.dw := ex_ctrl.alu_dw + div.io.req.bits.fn := ex_ctrl.alu_fn + div.io.req.bits.in1 := ex_rs(0) + div.io.req.bits.in2 := ex_rs(1) + div.io.req.bits.tag := ex_waddr + + val mul = pipelinedMul.option { + val m = Module(new PipelinedMultiplier(xLen, 2)) + m.io.req.valid := ex_reg_valid && ex_ctrl.mul + m.io.req.bits := div.io.req.bits + m + } + + ex_reg_valid := !ctrl_killd + ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay + ex_reg_xcpt := !ctrl_killd && id_xcpt + ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt + + when(!ctrl_killd) { + ex_ctrl := id_ctrl + ex_reg_rvc := ibuf.io.inst(0).bits.rvc + ex_ctrl.csr := id_csr + when(id_ctrl.fence && id_fence_succ === 0.U)(id_reg_pause := true.B) + when(id_fence_next)(id_reg_fence := true.B) + when(id_xcpt) { // pass PC down ALU writeback pipeline for badaddr + ex_ctrl.alu_fn := FN_ADD + ex_ctrl.alu_dw := DW_XPR + ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction + ex_ctrl.sel_alu2 := A2_ZERO + when(id_xcpt1.asUInt.orR) { // badaddr := PC+2 + ex_ctrl.sel_alu1 := A1_PC + ex_ctrl.sel_alu2 := A2_SIZE + ex_reg_rvc := true.B + } + when(bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC + ex_ctrl.sel_alu1 := A1_PC + ex_ctrl.sel_alu2 := A2_ZERO + } + } + ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush + ex_reg_load_use := id_load_use + ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) + ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) + when(id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { + ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) + } + when(id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { + ex_ctrl.mem_cmd := M_HFENCEV + } + if (tile.dcache.flushOnFenceI) { + when(id_ctrl.fence_i) { + ex_reg_mem_size := 0.U + } + } + + for (i <- 0 until id_raddr.size) { + val do_bypass = id_bypass_src(i).reduce(_ || _) + val bypass_src = PriorityEncoder(id_bypass_src(i)) + ex_reg_rs_bypass(i) := do_bypass + ex_reg_rs_lsb(i) := bypass_src + when(id_ren(i) && !do_bypass) { + ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size) - 1, 0) + ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) + } + } + when(id_illegal_insn || id_virtual_insn) { + val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) + ex_reg_rs_bypass(0) := false.B + ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size) - 1, 0) + ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) + } + } + when(!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) { + ex_reg_cause := id_cause + ex_reg_inst := id_inst(0) + ex_reg_raw_inst := id_raw_inst(0) + ex_reg_pc := ibuf.io.pc + ex_reg_btb_resp := ibuf.io.btb_resp + ex_reg_wphit := bpu.io.bpwatch.map(bpw => bpw.ivalid(0)) + ex_reg_set_vconfig := id_set_vconfig && !id_xcpt + } + + // replay inst in ex stage? + val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt + val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid + + val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready || + ex_ctrl.div && !div.io.req.ready || + ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) + + val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use + val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use)) + val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid + // detect 2-cycle load-use delay for LB/LH/SC + val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U + val ex_sfence = + usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG) + + val (ex_xcpt, ex_cause) = checkExceptions(List( + (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause) + )) + + val exCoverCauses = idCoverCauses + coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) + + // memory stage + val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt + + val mem_br_target = mem_reg_pc.asSInt + + Mux( + mem_ctrl.branch && mem_br_taken, + ImmGen(IMM_SB, mem_reg_inst), + Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S)) + ) + + val mem_npc = (Mux( + mem_ctrl.jalr || mem_reg_sfence, + encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, + mem_br_target + ) & -2.S).asUInt + + val mem_wrong_npc = + Mux( + ex_pc_valid, + mem_npc =/= ex_reg_pc, + Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B) + ) + + val mem_npc_misaligned = !csr.io.status.isa('c' - 'a') && mem_npc(1) && !mem_reg_sfence + val mem_int_wdata = + Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt + val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal + val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal + val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) + val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken + take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence) + + mem_reg_valid := !ctrl_killx + mem_reg_replay := !take_pc_mem_wb && replay_ex + mem_reg_xcpt := !ctrl_killx && ex_xcpt + mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt + + // on pipeline flushes, cause mem_npc to hold the sequential npc, which + // will drive the W-stage npc mux + when(mem_reg_valid && mem_reg_flush_pipe) { + mem_reg_sfence := false.B + }.elsewhen(ex_pc_valid) { + mem_ctrl := ex_ctrl + mem_reg_rvc := ex_reg_rvc + mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) + mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) + mem_reg_sfence := ex_sfence + mem_reg_btb_resp := ex_reg_btb_resp + mem_reg_flush_pipe := ex_reg_flush_pipe + mem_reg_slow_bypass := ex_slow_bypass + mem_reg_wphit := ex_reg_wphit + mem_reg_set_vconfig := ex_reg_set_vconfig + + mem_reg_cause := ex_cause + mem_reg_inst := ex_reg_inst + mem_reg_raw_inst := ex_reg_raw_inst + mem_reg_mem_size := ex_reg_mem_size + mem_reg_hls_or_dv := io.dmem.req.bits.dv + mem_reg_pc := ex_reg_pc + // IDecode ensured they are 1H + mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) + mem_br_taken := alu.io.cmp_out + + when(ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { + val size = Mux(ex_ctrl.rocc, log2Ceil(xLen / 8).U, ex_reg_mem_size) + mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data + } + if (usingVector) { + when(ex_reg_set_vconfig) { + mem_reg_rs2 := ex_new_vconfig.get.asUInt + } + } + when(ex_ctrl.jalr && csr.io.status.debug) { + // flush I$ on D-mode JALR to effect uncached fetch without D$ flush + mem_ctrl.fence_i := true.B + mem_reg_flush_pipe := true.B + } + } + + val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st) + val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st) + + val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( + (mem_debug_breakpoint, CSR.debugTriggerCause.U), + (mem_breakpoint, Causes.breakpoint.U) + )) + + val (mem_xcpt, mem_cause) = checkExceptions(List( + (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), + (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), + (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause) + )) + + val memCoverCauses = (exCoverCauses ++ List( + (CSR.debugTriggerCause, "DEBUG_TRIGGER"), + (Causes.breakpoint, "BREAKPOINT"), + (Causes.misaligned_fetch, "MISALIGNED_FETCH") + )).distinct + + coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) + + val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port + val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem + val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) + val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) + val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all + val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid + div.io.kill := killm_common && RegNext(div.io.req.fire) + val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem + + // writeback stage + wb_reg_valid := !ctrl_killm + wb_reg_replay := replay_mem && !take_pc_wb + wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) + wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe + when(mem_pc_valid) { + wb_ctrl := mem_ctrl + wb_reg_sfence := mem_reg_sfence + wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) + when(mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) { + wb_reg_rs2 := mem_reg_rs2 + } + wb_reg_cause := mem_cause + wb_reg_inst := mem_reg_inst + wb_reg_raw_inst := mem_reg_raw_inst + wb_reg_mem_size := mem_reg_mem_size + wb_reg_hls_or_dv := mem_reg_hls_or_dv + wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV + wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG + wb_reg_pc := mem_reg_pc + wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => + (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) + } + wb_reg_set_vconfig := mem_reg_set_vconfig + } + + val (wb_xcpt, wb_cause) = checkExceptions(List( + (wb_reg_xcpt, wb_reg_cause), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), + (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) + )) + + val wbCoverCauses = List( + (Causes.misaligned_store, "MISALIGNED_STORE"), + (Causes.misaligned_load, "MISALIGNED_LOAD"), + (Causes.store_access, "STORE_ACCESS"), + (Causes.load_access, "LOAD_ACCESS") + ) ++ (if (usingVM) + List( + (Causes.store_page_fault, "STORE_PAGE_FAULT"), + (Causes.load_page_fault, "LOAD_PAGE_FAULT") + ) + else Nil) ++ (if (usingHypervisor) + List( + (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), + (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT") + ) + else Nil) + + coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) + + val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt + val wb_wxd = wb_reg_valid && wb_ctrl.wxd + val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec + val replay_wb_common = io.dmem.s2_nack || wb_reg_replay + val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready + val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall + val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) + val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec + take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe + + // writeback arbitration + val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool + val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool + val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) + val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data + val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay + + class LLWB extends Bundle { + val data = UInt(xLen.W) + val tag = UInt(5.W) + } + + val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec + ll_arb.io.in.foreach(_.valid := false.B) + ll_arb.io.in.foreach(_.bits := DontCare) + val ll_wdata = WireInit(ll_arb.io.out.bits.data) + val ll_waddr = WireInit(ll_arb.io.out.bits.tag) + val ll_wen = WireInit(ll_arb.io.out.fire) + ll_arb.io.out.ready := !wb_wxd + + div.io.resp.ready := ll_arb.io.in(0).ready + ll_arb.io.in(0).valid := div.io.resp.valid + ll_arb.io.in(0).bits.data := div.io.resp.bits.data + ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag + + if (usingRoCC) { + io.rocc.resp.ready := ll_arb.io.in(1).ready + ll_arb.io.in(1).valid := io.rocc.resp.valid + ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data + ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd + } else { + // tie off RoCC + io.rocc.resp.ready := false.B + io.rocc.mem.req.ready := false.B + } + + io.vector.map { v => + v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) + ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp + ll_arb.io.in(2).bits.data := v.resp.bits.data + ll_arb.io.in(2).bits.tag := v.resp.bits.rd + } + // Dont care mem since not all RoCC need accessing memory + io.rocc.mem := DontCare + + when(dmem_resp_replay && dmem_resp_xpu) { + ll_arb.io.out.ready := false.B + ll_waddr := dmem_resp_waddr + ll_wen := true.B + } + + val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt + val wb_wen = wb_valid && wb_ctrl.wxd + val rf_wen = wb_wen || ll_wen + val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) + + val rf_wdata = Mux( + dmem_resp_valid && dmem_resp_xpu, + io.dmem.resp.bits.data(xLen - 1, 0), + Mux( + ll_wen, + ll_wdata, + Mux( + wb_ctrl.csr =/= CSR.N, + csr.io.rw.rdata, + Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata) + ) + ) + ) + + when(rf_wen)(rf.write(rf_waddr, rf_wdata)) + + // hook up control/status regfile + csr.io.ungated_clock := clock + csr.io.decode(0).inst := id_inst(0) + csr.io.exception := wb_xcpt + csr.io.cause := wb_cause + csr.io.retire := wb_valid + csr.io.inst(0) := (if (usingCompressed) + Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) + else wb_reg_inst) + csr.io.interrupts := io.interrupts + csr.io.hartid := io.hartid + io.fpu.fcsr_rm := csr.io.fcsr_rm + val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) + val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) + csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid + csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill( + 5, + vector_fcsr_flags_valid + )) + io.fpu.time := csr.io.time(31, 0) + io.fpu.hartid := io.hartid + csr.io.rocc_interrupt := io.rocc.interrupt + csr.io.pc := wb_reg_pc + + val tval_dmem_addr = !wb_reg_xcpt + + val tval_any_addr = tval_dmem_addr || + wb_reg_cause.isOneOf( + Causes.breakpoint.U, + Causes.fetch_access.U, + Causes.fetch_page_fault.U, + Causes.fetch_guest_page_fault.U + ) + + val tval_inst = wb_reg_cause === Causes.illegal_instruction.U + val tval_valid = wb_xcpt && (tval_any_addr || tval_inst) + csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv) + csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) + + val (htval, mhtinst_read_pseudo) = { + val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U + val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) + assert(!htval_valid_imem || io.imem.gpa.valid) + + val htval_valid_dmem = + wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR + val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) + + val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits + // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address + // translation + val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem) + (htval, mhtinst_read_pseudo) + } + + csr.io.vector.foreach { v => + v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid + v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) + v.set_vs_dirty := wb_valid && wb_ctrl.vec + v.set_vstart.valid := wb_valid && wb_reg_set_vconfig + v.set_vstart.bits := 0.U + } + + io.vector.foreach { v => + when(v.wb.retire || v.wb.xcpt || wb_ctrl.vec) { + csr.io.pc := v.wb.pc + csr.io.retire := v.wb.retire + csr.io.inst(0) := v.wb.inst + when(v.wb.xcpt && !wb_reg_xcpt) { + wb_xcpt := true.B + wb_cause := v.wb.cause + csr.io.tval := v.wb.tval + } + } + v.wb.store_pending := io.dmem.store_pending + v.wb.vxrm := csr.io.vector.get.vxrm + v.wb.frm := csr.io.fcsr_rm + csr.io.vector.get.set_vxsat := v.set_vxsat + when(v.set_vconfig.valid) { + csr.io.vector.get.set_vconfig.valid := true.B + csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits + } + when(v.set_vstart.valid) { + csr.io.vector.get.set_vstart.valid := true.B + csr.io.vector.get.set_vstart.bits := v.set_vstart.bits + } + } + + csr.io.htval := htval + csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo + io.ptw.ptbr := csr.io.ptbr + io.ptw.hgatp := csr.io.hgatp + io.ptw.vsatp := csr.io.vsatp + (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } + io.ptw.status := csr.io.status + io.ptw.hstatus := csr.io.hstatus + io.ptw.gstatus := csr.io.gstatus + io.ptw.pmp := csr.io.pmp + csr.io.rw.addr := wb_reg_inst(31, 20) + csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) + csr.io.rw.wdata := wb_reg_wdata + + io.rocc.csrs <> csr.io.roccCSRs + io.trace.time := csr.io.time + io.trace.insns := csr.io.trace + if (rocketParams.debugROB.isDefined) { + val sz = rocketParams.debugROB.get.size + if (sz < 1) { // use unsynthesizable ROB + val csr_trace_with_wdata = WireInit(csr.io.trace(0)) + csr_trace_with_wdata.wdata.get := rf_wdata + val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) + val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) + val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) + + io.vector.foreach { v => + when(v.wb.retire) { + should_wb := v.wb.rob_should_wb + has_wb := false.B + wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11, 7)) + } + } + + DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) + + io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) + + DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) + } else { // synthesizable ROB (no FPRs) + require(!usingVector, "Synthesizable ROB does not support vector implementations") + val csr_trace_with_wdata = WireInit(csr.io.trace(0)) + csr_trace_with_wdata.wdata.get := rf_wdata + + val debug_rob = Module(new HardDebugROB(sz, 32)) + debug_rob.io.i_insn := csr_trace_with_wdata + debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && + !csr.io.trace(0).exception + debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard + debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) + + debug_rob.io.wb_val := ll_wen + debug_rob.io.wb_tag := rf_waddr + debug_rob.io.wb_data := rf_wdata + + io.trace.insns(0) := debug_rob.io.o_insn + } + } else { + io.trace.insns := csr.io.trace + } + for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { + iobpw.valid(0) := wphit + iobpw.action := bp.control.action + // tie off bpwatch valids + iobpw.rvalid.foreach(_ := false.B) + iobpw.wvalid.foreach(_ := false.B) + iobpw.ivalid.foreach(_ := false.B) + } + + val hazard_targets = Seq( + (id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), + (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), + (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr) + ) + + val fp_hazard_targets = Seq( + (io.fpu.dec.ren1, id_raddr1), + (io.fpu.dec.ren2, id_raddr2), + (io.fpu.dec.ren3, id_raddr3), + (io.fpu.dec.wen, id_waddr) + ) + + val sboard = new Scoreboard(32, true) + sboard.clear(ll_wen, ll_waddr) + + def id_sboard_clear_bypass(r: UInt) = + // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check + if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r + else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r + + val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) + sboard.set(wb_set_sboard && wb_wen, wb_waddr) + + // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. + val ex_cannot_bypass = + ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec + val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) + val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) + val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) + + // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. + val mem_mem_cmd_bh = + if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass + else true.B + + val mem_cannot_bypass = + mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec + val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) + val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) + val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem) + id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem + + val id_vconfig_hazard = id_ctrl.vec && ( + (ex_reg_valid && ex_reg_set_vconfig) || + (mem_reg_valid && mem_reg_set_vconfig) || + (wb_reg_valid && wb_reg_set_vconfig) + ) + + // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. + val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) + val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) + val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) + + val id_stall_fpu = if (usingFPU) { + val fp_sboard = new Scoreboard(32) + fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) + val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) + fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) + fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) + + checkHazards(fp_hazard_targets, fp_sboard.read _) + } else false.B + + val dcache_blocked = { + // speculate that a blocked D$ will unblock the cycle after a Grant + val blocked = Reg(Bool()) + blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack) + blocked && !io.dmem.perf.grant + } + + val rocc_blocked = Reg(Bool()) + rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked) + + val ctrl_stalld = + id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || + id_vconfig_hazard || + csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) || + id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy || + id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy || + id_ctrl.fp && id_stall_fpu || + id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses + id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy + id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay + !clock_en || + id_do_fence || io.rocc.busy || + csr.io.csr_stall || + id_reg_pause || + io.traceStall + + ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst( + 0 + ).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt + + io.imem.req.valid := take_pc + io.imem.req.bits.speculative := !take_pc_wb + io.imem.req.bits.pc := + Mux( + wb_xcpt || csr.io.eret, + csr.io.evec, // exception or [m|s]ret + Mux( + replay_wb, + wb_reg_pc, // replay + mem_npc + ) + ) // flush or branch misprediction + io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack + io.imem.might_request := { + imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map( + _.trap_check_busy + ).getOrElse(false.B) + imem_might_request_reg + } + io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) + io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence + io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) + io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) + io.imem.sfence.bits.addr := wb_reg_wdata + io.imem.sfence.bits.asid := wb_reg_rs2 + io.imem.sfence.bits.hv := wb_reg_hfence_v + io.imem.sfence.bits.hg := wb_reg_hfence_g + io.ptw.sfence := io.imem.sfence + + ibuf.io.inst(0).ready := !ctrl_stalld + + io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken) + io.imem.btb_update.bits.isValid := mem_cfi + io.imem.btb_update.bits.cfiType := + Mux( + (mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), + CFIType.call, + Mux( + mem_ctrl.jalr && (mem_reg_inst(19, 15) & regAddrMask.U) === BitPat("b00?01"), + CFIType.ret, + Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump, CFIType.branch) + ) + ) + io.imem.btb_update.bits.target := io.imem.req.bits.pc + io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) + io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes * fetchWidth - 1).U) + io.imem.btb_update.bits.prediction := mem_reg_btb_resp + io.imem.btb_update.bits.taken := DontCare + + io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb + io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc + io.imem.bht_update.bits.taken := mem_br_taken + io.imem.bht_update.bits.mispredict := mem_wrong_npc + io.imem.bht_update.bits.branch := mem_ctrl.branch + io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht + + // Connect RAS in Frontend + io.imem.ras_update := DontCare + + io.fpu.valid := !ctrl_killd && id_ctrl.fp + io.fpu.killx := ctrl_killx + io.fpu.killm := killm_common + io.fpu.inst := id_inst(0) + io.fpu.fromint_data := ex_rs(0) + io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu + io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) + io.fpu.ll_resp_type := io.dmem.resp.bits.size + io.fpu.ll_resp_tag := dmem_resp_waddr + io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate + + io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) + + io.vector.map { v => + when(!(dmem_resp_valid && dmem_resp_fpu)) { + io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp + io.fpu.ll_resp_data := v.resp.bits.data + io.fpu.ll_resp_type := v.resp.bits.size + io.fpu.ll_resp_tag := v.resp.bits.rd + } + } + + io.vector.foreach { v => + v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx + v.ex.inst := ex_reg_inst + v.ex.vconfig := csr.io.vector.get.vconfig + v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) + v.ex.rs1 := ex_rs(0) + v.ex.rs2 := ex_rs(1) + v.ex.pc := ex_reg_pc + v.mem.frs1 := io.fpu.store_data + v.killm := killm_common + v.status := csr.io.status + } + + io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem + val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) + require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) + io.dmem.req.bits.tag := ex_dcache_tag + io.dmem.req.bits.cmd := ex_ctrl.mem_cmd + io.dmem.req.bits.size := ex_reg_mem_size + io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) + io.dmem.req.bits.phys := false.B + io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) + io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) + io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) + io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv + io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U) + io.dmem.req.bits.no_alloc := DontCare + io.dmem.req.bits.no_xcpt := DontCare + io.dmem.req.bits.data := DontCare + io.dmem.req.bits.mask := DontCare + + io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 + else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) + io.dmem.s1_data.mask := DontCare + + io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem + io.dmem.s2_kill := false.B + // don't let D$ go to sleep if we're probably going to use it soon + io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall + + io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common + io.rocc.exception := wb_xcpt && csr.io.status.xs.orR + io.rocc.cmd.bits.status := csr.io.status + io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) + io.rocc.cmd.bits.rs1 := wb_reg_wdata + io.rocc.cmd.bits.rs2 := wb_reg_rs2 + + // gate the clock + val unpause = + csr.io.time(rocketParams.lgPauseCycles - 1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc + when(unpause)(id_reg_pause := false.B) + io.cease := csr.io.status.cease && !clock_en_reg + io.wfi := csr.io.status.wfi + if (rocketParams.clockGate) { + long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause + clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid) + clock_en_reg := + ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight + io.ptw.customCSRs.disableCoreClockGate || // chicken bit + !div.io.req.ready || // mul/div in flight + usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight + io.dmem.replay_next || // long-latency load replaying + (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending + + assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en) + } + + // evaluate performance counters + val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid)) + csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } + + val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) + + coreMonitorBundle.clock := clock + coreMonitorBundle.reset := reset + coreMonitorBundle.hartid := io.hartid + coreMonitorBundle.timer := csr.io.time(31, 0) + coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception + coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended - 1, 0).sextTo(xLen) + coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard + coreMonitorBundle.wrenf := false.B + coreMonitorBundle.wrdst := wb_waddr + coreMonitorBundle.wrdata := rf_wdata + coreMonitorBundle.rd0src := wb_reg_inst(19, 15) + coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) + coreMonitorBundle.rd1src := wb_reg_inst(24, 20) + coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) + coreMonitorBundle.inst := csr.io.trace(0).insn + coreMonitorBundle.excpt := csr.io.trace(0).exception + coreMonitorBundle.priv_mode := csr.io.trace(0).priv + + if (enableCommitLog) { + val t = csr.io.trace(0) + val rd = wb_waddr + val wfd = wb_ctrl.wfd + val wxd = wb_ctrl.wxd + val has_data = wb_wen && !wb_set_sboard + + when(t.valid && !t.exception) { + when(wfd) { + printf("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd + 32.U) + } + .elsewhen(wxd && rd =/= 0.U && has_data) { + printf("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) + } + .elsewhen(wxd && rd =/= 0.U && !has_data) { + printf("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) + } + .otherwise { + printf("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) + } + } + + when(ll_wen && rf_waddr =/= 0.U) { + printf("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) + } + } else { + when(csr.io.trace(0).valid) { + printf( + "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x) wb_xcpt:%d\n", + io.hartid, + coreMonitorBundle.timer, + coreMonitorBundle.valid, + coreMonitorBundle.pc, + Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), + Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), + coreMonitorBundle.wrenx, + Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), + Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), + Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), + Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), + coreMonitorBundle.inst, + coreMonitorBundle.inst, + wb_xcpt + ) + } + } + + // CoreMonitorBundle for late latency writes + val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) + + xrfWriteBundle.clock := clock + xrfWriteBundle.reset := reset + xrfWriteBundle.hartid := io.hartid + xrfWriteBundle.timer := csr.io.time(31, 0) + xrfWriteBundle.valid := false.B + xrfWriteBundle.pc := 0.U + xrfWriteBundle.wrdst := rf_waddr + xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) + xrfWriteBundle.wrenf := false.B + xrfWriteBundle.wrdata := rf_wdata + xrfWriteBundle.rd0src := 0.U + xrfWriteBundle.rd0val := 0.U + xrfWriteBundle.rd1src := 0.U + xrfWriteBundle.rd1val := 0.U + xrfWriteBundle.inst := 0.U + xrfWriteBundle.excpt := false.B + xrfWriteBundle.priv_mode := csr.io.trace(0).priv + + if (rocketParams.haveSimTimeout) + PlusArg.timeout( + name = "max_core_cycles", + docstring = "Kill the emulation after INT rdtime cycles. Off if 0." + )(csr.io.time) + + } // leaving gated-clock domain + val rocketImpl = withClock(gated_clock)(new RocketImpl) + + def checkExceptions(x: Seq[(Bool, UInt)]) = + (WireInit(x.map(_._1).reduce(_ || _)), WireInit(PriorityMux(x))) + + def coverExceptions( + exceptionValid: Bool, + cause: UInt, + labelPrefix: String, + coverCausesLabels: Seq[(Int, String)] + ): Unit = { + for ((coverCause, label) <- coverCausesLabels) { + property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_$label") + } + } + + def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = + targets.map(h => h._1 && cond(h._2)).reduce(_ || _) + + def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea + else { + // efficient means to compress 64-bit VA into vaddrBits+1 bits + // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) + val b = vaddrBitsExtended - 1 + val a = (a0 >> b).asSInt + val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b - 1)) + Cat(msb, ea(b - 1, 0)) + } + + class Scoreboard(n: Int, zero: Boolean = false) { + def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) + def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) + def read(addr: UInt): Bool = r(addr) + def readBypassed(addr: UInt): Bool = _next(addr) + + private val _r = RegInit(0.U(n.W)) + private val r = if (zero) (_r >> 1 << 1) else _r + private var _next = r + private var ens = false.B + private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) + + private def update(en: Bool, update: UInt) = { + _next = update + ens = ens || en + when(ens)(_r := _next) + } + + } + +} + +class RegFile(n: Int, w: Int, zero: Boolean = false) { + val rf = Mem(n, UInt(w.W)) + private def access(addr: UInt) = rf(~addr(log2Up(n) - 1, 0)) + private val reads = ArrayBuffer[(UInt, UInt)]() + private var canRead = true + + def read(addr: UInt) = { + require(canRead) + reads += addr -> Wire(UInt()) + reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) + reads.last._2 + } + + def write(addr: UInt, data: UInt) = { + canRead = false + when(addr =/= 0.U) { + access(addr) := data + for ((raddr, rdata) <- reads) + when(addr === raddr)(rdata := data) + } + } + +} + +object ImmGen { + + def apply(sel: UInt, inst: UInt) = { + val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) + val b30_20 = Mux(sel === IMM_U, inst(30, 20).asSInt, sign) + val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19, 12).asSInt) + val b11 = Mux( + sel === IMM_U || sel === IMM_Z, + 0.S, + Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign)) + ) + val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30, 25)) + val b4_1 = Mux( + sel === IMM_U, + 0.U, + Mux(sel === IMM_S || sel === IMM_SB, inst(11, 8), Mux(sel === IMM_Z, inst(19, 16), inst(24, 21))) + ) + val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) + + Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt + } + +} diff --git a/arch/src/main/scala/framework/rocket/RocketSubsystem.scala b/arch/src/main/scala/framework/core/rocket/RocketSubsystem.scala similarity index 58% rename from arch/src/main/scala/framework/rocket/RocketSubsystem.scala rename to arch/src/main/scala/framework/core/rocket/RocketSubsystem.scala index 6248477c..94865181 100644 --- a/arch/src/main/scala/framework/rocket/RocketSubsystem.scala +++ b/arch/src/main/scala/framework/core/rocket/RocketSubsystem.scala @@ -1,38 +1,37 @@ // See LICENSE.SiFive for license details. -package framework.rocket +package framework.core.rocket import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug.HasPeripheryDebug import freechips.rocketchip.devices.tilelink.{CanHavePeripheryCLINT, CanHavePeripheryPLIC} -import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.prci.{ClockCrossingType, NoResetCrossing, ResetCrossingType, SynchronousCrossing} import freechips.rocketchip.tile.{RocketTile, RocketTileParams} import freechips.rocketchip.util.HasCoreMonitorBundles -import framework.rocket._ +import framework.core.rocket._ // currently, this RocketCrossingParamsBB is not used, we use the default RocketCrossingParams case class RocketCrossingParamsBB( - crossingType: ClockCrossingType = SynchronousCrossing(), - master: HierarchicalElementPortParamsLike = HierarchicalElementMasterPortParams(), - slave: HierarchicalElementSlavePortParams = HierarchicalElementSlavePortParams(), + crossingType: ClockCrossingType = SynchronousCrossing(), + master: HierarchicalElementPortParamsLike = HierarchicalElementMasterPortParams(), + slave: HierarchicalElementSlavePortParams = HierarchicalElementSlavePortParams(), mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS, - resetCrossingType: ResetCrossingType = NoResetCrossing(), - forceSeparateClockReset: Boolean = false -) extends HierarchicalElementCrossingParamsLike + resetCrossingType: ResetCrossingType = NoResetCrossing(), + forceSeparateClockReset: Boolean = false) + extends HierarchicalElementCrossingParamsLike case class RocketTileAttachParams( - tileParams: RocketTileParams, - crossingParams: RocketCrossingParams -) extends CanAttachTile { type TileType = RocketTile } - + tileParams: RocketTileParams, + crossingParams: RocketCrossingParams) + extends CanAttachTile { type TileType = RocketTile } case class RocketTileAttachParamsBB( - tileParams: RocketTileParamsBB, - crossingParams: RocketCrossingParams -) extends CanAttachTile { type TileType = RocketTileBB } + tileParams: RocketTileParamsBB, + crossingParams: RocketCrossingParams) + extends CanAttachTile { type TileType = RocketTileBB } trait HasRocketTiles { this: BaseSubsystem with InstantiatesHierarchicalElements => @@ -41,9 +40,11 @@ trait HasRocketTiles { def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle }).toList + } -class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem +class RocketSubsystem(implicit p: Parameters) + extends BaseSubsystem with InstantiatesHierarchicalElements with HasTileNotificationSinks with HasTileInputConstants @@ -53,12 +54,12 @@ class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem with HasHierarchicalElementsRootContext with HasHierarchicalElements with HasCoreMonitorBundles - with HasRocketTiles -{ + with HasRocketTiles { override lazy val module = new RocketSubsystemModuleImp(this) } -class RocketSubsystemModuleImp[+L <: RocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) +class RocketSubsystemModuleImp[+L <: RocketSubsystem](_outer: L) + extends BaseSubsystemModuleImp(_outer) with HasHierarchicalElementsRootContextModuleImp { override lazy val outer = _outer } diff --git a/arch/src/main/scala/framework/rocket/RocketTileBB.scala b/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala similarity index 55% rename from arch/src/main/scala/framework/rocket/RocketTileBB.scala rename to arch/src/main/scala/framework/core/rocket/RocketTileBB.scala index 26764db9..856bbc91 100644 --- a/arch/src/main/scala/framework/rocket/RocketTileBB.scala +++ b/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala @@ -1,7 +1,7 @@ // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. -package framework.rocket +package framework.core.rocket import chisel3._ @@ -10,22 +10,32 @@ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ -import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} -import freechips.rocketchip.diplomacy.{ - AddressSet, DisableMonitors, BufferParams -} +import freechips.rocketchip.devices.tilelink.{BasicBusBlocker, BasicBusBlockerParams} +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, DisableMonitors} import freechips.rocketchip.resources.{ - SimpleDevice, Description, - ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, + Description, + Resource, + ResourceAddress, + ResourceAnchors, + ResourceBinding, + ResourceBindings, + SimpleDevice } import freechips.rocketchip.interrupts.IntIdentityNode -import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} +import freechips.rocketchip.tilelink.{TLBuffer, TLIdentityNode} import freechips.rocketchip.rocket.{ - RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, - HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket + BTBParams, + DCacheParams, + HasHellaCache, + HasICacheFrontend, + HasICacheFrontendModule, + ICacheParams, + Rocket, + RocketCoreParams, + ScratchpadSlavePort } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike -import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} +import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters, RationalCrossing} import freechips.rocketchip.util.{Annotated, InOrderArbiter} import freechips.rocketchip.util.BooleanToAugmentedBoolean @@ -33,55 +43,72 @@ import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) case class RocketTileParamsBB( - core: RocketCoreParams = RocketCoreParams(), - icache: Option[ICacheParams] = Some(ICacheParams()), - dcache: Option[DCacheParams] = Some(DCacheParams()), - btb: Option[BTBParams] = Some(BTBParams()), - dataScratchpadBytes: Int = 0, - tileId: Int = 0, - beuAddr: Option[BigInt] = None, - blockerCtrlAddr: Option[BigInt] = None, - clockSinkParams: ClockSinkParameters = ClockSinkParameters(), - boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None, - - usingRVVRoCC: Boolean = false - ) extends InstantiableTileParams[RocketTileBB] { + core: RocketCoreParams = RocketCoreParams(), + icache: Option[ICacheParams] = Some(ICacheParams()), + dcache: Option[DCacheParams] = Some(DCacheParams()), + btb: Option[BTBParams] = Some(BTBParams()), + dataScratchpadBytes: Int = 0, + tileId: Int = 0, + beuAddr: Option[BigInt] = None, + blockerCtrlAddr: Option[BigInt] = None, + clockSinkParams: ClockSinkParameters = ClockSinkParameters(), + boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None, + usingRVVRoCC: Boolean = false) + extends InstantiableTileParams[RocketTileBB] { require(icache.isDefined) require(dcache.isDefined) - val baseName = "rockettile" + val baseName = "rockettile" val uniqueName = s"${baseName}_$tileId" - def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTileBB = { + + def instantiate( + crossing: HierarchicalElementCrossingParamsLike, + lookup: LookupByHartIdImpl + )( + implicit p: Parameters + ): RocketTileBB = new RocketTileBB(this, crossing, lookup) - } + } -class RocketTileBB private( - val rocketParams: RocketTileParamsBB, - crossing: ClockCrossingType, - lookup: LookupByHartIdImpl, - q: Parameters) +class RocketTileBB private ( + val rocketParams: RocketTileParamsBB, + crossing: ClockCrossingType, + lookup: LookupByHartIdImpl, + q: Parameters) extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications - with HasLazyRoCC // Use standard HasLazyRoCC instead of HasLazyRoCCBB + with HasLazyRoCC // Use standard HasLazyRoCC instead of HasLazyRoCCBB with HasHellaCache - with HasICacheFrontend -{ + with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly - def this(params: RocketTileParamsBB, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + def this( + params: RocketTileParamsBB, + crossing: HierarchicalElementCrossingParamsLike, + lookup: LookupByHartIdImpl + )( + implicit p: Parameters + ) = this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } - val slaveNode = TLIdentityNode() - val masterNode = visibilityNode + val slaveNode = TLIdentityNode() + val masterNode = visibilityNode + + val dtim_adapter = rocketParams.dcache.flatMap { d => + d.scratch.map { s => + LazyModule(new ScratchpadSlavePort( + AddressSet.misaligned(s, d.dataScratchpadBytes), + lazyCoreParamsView.coreDataBytes, + rocketParams.core.useAtomics && !rocketParams.core.useAtomicsOnlyForIO + )) + } + } - val dtim_adapter = rocketParams.dcache.flatMap { d => d.scratch.map { s => - LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, rocketParams.core.useAtomics && !rocketParams.core.useAtomicsOnlyForIO)) - }} dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => - val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) + val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen / 8)) intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu @@ -95,56 +122,74 @@ class RocketTileBB private( tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // TODO: this doesn't block other masters, e.g. RoCCs - tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } + tlOtherMastersNode := tile_master_blocker.map(_.node := tlMasterXbar.node) getOrElse { tlMasterXbar.node } masterNode :=* tlOtherMastersNode - DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode } + DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) - nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) + nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map( + _.useDCache.toInt + ).getOrElse(0) - val dtimProperty = dtim_adapter.map(d => Map( - "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) + val dtimProperty = dtim_adapter.map(d => + Map( + "sifive,dtim" -> d.device.asProperty + ) + ).getOrElse(Nil) val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) - val beuProperty = bus_error_unit.map(d => Map( - "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) + val beuProperty = bus_error_unit.map(d => + Map( + "sifive,buserror" -> d.device.asProperty + ) + ).getOrElse(Nil) val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { override def parent = Some(ResourceAnchors.cpus) + override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) - Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty - ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty) + Description( + name, + mapping ++ cpuProperties ++ nextLevelCacheProperty + ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty + ) } + } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) vector_unit.foreach(vu => tlMasterXbar.node :=* vu.atlNode) vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) - ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(rocketParams.tileId)) } override lazy val module = new RocketTileModuleImpBB(this) - override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { - case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() - case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) - case _ => TLBuffer(BufferParams.none) - } + override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = + (rocketParams.boundaryBuffers, crossing) match { + case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer() + case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => + TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) + case _ => TLBuffer(BufferParams.none) + } + + override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = + (rocketParams.boundaryBuffers, crossing) match { + case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer() + case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => + TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) + case _ => TLBuffer(BufferParams.none) + } - override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { - case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() - case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) - case _ => TLBuffer(BufferParams.none) - } } -class RocketTileModuleImpBB(outer: RocketTileBB) extends BaseTileModuleImp(outer) +class RocketTileModuleImpBB(outer: RocketTileBB) + extends BaseTileModuleImp(outer) with HasFpuOptBB - with HasLazyRoCCModuleBB // Use HasLazyRoCCModuleBB but with standard RoCC types + with HasLazyRoCCModuleBB // Use HasLazyRoCCModuleBB but with standard RoCC types with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) @@ -173,9 +218,10 @@ class RocketTileModuleImpBB(outer: RocketTileBB) extends BaseTileModuleImp(outer // Report when the tile has ceased to retire instructions; for now the only cause is clock gating outer.reportCease(outer.rocketParams.core.clockGate.option( !outer.dcache.module.io.cpu.clock_enabled && - !outer.frontend.module.io.cpu.clock_enabled && - !ptw.io.dpath.clock_enabled && - core.io.cease)) + !outer.frontend.module.io.cpu.clock_enabled && + !ptw.io.dpath.clock_enabled && + core.io.cease + )) outer.reportWFI(Some(core.io.wfi)) @@ -183,19 +229,21 @@ class RocketTileModuleImpBB(outer: RocketTileBB) extends BaseTileModuleImp(outer outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt - beu.module.io.errors.dcache := outer.dcache.module.io.errors - beu.module.io.errors.icache := outer.frontend.module.io.errors + beu.module.io.errors.dcache := outer.dcache.module.io.errors + beu.module.io.errors.icache := outer.frontend.module.io.errors } - core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } + core.io.interrupts.nmi.foreach(nmi => nmi := outer.nmiSinkNode.get.bundle) // Pass through various external constants and reports that were bundle-bridged into the tile outer.traceSourceNode.bundle <> core.io.trace core.io.traceStall := outer.traceAuxSinkNode.bundle.stall outer.bpwatchSourceNode.bundle <> core.io.bpwatch - core.io.hartid := outer.hartIdSinkNode.bundle - require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, - s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)") + core.io.hartid := outer.hartIdSinkNode.bundle + require( + core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, + s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)" + ) // Connect the core pipeline to other intra-tile modules outer.frontend.module.io.cpu <> core.io.imem @@ -206,40 +254,42 @@ class RocketTileModuleImpBB(outer: RocketTileBB) extends BaseTileModuleImp(outer if (fpuOpt.isEmpty) { core.io.fpu := DontCare } - outer.vector_unit foreach { v => if (outer.rocketParams.core.vector.get.useDCache) { - dcachePorts += v.module.io.dmem - } else { - v.module.io.dmem := DontCare - } } + outer.vector_unit foreach { v => + if (outer.rocketParams.core.vector.get.useDCache) { + dcachePorts += v.module.io.dmem + } else { + v.module.io.dmem := DontCare + } + } core.io.ptw <> ptw.io.dpath // Connect the coprocessor interfaces if (outer.roccs.size > 0) { cmdRouter.get.io.in <> core.io.rocc.cmd - outer.roccs.foreach{ lm => - lm.module.io.exception := core.io.rocc.exception - lm.module.io.fpu_req.ready := DontCare - lm.module.io.fpu_resp.valid := DontCare + outer.roccs.foreach { lm => + lm.module.io.exception := core.io.rocc.exception + lm.module.io.fpu_req.ready := DontCare + lm.module.io.fpu_resp.valid := DontCare lm.module.io.fpu_resp.bits.data := DontCare - lm.module.io.fpu_resp.bits.exc := DontCare + lm.module.io.fpu_resp.bits.exc := DontCare } core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _) - (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } + (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach(t => t._2 <> t._1) } else { // tie off - core.io.rocc.cmd.ready := false.B + core.io.rocc.cmd.ready := false.B core.io.rocc.resp.valid := false.B - core.io.rocc.resp.bits := DontCare - core.io.rocc.busy := DontCare - core.io.rocc.interrupt := DontCare + core.io.rocc.resp.bits := DontCare + core.io.rocc.busy := DontCare + core.io.rocc.interrupt := DontCare } // Dont care mem since not all RoCC need accessing memory core.io.rocc.mem := DontCare // Rocket has higher priority to DTIM than other TileLink clients - outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } + outer.dtim_adapter.foreach(lm => dcachePorts += lm.module.io.dmem) // TODO eliminate this redundancy val h = dcachePorts.size @@ -256,7 +306,7 @@ trait HasFpuOptBB { this: RocketTileModuleImpBB => val fpuOpt = outer.rocketParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) fpuOpt.foreach { fpu => val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) - val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt + val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt if (nFPUPorts > 0) { val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) fpu.io.cp_req <> fpArb.io.out_req @@ -267,13 +317,13 @@ trait HasFpuOptBB { this: RocketTileModuleImpBB => fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) } - outer.vector_unit.foreach(vu => { + outer.vector_unit.foreach { vu => fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) - }) + } } else { - fpu.io.cp_req.valid := false.B - fpu.io.cp_req.bits := DontCare + fpu.io.cp_req.valid := false.B + fpu.io.cp_req.bits := DontCare fpu.io.cp_resp.ready := false.B } } diff --git a/arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala b/arch/src/main/scala/framework/core/rocket/id/RVVRoCCDecode.scala similarity index 71% rename from arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala rename to arch/src/main/scala/framework/core/rocket/id/RVVRoCCDecode.scala index b6f91ed4..fe8dda6a 100644 --- a/arch/src/main/scala/framework/rocket/id/RVVRoCCDecode.scala +++ b/arch/src/main/scala/framework/core/rocket/id/RVVRoCCDecode.scala @@ -1,7 +1,7 @@ // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. -package framework.rocket.id +package framework.core.rocket.id import chisel3._ import chisel3.util._ @@ -33,17 +33,19 @@ import freechips.rocketchip.util._ * Note: This decoder uses wildcard patterns that may match invalid encodings. * The RoCC accelerator should validate instructions and handle illegal opcodes appropriately. */ -class RVVRoCCDecode(implicit val p: Parameters) extends DecodeConstants with ScalarOpConstants with MemoryOpConstants -{ +class RVVRoCCDecode(implicit val p: Parameters) extends DecodeConstants with ScalarOpConstants with MemoryOpConstants { import freechips.rocketchip.rocket.Instructions._ // Common decode signals for RVV instructions (rocc field set to Y) // Most RVV instructions don't read scalar registers by default (overridden by specific patterns) - private val rvvRoCCBase: List[BitPat] = List(Y,N,Y,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N) + private val rvvRoCCBase: List[BitPat] = + List(Y, N, Y, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR.N, N, N, N, N) // Vector configuration instructions need wxd=Y and may read rs1 - private val vcfgSigs: List[BitPat] = List(Y,N,Y,N,N,N,N,Y,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N) - private val vcfgImmSigs: List[BitPat] = List(Y,N,Y,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N) + private val vcfgSigs: List[BitPat] = + List(Y, N, Y, N, N, N, N, Y, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, Y, CSR.N, N, N, N, N) + private val vcfgImmSigs: List[BitPat] = + List(Y, N, Y, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, Y, CSR.N, N, N, N, N) val table: Array[(BitPat, List[BitPat])] = Array( // All V-type instructions (opcode = 1010111) @@ -52,24 +54,23 @@ class RVVRoCCDecode(implicit val p: Parameters) extends DecodeConstants with Sca // decode signals here to avoid pattern overlap issues. The RoCC accelerator should // handle the detailed decoding of vset instructions. BitPat("b?????????????????????????????????1010111") -> rvvRoCCBase, - // Vector load instructions (opcode = 0000111, funct3 = 000/101/110/111) // funct3=101: VLE16, VLE256, etc. // funct3=110: VLE32, VLE512, etc. // funct3=111: VLE64, VLE1024, etc. - BitPat("b?????????????????000?????0000111") -> rvvRoCCBase, - BitPat("b?????????????????101?????0000111") -> rvvRoCCBase, - BitPat("b?????????????????110?????0000111") -> rvvRoCCBase, - BitPat("b?????????????????111?????0000111") -> rvvRoCCBase, - + BitPat("b?????????????????000?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????101?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????110?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????111?????0000111") -> rvvRoCCBase, // Vector store instructions (opcode = 0100111, but NOT funct3=010 which is FP store) // funct3=000: VSE8, VSE128, VS*R, etc. // funct3=101: VSE16, VSE256, etc. // funct3=110: VSE32, VSE512, etc. // funct3=111: VSE64, VSE1024, etc. - BitPat("b?????????????????000?????0100111") -> rvvRoCCBase, - BitPat("b?????????????????101?????0100111") -> rvvRoCCBase, - BitPat("b?????????????????110?????0100111") -> rvvRoCCBase, - BitPat("b?????????????????111?????0100111") -> rvvRoCCBase + BitPat("b?????????????????000?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????101?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????110?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????111?????0100111") -> rvvRoCCBase ) + } diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala new file mode 100644 index 00000000..819080d6 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -0,0 +1,80 @@ +package framework.frontend + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile.RoCCCommand +import freechips.rocketchip.tile.RoCCResponse +import framework.frontend.decoder.{GlobalDecoder, PostGDCmd} +import framework.frontend.globalrs.{ + GlobalReservationStation, + GlobalReservationStationParam, + GlobalRsComplete, + GlobalRsIssue +} +import framework.frontend.FrontendParam + +/** + * Frontend Module + * Encapsulates GlobalDecoder and GlobalReservationStation + */ +@instantiable +class Frontend(val parameter: FrontendParam)(implicit p: Parameters) + extends Module + with SerializableModule[FrontendParam] { + + @public + val io = IO(new Bundle { + + // RoCC command input + val cmd = Flipped(Decoupled(new Bundle { + val cmd = new RoCCCommand + })) + + // Issue to domains + val ball_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)(p)) + val mem_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)(p)) + val gp_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)(p)) + + // Complete from domains + val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries)(p))) + val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries)(p))) + val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries)(p))) + + // RoCC response + val resp = Decoupled(new RoCCResponse) + val busy = Output(Bool()) + }) + + // Instantiate GlobalDecoder + val gDecoder: Instance[GlobalDecoder] = Instantiate(new GlobalDecoder(parameter)) + gDecoder.io.id_i.valid := io.cmd.valid + gDecoder.io.id_i.bits.cmd := io.cmd.bits.cmd + io.cmd.ready := gDecoder.io.id_i.ready + + // Instantiate GlobalReservationStation + val globalRsParam = GlobalReservationStationParam( + rob_entries = parameter.rob_entries, + rs_out_of_order_response = parameter.rs_out_of_order_response + ) + + val globalRs: Instance[GlobalReservationStation] = Instantiate(new GlobalReservationStation(globalRsParam)(p)) + globalRs.io.global_decode_cmd_i <> gDecoder.io.id_o + + // Connect to domains + io.ball_issue_o <> globalRs.io.ball_issue_o + io.mem_issue_o <> globalRs.io.mem_issue_o + io.gp_issue_o <> globalRs.io.gp_issue_o + + globalRs.io.ball_complete_i <> io.ball_complete_i + globalRs.io.mem_complete_i <> io.mem_complete_i + globalRs.io.gp_complete_i <> io.gp_complete_i + + // RoCC response + io.resp <> globalRs.io.rs_rocc_o.resp + io.busy := globalRs.io.rs_rocc_o.busy + + override lazy val desiredName = "Frontend" +} diff --git a/arch/src/main/scala/framework/frontend/FrontendParam.scala b/arch/src/main/scala/framework/frontend/FrontendParam.scala new file mode 100644 index 00000000..64adcdc2 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/FrontendParam.scala @@ -0,0 +1,8 @@ +package framework.frontend + +import chisel3.experimental.{SerializableModuleParameter} + +case class FrontendParam( + rob_entries: Int, + rs_out_of_order_response: Boolean) + extends SerializableModuleParameter diff --git a/arch/src/main/scala/framework/frontend/decoder/GISA.scala b/arch/src/main/scala/framework/frontend/decoder/GISA.scala index 8878a42c..d71906d3 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GISA.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GISA.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ object GISA { - val FENCE_BITPAT = BitPat("b0011111") // 31 (0x1F) + val FENCE_BITPAT = BitPat("b0011111") // 31 (0x1F) } // Domain ID constants diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index d410f6e1..191ff1e0 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -3,51 +3,71 @@ package framework.frontend.decoder import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import freechips.rocketchip.tile._ import framework.frontend.decoder.GISA._ -import framework.memdomain.DISA._ +import framework.memdomain.frontend.cmd_channel.decoder.DISA._ import framework.gpdomain.sequencer.decoder.DISA._ +import framework.frontend.FrontendParam class BuckyballRawCmd(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand } -class PostGDCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val domain_id = UInt(4.W) - val raw_cmd = new RoCCCommand +class PostGDCmd(implicit p: Parameters) extends Bundle { + val domain_id = UInt(4.W) + val raw_cmd = new RoCCCommand } -class GlobalDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class GlobalDecoder(val parameter: FrontendParam)(implicit p: Parameters) + extends Module + with SerializableModule[FrontendParam] { + + @public val io = IO(new Bundle { + val id_i = Flipped(Decoupled(new Bundle { val cmd = new RoCCCommand })) + val id_o = Decoupled(new PostGDCmd) }) // If reservation station is blocked, id_i is also blocked io.id_i.ready := io.id_o.ready - val func7 = io.id_i.bits.cmd.inst.funct + val func7 = io.id_i.bits.cmd.inst.funct val opcode = io.id_i.bits.cmd.inst.opcode // Instruction type determination: distinguish Ball, Mem, Fence, GP (RVV) instructions - val is_mem_inst = (func7 === MVIN_BITPAT) || (func7 === MVOUT_BITPAT) - val is_frontend_inst = (func7 === FENCE_BITPAT) + val is_mem_inst = (func7 === MVIN_BITPAT) || + (func7 === MVOUT_BITPAT) || + (func7 === MSET_BITPAT) + + val is_frontend_inst = func7 === FENCE_BITPAT + // RVV instructions: opcode 0x57 (vector compute), 0x07 (vector load), 0x27 (vector store) - val is_gp_inst = (opcode === RVV_OPCODE_V) || (opcode === RVV_OPCODE_VL) || (opcode === RVV_OPCODE_VS) - val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_gp_inst + val is_gp_inst = (opcode === RVV_OPCODE_V) || + (opcode === RVV_OPCODE_VL) || + (opcode === RVV_OPCODE_VS) + + val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_gp_inst // Encode domain ID - val domain_id = MuxCase(DomainId.BALL, Seq( - is_frontend_inst -> DomainId.FRONTEND, - is_mem_inst -> DomainId.MEM, - is_gp_inst -> DomainId.GP, - is_ball_inst -> DomainId.BALL - )) + val domain_id = MuxCase( + DomainId.BALL, + Seq( + is_frontend_inst -> DomainId.FRONTEND, + is_mem_inst -> DomainId.MEM, + is_gp_inst -> DomainId.GP, + is_ball_inst -> DomainId.BALL + ) + ) // Output control io.id_o.valid := io.id_i.valid diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index ec719cad..4964bcb3 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -3,56 +3,64 @@ package framework.frontend.globalrs import chisel3._ import chisel3.util._ import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.frontend.decoder.PostGDCmd +import framework.frontend.FrontendParam -class GlobalROB(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) + extends Module + with SerializableModule[FrontendParam] { + + @public val io = IO(new Bundle { // Allocation interface val alloc = Flipped(new DecoupledIO(new PostGDCmd)) // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new GlobalRobEntry) + val issue = new DecoupledIO(new GlobalRobEntry(parameter.rob_entries)) // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(b.rob_entries).W))) + val complete = Flipped(new DecoupledIO(UInt(log2Up(parameter.rob_entries).W))) // Status signals - exposed to reservation station for decision making - val empty = Output(Bool()) - val full = Output(Bool()) + val empty = Output(Bool()) + val full = Output(Bool()) // head pointer position - val head_ptr = Output(UInt(log2Up(b.rob_entries).W)) + val head_ptr = Output(UInt(log2Up(parameter.rob_entries).W)) // Number of issued but uncompleted instructions - val issued_count = Output(UInt(log2Up(b.rob_entries + 1).W)) + val issued_count = Output(UInt(log2Up(parameter.rob_entries + 1).W)) // Whether each entry is valid - val entry_valid = Output(Vec(b.rob_entries, Bool())) + val entry_valid = Output(Vec(parameter.rob_entries, Bool())) // Whether each entry is complete - val entry_complete = Output(Vec(b.rob_entries, Bool())) + val entry_complete = Output(Vec(parameter.rob_entries, Bool())) }) // Circular ROB structure - // Initialize to zero to avoid X states in FPGA (critical for FireSim) - val robEntries = RegInit(VecInit(Seq.fill(b.rob_entries)(0.U.asTypeOf(new GlobalRobEntry)))) + val robEntries = + RegInit(VecInit(Seq.fill(parameter.rob_entries)(0.U.asTypeOf(new GlobalRobEntry(parameter.rob_entries))))) // Whether entry is valid - val robValid = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robValid = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Whether entry is issued - val robIssued = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Whether entry is complete - val robComplete = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Circular queue pointers // Points to oldest uncommitted instruction - val headPtr = RegInit(0.U(log2Up(b.rob_entries).W)) + val headPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) // Points to next position to allocate - val tailPtr = RegInit(0.U(log2Up(b.rob_entries).W)) + val tailPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) // ROB ID circular counter - val robIdCounter = RegInit(0.U(log2Up(b.rob_entries).W)) + val robIdCounter = RegInit(0.U(log2Up(parameter.rob_entries).W)) // Number of issued but uncompleted instructions (used to limit issue) - val issuedCount = RegInit(0.U(log2Up(b.rob_entries + 1).W)) + val issuedCount = RegInit(0.U(log2Up(parameter.rob_entries + 1).W)) // Maximum issue limit: half of ROB depth - val maxIssueLimit = (b.rob_entries / 2).U + val maxIssueLimit = (parameter.rob_entries / 2).U // Queue status val isEmpty = headPtr === tailPtr && !robValid(headPtr) @@ -66,13 +74,13 @@ class GlobalROB(implicit b: CustomBuckyballConfig, p: Parameters) extends Module when(io.alloc.fire) { robEntries(tailPtr).cmd := io.alloc.bits robEntries(tailPtr).rob_id := robIdCounter - robValid(tailPtr) := true.B - robIssued(tailPtr) := false.B - robComplete(tailPtr) := false.B + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B // Update tail pointer and rob_id counter (circular) - tailPtr := Mux(tailPtr === (b.rob_entries - 1).U, 0.U, tailPtr + 1.U) - robIdCounter := Mux(robIdCounter === (b.rob_entries - 1).U, 0.U, robIdCounter + 1.U) + tailPtr := Mux(tailPtr === (parameter.rob_entries - 1).U, 0.U, tailPtr + 1.U) + robIdCounter := Mux(robIdCounter === (parameter.rob_entries - 1).U, 0.U, robIdCounter + 1.U) } // ----------------------------------------------------------------------------- @@ -93,28 +101,28 @@ class GlobalROB(implicit b: CustomBuckyballConfig, p: Parameters) extends Module // ----------------------------------------------------------------------------- // Find first valid and unissued instruction starting from head val canIssue = Wire(Bool()) - val issuePtr = Wire(UInt(log2Up(b.rob_entries).W)) + val issuePtr = Wire(UInt(log2Up(parameter.rob_entries).W)) // Default values canIssue := false.B issuePtr := headPtr // Scan from head to find first issuable instruction - val scanValid = Wire(Vec(b.rob_entries, Bool())) - for (i <- 0 until b.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.rob_entries.U, - headPtr + i.U - b.rob_entries.U, - headPtr + i.U) + val scanValid = Wire(Vec(parameter.rob_entries, Bool())) + for (i <- 0 until parameter.rob_entries) { + val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) } // Find first issuable position val firstValid = PriorityEncoder(scanValid.asUInt) - val hasValid = scanValid.asUInt.orR + val hasValid = scanValid.asUInt.orR - val actualIssuePtr = Mux(headPtr + firstValid >= b.rob_entries.U, - headPtr + firstValid - b.rob_entries.U, - headPtr + firstValid) + val actualIssuePtr = Mux( + headPtr + firstValid >= parameter.rob_entries.U, + headPtr + firstValid - parameter.rob_entries.U, + headPtr + firstValid + ) // Can only issue if issue limit is not reached val canIssueMore = issuedCount < maxIssueLimit @@ -126,37 +134,38 @@ class GlobalROB(implicit b: CustomBuckyballConfig, p: Parameters) extends Module when(io.issue.fire) { robIssued(issuePtr) := true.B - issuedCount := issuedCount + 1.U + issuedCount := issuedCount + 1.U } // ----------------------------------------------------------------------------- // Instruction commit - commit all completed instructions out-of-order // ----------------------------------------------------------------------------- // Commit all completed instructions - for (i <- 0 until b.rob_entries) { + for (i <- 0 until parameter.rob_entries) { when(robValid(i.U) && robComplete(i.U)) { - robValid(i.U) := false.B - robIssued(i.U) := false.B + robValid(i.U) := false.B + robIssued(i.U) := false.B robComplete(i.U) := false.B } } // Update head pointer: skip all completed (about to be cleared) positions // Find first "valid and incomplete" instruction position starting from head - val nextHeadCandidates = Wire(Vec(b.rob_entries, Bool())) - for (i <- 0 until b.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.rob_entries.U, - headPtr + i.U - b.rob_entries.U, - headPtr + i.U) + val nextHeadCandidates = Wire(Vec(parameter.rob_entries, Bool())) + for (i <- 0 until parameter.rob_entries) { + val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) // Entry is valid and incomplete (will not be committed) nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) } val hasUncommitted = nextHeadCandidates.asUInt.orR val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) - val nextHeadPtr = Mux(headPtr + nextHeadOffset >= b.rob_entries.U, - headPtr + nextHeadOffset - b.rob_entries.U, - headPtr + nextHeadOffset) + + val nextHeadPtr = Mux( + headPtr + nextHeadOffset >= parameter.rob_entries.U, + headPtr + nextHeadOffset - parameter.rob_entries.U, + headPtr + nextHeadOffset + ) // Update head pointer: // - If there are uncompleted instructions, move head to first uncompleted position @@ -166,10 +175,10 @@ class GlobalROB(implicit b: CustomBuckyballConfig, p: Parameters) extends Module // ----------------------------------------------------------------------------- // Status signals - exposed to reservation station // ----------------------------------------------------------------------------- - io.empty := isEmpty - io.full := isFull - io.head_ptr := headPtr - io.issued_count := issuedCount - io.entry_valid := robValid + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid io.entry_complete := robComplete } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 853bc2e4..265fd915 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -3,75 +3,90 @@ package framework.frontend.globalrs import chisel3._ import chisel3.util._ import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.frontend.decoder.{PostGDCmd, DomainId} +import framework.frontend.decoder.{DomainId, PostGDCmd} import framework.frontend.decoder.GISA._ import freechips.rocketchip.tile.RoCCResponse // Global ROB entry - only contains basic information, does not include specific instruction decoding -class GlobalRobEntry(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { +class GlobalRobEntry(rob_entries: Int)(implicit p: Parameters) extends Bundle { val cmd = new PostGDCmd - val rob_id = UInt(log2Up(b.rob_entries).W) + val rob_id = UInt(log2Up(rob_entries).W) } // Global RS issue interface -class GlobalRsIssue(implicit b: CustomBuckyballConfig, p: Parameters) extends GlobalRobEntry +class GlobalRsIssue(rob_entries: Int)(implicit p: Parameters) extends GlobalRobEntry(rob_entries) // Global RS completion interface -class GlobalRsComplete(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val rob_id = UInt(log2Up(b.rob_entries).W) +class GlobalRsComplete(rob_entries: Int)(implicit p: Parameters) extends Bundle { + val rob_id = UInt(log2Up(rob_entries).W) } // No additional interface Bundle needed, defined directly in IO +case class GlobalReservationStationParam( + rob_entries: Int, + rs_out_of_order_response: Boolean) + extends SerializableModuleParameter + // Global reservation station - between GlobalDecoder and each Domain -class GlobalReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class GlobalReservationStation(val parameter: GlobalReservationStationParam)(implicit p: Parameters) + extends Module + with SerializableModule[GlobalReservationStationParam] { + + @public val io = IO(new Bundle { // GlobalDecoder -> Global RS val global_decode_cmd_i = Flipped(new DecoupledIO(new PostGDCmd)) - - // Global RS -> BallDomain (single channel) - val ball_issue_o = Decoupled(new GlobalRsIssue) - - // Global RS -> MemDomain (single channel) - val mem_issue_o = Decoupled(new GlobalRsIssue) - - // Global RS -> GpDomain (single channel) - val gp_issue_o = Decoupled(new GlobalRsIssue) - - // BallDomain -> Global RS (single channel) - val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete)) - - // MemDomain -> Global RS (single channel) - val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete)) - - // GpDomain -> Global RS (single channel) - val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete)) + // Global RS -> BallDomain + // -> MemDomain + // -> GpDomain + val ball_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)) + val mem_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)) + val gp_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)) + // BallDomain -> Global RS + // MemDomain -> + // GpDomain -> + val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries))) + val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries))) + val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries))) // RoCC response val rs_rocc_o = new Bundle { - val resp = new DecoupledIO(new RoCCResponse()(p)) - val busy = Output(Bool()) + val resp = new DecoupledIO(new RoCCResponse) + val busy = Output(Bool()) } + }) - val rob = Module(new GlobalROB) + // Convert GlobalReservationStationParam to FrontendParam for GlobalROB + import framework.frontend.FrontendParam + + val frontendParam = FrontendParam( + rob_entries = parameter.rob_entries, + rs_out_of_order_response = parameter.rs_out_of_order_response + ) + + val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(frontendParam)) // ----------------------------------------------------------------------------- // Fence handling - fence instructions require ROB to be empty before execution // ----------------------------------------------------------------------------- val fenceActive = RegInit(false.B) // Cannot use fire, would form a loop - val func7 = io.global_decode_cmd_i.bits.raw_cmd.inst.funct - val isFenceCmd = io.global_decode_cmd_i.valid && (func7 === FENCE_BITPAT) - val robEmpty = rob.io.empty + val func7 = io.global_decode_cmd_i.bits.raw_cmd.inst.funct + val isFenceCmd = io.global_decode_cmd_i.valid && (func7 === FENCE_BITPAT) + val robEmpty = rob.io.empty // Fence state machine: only activate when fence instruction is accepted (fire) - when (io.global_decode_cmd_i.fire && isFenceCmd && !fenceActive) { + when(io.global_decode_cmd_i.fire && isFenceCmd && !fenceActive) { fenceActive := true.B } - when (fenceActive && robEmpty) { + when(fenceActive && robEmpty) { fenceActive := false.B } @@ -109,36 +124,36 @@ class GlobalReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) // Set ROB ready signal - can only issue when target domain is ready rob.io.issue.ready := (is_ball_domain && io.ball_issue_o.ready) || - (is_mem_domain && io.mem_issue_o.ready) || - (is_gp_domain && io.gp_issue_o.ready) + (is_mem_domain && io.mem_issue_o.ready) || + (is_gp_domain && io.gp_issue_o.ready) // ----------------------------------------------------------------------------- // Completion signal processing // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.rob_entries).W), 3)) + val completeArb = Module(new Arbiter(UInt(log2Up(parameter.rob_entries).W), 3)) // Connect Ball, Mem, and GP domain completion signals to arbiter completeArb.io.in(0).valid := io.ball_complete_i.valid completeArb.io.in(0).bits := io.ball_complete_i.bits.rob_id - io.ball_complete_i.ready := completeArb.io.in(0).ready + io.ball_complete_i.ready := completeArb.io.in(0).ready completeArb.io.in(1).valid := io.mem_complete_i.valid completeArb.io.in(1).bits := io.mem_complete_i.bits.rob_id - io.mem_complete_i.ready := completeArb.io.in(1).ready + io.mem_complete_i.ready := completeArb.io.in(1).ready completeArb.io.in(2).valid := io.gp_complete_i.valid completeArb.io.in(2).bits := io.gp_complete_i.bits.rob_id - io.gp_complete_i.ready := completeArb.io.in(2).ready + io.gp_complete_i.ready := completeArb.io.in(2).ready // Decide whether to filter completion signals based on configuration - if (b.rs_out_of_order_response) { + if (parameter.rs_out_of_order_response) { // Out-of-order mode: accept all completion signals, ROB commits out-of-order internally rob.io.complete <> completeArb.io.out } else { // Sequential mode: only accept completion signals where rob_id == head_ptr val isHeadComplete = completeArb.io.out.bits === rob.io.head_ptr - rob.io.complete.valid := completeArb.io.out.valid && isHeadComplete - rob.io.complete.bits := completeArb.io.out.bits + rob.io.complete.valid := completeArb.io.out.valid && isHeadComplete + rob.io.complete.bits := completeArb.io.out.bits completeArb.io.out.ready := rob.io.complete.ready && isHeadComplete } diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index aef4f59d..c4ae9ce2 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -4,36 +4,73 @@ import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} +import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.gpdomain.sequencer.decoder.DomainDecoder +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +object GpDomainParam { + implicit def rw: upickle.default.ReadWriter[GpDomainParam] = upickle.default.macroRW + + /** + * Load from JSON file + */ + def fromJson(path: String): GpDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[GpDomainParam](jsonStr) + } + + /** + * Generate from global config + */ + def fromGlobal(global: framework.builtin.BaseConfig): GpDomainParam = { + GpDomainParam( + rob_entries = global.rob_entries + ) + } + +} + +case class GpDomainParam( + rob_entries: Int) + extends SerializableModuleParameter { + override def toString: String = + s"""GpDomainParam + | ROB entries: $rob_entries + |""".stripMargin +} /** * General Purpose Domain */ -class GpDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - // Receive instructions from GlobalRS - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) +@instantiable +class GpDomain(val parameter: GpDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[GpDomainParam] { - // Report completion to GlobalRS - val global_complete_o = Decoupled(new GlobalRsComplete) + @public + val io = IO(new Bundle { + // Receive instructions from GlobalRS + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries))) - // Status signal - val busy = Output(Bool()) -} + // Report completion to GlobalRS + val global_complete_o = Decoupled(new GlobalRsComplete(parameter.rob_entries)) -class GpDomain(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new GpDomainIO) + // Status signal + val busy = Output(Bool()) + }) io.global_issue_i.ready := io.global_complete_o.ready // ----------------------------------------------------------------------------- // Decode Stage // ----------------------------------------------------------------------------- - val decoder = Module(new DomainDecoder) + val decoder: Instance[framework.gpdomain.sequencer.decoder.DomainDecoder] = + Instantiate(new framework.gpdomain.sequencer.decoder.DomainDecoder(parameter)) decoder.io.inst_i := io.global_issue_i.bits.cmd.raw_cmd val decoded = decoder.io.decoded_o - io.global_complete_o.valid := io.global_issue_i.valid + io.global_complete_o.valid := io.global_issue_i.valid io.global_complete_o.bits.rob_id := io.global_issue_i.bits.rob_id io.busy := false.B diff --git a/arch/src/main/scala/framework/gpdomain/configs/default.json b/arch/src/main/scala/framework/gpdomain/configs/default.json new file mode 100644 index 00000000..51c7186f --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/configs/default.json @@ -0,0 +1,3 @@ +{ + "rob_entries": 16 +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala index b1a8272d..ec5a5971 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala @@ -5,14 +5,13 @@ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ - class BuckyballRawCmd(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand } object DISA { // RVV Instruction Opcodes - val RVV_OPCODE_V = "b1010111".U // 0x57: OP-V (vector compute) - val RVV_OPCODE_VL = "b0000111".U // 0x07: LOAD-FP (vector load) - val RVV_OPCODE_VS = "b0100111".U // 0x27: STORE-FP (vector store) + val RVV_OPCODE_V = "b1010111".U // 0x57: OP-V (vector compute) + val RVV_OPCODE_VL = "b0000111".U // 0x07: LOAD-FP (vector load) + val RVV_OPCODE_VS = "b0100111".U // 0x27: STORE-FP (vector store) } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala index da76280d..c33559f5 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/Decoder.scala @@ -15,7 +15,11 @@ object DecoderParam { implicit def rwP: upickle.default.ReadWriter[DecoderParam] = upickle.default.macroRW } -case class DecoderParam(fpuEnable: Boolean, zvbbEnable: Boolean, useXsfmm: Boolean, allInstructions: Seq[Instruction]) +case class DecoderParam( + fpuEnable: Boolean, + zvbbEnable: Boolean, + useXsfmm: Boolean, + allInstructions: Seq[Instruction]) extends SerializableModuleParameter trait T1DecodeFiled[D <: Data] extends DecodeField[T1DecodePattern, D] with FieldName @@ -29,6 +33,7 @@ trait BoolField extends T1DecodeFiled[Bool] with BoolDecodeField[T1DecodePattern case attribute.N => n case attribute.DC => dc } + } trait T1UopField extends T1DecodeFiled[UInt] with FieldName { @@ -44,6 +49,7 @@ trait T1fpExecutionTypeUopField extends T1DecodeFiled[UInt] with FieldName { } object Decoder { + object logic extends BoolField { override def getTriState(pattern: T1DecodePattern): TriState = pattern.isLogic.value } @@ -233,6 +239,7 @@ object Decoder { } object topUop extends T1TopUopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.topUop.value match { case _: TopT0.type => BitPat("b00000") case _: TopT1.type => BitPat("b00001") @@ -268,9 +275,11 @@ object Decoder { case _: TopT31.type => BitPat("b11111") case _ => BitPat.dontCare(5) } + } object uop extends T1UopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.decoderUop.value match { case addCase: AdderUOPType => addCase match { @@ -380,15 +389,18 @@ object Decoder { } case _ => BitPat.dontCare(4) } + } object fpExecutionType extends T1fpExecutionTypeUopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.fpExecutionType match { case FpExecutionType.Compare => BitPat("b10") case FpExecutionType.MA => BitPat("b00") case FpExecutionType.Other => BitPat("b11") case FpExecutionType.Nil => BitPat.dontCare(2) } + } object maskPipeType extends BoolField { @@ -400,6 +412,7 @@ object Decoder { } object maskPipeUop extends T1TopUopField { + override def genTable(pattern: T1DecodePattern): BitPat = pattern.maskPipeUop.value match { case _: MaskUop0.type => BitPat("b00000") case _: MaskUop1.type => BitPat("b00001") @@ -415,9 +428,10 @@ object Decoder { case _: MaskUop11.type => BitPat("b01011") case _ => BitPat.dontCare(chiselType.getWidth) } + } - def allFields(param: DecoderParam): Seq[T1DecodeFiled[_ >: Bool <: UInt]] = Seq( + def allFields(param: DecoderParam): Seq[T1DecodeFiled[_ >: Bool <: UInt]] = Seq( logic, adder, shift, @@ -491,7 +505,8 @@ object Decoder { ) else Seq() } - def allDecodePattern(param: DecoderParam): Seq[T1DecodePattern] = + + def allDecodePattern(param: DecoderParam): Seq[T1DecodePattern] = param.allInstructions.map(T1DecodePattern(_, param)).toSeq.sortBy(_.instruction.name) def decodeTable(param: DecoderParam): DecodeTable[T1DecodePattern] = @@ -507,7 +522,13 @@ trait FieldName { case class SpecialAux(name: String, vs: Int, value: String) case class SpecialMap(name: String, vs: Int, data: Map[String, String]) -case class SpecialAuxInstr(instrName: String, vs: Int, value: String, name: String) + +case class SpecialAuxInstr( + instrName: String, + vs: Int, + value: String, + name: String) + case class Op( tpe: String, funct6: String, @@ -519,6 +540,7 @@ case class Op( vd: String, opcode: String) extends DecodePattern { + // include 32 bits: funct6 + vm + vs2 + vs1 + funct3 + vd + opcode def bitPat: BitPat = BitPat( "b" + @@ -535,4 +557,5 @@ case class Op( vd + opcode ) + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala index 4e69a68f..e0880ecf 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala @@ -3,15 +3,18 @@ package framework.gpdomain.sequencer.decoder import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.gpdomain.GpDomainParam import framework.gpdomain.sequencer.decoder.{Decoder, DecoderParam} import freechips.rocketchip.tile.RoCCCommand +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} /** * Domain Decoder Parameter Object * Contains the configuration for RVV instruction decoding */ object DomainDecoderParameter { + // Get all RVV instructions from our local database lazy val allInstructions: Seq[InstructionEncoding.Instruction] = { RVVInstructions.allInstructions @@ -19,18 +22,19 @@ object DomainDecoderParameter { // Create decoder parameter using our local instruction types lazy val decoderParam: DecoderParam = DecoderParam( - fpuEnable = true, // Enable floating-point vector instructions - zvbbEnable = true, // Enable vector bit manipulation - useXsfmm = false, // Disable xsfmm extension for now + fpuEnable = true, // Enable floating-point vector instructions + zvbbEnable = true, // Enable vector bit manipulation + useXsfmm = false, // Disable xsfmm extension for now allInstructions = allInstructions ) + } /** * Domain Decoder IO */ -class DomainDecoderIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val inst_i = Input(new RoCCCommand) +class DomainDecoderIO(implicit p: Parameters) extends Bundle { + val inst_i = Input(new RoCCCommand) val decoded_o = Decoder.bundle(DomainDecoderParameter.decoderParam).cloneType } @@ -38,7 +42,11 @@ class DomainDecoderIO(implicit b: CustomBuckyballConfig, p: Parameters) extends * Domain Decoder Module * Encapsulates the T1 decoder logic with local instruction database */ -class DomainDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class DomainDecoder(val parameter: GpDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[GpDomainParam] { + @public val io = IO(new DomainDecoderIO) import DomainDecoderParameter._ diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala index 7273a6b0..6de76028 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDatabase.scala @@ -8,6 +8,7 @@ package framework.gpdomain.sequencer.decoder * Provides instruction definitions without external dependencies */ object InstructionEncoding { + /** Like chisel3.BitPat, this stores the instruction encoding */ case class Encoding(value: BigInt, mask: BigInt) { def toBitMask(bit_pat: String) = @@ -21,24 +22,27 @@ object InstructionEncoding { def fromString(str: String): Encoding = { require(str.length == 32, s"Encoding string must be 32 bits, got ${str.length}") Encoding( - str.reverse.zipWithIndex.map { case (c, i) => - c match { - case '1' => BigInt(1) << i - case '0' => BigInt(0) - case '?' => BigInt(0) - case _ => throw new IllegalArgumentException(s"Invalid encoding character: $c") - } + str.reverse.zipWithIndex.map { + case (c, i) => + c match { + case '1' => BigInt(1) << i + case '0' => BigInt(0) + case '?' => BigInt(0) + case _ => throw new IllegalArgumentException(s"Invalid encoding character: $c") + } }.sum, - str.reverse.zipWithIndex.map { case (c, i) => - c match { - case '1' => BigInt(1) << i - case '0' => BigInt(1) << i - case '?' => BigInt(0) - case _ => throw new IllegalArgumentException(s"Invalid encoding character: $c") - } + str.reverse.zipWithIndex.map { + case (c, i) => + c match { + case '1' => BigInt(1) << i + case '0' => BigInt(1) << i + case '?' => BigInt(0) + case _ => throw new IllegalArgumentException(s"Invalid encoding character: $c") + } }.sum ) } + } case class Arg(name: String, msb: Int, lsb: Int) { @@ -56,20 +60,20 @@ object InstructionEncoding { } case class Instruction( - name: String, - encoding: Encoding, - args: Seq[Arg], - instructionSets: Seq[InstructionSet], - pseudoFrom: Option[Instruction], - ratified: Boolean, - custom: Boolean - ) { + name: String, + encoding: Encoding, + args: Seq[Arg], + instructionSets: Seq[InstructionSet], + pseudoFrom: Option[Instruction], + ratified: Boolean, + custom: Boolean) { def instructionSet: InstructionSet = instructionSets.head } object Instruction { implicit val rw: upickle.default.ReadWriter[Instruction] = upickle.default.macroRW } + } /** @@ -80,22 +84,22 @@ object RVVInstructions { import InstructionEncoding._ // Common argument definitions - val vd = Arg("vd", 11, 7) - val vs1 = Arg("vs1", 19, 15) - val vs2 = Arg("vs2", 24, 20) - val vs3 = Arg("vs3", 11, 7) - val vm = Arg("vm", 25, 25) - val rs1 = Arg("rs1", 19, 15) - val rs2 = Arg("rs2", 24, 20) - val rd = Arg("rd", 11, 7) - val zimm5 = Arg("zimm5", 19, 15) + val vd = Arg("vd", 11, 7) + val vs1 = Arg("vs1", 19, 15) + val vs2 = Arg("vs2", 24, 20) + val vs3 = Arg("vs3", 11, 7) + val vm = Arg("vm", 25, 25) + val rs1 = Arg("rs1", 19, 15) + val rs2 = Arg("rs2", 24, 20) + val rd = Arg("rd", 11, 7) + val zimm5 = Arg("zimm5", 19, 15) val zimm10 = Arg("zimm10", 29, 20) val zimm11 = Arg("zimm11", 30, 20) - val simm5 = Arg("simm5", 19, 15) - val nf = Arg("nf", 31, 29) + val simm5 = Arg("simm5", 19, 15) + val nf = Arg("nf", 31, 29) // Instruction set definitions - val rv_v = InstructionSet("rv_v") + val rv_v = InstructionSet("rv_v") val rv_zvbb = InstructionSet("rv_zvbb") /** @@ -104,10 +108,10 @@ object RVVInstructions { */ def allInstructions: Seq[Instruction] = { configInstructions ++ - integerArithmeticInstructions ++ - loadStoreInstructions ++ - maskInstructions ++ - permuteInstructions + integerArithmeticInstructions ++ + loadStoreInstructions ++ + maskInstructions ++ + permuteInstructions } // ============================================================================ @@ -116,7 +120,10 @@ object RVVInstructions { def configInstructions: Seq[Instruction] = Seq( Instruction( name = "vsetvli", - encoding = Encoding.fromString("0????????????????111?????1010111"), // 31=0, zimm11(30..20), rs1(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) + encoding = + Encoding.fromString( + "0????????????????111?????1010111" + ), // 31=0, zimm11(30..20), rs1(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) args = Seq(rd, rs1, zimm11), instructionSets = Seq(rv_v), pseudoFrom = None, @@ -125,7 +132,10 @@ object RVVInstructions { ), Instruction( name = "vsetivli", - encoding = Encoding.fromString("11???????????????111?????1010111"), // 31..30=11, zimm10(29..20), zimm5(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) + encoding = + Encoding.fromString( + "11???????????????111?????1010111" + ), // 31..30=11, zimm10(29..20), zimm5(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) args = Seq(rd, zimm10, zimm5), instructionSets = Seq(rv_v), pseudoFrom = None, @@ -134,7 +144,10 @@ object RVVInstructions { ), Instruction( name = "vsetvl", - encoding = Encoding.fromString("1000000??????????111?????1010111"), // 31=1, 30..25=000000, rs2(24..20), rs1(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) + encoding = + Encoding.fromString( + "1000000??????????111?????1010111" + ), // 31=1, 30..25=000000, rs2(24..20), rs1(19..15), funct3=111(14..12), rd(11..7), opcode=1010111(6..0) args = Seq(rd, rs1, rs2), instructionSets = Seq(rv_v), pseudoFrom = None, @@ -175,7 +188,6 @@ object RVVInstructions { ratified = true, custom = false ), - // VSUB variants Instruction( name = "vsub.vv", @@ -195,7 +207,6 @@ object RVVInstructions { ratified = true, custom = false ), - // VMUL variants Instruction( name = "vmul.vv", @@ -224,7 +235,10 @@ object RVVInstructions { // Unit-stride loads Instruction( name = "vle8.v", - encoding = Encoding.fromString("???000?00000?????000?????0000111"), // nf, mew=0, mop=00, lumop=00000, funct3=000, opcode=0000111 + encoding = + Encoding.fromString( + "???000?00000?????000?????0000111" + ), // nf, mew=0, mop=00, lumop=00000, funct3=000, opcode=0000111 args = Seq(vd, rs1, vm), instructionSets = Seq(rv_v), pseudoFrom = None, @@ -258,7 +272,6 @@ object RVVInstructions { ratified = true, custom = false ), - // Unit-stride stores Instruction( name = "vse8.v", @@ -354,4 +367,5 @@ object RVVInstructions { custom = false ) ) + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala index a2b366e2..4ba60527 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/InstructionDocumentation.scala @@ -5,12 +5,14 @@ package framework.gpdomain.sequencer.decoder import framework.gpdomain.sequencer.decoder.InstructionEncoding.Instruction -/** Generate documentation for each instructions for T1. The documentation should contain the behavior for instruction - * in a specific configuration in T1. - * @todo - * should it be a post process at omreader? - */ +/** + * Generate documentation for each instructions for T1. The documentation should contain the behavior for instruction + * in a specific configuration in T1. + * @todo + * should it be a post process at omreader? + */ case class InstructionDocumentation(instruction: Instruction, param: DecoderParam) { + override def toString: String = instruction.name match { case "vaadd.vv" => "TODO!" case "vaadd.vx" => "TODO!" @@ -462,4 +464,5 @@ case class InstructionDocumentation(instruction: Instruction, param: DecoderPara case "vtdiscard" => "TODO!" case _ => "TODO" } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala index e4bf4f7b..bd7c3f4c 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala @@ -45,9 +45,10 @@ class T1InstructionOM( attributes := attributesIn } -/** A case class that should wrap all Vector Instructions. This is used to store the attribute for Vector Instruction - * under the T1 uArch. It generates [[chisel3.util.experimental.decode.TruthTable]], as well as documentation field. - */ +/** + * A case class that should wrap all Vector Instructions. This is used to store the attribute for Vector Instruction + * under the T1 uArch. It generates [[chisel3.util.experimental.decode.TruthTable]], as well as documentation field. + */ case class T1DecodePattern(instruction: Instruction, param: DecoderParam) extends DecodePattern { override def bitPat: BitPat = BitPat("b" + instruction.encoding.toString) @@ -189,4 +190,5 @@ case class T1DecodePattern(instruction: Instruction, param: DecoderParam) extend ) obj.getPropertyReference } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala index 603e049c..753a2570 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala @@ -9,15 +9,20 @@ import chisel3.util.experimental.decode.TruthTable import scala.language.postfixOps object TableGenerator extends App { + implicit class CrossAble[X](xs: Traversable[X]) { + def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { x <- xs y <- ys } yield (x, y) + } + implicit def bool2str(b: Boolean): String = if (b) "b1" else "b0" object LogicTable { + object LogicOpcode { var index = 0 } @@ -51,13 +56,16 @@ object TableGenerator extends App { val table: List[(BitPat, BitPat)] = bitValue .cross(bitValue) .cross(opList) - .map { case ((op0, op1), op) => - BitPat(toBinary(op.value)) ## BitPat(op0) ## BitPat(op1) -> BitPat(op.op(op0, op1)) + .map { + case ((op0, op1), op) => + BitPat(toBinary(op.value)) ## BitPat(op0) ## BitPat(op1) -> BitPat(op.op(op0, op1)) } .toList + } object LaneDecodeTable { + object LaneUop { var index = 0 } @@ -67,14 +75,9 @@ object TableGenerator extends App { LaneUop.index = LaneUop.index + 1 } - /*object SubUnitCode { - var index = 1 - } - - sealed trait SubUnitCode { - val value: Int = SubUnitCode.index - SubUnitCode.index = SubUnitCode.index << 1 - }*/ + /* object SubUnitCode { var index = 1 } + * + * sealed trait SubUnitCode { val value: Int = SubUnitCode.index SubUnitCode.index = SubUnitCode.index << 1 } */ trait BaseObject trait SubUnit extends BaseObject @@ -171,10 +174,9 @@ object TableGenerator extends App { toBinary(groupId, 2) ) -> BitPat(toBinary(index, 2)) ## BitPat(toBinary(mask, 4)) } - val res: TruthTable = TruthTable(table, BitPat.dontCare(6)) + val res: TruthTable = TruthTable(table, BitPat.dontCare(6)) } - def toBinary(i: Int, digits: Int = 3): String = { + def toBinary(i: Int, digits: Int = 3): String = String.format("b%" + digits + "s", i.toBinaryString).replace(' ', '0') - } } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala index 4e722823..a928020e 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/adderUop.scala @@ -19,7 +19,8 @@ object addUop10 extends AdderUOPType object addUop11 extends AdderUOPType object AdderUOP { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> addUop0, t1 _ -> addUop1, @@ -36,7 +37,8 @@ object AdderUOP { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vaadd.vv", "vaadd.vx", @@ -65,7 +67,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vasub.vv", "vasub.vx", @@ -90,7 +93,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t2(t1DecodePattern: T1DecodePattern): Boolean = { + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmslt.vv", "vmslt.vx", @@ -99,7 +103,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t3(t1DecodePattern: T1DecodePattern): Boolean = { + + def t3(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsle.vi", "vmsle.vv", @@ -110,7 +115,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsgt.vi", "vmsgt.vx", @@ -119,7 +125,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmax.vv", "vmax.vx", @@ -130,7 +137,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t7(t1DecodePattern: T1DecodePattern): Boolean = { + + def t7(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmin.vv", "vmin.vx", @@ -141,7 +149,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmseq.vi", "vmseq.vv", @@ -149,7 +158,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsne.vi", "vmsne.vv", @@ -157,7 +167,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t10(t1DecodePattern: T1DecodePattern): Boolean = { + + def t10(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vadc.vim", "vadc.vvm", @@ -171,7 +182,8 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t11(t1DecodePattern: T1DecodePattern): Boolean = { + + def t11(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsbc.vv", "vmsbc.vvm", @@ -182,4 +194,5 @@ object AdderUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala index 70bd21af..13d2e875 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/divUop.scala @@ -13,7 +13,8 @@ object divUop9 extends DivUOPType object divUop10 extends DivUOPType object DivUOP { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> divUop0, t1 _ -> divUop1, @@ -24,7 +25,8 @@ object DivUOP { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vdiv.vv", "vdiv.vx", @@ -33,7 +35,8 @@ object DivUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vrem.vv", "vrem.vx", @@ -42,23 +45,27 @@ object DivUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfdiv.vf", "vfdiv.vv" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfsqrt.v" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t10(t1DecodePattern: T1DecodePattern): Boolean = { + + def t10(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfrdiv.vf" ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala index dc7649f1..9ba81d4d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/floatUop.scala @@ -22,6 +22,7 @@ object FUT13 extends FloatUopType object FUT14 extends FloatUopType object FloatUop { + def apply(t1DecodePattern: T1DecodePattern) = { Seq( t0 _ -> FUT0, @@ -42,6 +43,7 @@ object FloatUop { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(t1(t1DecodePattern) @@ -60,6 +62,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction) } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmsac.vf", @@ -71,6 +74,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfnmsac.vf", @@ -82,6 +86,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfnmacc.vf", @@ -93,6 +98,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfclass.v", @@ -102,6 +108,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmsub.vf", @@ -110,6 +117,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfnmsub.vf", @@ -118,6 +126,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfnmadd.vf", @@ -126,6 +135,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfadd.vf", @@ -140,6 +150,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfcvt.xu.f.v", @@ -148,12 +159,14 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfcvt.x.f.v" ) allMatched.contains(t1DecodePattern.instruction.name) } + def t12(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmax.vf", @@ -162,6 +175,7 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t13(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfcvt.rtz.xu.f.v", @@ -169,10 +183,12 @@ object FloatUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t14(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfcvt.rtz.x.f.v" ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala index 22312909..1fe108a2 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/fpExecutionType.scala @@ -6,30 +6,39 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object FpExecutionType { - trait Type extends Uop { + + trait Type extends Uop { def apply(t1DecodePattern: T1DecodePattern): Boolean } + case object Compare extends Type { def apply(t1DecodePattern: T1DecodePattern): Boolean = isFcompare.y(t1DecodePattern) } - case object Other extends Type { + + case object Other extends Type { def apply(t1DecodePattern: T1DecodePattern): Boolean = isFother.y(t1DecodePattern) } - case object MA extends Type { + + case object MA extends Type { def apply(t1DecodePattern: T1DecodePattern): Boolean = !(isFcompare.y(t1DecodePattern) || isFother.y(t1DecodePattern)) } - case object Nil extends Type { + + case object Nil extends Type { + def apply(t1DecodePattern: T1DecodePattern): Boolean = { require(requirement = false, "unreachable") false } + } + def apply(t1DecodePattern: T1DecodePattern): Type = { val tpe = Seq(Compare, Other, MA).filter(tpe => tpe(t1DecodePattern)) require(tpe.size <= 1) tpe.headOption.getOrElse(Nil) } + } case class FpExecutionType(value: FpExecutionType.Type) extends UopDecodeAttribute[FpExecutionType.Type] { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala index 93cacd7b..1a848b1f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAdder.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isAdder { + def apply(t1DecodePattern: T1DecodePattern): isAdder = Seq( y _ -> Y, @@ -111,6 +112,7 @@ object isAdder { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala index 73987b23..23b1c3b6 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isAverage.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isAverage { + def apply(t1DecodePattern: T1DecodePattern): isAverage = Seq( y _ -> Y, @@ -28,6 +29,7 @@ object isAverage { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) @@ -80,6 +82,7 @@ object isAverage { ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class isAverage(value: TriState) extends BooleanDecodeAttribute { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala index 75327c57..9c723142 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCompress.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isCompress { + def apply(t1DecodePattern: T1DecodePattern): isCompress = Seq( y _ -> Y, @@ -21,6 +22,7 @@ object isCompress { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala index f70f5b41..7768adfc 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrossread.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isCrossread { + def apply(t1DecodePattern: T1DecodePattern): isCrossread = Seq( y _ -> Y, @@ -59,6 +60,7 @@ object isCrossread { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala index ed17151c..ab957ddc 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isCrosswrite.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isCrosswrite { + def apply(t1DecodePattern: T1DecodePattern): isCrosswrite = Seq( y _ -> Y, @@ -53,6 +54,7 @@ object isCrosswrite { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) @@ -105,6 +107,7 @@ object isCrosswrite { ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class isCrosswrite(value: TriState) extends BooleanDecodeAttribute { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala index d2ff7438..1452d516 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDivider.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isDivider { + def apply(t1DecodePattern: T1DecodePattern): isDivider = Seq( y _ -> Y, @@ -32,6 +33,7 @@ object isDivider { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala index 3385935b..0d17e7fd 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isDontneedexecuteinlane.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isDontneedexecuteinlane { + def apply(t1DecodePattern: T1DecodePattern): isDontneedexecuteinlane = Seq( y _ -> Y, @@ -136,6 +137,7 @@ object isDontneedexecuteinlane { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala index df57b48f..ad126d1b 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isExtend.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isExtend { + def apply(t1DecodePattern: T1DecodePattern): isExtend = Seq( y _ -> Y, @@ -26,6 +27,7 @@ object isExtend { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala index 83cbbd1d..fdad714d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFcompare.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFcompare { + def apply(t1DecodePattern: T1DecodePattern): isFcompare = Seq( y _ -> Y, @@ -36,6 +37,7 @@ object isFcompare { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala index 95ad026d..93342100 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFfo.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFfo { + def apply(t1DecodePattern: T1DecodePattern): isFfo = Seq( y _ -> Y, @@ -24,6 +25,7 @@ object isFfo { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala index c14dc3ee..8ba3a76f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFirstwiden.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFirstwiden { + def apply(t1DecodePattern: T1DecodePattern): isFirstwiden = Seq( y _ -> Y, @@ -55,6 +56,7 @@ object isFirstwiden { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala index 48d776af..47dbb423 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloat.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFloat { + def apply(t1DecodePattern: T1DecodePattern): isFloat = Seq( y _ -> Y, @@ -115,6 +116,7 @@ object isFloat { else Seq() allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala index d13574ab..03c3dd6c 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloatmul.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFloatmul { + def apply(t1DecodePattern: T1DecodePattern): isFloatmul = Seq( y _ -> Y, @@ -25,6 +26,7 @@ object isFloatmul { else Seq() allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala index c18a353d..eabfca86 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFloattype.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFloattype { + def apply(t1DecodePattern: T1DecodePattern): isFloattype = Seq( y _ -> Y, @@ -124,6 +125,7 @@ object isFloattype { else Seq() allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala index 61dd3c8c..373e7885 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFma.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFma { + def apply(t1DecodePattern: T1DecodePattern): isFma = Seq( y _ -> Y, @@ -45,6 +46,7 @@ object isFma { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala index 965c26c4..4f9db018 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isFother.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isFother { + def apply(t1DecodePattern: T1DecodePattern): isFother = Seq( y _ -> Y, @@ -35,6 +36,7 @@ object isFother { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala index 83b6e01d..a771d262 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isGather { + def apply(t1DecodePattern: T1DecodePattern): isGather = Seq( y _ -> Y, @@ -24,6 +25,7 @@ object isGather { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala index 5552833c..1867d225 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isGather16.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isGather16 { + def apply(t1DecodePattern: T1DecodePattern): isGather16 = Seq( y _ -> Y, @@ -21,6 +22,7 @@ object isGather16 { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala index 07349be3..3c6e40f6 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isId.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isId { + def apply(t1DecodePattern: T1DecodePattern): isId = Seq( y _ -> Y, @@ -78,6 +79,7 @@ object isId { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala index cd4426fe..95ca2064 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIndextype.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isIndextype { + def apply(t1DecodePattern: T1DecodePattern): isIndextype = Seq( y _ -> Y, @@ -52,6 +53,7 @@ object isIndextype { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala index c2dd11a6..346a0ff7 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isIota.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isIota { + def apply(t1DecodePattern: T1DecodePattern): isIota = Seq( y _ -> Y, @@ -21,6 +22,7 @@ object isIota { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala index f08b07f2..6d6c0b54 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isItype.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isItype { + def apply(t1DecodePattern: T1DecodePattern): isItype = Seq( y _ -> Y, @@ -57,6 +58,7 @@ object isItype { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala index 0b4c45bb..34d50375 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isLogic.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isLogic { + def apply(t1DecodePattern: T1DecodePattern): isLogic = Seq( y _ -> Y, @@ -40,6 +41,7 @@ object isLogic { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala index 72ee2cbe..60b7382d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskPipeType.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMaskPipeType { + def apply(t1DecodePattern: T1DecodePattern): isMaskPipeType = Seq( y _ -> Y, @@ -101,6 +102,7 @@ object isMaskPipeType { allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala index f143ef20..caa580d7 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskdestination.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMaskdestination { + def apply(t1DecodePattern: T1DecodePattern): isMaskdestination = Seq( y _ -> Y, @@ -60,6 +61,7 @@ object isMaskdestination { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala index 4469e9a4..fe8b5ef1 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasklogic.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMasklogic { + def apply(t1DecodePattern: T1DecodePattern): isMasklogic = Seq( y _ -> Y, @@ -34,6 +35,7 @@ object isMasklogic { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala index 27dada01..5da843cf 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMasksource.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMasksource { + def apply(t1DecodePattern: T1DecodePattern): isMasksource = Seq( y _ -> Y, @@ -43,6 +44,7 @@ object isMasksource { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala index e415460c..70d0dd51 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMaskunit.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMaskunit { + def apply(t1DecodePattern: T1DecodePattern): isMaskunit = Seq( y _ -> Y, @@ -80,6 +81,7 @@ object isMaskunit { val allMatched = mvType ++ compress ++ maskDestination ++ isFFO allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala index 5825ac17..a050fccc 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMulticycle.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMulticycle { + def apply(t1DecodePattern: T1DecodePattern): isMulticycle = Seq( y _ -> Y, @@ -124,6 +125,7 @@ object isMulticycle { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala index bd0833ce..80d80466 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMultiplier.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMultiplier { + def apply(t1DecodePattern: T1DecodePattern): isMultiplier = Seq( y _ -> Y, @@ -51,6 +52,7 @@ object isMultiplier { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala index 1704a7d6..ab1e5e36 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isMv.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isMv { + def apply(t1DecodePattern: T1DecodePattern): isMv = Seq( y _ -> Y, @@ -24,6 +25,7 @@ object isMv { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala index 4c162533..9e98c73f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNarrow.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isNarrow { + def apply(t1DecodePattern: T1DecodePattern): isNarrow = Seq( y _ -> Y, @@ -32,6 +33,7 @@ object isNarrow { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala index 178bfa12..1f7782f9 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isNr.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isNr { + def apply(t1DecodePattern: T1DecodePattern): isNr = Seq( y _ -> Y, @@ -24,6 +25,7 @@ object isNr { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala index 34167406..26e24f72 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOrderreduce.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isOrderreduce { + def apply(t1DecodePattern: T1DecodePattern): isOrderreduce = Seq( y _ -> Y, @@ -21,6 +22,7 @@ object isOrderreduce { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala index 63c3559e..60759f93 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isOther.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isOther { + def apply(t1DecodePattern: T1DecodePattern): isOther = Seq( y _ -> Y, @@ -47,6 +48,7 @@ object isOther { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala index fcf7e4a0..35989575 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isPopcount.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isPopcount { + def apply(t1DecodePattern: T1DecodePattern): isPopcount = Seq( y _ -> Y, @@ -21,6 +22,7 @@ object isPopcount { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala index 0fd34132..f4ed3059 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReadonly.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isReadonly { + def apply(t1DecodePattern: T1DecodePattern): isReadonly = Seq( y _ -> Y, @@ -28,6 +29,7 @@ object isReadonly { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala index 8f7e0ef1..2d6f293e 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isRed.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isRed { + def apply(t1DecodePattern: T1DecodePattern): isRed = Seq( y _ -> Y, @@ -37,6 +38,7 @@ object isRed { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala index 6f12d7e1..a7825d39 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isReverse.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isReverse { + def apply(t1DecodePattern: T1DecodePattern): isReverse = Seq( y _ -> Y, @@ -22,6 +23,7 @@ object isReverse { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala index dcef5855..be1dd104 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSaturate.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isSaturate { + def apply(t1DecodePattern: T1DecodePattern): isSaturate = Seq( y _ -> Y, @@ -38,6 +39,7 @@ object isSaturate { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) @@ -90,6 +92,7 @@ object isSaturate { ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class isSaturate(value: TriState) extends BooleanDecodeAttribute { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala index 6d3f1db9..39f3dbf5 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isScheduler.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isScheduler { + def apply(t1DecodePattern: T1DecodePattern): isScheduler = Seq( y _ -> Y, @@ -263,6 +264,7 @@ object isScheduler { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala index 7fd1ba80..1b8122a5 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isShift.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isShift { + def apply(t1DecodePattern: T1DecodePattern): isShift = Seq( y _ -> Y, @@ -41,6 +42,7 @@ object isShift { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala index 994693da..ecf2f4a7 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSlid.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isSlid { + def apply(t1DecodePattern: T1DecodePattern): isSlid = Seq( y _ -> Y, @@ -28,6 +29,7 @@ object isSlid { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala index 37ac7f9e..dfa9045e 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecial.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isSpecial { + def apply(t1DecodePattern: T1DecodePattern): isSpecial = Seq( y _ -> Y, @@ -135,6 +136,7 @@ object isSpecial { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala index d54efaa4..54516774 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSpecialslot.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isSpecialslot { + def apply(t1DecodePattern: T1DecodePattern): isSpecialslot = Seq( y _ -> Y, @@ -140,6 +141,7 @@ object isSpecialslot { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala index 2f9a2d4a..741d2f78 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSreadvd.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isSreadvd { + def apply(t1DecodePattern: T1DecodePattern): isSreadvd = Seq( y _ -> Y, @@ -296,6 +297,7 @@ object isSreadvd { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala index 48db0886..49243c44 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isSwrite.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isSwrite { + def apply(t1DecodePattern: T1DecodePattern): isSwrite = Seq( y _ -> Y, @@ -153,6 +154,7 @@ object isSwrite { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala index f862fbf4..29dde00e 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isTargetrd.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isTargetrd { + def apply(t1DecodePattern: T1DecodePattern): isTargetrd = Seq( y _ -> Y, @@ -24,6 +25,7 @@ object isTargetrd { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala index 828c1ace..bbf09061 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnorderwrite.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isUnorderwrite { + def apply(t1DecodePattern: T1DecodePattern): isUnorderwrite = Seq( y _ -> Y, @@ -34,6 +35,7 @@ object isUnorderwrite { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala index ddedf7d8..dda6ce36 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned0.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isUnsigned0 { + def apply(t1DecodePattern: T1DecodePattern): isUnsigned0 = Seq( y _ -> Y, @@ -158,6 +159,7 @@ object isUnsigned0 { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala index a9500f99..283aa5e1 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isUnsigned1.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isUnsigned1 { + def apply(t1DecodePattern: T1DecodePattern): isUnsigned1 = Seq( y _ -> Y, @@ -119,6 +120,7 @@ object isUnsigned1 { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala index 159418a4..4d7c5fe6 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVector.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isVector { + def apply(t1DecodePattern: T1DecodePattern): isVector = Seq( y _ -> Y, @@ -19,6 +20,7 @@ object isVector { val allMatched = t1DecodePattern.param.allInstructions.filter(i => i.instructionSet.name == "rv_v") allMatched.contains(t1DecodePattern.instruction) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala index c89df48e..89d4988f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVtype.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isVtype { + def apply(t1DecodePattern: T1DecodePattern): isVtype = Seq( y _ -> Y, @@ -189,6 +190,7 @@ object isVtype { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala index c7e0676c..fb3d1a77 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isVwmacc.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isVwmacc { + def apply(t1DecodePattern: T1DecodePattern): isVwmacc = Seq( y _ -> Y, @@ -27,6 +28,7 @@ object isVwmacc { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala index 0d160b88..ffc295bb 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWidenreduce.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isWidenreduce { + def apply(t1DecodePattern: T1DecodePattern): isWidenreduce = Seq( y _ -> Y, @@ -22,6 +23,7 @@ object isWidenreduce { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) @@ -74,6 +76,7 @@ object isWidenreduce { ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class isWidenreduce(value: TriState) extends BooleanDecodeAttribute { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala index bba534f1..b352a175 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isWriteCount.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isWriteCount { + def apply(t1DecodePattern: T1DecodePattern): isWriteCount = Seq( y _ -> Y, @@ -81,6 +82,7 @@ object isWriteCount { allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala index 7436f37f..5c88ea6f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZero.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isZero { + def apply(t1DecodePattern: T1DecodePattern): isZero = Seq( y _ -> Y, @@ -40,6 +41,7 @@ object isZero { ) allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala index 298784b9..53d6e5be 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvbb.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isZvbb { + def apply(t1DecodePattern: T1DecodePattern): isZvbb = Seq( y _ -> Y, @@ -39,6 +40,7 @@ object isZvbb { else Seq() allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala index f89e54af..45045e51 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/isZvma.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object isZvma { + def apply(t1DecodePattern: T1DecodePattern): isZvma = Seq( y _ -> Y, @@ -42,6 +43,7 @@ object isZvma { else Seq() allMatched.contains(t1DecodePattern.instruction.name) } + def n(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = t1DecodePattern.param.allInstructions.filter(i => !(y(t1DecodePattern) || dc(t1DecodePattern))) allMatched.contains(t1DecodePattern.instruction) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala index 2345c8b7..22685ae6 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/logicUop.scala @@ -16,7 +16,8 @@ object logicUop8 extends LogicUopType object logicUop9 extends LogicUopType object LogicUop { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> logicUop0, t1 _ -> logicUop1, @@ -30,7 +31,8 @@ object LogicUop { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vand.vi", "vand.vv", @@ -40,7 +42,8 @@ object LogicUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmor.mm", "vor.vi", @@ -50,7 +53,8 @@ object LogicUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t2(t1DecodePattern: T1DecodePattern): Boolean = { + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmxor.mm", "vredxor.vs", @@ -60,34 +64,40 @@ object LogicUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmandn.mm" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t5(t1DecodePattern: T1DecodePattern): Boolean = { + + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmorn.mm" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmxnor.mm" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmnand.mm" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmnor.mm" ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala index d4b74867..668c8c58 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/maskPipeOpcode.scala @@ -18,11 +18,13 @@ object MaskUop8 extends MaskPipeUop object MaskUop9 extends MaskPipeUop object MaskUop10 extends MaskPipeUop object MaskUop11 extends MaskPipeUop + // 0000 x => extend x?4:2 [0,1] // 0001 x => gather x?16:sew [2,3] // 001 xy => slide x?up:down y?s:1 [4,7] // 010 xx => 0: add 1: logic 2: float 3: order [8,11] object MaskPipeOpcode { + def apply(t1DecodePattern: T1DecodePattern): MaskPipeOpcode = { Seq( t0 _ -> MaskUop0, @@ -85,6 +87,7 @@ object MaskPipeOpcode { val allMatched: Seq[String] = extend ++ isCrossWrite allMatched.contains(t1DecodePattern.instruction.name) } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vsext.vf4", @@ -107,35 +110,39 @@ object MaskPipeOpcode { allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfslide1down.vf", "vslide1down.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t5(t1DecodePattern: T1DecodePattern): Boolean = { + + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vslidedown.vi", "vslidedown.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfslide1up.vf", "vslide1up.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t7(t1DecodePattern: T1DecodePattern): Boolean = { + + def t7(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vslideup.vi", "vslideup.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vcpop.m", "vredmax.vs", @@ -148,7 +155,8 @@ object MaskPipeOpcode { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vredand.vs", "vredor.vs", @@ -156,6 +164,7 @@ object MaskPipeOpcode { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfredmax.vs", @@ -165,6 +174,7 @@ object MaskPipeOpcode { ) allMatched.contains(t1DecodePattern.instruction.name) } + def t11(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfredosum.vs", @@ -172,6 +182,7 @@ object MaskPipeOpcode { ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class MaskPipeOpcode(value: MaskPipeUop) extends UopDecodeAttribute[MaskPipeUop] { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala index 788349ea..89f14874 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/mulUop.scala @@ -14,7 +14,8 @@ object mulUop10 extends MulUOPType object mulUop14 extends MulUOPType object MulUOP { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> mulUop0, t1 _ -> mulUop1, @@ -26,7 +27,8 @@ object MulUOP { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmul.vv", "vmul.vx", @@ -41,14 +43,16 @@ object MulUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmadd.vv", "vmadd.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t3(t1DecodePattern: T1DecodePattern): Boolean = { + + def t3(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmulh.vv", "vmulh.vx", @@ -59,7 +63,8 @@ object MulUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t5(t1DecodePattern: T1DecodePattern): Boolean = { + + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmacc.vv", "vmacc.vx", @@ -73,20 +78,23 @@ object MulUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t10(t1DecodePattern: T1DecodePattern): Boolean = { + + def t10(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vnmsub.vv", "vnmsub.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t14(t1DecodePattern: T1DecodePattern): Boolean = { + + def t14(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vnmsac.vv", "vnmsac.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class MulUOP(value: MulUOPType) extends UopDecodeAttribute[MulUOPType] { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala index 07d77dbb..8dc4eeeb 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/otherUop.scala @@ -18,7 +18,8 @@ object otherUop8 extends OtherUopType object otherUop9 extends OtherUopType object OtherUop { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> otherUop0, t1 _ -> otherUop1, @@ -34,31 +35,36 @@ object OtherUop { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfirst.m" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsbf.m" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t2(t1DecodePattern: T1DecodePattern): Boolean = { + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsof.m" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t3(t1DecodePattern: T1DecodePattern): Boolean = { + + def t3(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsif.m" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vrgather.vi", "vrgather.vv", @@ -67,7 +73,8 @@ object OtherUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t5(t1DecodePattern: T1DecodePattern): Boolean = { + + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmerge.vfm", "vfmv.v.f", @@ -80,7 +87,8 @@ object OtherUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vnclip.wi", "vnclip.wv", @@ -91,7 +99,8 @@ object OtherUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t7(t1DecodePattern: T1DecodePattern): Boolean = { + + def t7(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmv.s.f", "vmv.s.x", @@ -99,16 +108,19 @@ object OtherUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vcpop.m" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vid.v" ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala index 827a17ec..75e371b2 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/package.scala @@ -8,18 +8,21 @@ import chisel3.properties.{ClassType, Property} package object attribute { - /** Attribute that will be encode the property of an instruction in the uarch and will be additional encode into the - * object module, which will be used to provide metadata for verifications. - */ + /** + * Attribute that will be encode the property of an instruction in the uarch and will be additional encode into the + * object module, which will be used to provide metadata for verifications. + */ trait DecodeAttribute[T] { val identifier: String = this.getClass.getSimpleName.replace("$", "") val value: T val description: String + // Property of this attribute def om: Property[ClassType] = { val obj = Instantiate(new T1DecodeAttributeOM(identifier, description, value.toString)) obj.getPropertyReference } + } sealed trait TriState diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala index 057be2d0..efc384bf 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala @@ -13,7 +13,8 @@ object shiftUop4 extends ShiftUopType object shiftUop6 extends ShiftUopType object ShiftUop { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> shiftUop0, t1 _ -> shiftUop1, @@ -24,7 +25,8 @@ object ShiftUop { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vnsrl.wi", "vnsrl.wv", @@ -35,7 +37,8 @@ object ShiftUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vsll.vi", "vsll.vv", @@ -43,7 +46,8 @@ object ShiftUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t2(t1DecodePattern: T1DecodePattern): Boolean = { + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vnsra.wi", "vnsra.wv", @@ -54,7 +58,8 @@ object ShiftUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vssrl.vi", "vssrl.vv", @@ -62,7 +67,8 @@ object ShiftUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vssra.vi", "vssra.vv", @@ -70,6 +76,7 @@ object ShiftUop { ) allMatched.contains(t1DecodePattern.instruction.name) } + } case class ShiftUop(value: ShiftUopType) extends UopDecodeAttribute[ShiftUopType] { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala index 6f5bb1aa..8615238b 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/topUop.scala @@ -40,7 +40,8 @@ object TopT30 extends TopUopType object TopT31 extends TopUopType object TopUop { - def apply(t1DecodePattern: T1DecodePattern): TopUop = { + + def apply(t1DecodePattern: T1DecodePattern): TopUop = { Seq( t0 _ -> TopT0, t1 _ -> TopT1, @@ -78,85 +79,100 @@ object TopUop { case (fn, tpe) if fn(t1DecodePattern) => TopUop(tpe) }.getOrElse(TopUop(TopT0)) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vslidedown.vi", "vslidedown.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vslideup.vi", "vslideup.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t2(t1DecodePattern: T1DecodePattern): Boolean = { + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vslide1down.vx", "vfslide1down.vf" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t3(t1DecodePattern: T1DecodePattern): Boolean = { + + def t3(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vslide1up.vx", "vfslide1up.vf" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vrgather.vv" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t5(t1DecodePattern: T1DecodePattern): Boolean = { + + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vrgatherei16.vv" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq() allMatched.contains(t1DecodePattern.instruction.name) } - def t7(t1DecodePattern: T1DecodePattern): Boolean = { + + def t7(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq() allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("viota.m") allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vcompress.vm") allMatched.contains(t1DecodePattern.instruction.name) } - def t10(t1DecodePattern: T1DecodePattern): Boolean = { + + def t10(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmv.s.f", "vmv.s.x" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t11(t1DecodePattern: T1DecodePattern): Boolean = { + + def t11(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfmv.f.s", "vmv.x.s" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t12(t1DecodePattern: T1DecodePattern): Boolean = { + + def t12(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq() allMatched.contains(t1DecodePattern.instruction.name) } - def t13(t1DecodePattern: T1DecodePattern): Boolean = { + + def t13(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq() allMatched.contains(t1DecodePattern.instruction.name) } - def t14(t1DecodePattern: T1DecodePattern): Boolean = { + + def t14(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmsbf.m", "vmsif.m", @@ -164,11 +180,13 @@ object TopUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t15(t1DecodePattern: T1DecodePattern): Boolean = { + + def t15(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vfirst.m") allMatched.contains(t1DecodePattern.instruction.name) } - def t16(t1DecodePattern: T1DecodePattern): Boolean = { + + def t16(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vcpop.m", "vredmax.vs", @@ -179,14 +197,16 @@ object TopUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t17(t1DecodePattern: T1DecodePattern): Boolean = { + + def t17(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vwredsum.vs", "vwredsumu.vs" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t18(t1DecodePattern: T1DecodePattern): Boolean = { + + def t18(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vredand.vs", "vredor.vs", @@ -194,30 +214,36 @@ object TopUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t19(t1DecodePattern: T1DecodePattern): Boolean = { + + def t19(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vfredmax.vs", "vfredmin.vs" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t20(t1DecodePattern: T1DecodePattern): Boolean = { + + def t20(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vfredusum.vs") allMatched.contains(t1DecodePattern.instruction.name) } - def t21(t1DecodePattern: T1DecodePattern): Boolean = { + + def t21(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vfredosum.vs") allMatched.contains(t1DecodePattern.instruction.name) } - def t22(t1DecodePattern: T1DecodePattern): Boolean = { + + def t22(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vfwredusum.vs") allMatched.contains(t1DecodePattern.instruction.name) } - def t23(t1DecodePattern: T1DecodePattern): Boolean = { + + def t23(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vfwredosum.vs") allMatched.contains(t1DecodePattern.instruction.name) } - def t24(t1DecodePattern: T1DecodePattern): Boolean = { + + def t24(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vmadc.vi", "vmadc.vim", @@ -262,34 +288,42 @@ object TopUop { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t25(t1DecodePattern: T1DecodePattern): Boolean = { + + def t25(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq() allMatched.contains(t1DecodePattern.instruction.name) } - def t26(t1DecodePattern: T1DecodePattern): Boolean = { + + def t26(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vzext.vf2") allMatched.contains(t1DecodePattern.instruction.name) } - def t27(t1DecodePattern: T1DecodePattern): Boolean = { + + def t27(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vsext.vf2") allMatched.contains(t1DecodePattern.instruction.name) } - def t28(t1DecodePattern: T1DecodePattern): Boolean = { + + def t28(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vzext.vf4") allMatched.contains(t1DecodePattern.instruction.name) } - def t29(t1DecodePattern: T1DecodePattern): Boolean = { + + def t29(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vsext.vf4") allMatched.contains(t1DecodePattern.instruction.name) } - def t30(t1DecodePattern: T1DecodePattern): Boolean = { + + def t30(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vzext.vf8") allMatched.contains(t1DecodePattern.instruction.name) } - def t31(t1DecodePattern: T1DecodePattern): Boolean = { + + def t31(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq("vsext.vf8") allMatched.contains(t1DecodePattern.instruction.name) } + } case class TopUop(value: TopUopType) extends UopDecodeAttribute[TopUopType] { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala index e4f665e7..0673d65d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/uop.scala @@ -6,6 +6,7 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern object DecoderUop { + def apply(t1DecodePattern: T1DecodePattern): DecoderUop = { val tpe: Option[DecoderUop] = Seq( isDivider.y(t1DecodePattern) -> DivUOP(t1DecodePattern), @@ -23,6 +24,7 @@ object DecoderUop { require(tpe.size <= 1) tpe.getOrElse(DecoderUop(UopDC)) } + } case class DecoderUop(value: Uop) extends UopDecodeAttribute[Uop] { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala index 2a127c23..7b153009 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zeroUop.scala @@ -9,14 +9,16 @@ trait ZeroUOPType extends Uop object zeroUop0 extends ZeroUOPType object ZeroUOP { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> zeroUop0 ).collectFirst { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vcompress.vm", "vfslide1down.vf", @@ -41,4 +43,5 @@ object ZeroUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala index 5c20adec..9361933f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/zvbbUop.scala @@ -18,7 +18,8 @@ object zvbbUop8 extends ZvbbUOPType // andn object zvbbUop9 extends ZvbbUOPType // pop object ZvbbUOP { - def apply(t1DecodePattern: T1DecodePattern): Uop = { + + def apply(t1DecodePattern: T1DecodePattern): Uop = { Seq( t0 _ -> zvbbUop0, t1 _ -> zvbbUop1, @@ -34,44 +35,51 @@ object ZvbbUOP { case (fn, tpe) if fn(t1DecodePattern) => tpe }.getOrElse(UopDC) } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { + + def t0(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vbrev.v" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t1(t1DecodePattern: T1DecodePattern): Boolean = { + + def t1(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vbrev8.v" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t2(t1DecodePattern: T1DecodePattern): Boolean = { + + def t2(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vrev8.v" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t3(t1DecodePattern: T1DecodePattern): Boolean = { + + def t3(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vclz.v" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t4(t1DecodePattern: T1DecodePattern): Boolean = { + + def t4(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vctz.v" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t5(t1DecodePattern: T1DecodePattern): Boolean = { + + def t5(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vrol.vv", "vrol.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t6(t1DecodePattern: T1DecodePattern): Boolean = { + + def t6(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vror.vv", "vror.vx", @@ -79,7 +87,8 @@ object ZvbbUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t7(t1DecodePattern: T1DecodePattern): Boolean = { + + def t7(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vwsll.vv", "vwsll.vx", @@ -87,17 +96,20 @@ object ZvbbUOP { ) allMatched.contains(t1DecodePattern.instruction.name) } - def t8(t1DecodePattern: T1DecodePattern): Boolean = { + + def t8(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vandn.vv", "vandn.vx" ) allMatched.contains(t1DecodePattern.instruction.name) } - def t9(t1DecodePattern: T1DecodePattern): Boolean = { + + def t9(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched: Seq[String] = Seq( "vcpop.v" ) allMatched.contains(t1DecodePattern.instruction.name) } + } diff --git a/arch/src/main/scala/framework/memdomain/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/DomainDecoder.scala deleted file mode 100644 index 3d9878de..00000000 --- a/arch/src/main/scala/framework/memdomain/DomainDecoder.scala +++ /dev/null @@ -1,96 +0,0 @@ -package framework.memdomain - -import chisel3._ -import chisel3.util._ -import framework.frontend.decoder.{PostGDCmd, DomainId} -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.DISA._ -import framework.memdomain.dma.LocalAddr -import freechips.rocketchip.tile._ -import org.chipsalliance.cde.config.Parameters - -// Detailed decode output for Mem domain -class MemDecodeCmd(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - private val numBanks = b.sp_banks + b.acc_banks - val is_load = Bool() - val is_store = Bool() - - // Memory address - val mem_addr = UInt(b.memAddrLen.W) - - // Iteration count - val iter = UInt(10.W) - - // Scratchpad address and bank information - // 3 bits, supports 8 banks (SPAD+ACC) - val sp_bank = UInt(log2Up(numBanks).W) - // 12 bits, uses SPAD row count (sufficient to accommodate ACC's 10-bit address) - val sp_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - - val special = UInt(40.W) -} - - -// LS decode fields -object LSDecodeFields extends Enumeration { - type Field = Value - val LD_EN, ST_EN, MEMADDR, SPADDR, ITER, SPECIAL, VALID = Value -} - -// Default constants for Mem decoder -object MemDefaultConstants { - val Y = true.B - val N = false.B - val DADDR = 0.U(14.W) - val DITER = 0.U(10.W) - val DSPECIAL = 0.U(40.W) -} - -class MemDomainDecoder(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - import MemDefaultConstants._ - - val io = IO(new Bundle { - val raw_cmd_i = Flipped(Decoupled(new PostGDCmd)) - val mem_decode_cmd_o = Decoupled(new MemDecodeCmd) - }) - - val spAddrLen = b.spAddrLen - val memAddrLen = b.memAddrLen - - // Only process Mem instructions - io.raw_cmd_i.ready := io.mem_decode_cmd_o.ready - - val func7 = io.raw_cmd_i.bits.raw_cmd.inst.funct - val rs1 = io.raw_cmd_i.bits.raw_cmd.rs1 - val rs2 = io.raw_cmd_i.bits.raw_cmd.rs2 - - // Load/Store instruction decoding - import LSDecodeFields._ - val ls_default_decode = List(N,N,DADDR,DADDR,DITER,DSPECIAL,N) - val ls_decode_list = ListLookup(func7, ls_default_decode, Array( - MVIN_BITPAT -> List(Y,N,rs1(memAddrLen-1,0),rs2(spAddrLen-1,0),rs2(spAddrLen+9,spAddrLen),rs2(63,spAddrLen + 10),Y), // mvin - MVOUT_BITPAT -> List(N,Y,rs1(memAddrLen-1,0),rs2(spAddrLen-1,0),rs2(spAddrLen+9,spAddrLen),rs2(63,spAddrLen + 10),Y) // mvout - )) - - assert(!(io.raw_cmd_i.fire && !ls_decode_list(LSDecodeFields.VALID.id).asBool), - s"MemDomainDecoder: Invalid command opcode, func7 = 0x%x\n", func7) - -// ----------------------------------------------------------------------------- -// Output assignment -// ----------------------------------------------------------------------------- - io.mem_decode_cmd_o.valid := io.raw_cmd_i.valid && (io.raw_cmd_i.bits.domain_id === DomainId.MEM) - - io.mem_decode_cmd_o.bits.is_load := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.LD_EN.id).asBool, false.B) - io.mem_decode_cmd_o.bits.is_store := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.ST_EN.id).asBool, false.B) - io.mem_decode_cmd_o.bits.mem_addr := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.MEMADDR.id).asUInt, 0.U(b.memAddrLen.W)) - io.mem_decode_cmd_o.bits.iter := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.ITER.id).asUInt, 0.U(10.W)) - - - // Address parsing - val ls_spaddr = ls_decode_list(LSDecodeFields.SPADDR.id).asUInt - val ls_laddr = LocalAddr.cast_to_sp_addr(b.local_addr_t, ls_spaddr) - - io.mem_decode_cmd_o.bits.sp_bank := Mux(io.mem_decode_cmd_o.valid, ls_laddr.mem_bank(), 0.U(log2Up(b.sp_banks + b.acc_banks).W)) - io.mem_decode_cmd_o.bits.sp_bank_addr := Mux(io.mem_decode_cmd_o.valid, ls_laddr.mem_row(), 0.U(log2Up(b.spad_bank_entries + b.acc_bank_entries).W)) - io.mem_decode_cmd_o.bits.special := Mux(io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.SPECIAL.id).asUInt, 0.U(40.W)) -} diff --git a/arch/src/main/scala/framework/memdomain/MemController.scala b/arch/src/main/scala/framework/memdomain/MemController.scala deleted file mode 100644 index 312dff1a..00000000 --- a/arch/src/main/scala/framework/memdomain/MemController.scala +++ /dev/null @@ -1,136 +0,0 @@ -package framework.memdomain - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.frontend.decoder.PostGDCmd -import freechips.rocketchip.tile._ -import framework.memdomain.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} -import framework.memdomain.mem.{SramReadIO, SramWriteIO, Scratchpad} -import framework.memdomain.{MemLoader, MemStorer} -import framework.memdomain.rs.MemReservationStation -import framework.memdomain.tlb.{BBTLBCluster, BBTLBIO, BBTLBExceptionIO} -import framework.memdomain.pmc.MemCyclePMC -import freechips.rocketchip.tilelink.TLEdgeOut -import freechips.rocketchip.rocket.TLBPTWIO -import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} -import framework.balldomain.blink.{SramReadWithRobId, SramWriteWithRobId, SramReadWithInfo, SramWriteWithInfo} -import framework.switcher.{ToPhysicalLine, ToVirtualLine} - -/** - * MemController: Controller that encapsulates scratchpad and accumulator - * Provides DMA interface and Ball Domain interface - */ -class MemController(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOut) extends Module { - private val numBanks = b.sp_banks + b.acc_banks - val io = IO(new Bundle { - // Issue interface from global RS (single channel) - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) - - // Report completion to global RS (single channel) - val global_complete_o = Decoupled(new GlobalRsComplete) - - // SRAM read/write interface - used by load/store - val interdma = new Bundle { - val sramread = Vec(b.sp_banks, Flipped(new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) - val sramwrite = Vec(b.sp_banks, Flipped(new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accread = Vec(b.acc_banks, Flipped(new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) - val accwrite = Vec(b.acc_banks, Flipped(new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) - } - - // DMA interface - used by Outer DRAM controller - val intradma = new Bundle { - val read = new Bundle { - val req = Decoupled(new BBReadRequest()) - val resp = Flipped(Decoupled(new BBReadResponse(b.spad_w))) - } - val write = new Bundle { - val req = Decoupled(new BBWriteRequest(b.spad_w)) - val resp = Flipped(Decoupled(new BBWriteResponse)) - } - } - - // TLB interface - exposed externally for DMA use - val tlb = Vec(2, Flipped(new BBTLBIO)) - - // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) - val ptw = Vec(1, new TLBPTWIO) - - // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) - val tlbExp = Vec(1, new BBTLBExceptionIO) - - // Busy signal - val busy = Output(Bool()) - }) - - val memDecoder = Module(new MemDomainDecoder) - val memRs = Module(new MemReservationStation) - val memLoader = Module(new MemLoader) - val memStorer = Module(new MemStorer) - // TLB cluster - use shared TLB like Gemmini - val tlbCluster = Module(new BBTLBCluster(2, b.tlb_size, b.dma_maxbytes, use_shared_tlb = true)) - -// ----------------------------------------------------------------------------- -// Global RS -> MemDecoder -// ----------------------------------------------------------------------------- - memDecoder.io.raw_cmd_i.valid := io.global_issue_i.valid - memDecoder.io.raw_cmd_i.bits := io.global_issue_i.bits.cmd - io.global_issue_i.ready := memDecoder.io.raw_cmd_i.ready - -// ----------------------------------------------------------------------------- -// MemDecoder -> MemReservationStation -// ----------------------------------------------------------------------------- - // Connect decoded instruction and global rob_id - memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid - memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits - memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id - memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready - -// ----------------------------------------------------------------------------- -// MemReservationStation -> MemLoader/MemStorer -// ----------------------------------------------------------------------------- - memLoader.io.cmdReq <> memRs.io.issue_o.ld - memStorer.io.cmdReq <> memRs.io.issue_o.st - memRs.io.commit_i.ld <> memLoader.io.cmdResp - memRs.io.commit_i.st <> memStorer.io.cmdResp - -//----------------------------------------------------------------------------- -// PMC - Performance Monitor Counter -// ----------------------------------------------------------------------------- - val pmc = Module(new MemCyclePMC) - pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire - pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits - pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire - pmc.io.stReq_i.bits := memRs.io.issue_o.st.bits - pmc.io.ldResp_o.valid := memLoader.io.cmdResp.fire - pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits - pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire - pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits -// - // Connect MemLoader and MemStorer to DMA - memLoader.io.dmaReq <> io.intradma.read.req - io.intradma.read.resp <> memLoader.io.dmaResp - memStorer.io.dmaReq <> io.intradma.write.req - io.intradma.write.resp <> memStorer.io.dmaResp - - // Connect TLB - now using internal BBTLBCluster - io.tlb <> tlbCluster.io.clients - io.ptw <> tlbCluster.io.ptw - - // Connect exception interface - note direction: internal TLB's exp is Output, external interface is Input - tlbCluster.io.exp <> io.tlbExp - - // Connect MemLoader and MemStorer to MemController's DMA interface - memLoader.io.sramWrite <> io.interdma.sramwrite - memLoader.io.accWrite <>io.interdma.accwrite - memStorer.io.sramRead <> io.interdma.sramread - memStorer.io.accRead <> io.interdma.accread - - // Completion signal connected to global RS - io.global_complete_o <> memRs.io.complete_o - - // Busy signal - // Simple busy signal - io.busy := !memRs.io.complete_o.ready -} diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 17c04ded..3087ee02 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -2,124 +2,173 @@ package framework.memdomain import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import examples.BuckyballConfigs.CustomBuckyballConfig import framework.frontend.decoder.PostGDCmd import freechips.rocketchip.tile._ -import framework.memdomain.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} -import framework.memdomain.mem.{SramReadIO, SramWriteIO, Scratchpad} -import framework.memdomain.{MemLoader, MemStorer, MemController} -import framework.memdomain.rs.MemReservationStation -import framework.memdomain.tlb.{BBTLBCluster, BBTLBIO, BBTLBExceptionIO} -import framework.memdomain.pmc.MemCyclePMC + +import framework.balldomain.blink.{BankRead, BankWrite} import freechips.rocketchip.tilelink.TLEdgeOut import freechips.rocketchip.rocket.TLBPTWIO -import framework.frontend.globalrs.{GlobalRsIssue, GlobalRsComplete} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} -import framework.switcher.{ToPhysicalLine, ToVirtualLine} +import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} + +import framework.memdomain.frontend.MemController +import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} +import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBIO} + +import framework.memdomain.midend.MemScheduler +import framework.memdomain.backend.MemManager + +object MemDomainParam { + implicit def rw: upickle.default.ReadWriter[MemDomainParam] = upickle.default.macroRW + + /** + * Load from JSON file + */ + def fromJson(path: String): MemDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[MemDomainParam](jsonStr) + } + + /** + * Generate from global config + */ + def fromGlobal(global: framework.builtin.BaseConfig): MemDomainParam = { + MemDomainParam( + bankNum = global.bankNum, + bankWidth = global.bankWidth, + bankEntries = global.bankEntries, + bankMaskLen = global.bankMaskLen, + tlb_size = global.tlb_size, + rob_entries = global.rob_entries, + dma_maxbytes = global.dma_maxbytes, + memAddrLen = global.memAddrLen, + bankChannel = 8 // Default value + ) + } -class MemDomain(implicit b: CustomBuckyballConfig, p: Parameters, edge: TLEdgeOut) extends Module { - private val numBanks = b.sp_banks + b.acc_banks - val io = IO(new Bundle { - // Issue interface from global RS (single channel) - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue)) +} + +case class MemDomainParam( + bankNum: Int, + bankWidth: Int, + bankEntries: Int, + bankMaskLen: Int, + tlb_size: Int, + rob_entries: Int, + dma_maxbytes: Int, + memAddrLen: Int, + bankChannel: Int) + extends SerializableModuleParameter { + override def toString: String = + s"""MemDomainParam + | Bank num: $bankNum + | Bank width: $bankWidth bits + | Bank entries: $bankEntries + | Bank mask length: $bankMaskLen + | TLB size: $tlb_size + | ROB entries: $rob_entries + | DMA max bytes: $dma_maxbytes + | Mem addr len: $memAddrLen + | Bank channel: $bankChannel + |""".stripMargin +} - // Report completion to global RS (single channel) - val global_complete_o = Decoupled(new GlobalRsComplete) +@instantiable +class MemDomain(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { - // SRAM interface for interaction with Ball Domain + @public + val io = IO(new Bundle { + // ------------------------------------------------- + // Command Channel + // ------------------------------------------------- + // global RS -> MemDomain + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries)(p))) + // MemDomain -> global RS + val global_complete_o = Decoupled(new GlobalRsComplete(parameter.rob_entries)(p)) + val busy = Output(Bool()) + + // ------------------------------------------------- + // Inside Channel + // ------------------------------------------------- + // Bank interface for interaction with Ball Domain val ballDomain = new Bundle { - val sramRead = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) - val sramWrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) + + val bankRead = Vec( + parameter.bankNum, + new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum) + ) + + val bankWrite = Vec( + parameter.bankNum, + new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.bankNum + ) + ) + } - // DMA interface + // ------------------------------------------------- + // Outside Channel + // ------------------------------------------------- val dma = new Bundle { + val read = new Bundle { - val req = Decoupled(new BBReadRequest()) - val resp = Flipped(Decoupled(new BBReadResponse(b.spad_w))) + val req = Decoupled(new BBReadRequest()) + val resp = Flipped(Decoupled(new BBReadResponse(parameter.bankWidth))) } + val write = new Bundle { - val req = Decoupled(new BBWriteRequest(b.spad_w)) + val req = Decoupled(new BBWriteRequest(parameter.bankWidth)) val resp = Flipped(Decoupled(new BBWriteResponse)) } - } - - // TLB interface - exposed externally for DMA use - val tlb = Vec(2, Flipped(new BBTLBIO)) - // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) - val ptw = Vec(1, new TLBPTWIO) + } - // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) + val tlb = Vec(2, Flipped(new BBTLBIO)) + val ptw = Vec(1, new TLBPTWIO) val tlbExp = Vec(1, new BBTLBExceptionIO) - - // Busy signal - val busy = Output(Bool()) }) - val memController = Module(new MemController) - val translator = Module(new Translator) - val spad = Module(new Scratchpad()) - -// ----------------------------------------------------------------------------- -// Global RS -> MemDecoder -// ----------------------------------------------------------------------------- - memController.io.global_issue_i.valid := io.global_issue_i.valid - memController.io.global_issue_i.bits.cmd := io.global_issue_i.bits.cmd - io.global_issue_i.ready := memController.io.global_issue_i.ready - -// ----------------------------------------------------------------------------- -// MemDecoder -> MemReservationStation -// ----------------------------------------------------------------------------- - // Connect decoded instruction and global rob_id - memController.io.global_issue_i.bits.rob_id := io.global_issue_i.bits.rob_id - - - // Connect MemLoader and MemStorer to DMA - memController.io.intradma.read.req <> io.dma.read.req - io.dma.read.resp <> memController.io.intradma.read.resp - memController.io.intradma.write.req <> io.dma.write.req - io.dma.write.resp <> memController.io.intradma.write.resp - - // Connect TLB - now using internal BBTLBCluster - io.tlb <> memController.io.tlb - io.ptw <> memController.io.ptw - - // Connect exception interface - note direction: internal TLB's exp is Output, external interface is Input - memController.io.tlbExp <> io.tlbExp - - // Connect MemLoader and MemStorer to MemController's DMA interface - - val toVirtualLines0 = Module(new ToVirtualLine()(b, p)) - - memController.io.interdma.sramwrite <> toVirtualLines0.io.sramWrite_i - memController.io.interdma.accwrite <> toVirtualLines0.io.accWrite_i - memController.io.interdma.sramread <> toVirtualLines0.io.sramRead_i - memController.io.interdma.accread <> toVirtualLines0.io.accRead_i - - translator.io.dma_in.sramread <> toVirtualLines0.io.sramRead_o - translator.io.dma_in.sramwrite <> toVirtualLines0.io.sramWrite_o - - translator.io.dma_out.sramread <> spad.io.dma.sramread - translator.io.dma_out.sramwrite <> spad.io.dma.sramwrite - - // ToPhysical interface - // Ball Domain SRAM interface connected to MemController's Ball Domain interface - - translator.io.exec_in.sramread <> io.ballDomain.sramRead - translator.io.exec_in.sramwrite <> io.ballDomain.sramWrite - - translator.io.exec_out.sramread <> spad.io.exec.sramread - translator.io.exec_out.sramwrite <> spad.io.exec.sramwrite - - // translator.io.dma_return := DontCare - // translator.io.exec_return := DontCare - - // Completion signal connected to global RS - io.global_complete_o <> memController.io.global_complete_o - - // Busy signal - // Simple busy signal - io.busy := memController.io.busy + val frontend: Instance[MemController] = Instantiate(new MemController(parameter)(edge)) + val midend: Instance[MemScheduler] = Instantiate(new MemScheduler(parameter)) + val backend: Instance[MemManager] = Instantiate(new MemManager(parameter)) + + // ------------------------------------------------- + // Connection with outside (all in frontend) + // ------------------------------------------------- + // Global RS interface + frontend.io.global_issue_i <> io.global_issue_i + frontend.io.global_complete_o <> io.global_complete_o + frontend.io.busy := io.busy + + // DMA interface + frontend.io.intradma <> io.dma + + // TLB interface + frontend.io.tlb <> io.tlb + frontend.io.ptw <> io.ptw + frontend.io.tlbExp <> io.tlbExp + + // Ball Domain interface (connects to frontend's interdma) + frontend.io.interdma.bankRead <> io.ballDomain.bankRead + frontend.io.interdma.bankWrite <> io.ballDomain.bankWrite + + // ------------------------------------------------- + // Internal Connection (frontend - midend - backend) + // ------------------------------------------------- + // Frontend to Midend: route interdma requests to scheduler + midend.io.frontend.bankRead <> frontend.io.interdma.bankRead + midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite + + // Midend to Backend: route scheduled requests to memory manager + midend.io.mem_req <> backend.io.mem_req } diff --git a/arch/src/main/scala/framework/memdomain/MemLoader.scala b/arch/src/main/scala/framework/memdomain/MemLoader.scala deleted file mode 100644 index a01f76e5..00000000 --- a/arch/src/main/scala/framework/memdomain/MemLoader.scala +++ /dev/null @@ -1,135 +0,0 @@ -package framework.memdomain - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.rs.{MemRsIssue, MemRsComplete} -import framework.memdomain.mem.SramWriteIO -import framework.memdomain.dma.{BBReadRequest, BBReadResponse, LocalAddr} -import freechips.rocketchip.rocket.MStatus -import framework.balldomain.blink.{SramWriteWithRobId, SramWriteWithInfo} - -class MemLoader(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val rob_id_width = log2Up(b.rob_entries) - val numBanks = b.sp_banks + b.acc_banks - val io = IO(new Bundle { - // Load instruction from ReservationStation - val cmdReq = Flipped(Decoupled(new MemRsIssue)) - // Completion signal sent to ReservationStation - val cmdResp = Decoupled(new MemRsComplete) - // Direct connection to DMA read interface - val dmaReq = Decoupled(new BBReadRequest()) - val dmaResp = Flipped(Decoupled(new BBReadResponse(b.spad_w))) - // Connected to Scratchpad SRAM write interface - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) - }) - - val s_idle :: s_dma_req :: s_dma_wait :: Nil = Enum(3) - val state = RegInit(s_idle) - - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - // Cache mem_addr - val mem_addr_reg = Reg(UInt(b.memAddrLen.W)) - // Cache iteration count - val iter_reg = Reg(UInt(10.W)) - // Count number of responses received, supports up to 16 responses - val resp_count = Reg(UInt(log2Up(16).W)) - - // Cache decoded bank information - val wr_bank_reg = Reg(UInt(log2Up(b.sp_banks + b.acc_banks).W)) - val wr_bank_addr_reg = Reg(UInt(log2Up(b.spad_bank_entries).W)) - // Whether this is an acc bank operation - val is_acc_reg = RegInit(false.B) - // Cache stride - val stride_reg = Reg(UInt(10.W)) - - // Receive load instruction - io.cmdReq.ready := state === s_idle - - when (io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { - state := s_dma_req - rob_id_reg := io.cmdReq.bits.rob_id - mem_addr_reg := io.cmdReq.bits.cmd.mem_addr - iter_reg := io.cmdReq.bits.cmd.iter - wr_bank_reg := io.cmdReq.bits.cmd.sp_bank - wr_bank_addr_reg := io.cmdReq.bits.cmd.sp_bank_addr - // Determine if acc based on bank - is_acc_reg := (io.cmdReq.bits.cmd.sp_bank >= b.sp_banks.U) - stride_reg := io.cmdReq.bits.cmd.special(10,0) - resp_count := 0.U - } - - // Issue DMA read request - read iter_reg rows of data - io.dmaReq.valid := state === s_dma_req - io.dmaReq.bits.vaddr := mem_addr_reg - // Byte count of iter rows of data - io.dmaReq.bits.len := iter_reg * (b.veclane * b.inputType.getWidth / 8).U - // Simplified: use default status - io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) - io.dmaReq.bits.stride := stride_reg - - when (io.dmaReq.fire) { - state := s_dma_wait - // Reset response counter - resp_count := 0.U - } - - // Wait for DMA response - io.dmaResp.ready := state === s_dma_wait - - when (io.dmaResp.fire) { - resp_count := resp_count + 1.U - // Return to idle state when last response is received - when (io.dmaResp.bits.last) { - state := s_idle - } - } - - // Stream write to SRAM - write immediately upon receiving each response - // Calculate current write bank and address - // Use address counter from DMA response - val current_bank_addr = wr_bank_addr_reg + io.dmaResp.bits.addrcounter - // All responses write to the same bank - val target_bank = wr_bank_reg - val target_row = current_bank_addr - - for (i <- 0 until b.sp_banks) { - io.sramWrite(i).io.req.valid := io.dmaResp.fire && (target_bank === i.U) - io.sramWrite(i).io.req.bits.addr := target_row - io.sramWrite(i).io.req.bits.data := io.dmaResp.bits.data - io.sramWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(true.B)) - io.sramWrite(i).rob_id := rob_id_reg - } - // Default assignment - for (i <- 0 until b.acc_banks) { - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits.addr := 0.U - io.accWrite(i).io.req.bits.data := 0.U - io.accWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(false.B)) - io.accWrite(i).rob_id := 0.U - } - - for (i <- 0 until b.acc_banks/2) { - when(io.dmaResp.fire && is_acc_reg){ - when(io.dmaResp.bits.addrcounter(2)){ - io.accWrite(i).io.req.valid := target_row(log2Ceil(b.acc_banks/2) - 1, 0) === i.U - io.accWrite(i).io.req.bits.addr := wr_bank_addr_reg + (io.dmaResp.bits.addrcounter >> (log2Ceil(b.acc_banks/2) + 1)) - io.accWrite(i).io.req.bits.data := io.dmaResp.bits.data - io.accWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) - io.accWrite(i).rob_id := rob_id_reg - }.otherwise{ - io.accWrite(i + b.acc_banks/2).io.req.valid := target_row(log2Ceil(b.acc_banks/2) - 1, 0) === i.U - io.accWrite(i + b.acc_banks/2).io.req.bits.addr := wr_bank_addr_reg + (io.dmaResp.bits.addrcounter >> (log2Ceil(b.acc_banks/2) + 1)) - io.accWrite(i + b.acc_banks/2).io.req.bits.data := io.dmaResp.bits.data - io.accWrite(i + b.acc_banks/2).io.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) - io.accWrite(i + b.acc_banks/2).rob_id := rob_id_reg - } - } - } - - // Send completion signal - only send when last response is received - io.cmdResp.valid := io.dmaResp.fire && io.dmaResp.bits.last - io.cmdResp.bits.rob_id := rob_id_reg -} diff --git a/arch/src/main/scala/framework/memdomain/MemStorer.scala b/arch/src/main/scala/framework/memdomain/MemStorer.scala deleted file mode 100644 index a4a5f60b..00000000 --- a/arch/src/main/scala/framework/memdomain/MemStorer.scala +++ /dev/null @@ -1,313 +0,0 @@ -package framework.memdomain - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.rs.{MemRsIssue, MemRsComplete} -import freechips.rocketchip.rocket.MStatus -import framework.memdomain.mem.SramReadIO -import framework.memdomain.dma.{BBWriteRequest, BBWriteResponse, LocalAddr} -import framework.balldomain.blink.{SramReadWithRobId, SramReadWithInfo} - -class MemStorer(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val rob_id_width = log2Up(b.rob_entries) - // Byte count of one row of data - val line_bytes = b.spad_w / 8 - // 16-byte alignment - val align_bytes = 16 - - val io = IO(new Bundle { - // Store instruction from ReservationStation - val cmdReq = Flipped(Decoupled(new MemRsIssue)) - // Completion signal sent to ReservationStation - val cmdResp = Decoupled(new MemRsComplete) - // Direct connection to DMA write interface - val dmaReq = Decoupled(new BBWriteRequest(b.spad_w)) - val dmaResp = Flipped(Decoupled(new BBWriteResponse)) - // Connected to Scratchpad SRAM read interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadWithRobId(b.spad_bank_entries, b.spad_w))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadWithRobId(b.acc_bank_entries, b.acc_w))) - }) - - val s_idle :: s_sram_req :: s_dma_wait :: Nil = Enum(3) - val state = RegInit(s_idle) - - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val mem_addr_reg = Reg(UInt(b.memAddrLen.W)) - val iter_reg = Reg(UInt(10.W)) - val sram_count = Reg(UInt(10.W)) - // Whether this is an acc bank operation - val acc_reg = RegInit(false.B) - // Used to alternately read two acc banks - val acc_flip_reg = RegInit(false.B) - // Cache stride - val stride_reg = Reg(UInt(10.W)) - // Cache decoded bank information - // Need 3 bits to support 8 banks (SPAD+ACC) - val rd_bank_reg = Reg(UInt(log2Up(b.sp_banks + b.acc_banks).W)) - val rd_bank_addr_reg = Reg(UInt(log2Up(b.spad_bank_entries).W)) - - // Data buffer related registers - // 16-byte buffer - val data_buffer = Reg(UInt((align_bytes * 8).W)) - // Number of valid bytes in buffer - val buffer_valid_bytes = Reg(UInt(log2Ceil(align_bytes + 1).W)) - // Starting address corresponding to buffer - val buffer_start_addr = Reg(UInt(b.memAddrLen.W)) - - // Receive store instruction - io.cmdReq.ready := state === s_idle - - when (io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { - state := s_sram_req - rob_id_reg := io.cmdReq.bits.rob_id - mem_addr_reg := io.cmdReq.bits.cmd.mem_addr - iter_reg := io.cmdReq.bits.cmd.iter - rd_bank_reg := io.cmdReq.bits.cmd.sp_bank - rd_bank_addr_reg := io.cmdReq.bits.cmd.sp_bank_addr - sram_count := 0.U - // Determine if acc based on bank - acc_reg := (io.cmdReq.bits.cmd.sp_bank >= b.sp_banks.U) - // Reset flip register - acc_flip_reg := true.B - stride_reg := io.cmdReq.bits.cmd.special(10,0) - // Initialize buffer state - buffer_valid_bytes := 0.U - } - - // Stream read SRAM data - // Calculate current read bank and address - val current_bank_addr = rd_bank_addr_reg + sram_count - // All reads come from the same bank - val target_bank = rd_bank_reg - val target_row = current_bank_addr - - for (i <- 0 until b.sp_banks) { - io.sramRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) && !acc_reg - io.sramRead(i).io.req.bits.addr := target_row - io.sramRead(i).io.req.bits.fromDMA := true.B - io.sramRead(i).rob_id := rob_id_reg - } - - // Default assignment - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits.addr := 0.U - io.accRead(i).io.req.bits.fromDMA := true.B - io.accRead(i).rob_id := 0.U - } - - for (i <- 0 until b.acc_banks/2){ - when((state === s_sram_req) && acc_reg){ - when(sram_count(2) === 0.U){ - io.accRead(i).io.req.valid := i.U === target_row(log2Ceil(b.acc_banks/2) - 1, 0) - io.accRead(i).io.req.bits.addr := rd_bank_addr_reg + (sram_count >> (log2Ceil(b.acc_banks/2) + 1)) - io.accRead(i).io.req.bits.fromDMA := true.B - io.accRead(i).rob_id := rob_id_reg - }.otherwise{ - io.accRead(i + b.acc_banks/2).io.req.valid := i.U === target_row(log2Ceil(b.acc_banks/2) - 1, 0) - io.accRead(i + b.acc_banks/2).io.req.bits.addr := rd_bank_addr_reg + (sram_count >> (log2Ceil(b.acc_banks/2) + 1)) - io.accRead(i + b.acc_banks/2).io.req.bits.fromDMA := true.B - io.accRead(i + b.acc_banks/2).rob_id := rob_id_reg - } - } - } - - // SRAM response processing - val sram_resp_valid = io.sramRead.map(_.io.resp.valid).reduce(_ || _) - val sram_resp_data = Mux1H(io.sramRead.map(_.io.resp.valid), io.sramRead.map(_.io.resp.bits.data)) - val acc_resp_valid = io.accRead.map(_.io.resp.valid).reduce(_ || _) - val acc_resp_data = Mux1H(io.accRead.map(_.io.resp.valid), io.accRead.map(_.io.resp.bits.data)) - - // Calculate memory address corresponding to current row - val current_mem_addr = mem_addr_reg + sram_count(1,0) * line_bytes.U + ((sram_count >> 2) << 2) * stride_reg * line_bytes.U - // Lower 4 bits of address, 0 when 16-byte aligned - val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) - val aligned_addr = Cat(current_mem_addr(b.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) - val is_aligned = addr_offset === 0.U - dontTouch(is_aligned) - dontTouch(aligned_addr) - - // Data merge logic (line_bytes = 16 bytes) - val incoming_data = Mux(sram_resp_valid, sram_resp_data.asUInt, acc_resp_data.asUInt) - // Always 16 bytes - val incoming_bytes = 16.U - - // Data merged into buffer - val merged_data = Wire(UInt((align_bytes * 8).W)) - val total_valid_bytes = Wire(UInt(log2Ceil(align_bytes * 2).W)) - val is_last_iter = (sram_count >= (iter_reg - 1.U) && iter_reg > 0.U) || iter_reg === 0.U - - when (buffer_valid_bytes === 0.U) { - // Buffer is empty - when (addr_offset === 0.U) { - // Address is aligned, use data directly - merged_data := incoming_data - total_valid_bytes := incoming_bytes - }.otherwise { - // Address not aligned, first time: use low bits of new data as high bits of send data, pad low bits with 0 - val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) - merged_data := new_data_low << (addr_offset * 8.U) - total_valid_bytes := align_bytes.U - } - }.otherwise { - // Buffer has data, concatenate: low bits of new data as high bits + buffer data as low bits - val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) - merged_data := (new_data_low << (addr_offset * 8.U)) | data_buffer - // Always 16 bytes - total_valid_bytes := align_bytes.U - } - - // Send logic: except for last iteration, can always fill 16 bytes - val can_send_full_line = total_valid_bytes >= align_bytes.U - val send_bytes = Mux(can_send_full_line, align_bytes.U, total_valid_bytes) - - // Determine send address - always use aligned address - val send_addr = Mux(buffer_valid_bytes === 0.U, aligned_addr, - Cat(buffer_start_addr(b.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W))) - - // DMA request logic - val should_send_normal = (sram_resp_valid || acc_resp_valid) && can_send_full_line - val should_send_first_unaligned = (sram_resp_valid || acc_resp_valid) && (buffer_valid_bytes === 0.U && addr_offset =/= 0.U) - val should_send_last = (sram_resp_valid || acc_resp_valid) && is_last_iter && !can_send_full_line - val should_send = should_send_normal || should_send_first_unaligned || should_send_last - - // Add a flag to track whether all data has been processed - // Completion detection logic - supports two cases: - // 1. Clean data completion (fully aligned case) - val aligned_completion = buffer_valid_bytes === 0.U && is_last_iter - // 2. Remaining data needs to be sent (unaligned case) - // Has remaining data - val has_remaining_data_completion = buffer_valid_bytes > 0.U && is_last_iter - val unaligned_completion_final_send = has_remaining_data_completion && !(sram_resp_valid || acc_resp_valid) - - // Generate mask - val send_mask = Wire(UInt(align_bytes.W)) - when (buffer_valid_bytes === 0.U && addr_offset =/= 0.U) { - // First unaligned: send high bits of new data, mask on high bits - val valid_bytes = align_bytes.U - addr_offset - // 0xFF00 (if addr_offset=8) - send_mask := ((1.U << valid_bytes) - 1.U) << addr_offset - }.elsewhen (buffer_valid_bytes > 0.U && can_send_full_line) { - // Middle concatenation: send full 16 bytes - send_mask := ~0.U(align_bytes.W) // 0xFFFF - }.elsewhen (unaligned_completion_final_send) { - // Last send remaining buffer data: buffer data in low bits - send_mask := (1.U << buffer_valid_bytes) - 1.U // 0x00FF - }.otherwise { - // Aligned case: full data - send_mask := ~0.U(align_bytes.W) // 0xFFFF - } - - // DMA request signal control logic - can only update when DMA is ready - val dma_req_valid_reg = RegInit(false.B) - val dma_req_vaddr_reg = RegInit(0.U(b.memAddrLen.W)) - val dma_req_data_reg = RegInit(0.U((align_bytes * 8).W)) - val dma_req_len_reg = RegInit(0.U(8.W)) - val dma_req_mask_reg = RegInit(0.U(align_bytes.W)) - val dma_req_status_reg = RegInit(0.U.asTypeOf(new MStatus)) - - // Calculate DMA request signals - val dma_req_valid_next = (should_send || unaligned_completion_final_send) && (state === s_sram_req || state === s_dma_wait) - val dma_req_vaddr_next = Mux(unaligned_completion_final_send, buffer_start_addr, send_addr) - val dma_req_data_next = Mux(unaligned_completion_final_send, data_buffer, merged_data) - val dma_req_len_next = align_bytes.U - val dma_req_mask_next = Mux(unaligned_completion_final_send, (1.U << buffer_valid_bytes) - 1.U, send_mask) - val dma_req_status_next = 0.U.asTypeOf(new MStatus) - - // Only update registers when DMA is ready - when (io.dmaReq.ready) { - dma_req_valid_reg := dma_req_valid_next - dma_req_vaddr_reg := dma_req_vaddr_next - dma_req_data_reg := dma_req_data_next - dma_req_len_reg := dma_req_len_next - dma_req_mask_reg := dma_req_mask_next - dma_req_status_reg := dma_req_status_next - } - - // Connect to DMA interface - io.dmaReq.valid := dma_req_valid_reg - io.dmaReq.bits.vaddr := dma_req_vaddr_reg - io.dmaReq.bits.data := dma_req_data_reg - io.dmaReq.bits.len := dma_req_len_reg - io.dmaReq.bits.mask := dma_req_mask_reg - io.dmaReq.bits.status := dma_req_status_reg - - // Connect SRAM response ready signal - based on DMA ready state - io.sramRead.foreach(_.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) - io.accRead.foreach(_.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) - // State transition and counter update - when (io.sramRead.map(_.io.req.fire).reduce(_ || _)) { - state := s_dma_wait - } - - when (io.dmaReq.fire) { - when (!unaligned_completion_final_send) { - sram_count := sram_count + 1.U - } - - // Update buffer state - when (addr_offset =/= 0.U && (sram_resp_valid || acc_resp_valid)) { - // Unaligned case: cache high bits of new data - // Cache is the high bits part - val remaining_bytes = align_bytes.U - addr_offset - data_buffer := incoming_data >> (addr_offset * 8.U) - buffer_valid_bytes := remaining_bytes - // Update buffer corresponding address (point to next 16-byte aligned address) - when (buffer_valid_bytes === 0.U) { - buffer_start_addr := aligned_addr + align_bytes.U - }.otherwise { - buffer_start_addr := buffer_start_addr + align_bytes.U - } - }.elsewhen (unaligned_completion_final_send) { - // Sent final remaining data, clear buffer - buffer_valid_bytes := 0.U - }.otherwise { - // In aligned case, if previous buffer data was merged and sent, need to clear buffer - when (buffer_valid_bytes > 0.U && can_send_full_line && sram_resp_valid) { - buffer_valid_bytes := 0.U - } - } - - // Fix state transition logic - when (unaligned_completion_final_send) { - // Only return to idle after unaligned_completion_final_send completes - state := s_idle - }.elsewhen (aligned_completion) { - // All data has been sent - state := s_idle - }.elsewhen (sram_count + 1.U >= iter_reg && iter_reg > 0.U) { - // Iteration ended, but there may still be buffer data to send - when (buffer_valid_bytes > 0.U) { - // Maintain state, wait for unaligned_completion_final_send - state := s_dma_wait - }.otherwise { - state := s_idle - } - }.elsewhen (iter_reg === 0.U) { - state := s_idle - }.otherwise { - state := s_sram_req - } - } - - // Wait for DMA to truly complete - io.dmaResp.ready := true.B - - // Fix completion signal logic - only issue completion signal after all data transfer is truly complete - val task_complete = RegInit(false.B) - when (io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { - task_complete := false.B - }.elsewhen (io.dmaReq.fire && (unaligned_completion_final_send || aligned_completion)) { - task_complete := true.B - } - - io.cmdResp.valid := task_complete && (state === s_idle) - io.cmdResp.bits.rob_id := rob_id_reg - - // Reset flag after sending completion signal - when (io.cmdResp.fire) { - task_complete := false.B - } -} diff --git a/arch/src/main/scala/framework/memdomain/Translator.scala b/arch/src/main/scala/framework/memdomain/Translator.scala deleted file mode 100644 index aed404cd..00000000 --- a/arch/src/main/scala/framework/memdomain/Translator.scala +++ /dev/null @@ -1,31 +0,0 @@ -package framework.memdomain - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} - -class Translator(implicit b: CustomBuckyballConfig, p: Parameters) extends Module{ - val numBanks = b.sp_banks + b.acc_banks - class BanksIO extends Bundle { - val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) - val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - } - - val io = IO(new Bundle { - val dma_in = new BanksIO - // val dma_return = Flipped(new BanksIO) - val dma_out = Flipped(new BanksIO) - val exec_in = new BanksIO - // val exec_return = Flipped(new BanksIO) - val exec_out = Flipped(new BanksIO) - }) - - io.dma_out <> io.dma_in - // io.dma_return <> io.dma_in - io.exec_out <> io.exec_in - // io.exec_return <> io.exec_in -} - diff --git a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala b/arch/src/main/scala/framework/memdomain/backend/MemManager.scala new file mode 100644 index 00000000..96922833 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/MemManager.scala @@ -0,0 +1,116 @@ +package framework.memdomain.backend + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.memdomain.MemDomainParam +import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} +import framework.memdomain.backend.accpipe.AccPipe + +/** + * MemManager: Backend memory manager + * Manages the physical memory resources (Scratchpad + Accumulator Banks) + * + * Features: + * - Instantiates bankNum SRAM banks and bankChannel AccPipes + * - Supports up to bankChannel concurrent bank accesses per cycle + * - All requests go through AccPipe, which handles both direct write mode and accumulator mode (read-modify-write) + * - Assert checks ensure no bank_id conflicts in the same cycle + */ +class MemRequestIO(parameter: MemDomainParam) extends Bundle { + val write = Flipped(new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) + val read = Flipped(new SramReadIO(parameter.bankEntries, parameter.bankWidth)) + val bank_id = Input(UInt(log2Up(parameter.bankNum).W)) +} + +@instantiable +class MemManager(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public + val io = IO(new Bundle { + // Interface from midend (new architecture) + val mem_req = Vec(parameter.bankChannel, new MemRequestIO(parameter)) + }) + + // Instantiate bankNum SRAM banks + val banks: Seq[Instance[SramBank]] = Seq.fill(parameter.bankNum) { + Instantiate(new SramBank(parameter)) + } + + // Instantiate bankChannel accumulator pipes (all requests go through AccPipe) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(parameter.bankChannel) { + Instantiate(new AccPipe(parameter)) + } + + // ----------------------------------------------------------------------------- + // Request routing: All requests go through AccPipe + // ----------------------------------------------------------------------------- + // Route all requests to AccPipe (AccPipe handles both wmode and read operations) + for (i <- 0 until parameter.bankChannel) { + accPipes(i).io.write <> io.mem_req(i).write + accPipes(i).io.read <> io.mem_req(i).read + accPipes(i).io.bank_id := io.mem_req(i).bank_id + } + + // ----------------------------------------------------------------------------- + // Bank conflict detection + // ----------------------------------------------------------------------------- + // Check for bank_id conflicts across all requests (all go through AccPipe) + for (i <- 0 until parameter.bankChannel) { + for (j <- (i + 1) until parameter.bankChannel) { + // Check write conflicts + when(io.mem_req(i).write.req.valid && io.mem_req(j).write.req.valid) { + assert( + io.mem_req(i).bank_id =/= io.mem_req(j).bank_id, + s"[MemManager]: Write Bank ID conflict between request $i and $j" + ) + } + // Check read conflicts + when(io.mem_req(i).read.req.valid && io.mem_req(j).read.req.valid) { + assert( + io.mem_req(i).bank_id =/= io.mem_req(j).bank_id, + s"[MemManager]: Read Bank ID conflict between request $i and $j" + ) + } + } + } + + // ----------------------------------------------------------------------------- + // Bank routing and connection + // ----------------------------------------------------------------------------- + // Each bank connects to the AccPipe whose current_bank_id matches this bank's ID + // Since we have conflict detection, each bank can have at most one request per cycle + banks.zipWithIndex.foreach { + case (bank, bankIdx) => + val bank_id = bankIdx.U + + // Default: no write request + bank.io.sramWrite.req.valid := false.B + + // Connect write request: find matching AccPipe and connect + accPipes.foreach { accPipe => + val isMatch = accPipe.io.sramWrite.req.valid && accPipe.busy && (accPipe.current_bank_id === bank_id) + when(isMatch) { + bank.io.sramWrite.req <> accPipe.io.sramWrite.req + accPipe.io.sramWrite.resp <> bank.io.sramWrite.resp + } + } + + // Default: no read request + bank.io.sramRead.req.valid := false.B + + // Connect read request: find matching AccPipe and connect + accPipes.foreach { accPipe => + val isMatch = accPipe.io.sramRead.req.valid && accPipe.busy && (accPipe.current_bank_id === bank_id) + when(isMatch) { + bank.io.sramRead.req <> accPipe.io.sramRead.req + accPipe.io.sramRead.resp <> bank.io.sramRead.resp + } + } + } +} diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala new file mode 100644 index 00000000..20d49e7f --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -0,0 +1,159 @@ +package framework.memdomain.backend.accpipe + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import framework.memdomain.MemDomainParam +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO, SramWriteReq, SramWriteResp} +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +/** + * AccPipe: Accumulator Pipeline + * Handles read-modify-write operations for accumulation + * Separated from SramBank for flexibility + */ +@instantiable +class AccPipe(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public + val io = IO(new Bundle { + // Interface to SramBank + val sramRead = new SramReadIO(parameter.bankEntries, parameter.bankWidth) + val sramWrite = new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen) + + // Interface from midend + val read = Flipped(new SramReadIO(parameter.bankEntries, parameter.bankWidth)) + val write = Flipped(new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) + + // Control signals + val bank_id = Input(UInt(log2Up(parameter.bankNum).W)) + }) + + @public + val current_bank_id = Reg(UInt(log2Up(parameter.bankNum).W)) + @public + val busy = Reg(Bool()) + + // State machine for read-modify-write + val s_idle :: s_read :: s_accumulate :: s_write :: Nil = Enum(4) + val state = RegInit(s_idle) + + // Update current_bank_id and busy signal + when(state === s_idle) { + when(io.write.req.valid) { + current_bank_id := io.bank_id + busy := true.B + }.elsewhen(io.read.req.valid) { + current_bank_id := io.bank_id + busy := true.B + }.otherwise { + busy := false.B + } + }.otherwise { + busy := true.B + } + + // Pipeline registers + val acc_addr = RegInit(0.U(log2Ceil(parameter.bankEntries).W)) + val acc_data = RegInit(0.U(parameter.bankWidth.W)) + val acc_mask = RegInit(VecInit(Seq.fill(parameter.bankMaskLen)(false.B))) + + // State machine logic + when(state === s_idle) { + when(io.write.req.valid) { + // Direct write mode: pass through + when(!io.write.req.bits.wmode) { + io.sramWrite.req.valid := io.write.req.valid + io.sramWrite.req.bits.addr := io.write.req.bits.addr + io.sramWrite.req.bits.data := io.write.req.bits.data + io.sramWrite.req.bits.mask := io.write.req.bits.mask + io.write.req.ready := io.sramWrite.req.ready + + io.write.resp.valid := io.sramWrite.req.ready + io.write.resp.bits.ok := io.sramWrite.req.ready + io.sramWrite.req.ready := io.write.resp.ready + + when(io.sramWrite.req.ready) { + state := s_idle + busy := false.B + } + }.otherwise { + // Accumulator mode: start read-modify-write + io.sramRead.req.valid := true.B + io.sramRead.req.bits.addr := io.write.req.bits.addr + io.sramRead.req.bits.fromDMA := false.B + io.write.req.ready := io.sramRead.req.ready + + acc_addr := io.write.req.bits.addr + acc_data := io.write.req.bits.data + acc_mask := io.write.req.bits.mask + + state := s_read + } + }.elsewhen(io.read.req.valid) { + // Pure read operation (not accumulation) + io.sramRead.req.valid := io.read.req.valid + io.sramRead.req.bits.addr := io.read.req.bits.addr + io.sramRead.req.bits.fromDMA := false.B + io.read.req.ready := io.sramRead.req.ready + + state := s_read + } + }.elsewhen(state === s_read) { + // Wait for read response + when(io.sramRead.resp.valid) { + // If we got here from a write request, it's accumulation + // If we got here from a read request, it's a pure read + when(io.read.req.valid) { + // Pure read: pass data back immediately + io.read.resp.valid := io.sramRead.resp.valid + io.read.resp.bits.data := io.sramRead.resp.bits.data + io.read.resp.bits.fromDMA := io.sramRead.resp.bits.fromDMA + io.sramRead.resp.ready := io.read.resp.ready + + when(io.read.resp.ready) { + state := s_idle + busy := false.B + } + }.otherwise { + // Accumulation: proceed to accumulate + state := s_accumulate + } + } + }.elsewhen(state === s_accumulate) { + // Accumulate: old_data + new_data + val new_data = io.sramRead.resp.bits.data + acc_data + acc_data := new_data + + state := s_write + }.elsewhen(state === s_write) { + // Write back accumulated result + io.sramWrite.req.valid := true.B + io.sramWrite.req.bits.addr := acc_addr + io.sramWrite.req.bits.data := acc_data + io.sramWrite.req.bits.mask := acc_mask + + io.write.resp.valid := io.sramWrite.req.ready + io.write.resp.bits.ok := io.sramWrite.req.ready + io.sramWrite.req.ready := io.write.resp.ready + + when(io.sramWrite.req.ready) { + state := s_idle + busy := false.B + } + } + + // Tie off unused signals in unused states + when(state === s_read) { + io.sramRead.resp.ready := true.B + }.otherwise { + io.sramRead.resp.ready := false.B + } + + when(state =/= s_write && state =/= s_idle) { + io.sramWrite.req.valid := false.B + } +} diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala new file mode 100644 index 00000000..2151e39e --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala @@ -0,0 +1,62 @@ +package framework.memdomain.backend.accpipe + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import framework.memdomain.MemDomainParam +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +/** + * BankPipe: Bank Pipeline (直通，非流水线) + * Direct connection to SramBank for read and write operations + * Used for direct write/overwrite operations (non-accumulation) + * Can also serve as a bypass when AccPipe is not fully utilized + */ +@instantiable +class BankPipe(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public + val io = IO(new Bundle { + // Interface to SramBank + val sramRead = new SramReadIO(parameter.bankEntries, parameter.bankWidth) + val sramWrite = new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen) + + // Interface from midend + val read = Flipped(new SramReadIO(parameter.bankEntries, parameter.bankWidth)) + val write = Flipped(new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) + + // Control signals + val bank_id = Input(UInt(log2Up(parameter.bankNum).W)) + }) + + @public + val current_bank_id = Reg(UInt(log2Up(parameter.bankNum).W)) + @public + val busy = Reg(Bool()) + + // Update current_bank_id and busy signal + when(io.write.req.valid || io.read.req.valid) { + current_bank_id := io.bank_id + busy := true.B + }.otherwise { + busy := false.B + } + + // ----------------------------------------------------------------------------- + // Write path (直通) + // ----------------------------------------------------------------------------- + // Direct write: pass through to SramBank + io.sramWrite.req <> io.write.req + io.write.resp <> io.sramWrite.resp + + // ----------------------------------------------------------------------------- + // Read path (直通) + // ----------------------------------------------------------------------------- + // Direct read: pass through to SramBank + io.sramRead.req <> io.read.req + io.read.resp <> io.sramRead.resp +} diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala new file mode 100644 index 00000000..7a5ad0a2 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala @@ -0,0 +1,59 @@ +package framework.memdomain.backend.banks + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import framework.memdomain.MemDomainParam +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +/** + * SramBank: Pure SRAM bank + * Simple read/write memory without any accumulation logic + * Each bank is a single-port SRAM + */ +@instantiable +class SramBank(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + val aligned_to = 8 + val mask_len = (parameter.bankWidth / (aligned_to * 8)) max 1 + val mask_elem = UInt((parameter.bankWidth min (aligned_to * 8)).W) + + @public + val io = IO(new Bundle { + // Bank interface (connected to MemManager) + val sramRead = new SramReadIO(parameter.bankEntries, parameter.bankWidth) + val sramWrite = new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen) + }) + + // SRAM memory + val mem = SyncReadMem(parameter.bankEntries, Vec(mask_len, mask_elem)) + + // ----------------------------------------------------------------------------- + // Read path + // ----------------------------------------------------------------------------- + // Bank read (single port - can't read and write simultaneously) + io.sramRead.req.ready := !io.sramWrite.req.valid + + val raddr = io.sramRead.req.bits.addr + val ren = io.sramRead.req.fire + val rdata = mem.read(raddr, ren) + + io.sramRead.resp.valid := RegNext(ren) + io.sramRead.resp.bits.data := RegNext(rdata.asUInt) + io.sramRead.resp.bits.fromDMA := false.B + + // ----------------------------------------------------------------------------- + // Write path + // ----------------------------------------------------------------------------- + io.sramWrite.req.ready := !io.sramRead.req.valid + + when(io.sramWrite.req.valid) { + mem.write( + io.sramWrite.req.bits.addr, + io.sramWrite.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), + io.sramWrite.req.bits.mask + ) + } +} diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala new file mode 100644 index 00000000..912f3296 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala @@ -0,0 +1,38 @@ +package framework.memdomain.backend.banks + +import chisel3._ +import chisel3.util._ + +/** + * Generic SRAM interface definitions + */ +class SramReadReq(val n: Int) extends Bundle { + val addr = UInt(log2Ceil(n).W) + val fromDMA = Bool() +} + +class SramReadResp(val w: Int) extends Bundle { + val data = UInt(w.W) + val fromDMA = Bool() +} + +class SramReadIO(val n: Int, val w: Int) extends Bundle { + val req = Flipped(Decoupled(new SramReadReq(n))) + val resp = Decoupled(new SramReadResp(w)) +} + +class SramWriteReq(val n: Int, val w: Int, val mask_len: Int) extends Bundle { + val addr = UInt(log2Ceil(n).W) + val mask = Vec(mask_len, Bool()) + val data = UInt(w.W) + val wmode = Bool() // true=accumulator mode, false=direct write mode +} + +class SramWriteIO(val n: Int, val w: Int, val mask_len: Int) extends Bundle { + val req = Flipped(Decoupled(new SramWriteReq(n, w, mask_len))) + val resp = Decoupled(new SramWriteResp()) +} + +class SramWriteResp() extends Bundle { + val ok = Bool() +} diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json new file mode 100644 index 00000000..2e8a78a6 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -0,0 +1,10 @@ +{ + "bankNum": 32, + "bankWidth": 128, + "bankEntries": 128, + "bankMaskLen": 16, + "tlb_size": 4, + "rob_entries": 16, + "dma_maxbytes": 64, + "bankChannel": 8 +} diff --git a/arch/src/main/scala/framework/memdomain/dma/LocalAddr.scala b/arch/src/main/scala/framework/memdomain/dma/LocalAddr.scala deleted file mode 100644 index 31b9b0ab..00000000 --- a/arch/src/main/scala/framework/memdomain/dma/LocalAddr.scala +++ /dev/null @@ -1,147 +0,0 @@ -package framework.memdomain.dma - -import chisel3._ -import chisel3.util._ - -class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle { - private val localAddrBits = 32 // TODO magic number - - private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries) - private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries) - private val maxAddrBits = spAddrBits max accAddrBits - private val memAddrBits = log2Ceil(sp_banks * sp_bank_entries + acc_banks * acc_bank_entries) - - private val spBankBits = log2Up(sp_banks) - private val spBankRowBits = log2Up(sp_bank_entries) - - private val accBankBits = log2Up(acc_banks) - val accBankRowBits = log2Up(acc_bank_entries) - - val spRows = sp_banks * sp_bank_entries - - val is_acc_addr = Bool() - val accumulate = Bool() - val read_full_acc_row = Bool() - - private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth - assert(maxAddrBits + metadata_w < 32) - - val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W) - val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W) - val data = UInt(memAddrBits.W) - - def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits) - def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) - def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits) - def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0) - def mem_bank(dummy: Int = 0) = data(memAddrBits - 1, spBankRowBits) - def mem_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) - - def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0) - def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0) - - def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data - def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this)) - def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR && - (if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B) - - def +(other: UInt) = { - require(isPow2(sp_bank_entries)) // TODO remove this requirement - require(isPow2(acc_bank_entries)) // TODO remove this requirement - - val result = WireInit(this) - result.data := data + other - result - } - - def <=(other: LocalAddr) = - is_acc_addr === other.is_acc_addr && - Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr()) - - def <(other: LocalAddr) = - is_acc_addr === other.is_acc_addr && - Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr()) - - def >(other: LocalAddr) = - is_acc_addr === other.is_acc_addr && - Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr()) - - def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { - require(isPow2(sp_bank_entries)) // TODO remove this requirement - require(isPow2(acc_bank_entries)) // TODO remove this requirement - - val sum = data +& other - - val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits)) - - val result = WireInit(this) - result.data := sum(maxAddrBits - 1, 0) - - (result, overflow) - } - - // This function can only be used with non-accumulator addresses. Returns both new address and underflow - def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = { - require(isPow2(sp_bank_entries)) // TODO remove this requirement - require(isPow2(acc_bank_entries)) // TODO remove this requirement - - val underflow = data < (floor +& other) - - val result = WireInit(this) - result.data := Mux(underflow, floor, data - other) - - (result, underflow) - } - - def make_this_garbage(dummy: Int = 0): Unit = { - is_acc_addr := true.B - accumulate := true.B - read_full_acc_row := true.B - garbage_bit := 1.U - data := ~(0.U(maxAddrBits.W)) - } - -} - -object LocalAddr { - def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { - // This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience - // function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths - val result = WireInit(t.asTypeOf(local_addr_t)) - if (result.garbage_bit.getWidth > 0) result.garbage := 0.U - result - } - - def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { - // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage - // address - val result = WireInit(cast_to_local_addr(local_addr_t, t)) - result.is_acc_addr := false.B - result.accumulate := false.B - result.read_full_acc_row := false.B - - // assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses") - - result - } - - def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = { - // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage - // address - val result = WireInit(cast_to_local_addr(local_addr_t, t)) - result.is_acc_addr := true.B - result.accumulate := accumulate - result.read_full_acc_row := read_full - - // assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses") - - result - } - - def garbage_addr(local_addr_t: LocalAddr): LocalAddr = { - val result = Wire(chiselTypeOf(local_addr_t)) - result := DontCare - result.make_this_garbage() - result - } -} diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala b/arch/src/main/scala/framework/memdomain/frontend/MemController.scala new file mode 100644 index 00000000..fd570bdb --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/MemController.scala @@ -0,0 +1,168 @@ +package framework.memdomain.frontend + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.frontend.decoder.PostGDCmd +import freechips.rocketchip.tile._ +import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.memdomain.frontend.outside_channel.{MemLoader, MemStorer} +import framework.memdomain.frontend.cmd_channel.rs.MemReservationStation +import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO} +import framework.memdomain.utils.pmc.MemCyclePMC +import freechips.rocketchip.tilelink.TLEdgeOut +import freechips.rocketchip.rocket.TLBPTWIO +import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.balldomain.blink.{BankRead, BankWrite} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.memdomain.MemDomainParam + +/** + * MemController: Controller that encapsulates scratchpad and accumulator + * Provides DMA interface and Ball Domain interface + */ +@instantiable +class MemController(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public + val io = IO(new Bundle { + // Issue interface from global RS (single channel) + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries))) + + // Report completion to global RS (single channel) + val global_complete_o = Decoupled(new GlobalRsComplete(parameter.rob_entries)) + + // Bank read/write interface - used by load/store + val interdma = new Bundle { + + val bankRead = Vec( + parameter.bankNum, + Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum)) + ) + + val bankWrite = Vec( + parameter.bankNum, + Flipped(new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.bankNum + )) + ) + + } + + // DMA interface - used by Outer DRAM controller + val intradma = new Bundle { + + val read = new Bundle { + val req = Decoupled(new BBReadRequest()) + val resp = Flipped(Decoupled(new BBReadResponse(parameter.bankWidth))) + } + + val write = new Bundle { + val req = Decoupled(new BBWriteRequest(parameter.bankWidth)) + val resp = Flipped(Decoupled(new BBWriteResponse)) + } + + } + + // TLB interface - exposed externally for DMA modules (BBStreamReader/BBStreamWriter) + // TLB connection is managed internally, but interface needs to be exposed for external DMA + val tlb = Vec(2, Flipped(new BBTLBIO)) + + // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) + val ptw = Vec(1, new TLBPTWIO) + + // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) + val tlbExp = Vec(1, new BBTLBExceptionIO) + + // Busy signal + val busy = Output(Bool()) + }) + + val memDecoder: Instance[framework.memdomain.frontend.cmd_channel.decoder.MemDomainDecoder] = + Instantiate(new framework.memdomain.frontend.cmd_channel.decoder.MemDomainDecoder(parameter)) + val memRs: Instance[framework.memdomain.frontend.cmd_channel.rs.MemReservationStation] = + Instantiate(new framework.memdomain.frontend.cmd_channel.rs.MemReservationStation(parameter)) + val memLoader: Instance[framework.memdomain.frontend.outside_channel.MemLoader] = + Instantiate(new framework.memdomain.frontend.outside_channel.MemLoader(parameter)) + val memStorer: Instance[framework.memdomain.frontend.outside_channel.MemStorer] = + Instantiate(new framework.memdomain.frontend.outside_channel.MemStorer(parameter)) + + // TLB cluster - internal TLB management for DMA modules + // Supports 2 clients: BBStreamReader (client 1) and BBStreamWriter (client 0) + val tlbCluster = + Module(new BBTLBCluster(2, parameter.tlb_size, parameter.dma_maxbytes, use_shared_tlb = true)(edge, p)) + +// ----------------------------------------------------------------------------- +// Global RS -> MemDecoder +// ----------------------------------------------------------------------------- + memDecoder.io.raw_cmd_i.valid := io.global_issue_i.valid + memDecoder.io.raw_cmd_i.bits := io.global_issue_i.bits.cmd + io.global_issue_i.ready := memDecoder.io.raw_cmd_i.ready + +// ----------------------------------------------------------------------------- +// MemDecoder -> MemReservationStation +// ----------------------------------------------------------------------------- + // Connect decoded instruction and global rob_id + memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid + memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits + memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id + memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready + +// ----------------------------------------------------------------------------- +// MemReservationStation -> MemLoader/MemStorer +// ----------------------------------------------------------------------------- + memLoader.io.cmdReq <> memRs.io.issue_o.ld + memStorer.io.cmdReq <> memRs.io.issue_o.st + memRs.io.commit_i.ld <> memLoader.io.cmdResp + memRs.io.commit_i.st <> memStorer.io.cmdResp + +//----------------------------------------------------------------------------- +// PMC - Performance Monitor Counter +// ----------------------------------------------------------------------------- + val pmc: Instance[framework.memdomain.utils.pmc.MemCyclePMC] = + Instantiate(new framework.memdomain.utils.pmc.MemCyclePMC(parameter)) + pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire + pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits + pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire + pmc.io.stReq_i.bits := memRs.io.issue_o.st.bits + pmc.io.ldResp_o.valid := memLoader.io.cmdResp.fire + pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits + pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire + pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits +// + // Connect MemLoader and MemStorer to DMA interface + memLoader.io.dmaReq <> io.intradma.read.req + io.intradma.read.resp <> memLoader.io.dmaResp + memStorer.io.dmaReq <> io.intradma.write.req + io.intradma.write.resp <> memStorer.io.dmaResp + + // TLB connection - internal TLB cluster connected to external DMA modules + // Client 0: BBStreamWriter, Client 1: BBStreamReader + io.tlb <> tlbCluster.io.clients + + // PTW interface - connect to upper level page table walker + io.ptw <> tlbCluster.io.ptw + + // TLB exception interface - connect to upper level for flush handling + tlbCluster.io.exp <> io.tlbExp + + // Connect MemLoader and MemStorer to MemController's DMA interface + memLoader.io.bankWrite <> io.interdma.bankWrite + memStorer.io.bankRead <> io.interdma.bankRead + + // Completion signal connected to global RS + io.global_complete_o <> memRs.io.complete_o + + // Busy signal + // Simple busy signal + io.busy := !memRs.io.complete_o.ready +} diff --git a/arch/src/main/scala/framework/memdomain/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala similarity index 59% rename from arch/src/main/scala/framework/memdomain/DISA.scala rename to arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index c4365448..8aa457f9 100644 --- a/arch/src/main/scala/framework/memdomain/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -1,4 +1,4 @@ -package framework.memdomain +package framework.memdomain.frontend.cmd_channel.decoder import chisel3._ import chisel3.util._ @@ -6,12 +6,12 @@ import org.chipsalliance.cde.config.Parameters // import framework.ballcore.ballcore.RoCCCommandBB import freechips.rocketchip.tile._ - class BuckyballRawCmd(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand } object DISA { - val MVIN_BITPAT = BitPat("b0011000") // 24 - val MVOUT_BITPAT = BitPat("b0011001") // 25 + val MSET_BITPAT = BitPat("b0010111") // 23 + val MVIN_BITPAT = BitPat("b0011000") // 24 + val MVOUT_BITPAT = BitPat("b0011001") // 25 } diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala new file mode 100644 index 00000000..9d43d71f --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -0,0 +1,143 @@ +package framework.memdomain.frontend.cmd_channel.decoder + +import chisel3._ +import chisel3.util._ +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.decoder.PostGDCmd +import framework.memdomain.MemDomainParam +import framework.memdomain.frontend.cmd_channel.decoder.DISA._ +import freechips.rocketchip.tile._ +import org.chipsalliance.cde.config.Parameters +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +// Detailed decode output for Mem domain +class MemDecodeCmd(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { + val is_load = Bool() + val is_store = Bool() + // Memory address + val mem_addr = UInt(parameter.memAddrLen.W) + // Iteration count + val iter = UInt(10.W) + // Bank information + // 3 bits, supports 8 banks (SPAD+ACC) + val bank_id = UInt(log2Up(parameter.bankNum).W) + val special = UInt(40.W) +} + +// LS decode fields +object LSDecodeFields extends Enumeration { + type Field = Value + val LD_EN, ST_EN, MEMADDR, BANK_ID, ITER, SPECIAL, VALID = Value +} + +// Default constants for Mem decoder +object MemDefaultConstants { + val Y = true.B + val N = false.B + val DADDR = 0.U(14.W) + val DITER = 0.U(10.W) + val DSPECIAL = 0.U(40.W) +} + +@instantiable +class MemDomainDecoder(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + import MemDefaultConstants._ + + @public + val io = IO(new Bundle { + val raw_cmd_i = Flipped(Decoupled(new PostGDCmd)) + val mem_decode_cmd_o = Decoupled(new MemDecodeCmd(parameter)) + }) + + val bankAddrLen = log2Up(parameter.bankEntries) + val memAddrLen = parameter.memAddrLen + + // Only process Mem instructions + io.raw_cmd_i.ready := io.mem_decode_cmd_o.ready + + val func7 = io.raw_cmd_i.bits.raw_cmd.inst.funct + val rs1 = io.raw_cmd_i.bits.raw_cmd.rs1 + val rs2 = io.raw_cmd_i.bits.raw_cmd.rs2 + + // Load/Store instruction decoding + import LSDecodeFields._ + val ls_default_decode = List(N, N, DADDR, DADDR, DITER, DSPECIAL, N) + + val ls_decode_list = ListLookup( + func7, + ls_default_decode, + Array( + MSET_BITPAT -> List( + Y, + N, + rs1(memAddrLen - 1, 0), + rs2(bankAddrLen - 1, 0), + rs2(bankAddrLen + 9, bankAddrLen), + rs2(63, bankAddrLen + 10), + Y + ), // mset + MVIN_BITPAT -> List( + Y, + N, + rs1(memAddrLen - 1, 0), + rs2(bankAddrLen - 1, 0), + rs2(bankAddrLen + 9, bankAddrLen), + rs2(63, bankAddrLen + 10), + Y + ), // mvin + MVOUT_BITPAT -> List( + N, + Y, + rs1(memAddrLen - 1, 0), + rs2(bankAddrLen - 1, 0), + rs2(bankAddrLen + 9, bankAddrLen), + rs2(63, bankAddrLen + 10), + Y + ) // mvout + ) + ) + + assert( + !(io.raw_cmd_i.fire && !ls_decode_list(LSDecodeFields.VALID.id).asBool), + s"MemDomainDecoder: Invalid command opcode, func7 = 0x%x\n", + func7 + ) + +// ----------------------------------------------------------------------------- +// Output assignment +// ----------------------------------------------------------------------------- + io.mem_decode_cmd_o.valid := io.raw_cmd_i.valid && (io.raw_cmd_i.bits.domain_id === DomainId.MEM) + + io.mem_decode_cmd_o.bits.is_load := Mux( + io.mem_decode_cmd_o.valid, + ls_decode_list(LSDecodeFields.LD_EN.id).asBool, + false.B + ) + io.mem_decode_cmd_o.bits.is_store := Mux( + io.mem_decode_cmd_o.valid, + ls_decode_list(LSDecodeFields.ST_EN.id).asBool, + false.B + ) + io.mem_decode_cmd_o.bits.mem_addr := Mux( + io.mem_decode_cmd_o.valid, + ls_decode_list(LSDecodeFields.MEMADDR.id).asUInt, + 0.U(parameter.memAddrLen.W) + ) + io.mem_decode_cmd_o.bits.iter := Mux( + io.mem_decode_cmd_o.valid, + ls_decode_list(LSDecodeFields.ITER.id).asUInt, + 0.U(10.W) + ) + + // Address parsing + val ls_bank_id = ls_decode_list(LSDecodeFields.BANK_ID.id).asUInt + io.mem_decode_cmd_o.bits.bank_id := Mux(io.mem_decode_cmd_o.valid, ls_bank_id, 0.U(log2Up(parameter.bankNum).W)) + io.mem_decode_cmd_o.bits.special := Mux( + io.mem_decode_cmd_o.valid, + ls_decode_list(LSDecodeFields.SPECIAL.id).asUInt, + 0.U(40.W) + ) +} diff --git a/arch/src/main/scala/framework/memdomain/rs/README.md b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/README.md similarity index 100% rename from arch/src/main/scala/framework/memdomain/rs/README.md rename to arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/README.md diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala new file mode 100644 index 00000000..ee472f84 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala @@ -0,0 +1,111 @@ +package framework.memdomain.frontend.cmd_channel.rs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import org.chipsalliance.cde.config.Parameters +import framework.memdomain.MemDomainParam +import framework.memdomain.frontend.cmd_channel.decoder.MemDecodeCmd +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +// Mem domain issue interface - includes global rob_id +class MemRsIssue(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { + val cmd = new MemDecodeCmd(parameter) + // Global ROB ID + val rob_id = UInt(log2Up(parameter.rob_entries).W) +} + +// Mem domain completion interface +class MemRsComplete(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { + val rob_id = UInt(log2Up(parameter.rob_entries).W) +} + +// Mem domain issue interface combination (Load + Store) +class MemIssueInterface(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { + val ld = Decoupled(new MemRsIssue(parameter)) + val st = Decoupled(new MemRsIssue(parameter)) +} + +// Mem domain completion interface combination (Load + Store) +class MemCommitInterface(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { + val ld = Flipped(Decoupled(new MemRsComplete(parameter))) + val st = Flipped(Decoupled(new MemRsComplete(parameter))) +} + +// Local Mem reservation station - simple FIFO scheduler +@instantiable +class MemReservationStation(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public + val io = IO(new Bundle { + + // Decoded instruction input (with global rob_id) + val mem_decode_cmd_i = Flipped(new DecoupledIO(new Bundle { + val cmd = new MemDecodeCmd(parameter) + // Global ROB ID + val rob_id = UInt(log2Up(parameter.rob_entries).W) + })) + + // Rs -> MemLoader/MemStorer + val issue_o = new MemIssueInterface(parameter) + val commit_i = new MemCommitInterface(parameter) + + // Output completion signal (with global rob_id, single channel) + val complete_o = Decoupled(new MemRsComplete(parameter)) + }) + + // Simple FIFO queue, only for buffering + val fifo = Module(new Queue( + new Bundle { + val cmd = new MemDecodeCmd(parameter) + val rob_id = UInt(log2Up(parameter.rob_entries).W) + }, + entries = 4 + )) // Small buffer is sufficient + +// ----------------------------------------------------------------------------- +// Inbound - FIFO enqueue +// ----------------------------------------------------------------------------- + fifo.io.enq <> io.mem_decode_cmd_i + +// ----------------------------------------------------------------------------- +// Outbound - instruction issue (dispatch based on is_load/is_store) +// ----------------------------------------------------------------------------- + val headEntry = fifo.io.deq.bits + + // Load issue + io.issue_o.ld.valid := fifo.io.deq.valid && headEntry.cmd.is_load + io.issue_o.ld.bits.cmd := headEntry.cmd + io.issue_o.ld.bits.rob_id := headEntry.rob_id + + // Store issue + io.issue_o.st.valid := fifo.io.deq.valid && headEntry.cmd.is_store + io.issue_o.st.bits.cmd := headEntry.cmd + io.issue_o.st.bits.rob_id := headEntry.rob_id + + // FIFO deq.ready - can only dequeue when target unit is ready + fifo.io.deq.ready := + (headEntry.cmd.is_load && io.issue_o.ld.ready) || + (headEntry.cmd.is_store && io.issue_o.st.ready) + +// ----------------------------------------------------------------------------- +// Completion signal processing - directly forward to global RS +// ----------------------------------------------------------------------------- + val completeArb = Module(new Arbiter(UInt(log2Up(parameter.rob_entries).W), 2)) + + completeArb.io.in(0).valid := io.commit_i.ld.valid + completeArb.io.in(0).bits := io.commit_i.ld.bits.rob_id + io.commit_i.ld.ready := completeArb.io.in(0).ready + + completeArb.io.in(1).valid := io.commit_i.st.valid + completeArb.io.in(1).bits := io.commit_i.st.bits.rob_id + io.commit_i.st.ready := completeArb.io.in(1).ready + + // Forward completion signal (with global rob_id) + io.complete_o.valid := completeArb.io.out.valid + io.complete_o.bits.rob_id := completeArb.io.out.bits + completeArb.io.out.ready := io.complete_o.ready +} diff --git a/arch/src/main/scala/framework/memdomain/rs/ringFifo.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/ringFifo.scala similarity index 82% rename from arch/src/main/scala/framework/memdomain/rs/ringFifo.scala rename to arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/ringFifo.scala index 1d4cc1fb..15d37e94 100644 --- a/arch/src/main/scala/framework/memdomain/rs/ringFifo.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/ringFifo.scala @@ -1,4 +1,4 @@ -package framework.memdomain.rs +package framework.memdomain.frontend.cmd_channel.rs import chisel3._ import chisel3.util._ @@ -10,7 +10,7 @@ import chisel3.util._ class RingFifo[T <: Data](gen: T, n: Int) extends Module { require(n > 0, "FIFO size must be greater than 0") - val io = IO(new Bundle{ + val io = IO(new Bundle { // Flipped reverses the interface val enq = Flipped(new DecoupledIO(gen)) val deq = new DecoupledIO(gen) @@ -36,9 +36,16 @@ class RingFifo[T <: Data](gen: T, n: Int) extends Module { // Determine if it will be full next // Enqueue, and no dequeue, and stack will be full next - val isFullNext = Mux(doEnq && !doDeq && (enqPtrInc === deqPtr), - true.B , Mux(doDeq && isFull, // Dequeue, and full - false.B, isFull)) + val isFullNext = Mux( + doEnq && !doDeq && (enqPtrInc === deqPtr), + true.B, + Mux( + doDeq && isFull, // Dequeue, and full + false.B, + isFull + ) + ) + // Enqueue, change tail, add one element backward enqPtr := Mux(doEnq, enqPtrInc, enqPtr) // Dequeue, change head, head moves backward by one @@ -46,7 +53,7 @@ class RingFifo[T <: Data](gen: T, n: Int) extends Module { isFull := isFullNext val ram = Mem(n, gen) - when (doEnq){ + when(doEnq) { ram(enqPtr) := io.enq.bits } io.enq.ready := !isFull diff --git a/arch/src/main/scala/framework/memdomain/rs/rob.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala similarity index 67% rename from arch/src/main/scala/framework/memdomain/rs/rob.scala rename to arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala index b9776908..d6e24947 100644 --- a/arch/src/main/scala/framework/memdomain/rs/rob.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala @@ -1,28 +1,29 @@ -package framework.memdomain.rs +package framework.memdomain.frontend.cmd_channel.rs import chisel3._ import chisel3.util._ import chisel3.experimental._ import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.MemDecodeCmd +import framework.memdomain.MemDomainParam +import framework.memdomain.frontend.cmd_channel.decoder.MemDecodeCmd // ROB entry data structure - preserves ROB ID to support out-of-order completion -class RobEntry(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val cmd = new MemDecodeCmd - val rob_id = UInt(log2Up(b.rob_entries).W) +class RobEntry(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { + val cmd = new MemDecodeCmd(parameter) + val rob_id = UInt(log2Up(parameter.rob_entries).W) } -class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +class ROB(parameter: MemDomainParam)(implicit p: Parameters) extends Module { + val io = IO(new Bundle { // Allocation interface - val alloc = Flipped(new DecoupledIO(new MemDecodeCmd)) + val alloc = Flipped(new DecoupledIO(new MemDecodeCmd(parameter))) // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new RobEntry) + val issue = new DecoupledIO(new RobEntry(parameter)) // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(b.rob_entries).W))) + val complete = Flipped(new DecoupledIO(UInt(log2Up(parameter.rob_entries).W))) // Commit interface - commit completed head instruction // val commit = new DecoupledIO(new RobEntry) @@ -33,13 +34,13 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { }) // Only use FIFO + completion status table, only enqueue/dequeue, sequential execution and sequential completion - val robFifo = Module(new Queue(new RobEntry, b.rob_entries)) - val robIdCounter = RegInit(0.U(log2Up(b.rob_entries).W)) + val robFifo = Module(new Queue(new RobEntry(parameter), parameter.rob_entries)) + val robIdCounter = RegInit(0.U(log2Up(parameter.rob_entries).W)) // Initialize to false to avoid X states in FPGA - val robTable = RegInit(VecInit(Seq.fill(b.rob_entries)(false.B))) + val robTable = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) // Initialize completion status table - for (i <- 0 until b.rob_entries) { + for (i <- 0 until parameter.rob_entries) { when(reset.asBool) { robTable(i) := true.B } @@ -55,7 +56,7 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { io.alloc.ready := robFifo.io.enq.ready when(io.alloc.fire) { - robIdCounter := robIdCounter + 1.U + robIdCounter := robIdCounter + 1.U robTable(robIdCounter) := false.B } @@ -72,17 +73,16 @@ class ROB (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // ----------------------------------------------------------------------------- val headEntry = robFifo.io.deq.bits val headCompleted = robTable(headEntry.rob_id) - io.issue.valid := robFifo.io.deq.valid && !headCompleted - io.issue.bits := headEntry + io.issue.valid := robFifo.io.deq.valid && !headCompleted + io.issue.bits := headEntry robFifo.io.deq.ready := io.issue.ready && !headCompleted - // ----------------------------------------------------------------------------- // Status signals // ----------------------------------------------------------------------------- val isEmpty = robTable.reduce(_ && _) - val isFull = !robFifo.io.enq.ready + val isFull = !robFifo.io.enq.ready io.empty := isEmpty io.full := isFull diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala new file mode 100644 index 00000000..06fa0a88 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -0,0 +1,118 @@ +package framework.memdomain.frontend.outside_channel + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import framework.memdomain.MemDomainParam +import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} +import framework.memdomain.backend.banks.SramWriteIO +import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse} +import freechips.rocketchip.rocket.MStatus +import framework.balldomain.blink.BankWrite +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +@instantiable +class MemLoader(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + val rob_id_width = log2Up(parameter.rob_entries) + + @public + val io = IO(new Bundle { + // Load instruction from ReservationStation + val cmdReq = Flipped(Decoupled(new MemRsIssue(parameter))) + // Completion signal sent to ReservationStation + val cmdResp = Decoupled(new MemRsComplete(parameter)) + // Direct connection to DMA read interface + val dmaReq = Decoupled(new BBReadRequest()) + val dmaResp = Flipped(Decoupled(new BBReadResponse(parameter.bankWidth))) + + // Connected to Bank write interface + val bankWrite = Vec( + parameter.bankNum, + Flipped(new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.bankNum + )) + ) + + }) + + val s_idle :: s_dma_req :: s_dma_wait :: Nil = Enum(3) + val state = RegInit(s_idle) + + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + // Cache mem_addr + val mem_addr_reg = Reg(UInt(parameter.memAddrLen.W)) + // Cache iteration count + val iter_reg = Reg(UInt(10.W)) + // Count number of responses received, supports up to 16 responses + val resp_count = Reg(UInt(log2Up(16).W)) + + // Cache decoded bank information + val wr_bank_reg = Reg(UInt(log2Up(parameter.bankNum).W)) + // Cache stride + val stride_reg = Reg(UInt(10.W)) + + // Receive load instruction + io.cmdReq.ready := state === s_idle + + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { + state := s_dma_req + rob_id_reg := io.cmdReq.bits.rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + iter_reg := io.cmdReq.bits.cmd.iter + wr_bank_reg := io.cmdReq.bits.cmd.bank_id + stride_reg := io.cmdReq.bits.cmd.special(10, 0) + resp_count := 0.U + } + + // Issue DMA read request - read iter_reg rows of data + io.dmaReq.valid := state === s_dma_req + io.dmaReq.bits.vaddr := mem_addr_reg + // Byte count of iter rows of data + io.dmaReq.bits.len := iter_reg * (parameter.bankWidth / 8).U + // Simplified: use default status + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + io.dmaReq.bits.stride := stride_reg + + when(io.dmaReq.fire) { + state := s_dma_wait + // Reset response counter + resp_count := 0.U + } + + // Wait for DMA response + io.dmaResp.ready := state === s_dma_wait + + when(io.dmaResp.fire) { + resp_count := resp_count + 1.U + // Return to idle state when last response is received + when(io.dmaResp.bits.last) { + state := s_idle + } + } + + // Stream write to SRAM - write immediately upon receiving each response + // All responses write to the same bank, starting from row 0 + val target_bank = wr_bank_reg + val target_row = io.dmaResp.bits.addrcounter + + for (i <- 0 until parameter.bankNum) { + io.bankWrite(i).io.req.valid := io.dmaResp.fire && (target_bank === i.U) + io.bankWrite(i).io.req.bits.addr := target_row + io.bankWrite(i).io.req.bits.data := io.dmaResp.bits.data + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + io.bankWrite(i).io.req.bits.wmode := false.B // Load is always overwrite + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).bank_id := target_bank + } + + // Send completion signal - only send when last response is received + io.cmdResp.valid := io.dmaResp.fire && io.dmaResp.bits.last + io.cmdResp.bits.rob_id := rob_id_reg +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala new file mode 100644 index 00000000..1eff7865 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -0,0 +1,289 @@ +package framework.memdomain.frontend.outside_channel + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import framework.memdomain.MemDomainParam +import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} +import freechips.rocketchip.rocket.MStatus +import framework.memdomain.backend.banks.SramReadIO +import framework.memdomain.frontend.outside_channel.dma.{BBWriteRequest, BBWriteResponse} +import framework.balldomain.blink.BankRead +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} + +@instantiable +class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + val rob_id_width = log2Up(parameter.rob_entries) + // Byte count of one row of data + val line_bytes = parameter.bankWidth / 8 + // 16-byte alignment + val align_bytes = 16 + + @public + val io = IO(new Bundle { + // Store instruction from ReservationStation + val cmdReq = Flipped(Decoupled(new MemRsIssue(parameter))) + // Completion signal sent to ReservationStation + val cmdResp = Decoupled(new MemRsComplete(parameter)) + // Direct connection to DMA write interface + val dmaReq = Decoupled(new BBWriteRequest(parameter.bankWidth)) + val dmaResp = Flipped(Decoupled(new BBWriteResponse)) + + // Connected to Bank read interface + val bankRead = Vec( + parameter.bankNum, + Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum)) + ) + + }) + + val s_idle :: s_sram_req :: s_dma_wait :: Nil = Enum(3) + val state = RegInit(s_idle) + + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val mem_addr_reg = Reg(UInt(parameter.memAddrLen.W)) + val iter_reg = Reg(UInt(10.W)) + val sram_count = Reg(UInt(10.W)) + // Cache stride + val stride_reg = Reg(UInt(10.W)) + // Cache decoded bank information + val rd_bank_reg = Reg(UInt(log2Up(parameter.bankNum).W)) + + // Data buffer related registers + // 16-byte buffer + val data_buffer = Reg(UInt((align_bytes * 8).W)) + // Number of valid bytes in buffer + val buffer_valid_bytes = Reg(UInt(log2Ceil(align_bytes + 1).W)) + // Starting address corresponding to buffer + val buffer_start_addr = Reg(UInt(parameter.memAddrLen.W)) + + // Receive store instruction + io.cmdReq.ready := state === s_idle + + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { + state := s_sram_req + rob_id_reg := io.cmdReq.bits.rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + iter_reg := io.cmdReq.bits.cmd.iter + rd_bank_reg := io.cmdReq.bits.cmd.bank_id + sram_count := 0.U + stride_reg := io.cmdReq.bits.cmd.special(10, 0) + // Initialize buffer state + buffer_valid_bytes := 0.U + } + + // Stream read SRAM data + // All reads come from the same bank, starting from row 0 + val target_bank = rd_bank_reg + val target_row = sram_count + + for (i <- 0 until parameter.bankNum) { + io.bankRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) + io.bankRead(i).io.req.bits.addr := target_row + io.bankRead(i).io.req.bits.fromDMA := true.B + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).bank_id := target_bank + } + + // Bank response processing + val bank_resp_valid = io.bankRead.map(_.io.resp.valid).reduce(_ || _) + val bank_resp_data = Mux1H(io.bankRead.map(_.io.resp.valid), io.bankRead.map(_.io.resp.bits.data)) + + // Calculate memory address corresponding to current row + val current_mem_addr = + mem_addr_reg + sram_count(1, 0) * line_bytes.U + ((sram_count >> 2) << 2) * stride_reg * line_bytes.U + // Lower 4 bits of address, 0 when 16-byte aligned + val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) + val aligned_addr = Cat(current_mem_addr(parameter.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) + val is_aligned = addr_offset === 0.U + dontTouch(is_aligned) + dontTouch(aligned_addr) + + // Data merge logic (line_bytes = 16 bytes) + val incoming_data = bank_resp_data.asUInt + // Always 16 bytes + val incoming_bytes = 16.U + + // Data merged into buffer + val merged_data = Wire(UInt((align_bytes * 8).W)) + val total_valid_bytes = Wire(UInt(log2Ceil(align_bytes * 2).W)) + val is_last_iter = (sram_count >= (iter_reg - 1.U) && iter_reg > 0.U) || iter_reg === 0.U + + when(buffer_valid_bytes === 0.U) { + // Buffer is empty + when(addr_offset === 0.U) { + // Address is aligned, use data directly + merged_data := incoming_data + total_valid_bytes := incoming_bytes + }.otherwise { + // Address not aligned, first time: use low bits of new data as high bits of send data, pad low bits with 0 + val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) + merged_data := new_data_low << (addr_offset * 8.U) + total_valid_bytes := align_bytes.U + } + }.otherwise { + // Buffer has data, concatenate: low bits of new data as high bits + buffer data as low bits + val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) + merged_data := (new_data_low << (addr_offset * 8.U)) | data_buffer + // Always 16 bytes + total_valid_bytes := align_bytes.U + } + + // Send logic: except for last iteration, can always fill 16 bytes + val can_send_full_line = total_valid_bytes >= align_bytes.U + val send_bytes = Mux(can_send_full_line, align_bytes.U, total_valid_bytes) + + // Determine send address - always use aligned address + val send_addr = Mux( + buffer_valid_bytes === 0.U, + aligned_addr, + Cat(buffer_start_addr(parameter.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) + ) + + // DMA request logic + val should_send_normal = bank_resp_valid && can_send_full_line + val should_send_first_unaligned = bank_resp_valid && (buffer_valid_bytes === 0.U && addr_offset =/= 0.U) + val should_send_last = bank_resp_valid && is_last_iter && !can_send_full_line + val should_send = should_send_normal || should_send_first_unaligned || should_send_last + + // Add a flag to track whether all data has been processed + // Completion detection logic - supports two cases: + // 1. Clean data completion (fully aligned case) + val aligned_completion = buffer_valid_bytes === 0.U && is_last_iter + // 2. Remaining data needs to be sent (unaligned case) + // Has remaining data + val has_remaining_data_completion = buffer_valid_bytes > 0.U && is_last_iter + val unaligned_completion_final_send = has_remaining_data_completion && !bank_resp_valid + + // Generate mask + val send_mask = Wire(UInt(align_bytes.W)) + when(buffer_valid_bytes === 0.U && addr_offset =/= 0.U) { + // First unaligned: send high bits of new data, mask on high bits + val valid_bytes = align_bytes.U - addr_offset + // 0xFF00 (if addr_offset=8) + send_mask := ((1.U << valid_bytes) - 1.U) << addr_offset + }.elsewhen(buffer_valid_bytes > 0.U && can_send_full_line) { + // Middle concatenation: send full 16 bytes + send_mask := ~0.U(align_bytes.W) // 0xFFFF + }.elsewhen(unaligned_completion_final_send) { + // Last send remaining buffer data: buffer data in low bits + send_mask := (1.U << buffer_valid_bytes) - 1.U // 0x00FF + }.otherwise { + // Aligned case: full data + send_mask := ~0.U(align_bytes.W) // 0xFFFF + } + + // DMA request signal control logic - can only update when DMA is ready + val dma_req_valid_reg = RegInit(false.B) + val dma_req_vaddr_reg = RegInit(0.U(parameter.memAddrLen.W)) + val dma_req_data_reg = RegInit(0.U((align_bytes * 8).W)) + val dma_req_len_reg = RegInit(0.U(8.W)) + val dma_req_mask_reg = RegInit(0.U(align_bytes.W)) + val dma_req_status_reg = RegInit(0.U.asTypeOf(new MStatus)) + + // Calculate DMA request signals + val dma_req_valid_next = + (should_send || unaligned_completion_final_send) && (state === s_sram_req || state === s_dma_wait) + val dma_req_vaddr_next = Mux(unaligned_completion_final_send, buffer_start_addr, send_addr) + val dma_req_data_next = Mux(unaligned_completion_final_send, data_buffer, merged_data) + val dma_req_len_next = align_bytes.U + val dma_req_mask_next = Mux(unaligned_completion_final_send, (1.U << buffer_valid_bytes) - 1.U, send_mask) + val dma_req_status_next = 0.U.asTypeOf(new MStatus) + + // Only update registers when DMA is ready + when(io.dmaReq.ready) { + dma_req_valid_reg := dma_req_valid_next + dma_req_vaddr_reg := dma_req_vaddr_next + dma_req_data_reg := dma_req_data_next + dma_req_len_reg := dma_req_len_next + dma_req_mask_reg := dma_req_mask_next + dma_req_status_reg := dma_req_status_next + } + + // Connect to DMA interface + io.dmaReq.valid := dma_req_valid_reg + io.dmaReq.bits.vaddr := dma_req_vaddr_reg + io.dmaReq.bits.data := dma_req_data_reg + io.dmaReq.bits.len := dma_req_len_reg + io.dmaReq.bits.mask := dma_req_mask_reg + io.dmaReq.bits.status := dma_req_status_reg + + // Connect Bank response ready signal - based on DMA ready state + io.bankRead.foreach(_.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) + // State transition and counter update + when(io.bankRead.map(_.io.req.fire).reduce(_ || _)) { + state := s_dma_wait + } + + when(io.dmaReq.fire) { + when(!unaligned_completion_final_send) { + sram_count := sram_count + 1.U + } + + // Update buffer state + when(addr_offset =/= 0.U && bank_resp_valid) { + // Unaligned case: cache high bits of new data + // Cache is the high bits part + val remaining_bytes = align_bytes.U - addr_offset + data_buffer := incoming_data >> (addr_offset * 8.U) + buffer_valid_bytes := remaining_bytes + // Update buffer corresponding address (point to next 16-byte aligned address) + when(buffer_valid_bytes === 0.U) { + buffer_start_addr := aligned_addr + align_bytes.U + }.otherwise { + buffer_start_addr := buffer_start_addr + align_bytes.U + } + }.elsewhen(unaligned_completion_final_send) { + // Sent final remaining data, clear buffer + buffer_valid_bytes := 0.U + }.otherwise { + // In aligned case, if previous buffer data was merged and sent, need to clear buffer + when(buffer_valid_bytes > 0.U && can_send_full_line && bank_resp_valid) { + buffer_valid_bytes := 0.U + } + } + + // Fix state transition logic + when(unaligned_completion_final_send) { + // Only return to idle after unaligned_completion_final_send completes + state := s_idle + }.elsewhen(aligned_completion) { + // All data has been sent + state := s_idle + }.elsewhen(sram_count + 1.U >= iter_reg && iter_reg > 0.U) { + // Iteration ended, but there may still be buffer data to send + when(buffer_valid_bytes > 0.U) { + // Maintain state, wait for unaligned_completion_final_send + state := s_dma_wait + }.otherwise { + state := s_idle + } + }.elsewhen(iter_reg === 0.U) { + state := s_idle + }.otherwise { + state := s_sram_req + } + } + + // Wait for DMA to truly complete + io.dmaResp.ready := true.B + + // Fix completion signal logic - only issue completion signal after all data transfer is truly complete + val task_complete = RegInit(false.B) + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { + task_complete := false.B + }.elsewhen(io.dmaReq.fire && (unaligned_completion_final_send || aligned_completion)) { + task_complete := true.B + } + + io.cmdResp.valid := task_complete && (state === s_idle) + io.cmdResp.bits.rob_id := rob_id_reg + + // Reset flag after sending completion signal + when(io.cmdResp.fire) { + task_complete := false.B + } +} diff --git a/arch/src/main/scala/framework/memdomain/dma/DMA.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/DMA.scala similarity index 56% rename from arch/src/main/scala/framework/memdomain/dma/DMA.scala rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/DMA.scala index 48231f89..6b89c842 100644 --- a/arch/src/main/scala/framework/memdomain/dma/DMA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/DMA.scala @@ -1,4 +1,4 @@ -package framework.memdomain.dma +package framework.memdomain.frontend.outside_channel.dma import chisel3._ import chisel3.util._ @@ -11,32 +11,30 @@ import freechips.rocketchip.rocket.MStatus import freechips.rocketchip.rocket.constants.MemoryOpConstants import framework.builtin.util.Util._ -import framework.memdomain.tlb.BBTLBIO -import framework.memdomain.dma.LocalAddr - +import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO class BBReadRequest()(implicit p: Parameters) extends CoreBundle { - val vaddr = UInt(coreMaxAddrBits.W) + val vaddr = UInt(coreMaxAddrBits.W) // Read length (bytes) - val len = UInt(16.W) + val len = UInt(16.W) val status = new MStatus // Stride (bytes) val stride = UInt(10.W) } class BBReadResponse(dataWidth: Int) extends Bundle { - val data = UInt(dataWidth.W) - val last = Bool() + val data = UInt(dataWidth.W) + val last = Bool() val addrcounter = UInt(10.W) } class BBWriteRequest(dataWidth: Int)(implicit p: Parameters) extends CoreBundle { - val vaddr = UInt(coreMaxAddrBits.W) - val data = UInt(dataWidth.W) + val vaddr = UInt(coreMaxAddrBits.W) + val data = UInt(dataWidth.W) // Write length (bytes) - val len = UInt(16.W) + val len = UInt(16.W) // Byte mask - val mask = UInt((dataWidth / 8).W) + val mask = UInt((dataWidth / 8).W) val status = new MStatus } @@ -44,52 +42,62 @@ class BBWriteResponse extends Bundle { val done = Bool() } -class BBStreamReader(nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int) - (implicit p: Parameters) extends LazyModule { +class BBStreamReader( + nXacts: Int, + beatBits: Int, + maxBytes: Int, + dataWidth: Int +)( + implicit p: Parameters) + extends LazyModule { + val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "buckyball-stream-reader", sourceId = IdRange(0, nXacts)))))) + name = "buckyball-stream-reader", + sourceId = IdRange(0, nXacts) + ))))) lazy val module = new Impl + class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { val (tl, edge) = node.out(0) - val beatBytes = beatBits / 8 + val beatBytes = beatBits / 8 val io = IO(new Bundle { - val req = Flipped(Decoupled(new BBReadRequest())) - val resp = Decoupled(new BBReadResponse(dataWidth)) - val tlb = new BBTLBIO - val busy = Output(Bool()) + val req = Flipped(Decoupled(new BBReadRequest())) + val resp = Decoupled(new BBReadResponse(dataWidth)) + val tlb = new BBTLBIO + val busy = Output(Bool()) val flush = Input(Bool()) }) val s_idle :: s_req_new_block :: Nil = Enum(2) - val state = RegInit(s_idle) + val state = RegInit(s_idle) - val req = Reg(new BBReadRequest()) + val req = Reg(new BBReadRequest()) // Number of bytes requested val bytesRequested = Reg(UInt(16.W)) // Number of bytes received - val bytesReceived = Reg(UInt(16.W)) - val bytesLeft = req.len - bytesRequested + val bytesReceived = Reg(UInt(16.W)) + val bytesLeft = req.len - bytesRequested // Select request size - simplified version, fixed use of beatBytes - val read_size = minOf(beatBytes.U, bytesLeft) + val read_size = minOf(beatBytes.U, bytesLeft) val read_vaddr = req.vaddr + bytesRequested * req.stride // Track byte range corresponding to each request for correct last signal calculation // Starting byte position of current request val req_byte_start = Reg(UInt(16.W)) // Ending byte position of current request - val req_byte_end = Wire(UInt(16.W)) + val req_byte_end = Wire(UInt(16.W)) req_byte_end := req_byte_start + read_size // Transaction ID management - val xactBusy = RegInit(0.U(nXacts.W)) + val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) - val xactId = OHToUInt(xactOnehot) + val xactId = OHToUInt(xactOnehot) - val xactBusy_fire = WireInit(false.B) - val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) + val xactBusy_fire = WireInit(false.B) + val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) val xactBusy_remove = ~Mux(tl.d.fire, (1.U << tl.d.bits.source).asUInt, 0.U) xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt @@ -103,86 +111,84 @@ class BBStreamReader(nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int) // TLB processing pipeline - simplified based on Gemmini class TLBundleAWithInfo extends Bundle { - val tl_a = tl.a.bits.cloneType - val vaddr = Output(UInt(vaddrBits.W)) + val tl_a = tl.a.bits.cloneType + val vaddr = Output(UInt(vaddrBits.W)) val status = Output(new MStatus) } val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) - xactBusy_fire := untranslated_a.fire && state === s_req_new_block - untranslated_a.valid := state === s_req_new_block && !xactBusy.andR - untranslated_a.bits.tl_a := get - untranslated_a.bits.vaddr := read_vaddr + xactBusy_fire := untranslated_a.fire && state === s_req_new_block + untranslated_a.valid := state === s_req_new_block && !xactBusy.andR + untranslated_a.bits.tl_a := get + untranslated_a.bits.vaddr := read_vaddr untranslated_a.bits.status := req.status - - // Simplified: no retry mechanism, direct connection - val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) + val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a - io.tlb.req.valid := tlb_q.io.deq.fire - io.tlb.req.bits := DontCare - io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr + io.tlb.req.valid := tlb_q.io.deq.fire + io.tlb.req.bits := DontCare + io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr io.tlb.req.bits.tlb_req.passthrough := false.B - io.tlb.req.bits.tlb_req.size := 0.U - io.tlb.req.bits.tlb_req.cmd := M_XRD - io.tlb.req.bits.status := tlb_q.io.deq.bits.status + io.tlb.req.bits.tlb_req.size := 0.U + io.tlb.req.bits.tlb_req.cmd := M_XRD + io.tlb.req.bits.status := tlb_q.io.deq.bits.status - val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) + val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq translate_q.io.deq.ready := tl.a.ready || io.tlb.resp.miss // TileLink connection - tl.a.valid := translate_q.io.deq.valid - tl.a.bits := translate_q.io.deq.bits.tl_a + tl.a.valid := translate_q.io.deq.valid + tl.a.bits := translate_q.io.deq.bits.tl_a tl.a.bits.address := io.tlb.resp.paddr // Iteration counter for tracking number of requests - val iter_counter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) // Table for managing iteration counts val iter_mangage_table = RegInit(VecInit(Seq.fill(16)(0.U(10.W)))) // Iteration count management - update after each request - when (tl.a.fire) { - iter_counter := iter_counter + 1.U + when(tl.a.fire) { + iter_counter := iter_counter + 1.U iter_mangage_table(tl.a.bits.source) := iter_counter } // Response processing - io.resp.valid := tl.d.valid - io.resp.bits.data := tl.d.bits.data + io.resp.valid := tl.d.valid + io.resp.bits.data := tl.d.bits.data // Use source as address counter io.resp.bits.addrcounter := iter_mangage_table(tl.d.bits.source) // Fix last signal: calculate using received byte count // Total byte count after receiving current beat val resp_bytes_end = bytesReceived + beatBytes.U io.resp.bits.last := edge.last(tl.d) && (resp_bytes_end >= req.len) - tl.d.ready := io.resp.ready + tl.d.ready := io.resp.ready // Update received byte count - when (tl.d.fire) { + when(tl.d.fire) { bytesReceived := bytesReceived + beatBytes.U } // State machine io.req.ready := state === s_idle - io.busy := xactBusy.orR || (state =/= s_idle) + io.busy := xactBusy.orR || (state =/= s_idle) - when (io.req.fire) { - req := io.req.bits + when(io.req.fire) { + req := io.req.bits bytesRequested := 0.U // Reset received byte count - bytesReceived := 0.U + bytesReceived := 0.U // Reset iteration counter - iter_counter := 0.U - state := s_req_new_block + iter_counter := 0.U + state := s_req_new_block } - when (untranslated_a.fire) { + when(untranslated_a.fire) { // Use actual requested byte count bytesRequested := bytesRequested + read_size // Check if more requests need to be sent - when (bytesRequested + read_size >= req.len) { + when(bytesRequested + read_size >= req.len) { // All requests sent state := s_idle }.otherwise { @@ -191,44 +197,55 @@ class BBStreamReader(nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int) } } } + } // Convention: data is already aligned and has mask -class BBStreamWriter(nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int) - (implicit p: Parameters) extends LazyModule { +class BBStreamWriter( + nXacts: Int, + beatBits: Int, + maxBytes: Int, + dataWidth: Int +)( + implicit p: Parameters) + extends LazyModule { + val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "buckyball-stream-writer", sourceId = IdRange(0, nXacts)))))) + name = "buckyball-stream-writer", + sourceId = IdRange(0, nXacts) + ))))) lazy val module = new Impl + class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { val (tl, edge) = node.out(0) - val beatBytes = beatBits / 8 + val beatBytes = beatBits / 8 val io = IO(new Bundle { - val req = Flipped(Decoupled(new BBWriteRequest(dataWidth))) - val resp = Decoupled(new BBWriteResponse) - val tlb = new BBTLBIO - val busy = Output(Bool()) + val req = Flipped(Decoupled(new BBWriteRequest(dataWidth))) + val resp = Decoupled(new BBWriteResponse) + val tlb = new BBTLBIO + val busy = Output(Bool()) val flush = Input(Bool()) }) val s_idle :: s_writing :: Nil = Enum(2) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val req = Reg(new BBWriteRequest(dataWidth)) - val xactBusy = RegInit(0.U(nXacts.W)) + val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) - val xactId = OHToUInt(xactOnehot) + val xactId = OHToUInt(xactOnehot) - val xactBusy_fire = WireInit(false.B) - val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) + val xactBusy_fire = WireInit(false.B) + val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) val xactBusy_remove = ~Mux(tl.d.fire, (1.U << tl.d.bits.source).asUInt, 0.U) xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt // Simplified: data is already aligned, directly construct TileLink request val lg_beat_bytes = log2Ceil(beatBytes) - val use_put_full = req.mask === ~0.U(beatBytes.W) + val use_put_full = req.mask === ~0.U(beatBytes.W) val putFull = edge.Put( fromSource = xactId, @@ -249,55 +266,56 @@ class BBStreamWriter(nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int) // TLB processing pipeline class TLBundleAWithInfo extends Bundle { - val tl_a = tl.a.bits.cloneType - val vaddr = Output(UInt(vaddrBits.W)) + val tl_a = tl.a.bits.cloneType + val vaddr = Output(UInt(vaddrBits.W)) val status = Output(new MStatus) } val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) - xactBusy_fire := untranslated_a.fire - untranslated_a.valid := state === s_writing && !xactBusy.andR - untranslated_a.bits.tl_a := selected_put - untranslated_a.bits.vaddr := req.vaddr + xactBusy_fire := untranslated_a.fire + untranslated_a.valid := state === s_writing && !xactBusy.andR + untranslated_a.bits.tl_a := selected_put + untranslated_a.bits.vaddr := req.vaddr untranslated_a.bits.status := req.status - val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) + val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a - io.tlb.req.valid := tlb_q.io.deq.valid - io.tlb.req.bits := DontCare - io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr + io.tlb.req.valid := tlb_q.io.deq.valid + io.tlb.req.bits := DontCare + io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr io.tlb.req.bits.tlb_req.passthrough := false.B - io.tlb.req.bits.tlb_req.size := 0.U - io.tlb.req.bits.tlb_req.cmd := M_XWR - io.tlb.req.bits.status := tlb_q.io.deq.bits.status + io.tlb.req.bits.tlb_req.size := 0.U + io.tlb.req.bits.tlb_req.cmd := M_XWR + io.tlb.req.bits.status := tlb_q.io.deq.bits.status - val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) + val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq translate_q.io.deq.ready := tl.a.ready || io.tlb.resp.miss // TileLink connection - tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss - tl.a.bits := translate_q.io.deq.bits.tl_a + tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss + tl.a.bits := translate_q.io.deq.bits.tl_a tl.a.bits.address := io.tlb.resp.paddr tl.d.ready := true.B // Response processing - io.resp.valid := tl.d.valid && edge.last(tl.d) + io.resp.valid := tl.d.valid && edge.last(tl.d) io.resp.bits.done := true.B // State machine io.req.ready := state === s_idle - io.busy := xactBusy.orR || (state =/= s_idle) + io.busy := xactBusy.orR || (state =/= s_idle) - when (io.req.fire) { - req := io.req.bits + when(io.req.fire) { + req := io.req.bits state := s_writing } - when (untranslated_a.fire) { + when(untranslated_a.fire) { state := s_idle } } + } diff --git a/arch/src/main/scala/framework/memdomain/dma/README.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/README.md similarity index 100% rename from arch/src/main/scala/framework/memdomain/dma/README.md rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/README.md diff --git a/arch/src/main/scala/framework/memdomain/tlb/BBTLB.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLB.scala similarity index 61% rename from arch/src/main/scala/framework/memdomain/tlb/BBTLB.scala rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLB.scala index c5bf3391..ddf91fec 100644 --- a/arch/src/main/scala/framework/memdomain/tlb/BBTLB.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLB.scala @@ -1,4 +1,4 @@ -package framework.memdomain.tlb +package framework.memdomain.frontend.outside_channel.tlb import chisel3._ import chisel3.util._ @@ -12,36 +12,36 @@ import framework.builtin.util.Util._ class BBTLBReq(val lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle { val tlb_req = new TLBReq(lgMaxSize) - val status = new MStatus + val status = new MStatus } class BBTLBExceptionIO extends Bundle { - val interrupt = Output(Bool()) + val interrupt = Output(Bool()) val flush_retry = Input(Bool()) - val flush_skip = Input(Bool()) + val flush_skip = Input(Bool()) def flush(dummy: Int = 0): Bool = flush_retry || flush_skip } -class BBTLB(entries: Int, maxSize: Int)(implicit edge: TLEdgeOut, p: Parameters) - extends CoreModule { +class BBTLB(entries: Int, maxSize: Int)(implicit val edge: TLEdgeOut, p: Parameters) extends CoreModule { val lgMaxSize = log2Ceil(maxSize) + val io = IO(new Bundle { - val req = Flipped(Valid(new BBTLBReq(lgMaxSize))) + val req = Flipped(Valid(new BBTLBReq(lgMaxSize))) val resp = new TLBResp - val ptw = new TLBPTWIO - val exp = new BBTLBExceptionIO + val ptw = new TLBPTWIO + val exp = new BBTLBExceptionIO }) val interrupt = RegInit(false.B) io.exp.interrupt := interrupt - val tlb = Module(new TLB(false, lgMaxSize, TLBConfig(nSets=1, nWays=entries))) + val tlb = Module(new TLB(false, lgMaxSize, TLBConfig(nSets = 1, nWays = entries))) tlb.io.req.valid := io.req.valid - tlb.io.req.bits := io.req.bits.tlb_req - io.resp := tlb.io.resp - tlb.io.kill := false.B + tlb.io.req.bits := io.req.bits.tlb_req + io.resp := tlb.io.resp + tlb.io.kill := false.B tlb.io.sfence.valid := io.exp.flush() tlb.io.sfence.bits.rs1 := false.B @@ -54,19 +54,21 @@ class BBTLB(entries: Int, maxSize: Int)(implicit edge: TLEdgeOut, p: Parameters) io.ptw <> tlb.io.ptw tlb.io.ptw.status := io.req.bits.status - val exception = io.req.valid && Mux(io.req.bits.tlb_req.cmd === M_XRD, + val exception = io.req.valid && Mux( + io.req.bits.tlb_req.cmd === M_XRD, tlb.io.resp.pf.ld || tlb.io.resp.ae.ld || tlb.io.resp.gf.ld, - tlb.io.resp.pf.st || tlb.io.resp.ae.st || tlb.io.resp.gf.st) + tlb.io.resp.pf.st || tlb.io.resp.ae.st || tlb.io.resp.gf.st + ) - when (exception) { + when(exception) { interrupt := true.B } - when (interrupt && io.exp.flush_skip) { + when(interrupt && io.exp.flush_skip) { interrupt := false.B } - when (interrupt && io.exp.flush_retry) { + when(interrupt && io.exp.flush_retry) { interrupt := false.B } diff --git a/arch/src/main/scala/framework/memdomain/tlb/README.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/README.md similarity index 100% rename from arch/src/main/scala/framework/memdomain/tlb/README.md rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/README.md diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala new file mode 100644 index 00000000..18c60355 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala @@ -0,0 +1,89 @@ +package framework.memdomain.frontend.outside_channel.tlb + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile.{CoreBundle, CoreModule} +import freechips.rocketchip.tilelink.TLEdgeOut + +class BBTLBIO(implicit p: Parameters) extends CoreBundle { + val lgMaxSize = log2Ceil(coreDataBytes) + val req = Valid(new BBTLBReq(lgMaxSize)) + val resp = Flipped(new TLBResp) +} + +class BBTLBCluster( + nClients: Int, + entries: Int, + maxSize: Int, + use_shared_tlb: Boolean = true +)( + implicit val edge: TLEdgeOut, + p: Parameters) + extends CoreModule { + + val num_tlbs = if (use_shared_tlb) 1 else nClients + val lgMaxSize = log2Ceil(coreDataBytes) + + val io = IO(new Bundle { + val clients = Flipped(Vec(nClients, new BBTLBIO)) + val ptw = Vec(num_tlbs, new TLBPTWIO) + val exp = Vec(num_tlbs, new BBTLBExceptionIO) + }) + + val tlbs = Seq.fill(num_tlbs)(Module(new BBTLB(entries, maxSize))) + + io.ptw <> VecInit(tlbs.map(_.io.ptw)) + io.exp <> VecInit(tlbs.map(_.io.exp)) + + val tlbArbOpt = if (use_shared_tlb) Some(Module(new RRArbiter(new BBTLBReq(lgMaxSize), nClients))) else None + + if (use_shared_tlb) { + val tlbArb = tlbArbOpt.get + val tlb = tlbs.head + tlb.io.req.valid := tlbArb.io.out.valid + tlb.io.req.bits := tlbArb.io.out.bits + tlbArb.io.out.ready := true.B + } + + io.clients.zipWithIndex.foreach { + case (client, i) => + val last_translated_valid = RegInit(false.B) + val last_translated_vpn = RegInit(0.U(vaddrBits.W)) + val last_translated_ppn = RegInit(0.U(paddrBits.W)) + + val l0_tlb_hit = + last_translated_valid && ((client.req.bits.tlb_req.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt) + val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.tlb_req.vaddr(pgIdxBits - 1, 0)) + + val tlb = if (use_shared_tlb) tlbs.head else tlbs(i) + val tlbReq = if (use_shared_tlb) tlbArbOpt.get.io.in(i).bits else tlb.io.req.bits + val tlbReqValid = if (use_shared_tlb) tlbArbOpt.get.io.in(i).valid else tlb.io.req.valid + val tlbReqFire = if (use_shared_tlb) tlbArbOpt.get.io.in(i).fire else tlb.io.req.fire + + val l0_tlb_paddr_reg = RegEnable(client.req.bits.tlb_req.vaddr, client.req.valid) + + tlbReqValid := RegNext(client.req.valid && !l0_tlb_hit) + tlbReq := RegNext(client.req.bits) + + when(tlbReqFire && !tlb.io.resp.miss) { + last_translated_valid := true.B + last_translated_vpn := tlbReq.tlb_req.vaddr + last_translated_ppn := tlb.io.resp.paddr + } + + when(tlb.io.exp.flush()) { + last_translated_valid := false.B + } + + when(tlbReqFire) { + client.resp := tlb.io.resp + }.otherwise { + client.resp := DontCare + client.resp.paddr := RegNext(l0_tlb_paddr) + client.resp.miss := !RegNext(l0_tlb_hit) + } + } +} diff --git a/arch/src/main/scala/framework/memdomain/tlb/spec-BBTLB.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLB.md similarity index 100% rename from arch/src/main/scala/framework/memdomain/tlb/spec-BBTLB.md rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLB.md diff --git a/arch/src/main/scala/framework/memdomain/tlb/spec-BBTLBCluster.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLBCluster.md similarity index 100% rename from arch/src/main/scala/framework/memdomain/tlb/spec-BBTLBCluster.md rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLBCluster.md diff --git a/arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala b/arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala deleted file mode 100644 index dff1124c..00000000 --- a/arch/src/main/scala/framework/memdomain/mem/AccMonitor.scala +++ /dev/null @@ -1,165 +0,0 @@ -package framework.memdomain.mem - -import chisel3._ -import chisel3.util._ - -import framework.builtin.util.Util._ - -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} - -class AccMonitorWriteIO(n: Int, w: Int, mask_len: Int)(implicit b: CustomBuckyballConfig, p: Parameters)extends Bundle { - val io = new SramWriteIO(n, w, mask_len) - - val rob_id = Input(UInt(log2Up(b.rob_entries).W)) - val is_acc = Input(Bool()) - val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) -} - -class AccMonitorReadIO(n: Int, w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle{ - val io = new SramReadIO(n, w) - - val rob_id = Input(UInt(log2Up(b.rob_entries).W)) - val is_acc = Input(Bool()) - val bank_id = Input(UInt(log2Up(b.sp_banks+b.acc_banks).W)) -} - -class AccPipe(val n: Int, val w: Int, val mask_len: Int) (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new Bundle { - val write_in = new AccMonitorWriteIO(n, w, mask_len) // outer —> Acc - val read = Flipped(new AccMonitorReadIO(n, w)) // Acc <—> SramBank - val write_out = Flipped(new SramWriteIO(n, w, mask_len)) // Acc —> SramBank - }) - - // Pipeline registers - val valid_reg = RegInit(false.B) - val addr_reg = RegInit(0.U(log2Ceil(n).W)) - val data_reg = RegInit(0.U(w.W)) - val mask_reg = RegInit(VecInit(Seq.fill(mask_len)(false.B))) - - // Default/forward metadata (so it's always driven) - io.read.rob_id := io.write_in.rob_id - io.read.is_acc := io.write_in.is_acc - io.read.bank_id := io.write_in.bank_id - - - when (io.write_in.is_acc || RegNext(io.write_in.is_acc)) { -// ----------------------------------------------------------------------------- -// exec->AccPipe->SramBank -// ----------------------------------------------------------------------------- - // Stage 1: Read request - io.read.io.req.valid := io.write_in.io.req.valid - io.read.io.req.bits.addr := io.write_in.io.req.bits.addr - // AccPipe read is not from DMA - io.read.io.req.bits.fromDMA := false.B - valid_reg := io.write_in.io.req.valid - addr_reg := io.write_in.io.req.bits.addr - data_reg := io.write_in.io.req.bits.data - mask_reg := io.write_in.io.req.bits.mask - - // Stage 2: Accumulate (when read data is ready) - val acc_data = WireDefault(0.U(w.W)) - when (valid_reg && io.read.io.resp.valid) { - acc_data := data_reg + io.read.io.resp.bits.data - }.otherwise { - acc_data := data_reg - } - - // Stage 3: Write back - io.write_out.req.valid := valid_reg && io.read.io.resp.valid - io.write_out.req.bits.addr := addr_reg - io.write_out.req.bits.data := acc_data - io.write_out.req.bits.mask := mask_reg - - // Backpressure - io.write_in.io.req.ready := io.read.io.req.ready - io.read.io.resp.ready := io.write_out.req.ready - }.otherwise { -// ----------------------------------------------------------------------------- -// main->SramBank -// ----------------------------------------------------------------------------- - io.read.io.req.valid := false.B - io.read.io.req.bits.addr := 0.U(log2Ceil(n).W) - io.read.io.req.bits.fromDMA := false.B - - io.write_out.req.valid := io.write_in.io.req.valid - io.write_out.req.bits.addr := io.write_in.io.req.bits.addr - io.write_out.req.bits.data := io.write_in.io.req.bits.data - io.write_out.req.bits.mask := io.write_in.io.req.bits.mask - - io.write_in.io.req.ready := io.write_out.req.ready - io.read.io.resp.ready := false.B - } -} - - -class AccReadRouter(val n: Int, val w: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new Bundle { - val read_in1 = new AccMonitorReadIO(n, w) - val read_in2 = new AccMonitorReadIO(n, w) - val read_out = Flipped(new SramReadIO(n, w)) - }) - -// ----------------------------------------------------------------------------- -// Arbiter - use two Arbiters to handle req and resp separately -// ----------------------------------------------------------------------------- - // Priority arbiter, read_in2 has index 0 for higher priority - val req_arbiter = Module(new Arbiter(new SramReadReq(n), 2)) - req_arbiter.io.in(0) <> io.read_in2.io.req - req_arbiter.io.in(1) <> io.read_in1.io.req - io.read_out.req <> req_arbiter.io.out - - // Response distributor: record which input initiated the request - val resp_to_in1 = RegNext(req_arbiter.io.chosen === 1.U && req_arbiter.io.out.fire, false.B) - val resp_to_in2 = RegNext(req_arbiter.io.chosen === 0.U && req_arbiter.io.out.fire, false.B) - - // Response distribution - io.read_in1.io.resp.valid := io.read_out.resp.valid && resp_to_in1 - io.read_in1.io.resp.bits := io.read_out.resp.bits - io.read_in2.io.resp.valid := io.read_out.resp.valid && resp_to_in2 - io.read_in2.io.resp.bits := io.read_out.resp.bits - - // Response ready signal - io.read_out.resp.ready := - (resp_to_in1 && io.read_in1.io.resp.ready) || - (resp_to_in2 && io.read_in2.io.resp.ready) - - assert(!(io.read_in1.io.req.valid && io.read_in2.io.req.valid), "[AccBank Router]: Read requests is not allowed at the same time") -} - - -class AccMonitor(n: Int, w: Int, aligned_to: Int, single_ported: Boolean) (implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val mask_len = (w / (aligned_to * 8)) max 1 - val mask_elem = UInt((w min (aligned_to * 8)).W) - - val io = IO(new Bundle { - val read = new AccMonitorReadIO(n, w) - val write = new AccMonitorWriteIO(n, w, mask_len) - }) - - val sram = Module(new SramBank(n, w, aligned_to, single_ported)) - val pipe = Module(new AccPipe(n, w, mask_len)) - val read_router = Module(new AccReadRouter(n, w)) - -// ----------------------------------------------------------------------------- -// Write request enters pipeline -// ----------------------------------------------------------------------------- - pipe.io.write_in <> io.write - -// ----------------------------------------------------------------------------- -// Read request arbitration -// ----------------------------------------------------------------------------- - read_router.io.read_in1 <> pipe.io.read - read_router.io.read_in2 <> io.read - - // Connect AccRouter output to SramBank - sram.io.read <> read_router.io.read_out - -// ----------------------------------------------------------------------------- -// Pipeline output connected to underlying SRAM write port -// ----------------------------------------------------------------------------- - sram.io.write <> pipe.io.write_out - -} diff --git a/arch/src/main/scala/framework/memdomain/mem/README.md b/arch/src/main/scala/framework/memdomain/mem/README.md deleted file mode 100644 index 3678ed63..00000000 --- a/arch/src/main/scala/framework/memdomain/mem/README.md +++ /dev/null @@ -1,121 +0,0 @@ -# Memory Domain Modules - -Core memory building blocks for Buckyball, located at `arch/src/main/scala/framework/memdomain/mem`. This directory provides single-ported SRAM banks, an accumulation monitor around the bank, and a multi-bank scratchpad with request arbitration. - -## Modules - -- **SramBank**: Single-ported synchronous SRAM bank with 1-cycle read latency and write-ready arbitration. -- **AccMonitor**: Wraps a `SramBank` with an accumulation pipeline (`AccPipe`) and a read router (`AccReadRouter`). Supports read-modify-write when `is_acc` is asserted. -- **Scratchpad**: Instantiates one `AccMonitor` per bank and arbitrates between DMA and execution-unit (exec) traffic. - -## File Layout - -``` -mem/ -├── SramBank.scala # Basic single-ported SRAM bank -├── AccMonitor.scala # Accumulate pipeline + read router around SRAM -└── Scratchpad.scala # Multi-bank manager and request arbitration -``` - -## Configuration - -All modules are parameterized via `examples.BuckyballConfigs.CustomBuckyballConfig` and `org.chipsalliance.cde.config.Parameters`: - -- Bank count: `b.sp_banks`, `b.acc_banks` -- Entries per bank: `b.spad_bank_entries` -- Data width: `b.spad_w` -- Alignment: `b.aligned_to` -- Single-ported banks: `b.sp_singleported` (must be true; enforced by assertion in `Scratchpad`) - ---- - -## SramBank - -### Interface - -```scala -class SramReadReq(val n: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) - val fromDMA = Bool() -} - -class SramReadResp(val w: Int) extends Bundle { - val data = UInt(w.W) - val fromDMA = Bool() -} - -class SramWriteReq(val n: Int, val w: Int, val mask_len: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) - val mask = Vec(mask_len, Bool()) - val data = UInt(w.W) -} -``` - -### Behavior - -- Single-ported arbitration: `assert(!(io.read.req.valid && io.write.req.valid))` forbids same-cycle read+write. -- Handshake: `io.read.req.ready := !io.write.req.valid`, `io.write.req.ready := !io.read.req.valid`. -- Read latency: 1 cycle; `resp.valid := RegNext(io.read.req.fire)`, `resp.bits.data := mem.read(addr, ren).asUInt`. -- Write: stores `data` as a `Vec(mask_len, mask_elem)`. Current implementation writes all lanes; per-bit mask can be added in future. - ---- - -## AccMonitor - -`AccMonitor(n, w, aligned_to, single_ported)` composes: - -- `SramBank`: underlying single-ported storage. -- `AccPipe`: 3-stage read–accumulate–write pipeline when `is_acc` is asserted. -- `AccReadRouter`: 2-input arbiter for read requests and response distribution. - -### AccPipe - -- Trigger: pipeline active when `io.write_in.is_acc || RegNext(io.write_in.is_acc)`. -- Stage 1 (Read issue): forwards `addr` and sets `fromDMA := false.B`. -- Stage 2 (Accumulate): if `valid_reg && io.read.io.resp.valid`, compute `acc_data := data_reg + resp.data`; otherwise pass through `data_reg`. -- Stage 3 (Write back): issues write with `acc_data`, preserving `addr` and `mask`. -- Bypass: if not accumulating, write requests pass through directly to SRAM. -- Backpressure: `write_in.ready` mirrors `read.req.ready`; `read.resp.ready` mirrors `write_out.req.ready`. - -### AccReadRouter - -- Request arbitration: 2-way `Arbiter[SramReadReq]`, with input 0 (second client) prioritized. -- Response routing: captures `req_arbiter.io.chosen` to send `resp` to the initiating client. -- Ready: `read_out.resp.ready` is high when the selected client is ready. -- Safety: `assert(!(io.read_in1.io.req.valid && io.read_in2.io.req.valid))`. - ---- - -## Scratchpad - -- Banks: `numBanks = b.sp_banks + b.acc_banks`; instantiates `AccMonitor` per bank. -- Read arbitration per bank: priority `exec` > `dma`. - - Select: `exec_read_sel = exec_read_req.valid`; `main_read_sel = main_read_req.valid && !exec_read_sel`. - - Response distribution: records which client fired, then forwards `resp` accordingly. - - Ready: bank `resp.ready` is the OR of the selected client's ready. -- Write arbitration per bank: priority `exec` > `dma`; muxes `addr`, `data`, `mask` and metadata (`is_acc`, `bank_id`, `rob_id`). -- Metadata: read-side metadata is tied off (`rob_id := 0.U`, `is_acc := false.B`, `bank_id := i.U`). -- Assertions: - - `assert(b.sp_singleported)` — Scratchpad expects single-ported SRAM. - - `assert(!(exec_read_req.valid && exec_write.io.req.valid))` — exec read and write cannot target the same bank simultaneously. - ---- - -## Key Guarantees & Notes - -1. **Single-Port Discipline**: No same-cycle read/write in `SramBank`; higher layers arbitrate accordingly. -2. **Priority Policy**: `exec` traffic wins over `dma` for both reads and writes; `AccReadRouter` prioritizes its second input. -3. **Accumulation Semantics**: When `is_acc` is asserted, writes become read-modify-write with `+` over the fetched word. -4. **Masking**: Write requests carry a mask vector; current `SramBank` implementation writes all lanes and can be extended to honor per-bit masks. -5. **Latency**: Reads have 1-cycle latency from `req.fire` to `resp.valid`; accumulation path adds pipeline staging. -6. **Parameterization**: Widths, depths, and counts come from config; ensure `w` and `aligned_to` satisfy `require(w % aligned_to == 0 || w < aligned_to)`. - ---- - -## Where to Look - -- Bank implementation: `SramBank.scala` -- Accumulate pipeline & router: `AccMonitor.scala` -- Multi-bank arbitration & top-level wiring: `Scratchpad.scala` - -These modules are designed to be composed cleanly with Chisel handshakes and explicit assertions to catch illegal concurrent accesses. diff --git a/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala b/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala deleted file mode 100644 index f7d6a13f..00000000 --- a/arch/src/main/scala/framework/memdomain/mem/Scratchpad.scala +++ /dev/null @@ -1,118 +0,0 @@ -package framework.memdomain.mem - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ - -import framework.builtin.util.Util._ -import examples.BuckyballConfigs.CustomBuckyballConfig - -import framework.memdomain.mem.AccMonitor -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} - - -class Scratchpad(implicit b: CustomBuckyballConfig, implicit val p: Parameters) - extends Module with HasCoreParameters { - - // Assertion: ensure configuration consistency - assert(b.sp_singleported, "Scratchpad expects single-ported SRAM banks") - private val numBanks = b.sp_banks + b.acc_banks - val io = IO(new Bundle { - // SRAM read/write interface - used by load/store - val dma = new Bundle { - val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) - val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - } - // Execution unit read/write interface - one read and write per bank, OpA and OpB guaranteed to access different banks - val exec = new Bundle { - val sramread = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) - val sramwrite = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - } - }) - -// ----------------------------------------------------------------------------- -// Scratchpad -// ----------------------------------------------------------------------------- - - // SRAM banks - each bank has only one port, supports simultaneous read and write - val spad_mems = Seq.fill(numBanks) { Module(new AccMonitor( - b.spad_bank_entries, b.spad_w, - // Use configuration parameters - b.aligned_to, b.sp_singleported - )) } - - // Request arbitration and connection for each bank - spad_mems.zipWithIndex.foreach { case (bank, i) => - - // All read request sources - val main_read_req = io.dma.sramread(i).io.req - val exec_read_req = io.exec.sramread(i).io.req - - // All write request sources - val main_write = io.dma.sramwrite(i) - val exec_write = io.exec.sramwrite(i) - - // Assertion: OpA and OpB should not access the same bank simultaneously - assert(!(exec_read_req.valid && exec_write.io.req.valid), - s"Bank ${i}: exec and write cannot access the same bank simultaneously") - - // Read request arbitration: priority exec > main - val exec_read_sel = exec_read_req.valid - val main_read_sel = main_read_req.valid && !exec_read_sel - - // Write request arbitration: exec has higher priority - val exec_write_sel = exec_write.io.req.valid - - val main_isacc_sel = main_write.is_acc - val exec_isacc_sel = exec_write.is_acc - - val main_bankid = main_write.bank_id - val exec_bankid = exec_write.bank_id - - val main_robid = main_write.rob_id - val exec_robid = exec_write.rob_id - - // Connect read request to SramBank - bank.io.read.io.req.valid := exec_read_sel || main_read_sel - bank.io.read.io.req.bits := Mux(exec_read_sel, exec_read_req.bits, main_read_req.bits) - - // Read request ready reverse connection - main_read_req.ready := main_read_sel && bank.io.read.io.req.ready - exec_read_req.ready := exec_read_sel && bank.io.read.io.req.ready - - // Record which client initiated read request (for response distribution) - val resp_to_main = RegNext(main_read_sel && bank.io.read.io.req.fire, false.B) - val resp_to_exec = RegNext(exec_read_sel && bank.io.read.io.req.fire, false.B) - - // Read response distribution - io.dma.sramread(i).io.resp.valid := bank.io.read.io.resp.valid && resp_to_main - io.dma.sramread(i).io.resp.bits := bank.io.read.io.resp.bits - - io.exec.sramread(i).io.resp.valid := bank.io.read.io.resp.valid && resp_to_exec - io.exec.sramread(i).io.resp.bits := bank.io.read.io.resp.bits - - // Read response ready signal: either client ready is sufficient - bank.io.read.io.resp.ready := - (resp_to_main && io.dma.sramread(i).io.resp.ready) || - (resp_to_exec && io.exec.sramread(i).io.resp.ready) - - // Connect write request to SramBank - bank.io.write.io.req.valid := Mux(exec_write_sel, exec_write.io.req.valid, main_write.io.req.valid) - bank.io.write.io.req.bits.addr := Mux(exec_write_sel, exec_write.io.req.bits.addr, main_write.io.req.bits.addr) - bank.io.write.io.req.bits.data := Mux(exec_write_sel, exec_write.io.req.bits.data, main_write.io.req.bits.data) - bank.io.write.io.req.bits.mask := Mux(exec_write_sel, exec_write.io.req.bits.mask, main_write.io.req.bits.mask) - bank.io.write.is_acc := Mux(exec_write_sel, exec_isacc_sel, false.B) - bank.io.write.bank_id := Mux(exec_write_sel, exec_bankid, main_bankid) - bank.io.write.rob_id := Mux(exec_write_sel, exec_robid, main_robid) - - // Write request ready reverse connection - main_write.io.req.ready := !exec_write_sel && bank.io.write.io.req.ready - exec_write.io.req.ready := exec_write_sel && bank.io.write.io.req.ready - - // Tie-off read metadata (unused for now) - bank.io.read.rob_id := 0.U - bank.io.read.is_acc := false.B - bank.io.read.bank_id := i.U - } -} diff --git a/arch/src/main/scala/framework/memdomain/mem/SramBank.scala b/arch/src/main/scala/framework/memdomain/mem/SramBank.scala deleted file mode 100644 index 152a98a1..00000000 --- a/arch/src/main/scala/framework/memdomain/mem/SramBank.scala +++ /dev/null @@ -1,83 +0,0 @@ -package framework.memdomain.mem - -import chisel3._ -import chisel3.util._ - -import framework.builtin.util.Util._ - -class SramReadReq(val n: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) - val fromDMA = Bool() -} - -class SramReadResp(val w: Int) extends Bundle { - val data = UInt(w.W) - val fromDMA = Bool() -} - -class SramReadIO(val n: Int, val w: Int) extends Bundle { - val req = Flipped(Decoupled(new SramReadReq(n))) - val resp = Decoupled(new SramReadResp(w)) -} - -class SramWriteReq(val n: Int, val w: Int, val mask_len: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) - val mask = Vec(mask_len, Bool()) - val data = UInt(w.W) -} - -class SramWriteIO(val n: Int, val w: Int, val mask_len: Int) extends Bundle { - val req = Flipped(Decoupled(new SramWriteReq(n, w, mask_len))) -} - -class SramBank(n: Int, w: Int, aligned_to: Int, single_ported: Boolean) extends Module { - require(w % aligned_to == 0 || w < aligned_to) - - val mask_len = (w / (aligned_to * 8)) max 1 // How many mask bits are there? - val mask_elem = UInt((w min (aligned_to * 8)).W) // What datatype does each mask bit correspond to? - - val io = IO(new Bundle { - val read = new SramReadIO(n, w) - val write = new SramWriteIO(n, w, mask_len) - }) - - val mem = SyncReadMem(n, Vec(mask_len, mask_elem)) - - // Note: Memory is not initialized on reset to avoid FIRRTL compilation explosion - // Software should initialize memory before use if needed - - // Only one request per cycle is allowed - assert(!(io.read.req.valid && io.write.req.valid), "SramBank: Read and write requests is not allowed at the same time") - - // Read request can be ready as long as there is no write request - io.read.req.ready := !io.write.req.valid - -// ----------------------------------------------------------------------------- -// Write -// ----------------------------------------------------------------------------- - // Write request is always ready unless there is a read request in progress - io.write.req.ready := !io.read.req.valid - - when (io.write.req.valid) { - mem.write(io.write.req.bits.addr, io.write.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), VecInit((~(0.U(mask_len.W))).asBools)) - } - -// ----------------------------------------------------------------------------- -// Read -// ----------------------------------------------------------------------------- - val raddr = io.read.req.bits.addr - val ren = io.read.req.fire - val rdata = mem.read(raddr, ren).asUInt - val fromDMA = io.read.req.bits.fromDMA - - // Make a queue which buffers the result of an SRAM read if it can't immediately be consumed - // val q = Module(new Queue(new SramReadResp(w), 1, true, true)) - // q.io.enq.valid := RegNext(ren) - // q.io.enq.bits.data := rdata - // q.io.enq.bits.fromDMA := RegNext(fromDMA) - - // io.read.resp <> q.io.deq - io.read.resp.valid := RegNext(ren) - io.read.resp.bits.data := rdata - io.read.resp.bits.fromDMA := RegNext(fromDMA) -} diff --git a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala b/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala new file mode 100644 index 00000000..078363eb --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala @@ -0,0 +1,102 @@ +package framework.memdomain.midend + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.balldomain.blink.{BankRead, BankWrite} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.memdomain.MemDomainParam +import framework.memdomain.backend.MemRequestIO + +/** + * MemScheduler: Midend module for memory scheduling + * Connects MemController to MemManager + * + * Basic direct connection: routes requests from frontend to backend channels + */ +@instantiable +class MemScheduler(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public + val io = IO(new Bundle { + + // Input from frontend (MemController) + val frontend = new Bundle { + + val bankRead = Vec( + parameter.bankNum, + Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum)) + ) + + val bankWrite = Vec( + parameter.bankNum, + Flipped(new BankWrite( + parameter.bankEntries, + parameter.bankWidth, + parameter.bankMaskLen, + parameter.rob_entries, + parameter.bankNum + )) + ) + + } + + // Output to backend (MemManager) + val mem_req = Vec(parameter.bankChannel, new MemRequestIO(parameter)) + }) + + // ----------------------------------------------------------------------------- + // Basic direct connection: route frontend requests to backend channels + // ----------------------------------------------------------------------------- + // Simple mapping: each channel handles requests for a specific bank + // Channel ch handles bank (ch % bankNum) + + for (ch <- 0 until parameter.bankChannel) { + val targetBank = (ch % parameter.bankNum).U + val bankIdx = ch % parameter.bankNum + + // Default: no request + io.mem_req(ch).write.req.valid := false.B + io.mem_req(ch).read.req.valid := false.B + io.mem_req(ch).bank_id := targetBank + + // Connect write request + val writeValid = io.frontend.bankWrite(bankIdx).io.req.valid && + (io.frontend.bankWrite(bankIdx).bank_id === targetBank) + when(writeValid) { + io.mem_req(ch).write.req.valid := io.frontend.bankWrite(bankIdx).io.req.valid + io.mem_req(ch).write.req.bits := io.frontend.bankWrite(bankIdx).io.req.bits + io.frontend.bankWrite(bankIdx).io.req.ready := io.mem_req(ch).write.req.ready + io.frontend.bankWrite(bankIdx).io.resp.valid := io.mem_req(ch).write.resp.valid + io.frontend.bankWrite(bankIdx).io.resp.bits := io.mem_req(ch).write.resp.bits + io.mem_req(ch).write.resp.ready := io.frontend.bankWrite(bankIdx).io.resp.ready + io.mem_req(ch).write.req.bits.wmode := io.frontend.bankWrite(bankIdx).io.req.bits.wmode + io.mem_req(ch).bank_id := io.frontend.bankWrite(bankIdx).bank_id + }.otherwise { + io.frontend.bankWrite(bankIdx).io.req.ready := false.B + io.frontend.bankWrite(bankIdx).io.resp.valid := false.B + io.frontend.bankWrite(bankIdx).io.resp.ready := true.B + } + + // Connect read request + val readValid = io.frontend.bankRead(bankIdx).io.req.valid && + (io.frontend.bankRead(bankIdx).bank_id === targetBank) + when(readValid) { + io.mem_req(ch).read.req.valid := io.frontend.bankRead(bankIdx).io.req.valid + io.mem_req(ch).read.req.bits := io.frontend.bankRead(bankIdx).io.req.bits + io.frontend.bankRead(bankIdx).io.req.ready := io.mem_req(ch).read.req.ready + io.frontend.bankRead(bankIdx).io.resp.valid := io.mem_req(ch).read.resp.valid + io.frontend.bankRead(bankIdx).io.resp.bits := io.mem_req(ch).read.resp.bits + io.mem_req(ch).read.resp.ready := io.frontend.bankRead(bankIdx).io.resp.ready + io.mem_req(ch).bank_id := io.frontend.bankRead(bankIdx).bank_id + }.otherwise { + io.frontend.bankRead(bankIdx).io.req.ready := false.B + io.frontend.bankRead(bankIdx).io.resp.valid := false.B + io.frontend.bankRead(bankIdx).io.resp.ready := true.B + } + } +} diff --git a/arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala b/arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala new file mode 100644 index 00000000..6f26e081 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala @@ -0,0 +1 @@ +package framework.memdomain.midend.bmt diff --git a/arch/src/main/scala/framework/memdomain/rs/reservationStation.scala b/arch/src/main/scala/framework/memdomain/rs/reservationStation.scala deleted file mode 100644 index d8d13f7f..00000000 --- a/arch/src/main/scala/framework/memdomain/rs/reservationStation.scala +++ /dev/null @@ -1,99 +0,0 @@ -package framework.memdomain.rs - -import chisel3._ -import chisel3.util._ -import chisel3.experimental._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain._ -// Mem domain issue interface - includes global rob_id -class MemRsIssue(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val cmd = new MemDecodeCmd - // Global ROB ID - val rob_id = UInt(log2Up(b.rob_entries).W) -} - -// Mem domain completion interface -class MemRsComplete(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val rob_id = UInt(log2Up(b.rob_entries).W) -} - -// Mem domain issue interface combination (Load + Store) -class MemIssueInterface(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val ld = Decoupled(new MemRsIssue) - val st = Decoupled(new MemRsIssue) -} - -// Mem domain completion interface combination (Load + Store) -class MemCommitInterface(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val ld = Flipped(Decoupled(new MemRsComplete)) - val st = Flipped(Decoupled(new MemRsComplete)) -} - -// Local Mem reservation station - simple FIFO scheduler -class MemReservationStation(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new Bundle { - // Decoded instruction input (with global rob_id) - val mem_decode_cmd_i = Flipped(new DecoupledIO(new Bundle { - val cmd = new MemDecodeCmd - // Global ROB ID - val rob_id = UInt(log2Up(b.rob_entries).W) - })) - - // Rs -> MemLoader/MemStorer - val issue_o = new MemIssueInterface - val commit_i = new MemCommitInterface - - // Output completion signal (with global rob_id, single channel) - val complete_o = Decoupled(new MemRsComplete) - }) - - // Simple FIFO queue, only for buffering - val fifo = Module(new Queue(new Bundle { - val cmd = new MemDecodeCmd - val rob_id = UInt(log2Up(b.rob_entries).W) - }, entries = 4)) // Small buffer is sufficient - -// ----------------------------------------------------------------------------- -// Inbound - FIFO enqueue -// ----------------------------------------------------------------------------- - fifo.io.enq <> io.mem_decode_cmd_i - -// ----------------------------------------------------------------------------- -// Outbound - instruction issue (dispatch based on is_load/is_store) -// ----------------------------------------------------------------------------- - val headEntry = fifo.io.deq.bits - - // Load issue - io.issue_o.ld.valid := fifo.io.deq.valid && headEntry.cmd.is_load - io.issue_o.ld.bits.cmd := headEntry.cmd - io.issue_o.ld.bits.rob_id := headEntry.rob_id - - // Store issue - io.issue_o.st.valid := fifo.io.deq.valid && headEntry.cmd.is_store - io.issue_o.st.bits.cmd := headEntry.cmd - io.issue_o.st.bits.rob_id := headEntry.rob_id - - // FIFO deq.ready - can only dequeue when target unit is ready - fifo.io.deq.ready := - (headEntry.cmd.is_load && io.issue_o.ld.ready) || - (headEntry.cmd.is_store && io.issue_o.st.ready) - -// ----------------------------------------------------------------------------- -// Completion signal processing - directly forward to global RS -// ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.rob_entries).W), 2)) - - completeArb.io.in(0).valid := io.commit_i.ld.valid - completeArb.io.in(0).bits := io.commit_i.ld.bits.rob_id - io.commit_i.ld.ready := completeArb.io.in(0).ready - - completeArb.io.in(1).valid := io.commit_i.st.valid - completeArb.io.in(1).bits := io.commit_i.st.bits.rob_id - io.commit_i.st.ready := completeArb.io.in(1).ready - - // Forward completion signal (with global rob_id) - io.complete_o.valid := completeArb.io.out.valid - io.complete_o.bits.rob_id := completeArb.io.out.bits - completeArb.io.out.ready := io.complete_o.ready -} diff --git a/arch/src/main/scala/framework/memdomain/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/tlb/TLBCluster.scala deleted file mode 100644 index 0bb4cc9f..00000000 --- a/arch/src/main/scala/framework/memdomain/tlb/TLBCluster.scala +++ /dev/null @@ -1,81 +0,0 @@ -package framework.memdomain.tlb - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile.{CoreBundle, CoreModule} -import freechips.rocketchip.tilelink.TLEdgeOut - - -class BBTLBIO(implicit p: Parameters) extends CoreBundle { - val lgMaxSize = log2Ceil(coreDataBytes) - val req = Valid(new BBTLBReq(lgMaxSize)) - val resp = Flipped(new TLBResp) -} - -class BBTLBCluster(nClients: Int, entries: Int, maxSize: Int, use_shared_tlb: Boolean = true) - (implicit edge: TLEdgeOut, p: Parameters) extends CoreModule { - - val num_tlbs = if (use_shared_tlb) 1 else nClients - val lgMaxSize = log2Ceil(coreDataBytes) - - val io = IO(new Bundle { - val clients = Flipped(Vec(nClients, new BBTLBIO)) - val ptw = Vec(num_tlbs, new TLBPTWIO) - val exp = Vec(num_tlbs, new BBTLBExceptionIO) - }) - - val tlbs = Seq.fill(num_tlbs)(Module(new BBTLB(entries, maxSize))) - - io.ptw <> VecInit(tlbs.map(_.io.ptw)) - io.exp <> VecInit(tlbs.map(_.io.exp)) - - val tlbArbOpt = if (use_shared_tlb) Some(Module(new RRArbiter(new BBTLBReq(lgMaxSize), nClients))) else None - - if (use_shared_tlb) { - val tlbArb = tlbArbOpt.get - val tlb = tlbs.head - tlb.io.req.valid := tlbArb.io.out.valid - tlb.io.req.bits := tlbArb.io.out.bits - tlbArb.io.out.ready := true.B - } - - io.clients.zipWithIndex.foreach { case (client, i) => - val last_translated_valid = RegInit(false.B) - val last_translated_vpn = RegInit(0.U(vaddrBits.W)) - val last_translated_ppn = RegInit(0.U(paddrBits.W)) - - val l0_tlb_hit = last_translated_valid && ((client.req.bits.tlb_req.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt) - val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.tlb_req.vaddr(pgIdxBits-1,0)) - - val tlb = if (use_shared_tlb) tlbs.head else tlbs(i) - val tlbReq = if (use_shared_tlb) tlbArbOpt.get.io.in(i).bits else tlb.io.req.bits - val tlbReqValid = if (use_shared_tlb) tlbArbOpt.get.io.in(i).valid else tlb.io.req.valid - val tlbReqFire = if (use_shared_tlb) tlbArbOpt.get.io.in(i).fire else tlb.io.req.fire - - val l0_tlb_paddr_reg = RegEnable(client.req.bits.tlb_req.vaddr, client.req.valid) - - tlbReqValid := RegNext(client.req.valid && !l0_tlb_hit) - tlbReq := RegNext(client.req.bits) - - when (tlbReqFire && !tlb.io.resp.miss) { - last_translated_valid := true.B - last_translated_vpn := tlbReq.tlb_req.vaddr - last_translated_ppn := tlb.io.resp.paddr - } - - when (tlb.io.exp.flush()) { - last_translated_valid := false.B - } - - when (tlbReqFire) { - client.resp := tlb.io.resp - }.otherwise { - client.resp := DontCare - client.resp.paddr := RegNext(l0_tlb_paddr) - client.resp.miss := !RegNext(l0_tlb_hit) - } - } -} diff --git a/arch/src/main/scala/framework/memdomain/pmc/MemCyclePMC.scala b/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala similarity index 53% rename from arch/src/main/scala/framework/memdomain/pmc/MemCyclePMC.scala rename to arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala index 99e073a9..0e6ae32d 100644 --- a/arch/src/main/scala/framework/memdomain/pmc/MemCyclePMC.scala +++ b/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala @@ -1,17 +1,24 @@ -package framework.memdomain.pmc +package framework.memdomain.utils.pmc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.rs.{MemRsIssue, MemRsComplete} +import framework.memdomain.MemDomainParam +import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -class MemCyclePMC(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class MemCyclePMC(val parameter: MemDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[MemDomainParam] { + + @public val io = IO(new Bundle { - val ldReq_i = Input(Valid(new MemRsIssue)) - val stReq_i = Input(Valid(new MemRsIssue)) - val ldResp_o = Input(Valid(new MemRsComplete)) - val stResp_o = Input(Valid(new MemRsComplete)) + val ldReq_i = Input(Valid(new MemRsIssue(parameter))) + val stReq_i = Input(Valid(new MemRsIssue(parameter))) + val ldResp_o = Input(Valid(new MemRsComplete(parameter))) + val stResp_o = Input(Valid(new MemRsComplete(parameter))) val ldTotalCycles = Output(UInt(64.W)) val stTotalCycles = Output(UInt(64.W)) }) @@ -19,7 +26,7 @@ class MemCyclePMC(implicit b: CustomBuckyballConfig, p: Parameters) extends Modu val cycleCounter = RegInit(0.U(64.W)) cycleCounter := cycleCounter + 1.U - val startTime = Reg(Vec(b.rob_entries, UInt(64.W))) + val startTime = Reg(Vec(parameter.rob_entries, UInt(64.W))) val ldTotalCycles = RegInit(0.U(64.W)) val stTotalCycles = RegInit(0.U(64.W)) @@ -32,14 +39,14 @@ class MemCyclePMC(implicit b: CustomBuckyballConfig, p: Parameters) extends Modu } when(io.ldResp_o.valid) { - val robId = io.ldResp_o.bits.rob_id + val robId = io.ldResp_o.bits.rob_id val elapsed = cycleCounter - startTime(robId) ldTotalCycles := ldTotalCycles + elapsed printf("[PMC] Load completed, elapsed: %d cycles\n", elapsed) } when(io.stResp_o.valid) { - val robId = io.stResp_o.bits.rob_id + val robId = io.stResp_o.bits.rob_id val elapsed = cycleCounter - startTime(robId) stTotalCycles := stTotalCycles + elapsed printf("[PMC] Store completed, elapsed: %d cycles\n", elapsed) diff --git a/arch/src/main/scala/framework/rocket/Configs.scala b/arch/src/main/scala/framework/rocket/Configs.scala deleted file mode 100644 index 47f466d4..00000000 --- a/arch/src/main/scala/framework/rocket/Configs.scala +++ /dev/null @@ -1,194 +0,0 @@ -package framework.rocket - -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import org.chipsalliance.diplomacy.lazymodule._ - -import freechips.rocketchip.rocket._ -import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType} -import freechips.rocketchip.subsystem.{TilesLocated, NumTiles, HierarchicalLocation, RocketCrossingParams, SystemBusKey, CacheBlockBytes, RocketTileAttachParams, InSubsystem, InCluster, HierarchicalElementMasterPortParams, HierarchicalElementSlavePortParams, CBUS, CCBUS, ClustersLocated, TileAttachConfig, CloneTileAttachParams} -import freechips.rocketchip.tile.{RocketTileParams, RocketTileBoundaryBufferParams, FPUParams} -import scala.reflect.ClassTag - -import framework.rocket.{RocketTileParamsBB, RocketCrossingParamsBB} - - -class WithNBuckyballCores( - n: Int, - location: HierarchicalLocation, - crossing: RocketCrossingParams, -) extends Config((site, here, up) => { - case TilesLocated(`location`) => { - val prev = up(TilesLocated(`location`), site) - val idOffset = up(NumTiles) - val big = RocketTileParamsBB( - usingRVVRoCC = true, - core = RocketCoreParams( - mulDiv = Some(MulDivParams( - mulUnroll = 8, - mulEarlyOut = true, - divEarlyOut = true, - )), - useZba = true, - useZbb = true, - useZbs = true, - fpu = Some(FPUParams(minFLen = 16))), - dcache = Some(DCacheParams( - nSets = 64, - nWays = 8, - rowBits = site(SystemBusKey).beatBits, - nMSHRs = 0, - blockBytes = site(CacheBlockBytes))), - icache = Some(ICacheParams( - nSets = 64, - nWays = 8, - rowBits = site(SystemBusKey).beatBits, - blockBytes = site(CacheBlockBytes)))) - List.tabulate(n)(i => RocketTileAttachParamsBB( - big.copy(tileId = i + idOffset), - crossing - )) ++ prev - } - case NumTiles => up(NumTiles) + n -}) { - def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams( - master = HierarchicalElementMasterPortParams.locationDefault(location), - slave = HierarchicalElementSlavePortParams.locationDefault(location), - mmioBaseAddressPrefixWhere = location match { - case InSubsystem => CBUS - case InCluster(clusterId) => CCBUS(clusterId) - } - )) -} - -class RocketTileAttachConfig(f: RocketTileAttachParams => RocketTileAttachParams) extends TileAttachConfig[RocketTileAttachParams](f) - -class RocketTileConfig(f: RocketTileParams => RocketTileParams) extends RocketTileAttachConfig(tp => tp.copy( - tileParams = f(tp.tileParams) -)) - -class RocketCrossingConfig(f: RocketCrossingParams => RocketCrossingParams) extends RocketTileAttachConfig(tp => tp.copy( - crossingParams = f(tp.crossingParams) -)) - -class RocketCoreConfig(f: RocketCoreParams => RocketCoreParams) extends RocketTileConfig(tp => tp.copy( - core = f(tp.core) -)) - -class RocketICacheConfig(f: ICacheParams => ICacheParams) extends RocketTileConfig(tp => tp.copy( - icache = tp.icache.map(ic => f(ic)) -)) - -class RocketDCacheConfig(f: DCacheParams => DCacheParams) extends RocketTileConfig(tp => tp.copy( - dcache = tp.dcache.map(dc => f(dc)) -)) - -class WithL1ICacheSets(sets: Int) extends RocketICacheConfig(_.copy(nSets=sets)) -class WithL1ICacheWays(ways: Int) extends RocketICacheConfig(_.copy(nWays=ways)) -class WithL1ICacheECC(dataECC: String, tagECC: String) extends RocketICacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC))) -class WithL1ICacheRowBits(n: Int) extends RocketICacheConfig(_.copy(rowBits = n)) -class WithL1ICacheTLBSets(sets: Int) extends RocketICacheConfig(_.copy(nTLBSets = sets)) -class WithL1ICacheTLBWays(ways: Int) extends RocketICacheConfig(_.copy(nTLBWays = ways)) -class WithL1ICacheTLBBasePageSectors(sectors: Int) extends RocketICacheConfig(_.copy(nTLBBasePageSectors = sectors)) -class WithL1ICacheTLBSuperpages(superpages: Int) extends RocketICacheConfig(_.copy(nTLBSuperpages = superpages)) -class WithL1ICacheBlockBytes(bytes: Int = 64) extends RocketICacheConfig(_.copy(blockBytes = bytes)) - -class WithL1DCacheSets(sets: Int) extends RocketDCacheConfig(_.copy(nSets=sets)) -class WithL1DCacheWays(ways: Int) extends RocketDCacheConfig(_.copy(nWays=ways)) -class WithL1DCacheECC(dataECC: String, tagECC: String) extends RocketDCacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC))) -class WithL1DCacheRowBits(n: Int) extends RocketDCacheConfig(_.copy(rowBits = n)) -class WithL1DCacheTLBSets(sets: Int) extends RocketDCacheConfig(_.copy(nTLBSets = sets)) -class WithL1DCacheTLBWays(ways: Int) extends RocketDCacheConfig(_.copy(nTLBWays = ways)) -class WithL1DCacheTLBBasePageSectors(sectors: Int) extends RocketDCacheConfig(_.copy(nTLBBasePageSectors = sectors)) -class WithL1DCacheTLBSuperpages(superpages: Int) extends RocketDCacheConfig(_.copy(nTLBSuperpages = superpages)) -class WithL1DCacheBlockBytes(bytes: Int = 64) extends RocketDCacheConfig(_.copy(blockBytes = bytes)) -class WithL1DCacheNonblocking(nMSHRs: Int) extends RocketDCacheConfig(_.copy(nMSHRs = nMSHRs)) -class WithL1DCacheClockGating extends RocketDCacheConfig(_.copy(clockGate = true)) -class WithL1DCacheDTIMAddress(address: BigInt) extends RocketDCacheConfig(_.copy(scratch = Some(address))) - -class WithScratchpadsOnly extends RocketTileConfig(tp => tp.copy( - core = tp.core.copy(useVM = false), - dcache = tp.dcache.map(_.copy( - nSets = 256, // 16Kb scratchpad - nWays = 1, - scratch = Some(0x80000000L))) -)) - -class WithCacheRowBits(n: Int) extends RocketTileConfig(tp => tp.copy( - dcache = tp.dcache.map(_.copy(rowBits = n)), - icache = tp.icache.map(_.copy(rowBits = n)) -)) - -class WithBEU(addr: BigInt) extends RocketTileConfig(_.copy(beuAddr = Some(addr))) -class WithBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends RocketTileConfig(_.copy(boundaryBuffers = buffers)) - -class WithRV32 extends RocketCoreConfig(c => c.copy( - xLen = 32, - pgLevels = 2, // sv32 - fpu = c.fpu.map(_.copy(fLen = 32)), - mulDiv = Some(MulDivParams(mulUnroll = 8)) -)) - -class WithoutVM extends RocketCoreConfig(_.copy(useVM = false)) -class WithCFlushEnabled extends RocketCoreConfig(_.copy(haveCFlush = true)) -class WithNBreakpoints(hwbp: Int) extends RocketCoreConfig(_.copy(nBreakpoints = hwbp)) -class WithHypervisor(hext: Boolean = true) extends RocketCoreConfig(_.copy(useHypervisor = hext)) -class WithCease(enable: Boolean = true) extends RocketCoreConfig(_.copy(haveCease = enable)) -class WithCoreClockGatingEnabled extends RocketCoreConfig(_.copy(clockGate = true)) -class WithPgLevels(n: Int) extends RocketCoreConfig(_.copy(pgLevels = n)) -class WithZba extends RocketCoreConfig(_.copy(useZba = true)) -class WithZbb extends RocketCoreConfig(_.copy(useZbb = true)) -class WithZbs extends RocketCoreConfig(_.copy(useZbs = true)) -class WithB extends RocketCoreConfig(_.copy(useZba = true, useZbb = true, useZbs = true)) -class WithSV48 extends WithPgLevels(4) -class WithSV39 extends WithPgLevels(3) - -// Simulation-only configs -class WithNoSimulationTimeout extends RocketCoreConfig(_.copy(haveSimTimeout = false)) -class WithDebugROB(enable: Boolean = true, size: Int = 0) extends RocketCoreConfig(_.copy(debugROB = Option.when(enable)(DebugROBParams(size)))) - -// FPU configs -class WithoutFPU extends RocketCoreConfig(_.copy(fpu = None)) -class WithFP16 extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(minFLen = 16)))) -class WithFPUWithoutDivSqrt extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(divSqrt = false)))) - -// mul-div configs -class WithFastMulDiv extends RocketCoreConfig(c => c.copy(mulDiv = Some( - MulDivParams(mulUnroll = 8, mulEarlyOut = c.xLen > 32, divEarlyOut = true) -))) -class WithCustomFastMulDiv(mUnroll: Int = 8, mEarlyOut: Boolean = true, dUnroll: Int = 1, dEarlyOut: Boolean = true, dEarlyOutGranularity: Int = 1) extends RocketCoreConfig(_.copy(mulDiv = Some( - MulDivParams(mulUnroll = mUnroll, mulEarlyOut = mEarlyOut, divUnroll = dUnroll, divEarlyOut = dEarlyOut, divEarlyOutGranularity = dEarlyOutGranularity) -))) -class WithoutMulDiv extends RocketCoreConfig(_.copy(mulDiv = None)) - -// Branch-prediction configs -class WithDefaultBtb extends RocketTileConfig(t => t.copy(btb = Some(BTBParams()))) -class WithNoBtb extends RocketTileConfig(_.copy(btb = None)) - -// Tile CDC configs -class WithCDC(crossingType: ClockCrossingType = SynchronousCrossing()) extends RocketCrossingConfig(_.copy(crossingType = crossingType)) -class WithSeperateClockReset extends RocketCrossingConfig(_.copy(forceSeparateClockReset = true)) -class WithSynchronousCDCs extends WithCDC(SynchronousCrossing()) -class WithAsynchronousCDCs(depth: Int, sync: Int) extends WithCDC(AsynchronousCrossing(depth, sync)) -class WithRationalCDCs extends WithCDC(RationalCrossing()) - -class WithCloneRocketTiles( - n: Int = 1, - cloneTileId: Int = 0, - location: HierarchicalLocation = InSubsystem, - cloneLocation: HierarchicalLocation = InSubsystem -) extends Config((site, here, up) => { - case TilesLocated(`location`) => { - val prev = up(TilesLocated(location), site) - val idOffset = up(NumTiles) - val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId) - .get.asInstanceOf[RocketTileAttachParams] - (0 until n).map { i => - CloneTileAttachParams(cloneTileId, tileAttachParams.copy( - tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset) - )) - } ++ prev - } - case NumTiles => up(NumTiles) + n -}) diff --git a/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala deleted file mode 100644 index e6192fbb..00000000 --- a/arch/src/main/scala/framework/rocket/LazyRoCCBB.scala +++ /dev/null @@ -1,151 +0,0 @@ -// See LICENSE.Berkeley for license details. -// See LICENSE.SiFive for license details. - -package framework.rocket - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.IntParam - -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ - - -import org.chipsalliance.cde.config._ -import org.chipsalliance.diplomacy.lazymodule._ - -import freechips.rocketchip.rocket.{ - MStatus, HellaCacheIO, TLBPTWIO, CanHavePTW, CanHavePTWModule, - SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ -} -import freechips.rocketchip.tilelink.{ - TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters -} -import freechips.rocketchip.util.InOrderArbiter - -case object BuildRoCCBB extends Field[Seq[Parameters => LazyRoCCBB]](Nil) - - -class RoCCCommandBB(implicit p: Parameters) extends CoreBundle()(p) { - val inst = new RoCCInstruction - val rs1 = Bits(xLen.W) - val rs2 = Bits(xLen.W) - val status = new MStatus -} - -class RoCCResponseBB(implicit p: Parameters) extends CoreBundle()(p) { - val rd = Bits(5.W) - val data = Bits(xLen.W) -} - -class RoCCCoreIOBB(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { - val cmd = Flipped(Decoupled(new RoCCCommandBB)) - val resp = Decoupled(new RoCCResponseBB) - val mem = new HellaCacheIO - val busy = Output(Bool()) - val interrupt = Output(Bool()) - val exception = Input(Bool()) - val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) -} - -class RoCCIOBB(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIOBB(nRoCCCSRs)(p) { - val ptw = Vec(nPTWPorts, new TLBPTWIO) - val fpu_req = Decoupled(new FPInput) - val fpu_resp = Flipped(Decoupled(new FPResult)) -} - -/** Base classes for Diplomatic TL2 RoCC units **/ -abstract class LazyRoCCBB( - val opcodes: OpcodeSet, - val nPTWPorts: Int = 0, - val usesFPU: Boolean = false, - val roccCSRs: Seq[CustomCSR] = Nil -)(implicit p: Parameters) extends LazyModule { - val module: LazyRoCCModuleImpBB - require(roccCSRs.map(_.id).toSet.size == roccCSRs.size) - val atlNode: TLNode = TLIdentityNode() - val tlNode: TLNode = TLIdentityNode() - val stlNode: TLNode = TLIdentityNode() -} - -class LazyRoCCModuleImpBB(outer: LazyRoCCBB) extends LazyModuleImp(outer) { - val io = IO(new RoCCIOBB(outer.nPTWPorts, outer.roccCSRs.size)) - io := DontCare -} - -/** Mixins for including RoCC **/ - -trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => - val roccs = p(BuildRoCCBB).map(_(p)) - val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs - require(roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, - "LazyRoCC instantiations require overlapping CSRs") - roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl } - roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl } - roccs.map(_.stlNode).foreach { stl => stl :*= tlSlaveXbar.node } - - nPTWPorts += roccs.map(_.nPTWPorts).sum - nDCachePorts += roccs.size -} - -trait HasLazyRoCCModuleBB extends CanHavePTWModule - with HasCoreParameters { this: RocketTileModuleImpBB => - - val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) { - val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) - // Get usingRVVRoCC from tile parameters - val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC - val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) - outer.roccs.zipWithIndex.foreach { case (rocc, i) => - rocc.module.io.ptw ++=: ptwPorts - rocc.module.io.cmd <> cmdRouter.io.out(i) - val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) - dcIF.io.requestor <> rocc.module.io.mem - dcachePorts += dcIF.io.cache - respArb.io.in(i) <> Queue(rocc.module.io.resp) - } - (Some(respArb), Some(cmdRouter)) - } else { - (None, None) - } - val roccCSRIOs = outer.roccs.map(_.module.io.csrs) -} - - -class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implicit p: Parameters) - extends CoreModule()(p) { - val io = IO(new Bundle { - val in = Flipped(Decoupled(new RoCCCommand)) - val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) - val busy = Output(Bool()) - }) - - val cmd = Queue(io.in) - - // Check which opcodes match - val opcodeMatches = opcodes.map(opcode => opcode.matches(cmd.bits.inst.opcode)) - val anyMatch = opcodeMatches.reduce(_ || _) - - val cmdReadys = io.out.zip(opcodeMatches).zipWithIndex.map { case ((out, matches), i) => - // In RVVRoCC mode: route unmatched opcodes to first RoCC (index 0) - // Otherwise: only route if opcode matches - val shouldRoute = if (usingRVVRoCC && i == 0) { - matches || !anyMatch // First RoCC gets matched opcodes OR unmatched opcodes - } else { - matches // Other RoCCs only get their matched opcodes - } - - out.valid := cmd.valid && shouldRoute - out.bits := cmd.bits - out.ready && shouldRoute - } - cmd.ready := cmdReadys.reduce(_ || _) - io.busy := cmd.valid - - // In RVVRoCC mode, allow unmatched opcodes to go to first RoCC - // Otherwise, assert that only one RoCC matches - if (!usingRVVRoCC) { - assert(PopCount(cmdReadys) <= 1.U, - "Custom opcode matched for more than one accelerator") - } -} diff --git a/arch/src/main/scala/framework/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/rocket/RocketCoreBB.scala deleted file mode 100644 index 304b3f8e..00000000 --- a/arch/src/main/scala/framework/rocket/RocketCoreBB.scala +++ /dev/null @@ -1,1256 +0,0 @@ -// See LICENSE.Berkeley for license details. -// See LICENSE.SiFive for license details. - -package framework.rocket - -import chisel3._ -import chisel3.util._ -import chisel3.withClock -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ -import freechips.rocketchip.util._ -import freechips.rocketchip.util.property -import scala.collection.mutable.ArrayBuffer -import freechips.rocketchip.rocket._ - -import framework.rocket.RoCCCoreIOBB -import framework.rocket.id.RVVRoCCDecode - - -trait HasRocketCoreIOBB extends HasRocketCoreParameters { - implicit val p: Parameters - def nTotalRoCCCSRs: Int - val io = IO(new CoreBundle()(p) { - val hartid = Input(UInt(hartIdLen.W)) - val reset_vector = Input(UInt(resetVectorLen.W)) - val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParamsBB].beuAddr.isDefined)) - val imem = new FrontendIO - val dmem = new HellaCacheIO - val ptw = Flipped(new DatapathPTWIO()) - val fpu = Flipped(new FPUCoreIO()) - val rocc = Flipped(new RoCCCoreIOBB(nTotalRoCCCSRs)) - val trace = Output(new TraceBundle) - val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) - val cease = Output(Bool()) - val wfi = Output(Bool()) - val traceStall = Input(Bool()) - val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None - }) -} - - -class RocketBB(tile: RocketTileBB)(implicit p: Parameters) extends CoreModule()(p) - with HasRocketCoreParameters - with HasRocketCoreIOBB { - def nTotalRoCCCSRs = tile.roccCSRs.flatten.size - import ALU._ - - val clock_en_reg = RegInit(true.B) - val long_latency_stall = Reg(Bool()) - val id_reg_pause = Reg(Bool()) - val imem_might_request_reg = Reg(Bool()) - val clock_en = WireDefault(true.B) - val gated_clock = - if (!rocketParams.clockGate) clock - else ClockGate(clock, clock_en, "rocket_clock_gate") - - class RocketImpl { // entering gated-clock domain - - // performance counters - def pipelineIDToWB[T <: Data](x: T): T = - RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) - val perfEvents = new EventSets(Seq( - new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( - ("exception", () => false.B), - ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), - ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), - ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), - ("system", () => id_ctrl.csr =/= CSR.N), - ("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)), - ("branch", () => id_ctrl.branch), - ("jal", () => id_ctrl.jal), - ("jalr", () => id_ctrl.jalr)) - ++ (if (!usingMulDiv) Seq() else Seq( - ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), - ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) - ++ (if (!usingFPU) Seq() else Seq( - ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), - ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), - ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), - ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), - ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), - ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)), - ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))), - new EventSet((mask, hits) => (mask & hits).orR, Seq( - ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem), - ("long-latency interlock", () => id_sboard_hazard), - ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N), - ("I$ blocked", () => icache_blocked), - ("D$ blocked", () => id_ctrl.mem && dcache_blocked), - ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), - ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), - ("flush", () => wb_reg_flush_pipe), - ("replay", () => replay_wb)) - ++ (if (!usingMulDiv) Seq() else Seq( - ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div))) - ++ (if (!usingFPU) Seq() else Seq( - ("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))), - new EventSet((mask, hits) => (mask & hits).orR, Seq( - ("I$ miss", () => io.imem.perf.acquire), - ("D$ miss", () => io.dmem.perf.acquire), - ("D$ release", () => io.dmem.perf.release), - ("ITLB miss", () => io.imem.perf.tlbMiss), - ("DTLB miss", () => io.dmem.perf.tlbMiss), - ("L2 TLB miss", () => io.ptw.perf.l2miss))))) - - - val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen - - val usingRVVRoCC = tile.rocketParams.usingRVVRoCC - - // Ensure usingVector and usingRVVRoCC are mutually exclusive - require(!usingVector || !usingRVVRoCC, - "usingVector and usingRVVRoCC cannot both be enabled. " + - "Use usingVector for built-in vector unit, or usingRVVRoCC to route vector instructions to RoCC.") - - val decode_table = { - (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: - (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: - (usingRVVRoCC.option(new RVVRoCCDecode)) ++: - (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: - (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: - (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: - (usingRoCC.option(new RoCCDecode)) ++: - (if (xLen == 32) new I32Decode else new I64Decode) +: - (usingVM.option(new SVMDecode)) ++: - (usingSupervisor.option(new SDecode)) ++: - (usingHypervisor.option(new HypervisorDecode)) ++: - ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: - (usingDebug.option(new DebugDecode)) ++: - (usingNMI.option(new NMIDecode)) ++: - (usingConditionalZero.option(new ConditionalZeroDecode)) ++: - Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: - coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: - rocketParams.haveCease.option(new CeaseDecode) ++: - usingVector.option(new VCFGDecode) ++: - (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: - (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: - coreParams.useZbs.option(new ZbsDecode) ++: - Seq(new IDecode) - } flatMap(_.table) - - val ex_ctrl = Reg(new IntCtrlSigs) - val mem_ctrl = Reg(new IntCtrlSigs) - val wb_ctrl = Reg(new IntCtrlSigs) - - val ex_reg_xcpt_interrupt = Reg(Bool()) - val ex_reg_valid = Reg(Bool()) - val ex_reg_rvc = Reg(Bool()) - val ex_reg_btb_resp = Reg(new BTBResp) - val ex_reg_xcpt = Reg(Bool()) - val ex_reg_flush_pipe = Reg(Bool()) - val ex_reg_load_use = Reg(Bool()) - val ex_reg_cause = Reg(UInt()) - val ex_reg_replay = Reg(Bool()) - val ex_reg_pc = Reg(UInt()) - val ex_reg_mem_size = Reg(UInt()) - val ex_reg_hls = Reg(Bool()) - val ex_reg_inst = Reg(Bits()) - val ex_reg_raw_inst = Reg(UInt()) - val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) - val ex_reg_set_vconfig = Reg(Bool()) - - val mem_reg_xcpt_interrupt = Reg(Bool()) - val mem_reg_valid = Reg(Bool()) - val mem_reg_rvc = Reg(Bool()) - val mem_reg_btb_resp = Reg(new BTBResp) - val mem_reg_xcpt = Reg(Bool()) - val mem_reg_replay = Reg(Bool()) - val mem_reg_flush_pipe = Reg(Bool()) - val mem_reg_cause = Reg(UInt()) - val mem_reg_slow_bypass = Reg(Bool()) - val mem_reg_load = Reg(Bool()) - val mem_reg_store = Reg(Bool()) - val mem_reg_set_vconfig = Reg(Bool()) - val mem_reg_sfence = Reg(Bool()) - val mem_reg_pc = Reg(UInt()) - val mem_reg_inst = Reg(Bits()) - val mem_reg_mem_size = Reg(UInt()) - val mem_reg_hls_or_dv = Reg(Bool()) - val mem_reg_raw_inst = Reg(UInt()) - val mem_reg_wdata = Reg(Bits()) - val mem_reg_rs2 = Reg(Bits()) - val mem_br_taken = Reg(Bool()) - val take_pc_mem = Wire(Bool()) - val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) - - val wb_reg_valid = Reg(Bool()) - val wb_reg_xcpt = Reg(Bool()) - val wb_reg_replay = Reg(Bool()) - val wb_reg_flush_pipe = Reg(Bool()) - val wb_reg_cause = Reg(UInt()) - val wb_reg_set_vconfig = Reg(Bool()) - val wb_reg_sfence = Reg(Bool()) - val wb_reg_pc = Reg(UInt()) - val wb_reg_mem_size = Reg(UInt()) - val wb_reg_hls_or_dv = Reg(Bool()) - val wb_reg_hfence_v = Reg(Bool()) - val wb_reg_hfence_g = Reg(Bool()) - val wb_reg_inst = Reg(Bits()) - val wb_reg_raw_inst = Reg(UInt()) - val wb_reg_wdata = Reg(Bits()) - val wb_reg_rs2 = Reg(Bits()) - val take_pc_wb = Wire(Bool()) - val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) - - val take_pc_mem_wb = take_pc_wb || take_pc_mem - val take_pc = take_pc_mem_wb - - // decode stage - val ibuf = Module(new IBuf) - val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) - val id_raw_inst = ibuf.io.inst.map(_.bits.raw) - val id_inst = id_expanded_inst.map(_.bits) - ibuf.io.imem <> io.imem.resp - ibuf.io.kill := take_pc - - require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) - require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") - require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") - val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) - - val lgNXRegs = if (coreParams.useRVE) 4 else 5 - val regAddrMask = (1 << lgNXRegs) - 1 - - def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) - val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) - val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) - val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) - val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) - - val id_load_use = Wire(Bool()) - val id_reg_fence = RegInit(false.B) - val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) - val id_raddr = IndexedSeq(id_raddr1, id_raddr2) - val rf = new RegFile(regAddrMask, xLen) - val id_rs = id_raddr.map(rf.read _) - val ctrl_killd = Wire(Bool()) - val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt - - val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) - val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) - val id_system_insn = id_ctrl.csr === CSR.I - val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U - val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) - val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) - val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B - - id_ctrl.vec := false.B - if (usingVector) { - val v_decode = rocketParams.vector.get.decoder(p) - v_decode.io.inst := id_inst(0) - v_decode.io.vconfig := csr.io.vector.get.vconfig - when (v_decode.io.legal) { - id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill - id_ctrl.fp := v_decode.io.fp - id_ctrl.rocc := false.B - id_ctrl.branch := false.B - id_ctrl.jal := false.B - id_ctrl.jalr := false.B - id_ctrl.rxs2 := v_decode.io.read_rs2 - id_ctrl.rxs1 := v_decode.io.read_rs1 - id_ctrl.mem := false.B - id_ctrl.rfs1 := v_decode.io.read_frs1 - id_ctrl.rfs2 := false.B - id_ctrl.rfs3 := false.B - id_ctrl.wfd := v_decode.io.write_frd - id_ctrl.mul := false.B - id_ctrl.div := false.B - id_ctrl.wxd := v_decode.io.write_rd - id_ctrl.csr := CSR.N - id_ctrl.fence_i := false.B - id_ctrl.fence := false.B - id_ctrl.amo := false.B - id_ctrl.dp := false.B - id_ctrl.vec := true.B - } - } - - - val id_illegal_insn = !id_ctrl.legal || - (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || - id_ctrl.amo && !csr.io.status.isa('a'-'a') || - id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) || - (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) || - id_ctrl.dp && !csr.io.status.isa('d'-'a') || - ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') || - id_raddr2_illegal && id_ctrl.rxs2 || - id_raddr1_illegal && id_ctrl.rxs1 || - id_waddr_illegal && id_ctrl.wxd || - id_ctrl.rocc && csr.io.decode(0).rocc_illegal || - id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) || - !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) - val id_virtual_insn = id_ctrl.legal && - ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) || - (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) - // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) - val id_amo_aq = id_inst(0)(26) - val id_amo_rl = id_inst(0)(25) - val id_fence_pred = id_inst(0)(27,24) - val id_fence_succ = id_inst(0)(23,20) - val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq - val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid - when (!id_mem_busy) { id_reg_fence := false.B } - val id_rocc_busy = usingRoCC.B && - (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || - mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) - val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren - val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B) - val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) || - id_vec_busy && id_ctrl.fence || - id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))) - - val bpu = Module(new BreakpointUnit(nBreakpoints)) - bpu.io.status := csr.io.status - bpu.io.bp := csr.io.bp - bpu.io.pc := ibuf.io.pc - bpu.io.ea := mem_reg_wdata - bpu.io.mcontext := csr.io.mcontext - bpu.io.scontext := csr.io.scontext - - val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 - val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 - val (id_xcpt, id_cause) = checkExceptions(List( - (csr.io.interrupt, csr.io.interrupt_cause), - (bpu.io.debug_if, CSR.debugTriggerCause.U), - (bpu.io.xcpt_if, Causes.breakpoint.U), - (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), - (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), - (id_xcpt0.ae.inst, Causes.fetch_access.U), - (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), - (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), - (id_xcpt1.ae.inst, Causes.fetch_access.U), - (id_virtual_insn, Causes.virtual_instruction.U), - (id_illegal_insn, Causes.illegal_instruction.U))) - - val idCoverCauses = List( - (CSR.debugTriggerCause, "DEBUG_TRIGGER"), - (Causes.breakpoint, "BREAKPOINT"), - (Causes.fetch_access, "FETCH_ACCESS"), - (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") - ) ++ (if (usingVM) List( - (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") - ) else Nil) - coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) - - val dcache_bypass_data = - if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) - else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) - else wb_reg_wdata - - // detect bypass opportunities - val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U - val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U - val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U - val bypass_sources = IndexedSeq( - (true.B, 0.U, 0.U), // treat reading x0 as a bypass - (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), - (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), - (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) - val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) - - // execute stage - val bypass_mux = bypass_sources.map(_._3) - val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) - val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) - val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) - val ex_rs = for (i <- 0 until id_raddr.size) - yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) - val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) - val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) - val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( - A1_RS1 -> ex_rs(0).asSInt, - A1_PC -> ex_reg_pc.asSInt, - A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) - )) - val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt - val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( - A2_RS2 -> ex_rs(1).asSInt, - A2_IMM -> ex_imm, - A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), - ) ++ (if (coreParams.useZbs) Seq( - A2_RS2OH -> ex_op2_oh, - A2_IMMOH -> ex_op2_oh, - ) else Nil)) - - val (ex_new_vl, ex_new_vconfig) = if (usingVector) { - val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( - ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), - !ex_reg_inst(31) -> ex_reg_inst(30,20)))) - val ex_avl = Mux(ex_ctrl.rxs1, - Mux(ex_reg_inst(19,15) === 0.U, - Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), - ex_rs(0) - ), - ex_reg_inst(19,15)) - val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) - val ex_new_vconfig = Wire(new VConfig) - ex_new_vconfig.vtype := ex_new_vtype - ex_new_vconfig.vl := ex_new_vl - (Some(ex_new_vl), Some(ex_new_vconfig)) - } else { (None, None) } - - val alu = Module(new ALU) - alu.io.dw := ex_ctrl.alu_dw - alu.io.fn := ex_ctrl.alu_fn - alu.io.in2 := ex_op2.asUInt - alu.io.in1 := ex_op1.asUInt - - // multiplier and divider - val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) - div.io.req.valid := ex_reg_valid && ex_ctrl.div - div.io.req.bits.dw := ex_ctrl.alu_dw - div.io.req.bits.fn := ex_ctrl.alu_fn - div.io.req.bits.in1 := ex_rs(0) - div.io.req.bits.in2 := ex_rs(1) - div.io.req.bits.tag := ex_waddr - val mul = pipelinedMul.option { - val m = Module(new PipelinedMultiplier(xLen, 2)) - m.io.req.valid := ex_reg_valid && ex_ctrl.mul - m.io.req.bits := div.io.req.bits - m - } - - ex_reg_valid := !ctrl_killd - ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay - ex_reg_xcpt := !ctrl_killd && id_xcpt - ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt - - when (!ctrl_killd) { - ex_ctrl := id_ctrl - ex_reg_rvc := ibuf.io.inst(0).bits.rvc - ex_ctrl.csr := id_csr - when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } - when (id_fence_next) { id_reg_fence := true.B } - when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr - ex_ctrl.alu_fn := FN_ADD - ex_ctrl.alu_dw := DW_XPR - ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction - ex_ctrl.sel_alu2 := A2_ZERO - when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 - ex_ctrl.sel_alu1 := A1_PC - ex_ctrl.sel_alu2 := A2_SIZE - ex_reg_rvc := true.B - } - when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC - ex_ctrl.sel_alu1 := A1_PC - ex_ctrl.sel_alu2 := A2_ZERO - } - } - ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush - ex_reg_load_use := id_load_use - ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) - ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) - when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { - ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) - } - when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { - ex_ctrl.mem_cmd := M_HFENCEV - } - if (tile.dcache.flushOnFenceI) { - when (id_ctrl.fence_i) { - ex_reg_mem_size := 0.U - } - } - - for (i <- 0 until id_raddr.size) { - val do_bypass = id_bypass_src(i).reduce(_||_) - val bypass_src = PriorityEncoder(id_bypass_src(i)) - ex_reg_rs_bypass(i) := do_bypass - ex_reg_rs_lsb(i) := bypass_src - when (id_ren(i) && !do_bypass) { - ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) - ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) - } - } - when (id_illegal_insn || id_virtual_insn) { - val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) - ex_reg_rs_bypass(0) := false.B - ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) - ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) - } - } - when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) { - ex_reg_cause := id_cause - ex_reg_inst := id_inst(0) - ex_reg_raw_inst := id_raw_inst(0) - ex_reg_pc := ibuf.io.pc - ex_reg_btb_resp := ibuf.io.btb_resp - ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } - ex_reg_set_vconfig := id_set_vconfig && !id_xcpt - } - - // replay inst in ex stage? - val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt - val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid - val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready || - ex_ctrl.div && !div.io.req.ready || - ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) - val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use - val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use)) - val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid - // detect 2-cycle load-use delay for LB/LH/SC - val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U - val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG) - - val (ex_xcpt, ex_cause) = checkExceptions(List( - (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause))) - - val exCoverCauses = idCoverCauses - coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) - - // memory stage - val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt - val mem_br_target = mem_reg_pc.asSInt + - Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), - Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), - Mux(mem_reg_rvc, 2.S, 4.S))) - val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt - val mem_wrong_npc = - Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, - Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) - val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence - val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt - val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal - val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal - val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) - val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken - take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence) - - mem_reg_valid := !ctrl_killx - mem_reg_replay := !take_pc_mem_wb && replay_ex - mem_reg_xcpt := !ctrl_killx && ex_xcpt - mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt - - // on pipeline flushes, cause mem_npc to hold the sequential npc, which - // will drive the W-stage npc mux - when (mem_reg_valid && mem_reg_flush_pipe) { - mem_reg_sfence := false.B - }.elsewhen (ex_pc_valid) { - mem_ctrl := ex_ctrl - mem_reg_rvc := ex_reg_rvc - mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) - mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) - mem_reg_sfence := ex_sfence - mem_reg_btb_resp := ex_reg_btb_resp - mem_reg_flush_pipe := ex_reg_flush_pipe - mem_reg_slow_bypass := ex_slow_bypass - mem_reg_wphit := ex_reg_wphit - mem_reg_set_vconfig := ex_reg_set_vconfig - - mem_reg_cause := ex_cause - mem_reg_inst := ex_reg_inst - mem_reg_raw_inst := ex_reg_raw_inst - mem_reg_mem_size := ex_reg_mem_size - mem_reg_hls_or_dv := io.dmem.req.bits.dv - mem_reg_pc := ex_reg_pc - // IDecode ensured they are 1H - mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) - mem_br_taken := alu.io.cmp_out - - - when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { - val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) - mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data - } - if (usingVector) { when (ex_reg_set_vconfig) { - mem_reg_rs2 := ex_new_vconfig.get.asUInt - } } - when (ex_ctrl.jalr && csr.io.status.debug) { - // flush I$ on D-mode JALR to effect uncached fetch without D$ flush - mem_ctrl.fence_i := true.B - mem_reg_flush_pipe := true.B - } - } - - val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st) - val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st) - val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( - (mem_debug_breakpoint, CSR.debugTriggerCause.U), - (mem_breakpoint, Causes.breakpoint.U))) - - val (mem_xcpt, mem_cause) = checkExceptions(List( - (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), - (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), - (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) - - val memCoverCauses = (exCoverCauses ++ List( - (CSR.debugTriggerCause, "DEBUG_TRIGGER"), - (Causes.breakpoint, "BREAKPOINT"), - (Causes.misaligned_fetch, "MISALIGNED_FETCH") - )).distinct - coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) - - val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port - val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem - val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) - val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) - val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all - val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid - div.io.kill := killm_common && RegNext(div.io.req.fire) - val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem - - // writeback stage - wb_reg_valid := !ctrl_killm - wb_reg_replay := replay_mem && !take_pc_wb - wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) - wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe - when (mem_pc_valid) { - wb_ctrl := mem_ctrl - wb_reg_sfence := mem_reg_sfence - wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) - when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) { - wb_reg_rs2 := mem_reg_rs2 - } - wb_reg_cause := mem_cause - wb_reg_inst := mem_reg_inst - wb_reg_raw_inst := mem_reg_raw_inst - wb_reg_mem_size := mem_reg_mem_size - wb_reg_hls_or_dv := mem_reg_hls_or_dv - wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV - wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG - wb_reg_pc := mem_reg_pc - wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) } - wb_reg_set_vconfig := mem_reg_set_vconfig - } - - val (wb_xcpt, wb_cause) = checkExceptions(List( - (wb_reg_xcpt, wb_reg_cause), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), - (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) - )) - - val wbCoverCauses = List( - (Causes.misaligned_store, "MISALIGNED_STORE"), - (Causes.misaligned_load, "MISALIGNED_LOAD"), - (Causes.store_access, "STORE_ACCESS"), - (Causes.load_access, "LOAD_ACCESS") - ) ++ (if(usingVM) List( - (Causes.store_page_fault, "STORE_PAGE_FAULT"), - (Causes.load_page_fault, "LOAD_PAGE_FAULT") - ) else Nil) ++ (if (usingHypervisor) List( - (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), - (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), - ) else Nil) - coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) - - val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt - val wb_wxd = wb_reg_valid && wb_ctrl.wxd - val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec - val replay_wb_common = io.dmem.s2_nack || wb_reg_replay - val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready - val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall - val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) - val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec - take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe - - // writeback arbitration - val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool - val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool - val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) - val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data - val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay - - class LLWB extends Bundle { - val data = UInt(xLen.W) - val tag = UInt(5.W) - } - - val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec - ll_arb.io.in.foreach(_.valid := false.B) - ll_arb.io.in.foreach(_.bits := DontCare) - val ll_wdata = WireInit(ll_arb.io.out.bits.data) - val ll_waddr = WireInit(ll_arb.io.out.bits.tag) - val ll_wen = WireInit(ll_arb.io.out.fire) - ll_arb.io.out.ready := !wb_wxd - - div.io.resp.ready := ll_arb.io.in(0).ready - ll_arb.io.in(0).valid := div.io.resp.valid - ll_arb.io.in(0).bits.data := div.io.resp.bits.data - ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag - - if (usingRoCC) { - io.rocc.resp.ready := ll_arb.io.in(1).ready - ll_arb.io.in(1).valid := io.rocc.resp.valid - ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data - ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd - } else { - // tie off RoCC - io.rocc.resp.ready := false.B - io.rocc.mem.req.ready := false.B - } - - io.vector.map { v => - v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) - ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp - ll_arb.io.in(2).bits.data := v.resp.bits.data - ll_arb.io.in(2).bits.tag := v.resp.bits.rd - } - // Dont care mem since not all RoCC need accessing memory - io.rocc.mem := DontCare - - when (dmem_resp_replay && dmem_resp_xpu) { - ll_arb.io.out.ready := false.B - ll_waddr := dmem_resp_waddr - ll_wen := true.B - } - - val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt - val wb_wen = wb_valid && wb_ctrl.wxd - val rf_wen = wb_wen || ll_wen - val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) - val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), - Mux(ll_wen, ll_wdata, - Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, - Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), - wb_reg_wdata)))) - when (rf_wen) { rf.write(rf_waddr, rf_wdata) } - - // hook up control/status regfile - csr.io.ungated_clock := clock - csr.io.decode(0).inst := id_inst(0) - csr.io.exception := wb_xcpt - csr.io.cause := wb_cause - csr.io.retire := wb_valid - csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) - csr.io.interrupts := io.interrupts - csr.io.hartid := io.hartid - io.fpu.fcsr_rm := csr.io.fcsr_rm - val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) - val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) - csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid - csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) - io.fpu.time := csr.io.time(31,0) - io.fpu.hartid := io.hartid - csr.io.rocc_interrupt := io.rocc.interrupt - csr.io.pc := wb_reg_pc - - val tval_dmem_addr = !wb_reg_xcpt - val tval_any_addr = tval_dmem_addr || - wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) - val tval_inst = wb_reg_cause === Causes.illegal_instruction.U - val tval_valid = wb_xcpt && (tval_any_addr || tval_inst) - csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv) - csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) - val (htval, mhtinst_read_pseudo) = { - val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U - val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) - assert(!htval_valid_imem || io.imem.gpa.valid) - - val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR - val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) - - val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits - // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation - val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem) - (htval, mhtinst_read_pseudo) - } - - csr.io.vector.foreach { v => - v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid - v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) - v.set_vs_dirty := wb_valid && wb_ctrl.vec - v.set_vstart.valid := wb_valid && wb_reg_set_vconfig - v.set_vstart.bits := 0.U - } - - io.vector.foreach { v => - when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) { - csr.io.pc := v.wb.pc - csr.io.retire := v.wb.retire - csr.io.inst(0) := v.wb.inst - when (v.wb.xcpt && !wb_reg_xcpt) { - wb_xcpt := true.B - wb_cause := v.wb.cause - csr.io.tval := v.wb.tval - } - } - v.wb.store_pending := io.dmem.store_pending - v.wb.vxrm := csr.io.vector.get.vxrm - v.wb.frm := csr.io.fcsr_rm - csr.io.vector.get.set_vxsat := v.set_vxsat - when (v.set_vconfig.valid) { - csr.io.vector.get.set_vconfig.valid := true.B - csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits - } - when (v.set_vstart.valid) { - csr.io.vector.get.set_vstart.valid := true.B - csr.io.vector.get.set_vstart.bits := v.set_vstart.bits - } - } - - csr.io.htval := htval - csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo - io.ptw.ptbr := csr.io.ptbr - io.ptw.hgatp := csr.io.hgatp - io.ptw.vsatp := csr.io.vsatp - (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } - io.ptw.status := csr.io.status - io.ptw.hstatus := csr.io.hstatus - io.ptw.gstatus := csr.io.gstatus - io.ptw.pmp := csr.io.pmp - csr.io.rw.addr := wb_reg_inst(31,20) - csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) - csr.io.rw.wdata := wb_reg_wdata - - - io.rocc.csrs <> csr.io.roccCSRs - io.trace.time := csr.io.time - io.trace.insns := csr.io.trace - if (rocketParams.debugROB.isDefined) { - val sz = rocketParams.debugROB.get.size - if (sz < 1) { // use unsynthesizable ROB - val csr_trace_with_wdata = WireInit(csr.io.trace(0)) - csr_trace_with_wdata.wdata.get := rf_wdata - val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) - val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) - val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) - - io.vector.foreach { v => when (v.wb.retire) { - should_wb := v.wb.rob_should_wb - has_wb := false.B - wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) - }} - - DebugROB.pushTrace(clock, reset, - io.hartid, csr_trace_with_wdata, - should_wb, has_wb, wb_addr) - - io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) - - DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) - } else { // synthesizable ROB (no FPRs) - require(!usingVector, "Synthesizable ROB does not support vector implementations") - val csr_trace_with_wdata = WireInit(csr.io.trace(0)) - csr_trace_with_wdata.wdata.get := rf_wdata - - val debug_rob = Module(new HardDebugROB(sz, 32)) - debug_rob.io.i_insn := csr_trace_with_wdata - debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && - !csr.io.trace(0).exception - debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard - debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) - - debug_rob.io.wb_val := ll_wen - debug_rob.io.wb_tag := rf_waddr - debug_rob.io.wb_data := rf_wdata - - io.trace.insns(0) := debug_rob.io.o_insn - } - } else { - io.trace.insns := csr.io.trace - } - for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { - iobpw.valid(0) := wphit - iobpw.action := bp.control.action - // tie off bpwatch valids - iobpw.rvalid.foreach(_ := false.B) - iobpw.wvalid.foreach(_ := false.B) - iobpw.ivalid.foreach(_ := false.B) - } - - val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), - (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), - (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) - val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), - (io.fpu.dec.ren2, id_raddr2), - (io.fpu.dec.ren3, id_raddr3), - (io.fpu.dec.wen, id_waddr)) - - val sboard = new Scoreboard(32, true) - sboard.clear(ll_wen, ll_waddr) - def id_sboard_clear_bypass(r: UInt) = { - // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check - if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r - else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r - } - val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) - sboard.set(wb_set_sboard && wb_wen, wb_waddr) - - // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. - val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec - val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) - val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) - val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) - - // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. - val mem_mem_cmd_bh = - if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass - else true.B - val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec - val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) - val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) - val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem) - id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem - val id_vconfig_hazard = id_ctrl.vec && ( - (ex_reg_valid && ex_reg_set_vconfig) || - (mem_reg_valid && mem_reg_set_vconfig) || - (wb_reg_valid && wb_reg_set_vconfig)) - - // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. - val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) - val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) - val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) - - val id_stall_fpu = if (usingFPU) { - val fp_sboard = new Scoreboard(32) - fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) - val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) - fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) - fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) - - checkHazards(fp_hazard_targets, fp_sboard.read _) - } else false.B - - val dcache_blocked = { - // speculate that a blocked D$ will unblock the cycle after a Grant - val blocked = Reg(Bool()) - blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack) - blocked && !io.dmem.perf.grant - } - val rocc_blocked = Reg(Bool()) - rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked) - - val ctrl_stalld = - id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || - id_vconfig_hazard || - csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) || - id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy || - id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy || - id_ctrl.fp && id_stall_fpu || - id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses - id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy - id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay - !clock_en || - id_do_fence || io.rocc.busy || - csr.io.csr_stall || - id_reg_pause || - io.traceStall - ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt - - io.imem.req.valid := take_pc - io.imem.req.bits.speculative := !take_pc_wb - io.imem.req.bits.pc := - Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret - Mux(replay_wb, wb_reg_pc, // replay - mem_npc)) // flush or branch misprediction - io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack - io.imem.might_request := { - imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B) - imem_might_request_reg - } - io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) - io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence - io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) - io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) - io.imem.sfence.bits.addr := wb_reg_wdata - io.imem.sfence.bits.asid := wb_reg_rs2 - io.imem.sfence.bits.hv := wb_reg_hfence_v - io.imem.sfence.bits.hg := wb_reg_hfence_g - io.ptw.sfence := io.imem.sfence - - ibuf.io.inst(0).ready := !ctrl_stalld - - io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken) - io.imem.btb_update.bits.isValid := mem_cfi - io.imem.btb_update.bits.cfiType := - Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call, - Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, - Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump, - CFIType.branch))) - io.imem.btb_update.bits.target := io.imem.req.bits.pc - io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) - io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U) - io.imem.btb_update.bits.prediction := mem_reg_btb_resp - io.imem.btb_update.bits.taken := DontCare - - io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb - io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc - io.imem.bht_update.bits.taken := mem_br_taken - io.imem.bht_update.bits.mispredict := mem_wrong_npc - io.imem.bht_update.bits.branch := mem_ctrl.branch - io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht - - // Connect RAS in Frontend - io.imem.ras_update := DontCare - - io.fpu.valid := !ctrl_killd && id_ctrl.fp - io.fpu.killx := ctrl_killx - io.fpu.killm := killm_common - io.fpu.inst := id_inst(0) - io.fpu.fromint_data := ex_rs(0) - io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu - io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) - io.fpu.ll_resp_type := io.dmem.resp.bits.size - io.fpu.ll_resp_tag := dmem_resp_waddr - io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate - - io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) - - io.vector.map { v => - when (!(dmem_resp_valid && dmem_resp_fpu)) { - io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp - io.fpu.ll_resp_data := v.resp.bits.data - io.fpu.ll_resp_type := v.resp.bits.size - io.fpu.ll_resp_tag := v.resp.bits.rd - } - } - - io.vector.foreach { v => - v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx - v.ex.inst := ex_reg_inst - v.ex.vconfig := csr.io.vector.get.vconfig - v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) - v.ex.rs1 := ex_rs(0) - v.ex.rs2 := ex_rs(1) - v.ex.pc := ex_reg_pc - v.mem.frs1 := io.fpu.store_data - v.killm := killm_common - v.status := csr.io.status - } - - - io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem - val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) - require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) - io.dmem.req.bits.tag := ex_dcache_tag - io.dmem.req.bits.cmd := ex_ctrl.mem_cmd - io.dmem.req.bits.size := ex_reg_mem_size - io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) - io.dmem.req.bits.phys := false.B - io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) - io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) - io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) - io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv - io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U) - io.dmem.req.bits.no_alloc := DontCare - io.dmem.req.bits.no_xcpt := DontCare - io.dmem.req.bits.data := DontCare - io.dmem.req.bits.mask := DontCare - - io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) - io.dmem.s1_data.mask := DontCare - - io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem - io.dmem.s2_kill := false.B - // don't let D$ go to sleep if we're probably going to use it soon - io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall - - io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common - io.rocc.exception := wb_xcpt && csr.io.status.xs.orR - io.rocc.cmd.bits.status := csr.io.status - io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) - io.rocc.cmd.bits.rs1 := wb_reg_wdata - io.rocc.cmd.bits.rs2 := wb_reg_rs2 - - // gate the clock - val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc - when (unpause) { id_reg_pause := false.B } - io.cease := csr.io.status.cease && !clock_en_reg - io.wfi := csr.io.status.wfi - if (rocketParams.clockGate) { - long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause - clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid) - clock_en_reg := - ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight - io.ptw.customCSRs.disableCoreClockGate || // chicken bit - !div.io.req.ready || // mul/div in flight - usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight - io.dmem.replay_next || // long-latency load replaying - (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending - - assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en) - } - - // evaluate performance counters - val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid)) - csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } - - val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) - - coreMonitorBundle.clock := clock - coreMonitorBundle.reset := reset - coreMonitorBundle.hartid := io.hartid - coreMonitorBundle.timer := csr.io.time(31,0) - coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception - coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) - coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard - coreMonitorBundle.wrenf := false.B - coreMonitorBundle.wrdst := wb_waddr - coreMonitorBundle.wrdata := rf_wdata - coreMonitorBundle.rd0src := wb_reg_inst(19,15) - coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) - coreMonitorBundle.rd1src := wb_reg_inst(24,20) - coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) - coreMonitorBundle.inst := csr.io.trace(0).insn - coreMonitorBundle.excpt := csr.io.trace(0).exception - coreMonitorBundle.priv_mode := csr.io.trace(0).priv - - if (enableCommitLog) { - val t = csr.io.trace(0) - val rd = wb_waddr - val wfd = wb_ctrl.wfd - val wxd = wb_ctrl.wxd - val has_data = wb_wen && !wb_set_sboard - - when (t.valid && !t.exception) { - when (wfd) { - printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) - } - .elsewhen (wxd && rd =/= 0.U && has_data) { - printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) - } - .elsewhen (wxd && rd =/= 0.U && !has_data) { - printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) - } - .otherwise { - printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) - } - } - - when (ll_wen && rf_waddr =/= 0.U) { - printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) - } - } - else { - when (csr.io.trace(0).valid) { - printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x) wb_xcpt:%d\n", - io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, - coreMonitorBundle.pc, - Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), - Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), - coreMonitorBundle.wrenx, - Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), - Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), - Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), - Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), - coreMonitorBundle.inst, coreMonitorBundle.inst, wb_xcpt) - } - } - - // CoreMonitorBundle for late latency writes - val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) - - xrfWriteBundle.clock := clock - xrfWriteBundle.reset := reset - xrfWriteBundle.hartid := io.hartid - xrfWriteBundle.timer := csr.io.time(31,0) - xrfWriteBundle.valid := false.B - xrfWriteBundle.pc := 0.U - xrfWriteBundle.wrdst := rf_waddr - xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) - xrfWriteBundle.wrenf := false.B - xrfWriteBundle.wrdata := rf_wdata - xrfWriteBundle.rd0src := 0.U - xrfWriteBundle.rd0val := 0.U - xrfWriteBundle.rd1src := 0.U - xrfWriteBundle.rd1val := 0.U - xrfWriteBundle.inst := 0.U - xrfWriteBundle.excpt := false.B - xrfWriteBundle.priv_mode := csr.io.trace(0).priv - - if (rocketParams.haveSimTimeout) PlusArg.timeout( - name = "max_core_cycles", - docstring = "Kill the emulation after INT rdtime cycles. Off if 0." - )(csr.io.time) - - } // leaving gated-clock domain - val rocketImpl = withClock (gated_clock) { new RocketImpl } - - def checkExceptions(x: Seq[(Bool, UInt)]) = - (WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x))) - - def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { - for ((coverCause, label) <- coverCausesLabels) { - property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") - } - } - - def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = - targets.map(h => h._1 && cond(h._2)).reduce(_||_) - - def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { - // efficient means to compress 64-bit VA into vaddrBits+1 bits - // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) - val b = vaddrBitsExtended-1 - val a = (a0 >> b).asSInt - val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1)) - Cat(msb, ea(b-1, 0)) - } - - class Scoreboard(n: Int, zero: Boolean = false) - { - def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) - def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) - def read(addr: UInt): Bool = r(addr) - def readBypassed(addr: UInt): Bool = _next(addr) - - private val _r = RegInit(0.U(n.W)) - private val r = if (zero) (_r >> 1 << 1) else _r - private var _next = r - private var ens = false.B - private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) - private def update(en: Bool, update: UInt) = { - _next = update - ens = ens || en - when (ens) { _r := _next } - } - } -} - -class RegFile(n: Int, w: Int, zero: Boolean = false) { - val rf = Mem(n, UInt(w.W)) - private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) - private val reads = ArrayBuffer[(UInt,UInt)]() - private var canRead = true - def read(addr: UInt) = { - require(canRead) - reads += addr -> Wire(UInt()) - reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) - reads.last._2 - } - def write(addr: UInt, data: UInt) = { - canRead = false - when (addr =/= 0.U) { - access(addr) := data - for ((raddr, rdata) <- reads) - when (addr === raddr) { rdata := data } - } - } -} - -object ImmGen { - def apply(sel: UInt, inst: UInt) = { - val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) - val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) - val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) - val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S, - Mux(sel === IMM_UJ, inst(20).asSInt, - Mux(sel === IMM_SB, inst(7).asSInt, sign))) - val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25)) - val b4_1 = Mux(sel === IMM_U, 0.U, - Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), - Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) - val b0 = Mux(sel === IMM_S, inst(7), - Mux(sel === IMM_I, inst(20), - Mux(sel === IMM_Z, inst(15), 0.U))) - - Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt - } -} diff --git a/arch/src/main/scala/framework/switcher/README.md b/arch/src/main/scala/framework/switcher/README.md deleted file mode 100644 index d2092788..00000000 --- a/arch/src/main/scala/framework/switcher/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# Switcher Module - -This directory contains two small but critical adapters that translate between Ball devices' physical memory ports and a unified "virtual line" representation. - -- `ToVirtualLine`: Merges SPAD/ACC physical ports into a uniform virtual interface carrying metadata (`is_acc`, `bank_id`, `rob_id`). -- `ToPhysicalLine`: Restores the virtual interface back into physical SPAD/ACC ports, preserving data and `rob_id`. - -## Goals -- **Unified view**: Provide a single, consistent interface for memory requests and responses regardless of origin (SPAD or ACC). -- **Explicit metadata**: Attach `is_acc`, `bank_id`, and `rob_id` so downstream routing and accounting are straightforward. -- **Clear behavior**: Support either bank-sharing with arbitration or segmented direct mapping, depending on system choice. -- **Type correctness**: Keep widths and masks consistent; no implicit format conversions. - -## Interfaces -- Physical ports: - - `SramReadWithRobId(n, w)`: wraps `SramReadIO(n, w)` plus `rob_id`. - - `SramWriteWithRobId(n, w, mask_len)`: wraps `SramWriteIO(n, w, mask_len)` plus `rob_id`. -- Virtual ports: - - `SramReadWithInfo(n, w)`: `SramReadIO` plus `rob_id`, `is_acc` (Bool), `bank_id`. - - `SramWriteWithInfo(n, w, mask_len)`: `SramWriteIO` plus the same metadata. -- Widths: - - `rob_id` depends on `b.rob_entries`. - - `bank_id` wide enough for `b.sp_banks + b.acc_banks`. - - `is_acc` is a `Bool`. - -## ToVirtualLine -- Inputs: - - `sramRead_i/sramWrite_i`: size `b.sp_banks`. - - `accRead_i/accWrite_i`: size `b.acc_banks`. -- Outputs: - - `sramRead_o/sramWrite_o`: virtual lines. -- Port count (choose one design and keep consistent): - - **Max** design: `numBanks = max(b.sp_banks, b.acc_banks)`. Shared banks arbitrate (typically SPAD priority); tail banks connect to whichever exists. - - **Sum** design: `numBanks = b.sp_banks + b.acc_banks`. Lower range maps SPAD; upper range maps ACC. No arbitration; direct mapping with metadata. -- Read path: - - Drive `req` from physical to virtual; broadcast `resp` from virtual to the selected physical endpoint, using `ready` to consume. - - Set `rob_id/is_acc/bank_id` based on origin and index. Use `false.B/true.B` for `is_acc`. -- Write path: - - Map write `addr/data/mask` and metadata to virtual lines. - - No `resp` channel on writes; only handshake and field mapping. - -## ToPhysicalLine -- Inputs: - - `sramRead_i/sramWrite_i`: virtual lines (same size as ToVirtualLine outputs). -- Outputs: - - `sramRead_o/sramWrite_o`: size `b.sp_banks`. - - `accRead_o/accWrite_o`: size `b.acc_banks`. -- Routing: - - **Max** design: Use `is_acc` and `bank_id` to select the ACC bank; SPAD uses the virtual index `i`. - - **Sum** design: Lower (SPAD) and upper (ACC) segments map 1:1 back to physical ports; `bank_id` marks the internal index. -- Timing notes: - - If read `resp` and meta signals form a combinational loop, consider `RegNext` on meta to break it. - -## Integration -- In `bbus`, each Ball connects physical ports → `ToVirtualLine` → virtual interface. -- Then `ToPhysicalLine` restores to physical ports that connect to `MemRouter`. -- If a strict direct-connect behavior is desired, use the **Sum** design and ensure both sides agree on vector sizes. - -## Common Pitfalls -- Assigning `0.U/1.U` to `is_acc` (must be `false.B/true.B`). -- Using `io.sramRead_i(j)` instead of `io.accRead_i(i)` for ACC reads. -- Typos like `b.acc_Banks` (should be `b.acc_banks`). -- Dangling logical operators (e.g., trailing `||`) causing compile errors. -- Missing write-path mapping, leaving `ready` low and blocking writes. - -## Recommendations -- Decide upfront: **Max + arbitration** vs **Sum + segmented direct mapping** and keep both modules and top-level wiring consistent. -- Align priority policy (SPAD vs ACC) with system requirements if using shared-bank arbitration. -- Keep `rob_id` and `bank_id` consistent to avoid accounting and replay issues. diff --git a/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala b/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala deleted file mode 100644 index 4d43edf1..00000000 --- a/arch/src/main/scala/framework/switcher/ToPhysicalLine.scala +++ /dev/null @@ -1,141 +0,0 @@ -package framework.switcher - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.blink.{SramReadWithInfo, SramWriteWithInfo} - -class ToPhysicalLine(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - - private val numBanks = b.sp_banks + b.acc_banks - - val io = IO(new Bundle { - // Unified virtual input ports (from ToVirtualLine) - val sramRead_i = Vec(numBanks, new SramReadWithInfo(b.spad_bank_entries, b.spad_w)) - val sramWrite_i = Vec(numBanks, new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - - // Physical memory endpoints - val sramRead_o = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val sramWrite_o = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - - val accRead_o = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accWrite_o = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) - }) - - // -------------------------------------------------------------------------- - // Default initialization for all physical ports - // -------------------------------------------------------------------------- - - // SPAD read/write ports - for (i <- 0 until b.sp_banks) { - val spR = io.sramRead_o(i) - spR.req.valid := false.B - spR.req.bits := DontCare - spR.resp.ready := false.B - - val spW = io.sramWrite_o(i) - spW.req.valid := false.B - spW.req.bits := DontCare - } - - // ACC read/write ports - for (i <- 0 until b.acc_banks) { - val accR = io.accRead_o(i) - accR.req.valid := false.B - accR.req.bits := DontCare - accR.resp.ready := false.B - - val accW = io.accWrite_o(i) - accW.req.valid := false.B - accW.req.bits := DontCare - } - - // Default values for all virtual ports - for (i <- 0 until numBanks) { - val vR = io.sramRead_i(i) - vR.io.req.ready := false.B - vR.io.resp.valid := false.B - vR.io.resp.bits := DontCare - - val vW = io.sramWrite_i(i) - vW.io.req.ready := false.B - } - - // -------------------------------------------------------------------------- - // Read routing: virtual → SPAD (indices 0 .. sp_banks-1) - // -------------------------------------------------------------------------- - - for (i <- 0 until b.sp_banks) { - val vR = io.sramRead_i(i) - val spR = io.sramRead_o(i) - - // Request path (virtual → SPAD) - spR.req.valid := vR.io.req.valid - spR.req.bits.addr := vR.io.req.bits.addr - spR.req.bits.fromDMA := vR.io.req.bits.fromDMA - - vR.io.req.ready := spR.req.ready - - // Response path (SPAD → virtual) - vR.io.resp.valid := spR.resp.valid - vR.io.resp.bits := spR.resp.bits - spR.resp.ready := vR.io.resp.ready - } - - // -------------------------------------------------------------------------- - // Read routing: virtual → ACC (indices sp_banks .. sp_banks+acc_banks-1) - // -------------------------------------------------------------------------- - - for (i <- 0 until b.acc_banks) { - val idx = i + b.sp_banks - val vR = io.sramRead_i(idx) - val accR = io.accRead_o(i) - - // Request path (virtual → ACC) - accR.req.valid := vR.io.req.valid - accR.req.bits.addr := vR.io.req.bits.addr - accR.req.bits.fromDMA := vR.io.req.bits.fromDMA - - vR.io.req.ready := accR.req.ready - - // Response path (ACC → virtual) - vR.io.resp.valid := accR.resp.valid - vR.io.resp.bits := accR.resp.bits - accR.resp.ready := vR.io.resp.ready - } - - // -------------------------------------------------------------------------- - // Write routing: virtual → SPAD - // -------------------------------------------------------------------------- - - for (i <- 0 until b.sp_banks) { - val vW = io.sramWrite_i(i) - val spW = io.sramWrite_o(i) - - spW.req.valid := vW.io.req.valid - spW.req.bits.addr := vW.io.req.bits.addr - spW.req.bits.data := vW.io.req.bits.data - spW.req.bits.mask := vW.io.req.bits.mask - - vW.io.req.ready := spW.req.ready - } - - // -------------------------------------------------------------------------- - // Write routing: virtual → ACC - // -------------------------------------------------------------------------- - - for (i <- 0 until b.acc_banks) { - val idx = i + b.sp_banks - val vW = io.sramWrite_i(idx) - val accW = io.accWrite_o(i) - - accW.req.valid := vW.io.req.valid - accW.req.bits.addr := vW.io.req.bits.addr - accW.req.bits.data := vW.io.req.bits.data - accW.req.bits.mask := vW.io.req.bits.mask - - vW.io.req.ready := accW.req.ready - } -} \ No newline at end of file diff --git a/arch/src/main/scala/framework/switcher/ToVirtuaLine.scala b/arch/src/main/scala/framework/switcher/ToVirtuaLine.scala deleted file mode 100644 index 76e07780..00000000 --- a/arch/src/main/scala/framework/switcher/ToVirtuaLine.scala +++ /dev/null @@ -1,167 +0,0 @@ -package framework.switcher - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq, SramReadResp, SramWriteReq} -import framework.balldomain.blink.{SramReadWithRobId, SramWriteWithRobId, SramReadWithInfo, SramWriteWithInfo} - -class ToVirtualLine(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - // Total number of unified virtual banks = sp_banks + acc_banks - private val numBanks = b.sp_banks + b.acc_banks - - val io = IO(new Bundle { - // Physical SRAM/ACC ports - val sramRead_i = Vec(b.sp_banks, new SramReadWithRobId(b.spad_bank_entries, b.spad_w)) - val sramWrite_i = Vec(b.sp_banks, new SramWriteWithRobId(b.spad_bank_entries, b.spad_w, b.spad_mask_len)) - val accRead_i = Vec(b.acc_banks, new SramReadWithRobId(b.acc_bank_entries, b.acc_w)) - val accWrite_i = Vec(b.acc_banks, new SramWriteWithRobId(b.acc_bank_entries, b.acc_w, b.acc_mask_len)) - - // Unified virtual interface - val sramRead_o = Vec(numBanks, Flipped(new SramReadWithInfo(b.spad_bank_entries, b.spad_w))) - val sramWrite_o = Vec(numBanks, Flipped(new SramWriteWithInfo(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) - }) - - // -------------------------------------------------------------------------- - // Default initialization for virtual output banks - // -------------------------------------------------------------------------- - - for (i <- 0 until numBanks) { - val vr = io.sramRead_o(i) - vr.io.req.valid := false.B - vr.io.req.bits := DontCare - vr.io.resp.ready := false.B - vr.is_acc := false.B - vr.bank_id := 0.U - vr.rob_id := 0.U - - val vw = io.sramWrite_o(i) - vw.io.req.valid := false.B - vw.io.req.bits := DontCare - vw.is_acc := false.B - vw.bank_id := 0.U - vw.rob_id := 0.U - } - - // Default init for physical inputs - for (i <- 0 until b.sp_banks) { - val spR = io.sramRead_i(i) - spR.io.req.ready := false.B - spR.io.resp.valid := false.B - spR.io.resp.bits := DontCare - - val spW = io.sramWrite_i(i) - spW.io.req.ready := false.B - } - - for (i <- 0 until b.acc_banks) { - val accR = io.accRead_i(i) - accR.io.req.ready := false.B - accR.io.resp.valid := false.B - accR.io.resp.bits := DontCare - - val accW = io.accWrite_i(i) - accW.io.req.ready := false.B - } - - // -------------------------------------------------------------------------- - // Read Path Routing: SPAD → virtual line (low bank index range) - // -------------------------------------------------------------------------- - - for (i <- 0 until b.sp_banks) { - val vR = io.sramRead_o(i) - val sp = io.sramRead_i(i) - val spRq = sp.io.req - - val selSp = spRq.valid - - vR.io.req.valid := selSp - spRq.ready := selSp && vR.io.req.ready - - vR.io.req.bits.addr := spRq.bits.addr - vR.io.req.bits.fromDMA := spRq.bits.fromDMA - - vR.is_acc := false.B - vR.bank_id := i.U(vR.bank_id.getWidth.W) - vR.rob_id := sp.rob_id - - sp.io.resp.valid := vR.io.resp.valid - sp.io.resp.bits := vR.io.resp.bits - vR.io.resp.ready := sp.io.resp.ready && selSp - } - - // -------------------------------------------------------------------------- - // Read Path Routing: ACC → virtual line (higher bank index range) - // -------------------------------------------------------------------------- - - for (i <- 0 until b.acc_banks) { - val j = i + b.sp_banks - val vR = io.sramRead_o(j) - val acc = io.accRead_i(i) - val accRq = acc.io.req - - val selAcc = accRq.valid - - vR.io.req.valid := selAcc - accRq.ready := selAcc && vR.io.req.ready - - vR.io.req.bits.addr := accRq.bits.addr - vR.io.req.bits.fromDMA := accRq.bits.fromDMA - - vR.is_acc := true.B - vR.bank_id := i.U(vR.bank_id.getWidth.W) - vR.rob_id := acc.rob_id - - acc.io.resp.valid := vR.io.resp.valid - acc.io.resp.bits := vR.io.resp.bits - vR.io.resp.ready := acc.io.resp.ready && selAcc - } - - // -------------------------------------------------------------------------- - // Write Path Routing: SPAD → virtual line - // -------------------------------------------------------------------------- - - for (i <- 0 until b.sp_banks) { - val vW = io.sramWrite_o(i) - val sp = io.sramWrite_i(i) - val spRq = sp.io.req - - val selSp = spRq.valid - - vW.io.req.valid := selSp - spRq.ready := selSp && vW.io.req.ready - - vW.io.req.bits.addr := spRq.bits.addr - vW.io.req.bits.data := spRq.bits.data - vW.io.req.bits.mask := spRq.bits.mask - - vW.is_acc := false.B - vW.bank_id := i.U(vW.bank_id.getWidth.W) - vW.rob_id := sp.rob_id - } - - // -------------------------------------------------------------------------- - // Write Path Routing: ACC → virtual line - // -------------------------------------------------------------------------- - - for (i <- 0 until b.acc_banks) { - val j = i + b.sp_banks - val vW = io.sramWrite_o(j) - val acc = io.accWrite_i(i) - val accRq = acc.io.req - - val selAcc = accRq.valid - - vW.io.req.valid := selAcc - accRq.ready := selAcc && vW.io.req.ready - - vW.io.req.bits.addr := accRq.bits.addr - vW.io.req.bits.data := accRq.bits.data - vW.io.req.bits.mask := accRq.bits.mask - - vW.is_acc := true.B - vW.bank_id := i.U(vW.bank_id.getWidth.W) - vW.rob_id := acc.rob_id - } -} diff --git a/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala b/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala index e64742cb..0d794aad 100644 --- a/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala +++ b/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala @@ -2,11 +2,14 @@ package prototype.abft import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status +import prototype.abft.configs.ABFTConfig /** * ABFTSystolicArray - Simple systolic array with ABFT (Algorithm-Based Fault Tolerance) @@ -17,22 +20,33 @@ import framework.balldomain.blink.Status * - Result matrix C will have checksum row and column * - Verify checksums match to detect errors * - * Simple implementation: process veclane x veclane tiles + * Simple implementation: process InputNum x InputNum tiles */ -class ABFTSystolicArray(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +@instantiable +class ABFTSystolicArray(val parameter: ABFTConfig)(implicit p: Parameters) + extends Module + with SerializableModule[ABFTConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val accWidth = 32 + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // Command interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) - // Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + // Unified bank read/write interface + val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + val bankWrite = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - // Accumulator write interface (for partial sums) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + // Unified bank write interface for accumulator writes (accumulate mode) + val bankWriteAcc = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, accWidth, ballParam.bankMaskLen))) // Status output val status = new Status @@ -40,165 +54,165 @@ class ABFTSystolicArray(implicit b: CustomBuckyballConfig, p: Parameters) extend // State machine val idle :: sLoadA :: sLoadB :: sCompute :: sWrite :: sCheck :: complete :: Nil = Enum(7) - val state = RegInit(idle) + val state = RegInit(idle) - // Registers for matrix A (veclane x veclane) + // Registers for matrix A (InputNum x InputNum) val matrixA = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.S(b.inputType.getWidth.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.S(inputWidth.W))) )) ) - // Registers for matrix B (veclane x veclane) + // Registers for matrix B (InputNum x InputNum) val matrixB = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.S(b.inputType.getWidth.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.S(inputWidth.W))) )) ) - // Result matrix C (veclane x veclane) + // Result matrix C (InputNum x InputNum) val matrixC = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.S(32.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.S(32.W))) )) ) // Checksum registers - val checksumA_row = RegInit(VecInit(Seq.fill(b.veclane)(0.S(32.W)))) - val checksumB_col = RegInit(VecInit(Seq.fill(b.veclane)(0.S(32.W)))) - val checksumC_row = RegInit(VecInit(Seq.fill(b.veclane)(0.S(32.W)))) - val checksumC_col = RegInit(VecInit(Seq.fill(b.veclane)(0.S(32.W)))) + val checksumA_row = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) + val checksumB_col = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) + val checksumC_row = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) + val checksumC_col = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) // Counters - val rowCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val colCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val rowCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val colCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) // Instruction registers - val robid_reg = RegInit(0.U(10.W)) + val robid_reg = RegInit(0.U(10.W)) val op1_addr_reg = RegInit(0.U(10.W)) - val op1_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val op1_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) val op2_addr_reg = RegInit(0.U(10.W)) - val op2_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val wr_addr_reg = RegInit(0.U(10.W)) - val wr_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) - val cycle_reg = RegInit(0.U(6.W)) - val iterCnt = RegInit(0.U(32.W)) + val op2_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val wr_addr_reg = RegInit(0.U(10.W)) + val wr_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) + val cycle_reg = RegInit(0.U(6.W)) + val iterCnt = RegInit(0.U(32.W)) // Error detection flag val errorDetected = RegInit(false.B) // Write data register - val writeDataReg = Reg(UInt(spad_w.W)) - val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) // Default SRAM assignments - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := false.B + + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // Default accumulator assignments - for (i <- 0 until b.acc_banks) { - io.accWrite(i).req.valid := false.B - io.accWrite(i).req.bits.addr := 0.U - io.accWrite(i).req.bits.data := 0.U - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankWriteAcc(i).req.valid := false.B + io.bankWriteAcc(i).req.bits.addr := 0.U + io.bankWriteAcc(i).req.bits.data := 0.U + io.bankWriteAcc(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // Command interface defaults - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sLoadA - readCounter := 0.U - rowCounter := 0.U - colCounter := 0.U - writeCounter := 0.U + state := sLoadA + readCounter := 0.U + rowCounter := 0.U + colCounter := 0.U + writeCounter := 0.U errorDetected := false.B - robid_reg := io.cmdReq.bits.rob_id - op1_addr_reg := io.cmdReq.bits.cmd.op1_bank_addr + robid_reg := io.cmdReq.bits.rob_id + op1_addr_reg := 0.U // New ISA: all operations start from row 0 op1_bank_reg := io.cmdReq.bits.cmd.op1_bank - op2_addr_reg := io.cmdReq.bits.cmd.op2_bank_addr + op2_addr_reg := 0.U // New ISA: all operations start from row 0 op2_bank_reg := io.cmdReq.bits.cmd.op2_bank - wr_addr_reg := io.cmdReq.bits.cmd.wr_bank_addr - wr_bank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (b.veclane.U - 1.U)) / b.veclane.U - 1.U + wr_addr_reg := 0.U // New ISA: all operations start from row 0 + wr_bank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter + cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U } } is(sLoadA) { // Load matrix A row by row - when(readCounter < b.veclane.U) { - io.sramRead(op1_bank_reg).req.valid := true.B - io.sramRead(op1_bank_reg).req.bits.addr := op1_addr_reg + readCounter - readCounter := readCounter + 1.U + when(readCounter < InputNum.U) { + io.bankRead(op1_bank_reg).req.valid := true.B + io.bankRead(op1_bank_reg).req.bits.addr := op1_addr_reg + readCounter + readCounter := readCounter + 1.U } - io.sramRead(op1_bank_reg).resp.ready := true.B - when(io.sramRead(op1_bank_reg).resp.fire) { - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth - val raw = io.sramRead(op1_bank_reg).resp.bits.data(hi, lo) + io.bankRead(op1_bank_reg).resp.ready := true.B + when(io.bankRead(op1_bank_reg).resp.fire) { + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + val raw = io.bankRead(op1_bank_reg).resp.bits.data(hi, lo) matrixA(rowCounter)(col) := raw.asSInt } rowCounter := rowCounter + 1.U } - when(rowCounter === b.veclane.U) { - state := sLoadB + when(rowCounter === InputNum.U) { + state := sLoadB readCounter := 0.U - rowCounter := 0.U + rowCounter := 0.U // Compute checksum for matrix A (sum of each column) - for (col <- 0 until b.veclane) { - checksumA_row(col) := (0 until b.veclane).map(i => matrixA(i)(col)).reduce(_ + _) + for (col <- 0 until InputNum) { + checksumA_row(col) := (0 until InputNum).map(i => matrixA(i)(col)).reduce(_ + _) } } } is(sLoadB) { // Load matrix B row by row (same as matrix A) - when(readCounter < b.veclane.U) { - io.sramRead(op2_bank_reg).req.valid := true.B - io.sramRead(op2_bank_reg).req.bits.addr := op2_addr_reg + readCounter - readCounter := readCounter + 1.U + when(readCounter < InputNum.U) { + io.bankRead(op2_bank_reg).req.valid := true.B + io.bankRead(op2_bank_reg).req.bits.addr := op2_addr_reg + readCounter + readCounter := readCounter + 1.U } - io.sramRead(op2_bank_reg).resp.ready := true.B - when(io.sramRead(op2_bank_reg).resp.fire) { - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth - val raw = io.sramRead(op2_bank_reg).resp.bits.data(hi, lo) + io.bankRead(op2_bank_reg).resp.ready := true.B + when(io.bankRead(op2_bank_reg).resp.fire) { + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + val raw = io.bankRead(op2_bank_reg).resp.bits.data(hi, lo) matrixB(rowCounter)(col) := raw.asSInt } rowCounter := rowCounter + 1.U } - when(rowCounter === b.veclane.U) { - state := sCompute + when(rowCounter === InputNum.U) { + state := sCompute rowCounter := 0.U colCounter := 0.U // Compute checksum for matrix B (sum of each row) - for (row <- 0 until b.veclane) { - checksumB_col(row) := (0 until b.veclane).map(j => matrixB(row)(j)).reduce(_ + _) + for (row <- 0 until InputNum) { + checksumB_col(row) := (0 until InputNum).map(j => matrixB(row)(j)).reduce(_ + _) } } } @@ -206,19 +220,19 @@ class ABFTSystolicArray(implicit b: CustomBuckyballConfig, p: Parameters) extend is(sCompute) { // Simple systolic array computation: C[i][j] = sum(A[i][k] * B[k][j]) // Compute all elements in one cycle (simple implementation) - for (i <- 0 until b.veclane) { - for (j <- 0 until b.veclane) { - val sum = (0 until b.veclane).map(k => matrixA(i)(k) * matrixB(k)(j)).reduce(_ + _) + for (i <- 0 until InputNum) { + for (j <- 0 until InputNum) { + val sum = (0 until InputNum).map(k => matrixA(i)(k) * matrixB(k)(j)).reduce((a: SInt, b: SInt) => a + b) matrixC(i)(j) := sum } } // Compute checksums for result matrix C - for (col <- 0 until b.veclane) { - checksumC_row(col) := (0 until b.veclane).map(i => matrixC(i)(col)).reduce(_ + _) + for (col <- 0 until InputNum) { + checksumC_row(col) := (0 until InputNum).map(i => matrixC(i)(col)).reduce((a: SInt, b: SInt) => a + b) } - for (row <- 0 until b.veclane) { - checksumC_col(row) := (0 until b.veclane).map(j => matrixC(row)(j)).reduce(_ + _) + for (row <- 0 until InputNum) { + checksumC_col(row) := (0 until InputNum).map(j => matrixC(row)(j)).reduce((a: SInt, b: SInt) => a + b) } state := sCheck @@ -229,60 +243,59 @@ class ABFTSystolicArray(implicit b: CustomBuckyballConfig, p: Parameters) extend // For C = A * B, checksum of row i in C should equal sum(A[i][k] * checksumB_col[k]) // For C = A * B, checksum of col j in C should equal sum(checksumA_row[k] * B[k][j]) // Simple check: verify first row and first column checksums - val expectedRowChecksum = (0 until b.veclane).map(k => - matrixA(0)(k) * checksumB_col(k) - ).reduce(_ + _) + val expectedRowChecksum = + (0 until InputNum).map(k => matrixA(0)(k) * checksumB_col(k)).reduce((a: SInt, b: SInt) => a + b) - val expectedColChecksum = (0 until b.veclane).map(k => - checksumA_row(k) * matrixB(k)(0) - ).reduce(_ + _) + val expectedColChecksum = + (0 until InputNum).map(k => checksumA_row(k) * matrixB(k)(0)).reduce((a: SInt, b: SInt) => a + b) - val rowMatch = checksumC_row(0) === expectedRowChecksum - val colMatch = checksumC_col(0) === expectedColChecksum + val rowMatch = checksumC_row(0) === expectedRowChecksum + val colMatch = checksumC_col(0) === expectedColChecksum errorDetected := !rowMatch || !colMatch - state := sWrite - writeCounter := 0.U + state := sWrite + writeCounter := 0.U // Prepare first write data (clamp 32-bit result to 8-bit) - writeDataReg := Cat((0 until b.veclane).reverse.map(j => { - val clamped = Mux(matrixC(0)(j) > 127.S, 127.U, - Mux(matrixC(0)(j) < (-128).S, (-128).S.asUInt, - matrixC(0)(j)(b.inputType.getWidth - 1, 0))) + writeDataReg := Cat((0 until InputNum).reverse.map { j => + val clamped = + Mux(matrixC(0)(j) > 127.S, 127.U, Mux(matrixC(0)(j) < -128.S, -128.S.asUInt, matrixC(0)(j)(inputWidth - 1, 0))) clamped - })) - for (i <- 0 until b.spad_mask_len) { + }) + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } } is(sWrite) { // Write results back to scratchpad - io.sramWrite(wr_bank_reg).req.valid := writeCounter < b.veclane.U - io.sramWrite(wr_bank_reg).req.bits.addr := wr_addr_reg + writeCounter - io.sramWrite(wr_bank_reg).req.bits.data := writeDataReg - io.sramWrite(wr_bank_reg).req.bits.mask := writeMaskReg + io.bankWrite(wr_bank_reg).req.valid := writeCounter < InputNum.U + io.bankWrite(wr_bank_reg).req.bits.addr := wr_addr_reg + writeCounter + io.bankWrite(wr_bank_reg).req.bits.data := writeDataReg + io.bankWrite(wr_bank_reg).req.bits.mask := writeMaskReg - when(io.sramWrite(wr_bank_reg).req.fire) { - when(writeCounter === (b.veclane - 1).U) { + when(io.bankWrite(wr_bank_reg).req.fire) { + when(writeCounter === (InputNum - 1).U) { state := complete }.otherwise { writeCounter := writeCounter + 1.U // Prepare next row's write data (clamp 32-bit result to 8-bit) val nextRow = writeCounter + 1.U - writeDataReg := Cat((0 until b.veclane).reverse.map(j => { - val idx = nextRow - val clamped = Mux(matrixC(idx)(j) > 127.S, 127.U, - Mux(matrixC(idx)(j) < (-128).S, (-128).S.asUInt, - matrixC(idx)(j)(b.inputType.getWidth - 1, 0))) + writeDataReg := Cat((0 until InputNum).reverse.map { j => + val idx = nextRow + val clamped = Mux( + matrixC(idx)(j) > 127.S, + 127.U, + Mux(matrixC(idx)(j) < -128.S, -128.S.asUInt, matrixC(idx)(j)(inputWidth - 1, 0)) + ) clamped - })) + }) } } } is(complete) { when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B + io.cmdResp.valid := true.B io.cmdResp.bits.rob_id := robid_reg when(io.cmdResp.fire) { iterCnt := iterCnt + 1.U @@ -293,18 +306,18 @@ class ABFTSystolicArray(implicit b: CustomBuckyballConfig, p: Parameters) extend } // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sLoadA) || (state === sLoadB) - io.status.running := (state === sCompute) || (state === sCheck) || (state === sWrite) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sLoadA) || (state === sLoadB) + io.status.running := (state === sCompute) || (state === sCheck) || (state === sWrite) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt // Reset handling when(reset.asBool) { - for (i <- 0 until b.veclane) { - for (j <- 0 until b.veclane) { + for (i <- 0 until InputNum) { + for (j <- 0 until InputNum) { matrixA(i)(j) := 0.S matrixB(i)(j) := 0.S matrixC(i)(j) := 0.S @@ -315,7 +328,7 @@ class ABFTSystolicArray(implicit b: CustomBuckyballConfig, p: Parameters) extend checksumC_col(i) := 0.S } writeDataReg := 0.U - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 0.U } errorDetected := false.B diff --git a/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala b/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala index 5ae4b703..d0e453b2 100644 --- a/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala +++ b/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala @@ -2,52 +2,50 @@ package prototype.abft import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.abft.ABFTSystolicArray +import prototype.abft.configs.ABFTConfig /** * ABFTSystolicArrayBall - A systolic array Ball with ABFT support * Behavior: Read matrices A and B from Scratchpad, compute C = A * B with ABFT checks, * then write back to Scratchpad. */ -class ABFTSystolicArrayBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class ABFTSystolicArrayBall(config: ABFTConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate ABFT systolic array computation unit - private val abftUnit = Module(new ABFTSystolicArray) + private val abftUnit: Instance[ABFTSystolicArray] = Instantiate(new ABFTSystolicArray(config)) // Connect command interface abftUnit.io.cmdReq <> io.cmdReq abftUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - abftUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - abftUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Connect Accumulator write interface - for (i <- 0 until b.acc_banks) { - abftUnit.io.accWrite(i) <> io.accWrite(i).io - io.accWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (not used, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + abftUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + + abftUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // ABFTSystolicArrayBall uses overwrite mode for scratchpad + + // Accumulator write (for partial sums) - use accumulate mode + abftUnit.io.bankWriteAcc(i) <> io.bankWrite(i).io + // Note: bankWriteAcc uses accumulate mode, but we connect to the same bankWrite interface + // The wmode should be set to true for accumulator writes } // Pass through status signals diff --git a/arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala b/arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala new file mode 100644 index 00000000..549b7c04 --- /dev/null +++ b/arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala @@ -0,0 +1,61 @@ +package prototype.abft.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object ABFTConfig { + implicit def rw: upickle.default.ReadWriter[ABFTConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): ABFTConfig = { + ABFTConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): ABFTConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[ABFTConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: ABFTConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class ABFTConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""ABFTConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/abft/configs/default.json b/arch/src/main/scala/prototype/abft/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/abft/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/conv/Conv.scala b/arch/src/main/scala/prototype/conv/Conv.scala index 7e275098..a412ceab 100644 --- a/arch/src/main/scala/prototype/conv/Conv.scala +++ b/arch/src/main/scala/prototype/conv/Conv.scala @@ -2,99 +2,105 @@ package prototype.conv import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status +import prototype.conv.configs.ConvConfig /** * NVDLAConvBlackBox - BlackBox wrapper for NVDLA CONV module * Uses inline verilog to embed NVDLA CSC module */ class NVDLAConvBlackBox extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) // Simplified CONV interface val start = Input(Bool()) - val done = Output(Bool()) + val done = Output(Bool()) // Input feature map address - val ifmap_addr = Input(UInt(32.W)) + val ifmap_addr = Input(UInt(32.W)) // Weight address val weight_addr = Input(UInt(32.W)) // Output feature map address - val ofmap_addr = Input(UInt(32.W)) + val ofmap_addr = Input(UInt(32.W)) // Convolution parameters - val in_height = Input(UInt(16.W)) - val in_width = Input(UInt(16.W)) - val in_channels = Input(UInt(16.W)) + val in_height = Input(UInt(16.W)) + val in_width = Input(UInt(16.W)) + val in_channels = Input(UInt(16.W)) val out_channels = Input(UInt(16.W)) - val kernel_h = Input(UInt(8.W)) - val kernel_w = Input(UInt(8.W)) - val stride_h = Input(UInt(8.W)) - val stride_w = Input(UInt(8.W)) - val pad_h = Input(UInt(8.W)) - val pad_w = Input(UInt(8.W)) + val kernel_h = Input(UInt(8.W)) + val kernel_w = Input(UInt(8.W)) + val stride_h = Input(UInt(8.W)) + val stride_w = Input(UInt(8.W)) + val pad_h = Input(UInt(8.W)) + val pad_w = Input(UInt(8.W)) // Data width val data_width = Input(UInt(8.W)) }) - setInline("NVDLAConvBlackBox.v", + setInline( + "NVDLAConvBlackBox.v", s""" - |module NVDLAConvBlackBox( - | input clock, - | input reset, - | input start, - | output reg done, - | input [31:0] ifmap_addr, - | input [31:0] weight_addr, - | input [31:0] ofmap_addr, - | input [15:0] in_height, - | input [15:0] in_width, - | input [15:0] in_channels, - | input [15:0] out_channels, - | input [7:0] kernel_h, - | input [7:0] kernel_w, - | input [7:0] stride_h, - | input [7:0] stride_w, - | input [7:0] pad_h, - | input [7:0] pad_w, - | input [7:0] data_width - |); - | - | reg [31:0] cycle_count; - | reg running; - | - | always @(posedge clock) begin - | if (reset) begin - | done <= 1'b0; - | cycle_count <= 32'b0; - | running <= 1'b0; - | end else begin - | if (start && !running) begin - | running <= 1'b1; - | cycle_count <= 32'b0; - | done <= 1'b0; - | end else if (running) begin - | // Simplified: compute cycles based on convolution size - | // This is a placeholder - actual NVDLA CSC would be instantiated here - | if (cycle_count >= (in_height * in_width * kernel_h * kernel_w * in_channels * out_channels / 64)) begin - | done <= 1'b1; - | running <= 1'b0; - | end else begin - | cycle_count <= cycle_count + 1; - | end - | end - | end - | end - | - |endmodule - """.stripMargin) + |module NVDLAConvBlackBox( + | input clock, + | input reset, + | input start, + | output reg done, + | input [31:0] ifmap_addr, + | input [31:0] weight_addr, + | input [31:0] ofmap_addr, + | input [15:0] in_height, + | input [15:0] in_width, + | input [15:0] in_channels, + | input [15:0] out_channels, + | input [7:0] kernel_h, + | input [7:0] kernel_w, + | input [7:0] stride_h, + | input [7:0] stride_w, + | input [7:0] pad_h, + | input [7:0] pad_w, + | input [7:0] data_width + |); + | + | reg [31:0] cycle_count; + | reg running; + | + | always @(posedge clock) begin + | if (reset) begin + | done <= 1'b0; + | cycle_count <= 32'b0; + | running <= 1'b0; + | end else begin + | if (start && !running) begin + | running <= 1'b1; + | cycle_count <= 32'b0; + | done <= 1'b0; + | end else if (running) begin + | // Simplified: compute cycles based on convolution size + | // This is a placeholder - actual NVDLA CSC would be instantiated here + | if (cycle_count >= (in_height * in_width * kernel_h * kernel_w * in_channels * out_channels / 64)) begin + | done <= 1'b1; + | running <= 1'b0; + | end else begin + | cycle_count <= cycle_count + 1; + | end + | end + | end + | end + | + |endmodule + """.stripMargin + ) } /** @@ -102,20 +108,29 @@ class NVDLAConvBlackBox extends BlackBox with HasBlackBoxInline { * Simplified wrapper around NVDLA CONV module * Reads input feature map and weights from scratchpad, performs convolution, writes output */ -class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +@instantiable +class Conv(val parameter: ConvConfig)(implicit p: Parameters) extends Module with SerializableModule[ConvConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val accWidth = 32 + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // Command interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) - // Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + // Unified bank read/write interface + val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + val bankWrite = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - // Accumulator write interface (for partial sums in convolution) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + // Accumulator write interface (unified bank now) + val bankWriteAcc = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, accWidth, ballParam.bankMaskLen))) // Status output val status = new Status @@ -123,17 +138,17 @@ class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // State machine val idle :: sLoadIfmap :: sLoadWeight :: sCompute :: sWrite :: complete :: Nil = Enum(6) - val state = RegInit(idle) + val state = RegInit(idle) // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val ifmap_addr_reg = RegInit(0.U(10.W)) - val ifmap_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val robid_reg = RegInit(0.U(10.W)) + val ifmap_addr_reg = RegInit(0.U(10.W)) + val ifmap_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) val weight_addr_reg = RegInit(0.U(10.W)) - val weight_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val ofmap_addr_reg = RegInit(0.U(10.W)) - val ofmap_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val weight_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val ofmap_addr_reg = RegInit(0.U(10.W)) + val ofmap_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) // Convolution parameters from special field (40 bits total) // special[15:0] = in_height (16 bits) @@ -142,13 +157,13 @@ class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // Note: kernel_w is encoded in lower 8 bits of kernel_h, or use a different encoding // For simplicity, we'll use kernel_h for both dimensions or extract from iter val in_height_reg = RegInit(0.U(16.W)) - val in_width_reg = RegInit(0.U(16.W)) - val kernel_h_reg = RegInit(0.U(8.W)) - val kernel_w_reg = RegInit(0.U(8.W)) + val in_width_reg = RegInit(0.U(16.W)) + val kernel_h_reg = RegInit(0.U(8.W)) + val kernel_w_reg = RegInit(0.U(8.W)) // Counters - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) val computeCounter = RegInit(0.U(32.W)) // NVDLA CONV BlackBox instance @@ -157,97 +172,97 @@ class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { nvdlaConv.io.reset := reset.asBool // Default SRAM assignments - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := false.B + + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // Default accumulator assignments - for (i <- 0 until b.acc_banks) { - io.accWrite(i).req.valid := false.B - io.accWrite(i).req.bits.addr := 0.U - io.accWrite(i).req.bits.data := 0.U - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankWriteAcc(i).req.valid := false.B + io.bankWriteAcc(i).req.bits.addr := 0.U + io.bankWriteAcc(i).req.bits.data := 0.U + io.bankWriteAcc(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // Command interface defaults - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // NVDLA CONV interface defaults - nvdlaConv.io.start := false.B - nvdlaConv.io.ifmap_addr := ifmap_addr_reg - nvdlaConv.io.weight_addr := weight_addr_reg - nvdlaConv.io.ofmap_addr := ofmap_addr_reg - nvdlaConv.io.in_height := in_height_reg - nvdlaConv.io.in_width := in_width_reg - nvdlaConv.io.in_channels := 16.U // Default - nvdlaConv.io.out_channels := 16.U // Default - nvdlaConv.io.kernel_h := kernel_h_reg - nvdlaConv.io.kernel_w := kernel_w_reg - nvdlaConv.io.stride_h := 1.U - nvdlaConv.io.stride_w := 1.U - nvdlaConv.io.pad_h := 0.U - nvdlaConv.io.pad_w := 0.U - nvdlaConv.io.data_width := b.inputType.getWidth.U + nvdlaConv.io.start := false.B + nvdlaConv.io.ifmap_addr := ifmap_addr_reg + nvdlaConv.io.weight_addr := weight_addr_reg + nvdlaConv.io.ofmap_addr := ofmap_addr_reg + nvdlaConv.io.in_height := in_height_reg + nvdlaConv.io.in_width := in_width_reg + nvdlaConv.io.in_channels := 16.U // Default + nvdlaConv.io.out_channels := 16.U // Default + nvdlaConv.io.kernel_h := kernel_h_reg + nvdlaConv.io.kernel_w := kernel_w_reg + nvdlaConv.io.stride_h := 1.U + nvdlaConv.io.stride_w := 1.U + nvdlaConv.io.pad_h := 0.U + nvdlaConv.io.pad_w := 0.U + nvdlaConv.io.data_width := inputWidth.U // Status output - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sLoadIfmap) || (state === sLoadWeight) - io.status.running := (state === sCompute) || (state === sWrite) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sLoadIfmap) || (state === sLoadWeight) + io.status.running := (state === sCompute) || (state === sWrite) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := computeCounter + io.status.iter := computeCounter // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sLoadIfmap - readCounter := 0.U - writeCounter := 0.U + state := sLoadIfmap + readCounter := 0.U + writeCounter := 0.U computeCounter := 0.U - robid_reg := io.cmdReq.bits.rob_id - ifmap_addr_reg := io.cmdReq.bits.cmd.op1_bank_addr - ifmap_bank_reg := io.cmdReq.bits.cmd.op1_bank - weight_addr_reg := io.cmdReq.bits.cmd.op2_bank_addr + robid_reg := io.cmdReq.bits.rob_id + ifmap_addr_reg := 0.U // New ISA: all operations start from row 0 + ifmap_bank_reg := io.cmdReq.bits.cmd.op1_bank + weight_addr_reg := 0.U // New ISA: all operations start from row 0 weight_bank_reg := io.cmdReq.bits.cmd.op2_bank - ofmap_addr_reg := io.cmdReq.bits.cmd.wr_bank_addr - ofmap_bank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter + ofmap_addr_reg := 0.U // New ISA: all operations start from row 0 + ofmap_bank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter // Extract convolution parameters from special field (40 bits) in_height_reg := io.cmdReq.bits.cmd.special(15, 0) - in_width_reg := io.cmdReq.bits.cmd.special(31, 16) - kernel_h_reg := io.cmdReq.bits.cmd.special(39, 32) + in_width_reg := io.cmdReq.bits.cmd.special(31, 16) + kernel_h_reg := io.cmdReq.bits.cmd.special(39, 32) // kernel_w uses same value as kernel_h for simplicity, or could be encoded differently - kernel_w_reg := io.cmdReq.bits.cmd.special(39, 32) + kernel_w_reg := io.cmdReq.bits.cmd.special(39, 32) } } is(sLoadIfmap) { // Load input feature map (simplified: load one tile) when(readCounter < iter_reg) { - io.sramRead(ifmap_bank_reg).req.valid := true.B - io.sramRead(ifmap_bank_reg).req.bits.addr := ifmap_addr_reg + readCounter - io.sramRead(ifmap_bank_reg).req.bits.fromDMA := false.B + io.bankRead(ifmap_bank_reg).req.valid := true.B + io.bankRead(ifmap_bank_reg).req.bits.addr := ifmap_addr_reg + readCounter + io.bankRead(ifmap_bank_reg).req.bits.fromDMA := false.B - when(io.sramRead(ifmap_bank_reg).resp.valid) { - io.sramRead(ifmap_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U + when(io.bankRead(ifmap_bank_reg).resp.valid) { + io.bankRead(ifmap_bank_reg).resp.ready := true.B + readCounter := readCounter + 1.U } }.otherwise { - state := sLoadWeight + state := sLoadWeight readCounter := 0.U } } @@ -255,17 +270,17 @@ class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sLoadWeight) { // Load weights (simplified: load one tile) when(readCounter < iter_reg) { - io.sramRead(weight_bank_reg).req.valid := true.B - io.sramRead(weight_bank_reg).req.bits.addr := weight_addr_reg + readCounter - io.sramRead(weight_bank_reg).req.bits.fromDMA := false.B + io.bankRead(weight_bank_reg).req.valid := true.B + io.bankRead(weight_bank_reg).req.bits.addr := weight_addr_reg + readCounter + io.bankRead(weight_bank_reg).req.bits.fromDMA := false.B - when(io.sramRead(weight_bank_reg).resp.valid) { - io.sramRead(weight_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U + when(io.bankRead(weight_bank_reg).resp.valid) { + io.bankRead(weight_bank_reg).resp.ready := true.B + readCounter := readCounter + 1.U } }.otherwise { - state := sCompute - readCounter := 0.U + state := sCompute + readCounter := 0.U nvdlaConv.io.start := true.B } } @@ -273,7 +288,7 @@ class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sCompute) { // Wait for NVDLA CONV to complete when(nvdlaConv.io.done) { - state := sWrite + state := sWrite writeCounter := 0.U }.otherwise { computeCounter := computeCounter + 1.U @@ -283,13 +298,13 @@ class Conv(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sWrite) { // Write output feature map (simplified: write one tile) when(writeCounter < iter_reg) { - io.sramWrite(ofmap_bank_reg).req.valid := true.B - io.sramWrite(ofmap_bank_reg).req.bits.addr := ofmap_addr_reg + writeCounter + io.bankWrite(ofmap_bank_reg).req.valid := true.B + io.bankWrite(ofmap_bank_reg).req.bits.addr := ofmap_addr_reg + writeCounter // Simplified: write zeros as placeholder (actual output would come from NVDLA CONV) - io.sramWrite(ofmap_bank_reg).req.bits.data := 0.U - io.sramWrite(ofmap_bank_reg).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(1.U(1.W))) + io.bankWrite(ofmap_bank_reg).req.bits.data := 0.U + io.bankWrite(ofmap_bank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(1.U(1.W))) - when(io.sramWrite(ofmap_bank_reg).req.ready) { + when(io.bankWrite(ofmap_bank_reg).req.ready) { writeCounter := writeCounter + 1.U } }.otherwise { diff --git a/arch/src/main/scala/prototype/conv/ConvBall.scala b/arch/src/main/scala/prototype/conv/ConvBall.scala index f96ec594..8d7d0af4 100644 --- a/arch/src/main/scala/prototype/conv/ConvBall.scala +++ b/arch/src/main/scala/prototype/conv/ConvBall.scala @@ -2,52 +2,50 @@ package prototype.conv import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.conv.Conv +import prototype.conv.configs.ConvConfig /** * ConvBall - A Convolution computation Ball that complies with the Blink protocol * Behavior: Read input feature map and weights from Scratchpad, perform convolution using NVDLA CONV, * then write output feature map back to Scratchpad. */ -class ConvBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class ConvBall(config: ConvConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate Conv computation unit - private val convUnit = Module(new Conv) + private val convUnit: Instance[Conv] = Instantiate(new Conv(config)) // Connect command interface convUnit.io.cmdReq <> io.cmdReq convUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - convUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - convUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Connect Accumulator write interface (for partial sums in convolution) - for (i <- 0 until b.acc_banks) { - convUnit.io.accWrite(i) <> io.accWrite(i).io - io.accWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (not used, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + convUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + + convUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // ConvBall uses overwrite mode for scratchpad + + // Accumulator write (for partial sums) - use accumulate mode + // Note: ConvBall may need to write to accumulator banks with accumulate mode + // For now, assuming all writes use overwrite mode, but accumulator writes should use accumulate + // This needs to be determined based on Conv unit's actual behavior } // Pass through status signals diff --git a/arch/src/main/scala/prototype/conv/configs/ConvConfig.scala b/arch/src/main/scala/prototype/conv/configs/ConvConfig.scala new file mode 100644 index 00000000..4eb7dd1a --- /dev/null +++ b/arch/src/main/scala/prototype/conv/configs/ConvConfig.scala @@ -0,0 +1,61 @@ +package prototype.conv.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object ConvConfig { + implicit def rw: upickle.default.ReadWriter[ConvConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): ConvConfig = { + ConvConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): ConvConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[ConvConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: ConvConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class ConvConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""ConvConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/conv/configs/default.json b/arch/src/main/scala/prototype/conv/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/conv/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/format/Arithmetic.scala b/arch/src/main/scala/prototype/format/Arithmetic.scala index e2f1f0b4..d4484dc2 100644 --- a/arch/src/main/scala/prototype/format/Arithmetic.scala +++ b/arch/src/main/scala/prototype/format/Arithmetic.scala @@ -9,7 +9,7 @@ abstract class Arithmetic[T <: Data] { def sub(x: T, y: T): T def mul(x: T, y: T): T def div(x: T, y: T): T - def gt(x: T, y: T): Bool + def gt(x: T, y: T): Bool } // UInt arithmetic implementation @@ -18,15 +18,17 @@ class UIntArithmetic extends Arithmetic[UInt] { override def sub(x: UInt, y: UInt): UInt = x - y override def mul(x: UInt, y: UInt): UInt = x * y override def div(x: UInt, y: UInt): UInt = Mux(y =/= 0.U, x / y, 0.U) - override def gt(x: UInt, y: UInt): Bool = x > y + override def gt(x: UInt, y: UInt): Bool = x > y } // Factory object ArithmeticFactory { + def createArithmetic[T <: Data](dataType: T): Arithmetic[T] = { dataType match { case _: UInt => new UIntArithmetic().asInstanceOf[Arithmetic[T]] case _ => throw new IllegalArgumentException(s"Unsupported data type: ${dataType.getClass}") } } + } diff --git a/arch/src/main/scala/prototype/format/Dataformat.scala b/arch/src/main/scala/prototype/format/Dataformat.scala index 5bdac4df..5d423f66 100644 --- a/arch/src/main/scala/prototype/format/Dataformat.scala +++ b/arch/src/main/scala/prototype/format/Dataformat.scala @@ -5,50 +5,50 @@ import chisel3.util._ // Data format definition abstract class DataFormat { - def width: Int + def width: Int def dataType: Data - def name: String + def name: String } // INT8 format class INT8Format extends DataFormat { - override def width: Int = 8 - override def dataType: Data = UInt(8.W) - override def name: String = "INT8" + override def width: Int = 8 + override def dataType: Data = UInt(8.W) + override def name: String = "INT8" } // FP16 format class FP16Format extends DataFormat { - override def width: Int = 16 + override def width: Int = 16 // Temporarily use UInt representation, can be extended to Float type later - override def dataType: Data = UInt(16.W) - override def name: String = "FP16" + override def dataType: Data = UInt(16.W) + override def name: String = "FP16" } // FP32 format class FP32Format extends DataFormat { - override def width: Int = 32 + override def width: Int = 32 // Temporarily use UInt representation, can be extended to Float type later - override def dataType: Data = UInt(32.W) - override def name: String = "FP32" + override def dataType: Data = UInt(32.W) + override def name: String = "FP32" } - // Data format factory object DataFormatFactory { + def create(formatType: String): DataFormat = formatType.toUpperCase match { case "INT8" => new INT8Format case "FP16" => new FP16Format case "FP32" => new FP32Format - case _ => throw new IllegalArgumentException(s"Unsupported data format: $formatType") + case _ => throw new IllegalArgumentException(s"Unsupported data format: $formatType") } + } // Generic data format parameters case class DataFormatParams( - formatType: String = "INT8" -) { - def format: DataFormat = DataFormatFactory.create(formatType) - def width: Int = format.width - def dataType: Data = format.dataType + formatType: String = "INT8") { + def format: DataFormat = DataFormatFactory.create(formatType) + def width: Int = format.width + def dataType: Data = format.dataType } diff --git a/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala b/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala index 534cd84c..faa23f02 100644 --- a/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala +++ b/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala @@ -2,24 +2,33 @@ package prototype.ibuki.matmul import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status +@instantiable +class LIF(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val bankWidth = parameter.bankWidth -class LIF(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - + @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val cmdResp = Decoupled(new BallRsComplete(parameter)) // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + val sramRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) + val sramWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) // Status output val status = new Status @@ -27,106 +36,106 @@ class LIF(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // State definitions val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) + val state = RegInit(idle) - // Store a veclane x veclane tile + // Store a InputNum x InputNum tile val regArray = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) )) ) // Counters - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) // Instruction registers val robid_reg = RegInit(0.U(10.W)) val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val wbank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) val cycle_reg = RegInit(0.U(6.W)) - val iterCnt = RegInit(0.U(32.W)) + val iterCnt = RegInit(0.U(32.W)) // LIF parameters from special field // special[7:0] = threshold (8 bits) // special[15:8] = leak_factor (8 bits, represents leak rate) - val threshold_reg = RegInit(127.U(8.W)) // Default threshold - val leak_factor_reg = RegInit(240.U(8.W)) // Default leak factor (240/256 ≈ 0.9375) + val threshold_reg = RegInit(127.U(8.W)) // Default threshold + val leak_factor_reg = RegInit(240.U(8.W)) // Default leak factor (240/256 ≈ 0.9375) // Precompute write data - val writeDataReg = Reg(UInt(spad_w.W)) - val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(parameter.bankMaskLen, UInt(1.W))) // SRAM default assignment - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U + for (i <- 0 until parameter.numBanks) { + io.sramRead(i).req.valid := false.B + io.sramRead(i).req.bits.addr := 0.U io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B + io.sramRead(i).resp.ready := false.B - io.sramWrite(i).req.valid := false.B + io.sramWrite(i).req.valid := false.B io.sramWrite(i).req.bits.addr := 0.U io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U + state := sRead + readCounter := 0.U + respCounter := 0.U writeCounter := 0.U robid_reg := io.cmdReq.bits.rob_id - waddr_reg := io.cmdReq.bits.cmd.wr_bank_addr + waddr_reg := 0.U // New ISA: all operations start from row 0 wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr + raddr_reg := 0.U // New ISA: all operations start from row 0 rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (b.veclane.U - 1.U)) / b.veclane.U - 1.U + iter_reg := io.cmdReq.bits.cmd.iter + cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U // Extract LIF parameters from special field - threshold_reg := io.cmdReq.bits.cmd.special(7, 0) + threshold_reg := io.cmdReq.bits.cmd.special(7, 0) leak_factor_reg := io.cmdReq.bits.cmd.special(15, 8) } when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U + state := sRead + readCounter := 0.U writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + b.veclane.U - raddr_reg := raddr_reg + b.veclane.U - cycle_reg := cycle_reg - 1.U + respCounter := 0.U + waddr_reg := waddr_reg + InputNum.U + raddr_reg := raddr_reg + InputNum.U + cycle_reg := cycle_reg - 1.U } } is(sRead) { - when(readCounter < b.veclane.U) { + when(readCounter < InputNum.U) { // Issue read request - readCounter := readCounter + 1.U - io.sramRead(rbank_reg).req.valid := true.B + readCounter := readCounter + 1.U + io.sramRead(rbank_reg).req.valid := true.B io.sramRead(rbank_reg).req.bits.addr := raddr_reg + readCounter } // Receive response and perform LIF neuron computation io.sramRead(rbank_reg).resp.ready := true.B when(io.sramRead(rbank_reg).resp.fire) { - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth - val raw = io.sramRead(rbank_reg).resp.bits.data(hi, lo) + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + val raw = io.sramRead(rbank_reg).resp.bits.data(hi, lo) val signed = raw.asSInt // LIF neuron model: @@ -138,27 +147,27 @@ class LIF(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // leak_factor is unsigned (0-255), representing leak rate // Convert to signed for multiplication, then shift right by 8 val leak_factor_signed = leak_factor_reg.zext.asSInt - val leaked = (signed * leak_factor_signed) >> 8 + val leaked = (signed * leak_factor_signed) >> 8 // Fire condition: if leaked >= threshold, output spike (threshold), else output leaked // For simplicity, we output the threshold value as spike, or the leaked value - val result = Mux(leaked >= threshold_reg.asSInt, - threshold_reg.asSInt, - Mux(leaked < (-threshold_reg).asSInt, - (-threshold_reg).asSInt, - leaked)) + val result = Mux( + leaked >= threshold_reg.asSInt, + threshold_reg.asSInt, + Mux(leaked < (-threshold_reg).asSInt, (-threshold_reg).asSInt, leaked) + ) regArray(respCounter)(col) := result.asUInt } respCounter := respCounter + 1.U } - when(respCounter === b.veclane.U) { - state := sWrite + when(respCounter === InputNum.U) { + state := sWrite // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(0)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) // Set write mask (write all) - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } } @@ -166,23 +175,23 @@ class LIF(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sWrite) { // Write back results - io.sramWrite(wbank_reg).req.valid := writeCounter < b.veclane.U + io.sramWrite(wbank_reg).req.valid := writeCounter < InputNum.U io.sramWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter io.sramWrite(wbank_reg).req.bits.data := writeDataReg io.sramWrite(wbank_reg).req.bits.mask := writeMaskReg - when(writeCounter === (b.veclane - 1).U) { + when(writeCounter === (InputNum - 1).U) { state := complete }.otherwise { writeCounter := writeCounter + 1.U // Prepare next row's write data - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(writeCounter + 1.U)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) } } is(complete) { when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B + io.cmdResp.valid := true.B io.cmdResp.bits.rob_id := robid_reg when(io.cmdResp.fire) { iterCnt := iterCnt + 1.U @@ -193,22 +202,22 @@ class LIF(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { } // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < b.veclane.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === b.veclane.U)) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sRead) && (respCounter < InputNum.U) + io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt when(reset.asBool) { - for (i <- 0 until b.veclane) { - for (j <- 0 until b.veclane) { + for (i <- 0 until InputNum) { + for (j <- 0 until InputNum) { regArray(i)(j) := 0.U } } writeDataReg := 0.U - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 0.U } } diff --git a/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala b/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala index f58c67b8..d3952deb 100644 --- a/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala +++ b/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala @@ -2,49 +2,38 @@ package prototype.ibuki.matmul import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.ibuki.matmul.LIF - -class LIFMatmulBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) +@instantiable +class LIFMatmulBall(parameter: BallDomainParam, id: Int)(implicit p: Parameters) extends Module with BallRegist { + @public + val io = IO(new Blink(parameter, parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate LIF computation unit - private val lifUnit = Module(new LIF) + private val lifUnit: Instance[LIF] = Instantiate(new LIF(parameter)) // Connect command interface lifUnit.io.cmdReq <> io.cmdReq lifUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - lifUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - lifUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (LIF does not access accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + lifUnit.io.sramRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U - // Accumulator write interface (LIF does not write accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + lifUnit.io.sramWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // LIFMatmulBall uses overwrite mode } // Pass through status signals diff --git a/arch/src/main/scala/prototype/im2col/Im2colBall.scala b/arch/src/main/scala/prototype/im2col/Im2colBall.scala index 7fe70b5f..095db500 100644 --- a/arch/src/main/scala/prototype/im2col/Im2colBall.scala +++ b/arch/src/main/scala/prototype/im2col/Im2colBall.scala @@ -2,54 +2,42 @@ package prototype.im2col import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.im2col.Im2col +import prototype.im2col.configs.Im2colConfig /** * Im2colBall - An Im2col computation Ball that complies with the Blink protocol */ -class Im2colBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class Im2colBall(config: Im2colConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U def Blink: Blink = io // Instantiate Im2col - val im2colUnit = Module(new Im2col) + val im2colUnit: Instance[Im2col] = Instantiate(new Im2col(config)) // Connect command interface im2colUnit.io.cmdReq <> io.cmdReq im2colUnit.io.cmdResp <> io.cmdResp - // Connect SRAM read interface - Im2col needs to read data from scratchpad - for (i <- 0 until b.sp_banks) { - im2colUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - } - - // Connect SRAM write interface - Im2col needs to write to scratchpad - for (i <- 0 until b.sp_banks) { - im2colUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Handle Accumulator read interface - Im2col does not read accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramReadIO), we need to drive req.valid, req.bits (outputs) and resp.ready (output) - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } + // Connect Bank interface + for (i <- 0 until parameter.numBanks) { + im2colUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U - // Handle Accumulator write interface - Im2col does not write accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramWriteIO), we need to drive req.valid and req.bits (outputs) - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + im2colUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // Im2colBall uses overwrite mode } // Connect Status signals - directly obtained from internal unit diff --git a/arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala b/arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala new file mode 100644 index 00000000..cde87f2d --- /dev/null +++ b/arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala @@ -0,0 +1,62 @@ +package prototype.im2col.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object Im2colConfig { + implicit def rw: upickle.default.ReadWriter[Im2colConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): Im2colConfig = { + Im2colConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): Im2colConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[Im2colConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: Im2colConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class Im2colConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + // Derived parameters + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""Im2colConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/im2col/configs/default.json b/arch/src/main/scala/prototype/im2col/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/im2col/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/im2col/im2col.scala b/arch/src/main/scala/prototype/im2col/im2col.scala index 9e578b0d..188e73c4 100644 --- a/arch/src/main/scala/prototype/im2col/im2col.scala +++ b/arch/src/main/scala/prototype/im2col/im2col.scala @@ -3,27 +3,35 @@ package prototype.im2col import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status -import firrtl2.passes.CheckTypes.st +import prototype.im2col.configs.Im2colConfig +@instantiable +class Im2col(val parameter: Im2colConfig)(implicit p: Parameters) extends Module with SerializableModule[Im2colConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val bankWidth = parameter.bankWidth -class Im2col(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - + @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) - // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + // Connect to unified bank read/write interface + val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + val bankWrite = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) // Status output val status = new Status @@ -32,57 +40,56 @@ class Im2col(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // State definitions val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) // Current state register - val state = RegInit(idle) + val state = RegInit(idle) // Conversion buffer - val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W)))))) + val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(InputNum)(0.U(inputWidth.W)))))) // Row pointer marking top-left corner of convolution window - val rowptr = RegInit(0.U(10.W)) + val rowptr = RegInit(0.U(10.W)) // Column pointer marking top-left corner of convolution window - val colptr = RegInit(0.U(5.W)) + val colptr = RegInit(0.U(5.W)) // Request counter in read state - val reqcounter = RegInit(0.U(5.W)) + val reqcounter = RegInit(0.U(5.W)) // Response counter in read state - val respcounter = RegInit(0.U(5.W)) + val respcounter = RegInit(0.U(5.W)) // Store current instruction's RoB ID - val robid_reg = RegInit(0.U(10.W)) + val robid_reg = RegInit(0.U(10.W)) // Store kernel row count - val krow_reg = RegInit(0.U(log2Up(b.veclane).W)) + val krow_reg = RegInit(0.U(log2Up(InputNum).W)) // Store kernel column count - val kcol_reg = RegInit(0.U(log2Up(b.veclane).W)) + val kcol_reg = RegInit(0.U(log2Up(InputNum).W)) // Store input matrix row count - val inrow_reg = RegInit(0.U(10.W)) + val inrow_reg = RegInit(0.U(10.W)) // Store input matrix column count - val incol_reg = RegInit(0.U((log2Up(b.veclane) + 1).W)) + val incol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) // Store starting column number - val startcol_reg = RegInit(0.U((log2Up(b.veclane) + 1).W)) + val startcol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) // Store starting row number - val startrow_reg = RegInit(0.U(10.W)) + val startrow_reg = RegInit(0.U(10.W)) // Store write starting address - val waddr_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(10.W)) // Store write bank - val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) // Store read starting address - val raddr_reg = RegInit(0.U(10.W)) + val raddr_reg = RegInit(0.U(10.W)) // Store read bank - val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) - + val iterCnt = RegInit(0.U(32.W)) // SRAM default assignment - for(i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := (state === read) || (state === read_and_convert) - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := (state === read) || (state === read_and_convert) + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment io.cmdReq.ready := true.B - io.cmdResp.valid := false.B + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := 0.U val rowcnt = rowptr - startrow_reg @@ -95,28 +102,28 @@ class Im2col(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(idle) { // Instruction arrives, initialize registers when(io.cmdReq.fire) { - state := read - rowptr := io.cmdReq.bits.cmd.special(37,28) - colptr := io.cmdReq.bits.cmd.special(27,23) - reqcounter := 0.U - respcounter:= 0.U + state := read + rowptr := io.cmdReq.bits.cmd.special(37, 28) + colptr := io.cmdReq.bits.cmd.special(27, 23) + reqcounter := 0.U + respcounter := 0.U // Kernel column count - kcol_reg := io.cmdReq.bits.cmd.special(3,0) + kcol_reg := io.cmdReq.bits.cmd.special(3, 0) // Kernel row count - krow_reg := io.cmdReq.bits.cmd.special(7,4) + krow_reg := io.cmdReq.bits.cmd.special(7, 4) // Input matrix column count - incol_reg := io.cmdReq.bits.cmd.special(12,8) + incol_reg := io.cmdReq.bits.cmd.special(12, 8) // Input matrix row count - inrow_reg := io.cmdReq.bits.cmd.special(22,13) + inrow_reg := io.cmdReq.bits.cmd.special(22, 13) // Starting column number - startcol_reg := io.cmdReq.bits.cmd.special(27,23) + startcol_reg := io.cmdReq.bits.cmd.special(27, 23) // Starting row number - startrow_reg := io.cmdReq.bits.cmd.special(37,28) - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := io.cmdReq.bits.cmd.op2_bank_addr - wbank_reg := io.cmdReq.bits.cmd.op2_bank - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr - rbank_reg := io.cmdReq.bits.cmd.op1_bank + startrow_reg := io.cmdReq.bits.cmd.special(37, 28) + robid_reg := io.cmdReq.bits.rob_id + waddr_reg := 0.U // New ISA: all operations start from row 0 + wbank_reg := io.cmdReq.bits.cmd.op2_bank + raddr_reg := 0.U // New ISA: all operations start from row 0 + rbank_reg := io.cmdReq.bits.cmd.op1_bank } } // Read part of data, fill ConvertBuffer @@ -124,13 +131,13 @@ class Im2col(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // Send read request when(reqcounter < krow_reg) { reqcounter := reqcounter + 1.U - io.sramRead(rbank_reg).req.valid := true.B - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + reqcounter + startrow_reg + io.bankRead(rbank_reg).req.valid := true.B + io.bankRead(rbank_reg).req.bits.addr := raddr_reg + reqcounter + startrow_reg } // Process read response and store in ConvertBuffer - when(io.sramRead(rbank_reg).resp.fire) { - ConvertBuffer(respcounter) := io.sramRead(rbank_reg).resp.bits.data.asTypeOf(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - respcounter := respcounter + 1.U + when(io.bankRead(rbank_reg).resp.fire) { + ConvertBuffer(respcounter) := io.bankRead(rbank_reg).resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + respcounter := respcounter + 1.U } // Determine whether to transition state state := Mux(respcounter === krow_reg, read_and_convert, read) @@ -140,20 +147,23 @@ class Im2col(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(read_and_convert) { // Move pointer when(colptr <= colmax && rowptr <= rowmax) { - colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) - io.sramWrite(wbank_reg).req.valid := true.B - io.sramWrite(wbank_reg).req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt - io.sramWrite(wbank_reg).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(~0.U(1.W))) - io.sramWrite(wbank_reg).req.bits.data := { + colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) + io.bankWrite(wbank_reg).req.valid := true.B + io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt + io.bankWrite(wbank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(~0.U(1.W))) + io.bankWrite(wbank_reg).req.bits.data := { - val window = Wire(Vec(b.veclane, UInt(b.inputType.getWidth.W))) + val window = Wire(Vec(InputNum, UInt(inputWidth.W))) // Initialize all to 0 first - for (i <- 0 until b.veclane) { - window(i) := 0.U + for (i <- 0 until InputNum) { + window(i) := 0.U } // Fill window data - for (i <- 0 until 4; j <- 0 until 4) { + for { + i <- 0 until 4 + j <- 0 until 4 + } { when(i.U < krow_reg && j.U < kcol_reg) { val bufferRow = (rowcnt + i.U) % krow_reg val bufferCol = (colptr + j.U) % incol_reg @@ -165,39 +175,42 @@ class Im2col(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // Rearrange data // For example, for klen_reg=3, combine (00)(01)(02)(10)(11)(12)(20)(21)(22) - Cat((0 until b.veclane).map(i => window(i)).reverse) + Cat((0 until InputNum).map(i => window(i)).reverse) } } // Send read request early - when(colptr === colmax - 1.U){ - io.sramRead(rbank_reg).req.valid := true.B - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + krow_reg + rowptr + when(colptr === colmax - 1.U) { + io.bankRead(rbank_reg).req.valid := true.B + io.bankRead(rbank_reg).req.bits.addr := raddr_reg + krow_reg + rowptr } // Process read response and store in ConvertBuffer - when(io.sramRead(rbank_reg).resp.fire){ - ConvertBuffer(rowcnt % krow_reg) := io.sramRead(rbank_reg).resp.bits.data.asTypeOf(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - rowptr := rowptr + 1.U + when(io.bankRead(rbank_reg).resp.fire) { + ConvertBuffer(rowcnt % krow_reg) := io.bankRead(rbank_reg).resp.bits.data.asTypeOf(Vec( + InputNum, + UInt(inputWidth.W) + )) + rowptr := rowptr + 1.U } // Determine whether to transition state state := Mux(rowptr === rowmax && colptr === colmax, complete, read_and_convert) } // Complete state, send completion signal is(complete) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg - state := idle - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := robid_reg + state := idle + when(io.cmdResp.fire) { + iterCnt := iterCnt + 1.U + } } } // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === read) - io.status.running := (state === read_and_convert) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === read) + io.status.running := (state === read_and_convert) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt } diff --git a/arch/src/main/scala/prototype/matrix/MatrixBall.scala b/arch/src/main/scala/prototype/matrix/MatrixBall.scala index d920fbf6..99d389a4 100644 --- a/arch/src/main/scala/prototype/matrix/MatrixBall.scala +++ b/arch/src/main/scala/prototype/matrix/MatrixBall.scala @@ -2,55 +2,45 @@ package prototype.matrix import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.matrix.BBFP_Control +import prototype.matrix.configs.MatrixConfig /** * MatrixBall - A matrix computation Ball that complies with the Blink protocol */ -class MatrixBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class MatrixBall(config: MatrixConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U def Blink: Blink = io // Instantiate BBFP_Control - val matrixUnit = Module(new BBFP_Control) + val matrixUnit: Instance[BBFP_Control] = Instantiate(new BBFP_Control(parameter)) // Connect command interface matrixUnit.io.cmdReq <> io.cmdReq matrixUnit.io.cmdResp <> io.cmdResp // Set is_matmul_ws signal - matrixUnit.io.is_matmul_ws := false.B // TODO: - - // Connect SRAM read interface - MatrixBall needs to read data from scratchpad - for (i <- 0 until b.sp_banks) { - matrixUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - } - - // Connect SRAM write interface - MatrixBall needs to write to scratchpad - for (i <- 0 until b.sp_banks) { - matrixUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Handle Accumulator read interface - MatrixBall does not read accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramReadIO), we need to drive req.valid, req.bits (outputs) and resp.ready (output) - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } - - // Connect Accumulator write interface - MatrixBall writes results to accumulator - for (i <- 0 until b.acc_banks) { - matrixUnit.io.accWrite(i) <> io.accWrite(i).io - io.accWrite(i).rob_id := io.cmdReq.bits.rob_id + matrixUnit.io.is_matmul_ws := false.B // TODO: + + // Connect Bank interface + for (i <- 0 until parameter.numBanks) { + matrixUnit.io.sramRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + + matrixUnit.io.sramWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // MatrixBall uses overwrite mode } // Connect Status signals - directly obtained from internal unit diff --git a/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala b/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala index 014d6542..460391b9 100644 --- a/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala +++ b/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala @@ -3,36 +3,44 @@ package prototype.matrix import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.matrix._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam -class BBFP_ID(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val rob_id_width = log2Up(b.rob_entries) - val spad_w = b.veclane * b.inputType.getWidth +@instantiable +class BBFP_ID(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val rob_id_width = log2Up(parameter.rob_entries) + val bankWidth = parameter.bankWidth - val io = IO(new Bundle{ - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val is_matmul_ws = Output(Bool()) - val id_lu_o = Decoupled(new id_lu_req) + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val is_matmul_ws = Output(Bool()) + val id_lu_o = Decoupled(new id_lu_req(parameter)) }) val idle :: busy :: Nil = Enum(2) // Register definitions - val state = RegInit(idle) - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val iteration_counter = RegInit(0.U(10.W)) - val iteration = RegInit(0.U(10.W)) - val op1_bank = RegInit(0.U(2.W)) - val op1_bank_addr = RegInit(0.U(12.W)) - val op2_bank_addr = RegInit(0.U(12.W)) - val op2_bank = RegInit(0.U(2.W)) - val wr_bank = RegInit(0.U(2.W)) - val wr_bank_addr = RegInit(0.U(12.W)) - val is_matmul_ws = RegInit(false.B) + val state = RegInit(idle) + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val iteration_counter = RegInit(0.U(10.W)) + val iteration = RegInit(0.U(10.W)) + val op1_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val op2_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val wr_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val wr_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val is_matmul_ws = RegInit(false.B) io.is_matmul_ws := false.B switch(state) { @@ -43,25 +51,25 @@ class BBFP_ID(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is_matmul_ws := false.B rob_id_reg := io.cmdReq.bits.rob_id op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := io.cmdReq.bits.cmd.op1_bank_addr + op1_bank_addr := 0.U // New ISA: all operations start from row 0 op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := io.cmdReq.bits.cmd.op2_bank_addr + op2_bank_addr := 0.U // New ISA: all operations start from row 0 wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := io.cmdReq.bits.cmd.wr_bank_addr + wr_bank_addr := 0.U // New ISA: all operations start from row 0 state := busy io.is_matmul_ws := false.B } - when(io.cmdReq.valid && io.cmdReq.bits.cmd.special(0)){ + when(io.cmdReq.valid && io.cmdReq.bits.cmd.special(0)) { iteration := io.cmdReq.bits.cmd.iter iteration_counter := 0.U is_matmul_ws := true.B rob_id_reg := io.cmdReq.bits.rob_id op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := io.cmdReq.bits.cmd.op1_bank_addr + op1_bank_addr := 0.U // New ISA: all operations start from row 0 op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := io.cmdReq.bits.cmd.op2_bank_addr + op2_bank_addr := 0.U // New ISA: all operations start from row 0 wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := io.cmdReq.bits.cmd.wr_bank_addr + wr_bank_addr := 0.U // New ISA: all operations start from row 0 state := busy io.is_matmul_ws := true.B } @@ -70,14 +78,14 @@ class BBFP_ID(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { iteration_counter := iteration_counter + 1.U when(iteration_counter === iteration - 1.U) { iteration_counter := 0.U - state := idle - } + state := idle + } } } // Generate ID_LU request io.id_lu_o.valid := state === busy io.id_lu_o.bits.op1_bank := op1_bank - io.id_lu_o.bits.op1_bank_addr := op1_bank_addr + b.veclane.U - iteration_counter - 1.U + io.id_lu_o.bits.op1_bank_addr := op1_bank_addr + InputNum.U - iteration_counter - 1.U io.id_lu_o.bits.op2_bank := op2_bank io.id_lu_o.bits.op2_bank_addr := op2_bank_addr + iteration_counter io.id_lu_o.bits.wr_bank := wr_bank @@ -91,7 +99,6 @@ class BBFP_ID(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // Instruction completion signal - // Delay complete signal by 10 cycles // val complete_delay = RegInit(VecInit(Seq.fill(10)(false.B))) // complete_delay(0) := complete @@ -100,5 +107,4 @@ class BBFP_ID(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // } // val complete_10clk = complete_delay(9) - } diff --git a/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala b/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala index bc68a86d..d7a9bcc7 100644 --- a/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala +++ b/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala @@ -3,64 +3,73 @@ package prototype.matrix import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.matrix._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import examples.BuckyballConfigs.CustomBuckyballConfig +import examples.toy.balldomain.BallDomainParam -class id_lu_req(implicit b: CustomBuckyballConfig) extends Bundle { - val op1_bank = UInt(log2Up(b.sp_banks).W) - val op1_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - val op2_bank = UInt(log2Up(b.sp_banks).W) - val op2_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - val wr_bank = UInt(log2Up(b.sp_banks).W) - val wr_bank_addr = UInt(log2Up(b.spad_bank_entries).W) +class id_lu_req(parameter: BallDomainParam) extends Bundle { + val op1_bank = UInt(log2Up(parameter.numBanks).W) + val op1_bank_addr = UInt(log2Up(parameter.bankEntries).W) + val op2_bank = UInt(log2Up(parameter.numBanks).W) + val op2_bank_addr = UInt(log2Up(parameter.bankEntries).W) + val wr_bank = UInt(log2Up(parameter.numBanks).W) + val wr_bank_addr = UInt(log2Up(parameter.bankEntries).W) val opcode = UInt(3.W) val iter = UInt(10.W) val thread_id = UInt(10.W) - val rob_id = UInt(log2Up(b.rob_entries).W) + val rob_id = UInt(log2Up(parameter.rob_entries).W) } -class lu_ex_req(implicit b: CustomBuckyballConfig) extends Bundle { - val op1_bank = UInt(log2Up(b.sp_banks).W) - val op2_bank = UInt(log2Up(b.sp_banks).W) - val wr_bank = UInt(log2Up(b.sp_banks).W) - val wr_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - val opcode = UInt(3.W) - val iter = UInt(10.W) - val thread_id = UInt(10.W) - val rob_id = UInt(log2Up(b.rob_entries).W) +class lu_ex_req(parameter: BallDomainParam) extends Bundle { + val op1_bank = UInt(log2Up(parameter.numBanks).W) + val op2_bank = UInt(log2Up(parameter.numBanks).W) + val wr_bank = UInt(log2Up(parameter.numBanks).W) + val wr_bank_addr = UInt(log2Up(parameter.bankEntries).W) + val opcode = UInt(3.W) + val iter = UInt(10.W) + val thread_id = UInt(10.W) + val rob_id = UInt(log2Up(parameter.rob_entries).W) } -class ID_LU(implicit b: CustomBuckyballConfig) extends Module{ +@instantiable +class ID_LU(val parameter: BallDomainParam) extends Module with SerializableModule[BallDomainParam] { + + @public val io = IO(new Bundle { - val id_lu_i = Flipped(Decoupled(new id_lu_req)) - val ld_lu_o = Decoupled(new id_lu_req) + val id_lu_i = Flipped(Decoupled(new id_lu_req(parameter))) + val ld_lu_o = Decoupled(new id_lu_req(parameter)) }) - // 1-cycle delay register - val delayed_req = RegEnable(io.id_lu_i.bits, io.id_lu_i.fire) + + // 1-cycle delay register + val delayed_req = RegEnable(io.id_lu_i.bits, io.id_lu_i.fire) val delayed_valid = RegNext(io.id_lu_i.valid, false.B) // Output connection - io.ld_lu_o.bits := delayed_req + io.ld_lu_o.bits := delayed_req io.ld_lu_o.valid := delayed_valid // Backpressure: input is ready if output is ready (since we have a 1-slot buffer) io.id_lu_i.ready := io.ld_lu_o.ready } -class LU_EX(implicit b: CustomBuckyballConfig) extends Module{ +@instantiable +class LU_EX(val parameter: BallDomainParam) extends Module with SerializableModule[BallDomainParam] { + + @public val io = IO(new Bundle { - val lu_ex_i = Flipped(Decoupled(new lu_ex_req)) - val lu_ex_o = Decoupled(new lu_ex_req) + val lu_ex_i = Flipped(Decoupled(new lu_ex_req(parameter))) + val lu_ex_o = Decoupled(new lu_ex_req(parameter)) }) - // 1-cycle delay register - val delayed_req = RegEnable(io.lu_ex_i.bits, io.lu_ex_i.fire) + + // 1-cycle delay register + val delayed_req = RegEnable(io.lu_ex_i.bits, io.lu_ex_i.fire) val delayed_valid = RegNext(io.lu_ex_i.valid, false.B) // Output connection - io.lu_ex_o.bits := delayed_req + io.lu_ex_o.bits := delayed_req io.lu_ex_o.valid := delayed_valid // Backpressure: input is ready if output is ready (since we have a 1-slot buffer) diff --git a/arch/src/main/scala/prototype/matrix/bbfp_control.scala b/arch/src/main/scala/prototype/matrix/bbfp_control.scala index 877c6232..c1cb0d13 100644 --- a/arch/src/main/scala/prototype/matrix/bbfp_control.scala +++ b/arch/src/main/scala/prototype/matrix/bbfp_control.scala @@ -3,75 +3,87 @@ package prototype.matrix import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.matrix._ -import org.yaml.snakeyaml.events.Event.ID -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status -class BBFP_Control(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class BBFP_Control(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters - using default values for compatibility + val InputNum = 16 // Default value + val inputWidth = 8 // UInt8 + val accWidth = 32 // UInt32 + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val cmdResp = Decoupled(new BallRsComplete(parameter)) val is_matmul_ws = Input(Bool()) // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, b.spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, b.spad_w, b.spad_mask_len))) + val sramRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) + val sramWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) - // Connect to Accumulator read/write interface - // val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + // Connect to Accumulator write interface (unified bank now) + val accWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) // Status output val status = new Status }) + // ----------------------------------------------------------------------------- // BBFP_ID // ----------------------------------------------------------------------------- - val BBFP_ID = Module(new BBFP_ID) + val BBFP_ID: Instance[BBFP_ID] = Instantiate(new BBFP_ID(parameter)) BBFP_ID.io.cmdReq <> io.cmdReq // ----------------------------------------------------------------------------- // ID_LU // ----------------------------------------------------------------------------- - val ID_LU = Module(new ID_LU) + val ID_LU: Instance[ID_LU] = Instantiate(new ID_LU(parameter)) ID_LU.io.id_lu_i <> BBFP_ID.io.id_lu_o // ----------------------------------------------------------------------------- // BBFP_LoadUnit // ----------------------------------------------------------------------------- - val BBFP_LoadUnit = Module(new BBFP_LoadUnit) + val BBFP_LoadUnit: Instance[BBFP_LoadUnit] = Instantiate(new BBFP_LoadUnit(parameter)) BBFP_LoadUnit.io.id_lu_i <> ID_LU.io.ld_lu_o - for (i <- 0 until b.sp_banks) { + for (i <- 0 until parameter.numBanks) { io.sramRead(i).req <> BBFP_LoadUnit.io.sramReadReq(i) } // ----------------------------------------------------------------------------- // LU_EX // ----------------------------------------------------------------------------- - val LU_EX = Module(new LU_EX) + val LU_EX: Instance[LU_EX] = Instantiate(new LU_EX(parameter)) LU_EX.io.lu_ex_i <> BBFP_LoadUnit.io.lu_ex_o // ----------------------------------------------------------------------------- // BBFP_EX // ----------------------------------------------------------------------------- - val BBFP_EX = Module(new BBFP_EX) + val BBFP_EX: Instance[BBFP_EX] = Instantiate(new BBFP_EX(parameter)) BBFP_EX.io.lu_ex_i <> LU_EX.io.lu_ex_o - for (i <- 0 until b.sp_banks) { + for (i <- 0 until parameter.numBanks) { BBFP_EX.io.sramReadResp(i) <> io.sramRead(i).resp io.sramWrite(i) <> BBFP_EX.io.sramWrite(i) } BBFP_EX.io.is_matmul_ws := io.is_matmul_ws - for (i <- 0 until b.acc_banks) { + for (i <- 0 until parameter.numBanks) { io.accWrite(i) <> BBFP_EX.io.accWrite(i) - // io.accRead(i) := DontCare } io.cmdResp <> BBFP_EX.io.cmdResp // Status tracking - val iterCnt = RegInit(0.U(32.W)) - val hasInput = RegInit(false.B) + val iterCnt = RegInit(0.U(32.W)) + val hasInput = RegInit(false.B) val hasOutput = RegInit(false.B) when(io.cmdReq.fire) { @@ -79,19 +91,19 @@ class BBFP_Control(implicit b: CustomBuckyballConfig, p: Parameters) extends Mod } when(io.cmdResp.fire) { hasOutput := false.B - hasInput := false.B - iterCnt := iterCnt + 1.U + hasInput := false.B + iterCnt := iterCnt + 1.U } when(io.cmdResp.valid && !hasOutput) { hasOutput := true.B } - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := !hasInput && !hasOutput - io.status.init := hasInput && !hasOutput - io.status.running := hasOutput + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := !hasInput && !hasOutput + io.status.init := hasInput && !hasOutput + io.status.running := hasOutput io.status.complete := io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt } diff --git a/arch/src/main/scala/prototype/matrix/bbfp_ex.scala b/arch/src/main/scala/prototype/matrix/bbfp_ex.scala index d7403431..9d798e27 100644 --- a/arch/src/main/scala/prototype/matrix/bbfp_ex.scala +++ b/arch/src/main/scala/prototype/matrix/bbfp_ex.scala @@ -3,85 +3,94 @@ package prototype.matrix import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.matrix._ -import framework.memdomain.mem.{SramWriteIO, SramReadIO, SramReadResp} -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} - -class BBFP_EX(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val rob_id_width = log2Up(b.rob_entries) - val spad_w = b.veclane * b.inputType.getWidth - +import framework.memdomain.backend.banks.{SramReadResp, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam + +@instantiable +class BBFP_EX(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val accWidth = 32 + val rob_id_width = log2Up(parameter.rob_entries) + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) - val lu_ex_i = Flipped(Decoupled(new lu_ex_req)) - val sramReadResp = Vec(b.sp_banks, Flipped(Decoupled(new SramReadResp(spad_w)))) + val sramWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) + val lu_ex_i = Flipped(Decoupled(new lu_ex_req(parameter))) + val sramReadResp = Vec(parameter.numBanks, Flipped(Decoupled(new SramReadResp(bankWidth)))) val is_matmul_ws = Input(Bool()) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) - val cmdResp = Decoupled(new BallRsComplete) + val accWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) + val cmdResp = Decoupled(new BallRsComplete(parameter)) }) - for(i <- 0 until b.sp_banks) { - io.sramWrite(i).req.valid := false.B + for (i <- 0 until parameter.numBanks) { + io.sramWrite(i).req.valid := false.B io.sramWrite(i).req.bits.addr := 0.U io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(spad_w / 8)(false.B)) + io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(false.B)) } - for(i <- 0 until b.acc_banks) { - io.accWrite(i).req.valid := false.B + for (i <- 0 until parameter.numBanks) { + io.accWrite(i).req.valid := false.B io.accWrite(i).req.bits.addr := DontCare io.accWrite(i).req.bits.data := DontCare - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + io.accWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) } - io.cmdResp.valid := false.B + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := 0.U - val idle::weight_load::data_compute::Nil = Enum(3) - val weight_cycles = RegInit(0.U(10.W)) - val act_cycles = RegInit(0.U(10.W)) - val weight_expreg=RegInit(0.U(32.W)) - val act_expreg=RegInit(0.U(32.W)) + val idle :: weight_load :: data_compute :: Nil = Enum(3) + val weight_cycles = RegInit(0.U(10.W)) + val act_cycles = RegInit(0.U(10.W)) + val weight_expreg = RegInit(0.U(32.W)) + val act_expreg = RegInit(0.U(32.W)) // Extract signals from pipeline frontend - val op1_bank_reg = Reg(UInt(io.lu_ex_i.bits.op1_bank.getWidth.W)) - val op2_bank_reg = Reg(UInt(io.lu_ex_i.bits.op2_bank.getWidth.W)) - val wr_bank = Reg(UInt(io.lu_ex_i.bits.wr_bank.getWidth.W)) - val opcode = Reg(UInt(io.lu_ex_i.bits.opcode.getWidth.W)) - - - val act_shift_reg = Reg(Vec(16, Vec(16, UInt(7.W)))) - val col_enable = RegInit(VecInit(Seq.fill(16)(false.B))) - val input_cycle = RegInit(0.U(5.W)) + val op1_bank_reg = Reg(UInt(io.lu_ex_i.bits.op1_bank.getWidth.W)) + val op2_bank_reg = Reg(UInt(io.lu_ex_i.bits.op2_bank.getWidth.W)) + val wr_bank = Reg(UInt(io.lu_ex_i.bits.wr_bank.getWidth.W)) + val opcode = Reg(UInt(io.lu_ex_i.bits.opcode.getWidth.W)) + + val act_shift_reg = Reg(Vec(16, Vec(16, UInt(7.W)))) + val col_enable = RegInit(VecInit(Seq.fill(16)(false.B))) + val input_cycle = RegInit(0.U(5.W)) val act_data_ready = RegInit(false.B) - when(io.lu_ex_i.valid) { - op1_bank_reg := io.lu_ex_i.bits.op1_bank - op2_bank_reg := io.lu_ex_i.bits.op2_bank - wr_bank := io.lu_ex_i.bits.wr_bank - opcode := io.lu_ex_i.bits.opcode + op1_bank_reg := io.lu_ex_i.bits.op1_bank + op2_bank_reg := io.lu_ex_i.bits.op2_bank + wr_bank := io.lu_ex_i.bits.wr_bank + opcode := io.lu_ex_i.bits.opcode } val op1_bank = Mux(io.lu_ex_i.valid, io.lu_ex_i.bits.op1_bank, op1_bank_reg) val op2_bank = Mux(io.lu_ex_i.valid, io.lu_ex_i.bits.op2_bank, op2_bank_reg) - val state = RegInit(idle) + val state = RegInit(idle) val pe_array = Module(new BBFP_PE_Array16x16) // Use shift registers instead of original regular registers - // Activation data input logic val act_reg_ptr = RegInit(0.U(5.W)) // In idle and weight_load phases, store data like regular registers when(io.sramReadResp(op2_bank).valid && state =/= data_compute && act_data_ready === false.B) { val data = io.sramReadResp(op2_bank).bits.data - for(i <- 0 until 16) { - act_shift_reg(act_reg_ptr)(i) := data((i+1)*8-1, i*8)(6,0) + for (i <- 0 until 16) { + act_shift_reg(act_reg_ptr)(i) := data((i + 1) * 8 - 1, i * 8)(6, 0) } act_reg_ptr := act_reg_ptr + 1.U } @@ -92,97 +101,95 @@ class BBFP_EX(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { when(io.sramReadResp(op1_bank).valid && !io.is_matmul_ws) { val data = io.sramReadResp(op1_bank).bits.data - for(i <- 0 until 16) { - weight_reg(i) := data((i+1)*8-1, i*8)(6,0) + for (i <- 0 until 16) { + weight_reg(i) := data((i + 1) * 8 - 1, i * 8)(6, 0) } } // New registers for weight and activation counting // Save 64 4x32 registers for output - val output_buffer = Reg(Vec(64, Vec(4, UInt(32.W)))) + val output_buffer = Reg(Vec(64, Vec(4, UInt(32.W)))) // Save parallelogram output val output_buffer_parallelogram = Reg(Vec(32, Vec(16, UInt(32.W)))) - val output_ptr = RegInit(0.U(5.W)) - val output_ready = RegInit(false.B) + val output_ptr = RegInit(0.U(5.W)) + val output_ready = RegInit(false.B) // New output data processing logic // Extended to 7 bits to support 64 cycles - val write_cycles = RegInit(0.U(7.W)) + val write_cycles = RegInit(0.U(7.W)) val writing_output = RegInit(false.B) - val wr_bank_addr_base = Reg(UInt(io.lu_ex_i.bits.wr_bank_addr.getWidth.W)) + val wr_bank_addr_base = Reg(UInt(io.lu_ex_i.bits.wr_bank_addr.getWidth.W)) val addr_base_captured = RegInit(false.B) when(io.lu_ex_i.valid && !addr_base_captured) { - wr_bank_addr_base := io.lu_ex_i.bits.wr_bank_addr + wr_bank_addr_base := io.lu_ex_i.bits.wr_bank_addr addr_base_captured := true.B - weight_expreg := io.sramReadResp(op1_bank).bits.data(127,96) - act_expreg := io.sramReadResp(op2_bank).bits.data(127,96) + weight_expreg := io.sramReadResp(op1_bank).bits.data(127, 96) + act_expreg := io.sramReadResp(op2_bank).bits.data(127, 96) } - val result_exp = weight_expreg+act_expreg - - + val result_exp = weight_expreg + act_expreg // PE array default value assignment - pe_array.io.in_last := VecInit(Seq.fill(16)(false.B)) - pe_array.io.in_id := DontCare - pe_array.io.in_a := DontCare - pe_array.io.in_d := DontCare - pe_array.io.in_b := VecInit(Seq.fill(16)(0.U)) + pe_array.io.in_last := VecInit(Seq.fill(16)(false.B)) + pe_array.io.in_id := DontCare + pe_array.io.in_a := DontCare + pe_array.io.in_d := DontCare + pe_array.io.in_b := VecInit(Seq.fill(16)(0.U)) pe_array.io.in_control.foreach(_.propagate := 0.U) - pe_array.io.in_valid := VecInit(Seq.fill(16)(false.B)) + pe_array.io.in_valid := VecInit(Seq.fill(16)(false.B)) // Default SRAM write port assignment - for(i <- 0 until b.sp_banks){ - io.sramWrite(i).req.valid := false.B + for (i <- 0 until parameter.numBanks) { + io.sramWrite(i).req.valid := false.B io.sramWrite(i).req.bits.addr := 0.U io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(spad_w / 8)(false.B)) + io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(false.B)) } // Start writing to SRAM when output is ready when(output_ready && !writing_output) { writing_output := true.B - write_cycles := 0.U + write_cycles := 0.U } when(writing_output) { when(write_cycles < 16.U) { - // Concatenate 4x32-bit data into 128-bit wide data and write to SRAM - for(i <- 0 until b.acc_banks/2) { - when((wr_bank_addr_base + write_cycles)(0) === 0.U){ - io.accWrite(i).req.valid := true.B - io.accWrite(i).req.bits.addr := wr_bank_addr_base + (write_cycles >> 1.U) - val idx = (write_cycles * 4.U + i.U)(5,0) // 6 bits for 64 elements - io.accWrite(i).req.bits.data := Cat( - output_buffer(idx)(3), - output_buffer(idx)(2), - output_buffer(idx)(1), - output_buffer(idx)(0) - ) - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) - }.otherwise{ - io.accWrite(i + b.acc_banks/2).req.valid := true.B - io.accWrite(i + b.acc_banks/2).req.bits.addr := wr_bank_addr_base + (write_cycles >> 1.U) - val idx = (write_cycles * 4.U + i.U)(5,0) // 6 bits for 64 elements - io.accWrite(i + b.acc_banks/2).req.bits.data := Cat( - output_buffer(idx)(3), - output_buffer(idx)(2), - output_buffer(idx)(1), - output_buffer(idx)(0) - ) - io.accWrite(i + b.acc_banks/2).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + // Concatenate 4x32-bit data into 128-bit wide data and write to SRAM + for (i <- 0 until parameter.numBanks / 2) { + when((wr_bank_addr_base + write_cycles)(0) === 0.U) { + io.accWrite(i).req.valid := true.B + io.accWrite(i).req.bits.addr := wr_bank_addr_base + (write_cycles >> 1.U) + val idx = (write_cycles * 4.U + i.U)(5, 0) // 6 bits for 64 elements + io.accWrite(i).req.bits.data := Cat( + output_buffer(idx)(3), + output_buffer(idx)(2), + output_buffer(idx)(1), + output_buffer(idx)(0) + ) + io.accWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + }.otherwise { + io.accWrite(i + parameter.numBanks / 2).req.valid := true.B + io.accWrite(i + parameter.numBanks / 2).req.bits.addr := wr_bank_addr_base + (write_cycles >> 1.U) + val idx = (write_cycles * 4.U + i.U)(5, 0) // 6 bits for 64 elements + io.accWrite(i + parameter.numBanks / 2).req.bits.data := Cat( + output_buffer(idx)(3), + output_buffer(idx)(2), + output_buffer(idx)(1), + output_buffer(idx)(0) + ) + io.accWrite(i + parameter.numBanks / 2).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + } } - } - write_cycles := write_cycles + 1.U + write_cycles := write_cycles + 1.U }.otherwise { - // Write completed - writing_output := false.B - output_ready := false.B - addr_base_captured:=false.B + // Write completed + writing_output := false.B + output_ready := false.B + addr_base_captured := false.B io.cmdResp.bits.rob_id := io.lu_ex_i.bits.rob_id - io.cmdResp.valid := true.B + io.cmdResp.valid := true.B } } @@ -190,106 +197,105 @@ class BBFP_EX(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { switch(state) { is(idle) { - when(io.lu_ex_i.valid && !io.is_matmul_ws) { - // Start weight loading - weight_cycles := 0.U - state := weight_load - }.elsewhen(io.is_matmul_ws && act_data_ready){ - state := data_compute - act_cycles := 0.U - } + when(io.lu_ex_i.valid && !io.is_matmul_ws) { + // Start weight loading + weight_cycles := 0.U + state := weight_load + }.elsewhen(io.is_matmul_ws && act_data_ready) { + state := data_compute + act_cycles := 0.U + } } is(weight_load) { - // Load 16 cycles of weights - when(weight_cycles < 16.U) { - pe_array.io.in_d := weight_reg - pe_array.io.in_control.foreach(_.propagate := 1.U) - pe_array.io.in_valid.foreach(_ := true.B) - weight_cycles := weight_cycles + 1.U - }.otherwise { - // Weight loading completed, wait for activation data to be ready then enter computation - when(act_data_ready) { - act_cycles := 0.U - state := data_compute + // Load 16 cycles of weights + when(weight_cycles < 16.U) { + pe_array.io.in_d := weight_reg + pe_array.io.in_control.foreach(_.propagate := 1.U) + pe_array.io.in_valid.foreach(_ := true.B) + weight_cycles := weight_cycles + 1.U + }.otherwise { + // Weight loading completed, wait for activation data to be ready then enter computation + when(act_data_ready) { + act_cycles := 0.U + state := data_compute + } } } - } is(data_compute) { - act_cycles := act_cycles + 1.U - // In computation phase, start parallelogram input mode for shift registers - when(act_cycles < 31.U) { - // Each cycle enables more rows for shifting row by row - for(col <- 0 until 16) { - when(col.U <= act_cycles && col.U < 16.U) { - col_enable(col) := true.B - }.otherwise { - col_enable(col) := false.B - } - } + act_cycles := act_cycles + 1.U + // In computation phase, start parallelogram input mode for shift registers + when(act_cycles < 31.U) { + // Each cycle enables more rows for shifting row by row + for (col <- 0 until 16) { + when(col.U <= act_cycles && col.U < 16.U) { + col_enable(col) := true.B + }.otherwise { + col_enable(col) := false.B + } + } - // Shift register operation: enabled rows shift right - for(col <- 0 until 16) { - when(col_enable(col)) { - for(row <- 0 until 15) { - act_shift_reg(row)(col) := act_shift_reg(row + 1)(col) + // Shift register operation: enabled rows shift right + for (col <- 0 until 16) { + when(col_enable(col)) { + for (row <- 0 until 15) { + act_shift_reg(row)(col) := act_shift_reg(row + 1)(col) + } + // Pad left with 0 (because in computation phase, no new data is input) + act_shift_reg(15)(col) := 0.U(7.W) + } } - // Pad left with 0 (because in computation phase, no new data is input) - act_shift_reg(15)(col) := 0.U(7.W) - } - } - // Input rightmost element of each row (column 15) to PE array - val current_input = WireDefault(VecInit(Seq.fill(16)(0.U(7.W)))) - for(col <- 0 until 16) { - when(col_enable(col)) { - current_input(col) := act_shift_reg(0)(col) - }.otherwise { - current_input(col) := 0.U(7.W) - } + // Input rightmost element of each row (column 15) to PE array + val current_input = WireDefault(VecInit(Seq.fill(16)(0.U(7.W)))) + for (col <- 0 until 16) { + when(col_enable(col)) { + current_input(col) := act_shift_reg(0)(col) + }.otherwise { + current_input(col) := 0.U(7.W) + } + } + pe_array.io.in_a := current_input + pe_array.io.in_b.foreach(_ := 0.U) } - pe_array.io.in_a := current_input - pe_array.io.in_b.foreach(_ := 0.U) - } - // Start receiving output from cycle 16, end at cycle 47 + // Start receiving output from cycle 16, end at cycle 47 - when(act_cycles > 16.U && act_cycles <= 48.U) { - output_buffer_parallelogram(output_ptr) := pe_array.io.out_b - output_ptr := output_ptr + 1.U - } + when(act_cycles > 16.U && act_cycles <= 48.U) { + output_buffer_parallelogram(output_ptr) := pe_array.io.out_b + output_ptr := output_ptr + 1.U + } - // After cycle 47, convert parallelogram output to 64 4x32 registers - when(act_cycles === 49.U) { - output_ready := true.B - // Convert parallelogram output to 64 4x32 registers, organized in row-major order - for(row <- 0 until 16) { - for(col <- 0 until 16) { - val src_row = row + col - // Every 4 columns form one register group - val buffer_index = row * 4 + (col >> 2) - // Position within 4-element group - val element_index = col & 0x3 - if(src_row < 32) { - output_buffer(buffer_index)(element_index) := output_buffer_parallelogram(src_row)(col) - } else { - output_buffer(buffer_index)(element_index) := 0.U(32.W) + // After cycle 47, convert parallelogram output to 64 4x32 registers + when(act_cycles === 49.U) { + output_ready := true.B + // Convert parallelogram output to 64 4x32 registers, organized in row-major order + for (row <- 0 until 16) { + for (col <- 0 until 16) { + val src_row = row + col + // Every 4 columns form one register group + val buffer_index = row * 4 + (col >> 2) + // Position within 4-element group + val element_index = col & 0x3 + if (src_row < 32) { + output_buffer(buffer_index)(element_index) := output_buffer_parallelogram(src_row)(col) + } else { + output_buffer(buffer_index)(element_index) := 0.U(32.W) + } + } } } - } - } - // Reset data ready flag - when(act_cycles === 50.U) { - act_data_ready := false.B - act_reg_ptr := 0.U - output_ptr := 0.U - // Reset all row enable signals - col_enable := VecInit(Seq.fill(16)(false.B)) - state := idle - } + // Reset data ready flag + when(act_cycles === 50.U) { + act_data_ready := false.B + act_reg_ptr := 0.U + output_ptr := 0.U + // Reset all row enable signals + col_enable := VecInit(Seq.fill(16)(false.B)) + state := idle + } } } - io.sramReadResp.foreach { resp => resp.ready := state =/= idle } diff --git a/arch/src/main/scala/prototype/matrix/bbfp_load.scala b/arch/src/main/scala/prototype/matrix/bbfp_load.scala index e1d2ffcf..d0938859 100644 --- a/arch/src/main/scala/prototype/matrix/bbfp_load.scala +++ b/arch/src/main/scala/prototype/matrix/bbfp_load.scala @@ -3,58 +3,67 @@ package prototype.matrix import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.matrix._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.SramReadReq +import examples.toy.balldomain.BallDomainParam -class BBFP_LoadUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val rob_id_width = log2Up(b.rob_entries) - val spad_w = b.veclane * b.inputType.getWidth +@instantiable +class BBFP_LoadUnit(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val rob_id_width = log2Up(parameter.rob_entries) + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { - val sramReadReq = Vec(b.sp_banks,Decoupled(new SramReadReq(b.spad_bank_entries))) - val id_lu_i = Flipped(Decoupled(new id_lu_req)) - val lu_ex_o = Decoupled(new lu_ex_req) + val sramReadReq = Vec(parameter.numBanks, Decoupled(new SramReadReq(parameter.bankEntries))) + val id_lu_i = Flipped(Decoupled(new id_lu_req(parameter))) + val lu_ex_o = Decoupled(new lu_ex_req(parameter)) }) - val op1_bank = io.id_lu_i.bits.op1_bank + val op1_bank = io.id_lu_i.bits.op1_bank val op1_bank_addr = io.id_lu_i.bits.op1_bank_addr - val op2_bank = io.id_lu_i.bits.op2_bank + val op2_bank = io.id_lu_i.bits.op2_bank val op2_bank_addr = io.id_lu_i.bits.op2_bank_addr - val wr_bank = io.id_lu_i.bits.wr_bank - val wr_bank_addr = io.id_lu_i.bits.wr_bank_addr + val wr_bank = io.id_lu_i.bits.wr_bank + val wr_bank_addr = io.id_lu_i.bits.wr_bank_addr // Default assignment for each bank read request - for(i <- 0 until b.sp_banks){ - io.sramReadReq(i).valid := false.B + for (i <- 0 until parameter.numBanks) { + io.sramReadReq(i).valid := false.B io.sramReadReq(i).bits.fromDMA := false.B - io.sramReadReq(i).bits.addr := 0.U + io.sramReadReq(i).bits.addr := 0.U } // Generate SRAM read request based on ID_LU input - when(io.id_lu_i.valid){ - io.sramReadReq(op1_bank).valid := true.B + when(io.id_lu_i.valid) { + io.sramReadReq(op1_bank).valid := true.B io.sramReadReq(op1_bank).bits.fromDMA := false.B - io.sramReadReq(op1_bank).bits.addr := op1_bank_addr + io.sramReadReq(op1_bank).bits.addr := op1_bank_addr - io.sramReadReq(op2_bank).valid := true.B + io.sramReadReq(op2_bank).valid := true.B io.sramReadReq(op2_bank).bits.fromDMA := false.B - io.sramReadReq(op2_bank).bits.addr := op2_bank_addr + io.sramReadReq(op2_bank).bits.addr := op2_bank_addr } // Generate LU_EX request - io.lu_ex_o.valid := io.id_lu_i.valid - io.lu_ex_o.bits.op1_bank := op1_bank - io.lu_ex_o.bits.op2_bank := op2_bank - io.lu_ex_o.bits.wr_bank := wr_bank + io.lu_ex_o.valid := io.id_lu_i.valid + io.lu_ex_o.bits.op1_bank := op1_bank + io.lu_ex_o.bits.op2_bank := op2_bank + io.lu_ex_o.bits.wr_bank := wr_bank io.lu_ex_o.bits.wr_bank_addr := wr_bank_addr - io.lu_ex_o.bits.opcode := io.id_lu_i.bits.opcode - io.lu_ex_o.bits.iter := io.id_lu_i.bits.iter - io.lu_ex_o.bits.thread_id := io.id_lu_i.bits.thread_id - io.lu_ex_o.bits.rob_id := io.id_lu_i.bits.rob_id + io.lu_ex_o.bits.opcode := io.id_lu_i.bits.opcode + io.lu_ex_o.bits.iter := io.id_lu_i.bits.iter + io.lu_ex_o.bits.thread_id := io.id_lu_i.bits.thread_id + io.lu_ex_o.bits.rob_id := io.id_lu_i.bits.rob_id io.id_lu_i.ready := io.lu_ex_o.ready - } diff --git a/arch/src/main/scala/prototype/matrix/bbfp_pe.scala b/arch/src/main/scala/prototype/matrix/bbfp_pe.scala index a8236338..c1809ab7 100644 --- a/arch/src/main/scala/prototype/matrix/bbfp_pe.scala +++ b/arch/src/main/scala/prototype/matrix/bbfp_pe.scala @@ -1,8 +1,10 @@ package prototype.matrix + import chisel3._ import chisel3.util._ import chisel3.stage._ import prototype.matrix._ + // PE control signal Bundle class PEControl extends Bundle { // Propagation control @@ -10,15 +12,16 @@ class PEControl extends Bundle { } class MacUnit extends Module { + val io = IO(new Bundle { - // Unsigned input: [6]=sign, [5]=flag, [4:0]=value - val in_a = Input(UInt(7.W)) - // Unsigned input: [6]=sign, [5]=flag, [4:0]=value - val in_b = Input(UInt(7.W)) - // Unsigned input: [31]=sign, [30:0]=value - val in_c = Input(UInt(32.W)) - // Signed output - val out_d = Output(UInt(32.W)) + // Unsigned input: [6]=sign, [5]=flag, [4:0]=value + val in_a = Input(UInt(7.W)) + // Unsigned input: [6]=sign, [5]=flag, [4:0]=value + val in_b = Input(UInt(7.W)) + // Unsigned input: [31]=sign, [30:0]=value + val in_c = Input(UInt(32.W)) + // Signed output + val out_d = Output(UInt(32.W)) }) // Extract sign bits @@ -38,32 +41,20 @@ class MacUnit extends Module { // 31-bit value val value_c = io.in_c(30, 0) - // val extended_a = value_a.asUInt().pad(7) // Extend to 7 bits // val extended_b = value_b.asUInt().pad(7) // Extend to 7 bits - // Determine left shift based on flag bit val shifted_a = Mux(flag_a === 1.U, value_a << 2, value_a) val shifted_b = Mux(flag_b === 1.U, value_b << 2, value_b) - // Convert value to signed number, considering sign bit // First extend bit width to avoid overflow, then determine sign based on sign bit - val a_signed = Mux(sign_a === 1.U, - -(shifted_a.zext), - shifted_a.zext - ).asSInt + val a_signed = Mux(sign_a === 1.U, -(shifted_a.zext), shifted_a.zext).asSInt - val b_signed = Mux(sign_b === 1.U, - -(shifted_b.zext), - shifted_b.zext - ).asSInt + val b_signed = Mux(sign_b === 1.U, -(shifted_b.zext), shifted_b.zext).asSInt - val c_signed = Mux(sign_c === 1.U, - -(value_c.zext), - value_c.zext - ).asSInt + val c_signed = Mux(sign_c === 1.U, -(value_c.zext), value_c.zext).asSInt // Perform MAC operation: a * b + c val result = a_signed * b_signed + c_signed @@ -72,60 +63,60 @@ class MacUnit extends Module { io.out_d := result.asUInt } - // BBFP PE unit (only supports Weight Stationary) class BBFP_PE_WS(max_simultaneous_matmuls: Int = 16) extends Module { + val io = IO(new Bundle { - // Data input/output - // Input activation value - val in_a = Input(UInt(7.W)) - // Input partial sum - val in_b = Input(UInt(32.W)) - // Input weight - val in_d = Input(UInt(7.W)) - // Output activation value - val out_a = Output(UInt(7.W)) - // Output partial sum - val out_b = Output(UInt(32.W)) - // Output weight - val out_d = Output(UInt(7.W)) - // Control signals - val in_control = Input(new PEControl()) - val out_control = Output(new PEControl()) - - // ID and valid signals - val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) - val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) - - val in_last = Input(Bool()) - val out_last = Output(Bool()) - - val in_valid = Input(Bool()) - val out_valid = Output(Bool()) + // Data input/output + // Input activation value + val in_a = Input(UInt(7.W)) + // Input partial sum + val in_b = Input(UInt(32.W)) + // Input weight + val in_d = Input(UInt(7.W)) + // Output activation value + val out_a = Output(UInt(7.W)) + // Output partial sum + val out_b = Output(UInt(32.W)) + // Output weight + val out_d = Output(UInt(7.W)) + // Control signals + val in_control = Input(new PEControl()) + val out_control = Output(new PEControl()) + + // ID and valid signals + val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) + val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) + + val in_last = Input(Bool()) + val out_last = Output(Bool()) + + val in_valid = Input(Bool()) + val out_valid = Output(Bool()) }) // Instantiate MAC unit val mac_unit = Module(new MacUnit) // Input signals - val a = io.in_a - val b = io.in_b - val d = io.in_d - val prop = io.in_control.propagate + val a = io.in_a + val b = io.in_b + val d = io.in_d + val prop = io.in_control.propagate // val shift = io.in_control.shift // Removed - val id = io.in_id - val last = io.in_last + val id = io.in_id + val last = io.in_last val valid = io.in_valid // Accumulation register val weight = Reg(UInt(7.W)) // Pass-through signals - io.out_a := a + io.out_a := a io.out_control.propagate := prop - io.out_id := id - io.out_last := last - io.out_valid := valid + io.out_id := id + io.out_last := last + io.out_valid := valid // MAC unit connections mac_unit.io.in_a := a @@ -135,58 +126,57 @@ class BBFP_PE_WS(max_simultaneous_matmuls: Int = 16) extends Module { val PROPAGATE = 1.U(1.W) // Default assignment - io.out_b := b + io.out_b := b mac_unit.io.in_c := b // Weight Stationary mode when(prop === PROPAGATE) { - when(valid) { - weight := d - } - io.out_d := d - mac_unit.io.in_b := d - mac_unit.io.in_c := b - mac_unit.io.in_a := a - io.out_b := mac_unit.io.out_d - io.out_a := a + when(valid) { + weight := d + } + io.out_d := d + mac_unit.io.in_b := d + mac_unit.io.in_c := b + mac_unit.io.in_a := a + io.out_b := mac_unit.io.out_d + io.out_a := a }.otherwise { - // Computation mode: output c2, use c1 as weight for computation - io.out_a := a - io.out_d := DontCare - mac_unit.io.in_b := weight - mac_unit.io.in_c := b - mac_unit.io.in_a := a - io.out_b := mac_unit.io.out_d + // Computation mode: output c2, use c1 as weight for computation + io.out_a := a + io.out_d := DontCare + mac_unit.io.in_b := weight + mac_unit.io.in_c := b + mac_unit.io.in_a := a + io.out_b := mac_unit.io.out_d } // Do not update register when invalid when(!valid) { - weight := weight + weight := weight } } - - class BBFP_PE_Array2x2 extends Module { + val io = IO(new Bundle { - // Row input activation (horizontal propagation) - val in_a = Input(Vec(2, UInt(7.W))) - // Column input weight (vertical propagation) - val in_d = Input(Vec(2, UInt(7.W))) - // Column input partial sum (vertical propagation) - val in_b = Input(Vec(2, UInt(32.W))) - // Column input control signal (follows weight vertical propagation) - val in_control = Input(Vec(2, new PEControl())) - val in_id = Input(Vec(2, UInt(1.W))) - val in_last = Input(Vec(2, Bool())) - val in_valid = Input(Vec(2, Bool())) - - // Output - // Bottom row output partial sum - val out_b = Output(Vec(2, UInt(32.W))) - // Right column output activation - val out_a = Output(Vec(2, UInt(7.W))) - // Bottom row output weight - val out_d = Output(Vec(2, UInt(7.W))) + // Row input activation (horizontal propagation) + val in_a = Input(Vec(2, UInt(7.W))) + // Column input weight (vertical propagation) + val in_d = Input(Vec(2, UInt(7.W))) + // Column input partial sum (vertical propagation) + val in_b = Input(Vec(2, UInt(32.W))) + // Column input control signal (follows weight vertical propagation) + val in_control = Input(Vec(2, new PEControl())) + val in_id = Input(Vec(2, UInt(1.W))) + val in_last = Input(Vec(2, Bool())) + val in_valid = Input(Vec(2, Bool())) + + // Output + // Bottom row output partial sum + val out_b = Output(Vec(2, UInt(32.W))) + // Right column output activation + val out_a = Output(Vec(2, UInt(7.W))) + // Bottom row output weight + val out_d = Output(Vec(2, UInt(7.W))) }) // 2x2 PE array @@ -194,80 +184,80 @@ class BBFP_PE_Array2x2 extends Module { // Registers connecting between PEs // Activation horizontal propagation register (row direction, left->right) - val reg_a_h = Seq.fill(2)(Reg(UInt(7.W))) // pes(i)(0) -> pes(i)(1) + val reg_a_h = Seq.fill(2)(Reg(UInt(7.W))) // pes(i)(0) -> pes(i)(1) // Weight vertical propagation register (column direction, top->bottom) - val reg_d_v = Seq.fill(2)(Reg(UInt(7.W))) // pes(0)(j) -> pes(1)(j) + val reg_d_v = Seq.fill(2)(Reg(UInt(7.W))) // pes(0)(j) -> pes(1)(j) // Partial sum vertical propagation register (column direction, top->bottom) val reg_b_v = Seq.fill(2)(Reg(UInt(32.W))) // pes(0)(j) -> pes(1)(j) // Control signal vertical propagation register (column direction, top->bottom) - val reg_ctrl_v = Seq.fill(2)(Wire(new PEControl)) - val reg_id_v = Seq.fill(2)(Wire(UInt(1.W))) - val reg_last_v = Seq.fill(2)(Wire(Bool())) - val reg_valid_v = Seq.fill(2)(Wire(Bool())) + val reg_ctrl_v = Seq.fill(2)(Wire(new PEControl)) + val reg_id_v = Seq.fill(2)(Wire(UInt(1.W))) + val reg_last_v = Seq.fill(2)(Wire(Bool())) + val reg_valid_v = Seq.fill(2)(Wire(Bool())) // ================ PE(0,0) ================ // Row 0 activation input - pes(0)(0).io.in_a := io.in_a(0) + pes(0)(0).io.in_a := io.in_a(0) // Column 0 weight input - pes(0)(0).io.in_d := io.in_d(0) + pes(0)(0).io.in_d := io.in_d(0) // Column 0 partial sum input - pes(0)(0).io.in_b := io.in_b(0) + pes(0)(0).io.in_b := io.in_b(0) // Column 0 control signal input pes(0)(0).io.in_control := io.in_control(0) - pes(0)(0).io.in_id := io.in_id(0) - pes(0)(0).io.in_last := io.in_last(0) + pes(0)(0).io.in_id := io.in_id(0) + pes(0)(0).io.in_last := io.in_last(0) pes(0)(0).io.in_valid := io.in_valid(0) // ================ PE(0,1) ================ // Activation propagates horizontally from PE(0,0) (through register) - reg_a_h(0) := pes(0)(0).io.out_a - pes(0)(1).io.in_a := reg_a_h(0) + reg_a_h(0) := pes(0)(0).io.out_a + pes(0)(1).io.in_a := reg_a_h(0) // Weight, partial sum, control signal input from external column 1 - pes(0)(1).io.in_d := io.in_d(1) - pes(0)(1).io.in_b := io.in_b(1) + pes(0)(1).io.in_d := io.in_d(1) + pes(0)(1).io.in_b := io.in_b(1) pes(0)(1).io.in_control := io.in_control(1) - pes(0)(1).io.in_id := io.in_id(1) - pes(0)(1).io.in_last := io.in_last(1) + pes(0)(1).io.in_id := io.in_id(1) + pes(0)(1).io.in_last := io.in_last(1) pes(0)(1).io.in_valid := io.in_valid(1) // ================ PE(1,0) ================ // Activation input from external row 1 - pes(1)(0).io.in_a := io.in_a(1) + pes(1)(0).io.in_a := io.in_a(1) // Weight, partial sum, control signal propagate vertically from PE(0,0) (through register) - reg_d_v(0) := pes(0)(0).io.out_d - reg_b_v(0) := pes(0)(0).io.out_b - reg_ctrl_v(0) := pes(0)(0).io.out_control - reg_id_v(0) := pes(0)(0).io.out_id - reg_last_v(0) := pes(0)(0).io.out_last - reg_valid_v(0):= pes(0)(0).io.out_valid - - pes(1)(0).io.in_d := reg_d_v(0) - pes(1)(0).io.in_b := reg_b_v(0) + reg_d_v(0) := pes(0)(0).io.out_d + reg_b_v(0) := pes(0)(0).io.out_b + reg_ctrl_v(0) := pes(0)(0).io.out_control + reg_id_v(0) := pes(0)(0).io.out_id + reg_last_v(0) := pes(0)(0).io.out_last + reg_valid_v(0) := pes(0)(0).io.out_valid + + pes(1)(0).io.in_d := reg_d_v(0) + pes(1)(0).io.in_b := reg_b_v(0) pes(1)(0).io.in_control := reg_ctrl_v(0) - pes(1)(0).io.in_id := reg_id_v(0) - pes(1)(0).io.in_last := reg_last_v(0) + pes(1)(0).io.in_id := reg_id_v(0) + pes(1)(0).io.in_last := reg_last_v(0) pes(1)(0).io.in_valid := reg_valid_v(0) // ================ PE(1,1) ================ // Activation propagates horizontally from PE(1,0) (through register) - reg_a_h(1) := pes(1)(0).io.out_a - pes(1)(1).io.in_a := reg_a_h(1) + reg_a_h(1) := pes(1)(0).io.out_a + pes(1)(1).io.in_a := reg_a_h(1) // Weight, partial sum, control signal propagate vertically from PE(0,1) (through register) - reg_d_v(1) := pes(0)(1).io.out_d - reg_b_v(1) := pes(0)(1).io.out_b - reg_ctrl_v(1) := pes(0)(1).io.out_control - reg_id_v(1) := pes(0)(1).io.out_id - reg_last_v(1) := pes(0)(1).io.out_last - reg_valid_v(1):= pes(0)(1).io.out_valid - - pes(1)(1).io.in_d := reg_d_v(1) - pes(1)(1).io.in_b := reg_b_v(1) + reg_d_v(1) := pes(0)(1).io.out_d + reg_b_v(1) := pes(0)(1).io.out_b + reg_ctrl_v(1) := pes(0)(1).io.out_control + reg_id_v(1) := pes(0)(1).io.out_id + reg_last_v(1) := pes(0)(1).io.out_last + reg_valid_v(1) := pes(0)(1).io.out_valid + + pes(1)(1).io.in_d := reg_d_v(1) + pes(1)(1).io.in_b := reg_b_v(1) pes(1)(1).io.in_control := reg_ctrl_v(1) - pes(1)(1).io.in_id := reg_id_v(1) - pes(1)(1).io.in_last := reg_last_v(1) + pes(1)(1).io.in_id := reg_id_v(1) + pes(1)(1).io.in_last := reg_last_v(1) pes(1)(1).io.in_valid := reg_valid_v(1) // ================ Output connections ================ @@ -289,26 +279,27 @@ class BBFP_PE_Array2x2 extends Module { } class BBFP_PE_Array16x16 extends Module { + val io = IO(new Bundle { - // Row input activation (horizontal propagation) - 16 rows - val in_a = Input(Vec(16, UInt(7.W))) - // Column input weight (vertical propagation) - 16 columns - val in_d = Input(Vec(16, UInt(7.W))) - // Column input partial sum (vertical propagation) - 16 columns - val in_b = Input(Vec(16, UInt(32.W))) - // Column input control signal (follows weight vertical propagation) - 16 columns - val in_control = Input(Vec(16, new PEControl())) - val in_id = Input(Vec(16, UInt(1.W))) - val in_last = Input(Vec(16, Bool())) - val in_valid = Input(Vec(16, Bool())) - - // Output - // Bottom row output partial sum - val out_b = Output(Vec(16, UInt(32.W))) - // Right column output activation - val out_a = Output(Vec(16, UInt(7.W))) - // Bottom row output weight - val out_d = Output(Vec(16, UInt(7.W))) + // Row input activation (horizontal propagation) - 16 rows + val in_a = Input(Vec(16, UInt(7.W))) + // Column input weight (vertical propagation) - 16 columns + val in_d = Input(Vec(16, UInt(7.W))) + // Column input partial sum (vertical propagation) - 16 columns + val in_b = Input(Vec(16, UInt(32.W))) + // Column input control signal (follows weight vertical propagation) - 16 columns + val in_control = Input(Vec(16, new PEControl())) + val in_id = Input(Vec(16, UInt(1.W))) + val in_last = Input(Vec(16, Bool())) + val in_valid = Input(Vec(16, Bool())) + + // Output + // Bottom row output partial sum + val out_b = Output(Vec(16, UInt(32.W))) + // Right column output activation + val out_a = Output(Vec(16, UInt(7.W))) + // Bottom row output weight + val out_d = Output(Vec(16, UInt(7.W))) }) // 16x16 PE array @@ -316,19 +307,19 @@ class BBFP_PE_Array16x16 extends Module { // Registers connecting between PEs // Activation horizontal propagation register (row direction, left->right) - val reg_a_h = Seq.fill(16, 15)(Reg(UInt(7.W))) // pes(i)(j) -> pes(i)(j+1) + val reg_a_h = Seq.fill(16, 15)(Reg(UInt(7.W))) // pes(i)(j) -> pes(i)(j+1) // Weight vertical propagation register (column direction, top->bottom) - val reg_d_v = Seq.fill(15, 16)(Reg(UInt(7.W))) // pes(i)(j) -> pes(i+1)(j) + val reg_d_v = Seq.fill(15, 16)(Reg(UInt(7.W))) // pes(i)(j) -> pes(i+1)(j) // Partial sum vertical propagation register (column direction, top->bottom) val reg_b_v = Seq.fill(15, 16)(Reg(UInt(32.W))) // pes(i)(j) -> pes(i+1)(j) // Control signal vertical propagation register (column direction, top->bottom) - val reg_ctrl_v = Seq.fill(15, 16)(Wire(new PEControl)) - val reg_id_v = Seq.fill(15, 16)(Wire(UInt(1.W))) - val reg_last_v = Seq.fill(15, 16)(Wire(Bool())) - val reg_valid_v = Seq.fill(15, 16)(Wire(Bool())) + val reg_ctrl_v = Seq.fill(15, 16)(Wire(new PEControl)) + val reg_id_v = Seq.fill(15, 16)(Wire(UInt(1.W))) + val reg_last_v = Seq.fill(15, 16)(Wire(Bool())) + val reg_valid_v = Seq.fill(15, 16)(Wire(Bool())) // ================ PE array connections ================ for (i <- 0 until 16) { @@ -339,8 +330,8 @@ class BBFP_PE_Array16x16 extends Module { pes(i)(j).io.in_a := io.in_a(i) } else { // Other columns: propagate from left PE through register - reg_a_h(i)(j-1) := pes(i)(j-1).io.out_a - pes(i)(j).io.in_a := reg_a_h(i)(j-1) + reg_a_h(i)(j - 1) := pes(i)(j - 1).io.out_a + pes(i)(j).io.in_a := reg_a_h(i)(j - 1) } // Weight input connection (vertical propagation) @@ -349,38 +340,38 @@ class BBFP_PE_Array16x16 extends Module { pes(i)(j).io.in_d := io.in_d(j) } else { // Other rows: propagate from top PE through register - reg_d_v(i-1)(j) := pes(i-1)(j).io.out_d - pes(i)(j).io.in_d := reg_d_v(i-1)(j) + reg_d_v(i - 1)(j) := pes(i - 1)(j).io.out_d + pes(i)(j).io.in_d := reg_d_v(i - 1)(j) } // Partial sum input connection (vertical propagation) if (i == 0) { - // First row: input from external + // First row: input from external pes(i)(j).io.in_b := io.in_b(j) } else { - // Other rows: propagate from top PE through register - reg_b_v(i-1)(j) := pes(i-1)(j).io.out_b - pes(i)(j).io.in_b := reg_b_v(i-1)(j) + // Other rows: propagate from top PE through register + reg_b_v(i - 1)(j) := pes(i - 1)(j).io.out_b + pes(i)(j).io.in_b := reg_b_v(i - 1)(j) } // Control signal input connection (vertical propagation) if (i == 0) { - // First row: input from external + // First row: input from external pes(i)(j).io.in_control := io.in_control(j) - pes(i)(j).io.in_id := io.in_id(j) - pes(i)(j).io.in_last := io.in_last(j) + pes(i)(j).io.in_id := io.in_id(j) + pes(i)(j).io.in_last := io.in_last(j) pes(i)(j).io.in_valid := io.in_valid(j) } else { - // Other rows: propagate from top PE through register - reg_ctrl_v(i-1)(j) := pes(i-1)(j).io.out_control - reg_id_v(i-1)(j) := pes(i-1)(j).io.out_id - reg_last_v(i-1)(j) := pes(i-1)(j).io.out_last - reg_valid_v(i-1)(j):= pes(i-1)(j).io.out_valid - - pes(i)(j).io.in_control := reg_ctrl_v(i-1)(j) - pes(i)(j).io.in_id := reg_id_v(i-1)(j) - pes(i)(j).io.in_last := reg_last_v(i-1)(j) - pes(i)(j).io.in_valid := reg_valid_v(i-1)(j) + // Other rows: propagate from top PE through register + reg_ctrl_v(i - 1)(j) := pes(i - 1)(j).io.out_control + reg_id_v(i - 1)(j) := pes(i - 1)(j).io.out_id + reg_last_v(i - 1)(j) := pes(i - 1)(j).io.out_last + reg_valid_v(i - 1)(j) := pes(i - 1)(j).io.out_valid + + pes(i)(j).io.in_control := reg_ctrl_v(i - 1)(j) + pes(i)(j).io.in_id := reg_id_v(i - 1)(j) + pes(i)(j).io.in_last := reg_last_v(i - 1)(j) + pes(i)(j).io.in_valid := reg_valid_v(i - 1)(j) } } } @@ -393,17 +384,17 @@ class BBFP_PE_Array16x16 extends Module { // Bottom row output partial sum (all columns of row 15) for (j <- 0 until 16) { - out_b_reg(j) := pes(15)(j).io.out_b + out_b_reg(j) := pes(15)(j).io.out_b } // Right column output activation (row 15 of all rows) for (i <- 0 until 16) { - out_a_reg(i) := pes(i)(15).io.out_a + out_a_reg(i) := pes(i)(15).io.out_a } // Bottom row output weight (all columns of row 15) for (j <- 0 until 16) { - out_d_reg(j) := pes(15)(j).io.out_d + out_d_reg(j) := pes(15)(j).io.out_d } io.out_b := out_b_reg diff --git a/arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala b/arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala new file mode 100644 index 00000000..7a746003 --- /dev/null +++ b/arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala @@ -0,0 +1,62 @@ +package prototype.matrix.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object MatrixConfig { + implicit def rw: upickle.default.ReadWriter[MatrixConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): MatrixConfig = { + MatrixConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): MatrixConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[MatrixConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: MatrixConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class MatrixConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + // Derived parameters + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""MatrixConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/matrix/configs/default.json b/arch/src/main/scala/prototype/matrix/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/matrix/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala b/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala index 028444ef..b2a46402 100644 --- a/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala +++ b/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala @@ -2,148 +2,161 @@ package prototype.nagisa.matmul import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status - class PiDRAMmarcoBlackBox extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) // Control interface val start = Input(Bool()) - val done = Output(Bool()) + val done = Output(Bool()) // Data addresses - val op1_addr = Input(UInt(32.W)) - val op2_addr = Input(UInt(32.W)) + val op1_addr = Input(UInt(32.W)) + val op2_addr = Input(UInt(32.W)) val result_addr = Input(UInt(32.W)) // Computation parameters - val rows = Input(UInt(16.W)) - val cols = Input(UInt(16.W)) - val op_type = Input(UInt(4.W)) // 0: matmul, 1: add, 2: mul, etc. + val rows = Input(UInt(16.W)) + val cols = Input(UInt(16.W)) + val op_type = Input(UInt(4.W)) // 0: matmul, 1: add, 2: mul, etc. // Data width val data_width = Input(UInt(8.W)) }) - setInline("PiDRAMmarcoBlackBox.v", + setInline( + "PiDRAMmarcoBlackBox.v", s""" - |module PiDRAMmarcoBlackBox( - | input clock, - | input reset, - | input start, - | output reg done, - | input [31:0] op1_addr, - | input [31:0] op2_addr, - | input [31:0] result_addr, - | input [15:0] rows, - | input [15:0] cols, - | input [3:0] op_type, - | input [7:0] data_width - |); - | - | // State machine for marco computation - | reg [2:0] state; - | localparam IDLE = 3'b000; - | localparam LOAD = 3'b001; - | localparam COMPUTE = 3'b010; - | localparam STORE = 3'b011; - | localparam DONE = 3'b100; - | - | // Cycle counter for computation - | reg [31:0] cycle_count; - | reg [31:0] total_cycles; - | reg running; - | - | // Compute total cycles based on operation type and size - | always @(*) begin - | case(op_type) - | 4'b0000: // Matrix multiplication: rows * cols * cols - | total_cycles = rows * cols * cols; - | 4'b0001: // Element-wise addition: rows * cols - | total_cycles = rows * cols; - | 4'b0010: // Element-wise multiplication: rows * cols - | total_cycles = rows * cols; - | default: - | total_cycles = rows * cols; - | endcase - | end - | - | always @(posedge clock) begin - | if (reset) begin - | done <= 1'b0; - | state <= IDLE; - | cycle_count <= 32'b0; - | running <= 1'b0; - | end else begin - | case(state) - | IDLE: begin - | done <= 1'b0; - | cycle_count <= 32'b0; - | running <= 1'b0; - | if (start) begin - | state <= LOAD; - | running <= 1'b1; - | end - | end - | LOAD: begin - | // Load phase: simulate data loading from memory - | // In real marco, this would be handled by the memory controller - | state <= COMPUTE; - | end - | COMPUTE: begin - | // Compute phase: perform marco computation - | // This simulates the computation cycles in marco - | if (cycle_count >= total_cycles) begin - | state <= STORE; - | cycle_count <= 32'b0; - | end else begin - | cycle_count <= cycle_count + 1; - | end - | end - | STORE: begin - | // Store phase: write results back - | state <= DONE; - | end - | DONE: begin - | done <= 1'b1; - | running <= 1'b0; - | if (!start) begin - | state <= IDLE; - | end - | end - | default: begin - | state <= IDLE; - | end - | endcase - | end - | end - | - |endmodule - """.stripMargin) + |module PiDRAMmarcoBlackBox( + | input clock, + | input reset, + | input start, + | output reg done, + | input [31:0] op1_addr, + | input [31:0] op2_addr, + | input [31:0] result_addr, + | input [15:0] rows, + | input [15:0] cols, + | input [3:0] op_type, + | input [7:0] data_width + |); + | + | // State machine for marco computation + | reg [2:0] state; + | localparam IDLE = 3'b000; + | localparam LOAD = 3'b001; + | localparam COMPUTE = 3'b010; + | localparam STORE = 3'b011; + | localparam DONE = 3'b100; + | + | // Cycle counter for computation + | reg [31:0] cycle_count; + | reg [31:0] total_cycles; + | reg running; + | + | // Compute total cycles based on operation type and size + | always @(*) begin + | case(op_type) + | 4'b0000: // Matrix multiplication: rows * cols * cols + | total_cycles = rows * cols * cols; + | 4'b0001: // Element-wise addition: rows * cols + | total_cycles = rows * cols; + | 4'b0010: // Element-wise multiplication: rows * cols + | total_cycles = rows * cols; + | default: + | total_cycles = rows * cols; + | endcase + | end + | + | always @(posedge clock) begin + | if (reset) begin + | done <= 1'b0; + | state <= IDLE; + | cycle_count <= 32'b0; + | running <= 1'b0; + | end else begin + | case(state) + | IDLE: begin + | done <= 1'b0; + | cycle_count <= 32'b0; + | running <= 1'b0; + | if (start) begin + | state <= LOAD; + | running <= 1'b1; + | end + | end + | LOAD: begin + | // Load phase: simulate data loading from memory + | // In real marco, this would be handled by the memory controller + | state <= COMPUTE; + | end + | COMPUTE: begin + | // Compute phase: perform marco computation + | // This simulates the computation cycles in marco + | if (cycle_count >= total_cycles) begin + | state <= STORE; + | cycle_count <= 32'b0; + | end else begin + | cycle_count <= cycle_count + 1; + | end + | end + | STORE: begin + | // Store phase: write results back + | state <= DONE; + | end + | DONE: begin + | done <= 1'b1; + | running <= 1'b0; + | if (!start) begin + | state <= IDLE; + | end + | end + | default: begin + | state <= IDLE; + | end + | endcase + | end + | end + | + |endmodule + """.stripMargin + ) } - -class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +@instantiable +class marco(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val accWidth = 32 + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // Command interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val cmdResp = Decoupled(new BallRsComplete(parameter)) // Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + val sramRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) + val sramWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) - // Accumulator write interface (for partial sums in marco operations) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + // Accumulator write interface (unified bank now) + val accWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) // Status output val status = new Status @@ -151,29 +164,29 @@ class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // State machine val idle :: sLoadOp1 :: sLoadOp2 :: sCompute :: sWrite :: complete :: Nil = Enum(6) - val state = RegInit(idle) + val state = RegInit(idle) // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val op1_addr_reg = RegInit(0.U(10.W)) - val op1_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val op2_addr_reg = RegInit(0.U(10.W)) - val op2_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val robid_reg = RegInit(0.U(10.W)) + val op1_addr_reg = RegInit(0.U(10.W)) + val op1_bank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op2_addr_reg = RegInit(0.U(10.W)) + val op2_bank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) val result_addr_reg = RegInit(0.U(10.W)) - val result_bank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val result_bank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) // marco parameters from special field (40 bits total) // special[15:0] = rows (16 bits) // special[31:16] = cols (16 bits) // special[35:32] = op_type (4 bits): 0=matmul, 1=add, 2=mul - val rows_reg = RegInit(0.U(16.W)) - val cols_reg = RegInit(0.U(16.W)) + val rows_reg = RegInit(0.U(16.W)) + val cols_reg = RegInit(0.U(16.W)) val op_type_reg = RegInit(0.U(4.W)) // Counters - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) val computeCounter = RegInit(0.U(32.W)) // PiDRAM marco BlackBox instance @@ -182,72 +195,72 @@ class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { pidrammarco.io.reset := reset.asBool // Default SRAM assignments - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U + for (i <- 0 until parameter.numBanks) { + io.sramRead(i).req.valid := false.B + io.sramRead(i).req.bits.addr := 0.U io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B + io.sramRead(i).resp.ready := false.B - io.sramWrite(i).req.valid := false.B + io.sramWrite(i).req.valid := false.B io.sramWrite(i).req.bits.addr := 0.U io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // Default accumulator assignments - for (i <- 0 until b.acc_banks) { - io.accWrite(i).req.valid := false.B + for (i <- 0 until parameter.numBanks) { + io.accWrite(i).req.valid := false.B io.accWrite(i).req.bits.addr := 0.U io.accWrite(i).req.bits.data := 0.U - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(0.U(1.W))) + io.accWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // Command interface defaults - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // PiDRAM marco interface defaults - pidrammarco.io.start := false.B - pidrammarco.io.op1_addr := op1_addr_reg - pidrammarco.io.op2_addr := op2_addr_reg + pidrammarco.io.start := false.B + pidrammarco.io.op1_addr := op1_addr_reg + pidrammarco.io.op2_addr := op2_addr_reg pidrammarco.io.result_addr := result_addr_reg - pidrammarco.io.rows := rows_reg - pidrammarco.io.cols := cols_reg - pidrammarco.io.op_type := op_type_reg - pidrammarco.io.data_width := b.inputType.getWidth.U + pidrammarco.io.rows := rows_reg + pidrammarco.io.cols := cols_reg + pidrammarco.io.op_type := op_type_reg + pidrammarco.io.data_width := inputWidth.U // Status output - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sLoadOp1) || (state === sLoadOp2) - io.status.running := (state === sCompute) || (state === sWrite) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sLoadOp1) || (state === sLoadOp2) + io.status.running := (state === sCompute) || (state === sWrite) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := computeCounter + io.status.iter := computeCounter // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sLoadOp1 - readCounter := 0.U - writeCounter := 0.U + state := sLoadOp1 + readCounter := 0.U + writeCounter := 0.U computeCounter := 0.U - robid_reg := io.cmdReq.bits.rob_id - op1_addr_reg := io.cmdReq.bits.cmd.op1_bank_addr - op1_bank_reg := io.cmdReq.bits.cmd.op1_bank - op2_addr_reg := io.cmdReq.bits.cmd.op2_bank_addr - op2_bank_reg := io.cmdReq.bits.cmd.op2_bank - result_addr_reg := io.cmdReq.bits.cmd.wr_bank_addr + robid_reg := io.cmdReq.bits.rob_id + op1_addr_reg := 0.U // New ISA: all operations start from row 0 + op1_bank_reg := io.cmdReq.bits.cmd.op1_bank + op2_addr_reg := 0.U // New ISA: all operations start from row 0 + op2_bank_reg := io.cmdReq.bits.cmd.op2_bank + result_addr_reg := 0.U // New ISA: all operations start from row 0 result_bank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter + iter_reg := io.cmdReq.bits.cmd.iter // Extract marco parameters from special field (40 bits) // special[15:0] = rows, special[31:16] = cols, special[35:32] = op_type - rows_reg := io.cmdReq.bits.cmd.special(15, 0) - cols_reg := io.cmdReq.bits.cmd.special(31, 16) + rows_reg := io.cmdReq.bits.cmd.special(15, 0) + cols_reg := io.cmdReq.bits.cmd.special(31, 16) op_type_reg := io.cmdReq.bits.cmd.special(35, 32) } } @@ -255,16 +268,16 @@ class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sLoadOp1) { // Load operand 1 (simplified: load one tile) when(readCounter < iter_reg) { - io.sramRead(op1_bank_reg).req.valid := true.B - io.sramRead(op1_bank_reg).req.bits.addr := op1_addr_reg + readCounter + io.sramRead(op1_bank_reg).req.valid := true.B + io.sramRead(op1_bank_reg).req.bits.addr := op1_addr_reg + readCounter io.sramRead(op1_bank_reg).req.bits.fromDMA := false.B when(io.sramRead(op1_bank_reg).resp.valid) { io.sramRead(op1_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U + readCounter := readCounter + 1.U } }.otherwise { - state := sLoadOp2 + state := sLoadOp2 readCounter := 0.U } } @@ -272,17 +285,17 @@ class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sLoadOp2) { // Load operand 2 (simplified: load one tile) when(readCounter < iter_reg) { - io.sramRead(op2_bank_reg).req.valid := true.B - io.sramRead(op2_bank_reg).req.bits.addr := op2_addr_reg + readCounter + io.sramRead(op2_bank_reg).req.valid := true.B + io.sramRead(op2_bank_reg).req.bits.addr := op2_addr_reg + readCounter io.sramRead(op2_bank_reg).req.bits.fromDMA := false.B when(io.sramRead(op2_bank_reg).resp.valid) { io.sramRead(op2_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U + readCounter := readCounter + 1.U } }.otherwise { - state := sCompute - readCounter := 0.U + state := sCompute + readCounter := 0.U pidrammarco.io.start := true.B } } @@ -290,7 +303,7 @@ class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sCompute) { // Wait for PiDRAM marco to complete when(pidrammarco.io.done) { - state := sWrite + state := sWrite writeCounter := 0.U }.otherwise { computeCounter := computeCounter + 1.U @@ -300,11 +313,11 @@ class marco(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sWrite) { // Write result (simplified: write one tile) when(writeCounter < iter_reg) { - io.sramWrite(result_bank_reg).req.valid := true.B + io.sramWrite(result_bank_reg).req.valid := true.B io.sramWrite(result_bank_reg).req.bits.addr := result_addr_reg + writeCounter // Simplified: write zeros as placeholder (actual output would come from PiDRAM marco) io.sramWrite(result_bank_reg).req.bits.data := 0.U - io.sramWrite(result_bank_reg).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(1.U(1.W))) + io.sramWrite(result_bank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(1.U(1.W))) when(io.sramWrite(result_bank_reg).req.ready) { writeCounter := writeCounter + 1.U diff --git a/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala b/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala index 597d8daa..e89ec1a4 100644 --- a/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala +++ b/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala @@ -2,9 +2,10 @@ package prototype.nagisa.matmul import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.nagisa.matmul.marco /** @@ -12,42 +13,37 @@ import prototype.nagisa.matmul.marco * Behavior: Read operands from Scratchpad, perform marco computation (inspired by PiDRAM), * then write results back to Scratchpad. */ -class marcoMatmulBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) +@instantiable +class marcoMatmulBall(parameter: BallDomainParam, id: Int)(implicit p: Parameters) extends Module with BallRegist { + @public + val io = IO(new Blink(parameter, parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate marco computation unit - private val marcoUnit = Module(new marco) + private val marcoUnit: Instance[marco] = Instantiate(new marco(parameter)) // Connect command interface marcoUnit.io.cmdReq <> io.cmdReq marcoUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - marcoUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - marcoUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Connect Accumulator write interface (for partial sums in marco operations) - for (i <- 0 until b.acc_banks) { - marcoUnit.io.accWrite(i) <> io.accWrite(i).io - io.accWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (not used, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + marcoUnit.io.sramRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + + marcoUnit.io.sramWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // marcoMatmulBall uses overwrite mode for scratchpad + + // Accumulator write (for partial sums) - use accumulate mode + // Note: marco may need to write to accumulator banks with accumulate mode + // For now, assuming all writes use overwrite mode, but accumulator writes should use accumulate + // This needs to be determined based on marco unit's actual behavior } // Pass through status signals diff --git a/arch/src/main/scala/prototype/nnlut/NNLut.scala b/arch/src/main/scala/prototype/nnlut/NNLut.scala index 85dc872d..c0f88bca 100644 --- a/arch/src/main/scala/prototype/nnlut/NNLut.scala +++ b/arch/src/main/scala/prototype/nnlut/NNLut.scala @@ -2,27 +2,37 @@ package prototype.nnlut import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status +import prototype.nnlut.configs.NNLutConfig /** * NNLut - Neural Network Look-Up Table unit * Simple implementation: read data from scratchpad, lookup in LUT, write back */ -class NNLut(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +@instantiable +class NNLut(val parameter: NNLutConfig)(implicit p: Parameters) extends Module with SerializableModule[NNLutConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) - // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + // Connect to unified bank read/write interface + val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + val bankWrite = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) // Status output val status = new Status @@ -30,122 +40,123 @@ class NNLut(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // State definitions val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) + val state = RegInit(idle) - // Store a veclane x veclane tile + // Store a InputNum x InputNum tile val regArray = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) )) ) // Counters - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) // Instruction registers val robid_reg = RegInit(0.U(10.W)) val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) val cycle_reg = RegInit(0.U(6.W)) - val iterCnt = RegInit(0.U(32.W)) + val iterCnt = RegInit(0.U(32.W)) // Precompute write data - val writeDataReg = Reg(UInt(spad_w.W)) - val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) // Simple LUT: 256 entries for 8-bit input // This is a simple example LUT, can be replaced with actual NN-LUT values val LUT_SIZE = 256 + val lut = VecInit(Seq.tabulate(LUT_SIZE) { i => // Simple example: identity function with saturation // In real NN-LUT, this would contain pre-computed activation function values - val input = i.asSInt + val input = i.asSInt val output = Mux(input < -128.S, -128.S, Mux(input > 127.S, 127.S, input)) output.asUInt }) // SRAM default assignment - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := false.B + + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U + state := sRead + readCounter := 0.U + respCounter := 0.U writeCounter := 0.U robid_reg := io.cmdReq.bits.rob_id - waddr_reg := io.cmdReq.bits.cmd.wr_bank_addr + waddr_reg := 0.U // New ISA: all operations start from row 0 wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr + raddr_reg := 0.U // New ISA: all operations start from row 0 rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (b.veclane.U - 1.U)) / b.veclane.U - 1.U + iter_reg := io.cmdReq.bits.cmd.iter + cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U } when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U + state := sRead + readCounter := 0.U writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + b.veclane.U - raddr_reg := raddr_reg + b.veclane.U - cycle_reg := cycle_reg - 1.U + respCounter := 0.U + waddr_reg := waddr_reg + InputNum.U + raddr_reg := raddr_reg + InputNum.U + cycle_reg := cycle_reg - 1.U } } is(sRead) { - when(readCounter < b.veclane.U) { + when(readCounter < InputNum.U) { // Issue read request - readCounter := readCounter + 1.U - io.sramRead(rbank_reg).req.valid := true.B - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + readCounter + readCounter := readCounter + 1.U + io.bankRead(rbank_reg).req.valid := true.B + io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter } // Receive response and perform LUT lookup - io.sramRead(rbank_reg).resp.ready := true.B - when(io.sramRead(rbank_reg).resp.fire) { - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth - val raw = io.sramRead(rbank_reg).resp.bits.data(hi, lo) + io.bankRead(rbank_reg).resp.ready := true.B + when(io.bankRead(rbank_reg).resp.fire) { + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + val raw = io.bankRead(rbank_reg).resp.bits.data(hi, lo) // Perform LUT lookup // Convert signed value to unsigned index (0-255) // Take lower 8 bits as unsigned index for LUT - val idx = raw(7, 0) // Use lower 8 bits as unsigned index + val idx = raw(7, 0) // Use lower 8 bits as unsigned index regArray(respCounter)(col) := lut(idx) } respCounter := respCounter + 1.U } - when(respCounter === b.veclane.U) { - state := sWrite + when(respCounter === InputNum.U) { + state := sWrite // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(0)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) // Set write mask (write all) - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } } @@ -153,23 +164,23 @@ class NNLut(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { is(sWrite) { // Write back results - io.sramWrite(wbank_reg).req.valid := writeCounter < b.veclane.U - io.sramWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.sramWrite(wbank_reg).req.bits.data := writeDataReg - io.sramWrite(wbank_reg).req.bits.mask := writeMaskReg + io.bankWrite(wbank_reg).req.valid := writeCounter < InputNum.U + io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter + io.bankWrite(wbank_reg).req.bits.data := writeDataReg + io.bankWrite(wbank_reg).req.bits.mask := writeMaskReg - when(writeCounter === (b.veclane - 1).U) { + when(writeCounter === (InputNum - 1).U) { state := complete }.otherwise { writeCounter := writeCounter + 1.U // Prepare next row's write data - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(writeCounter + 1.U)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) } } is(complete) { when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B + io.cmdResp.valid := true.B io.cmdResp.bits.rob_id := robid_reg when(io.cmdResp.fire) { iterCnt := iterCnt + 1.U @@ -180,22 +191,22 @@ class NNLut(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { } // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < b.veclane.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === b.veclane.U)) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sRead) && (respCounter < InputNum.U) + io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt when(reset.asBool) { - for (i <- 0 until b.veclane) { - for (j <- 0 until b.veclane) { + for (i <- 0 until InputNum) { + for (j <- 0 until InputNum) { regArray(i)(j) := 0.U } } writeDataReg := 0.U - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 0.U } } diff --git a/arch/src/main/scala/prototype/nnlut/NNLutBall.scala b/arch/src/main/scala/prototype/nnlut/NNLutBall.scala index 21fce564..1372d5c1 100644 --- a/arch/src/main/scala/prototype/nnlut/NNLutBall.scala +++ b/arch/src/main/scala/prototype/nnlut/NNLutBall.scala @@ -2,52 +2,44 @@ package prototype.nnlut import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.nnlut.NNLut +import prototype.nnlut.configs.NNLutConfig /** * NNLutBall - A Neural Network Look-Up Table computation Ball that complies with the Blink protocol. * Behavior: Read data from Scratchpad, perform LUT lookup, then write back to Scratchpad. */ -class NNLutBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class NNLutBall(config: NNLutConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate NNLut computation unit - private val nnlutUnit = Module(new NNLut) + private val nnlutUnit: Instance[NNLut] = Instantiate(new NNLut(config)) // Connect command interface nnlutUnit.io.cmdReq <> io.cmdReq nnlutUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - nnlutUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - nnlutUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (NN-LUT does not access accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + nnlutUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U - // Accumulator write interface (NN-LUT does not write accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + nnlutUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // NNLutBall uses overwrite mode } // Pass through status signals diff --git a/arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala b/arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala new file mode 100644 index 00000000..e1f74ee8 --- /dev/null +++ b/arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala @@ -0,0 +1,61 @@ +package prototype.nnlut.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object NNLutConfig { + implicit def rw: upickle.default.ReadWriter[NNLutConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): NNLutConfig = { + NNLutConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): NNLutConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[NNLutConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: NNLutConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class NNLutConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""NNLutConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/nnlut/configs/default.json b/arch/src/main/scala/prototype/nnlut/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/nnlut/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/relu/Relu.scala b/arch/src/main/scala/prototype/relu/Relu.scala index 4cbbbce1..a183c7e6 100644 --- a/arch/src/main/scala/prototype/relu/Relu.scala +++ b/arch/src/main/scala/prototype/relu/Relu.scala @@ -3,29 +3,40 @@ package prototype.relu import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status - -class PipelinedRelu[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) - extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +import prototype.relu.configs.ReluConfig + +@instantiable +class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) + extends Module + with SerializableModule[ReluConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) - - // Connect to Scratchpad SRAM read/write interface - val sramRead = - Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec( - b.sp_banks, - Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len)) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) + + // Connect to unified bank read/write interface + val bankRead = + Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + + val bankWrite = Vec( + ballParam.numBanks, + Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen)) ) // Status output @@ -33,115 +44,115 @@ class PipelinedRelu[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) }) val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) + val state = RegInit(idle) - // Store a row of split elements (veclane elements) - // Store a veclane x veclane tile (perform element-wise ReLU then write back) + // Store a row of split elements (InputNum elements) + // Store a InputNum x InputNum tile (perform element-wise ReLU then write back) val regArray = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) )) ) // Counters - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) // Instruction registers val robid_reg = RegInit(0.U(10.W)) val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) val cycle_reg = RegInit(0.U(6.W)) // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) + val iterCnt = RegInit(0.U(32.W)) // Precompute write data - val writeDataReg = Reg(UInt(spad_w.W)) - val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) // SRAM default assignment - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := false.B + + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(ballParam.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U + state := sRead + readCounter := 0.U + respCounter := 0.U writeCounter := 0.U robid_reg := io.cmdReq.bits.rob_id - // For ReLU, output write-back should use decoded wr_bank/addr, not op2_* fields - waddr_reg := io.cmdReq.bits.cmd.wr_bank_addr + // For ReLU, output write-back should use decoded wr_bank/addr, not op2_* fields + waddr_reg := 0.U // New ISA: all operations start from row 0 wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr + raddr_reg := 0.U // New ISA: all operations start from row 0 rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (b.veclane.U - 1.U)) / b.veclane.U - 1.U + iter_reg := io.cmdReq.bits.cmd.iter + cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U } when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U + state := sRead + readCounter := 0.U writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + b.veclane.U - raddr_reg := raddr_reg + b.veclane.U - cycle_reg := cycle_reg - 1.U + respCounter := 0.U + waddr_reg := waddr_reg + InputNum.U + raddr_reg := raddr_reg + InputNum.U + cycle_reg := cycle_reg - 1.U } } is(sRead) { - when(readCounter < b.veclane.U) { - // Issue read request - readCounter := readCounter + 1.U - io.sramRead(rbank_reg).req.valid := true.B - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + readCounter + when(readCounter < InputNum.U) { + // Issue read request + readCounter := readCounter + 1.U + io.bankRead(rbank_reg).req.valid := true.B + io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - } + } // Receive response, only raise ready when there are outstanding reads - val dataWord = io.sramRead(rbank_reg).resp.bits.data + val dataWord = io.bankRead(rbank_reg).resp.bits.data // val hasOutstandingRead = readCounter =/= respCounter - io.sramRead(rbank_reg).resp.ready := true.B - when(io.sramRead(rbank_reg).resp.fire) { - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth - val raw = dataWord(hi, lo) + io.bankRead(rbank_reg).resp.ready := true.B + when(io.bankRead(rbank_reg).resp.fire) { + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + val raw = dataWord(hi, lo) val signed = raw.asSInt - val relu = Mux(signed < 0.S, 0.S(b.inputType.getWidth.W), signed) + val relu = Mux(signed < 0.S, 0.S(inputWidth.W), signed) regArray(respCounter)(col) := relu.asUInt } respCounter := respCounter + 1.U } - when(respCounter === b.veclane.U) { - state := sWrite + when(respCounter === InputNum.U) { + state := sWrite // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(0)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) // Set write mask (write all) - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } } @@ -149,25 +160,25 @@ class PipelinedRelu[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) is(sWrite) { // Correctly use ready/valid handshake to advance writes, avoid dropped writes - io.sramWrite(wbank_reg).req.valid := writeCounter < b.veclane.U - io.sramWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.sramWrite(wbank_reg).req.bits.data := writeDataReg - io.sramWrite(wbank_reg).req.bits.mask := writeMaskReg + io.bankWrite(wbank_reg).req.valid := writeCounter < InputNum.U + io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter + io.bankWrite(wbank_reg).req.bits.data := writeDataReg + io.bankWrite(wbank_reg).req.bits.mask := writeMaskReg - when(writeCounter === (b.veclane - 1).U) { + when(writeCounter === (InputNum - 1).U) { state := complete }.otherwise { writeCounter := writeCounter + 1.U // Prepare next row's write data - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(writeCounter + 1.U)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) } } is(complete) { when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := robid_reg when(io.cmdResp.fire) { iterCnt := iterCnt + 1.U } @@ -177,22 +188,22 @@ class PipelinedRelu[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) } // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < b.veclane.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === b.veclane.U)) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sRead) && (respCounter < InputNum.U) + io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt when(reset.asBool) { - for (i <- 0 until b.veclane) { - for (j <- 0 until b.veclane) { + for (i <- 0 until InputNum) { + for (j <- 0 until InputNum) { regArray(i)(j) := 0.U } } writeDataReg := 0.U - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until parameter.bankMaskLen) { writeMaskReg(i) := 0.U } } diff --git a/arch/src/main/scala/prototype/relu/ReluBall.scala b/arch/src/main/scala/prototype/relu/ReluBall.scala index 1084b297..2d352b1b 100644 --- a/arch/src/main/scala/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/prototype/relu/ReluBall.scala @@ -2,52 +2,44 @@ package prototype.relu import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.relu.PipelinedRelu - -/** ReluBall - A ReLU computation Ball that complies with the Blink protocol. - * Behavior: Read data from Scratchpad, perform element-wise ReLU (set negative values to 0), - * then write back to Scratchpad. - */ -class ReluBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) - val ballId = id.U +import prototype.relu.configs.ReluConfig + +/** + * ReluBall - A ReLU computation Ball that complies with the Blink protocol. + * Behavior: Read data from Scratchpad, perform element-wise ReLU (set negative values to 0), + * then write back to Scratchpad. + */ +@instantiable +class ReluBall(config: ReluConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate PipelinedRelu computation unit - private val reluUnit = Module(new PipelinedRelu[UInt]) + private val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(config)) // Connect command interface reluUnit.io.cmdReq <> io.cmdReq reluUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - reluUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - reluUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (ReLU does not access accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } - - // Accumulator write interface (ReLU does not write accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + reluUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + reluUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // ReluBall uses overwrite mode } // Pass through status signals diff --git a/arch/src/main/scala/prototype/relu/configs/ReluConfig.scala b/arch/src/main/scala/prototype/relu/configs/ReluConfig.scala new file mode 100644 index 00000000..a09a1e12 --- /dev/null +++ b/arch/src/main/scala/prototype/relu/configs/ReluConfig.scala @@ -0,0 +1,62 @@ +package prototype.relu.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object ReluConfig { + implicit def rw: upickle.default.ReadWriter[ReluConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): ReluConfig = { + ReluConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): ReluConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[ReluConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: ReluConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class ReluConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + // Derived parameters + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""ReluConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/relu/configs/default.json b/arch/src/main/scala/prototype/relu/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/relu/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/transfer/Transfer.scala b/arch/src/main/scala/prototype/transfer/Transfer.scala index 9cc5871a..8e07d35b 100644 --- a/arch/src/main/scala/prototype/transfer/Transfer.scala +++ b/arch/src/main/scala/prototype/transfer/Transfer.scala @@ -3,29 +3,40 @@ package prototype.transfer import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status - -class Transfer[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) - extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +import prototype.transfer.configs.TransferConfig + +@instantiable +class Transfer(val parameter: TransferConfig)(implicit p: Parameters) + extends Module + with SerializableModule[TransferConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) - - // Connect to Scratchpad SRAM read/write interface - val sramRead = - Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec( - b.sp_banks, - Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len)) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) + + // Connect to unified bank read/write interface + val bankRead = + Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + + val bankWrite = Vec( + ballParam.numBanks, + Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen)) ) // Status output @@ -33,111 +44,111 @@ class Transfer[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) }) val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) + val state = RegInit(idle) - // Store a row of split elements (veclane elements) + // Store a row of split elements (InputNum elements) val regArray = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) + VecInit(Seq.fill(InputNum)( + VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) )) ) // Counters - val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) // Instruction registers val robid_reg = RegInit(0.U(10.W)) val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) + val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) val cycle_reg = RegInit(0.U(6.W)) // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) + val iterCnt = RegInit(0.U(32.W)) // Precompute write data - val writeDataReg = Reg(UInt(spad_w.W)) - val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) // SRAM default assignment - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := false.B + + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(ballParam.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robid_reg // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U + state := sRead + readCounter := 0.U + respCounter := 0.U writeCounter := 0.U robid_reg := io.cmdReq.bits.rob_id - waddr_reg := io.cmdReq.bits.cmd.wr_bank_addr + waddr_reg := 0.U // New ISA: all operations start from row 0 wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr + raddr_reg := 0.U // New ISA: all operations start from row 0 rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (b.veclane.U - 1.U)) / b.veclane.U - 1.U + iter_reg := io.cmdReq.bits.cmd.iter + cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U } when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U + state := sRead + readCounter := 0.U writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + b.veclane.U - raddr_reg := raddr_reg + b.veclane.U - cycle_reg := cycle_reg - 1.U + respCounter := 0.U + waddr_reg := waddr_reg + InputNum.U + raddr_reg := raddr_reg + InputNum.U + cycle_reg := cycle_reg - 1.U } } is(sRead) { - when(readCounter < b.veclane.U) { - // Issue read request - readCounter := readCounter + 1.U - io.sramRead(rbank_reg).req.valid := true.B - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + readCounter + when(readCounter < InputNum.U) { + // Issue read request + readCounter := readCounter + 1.U + io.bankRead(rbank_reg).req.valid := true.B + io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - } + } // Receive response, only raise ready when there are outstanding reads - val dataWord = io.sramRead(rbank_reg).resp.bits.data + val dataWord = io.bankRead(rbank_reg).resp.bits.data // val hasOutstandingRead = readCounter =/= respCounter - io.sramRead(rbank_reg).resp.ready := true.B - when(io.sramRead(rbank_reg).resp.fire) { - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth + io.bankRead(rbank_reg).resp.ready := true.B + when(io.bankRead(rbank_reg).resp.fire) { + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth val raw = dataWord(hi, lo) regArray(respCounter)(col) := raw.asUInt } respCounter := respCounter + 1.U } - when(respCounter === b.veclane.U) { - state := sWrite + when(respCounter === InputNum.U) { + state := sWrite // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(0)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) // Set write mask (write all) - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until ballParam.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } } @@ -145,25 +156,25 @@ class Transfer[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) is(sWrite) { // Correctly use ready/valid handshake to advance writes, avoid dropped writes - io.sramWrite(wbank_reg).req.valid := writeCounter < b.veclane.U - io.sramWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.sramWrite(wbank_reg).req.bits.data := writeDataReg - io.sramWrite(wbank_reg).req.bits.mask := writeMaskReg + io.bankWrite(wbank_reg).req.valid := writeCounter < InputNum.U + io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter + io.bankWrite(wbank_reg).req.bits.data := writeDataReg + io.bankWrite(wbank_reg).req.bits.mask := writeMaskReg - when(writeCounter === (b.veclane - 1).U) { + when(writeCounter === (InputNum - 1).U) { state := complete }.otherwise { writeCounter := writeCounter + 1.U // Prepare next row's write data - writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(writeCounter + 1.U)(j))) + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) } } is(complete) { when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := robid_reg when(io.cmdResp.fire) { iterCnt := iterCnt + 1.U } @@ -173,22 +184,22 @@ class Transfer[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) } // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < b.veclane.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === b.veclane.U)) + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := (state === idle) + io.status.init := (state === sRead) && (respCounter < InputNum.U) + io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt when(reset.asBool) { - for (i <- 0 until b.veclane) { - for (j <- 0 until b.veclane) { + for (i <- 0 until InputNum) { + for (j <- 0 until InputNum) { regArray(i)(j) := 0.U } } writeDataReg := 0.U - for (i <- 0 until b.spad_mask_len) { + for (i <- 0 until ballParam.bankMaskLen) { writeMaskReg(i) := 0.U } } diff --git a/arch/src/main/scala/prototype/transfer/TransferBall.scala b/arch/src/main/scala/prototype/transfer/TransferBall.scala index 75ea7cd2..6f7c6fa6 100644 --- a/arch/src/main/scala/prototype/transfer/TransferBall.scala +++ b/arch/src/main/scala/prototype/transfer/TransferBall.scala @@ -2,51 +2,42 @@ package prototype.transfer import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.transfer.Transfer +import prototype.transfer.configs.TransferConfig // TransferBall - A data transfer Ball that complies with the Blink protocol. // Behavior: Read data from Scratchpad and write it back without modification. -class TransferBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module - with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class TransferBall(config: TransferConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U // Satisfy BallRegist requirements def Blink: Blink = io // Instantiate Transfer computation unit - private val transferUnit = Module(new Transfer[UInt]) + private val transferUnit: Instance[Transfer] = Instantiate(new Transfer(config)) // Connect command interface transferUnit.io.cmdReq <> io.cmdReq transferUnit.io.cmdResp <> io.cmdResp - // Connect Scratchpad SRAM read/write interface - for (i <- 0 until b.sp_banks) { - transferUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - transferUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Accumulator read interface (Transfer does not access accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } - - // Accumulator write interface (Transfer does not write accumulator, tie-off) - for (i <- 0 until b.acc_banks) { - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + // Connect Bank read/write interface + for (i <- 0 until parameter.numBanks) { + transferUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + transferUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // TransferBall uses overwrite mode } // Pass through status signals diff --git a/arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala b/arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala new file mode 100644 index 00000000..425a2f4d --- /dev/null +++ b/arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala @@ -0,0 +1,62 @@ +package prototype.transfer.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object TransferConfig { + implicit def rw: upickle.default.ReadWriter[TransferConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): TransferConfig = { + TransferConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): TransferConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[TransferConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: TransferConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class TransferConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + // Derived parameters + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""TransferConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/transfer/configs/default.json b/arch/src/main/scala/prototype/transfer/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/transfer/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/transpose/Transpose.scala b/arch/src/main/scala/prototype/transpose/Transpose.scala index c84e51e1..0582f336 100644 --- a/arch/src/main/scala/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/prototype/transpose/Transpose.scala @@ -3,148 +3,164 @@ package prototype.transpose import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status -import freechips.rocketchip.tilelink.MemoryOpCategories.wr -import os.read - -class PipelinedTransposer[T <: Data](implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +import prototype.transpose.configs.TransposeConfig + +@instantiable +class PipelinedTransposer(val parameter: TransposeConfig)(implicit p: Parameters) + extends Module + with SerializableModule[TransposeConfig] { + // Get parameters from config + val ballParam = parameter.ballParam + val InputNum = parameter.InputNum + val inputWidth = parameter.inputWidth + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) + val cmdResp = Decoupled(new BallRsComplete(ballParam)) - // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) + // Connect to unified bank read/write interface + val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + val bankWrite = + Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) // Status output val status = new Status }) val idle :: compute :: Nil = Enum(2) - val state = RegInit(idle) + val state = RegInit(idle) - // Matrix storage register (veclane x veclane) - val regArray = Reg(Vec(b.veclane * 2, Vec(b.veclane, UInt(b.inputType.getWidth.W)))) + // Matrix storage register (InputNum x InputNum) + val regArray = Reg(Vec(InputNum * 2, Vec(InputNum, UInt(inputWidth.W)))) // Counters - val readCounter = RegInit(0.U(10.W)) - val respCounter = RegInit(0.U(10.W)) - val writeCounter = RegInit(0.U(10.W)) + val readCounter = RegInit(0.U(10.W)) + val respCounter = RegInit(0.U(10.W)) + val writeCounter = RegInit(0.U(10.W)) val respWaitcounter = RegInit(0.U(10.W)) - val writeHeadptr = RegInit(0.U(10.W)) - val writeTailptr = RegInit(0.U(10.W)) + val writeHeadptr = RegInit(0.U(10.W)) + val writeTailptr = RegInit(0.U(10.W)) // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) - val iter_reg = RegInit(0.U(10.W)) + val robid_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(10.W)) + val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val raddr_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val iter_reg = RegInit(0.U(10.W)) val write_iter_reg = RegInit(0.U(10.W)) - val mode_reg = RegInit(0.U(1.W)) - + val mode_reg = RegInit(0.U(1.W)) // Precompute write data - val writeDataReg = Reg(UInt(spad_w.W)) - val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) val start_write = RegInit(false.B) // SRAM default assignment - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(0.U(1.W))) + for (i <- 0 until ballParam.numBanks) { + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).req.bits.fromDMA := false.B + io.bankRead(i).resp.ready := false.B + + io.bankWrite(i).req.valid := false.B + io.bankWrite(i).req.bits.addr := 0.U + io.bankWrite(i).req.bits.data := 0.U + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment - io.cmdReq.ready := state === idle + io.cmdReq.ready := state === idle - when(state === idle && io.cmdReq.fire){ - state := compute - readCounter := 0.U - respCounter := 0.U + when(state === idle && io.cmdReq.fire) { + state := compute + readCounter := 0.U + respCounter := 0.U respWaitcounter := io.cmdReq.bits.cmd.iter + respWaitcounter robid_reg := io.cmdReq.bits.rob_id - waddr_reg := io.cmdReq.bits.cmd.op2_bank_addr + waddr_reg := 0.U // New ISA: all operations start from row 0 wbank_reg := io.cmdReq.bits.cmd.op2_bank - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr + raddr_reg := 0.U // New ISA: all operations start from row 0 rbank_reg := io.cmdReq.bits.cmd.op1_bank iter_reg := io.cmdReq.bits.cmd.iter mode_reg := io.cmdReq.bits.cmd.special(0) } // read req - when(((mode_reg === 1.U) &&(state === compute) && RegNext(io.sramWrite(0).req.ready))|| - ((mode_reg === 0.U) && (state === compute))){ - readCounter := readCounter + 1.U - io.sramRead(rbank_reg).req.valid := readCounter < iter_reg - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) + when(((mode_reg === 1.U) && (state === compute) && RegNext(io.bankWrite(0).req.ready)) || + ((mode_reg === 0.U) && (state === compute))) { + readCounter := readCounter + 1.U + io.bankRead(rbank_reg).req.valid := readCounter < iter_reg + io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter + state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) } io.cmdResp.valid := (readCounter >= (iter_reg - 1.U)) && (state === compute) io.cmdResp.bits.rob_id := robid_reg // read resp - io.sramRead(rbank_reg).resp.ready := true.B - val dataWord = io.sramRead(rbank_reg).resp.bits.data - val row = respCounter(4,0) - when(io.sramRead(rbank_reg).resp.fire && respWaitcounter > 0.U){ - for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth + io.bankRead(rbank_reg).resp.ready := true.B + val dataWord = io.bankRead(rbank_reg).resp.bits.data + val row = respCounter(4, 0) + when(io.bankRead(rbank_reg).resp.fire && respWaitcounter > 0.U) { + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth regArray(row)(col) := dataWord(hi, lo) } respCounter := Mux(respCounter === iter_reg - 1.U, 0.U, respCounter + 1.U) - writeHeadptr := Mux(writeHeadptr === 2.U* b.veclane.U - 1.U, 0.U, writeHeadptr + 1.U) - respWaitcounter := Mux(state === idle && io.cmdReq.fire, io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, respWaitcounter - 1.U) + writeHeadptr := Mux(writeHeadptr === 2.U * InputNum.U - 1.U, 0.U, writeHeadptr + 1.U) + respWaitcounter := Mux( + state === idle && io.cmdReq.fire, + io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, + respWaitcounter - 1.U + ) } // write req - val wreg = RegInit(0.U(10.W)) - val array_full = ((writeTailptr < b.veclane.U) && (writeHeadptr >= b.veclane.U)) || - ((writeTailptr >= b.veclane.U) && (writeHeadptr < b.veclane.U)) - when(writeCounter === iter_reg - 1.U){ + val wreg = RegInit(0.U(10.W)) + val array_full = ((writeTailptr < InputNum.U) && (writeHeadptr >= InputNum.U)) || + ((writeTailptr >= InputNum.U) && (writeHeadptr < InputNum.U)) + when(writeCounter === iter_reg - 1.U) { start_write := false.B - }.elsewhen( array_full && !start_write){ - start_write := true.B - wreg := waddr_reg + }.elsewhen(array_full && !start_write) { + start_write := true.B + wreg := waddr_reg write_iter_reg := iter_reg - }.otherwise{ + }.otherwise { start_write := start_write } - when(start_write){ - io.sramWrite(wbank_reg).req.valid := true.B - io.sramWrite(wbank_reg).req.bits.addr := wreg + writeCounter - io.sramWrite(wbank_reg).req.bits.data := Mux( writeCounter(4) === 0.U, Cat((0 until b.veclane).reverse.map(i => regArray(i)(writeCounter(3,0)))) , - Cat((0 until b.veclane).reverse.map(i => regArray(i + b.veclane)(writeCounter(3,0))))) - io.sramWrite(wbank_reg).req.bits.mask := VecInit(Seq.fill(b.spad_mask_len)(~0.U(1.W))) - writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U,writeCounter + 1.U) - writeTailptr := Mux(writeTailptr === 2.U* b.veclane.U - 1.U, 0.U, writeTailptr + 1.U) + when(start_write) { + io.bankWrite(wbank_reg).req.valid := true.B + io.bankWrite(wbank_reg).req.bits.addr := wreg + writeCounter + io.bankWrite(wbank_reg).req.bits.data := Mux( + writeCounter(4) === 0.U, + Cat((0 until InputNum).reverse.map(i => regArray(i)(writeCounter(3, 0)))), + Cat((0 until InputNum).reverse.map(i => regArray(i + InputNum)(writeCounter(3, 0)))) + ) + io.bankWrite(wbank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(~0.U(1.W))) + writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U, writeCounter + 1.U) + writeTailptr := Mux(writeTailptr === 2.U * InputNum.U - 1.U, 0.U, writeTailptr + 1.U) } - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := state === idle - io.status.init := readCounter === 0.U && state === compute - io.status.running := state === compute - io.status.iter := readCounter + // Status signals + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := state === idle + io.status.init := readCounter === 0.U && state === compute + io.status.running := state === compute + io.status.iter := readCounter io.status.complete := io.cmdResp.valid } diff --git a/arch/src/main/scala/prototype/transpose/TransposeBall.scala b/arch/src/main/scala/prototype/transpose/TransposeBall.scala index a970ee8b..910a42fa 100644 --- a/arch/src/main/scala/prototype/transpose/TransposeBall.scala +++ b/arch/src/main/scala/prototype/transpose/TransposeBall.scala @@ -2,54 +2,42 @@ package prototype.transpose import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.transpose.PipelinedTransposer +import prototype.transpose.configs.TransposeConfig /** * TransposeBall - A transpose computation Ball that complies with the Blink protocol */ -class TransposeBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class TransposeBall(config: TransposeConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U def Blink: Blink = io // Instantiate PipelinedTransposer - val transposeUnit = Module(new PipelinedTransposer) + val transposeUnit: Instance[PipelinedTransposer] = Instantiate(new PipelinedTransposer(config)) // Connect command interface transposeUnit.io.cmdReq <> io.cmdReq transposeUnit.io.cmdResp <> io.cmdResp - // Connect SRAM read interface - Transpose needs to read data from scratchpad - for (i <- 0 until b.sp_banks) { - transposeUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - } - - // Connect SRAM write interface - Transpose needs to write to scratchpad - for (i <- 0 until b.sp_banks) { - transposeUnit.io.sramWrite(i) <> io.sramWrite(i).io - io.sramWrite(i).rob_id := io.cmdReq.bits.rob_id - } - - // Handle Accumulator read interface - Transpose does not read accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramReadIO), we need to drive req.valid, req.bits (outputs) and resp.ready (output) - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } + // Connect Bank interface + for (i <- 0 until parameter.numBanks) { + transposeUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U - // Handle Accumulator write interface - Transpose does not write accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramWriteIO), we need to drive req.valid and req.bits (outputs) - io.accWrite(i).io.req.valid := false.B - io.accWrite(i).io.req.bits := DontCare - io.accWrite(i).rob_id := 0.U + transposeUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := false.B // TransposeBall uses overwrite mode } // Connect Status signals - directly obtained from internal unit diff --git a/arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala b/arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala new file mode 100644 index 00000000..8ac2d4cf --- /dev/null +++ b/arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala @@ -0,0 +1,62 @@ +package prototype.transpose.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object TransposeConfig { + implicit def rw: upickle.default.ReadWriter[TransposeConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): TransposeConfig = { + TransposeConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): TransposeConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[TransposeConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: TransposeConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class TransposeConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + // Derived parameters + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""TransposeConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/transpose/configs/default.json b/arch/src/main/scala/prototype/transpose/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/transpose/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/vector/VecBall.scala b/arch/src/main/scala/prototype/vector/VecBall.scala index f44cd915..8a5b92cc 100644 --- a/arch/src/main/scala/prototype/vector/VecBall.scala +++ b/arch/src/main/scala/prototype/vector/VecBall.scala @@ -2,54 +2,43 @@ package prototype.vector import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.balldomain.blink.{Blink, BallRegist} +import examples.toy.balldomain.BallDomainParam +import framework.balldomain.blink.{BallRegist, Blink} import prototype.vector.VecUnit +import prototype.vector.configs.VecConfig /** * VecBall - A vector computation Ball that complies with the Blink protocol */ -class VecBall(id: Int)(implicit b: CustomBuckyballConfig, p: Parameters) extends Module with BallRegist { - val io = IO(new Blink) - val ballId = id.U +@instantiable +class VecBall(config: VecConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { + val parameter = config.ballParam + @public + val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) + val ballId = id.U def Blink: Blink = io // Instantiate VecUnit - val vecUnit = Module(new VecUnit) + val vecUnit: Instance[VecUnit] = Instantiate(new VecUnit(parameter)) // Connect command interface vecUnit.io.cmdReq <> io.cmdReq vecUnit.io.cmdResp <> io.cmdResp - // Connect SRAM read interface - VecUnit needs to read data from scratchpad - for (i <- 0 until b.sp_banks) { - vecUnit.io.sramRead(i) <> io.sramRead(i).io - io.sramRead(i).rob_id := io.cmdReq.bits.rob_id - } - - // Handle SRAM write interface - VecUnit does not write to scratchpad, so tie off - for (i <- 0 until b.sp_banks) { - // For Flipped(SramWriteIO), we need to drive req.valid and req.bits (outputs) - io.sramWrite(i).io.req.valid := false.B - io.sramWrite(i).io.req.bits := DontCare - io.sramWrite(i).rob_id := 0.U - } - - // Handle Accumulator read interface - VecUnit does not read accumulator, so tie off - for (i <- 0 until b.acc_banks) { - // For Flipped(SramReadIO), we need to drive req.valid, req.bits (outputs) and resp.ready (output) - io.accRead(i).io.req.valid := false.B - io.accRead(i).io.req.bits := DontCare - io.accRead(i).io.resp.ready := true.B - io.accRead(i).rob_id := 0.U - } - - // Connect Accumulator write interface - VecUnit writes results to accumulator - for (i <- 0 until b.acc_banks) { - vecUnit.io.accWrite(i) <> io.accWrite(i).io - io.accWrite(i).rob_id := io.cmdReq.bits.rob_id + // Connect Bank interface + for (i <- 0 until parameter.numBanks) { + vecUnit.io.bankRead(i) <> io.bankRead(i).io + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + io.bankRead(i).bank_id := i.U + + // VecUnit uses bankWrite for writes (accumulate mode) + vecUnit.io.bankWrite(i) <> io.bankWrite(i).io + io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + io.bankWrite(i).bank_id := i.U + io.bankWrite(i).io.req.bits.wmode := true.B // VecBall uses accumulate mode for writes } // Connect Status signals - directly obtained from internal unit diff --git a/arch/src/main/scala/prototype/vector/VecCtrlUnit.scala b/arch/src/main/scala/prototype/vector/VecCtrlUnit.scala index a8d59fb4..afa37edf 100644 --- a/arch/src/main/scala/prototype/vector/VecCtrlUnit.scala +++ b/arch/src/main/scala/prototype/vector/VecCtrlUnit.scala @@ -3,39 +3,45 @@ package prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam -class VecCtrlUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new Bundle{ - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp_o = Decoupled(new BallRsComplete) +@instantiable +class VecCtrlUnit(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { - val ctrl_ld_o = Decoupled(new ctrl_ld_req) - val ctrl_st_o = Decoupled(new ctrl_st_req) + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val cmdResp_o = Decoupled(new BallRsComplete(parameter)) + + val ctrl_ld_o = Decoupled(new ctrl_ld_req(parameter)) + val ctrl_st_o = Decoupled(new ctrl_st_req(parameter)) val ctrl_ex_o = Decoupled(new ctrl_ex_req) - val cmdResp_i = Flipped(Valid(new Bundle {val commit = Bool()})) // from store unit + val cmdResp_i = Flipped(Valid(new Bundle { val commit = Bool() })) // from store unit }) - val rob_id_reg = RegInit(0.U(log2Up(b.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(parameter.rob_entries).W)) val iter = RegInit(0.U(10.W)) - val op1_bank = RegInit(0.U(2.W)) - val op1_bank_addr = RegInit(0.U(12.W)) - val op2_bank_addr = RegInit(0.U(12.W)) - val op2_bank = RegInit(0.U(2.W)) - val wr_bank = RegInit(0.U(2.W)) - val wr_bank_addr = RegInit(0.U(12.W)) - val is_acc = RegInit(false.B) + val op1_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val op2_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val wr_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val wr_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val is_acc = RegInit(false.B) // Deprecated: use wmode instead val has_send = RegInit(false.B) val mode = RegInit(0.U(1.W)) val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) + val state = RegInit(idle) // ----------------------------------------------------------------------------- // Set registers when EX instruction arrives @@ -45,15 +51,15 @@ class VecCtrlUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Modu iter := io.cmdReq.bits.cmd.iter rob_id_reg := io.cmdReq.bits.rob_id op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := io.cmdReq.bits.cmd.op1_bank_addr + op1_bank_addr := 0.U // New ISA: all operations start from row 0 op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := io.cmdReq.bits.cmd.op2_bank_addr + op2_bank_addr := 0.U // New ISA: all operations start from row 0 wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := io.cmdReq.bits.cmd.wr_bank_addr - is_acc := io.cmdReq.bits.cmd.is_acc + wr_bank_addr := 0.U // New ISA: all operations start from row 0 + is_acc := false.B // Deprecated: use wmode instead mode := io.cmdReq.bits.cmd.special(0) - state := busy + state := busy } // ----------------------------------------------------------------------------- @@ -61,39 +67,39 @@ class VecCtrlUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Modu // ----------------------------------------------------------------------------- when(state === busy && !has_send) { - io.ctrl_ld_o.valid := true.B - io.ctrl_ld_o.bits.op1_bank := op1_bank - io.ctrl_ld_o.bits.op1_bank_addr := op1_bank_addr - io.ctrl_ld_o.bits.op2_bank := op2_bank - io.ctrl_ld_o.bits.op2_bank_addr := op2_bank_addr - io.ctrl_ld_o.bits.iter := iter - io.ctrl_ld_o.bits.mode := mode - - io.ctrl_ex_o.valid := true.B - io.ctrl_ex_o.bits.iter := iter - - io.ctrl_st_o.valid := true.B - io.ctrl_st_o.bits.wr_bank := wr_bank - io.ctrl_st_o.bits.wr_bank_addr := wr_bank_addr - io.ctrl_st_o.bits.iter := iter - - has_send := true.B + io.ctrl_ld_o.valid := true.B + io.ctrl_ld_o.bits.op1_bank := op1_bank + io.ctrl_ld_o.bits.op1_bank_addr := op1_bank_addr + io.ctrl_ld_o.bits.op2_bank := op2_bank + io.ctrl_ld_o.bits.op2_bank_addr := op2_bank_addr + io.ctrl_ld_o.bits.iter := iter + io.ctrl_ld_o.bits.mode := mode + + io.ctrl_ex_o.valid := true.B + io.ctrl_ex_o.bits.iter := iter + + io.ctrl_st_o.valid := true.B + io.ctrl_st_o.bits.wr_bank := wr_bank + io.ctrl_st_o.bits.wr_bank_addr := wr_bank_addr + io.ctrl_st_o.bits.iter := iter + + has_send := true.B }.otherwise { - io.ctrl_ld_o.valid := false.B - io.ctrl_ld_o.bits.op1_bank := 0.U - io.ctrl_ld_o.bits.op1_bank_addr := 0.U - io.ctrl_ld_o.bits.op2_bank := 0.U - io.ctrl_ld_o.bits.op2_bank_addr := 0.U - io.ctrl_ld_o.bits.iter := 0.U - io.ctrl_ld_o.bits.mode := 0.U - - io.ctrl_ex_o.valid := false.B - io.ctrl_ex_o.bits.iter := 0.U - - io.ctrl_st_o.valid := false.B - io.ctrl_st_o.bits.wr_bank := 0.U - io.ctrl_st_o.bits.wr_bank_addr := 0.U - io.ctrl_st_o.bits.iter := 0.U + io.ctrl_ld_o.valid := false.B + io.ctrl_ld_o.bits.op1_bank := 0.U + io.ctrl_ld_o.bits.op1_bank_addr := 0.U + io.ctrl_ld_o.bits.op2_bank := 0.U + io.ctrl_ld_o.bits.op2_bank_addr := 0.U + io.ctrl_ld_o.bits.iter := 0.U + io.ctrl_ld_o.bits.mode := 0.U + + io.ctrl_ex_o.valid := false.B + io.ctrl_ex_o.bits.iter := 0.U + + io.ctrl_st_o.valid := false.B + io.ctrl_st_o.bits.wr_bank := 0.U + io.ctrl_st_o.bits.wr_bank_addr := 0.U + io.ctrl_st_o.bits.iter := 0.U } // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/prototype/vector/VecEXUnit.scala b/arch/src/main/scala/prototype/vector/VecEXUnit.scala index 9605304a..d5c2f85f 100644 --- a/arch/src/main/scala/prototype/vector/VecEXUnit.scala +++ b/arch/src/main/scala/prototype/vector/VecEXUnit.scala @@ -3,50 +3,62 @@ package prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadResp} -import examples.BuckyballConfigs.CustomBuckyballConfig -import warp.VecBall +import examples.toy.balldomain.BallDomainParam +import prototype.vector.warp.VecBall - -class ctrl_ex_req(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { +class ctrl_ex_req extends Bundle { val iter = UInt(10.W) } -class ld_ex_req(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val op1 = Vec(b.veclane, UInt(b.inputType.getWidth.W)) - val op2 = Vec(b.veclane, UInt(b.inputType.getWidth.W)) - val iter = UInt(10.W) +class ld_ex_req(parameter: BallDomainParam) extends Bundle { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val op1 = Vec(InputNum, UInt(inputWidth.W)) + val op2 = Vec(InputNum, UInt(inputWidth.W)) + val iter = UInt(10.W) } -class VecEXUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class VecEXUnit(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val accWidth = 32 + + @public val io = IO(new Bundle { val ctrl_ex_i = Flipped(Decoupled(new ctrl_ex_req)) - val ld_ex_i = Flipped(Decoupled(new ld_ex_req)) + val ld_ex_i = Flipped(Decoupled(new ld_ex_req(parameter))) - val ex_st_o = Decoupled(new ex_st_req) + val ex_st_o = Decoupled(new ex_st_req(parameter)) }) val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) + val state = RegInit(idle) - val VecBall = Module(new VecBall) + val VecBall = Module(new VecBall()(p)) // Initialize default values for all signals - io.ctrl_ex_i.ready := false.B - io.ex_st_o.valid := false.B - io.ex_st_o.bits.rst := VecInit(Seq.fill(b.veclane)(0.U(b.accType.getWidth.W))) - io.ex_st_o.bits.iter := 0.U + io.ctrl_ex_i.ready := false.B + io.ex_st_o.valid := false.B + io.ex_st_o.bits.rst := VecInit(Seq.fill(InputNum)(0.U(accWidth.W))) + io.ex_st_o.bits.iter := 0.U // Initialize VecBall input signals with default values VecBall.io.iterIn.valid := false.B - VecBall.io.iterIn.bits := 0.U - VecBall.io.op1In.valid := false.B - VecBall.io.op1In.bits := VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) - VecBall.io.op2In.valid := false.B - VecBall.io.op2In.bits := VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) + VecBall.io.iterIn.bits := 0.U + VecBall.io.op1In.valid := false.B + VecBall.io.op1In.bits := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + VecBall.io.op2In.valid := false.B + VecBall.io.op2In.bits := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) VecBall.io.rstOut.ready := false.B // ----------------------------------------------------------------------------- @@ -54,33 +66,33 @@ class VecEXUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module // ----------------------------------------------------------------------------- io.ctrl_ex_i.ready := state === idle when(io.ctrl_ex_i.fire) { - VecBall.io.iterIn.valid := true.B - VecBall.io.iterIn.bits := io.ctrl_ex_i.bits.iter - state := busy + VecBall.io.iterIn.valid := true.B + VecBall.io.iterIn.bits := io.ctrl_ex_i.bits.iter + state := busy } // ----------------------------------------------------------------------------- // Accept read results from load unit and perform computation // ----------------------------------------------------------------------------- - io.ld_ex_i.ready := state === busy && VecBall.io.iterIn.ready - when(io.ld_ex_i.valid) { - VecBall.io.op1In.valid := true.B - VecBall.io.op1In.bits := io.ld_ex_i.bits.op1 - VecBall.io.op2In.valid := true.B - VecBall.io.op2In.bits := io.ld_ex_i.bits.op2 - //assert((io.ld_ex_i.bits.iter - VecBall.get_iterCounter() === 16.U) && VecBall.get_arrive(), - //"[VecLoad -> VecEX] iteration mismatch") - } + io.ld_ex_i.ready := state === busy && VecBall.io.iterIn.ready + when(io.ld_ex_i.valid) { + VecBall.io.op1In.valid := true.B + VecBall.io.op1In.bits := io.ld_ex_i.bits.op1 + VecBall.io.op2In.valid := true.B + VecBall.io.op2In.bits := io.ld_ex_i.bits.op2 + //assert((io.ld_ex_i.bits.iter - VecBall.get_iterCounter() === 16.U) && VecBall.get_arrive(), + //"[VecLoad -> VecEX] iteration mismatch") + } // ----------------------------------------------------------------------------- // Send computation results to store unit for write-back // ----------------------------------------------------------------------------- - io.ex_st_o.valid := VecBall.io.rstOut.valid - VecBall.io.rstOut.ready := io.ex_st_o.ready + io.ex_st_o.valid := VecBall.io.rstOut.valid + VecBall.io.rstOut.ready := io.ex_st_o.ready - when(io.ex_st_o.fire) { - io.ex_st_o.bits.rst := VecBall.io.rstOut.bits - io.ex_st_o.bits.iter := VecBall.io.iterOut.bits - } + when(io.ex_st_o.fire) { + io.ex_st_o.bits.rst := VecBall.io.rstOut.bits + io.ex_st_o.bits.iter := VecBall.io.iterOut.bits + } } diff --git a/arch/src/main/scala/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/prototype/vector/VecLoadUnit.scala index d90b9809..0240119a 100644 --- a/arch/src/main/scala/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/prototype/vector/VecLoadUnit.scala @@ -3,147 +3,153 @@ package prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO, SramReadReq, SramReadResp} -import examples.BuckyballConfigs.CustomBuckyballConfig - - -class ctrl_ld_req(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val op1_bank = UInt(log2Up(b.sp_banks).W) - val op1_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - val op2_bank = UInt(log2Up(b.sp_banks).W) - val op2_bank_addr = UInt(log2Up(b.spad_bank_entries).W) +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp} +import examples.toy.balldomain.BallDomainParam + +class ctrl_ld_req(parameter: BallDomainParam) extends Bundle { + val op1_bank = UInt(log2Up(parameter.numBanks).W) + val op1_bank_addr = UInt(log2Up(parameter.bankEntries).W) + val op2_bank = UInt(log2Up(parameter.numBanks).W) + val op2_bank_addr = UInt(log2Up(parameter.bankEntries).W) val iter = UInt(10.W) val mode = UInt(1.W) } -class VecLoadUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val rob_id_width = log2Up(b.rob_entries) +@instantiable +class VecLoadUnit(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val inputWidth = 8 + val bankWidth = parameter.bankWidth + val rob_id_width = log2Up(parameter.rob_entries) + + @public val io = IO(new Bundle { - val sramReadReq = Vec(b.sp_banks, Decoupled(new SramReadReq(b.spad_bank_entries))) - val sramReadResp = Vec(b.sp_banks, Flipped(Decoupled(new SramReadResp(b.spad_w)))) - val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req)) - val ld_ex_o = Decoupled(new ld_ex_req) + val bankReadReq = Vec(parameter.numBanks, Decoupled(new SramReadReq(parameter.bankEntries))) + val bankReadResp = Vec(parameter.numBanks, Flipped(Decoupled(new SramReadResp(bankWidth)))) + val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req(parameter))) + val ld_ex_o = Decoupled(new ld_ex_req(parameter)) }) - val op1_bank = RegInit(0.U(log2Up(b.sp_banks).W)) - val op2_bank = RegInit(0.U(log2Up(b.sp_banks).W)) - val op1_addr = RegInit(0.U(log2Up(b.spad_bank_entries).W)) - val op2_addr = RegInit(0.U(log2Up(b.spad_bank_entries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) - val mode = RegInit(0.U(1.W)) - - val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) - - // Output register to break combinational logic loop - val ld_ex_valid_reg = RegInit(false.B) - val ld_ex_op1_reg = Reg(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - val ld_ex_op2_reg = Reg(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - val ld_ex_iter_reg = RegInit(0.U(10.W)) - - // Default assignment for each bank read request - for (i <- 0 until b.sp_banks){ - io.sramReadReq(i).valid := false.B - io.sramReadReq(i).bits.fromDMA := false.B - io.sramReadReq(i).bits.addr := 0.U + val op1_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op2_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op1_addr = RegInit(0.U(log2Up(parameter.bankEntries).W)) + val op2_addr = RegInit(0.U(log2Up(parameter.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) + val mode = RegInit(0.U(1.W)) + + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) + + // Output register to break combinational logic loop + val ld_ex_valid_reg = RegInit(false.B) + val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) + val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) + val ld_ex_iter_reg = RegInit(0.U(10.W)) + + // Default assignment for each bank read request + for (i <- 0 until parameter.numBanks) { + io.bankReadReq(i).valid := false.B + io.bankReadReq(i).bits.fromDMA := false.B + io.bankReadReq(i).bits.addr := 0.U } - io.ctrl_ld_i.ready := state === idle + io.ctrl_ld_i.ready := state === idle // ----------------------------------------------------------------------------- // Set registers when Ctrl instruction arrives // ----------------------------------------------------------------------------- - when (io.ctrl_ld_i.fire) { - op1_bank := io.ctrl_ld_i.bits.op1_bank - op2_bank := io.ctrl_ld_i.bits.op2_bank - op1_addr := io.ctrl_ld_i.bits.op1_bank_addr - op2_addr := io.ctrl_ld_i.bits.op2_bank_addr - iter := io.ctrl_ld_i.bits.iter - iter_counter := 0.U - state := busy - mode := io.ctrl_ld_i.bits.mode - assert(io.ctrl_ld_i.bits.iter > 0.U, "iter should be greater than 0") + when(io.ctrl_ld_i.fire) { + op1_bank := io.ctrl_ld_i.bits.op1_bank + op2_bank := io.ctrl_ld_i.bits.op2_bank + op1_addr := io.ctrl_ld_i.bits.op1_bank_addr + op2_addr := io.ctrl_ld_i.bits.op2_bank_addr + iter := io.ctrl_ld_i.bits.iter + iter_counter := 0.U + state := busy + mode := io.ctrl_ld_i.bits.mode + assert(io.ctrl_ld_i.bits.iter > 0.U, "iter should be greater than 0") + } + io.bankReadResp.foreach { resp => + resp.ready := state === busy } - io.sramReadResp.foreach { resp => - resp.ready := state === busy - } - when(mode === 0.U){ + when(mode === 0.U) { // ----------------------------------------------------------------------------- // Send SRAM read request (only when output register is idle) // ----------------------------------------------------------------------------- - when (state === busy && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - io.sramReadReq(op1_bank).valid := iter_counter < iter - io.sramReadReq(op1_bank).bits.fromDMA := false.B - io.sramReadReq(op1_bank).bits.addr := op1_addr + iter_counter - - io.sramReadReq(op2_bank).valid := iter_counter < iter - io.sramReadReq(op2_bank).bits.fromDMA := false.B - io.sramReadReq(op2_bank).bits.addr := op2_addr + iter_counter - iter_counter := iter_counter + 1.U - } + when(state === busy && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { + io.bankReadReq(op1_bank).valid := iter_counter < iter + io.bankReadReq(op1_bank).bits.fromDMA := false.B + io.bankReadReq(op1_bank).bits.addr := op1_addr + iter_counter + + io.bankReadReq(op2_bank).valid := iter_counter < iter + io.bankReadReq(op2_bank).bits.fromDMA := false.B + io.bankReadReq(op2_bank).bits.addr := op2_addr + iter_counter + iter_counter := iter_counter + 1.U + } // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit (use register to break combinational logic loop) // ----------------------------------------------------------------------------- - // ready signal for sramReadResp: can receive when there's no pending data or downstream has received - /* - io.sramReadResp.foreach { resp => - resp.ready := !ld_ex_valid_reg || io.ld_ex_o.ready - } -*/ - // Receive SRAM data and cache to register - when (io.sramReadResp(op1_bank).valid && io.sramReadResp(op2_bank).valid && - (!ld_ex_valid_reg || io.ld_ex_o.ready) && (state === busy)) { - ld_ex_valid_reg := true.B - ld_ex_op1_reg := io.sramReadResp(op1_bank).bits.data.asTypeOf(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - ld_ex_op2_reg := io.sramReadResp(op2_bank).bits.data.asTypeOf(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - ld_ex_iter_reg := iter_counter - }.elsewhen(io.ld_ex_o.ready) { - ld_ex_valid_reg := false.B - } - - // Output comes from register - io.ld_ex_o.valid := ld_ex_valid_reg - io.ld_ex_o.bits.op1 := ld_ex_op1_reg - io.ld_ex_o.bits.op2 := ld_ex_op2_reg - io.ld_ex_o.bits.iter := ld_ex_iter_reg + // ready signal for bankReadResp: can receive when there's no pending data or downstream has received + /* io.bankReadResp.foreach { resp => resp.ready := !ld_ex_valid_reg || io.ld_ex_o.ready } */ + // Receive SRAM data and cache to register + when(io.bankReadResp(op1_bank).valid && io.bankReadResp(op2_bank).valid && + (!ld_ex_valid_reg || io.ld_ex_o.ready) && (state === busy)) { + ld_ex_valid_reg := true.B + ld_ex_op1_reg := io.bankReadResp(op1_bank).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_op2_reg := io.bankReadResp(op2_bank).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_iter_reg := iter_counter + }.elsewhen(io.ld_ex_o.ready) { + ld_ex_valid_reg := false.B + } + + // Output comes from register + io.ld_ex_o.valid := ld_ex_valid_reg + io.ld_ex_o.bits.op1 := ld_ex_op1_reg + io.ld_ex_o.bits.op2 := ld_ex_op2_reg + io.ld_ex_o.bits.iter := ld_ex_iter_reg // ----------------------------------------------------------------------------- // Reset iter_counter and return to idle state // ----------------------------------------------------------------------------- - when(state === busy && iter_counter === iter && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - state := idle - iter_counter := 0.U - } - }.otherwise{ - // Default assignment - io.ld_ex_o.valid := false.B - io.ld_ex_o.bits.op1 := VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) - io.ld_ex_o.bits.op2 := VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) - io.ld_ex_o.bits.iter := 0.U - when (state === busy && io.sramReadResp(0).valid){ - iter_counter := iter_counter + 1.U - ld_ex_op1_reg := io.sramReadResp(0).bits.data.asTypeOf(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - io.sramReadReq(1).valid := true.B - io.sramReadReq(1).bits.addr := op2_addr + iter_counter - io.sramReadReq(1).bits.fromDMA := false.B - } - when(state === busy && io.sramReadResp(1).valid && RegNext(io.sramReadResp(0).valid)){ - io.ld_ex_o.valid := true.B - io.ld_ex_o.bits.op1 := ld_ex_op1_reg - io.ld_ex_o.bits.op2 := io.sramReadResp(1).bits.data.asTypeOf(Vec(b.veclane, UInt(b.inputType.getWidth.W))) - io.ld_ex_o.bits.iter := iter_counter - 1.U - } - when(state === busy && iter_counter === iter ){ - state := idle - iter_counter := 0.U - } - } + when(state === busy && iter_counter === iter && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { + state := idle + iter_counter := 0.U + } + }.otherwise { + // Default assignment + io.ld_ex_o.valid := false.B + io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + io.ld_ex_o.bits.iter := 0.U + when(state === busy && io.bankReadResp(0).valid) { + iter_counter := iter_counter + 1.U + ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.bankReadReq(1).valid := true.B + io.bankReadReq(1).bits.addr := op2_addr + iter_counter + io.bankReadReq(1).bits.fromDMA := false.B + } + when(state === busy && io.bankReadResp(1).valid && RegNext(io.bankReadResp(0).valid)) { + io.ld_ex_o.valid := true.B + io.ld_ex_o.bits.op1 := ld_ex_op1_reg + io.ld_ex_o.bits.op2 := io.bankReadResp(1).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.ld_ex_o.bits.iter := iter_counter - 1.U + } + when(state === busy && iter_counter === iter) { + state := idle + iter_counter := 0.U + } + } } diff --git a/arch/src/main/scala/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/prototype/vector/VecStoreUnit.scala index 74f203e8..485fd989 100644 --- a/arch/src/main/scala/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/prototype/vector/VecStoreUnit.scala @@ -3,44 +3,56 @@ package prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.SramWriteIO +import examples.toy.balldomain.BallDomainParam - -class ctrl_st_req(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - val wr_bank = UInt(log2Up(b.sp_banks).W) - val wr_bank_addr = UInt(log2Up(b.spad_bank_entries).W) - val iter = UInt(10.W) +class ctrl_st_req(parameter: BallDomainParam) extends Bundle { + val wr_bank = UInt(log2Up(parameter.numBanks).W) + val wr_bank_addr = UInt(log2Up(parameter.bankEntries).W) + val iter = UInt(10.W) } -class ex_st_req(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { +class ex_st_req(parameter: BallDomainParam) extends Bundle { + // Derived parameters + val InputNum = 16 + val accWidth = 32 // Use accumulator type, 32 bits - val rst = Vec(b.veclane, UInt(b.accType.getWidth.W)) - val iter = UInt(10.W) + val rst = Vec(InputNum, UInt(accWidth.W)) + val iter = UInt(10.W) } -class VecStoreUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { +@instantiable +class VecStoreUnit(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters + val InputNum = 16 + val accWidth = 32 + + @public val io = IO(new Bundle { - val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req)) - val ex_st_i = Flipped(Decoupled(new ex_st_req)) + val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req(parameter))) + val ex_st_i = Flipped(Decoupled(new ex_st_req(parameter))) - // val sramWrite = Vec(b.sp_banks, new SramWriteIO(b.sp_bank_entries, spad_w, spad_w/8)) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + // Unified bank write interface (writes use accumulate mode) + val bankWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) - val cmdResp_o = Valid(new Bundle {val commit = Bool()}) + val cmdResp_o = Valid(new Bundle { val commit = Bool() }) }) - // val wr_bank = RegInit(0.U(log2Up(b.sp_banks).W)) - val wr_bank_addr = RegInit(0.U(log2Up(b.spad_bank_entries).W)) - val iter = RegInit(0.U(10.W)) + val wr_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val wr_bank_addr = RegInit(0.U(log2Up(parameter.bankEntries).W)) + val iter = RegInit(0.U(10.W)) val iter_counter = RegInit(0.U(10.W)) - val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) + val state = RegInit(idle) // ----------------------------------------------------------------------------- // Set registers when Ctrl instruction arrives @@ -48,79 +60,72 @@ class VecStoreUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Mod io.ctrl_st_i.ready := state === idle when(io.ctrl_st_i.fire) { - // wr_bank := io.ctrl_st_i.bits.wr_bank - wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr - iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) - iter_counter := 0.U - state := busy + wr_bank := io.ctrl_st_i.bits.wr_bank + wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr + iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) + iter_counter := 0.U + state := busy } // ----------------------------------------------------------------------------- // Accept computation results from EX unit and perform write-back // ----------------------------------------------------------------------------- - io.ex_st_i.ready := state === busy - // for(i <- 0 until b.sp_banks) { - // io.sramWrite(i).en := false.B - // io.sramWrite(i).addr := 0.U - // io.sramWrite(i).data := 0.U - // io.sramWrite(i).mask := VecInit(Seq.fill(spad_w / 8)(false.B)) - // } -io.accWrite.foreach { acc => - acc.req.valid := false.B - acc.req.bits.addr := 0.U - acc.req.bits.data := Cat(Seq.fill(b.acc_w / 8)(0.U(8.W))) - acc.req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(false.B)) - } -val waddr = wr_bank_addr + iter_counter(log2Ceil(b.veclane) - 1, 0) - when(io.ex_st_i.fire) { - for(i <- 0 until b.acc_banks/2) { - when(waddr(0) === 0.U){ - io.accWrite(i).req.valid := true.B - io.accWrite(i).req.bits.addr := wr_bank_addr + (iter_counter(log2Ceil(b.veclane) - 1, 0) >> 1.U) - - // Each accumulator bank stores veclane/acc_banks elements - // 16/4 = 4 elements - val elementsPerBank = b.veclane / b.acc_banks * 2 - val startIdx = i * elementsPerBank - val endIdx = startIdx + elementsPerBank - 1 + io.ex_st_i.ready := state === busy + io.bankWrite.foreach { acc => + acc.req.valid := false.B + acc.req.bits.addr := 0.U + acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) + acc.req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(false.B)) + } + val waddr = wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + when(io.ex_st_i.fire) { + for (i <- 0 until parameter.numBanks / 2) { + when(waddr(0) === 0.U) { + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := wr_bank_addr + (iter_counter(log2Ceil(InputNum) - 1, 0) >> 1.U) + + // Each accumulator bank stores InputNum/numBanks elements + val elementsPerBank = InputNum / parameter.numBanks * 2 + val startIdx = i * elementsPerBank + val endIdx = startIdx + elementsPerBank - 1 // Pack corresponding elements into a UInt val bankData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - io.accWrite(i).req.bits.data := bankData + io.bankWrite(i).req.bits.data := bankData - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) - }.otherwise{ - io.accWrite(i + b.acc_banks/2).req.valid := true.B - io.accWrite(i + b.acc_banks/2).req.bits.addr := wr_bank_addr + (iter_counter(log2Ceil(b.veclane) - 1, 0) >> 1.U) + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + }.otherwise { + io.bankWrite(i + parameter.numBanks / 2).req.valid := true.B + io.bankWrite(i + parameter.numBanks / 2).req.bits.addr := wr_bank_addr + (iter_counter( + log2Ceil(InputNum) - 1, + 0 + ) >> 1.U) - // Each accumulator bank stores veclane/acc_banks elements - // 16/4 = 4 elements - val elementsPerBank = b.veclane / b.acc_banks * 2 - val startIdx = i * elementsPerBank - val endIdx = startIdx + elementsPerBank - 1 + // Each accumulator bank stores InputNum/numBanks elements + val elementsPerBank = InputNum / parameter.numBanks * 2 + val startIdx = i * elementsPerBank + val endIdx = startIdx + elementsPerBank - 1 // Pack corresponding elements into a UInt val bankData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - io.accWrite(i + b.acc_banks/2).req.bits.data := bankData + io.bankWrite(i + parameter.numBanks / 2).req.bits.data := bankData - io.accWrite(i + b.acc_banks/2).req.bits.mask := VecInit(Seq.fill(b.acc_mask_len)(true.B)) + io.bankWrite(i + parameter.numBanks / 2).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) } } iter_counter := iter_counter + 1.U - } + } // ----------------------------------------------------------------------------- // Reset iter counter, commit cmdResp, return to idle state // ----------------------------------------------------------------------------- - when(state === busy && iter_counter >= iter) { - state := idle - io.cmdResp_o.valid := true.B - io.cmdResp_o.bits.commit := true.B - }.otherwise { - io.cmdResp_o.valid := false.B - io.cmdResp_o.bits.commit := false.B + when(state === busy && iter_counter >= iter) { + state := idle + io.cmdResp_o.valid := true.B + io.cmdResp_o.bits.commit := true.B + }.otherwise { + io.cmdResp_o.valid := false.B + io.cmdResp_o.bits.commit := false.B } - - } diff --git a/arch/src/main/scala/prototype/vector/VecUnit.scala b/arch/src/main/scala/prototype/vector/VecUnit.scala index 460ac337..05f81f77 100644 --- a/arch/src/main/scala/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/prototype/vector/VecUnit.scala @@ -1,29 +1,38 @@ package prototype.vector + import chisel3._ import chisel3.util._ import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import prototype.vector._ -import framework.memdomain.mem.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsIssue, BallRsComplete} -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status - -class VecUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spad_w = b.veclane * b.inputType.getWidth - +@instantiable +class VecUnit(val parameter: BallDomainParam)(implicit p: Parameters) + extends Module + with SerializableModule[BallDomainParam] { + // Derived parameters - using default values for compatibility + val InputNum = 16 // Default value, should be derived from parameter if needed + val inputWidth = 8 // UInt8 + val accWidth = 32 // UInt32 + val bankWidth = parameter.bankWidth + + @public val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) + val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) + val cmdResp = Decoupled(new BallRsComplete(parameter)) - // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - // val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) - // Connect to Accumulator read/write interface - // val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(b.acc_bank_entries, b.acc_w))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(b.acc_bank_entries, b.acc_w, b.acc_mask_len))) + // Connect to unified bank read/write interface + val bankRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) + // Connect to unified bank write interface + val bankWrite = + Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) // Status output val status = new Status @@ -32,39 +41,37 @@ class VecUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // ----------------------------------------------------------------------------- // VECCTRLUNIT // ----------------------------------------------------------------------------- - val VecCtrlUnit = Module(new VecCtrlUnit) + val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(parameter)) VecCtrlUnit.io.cmdReq <> io.cmdReq io.cmdResp <> VecCtrlUnit.io.cmdResp_o // ----------------------------------------------------------------------------- // VECLOADUNIT // ----------------------------------------------------------------------------- - val VecLoadUnit = Module(new VecLoadUnit) - VecLoadUnit.io.ctrl_ld_i <> VecCtrlUnit.io.ctrl_ld_o - for (i <- 0 until b.sp_banks) { - io.sramRead(i).req <> VecLoadUnit.io.sramReadReq(i) - VecLoadUnit.io.sramReadResp(i) <> io.sramRead(i).resp - } + val VecLoadUnit: Instance[VecLoadUnit] = Instantiate(new VecLoadUnit(parameter)) + VecLoadUnit.io.ctrl_ld_i <> VecCtrlUnit.io.ctrl_ld_o + for (i <- 0 until parameter.numBanks) { + io.bankRead(i).req <> VecLoadUnit.io.bankReadReq(i) + VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).resp + } // ----------------------------------------------------------------------------- // VECEX // ----------------------------------------------------------------------------- - val VecEX = Module(new VecEXUnit) - VecEX.io.ctrl_ex_i <> VecCtrlUnit.io.ctrl_ex_o - VecEX.io.ld_ex_i <> VecLoadUnit.io.ld_ex_o - + val VecEX: Instance[VecEXUnit] = Instantiate(new VecEXUnit(parameter)) + VecEX.io.ctrl_ex_i <> VecCtrlUnit.io.ctrl_ex_o + VecEX.io.ld_ex_i <> VecLoadUnit.io.ld_ex_o // ----------------------------------------------------------------------------- // VECSTOREUNIT // ----------------------------------------------------------------------------- - val VecStoreUnit = Module(new VecStoreUnit) - VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o + val VecStoreUnit: Instance[VecStoreUnit] = Instantiate(new VecStoreUnit(parameter)) + VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o - for (i <- 0 until b.acc_banks) { - io.accWrite(i) <> VecStoreUnit.io.accWrite(i) - } - VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o - + for (i <- 0 until parameter.numBanks) { + io.bankWrite(i) <> VecStoreUnit.io.bankWrite(i) + } + VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o // ----------------------------------------------------------------------------- // Set DontCare @@ -79,8 +86,8 @@ class VecUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { // ----------------------------------------------------------------------------- // Status tracking // ----------------------------------------------------------------------------- - val iterCnt = RegInit(0.U(32.W)) - val hasInput = RegInit(false.B) + val iterCnt = RegInit(0.U(32.W)) + val hasInput = RegInit(false.B) val hasOutput = RegInit(false.B) when(io.cmdReq.fire) { @@ -88,18 +95,18 @@ class VecUnit(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { } when(io.cmdResp.fire) { hasOutput := false.B - hasInput := false.B - iterCnt := iterCnt + 1.U + hasInput := false.B + iterCnt := iterCnt + 1.U } when(io.cmdResp.valid && !hasOutput) { hasOutput := true.B } - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := !hasInput && !hasOutput - io.status.init := hasInput && !hasOutput - io.status.running := hasOutput + io.status.ready := io.cmdReq.ready + io.status.valid := io.cmdResp.valid + io.status.idle := !hasInput && !hasOutput + io.status.init := hasInput && !hasOutput + io.status.running := hasOutput io.status.complete := io.cmdResp.fire - io.status.iter := iterCnt + io.status.iter := iterCnt } diff --git a/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala b/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala index 902a9941..c6ea8a95 100644 --- a/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala +++ b/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala @@ -12,11 +12,9 @@ import org.chipsalliance.diplomacy.nodes._ abstract class BondWrapper(implicit p: Parameters) extends LazyModule { val bondName = "vvv" - def to[T](name: String)(body: => T): T = { - LazyScope(s"bond_to_${name}", s"Bond_${bondName}_to_${name}") { body } - } + def to[T](name: String)(body: => T): T = + LazyScope(s"bond_to_$name", s"Bond_${bondName}_to_$name")(body) - def from[T](name: String)(body: => T): T = { - LazyScope(s"bond_from_${name}", s"Bond_${bondName}_from_${name}") { body } - } + def from[T](name: String)(body: => T): T = + LazyScope(s"bond_from_$name", s"Bond_${bondName}_from_$name")(body) } diff --git a/arch/src/main/scala/prototype/vector/bond/vvv.scala b/arch/src/main/scala/prototype/vector/bond/vvv.scala index 614a7bdf..5244ea6a 100644 --- a/arch/src/main/scala/prototype/vector/bond/vvv.scala +++ b/arch/src/main/scala/prototype/vector/bond/vvv.scala @@ -9,12 +9,12 @@ package prototype.vector.bond import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ -import prototype.vector.thread.{ThreadKey, ThreadBondKey, BaseThread} +import prototype.vector.thread.{BaseThread, ThreadBondKey, ThreadKey} class VVV(implicit p: Parameters) extends Bundle { - val lane = p(ThreadKey).get.lane - val bondParam = p(ThreadBondKey).get - val inputWidth = bondParam.inputWidth + val lane = p(ThreadKey).get.lane + val bondParam = p(ThreadBondKey).get + val inputWidth = bondParam.inputWidth val outputWidth = bondParam.outputWidth // Input interface (Flipped Decoupled) @@ -27,9 +27,11 @@ class VVV(implicit p: Parameters) extends Bundle { val out = Decoupled(new Bundle { val out = Vec(lane, UInt(outputWidth.W)) }) + } trait CanHaveVVVBond { this: BaseThread => + val vvvBond = params(ThreadBondKey).filter(_.bondType == "vvv").map { bondParam => // println(s"[VVVBond] Creating BondType: ${bondParam.bondType}") diff --git a/arch/src/main/scala/prototype/vector/configs/VecConfig.scala b/arch/src/main/scala/prototype/vector/configs/VecConfig.scala new file mode 100644 index 00000000..f1a238a6 --- /dev/null +++ b/arch/src/main/scala/prototype/vector/configs/VecConfig.scala @@ -0,0 +1,62 @@ +package prototype.vector.configs + +import chisel3._ +import chisel3.experimental.SerializableModuleParameter +import examples.toy.balldomain.BallDomainParam + +object VecConfig { + implicit def rw: upickle.default.ReadWriter[VecConfig] = upickle.default.macroRW + + def fromBallDomain(ballParam: BallDomainParam): VecConfig = { + VecConfig( + ballParam = ballParam + ) + } + + /** + * Load from JSON file + */ + def fromJson(path: String): VecConfig = { + val jsonStr = scala.io.Source.fromFile(path).mkString + upickle.default.read[VecConfig](jsonStr) + } + + /** + * Save to JSON file + */ + def toJson(config: VecConfig, path: String): Unit = { + val jsonStr = upickle.default.write(config, indent = 2) + val writer = new java.io.FileWriter(path) + try { + writer.write(jsonStr) + } finally { + writer.close() + } + } + +} + +case class VecConfig( + ballParam: BallDomainParam) + extends SerializableModuleParameter { + // Derived parameters + val bankNum = ballParam.numBanks + val bankEntries = ballParam.bankEntries + val bankWidth = ballParam.bankWidth + val bankMaskLen = ballParam.bankMaskLen + val rob_entries = ballParam.rob_entries + // InputNum and inputWidth are Ball-specific, not in BallDomainParam + val InputNum = 16 // Default value + val inputWidth = 8 // Default value + + override def toString: String = + s"""VecConfig + | Bank num: $bankNum + | Bank entries: $bankEntries + | Bank width: $bankWidth + | Bank mask length: $bankMaskLen + | ROB entries: $rob_entries + | Input num: $InputNum + | Input width: $inputWidth + |""".stripMargin +} diff --git a/arch/src/main/scala/prototype/vector/configs/default.json b/arch/src/main/scala/prototype/vector/configs/default.json new file mode 100644 index 00000000..0b9d3815 --- /dev/null +++ b/arch/src/main/scala/prototype/vector/configs/default.json @@ -0,0 +1,10 @@ +{ + "ballParam": { + "rob_entries": 16, + "numBanks": 32, + "bankEntries": 128, + "bankMaskLen": 16, + "InputNum": 16, + "inputWidth": 8 + } +} diff --git a/arch/src/main/scala/prototype/vector/op/cascade.scala b/arch/src/main/scala/prototype/vector/op/cascade.scala index ecabb34a..8b7b46d9 100644 --- a/arch/src/main/scala/prototype/vector/op/cascade.scala +++ b/arch/src/main/scala/prototype/vector/op/cascade.scala @@ -3,45 +3,45 @@ package prototype.vector.op import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ -import prototype.vector.thread.{ThreadKey, ThreadOpKey, ThreadBondKey, BaseThread} +import prototype.vector.thread.{BaseThread, ThreadBondKey, ThreadKey, ThreadOpKey} import prototype.vector.bond.VVV class CascadeOp(implicit p: Parameters) extends Module { - val lane = p(ThreadKey).get.lane - val bondParam = p(ThreadBondKey).get + val lane = p(ThreadKey).get.lane + val bondParam = p(ThreadBondKey).get val outputWidth = bondParam.outputWidth val io = IO(new VVV()(p)) - val reg1 = RegInit(VecInit(Seq.fill(lane)(0.U(outputWidth.W)))) - val reg2 = RegInit(VecInit(Seq.fill(lane)(0.U(outputWidth.W)))) - val valid1 = RegInit(false.B) - val valid2 = RegInit(false.B) + val reg1 = RegInit(VecInit(Seq.fill(lane)(0.U(outputWidth.W)))) + val reg2 = RegInit(VecInit(Seq.fill(lane)(0.U(outputWidth.W)))) + val valid1 = RegInit(false.B) + val valid2 = RegInit(false.B) io.in.ready := io.out.ready - when (io.in.valid) { + when(io.in.valid) { valid1 := true.B - reg1 := io.in.bits.in1.zip(io.in.bits.in2).map { case (a, b) => a + b } - }.elsewhen(!io.in.ready){ + reg1 := io.in.bits.in1.zip(io.in.bits.in2).map { case (a, b) => a + b } + }.elsewhen(!io.in.ready) { valid1 := valid1 }.otherwise { valid1 := false.B } - val valid = valid1 - when (io.out.ready && valid) { - io.out.valid := true.B + when(io.out.ready && valid) { + io.out.valid := true.B io.out.bits.out := reg1 }.otherwise { - io.out.valid := false.B + io.out.valid := false.B io.out.bits.out := VecInit(Seq.fill(lane)(0.U(outputWidth.W))) } } trait CanHaveCascadeOp { this: BaseThread => + val cascadeOp = params(ThreadOpKey).filter(_.OpType == "cascade").map { opParam => // println(s"[CascadeOp] Creating OpType: ${opParam.OpType}") diff --git a/arch/src/main/scala/prototype/vector/op/mul.scala b/arch/src/main/scala/prototype/vector/op/mul.scala index 91ed3f52..50fd8ec2 100644 --- a/arch/src/main/scala/prototype/vector/op/mul.scala +++ b/arch/src/main/scala/prototype/vector/op/mul.scala @@ -3,12 +3,12 @@ package prototype.vector.op import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ -import prototype.vector.thread.{ThreadKey, ThreadOpKey, ThreadBondKey, BaseThread} +import prototype.vector.thread.{BaseThread, ThreadBondKey, ThreadKey, ThreadOpKey} import prototype.vector.bond.VVV class MulOp(implicit p: Parameters) extends Module { - val lane = p(ThreadKey).get.lane - val bondParam = p(ThreadBondKey).get + val lane = p(ThreadKey).get.lane + val bondParam = p(ThreadBondKey).get val inputWidth = bondParam.inputWidth val io = IO(new VVV()(p)) @@ -16,20 +16,20 @@ class MulOp(implicit p: Parameters) extends Module { val reg1 = RegInit(VecInit(Seq.fill(lane)(0.U(inputWidth.W)))) val reg2 = RegInit(VecInit(Seq.fill(lane)(0.U(inputWidth.W)))) - val cnt = RegInit(0.U(log2Ceil(lane).W)) + val cnt = RegInit(0.U(log2Ceil(lane).W)) val active = RegInit(false.B) io.out.valid := active && io.out.ready - io.in.ready := io.out.ready + io.in.ready := io.out.ready - when (io.in.valid) { - reg1 := io.in.bits.in1 - reg2 := io.in.bits.in2 - cnt := 0.U + when(io.in.valid) { + reg1 := io.in.bits.in1 + reg2 := io.in.bits.in2 + cnt := 0.U active := true.B - } .elsewhen (active && io.out.ready) { + }.elsewhen(active && io.out.ready) { cnt := cnt + 1.U - when (cnt === (lane-1).U) { + when(cnt === (lane - 1).U) { active := false.B } } @@ -41,6 +41,7 @@ class MulOp(implicit p: Parameters) extends Module { } trait CanHaveMulOp { this: BaseThread => + val mulOp = params(ThreadOpKey).filter(_.OpType == "mul").map { opParam => // println(s"[MulOp] Creating OpType: ${opParam.OpType}") diff --git a/arch/src/main/scala/prototype/vector/thread/BaseThread.scala b/arch/src/main/scala/prototype/vector/thread/BaseThread.scala index 0f9740cd..06930c25 100644 --- a/arch/src/main/scala/prototype/vector/thread/BaseThread.scala +++ b/arch/src/main/scala/prototype/vector/thread/BaseThread.scala @@ -5,27 +5,36 @@ import chisel3._ import org.chipsalliance.cde.config._ // Parameter definitions -case class ThreadParam(lane: Int, attr: String, threadName: String, Op: OpParam) +case class ThreadParam( + lane: Int, + attr: String, + threadName: String, + Op: OpParam) + case class OpParam(OpType: String, bondType: BondParam) case class BondParam(bondType: String, inputWidth: Int = 8, outputWidth: Int = 32) -case object ThreadKey extends Field[Option[ThreadParam]](None) -case object ThreadOpKey extends Field[Option[OpParam]](None) +case object ThreadKey extends Field[Option[ThreadParam]](None) +case object ThreadOpKey extends Field[Option[OpParam]](None) case object ThreadBondKey extends Field[Option[BondParam]](None) -case object ThreadMapKey extends Field[Map[String, ThreadParam]](Map.empty) +case object ThreadMapKey extends Field[Map[String, ThreadParam]](Map.empty) //===----------------------------------------------------------------------===// // BaseThread base class //===----------------------------------------------------------------------===// class BaseThread(implicit p: Parameters) extends Module { - val io = IO(new Bundle {}) - val params = p + val io = IO(new Bundle {}) + val params = p val threadMap = p(ThreadMapKey) + val threadParam = threadMap.getOrElse( p(ThreadKey).get.threadName, throw new Exception(s"ThreadParam not found for threadName: ${p(ThreadKey).get.threadName}") ) - val opParam = p(ThreadOpKey).get + + val opParam = p(ThreadOpKey).get val bondParam = p(ThreadBondKey).get - println(s"[Thread_${threadParam.threadName}] Op: ${opParam.OpType}, bond: ${bondParam.bondType}, Lanes: ${threadParam.lane}") + println( + s"[Thread_${threadParam.threadName}] Op: ${opParam.OpType}, bond: ${bondParam.bondType}, Lanes: ${threadParam.lane}" + ) } diff --git a/arch/src/main/scala/prototype/vector/thread/CasThread.scala b/arch/src/main/scala/prototype/vector/thread/CasThread.scala index e90d4beb..5c0ed560 100644 --- a/arch/src/main/scala/prototype/vector/thread/CasThread.scala +++ b/arch/src/main/scala/prototype/vector/thread/CasThread.scala @@ -4,15 +4,13 @@ import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import prototype.vector.bond.CanHaveVVVBond -import prototype.vector.op.{CascadeOp, CanHaveCascadeOp} +import prototype.vector.op.{CanHaveCascadeOp, CascadeOp} -class CasThread(implicit p: Parameters) extends BaseThread - with CanHaveCascadeOp - with CanHaveVVVBond { +class CasThread(implicit p: Parameters) extends BaseThread with CanHaveCascadeOp with CanHaveVVVBond { // Connect CascadeOp and VVVBond for { - op <- cascadeOp + op <- cascadeOp bond <- vvvBond } { op.io.in <> bond.in diff --git a/arch/src/main/scala/prototype/vector/thread/MulThread.scala b/arch/src/main/scala/prototype/vector/thread/MulThread.scala index 5be6d498..1ee20cb8 100644 --- a/arch/src/main/scala/prototype/vector/thread/MulThread.scala +++ b/arch/src/main/scala/prototype/vector/thread/MulThread.scala @@ -4,15 +4,13 @@ import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import prototype.vector.bond.CanHaveVVVBond -import prototype.vector.op.{MulOp, CanHaveMulOp} +import prototype.vector.op.{CanHaveMulOp, MulOp} -class MulThread(implicit p: Parameters) extends BaseThread - with CanHaveMulOp - with CanHaveVVVBond { +class MulThread(implicit p: Parameters) extends BaseThread with CanHaveMulOp with CanHaveVVVBond { // Connect MulOp and VVVBond for { - op <- mulOp + op <- mulOp bond <- vvvBond } { op.io.in <> bond.in diff --git a/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala b/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala index b974e035..31946d01 100644 --- a/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala +++ b/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala @@ -9,8 +9,8 @@ import prototype.vector.thread._ import prototype.vector.bond.BondWrapper class MeshWarpInput extends Bundle { - val op1 = Vec(16, UInt(8.W)) - val op2 = Vec(16, UInt(8.W)) + val op1 = Vec(16, UInt(8.W)) + val op2 = Vec(16, UInt(8.W)) val thread_id = UInt(10.W) } @@ -19,50 +19,51 @@ class MeshWarpOutput extends Bundle { } class MeshWarp(implicit p: Parameters) extends Module { + val io = IO(new Bundle { - val in = Flipped(Decoupled(new MeshWarpInput)) + val in = Flipped(Decoupled(new MeshWarpInput)) val out = Decoupled(new MeshWarpOutput) }) val threadMap = (0 until 32).map { i => val threadName = i.toString // 0-15 mul, 16-31 cascade - val opType = if (i < 16) "mul" else "cascade" + val opType = if (i < 16) "mul" else "cascade" // mul operation: 8-bit input, 32-bit output; cascade operation: 32-bit input, 32-bit output - val bond = if (opType == "mul") { + val bond = if (opType == "mul") { BondParam("vvv", inputWidth = 8, outputWidth = 32) } else { BondParam("vvv", inputWidth = 32, outputWidth = 32) } - val op = OpParam(opType, bond) + val op = OpParam(opType, bond) // All threads use the same lane count - val thread = ThreadParam(16, s"attr$threadName", threadName, op) + val thread = ThreadParam(16, s"attr$threadName", threadName, op) threadName -> thread }.toMap val mulThreads = (0 until 16).map { i => - val threadName = i.toString - val threadParam = threadMap(threadName) - val opParam = threadParam.Op - val bondParam = opParam.bondType + val threadName = i.toString + val threadParam = threadMap(threadName) + val opParam = threadParam.Op + val bondParam = opParam.bondType val threadParams = p.alterMap(Map( - ThreadMapKey -> threadMap, - ThreadKey -> Some(threadParam), - ThreadOpKey -> Some(opParam), + ThreadMapKey -> threadMap, + ThreadKey -> Some(threadParam), + ThreadOpKey -> Some(opParam), ThreadBondKey -> Some(bondParam) )) Module(new MulThread()(threadParams)) } val casThreads = (16 until 32).map { i => - val threadName = i.toString - val threadParam = threadMap(threadName) - val opParam = threadParam.Op - val bondParam = opParam.bondType + val threadName = i.toString + val threadParam = threadMap(threadName) + val opParam = threadParam.Op + val bondParam = opParam.bondType val threadParams = p.alterMap(Map( - ThreadMapKey -> threadMap, - ThreadKey -> Some(threadParam), - ThreadOpKey -> Some(opParam), + ThreadMapKey -> threadMap, + ThreadKey -> Some(threadParam), + ThreadOpKey -> Some(opParam), ThreadBondKey -> Some(bondParam) )) Module(new CasThread()(threadParams)) @@ -71,7 +72,7 @@ class MeshWarp(implicit p: Parameters) extends Module { io.in.ready := mulThreads(0).vvvBond.get.in.ready for (i <- 0 until 16) { - val mulThread = mulThreads(i) + val mulThread = mulThreads(i) val casThread = casThreads(i) for { mulBond <- mulThread.vvvBond @@ -85,7 +86,7 @@ class MeshWarp(implicit p: Parameters) extends Module { if (i == 0) { casBond.in.bits.in2 := VecInit(Seq.fill(16)(0.U(32.W))) // First cascade thread's valid is determined by mulBond's output valid - casBond.in.valid := mulBond.out.valid + casBond.in.valid := mulBond.out.valid // First cascade thread's output ready is connected to next cascade thread's input ready if (i < 15) { for { @@ -101,7 +102,7 @@ class MeshWarp(implicit p: Parameters) extends Module { // Directly connect 32-bit output to 32-bit input casBond.in.bits.in2 := prevCasBond.out.bits.out // casBond's valid is jointly determined by previous casBond's output valid and current mulBond's output valid - casBond.in.valid := prevCasBond.out.valid || mulBond.out.valid + casBond.in.valid := prevCasBond.out.valid || mulBond.out.valid } // Middle cascade thread's output ready is connected to next cascade thread's input ready if (i < 15) { @@ -114,13 +115,13 @@ class MeshWarp(implicit p: Parameters) extends Module { } // Only allow mulOp corresponding to thread_id to drive input - when (i.U === io.in.bits.thread_id && io.in.valid) { - mulBond.in.valid := true.B + when(i.U === io.in.bits.thread_id && io.in.valid) { + mulBond.in.valid := true.B mulBond.in.bits.in1 := io.in.bits.op1 mulBond.in.bits.in2 := io.in.bits.op2 - io.in.ready := mulBond.in.ready + io.in.ready := mulBond.in.ready }.otherwise { - mulBond.in.valid := false.B + mulBond.in.valid := false.B mulBond.in.bits.in1 := VecInit(Seq.fill(16)(0.U(8.W))) mulBond.in.bits.in2 := VecInit(Seq.fill(16)(0.U(8.W))) } @@ -131,8 +132,8 @@ class MeshWarp(implicit p: Parameters) extends Module { for { finalCasBond <- casThreads(15).vvvBond } { - io.out.valid := finalCasBond.out.valid - io.out.bits.res := finalCasBond.out.bits.out + io.out.valid := finalCasBond.out.valid + io.out.bits.res := finalCasBond.out.bits.out finalCasBond.out.ready := io.out.ready } } diff --git a/arch/src/main/scala/prototype/vector/warp/VecBall.scala b/arch/src/main/scala/prototype/vector/warp/VecBall.scala index f4b632d1..b624fdc0 100644 --- a/arch/src/main/scala/prototype/vector/warp/VecBall.scala +++ b/arch/src/main/scala/prototype/vector/warp/VecBall.scala @@ -8,13 +8,13 @@ class BallIO extends Bundle { // val start = Output(Bool()) // val arrive = Output(Bool()) // val done = Output(Bool()) - val iterIn = Flipped(Decoupled(UInt(10.W))) + val iterIn = Flipped(Decoupled(UInt(10.W))) val iterOut = Valid(UInt(10.W)) } class VecBallIO extends BallIO { - val op1In = Flipped(Valid(Vec(16, UInt(8.W)))) - val op2In = Flipped(Valid(Vec(16, UInt(8.W)))) + val op1In = Flipped(Valid(Vec(16, UInt(8.W)))) + val op2In = Flipped(Valid(Vec(16, UInt(8.W)))) val rstOut = Decoupled(Vec(16, UInt(32.W))) } @@ -22,17 +22,17 @@ class VecBall(implicit p: Parameters) extends Module { val io = IO(new VecBallIO()) // Internal state registers & iteration counter - val start = RegInit(false.B) - val arrive = RegInit(false.B) - val done = RegInit(false.B) - val iter = RegInit(0.U(10.W)) + val start = RegInit(false.B) + val arrive = RegInit(false.B) + val done = RegInit(false.B) + val iter = RegInit(0.U(10.W)) val iterCounter = RegInit(0.U(10.W)) // Independent control logic val threadId = RegInit(0.U(4.W)) - when (io.op1In.valid && io.op2In.valid && threadId < 15.U) { + when(io.op1In.valid && io.op2In.valid && threadId < 15.U) { threadId := threadId + 1.U - } .elsewhen (io.op1In.valid && io.op2In.valid && threadId === 15.U) { + }.elsewhen(io.op1In.valid && io.op2In.valid && threadId === 15.U) { threadId := 0.U } @@ -40,31 +40,31 @@ class VecBall(implicit p: Parameters) extends Module { val meshWarp = Module(new MeshWarp()(p)) // Connect external IO to MeshWarp - meshWarp.io.in.valid := io.op1In.valid && io.op2In.valid - meshWarp.io.in.bits.op1 := io.op1In.bits - meshWarp.io.in.bits.op2 := io.op2In.bits + meshWarp.io.in.valid := io.op1In.valid && io.op2In.valid + meshWarp.io.in.bits.op1 := io.op1In.bits + meshWarp.io.in.bits.op2 := io.op2In.bits meshWarp.io.in.bits.thread_id := threadId - io.rstOut.valid := meshWarp.io.out.valid - io.rstOut.bits := meshWarp.io.out.bits.res + io.rstOut.valid := meshWarp.io.out.valid + io.rstOut.bits := meshWarp.io.out.bits.res meshWarp.io.out.ready := io.rstOut.ready // Handle iteration input - when (io.iterIn.fire) {iterCounter := 0.U; iter := io.iterIn.bits} + when(io.iterIn.fire) { iterCounter := 0.U; iter := io.iterIn.bits } // Pull start high when external input arrives - when (io.op1In.valid && io.op2In.valid) {start := true.B} + when(io.op1In.valid && io.op2In.valid)(start := true.B) // Pull arrive high when first output starts to be valid - when (io.rstOut.valid && !arrive) {arrive := true.B} + when(io.rstOut.valid && !arrive)(arrive := true.B) // Increment by one for each output - when (io.rstOut.valid && iterCounter =/= iter) {iterCounter := iterCounter + 1.U} + when(io.rstOut.valid && iterCounter =/= iter)(iterCounter := iterCounter + 1.U) // Pull done high when iter returns to 0 - when (iterCounter === iter) {done := true.B} + when(iterCounter === iter)(done := true.B) // Reset logic - when (io.iterIn.fire) { - start := false.B - arrive := false.B - done := false.B + when(io.iterIn.fire) { + start := false.B + arrive := false.B + done := false.B iterCounter := 0.U } @@ -75,8 +75,8 @@ class VecBall(implicit p: Parameters) extends Module { // Output current iteration count io.iterOut.valid := io.rstOut.valid - io.iterOut.bits := iterCounter - io.iterIn.ready := meshWarp.io.in.ready + io.iterOut.bits := iterCounter + io.iterIn.ready := meshWarp.io.in.ready // def get_iterCounter(): UInt = { // iterCounter diff --git a/arch/src/main/scala/sims/firesim/TargetConfigs.scala b/arch/src/main/scala/sims/firesim/TargetConfigs.scala index 9d4b3531..e22a6825 100644 --- a/arch/src/main/scala/sims/firesim/TargetConfigs.scala +++ b/arch/src/main/scala/sims/firesim/TargetConfigs.scala @@ -7,30 +7,38 @@ import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.tilelink.{BootROMParams, BootROMLocated} +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} -class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => { - val chipyardBootROM = new File(s"./thirdparty/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img") - val firesimBootROM = new File(s"./thirdparty/chipyard/target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img") +class WithBootROM + extends Config((site, here, up) => { + case BootROMLocated(x) => { + val chipyardBootROM = + new File(s"./thirdparty/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img") + val firesimBootROM = new File( + s"./thirdparty/chipyard/target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img" + ) - val bootROMPath = if (chipyardBootROM.exists()) { - chipyardBootROM.getAbsolutePath() - } else { - firesimBootROM.getAbsolutePath() - } - up(BootROMLocated(x)).map(_.copy(contentFileName = bootROMPath)) - } -}) + val bootROMPath = if (chipyardBootROM.exists()) { + chipyardBootROM.getAbsolutePath() + } else { + firesimBootROM.getAbsolutePath() + } + up(BootROMLocated(x)).map(_.copy(contentFileName = bootROMPath)) + } + }) -class FireSimGemminiBuckyballConfig extends Config( - new WithBootROM ++ - new firechip.chip.WithDefaultFireSimBridges ++ - new firechip.chip.WithFireSimConfigTweaks ++ - new chipyard.GemminiRocketConfig) +class FireSimGemminiBuckyballConfig + extends Config( + new WithBootROM ++ + new firechip.chip.WithDefaultFireSimBridges ++ + new firechip.chip.WithFireSimConfigTweaks ++ + new chipyard.GemminiRocketConfig + ) -class FireSimBuckyballToyConfig extends Config( - new WithBootROM ++ - new firechip.chip.WithDefaultFireSimBridges ++ - new firechip.chip.WithFireSimConfigTweaks ++ - new examples.toy.BuckyballToyConfig) +class FireSimBuckyballToyConfig + extends Config( + new WithBootROM ++ + new firechip.chip.WithDefaultFireSimBridges ++ + new firechip.chip.WithFireSimConfigTweaks ++ + new examples.toy.BuckyballToyConfig + ) diff --git a/arch/src/main/scala/sims/palladium/TargetConfigs.scala b/arch/src/main/scala/sims/palladium/TargetConfigs.scala index e2bbcfb7..450519d1 100644 --- a/arch/src/main/scala/sims/palladium/TargetConfigs.scala +++ b/arch/src/main/scala/sims/palladium/TargetConfigs.scala @@ -3,15 +3,17 @@ package sims.palladium import org.chipsalliance.cde.config.Config import chipyard._ -class BuckyballToyP2EConfig extends Config( - new palladium.fpga.WithFPGAFrequency(50) ++ - new palladium.fpga.WithVCU19PTweaks ++ - new examples.toy.BuckyballToy256Config // Test with 256 cores + 8 L2 banks -) +class BuckyballToyP2EConfig + extends Config( + new palladium.fpga.WithFPGAFrequency(50) ++ + new palladium.fpga.WithVCU19PTweaks ++ + new examples.toy.BuckyballToy256Config // Test with 256 cores + 8 L2 banks + ) // Cross-bar config -class BuckyballToyP2ECBConfig extends Config( - new palladium.fpga.WithFPGAFrequency(50) ++ - new palladium.fpga.WithVCU19PTweaks ++ - new examples.toy.BuckyballToy256CBConfig -) +class BuckyballToyP2ECBConfig + extends Config( + new palladium.fpga.WithFPGAFrequency(50) ++ + new palladium.fpga.WithVCU19PTweaks ++ + new examples.toy.BuckyballToy256CBConfig + ) diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index b61566a6..be588c84 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -2,78 +2,80 @@ package sims.verify import chisel3._ import _root_.circt.stage.ChiselStage -import org.chipsalliance.cde.config.{Config, Parameters, Field} +import org.chipsalliance.cde.config.{Config, Field, Parameters} import examples.BuckyballConfigs.CustomBuckyballConfig +import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Blink import prototype.vector.VecBall +import prototype.vector.configs.VecConfig import prototype.matrix.MatrixBall +import prototype.matrix.configs.MatrixConfig import prototype.transpose.TransposeBall +import prototype.transpose.configs.TransposeConfig import prototype.im2col.Im2colBall +import prototype.im2col.configs.Im2colConfig import prototype.relu.ReluBall +import prototype.relu.configs.ReluConfig import prototype.nnlut.NNLutBall +import prototype.nnlut.configs.NNLutConfig // Ball type definitions sealed trait BallType -case object VecBallType extends BallType -case object MatrixBallType extends BallType +case object VecBallType extends BallType +case object MatrixBallType extends BallType case object TransposeBallType extends BallType -case object Im2colBallType extends BallType -case object ReluBallType extends BallType -case object NNLutBallType extends BallType +case object Im2colBallType extends BallType +case object ReluBallType extends BallType +case object NNLutBallType extends BallType // Config Key case object TargetBallKey extends Field[BallType](VecBallType) // TargetBall - directly instantiate pre-packaged Ball class TargetBall(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val io = IO(new Blink) + // Create BallDomainParam from global config + val ballParam = BallDomainParam.fromGlobal(b) + + // Create Blink IO with parameter + val io = IO(new Blink(ballParam, ballParam.bankEntries, ballParam.bankWidth, ballParam.bankMaskLen)) p(TargetBallKey) match { - case VecBallType => - val ball = Module(new VecBall(0)) + case VecBallType => + val ball = Module(new VecBall(VecConfig.fromBallDomain(ballParam), 0)) io <> ball.io - case MatrixBallType => - val ball = Module(new MatrixBall(0)) + case MatrixBallType => + val ball = Module(new MatrixBall(MatrixConfig.fromBallDomain(ballParam), 0)) io <> ball.io - case Im2colBallType => - val ball = Module(new Im2colBall(0)) + case Im2colBallType => + val ball = Module(new Im2colBall(Im2colConfig.fromBallDomain(ballParam), 0)) io <> ball.io case TransposeBallType => - val ball = Module(new TransposeBall(0)) + val ball = Module(new TransposeBall(TransposeConfig.fromBallDomain(ballParam), 0)) io <> ball.io - case ReluBallType => - val ball = Module(new ReluBall(0)) + case ReluBallType => + val ball = Module(new ReluBall(ReluConfig.fromBallDomain(ballParam), 0)) io <> ball.io - case NNLutBallType => - val ball = Module(new NNLutBall(0)) + case NNLutBallType => + val ball = Module(new NNLutBall(NNLutConfig.fromBallDomain(ballParam), 0)) io <> ball.io - case _ => throw new scala.MatchError("TargetBall does not handle this ball type") + case _ => throw new scala.MatchError("TargetBall does not handle this ball type") } override lazy val desiredName = "TargetBall" } -// WithBlink configuration - empty configuration, used to combine with other configurations -// class WithBlink extends Config((site, here, up) => { -// case _ => up(site) -// }) - -// ============================================================================ -// Config combination usage examples: -// new Config(new WithVecBall ++ new WithBlink) -// new Config(new WithMatrixBall ++ new WithBlink) -// new Config(new WithTransposeBall ++ new WithBlink) -// ============================================================================ +class WithTargetBall(ballType: BallType) + extends Config((site, here, up) => { + case TargetBallKey => ballType + }) -class WithTargetBall(ballType: BallType) extends Config((site, here, up) => { - case TargetBallKey => ballType -}) - -class CustomBallTopConfig(ballType: BallType) extends Config( - // new WithBlink ++ - new WithTargetBall(ballType) -) +class CustomBallTopConfig(ballType: BallType) + extends Config( + // new WithBlink ++ + new WithTargetBall(ballType) + ) object BallTopMain extends App { + // Select Ball type from command line arguments val ballType = if (args.isEmpty) { println("Usage: BallTopMain [firtool-opts...]") @@ -82,20 +84,20 @@ object BallTopMain extends App { VecBallType } else { args(0).toLowerCase match { - case "vecball" => VecBallType - case "matrixball" => MatrixBallType + case "vecball" => VecBallType + case "matrixball" => MatrixBallType case "transposeball" => TransposeBallType - case "im2colball" => Im2colBallType - case "reluball" => ReluBallType - case "nnlutball" => NNLutBallType - case other => + case "im2colball" => Im2colBallType + case "reluball" => ReluBallType + case "nnlutball" => NNLutBallType + case other => println(s"Unknown ball type: $other, using vecball") VecBallType } } implicit val config: CustomBuckyballConfig = examples.CustomBuckyballConfig() - implicit val params: Parameters = new Config(new CustomBallTopConfig(ballType)) + implicit val params: Parameters = new Config(new CustomBallTopConfig(ballType)) ChiselStage.emitSystemVerilogFile( new TargetBall(), diff --git a/arch/src/main/scala/sims/verilator/TargetConfig.scala b/arch/src/main/scala/sims/verilator/TargetConfig.scala index 5666bf7c..dd0ea5cd 100644 --- a/arch/src/main/scala/sims/verilator/TargetConfig.scala +++ b/arch/src/main/scala/sims/verilator/TargetConfig.scala @@ -5,26 +5,28 @@ import chisel3._ import _root_.circt.stage.ChiselStage import org.chipsalliance.cde.config.{Config, Parameters} -import freechips.rocketchip.devices.tilelink.{BootROMParams, BootROMLocated} +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.subsystem.InSubsystem - // Custom BootROM configuration, pointing to correct resource path -class WithCustomBootROM extends Config((site, here, up) => { - case BootROMLocated(InSubsystem) => Some(BootROMParams( - contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" - )) -}) - -class BuckyballToyVerilatorConfig extends Config( - new WithCustomBootROM ++ - new examples.toy.BuckyballToyConfig) - -class BuckyballGemminiVerilatorConfig extends Config( - new WithCustomBootROM ++ - new gemmini.DefaultGemminiConfig) - - +class WithCustomBootROM + extends Config((site, here, up) => { + case BootROMLocated(InSubsystem) => Some(BootROMParams( + contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" + )) + }) + +class BuckyballToyVerilatorConfig + extends Config( + new WithCustomBootROM ++ + new examples.toy.BuckyballToyConfig + ) + +class BuckyballGemminiVerilatorConfig + extends Config( + new WithCustomBootROM ++ + new gemmini.DefaultGemminiConfig + ) object Elaborate extends App { // Accept full config class name like "sims.verilator.BuckyballToyVerilatorConfig" @@ -38,18 +40,19 @@ object Elaborate extends App { println(s"Elaborating with config class: $configClassName") // Dynamically load the config class - val config: Config = try { - val configClass = Class.forName(configClassName) - configClass.getDeclaredConstructor().newInstance().asInstanceOf[Config] - } catch { - case e: ClassNotFoundException => - println(s"Error: Config class not found: $configClassName") - sys.exit(1) - case e: Exception => - println(s"Error loading config class: ${e.getMessage}") - e.printStackTrace() - sys.exit(1) - } + val config: Config = + try { + val configClass = Class.forName(configClassName) + configClass.getDeclaredConstructor().newInstance().asInstanceOf[Config] + } catch { + case e: ClassNotFoundException => + println(s"Error: Config class not found: $configClassName") + sys.exit(1) + case e: Exception => + println(s"Error loading config class: ${e.getMessage}") + e.printStackTrace() + sys.exit(1) + } ChiselStage.emitSystemVerilogFile( new chipyard.harness.TestHarness()(config.toInstance), diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c index 2de6c03a..f71ffd6f 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c @@ -8,7 +8,7 @@ #define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 16, 23) | FIELD(iter, 24, 33) | FIELD(mode, 34, 34)), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 17) | FIELD(mode, 18, 18)), \ BB_MUL_WARP16_FUNC7) #endif // _BB_MUL_WARP16_H_ diff --git a/scripts/init.sh b/scripts/init.sh index 6cc81334..809b7588 100755 --- a/scripts/init.sh +++ b/scripts/init.sh @@ -158,12 +158,12 @@ if run_step "9"; then ./install-mill.sh fi -# if run_step "10"; then -# begin_step "10" "pre-compile buckyball arch code" -# source ${BBDIR}/env.sh -# cd ${BBDIR}/ -# bbdev verilator --verilog -# fi +if run_step "10"; then + begin_step "10" "install fmt tools" + source ${BBDIR}/env.sh + cd ${BBDIR} + ${BBDIR}/scripts/install-scalafmt.sh +fi if run_step "11"; then begin_step "11" "Install pre-commit" diff --git a/scripts/install-scalafmt.sh b/scripts/install-scalafmt.sh new file mode 100755 index 00000000..51605bb9 --- /dev/null +++ b/scripts/install-scalafmt.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +set -e + +BBDIR=$(git rev-parse --show-toplevel) +source ${BBDIR}/scripts/utils.sh + +INSTALL_DIR="${HOME}/.local/bin" +mkdir -p "${INSTALL_DIR}" + +SCALAFMT_VERSION=$(grep "^version" ${BBDIR}/arch/.scalafmt.conf 2>/dev/null | sed 's/version = //;s/"//g' | tr -d ' ' || echo "3.9.6") + +if command -v cs &> /dev/null; then + cs install scalafmt:${SCALAFMT_VERSION} --install-dir "${INSTALL_DIR}" +else + echo "Downloading coursier..." + curl -fL https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-linux.gz | gzip -d > /tmp/cs + chmod +x /tmp/cs + /tmp/cs install scalafmt:${SCALAFMT_VERSION} --install-dir "${INSTALL_DIR}" + rm /tmp/cs +fi + +replace_content ${BBDIR}/env.sh install-scalafmt "# line auto-generated by $0 +export PATH=${INSTALL_DIR}:\${PATH}" + +echo "✓ Scalafmt ${SCALAFMT_VERSION} installed to ${INSTALL_DIR}" From 41f8f46f68fe872019aa306b7f29b109d1a451d3 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 24 Dec 2025 22:06:11 +0800 Subject: [PATCH 018/238] [bb-test] fix: fix the mistake of the bits of the ISA inst need resolved --- bb-tests/workloads/lib/bbhw/isa/24_mvin.c | 4 ++-- bb-tests/workloads/lib/bbhw/isa/25_mvout.c | 4 ++-- bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c | 2 +- bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c | 2 +- bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c | 2 +- bb-tests/workloads/lib/bbhw/isa/33_im2col.c | 6 +++--- bb-tests/workloads/lib/bbhw/isa/34_transpose.c | 2 +- bb-tests/workloads/lib/bbhw/isa/38_relu.c | 3 ++- bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c | 4 ++-- bb-tests/workloads/lib/bbhw/isa/40_nnlut.c | 6 +++--- bb-tests/workloads/lib/bbhw/isa/41_snn.c | 10 +++++----- bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c | 6 +++--- bb-tests/workloads/lib/bbhw/isa/43_conv.c | 10 +++++----- bb-tests/workloads/lib/bbhw/isa/44_cim.c | 8 ++++---- bb-tests/workloads/lib/bbhw/isa/45_transfer.c | 6 +++--- 15 files changed, 38 insertions(+), 37 deletions(-) diff --git a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c index 19c1ffc8..533bb5a2 100644 --- a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c @@ -7,8 +7,8 @@ #define bb_mvin(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(mem_addr, 0, 14), \ - (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 31)), \ + FIELD(mem_addr, 0, 31), \ + (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 33)), \ BB_MVIN_FUNC7) #endif // _BB_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c index 03c5b450..89db0c54 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c @@ -7,8 +7,8 @@ #define bb_mvout(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(mem_addr, 0, 14), \ - (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 31)), \ + FIELD(mem_addr, 0, 31), \ + (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 33)), \ BB_MVOUT_FUNC7) #endif // _BB_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c b/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c index 1456c9db..763e1fa7 100644 --- a/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c +++ b/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c @@ -8,6 +8,6 @@ #define bb_bbfp_mul(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 16, 23) | FIELD(iter, 24, 33)), BB_BBFP_MUL_FUNC7) + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_BBFP_MUL_FUNC7) #endif // _BBFP_MUL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c index 64ef6f56..15d6a238 100644 --- a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c +++ b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c @@ -8,7 +8,7 @@ #define bb_matmul_ws(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 16, 23) | FIELD(iter, 24, 33) | FIELD(1, 34, 34)), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(ws_flag, 24, 24)), \ BB_MATMUL_WS_FUNC7) #endif // _MATMUL_WS_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c index f71ffd6f..f1397080 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c @@ -8,7 +8,7 @@ #define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 17) | FIELD(mode, 18, 18)), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(mode, 24, 24)), \ BB_MUL_WARP16_FUNC7) #endif // _BB_MUL_WARP16_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c index 1eac76bc..8f5e795f 100644 --- a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c +++ b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c @@ -9,9 +9,9 @@ startcol) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(kcol, 26, 29) | FIELD(krow, 30, 33) | FIELD(incol, 34, 38) | \ - FIELD(inrow, 39, 43) | FIELD(startcol, 49, 53) | \ - FIELD(startrow, 54, 58)), \ + (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | FIELD(incol, 8, 12) | \ + FIELD(inrow, 13, 17) | FIELD(startcol, 23, 27) | \ + FIELD(startrow, 28, 32)), \ BB_IM2COL_FUNC7) #endif // _BB_IM2COL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c index 6b7aefae..88af6fe4 100644 --- a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c +++ b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c @@ -8,6 +8,6 @@ #define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(iter, 15, 24) | FIELD(mode, 25, 25)), BB_TRANSPOSE_FUNC7) + (FIELD(iter, 0, 15) | FIELD(mode, 16, 16)), BB_TRANSPOSE_FUNC7) #endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/38_relu.c b/bb-tests/workloads/lib/bbhw/isa/38_relu.c index 02a91d7f..af013bc6 100644 --- a/bb-tests/workloads/lib/bbhw/isa/38_relu.c +++ b/bb-tests/workloads/lib/bbhw/isa/38_relu.c @@ -7,7 +7,8 @@ #define bb_relu(bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R(FIELD(bank_id, 0, 7), \ - FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 17), \ + FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23), \ BB_RELU_FUNC7) #endif // _BB_RELU_H_ + diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c index b214dc27..16ca979c 100644 --- a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c +++ b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c @@ -7,8 +7,8 @@ #define bb_bbus_config(src_bid, dst_bid, enable) \ BUCKYBALL_INSTRUCTION_R_R(0, \ - (FIELD(src_bid, 25, 30) | FIELD(dst_bid, 31, 36) | \ - FIELD(enable, 37, 37)), \ + (FIELD(src_bid,0, 5) | FIELD(dst_bid, 6, 11) | \ + FIELD(enable, 12, 12)), \ BB_BBUS_CONFIG_FUNC7) #endif // _BB_BBUS_CONFIG_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c index a6b174ff..354d4222 100644 --- a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c +++ b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c @@ -5,9 +5,9 @@ #define BB_NNLUT_FUNC7 40 -#define bb_nnlut(op1_addr, wr_addr, iter) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_addr, 0, 14), \ - (FIELD(wr_addr, 0, 14) | FIELD(iter, 15, 24)), \ +#define bb_nnlut(op1_bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), \ BB_NNLUT_FUNC7) #endif // _BB_NNLUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_snn.c b/bb-tests/workloads/lib/bbhw/isa/41_snn.c index f52e52aa..2e832e20 100644 --- a/bb-tests/workloads/lib/bbhw/isa/41_snn.c +++ b/bb-tests/workloads/lib/bbhw/isa/41_snn.c @@ -4,11 +4,11 @@ #include "isa.h" #define BB_SNN_FUNC7 41 -#define bb_snn(op1_addr, wr_addr, iter, threshold, leak_factor) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_addr, 0, 14), \ - (FIELD(wr_addr, 0, 14) | FIELD(iter, 15, 24) | \ - FIELD(threshold, 25, 32) | \ - FIELD(leak_factor, 33, 40)), \ +#define bb_snn(op1_bank_id, wr_bank_id, iter, threshold, leak_factor) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ + FIELD(threshold, 24, 31) | \ + FIELD(leak_factor, 32, 39)), \ BB_SNN_FUNC7) #endif // _BB_SNN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c index f9bf354a..564298bf 100644 --- a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c +++ b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c @@ -4,9 +4,9 @@ #include "isa.h" #define BB_ABFT_SYSTOLIC_FUNC7 42 -#define bb_abft_systolic(op1_addr, op2_addr, wr_addr, iter) \ +#define bb_abft_systolic(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_addr, 0, 14) | FIELD(op2_addr, 15, 29)), \ - (FIELD(wr_addr, 0, 14) | FIELD(iter, 15, 24)), BB_ABFT_SYSTOLIC_FUNC7) + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_ABFT_SYSTOLIC_FUNC7) #endif // _BB_ABFT_SYSTOLIC_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_conv.c b/bb-tests/workloads/lib/bbhw/isa/43_conv.c index e8bfa393..f3e37e86 100644 --- a/bb-tests/workloads/lib/bbhw/isa/43_conv.c +++ b/bb-tests/workloads/lib/bbhw/isa/43_conv.c @@ -5,13 +5,13 @@ #define BB_CONV_FUNC7 43 -#define bb_conv(ifmap_addr, weight_addr, ofmap_addr, iter, in_height, \ +#define bb_conv(ifmap_bank_id, weight_bank_id, ofmap_bank_id, iter, in_height, \ in_width, kernel_h, kernel_w) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(ifmap_addr, 0, 14) | FIELD(weight_addr, 15, 29)), \ - (FIELD(ofmap_addr, 0, 14) | FIELD(iter, 15, 24) | \ - FIELD(in_height, 25, 40) | FIELD(in_width, 41, 56) | \ - FIELD(kernel_h, 57, 64)), \ + (FIELD(ifmap_bank_id, 0, 7) | FIELD(weight_bank_id, 8, 15)), \ + (FIELD(ofmap_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ + FIELD(in_height, 24, 39) | FIELD(in_width, 40, 55) | \ + FIELD(kernel_h, 56, 63)), \ BB_CONV_FUNC7) #endif // _BB_CONV_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/44_cim.c b/bb-tests/workloads/lib/bbhw/isa/44_cim.c index 0986110e..6f2d5468 100644 --- a/bb-tests/workloads/lib/bbhw/isa/44_cim.c +++ b/bb-tests/workloads/lib/bbhw/isa/44_cim.c @@ -4,11 +4,11 @@ #include "isa.h" #define BB_CIM_FUNC7 44 -#define bb_cim(op1_addr, op2_addr, result_addr, iter, rows, cols, op_type) \ +#define bb_cim(op1_bank_id, op2_bank_id, result_bank_id, iter, rows, cols, op_type) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_addr, 0, 14) | FIELD(op2_addr, 15, 29)), \ - (FIELD(result_addr, 0, 14) | FIELD(iter, 15, 24) | FIELD(rows, 25, 40) | \ - FIELD(cols, 41, 56) | FIELD(op_type, 57, 60)), \ + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(result_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(rows, 24, 39) | \ + FIELD(cols, 40, 55) | FIELD(op_type, 56, 59)), \ BB_CIM_FUNC7) #endif // _BB_CIM_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c index 23afd483..a81252bf 100644 --- a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c +++ b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c @@ -5,10 +5,10 @@ #define BB_TRANSFER_FUNC7 45 -#define bb_transfer(op1_addr, wr_addr, iter) \ +#define bb_transfer(op1_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(op1_addr, 0, 14), \ - (FIELD(wr_addr, 0, 14) | FIELD((iter > 1023 ? 1023 : iter), 15, 24)), \ + FIELD(op1_bank_id, 0, 7), \ + (FIELD(wr_bank_id, 0, 7) | FIELD((iter > 1023 ? 1023 : iter), 8, 23)), \ BB_TRANSFER_FUNC7) #endif // _BB_TRANSFER_H_ From 45f09ff3eb622aee6882da1b8265ca1a7c6d45ae Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 29 Dec 2025 03:35:45 +0800 Subject: [PATCH 019/238] [arch] feat: complete implementation of hierarchical parameterisation --- arch/build.sbt | 4 +- .../main/scala/examples/BuckyBallConfig.scala | 56 --- arch/src/main/scala/examples/README.md | 346 --------------- .../scala/examples/toy/CustomConfigs.scala | 13 +- arch/src/main/scala/examples/toy/README.md | 167 -------- .../scala/examples/toy/ToyBuckyBall.scala | 147 +------ .../examples/toy/balldomain/BallDomain.scala | 93 +--- .../scala/examples/toy/balldomain/DISA.scala | 6 - .../toy/balldomain/DomainDecoder.scala | 15 +- .../toy/balldomain/bbus/busRegister.scala | 43 +- .../toy/balldomain/configs/default.json | 9 - .../toy/balldomain/emptyball/EmptyBall.scala | 19 +- .../examples/toy/balldomain/rs/README.md | 214 ---------- .../toy/balldomain/rs/rsRegister.scala | 28 -- arch/src/main/scala/framework/README.md | 284 ------------ .../framework/balldomain/bbus/bbus.scala | 39 +- .../bbus/cmdrouter/CmdReqRouter.scala | 11 +- .../bbus/cmdrouter/CmdRespRouter.scala | 11 +- .../balldomain/bbus/cmdrouter/CmdRouter.scala | 27 +- .../balldomain/bbus/memrouter/memRouter.scala | 51 +-- .../balldomain/bbus/pmc/BallCyclePMC.scala | 10 +- .../framework/balldomain/blink/baseball.scala | 2 +- .../framework/balldomain/blink/blink.scala | 68 ++- .../balldomain/configs/BallDomainParam.scala | 28 ++ .../framework/balldomain/configs/default.json | 7 + .../balldomain}/prototype/README.md | 0 .../balldomain}/prototype/relu/README.md | 0 .../balldomain}/prototype/relu/Relu.scala | 48 +-- .../balldomain}/prototype/relu/ReluBall.scala | 23 +- .../relu/configs/ReluBallParam.scala | 21 + .../prototype/relu/configs/default.json | 4 + .../balldomain}/prototype/vector/README.md | 0 .../prototype/vector/VecBall.scala | 24 +- .../prototype/vector/VecCtrlUnit.scala | 30 +- .../prototype/vector/VecEXUnit.scala | 89 ++++ .../prototype/vector/VecLoadUnit.scala | 53 ++- .../prototype/vector/VecStoreUnit.scala | 63 ++- .../prototype/vector/VecUnit.scala | 44 +- .../prototype/vector/bond/BondWrapper.scala | 14 + .../prototype/vector/bond/README.md | 0 .../prototype/vector/bond/vvv.scala | 29 ++ .../vector/configs/VectorBallParam.scala | 26 ++ .../prototype/vector/configs/default.json | 8 + .../balldomain}/prototype/vector/op/README.md | 0 .../prototype/vector/op/cascade.scala | 28 +- .../balldomain/prototype/vector/op/mul.scala | 37 ++ .../prototype/vector/thread/BaseThread.scala | 13 + .../prototype/vector/thread/CasThread.scala | 16 + .../prototype/vector/thread/MulThread.scala | 16 + .../prototype/vector/thread/README.md | 0 .../prototype/vector/warp/MeshWarp.scala | 84 ++++ .../prototype/vector/warp/README.md | 0 .../balldomain/rs/reservationStation.scala | 83 ++-- .../scala/framework/balldomain/rs/rob.scala | 78 ++-- .../scala/framework/builtin/BaseConfigs.scala | 82 ---- .../main/scala/framework/builtin/README.md | 340 --------------- .../framework/builtin/configs/default.json | 21 - .../scala/framework/builtin/util/README.md | 225 ---------- .../framework/core/configs/CoreParam.scala | 23 + .../scala/framework/core/configs/default.json | 7 + .../framework/core/rocket/LazyRoCCBB.scala | 13 +- .../scala/framework/frontend/Frontend.scala | 50 +-- .../framework/frontend/FrontendParam.scala | 8 - .../frontend/configs/FrontendParam.scala | 20 + .../framework/frontend/configs/default.json | 4 + .../frontend/decoder/GobalDecoder.scala | 22 +- .../frontend/globalrs/GlobalROB.scala | 79 ++-- .../globalrs/GlobalReservationStation.scala | 57 +-- .../scala/framework/gpdomain/GPDomain.scala | 55 +-- .../gpdomain/configs/GpDomainParam.scala | 21 + .../framework/gpdomain/configs/default.json | 4 +- .../gpdomain/sequencer/decoder/DISA.scala | 8 +- .../sequencer/decoder/DomainDecoder.scala | 18 +- .../scala/framework/memdomain/MemDomain.scala | 151 +++---- .../memdomain/backend/MemManager.scala | 33 +- .../memdomain/backend/accpipe/AccPipe.scala | 28 +- .../memdomain/backend/accpipe/BankPipe.scala | 20 +- .../memdomain/backend/banks/SramBank.scala | 18 +- .../memdomain/backend/banks/SramIO.scala | 34 +- .../memdomain/configs/MemDomainParam.scala | 29 ++ .../framework/memdomain/configs/default.json | 6 +- .../memdomain/frontend/MemController.scala | 76 +--- .../frontend/cmd_channel/decoder/DISA.scala | 7 - .../cmd_channel/decoder/DomainDecoder.scala | 27 +- .../cmd_channel/rs/reservationStation.scala | 46 +- .../frontend/cmd_channel/rs/rob.scala | 25 +- .../frontend/outside_channel/MemLoader.scala | 36 +- .../frontend/outside_channel/MemStorer.scala | 37 +- .../outside_channel/dma/BBStreamReader.scala | 181 ++++++++ .../outside_channel/dma/BBStreamWriter.scala | 139 ++++++ .../frontend/outside_channel/dma/DMA.scala | 321 -------------- .../frontend/outside_channel/tlb/BBTLB.scala | 76 ---- .../outside_channel/tlb/BBTLBIO.scala | 171 ++++++++ .../frontend/outside_channel/tlb/README.md | 252 ----------- .../frontend/outside_channel/tlb/TLB.scala | 160 +++++++ .../outside_channel/tlb/TLBCluster.scala | 126 +++--- .../outside_channel/tlb/TLBEntry.scala | 40 ++ .../outside_channel/tlb/spec-BBTLB.md | 29 -- .../outside_channel/tlb/spec-BBTLBCluster.md | 88 ---- .../memdomain/midend/MemScheduler.scala | 35 +- .../memdomain/utils/pmc/MemCyclePMC.scala | 18 +- .../scala/framework/top/GlobalConfig.scala | 38 ++ .../{builtin/util => utils}/Util.scala | 2 +- .../prototype/abft/ABFTSystolicArray.scala | 336 --------------- .../abft/ABFTSystolicArrayBall.scala | 55 --- .../prototype/abft/configs/ABFTConfig.scala | 61 --- .../scala/prototype/abft/configs/default.json | 10 - arch/src/main/scala/prototype/conv/Conv.scala | 322 -------------- .../main/scala/prototype/conv/ConvBall.scala | 55 --- .../prototype/conv/configs/ConvConfig.scala | 61 --- .../scala/prototype/conv/configs/default.json | 10 - .../scala/prototype/format/Arithmetic.scala | 34 -- .../scala/prototype/format/Dataformat.scala | 54 --- .../src/main/scala/prototype/format/README.md | 134 ------ .../scala/prototype/ibuki/matmul/LIF.scala | 224 ---------- .../ibuki/matmul/LIFMatmulBall.scala | 43 -- .../scala/prototype/im2col/Im2colBall.scala | 47 -- .../src/main/scala/prototype/im2col/README.md | 111 ----- .../im2col/configs/Im2colConfig.scala | 62 --- .../prototype/im2col/configs/default.json | 10 - .../main/scala/prototype/im2col/im2col.scala | 216 ---------- .../scala/prototype/matrix/MatrixBall.scala | 50 --- .../src/main/scala/prototype/matrix/README.md | 153 ------- .../prototype/matrix/bbfpIns_decode.scala | 110 ----- .../scala/prototype/matrix/bbfp_buffer.scala | 77 ---- .../scala/prototype/matrix/bbfp_control.scala | 109 ----- .../main/scala/prototype/matrix/bbfp_ex.scala | 302 ------------- .../scala/prototype/matrix/bbfp_load.scala | 69 --- .../main/scala/prototype/matrix/bbfp_pe.scala | 403 ------------------ .../matrix/configs/MatrixConfig.scala | 62 --- .../prototype/matrix/configs/default.json | 10 - .../scala/prototype/nagisa/matmul/Macro.scala | 337 --------------- .../nagisa/matmul/MacroMatmulBall.scala | 53 --- .../main/scala/prototype/nnlut/NNLut.scala | 213 --------- .../scala/prototype/nnlut/NNLutBall.scala | 49 --- .../prototype/nnlut/configs/NNLutConfig.scala | 61 --- .../prototype/nnlut/configs/default.json | 10 - .../prototype/relu/configs/ReluConfig.scala | 62 --- .../scala/prototype/relu/configs/default.json | 10 - .../main/scala/prototype/transfer/README.md | 206 --------- .../scala/prototype/transfer/Transfer.scala | 206 --------- .../prototype/transfer/TransferBall.scala | 47 -- .../transfer/configs/TransferConfig.scala | 62 --- .../prototype/transfer/configs/default.json | 10 - .../main/scala/prototype/transpose/README.md | 115 ----- .../scala/prototype/transpose/Transpose.scala | 166 -------- .../prototype/transpose/TransposeBall.scala | 47 -- .../transpose/configs/TransposeConfig.scala | 62 --- .../prototype/transpose/configs/default.json | 10 - .../scala/prototype/vector/VecEXUnit.scala | 98 ----- .../prototype/vector/bond/BondWrapper.scala | 20 - .../scala/prototype/vector/bond/vvv.scala | 42 -- .../prototype/vector/configs/VecConfig.scala | 62 --- .../prototype/vector/configs/default.json | 10 - .../main/scala/prototype/vector/op/mul.scala | 52 --- .../prototype/vector/thread/BaseThread.scala | 40 -- .../prototype/vector/thread/CasThread.scala | 19 - .../prototype/vector/thread/MulThread.scala | 19 - .../prototype/vector/warp/MeshWarp.scala | 139 ------ .../scala/prototype/vector/warp/VecBall.scala | 89 ---- .../main/scala/sims/verify/TargetConfig.scala | 64 ++- scripts/replace-content.py | 7 +- 162 files changed, 2047 insertions(+), 9365 deletions(-) delete mode 100644 arch/src/main/scala/examples/BuckyBallConfig.scala delete mode 100644 arch/src/main/scala/examples/README.md delete mode 100644 arch/src/main/scala/examples/toy/README.md delete mode 100644 arch/src/main/scala/examples/toy/balldomain/configs/default.json delete mode 100644 arch/src/main/scala/examples/toy/balldomain/rs/README.md delete mode 100644 arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala delete mode 100644 arch/src/main/scala/framework/README.md create mode 100644 arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/configs/default.json rename arch/src/main/scala/{ => framework/balldomain}/prototype/README.md (100%) rename arch/src/main/scala/{ => framework/balldomain}/prototype/relu/README.md (100%) rename arch/src/main/scala/{ => framework/balldomain}/prototype/relu/Relu.scala (81%) rename arch/src/main/scala/{ => framework/balldomain}/prototype/relu/ReluBall.scala (65%) create mode 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"edu.berkeley.cs" %% "rocketchip" % "1.6" + "edu.berkeley.cs" %% "rocketchip" % "1.6", + "com.lihaoyi" %% "os-lib" % "0.10.0", + "com.lihaoyi" %% "upickle" % "3.3.1" ) ) ) diff --git a/arch/src/main/scala/examples/BuckyBallConfig.scala b/arch/src/main/scala/examples/BuckyBallConfig.scala deleted file mode 100644 index 8e3ce957..00000000 --- a/arch/src/main/scala/examples/BuckyBallConfig.scala +++ /dev/null @@ -1,56 +0,0 @@ -package examples - -import chisel3._ -import framework.builtin.BaseConfig -import examples.toy.BuckyballToyConfig -import scala.io.Source -import upickle.default._ - -object BuckyballConfigs { - val defaultConfig = BaseConfig() - val toyConfig = BuckyballToyConfig.defaultConfig - - // Actually used configuration - val customConfig = toyConfig - - type CustomBuckyballConfig = BaseConfig - - /** - * Load global config from JSON file - * Usage: BuckyballConfigs.fromJson("path/to/config.json") - */ - def fromJson(path: String): BaseConfig = { - val jsonStr = Source.fromFile(path).mkString - read[BaseConfig](jsonStr) - } - - /** - * Load global config from JSON string - */ - def fromJsonString(json: String): BaseConfig = - read[BaseConfig](json) - - /** - * Save global config to JSON file - */ - def toJsonFile(config: BaseConfig, path: String): Unit = { - val jsonStr = write(config, indent = 2) - java.nio.file.Files.write( - java.nio.file.Paths.get(path), - jsonStr.getBytes - ) - } - -} - -// Get currently selected configuration -object CustomBuckyballConfig { - import BuckyballConfigs._ - def apply(): CustomBuckyballConfig = BuckyballConfigs.customConfig - - /** - * Create config from JSON file - * Usage: CustomBuckyballConfig.fromJson("configs/my_config.json") - */ - def fromJson(path: String): CustomBuckyballConfig = BuckyballConfigs.fromJson(path) -} diff --git a/arch/src/main/scala/examples/README.md b/arch/src/main/scala/examples/README.md deleted file mode 100644 index c9cc7c49..00000000 --- a/arch/src/main/scala/examples/README.md +++ /dev/null @@ -1,346 +0,0 @@ -# Buckyball Example Configurations - -## Overview - -This directory contains example configurations and reference implementations of the Buckyball framework, demonstrating how to configure and extend Buckyball systems. Located at `arch/src/main/scala/examples`, it serves as the configuration layer, providing configuration templates and system instances for developers. - -Main components include: -- **BuckyballConfig.scala**: Global configuration parameter definitions -- **toy/**: Complete example system implementation with custom coprocessor and CSR extensions - -## Code Structure - -``` -examples/ -├── BuckyballConfig.scala - Global configuration definitions -└── toy/ - Complete example system - ├── balldomain/ - Ball domain component implementation - │ ├── BallDomain.scala - Ball domain top-level - │ ├── bbus/ - Ball bus registration - │ │ └── busRegister.scala - │ ├── rs/ - Ball RS registration - │ │ └── rsRegister.scala - │ └── decoder/ - Ball decoder (if exists) - ├── CustomConfigs.scala - System configuration composition - └── ToyBuckyball.scala - System top-level module -``` - -### File Dependencies - -**BuckyballConfig.scala** (Base Configuration Layer) -- Defines global configuration parameters and defaults -- Inherited and extended by all other configuration files -- Provides system-level configuration interface - -**toy/CustomConfigs.scala** (Configuration Composition Layer) -- Inherits from BuckyballConfig and adds custom parameters -- Composes multiple configuration fragments into complete configuration -- Provides configuration support for ToyBuckyball - -**toy/ToyBuckyball.scala** (System Instantiation Layer) -- Uses CustomConfigs to instantiate complete system -- Serves as entry point for Mill build -- Generates final Verilog code - -## Module Details - -### BuckyballConfig.scala - -**Main Function**: Define global configuration parameters for the Buckyball framework - -**Key Components**: - -```scala -object BuckyballConfigs { - val defaultConfig = BaseConfig - val toyConfig = BuckyballToyConfig.defaultConfig - - // Actually used configuration - val customConfig = toyConfig - - type CustomBuckyballConfig = BaseConfig -} -``` - -**Configuration Selection**: -The framework uses `customConfig` to select the active configuration. This allows easy switching between different system configurations. - -**Input/Output**: -- Input: No direct input, parameters passed through configuration system -- Output: Configuration parameters for use by other modules -- Edge cases: Configuration conflicts resolved by priority-based overriding - -### toy/ - Example System - -The toy system demonstrates a complete Buckyball implementation with various Ball devices. - -#### toy/ToyBuckyball.scala - -**Main Function**: System top-level module, instantiates complete toy system - -**Key Components**: - -```scala -class ToyBuckyball(implicit b: CustomBuckyballConfig, p: Parameters) extends LazyRoCC { - override lazy val module = new ToyBuckyballModuleImp(this) -} - -class ToyBuckyballModuleImp(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) { - // Global Decoder - val globalDecoder = Module(new GlobalDecoder) - - // Global Reservation Station (with ROB) - val globalRS = Module(new GlobalReservationStation) - - // Ball Domain (regular Module, not LazyModule) - val ballDomain = Module(new BallDomain) - - // Memory Domain (complete domain with DMA+TLB+SRAM) - val memDomain = LazyModule(new MemDomain) - - // Connect components - globalDecoder.io.rocc <> io.cmd - globalRS.io.decode <> globalDecoder.io.issue - ballDomain.io.issue <> globalRS.io.ballIssue - memDomain.module.io.issue <> globalRS.io.memIssue - // ... more connections -} -``` - -**Build Flow**: -1. Load configuration from BuckyballConfig -2. Instantiate ToyBuckyball LazyRoCC module -3. Generate Verilog through ChiselStage -4. Output to generated-src directory - -**Input/Output**: -- Input: RoCC interface commands from Rocket core -- Output: RoCC interface responses, busy signals -- Edge cases: Configuration errors cause build failure - -#### toy/balldomain/ - Ball Domain Components - -**BallDomain.scala**: Ball domain top-level module -- Integrates Ball Decoder, local Ball RS, and BBus -- Provides single-channel interface to Global RS -- Routes commands to appropriate Ball devices - -**bbus/busRegister.scala**: Ball bus registration -```scala -class BBusModule extends BBus { - // Register Ball device generators - registerBall(() => new VecBall, ballId = 0.U) - registerBall(() => new MatrixBall, ballId = 1.U) - registerBall(() => new TransposeBall, ballId = 2.U) - registerBall(() => new Im2colBall, ballId = 3.U) - registerBall(() => new ReluBall, ballId = 4.U) -} -``` - -**rs/rsRegister.scala**: Ball RS device registration -```scala -class BallRSModule extends BallReservationStation { - // Register Ball device information - registerBallInfo(name = "VecBall", bid = 0, latency = 10) - registerBallInfo(name = "MatrixBall", bid = 1, latency = 20) - registerBallInfo(name = "TransposeBall", bid = 2, latency = 15) - registerBallInfo(name = "Im2colBall", bid = 3, latency = 15) - registerBallInfo(name = "ReluBall", bid = 4, latency = 10) -} -``` - -#### toy/CustomConfigs.scala - -**Main Function**: Compose multiple configuration fragments for the toy system - -**Configuration Composition**: - -```scala -object BuckyballToyConfig { - val defaultConfig = BaseConfig( - opcodes = OpcodeSet.custom3, - inputType = UInt(8.W), // INT8 input - accType = UInt(32.W), // INT32 accumulator - veclane = 16, // 16-element vectors - accveclane = 4, // 4-element accumulator vectors - rob_entries = 16, // 16 ROB entries - sp_banks = 4, // 4 scratchpad banks - acc_banks = 8, // 8 accumulator banks - sp_capacity = CapacityInKilobytes(256), // 256KB scratchpad - acc_capacity = CapacityInKilobytes(64), // 64KB accumulator - numVecPE = 16, // 16 vector PEs - numVecThread = 16 // 16 vector threads - ) -} -``` - -**Configuration Parameters**: -- **opcodes**: Custom instruction opcode set (custom3 = 0x7b) -- **inputType**: Data type for input operands -- **accType**: Data type for accumulator -- **veclane**: Number of elements per vector lane -- **rob_entries**: Reorder buffer depth -- **Memory configuration**: Bank counts and capacities -- **Vector configuration**: PE count and thread count - -## Usage Guide - -### Building the Toy System - -**Generate Verilog**: -```bash -cd arch -mill arch.runMain examples.toy.ToyBuckyball -``` - -**Generated Files**: -- Location: `arch/generated-src/toy/` -- Files: Verilog (.v), FIRRTL (.fir), annotation (.anno.json) - -### Custom Configuration Development - -**Steps**: -1. Copy `CustomConfigs.scala` as template -2. Modify configuration parameters to meet requirements -3. Implement necessary custom components -4. Update top-level module to reference new configuration -5. Register Ball devices in BBus and Ball RS - -**Example: Adding New Ball Device**: - -1. Implement Ball device: -```scala -class MyCustomBall(implicit b: CustomBuckyballConfig, p: Parameters) - extends Module with BallRegist { - // Implement Ball interfaces - val io = IO(new BlinkIO) - def ballId = 6.U // Assign unique Ball ID - // ... implementation -} -``` - -2. Register in BBusModule: -```scala -registerBall(() => new MyCustomBall, ballId = 6.U) -``` - -3. Register in BallRSModule: -```scala -registerBallInfo(name = "MyCustomBall", bid = 6, latency = 12) -``` - -### Configuration Best Practices - -**Parameter Selection**: -1. **Memory Sizes**: Balance capacity vs. area - - Scratchpad: Main working memory for data - - Accumulator: Smaller, used for accumulation results - -2. **ROB Depth**: Impacts instruction-level parallelism - - Larger ROB: More in-flight instructions, higher parallelism - - Smaller ROB: Lower area, simpler control logic - -3. **Bank Counts**: Affects memory bandwidth - - More banks: Higher parallel access bandwidth - - Fewer banks: Simpler arbitration, lower area - -4. **Vector Configuration**: Depends on workload - - Vector lane width: Match data parallelism - - PE/Thread count: Balance performance vs. area - -**Common Configurations**: - -```scala -// High-performance configuration -val highPerfConfig = BaseConfig( - veclane = 32, // Wider vectors - rob_entries = 32, // Deeper ROB - sp_banks = 8, // More banks - sp_capacity = CapacityInKilobytes(512) -) - -// Area-optimized configuration -val smallConfig = BaseConfig( - veclane = 8, - rob_entries = 8, - sp_banks = 2, - sp_capacity = CapacityInKilobytes(64) -) -``` - -### Important Notes - -1. **Configuration Priority**: Later configurations in the chain override earlier ones with same parameter names -2. **Dependency Management**: Ensure custom component dependencies are correctly declared in configuration -3. **Build Path**: Generated file paths specified by TargetDirAnnotation -4. **Parameter Validation**: Configuration parameters validated during instantiation; invalid configurations cause build failure -5. **Ball ID Uniqueness**: Each Ball device must have unique ID across the system -6. **Bank Access Rules**: Remember op1 and op2 cannot access same bank simultaneously - -## System Architecture - -The toy system implements the complete Buckyball architecture: - -``` -┌─────────────────────────────────────────────────────────┐ -│ Rocket Core (via RoCC) │ -└────────────────────┬────────────────────────────────────┘ - │ - ┌────────▼────────┐ - │ Global Decoder │ - └────────┬────────┘ - │ - ┌────────▼────────┐ - │ Global RS │ - │ (with ROB) │ - └────┬──────┬─────┘ - │ │ - ┌───────▼──┐ ┌▼──────────┐ - │ Ball │ │ Mem │ - │ Domain │ │ Domain │ - │ │ │ │ - │ ┌─────┐ │ │ ┌──────┐ │ - │ │BBus │ │ │ │ DMA │ │ - │ └──┬──┘ │ │ │+TLB │ │ - │ │ │ │ └───┬──┘ │ - │ ┌──▼───┐│ │ │ │ - │ │Balls ││ │ ┌──▼──┐ │ - │ └──────┘│ │ │Mem │ │ - └──────┬───┘ │ │Ctrl │ │ - │ │ └─────┘ │ - │ └─────┬────┘ - │ │ - ┌───▼───────────▼───┐ - │ Memory Controller│ - │ (Scratchpad+Acc) │ - └───────────────────┘ -``` - -**Supported Ball Devices**: -- **VecBall** (ID=0): Vector operations -- **MatrixBall** (ID=1): Matrix multiplication (various formats) -- **TransposeBall** (ID=2): Matrix transpose -- **Im2colBall** (ID=3): Im2col transformation for convolution -- **ReluBall** (ID=4): ReLU activation function - -## Related Documentation - -- [Framework Overview](../framework/README.md) - Core framework architecture -- [Ball Domain Details](toy/balldomain/README.md) - Ball domain implementation -- [Prototype Ball Devices](../prototype/README.md) - Ball device implementations -- [Memory Domain](../framework/builtin/memdomain/README.md) - Memory subsystem -- [Simulation Guide](../sims/README.md) - Running simulations - -## Troubleshooting - -**Issue**: Build fails with "Ball ID conflict" -- **Solution**: Ensure each Ball device has unique ID in both BBus and RS registration - -**Issue**: Generated Verilog has timing violations -- **Solution**: Reduce clock frequency or optimize critical paths - -**Issue**: Simulation shows incorrect results -- **Solution**: Verify Ball device implementation and memory access patterns - -**Issue**: Configuration parameter not taking effect -- **Solution**: Check configuration priority and ensure parameter is in correct config fragment diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 840cfd4f..1c61c600 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -6,20 +6,15 @@ import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.subsystem.SystemBusKey import freechips.rocketchip.tile._ import examples.toy.ToyBuckyball -import framework.builtin.BaseConfig -import examples.BuckyballConfigs.CustomBuckyballConfig -import examples.CustomBuckyballConfig +import framework.top.GlobalConfig object BuckyballToyConfig { - - val defaultConfig = new BaseConfig( - bankNum = 32 - ) - + // 简化：直接使用GlobalConfig() + val defaultConfig = GlobalConfig() } class BuckyballCustomConfig( - buckyballConfig: CustomBuckyballConfig = CustomBuckyballConfig()) + buckyballConfig: GlobalConfig = GlobalConfig()) extends Config((site, here, up) => { case BuildRoCC => up(BuildRoCC) ++ Seq { (p: Parameters) => diff --git a/arch/src/main/scala/examples/toy/README.md b/arch/src/main/scala/examples/toy/README.md deleted file mode 100644 index 2ded842b..00000000 --- a/arch/src/main/scala/examples/toy/README.md +++ /dev/null @@ -1,167 +0,0 @@ -# Toy Buckyball Example Implementation - -## Overview - -This directory contains a complete example implementation of the Buckyball framework, demonstrating how to build a custom coprocessor based on the RoCC interface. Located in `arch/src/main/scala/examples/toy`, it serves as a reference implementation for the Buckyball system, integrating global decoder, Ball domain, and memory domain. - -Core components: -- **ToyBuckyball.scala**: Main RoCC coprocessor implementation -- **CustomConfigs.scala**: System configuration and RoCC integration -- **CSR.scala**: Custom control and status registers -- **balldomain/**: Ball domain related components - -## Code Structure - -``` -toy/ -├── ToyBuckyball.scala - Main coprocessor implementation -├── CustomConfigs.scala - Configuration definitions -├── CSR.scala - CSR implementation -└── balldomain/ - Ball domain components -``` - -### File Dependencies - -**ToyBuckyball.scala** (Core implementation layer) -- Extends LazyRoCCBB, implements RoCC coprocessor interface -- Integrates GlobalDecoder, BallDomain, MemDomain -- Manages TileLink connections and DMA components - -**CustomConfigs.scala** (Configuration layer) -- Defines BuckyballCustomConfig and BuckyballToyConfig -- Configures RoCC integration and system parameters -- Provides multi-core configuration support - -**CSR.scala** (Register layer) -- Implements FenceCSR control register -- Provides simple 64-bit register interface - -## Module Description - -### ToyBuckyball.scala - -**Main functionality**: Implements complete Buckyball RoCC coprocessor - -**Key components**: - -```scala -class ToyBuckyball(val b: CustomBuckyballConfig)(implicit p: Parameters) - extends LazyRoCCBB (opcodes = b.opcodes, nPTWPorts = 2) { - - val reader = LazyModule(new BBStreamReader(...)) - val writer = LazyModule(new BBStreamWriter(...)) - val xbar_node = TLXbar() -} -``` - -**System architecture**: -```scala -// Frontend: global decoder -val gDecoder = Module(new GlobalDecoder) - -// Backend: Ball domain and memory domain -val ballDomain = Module(new BallDomain) -val memDomain = Module(new MemDomain) - -// Response arbitration -val respArb = Module(new Arbiter(new RoCCResponseBB()(p), 2)) -``` - -**TileLink connections**: -```scala -xbar_node := TLBuffer() := reader.node -xbar_node := TLBuffer() := writer.node -id_node := TLWidthWidget(b.dma_buswidth/8) := TLBuffer() := xbar_node -``` - -**Inputs/Outputs**: -- Input: RoCC command interface, PTW interface -- Output: RoCC response, TileLink memory access -- Edge cases: Busy-wait handling during Fence operations - -### CustomConfigs.scala - -**Main functionality**: Defines system configuration and RoCC integration - -**Configuration class definition**: -```scala -class BuckyballCustomConfig( - buckyballConfig: CustomBuckyballConfig = CustomBuckyballConfig() -) extends Config((site, here, up) => { - case BuildRoCCBB => up(BuildRoCCBB) ++ Seq( - (p: Parameters) => { - val buckyball = LazyModule(new ToyBuckyball(buckyballConfig)) - buckyball - } - ) -}) -``` - -**System configuration**: -```scala -class BuckyballToyConfig extends Config( - new framework.core.rocket.WithNBuckyballCores(1) ++ - new BuckyballCustomConfig(CustomBuckyballConfig()) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new WithCustomBootROM ++ - new chipyard.config.AbstractConfig -) -``` - -**Multi-core support**: -```scala -class WithMultiRoCCToyBuckyball(harts: Int*) extends Config(...) -``` - -### CSR.scala - -**Main functionality**: Provides custom control and status registers - -**Implementation**: -```scala -object FenceCSR { - def apply(): UInt = RegInit(0.U(64.W)) -} -``` - -**Fence handling logic**: -```scala -val fenceCSR = FenceCSR() -val fenceSet = ballDomain.io.fence_o -val allDomainsIdle = !ballDomain.io.busy && !memDomain.io.busy - -when (fenceSet) { - fenceCSR := 1.U - io.cmd.ready := allDomainsIdle -} -``` - -## Usage - -### System Integration - -**RoCC interface integration**: -- Register coprocessor through BuildRoCCBB configuration key -- Support multi-core configuration -- Provide 2 PTW ports for address translation - -**Inter-domain communication**: -```scala -// BallDomain -> MemDomain bridge -ballDomain.io.sramRead <> memDomain.io.ballDomain.sramRead -ballDomain.io.sramWrite <> memDomain.io.ballDomain.sramWrite -``` - -**DMA connections**: -```scala -memDomain.io.dma.read.req <> outer.reader.module.io.req -memDomain.io.dma.write.req <> outer.writer.module.io.req -``` - -### Notes - -1. **Fence semantics**: Use CSR to implement Fence operation synchronization -2. **Busy-wait detection**: Assertion checks to prevent long simulation stalls -3. **TLB integration**: TLB functionality integrated in MemDomain -4. **Response arbitration**: BallDomain has higher priority than MemDomain -5. **Configuration dependencies**: Correctly configure CustomBuckyballConfig parameters diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 1d06cf67..736d181f 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -13,37 +13,27 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile.{LazyRoCC, LazyRoCCModuleImp} import chisel3.experimental.hierarchy.{Instance, Instantiate} -import framework.frontend.{Frontend, FrontendParam} -import framework.memdomain.{MemDomain, MemDomainParam} -import framework.gpdomain.{GpDomain, GpDomainParam} -import framework.memdomain.frontend.outside_channel.dma.{BBStreamReader, BBStreamWriter} -import examples.toy.balldomain.{BallDomain, BallDomainParam} -import examples.BuckyballConfigs.CustomBuckyballConfig - -class ToyBuckyball(val b: CustomBuckyballConfig)(implicit p: Parameters) +import framework.top.GlobalConfig +import examples.toy.balldomain.BallDomain +import framework.frontend.Frontend +import framework.gpdomain.GpDomain +import framework.memdomain.MemDomain + +class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) extends LazyRoCC(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { - val xLen = p(TileKey).core.xLen // the width of core's register file + // the width of core's register file + val xLen = p(TileKey).core.xLen val id_node = TLIdentityNode() val xbar_node = TLXbar() - val reader = LazyModule(new BBStreamReader(b.max_in_flight_mem_reqs, b.dma_buswidth, b.dma_maxbytes, b.bankWidth)(p)) - val writer = LazyModule(new BBStreamWriter(b.max_in_flight_mem_reqs, b.dma_buswidth, b.dma_maxbytes, b.bankWidth)(p)) - - // Note: BallDomain is now a regular Module, no longer a LazyModule - // Will be instantiated in module - - xbar_node := TLBuffer() := reader.node - xbar_node := TLBuffer() := writer.node - id_node := TLWidthWidget(b.dma_buswidth / 8) := TLBuffer() := xbar_node + xbar_node := TLBuffer() := id_node + xbar_node := TLBuffer() := id_node + id_node := TLWidthWidget(b.memDomain.dma_buswidth / 8) := TLBuffer() := xbar_node override lazy val module = new ToyBuckyballModule(this) - // The LazyRoCC class contains two TLOutputNode instances, atlNode and tlNode. - // atlNode connects into a tile-local arbiter along with the backside of the L1 instruction cache. - // tlNode connects directly to the L1-L2 crossbar. - // The corresponding Tilelink ports in the module implementation's IO bundle are atl and tl, respectively. override val tlNode = id_node override val atlNode = TLIdentityNode() val node = tlNode @@ -51,100 +41,26 @@ class ToyBuckyball(val b: CustomBuckyballConfig)(implicit p: Parameters) class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) with HasCoreParameters { import outer.b._ + val edge: TLEdgeOut = outer.id_node.edges.out.head + val b: GlobalConfig = outer.b - val tagWidth = 32 - -// ----------------------------------------------------------------------------- -// Frontend: TLB moved inside MemDomain -// ----------------------------------------------------------------------------- - val edge: TLEdgeOut = outer.id_node.edges.out.head + val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) + val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge)) + val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) -// ----------------------------------------------------------------------------- -// Frontend: Global Decoder + Global Reservation Station -// ----------------------------------------------------------------------------- - val b: CustomBuckyballConfig = outer.b - - // Frontend parameter - val frontendParam = FrontendParam( - rob_entries = b.rob_entries, - rs_out_of_order_response = b.rs_out_of_order_response - ) - - val frontend: Instance[Frontend] = Instantiate(new Frontend(frontendParam)) frontend.io.cmd.valid := io.cmd.valid frontend.io.cmd.bits.cmd := io.cmd.bits io.cmd.ready := frontend.io.cmd.ready -// ----------------------------------------------------------------------------- -// Backend: Mem Domain - complete domain containing DMA+TLB+SRAM -// ----------------------------------------------------------------------------- - // Load MemDomain config: try JSON file first, fallback to global config - val memDomainParam = - try { - MemDomainParam.fromJson("arch/src/main/scala/framework/memdomain/configs/default.json") - } catch { - case _: Exception => MemDomainParam.fromGlobal(b) - } - -// ----------------------------------------------------------------------------- -// Backend: Ball Domain -// ----------------------------------------------------------------------------- - // Load BallDomain config: try JSON file first, fallback to global config - val ballDomainParam = - try { - BallDomainParam.fromJson("arch/src/main/scala/examples/toy/balldomain/configs/default.json") - } catch { - case _: Exception => BallDomainParam.fromGlobal(b) - } - - // Require parameter matching between BallDomain and MemDomain - require( - ballDomainParam.bbusChannel == memDomainParam.bankChannel, - s"BallDomain bbusChannel (${ballDomainParam.bbusChannel}) must equal MemDomain bankChannel (${memDomainParam.bankChannel})" - ) - require( - ballDomainParam.numBanks == memDomainParam.bankNum, - s"BallDomain numBanks (${ballDomainParam.numBanks}) must equal MemDomain bankNum (${memDomainParam.bankNum})" - ) - require( - ballDomainParam.bankEntries == memDomainParam.bankEntries, - s"BallDomain bankEntries (${ballDomainParam.bankEntries}) must equal MemDomain bankEntries (${memDomainParam.bankEntries})" - ) - require( - ballDomainParam.bankWidth == memDomainParam.bankWidth, - s"BallDomain bankWidth (${ballDomainParam.bankWidth}) must equal MemDomain bankWidth (${memDomainParam.bankWidth})" - ) - require( - ballDomainParam.bankMaskLen == memDomainParam.bankMaskLen, - s"BallDomain bankMaskLen (${ballDomainParam.bankMaskLen}) must equal MemDomain bankMaskLen (${memDomainParam.bankMaskLen})" - ) - require( - ballDomainParam.rob_entries == memDomainParam.rob_entries, - s"BallDomain rob_entries (${ballDomainParam.rob_entries}) must equal MemDomain rob_entries (${memDomainParam.rob_entries})" - ) - - val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(ballDomainParam)(outer.p)) - // Frontend -> BallDomain ballDomain.global_issue_i <> frontend.io.ball_issue_o frontend.io.ball_complete_i <> ballDomain.global_complete_o - val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(memDomainParam)(edge)) - // Frontend -> MemDomain memDomain.io.global_issue_i <> frontend.io.mem_issue_o frontend.io.mem_complete_i <> memDomain.io.global_complete_o - // MemDomain -> DMA - memDomain.io.dma.read.req <> outer.reader.module.io.req - outer.reader.module.io.resp <> memDomain.io.dma.read.resp - memDomain.io.dma.write.req <> outer.writer.module.io.req - outer.writer.module.io.resp <> memDomain.io.dma.write.resp - - // DMA -> TLB (now through MemDomain) - outer.reader.module.io.tlb <> memDomain.io.tlb(1) - outer.writer.module.io.tlb <> memDomain.io.tlb(0) - // PTW connected to MemDomain's TLB (shared TLB has only 1 PTW port) io.ptw(0) <> memDomain.io.ptw(0) @@ -153,44 +69,17 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w memDomain.io.tlbExp(0).flush_skip := false.B memDomain.io.tlbExp(0).flush_retry := false.B - // Flush signals to DMA components (obtained from MemDomain's TLB exceptions) - outer.reader.module.io.flush := memDomain.io.tlbExp(0).flush() - outer.writer.module.io.flush := memDomain.io.tlbExp(0).flush() - -// ----------------------------------------------------------------------------- -// Backend: Gen Domain - General purpose domain (for T1 vector processor) -// ----------------------------------------------------------------------------- - // Load GpDomain config: try JSON file first, fallback to global config - val gpDomainParam = - try { - GpDomainParam.fromJson("arch/src/main/scala/framework/gpdomain/configs/default.json") - } catch { - case _: Exception => GpDomainParam.fromGlobal(b) - } - - val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(gpDomainParam)(outer.p)) - // Frontend -> GpDomain gpDomain.io.global_issue_i <> frontend.io.gp_issue_o frontend.io.gp_complete_i <> gpDomain.io.global_complete_o -// ----------------------------------------------------------------------------- -// Backend: Domain Bridge: BallDomain -> MemDomain -// ----------------------------------------------------------------------------- ballDomain.bankRead <> memDomain.io.ballDomain.bankRead ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite -// --------------------------------------------------------------------------- -// RoCC response and status signals -// --------------------------------------------------------------------------- - io.resp <> frontend.io.resp io.busy := frontend.io.busy io.interrupt := memDomain.io.tlbExp(0).interrupt -// --------------------------------------------------------------------------- -// Busy counter to prevent long simulation stalls -// --------------------------------------------------------------------------- val busy_counter = RegInit(0.U(32.W)) busy_counter := Mux(frontend.io.busy, busy_counter + 1.U, 0.U) assert(busy_counter < 10000.U, "ToyBuckyball: busy for too long!") diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 069518c1..c1cea833 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -3,108 +3,37 @@ package examples.toy.balldomain import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ -import examples.BuckyballConfigs.CustomBuckyballConfig -import examples.toy.balldomain.rs.BallRSModule +import framework.top.GlobalConfig import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} +import framework.balldomain.rs.BallReservationStation -object BallDomainParam { - implicit def rw: upickle.default.ReadWriter[BallDomainParam] = upickle.default.macroRW - - /** - * Load from JSON file - */ - def fromJson(path: String): BallDomainParam = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[BallDomainParam](jsonStr) - } - - /** - * Generate from global config - */ - def fromGlobal(global: framework.builtin.BaseConfig): BallDomainParam = { - BallDomainParam( - rob_entries = global.rob_entries, - numBanks = global.bankNum, - bbusChannel = global.bankChannel, - bankEntries = global.bankEntries, - bankWidth = global.bankWidth, - bankMaskLen = global.bankMaskLen, - emptyBallid = global.emptyBallid - ) - } - -} - -case class BallDomainParam( - rob_entries: Int, - numBanks: Int, - bbusChannel: Int, - bankEntries: Int, - bankWidth: Int, - bankMaskLen: Int, - emptyBallid: Int = 5) - extends SerializableModuleParameter { - override def toString: String = - s"""BallDomainParam - | ROB entries: $rob_entries - | Num banks: $numBanks - | BBus channel: $bbusChannel - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | Empty Ball ID: $emptyBallid - |""".stripMargin -} - -/** - * Ball Domain top level - uses new simplified BBus architecture - */ @instantiable -class BallDomain(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { +class BallDomain(val b: GlobalConfig) extends Module { @public - val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries)))) + val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(b)))) @public - val global_complete_o = IO(Decoupled(new GlobalRsComplete(parameter.rob_entries))) + val global_complete_o = IO(Decoupled(new GlobalRsComplete(b))) @public - val bankRead = IO(Vec( - parameter.numBanks, - Flipped(new BankRead( - parameter.bankEntries, - parameter.bankWidth, - parameter.rob_entries, - parameter.numBanks - )) - )) + val bankRead = IO(Vec(b.memDomain.bankNum, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec( - parameter.numBanks, - Flipped(new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.numBanks - )) - )) + val bankWrite = IO(Vec(b.memDomain.bankNum, Flipped(new BankWrite(b)))) // Create new BBus module - val bbus: Instance[BBusModule] = Instantiate(new BBusModule(parameter)) + val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) + val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) + val ballRs: Instance[BallReservationStation] = Instantiate(new BallReservationStation(b)) //--------------------------------------------------------------------------- // Global RS -> Decoder (receive global issue and construct PostGDCmd) //--------------------------------------------------------------------------- - val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(parameter)(p)) // Convert global RS issue to Decoder input format ballDecoder.raw_cmd_i.valid := global_issue_i.valid @@ -114,7 +43,6 @@ class BallDomain(val parameter: BallDomainParam)(implicit p: Parameters) //--------------------------------------------------------------------------- // Decoder -> Local BallRS (multi-channel issue to each Ball device) //--------------------------------------------------------------------------- - val ballRs: Instance[BallRSModule] = Instantiate(new BallRSModule(parameter)) // Connect decoded instruction and global rob_id ballRs.ball_decode_cmd_i.valid := ballDecoder.ball_decode_cmd_o.valid @@ -139,5 +67,4 @@ class BallDomain(val parameter: BallDomainParam)(implicit p: Parameters) //--------------------------------------------------------------------------- global_complete_o <> ballRs.complete_o - override lazy val desiredName = "BallDomain" } diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 433fc46a..ec5575e9 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -2,12 +2,6 @@ package examples.toy.balldomain import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ - -class BuckyballRawCmd(implicit p: Parameters) extends Bundle { - val cmd = new RoCCCommand -} object DISA { val BB_BBFP_MUL = BitPat("b0011010") // 26 diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index d1d5f739..a2ba9970 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -6,9 +6,10 @@ import chisel3.experimental.hierarchy.{instantiable, public} import org.chipsalliance.cde.config.Parameters import framework.frontend.decoder.{DomainId, PostGDCmd} import examples.toy.balldomain.DISA._ +import framework.top.GlobalConfig // Detailed decode output for Ball domain -class BallDecodeCmd(parameter: BallDomainParam) extends Bundle { +class BallDecodeCmd(numBanks: Int) extends Bundle { // Ball ID val bid = UInt(5.W) @@ -25,9 +26,9 @@ class BallDecodeCmd(parameter: BallDomainParam) extends Bundle { val special = UInt(40.W) // Ball operand bank IDs (now directly from rs1/rs2) - val op1_bank = UInt(log2Up(parameter.numBanks).W) - val op2_bank = UInt(log2Up(parameter.numBanks).W) - val wr_bank = UInt(log2Up(parameter.numBanks).W) + val op1_bank = UInt(log2Up(numBanks).W) + val op2_bank = UInt(log2Up(numBanks).W) + val wr_bank = UInt(log2Up(numBanks).W) val rs1 = UInt(64.W) val rs2 = UInt(64.W) @@ -51,14 +52,14 @@ object BallDefaultConstants { } @instantiable -class BallDomainDecoder(val parameter: BallDomainParam)(implicit p: Parameters) extends Module { +class BallDomainDecoder(val b: GlobalConfig) extends Module { import BallDefaultConstants._ @public - val raw_cmd_i = IO(Flipped(Decoupled(new PostGDCmd))) + val raw_cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) @public - val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(parameter))) + val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum))) val spAddrLen = 14 // b.spAddrLen replaced with constant diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index dc6721fe..5a19decd 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -4,39 +4,30 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.instantiable import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.bbus.BBus -import prototype.vector.configs.VecConfig -import prototype.matrix.configs.MatrixConfig -import prototype.im2col.configs.Im2colConfig -import prototype.transpose.configs.TransposeConfig -import prototype.relu.configs.ReluConfig -import prototype.transfer.configs.TransferConfig +import framework.balldomain.prototype.vector.configs.VectorBallParam +// import prototype.matrix.configs.MatrixConfig +// import prototype.im2col.configs.Im2colConfig +// import prototype.transpose.configs.TransposeConfig +// import prototype.relu.configs.ReluConfig +// import prototype.transfer.configs.TransferConfig /** * BBusModule - Ball bus module that directly extends BBus */ @instantiable -class BBusModule(parameter: BallDomainParam)(implicit p: Parameters) +class BBusModule(b: GlobalConfig) extends BBus( - parameter, + b, // Define Ball device generators to register Seq( - () => new prototype.vector.VecBall(VecConfig.fromBallDomain(parameter), 0), - () => new prototype.matrix.MatrixBall(MatrixConfig.fromBallDomain(parameter), 1), - () => new prototype.im2col.Im2colBall(Im2colConfig.fromBallDomain(parameter), 2), - () => new prototype.transpose.TransposeBall(TransposeConfig.fromBallDomain(parameter), 3), - () => new prototype.relu.ReluBall(ReluConfig.fromBallDomain(parameter), 4), - () => - new examples.toy.balldomain.emptyball.EmptyBall( - parameter, - 5, - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen - ), - () => new prototype.transfer.TransferBall(TransferConfig.fromBallDomain(parameter), 6) + () => new framework.balldomain.prototype.vector.VecBall(b, 0), + // () => new prototype.matrix.MatrixBall(MatrixConfig.fromBallDomain(parameter), 1), + // () => new prototype.im2col.Im2colBall(Im2colConfig.fromBallDomain(parameter), 2), + // () => new prototype.transpose.TransposeBall(TransposeConfig.fromBallDomain(parameter), 3), + // () => new prototype.relu.ReluBall(ReluConfig.fromBallDomain(parameter), 4), + () => new examples.toy.balldomain.emptyball.EmptyBall(b, 5) + // () => new prototype.transfer.TransferBall(TransferConfig.fromBallDomain(parameter), 6) ) - ) { - override lazy val desiredName = "BBusModule" -} + ) {} diff --git a/arch/src/main/scala/examples/toy/balldomain/configs/default.json b/arch/src/main/scala/examples/toy/balldomain/configs/default.json deleted file mode 100644 index 000d56bb..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/configs/default.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "rob_entries": 16, - "numBanks": 32, - "bbusChannel": 8, - "bankEntries": 128, - "bankWidth": 128, - "bankMaskLen": 16, - "emptyBallid": 5 -} diff --git a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala index 3354fb1e..ddbf5d61 100644 --- a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala +++ b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala @@ -3,29 +3,26 @@ package examples.toy.balldomain.emptyball import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} +import framework.top.GlobalConfig +import framework.balldomain.blink.{BallRegist, BlinkIO} @instantiable class EmptyBall( - parameter: BallDomainParam, - id: Int, - bankEntries: Int, - bankWidth: Int, - bankMaskLen: Int) + b: GlobalConfig, + id: Int) extends Module with BallRegist { @public - val io = IO(new Blink(parameter, bankEntries, bankWidth, bankMaskLen)) + val io = IO(new BlinkIO(b)) val ballId = id.U - def Blink: Blink = io + def Blink: BlinkIO = io io.cmdResp.valid := RegNext(io.cmdReq.valid) io.cmdResp.bits.rob_id := RegNext(io.cmdReq.bits.rob_id) io.cmdReq.ready := true.B - for (i <- 0 until parameter.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { io.bankRead(i).io.req.valid := false.B io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.req.bits.fromDMA := false.B @@ -36,7 +33,7 @@ class EmptyBall( io.bankWrite(i).io.req.valid := false.B io.bankWrite(i).io.req.bits.addr := 0.U io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) io.bankWrite(i).rob_id := 0.U io.bankWrite(i).bank_id := 0.U io.bankWrite(i).io.req.bits.wmode := false.B diff --git a/arch/src/main/scala/examples/toy/balldomain/rs/README.md b/arch/src/main/scala/examples/toy/balldomain/rs/README.md deleted file mode 100644 index 605b935a..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/rs/README.md +++ /dev/null @@ -1,214 +0,0 @@ -# Reservation Station & ROB - -## Overview - -This module implements the Reservation Station and Reorder Buffer (ROB) in the Buckyball system for out-of-order execution and instruction scheduling support. The reservation station manages instruction issue and completion, while ROB ensures instructions commit in program order, maintaining precise exception semantics. - -## File Structure - -``` -rs/ -├── reservationStation.scala - Reservation station implementation -└── rob.scala - Reorder buffer implementation -``` - -## Core Components - -### BallReservationStation - Ball Domain Reservation Station - -The reservation station is a key component connecting the instruction decoder and execution units, responsible for: - -**Main functionality**: -- Receives instructions from Ball domain decoder -- Dispatches to different execution units based on instruction type -- Manages instruction issue and completion status -- Generates RoCC responses - -**Supported execution units**: -- **ball1**: VecUnit (vector processing unit) -- **ball2**: BBFP (floating-point processing unit) -- **ball3**: im2col (image processing accelerator) -- **ball4**: transpose (matrix transpose accelerator) - -**Interface design**: -```scala -class BallReservationStation extends Module { - val io = IO(new Bundle { - // Instruction input - val ball_decode_cmd_i = Flipped(DecoupledIO(new BallDecodeCmd)) - - // RoCC response output - val rs_rocc_o = new Bundle { - val resp = DecoupledIO(new RoCCResponseBB) - val busy = Output(Bool()) - } - - // Execution unit interfaces - val issue_o = new BallIssueInterface // Issue interface - val commit_i = new BallCommitInterface // Commit interface - }) -} -``` - -**Instruction dispatch logic**: -```scala -// Dispatch instructions based on bid (Ball ID) -io.issue_o.ball1.valid := rob.io.issue.valid && rob.io.issue.bits.cmd.bid === 1.U // VecUnit -io.issue_o.ball2.valid := rob.io.issue.valid && rob.io.issue.bits.cmd.bid === 2.U // BBFP -io.issue_o.ball3.valid := rob.io.issue.valid && rob.io.issue.bits.cmd.bid === 3.U // im2col -io.issue_o.ball4.valid := rob.io.issue.valid && rob.io.issue.bits.cmd.bid === 4.U // transpose -``` - -### ROB - Reorder Buffer - -ROB implements sequential instruction management and out-of-order completion support: - -**Design features**: -- Uses FIFO queue to maintain instruction order -- Uses completion status table to track instruction execution status -- Supports out-of-order completion but in-order issue -- Provides ROB ID for instruction identification - -**Core data structures**: -```scala -class RobEntry extends Bundle { - val cmd = new BallDecodeCmd // Instruction content - val rob_id = UInt(log2Up(rob_entries).W) // ROB identifier -} -``` - -**State management**: -```scala -val robFifo = Module(new Queue(new RobEntry, rob_entries)) // Instruction queue -val robTable = Reg(Vec(rob_entries, Bool())) // Completion status table -val robIdCounter = RegInit(0.U(log2Up(rob_entries).W)) // ID counter -``` - -## Workflow - -### Instruction Allocation Flow -1. **Instruction enqueue**: Instructions from decoder enter ROB -2. **Assign ROB ID**: Allocate unique ROB ID to each instruction -3. **State initialization**: Mark as incomplete in completion status table - -```scala -when(io.alloc.fire) { - robIdCounter := robIdCounter + 1.U - robTable(robIdCounter) := false.B // Mark as incomplete -} -``` - -### Instruction Issue Flow -1. **Head check**: Check if ROB head instruction is incomplete -2. **Type dispatch**: Dispatch instruction to corresponding execution unit based on bid -3. **Ready control**: Only issue when target execution unit is ready - -```scala -val headEntry = robFifo.io.deq.bits -val headCompleted = robTable(headEntry.rob_id) -io.issue.valid := robFifo.io.deq.valid && !headCompleted -``` - -### Instruction Completion Flow -1. **Completion arbitration**: Multiple execution unit completion signals handled by arbiter -2. **State update**: Update completion status table based on ROB ID -3. **Queue dequeue**: Remove completed head instruction from ROB - -```scala -val completeArb = Module(new Arbiter(UInt(log2Up(rob_entries).W), 4)) -when(io.complete.fire) { - robTable(io.complete.bits) := true.B // Mark as completed -} -``` - -## Configuration Parameters - -### Key Configuration Items -- **rob_entries**: ROB entry count, affects out-of-order execution window size -- **Execution unit count**: Currently supports 4 Ball execution units -- **Arbitration strategy**: Uses round-robin arbitration for multiple completion signals - -### Performance Considerations -- **ROB size**: Larger ROB supports more out-of-order execution but increases hardware overhead -- **Issue bandwidth**: Currently maximum one instruction issued per cycle -- **Completion bandwidth**: Supports multiple instruction completions per cycle - -## Interface Protocol - -### BallIssueInterface - Issue Interface -```scala -class BallIssueInterface extends Bundle { - val ball1 = Decoupled(new BallRsIssue) // VecUnit issue - val ball2 = Decoupled(new BallRsIssue) // BBFP issue - val ball3 = Decoupled(new BallRsIssue) // im2col issue - val ball4 = Decoupled(new BallRsIssue) // transpose issue -} -``` - -### BallCommitInterface - Commit Interface -```scala -class BallCommitInterface extends Bundle { - val ball1 = Flipped(Decoupled(new BallRsComplete)) // VecUnit commit - val ball2 = Flipped(Decoupled(new BallRsComplete)) // BBFP commit - val ball3 = Flipped(Decoupled(new BallRsComplete)) // im2col commit - val ball4 = Flipped(Decoupled(new BallRsComplete)) // transpose commit -} -``` - -## Usage Examples - -### Basic Configuration -```scala -// Configure ROB size in CustomBuckyballConfig -class MyBuckyballConfig extends CustomBuckyballConfig { - override val rob_entries = 16 // 16-entry ROB -} - -// Instantiate reservation station -val reservationStation = Module(new BallReservationStation) -``` - -### Connecting Execution Units -```scala -// Connect VecUnit -vecUnit.io.cmd <> reservationStation.io.issue_o.ball1 -reservationStation.io.commit_i.ball1 <> vecUnit.io.resp - -// Connect BBFP -bbfp.io.cmd <> reservationStation.io.issue_o.ball2 -reservationStation.io.commit_i.ball2 <> bbfp.io.resp -``` - -## Debug and Monitoring - -### Status Signals -- **io.rs_rocc_o.busy**: Reservation station busy status -- **rob.io.empty**: ROB empty status -- **rob.io.full**: ROB full status - -### Performance Counters -The following performance counters can be added for monitoring: -- Instruction issue count -- Instruction completion count -- ROB utilization -- Load distribution across execution units - -## Extension Guide - -### Adding New Execution Units -1. Add new issue port in `BallIssueInterface` -2. Add corresponding commit port in `BallCommitInterface` -3. Add corresponding dispatch and arbitration logic in reservation station -4. Update completion signal arbiter port count - -### Optimization Suggestions -- **Multi-issue support**: Can be extended to issue multiple instructions per cycle -- **Dynamic scheduling**: Implement more complex scheduling algorithms -- **Load balancing**: Perform load balancing across multiple execution units of the same type - -## Related Documentation - -- [Ball Domain Overview](../README.md) -- [Ball Domain Bus](../bbus/README.md) -- [Image Processing Accelerator](../im2col/README.md) -- [Vector Processing Unit](../../../prototype/vector/README.md) diff --git a/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala b/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala deleted file mode 100644 index 39e80f15..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala +++ /dev/null @@ -1,28 +0,0 @@ -package examples.toy.balldomain.rs - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.instantiable -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.rs.{BallReservationStation, BallRsRegist} - -/** - * Ball RS module - references BBus mechanism, manages Ball device registration and connections - */ -@instantiable -class BallRSModule(parameter: BallDomainParam) - extends BallReservationStation( - parameter, - // Define Ball device information to register - Seq( - BallRsRegist(ballId = 0, ballName = "VecBall"), - BallRsRegist(ballId = 1, ballName = "MatrixBall"), - BallRsRegist(ballId = 2, ballName = "Im2colBall"), - BallRsRegist(ballId = 3, ballName = "TransposeBall"), - BallRsRegist(ballId = 4, ballName = "ReluBall"), - BallRsRegist(ballId = 5, ballName = "EmptyBall"), - BallRsRegist(ballId = 6, ballName = "TransferBall") - ) - ) { - override lazy val desiredName = "BallRSModule" -} diff --git a/arch/src/main/scala/framework/README.md b/arch/src/main/scala/framework/README.md deleted file mode 100644 index ceb657b9..00000000 --- a/arch/src/main/scala/framework/README.md +++ /dev/null @@ -1,284 +0,0 @@ -# Buckyball Framework Core - -## Overview - -This directory contains the core implementation of the Buckyball framework, serving as the foundation layer for the entire hardware architecture. Located at `arch/src/main/scala/framework`, it provides a complete implementation of processor cores, built-in components, and system interconnects. - -Main functional modules include: -- **builtin**: Built-in hardware component library, including memory domain and frontend modules -- **blink**: System interconnect and communication framework - -## Code Structure - -``` -framework/ -├── builtin/ - Built-in component library -│ ├── memdomain/ - Memory domain implementation -│ │ ├── dma/ - DMA engines (BBStreamReader/Writer) -│ │ ├── mem/ - Memory components (Scratchpad, Accumulator, SRAM banks) -│ │ ├── rs/ - Memory domain reservation station -│ │ ├── tlb/ - TLB implementation -│ │ ├── MemController.scala - Memory controller -│ │ ├── MemDomain.scala - Memory domain top-level -│ │ ├── MemLoader.scala - Load instruction handler -│ │ └── MemStorer.scala - Store instruction handler -│ ├── frontend/ - Frontend components -│ │ ├── GobalDecoder.scala - Global instruction decoder -│ │ ├── globalrs/ - Global reservation station -│ │ │ ├── GlobalReservationStation.scala -│ │ │ └── GlobalROB.scala - Global reorder buffer -│ │ └── rs/ - Ball domain reservation station -│ ├── util/ - Framework utility functions -│ └── BaseConfigs.scala - Base configuration parameters -└── blink/ - System interconnect framework - ├── baseball.scala - Ball device base trait - ├── blink.scala - Blink protocol definitions - └── bbus.scala - Ball bus implementation -``` - -### Module Dependencies - -``` -Application Layer → builtin components → blink interconnect → Physical interface - ↓ ↓ - Memory domain Ball protocol - Frontend System bus -``` - -## Module Details - -### builtin/ - Built-in Component Library - -**Main Function**: Provides standardized hardware component implementations - -**Component Categories**: - -#### memdomain/ - Memory Domain -The memory domain encapsulates all memory-related functionality: - -**Key Components**: -- **MemDomain.scala**: Top-level memory domain module - - Integrates MemController, MemLoader, MemStorer, and TLB - - Provides unified interface to Global RS - - Handles both load and store operations - -- **MemController.scala**: Memory controller - - Encapsulates Scratchpad and Accumulator - - Provides DMA and Ball Domain interfaces - - Handles bank arbitration and routing - -- **MemLoader.scala**: Load instruction handler - - Receives load instructions from reservation station - - Issues DMA read requests - - Writes data to Scratchpad/Accumulator - -- **MemStorer.scala**: Store instruction handler - - Receives store instructions from reservation station - - Reads data from Scratchpad/Accumulator - - Issues DMA write requests with data alignment and masking - -- **dma/**: DMA engines - - **BBStreamReader**: Streaming DMA read with TLB support - - **BBStreamWriter**: Streaming DMA write with alignment handling - - Transaction ID management for multiple outstanding requests - -- **mem/**: Memory components - - **Scratchpad.scala**: 4-bank scratchpad memory (256KB total) - - **AccBank.scala**: Accumulator bank with accumulation pipeline - - **SramBank.scala**: Generic single-port SRAM bank implementation - -- **rs/**: Memory domain reservation station - - **reservationStation.scala**: Local FIFO-based scheduler - - **rob.scala**: Local reorder buffer for memory instructions - - **ringFifo.scala**: Circular FIFO implementation - -- **tlb/**: Translation Lookaside Buffer - - Virtual to physical address translation - - Integrated with DMA engines - -#### frontend/ - Frontend Components -The frontend handles global instruction management: - -**Key Components**: -- **GobalDecoder.scala**: Global instruction decoder - - Classifies instructions into Ball/Memory/Fence types - - Constructs PostGDCmd for domain-specific decoders - - Interfaces with Global RS - -- **globalrs/**: Global reservation station - - **GlobalReservationStation.scala**: Central instruction manager - - Allocates ROB entries - - Issues instructions to Ball and Memory domains - - Handles instruction completion from both domains - - Manages Fence instruction synchronization - - **GlobalROB.scala**: Global reorder buffer - - Tracks instruction state across domains - - Supports out-of-order completion - - Sequential commit of completed instructions - -- **rs/**: Ball domain reservation station - - **reservationStation.scala**: Ball-specific scheduler - - **rob.scala**: Local ROB for Ball instructions - -#### util/ - Framework Utilities -Common utility functions and helper modules - -#### BaseConfigs.scala -**Configuration Parameters**: -```scala -case class BaseConfig( - veclane: Int = 16, // Vector lane width - accveclane: Int = 4, // Accumulator vector lane width - rob_entries: Int = 16, // Number of ROB entries - rs_out_of_order_response: Boolean = true, // Out-of-order response support - sp_banks: Int = 4, // Scratchpad bank count - acc_banks: Int = 8, // Accumulator bank count - sp_capacity: BuckyballMemCapacity = CapacityInKilobytes(256), - acc_capacity: BuckyballMemCapacity = CapacityInKilobytes(64), - spAddrLen: Int = 15, // SPAD address length - memAddrLen: Int = 32, // Memory address length - numVecPE: Int = 16, // Vector PEs per thread - numVecThread: Int = 16, // Vector threads - emptyBallid: Int = 5 // Empty ball ID -) -``` - -### blink/ - System Interconnect - -**Main Function**: Implements system-level interconnect and Ball protocol - -**Key Components**: -- **baseball.scala**: Ball device base trait - - Defines `BallRegist` trait for Ball device registration - - Provides common interface for all Ball devices - -- **blink.scala**: Blink protocol definitions - - Command/response interfaces - - Status and control signals - - SRAM read/write interfaces - -- **bbus.scala**: Ball bus implementation (BBus) - - Manages multiple Ball device connections - - Command router: Routes commands to appropriate Ball devices - - Bus router: Arbitrates Ball device responses - - Memory router: Handles memory access arbitration - - Performance monitoring counters - -**Interconnect Features**: -- Support for multiple bus protocols -- Arbitration and routing functionality -- Latency and bandwidth management -- Dynamic Ball device registration - -## Usage Guide - -### Framework Integration - -**Configuration System**: -```scala -class BuckyballConfig extends Config( - new WithBuiltinComponents ++ - new WithBlinkInterconnect ++ - new BaseConfig -) -``` - -**Module Instantiation**: -```scala -class BuckyballSystem(implicit p: Parameters) extends LazyModule { - // Memory domain - val memdomain = Module(new MemDomain) - - // Ball domain - val balldomain = Module(new BallDomain) - - // Global RS - val globalRS = Module(new GlobalReservationStation) - - // Connect modules - balldomain.io.issue <> globalRS.io.ballIssue - memdomain.io.issue <> globalRS.io.memIssue - globalRS.io.ballComplete <> balldomain.io.complete - globalRS.io.memComplete <> memdomain.io.complete -} -``` - -### Extension Development - -**Adding New Components**: -1. Create new component module in builtin directory -2. Implement standard Module interface -3. Register in configuration system -4. Update interconnect and routing logic - -**Custom Ball Device**: -1. Extend `BallRegist` trait -2. Implement Blink protocol interfaces -3. Register in BBus -4. Add to Ball RS device list - -### Design Principles - -1. **Parameter Passing**: Use Chipyard's Parameters system for configuration -2. **Clock Domains**: Pay attention to clock domain crossing between modules -3. **Reset Strategy**: Ensure proper reset sequencing and dependencies -4. **Performance Optimization**: Focus on critical paths and timing constraints -5. **Debug Support**: Integrate necessary debug and monitoring interfaces -6. **Memory Access**: Respect bank access constraints (op1 and op2 cannot access same bank) -7. **Handshake Protocols**: Use ready/valid handshake for all data transfers - -## Architecture Highlights - -### Instruction Flow -``` -RoCC → Global Decoder → Global RS → Ball Domain / Mem Domain - ↓ ↓ ↓ - Global ROB Ball Decoder Mem Decoder - (tracks state) ↓ ↓ - Ball Devices Loader/Storer - ↓ ↓ - MemController ← → MemController -``` - -### Memory Access Flow -``` -Ball Devices ──→ MemController ──→ Scratchpad (4 banks) - │ └→ Accumulator (8 banks) - │ -Mem Domain ──→ MemController - (Loader/Storer) │ - ↓ - DMA + TLB - ↓ - Main Memory -``` - -## Related Documentation - -- [Blink Interconnect System](blink/README.md) - System interconnect implementation -- [Built-in Components](builtin/README.md) - Standard hardware components -- [Memory Domain](builtin/memdomain/README.md) - Memory subsystem details -- [Frontend Components](builtin/frontend/README.md) - Instruction management -- [Buckyball Source Overview](../README.md) - Upper-level architecture - -## Performance Considerations - -1. **ROB Size**: 16 entries support up to 16 in-flight instructions -2. **Bank Parallelism**: 4 scratchpad + 8 accumulator banks enable parallel access -3. **Out-of-Order Execution**: Global RS supports out-of-order completion when enabled -4. **DMA Bandwidth**: 128-bit bus width provides high memory bandwidth -5. **Pipeline Depth**: Multi-stage pipeline allows high clock frequency - -## Common Issues and Solutions - -**Issue**: Instructions stall in Global RS -- **Solution**: Check ROB capacity and completion signals from domains - -**Issue**: Memory access conflicts -- **Solution**: Ensure op1 and op2 don't access same bank, respect bank boundaries - -**Issue**: DMA timeout -- **Solution**: Verify TLB configuration and page table walker connectivity - -**Issue**: Ball device not responding -- **Solution**: Check Ball device registration in BBus and RS device list diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index db2a2a58..3e4f8173 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -2,8 +2,8 @@ package framework.balldomain.bbus import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import examples.toy.balldomain.BallDomainParam +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.blink.BallRegist import framework.balldomain.bbus.pmc.BallCyclePMC @@ -21,40 +21,38 @@ class BBusConfigIO(numBalls: Int) extends Bundle { * BBus - Ball bus, manages connections and arbitration of multiple Ball devices */ @instantiable -class BBus(val parameter: BallDomainParam, ballGenerators: Seq[() => BallRegist with Module]) extends Module { +class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module]) extends Module { val numBalls = ballGenerators.length @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(parameter))))) + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(parameter)))) + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) @public val bankRead = IO(Vec( - parameter.numBanks, - Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.numBanks)) + b.memDomain.bankNum, + Flipped(new BankRead(b)) )) @public val bankWrite = IO(Vec( - parameter.numBanks, - Flipped(new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.numBanks - )) + b.memDomain.bankNum, + Flipped(new BankWrite(b)) )) // Instantiate all registered Balls - val balls = ballGenerators.map(gen => Module(gen())) + // Note: Since Instantiate requires 'new' expression and ballGenerators are functions, + // we use Module here. The balls themselves are @instantiable, but when instantiated + // from a function generator pattern, we use Module. This is acceptable as the balls + // are still properly instantiated and can be used with the hierarchy system. + val balls = ballGenerators.map(gen => gen()) // ----------------------------------------------------------------------------- // cmd router // ----------------------------------------------------------------------------- - val cmdRouter = Module(new CmdRouter(parameter, numBalls)) + val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b, numBalls)) val idle_ball = Wire(Vec(numBalls, Bool())) for (i <- 0 until numBalls) { idle_ball(i) := balls(i).Blink.cmdReq.ready @@ -81,12 +79,12 @@ class BBus(val parameter: BallDomainParam, ballGenerators: Seq[() => BallRegist // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- - val memoryrouter = Module(new MemRouter(parameter, numBalls, parameter.bbusChannel)) + val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b, numBalls, b.memDomain.bankChannel)) memoryrouter.io.bbusConfig_i <> cmdRouter.io.bbusConfig_o // Direct connection from balls to memory router (no ToVirtualLine) for (i <- 0 until numBalls) { - for (j <- 0 until parameter.numBanks) { + for (j <- 0 until b.memDomain.bankNum) { memoryrouter.io.bankRead_i(i)(j) <> balls(i).Blink.bankRead(j) memoryrouter.io.bankWrite_i(i)(j) <> balls(i).Blink.bankWrite(j) } @@ -98,7 +96,7 @@ class BBus(val parameter: BallDomainParam, ballGenerators: Seq[() => BallRegist // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- - val pmc = Module(new BallCyclePMC(parameter, numBalls)) + val pmc = Module(new BallCyclePMC(b, numBalls)) for (i <- 0 until numBalls) { pmc.io.cmdReq_i(i).valid := cmdRouter.io.cmdReq_i(i).fire @@ -108,5 +106,4 @@ class BBus(val parameter: BallDomainParam, ballGenerators: Seq[() => BallRegist pmc.io.cmdResp_o(i).bits := cmdRouter.io.cmdResp_o(i).bits } - override lazy val desiredName = "BBus" } diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala index 913e59c4..18c49dee 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala @@ -2,18 +2,18 @@ package framework.balldomain.bbus.cmdrouter import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.rs.BallRsIssue -class CmdReqRouter(val parameter: BallDomainParam, val numBalls: Int) extends Module { +class CmdReqRouter(val b: GlobalConfig, val numBalls: Int) extends Module { val io = IO(new Bundle { - val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(parameter)))) + val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b)))) val ballIdle = Input(Vec(numBalls, Bool())) - val cmdReq_o = Decoupled(new BallRsIssue(parameter)) + val cmdReq_o = Decoupled(new BallRsIssue(b)) }) - val arbiter = Module(new RRArbiter(new BallRsIssue(parameter), numBalls)) + val arbiter = Module(new RRArbiter(new BallRsIssue(b), numBalls)) for (i <- 0 until numBalls) { arbiter.io.in(i).valid := io.cmdReq_i(i).valid && io.ballIdle(i) @@ -23,5 +23,4 @@ class CmdReqRouter(val parameter: BallDomainParam, val numBalls: Int) extends Mo io.cmdReq_o <> arbiter.io.out - override lazy val desiredName = "CmdReqRouter" } diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala index 0d649b81..4a14fec1 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala @@ -2,17 +2,17 @@ package framework.balldomain.bbus.cmdrouter import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.rs.BallRsComplete -class CmdRespRouter(val parameter: BallDomainParam, val numBalls: Int) extends Module { +class CmdRespRouter(b: GlobalConfig, numBalls: Int) extends Module { val io = IO(new Bundle { - val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(parameter)))) - val cmdResp_o = Decoupled(new BallRsComplete(parameter)) + val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(b)))) + val cmdResp_o = Decoupled(new BallRsComplete(b)) }) - val arbiter = Module(new RRArbiter(new BallRsComplete(parameter), numBalls)) + val arbiter = Module(new RRArbiter(new BallRsComplete(b), numBalls)) for (i <- 0 until numBalls) { arbiter.io.in(i) <> io.cmdResp_i(i) @@ -20,5 +20,4 @@ class CmdRespRouter(val parameter: BallDomainParam, val numBalls: Int) extends M io.cmdResp_o <> arbiter.io.out - override lazy val desiredName = "CmdRespRouter" } diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala index f7779260..6766e152 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala @@ -2,22 +2,26 @@ package framework.balldomain.bbus.cmdrouter import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.bbus.BBusConfigIO +import framework.balldomain.bbus.cmdrouter.CmdReqRouter +import chisel3.experimental.hierarchy.{instantiable, public} -class CmdRouter(val parameter: BallDomainParam, val numBalls: Int) extends Module { +@instantiable +class CmdRouter(b: GlobalConfig, numBalls: Int) extends Module { + @public val io = IO(new Bundle { - val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(parameter)))) - val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(parameter)))) + val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b)))) + val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(b)))) val ballIdle = Input(Vec(numBalls, Bool())) - val cmdReq_o = Decoupled(new BallRsIssue(parameter)) - val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete(parameter))) + val cmdReq_o = Decoupled(new BallRsIssue(b)) + val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete(b))) val bbusConfig_o = Decoupled(new BBusConfigIO(numBalls)) }) - val reqRouter = Module(new CmdReqRouter(parameter, numBalls)) + val reqRouter = Module(new CmdReqRouter(b, numBalls)) reqRouter.io.cmdReq_i <> io.cmdReq_i reqRouter.io.ballIdle := io.ballIdle @@ -30,11 +34,10 @@ class CmdRouter(val parameter: BallDomainParam, val numBalls: Int) extends Modul io.bbusConfig_o.bits.src_bid := 0.U io.bbusConfig_o.bits.dst_bid := 0.U io.bbusConfig_o.bits.set := false.B - when(io.cmdReq_i(parameter.emptyBallid).valid) { + when(io.cmdReq_i(b.ballDomain.emptyBallid).valid) { io.bbusConfig_o.valid := true.B - io.bbusConfig_o.bits.src_bid := io.cmdReq_i(parameter.emptyBallid).bits.cmd.special(5, 0) - io.bbusConfig_o.bits.dst_bid := io.cmdReq_i(parameter.emptyBallid).bits.cmd.special(11, 6) - io.bbusConfig_o.bits.set := io.cmdReq_i(parameter.emptyBallid).bits.cmd.special(12, 12) + io.bbusConfig_o.bits.src_bid := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(5, 0) + io.bbusConfig_o.bits.dst_bid := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(11, 6) + io.bbusConfig_o.bits.set := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(12, 12) } - override lazy val desiredName = "CmdRouter" } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 01f43aad..553865a3 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -2,62 +2,25 @@ package framework.balldomain.bbus.memrouter import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.memdomain.backend.banks.{SramReadIO, SramReadReq, SramReadResp, SramWriteIO, SramWriteReq} import framework.balldomain.blink.{BankRead, BankWrite} import framework.balldomain.bbus.BBusConfigIO -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig @instantiable -class MemRouter(val parameter: BallDomainParam, val numBalls: Int, val bbusChannel: Int) - extends Module - with SerializableModule[BallDomainParam] { +class MemRouter(val b: GlobalConfig, val numBalls: Int, val bbusChannel: Int) extends Module { @public val io = IO(new Bundle { - val bankRead_i = Vec( - numBalls, - Vec( - parameter.numBanks, - new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.numBanks) - ) - ) - - val bankWrite_i = Vec( - numBalls, - Vec( - parameter.numBanks, - new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.numBanks - ) - ) - ) + val bankRead_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankRead(b))) + val bankWrite_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankWrite(b))) val bbusConfig_i = Flipped(Decoupled(new BBusConfigIO(numBalls))) // Output: bbusChannel channels to MemDomain frontend - val bankRead_o = Vec( - bbusChannel, - Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.numBanks)) - ) - - val bankWrite_o = Vec( - bbusChannel, - Flipped(new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.numBanks - )) - ) + val bankRead_o = Vec(bbusChannel, Flipped(new BankRead(b))) + val bankWrite_o = Vec(bbusChannel, Flipped(new BankWrite(b))) }) diff --git a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala index f0b12a68..b9264faf 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala @@ -2,22 +2,22 @@ package framework.balldomain.bbus.pmc import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.rs.BallRsIssue import framework.balldomain.rs.BallRsComplete -class BallCyclePMC(val parameter: BallDomainParam, val numBalls: Int) extends Module { +class BallCyclePMC(val b: GlobalConfig, val numBalls: Int) extends Module { val io = IO(new Bundle { - val cmdReq_i = Input(Vec(numBalls, Valid(new BallRsIssue(parameter)))) - val cmdResp_o = Input(Vec(numBalls, Valid(new BallRsComplete(parameter)))) + val cmdReq_i = Input(Vec(numBalls, Valid(new BallRsIssue(b)))) + val cmdResp_o = Input(Vec(numBalls, Valid(new BallRsComplete(b)))) val totalCycles = Output(Vec(numBalls, UInt(64.W))) }) val cycleCounter = RegInit(0.U(64.W)) cycleCounter := cycleCounter + 1.U - val startTime = Reg(Vec(parameter.rob_entries, UInt(64.W))) + val startTime = Reg(Vec(b.frontend.rob_entries, UInt(64.W))) val ballTotalCycles = RegInit(VecInit(Seq.fill(numBalls)(0.U(64.W)))) for (i <- 0 until numBalls) { diff --git a/arch/src/main/scala/framework/balldomain/blink/baseball.scala b/arch/src/main/scala/framework/balldomain/blink/baseball.scala index 25c0ce2f..7cfcbc2e 100644 --- a/arch/src/main/scala/framework/balldomain/blink/baseball.scala +++ b/arch/src/main/scala/framework/balldomain/blink/baseball.scala @@ -6,6 +6,6 @@ import org.chipsalliance.cde.config.Parameters // Base trait for Ball devices trait BallRegist { - def Blink: Blink + def Blink: BlinkIO def ballId: UInt } diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index 349e3d1f..f7eac718 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -2,9 +2,10 @@ package framework.balldomain.blink import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import chisel3.experimental.hierarchy.{instantiable, public} // Ball device status bundle class Status extends Bundle { @@ -18,51 +19,42 @@ class Status extends Bundle { } // BankRead with rob_id, bank_id -class BankRead( - val n: Int, - val w: Int, - rob_entries: Int, - total_banks: Int) - extends Bundle { - val io = new SramReadIO(n, w) +class BankRead(val b: GlobalConfig) extends Bundle { + val io = new SramReadIO(b) // Input because the outer layer has Flipped - val rob_id = Input(UInt(log2Up(rob_entries).W)) - val bank_id = Input(UInt(log2Up(total_banks).W)) + val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) } // BankWrite with rob_id, bank_id // wmode is in SramWriteIO.io.req.bits.wmode: true = accumulate (累加), false = overwrite (覆盖) -class BankWrite( - val n: Int, - val w: Int, - val mask_len: Int, - rob_entries: Int, - total_banks: Int) - extends Bundle { - val io = new SramWriteIO(n, w, mask_len) +class BankWrite(val b: GlobalConfig) extends Bundle { + val io = new SramWriteIO(b) // Input because the outer layer has Flipped - val rob_id = Input(UInt(log2Up(rob_entries).W)) - val bank_id = Input(UInt(log2Up(total_banks).W)) + val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) +} + +// Blink IO Bundle - interface for Ball devices +class BlinkIO(b: GlobalConfig) extends Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(b.memDomain.bankNum, Flipped(new BankRead(b))) + val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) + val status = new Status } // Standard interface for Ball devices // bankEntries, bankWidth, bankMaskLen come from MemDomain, not BallDomain -class Blink( - parameter: BallDomainParam, - bankEntries: Int, - bankWidth: Int, - bankMaskLen: Int) - extends Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val cmdResp = Decoupled(new BallRsComplete(parameter)) - - val bankRead = - Vec(parameter.numBanks, Flipped(new BankRead(bankEntries, bankWidth, parameter.rob_entries, parameter.numBanks))) - - val bankWrite = Vec( - parameter.numBanks, - Flipped(new BankWrite(bankEntries, bankWidth, bankMaskLen, parameter.rob_entries, parameter.numBanks)) - ) - - val status = new Status +@instantiable +class Blink(b: GlobalConfig) extends Module { + @public + val io = IO(new BlinkIO(b)) + + // Convenience aliases for backward compatibility + def cmdReq: DecoupledIO[BallRsIssue] = io.cmdReq + def cmdResp: DecoupledIO[BallRsComplete] = io.cmdResp + def bankRead: Vec[BankRead] = io.bankRead + def bankWrite: Vec[BankWrite] = io.bankWrite + def status: Status = io.status } diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala new file mode 100644 index 00000000..a6be8950 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -0,0 +1,28 @@ +package framework.balldomain.configs + +import upickle.default._ + +/** + * Ball ID映射配置 + */ +case class BallIdMapping( + ballId: Int, + ballName: String) + +/** + * BallDomain参数 + */ +case class BallDomainParam( + emptyBallid: Int, + ballIdMappings: Seq[BallIdMapping]) + +object BallDomainParam { + implicit val ballIdMappingRW: ReadWriter[BallIdMapping] = macroRW + implicit val rw: ReadWriter[BallDomainParam] = macroRW + + def apply(): BallDomainParam = { + val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/balldomain/configs/default.json").mkString + read[BallDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json new file mode 100644 index 00000000..62059e78 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -0,0 +1,7 @@ +{ + "emptyBallid": 5, + "ballIdMappings": [ + {"ballId": 0, "ballName": "VecBall"}, + {"ballId": 5, "ballName": "EmptyBall"} + ] +} diff --git a/arch/src/main/scala/prototype/README.md b/arch/src/main/scala/framework/balldomain/prototype/README.md similarity index 100% rename from arch/src/main/scala/prototype/README.md rename to arch/src/main/scala/framework/balldomain/prototype/README.md diff --git a/arch/src/main/scala/prototype/relu/README.md b/arch/src/main/scala/framework/balldomain/prototype/relu/README.md similarity index 100% rename from arch/src/main/scala/prototype/relu/README.md rename to arch/src/main/scala/framework/balldomain/prototype/relu/README.md diff --git a/arch/src/main/scala/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala similarity index 81% rename from arch/src/main/scala/prototype/relu/Relu.scala rename to arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index a183c7e6..ec198a0c 100644 --- a/arch/src/main/scala/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -1,42 +1,38 @@ -package prototype.relu +package framework.balldomain.prototype.relu import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import prototype.vector._ +import framework.balldomain.prototype.vector._ import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam import framework.balldomain.blink.Status -import prototype.relu.configs.ReluConfig +import framework.top.GlobalConfig +import framework.balldomain.prototype.relu.configs.ReluBallParam @instantiable -class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) - extends Module - with SerializableModule[ReluConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val bankWidth = parameter.bankWidth +class PipelinedRelu(val b: GlobalConfig) extends Module { + // Get parameters from ball's own config JSON file + val ballConfig = ReluBallParam() + val InputNum = ballConfig.InputNum + val inputWidth = ballConfig.inputWidth + val bankWidth = b.memDomain.bankWidth @public val io = IO(new Bundle { // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) // Connect to unified bank read/write interface val bankRead = - Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) + Vec(b.memDomain.bankNum, Flipped(new SramReadIO(b))) val bankWrite = Vec( - ballParam.numBanks, - Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen)) + b.memDomain.bankNum, + Flipped(new SramWriteIO(b)) ) // Status output @@ -62,9 +58,9 @@ class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) // Instruction registers val robid_reg = RegInit(0.U(10.W)) val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val iter_reg = RegInit(0.U(10.W)) val cycle_reg = RegInit(0.U(6.W)) // Batch iteration counter @@ -72,10 +68,10 @@ class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) // Precompute write data val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) + val writeMaskReg = Reg(Vec(b.memDomain.bankMaskLen, UInt(1.W))) // SRAM default assignment - for (i <- 0 until ballParam.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { io.bankRead(i).req.valid := false.B io.bankRead(i).req.bits.addr := 0.U io.bankRead(i).req.bits.fromDMA := false.B @@ -84,7 +80,7 @@ class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) io.bankWrite(i).req.valid := false.B io.bankWrite(i).req.bits.addr := 0.U io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(ballParam.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) } // cmd interface default assignment @@ -152,7 +148,7 @@ class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) // Precompute first write data (row 0, concatenated by column) writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) // Set write mask (write all) - for (i <- 0 until parameter.bankMaskLen) { + for (i <- 0 until b.memDomain.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } } @@ -203,7 +199,7 @@ class PipelinedRelu(val parameter: ReluConfig)(implicit p: Parameters) } } writeDataReg := 0.U - for (i <- 0 until parameter.bankMaskLen) { + for (i <- 0 until b.memDomain.bankMaskLen) { writeMaskReg(i) := 0.U } } diff --git a/arch/src/main/scala/prototype/relu/ReluBall.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala similarity index 65% rename from arch/src/main/scala/prototype/relu/ReluBall.scala rename to arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala index 2d352b1b..f1b99d73 100644 --- a/arch/src/main/scala/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala @@ -1,13 +1,12 @@ -package prototype.relu +package framework.balldomain.prototype.relu import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.relu.PipelinedRelu -import prototype.relu.configs.ReluConfig +import framework.balldomain.blink.{BallRegist, BlinkIO} +import framework.balldomain.prototype.relu.PipelinedRelu +import framework.top.GlobalConfig /** * ReluBall - A ReLU computation Ball that complies with the Blink protocol. @@ -15,24 +14,23 @@ import prototype.relu.configs.ReluConfig * then write back to Scratchpad. */ @instantiable -class ReluBall(config: ReluConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam +class ReluBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U + val io = IO(new BlinkIO(b)) + val ballId = id.U // Satisfy BallRegist requirements - def Blink: Blink = io + def Blink: BlinkIO = io // Instantiate PipelinedRelu computation unit - private val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(config)) + private val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(b)) // Connect command interface reluUnit.io.cmdReq <> io.cmdReq reluUnit.io.cmdResp <> io.cmdResp // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { reluUnit.io.bankRead(i) <> io.bankRead(i).io io.bankRead(i).rob_id := io.cmdReq.bits.rob_id io.bankRead(i).bank_id := i.U @@ -45,5 +43,4 @@ class ReluBall(config: ReluConfig, id: Int)(implicit p: Parameters) extends Modu // Pass through status signals io.status <> reluUnit.io.status - override lazy val desiredName: String = "ReluBall" } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala new file mode 100644 index 00000000..ba1a32b7 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala @@ -0,0 +1,21 @@ +package framework.balldomain.prototype.relu.configs + +import upickle.default._ + +/** + * ReluBall参数 + */ +case class ReluBallParam( + InputNum: Int, + inputWidth: Int) + +object ReluBallParam { + implicit val rw: ReadWriter[ReluBallParam] = macroRW + + def apply(): ReluBallParam = { + val jsonStr = + scala.io.Source.fromFile("arch/src/main/scala/framework/balldomain/prototype/relu/configs/default.json").mkString + read[ReluBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/default.json new file mode 100644 index 00000000..a4552216 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/default.json @@ -0,0 +1,4 @@ +{ + "InputNum": 16, + "inputWidth": 8 +} diff --git a/arch/src/main/scala/prototype/vector/README.md b/arch/src/main/scala/framework/balldomain/prototype/vector/README.md similarity index 100% rename from arch/src/main/scala/prototype/vector/README.md rename to arch/src/main/scala/framework/balldomain/prototype/vector/README.md diff --git a/arch/src/main/scala/prototype/vector/VecBall.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala similarity index 57% rename from arch/src/main/scala/prototype/vector/VecBall.scala rename to arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala index 8a5b92cc..eafdc52e 100644 --- a/arch/src/main/scala/prototype/vector/VecBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala @@ -1,35 +1,32 @@ -package prototype.vector +package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.vector.VecUnit -import prototype.vector.configs.VecConfig +import framework.balldomain.blink.{BallRegist, BlinkIO} +import framework.balldomain.prototype.vector.VecUnit +import framework.top.GlobalConfig /** * VecBall - A vector computation Ball that complies with the Blink protocol */ @instantiable -class VecBall(config: VecConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam +class VecBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U + val io = IO(new BlinkIO(b)) + val ballId = id.U - def Blink: Blink = io + def Blink: BlinkIO = io // Instantiate VecUnit - val vecUnit: Instance[VecUnit] = Instantiate(new VecUnit(parameter)) + val vecUnit: Instance[VecUnit] = Instantiate(new VecUnit(b)) // Connect command interface vecUnit.io.cmdReq <> io.cmdReq vecUnit.io.cmdResp <> io.cmdResp // Connect Bank interface - for (i <- 0 until parameter.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { vecUnit.io.bankRead(i) <> io.bankRead(i).io io.bankRead(i).rob_id := io.cmdReq.bits.rob_id io.bankRead(i).bank_id := i.U @@ -44,5 +41,4 @@ class VecBall(config: VecConfig, id: Int)(implicit p: Parameters) extends Module // Connect Status signals - directly obtained from internal unit io.status <> vecUnit.io.status - override lazy val desiredName = "VecBall" } diff --git a/arch/src/main/scala/prototype/vector/VecCtrlUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala similarity index 80% rename from arch/src/main/scala/prototype/vector/VecCtrlUnit.scala rename to arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala index afa37edf..d92e4bec 100644 --- a/arch/src/main/scala/prototype/vector/VecCtrlUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala @@ -1,40 +1,34 @@ -package prototype.vector +package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig @instantiable -class VecCtrlUnit(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { +class VecCtrlUnit(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val cmdResp_o = Decoupled(new BallRsComplete(parameter)) + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp_o = Decoupled(new BallRsComplete(b)) - val ctrl_ld_o = Decoupled(new ctrl_ld_req(parameter)) - val ctrl_st_o = Decoupled(new ctrl_st_req(parameter)) - val ctrl_ex_o = Decoupled(new ctrl_ex_req) + val ctrl_ld_o = Decoupled(new ctrl_ld_req(b)) + val ctrl_st_o = Decoupled(new ctrl_st_req(b)) + val ctrl_ex_o = Decoupled(new ctrl_ex_req(b)) val cmdResp_i = Flipped(Valid(new Bundle { val commit = Bool() })) // from store unit }) - val rob_id_reg = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) val iter = RegInit(0.U(10.W)) - val op1_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val op2_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val wr_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val wr_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility val is_acc = RegInit(false.B) // Deprecated: use wmode instead val has_send = RegInit(false.B) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala new file mode 100644 index 00000000..f025af87 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala @@ -0,0 +1,89 @@ +package framework.balldomain.prototype.vector + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.prototype.vector.warp.MeshWarp +import framework.balldomain.prototype.vector.configs.VectorBallParam + +class ctrl_ex_req(b: GlobalConfig) extends Bundle { + val iter = UInt(10.W) +} + +class ld_ex_req(b: GlobalConfig) extends Bundle { + val config = VectorBallParam() + val op1 = Vec(config.lane, UInt(config.inputWidth.W)) + val op2 = Vec(config.lane, UInt(config.inputWidth.W)) + val iter = UInt(10.W) +} + +@instantiable +class VecEXUnit(val b: GlobalConfig) extends Module { + val config = VectorBallParam() + val InputNum = config.lane + val inputWidth = config.inputWidth + val accWidth = config.outputWidth + + @public + val io = IO(new Bundle { + val ctrl_ex_i = Flipped(Decoupled(new ctrl_ex_req(b))) + val ld_ex_i = Flipped(Decoupled(new ld_ex_req(b))) + + val ex_st_o = Decoupled(new ex_st_req(b)) + }) + + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) + + val meshWarp = Module(new MeshWarp(config)) + + // Thread ID for MeshWarp (always use thread 0 for now) + val threadId = RegInit(0.U(10.W)) + + // Initialize default values for all signals + io.ctrl_ex_i.ready := false.B + io.ex_st_o.valid := false.B + io.ex_st_o.bits.rst := VecInit(Seq.fill(InputNum)(0.U(accWidth.W))) + io.ex_st_o.bits.iter := 0.U + + // Initialize MeshWarp input signals with default values + meshWarp.io.in.valid := false.B + meshWarp.io.in.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + meshWarp.io.in.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + meshWarp.io.in.bits.thread_id := threadId + meshWarp.io.out.ready := false.B + +// ----------------------------------------------------------------------------- +// Set registers when Ctrl instruction arrives +// ----------------------------------------------------------------------------- + io.ctrl_ex_i.ready := state === idle + when(io.ctrl_ex_i.fire) { + threadId := 0.U // Use thread 0 for computation + state := busy + } + +// ----------------------------------------------------------------------------- +// Accept read results from load unit and perform computation +// ----------------------------------------------------------------------------- + io.ld_ex_i.ready := state === busy && meshWarp.io.in.ready + when(io.ld_ex_i.valid) { + meshWarp.io.in.valid := true.B + meshWarp.io.in.bits.op1 := io.ld_ex_i.bits.op1 + meshWarp.io.in.bits.op2 := io.ld_ex_i.bits.op2 + meshWarp.io.in.bits.thread_id := threadId + } + +// ----------------------------------------------------------------------------- +// Send computation results to store unit for write-back +// ----------------------------------------------------------------------------- + io.ex_st_o.valid := meshWarp.io.out.valid + meshWarp.io.out.ready := io.ex_st_o.ready + + when(io.ex_st_o.fire) { + io.ex_st_o.bits.rst := meshWarp.io.out.bits.res + io.ex_st_o.bits.iter := io.ld_ex_i.bits.iter // Use iter from ld_ex_i + } + +} diff --git a/arch/src/main/scala/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala similarity index 78% rename from arch/src/main/scala/prototype/vector/VecLoadUnit.scala rename to arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 0240119a..e06729a6 100644 --- a/arch/src/main/scala/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -1,47 +1,42 @@ -package prototype.vector +package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ import framework.memdomain.backend.banks.{SramReadReq, SramReadResp} -import examples.toy.balldomain.BallDomainParam - -class ctrl_ld_req(parameter: BallDomainParam) extends Bundle { - val op1_bank = UInt(log2Up(parameter.numBanks).W) - val op1_bank_addr = UInt(log2Up(parameter.bankEntries).W) - val op2_bank = UInt(log2Up(parameter.numBanks).W) - val op2_bank_addr = UInt(log2Up(parameter.bankEntries).W) +import framework.top.GlobalConfig +import framework.balldomain.prototype.vector.configs.VectorBallParam + +class ctrl_ld_req(b: GlobalConfig) extends Bundle { + val op1_bank = UInt(log2Up(b.memDomain.bankNum).W) + val op1_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) + val op2_bank = UInt(log2Up(b.memDomain.bankNum).W) + val op2_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) val iter = UInt(10.W) val mode = UInt(1.W) } @instantiable -class VecLoadUnit(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val bankWidth = parameter.bankWidth - val rob_id_width = log2Up(parameter.rob_entries) +class VecLoadUnit(val b: GlobalConfig) extends Module { + val config = VectorBallParam() + val InputNum = config.lane + val inputWidth = config.inputWidth + val bankWidth = b.memDomain.bankWidth + val rob_id_width = log2Up(b.frontend.rob_entries) @public val io = IO(new Bundle { - val bankReadReq = Vec(parameter.numBanks, Decoupled(new SramReadReq(parameter.bankEntries))) - val bankReadResp = Vec(parameter.numBanks, Flipped(Decoupled(new SramReadResp(bankWidth)))) - val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req(parameter))) - val ld_ex_o = Decoupled(new ld_ex_req(parameter)) + val bankReadReq = Vec(b.memDomain.bankNum, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(b.memDomain.bankNum, Flipped(Decoupled(new SramReadResp(b)))) + val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req(b))) + val ld_ex_o = Decoupled(new ld_ex_req(b)) }) - val op1_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val op2_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val op1_addr = RegInit(0.U(log2Up(parameter.bankEntries).W)) - val op2_addr = RegInit(0.U(log2Up(parameter.bankEntries).W)) + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val iter = RegInit(0.U(10.W)) val iter_counter = RegInit(0.U(10.W)) val mode = RegInit(0.U(1.W)) @@ -56,7 +51,7 @@ class VecLoadUnit(val parameter: BallDomainParam)(implicit p: Parameters) val ld_ex_iter_reg = RegInit(0.U(10.W)) // Default assignment for each bank read request - for (i <- 0 until parameter.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { io.bankReadReq(i).valid := false.B io.bankReadReq(i).bits.fromDMA := false.B io.bankReadReq(i).bits.addr := 0.U diff --git a/arch/src/main/scala/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala similarity index 63% rename from arch/src/main/scala/prototype/vector/VecStoreUnit.scala rename to arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 485fd989..993bf696 100644 --- a/arch/src/main/scala/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -1,53 +1,48 @@ -package prototype.vector +package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ import framework.memdomain.backend.banks.SramWriteIO -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig +import framework.balldomain.prototype.vector.configs.VectorBallParam -class ctrl_st_req(parameter: BallDomainParam) extends Bundle { - val wr_bank = UInt(log2Up(parameter.numBanks).W) - val wr_bank_addr = UInt(log2Up(parameter.bankEntries).W) +class ctrl_st_req(b: GlobalConfig) extends Bundle { + val wr_bank = UInt(log2Up(b.memDomain.bankNum).W) + val wr_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) val iter = UInt(10.W) } -class ex_st_req(parameter: BallDomainParam) extends Bundle { - // Derived parameters - val InputNum = 16 - val accWidth = 32 - // Use accumulator type, 32 bits +class ex_st_req(b: GlobalConfig) extends Bundle { + val config = VectorBallParam() + val InputNum = config.lane + val accWidth = config.outputWidth + // Use accumulator type val rst = Vec(InputNum, UInt(accWidth.W)) val iter = UInt(10.W) } @instantiable -class VecStoreUnit(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val accWidth = 32 +class VecStoreUnit(val b: GlobalConfig) extends Module { + val config = VectorBallParam() + val InputNum = config.lane + val accWidth = config.outputWidth @public val io = IO(new Bundle { - val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req(parameter))) - val ex_st_i = Flipped(Decoupled(new ex_st_req(parameter))) + val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req(b))) + val ex_st_i = Flipped(Decoupled(new ex_st_req(b))) // Unified bank write interface (writes use accumulate mode) val bankWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) + Vec(b.memDomain.bankNum, Flipped(new SramWriteIO(b))) val cmdResp_o = Valid(new Bundle { val commit = Bool() }) }) - val wr_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val wr_bank_addr = RegInit(0.U(log2Up(parameter.bankEntries).W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val iter = RegInit(0.U(10.W)) val iter_counter = RegInit(0.U(10.W)) @@ -75,17 +70,17 @@ class VecStoreUnit(val parameter: BallDomainParam)(implicit p: Parameters) acc.req.valid := false.B acc.req.bits.addr := 0.U acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) - acc.req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(false.B)) + acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) } val waddr = wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) when(io.ex_st_i.fire) { - for (i <- 0 until parameter.numBanks / 2) { + for (i <- 0 until b.memDomain.bankNum / 2) { when(waddr(0) === 0.U) { io.bankWrite(i).req.valid := true.B io.bankWrite(i).req.bits.addr := wr_bank_addr + (iter_counter(log2Ceil(InputNum) - 1, 0) >> 1.U) // Each accumulator bank stores InputNum/numBanks elements - val elementsPerBank = InputNum / parameter.numBanks * 2 + val elementsPerBank = InputNum / b.memDomain.bankNum * 2 val startIdx = i * elementsPerBank val endIdx = startIdx + elementsPerBank - 1 @@ -93,24 +88,24 @@ class VecStoreUnit(val parameter: BallDomainParam)(implicit p: Parameters) val bankData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) io.bankWrite(i).req.bits.data := bankData - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) }.otherwise { - io.bankWrite(i + parameter.numBanks / 2).req.valid := true.B - io.bankWrite(i + parameter.numBanks / 2).req.bits.addr := wr_bank_addr + (iter_counter( + io.bankWrite(i + b.memDomain.bankNum / 2).req.valid := true.B + io.bankWrite(i + b.memDomain.bankNum / 2).req.bits.addr := wr_bank_addr + (iter_counter( log2Ceil(InputNum) - 1, 0 ) >> 1.U) // Each accumulator bank stores InputNum/numBanks elements - val elementsPerBank = InputNum / parameter.numBanks * 2 + val elementsPerBank = InputNum / b.memDomain.bankNum * 2 val startIdx = i * elementsPerBank val endIdx = startIdx + elementsPerBank - 1 // Pack corresponding elements into a UInt val bankData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - io.bankWrite(i + parameter.numBanks / 2).req.bits.data := bankData + io.bankWrite(i + b.memDomain.bankNum / 2).req.bits.data := bankData - io.bankWrite(i + parameter.numBanks / 2).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + io.bankWrite(i + b.memDomain.bankNum / 2).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) } } iter_counter := iter_counter + 1.U diff --git a/arch/src/main/scala/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala similarity index 72% rename from arch/src/main/scala/prototype/vector/VecUnit.scala rename to arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index 05f81f77..e0045334 100644 --- a/arch/src/main/scala/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -1,38 +1,36 @@ -package prototype.vector +package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import prototype.vector._ +import framework.balldomain.prototype.vector._ import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam +import framework.top.GlobalConfig import framework.balldomain.blink.Status +import framework.balldomain.prototype.vector.configs.VectorBallParam @instantiable -class VecUnit(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - using default values for compatibility - val InputNum = 16 // Default value, should be derived from parameter if needed - val inputWidth = 8 // UInt8 - val accWidth = 32 // UInt32 - val bankWidth = parameter.bankWidth +class VecUnit(val b: GlobalConfig) extends Module { + // Get parameters from ball's own config JSON file + val ballConfig = VectorBallParam() + val InputNum = ballConfig.lane + val inputWidth = ballConfig.inputWidth + val accWidth = ballConfig.outputWidth + val bankWidth = b.memDomain.bankWidth @public val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val cmdResp = Decoupled(new BallRsComplete(parameter)) + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) // Connect to unified bank read/write interface - val bankRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) + val bankRead = Vec(b.memDomain.bankNum, Flipped(new SramReadIO(b))) // Connect to unified bank write interface val bankWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) + Vec(b.memDomain.bankNum, Flipped(new SramWriteIO(b))) // Status output val status = new Status @@ -41,16 +39,16 @@ class VecUnit(val parameter: BallDomainParam)(implicit p: Parameters) // ----------------------------------------------------------------------------- // VECCTRLUNIT // ----------------------------------------------------------------------------- - val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(parameter)) + val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(b)) VecCtrlUnit.io.cmdReq <> io.cmdReq io.cmdResp <> VecCtrlUnit.io.cmdResp_o // ----------------------------------------------------------------------------- // VECLOADUNIT // ----------------------------------------------------------------------------- - val VecLoadUnit: Instance[VecLoadUnit] = Instantiate(new VecLoadUnit(parameter)) + val VecLoadUnit: Instance[VecLoadUnit] = Instantiate(new VecLoadUnit(b)) VecLoadUnit.io.ctrl_ld_i <> VecCtrlUnit.io.ctrl_ld_o - for (i <- 0 until parameter.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { io.bankRead(i).req <> VecLoadUnit.io.bankReadReq(i) VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).resp } @@ -58,17 +56,17 @@ class VecUnit(val parameter: BallDomainParam)(implicit p: Parameters) // ----------------------------------------------------------------------------- // VECEX // ----------------------------------------------------------------------------- - val VecEX: Instance[VecEXUnit] = Instantiate(new VecEXUnit(parameter)) + val VecEX: Instance[VecEXUnit] = Instantiate(new VecEXUnit(b)) VecEX.io.ctrl_ex_i <> VecCtrlUnit.io.ctrl_ex_o VecEX.io.ld_ex_i <> VecLoadUnit.io.ld_ex_o // ----------------------------------------------------------------------------- // VECSTOREUNIT // ----------------------------------------------------------------------------- - val VecStoreUnit: Instance[VecStoreUnit] = Instantiate(new VecStoreUnit(parameter)) + val VecStoreUnit: Instance[VecStoreUnit] = Instantiate(new VecStoreUnit(b)) VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o - for (i <- 0 until parameter.numBanks) { + for (i <- 0 until b.memDomain.bankNum) { io.bankWrite(i) <> VecStoreUnit.io.bankWrite(i) } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/bond/BondWrapper.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/bond/BondWrapper.scala new file mode 100644 index 00000000..ba46b3da --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/bond/BondWrapper.scala @@ -0,0 +1,14 @@ +package framework.balldomain.prototype.vector.bond + +import chisel3._ +import chisel3.util._ + +abstract class BondWrapper { + val bondName = "vvv" + + def to[T](name: String)(body: => T): T = + body + + def from[T](name: String)(body: => T): T = + body +} diff --git a/arch/src/main/scala/prototype/vector/bond/README.md b/arch/src/main/scala/framework/balldomain/prototype/vector/bond/README.md similarity index 100% rename from arch/src/main/scala/prototype/vector/bond/README.md rename to arch/src/main/scala/framework/balldomain/prototype/vector/bond/README.md diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/bond/vvv.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/bond/vvv.scala new file mode 100644 index 00000000..5dcfffea --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/bond/vvv.scala @@ -0,0 +1,29 @@ +//===----------------------------------------------------------------------===// +// VVV Bond: +// Input: Vec, Vec +// Output: Vec +//===----------------------------------------------------------------------===// + +package framework.balldomain.prototype.vector.bond + +import chisel3._ +import chisel3.util._ +import framework.balldomain.prototype.vector.configs.VectorBallParam +import chisel3.experimental.hierarchy.{instantiable, public} + +@instantiable +class VVV(val config: VectorBallParam, val inputWidth: Int, val outputWidth: Int) extends Bundle { + val lane = config.lane + + @public + val in = Flipped(Decoupled(new Bundle { + val in1 = Vec(lane, UInt(inputWidth.W)) + val in2 = Vec(lane, UInt(inputWidth.W)) + })) + + @public + val out = Decoupled(new Bundle { + val out = Vec(lane, UInt(outputWidth.W)) + }) + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala new file mode 100644 index 00000000..00756d3f --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala @@ -0,0 +1,26 @@ +package framework.balldomain.prototype.vector.configs + +import upickle.default._ + +/** + * VectorBall参数 + */ +case class VectorBallParam( + InputNum: Int, + inputWidth: Int, + lane: Int, + outputWidth: Int, + numMulThreads: Int, + numCasThreads: Int) + +object VectorBallParam { + implicit val rw: ReadWriter[VectorBallParam] = macroRW + + def apply(): VectorBallParam = { + val jsonStr = scala.io.Source.fromFile( + "arch/src/main/scala/framework/balldomain/prototype/vector/configs/default.json" + ).mkString + read[VectorBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/default.json new file mode 100644 index 00000000..d5ad5924 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/default.json @@ -0,0 +1,8 @@ +{ + "InputNum": 16, + "inputWidth": 8, + "lane": 16, + "outputWidth": 32, + "numMulThreads": 16, + "numCasThreads": 16 +} diff --git a/arch/src/main/scala/prototype/vector/op/README.md b/arch/src/main/scala/framework/balldomain/prototype/vector/op/README.md similarity index 100% rename from arch/src/main/scala/prototype/vector/op/README.md rename to arch/src/main/scala/framework/balldomain/prototype/vector/op/README.md diff --git a/arch/src/main/scala/prototype/vector/op/cascade.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/op/cascade.scala similarity index 52% rename from arch/src/main/scala/prototype/vector/op/cascade.scala rename to arch/src/main/scala/framework/balldomain/prototype/vector/op/cascade.scala index 8b7b46d9..f0805623 100644 --- a/arch/src/main/scala/prototype/vector/op/cascade.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/op/cascade.scala @@ -1,17 +1,16 @@ -package prototype.vector.op +package framework.balldomain.prototype.vector.op import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config._ -import prototype.vector.thread.{BaseThread, ThreadBondKey, ThreadKey, ThreadOpKey} -import prototype.vector.bond.VVV +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.vector.bond.VVV -class CascadeOp(implicit p: Parameters) extends Module { - val lane = p(ThreadKey).get.lane - val bondParam = p(ThreadBondKey).get - val outputWidth = bondParam.outputWidth +class CascadeOp(val config: VectorBallParam) extends Module { + val lane = config.lane + val inputWidth = config.outputWidth // Cascade uses outputWidth as input + val outputWidth = config.outputWidth - val io = IO(new VVV()(p)) + val io = IO(new VVV(config, inputWidth, outputWidth)) val reg1 = RegInit(VecInit(Seq.fill(lane)(0.U(outputWidth.W)))) val reg2 = RegInit(VecInit(Seq.fill(lane)(0.U(outputWidth.W)))) @@ -39,14 +38,3 @@ class CascadeOp(implicit p: Parameters) extends Module { io.out.bits.out := VecInit(Seq.fill(lane)(0.U(outputWidth.W))) } } - -trait CanHaveCascadeOp { this: BaseThread => - - val cascadeOp = params(ThreadOpKey).filter(_.OpType == "cascade").map { opParam => - // println(s"[CascadeOp] Creating OpType: ${opParam.OpType}") - - Module(new CascadeOp()(params)) - } - - def getCascadeOp = cascadeOp -} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/op/mul.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/op/mul.scala new file mode 100644 index 00000000..03e9fe58 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/op/mul.scala @@ -0,0 +1,37 @@ +package framework.balldomain.prototype.vector.op + +import chisel3._ +import chisel3.util._ +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.vector.bond.VVV + +class MulOp(val config: VectorBallParam) extends Module { + val lane = config.lane + val inputWidth = config.inputWidth + val outputWidth = config.outputWidth + + val io = IO(new VVV(config, inputWidth, outputWidth)) + val reg1 = RegInit(VecInit(Seq.fill(lane)(0.U(inputWidth.W)))) + val reg2 = RegInit(VecInit(Seq.fill(lane)(0.U(inputWidth.W)))) + val cnt = RegInit(0.U(log2Ceil(lane).W)) + val active = RegInit(false.B) + + io.out.valid := active && io.out.ready + io.in.ready := io.out.ready + + when(io.in.valid) { + reg1 := io.in.bits.in1 + reg2 := io.in.bits.in2 + cnt := 0.U + active := true.B + }.elsewhen(active && io.out.ready) { + cnt := cnt + 1.U + when(cnt === (lane - 1).U) { + active := false.B + } + } + + for (i <- 0 until lane) { + io.out.bits.out(i) := Mux(io.out.valid, reg1(cnt) * reg2(i), 0.U) + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/thread/BaseThread.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/BaseThread.scala new file mode 100644 index 00000000..cf7469b7 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/BaseThread.scala @@ -0,0 +1,13 @@ +//===- BaseThread.scala - Level 1: Thread ---===// +package framework.balldomain.prototype.vector.thread + +import chisel3._ +import framework.balldomain.prototype.vector.configs.VectorBallParam + +//===----------------------------------------------------------------------===// +// BaseThread base class +//===----------------------------------------------------------------------===// +class BaseThread(val config: VectorBallParam, val opType: String) extends Module { + val io = IO(new Bundle {}) + val lane = config.lane +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/thread/CasThread.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/CasThread.scala new file mode 100644 index 00000000..fbd130f3 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/CasThread.scala @@ -0,0 +1,16 @@ +package framework.balldomain.prototype.vector.thread + +import chisel3._ +import chisel3.util._ +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.vector.bond.VVV +import framework.balldomain.prototype.vector.op.CascadeOp + +class CasThread(config: VectorBallParam) extends BaseThread(config, "cascade") { + val cascadeOp = Module(new CascadeOp(this.config)) + val vvvBond = IO(new VVV(this.config, this.config.outputWidth, this.config.outputWidth)) + + // Connect CascadeOp and VVVBond + cascadeOp.io.in <> vvvBond.in + cascadeOp.io.out <> vvvBond.out +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/thread/MulThread.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/MulThread.scala new file mode 100644 index 00000000..dc9b0025 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/MulThread.scala @@ -0,0 +1,16 @@ +package framework.balldomain.prototype.vector.thread + +import chisel3._ +import chisel3.util._ +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.vector.bond.VVV +import framework.balldomain.prototype.vector.op.MulOp + +class MulThread(config: VectorBallParam) extends BaseThread(config, "mul") { + val mulOp = Module(new MulOp(this.config)) + val vvvBond = IO(new VVV(this.config, this.config.inputWidth, this.config.outputWidth)) + + // Connect MulOp and VVVBond + mulOp.io.in <> vvvBond.in + mulOp.io.out <> vvvBond.out +} diff --git a/arch/src/main/scala/prototype/vector/thread/README.md b/arch/src/main/scala/framework/balldomain/prototype/vector/thread/README.md similarity index 100% rename from arch/src/main/scala/prototype/vector/thread/README.md rename to arch/src/main/scala/framework/balldomain/prototype/vector/thread/README.md diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/warp/MeshWarp.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/warp/MeshWarp.scala new file mode 100644 index 00000000..dc07b947 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/warp/MeshWarp.scala @@ -0,0 +1,84 @@ +package framework.balldomain.prototype.vector.warp + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.vector.thread._ + +class MeshWarpInput(val config: VectorBallParam) extends Bundle { + val op1 = Vec(config.lane, UInt(config.inputWidth.W)) + val op2 = Vec(config.lane, UInt(config.inputWidth.W)) + val thread_id = UInt(10.W) +} + +class MeshWarpOutput(val config: VectorBallParam) extends Bundle { + val res = Vec(config.lane, UInt(config.outputWidth.W)) +} + +class MeshWarp(val config: VectorBallParam) extends Module { + + val io = IO(new Bundle { + val in = Flipped(Decoupled(new MeshWarpInput(config))) + val out = Decoupled(new MeshWarpOutput(config)) + }) + + val mulThreads = (0 until config.numMulThreads).map { i => + Module(new MulThread(config)) + } + + val casThreads = (0 until config.numCasThreads).map { i => + Module(new CasThread(config)) + } + + io.in.ready := mulThreads(0).vvvBond.in.ready + + for (i <- 0 until config.numMulThreads) { + val mulThread = mulThreads(i) + val casThread = casThreads(i) + val mulBond = mulThread.vvvBond + val casBond = casThread.vvvBond + + // Connect mul thread output to cascade thread input + casBond.in.bits.in1 := mulBond.out.bits.out + mulBond.out.ready := casBond.in.ready + + // Connect cascade thread's second input and output ready signal + if (i == 0) { + casBond.in.bits.in2 := VecInit(Seq.fill(config.lane)(0.U(config.outputWidth.W))) + // First cascade thread's valid is determined by mulBond's output valid + casBond.in.valid := mulBond.out.valid + // First cascade thread's output ready is connected to next cascade thread's input ready + if (i < config.numCasThreads - 1) { + casBond.out.ready := casThreads(i + 1).vvvBond.in.ready + } + } else { + // Directly connect output to input + casBond.in.bits.in2 := casThreads(i - 1).vvvBond.out.bits.out + // casBond's valid is jointly determined by previous casBond's output valid and current mulBond's output valid + casBond.in.valid := casThreads(i - 1).vvvBond.out.valid || mulBond.out.valid + // Middle cascade thread's output ready is connected to next cascade thread's input ready + if (i < config.numCasThreads - 1) { + casBond.out.ready := casThreads(i + 1).vvvBond.in.ready + } + } + + // Only allow mulOp corresponding to thread_id to drive input + when(i.U === io.in.bits.thread_id && io.in.valid) { + mulBond.in.valid := true.B + mulBond.in.bits.in1 := io.in.bits.op1 + mulBond.in.bits.in2 := io.in.bits.op2 + io.in.ready := mulBond.in.ready + }.otherwise { + mulBond.in.valid := false.B + mulBond.in.bits.in1 := VecInit(Seq.fill(config.lane)(0.U(config.inputWidth.W))) + mulBond.in.bits.in2 := VecInit(Seq.fill(config.lane)(0.U(config.inputWidth.W))) + } + } + + // Connect output + val finalCasBond = casThreads(config.numCasThreads - 1).vvvBond + io.out.valid := finalCasBond.out.valid + io.out.bits.res := finalCasBond.out.bits.out + finalCasBond.out.ready := io.out.ready +} diff --git a/arch/src/main/scala/prototype/vector/warp/README.md b/arch/src/main/scala/framework/balldomain/prototype/vector/warp/README.md similarity index 100% rename from arch/src/main/scala/prototype/vector/warp/README.md rename to arch/src/main/scala/framework/balldomain/prototype/vector/warp/README.md diff --git a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala index 07482e5a..31719ec4 100644 --- a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala @@ -3,65 +3,58 @@ package framework.balldomain.rs import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public} -import examples.toy.balldomain._ -import framework.balldomain.blink.BallRegist - -// Ball device information - configuration information for registering Ball devices -case class BallRsRegist( - ballId: Int, - ballName: String) +import framework.top.GlobalConfig +import examples.toy.balldomain.BallDecodeCmd // Ball domain issue interface - includes global rob_id -class BallRsIssue(parameter: BallDomainParam) extends Bundle { - val cmd = new BallDecodeCmd(parameter) +class BallRsIssue(b: GlobalConfig) extends Bundle { + val cmd = new BallDecodeCmd(b.memDomain.bankNum) // Global ROB ID - val rob_id = UInt(log2Up(parameter.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } // Ball domain completion interface -class BallRsComplete(parameter: BallDomainParam) extends Bundle { - val rob_id = UInt(log2Up(parameter.rob_entries).W) +class BallRsComplete(b: GlobalConfig) extends Bundle { + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } // Generic Ball domain issue interface - supports dynamic number of Ball devices -class BallIssueInterface(numBalls: Int, parameter: BallDomainParam) extends Bundle { - val balls = Vec(numBalls, Decoupled(new BallRsIssue(parameter))) +class BallIssueInterface(b: GlobalConfig) extends Bundle { + val balls = Vec(b.memDomain.bankNum, Decoupled(new BallRsIssue(b))) } // Generic Ball domain completion interface - supports dynamic number of Ball devices -class BallCommitInterface(numBalls: Int, parameter: BallDomainParam) extends Bundle { - val balls = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(parameter)))) +class BallCommitInterface(b: GlobalConfig) extends Bundle { + val balls = Vec(b.memDomain.bankNum, Flipped(Decoupled(new BallRsComplete(b)))) } // Local Ball reservation station - simple FIFO scheduler @instantiable -class BallReservationStation(val parameter: BallDomainParam, BallRsRegists: Seq[BallRsRegist]) extends Module { - - val numBalls = BallRsRegists.length +class BallReservationStation(val b: GlobalConfig) extends Module { @public val ball_decode_cmd_i = IO(Flipped(new DecoupledIO(new Bundle { - val cmd = new BallDecodeCmd(parameter) + val cmd = new BallDecodeCmd(b.memDomain.bankNum) // Global ROB ID - val rob_id = UInt(log2Up(parameter.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) }))) // Rs -> BallController (multi-channel issue) @public - val issue_o = IO(new BallIssueInterface(numBalls, parameter)) + val issue_o = IO(new BallIssueInterface(b)) @public - val commit_i = IO(new BallCommitInterface(numBalls, parameter)) + val commit_i = IO(new BallCommitInterface(b)) // Output completion signal (with global rob_id, single channel) @public - val complete_o = IO(Decoupled(new BallRsComplete(parameter))) + val complete_o = IO(Decoupled(new BallRsComplete(b))) // Simple FIFO queue, only for buffering val fifo = Module(new Queue( new Bundle { - val cmd = new BallDecodeCmd(parameter) - val rob_id = UInt(log2Up(parameter.rob_entries).W) + val cmd = new BallDecodeCmd(b.memDomain.bankNum) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) }, entries = 4 )) // Small buffer is sufficient @@ -76,29 +69,47 @@ class BallReservationStation(val parameter: BallDomainParam, BallRsRegists: Seq[ // ----------------------------------------------------------------------------- val headEntry = fifo.io.deq.bits + // Build ballId to index mapping from config + // Config order should match the order in busRegister.scala + // Each index in issue_o.balls corresponds to a ball registered in BBus + val numConfiguredBalls = b.ballDomain.ballIdMappings.length + // Set issue signals for each Ball device - for (i <- 0 until numBalls) { - val ballId = BallRsRegists(i).ballId.U - issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === ballId - issue_o.balls(i).bits.cmd := headEntry.cmd - issue_o.balls(i).bits.rob_id := headEntry.rob_id + // Use configured ball id mappings: index i in issue_o.balls corresponds to ballIdMappings(i).ballId + for (i <- 0 until b.memDomain.bankNum) { + if (i < numConfiguredBalls) { + val configuredBallId = b.ballDomain.ballIdMappings(i).ballId.U + issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === configuredBallId + issue_o.balls(i).bits.cmd := headEntry.cmd + issue_o.balls(i).bits.rob_id := headEntry.rob_id + } else { + // Unused slots - no valid signal + issue_o.balls(i).valid := false.B + issue_o.balls(i).bits.cmd := DontCare + issue_o.balls(i).bits.rob_id := DontCare + } } // FIFO deq.ready - can only dequeue when target Ball device is ready + // Find which index corresponds to the requested ballId fifo.io.deq.ready := VecInit( - BallRsRegists.zipWithIndex.map { - case (info, idx) => - (headEntry.cmd.bid === info.ballId.U) && issue_o.balls(idx).ready + (0 until b.memDomain.bankNum).map { idx => + if (idx < numConfiguredBalls) { + val configuredBallId = b.ballDomain.ballIdMappings(idx).ballId.U + (headEntry.cmd.bid === configuredBallId) && issue_o.balls(idx).ready + } else { + false.B + } } ).asUInt.orR // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(parameter.rob_entries).W), numBalls)) + val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), b.memDomain.bankNum)) // Connect completion signals from all Ball devices to arbiter - for (i <- 0 until numBalls) { + for (i <- 0 until b.memDomain.bankNum) { completeArb.io.in(i).valid := commit_i.balls(i).valid completeArb.io.in(i).bits := commit_i.balls(i).bits.rob_id commit_i.balls(i).ready := completeArb.io.in(i).ready diff --git a/arch/src/main/scala/framework/balldomain/rs/rob.scala b/arch/src/main/scala/framework/balldomain/rs/rob.scala index 6e7e8b6a..ad75bac8 100644 --- a/arch/src/main/scala/framework/balldomain/rs/rob.scala +++ b/arch/src/main/scala/framework/balldomain/rs/rob.scala @@ -2,28 +2,28 @@ package framework.balldomain.rs import chisel3._ import chisel3.util._ -import examples.toy.balldomain.BallDomainParam -import examples.toy.balldomain.BallDecodeCmd +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.top.GlobalConfig // ROB entry data structure - preserves ROB ID to support out-of-order completion -class RobEntry(val parameter: BallDomainParam) extends Bundle { - val cmd = new BallDecodeCmd(parameter) - val rob_id = UInt(log2Up(parameter.rob_entries).W) +class RobEntry(val b: GlobalConfig) extends Bundle { + val cmd = new BallRsIssue(b) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } -class ROB(val parameter: BallDomainParam) extends Module { +class ROB(val b: GlobalConfig) extends Module { val io = IO(new Bundle { // Allocation interface - val alloc = Flipped(new DecoupledIO(new BallDecodeCmd(parameter))) + val alloc = Flipped(new DecoupledIO(new BallRsIssue(b))) // Externally specified rob_id - val alloc_rob_id = Input(UInt(log2Up(parameter.rob_entries).W)) + val alloc_rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new RobEntry(parameter)) + val issue = new DecoupledIO(new RobEntry(b)) // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(parameter.rob_entries).W))) + val complete = Flipped(new DecoupledIO(UInt(log2Up(b.frontend.rob_entries).W))) // Commit interface - commit completed head instruction // val commit = new DecoupledIO(new RobEntry) @@ -32,37 +32,37 @@ class ROB(val parameter: BallDomainParam) extends Module { val empty = Output(Bool()) val full = Output(Bool()) // head pointer position - val head_ptr = Output(UInt(log2Up(parameter.rob_entries).W)) + val head_ptr = Output(UInt(log2Up(b.frontend.rob_entries).W)) // Number of issued but uncompleted instructions - val issued_count = Output(UInt(log2Up(parameter.rob_entries + 1).W)) + val issued_count = Output(UInt(log2Up(b.frontend.rob_entries + 1).W)) // Whether each entry is valid - val entry_valid = Output(Vec(parameter.rob_entries, Bool())) + val entry_valid = Output(Vec(b.frontend.rob_entries, Bool())) // Whether each entry is complete - val entry_complete = Output(Vec(parameter.rob_entries, Bool())) + val entry_complete = Output(Vec(b.frontend.rob_entries, Bool())) }) // Circular ROB structure // Initialize to zero to avoid X states in FPGA - val robEntries = RegInit(VecInit(Seq.fill(parameter.rob_entries)(0.U.asTypeOf(new RobEntry(parameter))))) + val robEntries = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(0.U.asTypeOf(new RobEntry(b))))) // Whether entry is valid - val robValid = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) + val robValid = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Whether entry is issued - val robIssued = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Whether entry is complete - val robComplete = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Circular queue pointers // Points to oldest uncommitted instruction - val headPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val headPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // Points to next position to allocate - val tailPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val tailPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // ROB ID circular counter - val robIdCounter = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val robIdCounter = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // Number of issued but uncompleted instructions (used to limit issue) - val issuedCount = RegInit(0.U(log2Up(parameter.rob_entries + 1).W)) + val issuedCount = RegInit(0.U(log2Up(b.frontend.rob_entries + 1).W)) // Maximum issue limit: half of ROB depth - val maxIssueLimit = (parameter.rob_entries / 2).U + val maxIssueLimit = (b.frontend.rob_entries / 2).U // Queue status val isEmpty = headPtr === tailPtr && !robValid(headPtr) @@ -70,8 +70,8 @@ class ROB(val parameter: BallDomainParam) extends Module { val count = Mux( isFull, - parameter.rob_entries.U, - Mux(tailPtr >= headPtr, tailPtr - headPtr, parameter.rob_entries.U + tailPtr - headPtr) + b.frontend.rob_entries.U, + Mux(tailPtr >= headPtr, tailPtr - headPtr, b.frontend.rob_entries.U + tailPtr - headPtr) ) // ----------------------------------------------------------------------------- @@ -87,8 +87,8 @@ class ROB(val parameter: BallDomainParam) extends Module { robComplete(tailPtr) := false.B // Update tail pointer and rob_id counter (circular) - tailPtr := Mux(tailPtr === (parameter.rob_entries - 1).U, 0.U, tailPtr + 1.U) - robIdCounter := Mux(robIdCounter === (parameter.rob_entries - 1).U, 0.U, robIdCounter + 1.U) + tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) + robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) } // ----------------------------------------------------------------------------- @@ -109,16 +109,16 @@ class ROB(val parameter: BallDomainParam) extends Module { // ----------------------------------------------------------------------------- // Find first valid and unissued instruction starting from head val canIssue = Wire(Bool()) - val issuePtr = Wire(UInt(log2Up(parameter.rob_entries).W)) + val issuePtr = Wire(UInt(log2Up(b.frontend.rob_entries).W)) // Default values canIssue := false.B issuePtr := headPtr // Scan from head to find first issuable instruction - val scanValid = Wire(Vec(parameter.rob_entries, Bool())) - for (i <- 0 until parameter.rob_entries) { - val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) + val scanValid = Wire(Vec(b.frontend.rob_entries, Bool())) + for (i <- 0 until b.frontend.rob_entries) { + val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) } @@ -127,8 +127,8 @@ class ROB(val parameter: BallDomainParam) extends Module { val hasValid = scanValid.asUInt.orR val actualIssuePtr = Mux( - headPtr + firstValid >= parameter.rob_entries.U, - headPtr + firstValid - parameter.rob_entries.U, + headPtr + firstValid >= b.frontend.rob_entries.U, + headPtr + firstValid - b.frontend.rob_entries.U, headPtr + firstValid ) @@ -157,7 +157,7 @@ class ROB(val parameter: BallDomainParam) extends Module { // } // Sequential commit version // Commit all completed instructions - for (i <- 0 until parameter.rob_entries) { + for (i <- 0 until b.frontend.rob_entries) { when(robValid(i.U) && robComplete(i.U)) { robValid(i.U) := false.B robIssued(i.U) := false.B @@ -167,9 +167,9 @@ class ROB(val parameter: BallDomainParam) extends Module { // Update head pointer: skip all completed (about to be cleared) positions // Find first "valid and incomplete" instruction position starting from head - val nextHeadCandidates = Wire(Vec(parameter.rob_entries, Bool())) - for (i <- 0 until parameter.rob_entries) { - val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) + val nextHeadCandidates = Wire(Vec(b.frontend.rob_entries, Bool())) + for (i <- 0 until b.frontend.rob_entries) { + val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) // Entry is valid and incomplete (will not be committed) nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) } @@ -178,8 +178,8 @@ class ROB(val parameter: BallDomainParam) extends Module { val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) val nextHeadPtr = Mux( - headPtr + nextHeadOffset >= parameter.rob_entries.U, - headPtr + nextHeadOffset - parameter.rob_entries.U, + headPtr + nextHeadOffset >= b.frontend.rob_entries.U, + headPtr + nextHeadOffset - b.frontend.rob_entries.U, headPtr + nextHeadOffset ) diff --git a/arch/src/main/scala/framework/builtin/BaseConfigs.scala b/arch/src/main/scala/framework/builtin/BaseConfigs.scala deleted file mode 100644 index c3c8fccd..00000000 --- a/arch/src/main/scala/framework/builtin/BaseConfigs.scala +++ /dev/null @@ -1,82 +0,0 @@ -package framework.builtin - -import scala.math.{max, pow, sqrt} -import chisel3._ -import chisel3.util._ -import chisel3.experimental.SerializableModuleParameter -import freechips.rocketchip.tile.OpcodeSet -import org.chipsalliance.cde.config._ - -sealed abstract trait BuckyballMemCapacity -case class CapacityInKilobytes(kilobytes: Int) extends BuckyballMemCapacity -case class CapacityInVectors(vectors: Int) extends BuckyballMemCapacity -// case class CapacityInMatrices(matrices: Int) extends BuckyballMemCapacity - -object BaseConfig { - - // upickle support for BuckyballMemCapacity - implicit def memCapacityRW: upickle.default.ReadWriter[BuckyballMemCapacity] = - upickle.default.ReadWriter.merge( - upickle.default.macroRW[CapacityInKilobytes], - upickle.default.macroRW[CapacityInVectors] - ) - - // upickle support for BaseConfig - implicit def rw: upickle.default.ReadWriter[BaseConfig] = upickle.default.macroRW -} - -case class BaseConfig( - tlb_size: Int = 4, - // Number of RoB entries - rob_entries: Int = 16, - // Whether reservation station responds out-of-order (false = wait for ROB to be empty before responding) - rs_out_of_order_response: Boolean = true, - // Unused - dma_maxbytes: Int = 64, - dma_buswidth: Int = 128, - bankNum: Int = 32, - // bit - bankWidth: Int = 128, - bankCapacity: BuckyballMemCapacity = CapacityInKilobytes(16), - sp_singleported: Boolean = true, - max_in_flight_mem_reqs: Int = 16, // Unused - aligned_to: Int = 1, - spad_read_delay: Int = 0, - // Index length supporting SPAD (16384 rows) + ACC (4096 rows) - // spAddrLen: Int = 15, - // Index length for 4GB - memAddrLen: Int = 32, - // Number of vector PEs per thread - numVecPE: Int = 16, - // Number of vector threads per thread - numVecThread: Int = 16, - // Empty ball id - emptyBallid: Int = 5, - // Bank channel (BBus bandwidth, same as MemDomain bankChannel) - bankChannel: Int = 8) - extends SerializableModuleParameter { - // Fixed data widths - val inputWidth: Int = 8 // UInt8 - val accWidth: Int = 32 // UInt32 - - val bankMaskLen = (bankWidth / (aligned_to * 8)) max 1 - - val bankEntries = bankCapacity match { - case CapacityInKilobytes(kb) => kb * 1024 * 8 / (bankNum * bankWidth) - } - - // Helper methods to get Data types - def inputType: Data = UInt(inputWidth.W) - def accType: Data = UInt(accWidth.W) - - override def toString: String = - s"""BuckyballConfig - | ROB entries: $rob_entries - | Bank num: $bankNum - | Bank width: $bankWidth bits - | Bank entries: $bankEntries - | Bank capacity: $bankCapacity - | TLB size: $tlb_size - | DMA max bytes: $dma_maxbytes - |""".stripMargin -} diff --git a/arch/src/main/scala/framework/builtin/README.md b/arch/src/main/scala/framework/builtin/README.md deleted file mode 100644 index de47673d..00000000 --- a/arch/src/main/scala/framework/builtin/README.md +++ /dev/null @@ -1,340 +0,0 @@ -# Buckyball Built-in Component Library - -## Overview - -This directory contains the built-in hardware component implementations of the Buckyball framework, providing standardized and reusable hardware modules. Located at `arch/src/main/scala/framework/builtin`, it serves as the component library layer, offering verified hardware building blocks for upper-level systems. - -Main component modules: -- **memdomain**: Memory domain components, including storage and DMA engines -- **frontend**: Frontend processing components for instruction decode and scheduling -- **util**: Framework-level utility functions -- **BaseConfigs.scala**: Base configuration definitions - -## Code Structure - -``` -builtin/ -├── BaseConfigs.scala - Base configuration parameter definitions -├── memdomain/ - Memory domain implementation -│ ├── dma/ - DMA engines (BBStreamReader/Writer) -│ ├── mem/ - Memory components (Scratchpad, Accumulator) -│ ├── rs/ - Memory domain reservation station -│ ├── tlb/ - TLB implementation -│ ├── MemController.scala - Memory controller -│ ├── MemDomain.scala - Memory domain top-level -│ ├── MemLoader.scala - Load instruction handler -│ ├── MemStorer.scala - Store instruction handler -│ └── DomainDecoder.scala - Memory domain decoder -├── frontend/ - Frontend components -│ ├── GobalDecoder.scala - Global instruction decoder -│ ├── globalrs/ - Global reservation station -│ │ ├── GlobalReservationStation.scala -│ │ └── GlobalROB.scala - Global reorder buffer -│ └── rs/ - Ball domain reservation station -│ ├── reservationStation.scala -│ └── rob.scala -└── util/ - Utility function library -``` - -### Module Dependencies - -``` -Configuration Layer (BaseConfigs.scala) - ↓ -Component Layer (memdomain, frontend, util) - ↓ -Application Layer (examples, prototypes) -``` - -**BaseConfigs.scala** (Configuration Base Layer) -- Defines base configuration parameters for all built-in components -- Provides default configuration and parameter validation -- Referenced by all sub-modules as configuration source - -**memdomain/** (Memory Subsystem) -- Depends on BaseConfigs for memory-related configuration -- Implements storage, DMA, address management, etc. -- Provides memory access services for other components - -**frontend/** (Frontend Processing) -- Uses frontend configuration parameters from BaseConfigs -- Implements instruction fetch, decode, and scheduling -- Tightly integrated with processor core - -**util/** (Utility Library) -- Provides common hardware design utility functions -- Widely used by other components -- Independent of specific configuration parameters - -## Module Details - -### BaseConfigs.scala - -**Main Function**: Define base configuration parameters and defaults for built-in components - -**Key Components**: - -```scala -case class BaseConfig( - opcodes: OpcodeSet = OpcodeSet.custom3, - - inputType: Data, // Input data type - accType: Data, // Accumulator data type - - veclane: Int = 16, // Vector lane width - accveclane: Int = 4, // Accumulator vector lane - - tlb_size: Int = 4, // TLB size - rob_entries: Int = 16, // Number of ROB entries - rs_out_of_order_response: Boolean = true, // Out-of-order response support - - dma_maxbytes: Int = 64, // Unused - dma_buswidth: Int = 128, // DMA bus width - - sp_banks: Int = 4, // Scratchpad bank count - acc_banks: Int = 8, // Accumulator bank count - - sp_capacity: BuckyballMemCapacity = CapacityInKilobytes(256), - acc_capacity: BuckyballMemCapacity = CapacityInKilobytes(64), - - spAddrLen: Int = 15, // SPAD address length - memAddrLen: Int = 32, // Memory address length - - numVecPE: Int = 16, // Vector PEs per thread - numVecThread: Int = 16, // Vector threads - - emptyBallid: Int = 5 // Empty ball ID -) -``` - -**Configuration Parameters**: -- **Memory Domain**: Bank counts, capacities, address lengths -- **Frontend**: ROB entries, out-of-order response -- **Vector Unit**: PE count, thread count, lane width -- **Data Types**: Input and accumulator data types - -**Parameter Validation**: -```scala -require(sp_banks > 0, "SP banks must be positive") -require(acc_banks > 0, "ACC banks must be positive") -require(rob_entries > 0 && isPow2(rob_entries), "ROB entries must be power of 2") -``` - -**Input/Output**: -- Input: User-defined configuration overrides -- Output: Validated complete configuration parameters -- Edge cases: Parameter conflict detection and error reporting - -### memdomain/ Submodule - -**Main Function**: Implement complete memory domain functionality - -**Key Components**: -- **MemDomain.scala**: Memory domain top-level module - - Integrates all memory subsystem components - - Provides unified external interface - - Manages DMA and Ball domain access coordination - -- **MemController.scala**: Memory controller - - Encapsulates Scratchpad and Accumulator - - Dual-port design for DMA and Ball domain - - Bank arbitration and routing - -- **MemLoader.scala**: Load instruction handler - - Receives load instructions from reservation station - - Issues DMA read requests - - Writes data to Scratchpad/Accumulator - -- **MemStorer.scala**: Store instruction handler - - Reads data from Scratchpad/Accumulator - - Issues DMA write requests with alignment - - Handles byte masking - -- **dma/**: DMA engines - - **BBStreamReader**: Streaming read with TLB support - - **BBStreamWriter**: Streaming write with alignment - - Transaction ID management - -- **mem/**: Memory components - - **Scratchpad**: Multi-bank scratchpad memory - - **AccBank**: Accumulator bank with accumulation pipeline - - **SramBank**: Generic SRAM bank - -- **tlb/**: Translation Lookaside Buffer - - Virtual to physical address translation - - Integrated with DMA engines - -- **rs/**: Memory domain reservation station - - FIFO-based instruction scheduler - - Local ROB for memory instructions - -**Interface Definition**: -```scala -class MemDomainIO(implicit b: CustomBuckyballConfig, p: Parameters) extends Bundle { - // From Global RS - val issue = Flipped(Decoupled(new MemRsIssue)) - - // To Global RS - val complete = Decoupled(new MemRsComplete) - - // Ball domain SRAM interface - val sramRead = Vec(sp_banks, Flipped(new SramReadIO)) - val sramWrite = Vec(sp_banks, Flipped(new SramWriteIO)) - val accRead = Vec(acc_banks, Flipped(new SramReadIO)) - val accWrite = Vec(acc_banks, Flipped(new SramWriteIO)) - - // DMA interface - val dma = new Bundle { - val read = Decoupled(new BBReadRequest) - val write = Decoupled(new BBWriteRequest) - } - - // TLB interface - val tlb = Vec(2, new BBTLBIO) - val ptw = Vec(2, Flipped(new TLBPTWIO)) - val tlbExp = Output(Vec(2, new BBTLBExceptionIO)) -} -``` - -### frontend/ Submodule - -**Main Function**: Implement processor frontend functionality for instruction decode and scheduling - -**Core Components**: -- **GobalDecoder.scala**: Global instruction decoder - - Classifies instructions into Ball/Memory/Fence types - - Constructs PostGDCmd for domain-specific decoders - - Interfaces with Global RS - -- **globalrs/**: Global reservation station - - **GlobalReservationStation.scala**: Central instruction manager - - Allocates ROB entries - - Issues to Ball and Memory domains - - Handles completion from both domains - - Manages Fence synchronization - - **GlobalROB.scala**: Global reorder buffer - - Tracks instruction state across domains - - Supports out-of-order completion - - Sequential commit - -- **rs/**: Ball domain reservation station - - **reservationStation.scala**: Ball-specific scheduler - - **rob.scala**: Local ROB for Ball instructions - -**Data Flow**: -``` -RoCC → Global Decoder → Global RS → Ball Domain / Mem Domain - ↓ ↓ ↓ - Global ROB Ball Decoder Mem Decoder - (tracks state) ↓ ↓ - Ball Devices Loader/Storer -``` - -### util/ Submodule - -**Main Function**: Provide common utility functions - -**Utility Categories**: -- Mathematical operation tools -- Interface conversion tools -- Debug and monitoring tools -- Common hardware patterns - -## Usage Guide - -### Configuration Usage - -**Basic Configuration Inheritance**: -```scala -class MySystemConfig extends Config( - new BaseConfig ++ - new WithCustomMemDomain(spBanks = 8) ++ - new WithCustomFrontend(robEntries = 32) -) -``` - -**Parameter Access**: -```scala -class MyModule(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - val spBanks = b.sp_banks - val accBanks = b.acc_banks - val robEntries = b.rob_entries -} -``` - -### Extension Development - -**Adding New Components**: -1. Create new module in corresponding subdirectory -2. Add configuration parameters in BaseConfigs.scala -3. Implement standard Module interface -4. Add corresponding test cases -5. Update documentation - -**Custom Configuration**: -```scala -case class MyComponentParams( - param1: Int = 16, - param2: Boolean = true -) - -class WithMyComponent(param1: Int, param2: Boolean) extends Config((site, here, up) => { - case MyComponentKey => MyComponentParams(param1, param2) -}) -``` - -### Important Notes - -1. **Configuration Consistency**: Ensure related component configurations are compatible -2. **Resource Constraints**: Pay attention to reasonable hardware resource allocation -3. **Timing Optimization**: Focus on timing paths across components -4. **Interface Standards**: Follow unified interface design specifications -5. **Test Coverage**: Provide sufficient test cases for each component -6. **Memory Access**: Respect bank access constraints (op1 and op2 cannot access same bank) -7. **ROB Management**: Coordinate between Global ROB and local ROBs - -## Architecture Highlights - -### Instruction Pipeline -``` -RoCC Interface - ↓ -Global Decoder (classify instruction type) - ↓ -Global RS (with ROB) ← tracks all in-flight instructions - ↓ ↓ -Ball Domain Mem Domain - ↓ ↓ -Ball Devices Loader/Storer - ↓ ↓ - MemController - ↓ ↓ -Scratchpad Accumulator -``` - -### Memory Architecture -``` -Main Memory - ↓ (DMA + TLB) -MemController -├─→ Scratchpad (4 banks × 64KB = 256KB) -└─→ Accumulator (8 banks × 8KB = 64KB) - ↑ -Ball Devices (read/write access) -``` - -## Performance Considerations - -1. **ROB Depth**: 16 entries support up to 16 in-flight instructions -2. **Memory Banks**: 4 scratchpad + 8 accumulator banks enable parallel access -3. **Out-of-Order Execution**: Global RS supports OOO when enabled -4. **DMA Bandwidth**: 128-bit bus provides high memory throughput -5. **Pipeline Depth**: Multi-stage pipeline for high clock frequency - -## Related Documentation - -- [Memory Domain Details](memdomain/README.md) - Memory subsystem implementation -- [Frontend Components](frontend/README.md) - Instruction decode and scheduling -- [DMA Engines](memdomain/dma/README.md) - DMA implementation -- [TLB Management](memdomain/tlb/README.md) - Address translation -- [Framework Overview](../README.md) - Upper-level architecture diff --git a/arch/src/main/scala/framework/builtin/configs/default.json b/arch/src/main/scala/framework/builtin/configs/default.json deleted file mode 100644 index 51371b5a..00000000 --- a/arch/src/main/scala/framework/builtin/configs/default.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "tlb_size": 4, - "rob_entries": 16, - "rs_out_of_order_response": true, - "dma_maxbytes": 64, - "dma_buswidth": 128, - "bankNum": 32, - "bankWidth": 128, - "bankCapacity": { - "$type": "framework.builtin.CapacityInKilobytes", - "kilobytes": 16 - }, - "sp_singleported": true, - "max_in_flight_mem_reqs": 16, - "aligned_to": 1, - "spad_read_delay": 0, - "memAddrLen": 32, - "numVecPE": 16, - "numVecThread": 16, - "emptyBallid": 5 -} diff --git a/arch/src/main/scala/framework/builtin/util/README.md b/arch/src/main/scala/framework/builtin/util/README.md deleted file mode 100644 index b748af2d..00000000 --- a/arch/src/main/scala/framework/builtin/util/README.md +++ /dev/null @@ -1,225 +0,0 @@ -# Framework Utility Library - -## Overview - -This directory contains framework-level utility functions and helper modules for Buckyball, providing general-purpose hardware design tools. Located in `arch/src/main/scala/framework/builtin/util`, it serves as a utility layer, offering reusable hardware building blocks and utility functions for other framework components. - -Main utility categories: -- Mathematical operations and bit manipulation tools -- Interface conversion and adapters -- Debug and performance monitoring tools -- Common hardware pattern implementations - -## Code Structure - -``` -util/ -└── (specific utility files to be analyzed) -``` - -### Utility Categories - -**Math Tools** -- Bit width calculation and logarithm functions -- Numeric conversion and formatting -- Optimized arithmetic operation implementations - -**Interface Tools** -- Protocol conversion adapters -- Signal synchronization and clock domain crossing -- Handshake protocol implementations - -**Debug Tools** -- Performance counter templates -- Debug signal output -- State monitoring interfaces - -## Module Description - -### Mathematical Operations Tools - -**Main functionality**: Provides common mathematical operations and bit manipulation functions - -**Key functions**: - -```scala -object MathUtils { - // Calculate log2 ceiling - def log2Ceil(x: Int): Int = { - require(x > 0) - (log(x) / log(2)).ceil.toInt - } - - // Check if power of 2 - def isPow2(x: Int): Boolean = x > 0 && (x & (x - 1)) == 0 - - // Calculate smallest power of 2 >= x - def nextPow2(x: Int): Int = { - if (isPow2(x)) x else 1 << log2Ceil(x) - } -} -``` - -**Bit manipulation tools**: -```scala -object BitUtils { - // Bit reversal - def reverseBits(data: UInt, width: Int): UInt = { - VecInit((0 until width).map(i => data(i))).asUInt - } - - // Hamming weight (count of 1s) - def popCount(data: UInt): UInt = { - PopCount(data) - } - - // Leading zero count - def leadingZeros(data: UInt, width: Int): UInt = { - PriorityEncoder(Reverse(data)) - } -} -``` - -### Interface Conversion Tools - -**Main functionality**: Provides common interface conversion and adaptation - -**Protocol converters**: -```scala -class DecoupledToValid[T <: Data](gen: T) extends Module { - val io = IO(new Bundle { - val in = Flipped(Decoupled(gen)) - val out = Valid(gen) - }) - - io.out.valid := io.in.valid - io.out.bits := io.in.bits - io.in.ready := true.B -} - -class ValidToDecoupled[T <: Data](gen: T) extends Module { - val io = IO(new Bundle { - val in = Flipped(Valid(gen)) - val out = Decoupled(gen) - }) - - io.out.valid := io.in.valid - io.out.bits := io.in.bits -} -``` - -**Clock domain crossing**: -```scala -class AsyncFIFO[T <: Data](gen: T, depth: Int) extends Module { - val io = IO(new Bundle { - val enq_clock = Input(Clock()) - val enq_reset = Input(Bool()) - val enq = Flipped(Decoupled(gen)) - - val deq_clock = Input(Clock()) - val deq_reset = Input(Bool()) - val deq = Decoupled(gen) - }) - - // Async FIFO implementation - // Uses Gray code pointers to avoid metastability -} -``` - -### Debug and Monitoring Tools - -**Main functionality**: Provides general debugging and performance monitoring tools - -**Performance counter**: -```scala -class PerfCounter(name: String) extends Module { - val io = IO(new Bundle { - val inc = Input(Bool()) - val value = Output(UInt(64.W)) - }) - - val counter = RegInit(0.U(64.W)) - when(io.inc) { - counter := counter + 1.U - } - io.value := counter - - // Optional debug output - when(io.inc) { - printf(s"[PerfCounter] $name: %d\n", counter + 1.U) - } -} -``` - -**Debug signal output**: -```scala -object DebugUtils { - def debugPrint(cond: Bool, fmt: String, args: Bits*): Unit = { - when(cond) { - printf(fmt, args: _*) - } - } - - def assert(cond: Bool, msg: String): Unit = { - chisel3.assert(cond, msg) - } - - def cover(cond: Bool, msg: String): Unit = { - chisel3.cover(cond, msg) - } -} -``` - -## Usage - -### Usage Examples - -**Using math tools**: -```scala -import util.MathUtils._ - -class MyModule extends Module { - val addrBits = log2Ceil(entries) - val bankSize = nextPow2(requestedSize) - - require(isPow2(bankSize), "Bank size must be power of 2") -} -``` - -**Using interface conversion**: -```scala -val converter = Module(new DecoupledToValid(UInt(32.W))) -converter.io.in <> some_decoupled_signal -val valid_signal = converter.io.out -``` - -**Using performance monitoring**: -```scala -val hit_counter = Module(new PerfCounter("cache_hits")) -hit_counter.io.inc := cache_hit - -val miss_counter = Module(new PerfCounter("cache_misses")) -miss_counter.io.inc := cache_miss -``` - -### Extension Development - -**Adding new tools**: -1. Determine utility's generality and reuse value -2. Implement standard Chisel module interfaces -3. Add sufficient parameterization support -4. Provide usage examples and test cases - -**Tool design principles**: -- Keep interfaces concise and clear -- Support parameterized configuration -- Provide good error checking -- Consider hardware implementation efficiency - -### Notes - -1. **Hardware overhead**: Utility functions should consider hardware implementation costs -2. **Timing impact**: Avoid using complex tools on critical paths -3. **Parameter validation**: Perform sufficient parameter checking at compile time -4. **Complete documentation**: Provide clear usage instructions for each tool -5. **Test coverage**: Ensure correctness and boundary case handling of utility functions diff --git a/arch/src/main/scala/framework/core/configs/CoreParam.scala b/arch/src/main/scala/framework/core/configs/CoreParam.scala new file mode 100644 index 00000000..a5381c5a --- /dev/null +++ b/arch/src/main/scala/framework/core/configs/CoreParam.scala @@ -0,0 +1,23 @@ +package framework.core.configs + +import upickle.default._ + +/** + * Core参数 + */ +case class CoreParam( + coreDataBytes: Int, + xLen: Int, + vaddrBits: Int, + paddrBits: Int, + pgIdxBits: Int) + +object CoreParam { + implicit val rw: ReadWriter[CoreParam] = macroRW + + def apply(): CoreParam = { + val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/core/configs/default.json").mkString + read[CoreParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/core/configs/default.json b/arch/src/main/scala/framework/core/configs/default.json new file mode 100644 index 00000000..7e1a21a1 --- /dev/null +++ b/arch/src/main/scala/framework/core/configs/default.json @@ -0,0 +1,7 @@ +{ + "coreDataBytes": 64, + "xLen": 64, + "vaddrBits": 39, + "paddrBits": 56, + "pgIdxBits": 12 +} diff --git a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala index 471822cc..688951ff 100644 --- a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala +++ b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala @@ -28,16 +28,15 @@ import freechips.rocketchip.rocket.{ import freechips.rocketchip.tilelink.{TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters, TLNode} import freechips.rocketchip.util.InOrderArbiter -case object BuildRoCCBB extends Field[Seq[Parameters => LazyRoCCBB]](Nil) - -class RoCCCommandBB(implicit p: Parameters) extends CoreBundle()(p) { +// Custom simplified RoCC types without implicit Parameters +class RoCCCommandBB(xLen: Int = 64) extends Bundle { val inst = new RoCCInstruction val rs1 = Bits(xLen.W) val rs2 = Bits(xLen.W) val status = new MStatus } -class RoCCResponseBB(implicit p: Parameters) extends CoreBundle()(p) { +class RoCCResponseBB(xLen: Int = 64) extends Bundle { val rd = Bits(5.W) val data = Bits(xLen.W) } @@ -82,7 +81,7 @@ class LazyRoCCModuleImpBB(outer: LazyRoCCBB) extends LazyModuleImp(outer) { /** Mixins for including RoCC * */ trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => - val roccs = p(BuildRoCCBB).map(_(p)) + val roccs = p(BuildRoCC).map(_(p)) val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs require( roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, @@ -124,8 +123,8 @@ class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implic extends CoreModule()(p) { val io = IO(new Bundle { - val in = Flipped(Decoupled(new RoCCCommand)) - val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) + val in = Flipped(Decoupled(new RoCCCommandBB)) + val out = Vec(opcodes.size, Decoupled(new RoCCCommandBB)) val busy = Output(Bool()) }) diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala index 819080d6..3b64fac3 100644 --- a/arch/src/main/scala/framework/frontend/Frontend.scala +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -3,67 +3,49 @@ package framework.frontend import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile.RoCCCommand -import freechips.rocketchip.tile.RoCCResponse import framework.frontend.decoder.{GlobalDecoder, PostGDCmd} -import framework.frontend.globalrs.{ - GlobalReservationStation, - GlobalReservationStationParam, - GlobalRsComplete, - GlobalRsIssue -} -import framework.frontend.FrontendParam +import framework.frontend.globalrs.{GlobalReservationStation, GlobalRsComplete, GlobalRsIssue} +import framework.top.GlobalConfig +import framework.core.rocket.{RoCCCommandBB, RoCCResponseBB} /** * Frontend Module * Encapsulates GlobalDecoder and GlobalReservationStation */ @instantiable -class Frontend(val parameter: FrontendParam)(implicit p: Parameters) - extends Module - with SerializableModule[FrontendParam] { +class Frontend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // RoCC command input val cmd = Flipped(Decoupled(new Bundle { - val cmd = new RoCCCommand + val cmd = new RoCCCommandBB(b.core.xLen) })) // Issue to domains - val ball_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)(p)) - val mem_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)(p)) - val gp_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)(p)) - + val ball_issue_o = Decoupled(new GlobalRsIssue(b)) + val mem_issue_o = Decoupled(new GlobalRsIssue(b)) + val gp_issue_o = Decoupled(new GlobalRsIssue(b)) // Complete from domains - val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries)(p))) - val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries)(p))) - val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries)(p))) + val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) // RoCC response - val resp = Decoupled(new RoCCResponse) + val resp = Decoupled(new RoCCResponseBB(b.core.xLen)) val busy = Output(Bool()) }) - // Instantiate GlobalDecoder - val gDecoder: Instance[GlobalDecoder] = Instantiate(new GlobalDecoder(parameter)) + val gDecoder: Instance[GlobalDecoder] = Instantiate(new GlobalDecoder(b)) + val globalRs: Instance[GlobalReservationStation] = Instantiate(new GlobalReservationStation(b)) + gDecoder.io.id_i.valid := io.cmd.valid gDecoder.io.id_i.bits.cmd := io.cmd.bits.cmd io.cmd.ready := gDecoder.io.id_i.ready - // Instantiate GlobalReservationStation - val globalRsParam = GlobalReservationStationParam( - rob_entries = parameter.rob_entries, - rs_out_of_order_response = parameter.rs_out_of_order_response - ) - - val globalRs: Instance[GlobalReservationStation] = Instantiate(new GlobalReservationStation(globalRsParam)(p)) globalRs.io.global_decode_cmd_i <> gDecoder.io.id_o - // Connect to domains io.ball_issue_o <> globalRs.io.ball_issue_o io.mem_issue_o <> globalRs.io.mem_issue_o io.gp_issue_o <> globalRs.io.gp_issue_o @@ -72,9 +54,7 @@ class Frontend(val parameter: FrontendParam)(implicit p: Parameters) globalRs.io.mem_complete_i <> io.mem_complete_i globalRs.io.gp_complete_i <> io.gp_complete_i - // RoCC response io.resp <> globalRs.io.rs_rocc_o.resp io.busy := globalRs.io.rs_rocc_o.busy - override lazy val desiredName = "Frontend" } diff --git a/arch/src/main/scala/framework/frontend/FrontendParam.scala b/arch/src/main/scala/framework/frontend/FrontendParam.scala deleted file mode 100644 index 64adcdc2..00000000 --- a/arch/src/main/scala/framework/frontend/FrontendParam.scala +++ /dev/null @@ -1,8 +0,0 @@ -package framework.frontend - -import chisel3.experimental.{SerializableModuleParameter} - -case class FrontendParam( - rob_entries: Int, - rs_out_of_order_response: Boolean) - extends SerializableModuleParameter diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala new file mode 100644 index 00000000..4892653a --- /dev/null +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -0,0 +1,20 @@ +package framework.frontend.configs + +import upickle.default._ + +/** + * Frontend参数 - 包含前端所有配置 + */ +case class FrontendParam( + rob_entries: Int, + rs_out_of_order_response: Boolean) + +object FrontendParam { + implicit val rw: ReadWriter[FrontendParam] = macroRW + + def apply(): FrontendParam = { + val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/frontend/configs/default.json").mkString + read[FrontendParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/frontend/configs/default.json b/arch/src/main/scala/framework/frontend/configs/default.json new file mode 100644 index 00000000..f85dc375 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/configs/default.json @@ -0,0 +1,4 @@ +{ + "rob_entries": 16, + "rs_out_of_order_response": true +} diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index 191ff1e0..faa78e75 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -4,38 +4,36 @@ import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.top.GlobalConfig import freechips.rocketchip.tile._ import framework.frontend.decoder.GISA._ import framework.memdomain.frontend.cmd_channel.decoder.DISA._ import framework.gpdomain.sequencer.decoder.DISA._ -import framework.frontend.FrontendParam -class BuckyballRawCmd(implicit p: Parameters) extends Bundle { - val cmd = new RoCCCommand +import framework.core.rocket.RoCCCommandBB + +class BuckyballRawCmd(val b: GlobalConfig) extends Bundle { + val cmd = new RoCCCommandBB(b.core.xLen) } -class PostGDCmd(implicit p: Parameters) extends Bundle { +class PostGDCmd(b: GlobalConfig) extends Bundle { val domain_id = UInt(4.W) - val raw_cmd = new RoCCCommand + val raw_cmd = new RoCCCommandBB(b.core.xLen) } @instantiable -class GlobalDecoder(val parameter: FrontendParam)(implicit p: Parameters) - extends Module - with SerializableModule[FrontendParam] { +class GlobalDecoder(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { val id_i = Flipped(Decoupled(new Bundle { - val cmd = new RoCCCommand + val cmd = new RoCCCommandBB(b.core.xLen) })) - val id_o = Decoupled(new PostGDCmd) + val id_o = Decoupled(new PostGDCmd(b)) }) // If reservation station is blocked, id_i is also blocked diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 4964bcb3..35d49732 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -4,67 +4,58 @@ import chisel3._ import chisel3.util._ import chisel3.experimental._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.top.GlobalConfig import framework.frontend.decoder.PostGDCmd -import framework.frontend.FrontendParam @instantiable -class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) - extends Module - with SerializableModule[FrontendParam] { +class GlobalROB(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Allocation interface - val alloc = Flipped(new DecoupledIO(new PostGDCmd)) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new GlobalRobEntry(parameter.rob_entries)) + val issue = new DecoupledIO(new GlobalRobEntry(b)) // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(parameter.rob_entries).W))) + val complete = Flipped(new DecoupledIO(UInt(log2Up(b.frontend.rob_entries).W))) // Status signals - exposed to reservation station for decision making val empty = Output(Bool()) val full = Output(Bool()) // head pointer position - val head_ptr = Output(UInt(log2Up(parameter.rob_entries).W)) + val head_ptr = Output(UInt(log2Up(b.frontend.rob_entries).W)) // Number of issued but uncompleted instructions - val issued_count = Output(UInt(log2Up(parameter.rob_entries + 1).W)) + val issued_count = Output(UInt(log2Up(b.frontend.rob_entries + 1).W)) // Whether each entry is valid - val entry_valid = Output(Vec(parameter.rob_entries, Bool())) + val entry_valid = Output(Vec(b.frontend.rob_entries, Bool())) // Whether each entry is complete - val entry_complete = Output(Vec(parameter.rob_entries, Bool())) + val entry_complete = Output(Vec(b.frontend.rob_entries, Bool())) }) // Circular ROB structure - val robEntries = - RegInit(VecInit(Seq.fill(parameter.rob_entries)(0.U.asTypeOf(new GlobalRobEntry(parameter.rob_entries))))) + val robEntries = + RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(0.U.asTypeOf(new GlobalRobEntry(b))))) // Whether entry is valid - val robValid = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) + val robValid = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Whether entry is issued - val robIssued = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Whether entry is complete - val robComplete = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) - - // Circular queue pointers + val robComplete = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Points to oldest uncommitted instruction - val headPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val headPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // Points to next position to allocate - val tailPtr = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val tailPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // ROB ID circular counter - val robIdCounter = RegInit(0.U(log2Up(parameter.rob_entries).W)) - + val robIdCounter = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // Number of issued but uncompleted instructions (used to limit issue) - val issuedCount = RegInit(0.U(log2Up(parameter.rob_entries + 1).W)) + val issuedCount = RegInit(0.U(log2Up(b.frontend.rob_entries + 1).W)) // Maximum issue limit: half of ROB depth - val maxIssueLimit = (parameter.rob_entries / 2).U - + val maxIssueLimit = (b.frontend.rob_entries / 2).U // Queue status - val isEmpty = headPtr === tailPtr && !robValid(headPtr) - val isFull = headPtr === tailPtr && robValid(headPtr) + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) // ----------------------------------------------------------------------------- // Inbound - instruction allocation @@ -79,8 +70,8 @@ class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) robComplete(tailPtr) := false.B // Update tail pointer and rob_id counter (circular) - tailPtr := Mux(tailPtr === (parameter.rob_entries - 1).U, 0.U, tailPtr + 1.U) - robIdCounter := Mux(robIdCounter === (parameter.rob_entries - 1).U, 0.U, robIdCounter + 1.U) + tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) + robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) } // ----------------------------------------------------------------------------- @@ -101,16 +92,16 @@ class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) // ----------------------------------------------------------------------------- // Find first valid and unissued instruction starting from head val canIssue = Wire(Bool()) - val issuePtr = Wire(UInt(log2Up(parameter.rob_entries).W)) + val issuePtr = Wire(UInt(log2Up(b.frontend.rob_entries).W)) // Default values canIssue := false.B issuePtr := headPtr // Scan from head to find first issuable instruction - val scanValid = Wire(Vec(parameter.rob_entries, Bool())) - for (i <- 0 until parameter.rob_entries) { - val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) + val scanValid = Wire(Vec(b.frontend.rob_entries, Bool())) + for (i <- 0 until b.frontend.rob_entries) { + val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) } @@ -119,8 +110,8 @@ class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) val hasValid = scanValid.asUInt.orR val actualIssuePtr = Mux( - headPtr + firstValid >= parameter.rob_entries.U, - headPtr + firstValid - parameter.rob_entries.U, + headPtr + firstValid >= b.frontend.rob_entries.U, + headPtr + firstValid - b.frontend.rob_entries.U, headPtr + firstValid ) @@ -141,7 +132,7 @@ class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) // Instruction commit - commit all completed instructions out-of-order // ----------------------------------------------------------------------------- // Commit all completed instructions - for (i <- 0 until parameter.rob_entries) { + for (i <- 0 until b.frontend.rob_entries) { when(robValid(i.U) && robComplete(i.U)) { robValid(i.U) := false.B robIssued(i.U) := false.B @@ -151,9 +142,9 @@ class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) // Update head pointer: skip all completed (about to be cleared) positions // Find first "valid and incomplete" instruction position starting from head - val nextHeadCandidates = Wire(Vec(parameter.rob_entries, Bool())) - for (i <- 0 until parameter.rob_entries) { - val ptr = Mux(headPtr + i.U >= parameter.rob_entries.U, headPtr + i.U - parameter.rob_entries.U, headPtr + i.U) + val nextHeadCandidates = Wire(Vec(b.frontend.rob_entries, Bool())) + for (i <- 0 until b.frontend.rob_entries) { + val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) // Entry is valid and incomplete (will not be committed) nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) } @@ -162,8 +153,8 @@ class GlobalROB(val parameter: FrontendParam)(implicit p: Parameters) val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) val nextHeadPtr = Mux( - headPtr + nextHeadOffset >= parameter.rob_entries.U, - headPtr + nextHeadOffset - parameter.rob_entries.U, + headPtr + nextHeadOffset >= b.frontend.rob_entries.U, + headPtr + nextHeadOffset - b.frontend.rob_entries.U, headPtr + nextHeadOffset ) diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 265fd915..9a533e35 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -4,74 +4,57 @@ import chisel3._ import chisel3.util._ import chisel3.experimental._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.top.GlobalConfig import framework.frontend.decoder.{DomainId, PostGDCmd} import framework.frontend.decoder.GISA._ -import freechips.rocketchip.tile.RoCCResponse +import framework.core.rocket.RoCCResponseBB // Global ROB entry - only contains basic information, does not include specific instruction decoding -class GlobalRobEntry(rob_entries: Int)(implicit p: Parameters) extends Bundle { - val cmd = new PostGDCmd - val rob_id = UInt(log2Up(rob_entries).W) +class GlobalRobEntry(b: GlobalConfig) extends Bundle { + val cmd = new PostGDCmd(b) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } // Global RS issue interface -class GlobalRsIssue(rob_entries: Int)(implicit p: Parameters) extends GlobalRobEntry(rob_entries) +class GlobalRsIssue(b: GlobalConfig) extends GlobalRobEntry(b) // Global RS completion interface -class GlobalRsComplete(rob_entries: Int)(implicit p: Parameters) extends Bundle { - val rob_id = UInt(log2Up(rob_entries).W) +class GlobalRsComplete(b: GlobalConfig) extends Bundle { + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } // No additional interface Bundle needed, defined directly in IO -case class GlobalReservationStationParam( - rob_entries: Int, - rs_out_of_order_response: Boolean) - extends SerializableModuleParameter - // Global reservation station - between GlobalDecoder and each Domain @instantiable -class GlobalReservationStation(val parameter: GlobalReservationStationParam)(implicit p: Parameters) - extends Module - with SerializableModule[GlobalReservationStationParam] { +class GlobalReservationStation(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // GlobalDecoder -> Global RS - val global_decode_cmd_i = Flipped(new DecoupledIO(new PostGDCmd)) + val global_decode_cmd_i = Flipped(new DecoupledIO(new PostGDCmd(b))) // Global RS -> BallDomain // -> MemDomain // -> GpDomain - val ball_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)) - val mem_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)) - val gp_issue_o = Decoupled(new GlobalRsIssue(parameter.rob_entries)) + val ball_issue_o = Decoupled(new GlobalRsIssue(b)) + val mem_issue_o = Decoupled(new GlobalRsIssue(b)) + val gp_issue_o = Decoupled(new GlobalRsIssue(b)) // BallDomain -> Global RS // MemDomain -> // GpDomain -> - val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries))) - val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries))) - val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(parameter.rob_entries))) + val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) // RoCC response val rs_rocc_o = new Bundle { - val resp = new DecoupledIO(new RoCCResponse) + val resp = new DecoupledIO(new RoCCResponseBB(b.core.xLen)) val busy = Output(Bool()) } }) - // Convert GlobalReservationStationParam to FrontendParam for GlobalROB - import framework.frontend.FrontendParam - - val frontendParam = FrontendParam( - rob_entries = parameter.rob_entries, - rs_out_of_order_response = parameter.rs_out_of_order_response - ) - - val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(frontendParam)) + val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) // ----------------------------------------------------------------------------- // Fence handling - fence instructions require ROB to be empty before execution @@ -130,7 +113,7 @@ class GlobalReservationStation(val parameter: GlobalReservationStationParam)(imp // ----------------------------------------------------------------------------- // Completion signal processing // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(parameter.rob_entries).W), 3)) + val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), 3)) // Connect Ball, Mem, and GP domain completion signals to arbiter completeArb.io.in(0).valid := io.ball_complete_i.valid @@ -146,7 +129,7 @@ class GlobalReservationStation(val parameter: GlobalReservationStationParam)(imp io.gp_complete_i.ready := completeArb.io.in(2).ready // Decide whether to filter completion signals based on configuration - if (parameter.rs_out_of_order_response) { + if (b.frontend.rs_out_of_order_response) { // Out-of-order mode: accept all completion signals, ROB commits out-of-order internally rob.io.complete <> completeArb.io.out } else { diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index c4ae9ce2..8d73e751 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -2,59 +2,17 @@ package framework.gpdomain import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} -import framework.gpdomain.sequencer.decoder.DomainDecoder import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.top.GlobalConfig -object GpDomainParam { - implicit def rw: upickle.default.ReadWriter[GpDomainParam] = upickle.default.macroRW - - /** - * Load from JSON file - */ - def fromJson(path: String): GpDomainParam = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[GpDomainParam](jsonStr) - } - - /** - * Generate from global config - */ - def fromGlobal(global: framework.builtin.BaseConfig): GpDomainParam = { - GpDomainParam( - rob_entries = global.rob_entries - ) - } - -} - -case class GpDomainParam( - rob_entries: Int) - extends SerializableModuleParameter { - override def toString: String = - s"""GpDomainParam - | ROB entries: $rob_entries - |""".stripMargin -} - -/** - * General Purpose Domain - */ @instantiable -class GpDomain(val parameter: GpDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[GpDomainParam] { +class GpDomain(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Receive instructions from GlobalRS - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries))) - - // Report completion to GlobalRS - val global_complete_o = Decoupled(new GlobalRsComplete(parameter.rob_entries)) + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) + val global_complete_o = Decoupled(new GlobalRsComplete(b)) // Status signal val busy = Output(Bool()) @@ -66,8 +24,8 @@ class GpDomain(val parameter: GpDomainParam)(implicit p: Parameters) // Decode Stage // ----------------------------------------------------------------------------- val decoder: Instance[framework.gpdomain.sequencer.decoder.DomainDecoder] = - Instantiate(new framework.gpdomain.sequencer.decoder.DomainDecoder(parameter)) - decoder.io.inst_i := io.global_issue_i.bits.cmd.raw_cmd + Instantiate(new framework.gpdomain.sequencer.decoder.DomainDecoder(b)) + decoder.io.inst_i <> io.global_issue_i.bits.cmd val decoded = decoder.io.decoded_o io.global_complete_o.valid := io.global_issue_i.valid @@ -75,5 +33,4 @@ class GpDomain(val parameter: GpDomainParam)(implicit p: Parameters) io.busy := false.B - override lazy val desiredName = "GpDomain" } diff --git a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala new file mode 100644 index 00000000..68122df7 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala @@ -0,0 +1,21 @@ +package framework.gpdomain.configs + +import upickle.default._ + +/** + * GpDomain参数 + */ +case class GpDomainParam() + +object GpDomainParam { + implicit val rw: ReadWriter[GpDomainParam] = macroRW + + /** + * 从默认的局部JSON文件加载 + */ + def apply(): GpDomainParam = { + val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/gpdomain/configs/default.json").mkString + read[GpDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/gpdomain/configs/default.json b/arch/src/main/scala/framework/gpdomain/configs/default.json index 51c7186f..0967ef42 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/default.json +++ b/arch/src/main/scala/framework/gpdomain/configs/default.json @@ -1,3 +1 @@ -{ - "rob_entries": 16 -} +{} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala index ec5a5971..928c06da 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala @@ -2,12 +2,8 @@ package framework.gpdomain.sequencer.decoder import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ - -class BuckyballRawCmd(implicit p: Parameters) extends Bundle { - val cmd = new RoCCCommand -} +import framework.core.rocket.RoCCCommandBB +import framework.top.GlobalConfig object DISA { // RVV Instruction Opcodes diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala index e0880ecf..eb34d7e1 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala @@ -2,12 +2,10 @@ package framework.gpdomain.sequencer.decoder import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.gpdomain.GpDomainParam +import framework.top.GlobalConfig +import framework.core.rocket.RoCCCommandBB import framework.gpdomain.sequencer.decoder.{Decoder, DecoderParam} -import freechips.rocketchip.tile.RoCCCommand import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} /** * Domain Decoder Parameter Object @@ -33,8 +31,8 @@ object DomainDecoderParameter { /** * Domain Decoder IO */ -class DomainDecoderIO(implicit p: Parameters) extends Bundle { - val inst_i = Input(new RoCCCommand) +class DomainDecoderIO(b: GlobalConfig) extends Bundle { + val inst_i = Input(new RoCCCommandBB(b.core.xLen)) val decoded_o = Decoder.bundle(DomainDecoderParameter.decoderParam).cloneType } @@ -43,11 +41,9 @@ class DomainDecoderIO(implicit p: Parameters) extends Bundle { * Encapsulates the T1 decoder logic with local instruction database */ @instantiable -class DomainDecoder(val parameter: GpDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[GpDomainParam] { +class DomainDecoder(val b: GlobalConfig) extends Module { @public - val io = IO(new DomainDecoderIO) + val io = IO(new DomainDecoderIO(b)) import DomainDecoderParameter._ @@ -55,8 +51,8 @@ class DomainDecoder(val parameter: GpDomainParam)(implicit p: Parameters) val decode = Decoder.decode(decoderParam) // Decode the incoming instruction + // RoCCCommandBB has 'inst' field (RoCCInstruction Bundle), need to convert to UInt val inst = io.inst_i.inst.asUInt io.decoded_o := decode(inst) - override lazy val desiredName = "DomainDecoder" } diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 3087ee02..ce872d24 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -3,83 +3,30 @@ package framework.memdomain import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.frontend.decoder.PostGDCmd import freechips.rocketchip.tile._ - import framework.balldomain.blink.{BankRead, BankWrite} import freechips.rocketchip.tilelink.TLEdgeOut -import freechips.rocketchip.rocket.TLBPTWIO import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.memdomain.frontend.MemController -import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} -import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBIO} +import framework.memdomain.frontend.outside_channel.dma.{ + BBReadRequest, + BBReadResponse, + BBStreamReader, + BBStreamReaderParam, + BBStreamWriter, + BBStreamWriterParam, + BBWriteRequest, + BBWriteResponse +} +import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} import framework.memdomain.midend.MemScheduler import framework.memdomain.backend.MemManager - -object MemDomainParam { - implicit def rw: upickle.default.ReadWriter[MemDomainParam] = upickle.default.macroRW - - /** - * Load from JSON file - */ - def fromJson(path: String): MemDomainParam = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[MemDomainParam](jsonStr) - } - - /** - * Generate from global config - */ - def fromGlobal(global: framework.builtin.BaseConfig): MemDomainParam = { - MemDomainParam( - bankNum = global.bankNum, - bankWidth = global.bankWidth, - bankEntries = global.bankEntries, - bankMaskLen = global.bankMaskLen, - tlb_size = global.tlb_size, - rob_entries = global.rob_entries, - dma_maxbytes = global.dma_maxbytes, - memAddrLen = global.memAddrLen, - bankChannel = 8 // Default value - ) - } - -} - -case class MemDomainParam( - bankNum: Int, - bankWidth: Int, - bankEntries: Int, - bankMaskLen: Int, - tlb_size: Int, - rob_entries: Int, - dma_maxbytes: Int, - memAddrLen: Int, - bankChannel: Int) - extends SerializableModuleParameter { - override def toString: String = - s"""MemDomainParam - | Bank num: $bankNum - | Bank width: $bankWidth bits - | Bank entries: $bankEntries - | Bank mask length: $bankMaskLen - | TLB size: $tlb_size - | ROB entries: $rob_entries - | DMA max bytes: $dma_maxbytes - | Mem addr len: $memAddrLen - | Bank channel: $bankChannel - |""".stripMargin -} +import framework.top.GlobalConfig @instantiable -class MemDomain(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { @public val io = IO(new Bundle { @@ -87,9 +34,9 @@ class MemDomain(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Para // Command Channel // ------------------------------------------------- // global RS -> MemDomain - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries)(p))) + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) // MemDomain -> global RS - val global_complete_o = Decoupled(new GlobalRsComplete(parameter.rob_entries)(p)) + val global_complete_o = Decoupled(new GlobalRsComplete(b)) val busy = Output(Bool()) // ------------------------------------------------- @@ -97,22 +44,8 @@ class MemDomain(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Para // ------------------------------------------------- // Bank interface for interaction with Ball Domain val ballDomain = new Bundle { - - val bankRead = Vec( - parameter.bankNum, - new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum) - ) - - val bankWrite = Vec( - parameter.bankNum, - new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.bankNum - ) - ) + val bankRead = Vec(b.memDomain.bankNum, new BankRead(b)) + val bankWrite = Vec(b.memDomain.bankNum, new BankWrite(b)) } @@ -123,24 +56,24 @@ class MemDomain(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Para val read = new Bundle { val req = Decoupled(new BBReadRequest()) - val resp = Flipped(Decoupled(new BBReadResponse(parameter.bankWidth))) + val resp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) } val write = new Bundle { - val req = Decoupled(new BBWriteRequest(parameter.bankWidth)) + val req = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) val resp = Flipped(Decoupled(new BBWriteResponse)) } } - val tlb = Vec(2, Flipped(new BBTLBIO)) - val ptw = Vec(1, new TLBPTWIO) + val tlb = Vec(2, Flipped(new BBTLBIO(b))) + val ptw = Vec(1, new BBTLBPTWIO(b)) val tlbExp = Vec(1, new BBTLBExceptionIO) }) - val frontend: Instance[MemController] = Instantiate(new MemController(parameter)(edge)) - val midend: Instance[MemScheduler] = Instantiate(new MemScheduler(parameter)) - val backend: Instance[MemManager] = Instantiate(new MemManager(parameter)) + val frontend: Instance[MemController] = Instantiate(new MemController(b)(edge)) + val midend: Instance[MemScheduler] = Instantiate(new MemScheduler(b)) + val backend: Instance[MemManager] = Instantiate(new MemManager(b)) // ------------------------------------------------- // Connection with outside (all in frontend) @@ -171,4 +104,40 @@ class MemDomain(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Para // Midend to Backend: route scheduled requests to memory manager midend.io.mem_req <> backend.io.mem_req + + // ------------------------------------------------- + // DMA Modules (Reader and Writer) - Internal instantiation + // ------------------------------------------------- + val readerParam = BBStreamReaderParam( + nXacts = b.memDomain.dma_n_xacts, + beatBits = b.memDomain.dma_buswidth, + maxBytes = b.memDomain.dma_maxbytes, + dataWidth = b.memDomain.dma_buswidth, + tledge = edge + ) + + val writerParam = BBStreamWriterParam( + nXacts = b.memDomain.dma_n_xacts, + beatBits = b.memDomain.dma_buswidth, + maxBytes = b.memDomain.dma_maxbytes, + dataWidth = b.memDomain.dma_buswidth, + tledge = edge + ) + + val reader: Instance[BBStreamReader] = Instantiate(new BBStreamReader(readerParam, b)) + val writer: Instance[BBStreamWriter] = Instantiate(new BBStreamWriter(writerParam, b)) + + // Connect DMA to TLB and interfaces + reader.io.tlb <> io.tlb(1) + writer.io.tlb <> io.tlb(0) + + // Connect DMA to external DMA interface + io.dma.read.req <> reader.io.req + reader.io.resp <> io.dma.read.resp + io.dma.write.req <> writer.io.req + writer.io.resp <> io.dma.write.resp + + // Connect DMA flush signals to TLB exceptions + reader.io.flush := io.tlbExp(0).flush() + writer.io.flush := io.tlbExp(0).flush() } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala b/arch/src/main/scala/framework/memdomain/backend/MemManager.scala index 96922833..94e14c9a 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemManager.scala @@ -2,11 +2,8 @@ package framework.memdomain.backend import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.top.GlobalConfig import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import framework.memdomain.MemDomainParam import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} import framework.memdomain.backend.accpipe.AccPipe @@ -20,38 +17,36 @@ import framework.memdomain.backend.accpipe.AccPipe * - All requests go through AccPipe, which handles both direct write mode and accumulator mode (read-modify-write) * - Assert checks ensure no bank_id conflicts in the same cycle */ -class MemRequestIO(parameter: MemDomainParam) extends Bundle { - val write = Flipped(new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) - val read = Flipped(new SramReadIO(parameter.bankEntries, parameter.bankWidth)) - val bank_id = Input(UInt(log2Up(parameter.bankNum).W)) +class MemRequestIO(b: GlobalConfig) extends Bundle { + val write = Flipped(new SramWriteIO(b)) + val read = Flipped(new SramReadIO(b)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) } @instantiable -class MemManager(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemManager(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Interface from midend (new architecture) - val mem_req = Vec(parameter.bankChannel, new MemRequestIO(parameter)) + val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) }) // Instantiate bankNum SRAM banks - val banks: Seq[Instance[SramBank]] = Seq.fill(parameter.bankNum) { - Instantiate(new SramBank(parameter)) + val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum) { + Instantiate(new SramBank(b)) } // Instantiate bankChannel accumulator pipes (all requests go through AccPipe) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(parameter.bankChannel) { - Instantiate(new AccPipe(parameter)) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel) { + Instantiate(new AccPipe(b)) } // ----------------------------------------------------------------------------- // Request routing: All requests go through AccPipe // ----------------------------------------------------------------------------- // Route all requests to AccPipe (AccPipe handles both wmode and read operations) - for (i <- 0 until parameter.bankChannel) { + for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.write <> io.mem_req(i).write accPipes(i).io.read <> io.mem_req(i).read accPipes(i).io.bank_id := io.mem_req(i).bank_id @@ -61,8 +56,8 @@ class MemManager(val parameter: MemDomainParam)(implicit p: Parameters) // Bank conflict detection // ----------------------------------------------------------------------------- // Check for bank_id conflicts across all requests (all go through AccPipe) - for (i <- 0 until parameter.bankChannel) { - for (j <- (i + 1) until parameter.bankChannel) { + for (i <- 0 until b.memDomain.bankChannel) { + for (j <- (i + 1) until b.memDomain.bankChannel) { // Check write conflicts when(io.mem_req(i).write.req.valid && io.mem_req(j).write.req.valid) { assert( diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 20d49e7f..6c060c9e 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -2,11 +2,9 @@ package framework.memdomain.backend.accpipe import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO, SramWriteReq, SramWriteResp} +import framework.top.GlobalConfig +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} /** * AccPipe: Accumulator Pipeline @@ -14,26 +12,24 @@ import chisel3.experimental.{SerializableModule, SerializableModuleParameter} * Separated from SramBank for flexibility */ @instantiable -class AccPipe(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class AccPipe(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Interface to SramBank - val sramRead = new SramReadIO(parameter.bankEntries, parameter.bankWidth) - val sramWrite = new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen) + val sramRead = new SramReadIO(b) + val sramWrite = new SramWriteIO(b) // Interface from midend - val read = Flipped(new SramReadIO(parameter.bankEntries, parameter.bankWidth)) - val write = Flipped(new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) + val read = Flipped(new SramReadIO(b)) + val write = Flipped(new SramWriteIO(b)) // Control signals - val bank_id = Input(UInt(log2Up(parameter.bankNum).W)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) }) @public - val current_bank_id = Reg(UInt(log2Up(parameter.bankNum).W)) + val current_bank_id = Reg(UInt(log2Up(b.memDomain.bankNum).W)) @public val busy = Reg(Bool()) @@ -57,9 +53,9 @@ class AccPipe(val parameter: MemDomainParam)(implicit p: Parameters) } // Pipeline registers - val acc_addr = RegInit(0.U(log2Ceil(parameter.bankEntries).W)) - val acc_data = RegInit(0.U(parameter.bankWidth.W)) - val acc_mask = RegInit(VecInit(Seq.fill(parameter.bankMaskLen)(false.B))) + val acc_addr = RegInit(0.U(log2Ceil(b.memDomain.bankEntries).W)) + val acc_data = RegInit(0.U(b.memDomain.bankWidth.W)) + val acc_mask = RegInit(VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B))) // State machine logic when(state === s_idle) { diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala index 2151e39e..20220415 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala @@ -2,11 +2,9 @@ package framework.memdomain.backend.accpipe import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam +import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} /** * BankPipe: Bank Pipeline (直通，非流水线) @@ -15,26 +13,24 @@ import chisel3.experimental.{SerializableModule, SerializableModuleParameter} * Can also serve as a bypass when AccPipe is not fully utilized */ @instantiable -class BankPipe(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class BankPipe(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Interface to SramBank - val sramRead = new SramReadIO(parameter.bankEntries, parameter.bankWidth) - val sramWrite = new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen) + val sramRead = new SramReadIO(b) + val sramWrite = new SramWriteIO(b) // Interface from midend - val read = Flipped(new SramReadIO(parameter.bankEntries, parameter.bankWidth)) - val write = Flipped(new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) + val read = Flipped(new SramReadIO(b)) + val write = Flipped(new SramWriteIO(b)) // Control signals - val bank_id = Input(UInt(log2Up(parameter.bankNum).W)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) }) @public - val current_bank_id = Reg(UInt(log2Up(parameter.bankNum).W)) + val current_bank_id = Reg(UInt(log2Up(b.memDomain.bankNum).W)) @public val busy = Reg(Bool()) diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala index 7a5ad0a2..dab214a5 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala @@ -2,10 +2,8 @@ package framework.memdomain.backend.banks import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.top.GlobalConfig /** * SramBank: Pure SRAM bank @@ -13,22 +11,20 @@ import chisel3.experimental.{SerializableModule, SerializableModuleParameter} * Each bank is a single-port SRAM */ @instantiable -class SramBank(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class SramBank(val b: GlobalConfig) extends Module { val aligned_to = 8 - val mask_len = (parameter.bankWidth / (aligned_to * 8)) max 1 - val mask_elem = UInt((parameter.bankWidth min (aligned_to * 8)).W) + val mask_len = (b.memDomain.bankWidth / (aligned_to * 8)) max 1 + val mask_elem = UInt((b.memDomain.bankWidth min (aligned_to * 8)).W) @public val io = IO(new Bundle { // Bank interface (connected to MemManager) - val sramRead = new SramReadIO(parameter.bankEntries, parameter.bankWidth) - val sramWrite = new SramWriteIO(parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen) + val sramRead = new SramReadIO(b) + val sramWrite = new SramWriteIO(b) }) // SRAM memory - val mem = SyncReadMem(parameter.bankEntries, Vec(mask_len, mask_elem)) + val mem = SyncReadMem(b.memDomain.bankEntries, Vec(mask_len, mask_elem)) // ----------------------------------------------------------------------------- // Read path diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala index 912f3296..93e6356d 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala @@ -2,37 +2,39 @@ package framework.memdomain.backend.banks import chisel3._ import chisel3.util._ +import framework.top.GlobalConfig /** * Generic SRAM interface definitions */ -class SramReadReq(val n: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) +class SramReadReq(val b: GlobalConfig) extends Bundle { + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) val fromDMA = Bool() } -class SramReadResp(val w: Int) extends Bundle { - val data = UInt(w.W) +class SramReadResp(val b: GlobalConfig) extends Bundle { + val data = UInt(b.memDomain.bankWidth.W) val fromDMA = Bool() } -class SramReadIO(val n: Int, val w: Int) extends Bundle { - val req = Flipped(Decoupled(new SramReadReq(n))) - val resp = Decoupled(new SramReadResp(w)) +class SramReadIO(val b: GlobalConfig) extends Bundle { + val req = Flipped(Decoupled(new SramReadReq(b))) + val resp = Decoupled(new SramReadResp(b)) } -class SramWriteReq(val n: Int, val w: Int, val mask_len: Int) extends Bundle { - val addr = UInt(log2Ceil(n).W) - val mask = Vec(mask_len, Bool()) - val data = UInt(w.W) +class SramWriteReq(val b: GlobalConfig) extends Bundle { + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val data = UInt(b.memDomain.bankWidth.W) val wmode = Bool() // true=accumulator mode, false=direct write mode } -class SramWriteIO(val n: Int, val w: Int, val mask_len: Int) extends Bundle { - val req = Flipped(Decoupled(new SramWriteReq(n, w, mask_len))) - val resp = Decoupled(new SramWriteResp()) +class SramWriteIO(val b: GlobalConfig) extends Bundle { + val req = Flipped(Decoupled(new SramWriteReq(b))) + val resp = Decoupled(new SramWriteResp(b)) } -class SramWriteResp() extends Bundle { - val ok = Bool() +class SramWriteResp(val b: GlobalConfig) extends Bundle { + val ok = Bool() + val fromDMA = Bool() } diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala new file mode 100644 index 00000000..78f14504 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -0,0 +1,29 @@ +package framework.memdomain.configs + +import upickle.default._ + +/** + * MemDomain参数 + */ +case class MemDomainParam( + bankNum: Int, + bankWidth: Int, + bankEntries: Int, + bankMaskLen: Int, + tlb_size: Int, + dma_n_xacts: Int, + dma_maxbytes: Int, + bankChannel: Int, + max_in_flight_mem_reqs: Int, + dma_buswidth: Int, + memAddrLen: Int) + +object MemDomainParam { + implicit val rw: ReadWriter[MemDomainParam] = macroRW + + def apply(): MemDomainParam = { + val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/memdomain/configs/default.json").mkString + read[MemDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index 2e8a78a6..3bba2e9a 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -4,7 +4,9 @@ "bankEntries": 128, "bankMaskLen": 16, "tlb_size": 4, - "rob_entries": 16, "dma_maxbytes": 64, - "bankChannel": 8 + "bankChannel": 8, + "max_in_flight_mem_reqs": 16, + "dma_buswidth": 128, + "memAddrLen": 32 } diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala b/arch/src/main/scala/framework/memdomain/frontend/MemController.scala index fd570bdb..a36e6da1 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemController.scala @@ -2,60 +2,37 @@ package framework.memdomain.frontend import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig -import framework.frontend.decoder.PostGDCmd import freechips.rocketchip.tile._ import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.memdomain.frontend.outside_channel.{MemLoader, MemStorer} -import framework.memdomain.frontend.cmd_channel.rs.MemReservationStation -import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO} -import framework.memdomain.utils.pmc.MemCyclePMC +import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} import freechips.rocketchip.tilelink.TLEdgeOut -import freechips.rocketchip.rocket.TLBPTWIO import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import framework.memdomain.MemDomainParam +import framework.top.GlobalConfig +import framework.memdomain.frontend.cmd_channel.decoder.MemDomainDecoder +import framework.memdomain.frontend.cmd_channel.rs.MemReservationStation +import framework.memdomain.utils.pmc.MemCyclePMC /** * MemController: Controller that encapsulates scratchpad and accumulator * Provides DMA interface and Ball Domain interface */ @instantiable -class MemController(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { @public val io = IO(new Bundle { // Issue interface from global RS (single channel) - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(parameter.rob_entries))) - + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) // Report completion to global RS (single channel) - val global_complete_o = Decoupled(new GlobalRsComplete(parameter.rob_entries)) + val global_complete_o = Decoupled(new GlobalRsComplete(b)) // Bank read/write interface - used by load/store val interdma = new Bundle { - - val bankRead = Vec( - parameter.bankNum, - Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum)) - ) - - val bankWrite = Vec( - parameter.bankNum, - Flipped(new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.bankNum - )) - ) - + val bankRead = Vec(b.memDomain.bankNum, Flipped(new BankRead(b))) + val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) } // DMA interface - used by Outer DRAM controller @@ -63,11 +40,11 @@ class MemController(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: val read = new Bundle { val req = Decoupled(new BBReadRequest()) - val resp = Flipped(Decoupled(new BBReadResponse(parameter.bankWidth))) + val resp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) } val write = new Bundle { - val req = Decoupled(new BBWriteRequest(parameter.bankWidth)) + val req = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) val resp = Flipped(Decoupled(new BBWriteResponse)) } @@ -75,31 +52,24 @@ class MemController(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: // TLB interface - exposed externally for DMA modules (BBStreamReader/BBStreamWriter) // TLB connection is managed internally, but interface needs to be exposed for external DMA - val tlb = Vec(2, Flipped(new BBTLBIO)) - + val tlb = Vec(2, Flipped(new BBTLBIO(b))) // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) - val ptw = Vec(1, new TLBPTWIO) - + val ptw = Vec(1, new BBTLBPTWIO(b)) // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) val tlbExp = Vec(1, new BBTLBExceptionIO) - // Busy signal - val busy = Output(Bool()) + val busy = Output(Bool()) }) - val memDecoder: Instance[framework.memdomain.frontend.cmd_channel.decoder.MemDomainDecoder] = - Instantiate(new framework.memdomain.frontend.cmd_channel.decoder.MemDomainDecoder(parameter)) - val memRs: Instance[framework.memdomain.frontend.cmd_channel.rs.MemReservationStation] = - Instantiate(new framework.memdomain.frontend.cmd_channel.rs.MemReservationStation(parameter)) - val memLoader: Instance[framework.memdomain.frontend.outside_channel.MemLoader] = - Instantiate(new framework.memdomain.frontend.outside_channel.MemLoader(parameter)) - val memStorer: Instance[framework.memdomain.frontend.outside_channel.MemStorer] = - Instantiate(new framework.memdomain.frontend.outside_channel.MemStorer(parameter)) - + val memDecoder: Instance[MemDomainDecoder] = Instantiate(new MemDomainDecoder(b)) + val memRs: Instance[MemReservationStation] = Instantiate(new MemReservationStation(b)) + val memLoader: Instance[MemLoader] = Instantiate(new MemLoader(b)) + val memStorer: Instance[MemStorer] = Instantiate(new MemStorer(b)) + val pmc: Instance[MemCyclePMC] = Instantiate(new MemCyclePMC(b)) // TLB cluster - internal TLB management for DMA modules // Supports 2 clients: BBStreamReader (client 1) and BBStreamWriter (client 0) val tlbCluster = - Module(new BBTLBCluster(2, parameter.tlb_size, parameter.dma_maxbytes, use_shared_tlb = true)(edge, p)) + Instantiate(new BBTLBCluster(b)(edge)) // ----------------------------------------------------------------------------- // Global RS -> MemDecoder @@ -128,8 +98,6 @@ class MemController(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: //----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- - val pmc: Instance[framework.memdomain.utils.pmc.MemCyclePMC] = - Instantiate(new framework.memdomain.utils.pmc.MemCyclePMC(parameter)) pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire @@ -138,7 +106,7 @@ class MemController(val parameter: MemDomainParam)(edge: TLEdgeOut)(implicit p: pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits -// + // Connect MemLoader and MemStorer to DMA interface memLoader.io.dmaReq <> io.intradma.read.req io.intradma.read.resp <> memLoader.io.dmaResp diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index 8aa457f9..4da6fc37 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -2,13 +2,6 @@ package framework.memdomain.frontend.cmd_channel.decoder import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -// import framework.ballcore.ballcore.RoCCCommandBB -import freechips.rocketchip.tile._ - -class BuckyballRawCmd(implicit p: Parameters) extends Bundle { - val cmd = new RoCCCommand -} object DISA { val MSET_BITPAT = BitPat("b0010111") // 23 diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index 9d43d71f..e709eeb6 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -3,25 +3,22 @@ package framework.memdomain.frontend.cmd_channel.decoder import chisel3._ import chisel3.util._ import framework.frontend.decoder.{DomainId, PostGDCmd} -import framework.frontend.decoder.PostGDCmd -import framework.memdomain.MemDomainParam +import framework.top.GlobalConfig import framework.memdomain.frontend.cmd_channel.decoder.DISA._ import freechips.rocketchip.tile._ -import org.chipsalliance.cde.config.Parameters import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} // Detailed decode output for Mem domain -class MemDecodeCmd(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { +class MemDecodeCmd(b: GlobalConfig) extends Bundle { val is_load = Bool() val is_store = Bool() // Memory address - val mem_addr = UInt(parameter.memAddrLen.W) + val mem_addr = UInt(b.memDomain.memAddrLen.W) // Iteration count val iter = UInt(10.W) // Bank information // 3 bits, supports 8 banks (SPAD+ACC) - val bank_id = UInt(log2Up(parameter.bankNum).W) + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) val special = UInt(40.W) } @@ -41,19 +38,17 @@ object MemDefaultConstants { } @instantiable -class MemDomainDecoder(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemDomainDecoder(val b: GlobalConfig) extends Module { import MemDefaultConstants._ @public val io = IO(new Bundle { - val raw_cmd_i = Flipped(Decoupled(new PostGDCmd)) - val mem_decode_cmd_o = Decoupled(new MemDecodeCmd(parameter)) + val raw_cmd_i = Flipped(Decoupled(new PostGDCmd(b))) + val mem_decode_cmd_o = Decoupled(new MemDecodeCmd(b)) }) - val bankAddrLen = log2Up(parameter.bankEntries) - val memAddrLen = parameter.memAddrLen + val bankAddrLen = log2Up(b.memDomain.bankEntries) + val memAddrLen = b.memDomain.memAddrLen // Only process Mem instructions io.raw_cmd_i.ready := io.mem_decode_cmd_o.ready @@ -124,7 +119,7 @@ class MemDomainDecoder(val parameter: MemDomainParam)(implicit p: Parameters) io.mem_decode_cmd_o.bits.mem_addr := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.MEMADDR.id).asUInt, - 0.U(parameter.memAddrLen.W) + 0.U(b.memDomain.memAddrLen.W) ) io.mem_decode_cmd_o.bits.iter := Mux( io.mem_decode_cmd_o.valid, @@ -134,7 +129,7 @@ class MemDomainDecoder(val parameter: MemDomainParam)(implicit p: Parameters) // Address parsing val ls_bank_id = ls_decode_list(LSDecodeFields.BANK_ID.id).asUInt - io.mem_decode_cmd_o.bits.bank_id := Mux(io.mem_decode_cmd_o.valid, ls_bank_id, 0.U(log2Up(parameter.bankNum).W)) + io.mem_decode_cmd_o.bits.bank_id := Mux(io.mem_decode_cmd_o.valid, ls_bank_id, 0.U(log2Up(b.memDomain.bankNum).W)) io.mem_decode_cmd_o.bits.special := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.SPECIAL.id).asUInt, diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala index ee472f84..55d600d3 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala @@ -3,65 +3,61 @@ package framework.memdomain.frontend.cmd_channel.rs import chisel3._ import chisel3.util._ import chisel3.experimental._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam import framework.memdomain.frontend.cmd_channel.decoder.MemDecodeCmd import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.top.GlobalConfig // Mem domain issue interface - includes global rob_id -class MemRsIssue(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { - val cmd = new MemDecodeCmd(parameter) +class MemRsIssue(val b: GlobalConfig) extends Bundle { + val cmd = new MemDecodeCmd(b) // Global ROB ID - val rob_id = UInt(log2Up(parameter.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } // Mem domain completion interface -class MemRsComplete(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { - val rob_id = UInt(log2Up(parameter.rob_entries).W) +class MemRsComplete(val b: GlobalConfig) extends Bundle { + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } // Mem domain issue interface combination (Load + Store) -class MemIssueInterface(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { - val ld = Decoupled(new MemRsIssue(parameter)) - val st = Decoupled(new MemRsIssue(parameter)) +class MemIssueInterface(val b: GlobalConfig) extends Bundle { + val ld = Decoupled(new MemRsIssue(b)) + val st = Decoupled(new MemRsIssue(b)) } // Mem domain completion interface combination (Load + Store) -class MemCommitInterface(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { - val ld = Flipped(Decoupled(new MemRsComplete(parameter))) - val st = Flipped(Decoupled(new MemRsComplete(parameter))) +class MemCommitInterface(val b: GlobalConfig) extends Bundle { + val ld = Flipped(Decoupled(new MemRsComplete(b))) + val st = Flipped(Decoupled(new MemRsComplete(b))) } // Local Mem reservation station - simple FIFO scheduler @instantiable -class MemReservationStation(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemReservationStation(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Decoded instruction input (with global rob_id) val mem_decode_cmd_i = Flipped(new DecoupledIO(new Bundle { - val cmd = new MemDecodeCmd(parameter) + val cmd = new MemDecodeCmd(b) // Global ROB ID - val rob_id = UInt(log2Up(parameter.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) })) // Rs -> MemLoader/MemStorer - val issue_o = new MemIssueInterface(parameter) - val commit_i = new MemCommitInterface(parameter) + val issue_o = new MemIssueInterface(b) + val commit_i = new MemCommitInterface(b) // Output completion signal (with global rob_id, single channel) - val complete_o = Decoupled(new MemRsComplete(parameter)) + val complete_o = Decoupled(new MemRsComplete(b)) }) // Simple FIFO queue, only for buffering val fifo = Module(new Queue( new Bundle { - val cmd = new MemDecodeCmd(parameter) - val rob_id = UInt(log2Up(parameter.rob_entries).W) + val cmd = new MemDecodeCmd(b) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) }, entries = 4 )) // Small buffer is sufficient @@ -94,7 +90,7 @@ class MemReservationStation(val parameter: MemDomainParam)(implicit p: Parameter // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(parameter.rob_entries).W), 2)) + val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), 2)) completeArb.io.in(0).valid := io.commit_i.ld.valid completeArb.io.in(0).bits := io.commit_i.ld.bits.rob_id diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala index d6e24947..e488697e 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/rob.scala @@ -3,27 +3,26 @@ package framework.memdomain.frontend.cmd_channel.rs import chisel3._ import chisel3.util._ import chisel3.experimental._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam import framework.memdomain.frontend.cmd_channel.decoder.MemDecodeCmd +import framework.top.GlobalConfig // ROB entry data structure - preserves ROB ID to support out-of-order completion -class RobEntry(parameter: MemDomainParam)(implicit p: Parameters) extends Bundle { - val cmd = new MemDecodeCmd(parameter) - val rob_id = UInt(log2Up(parameter.rob_entries).W) +class RobEntry(b: GlobalConfig) extends Bundle { + val cmd = new MemDecodeCmd(b) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } -class ROB(parameter: MemDomainParam)(implicit p: Parameters) extends Module { +class ROB(val b: GlobalConfig) extends Module { val io = IO(new Bundle { // Allocation interface - val alloc = Flipped(new DecoupledIO(new MemDecodeCmd(parameter))) + val alloc = Flipped(new DecoupledIO(new MemDecodeCmd(b))) // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new RobEntry(parameter)) + val issue = new DecoupledIO(new RobEntry(b)) // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(parameter.rob_entries).W))) + val complete = Flipped(new DecoupledIO(UInt(log2Up(b.frontend.rob_entries).W))) // Commit interface - commit completed head instruction // val commit = new DecoupledIO(new RobEntry) @@ -34,13 +33,13 @@ class ROB(parameter: MemDomainParam)(implicit p: Parameters) extends Module { }) // Only use FIFO + completion status table, only enqueue/dequeue, sequential execution and sequential completion - val robFifo = Module(new Queue(new RobEntry(parameter), parameter.rob_entries)) - val robIdCounter = RegInit(0.U(log2Up(parameter.rob_entries).W)) + val robFifo = Module(new Queue(new RobEntry(b), b.frontend.rob_entries)) + val robIdCounter = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // Initialize to false to avoid X states in FPGA - val robTable = RegInit(VecInit(Seq.fill(parameter.rob_entries)(false.B))) + val robTable = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) // Initialize completion status table - for (i <- 0 until parameter.rob_entries) { + for (i <- 0 until b.frontend.rob_entries) { when(reset.asBool) { robTable(i) := true.B } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 06fa0a88..b36da430 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -2,42 +2,32 @@ package framework.memdomain.frontend.outside_channel import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import framework.memdomain.backend.banks.SramWriteIO import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse} import freechips.rocketchip.rocket.MStatus import framework.balldomain.blink.BankWrite import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import framework.top.GlobalConfig @instantiable -class MemLoader(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { - val rob_id_width = log2Up(parameter.rob_entries) +class MemLoader(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) @public val io = IO(new Bundle { // Load instruction from ReservationStation - val cmdReq = Flipped(Decoupled(new MemRsIssue(parameter))) + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) // Completion signal sent to ReservationStation - val cmdResp = Decoupled(new MemRsComplete(parameter)) + val cmdResp = Decoupled(new MemRsComplete(b)) // Direct connection to DMA read interface val dmaReq = Decoupled(new BBReadRequest()) - val dmaResp = Flipped(Decoupled(new BBReadResponse(parameter.bankWidth))) + val dmaResp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) // Connected to Bank write interface val bankWrite = Vec( - parameter.bankNum, - Flipped(new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.bankNum - )) + b.memDomain.bankNum, + Flipped(new BankWrite(b)) ) }) @@ -47,14 +37,14 @@ class MemLoader(val parameter: MemDomainParam)(implicit p: Parameters) val rob_id_reg = RegInit(0.U(rob_id_width.W)) // Cache mem_addr - val mem_addr_reg = Reg(UInt(parameter.memAddrLen.W)) + val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) // Cache iteration count val iter_reg = Reg(UInt(10.W)) // Count number of responses received, supports up to 16 responses val resp_count = Reg(UInt(log2Up(16).W)) // Cache decoded bank information - val wr_bank_reg = Reg(UInt(log2Up(parameter.bankNum).W)) + val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) // Cache stride val stride_reg = Reg(UInt(10.W)) @@ -75,7 +65,7 @@ class MemLoader(val parameter: MemDomainParam)(implicit p: Parameters) io.dmaReq.valid := state === s_dma_req io.dmaReq.bits.vaddr := mem_addr_reg // Byte count of iter rows of data - io.dmaReq.bits.len := iter_reg * (parameter.bankWidth / 8).U + io.dmaReq.bits.len := iter_reg * (b.memDomain.bankWidth / 8).U // Simplified: use default status io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) io.dmaReq.bits.stride := stride_reg @@ -102,11 +92,11 @@ class MemLoader(val parameter: MemDomainParam)(implicit p: Parameters) val target_bank = wr_bank_reg val target_row = io.dmaResp.bits.addrcounter - for (i <- 0 until parameter.bankNum) { + for (i <- 0 until b.memDomain.bankNum) { io.bankWrite(i).io.req.valid := io.dmaResp.fire && (target_bank === i.U) io.bankWrite(i).io.req.bits.addr := target_row io.bankWrite(i).io.req.bits.data := io.dmaResp.bits.data - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) io.bankWrite(i).io.req.bits.wmode := false.B // Load is always overwrite io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).bank_id := target_bank diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 1eff7865..d1addf33 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -2,40 +2,36 @@ package framework.memdomain.frontend.outside_channel import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam +import framework.top.GlobalConfig import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import freechips.rocketchip.rocket.MStatus import framework.memdomain.backend.banks.SramReadIO import framework.memdomain.frontend.outside_channel.dma.{BBWriteRequest, BBWriteResponse} import framework.balldomain.blink.BankRead import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} @instantiable -class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { - val rob_id_width = log2Up(parameter.rob_entries) +class MemStorer(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) // Byte count of one row of data - val line_bytes = parameter.bankWidth / 8 + val line_bytes = b.memDomain.bankWidth / 8 // 16-byte alignment val align_bytes = 16 @public val io = IO(new Bundle { // Store instruction from ReservationStation - val cmdReq = Flipped(Decoupled(new MemRsIssue(parameter))) + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) // Completion signal sent to ReservationStation - val cmdResp = Decoupled(new MemRsComplete(parameter)) + val cmdResp = Decoupled(new MemRsComplete(b)) // Direct connection to DMA write interface - val dmaReq = Decoupled(new BBWriteRequest(parameter.bankWidth)) + val dmaReq = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) val dmaResp = Flipped(Decoupled(new BBWriteResponse)) // Connected to Bank read interface val bankRead = Vec( - parameter.bankNum, - Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum)) + b.memDomain.bankNum, + Flipped(new BankRead(b)) ) }) @@ -44,13 +40,13 @@ class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val mem_addr_reg = Reg(UInt(parameter.memAddrLen.W)) + val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) val iter_reg = Reg(UInt(10.W)) val sram_count = Reg(UInt(10.W)) // Cache stride val stride_reg = Reg(UInt(10.W)) // Cache decoded bank information - val rd_bank_reg = Reg(UInt(log2Up(parameter.bankNum).W)) + val rd_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) // Data buffer related registers // 16-byte buffer @@ -58,7 +54,7 @@ class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) // Number of valid bytes in buffer val buffer_valid_bytes = Reg(UInt(log2Ceil(align_bytes + 1).W)) // Starting address corresponding to buffer - val buffer_start_addr = Reg(UInt(parameter.memAddrLen.W)) + val buffer_start_addr = Reg(UInt(b.memDomain.memAddrLen.W)) // Receive store instruction io.cmdReq.ready := state === s_idle @@ -80,7 +76,7 @@ class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) val target_bank = rd_bank_reg val target_row = sram_count - for (i <- 0 until parameter.bankNum) { + for (i <- 0 until b.memDomain.bankNum) { io.bankRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) io.bankRead(i).io.req.bits.addr := target_row io.bankRead(i).io.req.bits.fromDMA := true.B @@ -97,7 +93,8 @@ class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) mem_addr_reg + sram_count(1, 0) * line_bytes.U + ((sram_count >> 2) << 2) * stride_reg * line_bytes.U // Lower 4 bits of address, 0 when 16-byte aligned val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) - val aligned_addr = Cat(current_mem_addr(parameter.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) + val aligned_addr = + Cat(current_mem_addr(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) val is_aligned = addr_offset === 0.U dontTouch(is_aligned) dontTouch(aligned_addr) @@ -140,7 +137,7 @@ class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) val send_addr = Mux( buffer_valid_bytes === 0.U, aligned_addr, - Cat(buffer_start_addr(parameter.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) + Cat(buffer_start_addr(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) ) // DMA request logic @@ -178,7 +175,7 @@ class MemStorer(val parameter: MemDomainParam)(implicit p: Parameters) // DMA request signal control logic - can only update when DMA is ready val dma_req_valid_reg = RegInit(false.B) - val dma_req_vaddr_reg = RegInit(0.U(parameter.memAddrLen.W)) + val dma_req_vaddr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) val dma_req_data_reg = RegInit(0.U((align_bytes * 8).W)) val dma_req_len_reg = RegInit(0.U(8.W)) val dma_req_mask_reg = RegInit(0.U(align_bytes.W)) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala new file mode 100644 index 00000000..6d972021 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala @@ -0,0 +1,181 @@ +package framework.memdomain.frontend.outside_channel.dma + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.rocket.{MStatus, M_XRD} +import freechips.rocketchip.rocket.constants.MemoryOpConstants + +import framework.utils.Util._ +import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO +import framework.top.GlobalConfig + +class BBReadRequest extends Bundle { + val vaddr = UInt(64.W) + // Read length (bytes) + val len = UInt(16.W) + val status = new MStatus + // Stride (bytes) + val stride = UInt(10.W) +} + +class BBReadResponse(dataWidth: Int) extends Bundle { + val data = UInt(dataWidth.W) + val last = Bool() + val addrcounter = UInt(10.W) +} + +case class BBStreamReaderParam( + nXacts: Int, + beatBits: Int, + maxBytes: Int, + dataWidth: Int, + tledge: TLEdgeOut) + +@instantiable +class BBStreamReader(val parameter: BBStreamReaderParam, val b: GlobalConfig) extends Module { + + val vaddrBits = b.core.vaddrBits + + @public + val io = IO(new Bundle { + val req = Flipped(Decoupled(new BBReadRequest())) + val resp = Decoupled(new BBReadResponse(parameter.dataWidth)) + val tlb = new BBTLBIO(b) + val busy = Output(Bool()) + val flush = Input(Bool()) + }) + + val edge = parameter.tledge + val beatBytes = parameter.beatBits / 8 + + val s_idle :: s_req_new_block :: Nil = Enum(2) + val state = RegInit(s_idle) + + val req = Reg(new BBReadRequest()) + // Number of bytes requested + val bytesRequested = Reg(UInt(16.W)) + // Number of bytes received + val bytesReceived = Reg(UInt(16.W)) + val bytesLeft = req.len - bytesRequested + + // Select request size - simplified version, fixed use of beatBytes + val read_size = minOf(beatBytes.U, bytesLeft) + val read_vaddr = req.vaddr + bytesRequested * req.stride + + // Track byte range corresponding to each request for correct last signal calculation + // Starting byte position of current request + val req_byte_start = Reg(UInt(16.W)) + // Ending byte position of current request + val req_byte_end = Wire(UInt(16.W)) + req_byte_end := req_byte_start + read_size + + // Transaction ID management + val xactBusy = RegInit(0.U(parameter.nXacts.W)) + val xactOnehot = PriorityEncoderOH(~xactBusy) + val xactId = OHToUInt(xactOnehot) + + val xactBusy_fire = WireInit(false.B) + val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) + val xactBusy_remove = ~Mux(io.tlb.resp.valid && !io.tlb.resp.bits.miss, (1.U << xactId).asUInt, 0.U) + xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt + + // TileLink request construction - return to single beat requests to avoid address alignment issues + val get = edge.Get( + fromSource = xactId, + toAddress = 0.U, + // Request only one beat each time + lgSize = log2Ceil(beatBytes).U + )._2 + + // TLB processing pipeline - simplified based on Gemmini + class TLBundleAWithInfo extends Bundle { + val tl_a = get.cloneType + val vaddr = Output(UInt(vaddrBits.W)) + val status = Output(new MStatus) + } + + val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) + xactBusy_fire := untranslated_a.fire && state === s_req_new_block + untranslated_a.valid := state === s_req_new_block && !xactBusy.andR + untranslated_a.bits.tl_a := get + untranslated_a.bits.vaddr := read_vaddr + untranslated_a.bits.status := req.status + + // Simplified: no retry mechanism, direct connection + val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) + tlb_q.io.enq <> untranslated_a + + io.tlb.req.valid := tlb_q.io.deq.fire + io.tlb.req.bits := DontCare + io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr + io.tlb.req.bits.passthrough := false.B + io.tlb.req.bits.size := 0.U + io.tlb.req.bits.cmd := M_XRD + io.tlb.req.bits.prv := 3.U // Machine mode + io.tlb.req.bits.v := false.B + io.tlb.req.bits.status := tlb_q.io.deq.bits.status + + val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) + translate_q.io.enq <> tlb_q.io.deq + translate_q.io.deq.ready := io.tlb.resp.fire || io.tlb.resp.bits.miss + + // TileLink connection - using parameterized edge + val tl_a = Wire(Decoupled(get.cloneType)) + tl_a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss + tl_a.bits := translate_q.io.deq.bits.tl_a + tl_a.bits.address := io.tlb.resp.bits.paddr + + // Iteration counter for tracking number of requests + val iter_counter = RegInit(0.U(10.W)) + // Table for managing iteration counts + val iter_mangage_table = RegInit(VecInit(Seq.fill(16)(0.U(10.W)))) + // Iteration count management - update after each request + when(tl_a.fire) { + iter_counter := iter_counter + 1.U + iter_mangage_table(xactId) := iter_counter + } + + // Response processing - simplified without edge + io.resp.valid := io.tlb.resp.valid && !io.tlb.resp.bits.miss + io.resp.bits.data := DontCare + // Use source as address counter + io.resp.bits.addrcounter := iter_mangage_table(xactId) + // Fix last signal: calculate using received byte count + // Total byte count after receiving current beat + val resp_bytes_end = bytesReceived + beatBytes.U + io.resp.bits.last := io.tlb.resp.valid && !io.tlb.resp.bits.miss && (resp_bytes_end >= req.len) + + // Update received byte count + when(io.tlb.resp.valid && !io.tlb.resp.bits.miss) { + bytesReceived := bytesReceived + beatBytes.U + } + + // State machine + io.req.ready := state === s_idle + io.busy := xactBusy.orR || (state =/= s_idle) + + when(io.req.fire) { + req := io.req.bits + bytesRequested := 0.U + // Reset received byte count + bytesReceived := 0.U + // Reset iteration counter + iter_counter := 0.U + state := s_req_new_block + } + + when(untranslated_a.fire) { + // Use actual requested byte count + bytesRequested := bytesRequested + read_size + // Check if more requests need to be sent + when(bytesRequested + read_size >= req.len) { + // All requests sent + state := s_idle + }.otherwise { + // Continue sending next request + state := s_req_new_block + } + } +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala new file mode 100644 index 00000000..c121b534 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala @@ -0,0 +1,139 @@ +package framework.memdomain.frontend.outside_channel.dma + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.rocket.{MStatus, M_XWR} + +import framework.utils.Util._ +import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO +import framework.top.GlobalConfig + +class BBWriteRequest(dataWidth: Int) extends Bundle { + val vaddr = UInt(64.W) + val data = UInt(dataWidth.W) + // Write length (bytes) + val len = UInt(16.W) + // Byte mask + val mask = UInt((dataWidth / 8).W) + val status = new MStatus +} + +class BBWriteResponse extends Bundle { + val done = Bool() +} + +case class BBStreamWriterParam( + nXacts: Int, + beatBits: Int, + maxBytes: Int, + dataWidth: Int, + tledge: TLEdgeOut) + +@instantiable +class BBStreamWriter(val parameter: BBStreamWriterParam, val b: GlobalConfig) extends Module { + + val vaddrBits = b.core.vaddrBits + + @public + val io = IO(new Bundle { + val req = Flipped(Decoupled(new BBWriteRequest(parameter.dataWidth))) + val resp = Decoupled(new BBWriteResponse) + val tlb = new BBTLBIO(b) + val busy = Output(Bool()) + val flush = Input(Bool()) + }) + + val edge = parameter.tledge + val beatBytes = parameter.beatBits / 8 + + val s_idle :: s_writing :: Nil = Enum(2) + val state = RegInit(s_idle) + + val req = Reg(new BBWriteRequest(parameter.dataWidth)) + + val xactBusy = RegInit(0.U(parameter.nXacts.W)) + val xactOnehot = PriorityEncoderOH(~xactBusy) + val xactId = OHToUInt(xactOnehot) + + val xactBusy_fire = WireInit(false.B) + val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) + val xactBusy_remove = ~Mux(io.tlb.resp.valid && !io.tlb.resp.bits.miss, (1.U << xactId).asUInt, 0.U) + xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt + + // Simplified: data is already aligned, directly construct TileLink request + val lg_beat_bytes = log2Ceil(beatBytes) + val use_put_full = req.mask === ~0.U(beatBytes.W) + + val putFull = edge.Put( + fromSource = xactId, + toAddress = 0.U, + lgSize = lg_beat_bytes.U, + data = req.data + )._2 + + val putPartial = edge.Put( + fromSource = xactId, + toAddress = 0.U, + lgSize = lg_beat_bytes.U, + data = req.data, + mask = req.mask + )._2 + + val selected_put = Mux(use_put_full, putFull, putPartial) + + // TLB processing pipeline + class TLBundleAWithInfo extends Bundle { + val tl_a = selected_put.cloneType + val vaddr = Output(UInt(vaddrBits.W)) + val status = Output(new MStatus) + } + + val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) + xactBusy_fire := untranslated_a.fire + untranslated_a.valid := state === s_writing && !xactBusy.andR + untranslated_a.bits.tl_a := selected_put + untranslated_a.bits.vaddr := req.vaddr + untranslated_a.bits.status := req.status + + val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) + tlb_q.io.enq <> untranslated_a + + io.tlb.req.valid := tlb_q.io.deq.valid + io.tlb.req.bits := DontCare + io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr + io.tlb.req.bits.passthrough := false.B + io.tlb.req.bits.size := 0.U + io.tlb.req.bits.cmd := M_XWR + io.tlb.req.bits.prv := 3.U // Machine mode + io.tlb.req.bits.v := false.B + io.tlb.req.bits.status := tlb_q.io.deq.bits.status + + val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) + translate_q.io.enq <> tlb_q.io.deq + translate_q.io.deq.ready := io.tlb.resp.valid || io.tlb.resp.bits.miss + + // TileLink connection - using parameterized edge + val tl_a = Wire(Decoupled(selected_put.cloneType)) + tl_a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss + tl_a.bits := translate_q.io.deq.bits.tl_a + tl_a.bits.address := io.tlb.resp.bits.paddr + + // Response processing + io.resp.valid := io.tlb.resp.valid && !io.tlb.resp.bits.miss + io.resp.bits.done := true.B + + // State machine + io.req.ready := state === s_idle + io.busy := xactBusy.orR || (state =/= s_idle) + + when(io.req.fire) { + req := io.req.bits + state := s_writing + } + + when(untranslated_a.fire) { + state := s_idle + } +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/DMA.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/DMA.scala deleted file mode 100644 index 6b89c842..00000000 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/DMA.scala +++ /dev/null @@ -1,321 +0,0 @@ -package framework.memdomain.frontend.outside_channel.dma - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} -import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.rocket.MStatus -import freechips.rocketchip.rocket.constants.MemoryOpConstants - -import framework.builtin.util.Util._ -import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO - -class BBReadRequest()(implicit p: Parameters) extends CoreBundle { - val vaddr = UInt(coreMaxAddrBits.W) - // Read length (bytes) - val len = UInt(16.W) - val status = new MStatus - // Stride (bytes) - val stride = UInt(10.W) -} - -class BBReadResponse(dataWidth: Int) extends Bundle { - val data = UInt(dataWidth.W) - val last = Bool() - val addrcounter = UInt(10.W) -} - -class BBWriteRequest(dataWidth: Int)(implicit p: Parameters) extends CoreBundle { - val vaddr = UInt(coreMaxAddrBits.W) - val data = UInt(dataWidth.W) - // Write length (bytes) - val len = UInt(16.W) - // Byte mask - val mask = UInt((dataWidth / 8).W) - val status = new MStatus -} - -class BBWriteResponse extends Bundle { - val done = Bool() -} - -class BBStreamReader( - nXacts: Int, - beatBits: Int, - maxBytes: Int, - dataWidth: Int -)( - implicit p: Parameters) - extends LazyModule { - - val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "buckyball-stream-reader", - sourceId = IdRange(0, nXacts) - ))))) - - lazy val module = new Impl - - class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { - val (tl, edge) = node.out(0) - val beatBytes = beatBits / 8 - - val io = IO(new Bundle { - val req = Flipped(Decoupled(new BBReadRequest())) - val resp = Decoupled(new BBReadResponse(dataWidth)) - val tlb = new BBTLBIO - val busy = Output(Bool()) - val flush = Input(Bool()) - }) - - val s_idle :: s_req_new_block :: Nil = Enum(2) - val state = RegInit(s_idle) - - val req = Reg(new BBReadRequest()) - // Number of bytes requested - val bytesRequested = Reg(UInt(16.W)) - // Number of bytes received - val bytesReceived = Reg(UInt(16.W)) - val bytesLeft = req.len - bytesRequested - - // Select request size - simplified version, fixed use of beatBytes - val read_size = minOf(beatBytes.U, bytesLeft) - val read_vaddr = req.vaddr + bytesRequested * req.stride - - // Track byte range corresponding to each request for correct last signal calculation - // Starting byte position of current request - val req_byte_start = Reg(UInt(16.W)) - // Ending byte position of current request - val req_byte_end = Wire(UInt(16.W)) - req_byte_end := req_byte_start + read_size - - // Transaction ID management - val xactBusy = RegInit(0.U(nXacts.W)) - val xactOnehot = PriorityEncoderOH(~xactBusy) - val xactId = OHToUInt(xactOnehot) - - val xactBusy_fire = WireInit(false.B) - val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) - val xactBusy_remove = ~Mux(tl.d.fire, (1.U << tl.d.bits.source).asUInt, 0.U) - xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt - - // TileLink request construction - return to single beat requests to avoid address alignment issues - val get = edge.Get( - fromSource = xactId, - toAddress = 0.U, - // Request only one beat each time - lgSize = log2Ceil(beatBytes).U - )._2 - - // TLB processing pipeline - simplified based on Gemmini - class TLBundleAWithInfo extends Bundle { - val tl_a = tl.a.bits.cloneType - val vaddr = Output(UInt(vaddrBits.W)) - val status = Output(new MStatus) - } - - val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) - xactBusy_fire := untranslated_a.fire && state === s_req_new_block - untranslated_a.valid := state === s_req_new_block && !xactBusy.andR - untranslated_a.bits.tl_a := get - untranslated_a.bits.vaddr := read_vaddr - untranslated_a.bits.status := req.status - - // Simplified: no retry mechanism, direct connection - val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - tlb_q.io.enq <> untranslated_a - - io.tlb.req.valid := tlb_q.io.deq.fire - io.tlb.req.bits := DontCare - io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.tlb_req.passthrough := false.B - io.tlb.req.bits.tlb_req.size := 0.U - io.tlb.req.bits.tlb_req.cmd := M_XRD - io.tlb.req.bits.status := tlb_q.io.deq.bits.status - - val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - translate_q.io.enq <> tlb_q.io.deq - translate_q.io.deq.ready := tl.a.ready || io.tlb.resp.miss - - // TileLink connection - tl.a.valid := translate_q.io.deq.valid - tl.a.bits := translate_q.io.deq.bits.tl_a - tl.a.bits.address := io.tlb.resp.paddr - - // Iteration counter for tracking number of requests - val iter_counter = RegInit(0.U(10.W)) - // Table for managing iteration counts - val iter_mangage_table = RegInit(VecInit(Seq.fill(16)(0.U(10.W)))) - // Iteration count management - update after each request - when(tl.a.fire) { - iter_counter := iter_counter + 1.U - iter_mangage_table(tl.a.bits.source) := iter_counter - } - - // Response processing - io.resp.valid := tl.d.valid - io.resp.bits.data := tl.d.bits.data - // Use source as address counter - io.resp.bits.addrcounter := iter_mangage_table(tl.d.bits.source) - // Fix last signal: calculate using received byte count - // Total byte count after receiving current beat - val resp_bytes_end = bytesReceived + beatBytes.U - io.resp.bits.last := edge.last(tl.d) && (resp_bytes_end >= req.len) - tl.d.ready := io.resp.ready - - // Update received byte count - when(tl.d.fire) { - bytesReceived := bytesReceived + beatBytes.U - } - - // State machine - io.req.ready := state === s_idle - io.busy := xactBusy.orR || (state =/= s_idle) - - when(io.req.fire) { - req := io.req.bits - bytesRequested := 0.U - // Reset received byte count - bytesReceived := 0.U - // Reset iteration counter - iter_counter := 0.U - state := s_req_new_block - } - - when(untranslated_a.fire) { - // Use actual requested byte count - bytesRequested := bytesRequested + read_size - // Check if more requests need to be sent - when(bytesRequested + read_size >= req.len) { - // All requests sent - state := s_idle - }.otherwise { - // Continue sending next request - state := s_req_new_block - } - } - } - -} - -// Convention: data is already aligned and has mask -class BBStreamWriter( - nXacts: Int, - beatBits: Int, - maxBytes: Int, - dataWidth: Int -)( - implicit p: Parameters) - extends LazyModule { - - val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "buckyball-stream-writer", - sourceId = IdRange(0, nXacts) - ))))) - - lazy val module = new Impl - - class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { - val (tl, edge) = node.out(0) - val beatBytes = beatBits / 8 - - val io = IO(new Bundle { - val req = Flipped(Decoupled(new BBWriteRequest(dataWidth))) - val resp = Decoupled(new BBWriteResponse) - val tlb = new BBTLBIO - val busy = Output(Bool()) - val flush = Input(Bool()) - }) - - val s_idle :: s_writing :: Nil = Enum(2) - val state = RegInit(s_idle) - - val req = Reg(new BBWriteRequest(dataWidth)) - - val xactBusy = RegInit(0.U(nXacts.W)) - val xactOnehot = PriorityEncoderOH(~xactBusy) - val xactId = OHToUInt(xactOnehot) - - val xactBusy_fire = WireInit(false.B) - val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) - val xactBusy_remove = ~Mux(tl.d.fire, (1.U << tl.d.bits.source).asUInt, 0.U) - xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt - - // Simplified: data is already aligned, directly construct TileLink request - val lg_beat_bytes = log2Ceil(beatBytes) - val use_put_full = req.mask === ~0.U(beatBytes.W) - - val putFull = edge.Put( - fromSource = xactId, - toAddress = 0.U, - lgSize = lg_beat_bytes.U, - data = req.data - )._2 - - val putPartial = edge.Put( - fromSource = xactId, - toAddress = 0.U, - lgSize = lg_beat_bytes.U, - data = req.data, - mask = req.mask - )._2 - - val selected_put = Mux(use_put_full, putFull, putPartial) - - // TLB processing pipeline - class TLBundleAWithInfo extends Bundle { - val tl_a = tl.a.bits.cloneType - val vaddr = Output(UInt(vaddrBits.W)) - val status = Output(new MStatus) - } - - val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) - xactBusy_fire := untranslated_a.fire - untranslated_a.valid := state === s_writing && !xactBusy.andR - untranslated_a.bits.tl_a := selected_put - untranslated_a.bits.vaddr := req.vaddr - untranslated_a.bits.status := req.status - - val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - tlb_q.io.enq <> untranslated_a - - io.tlb.req.valid := tlb_q.io.deq.valid - io.tlb.req.bits := DontCare - io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.tlb_req.passthrough := false.B - io.tlb.req.bits.tlb_req.size := 0.U - io.tlb.req.bits.tlb_req.cmd := M_XWR - io.tlb.req.bits.status := tlb_q.io.deq.bits.status - - val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - translate_q.io.enq <> tlb_q.io.deq - translate_q.io.deq.ready := tl.a.ready || io.tlb.resp.miss - - // TileLink connection - tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss - tl.a.bits := translate_q.io.deq.bits.tl_a - tl.a.bits.address := io.tlb.resp.paddr - - tl.d.ready := true.B - - // Response processing - io.resp.valid := tl.d.valid && edge.last(tl.d) - io.resp.bits.done := true.B - - // State machine - io.req.ready := state === s_idle - io.busy := xactBusy.orR || (state =/= s_idle) - - when(io.req.fire) { - req := io.req.bits - state := s_writing - } - - when(untranslated_a.fire) { - state := s_idle - } - } - -} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLB.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLB.scala deleted file mode 100644 index ddf91fec..00000000 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLB.scala +++ /dev/null @@ -1,76 +0,0 @@ -package framework.memdomain.frontend.outside_channel.tlb - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile.{CoreBundle, CoreModule} -import freechips.rocketchip.tilelink.TLEdgeOut - -import framework.builtin.util.Util._ - -class BBTLBReq(val lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle { - val tlb_req = new TLBReq(lgMaxSize) - val status = new MStatus -} - -class BBTLBExceptionIO extends Bundle { - val interrupt = Output(Bool()) - val flush_retry = Input(Bool()) - val flush_skip = Input(Bool()) - - def flush(dummy: Int = 0): Bool = flush_retry || flush_skip -} - -class BBTLB(entries: Int, maxSize: Int)(implicit val edge: TLEdgeOut, p: Parameters) extends CoreModule { - - val lgMaxSize = log2Ceil(maxSize) - - val io = IO(new Bundle { - val req = Flipped(Valid(new BBTLBReq(lgMaxSize))) - val resp = new TLBResp - val ptw = new TLBPTWIO - val exp = new BBTLBExceptionIO - }) - - val interrupt = RegInit(false.B) - io.exp.interrupt := interrupt - - val tlb = Module(new TLB(false, lgMaxSize, TLBConfig(nSets = 1, nWays = entries))) - tlb.io.req.valid := io.req.valid - tlb.io.req.bits := io.req.bits.tlb_req - io.resp := tlb.io.resp - tlb.io.kill := false.B - - tlb.io.sfence.valid := io.exp.flush() - tlb.io.sfence.bits.rs1 := false.B - tlb.io.sfence.bits.rs2 := false.B - tlb.io.sfence.bits.addr := DontCare - tlb.io.sfence.bits.asid := DontCare - tlb.io.sfence.bits.hv := false.B - tlb.io.sfence.bits.hg := false.B - - io.ptw <> tlb.io.ptw - tlb.io.ptw.status := io.req.bits.status - - val exception = io.req.valid && Mux( - io.req.bits.tlb_req.cmd === M_XRD, - tlb.io.resp.pf.ld || tlb.io.resp.ae.ld || tlb.io.resp.gf.ld, - tlb.io.resp.pf.st || tlb.io.resp.ae.st || tlb.io.resp.gf.st - ) - - when(exception) { - interrupt := true.B - } - - when(interrupt && io.exp.flush_skip) { - interrupt := false.B - } - - when(interrupt && io.exp.flush_retry) { - interrupt := false.B - } - - assert(!io.exp.flush_retry || !io.exp.flush_skip, "TLB: flushing with both retry and skip at same time") -} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala new file mode 100644 index 00000000..0cea594d --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala @@ -0,0 +1,171 @@ +package framework.memdomain.frontend.outside_channel.tlb + +import chisel3._ +import chisel3.util.{Decoupled, Valid} +import chisel3.util.log2Ceil +import framework.top.GlobalConfig + +// TLB Exception types +class TLBExceptions extends Bundle { + val ld = Bool() + val st = Bool() + val inst = Bool() +} + +// MStatus - Simplified status register +class BBTLBMStatus(val xLen: Int) extends Bundle { + val prv = UInt(2.W) + val v = Bool() + val mxr = Bool() + val sum = Bool() + val debug = Bool() +} + +// TLB Request +class BBTLBReq(val lgMaxSize: Int, val vaddrBits: Int, val xLen: Int) extends Bundle { + val vaddr = UInt(vaddrBits.W) + val passthrough = Bool() + val size = UInt(log2Ceil(lgMaxSize + 1).W) + val cmd = Bits(5.W) // M_SZ = 5 + val prv = UInt(2.W) // PRV.SZ = 2 + val v = Bool() + val status = new BBTLBMStatus(xLen) +} + +// TLB Response +class BBTLBResp(val lgMaxSize: Int, val paddrBits: Int, val vaddrBits: Int) extends Bundle { + val miss = Bool() + val paddr = UInt(paddrBits.W) + val gpa = UInt(vaddrBits.W) + val gpa_is_pte = Bool() + val pf = new TLBExceptions + val gf = new TLBExceptions + val ae = new TLBExceptions + val ma = new TLBExceptions + val cacheable = Bool() + val must_alloc = Bool() + val prefetchable = Bool() + val size = UInt(log2Ceil(lgMaxSize + 1).W) + val cmd = UInt(5.W) // M_SZ = 5 +} + +// TLB Exception IO +class BBTLBExceptionIO extends Bundle { + val interrupt = Output(Bool()) + val flush_retry = Input(Bool()) + val flush_skip = Input(Bool()) + + def flush(dummy: Int = 0): Bool = flush_retry || flush_skip +} + +// Page Table Base Register +class BBTLBPTBR(val paddrBits: Int, val pgIdxBits: Int, val xLen: Int) extends Bundle { + val modeBits = if (xLen == 32) 1 else 4 + val maxASIdBits = if (xLen == 32) 9 else 16 + val mode = UInt(modeBits.W) + val asid = UInt(maxASIdBits.W) + val ppn = UInt((paddrBits - pgIdxBits).W) +} + +// PTW Request +class BBTLBPTWReq(val vaddrBits: Int, val pgIdxBits: Int) extends Bundle { + val vpnBits = vaddrBits - pgIdxBits + val addr = UInt(vpnBits.W) + val need_gpa = Bool() + val vstage1 = Bool() + val stage2 = Bool() +} + +// PTE (Page Table Entry) - Simplified +class BBTLBPTE(val paddrBits: Int, val pgIdxBits: Int) extends Bundle { + val ppnBits = paddrBits - pgIdxBits + val ppn = UInt(ppnBits.W) + val reserved_for_future = UInt(10.W) + val reserved_for_software = Bits(2.W) + val d = Bool() // dirty + val a = Bool() // access + val g = Bool() // global + val u = Bool() // user + val x = Bool() // executable + val w = Bool() // writable + val r = Bool() // readable + val v = Bool() // valid + + def sr(): Bool = v && r + def sw(): Bool = v && w && d + def sx(): Bool = v && x +} + +// PTW Response +class BBTLBPTWResp( + val vaddrBits: Int, + val paddrBits: Int, + val pgIdxBits: Int, + val pgLevels: Int) + extends Bundle { + val ae_ptw = Bool() + val ae_final = Bool() + val pf = Bool() + val gf = Bool() + val hr = Bool() + val hw = Bool() + val hx = Bool() + val pte = new BBTLBPTE(paddrBits, pgIdxBits) + val level = UInt(log2Ceil(pgLevels).W) + val fragmented_superpage = Bool() + val homogeneous = Bool() + val gpa = Valid(UInt(vaddrBits.W)) + val gpa_is_pte = Bool() +} + +// HStatus - Simplified hypervisor status +class BBTLBHStatus extends Bundle { + val vsxl = UInt(2.W) + val vtsr = Bool() + val vtw = Bool() + val vtvm = Bool() + val vgein = UInt(6.W) + val hu = Bool() +} + +// PMP - Simplified Physical Memory Protection +class BBTLBPMP(val paddrBits: Int) extends Bundle { + + val cfg = new Bundle { + val l = Bool() + val a = UInt(2.W) + val x = Bool() + val w = Bool() + val r = Bool() + } + + val addr = UInt((paddrBits - 2).W) // Assuming lgAlign = 2 +} + +// PTW IO +class BBTLBPTWIO(val b: GlobalConfig) extends Bundle { + val vaddrBits = b.core.vaddrBits + val paddrBits = b.core.paddrBits + val pgIdxBits = b.core.pgIdxBits + val xLen = b.core.xLen + val pgLevels = if (xLen == 32) 2 else 4 // Simplified: assume SV39 for 64-bit + val nPMPs = 16 // Fixed size, can be parameterized later + + val req = Decoupled(Valid(new BBTLBPTWReq(vaddrBits, pgIdxBits))) + val resp = Flipped(Valid(new BBTLBPTWResp(vaddrBits, paddrBits, pgIdxBits, pgLevels))) + val ptbr = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) + val hgatp = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) + val vsatp = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) + val status = Input(new BBTLBMStatus(xLen)) + val hstatus = Input(new BBTLBHStatus()) + val gstatus = Input(new BBTLBMStatus(xLen)) + val pmp = Input(Vec(nPMPs, new BBTLBPMP(paddrBits))) + // Note: customCSRs removed - not needed for our implementation +} + +// TLB Client IO (used in TLBCluster) +class BBTLBIO(val b: GlobalConfig) extends Bundle { + val lgMaxSize = log2Ceil(b.core.coreDataBytes) + val req = Flipped(Valid(new BBTLBReq(lgMaxSize, b.core.vaddrBits, b.core.xLen))) + val resp = Valid(new BBTLBResp(lgMaxSize, b.core.paddrBits, b.core.vaddrBits)) +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/README.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/README.md deleted file mode 100644 index 3791d836..00000000 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/README.md +++ /dev/null @@ -1,252 +0,0 @@ -# TLB Module (Translation Lookaside Buffer) - -## Overview - -The TLB module implements address translation caching from virtual to physical addresses, located at `framework/builtin/memdomain/tlb`. Based on Rocket-chip's TLB implementation, it provides Buckyball-specific TLB encapsulation and cluster management. - -## File Structure - -``` -tlb/ -├── BBTLB.scala - Buckyball TLB implementation -├── TLBCluster.scala - TLB cluster manager -├── spec-BBTLB.md - BBTLB specification -└── spec-BBTLBCluster.md - TLB cluster specification -``` - -## Core Components - -### BBTLB - Buckyball TLB - -BBTLB wraps Rocket-chip TLB with Buckyball-specific interface and exception handling: - -```scala -class BBTLB(entries: Int, maxSize: Int)(implicit edge: TLEdgeOut, p: Parameters) - extends CoreModule { - - val lgMaxSize = log2Ceil(maxSize) - val io = IO(new Bundle { - val req = Flipped(Valid(new BBTLBReq(lgMaxSize))) - val resp = new TLBResp - val ptw = new TLBPTWIO - val exp = new BBTLBExceptionIO - }) -} -``` - -**Request Interface**: -```scala -class BBTLBReq(val lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle { - val tlb_req = new TLBReq(lgMaxSize) // TLB request - val status = new MStatus // Processor status -} -``` - -**Exception Interface**: -```scala -class BBTLBExceptionIO extends Bundle { - val interrupt = Output(Bool()) // Interrupt output - val flush_retry = Input(Bool()) // Retry flush - val flush_skip = Input(Bool()) // Skip flush - - def flush(dummy: Int = 0): Bool = flush_retry || flush_skip -} -``` - -**Implementation**: Internally instantiates Rocket-chip TLB with single-set configuration: -```scala -val tlb = Module(new TLB(false, lgMaxSize, TLBConfig(nSets=1, nWays=entries))) -``` - -**Exception Detection**: -```scala -val exception = io.req.valid && Mux( - io.req.bits.tlb_req.cmd === M_XRD, - tlb.io.resp.pf.ld || tlb.io.resp.ae.ld, // Read exceptions - tlb.io.resp.pf.st || tlb.io.resp.ae.st // Write exceptions -) -``` - -### BBTLBCluster - TLB Cluster - -BBTLBCluster manages multiple TLB instances for concurrent client access: - -```scala -class BBTLBCluster(nClients: Int, entries: Int, maxSize: Int) - (implicit edge: TLEdgeOut, p: Parameters) extends CoreModule { - - val io = IO(new Bundle { - val clients = Flipped(Vec(nClients, new BBTLBIO)) - val ptw = Vec(nClients, new TLBPTWIO) - val exp = Vec(nClients, new BBTLBExceptionIO) - }) -} -``` - -**Client Interface**: -```scala -class BBTLBIO(implicit p: Parameters) extends CoreBundle { - val lgMaxSize = log2Ceil(coreDataBytes) - val req = Valid(new BBTLBReq(lgMaxSize)) // TLB request - val resp = Flipped(new TLBResp) // TLB response -} -``` - -**L0 TLB Cache**: Each client has an L0 TLB cache for recent translations: -```scala -val last_translated_valid = RegInit(false.B) -val last_translated_vpn = RegInit(0.U(vaddrBits.W)) -val last_translated_ppn = RegInit(0.U(paddrBits.W)) - -val l0_tlb_hit = last_translated_valid && - ((client.req.bits.tlb_req.vaddr >> pgIdxBits).asUInt === - (last_translated_vpn >> pgIdxBits).asUInt) -``` - -**Translation Flow**: -1. **L0 Cache Check**: First check L0 TLB cache for hit -2. **L1 TLB Query**: Query L1 TLB on L0 miss -3. **Page Table Walk**: PTW on TLB miss -4. **Cache Update**: Update L0 cache on successful translation - -```scala -when (tlbReqFire && !tlb.io.resp.miss) { - last_translated_valid := true.B - last_translated_vpn := tlbReq.tlb_req.vaddr - last_translated_ppn := tlb.io.resp.paddr -} -``` - -## Configuration - -**TLB Parameters**: -- `entries`: Number of TLB entries -- `maxSize`: Maximum transfer size -- `nClients`: Number of clients - -**Example**: -```scala -val tlbConfig = TLBConfig( - nSets = 1, // TLB sets - nWays = 32 // Ways per set -) -``` - -## Usage - -### Single TLB - -```scala -val bbtlb = Module(new BBTLB(entries = 32, maxSize = 64)) - -// Connect request -bbtlb.io.req.valid := tlbReqValid -bbtlb.io.req.bits.tlb_req := tlbRequest -bbtlb.io.req.bits.status := processorStatus - -// Get response -val tlbResp = bbtlb.io.resp -val physicalAddr = tlbResp.paddr -val tlbMiss = tlbResp.miss - -// Connect PTW -ptw <> bbtlb.io.ptw - -// Handle exceptions -when(bbtlb.io.exp.interrupt) { - // Handle TLB exception -} -``` - -### TLB Cluster - -```scala -val tlbCluster = Module(new BBTLBCluster( - nClients = 4, - entries = 32, - maxSize = 64 -)) - -// Connect clients -for (i <- 0 until nClients) { - tlbCluster.io.clients(i).req.valid := clientReqValid(i) - tlbCluster.io.clients(i).req.bits := clientReq(i) - clientResp(i) := tlbCluster.io.clients(i).resp -} - -// Connect PTW -for (i <- 0 until nClients) { - ptw(i) <> tlbCluster.io.ptw(i) -} -``` - -## Address Translation - -### Virtual Address Format - -``` -Virtual Address (64-bit): -[63:39] [38:30] [29:21] [20:12] [11:0] - VPN3 VPN2 VPN1 VPN0 Offset -``` - -### Physical Address Format - -``` -Physical Address: -[PPN][Offset] -``` - -### Translation Process - -1. **Address Parsing**: Parse VPN and offset from virtual address -2. **TLB Lookup**: Look up PPN for VPN in TLB -3. **Page Table Walk**: PTW on TLB miss -4. **Permission Check**: Check access permissions -5. **Address Composition**: Combine PPN and offset to form physical address - -## Exception Handling - -### Exception Types - -- **Page Fault**: Access to invalid page -- **Access Exception**: Insufficient permissions -- **TLB Miss**: Requires page table walk - -### Exception Handling Flow - -```scala -val exception = io.req.valid && Mux( - io.req.bits.tlb_req.cmd === M_XRD, - tlb.io.resp.pf.ld || tlb.io.resp.ae.ld, // Read exception - tlb.io.resp.pf.st || tlb.io.resp.ae.st // Write exception -) -``` - -### TLB Flush - -```scala -tlb.io.sfence.valid := io.exp.flush() -tlb.io.sfence.bits.rs1 := false.B -tlb.io.sfence.bits.rs2 := false.B -``` - -## Performance Optimization - -### L0 TLB Cache - -- Reduces L1 TLB access latency -- Improves address translation throughput -- Lowers power consumption - -### Parallel Processing - -- Multiple clients access in parallel -- Independent page table walkers -- Separate exception handling - -## Related Modules - -- [Memory Domain Overview](../README.md) -- [DMA Engines](../dma/README.md) -- [Memory Controller](../mem/README.md) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala new file mode 100644 index 00000000..224d56d4 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala @@ -0,0 +1,160 @@ +package framework.memdomain.frontend.outside_channel.tlb + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +/** TLB implementation with fully-associative structure and LRU replacement */ +@instantiable +class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { + val entries = b.memDomain.tlb_size + val vaddrBits = b.core.vaddrBits + val paddrBits = b.core.paddrBits + val pgIdxBits = b.core.pgIdxBits + val vpnBits = vaddrBits - pgIdxBits + val ppnBits = paddrBits - pgIdxBits + + @public + val io = IO(new Bundle { + val req = Flipped(Decoupled(new BBTLBReq(lgMaxSize, vaddrBits, b.core.xLen))) + val resp = Output(new BBTLBResp(lgMaxSize, paddrBits, vaddrBits)) + val ptw = new BBTLBPTWIO(b) + val sfence = Flipped(Valid(Bool())) // Simplified flush signal + val kill = Input(Bool()) + }) + + // TLB entries storage + val tlbEntries = Reg(Vec(entries, new TLBEntry(vaddrBits, pgIdxBits, paddrBits))) + val lru = Reg(Vec(entries, UInt(log2Ceil(entries).W))) // Simple LRU counter + + // State machine + val s_ready :: s_request :: s_wait :: Nil = Enum(3) + val state = RegInit(s_ready) + val refill_vpn = Reg(UInt(vpnBits.W)) + val refill_idx = Reg(UInt(log2Ceil(entries).W)) + + // Initialize LRU + when(reset.asBool) { + lru.foreach(_ := 0.U) + tlbEntries.foreach(_.invalidate()) + } + + val vpn = io.req.bits.vaddr(vaddrBits - 1, pgIdxBits) + val pgIdx = io.req.bits.vaddr(pgIdxBits - 1, 0) + + // TLB lookup + val hits = tlbEntries.map(_.hit(vpn)) + val hitVec = VecInit(hits) + val hitIdx = PriorityEncoder(hits) + val tlbHit = hits.reduce(_ || _) + + // Update LRU on hit + when(io.req.fire && tlbHit) { + lru(hitIdx) := (entries - 1).U + for (i <- 0 until entries) { + when(i.U =/= hitIdx && lru(i.U) > lru(hitIdx)) { + lru(i.U) := lru(i.U) - 1.U + } + } + } + + // Find LRU entry for replacement + val lruIdx = PriorityEncoder(lru.map(_ === 0.U)) + + // VM enable check (simplified: check if VM is enabled via status) + val vm_enabled = true.B // Simplified: assume VM is always enabled for now + + val tlbMiss = vm_enabled && !io.req.bits.passthrough && !tlbHit + + // State machine + io.req.ready := state === s_ready + + when(io.req.fire && tlbMiss && state === s_ready) { + state := s_request + refill_vpn := vpn + refill_idx := lruIdx + } + + when(state === s_request) { + when(io.kill) { + state := s_ready + }.elsewhen(io.ptw.req.ready) { + state := s_wait + } + } + + when(state === s_wait && io.ptw.resp.valid) { + state := s_ready + // Refill TLB entry + val pte = io.ptw.resp.bits.pte + val entryData = Wire(new TLBEntryData(paddrBits, pgIdxBits)) + entryData.ppn := pte.ppn(ppnBits - 1, 0) + entryData.u := pte.u + entryData.g := pte.g + entryData.sr := pte.sr() + entryData.sw := pte.sw() + entryData.sx := pte.sx() + entryData.cacheable := true.B // Simplified + entryData.pf := io.ptw.resp.bits.pf + entryData.ae_final := io.ptw.resp.bits.ae_final + + tlbEntries(refill_idx).insert(refill_vpn, entryData) + // Update LRU + lru(refill_idx) := (entries - 1).U + for (i <- 0 until entries) { + when(i.U =/= refill_idx && lru(i.U) > lru(refill_idx)) { + lru(i.U) := lru(i.U) - 1.U + } + } + } + + // PTW request + io.ptw.req.valid := state === s_request + io.ptw.req.bits.valid := !io.kill + io.ptw.req.bits.bits.addr := refill_vpn + io.ptw.req.bits.bits.vstage1 := false.B + io.ptw.req.bits.bits.stage2 := false.B + io.ptw.req.bits.bits.need_gpa := false.B + + // TLB flush on sfence + when(io.sfence.valid) { + tlbEntries.foreach(_.invalidate()) + state := s_ready + } + + // Response generation + val hitEntry = Mux( + tlbHit, + tlbEntries(hitIdx).data, + WireDefault(new TLBEntryData(paddrBits, pgIdxBits), 0.U.asTypeOf(new TLBEntryData(paddrBits, pgIdxBits))) + ) + + val paddr = Mux( + io.req.bits.passthrough || !vm_enabled, + io.req.bits.vaddr, + Cat(hitEntry.ppn, pgIdx) + ) + + io.resp.miss := tlbMiss || (state === s_wait) + io.resp.paddr := paddr(paddrBits - 1, 0) + io.resp.gpa := 0.U + io.resp.gpa_is_pte := false.B + io.resp.pf.ld := hitEntry.pf + io.resp.pf.st := hitEntry.pf + io.resp.pf.inst := hitEntry.pf + io.resp.gf.ld := false.B + io.resp.gf.st := false.B + io.resp.gf.inst := false.B + io.resp.ae.ld := hitEntry.ae_final + io.resp.ae.st := hitEntry.ae_final + io.resp.ae.inst := hitEntry.ae_final + io.resp.ma.ld := false.B + io.resp.ma.st := false.B + io.resp.ma.inst := false.B + io.resp.cacheable := hitEntry.cacheable + io.resp.must_alloc := false.B + io.resp.prefetchable := hitEntry.cacheable + io.resp.size := io.req.bits.size + io.resp.cmd := io.req.bits.cmd +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala index 18c60355..7d3a3ed2 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala @@ -2,52 +2,76 @@ package framework.memdomain.frontend.outside_channel.tlb import chisel3._ import chisel3.util._ - -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile.{CoreBundle, CoreModule} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import freechips.rocketchip.tilelink.TLEdgeOut +import framework.top.GlobalConfig -class BBTLBIO(implicit p: Parameters) extends CoreBundle { - val lgMaxSize = log2Ceil(coreDataBytes) - val req = Valid(new BBTLBReq(lgMaxSize)) - val resp = Flipped(new TLBResp) -} - -class BBTLBCluster( - nClients: Int, - entries: Int, - maxSize: Int, - use_shared_tlb: Boolean = true -)( - implicit val edge: TLEdgeOut, - p: Parameters) - extends CoreModule { +@instantiable +class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Module { - val num_tlbs = if (use_shared_tlb) 1 else nClients - val lgMaxSize = log2Ceil(coreDataBytes) + val nClients = 2 + val entries = b.memDomain.tlb_size + val maxSize = b.core.coreDataBytes + val lgMaxSize = log2Ceil(b.core.coreDataBytes) + val vaddrBits = b.core.vaddrBits + val paddrBits = b.core.paddrBits + val pgIdxBits = b.core.pgIdxBits + @public val io = IO(new Bundle { - val clients = Flipped(Vec(nClients, new BBTLBIO)) - val ptw = Vec(num_tlbs, new TLBPTWIO) - val exp = Vec(num_tlbs, new BBTLBExceptionIO) + val clients = Flipped(Vec(nClients, new BBTLBIO(b))) + val ptw = Vec(1, new BBTLBPTWIO(b)) // Shared TLB has only 1 PTW port + val exp = Vec(1, new BBTLBExceptionIO) // Shared TLB has only 1 exception interface }) - val tlbs = Seq.fill(num_tlbs)(Module(new BBTLB(entries, maxSize))) + val tlb = Instantiate(new TLB(b, lgMaxSize)) + + // Exception handling + val interrupt = RegInit(false.B) + io.exp(0).interrupt := interrupt + + // Connect PTW + io.ptw(0) <> tlb.io.ptw + + val tlbArb = Module(new RRArbiter(new BBTLBReq(lgMaxSize, vaddrBits, b.core.xLen), nClients)) + val tlbArbOut = tlbArb.io.out + val tlb_io = tlb.io + + tlb_io.req.valid := tlbArbOut.valid + tlb_io.req.bits := tlbArbOut.bits + tlbArbOut.ready := tlb_io.req.ready + + // Connect status to PTW + tlb_io.ptw.status := tlbArbOut.bits.status + tlb_io.kill := false.B - io.ptw <> VecInit(tlbs.map(_.io.ptw)) - io.exp <> VecInit(tlbs.map(_.io.exp)) + // Handle sfence from exception IO + tlb_io.sfence.valid := io.exp(0).flush() + tlb_io.sfence.bits := false.B - val tlbArbOpt = if (use_shared_tlb) Some(Module(new RRArbiter(new BBTLBReq(lgMaxSize), nClients))) else None + // Exception detection + val isRead = tlbArbOut.bits.cmd(0) === 0.U - if (use_shared_tlb) { - val tlbArb = tlbArbOpt.get - val tlb = tlbs.head - tlb.io.req.valid := tlbArb.io.out.valid - tlb.io.req.bits := tlbArb.io.out.bits - tlbArb.io.out.ready := true.B + val exception = tlbArbOut.valid && !tlb_io.resp.miss && Mux( + isRead, + tlb_io.resp.pf.ld || tlb_io.resp.ae.ld || tlb_io.resp.gf.ld, + tlb_io.resp.pf.st || tlb_io.resp.ae.st || tlb_io.resp.gf.st + ) + + when(exception) { + interrupt := true.B + } + + when(interrupt && io.exp(0).flush_skip) { + interrupt := false.B } + when(interrupt && io.exp(0).flush_retry) { + interrupt := false.B + } + + assert(!io.exp(0).flush_retry || !io.exp(0).flush_skip, "TLB: flushing with both retry and skip at same time") + io.clients.zipWithIndex.foreach { case (client, i) => val last_translated_valid = RegInit(false.B) @@ -55,35 +79,33 @@ class BBTLBCluster( val last_translated_ppn = RegInit(0.U(paddrBits.W)) val l0_tlb_hit = - last_translated_valid && ((client.req.bits.tlb_req.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt) - val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.tlb_req.vaddr(pgIdxBits - 1, 0)) - - val tlb = if (use_shared_tlb) tlbs.head else tlbs(i) - val tlbReq = if (use_shared_tlb) tlbArbOpt.get.io.in(i).bits else tlb.io.req.bits - val tlbReqValid = if (use_shared_tlb) tlbArbOpt.get.io.in(i).valid else tlb.io.req.valid - val tlbReqFire = if (use_shared_tlb) tlbArbOpt.get.io.in(i).fire else tlb.io.req.fire + last_translated_valid && ((client.req.bits.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt) + val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.vaddr(pgIdxBits - 1, 0)) - val l0_tlb_paddr_reg = RegEnable(client.req.bits.tlb_req.vaddr, client.req.valid) + tlbArb.io.in(i).valid := client.req.valid && !l0_tlb_hit + tlbArb.io.in(i).bits := client.req.bits - tlbReqValid := RegNext(client.req.valid && !l0_tlb_hit) - tlbReq := RegNext(client.req.bits) + val tlbReq = tlbArb.io.in(i).bits + val tlbReqFire = tlbArb.io.in(i).fire - when(tlbReqFire && !tlb.io.resp.miss) { + when(tlbReqFire && !tlb_io.resp.miss) { last_translated_valid := true.B - last_translated_vpn := tlbReq.tlb_req.vaddr - last_translated_ppn := tlb.io.resp.paddr + last_translated_vpn := tlbReq.vaddr + last_translated_ppn := tlb_io.resp.paddr } - when(tlb.io.exp.flush()) { + when(io.exp(0).flush()) { last_translated_valid := false.B } when(tlbReqFire) { - client.resp := tlb.io.resp + client.resp.valid := !tlb_io.resp.miss + client.resp.bits := tlb_io.resp }.otherwise { - client.resp := DontCare - client.resp.paddr := RegNext(l0_tlb_paddr) - client.resp.miss := !RegNext(l0_tlb_hit) + client.resp.valid := RegNext(!l0_tlb_hit) + client.resp.bits := DontCare + client.resp.bits.paddr := RegNext(l0_tlb_paddr) + client.resp.bits.miss := !RegNext(l0_tlb_hit) } } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala new file mode 100644 index 00000000..7dccc8d3 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala @@ -0,0 +1,40 @@ +package framework.memdomain.frontend.outside_channel.tlb + +import chisel3._ + +/** TLB entry data containing translation and permission information */ +class TLBEntryData(val paddrBits: Int, val pgIdxBits: Int) extends Bundle { + val ppnBits = paddrBits - pgIdxBits + + val ppn = UInt(ppnBits.W) + val u = Bool() // user page + val g = Bool() // global page + val sr = Bool() // supervisor read + val sw = Bool() // supervisor write + val sx = Bool() // supervisor execute + val cacheable = Bool() + + // Page fault and access exception flags + val pf = Bool() + val ae_final = Bool() +} + +/** TLB entry containing VPN tag and entry data */ +class TLBEntry(val vaddrBits: Int, val pgIdxBits: Int, val paddrBits: Int) extends Bundle { + val vpnBits = vaddrBits - pgIdxBits + + val tag_vpn = UInt(vpnBits.W) + val valid = Bool() + val data = new TLBEntryData(paddrBits, pgIdxBits) + + def hit(vpn: UInt): Bool = valid && (tag_vpn === vpn) + + def insert(vpn: UInt, entryData: TLBEntryData): Unit = { + tag_vpn := vpn + valid := true.B + data := entryData + } + + def invalidate(): Unit = + valid := false.B +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLB.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLB.md deleted file mode 100644 index a0037906..00000000 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLB.md +++ /dev/null @@ -1,29 +0,0 @@ -# BBTLB (Translation Lookaside Buffer) Specification - -## Overview - -BBTLB is a decoupled translation lookaside buffer implementation that accelerates virtual to physical address translation. Inheriting from CoreModule, it provides a TLB interface with exception handling mechanism, supporting page table walk (PTW) and various memory access commands. The module uses parameterized design to support configurable entry count and maximum page size, while integrating complete exception handling flow. - -## Interface Design - -The module's IO interface contains four main components: -- Request interface (req): Receives TLB request and status information -- Response interface (resp): TLB returns translation result, page fault flags, and access exception information -- Page table walker interface (ptw): PTW interface communicates with memory management unit, handling page table lookup on TLB misses -- Exception handling interface (exp): Exception handling interface manages interrupt signal generation and clearing, supporting both retry and skip flush operation modes - -## Internal Implementation - -Module internally instantiates a standard TLB module, configured as single-set associative structure (nSets=1, nWays=entries), with instruction TLB feature disabled. Internal TLB's request signal directly connects to input request's tlb_req field, while kill signal is hardwired to false, indicating no support for request cancellation. Page table walker interface communicates with internal TLB through direct connection, while passing request's status information to PTW module to ensure correct permission checking. - -## Exception Handling Flow - -Exception handling uses interrupt-based mechanism, tracking exception state through RegInit-initialized interrupt register. When valid request with page fault or access exception is detected, module performs corresponding exception checks based on memory command type: for read operations (M_XRD) checks load page fault and access exception, for write operations checks store page fault and access exception. Once exception condition is detected, interrupt signal is set high and maintained until flush operation received and flush signal successfully fires, then cleared. - -## SFENCE Operation Support - -Module implements complete SFENCE (Supervisor Fence) operation support for TLB flush and synchronization. SFENCE operation trigger condition is any form of flush signal (flush_retry or flush_skip). During SFENCE execution, all related address and ASID fields are set to DontCare, rs1 and rs2 flags are cleared, hv and hg flags are also disabled, indicating this implementation adopts simplified global flush strategy rather than selective flush. Module uses assertion to ensure not receiving retry and skip flush signals simultaneously, guaranteeing operation determinism. - -## Parameterized Configuration - -Module supports flexible configuration through constructor parameters: entries parameter controls TLB entry count, maxSize parameter defines maximum supported page size. lgMaxSize calculated through log2Ceil, used to determine address width and internal logic precision. This parameterized design enables the module to adapt to different system requirements and performance needs while maintaining interface consistency and implementation reusability. diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLBCluster.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLBCluster.md deleted file mode 100644 index 71e356d8..00000000 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/spec-BBTLBCluster.md +++ /dev/null @@ -1,88 +0,0 @@ -# BBTLBCluster (Translation Lookaside Buffer Cluster) Specification - -## Overview - -BBTLBCluster is a multi-client TLB cluster implementation that supports concurrent virtual address translation for multiple clients. Inheriting from CoreModule, it instantiates multiple BBTLB modules to provide independent TLB services for each client, while implementing an L0-level fast translation cache mechanism to improve performance. The module supports parameterized configuration of client count, TLB entries, and maximum page size. - -## Interface Design - -BBTLBCluster's IO interface contains three main components: -- Client interface (clients): Provides Vec(nClients, BBTLBIO), each client has independent request and response channels -- Page table walker interface (ptw): Vec(nClients, TLBPTWIO), provides independent PTW connection for each client -- Exception handling interface (exp): Vec(nClients, BBTLBExceptionIO), manages exceptions and flush operations for each client - -BBTLBIO interface definition: -- req: Valid(BBTLBReq), contains TLB request and related status information -- resp: Flipped(TLBResp), returns address translation result, miss flag, and exception information - -## Internal Architecture - -### TLB Instantiation -The module instantiates an independent BBTLB module for each client through `Seq.fill(nClients)(Module(new BBTLB(entries, maxSize)))` to create a TLB array. Each TLB instance's PTW and exception interfaces are directly connected to corresponding output ports. - -### L0 Fast Cache Mechanism -To improve translation performance for frequently accessed addresses, each client implements a single-entry L0-level translation cache: -- `last_translated_valid`: Indicates cache entry validity -- `last_translated_vpn`: Cached virtual page number -- `last_translated_ppn`: Cached physical page number - -L0 cache hit condition: cache is valid and current request's virtual page number matches cached virtual page number. - -## Address Translation Flow - -### L0 Cache Lookup -Each client's address translation first looks up in the L0 cache: -1. Check `l0_tlb_hit` condition: cache valid and page number match -2. If hit, directly calculate physical address: `Cat(last_translated_ppn >> pgIdxBits, vaddr(pgIdxBits-1,0))` -3. If miss, forward request to corresponding BBTLB module - -### TLB Lookup Flow -When L0 cache misses: -1. Use `RegNext` to delay one cycle and forward client request to TLB -2. TLB valid signal set to: `RegNext(client.req.valid && !l0_tlb_hit)` -3. TLB request data set to: `RegNext(client.req.bits)` - -### Cache Update Mechanism -When TLB request completes without miss, update L0 cache: -```scala -when (tlbReqFire && !tlb.io.resp.miss) { - last_translated_valid := true.B - last_translated_vpn := tlbReq.tlb_req.vaddr - last_translated_ppn := tlb.io.resp.paddr -} -``` - -## Response Path Design - -Module implements dual-path response mechanism: -1. **TLB Path**: When TLB request fires, directly return TLB response result -2. **L0 Cache Path**: When using L0 cache, return cached calculated physical address, miss flag set to `!RegNext(l0_tlb_hit)` - -Register `l0_tlb_paddr_reg` saves client request's virtual address for L0 cache path response. - -## Exception and Flush Handling - -Module maintains L0 cache coherency by monitoring each TLB's flush signal: -```scala -when (tlb.io.exp.flush()) { - last_translated_valid := false.B -} -``` - -When any flush operation occurs, L0 cache is immediately invalidated, ensuring address translation correctness. - -## Parameterized Configuration - -BBTLBCluster supports three main parameters: -- `nClients`: Number of supported clients, determines degree of concurrent TLB access -- `entries`: Number of entries per TLB instance -- `maxSize`: Maximum supported page size - -`lgMaxSize` calculated through `log2Ceil(coreDataBytes)`, used to determine address width and related logic precision. - -## Performance Optimization Features - -1. **L0 Fast Cache**: Provides single-entry fast access for each client, reducing hot address access latency -2. **Parallel Processing**: Multiple clients can perform address translation simultaneously, improving system throughput -3. **Independent PTW**: Each client has independent page table walker interface, avoiding PTW resource contention -4. **Pipeline Design**: Uses register delays to implement pipeline operations, improving clock frequency diff --git a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala b/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala index 078363eb..d4bdc683 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala @@ -3,11 +3,9 @@ package framework.memdomain.midend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters -import examples.BuckyballConfigs.CustomBuckyballConfig +import framework.top.GlobalConfig import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import framework.memdomain.MemDomainParam import framework.memdomain.backend.MemRequestIO /** @@ -17,36 +15,19 @@ import framework.memdomain.backend.MemRequestIO * Basic direct connection: routes requests from frontend to backend channels */ @instantiable -class MemScheduler(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemScheduler(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Input from frontend (MemController) val frontend = new Bundle { - - val bankRead = Vec( - parameter.bankNum, - Flipped(new BankRead(parameter.bankEntries, parameter.bankWidth, parameter.rob_entries, parameter.bankNum)) - ) - - val bankWrite = Vec( - parameter.bankNum, - Flipped(new BankWrite( - parameter.bankEntries, - parameter.bankWidth, - parameter.bankMaskLen, - parameter.rob_entries, - parameter.bankNum - )) - ) - + val bankRead = Vec(b.memDomain.bankNum, Flipped(new BankRead(b))) + val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) } // Output to backend (MemManager) - val mem_req = Vec(parameter.bankChannel, new MemRequestIO(parameter)) + val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) }) // ----------------------------------------------------------------------------- @@ -55,9 +36,9 @@ class MemScheduler(val parameter: MemDomainParam)(implicit p: Parameters) // Simple mapping: each channel handles requests for a specific bank // Channel ch handles bank (ch % bankNum) - for (ch <- 0 until parameter.bankChannel) { - val targetBank = (ch % parameter.bankNum).U - val bankIdx = ch % parameter.bankNum + for (ch <- 0 until b.memDomain.bankChannel) { + val targetBank = (ch % b.memDomain.bankNum).U + val bankIdx = ch % b.memDomain.bankNum // Default: no request io.mem_req(ch).write.req.valid := false.B diff --git a/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala b/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala index 0e6ae32d..1ecc4087 100644 --- a/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala +++ b/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala @@ -2,23 +2,19 @@ package framework.memdomain.utils.pmc import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.MemDomainParam +import framework.top.GlobalConfig import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} @instantiable -class MemCyclePMC(val parameter: MemDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[MemDomainParam] { +class MemCyclePMC(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val ldReq_i = Input(Valid(new MemRsIssue(parameter))) - val stReq_i = Input(Valid(new MemRsIssue(parameter))) - val ldResp_o = Input(Valid(new MemRsComplete(parameter))) - val stResp_o = Input(Valid(new MemRsComplete(parameter))) + val ldReq_i = Input(Valid(new MemRsIssue(b))) + val stReq_i = Input(Valid(new MemRsIssue(b))) + val ldResp_o = Input(Valid(new MemRsComplete(b))) + val stResp_o = Input(Valid(new MemRsComplete(b))) val ldTotalCycles = Output(UInt(64.W)) val stTotalCycles = Output(UInt(64.W)) }) @@ -26,7 +22,7 @@ class MemCyclePMC(val parameter: MemDomainParam)(implicit p: Parameters) val cycleCounter = RegInit(0.U(64.W)) cycleCounter := cycleCounter + 1.U - val startTime = Reg(Vec(parameter.rob_entries, UInt(64.W))) + val startTime = Reg(Vec(b.frontend.rob_entries, UInt(64.W))) val ldTotalCycles = RegInit(0.U(64.W)) val stTotalCycles = RegInit(0.U(64.W)) diff --git a/arch/src/main/scala/framework/top/GlobalConfig.scala b/arch/src/main/scala/framework/top/GlobalConfig.scala new file mode 100644 index 00000000..c2076461 --- /dev/null +++ b/arch/src/main/scala/framework/top/GlobalConfig.scala @@ -0,0 +1,38 @@ +package framework.top + +import upickle.default.{macroRW, ReadWriter} +import chisel3.experimental.SerializableModuleParameter +import framework.memdomain.configs.MemDomainParam +import framework.frontend.configs.FrontendParam +import framework.gpdomain.configs.GpDomainParam +import framework.balldomain.configs.BallDomainParam +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.relu.configs.ReluBallParam +import framework.core.configs.CoreParam + +case class GlobalConfig( + memDomain: MemDomainParam, + frontend: FrontendParam, + gpDomain: GpDomainParam, + ballDomain: BallDomainParam, + vectorBall: VectorBallParam, + reluBall: ReluBallParam, + core: CoreParam) + extends SerializableModuleParameter + +object GlobalConfig { + implicit val rw: ReadWriter[GlobalConfig] = macroRW[GlobalConfig] + + def apply(): GlobalConfig = { + GlobalConfig( + memDomain = MemDomainParam(), + frontend = FrontendParam(), + gpDomain = GpDomainParam(), + ballDomain = BallDomainParam(), + vectorBall = VectorBallParam(), + reluBall = ReluBallParam(), + core = CoreParam() + ) + } + +} diff --git a/arch/src/main/scala/framework/builtin/util/Util.scala b/arch/src/main/scala/framework/utils/Util.scala similarity index 99% rename from arch/src/main/scala/framework/builtin/util/Util.scala rename to arch/src/main/scala/framework/utils/Util.scala index a13ad6f7..77914c24 100644 --- a/arch/src/main/scala/framework/builtin/util/Util.scala +++ b/arch/src/main/scala/framework/utils/Util.scala @@ -1,4 +1,4 @@ -package framework.builtin.util +package framework.utils import chisel3._ import chisel3.util._ diff --git a/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala b/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala deleted file mode 100644 index 0d794aad..00000000 --- a/arch/src/main/scala/prototype/abft/ABFTSystolicArray.scala +++ /dev/null @@ -1,336 +0,0 @@ -package prototype.abft - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status -import prototype.abft.configs.ABFTConfig - -/** - * ABFTSystolicArray - Simple systolic array with ABFT (Algorithm-Based Fault Tolerance) - * - * ABFT mechanism: - * - Matrix A has an extra checksum row (sum of each column) - * - Matrix B has an extra checksum column (sum of each row) - * - Result matrix C will have checksum row and column - * - Verify checksums match to detect errors - * - * Simple implementation: process InputNum x InputNum tiles - */ -@instantiable -class ABFTSystolicArray(val parameter: ABFTConfig)(implicit p: Parameters) - extends Module - with SerializableModule[ABFTConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val accWidth = 32 - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // Command interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) - - // Unified bank read/write interface - val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) - val bankWrite = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - - // Unified bank write interface for accumulator writes (accumulate mode) - val bankWriteAcc = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, accWidth, ballParam.bankMaskLen))) - - // Status output - val status = new Status - }) - - // State machine - val idle :: sLoadA :: sLoadB :: sCompute :: sWrite :: sCheck :: complete :: Nil = Enum(7) - val state = RegInit(idle) - - // Registers for matrix A (InputNum x InputNum) - val matrixA = RegInit( - VecInit(Seq.fill(InputNum)( - VecInit(Seq.fill(InputNum)(0.S(inputWidth.W))) - )) - ) - - // Registers for matrix B (InputNum x InputNum) - val matrixB = RegInit( - VecInit(Seq.fill(InputNum)( - VecInit(Seq.fill(InputNum)(0.S(inputWidth.W))) - )) - ) - - // Result matrix C (InputNum x InputNum) - val matrixC = RegInit( - VecInit(Seq.fill(InputNum)( - VecInit(Seq.fill(InputNum)(0.S(32.W))) - )) - ) - - // Checksum registers - val checksumA_row = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) - val checksumB_col = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) - val checksumC_row = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) - val checksumC_col = RegInit(VecInit(Seq.fill(InputNum)(0.S(32.W)))) - - // Counters - val rowCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val colCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val op1_addr_reg = RegInit(0.U(10.W)) - val op1_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val op2_addr_reg = RegInit(0.U(10.W)) - val op2_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val wr_addr_reg = RegInit(0.U(10.W)) - val wr_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - val cycle_reg = RegInit(0.U(6.W)) - val iterCnt = RegInit(0.U(32.W)) - - // Error detection flag - val errorDetected = RegInit(false.B) - - // Write data register - val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) - - // Default SRAM assignments - for (i <- 0 until ballParam.numBanks) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := false.B - - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // Default accumulator assignments - for (i <- 0 until ballParam.numBanks) { - io.bankWriteAcc(i).req.valid := false.B - io.bankWriteAcc(i).req.bits.addr := 0.U - io.bankWriteAcc(i).req.bits.data := 0.U - io.bankWriteAcc(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // Command interface defaults - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg - - // State machine - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - state := sLoadA - readCounter := 0.U - rowCounter := 0.U - colCounter := 0.U - writeCounter := 0.U - errorDetected := false.B - - robid_reg := io.cmdReq.bits.rob_id - op1_addr_reg := 0.U // New ISA: all operations start from row 0 - op1_bank_reg := io.cmdReq.bits.cmd.op1_bank - op2_addr_reg := 0.U // New ISA: all operations start from row 0 - op2_bank_reg := io.cmdReq.bits.cmd.op2_bank - wr_addr_reg := 0.U // New ISA: all operations start from row 0 - wr_bank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U - } - } - - is(sLoadA) { - // Load matrix A row by row - when(readCounter < InputNum.U) { - io.bankRead(op1_bank_reg).req.valid := true.B - io.bankRead(op1_bank_reg).req.bits.addr := op1_addr_reg + readCounter - readCounter := readCounter + 1.U - } - - io.bankRead(op1_bank_reg).resp.ready := true.B - when(io.bankRead(op1_bank_reg).resp.fire) { - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - val raw = io.bankRead(op1_bank_reg).resp.bits.data(hi, lo) - matrixA(rowCounter)(col) := raw.asSInt - } - rowCounter := rowCounter + 1.U - } - - when(rowCounter === InputNum.U) { - state := sLoadB - readCounter := 0.U - rowCounter := 0.U - // Compute checksum for matrix A (sum of each column) - for (col <- 0 until InputNum) { - checksumA_row(col) := (0 until InputNum).map(i => matrixA(i)(col)).reduce(_ + _) - } - } - } - - is(sLoadB) { - // Load matrix B row by row (same as matrix A) - when(readCounter < InputNum.U) { - io.bankRead(op2_bank_reg).req.valid := true.B - io.bankRead(op2_bank_reg).req.bits.addr := op2_addr_reg + readCounter - readCounter := readCounter + 1.U - } - - io.bankRead(op2_bank_reg).resp.ready := true.B - when(io.bankRead(op2_bank_reg).resp.fire) { - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - val raw = io.bankRead(op2_bank_reg).resp.bits.data(hi, lo) - matrixB(rowCounter)(col) := raw.asSInt - } - rowCounter := rowCounter + 1.U - } - - when(rowCounter === InputNum.U) { - state := sCompute - rowCounter := 0.U - colCounter := 0.U - // Compute checksum for matrix B (sum of each row) - for (row <- 0 until InputNum) { - checksumB_col(row) := (0 until InputNum).map(j => matrixB(row)(j)).reduce(_ + _) - } - } - } - - is(sCompute) { - // Simple systolic array computation: C[i][j] = sum(A[i][k] * B[k][j]) - // Compute all elements in one cycle (simple implementation) - for (i <- 0 until InputNum) { - for (j <- 0 until InputNum) { - val sum = (0 until InputNum).map(k => matrixA(i)(k) * matrixB(k)(j)).reduce((a: SInt, b: SInt) => a + b) - matrixC(i)(j) := sum - } - } - - // Compute checksums for result matrix C - for (col <- 0 until InputNum) { - checksumC_row(col) := (0 until InputNum).map(i => matrixC(i)(col)).reduce((a: SInt, b: SInt) => a + b) - } - for (row <- 0 until InputNum) { - checksumC_col(row) := (0 until InputNum).map(j => matrixC(row)(j)).reduce((a: SInt, b: SInt) => a + b) - } - - state := sCheck - } - - is(sCheck) { - // ABFT verification: check if checksums match - // For C = A * B, checksum of row i in C should equal sum(A[i][k] * checksumB_col[k]) - // For C = A * B, checksum of col j in C should equal sum(checksumA_row[k] * B[k][j]) - // Simple check: verify first row and first column checksums - val expectedRowChecksum = - (0 until InputNum).map(k => matrixA(0)(k) * checksumB_col(k)).reduce((a: SInt, b: SInt) => a + b) - - val expectedColChecksum = - (0 until InputNum).map(k => checksumA_row(k) * matrixB(k)(0)).reduce((a: SInt, b: SInt) => a + b) - - val rowMatch = checksumC_row(0) === expectedRowChecksum - val colMatch = checksumC_col(0) === expectedColChecksum - - errorDetected := !rowMatch || !colMatch - state := sWrite - writeCounter := 0.U - // Prepare first write data (clamp 32-bit result to 8-bit) - writeDataReg := Cat((0 until InputNum).reverse.map { j => - val clamped = - Mux(matrixC(0)(j) > 127.S, 127.U, Mux(matrixC(0)(j) < -128.S, -128.S.asUInt, matrixC(0)(j)(inputWidth - 1, 0))) - clamped - }) - for (i <- 0 until parameter.bankMaskLen) { - writeMaskReg(i) := 1.U(1.W) - } - } - - is(sWrite) { - // Write results back to scratchpad - io.bankWrite(wr_bank_reg).req.valid := writeCounter < InputNum.U - io.bankWrite(wr_bank_reg).req.bits.addr := wr_addr_reg + writeCounter - io.bankWrite(wr_bank_reg).req.bits.data := writeDataReg - io.bankWrite(wr_bank_reg).req.bits.mask := writeMaskReg - - when(io.bankWrite(wr_bank_reg).req.fire) { - when(writeCounter === (InputNum - 1).U) { - state := complete - }.otherwise { - writeCounter := writeCounter + 1.U - // Prepare next row's write data (clamp 32-bit result to 8-bit) - val nextRow = writeCounter + 1.U - writeDataReg := Cat((0 until InputNum).reverse.map { j => - val idx = nextRow - val clamped = Mux( - matrixC(idx)(j) > 127.S, - 127.U, - Mux(matrixC(idx)(j) < -128.S, -128.S.asUInt, matrixC(idx)(j)(inputWidth - 1, 0)) - ) - clamped - }) - } - } - } - - is(complete) { - when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } - } - state := idle - } - } - - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sLoadA) || (state === sLoadB) - io.status.running := (state === sCompute) || (state === sCheck) || (state === sWrite) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt - - // Reset handling - when(reset.asBool) { - for (i <- 0 until InputNum) { - for (j <- 0 until InputNum) { - matrixA(i)(j) := 0.S - matrixB(i)(j) := 0.S - matrixC(i)(j) := 0.S - } - checksumA_row(i) := 0.S - checksumB_col(i) := 0.S - checksumC_row(i) := 0.S - checksumC_col(i) := 0.S - } - writeDataReg := 0.U - for (i <- 0 until parameter.bankMaskLen) { - writeMaskReg(i) := 0.U - } - errorDetected := false.B - } -} diff --git a/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala b/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala deleted file mode 100644 index d0e453b2..00000000 --- a/arch/src/main/scala/prototype/abft/ABFTSystolicArrayBall.scala +++ /dev/null @@ -1,55 +0,0 @@ -package prototype.abft - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.abft.ABFTSystolicArray -import prototype.abft.configs.ABFTConfig - -/** - * ABFTSystolicArrayBall - A systolic array Ball with ABFT support - * Behavior: Read matrices A and B from Scratchpad, compute C = A * B with ABFT checks, - * then write back to Scratchpad. - */ -@instantiable -class ABFTSystolicArrayBall(config: ABFTConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - // Satisfy BallRegist requirements - def Blink: Blink = io - - // Instantiate ABFT systolic array computation unit - private val abftUnit: Instance[ABFTSystolicArray] = Instantiate(new ABFTSystolicArray(config)) - - // Connect command interface - abftUnit.io.cmdReq <> io.cmdReq - abftUnit.io.cmdResp <> io.cmdResp - - // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { - abftUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - abftUnit.io.bankWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // ABFTSystolicArrayBall uses overwrite mode for scratchpad - - // Accumulator write (for partial sums) - use accumulate mode - abftUnit.io.bankWriteAcc(i) <> io.bankWrite(i).io - // Note: bankWriteAcc uses accumulate mode, but we connect to the same bankWrite interface - // The wmode should be set to true for accumulator writes - } - - // Pass through status signals - io.status <> abftUnit.io.status - - override lazy val desiredName: String = "ABFTSystolicArrayBall" -} diff --git a/arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala b/arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala deleted file mode 100644 index 549b7c04..00000000 --- a/arch/src/main/scala/prototype/abft/configs/ABFTConfig.scala +++ /dev/null @@ -1,61 +0,0 @@ -package prototype.abft.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object ABFTConfig { - implicit def rw: upickle.default.ReadWriter[ABFTConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): ABFTConfig = { - ABFTConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): ABFTConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[ABFTConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: ABFTConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class ABFTConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""ABFTConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/abft/configs/default.json b/arch/src/main/scala/prototype/abft/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/abft/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/conv/Conv.scala b/arch/src/main/scala/prototype/conv/Conv.scala deleted file mode 100644 index a412ceab..00000000 --- a/arch/src/main/scala/prototype/conv/Conv.scala +++ /dev/null @@ -1,322 +0,0 @@ -package prototype.conv - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status -import prototype.conv.configs.ConvConfig - -/** - * NVDLAConvBlackBox - BlackBox wrapper for NVDLA CONV module - * Uses inline verilog to embed NVDLA CSC module - */ -class NVDLAConvBlackBox extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val clock = Input(Clock()) - val reset = Input(Bool()) - - // Simplified CONV interface - val start = Input(Bool()) - val done = Output(Bool()) - - // Input feature map address - val ifmap_addr = Input(UInt(32.W)) - // Weight address - val weight_addr = Input(UInt(32.W)) - // Output feature map address - val ofmap_addr = Input(UInt(32.W)) - - // Convolution parameters - val in_height = Input(UInt(16.W)) - val in_width = Input(UInt(16.W)) - val in_channels = Input(UInt(16.W)) - val out_channels = Input(UInt(16.W)) - val kernel_h = Input(UInt(8.W)) - val kernel_w = Input(UInt(8.W)) - val stride_h = Input(UInt(8.W)) - val stride_w = Input(UInt(8.W)) - val pad_h = Input(UInt(8.W)) - val pad_w = Input(UInt(8.W)) - - // Data width - val data_width = Input(UInt(8.W)) - }) - - setInline( - "NVDLAConvBlackBox.v", - s""" - |module NVDLAConvBlackBox( - | input clock, - | input reset, - | input start, - | output reg done, - | input [31:0] ifmap_addr, - | input [31:0] weight_addr, - | input [31:0] ofmap_addr, - | input [15:0] in_height, - | input [15:0] in_width, - | input [15:0] in_channels, - | input [15:0] out_channels, - | input [7:0] kernel_h, - | input [7:0] kernel_w, - | input [7:0] stride_h, - | input [7:0] stride_w, - | input [7:0] pad_h, - | input [7:0] pad_w, - | input [7:0] data_width - |); - | - | reg [31:0] cycle_count; - | reg running; - | - | always @(posedge clock) begin - | if (reset) begin - | done <= 1'b0; - | cycle_count <= 32'b0; - | running <= 1'b0; - | end else begin - | if (start && !running) begin - | running <= 1'b1; - | cycle_count <= 32'b0; - | done <= 1'b0; - | end else if (running) begin - | // Simplified: compute cycles based on convolution size - | // This is a placeholder - actual NVDLA CSC would be instantiated here - | if (cycle_count >= (in_height * in_width * kernel_h * kernel_w * in_channels * out_channels / 64)) begin - | done <= 1'b1; - | running <= 1'b0; - | end else begin - | cycle_count <= cycle_count + 1; - | end - | end - | end - | end - | - |endmodule - """.stripMargin - ) -} - -/** - * Conv - Convolution computation unit - * Simplified wrapper around NVDLA CONV module - * Reads input feature map and weights from scratchpad, performs convolution, writes output - */ -@instantiable -class Conv(val parameter: ConvConfig)(implicit p: Parameters) extends Module with SerializableModule[ConvConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val accWidth = 32 - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // Command interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) - - // Unified bank read/write interface - val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) - val bankWrite = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - - // Accumulator write interface (unified bank now) - val bankWriteAcc = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, accWidth, ballParam.bankMaskLen))) - - // Status output - val status = new Status - }) - - // State machine - val idle :: sLoadIfmap :: sLoadWeight :: sCompute :: sWrite :: complete :: Nil = Enum(6) - val state = RegInit(idle) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val ifmap_addr_reg = RegInit(0.U(10.W)) - val ifmap_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val weight_addr_reg = RegInit(0.U(10.W)) - val weight_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val ofmap_addr_reg = RegInit(0.U(10.W)) - val ofmap_bank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - - // Convolution parameters from special field (40 bits total) - // special[15:0] = in_height (16 bits) - // special[31:16] = in_width (16 bits) - // special[39:32] = kernel_h (8 bits) - // Note: kernel_w is encoded in lower 8 bits of kernel_h, or use a different encoding - // For simplicity, we'll use kernel_h for both dimensions or extract from iter - val in_height_reg = RegInit(0.U(16.W)) - val in_width_reg = RegInit(0.U(16.W)) - val kernel_h_reg = RegInit(0.U(8.W)) - val kernel_w_reg = RegInit(0.U(8.W)) - - // Counters - val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val computeCounter = RegInit(0.U(32.W)) - - // NVDLA CONV BlackBox instance - val nvdlaConv = Module(new NVDLAConvBlackBox) - nvdlaConv.io.clock := clock - nvdlaConv.io.reset := reset.asBool - - // Default SRAM assignments - for (i <- 0 until ballParam.numBanks) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := false.B - - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // Default accumulator assignments - for (i <- 0 until ballParam.numBanks) { - io.bankWriteAcc(i).req.valid := false.B - io.bankWriteAcc(i).req.bits.addr := 0.U - io.bankWriteAcc(i).req.bits.data := 0.U - io.bankWriteAcc(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // Command interface defaults - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg - - // NVDLA CONV interface defaults - nvdlaConv.io.start := false.B - nvdlaConv.io.ifmap_addr := ifmap_addr_reg - nvdlaConv.io.weight_addr := weight_addr_reg - nvdlaConv.io.ofmap_addr := ofmap_addr_reg - nvdlaConv.io.in_height := in_height_reg - nvdlaConv.io.in_width := in_width_reg - nvdlaConv.io.in_channels := 16.U // Default - nvdlaConv.io.out_channels := 16.U // Default - nvdlaConv.io.kernel_h := kernel_h_reg - nvdlaConv.io.kernel_w := kernel_w_reg - nvdlaConv.io.stride_h := 1.U - nvdlaConv.io.stride_w := 1.U - nvdlaConv.io.pad_h := 0.U - nvdlaConv.io.pad_w := 0.U - nvdlaConv.io.data_width := inputWidth.U - - // Status output - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sLoadIfmap) || (state === sLoadWeight) - io.status.running := (state === sCompute) || (state === sWrite) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := computeCounter - - // State machine - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - state := sLoadIfmap - readCounter := 0.U - writeCounter := 0.U - computeCounter := 0.U - - robid_reg := io.cmdReq.bits.rob_id - ifmap_addr_reg := 0.U // New ISA: all operations start from row 0 - ifmap_bank_reg := io.cmdReq.bits.cmd.op1_bank - weight_addr_reg := 0.U // New ISA: all operations start from row 0 - weight_bank_reg := io.cmdReq.bits.cmd.op2_bank - ofmap_addr_reg := 0.U // New ISA: all operations start from row 0 - ofmap_bank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter - - // Extract convolution parameters from special field (40 bits) - in_height_reg := io.cmdReq.bits.cmd.special(15, 0) - in_width_reg := io.cmdReq.bits.cmd.special(31, 16) - kernel_h_reg := io.cmdReq.bits.cmd.special(39, 32) - // kernel_w uses same value as kernel_h for simplicity, or could be encoded differently - kernel_w_reg := io.cmdReq.bits.cmd.special(39, 32) - } - } - - is(sLoadIfmap) { - // Load input feature map (simplified: load one tile) - when(readCounter < iter_reg) { - io.bankRead(ifmap_bank_reg).req.valid := true.B - io.bankRead(ifmap_bank_reg).req.bits.addr := ifmap_addr_reg + readCounter - io.bankRead(ifmap_bank_reg).req.bits.fromDMA := false.B - - when(io.bankRead(ifmap_bank_reg).resp.valid) { - io.bankRead(ifmap_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U - } - }.otherwise { - state := sLoadWeight - readCounter := 0.U - } - } - - is(sLoadWeight) { - // Load weights (simplified: load one tile) - when(readCounter < iter_reg) { - io.bankRead(weight_bank_reg).req.valid := true.B - io.bankRead(weight_bank_reg).req.bits.addr := weight_addr_reg + readCounter - io.bankRead(weight_bank_reg).req.bits.fromDMA := false.B - - when(io.bankRead(weight_bank_reg).resp.valid) { - io.bankRead(weight_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U - } - }.otherwise { - state := sCompute - readCounter := 0.U - nvdlaConv.io.start := true.B - } - } - - is(sCompute) { - // Wait for NVDLA CONV to complete - when(nvdlaConv.io.done) { - state := sWrite - writeCounter := 0.U - }.otherwise { - computeCounter := computeCounter + 1.U - } - } - - is(sWrite) { - // Write output feature map (simplified: write one tile) - when(writeCounter < iter_reg) { - io.bankWrite(ofmap_bank_reg).req.valid := true.B - io.bankWrite(ofmap_bank_reg).req.bits.addr := ofmap_addr_reg + writeCounter - // Simplified: write zeros as placeholder (actual output would come from NVDLA CONV) - io.bankWrite(ofmap_bank_reg).req.bits.data := 0.U - io.bankWrite(ofmap_bank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(1.U(1.W))) - - when(io.bankWrite(ofmap_bank_reg).req.ready) { - writeCounter := writeCounter + 1.U - } - }.otherwise { - state := complete - } - } - - is(complete) { - io.cmdResp.valid := true.B - when(io.cmdResp.ready) { - state := idle - } - } - } -} diff --git a/arch/src/main/scala/prototype/conv/ConvBall.scala b/arch/src/main/scala/prototype/conv/ConvBall.scala deleted file mode 100644 index 8d7d0af4..00000000 --- a/arch/src/main/scala/prototype/conv/ConvBall.scala +++ /dev/null @@ -1,55 +0,0 @@ -package prototype.conv - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.conv.Conv -import prototype.conv.configs.ConvConfig - -/** - * ConvBall - A Convolution computation Ball that complies with the Blink protocol - * Behavior: Read input feature map and weights from Scratchpad, perform convolution using NVDLA CONV, - * then write output feature map back to Scratchpad. - */ -@instantiable -class ConvBall(config: ConvConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - // Satisfy BallRegist requirements - def Blink: Blink = io - - // Instantiate Conv computation unit - private val convUnit: Instance[Conv] = Instantiate(new Conv(config)) - - // Connect command interface - convUnit.io.cmdReq <> io.cmdReq - convUnit.io.cmdResp <> io.cmdResp - - // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { - convUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - convUnit.io.bankWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // ConvBall uses overwrite mode for scratchpad - - // Accumulator write (for partial sums) - use accumulate mode - // Note: ConvBall may need to write to accumulator banks with accumulate mode - // For now, assuming all writes use overwrite mode, but accumulator writes should use accumulate - // This needs to be determined based on Conv unit's actual behavior - } - - // Pass through status signals - io.status <> convUnit.io.status - - override lazy val desiredName: String = "ConvBall" -} diff --git a/arch/src/main/scala/prototype/conv/configs/ConvConfig.scala b/arch/src/main/scala/prototype/conv/configs/ConvConfig.scala deleted file mode 100644 index 4eb7dd1a..00000000 --- a/arch/src/main/scala/prototype/conv/configs/ConvConfig.scala +++ /dev/null @@ -1,61 +0,0 @@ -package prototype.conv.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object ConvConfig { - implicit def rw: upickle.default.ReadWriter[ConvConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): ConvConfig = { - ConvConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): ConvConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[ConvConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: ConvConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class ConvConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""ConvConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/conv/configs/default.json b/arch/src/main/scala/prototype/conv/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/conv/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/format/Arithmetic.scala b/arch/src/main/scala/prototype/format/Arithmetic.scala deleted file mode 100644 index d4484dc2..00000000 --- a/arch/src/main/scala/prototype/format/Arithmetic.scala +++ /dev/null @@ -1,34 +0,0 @@ -package prototype.format - -import chisel3._ -import chisel3.util._ - -// Arithmetic type class -abstract class Arithmetic[T <: Data] { - def add(x: T, y: T): T - def sub(x: T, y: T): T - def mul(x: T, y: T): T - def div(x: T, y: T): T - def gt(x: T, y: T): Bool -} - -// UInt arithmetic implementation -class UIntArithmetic extends Arithmetic[UInt] { - override def add(x: UInt, y: UInt): UInt = x + y - override def sub(x: UInt, y: UInt): UInt = x - y - override def mul(x: UInt, y: UInt): UInt = x * y - override def div(x: UInt, y: UInt): UInt = Mux(y =/= 0.U, x / y, 0.U) - override def gt(x: UInt, y: UInt): Bool = x > y -} - -// Factory -object ArithmeticFactory { - - def createArithmetic[T <: Data](dataType: T): Arithmetic[T] = { - dataType match { - case _: UInt => new UIntArithmetic().asInstanceOf[Arithmetic[T]] - case _ => throw new IllegalArgumentException(s"Unsupported data type: ${dataType.getClass}") - } - } - -} diff --git a/arch/src/main/scala/prototype/format/Dataformat.scala b/arch/src/main/scala/prototype/format/Dataformat.scala deleted file mode 100644 index 5d423f66..00000000 --- a/arch/src/main/scala/prototype/format/Dataformat.scala +++ /dev/null @@ -1,54 +0,0 @@ -package prototype.format - -import chisel3._ -import chisel3.util._ - -// Data format definition -abstract class DataFormat { - def width: Int - def dataType: Data - def name: String -} - -// INT8 format -class INT8Format extends DataFormat { - override def width: Int = 8 - override def dataType: Data = UInt(8.W) - override def name: String = "INT8" -} - -// FP16 format -class FP16Format extends DataFormat { - override def width: Int = 16 - // Temporarily use UInt representation, can be extended to Float type later - override def dataType: Data = UInt(16.W) - override def name: String = "FP16" -} - -// FP32 format -class FP32Format extends DataFormat { - override def width: Int = 32 - // Temporarily use UInt representation, can be extended to Float type later - override def dataType: Data = UInt(32.W) - override def name: String = "FP32" -} - -// Data format factory -object DataFormatFactory { - - def create(formatType: String): DataFormat = formatType.toUpperCase match { - case "INT8" => new INT8Format - case "FP16" => new FP16Format - case "FP32" => new FP32Format - case _ => throw new IllegalArgumentException(s"Unsupported data format: $formatType") - } - -} - -// Generic data format parameters -case class DataFormatParams( - formatType: String = "INT8") { - def format: DataFormat = DataFormatFactory.create(formatType) - def width: Int = format.width - def dataType: Data = format.dataType -} diff --git a/arch/src/main/scala/prototype/format/README.md b/arch/src/main/scala/prototype/format/README.md deleted file mode 100644 index 53021202..00000000 --- a/arch/src/main/scala/prototype/format/README.md +++ /dev/null @@ -1,134 +0,0 @@ -# Data Format Processing Module - -## Overview - -This directory implements data format definitions and arithmetic operation abstractions in Buckyball, providing a unified data type processing interface. Located at `arch/src/main/scala/prototype/format`, it serves as the data format layer, providing type-safe data format support for other prototype accelerators. - -Core components: -- **Dataformat.scala**: Data format definitions and factory classes -- **Arithmetic.scala**: Arithmetic operation type class implementations - -## Code Structure - -``` -format/ -├── Dataformat.scala - Data format definitions -└── Arithmetic.scala - Arithmetic operation abstractions -``` - -### File Dependencies - -**Dataformat.scala** (Format definition layer) -- Defines DataFormat abstract class and concrete format implementations -- Provides DataFormatFactory factory class -- Implements DataFormatParams parameter class - -**Arithmetic.scala** (Operation abstraction layer) -- Defines Arithmetic type class interface -- Implements UIntArithmetic concrete operations -- Provides ArithmeticFactory factory class - -## Module Description - -### Dataformat.scala - -**Main functionality**: Defines supported data format types - -**Format definition**: -```scala -abstract class DataFormat { - def width: Int - def dataType: Data - def name: String -} -``` - -**Supported formats**: -```scala -class INT8Format extends DataFormat { - override def width: Int = 8 - override def dataType: Data = UInt(8.W) - override def name: String = "INT8" -} - -class FP16Format extends DataFormat { - override def width: Int = 16 - override def dataType: Data = UInt(16.W) - override def name: String = "FP16" -} - -class FP32Format extends DataFormat { - override def width: Int = 32 - override def dataType: Data = UInt(32.W) - override def name: String = "FP32" -} -``` - -**Factory class**: -```scala -object DataFormatFactory { - def create(formatType: String): DataFormat = formatType.toUpperCase match { - case "INT8" => new INT8Format - case "FP16" => new FP16Format - case "FP32" => new FP32Format - case _ => throw new IllegalArgumentException(...) - } -} -``` - -**Parameter class**: -```scala -case class DataFormatParams(formatType: String = "INT8") { - def format: DataFormat = DataFormatFactory.create(formatType) - def width: Int = format.width - def dataType: Data = format.dataType -} -``` - -### Arithmetic.scala - -**Main functionality**: Provides type-safe arithmetic operation abstractions - -**Type class definition**: -```scala -abstract class Arithmetic[T <: Data] { - def add(x: T, y: T): T - def sub(x: T, y: T): T - def mul(x: T, y: T): T - def div(x: T, y: T): T - def gt(x: T, y: T): Bool -} -``` - -**UInt implementation**: -```scala -class UIntArithmetic extends Arithmetic[UInt] { - override def add(x: UInt, y: UInt): UInt = x + y - override def sub(x: UInt, y: UInt): UInt = x - y - override def mul(x: UInt, y: UInt): UInt = x * y - override def div(x: UInt, y: UInt): UInt = Mux(y =/= 0.U, x / y, 0.U) - override def gt(x: UInt, y: UInt): Bool = x > y -} -``` - -**Factory class**: -```scala -object ArithmeticFactory { - def createArithmetic[T <: Data](dataType: T): Arithmetic[T] = { - dataType match { - case _: UInt => new UIntArithmetic().asInstanceOf[Arithmetic[T]] - case _ => throw new IllegalArgumentException(...) - } - } -} -``` - -## Usage - -### Notes - -1. **Floating-point support**: FP16 and FP32 currently use UInt representation, can be extended to true floating-point types later -2. **Division by zero protection**: UInt division operation includes division-by-zero check, returns 0 as default value -3. **Type safety**: Uses Scala type system to ensure operation type safety -4. **Extensibility**: Factory pattern supports adding new data formats and arithmetic implementations -5. **Parameterization**: DataFormatParams provides convenient parameterized configuration interface diff --git a/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala b/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala deleted file mode 100644 index faa23f02..00000000 --- a/arch/src/main/scala/prototype/ibuki/matmul/LIF.scala +++ /dev/null @@ -1,224 +0,0 @@ -package prototype.ibuki.matmul - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status - -@instantiable -class LIF(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val cmdResp = Decoupled(new BallRsComplete(parameter)) - - // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) - val sramWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) - - // Status output - val status = new Status - }) - - // State definitions - val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) - - // Store a InputNum x InputNum tile - val regArray = RegInit( - VecInit(Seq.fill(InputNum)( - VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - )) - ) - - // Counters - val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - val cycle_reg = RegInit(0.U(6.W)) - val iterCnt = RegInit(0.U(32.W)) - - // LIF parameters from special field - // special[7:0] = threshold (8 bits) - // special[15:8] = leak_factor (8 bits, represents leak rate) - val threshold_reg = RegInit(127.U(8.W)) // Default threshold - val leak_factor_reg = RegInit(240.U(8.W)) // Default leak factor (240/256 ≈ 0.9375) - - // Precompute write data - val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(parameter.bankMaskLen, UInt(1.W))) - - // SRAM default assignment - for (i <- 0 until parameter.numBanks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg - - // State machine - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U - writeCounter := 0.U - - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U // New ISA: all operations start from row 0 - wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := 0.U // New ISA: all operations start from row 0 - rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U - - // Extract LIF parameters from special field - threshold_reg := io.cmdReq.bits.cmd.special(7, 0) - leak_factor_reg := io.cmdReq.bits.cmd.special(15, 8) - } - - when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U - writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + InputNum.U - raddr_reg := raddr_reg + InputNum.U - cycle_reg := cycle_reg - 1.U - } - } - - is(sRead) { - when(readCounter < InputNum.U) { - // Issue read request - readCounter := readCounter + 1.U - io.sramRead(rbank_reg).req.valid := true.B - io.sramRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - } - - // Receive response and perform LIF neuron computation - io.sramRead(rbank_reg).resp.ready := true.B - when(io.sramRead(rbank_reg).resp.fire) { - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - val raw = io.sramRead(rbank_reg).resp.bits.data(hi, lo) - val signed = raw.asSInt - - // LIF neuron model: - // 1. Leak: membrane_potential = membrane_potential * leak_factor / 256 - // 2. Integrate: (input is already in membrane_potential, so just apply leak) - // 3. Fire: if membrane_potential >= threshold, output spike (threshold value), else output leaked potential - - // Apply leak (multiply by leak_factor, then divide by 256) - // leak_factor is unsigned (0-255), representing leak rate - // Convert to signed for multiplication, then shift right by 8 - val leak_factor_signed = leak_factor_reg.zext.asSInt - val leaked = (signed * leak_factor_signed) >> 8 - - // Fire condition: if leaked >= threshold, output spike (threshold), else output leaked - // For simplicity, we output the threshold value as spike, or the leaked value - val result = Mux( - leaked >= threshold_reg.asSInt, - threshold_reg.asSInt, - Mux(leaked < (-threshold_reg).asSInt, (-threshold_reg).asSInt, leaked) - ) - - regArray(respCounter)(col) := result.asUInt - } - respCounter := respCounter + 1.U - } - - when(respCounter === InputNum.U) { - state := sWrite - // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) - // Set write mask (write all) - for (i <- 0 until parameter.bankMaskLen) { - writeMaskReg(i) := 1.U(1.W) - } - } - } - - is(sWrite) { - // Write back results - io.sramWrite(wbank_reg).req.valid := writeCounter < InputNum.U - io.sramWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.sramWrite(wbank_reg).req.bits.data := writeDataReg - io.sramWrite(wbank_reg).req.bits.mask := writeMaskReg - - when(writeCounter === (InputNum - 1).U) { - state := complete - }.otherwise { - writeCounter := writeCounter + 1.U - // Prepare next row's write data - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) - } - } - - is(complete) { - when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } - } - state := idle - } - } - - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < InputNum.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt - - when(reset.asBool) { - for (i <- 0 until InputNum) { - for (j <- 0 until InputNum) { - regArray(i)(j) := 0.U - } - } - writeDataReg := 0.U - for (i <- 0 until parameter.bankMaskLen) { - writeMaskReg(i) := 0.U - } - } -} diff --git a/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala b/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala deleted file mode 100644 index d3952deb..00000000 --- a/arch/src/main/scala/prototype/ibuki/matmul/LIFMatmulBall.scala +++ /dev/null @@ -1,43 +0,0 @@ -package prototype.ibuki.matmul - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.ibuki.matmul.LIF - -@instantiable -class LIFMatmulBall(parameter: BallDomainParam, id: Int)(implicit p: Parameters) extends Module with BallRegist { - @public - val io = IO(new Blink(parameter, parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) - val ballId = id.U - - // Satisfy BallRegist requirements - def Blink: Blink = io - - // Instantiate LIF computation unit - private val lifUnit: Instance[LIF] = Instantiate(new LIF(parameter)) - - // Connect command interface - lifUnit.io.cmdReq <> io.cmdReq - lifUnit.io.cmdResp <> io.cmdResp - - // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { - lifUnit.io.sramRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - lifUnit.io.sramWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // LIFMatmulBall uses overwrite mode - } - - // Pass through status signals - io.status <> lifUnit.io.status - - override lazy val desiredName: String = "LIFMatmulBall" -} diff --git a/arch/src/main/scala/prototype/im2col/Im2colBall.scala b/arch/src/main/scala/prototype/im2col/Im2colBall.scala deleted file mode 100644 index 095db500..00000000 --- a/arch/src/main/scala/prototype/im2col/Im2colBall.scala +++ /dev/null @@ -1,47 +0,0 @@ -package prototype.im2col - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.im2col.Im2col -import prototype.im2col.configs.Im2colConfig - -/** - * Im2colBall - An Im2col computation Ball that complies with the Blink protocol - */ -@instantiable -class Im2colBall(config: Im2colConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - def Blink: Blink = io - - // Instantiate Im2col - val im2colUnit: Instance[Im2col] = Instantiate(new Im2col(config)) - - // Connect command interface - im2colUnit.io.cmdReq <> io.cmdReq - im2colUnit.io.cmdResp <> io.cmdResp - - // Connect Bank interface - for (i <- 0 until parameter.numBanks) { - im2colUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - im2colUnit.io.bankWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // Im2colBall uses overwrite mode - } - - // Connect Status signals - directly obtained from internal unit - io.status <> im2colUnit.io.status - - override lazy val desiredName = "Im2colBall" -} diff --git a/arch/src/main/scala/prototype/im2col/README.md b/arch/src/main/scala/prototype/im2col/README.md deleted file mode 100644 index 71f5c5c1..00000000 --- a/arch/src/main/scala/prototype/im2col/README.md +++ /dev/null @@ -1,111 +0,0 @@ -# Im2col Image Processing Accelerator - -## Overview - -This directory implements Buckyball's Im2col operation accelerator for image-to-column matrix conversion in convolutional neural networks. Located at `arch/src/main/scala/prototype/im2col`, it serves as an image processing accelerator that converts convolution operations to matrix multiplication operations to improve computational efficiency. - -Core components: -- **im2col.scala**: Im2col accelerator main implementation - -## Code Structure - -``` -im2col/ -└── im2col.scala - Im2col accelerator implementation -``` - -### Module Responsibilities - -**Im2col.scala** (Accelerator implementation layer) -- Implements image-to-column matrix conversion logic -- Manages SRAM read/write operations -- Provides Ball domain command interface - -## Module Description - -### im2col.scala - -**Main functionality**: Implements sliding convolution window and data rearrangement - -**State machine definition**: -```scala -val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) -val state = RegInit(idle) -``` - -**Key registers**: -```scala -val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W)))))) -val rowptr = RegInit(0.U(10.W)) // Convolution window top-left row pointer -val colptr = RegInit(0.U(5.W)) // Convolution window top-left column pointer -val krow_reg = RegInit(0.U(log2Up(b.veclane).W)) // Convolution kernel row count -val kcol_reg = RegInit(0.U(log2Up(b.veclane).W)) // Convolution kernel column count -``` - -**Command parsing**: -```scala -when(io.cmdReq.fire) { - rowptr := io.cmdReq.bits.cmd.special(37,28) // Start row - colptr := io.cmdReq.bits.cmd.special(27,23) // Start column - kcol_reg := io.cmdReq.bits.cmd.special(3,0) // Convolution kernel column count - krow_reg := io.cmdReq.bits.cmd.special(7,4) // Convolution kernel row count - incol_reg := io.cmdReq.bits.cmd.special(12,8) // Input matrix column count - inrow_reg := io.cmdReq.bits.cmd.special(22,13) // Input matrix row count -} -``` - -**Data conversion logic**: -```scala -// Fill window data -for (i <- 0 until 4; j <- 0 until 4) { - when(i.U < krow_reg && j.U < kcol_reg) { - val bufferRow = (rowcnt + i.U) % krow_reg - val bufferCol = (colptr + j.U) % incol_reg - window((i.U * kcol_reg) + j.U) := ConvertBuffer(bufferRow)(bufferCol) - }.otherwise { - window((i.U * kcol_reg) + j.U) := 0.U - } -} -``` - -**SRAM interface**: -```scala -val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(...))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(...))) -}) -``` - -**Processing flow**: -1. **idle**: Wait for command, parse convolution parameters -2. **read**: Read initial convolution kernel-sized data into buffer -3. **read_and_convert**: Slide window, convert data and write back -4. **complete**: Send completion signal - -**Inputs/Outputs**: -- Input: Ball domain commands containing convolution parameters and address information -- Output: Converted column matrix data, completion signal -- Edge cases: Fill zero values when handling boundaries - -## Usage - -### Algorithm Principle - -**Im2col conversion**: Convert convolution operation to matrix multiplication -- Input: H×W image, K×K convolution kernel -- Output: (H-K+1)×(W-K+1) windows of size K×K, expanded as column vectors - -**Sliding window**: -- Slide convolution window in row-major order -- Each window position generates a column vector -- Uses circular buffer to optimize memory access - -### Notes - -1. **Buffer management**: Uses 4×veclane conversion buffer to store window data -2. **Boundary handling**: Fill zero values for positions beyond image boundaries -3. **Address calculation**: Supports configurable start address and bank selection -4. **Pipeline optimization**: Prefetch next row read requests during conversion -5. **Parameter limitation**: Maximum support for 4×4 convolution kernel size diff --git a/arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala b/arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala deleted file mode 100644 index cde87f2d..00000000 --- a/arch/src/main/scala/prototype/im2col/configs/Im2colConfig.scala +++ /dev/null @@ -1,62 +0,0 @@ -package prototype.im2col.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object Im2colConfig { - implicit def rw: upickle.default.ReadWriter[Im2colConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): Im2colConfig = { - Im2colConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): Im2colConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[Im2colConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: Im2colConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class Im2colConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - // Derived parameters - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""Im2colConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/im2col/configs/default.json b/arch/src/main/scala/prototype/im2col/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/im2col/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/im2col/im2col.scala b/arch/src/main/scala/prototype/im2col/im2col.scala deleted file mode 100644 index 188e73c4..00000000 --- a/arch/src/main/scala/prototype/im2col/im2col.scala +++ /dev/null @@ -1,216 +0,0 @@ -package prototype.im2col - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status -import prototype.im2col.configs.Im2colConfig - -@instantiable -class Im2col(val parameter: Im2colConfig)(implicit p: Parameters) extends Module with SerializableModule[Im2colConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) - - // Connect to unified bank read/write interface - val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) - val bankWrite = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - - // Status output - val status = new Status - }) - - // State definitions - val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) - // Current state register - val state = RegInit(idle) - // Conversion buffer - val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(InputNum)(0.U(inputWidth.W)))))) - // Row pointer marking top-left corner of convolution window - val rowptr = RegInit(0.U(10.W)) - // Column pointer marking top-left corner of convolution window - val colptr = RegInit(0.U(5.W)) - // Request counter in read state - val reqcounter = RegInit(0.U(5.W)) - // Response counter in read state - val respcounter = RegInit(0.U(5.W)) - // Store current instruction's RoB ID - val robid_reg = RegInit(0.U(10.W)) - // Store kernel row count - val krow_reg = RegInit(0.U(log2Up(InputNum).W)) - // Store kernel column count - val kcol_reg = RegInit(0.U(log2Up(InputNum).W)) - // Store input matrix row count - val inrow_reg = RegInit(0.U(10.W)) - // Store input matrix column count - val incol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) - // Store starting column number - val startcol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) - // Store starting row number - val startrow_reg = RegInit(0.U(10.W)) - // Store write starting address - val waddr_reg = RegInit(0.U(10.W)) - // Store write bank - val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - // Store read starting address - val raddr_reg = RegInit(0.U(10.W)) - // Store read bank - val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) - - // SRAM default assignment - for (i <- 0 until ballParam.numBanks) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := (state === read) || (state === read_and_convert) - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - // cmd interface default assignment - io.cmdReq.ready := true.B - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U - - val rowcnt = rowptr - startrow_reg - val colcnt = colptr - startcol_reg - val rowmax = inrow_reg - krow_reg - val colmax = incol_reg - kcol_reg - - switch(state) { - // Idle state, waiting for instruction - is(idle) { - // Instruction arrives, initialize registers - when(io.cmdReq.fire) { - state := read - rowptr := io.cmdReq.bits.cmd.special(37, 28) - colptr := io.cmdReq.bits.cmd.special(27, 23) - reqcounter := 0.U - respcounter := 0.U - // Kernel column count - kcol_reg := io.cmdReq.bits.cmd.special(3, 0) - // Kernel row count - krow_reg := io.cmdReq.bits.cmd.special(7, 4) - // Input matrix column count - incol_reg := io.cmdReq.bits.cmd.special(12, 8) - // Input matrix row count - inrow_reg := io.cmdReq.bits.cmd.special(22, 13) - // Starting column number - startcol_reg := io.cmdReq.bits.cmd.special(27, 23) - // Starting row number - startrow_reg := io.cmdReq.bits.cmd.special(37, 28) - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U // New ISA: all operations start from row 0 - wbank_reg := io.cmdReq.bits.cmd.op2_bank - raddr_reg := 0.U // New ISA: all operations start from row 0 - rbank_reg := io.cmdReq.bits.cmd.op1_bank - } - } - // Read part of data, fill ConvertBuffer - is(read) { - // Send read request - when(reqcounter < krow_reg) { - reqcounter := reqcounter + 1.U - io.bankRead(rbank_reg).req.valid := true.B - io.bankRead(rbank_reg).req.bits.addr := raddr_reg + reqcounter + startrow_reg - } - // Process read response and store in ConvertBuffer - when(io.bankRead(rbank_reg).resp.fire) { - ConvertBuffer(respcounter) := io.bankRead(rbank_reg).resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - respcounter := respcounter + 1.U - } - // Determine whether to transition state - state := Mux(respcounter === krow_reg, read_and_convert, read) - - } - // Convert data and read remaining data, write back to spad - is(read_and_convert) { - // Move pointer - when(colptr <= colmax && rowptr <= rowmax) { - colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) - io.bankWrite(wbank_reg).req.valid := true.B - io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt - io.bankWrite(wbank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(~0.U(1.W))) - io.bankWrite(wbank_reg).req.bits.data := { - - val window = Wire(Vec(InputNum, UInt(inputWidth.W))) - // Initialize all to 0 first - for (i <- 0 until InputNum) { - window(i) := 0.U - } - - // Fill window data - for { - i <- 0 until 4 - j <- 0 until 4 - } { - when(i.U < krow_reg && j.U < kcol_reg) { - val bufferRow = (rowcnt + i.U) % krow_reg - val bufferCol = (colptr + j.U) % incol_reg - window((i.U * kcol_reg) + j.U) := ConvertBuffer(bufferRow)(bufferCol) - }.otherwise { - window((i.U * kcol_reg) + j.U) := 0.U - } - } - - // Rearrange data - // For example, for klen_reg=3, combine (00)(01)(02)(10)(11)(12)(20)(21)(22) - Cat((0 until InputNum).map(i => window(i)).reverse) - } - } - // Send read request early - when(colptr === colmax - 1.U) { - io.bankRead(rbank_reg).req.valid := true.B - io.bankRead(rbank_reg).req.bits.addr := raddr_reg + krow_reg + rowptr - } - // Process read response and store in ConvertBuffer - when(io.bankRead(rbank_reg).resp.fire) { - ConvertBuffer(rowcnt % krow_reg) := io.bankRead(rbank_reg).resp.bits.data.asTypeOf(Vec( - InputNum, - UInt(inputWidth.W) - )) - rowptr := rowptr + 1.U - } - // Determine whether to transition state - state := Mux(rowptr === rowmax && colptr === colmax, complete, read_and_convert) - } - // Complete state, send completion signal - is(complete) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg - state := idle - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } - } - } - - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === read) - io.status.running := (state === read_and_convert) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt -} diff --git a/arch/src/main/scala/prototype/matrix/MatrixBall.scala b/arch/src/main/scala/prototype/matrix/MatrixBall.scala deleted file mode 100644 index 99d389a4..00000000 --- a/arch/src/main/scala/prototype/matrix/MatrixBall.scala +++ /dev/null @@ -1,50 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.matrix.BBFP_Control -import prototype.matrix.configs.MatrixConfig - -/** - * MatrixBall - A matrix computation Ball that complies with the Blink protocol - */ -@instantiable -class MatrixBall(config: MatrixConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - def Blink: Blink = io - - // Instantiate BBFP_Control - val matrixUnit: Instance[BBFP_Control] = Instantiate(new BBFP_Control(parameter)) - - // Connect command interface - matrixUnit.io.cmdReq <> io.cmdReq - matrixUnit.io.cmdResp <> io.cmdResp - - // Set is_matmul_ws signal - matrixUnit.io.is_matmul_ws := false.B // TODO: - - // Connect Bank interface - for (i <- 0 until parameter.numBanks) { - matrixUnit.io.sramRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - matrixUnit.io.sramWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // MatrixBall uses overwrite mode - } - - // Connect Status signals - directly obtained from internal unit - io.status <> matrixUnit.io.status - - override lazy val desiredName = "MatrixBall" -} diff --git a/arch/src/main/scala/prototype/matrix/README.md b/arch/src/main/scala/prototype/matrix/README.md deleted file mode 100644 index 7f506d2f..00000000 --- a/arch/src/main/scala/prototype/matrix/README.md +++ /dev/null @@ -1,153 +0,0 @@ -# Matrix Computation Accelerator - -## Overview - -This directory implements Buckyball's matrix computation accelerator for matrix multiplication and related operations. Located at `arch/src/main/scala/prototype/matrix`, it serves as a matrix computation accelerator supporting multiple data formats and operation modes. - -Core components: -- **bbfp_control.scala**: Matrix computation controller -- **bbfp_pe.scala**: Processing Element (PE) and MAC unit -- **bbfp_buffer.scala**: Data buffer management -- **bbfp_load.scala**: Data load unit -- **bbfp_ex.scala**: Execution unit -- **bbfpIns_decode.scala**: Instruction decoder - -## Code Structure - -``` -matrix/ -├── bbfp_control.scala - Controller main module -├── bbfp_pe.scala - Processing element implementation -├── bbfp_buffer.scala - Buffer management -├── bbfp_load.scala - Load unit -├── bbfp_ex.scala - Execution unit -└── bbfpIns_decode.scala - Instruction decode -``` - -### File Dependencies - -**bbfp_control.scala** (Controller layer) -- Integrates submodules (ID, LU, EX, etc.) -- Manages SRAM and Accumulator interfaces -- Handles Ball domain commands - -**bbfp_pe.scala** (Computation core layer) -- Implements MacUnit multiply-accumulate unit -- Defines PEControl control signals -- Handles signed/unsigned operations - -**Other modules** (Functional support layer) -- Provides data buffering, loading, execution and other support functions - -## Module Description - -### bbfp_control.scala - -**Main functionality**: Top-level control module for matrix computation accelerator - -**Module integration**: -```scala -class BBFP_Control extends Module { - val BBFP_ID = Module(new BBFP_ID) - val ID_LU = Module(new ID_LU) - val BBFP_LoadUnit = Module(new BBFP_LoadUnit) - val LU_EX = Module(new LU_EX) -} -``` - -**Interface definition**: -```scala -val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) - val is_matmul_ws = Input(Bool()) - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(...))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(...))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(...))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(...))) -}) -``` - -**Data flow**: -``` -cmdReq → BBFP_ID → ID_LU → BBFP_LoadUnit → LU_EX - ↓ - SRAM/ACC interface -``` - -### bbfp_pe.scala - -**Main functionality**: Implements basic processing element for matrix computation - -**MAC unit definition**: -```scala -class MacUnit extends Module { - val io = IO(new Bundle { - val in_a = Input(UInt(7.W)) // [6]=sign, [5]=flag, [4:0]=value - val in_b = Input(UInt(7.W)) // [6]=sign, [5]=flag, [4:0]=value - val in_c = Input(UInt(32.W)) // [31]=sign, [30:0]=value - val out_d = Output(UInt(32.W)) // Output result - }) -} -``` - -**Data format processing**: -```scala -// Extract sign bit and value -val sign_a = io.in_a(6) -val sign_b = io.in_b(6) -val flag_a = io.in_a(5) -val flag_b = io.in_b(5) -val value_a = io.in_a(4, 0) -val value_b = io.in_b(4, 0) - -// Determine left shift based on flag bit -val shifted_a = Mux(flag_a === 1.U, value_a << 2, value_a) -val shifted_b = Mux(flag_b === 1.U, value_b << 2, value_b) -``` - -**Signed arithmetic**: -```scala -val a_signed = Mux(sign_a === 1.U, -(shifted_a.zext), shifted_a.zext).asSInt -val b_signed = Mux(sign_b === 1.U, -(shifted_b.zext), shifted_b.zext).asSInt -``` - -**Control signals**: -```scala -class PEControl extends Bundle { - val propagate = UInt(1.W) // Propagation control -} -``` - -## Usage - -### Data Format - -**Input format**: 7-bit compressed format -- bit[6]: Sign bit (0=positive, 1=negative) -- bit[5]: Flag bit (1=left shift by 2) -- bit[4:0]: 5-bit value - -**Output format**: 32-bit signed number -- bit[31]: Sign bit -- bit[30:0]: 31-bit value - -### Operation Characteristics - -**MAC operation**: Multiply-Accumulate operation -- Supports signed and unsigned operations -- Configurable shift operations -- 32-bit accumulator output - -**Pipeline structure**: -- ID: Instruction decode stage -- LU: Load unit stage -- EX: Execution unit stage - -### Notes - -1. **Data format**: Uses custom 7-bit compressed format to reduce storage overhead -2. **Sign handling**: Supports correct signed number operations and sign extension -3. **Shift optimization**: Controls data preprocessing shift through flag bit -4. **Interface compatibility**: Fully compatible with SRAM and Accumulator interfaces -5. **Pipeline design**: Multi-stage pipeline improves throughput diff --git a/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala b/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala deleted file mode 100644 index 460391b9..00000000 --- a/arch/src/main/scala/prototype/matrix/bbfpIns_decode.scala +++ /dev/null @@ -1,110 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.matrix._ -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam - -@instantiable -class BBFP_ID(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val rob_id_width = log2Up(parameter.rob_entries) - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val is_matmul_ws = Output(Bool()) - val id_lu_o = Decoupled(new id_lu_req(parameter)) - }) - - val idle :: busy :: Nil = Enum(2) - // Register definitions - val state = RegInit(idle) - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val iteration_counter = RegInit(0.U(10.W)) - val iteration = RegInit(0.U(10.W)) - val op1_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val op2_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val wr_bank = RegInit(0.U(log2Up(parameter.numBanks).W)) - val wr_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val is_matmul_ws = RegInit(false.B) - io.is_matmul_ws := false.B - - switch(state) { - is(idle) { - when(io.cmdReq.valid && io.cmdReq.bits.cmd.bid === 1.U) { - iteration := io.cmdReq.bits.cmd.iter - iteration_counter := 0.U - is_matmul_ws := false.B - rob_id_reg := io.cmdReq.bits.rob_id - op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := 0.U // New ISA: all operations start from row 0 - op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := 0.U // New ISA: all operations start from row 0 - wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := 0.U // New ISA: all operations start from row 0 - state := busy - io.is_matmul_ws := false.B - } - when(io.cmdReq.valid && io.cmdReq.bits.cmd.special(0)) { - iteration := io.cmdReq.bits.cmd.iter - iteration_counter := 0.U - is_matmul_ws := true.B - rob_id_reg := io.cmdReq.bits.rob_id - op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := 0.U // New ISA: all operations start from row 0 - op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := 0.U // New ISA: all operations start from row 0 - wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := 0.U // New ISA: all operations start from row 0 - state := busy - io.is_matmul_ws := true.B - } - } - is(busy) { - iteration_counter := iteration_counter + 1.U - when(iteration_counter === iteration - 1.U) { - iteration_counter := 0.U - state := idle - } - } - } - // Generate ID_LU request - io.id_lu_o.valid := state === busy - io.id_lu_o.bits.op1_bank := op1_bank - io.id_lu_o.bits.op1_bank_addr := op1_bank_addr + InputNum.U - iteration_counter - 1.U - io.id_lu_o.bits.op2_bank := op2_bank - io.id_lu_o.bits.op2_bank_addr := op2_bank_addr + iteration_counter - io.id_lu_o.bits.wr_bank := wr_bank - io.id_lu_o.bits.wr_bank_addr := wr_bank_addr + iteration_counter - io.id_lu_o.bits.opcode := 1.U - io.id_lu_o.bits.iter := iteration - io.id_lu_o.bits.thread_id := iteration_counter - io.id_lu_o.bits.rob_id := rob_id_reg - - io.cmdReq.ready := io.id_lu_o.ready - - // Instruction completion signal - - // Delay complete signal by 10 cycles - // val complete_delay = RegInit(VecInit(Seq.fill(10)(false.B))) - // complete_delay(0) := complete - // for (i <- 1 until 10) { - // complete_delay(i) := complete_delay(i-1) - // } - // val complete_10clk = complete_delay(9) - -} diff --git a/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala b/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala deleted file mode 100644 index d7a9bcc7..00000000 --- a/arch/src/main/scala/prototype/matrix/bbfp_buffer.scala +++ /dev/null @@ -1,77 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.matrix._ -import examples.toy.balldomain.BallDomainParam - -class id_lu_req(parameter: BallDomainParam) extends Bundle { - val op1_bank = UInt(log2Up(parameter.numBanks).W) - val op1_bank_addr = UInt(log2Up(parameter.bankEntries).W) - val op2_bank = UInt(log2Up(parameter.numBanks).W) - val op2_bank_addr = UInt(log2Up(parameter.bankEntries).W) - val wr_bank = UInt(log2Up(parameter.numBanks).W) - val wr_bank_addr = UInt(log2Up(parameter.bankEntries).W) - val opcode = UInt(3.W) - val iter = UInt(10.W) - val thread_id = UInt(10.W) - val rob_id = UInt(log2Up(parameter.rob_entries).W) -} - -class lu_ex_req(parameter: BallDomainParam) extends Bundle { - val op1_bank = UInt(log2Up(parameter.numBanks).W) - val op2_bank = UInt(log2Up(parameter.numBanks).W) - val wr_bank = UInt(log2Up(parameter.numBanks).W) - val wr_bank_addr = UInt(log2Up(parameter.bankEntries).W) - val opcode = UInt(3.W) - val iter = UInt(10.W) - val thread_id = UInt(10.W) - val rob_id = UInt(log2Up(parameter.rob_entries).W) -} - -@instantiable -class ID_LU(val parameter: BallDomainParam) extends Module with SerializableModule[BallDomainParam] { - - @public - val io = IO(new Bundle { - val id_lu_i = Flipped(Decoupled(new id_lu_req(parameter))) - val ld_lu_o = Decoupled(new id_lu_req(parameter)) - }) - - // 1-cycle delay register - val delayed_req = RegEnable(io.id_lu_i.bits, io.id_lu_i.fire) - val delayed_valid = RegNext(io.id_lu_i.valid, false.B) - - // Output connection - io.ld_lu_o.bits := delayed_req - io.ld_lu_o.valid := delayed_valid - - // Backpressure: input is ready if output is ready (since we have a 1-slot buffer) - io.id_lu_i.ready := io.ld_lu_o.ready -} - -@instantiable -class LU_EX(val parameter: BallDomainParam) extends Module with SerializableModule[BallDomainParam] { - - @public - val io = IO(new Bundle { - val lu_ex_i = Flipped(Decoupled(new lu_ex_req(parameter))) - val lu_ex_o = Decoupled(new lu_ex_req(parameter)) - }) - - // 1-cycle delay register - val delayed_req = RegEnable(io.lu_ex_i.bits, io.lu_ex_i.fire) - val delayed_valid = RegNext(io.lu_ex_i.valid, false.B) - - // Output connection - io.lu_ex_o.bits := delayed_req - io.lu_ex_o.valid := delayed_valid - - // Backpressure: input is ready if output is ready (since we have a 1-slot buffer) - io.lu_ex_i.ready := io.lu_ex_o.ready -} diff --git a/arch/src/main/scala/prototype/matrix/bbfp_control.scala b/arch/src/main/scala/prototype/matrix/bbfp_control.scala deleted file mode 100644 index c1cb0d13..00000000 --- a/arch/src/main/scala/prototype/matrix/bbfp_control.scala +++ /dev/null @@ -1,109 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.matrix._ -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status - -@instantiable -class BBFP_Control(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - using default values for compatibility - val InputNum = 16 // Default value - val inputWidth = 8 // UInt8 - val accWidth = 32 // UInt32 - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val cmdResp = Decoupled(new BallRsComplete(parameter)) - val is_matmul_ws = Input(Bool()) - // Connect to Scratchpad SRAM read/write interface - val sramRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) - val sramWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) - - // Connect to Accumulator write interface (unified bank now) - val accWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) - - // Status output - val status = new Status - }) - -// ----------------------------------------------------------------------------- -// BBFP_ID -// ----------------------------------------------------------------------------- - val BBFP_ID: Instance[BBFP_ID] = Instantiate(new BBFP_ID(parameter)) - BBFP_ID.io.cmdReq <> io.cmdReq -// ----------------------------------------------------------------------------- -// ID_LU -// ----------------------------------------------------------------------------- - val ID_LU: Instance[ID_LU] = Instantiate(new ID_LU(parameter)) - ID_LU.io.id_lu_i <> BBFP_ID.io.id_lu_o - -// ----------------------------------------------------------------------------- -// BBFP_LoadUnit -// ----------------------------------------------------------------------------- - val BBFP_LoadUnit: Instance[BBFP_LoadUnit] = Instantiate(new BBFP_LoadUnit(parameter)) - BBFP_LoadUnit.io.id_lu_i <> ID_LU.io.ld_lu_o - for (i <- 0 until parameter.numBanks) { - io.sramRead(i).req <> BBFP_LoadUnit.io.sramReadReq(i) - } -// ----------------------------------------------------------------------------- -// LU_EX -// ----------------------------------------------------------------------------- - val LU_EX: Instance[LU_EX] = Instantiate(new LU_EX(parameter)) - LU_EX.io.lu_ex_i <> BBFP_LoadUnit.io.lu_ex_o - -// ----------------------------------------------------------------------------- -// BBFP_EX -// ----------------------------------------------------------------------------- - val BBFP_EX: Instance[BBFP_EX] = Instantiate(new BBFP_EX(parameter)) - BBFP_EX.io.lu_ex_i <> LU_EX.io.lu_ex_o - for (i <- 0 until parameter.numBanks) { - BBFP_EX.io.sramReadResp(i) <> io.sramRead(i).resp - io.sramWrite(i) <> BBFP_EX.io.sramWrite(i) - } - BBFP_EX.io.is_matmul_ws := io.is_matmul_ws - for (i <- 0 until parameter.numBanks) { - io.accWrite(i) <> BBFP_EX.io.accWrite(i) - } - io.cmdResp <> BBFP_EX.io.cmdResp - - // Status tracking - val iterCnt = RegInit(0.U(32.W)) - val hasInput = RegInit(false.B) - val hasOutput = RegInit(false.B) - - when(io.cmdReq.fire) { - hasInput := true.B - } - when(io.cmdResp.fire) { - hasOutput := false.B - hasInput := false.B - iterCnt := iterCnt + 1.U - } - when(io.cmdResp.valid && !hasOutput) { - hasOutput := true.B - } - - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := !hasInput && !hasOutput - io.status.init := hasInput && !hasOutput - io.status.running := hasOutput - io.status.complete := io.cmdResp.fire - io.status.iter := iterCnt - -} diff --git a/arch/src/main/scala/prototype/matrix/bbfp_ex.scala b/arch/src/main/scala/prototype/matrix/bbfp_ex.scala deleted file mode 100644 index 9d798e27..00000000 --- a/arch/src/main/scala/prototype/matrix/bbfp_ex.scala +++ /dev/null @@ -1,302 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.matrix._ -import framework.memdomain.backend.banks.{SramReadResp, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam - -@instantiable -class BBFP_EX(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val accWidth = 32 - val rob_id_width = log2Up(parameter.rob_entries) - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - val sramWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) - val lu_ex_i = Flipped(Decoupled(new lu_ex_req(parameter))) - val sramReadResp = Vec(parameter.numBanks, Flipped(Decoupled(new SramReadResp(bankWidth)))) - val is_matmul_ws = Input(Bool()) - val accWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) - val cmdResp = Decoupled(new BallRsComplete(parameter)) - }) - - for (i <- 0 until parameter.numBanks) { - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(false.B)) - } - - for (i <- 0 until parameter.numBanks) { - io.accWrite(i).req.valid := false.B - io.accWrite(i).req.bits.addr := DontCare - io.accWrite(i).req.bits.data := DontCare - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) - } - - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U - - val idle :: weight_load :: data_compute :: Nil = Enum(3) - val weight_cycles = RegInit(0.U(10.W)) - val act_cycles = RegInit(0.U(10.W)) - val weight_expreg = RegInit(0.U(32.W)) - val act_expreg = RegInit(0.U(32.W)) - // Extract signals from pipeline frontend - val op1_bank_reg = Reg(UInt(io.lu_ex_i.bits.op1_bank.getWidth.W)) - val op2_bank_reg = Reg(UInt(io.lu_ex_i.bits.op2_bank.getWidth.W)) - val wr_bank = Reg(UInt(io.lu_ex_i.bits.wr_bank.getWidth.W)) - val opcode = Reg(UInt(io.lu_ex_i.bits.opcode.getWidth.W)) - - val act_shift_reg = Reg(Vec(16, Vec(16, UInt(7.W)))) - val col_enable = RegInit(VecInit(Seq.fill(16)(false.B))) - val input_cycle = RegInit(0.U(5.W)) - val act_data_ready = RegInit(false.B) - - when(io.lu_ex_i.valid) { - op1_bank_reg := io.lu_ex_i.bits.op1_bank - op2_bank_reg := io.lu_ex_i.bits.op2_bank - wr_bank := io.lu_ex_i.bits.wr_bank - opcode := io.lu_ex_i.bits.opcode - } - - val op1_bank = Mux(io.lu_ex_i.valid, io.lu_ex_i.bits.op1_bank, op1_bank_reg) - val op2_bank = Mux(io.lu_ex_i.valid, io.lu_ex_i.bits.op2_bank, op2_bank_reg) - - val state = RegInit(idle) - val pe_array = Module(new BBFP_PE_Array16x16) - - // Use shift registers instead of original regular registers - - // Activation data input logic - val act_reg_ptr = RegInit(0.U(5.W)) - - // In idle and weight_load phases, store data like regular registers - when(io.sramReadResp(op2_bank).valid && state =/= data_compute && act_data_ready === false.B) { - val data = io.sramReadResp(op2_bank).bits.data - for (i <- 0 until 16) { - act_shift_reg(act_reg_ptr)(i) := data((i + 1) * 8 - 1, i * 8)(6, 0) - } - act_reg_ptr := act_reg_ptr + 1.U - } - when(act_reg_ptr === 16.U && state =/= data_compute) { - act_data_ready := true.B - } - val weight_reg = Reg(Vec(16, UInt(7.W))) - - when(io.sramReadResp(op1_bank).valid && !io.is_matmul_ws) { - val data = io.sramReadResp(op1_bank).bits.data - for (i <- 0 until 16) { - weight_reg(i) := data((i + 1) * 8 - 1, i * 8)(6, 0) - } - } - - // New registers for weight and activation counting - - // Save 64 4x32 registers for output - val output_buffer = Reg(Vec(64, Vec(4, UInt(32.W)))) - // Save parallelogram output - val output_buffer_parallelogram = Reg(Vec(32, Vec(16, UInt(32.W)))) - val output_ptr = RegInit(0.U(5.W)) - val output_ready = RegInit(false.B) - - // New output data processing logic - // Extended to 7 bits to support 64 cycles - val write_cycles = RegInit(0.U(7.W)) - val writing_output = RegInit(false.B) - - val wr_bank_addr_base = Reg(UInt(io.lu_ex_i.bits.wr_bank_addr.getWidth.W)) - val addr_base_captured = RegInit(false.B) - - when(io.lu_ex_i.valid && !addr_base_captured) { - wr_bank_addr_base := io.lu_ex_i.bits.wr_bank_addr - addr_base_captured := true.B - weight_expreg := io.sramReadResp(op1_bank).bits.data(127, 96) - act_expreg := io.sramReadResp(op2_bank).bits.data(127, 96) - } - val result_exp = weight_expreg + act_expreg - - // PE array default value assignment - pe_array.io.in_last := VecInit(Seq.fill(16)(false.B)) - pe_array.io.in_id := DontCare - pe_array.io.in_a := DontCare - pe_array.io.in_d := DontCare - pe_array.io.in_b := VecInit(Seq.fill(16)(0.U)) - pe_array.io.in_control.foreach(_.propagate := 0.U) - pe_array.io.in_valid := VecInit(Seq.fill(16)(false.B)) - - // Default SRAM write port assignment - for (i <- 0 until parameter.numBanks) { - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(false.B)) - } - - // Start writing to SRAM when output is ready - when(output_ready && !writing_output) { - writing_output := true.B - write_cycles := 0.U - } - - when(writing_output) { - when(write_cycles < 16.U) { - // Concatenate 4x32-bit data into 128-bit wide data and write to SRAM - for (i <- 0 until parameter.numBanks / 2) { - when((wr_bank_addr_base + write_cycles)(0) === 0.U) { - io.accWrite(i).req.valid := true.B - io.accWrite(i).req.bits.addr := wr_bank_addr_base + (write_cycles >> 1.U) - val idx = (write_cycles * 4.U + i.U)(5, 0) // 6 bits for 64 elements - io.accWrite(i).req.bits.data := Cat( - output_buffer(idx)(3), - output_buffer(idx)(2), - output_buffer(idx)(1), - output_buffer(idx)(0) - ) - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) - }.otherwise { - io.accWrite(i + parameter.numBanks / 2).req.valid := true.B - io.accWrite(i + parameter.numBanks / 2).req.bits.addr := wr_bank_addr_base + (write_cycles >> 1.U) - val idx = (write_cycles * 4.U + i.U)(5, 0) // 6 bits for 64 elements - io.accWrite(i + parameter.numBanks / 2).req.bits.data := Cat( - output_buffer(idx)(3), - output_buffer(idx)(2), - output_buffer(idx)(1), - output_buffer(idx)(0) - ) - io.accWrite(i + parameter.numBanks / 2).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(true.B)) - } - } - write_cycles := write_cycles + 1.U - }.otherwise { - // Write completed - writing_output := false.B - output_ready := false.B - addr_base_captured := false.B - io.cmdResp.bits.rob_id := io.lu_ex_i.bits.rob_id - io.cmdResp.valid := true.B - } - } - - io.lu_ex_i.ready := true.B - - switch(state) { - is(idle) { - when(io.lu_ex_i.valid && !io.is_matmul_ws) { - // Start weight loading - weight_cycles := 0.U - state := weight_load - }.elsewhen(io.is_matmul_ws && act_data_ready) { - state := data_compute - act_cycles := 0.U - } - } - is(weight_load) { - // Load 16 cycles of weights - when(weight_cycles < 16.U) { - pe_array.io.in_d := weight_reg - pe_array.io.in_control.foreach(_.propagate := 1.U) - pe_array.io.in_valid.foreach(_ := true.B) - weight_cycles := weight_cycles + 1.U - }.otherwise { - // Weight loading completed, wait for activation data to be ready then enter computation - when(act_data_ready) { - act_cycles := 0.U - state := data_compute - } - } - } - is(data_compute) { - act_cycles := act_cycles + 1.U - // In computation phase, start parallelogram input mode for shift registers - when(act_cycles < 31.U) { - // Each cycle enables more rows for shifting row by row - for (col <- 0 until 16) { - when(col.U <= act_cycles && col.U < 16.U) { - col_enable(col) := true.B - }.otherwise { - col_enable(col) := false.B - } - } - - // Shift register operation: enabled rows shift right - for (col <- 0 until 16) { - when(col_enable(col)) { - for (row <- 0 until 15) { - act_shift_reg(row)(col) := act_shift_reg(row + 1)(col) - } - // Pad left with 0 (because in computation phase, no new data is input) - act_shift_reg(15)(col) := 0.U(7.W) - } - } - - // Input rightmost element of each row (column 15) to PE array - val current_input = WireDefault(VecInit(Seq.fill(16)(0.U(7.W)))) - for (col <- 0 until 16) { - when(col_enable(col)) { - current_input(col) := act_shift_reg(0)(col) - }.otherwise { - current_input(col) := 0.U(7.W) - } - } - pe_array.io.in_a := current_input - pe_array.io.in_b.foreach(_ := 0.U) - } - // Start receiving output from cycle 16, end at cycle 47 - - when(act_cycles > 16.U && act_cycles <= 48.U) { - output_buffer_parallelogram(output_ptr) := pe_array.io.out_b - output_ptr := output_ptr + 1.U - } - - // After cycle 47, convert parallelogram output to 64 4x32 registers - when(act_cycles === 49.U) { - output_ready := true.B - // Convert parallelogram output to 64 4x32 registers, organized in row-major order - for (row <- 0 until 16) { - for (col <- 0 until 16) { - val src_row = row + col - // Every 4 columns form one register group - val buffer_index = row * 4 + (col >> 2) - // Position within 4-element group - val element_index = col & 0x3 - if (src_row < 32) { - output_buffer(buffer_index)(element_index) := output_buffer_parallelogram(src_row)(col) - } else { - output_buffer(buffer_index)(element_index) := 0.U(32.W) - } - } - } - } - - // Reset data ready flag - when(act_cycles === 50.U) { - act_data_ready := false.B - act_reg_ptr := 0.U - output_ptr := 0.U - // Reset all row enable signals - col_enable := VecInit(Seq.fill(16)(false.B)) - state := idle - } - } - } - - io.sramReadResp.foreach { resp => - resp.ready := state =/= idle - } -} diff --git a/arch/src/main/scala/prototype/matrix/bbfp_load.scala b/arch/src/main/scala/prototype/matrix/bbfp_load.scala deleted file mode 100644 index d0938859..00000000 --- a/arch/src/main/scala/prototype/matrix/bbfp_load.scala +++ /dev/null @@ -1,69 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.matrix._ -import framework.memdomain.backend.banks.SramReadReq -import examples.toy.balldomain.BallDomainParam - -@instantiable -class BBFP_LoadUnit(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val rob_id_width = log2Up(parameter.rob_entries) - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - val sramReadReq = Vec(parameter.numBanks, Decoupled(new SramReadReq(parameter.bankEntries))) - val id_lu_i = Flipped(Decoupled(new id_lu_req(parameter))) - val lu_ex_o = Decoupled(new lu_ex_req(parameter)) - }) - - val op1_bank = io.id_lu_i.bits.op1_bank - val op1_bank_addr = io.id_lu_i.bits.op1_bank_addr - val op2_bank = io.id_lu_i.bits.op2_bank - val op2_bank_addr = io.id_lu_i.bits.op2_bank_addr - val wr_bank = io.id_lu_i.bits.wr_bank - val wr_bank_addr = io.id_lu_i.bits.wr_bank_addr - - // Default assignment for each bank read request - for (i <- 0 until parameter.numBanks) { - io.sramReadReq(i).valid := false.B - io.sramReadReq(i).bits.fromDMA := false.B - io.sramReadReq(i).bits.addr := 0.U - } - - // Generate SRAM read request based on ID_LU input - when(io.id_lu_i.valid) { - io.sramReadReq(op1_bank).valid := true.B - io.sramReadReq(op1_bank).bits.fromDMA := false.B - io.sramReadReq(op1_bank).bits.addr := op1_bank_addr - - io.sramReadReq(op2_bank).valid := true.B - io.sramReadReq(op2_bank).bits.fromDMA := false.B - io.sramReadReq(op2_bank).bits.addr := op2_bank_addr - } - - // Generate LU_EX request - io.lu_ex_o.valid := io.id_lu_i.valid - io.lu_ex_o.bits.op1_bank := op1_bank - io.lu_ex_o.bits.op2_bank := op2_bank - io.lu_ex_o.bits.wr_bank := wr_bank - io.lu_ex_o.bits.wr_bank_addr := wr_bank_addr - io.lu_ex_o.bits.opcode := io.id_lu_i.bits.opcode - io.lu_ex_o.bits.iter := io.id_lu_i.bits.iter - io.lu_ex_o.bits.thread_id := io.id_lu_i.bits.thread_id - io.lu_ex_o.bits.rob_id := io.id_lu_i.bits.rob_id - - io.id_lu_i.ready := io.lu_ex_o.ready - -} diff --git a/arch/src/main/scala/prototype/matrix/bbfp_pe.scala b/arch/src/main/scala/prototype/matrix/bbfp_pe.scala deleted file mode 100644 index c1809ab7..00000000 --- a/arch/src/main/scala/prototype/matrix/bbfp_pe.scala +++ /dev/null @@ -1,403 +0,0 @@ -package prototype.matrix - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import prototype.matrix._ - -// PE control signal Bundle -class PEControl extends Bundle { - // Propagation control - val propagate = UInt(1.W) -} - -class MacUnit extends Module { - - val io = IO(new Bundle { - // Unsigned input: [6]=sign, [5]=flag, [4:0]=value - val in_a = Input(UInt(7.W)) - // Unsigned input: [6]=sign, [5]=flag, [4:0]=value - val in_b = Input(UInt(7.W)) - // Unsigned input: [31]=sign, [30:0]=value - val in_c = Input(UInt(32.W)) - // Signed output - val out_d = Output(UInt(32.W)) - }) - - // Extract sign bits - val sign_a = io.in_a(6) - val sign_b = io.in_b(6) - val sign_c = io.in_c(31) - - // Extract flag bits - val flag_a = io.in_a(5) - val flag_b = io.in_b(5) - - // Extract value parts - // 5-bit value - val value_a = io.in_a(4, 0) - // 5-bit value - val value_b = io.in_b(4, 0) - // 31-bit value - val value_c = io.in_c(30, 0) - - // val extended_a = value_a.asUInt().pad(7) // Extend to 7 bits - // val extended_b = value_b.asUInt().pad(7) // Extend to 7 bits - - // Determine left shift based on flag bit - val shifted_a = Mux(flag_a === 1.U, value_a << 2, value_a) - val shifted_b = Mux(flag_b === 1.U, value_b << 2, value_b) - - // Convert value to signed number, considering sign bit - // First extend bit width to avoid overflow, then determine sign based on sign bit - val a_signed = Mux(sign_a === 1.U, -(shifted_a.zext), shifted_a.zext).asSInt - - val b_signed = Mux(sign_b === 1.U, -(shifted_b.zext), shifted_b.zext).asSInt - - val c_signed = Mux(sign_c === 1.U, -(value_c.zext), value_c.zext).asSInt - - // Perform MAC operation: a * b + c - val result = a_signed * b_signed + c_signed - - // Output result - io.out_d := result.asUInt -} - -// BBFP PE unit (only supports Weight Stationary) -class BBFP_PE_WS(max_simultaneous_matmuls: Int = 16) extends Module { - - val io = IO(new Bundle { - // Data input/output - // Input activation value - val in_a = Input(UInt(7.W)) - // Input partial sum - val in_b = Input(UInt(32.W)) - // Input weight - val in_d = Input(UInt(7.W)) - // Output activation value - val out_a = Output(UInt(7.W)) - // Output partial sum - val out_b = Output(UInt(32.W)) - // Output weight - val out_d = Output(UInt(7.W)) - // Control signals - val in_control = Input(new PEControl()) - val out_control = Output(new PEControl()) - - // ID and valid signals - val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) - val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) - - val in_last = Input(Bool()) - val out_last = Output(Bool()) - - val in_valid = Input(Bool()) - val out_valid = Output(Bool()) - }) - - // Instantiate MAC unit - val mac_unit = Module(new MacUnit) - - // Input signals - val a = io.in_a - val b = io.in_b - val d = io.in_d - val prop = io.in_control.propagate - // val shift = io.in_control.shift // Removed - val id = io.in_id - val last = io.in_last - val valid = io.in_valid - - // Accumulation register - - val weight = Reg(UInt(7.W)) - // Pass-through signals - io.out_a := a - io.out_control.propagate := prop - io.out_id := id - io.out_last := last - io.out_valid := valid - - // MAC unit connections - mac_unit.io.in_a := a - mac_unit.io.in_b := d - - // Propagation control constant - val PROPAGATE = 1.U(1.W) - - // Default assignment - io.out_b := b - mac_unit.io.in_c := b - // Weight Stationary mode - when(prop === PROPAGATE) { - when(valid) { - weight := d - } - io.out_d := d - mac_unit.io.in_b := d - mac_unit.io.in_c := b - mac_unit.io.in_a := a - io.out_b := mac_unit.io.out_d - io.out_a := a - }.otherwise { - // Computation mode: output c2, use c1 as weight for computation - io.out_a := a - io.out_d := DontCare - mac_unit.io.in_b := weight - mac_unit.io.in_c := b - mac_unit.io.in_a := a - io.out_b := mac_unit.io.out_d - } - - // Do not update register when invalid - when(!valid) { - weight := weight - } -} - -class BBFP_PE_Array2x2 extends Module { - - val io = IO(new Bundle { - // Row input activation (horizontal propagation) - val in_a = Input(Vec(2, UInt(7.W))) - // Column input weight (vertical propagation) - val in_d = Input(Vec(2, UInt(7.W))) - // Column input partial sum (vertical propagation) - val in_b = Input(Vec(2, UInt(32.W))) - // Column input control signal (follows weight vertical propagation) - val in_control = Input(Vec(2, new PEControl())) - val in_id = Input(Vec(2, UInt(1.W))) - val in_last = Input(Vec(2, Bool())) - val in_valid = Input(Vec(2, Bool())) - - // Output - // Bottom row output partial sum - val out_b = Output(Vec(2, UInt(32.W))) - // Right column output activation - val out_a = Output(Vec(2, UInt(7.W))) - // Bottom row output weight - val out_d = Output(Vec(2, UInt(7.W))) - }) - - // 2x2 PE array - val pes = Seq.fill(2, 2)(Module(new BBFP_PE_WS())) - - // Registers connecting between PEs - // Activation horizontal propagation register (row direction, left->right) - val reg_a_h = Seq.fill(2)(Reg(UInt(7.W))) // pes(i)(0) -> pes(i)(1) - - // Weight vertical propagation register (column direction, top->bottom) - val reg_d_v = Seq.fill(2)(Reg(UInt(7.W))) // pes(0)(j) -> pes(1)(j) - - // Partial sum vertical propagation register (column direction, top->bottom) - val reg_b_v = Seq.fill(2)(Reg(UInt(32.W))) // pes(0)(j) -> pes(1)(j) - - // Control signal vertical propagation register (column direction, top->bottom) - val reg_ctrl_v = Seq.fill(2)(Wire(new PEControl)) - val reg_id_v = Seq.fill(2)(Wire(UInt(1.W))) - val reg_last_v = Seq.fill(2)(Wire(Bool())) - val reg_valid_v = Seq.fill(2)(Wire(Bool())) - - // ================ PE(0,0) ================ - // Row 0 activation input - pes(0)(0).io.in_a := io.in_a(0) - // Column 0 weight input - pes(0)(0).io.in_d := io.in_d(0) - // Column 0 partial sum input - pes(0)(0).io.in_b := io.in_b(0) - // Column 0 control signal input - pes(0)(0).io.in_control := io.in_control(0) - pes(0)(0).io.in_id := io.in_id(0) - pes(0)(0).io.in_last := io.in_last(0) - pes(0)(0).io.in_valid := io.in_valid(0) - - // ================ PE(0,1) ================ - // Activation propagates horizontally from PE(0,0) (through register) - reg_a_h(0) := pes(0)(0).io.out_a - pes(0)(1).io.in_a := reg_a_h(0) - // Weight, partial sum, control signal input from external column 1 - pes(0)(1).io.in_d := io.in_d(1) - pes(0)(1).io.in_b := io.in_b(1) - pes(0)(1).io.in_control := io.in_control(1) - pes(0)(1).io.in_id := io.in_id(1) - pes(0)(1).io.in_last := io.in_last(1) - pes(0)(1).io.in_valid := io.in_valid(1) - - // ================ PE(1,0) ================ - // Activation input from external row 1 - pes(1)(0).io.in_a := io.in_a(1) - // Weight, partial sum, control signal propagate vertically from PE(0,0) (through register) - reg_d_v(0) := pes(0)(0).io.out_d - reg_b_v(0) := pes(0)(0).io.out_b - reg_ctrl_v(0) := pes(0)(0).io.out_control - reg_id_v(0) := pes(0)(0).io.out_id - reg_last_v(0) := pes(0)(0).io.out_last - reg_valid_v(0) := pes(0)(0).io.out_valid - - pes(1)(0).io.in_d := reg_d_v(0) - pes(1)(0).io.in_b := reg_b_v(0) - pes(1)(0).io.in_control := reg_ctrl_v(0) - pes(1)(0).io.in_id := reg_id_v(0) - pes(1)(0).io.in_last := reg_last_v(0) - pes(1)(0).io.in_valid := reg_valid_v(0) - - // ================ PE(1,1) ================ - // Activation propagates horizontally from PE(1,0) (through register) - reg_a_h(1) := pes(1)(0).io.out_a - pes(1)(1).io.in_a := reg_a_h(1) - // Weight, partial sum, control signal propagate vertically from PE(0,1) (through register) - reg_d_v(1) := pes(0)(1).io.out_d - reg_b_v(1) := pes(0)(1).io.out_b - reg_ctrl_v(1) := pes(0)(1).io.out_control - reg_id_v(1) := pes(0)(1).io.out_id - reg_last_v(1) := pes(0)(1).io.out_last - reg_valid_v(1) := pes(0)(1).io.out_valid - - pes(1)(1).io.in_d := reg_d_v(1) - pes(1)(1).io.in_b := reg_b_v(1) - pes(1)(1).io.in_control := reg_ctrl_v(1) - pes(1)(1).io.in_id := reg_id_v(1) - pes(1)(1).io.in_last := reg_last_v(1) - pes(1)(1).io.in_valid := reg_valid_v(1) - - // ================ Output connections ================ - // Add registers for outputs - val out_b_reg = Reg(Vec(2, UInt(32.W))) - val out_a_reg = Reg(Vec(2, UInt(7.W))) - val out_d_reg = Reg(Vec(2, UInt(7.W))) - - out_b_reg(0) := pes(1)(0).io.out_b - out_b_reg(1) := pes(1)(1).io.out_b - out_a_reg(0) := pes(0)(1).io.out_a - out_a_reg(1) := pes(1)(1).io.out_a - out_d_reg(0) := pes(1)(0).io.out_d - out_d_reg(1) := pes(1)(1).io.out_d - - io.out_b := out_b_reg - io.out_a := out_a_reg - io.out_d := out_d_reg -} - -class BBFP_PE_Array16x16 extends Module { - - val io = IO(new Bundle { - // Row input activation (horizontal propagation) - 16 rows - val in_a = Input(Vec(16, UInt(7.W))) - // Column input weight (vertical propagation) - 16 columns - val in_d = Input(Vec(16, UInt(7.W))) - // Column input partial sum (vertical propagation) - 16 columns - val in_b = Input(Vec(16, UInt(32.W))) - // Column input control signal (follows weight vertical propagation) - 16 columns - val in_control = Input(Vec(16, new PEControl())) - val in_id = Input(Vec(16, UInt(1.W))) - val in_last = Input(Vec(16, Bool())) - val in_valid = Input(Vec(16, Bool())) - - // Output - // Bottom row output partial sum - val out_b = Output(Vec(16, UInt(32.W))) - // Right column output activation - val out_a = Output(Vec(16, UInt(7.W))) - // Bottom row output weight - val out_d = Output(Vec(16, UInt(7.W))) - }) - - // 16x16 PE array - val pes = Seq.fill(16, 16)(Module(new BBFP_PE_WS())) - - // Registers connecting between PEs - // Activation horizontal propagation register (row direction, left->right) - val reg_a_h = Seq.fill(16, 15)(Reg(UInt(7.W))) // pes(i)(j) -> pes(i)(j+1) - - // Weight vertical propagation register (column direction, top->bottom) - val reg_d_v = Seq.fill(15, 16)(Reg(UInt(7.W))) // pes(i)(j) -> pes(i+1)(j) - - // Partial sum vertical propagation register (column direction, top->bottom) - val reg_b_v = Seq.fill(15, 16)(Reg(UInt(32.W))) // pes(i)(j) -> pes(i+1)(j) - - // Control signal vertical propagation register (column direction, top->bottom) - val reg_ctrl_v = Seq.fill(15, 16)(Wire(new PEControl)) - val reg_id_v = Seq.fill(15, 16)(Wire(UInt(1.W))) - val reg_last_v = Seq.fill(15, 16)(Wire(Bool())) - val reg_valid_v = Seq.fill(15, 16)(Wire(Bool())) - - // ================ PE array connections ================ - for (i <- 0 until 16) { - for (j <- 0 until 16) { - // Activation input connection (horizontal propagation) - if (j == 0) { - // First column: input from external - pes(i)(j).io.in_a := io.in_a(i) - } else { - // Other columns: propagate from left PE through register - reg_a_h(i)(j - 1) := pes(i)(j - 1).io.out_a - pes(i)(j).io.in_a := reg_a_h(i)(j - 1) - } - - // Weight input connection (vertical propagation) - if (i == 0) { - // First row: input from external - pes(i)(j).io.in_d := io.in_d(j) - } else { - // Other rows: propagate from top PE through register - reg_d_v(i - 1)(j) := pes(i - 1)(j).io.out_d - pes(i)(j).io.in_d := reg_d_v(i - 1)(j) - } - - // Partial sum input connection (vertical propagation) - if (i == 0) { - // First row: input from external - pes(i)(j).io.in_b := io.in_b(j) - } else { - // Other rows: propagate from top PE through register - reg_b_v(i - 1)(j) := pes(i - 1)(j).io.out_b - pes(i)(j).io.in_b := reg_b_v(i - 1)(j) - } - - // Control signal input connection (vertical propagation) - if (i == 0) { - // First row: input from external - pes(i)(j).io.in_control := io.in_control(j) - pes(i)(j).io.in_id := io.in_id(j) - pes(i)(j).io.in_last := io.in_last(j) - pes(i)(j).io.in_valid := io.in_valid(j) - } else { - // Other rows: propagate from top PE through register - reg_ctrl_v(i - 1)(j) := pes(i - 1)(j).io.out_control - reg_id_v(i - 1)(j) := pes(i - 1)(j).io.out_id - reg_last_v(i - 1)(j) := pes(i - 1)(j).io.out_last - reg_valid_v(i - 1)(j) := pes(i - 1)(j).io.out_valid - - pes(i)(j).io.in_control := reg_ctrl_v(i - 1)(j) - pes(i)(j).io.in_id := reg_id_v(i - 1)(j) - pes(i)(j).io.in_last := reg_last_v(i - 1)(j) - pes(i)(j).io.in_valid := reg_valid_v(i - 1)(j) - } - } - } - - // ================ Output connections ================ - // Add registers for outputs - val out_b_reg = Reg(Vec(16, UInt(32.W))) - val out_a_reg = Reg(Vec(16, UInt(7.W))) - val out_d_reg = Reg(Vec(16, UInt(7.W))) - - // Bottom row output partial sum (all columns of row 15) - for (j <- 0 until 16) { - out_b_reg(j) := pes(15)(j).io.out_b - } - - // Right column output activation (row 15 of all rows) - for (i <- 0 until 16) { - out_a_reg(i) := pes(i)(15).io.out_a - } - - // Bottom row output weight (all columns of row 15) - for (j <- 0 until 16) { - out_d_reg(j) := pes(15)(j).io.out_d - } - - io.out_b := out_b_reg - io.out_a := out_a_reg - io.out_d := out_d_reg -} diff --git a/arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala b/arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala deleted file mode 100644 index 7a746003..00000000 --- a/arch/src/main/scala/prototype/matrix/configs/MatrixConfig.scala +++ /dev/null @@ -1,62 +0,0 @@ -package prototype.matrix.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object MatrixConfig { - implicit def rw: upickle.default.ReadWriter[MatrixConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): MatrixConfig = { - MatrixConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): MatrixConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[MatrixConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: MatrixConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class MatrixConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - // Derived parameters - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""MatrixConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/matrix/configs/default.json b/arch/src/main/scala/prototype/matrix/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/matrix/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala b/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala deleted file mode 100644 index b2a46402..00000000 --- a/arch/src/main/scala/prototype/nagisa/matmul/Macro.scala +++ /dev/null @@ -1,337 +0,0 @@ -package prototype.nagisa.matmul - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status - -class PiDRAMmarcoBlackBox extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val clock = Input(Clock()) - val reset = Input(Bool()) - - // Control interface - val start = Input(Bool()) - val done = Output(Bool()) - - // Data addresses - val op1_addr = Input(UInt(32.W)) - val op2_addr = Input(UInt(32.W)) - val result_addr = Input(UInt(32.W)) - - // Computation parameters - val rows = Input(UInt(16.W)) - val cols = Input(UInt(16.W)) - val op_type = Input(UInt(4.W)) // 0: matmul, 1: add, 2: mul, etc. - - // Data width - val data_width = Input(UInt(8.W)) - }) - - setInline( - "PiDRAMmarcoBlackBox.v", - s""" - |module PiDRAMmarcoBlackBox( - | input clock, - | input reset, - | input start, - | output reg done, - | input [31:0] op1_addr, - | input [31:0] op2_addr, - | input [31:0] result_addr, - | input [15:0] rows, - | input [15:0] cols, - | input [3:0] op_type, - | input [7:0] data_width - |); - | - | // State machine for marco computation - | reg [2:0] state; - | localparam IDLE = 3'b000; - | localparam LOAD = 3'b001; - | localparam COMPUTE = 3'b010; - | localparam STORE = 3'b011; - | localparam DONE = 3'b100; - | - | // Cycle counter for computation - | reg [31:0] cycle_count; - | reg [31:0] total_cycles; - | reg running; - | - | // Compute total cycles based on operation type and size - | always @(*) begin - | case(op_type) - | 4'b0000: // Matrix multiplication: rows * cols * cols - | total_cycles = rows * cols * cols; - | 4'b0001: // Element-wise addition: rows * cols - | total_cycles = rows * cols; - | 4'b0010: // Element-wise multiplication: rows * cols - | total_cycles = rows * cols; - | default: - | total_cycles = rows * cols; - | endcase - | end - | - | always @(posedge clock) begin - | if (reset) begin - | done <= 1'b0; - | state <= IDLE; - | cycle_count <= 32'b0; - | running <= 1'b0; - | end else begin - | case(state) - | IDLE: begin - | done <= 1'b0; - | cycle_count <= 32'b0; - | running <= 1'b0; - | if (start) begin - | state <= LOAD; - | running <= 1'b1; - | end - | end - | LOAD: begin - | // Load phase: simulate data loading from memory - | // In real marco, this would be handled by the memory controller - | state <= COMPUTE; - | end - | COMPUTE: begin - | // Compute phase: perform marco computation - | // This simulates the computation cycles in marco - | if (cycle_count >= total_cycles) begin - | state <= STORE; - | cycle_count <= 32'b0; - | end else begin - | cycle_count <= cycle_count + 1; - | end - | end - | STORE: begin - | // Store phase: write results back - | state <= DONE; - | end - | DONE: begin - | done <= 1'b1; - | running <= 1'b0; - | if (!start) begin - | state <= IDLE; - | end - | end - | default: begin - | state <= IDLE; - | end - | endcase - | end - | end - | - |endmodule - """.stripMargin - ) -} - -@instantiable -class marco(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val accWidth = 32 - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // Command interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(parameter))) - val cmdResp = Decoupled(new BallRsComplete(parameter)) - - // Scratchpad SRAM read/write interface - val sramRead = Vec(parameter.numBanks, Flipped(new SramReadIO(parameter.bankEntries, bankWidth))) - val sramWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, bankWidth, parameter.bankMaskLen))) - - // Accumulator write interface (unified bank now) - val accWrite = - Vec(parameter.numBanks, Flipped(new SramWriteIO(parameter.bankEntries, accWidth, parameter.bankMaskLen))) - - // Status output - val status = new Status - }) - - // State machine - val idle :: sLoadOp1 :: sLoadOp2 :: sCompute :: sWrite :: complete :: Nil = Enum(6) - val state = RegInit(idle) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val op1_addr_reg = RegInit(0.U(10.W)) - val op1_bank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) - val op2_addr_reg = RegInit(0.U(10.W)) - val op2_bank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) - val result_addr_reg = RegInit(0.U(10.W)) - val result_bank_reg = RegInit(0.U(log2Up(parameter.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - - // marco parameters from special field (40 bits total) - // special[15:0] = rows (16 bits) - // special[31:16] = cols (16 bits) - // special[35:32] = op_type (4 bits): 0=matmul, 1=add, 2=mul - val rows_reg = RegInit(0.U(16.W)) - val cols_reg = RegInit(0.U(16.W)) - val op_type_reg = RegInit(0.U(4.W)) - - // Counters - val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val computeCounter = RegInit(0.U(32.W)) - - // PiDRAM marco BlackBox instance - val pidrammarco = Module(new PiDRAMmarcoBlackBox) - pidrammarco.io.clock := clock - pidrammarco.io.reset := reset.asBool - - // Default SRAM assignments - for (i <- 0 until parameter.numBanks) { - io.sramRead(i).req.valid := false.B - io.sramRead(i).req.bits.addr := 0.U - io.sramRead(i).req.bits.fromDMA := false.B - io.sramRead(i).resp.ready := false.B - - io.sramWrite(i).req.valid := false.B - io.sramWrite(i).req.bits.addr := 0.U - io.sramWrite(i).req.bits.data := 0.U - io.sramWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // Default accumulator assignments - for (i <- 0 until parameter.numBanks) { - io.accWrite(i).req.valid := false.B - io.accWrite(i).req.bits.addr := 0.U - io.accWrite(i).req.bits.data := 0.U - io.accWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // Command interface defaults - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg - - // PiDRAM marco interface defaults - pidrammarco.io.start := false.B - pidrammarco.io.op1_addr := op1_addr_reg - pidrammarco.io.op2_addr := op2_addr_reg - pidrammarco.io.result_addr := result_addr_reg - pidrammarco.io.rows := rows_reg - pidrammarco.io.cols := cols_reg - pidrammarco.io.op_type := op_type_reg - pidrammarco.io.data_width := inputWidth.U - - // Status output - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sLoadOp1) || (state === sLoadOp2) - io.status.running := (state === sCompute) || (state === sWrite) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := computeCounter - - // State machine - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - state := sLoadOp1 - readCounter := 0.U - writeCounter := 0.U - computeCounter := 0.U - - robid_reg := io.cmdReq.bits.rob_id - op1_addr_reg := 0.U // New ISA: all operations start from row 0 - op1_bank_reg := io.cmdReq.bits.cmd.op1_bank - op2_addr_reg := 0.U // New ISA: all operations start from row 0 - op2_bank_reg := io.cmdReq.bits.cmd.op2_bank - result_addr_reg := 0.U // New ISA: all operations start from row 0 - result_bank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter - - // Extract marco parameters from special field (40 bits) - // special[15:0] = rows, special[31:16] = cols, special[35:32] = op_type - rows_reg := io.cmdReq.bits.cmd.special(15, 0) - cols_reg := io.cmdReq.bits.cmd.special(31, 16) - op_type_reg := io.cmdReq.bits.cmd.special(35, 32) - } - } - - is(sLoadOp1) { - // Load operand 1 (simplified: load one tile) - when(readCounter < iter_reg) { - io.sramRead(op1_bank_reg).req.valid := true.B - io.sramRead(op1_bank_reg).req.bits.addr := op1_addr_reg + readCounter - io.sramRead(op1_bank_reg).req.bits.fromDMA := false.B - - when(io.sramRead(op1_bank_reg).resp.valid) { - io.sramRead(op1_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U - } - }.otherwise { - state := sLoadOp2 - readCounter := 0.U - } - } - - is(sLoadOp2) { - // Load operand 2 (simplified: load one tile) - when(readCounter < iter_reg) { - io.sramRead(op2_bank_reg).req.valid := true.B - io.sramRead(op2_bank_reg).req.bits.addr := op2_addr_reg + readCounter - io.sramRead(op2_bank_reg).req.bits.fromDMA := false.B - - when(io.sramRead(op2_bank_reg).resp.valid) { - io.sramRead(op2_bank_reg).resp.ready := true.B - readCounter := readCounter + 1.U - } - }.otherwise { - state := sCompute - readCounter := 0.U - pidrammarco.io.start := true.B - } - } - - is(sCompute) { - // Wait for PiDRAM marco to complete - when(pidrammarco.io.done) { - state := sWrite - writeCounter := 0.U - }.otherwise { - computeCounter := computeCounter + 1.U - } - } - - is(sWrite) { - // Write result (simplified: write one tile) - when(writeCounter < iter_reg) { - io.sramWrite(result_bank_reg).req.valid := true.B - io.sramWrite(result_bank_reg).req.bits.addr := result_addr_reg + writeCounter - // Simplified: write zeros as placeholder (actual output would come from PiDRAM marco) - io.sramWrite(result_bank_reg).req.bits.data := 0.U - io.sramWrite(result_bank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(1.U(1.W))) - - when(io.sramWrite(result_bank_reg).req.ready) { - writeCounter := writeCounter + 1.U - } - }.otherwise { - state := complete - } - } - - is(complete) { - io.cmdResp.valid := true.B - when(io.cmdResp.ready) { - state := idle - } - } - } -} diff --git a/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala b/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala deleted file mode 100644 index e89ec1a4..00000000 --- a/arch/src/main/scala/prototype/nagisa/matmul/MacroMatmulBall.scala +++ /dev/null @@ -1,53 +0,0 @@ -package prototype.nagisa.matmul - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.nagisa.matmul.marco - -/** - * marcoMatmulBall - A Compute-in-Memory Ball that complies with the Blink protocol - * Behavior: Read operands from Scratchpad, perform marco computation (inspired by PiDRAM), - * then write results back to Scratchpad. - */ -@instantiable -class marcoMatmulBall(parameter: BallDomainParam, id: Int)(implicit p: Parameters) extends Module with BallRegist { - @public - val io = IO(new Blink(parameter, parameter.bankEntries, parameter.bankWidth, parameter.bankMaskLen)) - val ballId = id.U - - // Satisfy BallRegist requirements - def Blink: Blink = io - - // Instantiate marco computation unit - private val marcoUnit: Instance[marco] = Instantiate(new marco(parameter)) - - // Connect command interface - marcoUnit.io.cmdReq <> io.cmdReq - marcoUnit.io.cmdResp <> io.cmdResp - - // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { - marcoUnit.io.sramRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - marcoUnit.io.sramWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // marcoMatmulBall uses overwrite mode for scratchpad - - // Accumulator write (for partial sums) - use accumulate mode - // Note: marco may need to write to accumulator banks with accumulate mode - // For now, assuming all writes use overwrite mode, but accumulator writes should use accumulate - // This needs to be determined based on marco unit's actual behavior - } - - // Pass through status signals - io.status <> marcoUnit.io.status - - override lazy val desiredName: String = "marcoMatmulBall" -} diff --git a/arch/src/main/scala/prototype/nnlut/NNLut.scala b/arch/src/main/scala/prototype/nnlut/NNLut.scala deleted file mode 100644 index c0f88bca..00000000 --- a/arch/src/main/scala/prototype/nnlut/NNLut.scala +++ /dev/null @@ -1,213 +0,0 @@ -package prototype.nnlut - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status -import prototype.nnlut.configs.NNLutConfig - -/** - * NNLut - Neural Network Look-Up Table unit - * Simple implementation: read data from scratchpad, lookup in LUT, write back - */ -@instantiable -class NNLut(val parameter: NNLutConfig)(implicit p: Parameters) extends Module with SerializableModule[NNLutConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) - - // Connect to unified bank read/write interface - val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) - val bankWrite = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - - // Status output - val status = new Status - }) - - // State definitions - val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) - - // Store a InputNum x InputNum tile - val regArray = RegInit( - VecInit(Seq.fill(InputNum)( - VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - )) - ) - - // Counters - val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - val cycle_reg = RegInit(0.U(6.W)) - val iterCnt = RegInit(0.U(32.W)) - - // Precompute write data - val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) - - // Simple LUT: 256 entries for 8-bit input - // This is a simple example LUT, can be replaced with actual NN-LUT values - val LUT_SIZE = 256 - - val lut = VecInit(Seq.tabulate(LUT_SIZE) { i => - // Simple example: identity function with saturation - // In real NN-LUT, this would contain pre-computed activation function values - val input = i.asSInt - val output = Mux(input < -128.S, -128.S, Mux(input > 127.S, 127.S, input)) - output.asUInt - }) - - // SRAM default assignment - for (i <- 0 until ballParam.numBanks) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := false.B - - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg - - // State machine - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U - writeCounter := 0.U - - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U // New ISA: all operations start from row 0 - wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := 0.U // New ISA: all operations start from row 0 - rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U - } - - when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U - writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + InputNum.U - raddr_reg := raddr_reg + InputNum.U - cycle_reg := cycle_reg - 1.U - } - } - - is(sRead) { - when(readCounter < InputNum.U) { - // Issue read request - readCounter := readCounter + 1.U - io.bankRead(rbank_reg).req.valid := true.B - io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - } - - // Receive response and perform LUT lookup - io.bankRead(rbank_reg).resp.ready := true.B - when(io.bankRead(rbank_reg).resp.fire) { - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - val raw = io.bankRead(rbank_reg).resp.bits.data(hi, lo) - // Perform LUT lookup - // Convert signed value to unsigned index (0-255) - // Take lower 8 bits as unsigned index for LUT - val idx = raw(7, 0) // Use lower 8 bits as unsigned index - regArray(respCounter)(col) := lut(idx) - } - respCounter := respCounter + 1.U - } - - when(respCounter === InputNum.U) { - state := sWrite - // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) - // Set write mask (write all) - for (i <- 0 until parameter.bankMaskLen) { - writeMaskReg(i) := 1.U(1.W) - } - } - } - - is(sWrite) { - // Write back results - io.bankWrite(wbank_reg).req.valid := writeCounter < InputNum.U - io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.bankWrite(wbank_reg).req.bits.data := writeDataReg - io.bankWrite(wbank_reg).req.bits.mask := writeMaskReg - - when(writeCounter === (InputNum - 1).U) { - state := complete - }.otherwise { - writeCounter := writeCounter + 1.U - // Prepare next row's write data - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) - } - } - - is(complete) { - when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } - } - state := idle - } - } - - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < InputNum.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt - - when(reset.asBool) { - for (i <- 0 until InputNum) { - for (j <- 0 until InputNum) { - regArray(i)(j) := 0.U - } - } - writeDataReg := 0.U - for (i <- 0 until parameter.bankMaskLen) { - writeMaskReg(i) := 0.U - } - } -} diff --git a/arch/src/main/scala/prototype/nnlut/NNLutBall.scala b/arch/src/main/scala/prototype/nnlut/NNLutBall.scala deleted file mode 100644 index 1372d5c1..00000000 --- a/arch/src/main/scala/prototype/nnlut/NNLutBall.scala +++ /dev/null @@ -1,49 +0,0 @@ -package prototype.nnlut - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.nnlut.NNLut -import prototype.nnlut.configs.NNLutConfig - -/** - * NNLutBall - A Neural Network Look-Up Table computation Ball that complies with the Blink protocol. - * Behavior: Read data from Scratchpad, perform LUT lookup, then write back to Scratchpad. - */ -@instantiable -class NNLutBall(config: NNLutConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - // Satisfy BallRegist requirements - def Blink: Blink = io - - // Instantiate NNLut computation unit - private val nnlutUnit: Instance[NNLut] = Instantiate(new NNLut(config)) - - // Connect command interface - nnlutUnit.io.cmdReq <> io.cmdReq - nnlutUnit.io.cmdResp <> io.cmdResp - - // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { - nnlutUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - nnlutUnit.io.bankWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // NNLutBall uses overwrite mode - } - - // Pass through status signals - io.status <> nnlutUnit.io.status - - override lazy val desiredName: String = "NNLutBall" -} diff --git a/arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala b/arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala deleted file mode 100644 index e1f74ee8..00000000 --- a/arch/src/main/scala/prototype/nnlut/configs/NNLutConfig.scala +++ /dev/null @@ -1,61 +0,0 @@ -package prototype.nnlut.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object NNLutConfig { - implicit def rw: upickle.default.ReadWriter[NNLutConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): NNLutConfig = { - NNLutConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): NNLutConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[NNLutConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: NNLutConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class NNLutConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""NNLutConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/nnlut/configs/default.json b/arch/src/main/scala/prototype/nnlut/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/nnlut/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/relu/configs/ReluConfig.scala b/arch/src/main/scala/prototype/relu/configs/ReluConfig.scala deleted file mode 100644 index a09a1e12..00000000 --- a/arch/src/main/scala/prototype/relu/configs/ReluConfig.scala +++ /dev/null @@ -1,62 +0,0 @@ -package prototype.relu.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object ReluConfig { - implicit def rw: upickle.default.ReadWriter[ReluConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): ReluConfig = { - ReluConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): ReluConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[ReluConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: ReluConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class ReluConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - // Derived parameters - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""ReluConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/relu/configs/default.json b/arch/src/main/scala/prototype/relu/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/relu/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/transfer/README.md b/arch/src/main/scala/prototype/transfer/README.md deleted file mode 100644 index be885574..00000000 --- a/arch/src/main/scala/prototype/transfer/README.md +++ /dev/null @@ -1,206 +0,0 @@ -# Transfer Tile Data Mover Accelerator - -## Overview - -This directory implements Buckyball's tile-based Transfer accelerator, located at `arch/src/main/scala/prototype/transfer`. The module copies Scratchpad data by tiles (`veclane × veclane`) from a source bank/address to a destination bank/address, in a vectorized manner, and writes results back without any arithmetic modification. - -Core components: -- **Transfer.scala**: Transfer accelerator main implementation - -## Code Structure - -``` -transfer/ -└── Transfer.scala - Transfer accelerator implementation -``` - -### Module Responsibilities - -**Transfer.scala** (Accelerator implementation layer) -- Reads a `veclane × veclane` tile of data from a source Scratchpad bank/address -- Performs no element-wise computation (pure copy) -- Packs rows and writes back the same-sized tile with full mask to the destination bank/address -- Provides Ball domain command interface and returns completion response/status - -## Module Description - -### Transfer.scala - -**Main functionality**: - -Read input tile by tile (`veclane × veclane`) → Pack row data → Write output back row by row; supports `iter`-driven batch processing and pipelined workflow. - -**State machine definition**: - -```scala -val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) -val state = RegInit(idle) -``` - -**Key registers**: - -```scala -// Data cache: veclane × veclane, each element width is inputType.getWidth -val regArray = RegInit( - VecInit(Seq.fill(b.veclane)( - VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W))) - )) -) - -// Counters -val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) // Read request row count -val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) // Read response row count -val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) // Write-back row count - -// Instruction field registers -val robid_reg = RegInit(0.U(10.W)) // Command ROB ID -val waddr_reg = RegInit(0.U(10.W)) // Write-back start row address -val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) // Write-back target Scratchpad bank selection -val raddr_reg = RegInit(0.U(10.W)) // Read start row address -val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) // Read source Scratchpad bank selection -val iter_reg = RegInit(0.U(10.W)) // Processing row count/length specified in command -val cycle_reg = RegInit(0.U(6.W)) // Tile round count (derived from iter) -val iterCnt = RegInit(0.U(32.W)) // Completed batch count - -// Write-back data and mask -val spad_w = b.veclane * b.inputType.getWidth // Packed data width per row -val writeDataReg = Reg(UInt(spad_w.W)) // Packed data to write back per row -val writeMaskReg = Reg(Vec(b.spad_mask_len, UInt(1.W))) // Write-back mask vector -``` - -**Command parsing**: - -```scala -when(io.cmdReq.fire) { - // Enter read phase and initialize round counters - state := sRead - readCounter := 0.U // Clear read request row count - respCounter := 0.U // Clear read response row count - writeCounter := 0.U // Clear write-back row count - - // Record command identifier - robid_reg := io.cmdReq.bits.rob_id // ROB ID (for completion response matching) - - // Output (write-back) target address: use wr_* fields - waddr_reg := io.cmdReq.bits.cmd.wr_bank_addr // Write-back start row address - wbank_reg := io.cmdReq.bits.cmd.wr_bank // Write-back target bank - - // Input (read) source address: use op1_* fields - raddr_reg := io.cmdReq.bits.cmd.op1_bank_addr // Read start row address - rbank_reg := io.cmdReq.bits.cmd.op1_bank // Read source bank - - // Iteration and rounds - iter_reg := io.cmdReq.bits.cmd.iter // Total rows to process (iteration count) - // Calculate required tile rounds for this batch: each round processes veclane rows - // cycle_reg = ceil(iter / veclane) - 1, decrements after each read/write round completes - cycle_reg := (io.cmdReq.bits.cmd.iter +& (b.veclane.U - 1.U)) / b.veclane.U - 1.U -} -``` - -**Data path (split & pack)**: - -- Read returns a packed data row of width `spad_w = veclane × inputWidth`; -- Split into `veclane` elements (no arithmetic modification) and buffer into `regArray` by row; -- When writing back, repack a full row of `veclane` elements: - -```scala -// Split by column -val dataWord = io.sramRead(rbank_reg).resp.bits.data -for (col <- 0 until b.veclane) { - val hi = (col + 1) * b.inputType.getWidth - 1 - val lo = col * b.inputType.getWidth - val raw = dataWord(hi, lo) - regArray(respCounter)(col) := raw.asUInt -} - -// Pack regArray(rowIdx) into one row for write-back -writeDataReg := Cat((0 until b.veclane).reverse.map(j => regArray(rowIdx)(j))) -// Full mask write -for (i <- 0 until b.spad_mask_len) { writeMaskReg(i) := 1.U } -``` - -**SRAM interface**: - -```scala -val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(b.spad_bank_entries, spad_w))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(b.spad_bank_entries, spad_w, b.spad_mask_len))) - val status = new Status -}) -``` - -**Processing flow**: - -1. **idle**: Wait for command; parse input/output bank/addr, iteration count `iter`, and calculate `cycle_reg` accordingly. Optionally, advance to next round by adjusting addresses when `cycle_reg =/= 0`. -2. **sRead**: Issue consecutive read requests row by row for the source bank/addr; after receiving data, split and fill into `regArray`; enter write phase after accumulating `veclane` rows. -3. **sWrite**: Pack and write back row by row to consecutive addresses in `wbank` with full mask write; enter complete phase after writing `veclane` rows. -4. **complete**: When all rounds complete (`cycle_reg == 0`), issue `cmdResp` completion response; then return to `idle`. - -**Inputs/Outputs**: - -- Input: Ball domain commands (`wr_bank/wr_bank_addr`, `op1_bank/op1_bank_addr`, `iter`, etc.) -- Output: Copied tile written to destination bank, `cmdResp` completion notification -- Boundaries and constraints: - - Each round processes `veclane` rows, iteration round count derived from `iter`; - - Write-back uses full mask (can be extended for partial write as needed). - -## ISA Structure - -The Ball instruction corresponding to this module performs tile-based copy on Scratchpad data and writes back to the destination. - -**Function**: Copy input rows from source Scratchpad address to destination Scratchpad address, write back row by row, loop `iter` times. - -**Format**: `bb_transfer rs1, rs2` - -**Operands**: - -- `rs1[spAddrLen-1:0]`: Source Scratchpad address (op1_spaddr) -- `rs2[spAddrLen-1:0]`: Destination Scratchpad address (wr_spaddr) -- `rs2[spAddrLen+9:spAddrLen]`: Iteration count (iter, row count) -- `rs2[63:spAddrLen+10]`: special/reserved field (not used by current Transfer) - -Address note: Local address of `spAddrLen` width is further split into bank and row in hardware (see LocalAddr), no need to explicitly distinguish at ISA level. - -**Operation**: Read data from Scratchpad address specified by `rs1`, then write back row by row to address specified by `rs2`, loop `iter` times. - -rs1 (source address): - -``` -┌──────────────────────────────────────────────────────┐ -│ op1_spaddr │ -│ (spAddrLen bits) │ -├──────────────────────────────────────────────────────┤ -│ [spAddrLen-1:0] │ -└──────────────────────────────────────────────────────┘ -``` - -rs2 (destination address and iteration count): - -``` -┌──────────────────────────────────┬────────────────────┐ -│ iter (rows) │ wr_spaddr │ -│ (10 bits) │ (spAddrLen bits) │ -├──────────────────────────────────┼────────────────────┤ -│ [spAddrLen+9: spAddrLen] │ [spAddrLen-1:0] │ -└──────────────────────────────────┴────────────────────┘ -``` - -Note: During decode, `op1_spaddr` comes from `rs1`, `wr_spaddr` and `iter` come from `rs2`, remaining `special` high bits can be reserved for extension. - -## Usage - -- Place source data at Scratchpad starting position specified by `op1_bank/op1_bank_addr`, ensure each row width is `veclane × inputWidth`; -- Configure destination `wr_bank/wr_bank_addr`, and element row count `iter` to process; -- After sending Ball command, wait for `cmdResp` completion; -- Can poll `status`: `ready/valid/idle/init/running/complete/iter` to get runtime information. - -### Notes - -1. **Handshake robustness**: Prefer gating `resp.ready` by local buffer availability (e.g., `respCounter < readCounter && respCounter < b.veclane.U`) to avoid overruns; simple `true.B` is acceptable when the Scratchpad controller guarantees pacing. -2. **Bandwidth and alignment**: Each read/write is one packed row (`spad_w` bits), addresses need to be row-aligned and increment consecutively. -3. **Mask strategy**: Current implementation uses full mask write; if sparse/partial write needed, extend `writeMaskReg` generation logic or use constant full-ones without a register. -4. **Iteration and chunking**: When `iter` is not a multiple of `veclane`, `cycle_reg` handles remaining rows with ceiling rounding; addresses advance by `veclane` per round. -5. **Read/Write phasing**: If the Scratchpad bank ports disallow same-bank concurrent read/write, keep two-phase read-then-write; otherwise consider streaming per-row read→write to reduce buffer size. -6. **Reset behavior**: Reset clears `regArray`, `writeDataReg`, `writeMaskReg`, facilitating reproducible simulation. diff --git a/arch/src/main/scala/prototype/transfer/Transfer.scala b/arch/src/main/scala/prototype/transfer/Transfer.scala deleted file mode 100644 index 8e07d35b..00000000 --- a/arch/src/main/scala/prototype/transfer/Transfer.scala +++ /dev/null @@ -1,206 +0,0 @@ -package prototype.transfer - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status -import prototype.transfer.configs.TransferConfig - -@instantiable -class Transfer(val parameter: TransferConfig)(implicit p: Parameters) - extends Module - with SerializableModule[TransferConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) - - // Connect to unified bank read/write interface - val bankRead = - Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) - - val bankWrite = Vec( - ballParam.numBanks, - Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen)) - ) - - // Status output - val status = new Status - }) - - val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) - val state = RegInit(idle) - - // Store a row of split elements (InputNum elements) - val regArray = RegInit( - VecInit(Seq.fill(InputNum)( - VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - )) - ) - - // Counters - val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - val cycle_reg = RegInit(0.U(6.W)) - // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) - - // Precompute write data - val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) - - // SRAM default assignment - for (i <- 0 until ballParam.numBanks) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := false.B - - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(ballParam.bankMaskLen)(0.U(1.W))) - } - - // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg - - // State machine - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - state := sRead - readCounter := 0.U - respCounter := 0.U - writeCounter := 0.U - - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U // New ISA: all operations start from row 0 - wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := 0.U // New ISA: all operations start from row 0 - rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U - } - - when(cycle_reg =/= 0.U) { - state := sRead - readCounter := 0.U - writeCounter := 0.U - respCounter := 0.U - waddr_reg := waddr_reg + InputNum.U - raddr_reg := raddr_reg + InputNum.U - cycle_reg := cycle_reg - 1.U - } - } - - is(sRead) { - when(readCounter < InputNum.U) { - // Issue read request - readCounter := readCounter + 1.U - io.bankRead(rbank_reg).req.valid := true.B - io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - - } - - // Receive response, only raise ready when there are outstanding reads - val dataWord = io.bankRead(rbank_reg).resp.bits.data - // val hasOutstandingRead = readCounter =/= respCounter - io.bankRead(rbank_reg).resp.ready := true.B - when(io.bankRead(rbank_reg).resp.fire) { - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - val raw = dataWord(hi, lo) - regArray(respCounter)(col) := raw.asUInt - } - respCounter := respCounter + 1.U - } - - when(respCounter === InputNum.U) { - state := sWrite - // Precompute first write data (row 0, concatenated by column) - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) - // Set write mask (write all) - for (i <- 0 until ballParam.bankMaskLen) { - writeMaskReg(i) := 1.U(1.W) - } - } - } - - is(sWrite) { - // Correctly use ready/valid handshake to advance writes, avoid dropped writes - io.bankWrite(wbank_reg).req.valid := writeCounter < InputNum.U - io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.bankWrite(wbank_reg).req.bits.data := writeDataReg - io.bankWrite(wbank_reg).req.bits.mask := writeMaskReg - - when(writeCounter === (InputNum - 1).U) { - state := complete - }.otherwise { - writeCounter := writeCounter + 1.U - // Prepare next row's write data - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) - } - - } - - is(complete) { - when(cycle_reg === 0.U) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } - } - state := idle - } - } - - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < InputNum.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt - - when(reset.asBool) { - for (i <- 0 until InputNum) { - for (j <- 0 until InputNum) { - regArray(i)(j) := 0.U - } - } - writeDataReg := 0.U - for (i <- 0 until ballParam.bankMaskLen) { - writeMaskReg(i) := 0.U - } - } -} diff --git a/arch/src/main/scala/prototype/transfer/TransferBall.scala b/arch/src/main/scala/prototype/transfer/TransferBall.scala deleted file mode 100644 index 6f7c6fa6..00000000 --- a/arch/src/main/scala/prototype/transfer/TransferBall.scala +++ /dev/null @@ -1,47 +0,0 @@ -package prototype.transfer - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.transfer.Transfer -import prototype.transfer.configs.TransferConfig - -// TransferBall - A data transfer Ball that complies with the Blink protocol. -// Behavior: Read data from Scratchpad and write it back without modification. - -@instantiable -class TransferBall(config: TransferConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - // Satisfy BallRegist requirements - def Blink: Blink = io - - // Instantiate Transfer computation unit - private val transferUnit: Instance[Transfer] = Instantiate(new Transfer(config)) - - // Connect command interface - transferUnit.io.cmdReq <> io.cmdReq - transferUnit.io.cmdResp <> io.cmdResp - - // Connect Bank read/write interface - for (i <- 0 until parameter.numBanks) { - transferUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - transferUnit.io.bankWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // TransferBall uses overwrite mode - } - - // Pass through status signals - io.status <> transferUnit.io.status - - override lazy val desiredName: String = "TransferBall" -} diff --git a/arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala b/arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala deleted file mode 100644 index 425a2f4d..00000000 --- a/arch/src/main/scala/prototype/transfer/configs/TransferConfig.scala +++ /dev/null @@ -1,62 +0,0 @@ -package prototype.transfer.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object TransferConfig { - implicit def rw: upickle.default.ReadWriter[TransferConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): TransferConfig = { - TransferConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): TransferConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[TransferConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: TransferConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class TransferConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - // Derived parameters - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""TransferConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/transfer/configs/default.json b/arch/src/main/scala/prototype/transfer/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/transfer/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/transpose/README.md b/arch/src/main/scala/prototype/transpose/README.md deleted file mode 100644 index 3c01b53d..00000000 --- a/arch/src/main/scala/prototype/transpose/README.md +++ /dev/null @@ -1,115 +0,0 @@ -# Matrix Transpose Accelerator - -## Overview - -This directory implements Buckyball's matrix transpose accelerator for matrix transpose operations. Located at `arch/src/main/scala/prototype/transpose`, it serves as a matrix transpose accelerator supporting pipelined transpose operations. - -Core components: -- **Transpose.scala**: Pipelined transposer implementation - -## Code Structure - -``` -transpose/ -└── Transpose.scala - Pipelined transposer -``` - -### Module Responsibilities - -**Transpose.scala** (Transpose implementation layer) -- Implements PipelinedTransposer module -- Manages matrix data read, transpose, and write-back -- Provides Ball domain command interface - -## Module Description - -### Transpose.scala - -**Main functionality**: Implements pipelined matrix transpose operation - -**State machine definition**: -```scala -val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) -val state = RegInit(idle) -``` - -**Storage structure**: -```scala -// Matrix storage register (veclane x veclane) -val regArray = Reg(Vec(b.veclane, Vec(b.veclane, UInt(b.inputType.getWidth.W)))) -``` - -**Counter management**: -```scala -val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) -val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) -val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) -``` - -**Instruction registers**: -```scala -val robid_reg = RegInit(0.U(10.W)) // ROB ID -val waddr_reg = RegInit(0.U(10.W)) // Write address -val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) // Write bank -val raddr_reg = RegInit(0.U(10.W)) // Read address -val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) // Read bank -val iter_reg = RegInit(0.U(10.W)) // Iteration count -``` - -**Interface definition**: -```scala -val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue)) - val cmdResp = Decoupled(new BallRsComplete) - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(...))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(...))) -}) -``` - -**Processing flow**: -1. **idle**: Wait for command, parse transpose parameters -2. **sRead**: Read matrix data row by row into register array -3. **sWrite**: Write transposed data column by column -4. **complete**: Send completion signal - -**Transpose algorithm**: -- Uses veclane×veclane register array to store matrix -- Reads row-wise, writes column-wise to implement transpose -- Supports block-wise transpose for matrices of arbitrary size - -## Usage - -### Implementation Details - -**State machine**: -```scala -val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) -``` -- `idle`: Wait for instruction -- `sRead`: Read matrix data -- `sWrite`: Write transpose result -- `complete`: Complete and respond - -**Register array**: -```scala -val regArray = Reg(Vec(b.veclane, Vec(b.veclane, UInt(b.inputType.getWidth.W)))) -``` -Uses veclane×veclane register array to cache matrix data. - -**Transpose operation**: -- Read phase: Read data row by row into `regArray(row)(col)` -- Write phase: Read `regArray(i)(col)` column by column to form new rows for writing - -### Configuration Parameters - -**Matrix size**: Determined by b.veclane parameter -**Data width**: Determined by b.inputType.getWidth -**Bank configuration**: Supports multi-bank SRAM access - -### Notes - -1. **Matrix size limitation**: Maximum support for veclane×veclane matrices -2. **Memory bandwidth**: Transpose operation has high memory bandwidth requirements -3. **Register overhead**: Requires veclane² registers to store matrix -4. **Address calculation**: Transposed address calculation needs to be handled correctly -5. **Pipeline control**: Read/write counters need to be synchronized correctly diff --git a/arch/src/main/scala/prototype/transpose/Transpose.scala b/arch/src/main/scala/prototype/transpose/Transpose.scala deleted file mode 100644 index 0582f336..00000000 --- a/arch/src/main/scala/prototype/transpose/Transpose.scala +++ /dev/null @@ -1,166 +0,0 @@ -package prototype.transpose - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Status -import prototype.transpose.configs.TransposeConfig - -@instantiable -class PipelinedTransposer(val parameter: TransposeConfig)(implicit p: Parameters) - extends Module - with SerializableModule[TransposeConfig] { - // Get parameters from config - val ballParam = parameter.ballParam - val InputNum = parameter.InputNum - val inputWidth = parameter.inputWidth - val bankWidth = parameter.bankWidth - - @public - val io = IO(new Bundle { - // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(ballParam))) - val cmdResp = Decoupled(new BallRsComplete(ballParam)) - - // Connect to unified bank read/write interface - val bankRead = Vec(ballParam.numBanks, Flipped(new SramReadIO(ballParam.bankEntries, bankWidth))) - val bankWrite = - Vec(ballParam.numBanks, Flipped(new SramWriteIO(ballParam.bankEntries, bankWidth, ballParam.bankMaskLen))) - - // Status output - val status = new Status - }) - - val idle :: compute :: Nil = Enum(2) - val state = RegInit(idle) - - // Matrix storage register (InputNum x InputNum) - val regArray = Reg(Vec(InputNum * 2, Vec(InputNum, UInt(inputWidth.W)))) - - // Counters - val readCounter = RegInit(0.U(10.W)) - val respCounter = RegInit(0.U(10.W)) - val writeCounter = RegInit(0.U(10.W)) - val respWaitcounter = RegInit(0.U(10.W)) - val writeHeadptr = RegInit(0.U(10.W)) - val writeTailptr = RegInit(0.U(10.W)) - - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(ballParam.numBanks).W)) - val iter_reg = RegInit(0.U(10.W)) - val write_iter_reg = RegInit(0.U(10.W)) - val mode_reg = RegInit(0.U(1.W)) - - // Precompute write data - val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(ballParam.bankMaskLen, UInt(1.W))) - - val start_write = RegInit(false.B) - // SRAM default assignment - for (i <- 0 until ballParam.numBanks) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := false.B - - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(0.U(1.W))) - } - - // cmd interface default assignment - io.cmdReq.ready := state === idle - - when(state === idle && io.cmdReq.fire) { - state := compute - readCounter := 0.U - respCounter := 0.U - respWaitcounter := io.cmdReq.bits.cmd.iter + respWaitcounter - - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U // New ISA: all operations start from row 0 - wbank_reg := io.cmdReq.bits.cmd.op2_bank - raddr_reg := 0.U // New ISA: all operations start from row 0 - rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - mode_reg := io.cmdReq.bits.cmd.special(0) - } - // read req - when(((mode_reg === 1.U) && (state === compute) && RegNext(io.bankWrite(0).req.ready)) || - ((mode_reg === 0.U) && (state === compute))) { - readCounter := readCounter + 1.U - io.bankRead(rbank_reg).req.valid := readCounter < iter_reg - io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) - } - io.cmdResp.valid := (readCounter >= (iter_reg - 1.U)) && (state === compute) - io.cmdResp.bits.rob_id := robid_reg - - // read resp - io.bankRead(rbank_reg).resp.ready := true.B - val dataWord = io.bankRead(rbank_reg).resp.bits.data - val row = respCounter(4, 0) - when(io.bankRead(rbank_reg).resp.fire && respWaitcounter > 0.U) { - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - regArray(row)(col) := dataWord(hi, lo) - } - respCounter := Mux(respCounter === iter_reg - 1.U, 0.U, respCounter + 1.U) - writeHeadptr := Mux(writeHeadptr === 2.U * InputNum.U - 1.U, 0.U, writeHeadptr + 1.U) - respWaitcounter := Mux( - state === idle && io.cmdReq.fire, - io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, - respWaitcounter - 1.U - ) - } - - // write req - val wreg = RegInit(0.U(10.W)) - val array_full = ((writeTailptr < InputNum.U) && (writeHeadptr >= InputNum.U)) || - ((writeTailptr >= InputNum.U) && (writeHeadptr < InputNum.U)) - when(writeCounter === iter_reg - 1.U) { - start_write := false.B - }.elsewhen(array_full && !start_write) { - start_write := true.B - wreg := waddr_reg - write_iter_reg := iter_reg - }.otherwise { - start_write := start_write - } - - when(start_write) { - io.bankWrite(wbank_reg).req.valid := true.B - io.bankWrite(wbank_reg).req.bits.addr := wreg + writeCounter - io.bankWrite(wbank_reg).req.bits.data := Mux( - writeCounter(4) === 0.U, - Cat((0 until InputNum).reverse.map(i => regArray(i)(writeCounter(3, 0)))), - Cat((0 until InputNum).reverse.map(i => regArray(i + InputNum)(writeCounter(3, 0)))) - ) - io.bankWrite(wbank_reg).req.bits.mask := VecInit(Seq.fill(parameter.bankMaskLen)(~0.U(1.W))) - writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U, writeCounter + 1.U) - writeTailptr := Mux(writeTailptr === 2.U * InputNum.U - 1.U, 0.U, writeTailptr + 1.U) - } - // Status signals - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := state === idle - io.status.init := readCounter === 0.U && state === compute - io.status.running := state === compute - io.status.iter := readCounter - io.status.complete := io.cmdResp.valid - -} diff --git a/arch/src/main/scala/prototype/transpose/TransposeBall.scala b/arch/src/main/scala/prototype/transpose/TransposeBall.scala deleted file mode 100644 index 910a42fa..00000000 --- a/arch/src/main/scala/prototype/transpose/TransposeBall.scala +++ /dev/null @@ -1,47 +0,0 @@ -package prototype.transpose - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.{BallRegist, Blink} -import prototype.transpose.PipelinedTransposer -import prototype.transpose.configs.TransposeConfig - -/** - * TransposeBall - A transpose computation Ball that complies with the Blink protocol - */ -@instantiable -class TransposeBall(config: TransposeConfig, id: Int)(implicit p: Parameters) extends Module with BallRegist { - val parameter = config.ballParam - @public - val io = IO(new Blink(parameter, config.bankEntries, config.bankWidth, config.bankMaskLen)) - val ballId = id.U - - def Blink: Blink = io - - // Instantiate PipelinedTransposer - val transposeUnit: Instance[PipelinedTransposer] = Instantiate(new PipelinedTransposer(config)) - - // Connect command interface - transposeUnit.io.cmdReq <> io.cmdReq - transposeUnit.io.cmdResp <> io.cmdResp - - // Connect Bank interface - for (i <- 0 until parameter.numBanks) { - transposeUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U - - transposeUnit.io.bankWrite(i) <> io.bankWrite(i).io - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // TransposeBall uses overwrite mode - } - - // Connect Status signals - directly obtained from internal unit - io.status <> transposeUnit.io.status - - override lazy val desiredName = "TransposeBall" -} diff --git a/arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala b/arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala deleted file mode 100644 index 8ac2d4cf..00000000 --- a/arch/src/main/scala/prototype/transpose/configs/TransposeConfig.scala +++ /dev/null @@ -1,62 +0,0 @@ -package prototype.transpose.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object TransposeConfig { - implicit def rw: upickle.default.ReadWriter[TransposeConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): TransposeConfig = { - TransposeConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): TransposeConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[TransposeConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: TransposeConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class TransposeConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - // Derived parameters - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""TransposeConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/transpose/configs/default.json b/arch/src/main/scala/prototype/transpose/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/transpose/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/vector/VecEXUnit.scala b/arch/src/main/scala/prototype/vector/VecEXUnit.scala deleted file mode 100644 index d5c2f85f..00000000 --- a/arch/src/main/scala/prototype/vector/VecEXUnit.scala +++ /dev/null @@ -1,98 +0,0 @@ -package prototype.vector - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} -import chisel3.experimental.{SerializableModule, SerializableModuleParameter} -import org.chipsalliance.cde.config.Parameters - -import prototype.vector._ -import examples.toy.balldomain.BallDomainParam -import prototype.vector.warp.VecBall - -class ctrl_ex_req extends Bundle { - val iter = UInt(10.W) -} - -class ld_ex_req(parameter: BallDomainParam) extends Bundle { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val op1 = Vec(InputNum, UInt(inputWidth.W)) - val op2 = Vec(InputNum, UInt(inputWidth.W)) - val iter = UInt(10.W) -} - -@instantiable -class VecEXUnit(val parameter: BallDomainParam)(implicit p: Parameters) - extends Module - with SerializableModule[BallDomainParam] { - // Derived parameters - val InputNum = 16 - val inputWidth = 8 - val accWidth = 32 - - @public - val io = IO(new Bundle { - val ctrl_ex_i = Flipped(Decoupled(new ctrl_ex_req)) - val ld_ex_i = Flipped(Decoupled(new ld_ex_req(parameter))) - - val ex_st_o = Decoupled(new ex_st_req(parameter)) - }) - - val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) - - val VecBall = Module(new VecBall()(p)) - - // Initialize default values for all signals - io.ctrl_ex_i.ready := false.B - io.ex_st_o.valid := false.B - io.ex_st_o.bits.rst := VecInit(Seq.fill(InputNum)(0.U(accWidth.W))) - io.ex_st_o.bits.iter := 0.U - - // Initialize VecBall input signals with default values - VecBall.io.iterIn.valid := false.B - VecBall.io.iterIn.bits := 0.U - VecBall.io.op1In.valid := false.B - VecBall.io.op1In.bits := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - VecBall.io.op2In.valid := false.B - VecBall.io.op2In.bits := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - VecBall.io.rstOut.ready := false.B - -// ----------------------------------------------------------------------------- -// Set registers when Ctrl instruction arrives -// ----------------------------------------------------------------------------- - io.ctrl_ex_i.ready := state === idle - when(io.ctrl_ex_i.fire) { - VecBall.io.iterIn.valid := true.B - VecBall.io.iterIn.bits := io.ctrl_ex_i.bits.iter - state := busy - } - -// ----------------------------------------------------------------------------- -// Accept read results from load unit and perform computation -// ----------------------------------------------------------------------------- - io.ld_ex_i.ready := state === busy && VecBall.io.iterIn.ready - when(io.ld_ex_i.valid) { - VecBall.io.op1In.valid := true.B - VecBall.io.op1In.bits := io.ld_ex_i.bits.op1 - VecBall.io.op2In.valid := true.B - VecBall.io.op2In.bits := io.ld_ex_i.bits.op2 - //assert((io.ld_ex_i.bits.iter - VecBall.get_iterCounter() === 16.U) && VecBall.get_arrive(), - //"[VecLoad -> VecEX] iteration mismatch") - } - -// ----------------------------------------------------------------------------- -// Send computation results to store unit for write-back -// ----------------------------------------------------------------------------- - io.ex_st_o.valid := VecBall.io.rstOut.valid - VecBall.io.rstOut.ready := io.ex_st_o.ready - - when(io.ex_st_o.fire) { - io.ex_st_o.bits.rst := VecBall.io.rstOut.bits - io.ex_st_o.bits.iter := VecBall.io.iterOut.bits - } - -} diff --git a/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala b/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala deleted file mode 100644 index c6ea8a95..00000000 --- a/arch/src/main/scala/prototype/vector/bond/BondWrapper.scala +++ /dev/null @@ -1,20 +0,0 @@ -package prototype.vector.bond - -import org.chipsalliance.cde.config._ -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import org.chipsalliance.diplomacy._ -import org.chipsalliance.diplomacy.bundlebridge._ -import org.chipsalliance.diplomacy.lazymodule._ -import org.chipsalliance.diplomacy.nodes._ - -abstract class BondWrapper(implicit p: Parameters) extends LazyModule { - val bondName = "vvv" - - def to[T](name: String)(body: => T): T = - LazyScope(s"bond_to_$name", s"Bond_${bondName}_to_$name")(body) - - def from[T](name: String)(body: => T): T = - LazyScope(s"bond_from_$name", s"Bond_${bondName}_from_$name")(body) -} diff --git a/arch/src/main/scala/prototype/vector/bond/vvv.scala b/arch/src/main/scala/prototype/vector/bond/vvv.scala deleted file mode 100644 index 5244ea6a..00000000 --- a/arch/src/main/scala/prototype/vector/bond/vvv.scala +++ /dev/null @@ -1,42 +0,0 @@ -//===----------------------------------------------------------------------===// -// VVV Bond: -// Input: Vec, Vec -// Output: Vec -//===----------------------------------------------------------------------===// - -package prototype.vector.bond - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import prototype.vector.thread.{BaseThread, ThreadBondKey, ThreadKey} - -class VVV(implicit p: Parameters) extends Bundle { - val lane = p(ThreadKey).get.lane - val bondParam = p(ThreadBondKey).get - val inputWidth = bondParam.inputWidth - val outputWidth = bondParam.outputWidth - - // Input interface (Flipped Decoupled) - val in = Flipped(Decoupled(new Bundle { - val in1 = Vec(lane, UInt(inputWidth.W)) - val in2 = Vec(lane, UInt(inputWidth.W)) - })) - - // Decoupled output interface - val out = Decoupled(new Bundle { - val out = Vec(lane, UInt(outputWidth.W)) - }) - -} - -trait CanHaveVVVBond { this: BaseThread => - - val vvvBond = params(ThreadBondKey).filter(_.bondType == "vvv").map { bondParam => - // println(s"[VVVBond] Creating BondType: ${bondParam.bondType}") - - IO(new VVV()(params)) - } - - def getVVVBond = vvvBond -} diff --git a/arch/src/main/scala/prototype/vector/configs/VecConfig.scala b/arch/src/main/scala/prototype/vector/configs/VecConfig.scala deleted file mode 100644 index f1a238a6..00000000 --- a/arch/src/main/scala/prototype/vector/configs/VecConfig.scala +++ /dev/null @@ -1,62 +0,0 @@ -package prototype.vector.configs - -import chisel3._ -import chisel3.experimental.SerializableModuleParameter -import examples.toy.balldomain.BallDomainParam - -object VecConfig { - implicit def rw: upickle.default.ReadWriter[VecConfig] = upickle.default.macroRW - - def fromBallDomain(ballParam: BallDomainParam): VecConfig = { - VecConfig( - ballParam = ballParam - ) - } - - /** - * Load from JSON file - */ - def fromJson(path: String): VecConfig = { - val jsonStr = scala.io.Source.fromFile(path).mkString - upickle.default.read[VecConfig](jsonStr) - } - - /** - * Save to JSON file - */ - def toJson(config: VecConfig, path: String): Unit = { - val jsonStr = upickle.default.write(config, indent = 2) - val writer = new java.io.FileWriter(path) - try { - writer.write(jsonStr) - } finally { - writer.close() - } - } - -} - -case class VecConfig( - ballParam: BallDomainParam) - extends SerializableModuleParameter { - // Derived parameters - val bankNum = ballParam.numBanks - val bankEntries = ballParam.bankEntries - val bankWidth = ballParam.bankWidth - val bankMaskLen = ballParam.bankMaskLen - val rob_entries = ballParam.rob_entries - // InputNum and inputWidth are Ball-specific, not in BallDomainParam - val InputNum = 16 // Default value - val inputWidth = 8 // Default value - - override def toString: String = - s"""VecConfig - | Bank num: $bankNum - | Bank entries: $bankEntries - | Bank width: $bankWidth - | Bank mask length: $bankMaskLen - | ROB entries: $rob_entries - | Input num: $InputNum - | Input width: $inputWidth - |""".stripMargin -} diff --git a/arch/src/main/scala/prototype/vector/configs/default.json b/arch/src/main/scala/prototype/vector/configs/default.json deleted file mode 100644 index 0b9d3815..00000000 --- a/arch/src/main/scala/prototype/vector/configs/default.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "ballParam": { - "rob_entries": 16, - "numBanks": 32, - "bankEntries": 128, - "bankMaskLen": 16, - "InputNum": 16, - "inputWidth": 8 - } -} diff --git a/arch/src/main/scala/prototype/vector/op/mul.scala b/arch/src/main/scala/prototype/vector/op/mul.scala deleted file mode 100644 index 50fd8ec2..00000000 --- a/arch/src/main/scala/prototype/vector/op/mul.scala +++ /dev/null @@ -1,52 +0,0 @@ -package prototype.vector.op - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import prototype.vector.thread.{BaseThread, ThreadBondKey, ThreadKey, ThreadOpKey} -import prototype.vector.bond.VVV - -class MulOp(implicit p: Parameters) extends Module { - val lane = p(ThreadKey).get.lane - val bondParam = p(ThreadBondKey).get - val inputWidth = bondParam.inputWidth - - val io = IO(new VVV()(p)) - - val reg1 = RegInit(VecInit(Seq.fill(lane)(0.U(inputWidth.W)))) - val reg2 = RegInit(VecInit(Seq.fill(lane)(0.U(inputWidth.W)))) - - val cnt = RegInit(0.U(log2Ceil(lane).W)) - val active = RegInit(false.B) - - io.out.valid := active && io.out.ready - io.in.ready := io.out.ready - - when(io.in.valid) { - reg1 := io.in.bits.in1 - reg2 := io.in.bits.in2 - cnt := 0.U - active := true.B - }.elsewhen(active && io.out.ready) { - cnt := cnt + 1.U - when(cnt === (lane - 1).U) { - active := false.B - } - } - - for (i <- 0 until lane) { - io.out.bits.out(i) := Mux(io.out.valid, reg1(cnt) * reg2(i), 0.U) - } - -} - -trait CanHaveMulOp { this: BaseThread => - - val mulOp = params(ThreadOpKey).filter(_.OpType == "mul").map { opParam => - // println(s"[MulOp] Creating OpType: ${opParam.OpType}") - - Module(new MulOp()(params)) - } - - def getMulOp = mulOp -} diff --git a/arch/src/main/scala/prototype/vector/thread/BaseThread.scala b/arch/src/main/scala/prototype/vector/thread/BaseThread.scala deleted file mode 100644 index 06930c25..00000000 --- a/arch/src/main/scala/prototype/vector/thread/BaseThread.scala +++ /dev/null @@ -1,40 +0,0 @@ -//===- BaseThread.scala - Level 1: Thread ---===// -package prototype.vector.thread - -import chisel3._ -import org.chipsalliance.cde.config._ - -// Parameter definitions -case class ThreadParam( - lane: Int, - attr: String, - threadName: String, - Op: OpParam) - -case class OpParam(OpType: String, bondType: BondParam) -case class BondParam(bondType: String, inputWidth: Int = 8, outputWidth: Int = 32) - -case object ThreadKey extends Field[Option[ThreadParam]](None) -case object ThreadOpKey extends Field[Option[OpParam]](None) -case object ThreadBondKey extends Field[Option[BondParam]](None) -case object ThreadMapKey extends Field[Map[String, ThreadParam]](Map.empty) - -//===----------------------------------------------------------------------===// -// BaseThread base class -//===----------------------------------------------------------------------===// -class BaseThread(implicit p: Parameters) extends Module { - val io = IO(new Bundle {}) - val params = p - val threadMap = p(ThreadMapKey) - - val threadParam = threadMap.getOrElse( - p(ThreadKey).get.threadName, - throw new Exception(s"ThreadParam not found for threadName: ${p(ThreadKey).get.threadName}") - ) - - val opParam = p(ThreadOpKey).get - val bondParam = p(ThreadBondKey).get - println( - s"[Thread_${threadParam.threadName}] Op: ${opParam.OpType}, bond: ${bondParam.bondType}, Lanes: ${threadParam.lane}" - ) -} diff --git a/arch/src/main/scala/prototype/vector/thread/CasThread.scala b/arch/src/main/scala/prototype/vector/thread/CasThread.scala deleted file mode 100644 index 5c0ed560..00000000 --- a/arch/src/main/scala/prototype/vector/thread/CasThread.scala +++ /dev/null @@ -1,19 +0,0 @@ -package prototype.vector.thread - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import prototype.vector.bond.CanHaveVVVBond -import prototype.vector.op.{CanHaveCascadeOp, CascadeOp} - -class CasThread(implicit p: Parameters) extends BaseThread with CanHaveCascadeOp with CanHaveVVVBond { - - // Connect CascadeOp and VVVBond - for { - op <- cascadeOp - bond <- vvvBond - } { - op.io.in <> bond.in - op.io.out <> bond.out - } -} diff --git a/arch/src/main/scala/prototype/vector/thread/MulThread.scala b/arch/src/main/scala/prototype/vector/thread/MulThread.scala deleted file mode 100644 index 1ee20cb8..00000000 --- a/arch/src/main/scala/prototype/vector/thread/MulThread.scala +++ /dev/null @@ -1,19 +0,0 @@ -package prototype.vector.thread - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ -import prototype.vector.bond.CanHaveVVVBond -import prototype.vector.op.{CanHaveMulOp, MulOp} - -class MulThread(implicit p: Parameters) extends BaseThread with CanHaveMulOp with CanHaveVVVBond { - - // Connect MulOp and VVVBond - for { - op <- mulOp - bond <- vvvBond - } { - op.io.in <> bond.in - op.io.out <> bond.out - } -} diff --git a/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala b/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala deleted file mode 100644 index 31946d01..00000000 --- a/arch/src/main/scala/prototype/vector/warp/MeshWarp.scala +++ /dev/null @@ -1,139 +0,0 @@ -package prototype.vector.warp - -import chisel3._ -import chisel3.util._ -import chisel3.stage._ -import org.chipsalliance.cde.config.Parameters - -import prototype.vector.thread._ -import prototype.vector.bond.BondWrapper - -class MeshWarpInput extends Bundle { - val op1 = Vec(16, UInt(8.W)) - val op2 = Vec(16, UInt(8.W)) - val thread_id = UInt(10.W) -} - -class MeshWarpOutput extends Bundle { - val res = Vec(16, UInt(32.W)) -} - -class MeshWarp(implicit p: Parameters) extends Module { - - val io = IO(new Bundle { - val in = Flipped(Decoupled(new MeshWarpInput)) - val out = Decoupled(new MeshWarpOutput) - }) - - val threadMap = (0 until 32).map { i => - val threadName = i.toString - // 0-15 mul, 16-31 cascade - val opType = if (i < 16) "mul" else "cascade" - // mul operation: 8-bit input, 32-bit output; cascade operation: 32-bit input, 32-bit output - val bond = if (opType == "mul") { - BondParam("vvv", inputWidth = 8, outputWidth = 32) - } else { - BondParam("vvv", inputWidth = 32, outputWidth = 32) - } - val op = OpParam(opType, bond) - // All threads use the same lane count - val thread = ThreadParam(16, s"attr$threadName", threadName, op) - threadName -> thread - }.toMap - - val mulThreads = (0 until 16).map { i => - val threadName = i.toString - val threadParam = threadMap(threadName) - val opParam = threadParam.Op - val bondParam = opParam.bondType - val threadParams = p.alterMap(Map( - ThreadMapKey -> threadMap, - ThreadKey -> Some(threadParam), - ThreadOpKey -> Some(opParam), - ThreadBondKey -> Some(bondParam) - )) - Module(new MulThread()(threadParams)) - } - - val casThreads = (16 until 32).map { i => - val threadName = i.toString - val threadParam = threadMap(threadName) - val opParam = threadParam.Op - val bondParam = opParam.bondType - val threadParams = p.alterMap(Map( - ThreadMapKey -> threadMap, - ThreadKey -> Some(threadParam), - ThreadOpKey -> Some(opParam), - ThreadBondKey -> Some(bondParam) - )) - Module(new CasThread()(threadParams)) - } - - io.in.ready := mulThreads(0).vvvBond.get.in.ready - - for (i <- 0 until 16) { - val mulThread = mulThreads(i) - val casThread = casThreads(i) - for { - mulBond <- mulThread.vvvBond - casBond <- casThread.vvvBond - } { - // Connect mul thread output to cascade thread input - casBond.in.bits.in1 := mulBond.out.bits.out - mulBond.out.ready := casBond.in.ready - - // Connect cascade thread's second input and output ready signal - if (i == 0) { - casBond.in.bits.in2 := VecInit(Seq.fill(16)(0.U(32.W))) - // First cascade thread's valid is determined by mulBond's output valid - casBond.in.valid := mulBond.out.valid - // First cascade thread's output ready is connected to next cascade thread's input ready - if (i < 15) { - for { - nextCasBond <- casThreads(i + 1).vvvBond - } { - casBond.out.ready := nextCasBond.in.ready - } - } - } else { - for { - prevCasBond <- casThreads(i - 1).vvvBond - } { - // Directly connect 32-bit output to 32-bit input - casBond.in.bits.in2 := prevCasBond.out.bits.out - // casBond's valid is jointly determined by previous casBond's output valid and current mulBond's output valid - casBond.in.valid := prevCasBond.out.valid || mulBond.out.valid - } - // Middle cascade thread's output ready is connected to next cascade thread's input ready - if (i < 15) { - for { - nextCasBond <- casThreads(i + 1).vvvBond - } { - casBond.out.ready := nextCasBond.in.ready - } - } - } - - // Only allow mulOp corresponding to thread_id to drive input - when(i.U === io.in.bits.thread_id && io.in.valid) { - mulBond.in.valid := true.B - mulBond.in.bits.in1 := io.in.bits.op1 - mulBond.in.bits.in2 := io.in.bits.op2 - io.in.ready := mulBond.in.ready - }.otherwise { - mulBond.in.valid := false.B - mulBond.in.bits.in1 := VecInit(Seq.fill(16)(0.U(8.W))) - mulBond.in.bits.in2 := VecInit(Seq.fill(16)(0.U(8.W))) - } - } - } - - // Connect output - for { - finalCasBond <- casThreads(15).vvvBond - } { - io.out.valid := finalCasBond.out.valid - io.out.bits.res := finalCasBond.out.bits.out - finalCasBond.out.ready := io.out.ready - } -} diff --git a/arch/src/main/scala/prototype/vector/warp/VecBall.scala b/arch/src/main/scala/prototype/vector/warp/VecBall.scala deleted file mode 100644 index b624fdc0..00000000 --- a/arch/src/main/scala/prototype/vector/warp/VecBall.scala +++ /dev/null @@ -1,89 +0,0 @@ -package prototype.vector.warp - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config._ - -class BallIO extends Bundle { - // val start = Output(Bool()) - // val arrive = Output(Bool()) - // val done = Output(Bool()) - val iterIn = Flipped(Decoupled(UInt(10.W))) - val iterOut = Valid(UInt(10.W)) -} - -class VecBallIO extends BallIO { - val op1In = Flipped(Valid(Vec(16, UInt(8.W)))) - val op2In = Flipped(Valid(Vec(16, UInt(8.W)))) - val rstOut = Decoupled(Vec(16, UInt(32.W))) -} - -class VecBall(implicit p: Parameters) extends Module { - val io = IO(new VecBallIO()) - - // Internal state registers & iteration counter - val start = RegInit(false.B) - val arrive = RegInit(false.B) - val done = RegInit(false.B) - val iter = RegInit(0.U(10.W)) - val iterCounter = RegInit(0.U(10.W)) - - // Independent control logic - val threadId = RegInit(0.U(4.W)) - when(io.op1In.valid && io.op2In.valid && threadId < 15.U) { - threadId := threadId + 1.U - }.elsewhen(io.op1In.valid && io.op2In.valid && threadId === 15.U) { - threadId := 0.U - } - - // Instantiate MeshWarp - val meshWarp = Module(new MeshWarp()(p)) - - // Connect external IO to MeshWarp - meshWarp.io.in.valid := io.op1In.valid && io.op2In.valid - meshWarp.io.in.bits.op1 := io.op1In.bits - meshWarp.io.in.bits.op2 := io.op2In.bits - meshWarp.io.in.bits.thread_id := threadId - - io.rstOut.valid := meshWarp.io.out.valid - io.rstOut.bits := meshWarp.io.out.bits.res - meshWarp.io.out.ready := io.rstOut.ready - - // Handle iteration input - when(io.iterIn.fire) { iterCounter := 0.U; iter := io.iterIn.bits } - // Pull start high when external input arrives - when(io.op1In.valid && io.op2In.valid)(start := true.B) - // Pull arrive high when first output starts to be valid - when(io.rstOut.valid && !arrive)(arrive := true.B) - // Increment by one for each output - when(io.rstOut.valid && iterCounter =/= iter)(iterCounter := iterCounter + 1.U) - // Pull done high when iter returns to 0 - when(iterCounter === iter)(done := true.B) - - // Reset logic - when(io.iterIn.fire) { - start := false.B - arrive := false.B - done := false.B - iterCounter := 0.U - } - - // Output state - // io.start := start - // io.arrive := arrive - // io.done := done - - // Output current iteration count - io.iterOut.valid := io.rstOut.valid - io.iterOut.bits := iterCounter - io.iterIn.ready := meshWarp.io.in.ready - - // def get_iterCounter(): UInt = { - // iterCounter - // } - - // def get_arrive(): Bool = { - // arrive - // } - -} diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index be588c84..841112a2 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -3,21 +3,18 @@ package sims.verify import chisel3._ import _root_.circt.stage.ChiselStage import org.chipsalliance.cde.config.{Config, Field, Parameters} -import examples.BuckyballConfigs.CustomBuckyballConfig -import examples.toy.balldomain.BallDomainParam -import framework.balldomain.blink.Blink -import prototype.vector.VecBall -import prototype.vector.configs.VecConfig -import prototype.matrix.MatrixBall -import prototype.matrix.configs.MatrixConfig -import prototype.transpose.TransposeBall -import prototype.transpose.configs.TransposeConfig -import prototype.im2col.Im2colBall -import prototype.im2col.configs.Im2colConfig -import prototype.relu.ReluBall -import prototype.relu.configs.ReluConfig -import prototype.nnlut.NNLutBall -import prototype.nnlut.configs.NNLutConfig +import framework.top.GlobalConfig +import framework.balldomain.blink.BlinkIO +import framework.balldomain.prototype.vector.VecBall +// import framework.balldomain.prototype.matrix.MatrixBall +// import framework.balldomain.prototype.matrix.configs.MatrixConfig +// import framework.balldomain.prototype.transpose.TransposeBall +// import framework.balldomain.prototype.transpose.configs.TransposeConfig +// import framework.balldomain.prototype.im2col.Im2colBall +// import framework.balldomain.prototype.im2col.configs.Im2colConfig +// import framework.balldomain.prototype.relu.ReluBall +// import framework.balldomain.prototype.nnlut.NNLutBall +// import framework.balldomain.prototype.nnlut.configs.NNLutConfig // Ball type definitions sealed trait BallType @@ -32,35 +29,32 @@ case object NNLutBallType extends BallType case object TargetBallKey extends Field[BallType](VecBallType) // TargetBall - directly instantiate pre-packaged Ball -class TargetBall(implicit b: CustomBuckyballConfig, p: Parameters) extends Module { - // Create BallDomainParam from global config - val ballParam = BallDomainParam.fromGlobal(b) +class TargetBall(implicit b: GlobalConfig, p: Parameters) extends Module { - // Create Blink IO with parameter - val io = IO(new Blink(ballParam, ballParam.bankEntries, ballParam.bankWidth, ballParam.bankMaskLen)) + // Create BlinkIO with parameter + val io = IO(new BlinkIO(b)) p(TargetBallKey) match { case VecBallType => - val ball = Module(new VecBall(VecConfig.fromBallDomain(ballParam), 0)) + val ball = Module(new VecBall(b, 0)) // Use id=0 for VecBall io <> ball.io case MatrixBallType => - val ball = Module(new MatrixBall(MatrixConfig.fromBallDomain(ballParam), 0)) - io <> ball.io + // val ball = Module(new MatrixBall(MatrixConfig.fromBallDomain(ballParam), 0)) + // io <> ball.io case Im2colBallType => - val ball = Module(new Im2colBall(Im2colConfig.fromBallDomain(ballParam), 0)) - io <> ball.io + // val ball = Module(new Im2colBall(Im2colConfig.fromBallDomain(ballParam), 0)) + // io <> ball.io case TransposeBallType => - val ball = Module(new TransposeBall(TransposeConfig.fromBallDomain(ballParam), 0)) - io <> ball.io + // val ball = Module(new TransposeBall(TransposeConfig.fromBallDomain(ballParam), 0)) + // io <> ball.io case ReluBallType => - val ball = Module(new ReluBall(ReluConfig.fromBallDomain(ballParam), 0)) - io <> ball.io + // val ball = Module(new ReluBall(ReluConfig.fromBallDomain(ballParam), 0)) + // io <> ball.io case NNLutBallType => - val ball = Module(new NNLutBall(NNLutConfig.fromBallDomain(ballParam), 0)) - io <> ball.io + // val ball = Module(new NNLutBall(NNLutConfig.fromBallDomain(ballParam), 0)) + // io <> ball.io case _ => throw new scala.MatchError("TargetBall does not handle this ball type") } - override lazy val desiredName = "TargetBall" } class WithTargetBall(ballType: BallType) @@ -96,11 +90,11 @@ object BallTopMain extends App { } } - implicit val config: CustomBuckyballConfig = examples.CustomBuckyballConfig() - implicit val params: Parameters = new Config(new CustomBallTopConfig(ballType)) + implicit val b: GlobalConfig = GlobalConfig() + implicit val params: Parameters = new Config(new CustomBallTopConfig(ballType)) ChiselStage.emitSystemVerilogFile( - new TargetBall(), + new TargetBall()(b, params), // Remaining parameters passed to firtool firtoolOpts = args.drop(1), args = Array.empty diff --git a/scripts/replace-content.py b/scripts/replace-content.py index 9798b875..e55bc993 100755 --- a/scripts/replace-content.py +++ b/scripts/replace-content.py @@ -7,6 +7,7 @@ # $1 - file to replace text in # $2 - key used to find block of text to replace # $3 - text to fill in block that is replaced +# $4 - position to add if block not found: "head" or "tail" (default: "tail") import re import sys @@ -61,7 +62,11 @@ def CY_INITIALIZE_END_TOKEN(k): fh_content = fh_content.replace(replace_str, inner_contents) if CY_INITIALIZE_START_TOKEN(initialize_comment_key) not in fh_content: - fh_content += "\n%s\n" % inner_contents + position = sys.argv[4] if len(sys.argv) > 4 else "tail" + if position == "head": + fh_content = "%s\n%s" % (inner_contents, fh_content) + else: + fh_content += "\n%s\n" % inner_contents with open(sys.argv[1], "w") as fh: fh.write(fh_content) From e0594f4f9b680b84a6fc4db820af15925ddcecc6 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 30 Dec 2025 21:16:29 +0800 Subject: [PATCH 020/238] [arch] fix: fix lots of bugs to pass compilation --- .../scala/examples/toy/ToyBuckyBall.scala | 51 ++++++-- .../toy/balldomain/bbus/busRegister.scala | 2 +- .../toy/balldomain/emptyball/EmptyBall.scala | 14 +-- .../framework/balldomain/bbus/bbus.scala | 22 +--- .../balldomain/bbus/memrouter/memRouter.scala | 36 ++++++ .../framework/balldomain/blink/baseball.scala | 1 - .../balldomain/configs/BallDomainParam.scala | 3 +- .../framework/balldomain/configs/default.json | 5 +- .../balldomain/prototype/relu/Relu.scala | 7 +- .../relu/configs/ReluBallParam.scala | 2 +- .../prototype/vector/VecLoadUnit.scala | 28 ++--- .../prototype/vector/VecStoreUnit.scala | 10 +- .../vector/configs/VectorBallParam.scala | 2 +- .../balldomain/rs/reservationStation.scala | 12 +- .../framework/core/configs/CoreParam.scala | 5 +- .../scala/framework/core/configs/default.json | 3 +- .../frontend/configs/FrontendParam.scala | 2 +- .../scala/framework/gpdomain/GPDomain.scala | 3 +- .../gpdomain/configs/GpDomainParam.scala | 5 +- .../framework/gpdomain/configs/default.json | 4 +- .../scala/framework/memdomain/MemDomain.scala | 106 +++++------------ .../memdomain/backend/MemManager.scala | 94 ++++++++++----- .../memdomain/backend/accpipe/AccPipe.scala | 109 ++++++++++-------- .../memdomain/backend/accpipe/BankPipe.scala | 58 ---------- .../memdomain/backend/banks/SramBank.scala | 15 ++- .../memdomain/backend/banks/SramIO.scala | 9 +- .../memdomain/configs/MemDomainParam.scala | 2 +- .../framework/memdomain/configs/default.json | 3 +- .../memdomain/frontend/MemController.scala | 87 +++++++++----- .../frontend/outside_channel/MemLoader.scala | 1 + .../frontend/outside_channel/MemStorer.scala | 9 +- .../outside_channel/dma/BBStreamReader.scala | 35 +++--- .../outside_channel/dma/BBStreamWriter.scala | 26 +++-- .../outside_channel/tlb/BBTLBIO.scala | 78 +++++++------ .../outside_channel/tlb/TLBCluster.scala | 2 +- .../memdomain/midend/MemScheduler.scala | 55 ++------- scripts/install-t1.sh | 36 ++++++ 37 files changed, 494 insertions(+), 448 deletions(-) delete mode 100644 arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala create mode 100755 scripts/install-t1.sh diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 736d181f..1b3caf94 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -25,28 +25,44 @@ class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) // the width of core's register file val xLen = p(TileKey).core.xLen - val id_node = TLIdentityNode() + // DMA nodes for read and write paths + val reader_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + name = "bb-dma-reader", + sourceId = freechips.rocketchip.diplomacy.IdRange(0, b.memDomain.dma_n_xacts) + ))))) + + val writer_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + name = "bb-dma-writer", + sourceId = freechips.rocketchip.diplomacy.IdRange(0, b.memDomain.dma_n_xacts) + ))))) + val xbar_node = TLXbar() - xbar_node := TLBuffer() := id_node - xbar_node := TLBuffer() := id_node - id_node := TLWidthWidget(b.memDomain.dma_buswidth / 8) := TLBuffer() := xbar_node + // Connect reader and writer to xbar + xbar_node := TLBuffer() := reader_node + xbar_node := TLBuffer() := writer_node override lazy val module = new ToyBuckyballModule(this) - override val tlNode = id_node + // tlNode connects to mbus (bypassing L1 cache) + // This is where DMA traffic goes + override val tlNode = TLWidthWidget(b.memDomain.dma_buswidth / 8) := TLBuffer() := xbar_node + + // atlNode is not used (set to identity for compatibility) override val atlNode = TLIdentityNode() - val node = tlNode } class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) with HasCoreParameters { import outer.b._ - val edge: TLEdgeOut = outer.id_node.edges.out.head - val b: GlobalConfig = outer.b + val b: GlobalConfig = outer.b + + // Get TileLink edges from reader and writer nodes + val (tl_reader, edge_reader) = outer.reader_node.out(0) + val (tl_writer, edge_writer) = outer.writer_node.out(0) val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) - val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge)) + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) frontend.io.cmd.valid := io.cmd.valid @@ -62,7 +78,18 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w frontend.io.mem_complete_i <> memDomain.io.global_complete_o // PTW connected to MemDomain's TLB (shared TLB has only 1 PTW port) - io.ptw(0) <> memDomain.io.ptw(0) + // Connect all fields except customCSRs which is not supported in our BBTLBPTWIO + io.ptw(0).req <> memDomain.io.ptw(0).req + memDomain.io.ptw(0).resp <> io.ptw(0).resp + memDomain.io.ptw(0).ptbr <> io.ptw(0).ptbr + memDomain.io.ptw(0).hgatp <> io.ptw(0).hgatp + memDomain.io.ptw(0).vsatp <> io.ptw(0).vsatp + memDomain.io.ptw(0).status <> io.ptw(0).status + memDomain.io.ptw(0).hstatus <> io.ptw(0).hstatus + memDomain.io.ptw(0).gstatus <> io.ptw(0).gstatus + memDomain.io.ptw(0).pmp <> io.ptw(0).pmp + // customCSRs is tied off - we don't use custom CSRs in our implementation + memDomain.io.ptw(0).customCSRs := DontCare // TLB exception handling - shared TLB has only 1 exception interface // Set flush input signals @@ -76,6 +103,10 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w ballDomain.bankRead <> memDomain.io.ballDomain.bankRead ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite + // Connect TileLink DMA ports from MemDomain to LazyModule nodes + tl_reader <> memDomain.io.tl_reader + tl_writer <> memDomain.io.tl_writer + io.resp <> frontend.io.resp io.busy := frontend.io.busy io.interrupt := memDomain.io.tlbExp(0).interrupt diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 5a19decd..e4f26570 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -27,7 +27,7 @@ class BBusModule(b: GlobalConfig) // () => new prototype.im2col.Im2colBall(Im2colConfig.fromBallDomain(parameter), 2), // () => new prototype.transpose.TransposeBall(TransposeConfig.fromBallDomain(parameter), 3), // () => new prototype.relu.ReluBall(ReluConfig.fromBallDomain(parameter), 4), - () => new examples.toy.balldomain.emptyball.EmptyBall(b, 5) + () => new examples.toy.balldomain.emptyball.EmptyBall(b, 1) // () => new prototype.transfer.TransferBall(TransferConfig.fromBallDomain(parameter), 6) ) ) {} diff --git a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala index ddbf5d61..85c6c772 100644 --- a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala +++ b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala @@ -23,20 +23,20 @@ class EmptyBall( io.cmdReq.ready := true.B for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).io.req.valid := false.B - io.bankRead(i).io.req.bits.addr := 0.U - io.bankRead(i).io.req.bits.fromDMA := false.B - io.bankRead(i).io.resp.ready := false.B - io.bankRead(i).rob_id := 0.U - io.bankRead(i).bank_id := 0.U + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).rob_id := 0.U + io.bankRead(i).bank_id := 0.U io.bankWrite(i).io.req.valid := false.B io.bankWrite(i).io.req.bits.addr := 0.U io.bankWrite(i).io.req.bits.data := 0.U io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B // Add missing resp.ready io.bankWrite(i).rob_id := 0.U io.bankWrite(i).bank_id := 0.U - io.bankWrite(i).io.req.bits.wmode := false.B } io.status.ready := true.B io.status.valid := io.cmdResp.valid diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 3e4f8173..2b6d33c8 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -22,32 +22,22 @@ class BBusConfigIO(numBalls: Int) extends Bundle { */ @instantiable class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module]) extends Module { - val numBalls = ballGenerators.length - + val numBalls = b.ballDomain.ballNum @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) - + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) - + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) @public - val bankRead = IO(Vec( - b.memDomain.bankNum, - Flipped(new BankRead(b)) - )) - + val bankRead = IO(Vec(b.memDomain.bankNum, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec( - b.memDomain.bankNum, - Flipped(new BankWrite(b)) - )) + val bankWrite = IO(Vec(b.memDomain.bankNum, Flipped(new BankWrite(b)))) // Instantiate all registered Balls // Note: Since Instantiate requires 'new' expression and ballGenerators are functions, // we use Module here. The balls themselves are @instantiable, but when instantiated // from a function generator pattern, we use Module. This is acceptable as the balls // are still properly instantiated and can be used with the hierarchy system. - val balls = ballGenerators.map(gen => gen()) + val balls = ballGenerators.map(gen => Module(gen())) // ----------------------------------------------------------------------------- // cmd router diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 553865a3..80071c9b 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -24,4 +24,40 @@ class MemRouter(val b: GlobalConfig, val numBalls: Int, val bbusChannel: Int) ex }) + // Initialize all output ports to default values + // TODO: Implement actual routing logic + for (i <- 0 until bbusChannel) { + // BankRead outputs + io.bankRead_o(i).io.req.valid := false.B + io.bankRead_o(i).io.req.bits.addr := 0.U + io.bankRead_o(i).io.resp.ready := false.B + io.bankRead_o(i).rob_id := 0.U + io.bankRead_o(i).bank_id := 0.U + + // BankWrite outputs + io.bankWrite_o(i).io.req.valid := false.B + io.bankWrite_o(i).io.req.bits.addr := 0.U + io.bankWrite_o(i).io.req.bits.data := 0.U + io.bankWrite_o(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + io.bankWrite_o(i).io.req.bits.wmode := false.B + io.bankWrite_o(i).io.resp.ready := false.B + io.bankWrite_o(i).rob_id := 0.U + io.bankWrite_o(i).bank_id := 0.U + } + + // Initialize input ready signals + for (i <- 0 until numBalls) { + for (j <- 0 until b.memDomain.bankNum) { + io.bankRead_i(i)(j).io.req.ready := false.B + io.bankRead_i(i)(j).io.resp.valid := false.B + io.bankRead_i(i)(j).io.resp.bits.data := 0.U + + io.bankWrite_i(i)(j).io.req.ready := false.B + io.bankWrite_i(i)(j).io.resp.valid := false.B + io.bankWrite_i(i)(j).io.resp.bits.ok := false.B + } + } + + io.bbusConfig_i.ready := false.B + } diff --git a/arch/src/main/scala/framework/balldomain/blink/baseball.scala b/arch/src/main/scala/framework/balldomain/blink/baseball.scala index 7cfcbc2e..a133233b 100644 --- a/arch/src/main/scala/framework/balldomain/blink/baseball.scala +++ b/arch/src/main/scala/framework/balldomain/blink/baseball.scala @@ -2,7 +2,6 @@ package framework.balldomain.blink import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters // Base trait for Ball devices trait BallRegist { diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala index a6be8950..426af5a6 100644 --- a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -13,6 +13,7 @@ case class BallIdMapping( * BallDomain参数 */ case class BallDomainParam( + ballNum: Int, emptyBallid: Int, ballIdMappings: Seq[BallIdMapping]) @@ -21,7 +22,7 @@ object BallDomainParam { implicit val rw: ReadWriter[BallDomainParam] = macroRW def apply(): BallDomainParam = { - val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/balldomain/configs/default.json").mkString + val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/balldomain/configs/default.json").mkString read[BallDomainParam](jsonStr) } diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 62059e78..52fb4ba7 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,7 +1,8 @@ { - "emptyBallid": 5, + "ballNum": 2, + "emptyBallid": 1, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall"}, - {"ballId": 5, "ballName": "EmptyBall"} + {"ballId": 1, "ballName": "EmptyBall"} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index ec198a0c..697e9935 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -72,10 +72,9 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { // SRAM default assignment for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).req.bits.fromDMA := false.B - io.bankRead(i).resp.ready := false.B + io.bankRead(i).req.valid := false.B + io.bankRead(i).req.bits.addr := 0.U + io.bankRead(i).resp.ready := false.B io.bankWrite(i).req.valid := false.B io.bankWrite(i).req.bits.addr := 0.U diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala index ba1a32b7..3082b8a8 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala @@ -14,7 +14,7 @@ object ReluBallParam { def apply(): ReluBallParam = { val jsonStr = - scala.io.Source.fromFile("arch/src/main/scala/framework/balldomain/prototype/relu/configs/default.json").mkString + scala.io.Source.fromFile("src/main/scala/framework/balldomain/prototype/relu/configs/default.json").mkString read[ReluBallParam](jsonStr) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index e06729a6..61fef36a 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -52,9 +52,8 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // Default assignment for each bank read request for (i <- 0 until b.memDomain.bankNum) { - io.bankReadReq(i).valid := false.B - io.bankReadReq(i).bits.fromDMA := false.B - io.bankReadReq(i).bits.addr := 0.U + io.bankReadReq(i).valid := false.B + io.bankReadReq(i).bits.addr := 0.U } io.ctrl_ld_i.ready := state === idle @@ -82,14 +81,12 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // Send SRAM read request (only when output register is idle) // ----------------------------------------------------------------------------- when(state === busy && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - io.bankReadReq(op1_bank).valid := iter_counter < iter - io.bankReadReq(op1_bank).bits.fromDMA := false.B - io.bankReadReq(op1_bank).bits.addr := op1_addr + iter_counter - - io.bankReadReq(op2_bank).valid := iter_counter < iter - io.bankReadReq(op2_bank).bits.fromDMA := false.B - io.bankReadReq(op2_bank).bits.addr := op2_addr + iter_counter - iter_counter := iter_counter + 1.U + io.bankReadReq(op1_bank).valid := iter_counter < iter + io.bankReadReq(op1_bank).bits.addr := op1_addr + iter_counter + + io.bankReadReq(op2_bank).valid := iter_counter < iter + io.bankReadReq(op2_bank).bits.addr := op2_addr + iter_counter + iter_counter := iter_counter + 1.U } // ----------------------------------------------------------------------------- @@ -129,11 +126,10 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) io.ld_ex_o.bits.iter := 0.U when(state === busy && io.bankReadResp(0).valid) { - iter_counter := iter_counter + 1.U - ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - io.bankReadReq(1).valid := true.B - io.bankReadReq(1).bits.addr := op2_addr + iter_counter - io.bankReadReq(1).bits.fromDMA := false.B + iter_counter := iter_counter + 1.U + ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.bankReadReq(1).valid := true.B + io.bankReadReq(1).bits.addr := op2_addr + iter_counter } when(state === busy && io.bankReadResp(1).valid && RegNext(io.bankReadResp(0).valid)) { io.ld_ex_o.valid := true.B diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 993bf696..83658047 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -67,10 +67,12 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- io.ex_st_i.ready := state === busy io.bankWrite.foreach { acc => - acc.req.valid := false.B - acc.req.bits.addr := 0.U - acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) - acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + acc.req.valid := false.B + acc.req.bits.addr := 0.U + acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) + acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + acc.req.bits.wmode := false.B // Default: direct write mode + acc.resp.ready := false.B // Default: not ready for response } val waddr = wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) when(io.ex_st_i.fire) { diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala index 00756d3f..3da72064 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala @@ -18,7 +18,7 @@ object VectorBallParam { def apply(): VectorBallParam = { val jsonStr = scala.io.Source.fromFile( - "arch/src/main/scala/framework/balldomain/prototype/vector/configs/default.json" + "src/main/scala/framework/balldomain/prototype/vector/configs/default.json" ).mkString read[VectorBallParam](jsonStr) } diff --git a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala index 31719ec4..af09bd9f 100644 --- a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala @@ -20,12 +20,12 @@ class BallRsComplete(b: GlobalConfig) extends Bundle { // Generic Ball domain issue interface - supports dynamic number of Ball devices class BallIssueInterface(b: GlobalConfig) extends Bundle { - val balls = Vec(b.memDomain.bankNum, Decoupled(new BallRsIssue(b))) + val balls = Vec(b.ballDomain.ballNum, Decoupled(new BallRsIssue(b))) } // Generic Ball domain completion interface - supports dynamic number of Ball devices class BallCommitInterface(b: GlobalConfig) extends Bundle { - val balls = Vec(b.memDomain.bankNum, Flipped(Decoupled(new BallRsComplete(b)))) + val balls = Vec(b.ballDomain.ballNum, Flipped(Decoupled(new BallRsComplete(b)))) } // Local Ball reservation station - simple FIFO scheduler @@ -76,7 +76,7 @@ class BallReservationStation(val b: GlobalConfig) extends Module { // Set issue signals for each Ball device // Use configured ball id mappings: index i in issue_o.balls corresponds to ballIdMappings(i).ballId - for (i <- 0 until b.memDomain.bankNum) { + for (i <- 0 until b.ballDomain.ballNum) { if (i < numConfiguredBalls) { val configuredBallId = b.ballDomain.ballIdMappings(i).ballId.U issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === configuredBallId @@ -93,7 +93,7 @@ class BallReservationStation(val b: GlobalConfig) extends Module { // FIFO deq.ready - can only dequeue when target Ball device is ready // Find which index corresponds to the requested ballId fifo.io.deq.ready := VecInit( - (0 until b.memDomain.bankNum).map { idx => + (0 until b.ballDomain.ballNum).map { idx => if (idx < numConfiguredBalls) { val configuredBallId = b.ballDomain.ballIdMappings(idx).ballId.U (headEntry.cmd.bid === configuredBallId) && issue_o.balls(idx).ready @@ -106,10 +106,10 @@ class BallReservationStation(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), b.memDomain.bankNum)) + val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), b.ballDomain.ballNum)) // Connect completion signals from all Ball devices to arbiter - for (i <- 0 until b.memDomain.bankNum) { + for (i <- 0 until b.ballDomain.ballNum) { completeArb.io.in(i).valid := commit_i.balls(i).valid completeArb.io.in(i).bits := commit_i.balls(i).bits.rob_id commit_i.balls(i).ready := completeArb.io.in(i).ready diff --git a/arch/src/main/scala/framework/core/configs/CoreParam.scala b/arch/src/main/scala/framework/core/configs/CoreParam.scala index a5381c5a..4e0386c9 100644 --- a/arch/src/main/scala/framework/core/configs/CoreParam.scala +++ b/arch/src/main/scala/framework/core/configs/CoreParam.scala @@ -10,13 +10,14 @@ case class CoreParam( xLen: Int, vaddrBits: Int, paddrBits: Int, - pgIdxBits: Int) + pgIdxBits: Int, + nPMPs: Int) // Physical Memory Protection entries, typically 8 or 16 object CoreParam { implicit val rw: ReadWriter[CoreParam] = macroRW def apply(): CoreParam = { - val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/core/configs/default.json").mkString + val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/core/configs/default.json").mkString read[CoreParam](jsonStr) } diff --git a/arch/src/main/scala/framework/core/configs/default.json b/arch/src/main/scala/framework/core/configs/default.json index 7e1a21a1..d3ba0329 100644 --- a/arch/src/main/scala/framework/core/configs/default.json +++ b/arch/src/main/scala/framework/core/configs/default.json @@ -3,5 +3,6 @@ "xLen": 64, "vaddrBits": 39, "paddrBits": 56, - "pgIdxBits": 12 + "pgIdxBits": 12, + "nPMPs": 8 } diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index 4892653a..38d08b24 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -13,7 +13,7 @@ object FrontendParam { implicit val rw: ReadWriter[FrontendParam] = macroRW def apply(): FrontendParam = { - val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/frontend/configs/default.json").mkString + val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/frontend/configs/default.json").mkString read[FrontendParam](jsonStr) } diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index 8d73e751..bfe6889f 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -25,7 +25,8 @@ class GpDomain(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- val decoder: Instance[framework.gpdomain.sequencer.decoder.DomainDecoder] = Instantiate(new framework.gpdomain.sequencer.decoder.DomainDecoder(b)) - decoder.io.inst_i <> io.global_issue_i.bits.cmd + // Extract raw_cmd from PostGDCmd + decoder.io.inst_i <> io.global_issue_i.bits.cmd.raw_cmd val decoded = decoder.io.decoded_o io.global_complete_o.valid := io.global_issue_i.valid diff --git a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala index 68122df7..267811ad 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala +++ b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala @@ -5,7 +5,8 @@ import upickle.default._ /** * GpDomain参数 */ -case class GpDomainParam() +case class GpDomainParam( + placeholder: Int) object GpDomainParam { implicit val rw: ReadWriter[GpDomainParam] = macroRW @@ -14,7 +15,7 @@ object GpDomainParam { * 从默认的局部JSON文件加载 */ def apply(): GpDomainParam = { - val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/gpdomain/configs/default.json").mkString + val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/gpdomain/configs/default.json").mkString read[GpDomainParam](jsonStr) } diff --git a/arch/src/main/scala/framework/gpdomain/configs/default.json b/arch/src/main/scala/framework/gpdomain/configs/default.json index 0967ef42..36280ff7 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/default.json +++ b/arch/src/main/scala/framework/gpdomain/configs/default.json @@ -1 +1,3 @@ -{} +{ + "placeholder": 0 +} diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index ce872d24..2fd4736c 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -5,21 +5,11 @@ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import freechips.rocketchip.tile._ import framework.balldomain.blink.{BankRead, BankWrite} -import freechips.rocketchip.tilelink.TLEdgeOut +import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.memdomain.frontend.MemController -import framework.memdomain.frontend.outside_channel.dma.{ - BBReadRequest, - BBReadResponse, - BBStreamReader, - BBStreamReaderParam, - BBStreamWriter, - BBStreamWriterParam, - BBWriteRequest, - BBWriteResponse -} -import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} +import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBPTWIO} import framework.memdomain.midend.MemScheduler import framework.memdomain.backend.MemManager @@ -43,6 +33,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Inside Channel // ------------------------------------------------- // Bank interface for interaction with Ball Domain + // BankRead/BankWrite are used with Flipped at Ball Device side + // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) val ballDomain = new Bundle { val bankRead = Vec(b.memDomain.bankNum, new BankRead(b)) val bankWrite = Vec(b.memDomain.bankNum, new BankWrite(b)) @@ -52,23 +44,13 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ------------------------------------------------- // Outside Channel // ------------------------------------------------- - val dma = new Bundle { - - val read = new Bundle { - val req = Decoupled(new BBReadRequest()) - val resp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) - } - - val write = new Bundle { - val req = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) - val resp = Flipped(Decoupled(new BBWriteResponse)) - } - - } - - val tlb = Vec(2, Flipped(new BBTLBIO(b))) + // PTW and TLB exception interfaces for external connection val ptw = Vec(1, new BBTLBPTWIO(b)) val tlbExp = Vec(1, new BBTLBExceptionIO) + + // TileLink physical connections for DMA + val tl_reader = new TLBundle(edge.bundle) + val tl_writer = new TLBundle(edge.bundle) }) val frontend: Instance[MemController] = Instantiate(new MemController(b)(edge)) @@ -81,63 +63,39 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Global RS interface frontend.io.global_issue_i <> io.global_issue_i frontend.io.global_complete_o <> io.global_complete_o - frontend.io.busy := io.busy - - // DMA interface - frontend.io.intradma <> io.dma + io.busy := frontend.io.busy // TLB interface - frontend.io.tlb <> io.tlb + // Note: frontend.io.tlb is connected internally to DMA modules + // Only PTW and TLB exception interfaces are exposed to outside frontend.io.ptw <> io.ptw frontend.io.tlbExp <> io.tlbExp - // Ball Domain interface (connects to frontend's interdma) - frontend.io.interdma.bankRead <> io.ballDomain.bankRead - frontend.io.interdma.bankWrite <> io.ballDomain.bankWrite + // TileLink physical connections for DMA (Reader/Writer are inside frontend) + io.tl_reader <> frontend.io.tl_reader + io.tl_writer <> frontend.io.tl_writer + + // Ball Domain interface connects directly to midend (Ball devices' read/write requests) + midend.io.frontend.bankRead <> io.ballDomain.bankRead + midend.io.frontend.bankWrite <> io.ballDomain.bankWrite // ------------------------------------------------- // Internal Connection (frontend - midend - backend) // ------------------------------------------------- - // Frontend to Midend: route interdma requests to scheduler - midend.io.frontend.bankRead <> frontend.io.interdma.bankRead - midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite + // Frontend interdma (MemLoader/MemStorer) connects to midend + // MemLoader/MemStorer DMA operations also need to access banks + // For now we directly tie off interdma since ballDomain is the main data path + // TODO: Add multiplexing if interdma also needs bank access + for (i <- 0 until b.memDomain.bankNum) { + frontend.io.interdma.bankRead(i).io.req.ready := false.B + frontend.io.interdma.bankRead(i).io.resp.valid := false.B + frontend.io.interdma.bankRead(i).io.resp.bits := 0.U.asTypeOf(frontend.io.interdma.bankRead(i).io.resp.bits) + + frontend.io.interdma.bankWrite(i).io.req.ready := false.B + frontend.io.interdma.bankWrite(i).io.resp.valid := false.B + frontend.io.interdma.bankWrite(i).io.resp.bits := 0.U.asTypeOf(frontend.io.interdma.bankWrite(i).io.resp.bits) + } // Midend to Backend: route scheduled requests to memory manager midend.io.mem_req <> backend.io.mem_req - - // ------------------------------------------------- - // DMA Modules (Reader and Writer) - Internal instantiation - // ------------------------------------------------- - val readerParam = BBStreamReaderParam( - nXacts = b.memDomain.dma_n_xacts, - beatBits = b.memDomain.dma_buswidth, - maxBytes = b.memDomain.dma_maxbytes, - dataWidth = b.memDomain.dma_buswidth, - tledge = edge - ) - - val writerParam = BBStreamWriterParam( - nXacts = b.memDomain.dma_n_xacts, - beatBits = b.memDomain.dma_buswidth, - maxBytes = b.memDomain.dma_maxbytes, - dataWidth = b.memDomain.dma_buswidth, - tledge = edge - ) - - val reader: Instance[BBStreamReader] = Instantiate(new BBStreamReader(readerParam, b)) - val writer: Instance[BBStreamWriter] = Instantiate(new BBStreamWriter(writerParam, b)) - - // Connect DMA to TLB and interfaces - reader.io.tlb <> io.tlb(1) - writer.io.tlb <> io.tlb(0) - - // Connect DMA to external DMA interface - io.dma.read.req <> reader.io.req - reader.io.resp <> io.dma.read.resp - io.dma.write.req <> writer.io.req - writer.io.resp <> io.dma.write.resp - - // Connect DMA flush signals to TLB exceptions - reader.io.flush := io.tlbExp(0).flush() - writer.io.flush := io.tlbExp(0).flush() } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala b/arch/src/main/scala/framework/memdomain/backend/MemManager.scala index 94e14c9a..08363ad7 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemManager.scala @@ -18,9 +18,9 @@ import framework.memdomain.backend.accpipe.AccPipe * - Assert checks ensure no bank_id conflicts in the same cycle */ class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) - val read = Flipped(new SramReadIO(b)) - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val write = Flipped(new SramWriteIO(b)) // Sender perspective: send write requests + val read = Flipped(new SramReadIO(b)) // Sender perspective: send read requests + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) } @instantiable @@ -28,19 +28,12 @@ class MemManager(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Interface from midend (new architecture) - val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + // Interface from midend - MemManager routes requests to AccPipes + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) }) - // Instantiate bankNum SRAM banks - val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum) { - Instantiate(new SramBank(b)) - } - - // Instantiate bankChannel accumulator pipes (all requests go through AccPipe) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel) { - Instantiate(new AccPipe(b)) - } + val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) // ----------------------------------------------------------------------------- // Request routing: All requests go through AccPipe @@ -75,6 +68,19 @@ class MemManager(val b: GlobalConfig) extends Module { } } + // ----------------------------------------------------------------------------- + // Initialize all AccPipe sram interfaces to default values + // ----------------------------------------------------------------------------- + accPipes.foreach { accPipe => + accPipe.io.sramWrite.req.ready := false.B + accPipe.io.sramWrite.resp.valid := false.B + accPipe.io.sramWrite.resp.bits.ok := false.B + + accPipe.io.sramRead.req.ready := false.B + accPipe.io.sramRead.resp.valid := false.B + accPipe.io.sramRead.resp.bits.data := 0.U + } + // ----------------------------------------------------------------------------- // Bank routing and connection // ----------------------------------------------------------------------------- @@ -84,28 +90,52 @@ class MemManager(val b: GlobalConfig) extends Module { case (bank, bankIdx) => val bank_id = bankIdx.U - // Default: no write request - bank.io.sramWrite.req.valid := false.B + // Aggregate write requests from all AccPipes for this bank + val writeMatches = VecInit(accPipes.map { accPipe => + accPipe.io.sramWrite.req.valid && accPipe.io.busy && (accPipe.io.current_bank_id === bank_id) + }) + val hasWriteReq = writeMatches.asUInt.orR - // Connect write request: find matching AccPipe and connect - accPipes.foreach { accPipe => - val isMatch = accPipe.io.sramWrite.req.valid && accPipe.busy && (accPipe.current_bank_id === bank_id) - when(isMatch) { - bank.io.sramWrite.req <> accPipe.io.sramWrite.req - accPipe.io.sramWrite.resp <> bank.io.sramWrite.resp - } + // Connect write - only one AccPipe can match per bank per cycle (conflict detection ensures this) + when(hasWriteReq) { + val matchedAccPipe = Mux1H(writeMatches.zip(accPipes).map { + case (isMatch, accPipe) => + isMatch -> accPipe.io.sramWrite + }) + bank.io.sramWrite.req.valid := matchedAccPipe.req.valid + bank.io.sramWrite.req.bits := matchedAccPipe.req.bits + matchedAccPipe.req.ready := bank.io.sramWrite.req.ready + matchedAccPipe.resp.valid := bank.io.sramWrite.resp.valid + matchedAccPipe.resp.bits := bank.io.sramWrite.resp.bits + bank.io.sramWrite.resp.ready := matchedAccPipe.resp.ready + }.otherwise { + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) + bank.io.sramWrite.resp.ready := false.B } - // Default: no read request - bank.io.sramRead.req.valid := false.B + // Aggregate read requests from all AccPipes for this bank + val readMatches = VecInit(accPipes.map { accPipe => + accPipe.io.sramRead.req.valid && accPipe.io.busy && (accPipe.io.current_bank_id === bank_id) + }) + val hasReadReq = readMatches.asUInt.orR - // Connect read request: find matching AccPipe and connect - accPipes.foreach { accPipe => - val isMatch = accPipe.io.sramRead.req.valid && accPipe.busy && (accPipe.current_bank_id === bank_id) - when(isMatch) { - bank.io.sramRead.req <> accPipe.io.sramRead.req - accPipe.io.sramRead.resp <> bank.io.sramRead.resp - } + // Connect read - only one AccPipe can match per bank per cycle + when(hasReadReq) { + val matchedAccPipe = Mux1H(readMatches.zip(accPipes).map { + case (isMatch, accPipe) => + isMatch -> accPipe.io.sramRead + }) + bank.io.sramRead.req.valid := matchedAccPipe.req.valid + bank.io.sramRead.req.bits := matchedAccPipe.req.bits + matchedAccPipe.req.ready := bank.io.sramRead.req.ready + matchedAccPipe.resp.valid := bank.io.sramRead.resp.valid + matchedAccPipe.resp.bits := bank.io.sramRead.resp.bits + bank.io.sramRead.resp.ready := matchedAccPipe.resp.ready + }.otherwise { + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) + bank.io.sramRead.resp.ready := false.B } } } diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 6c060c9e..c299375e 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -16,23 +16,28 @@ class AccPipe(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Interface to SramBank - val sramRead = new SramReadIO(b) - val sramWrite = new SramWriteIO(b) - - // Interface from midend - val read = Flipped(new SramReadIO(b)) - val write = Flipped(new SramWriteIO(b)) - - // Control signals - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + // Interface to SramBank - AccPipe sends requests to bank (sender perspective) + val sramRead = Flipped(new SramReadIO(b)) + val sramWrite = Flipped(new SramWriteIO(b)) + + // Interface from midend - AccPipe receives requests (receiver perspective) + val read = new SramReadIO(b) + val write = new SramWriteIO(b) + + // Control and status signals + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val current_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val busy = Output(Bool()) }) - @public + // Internal registers val current_bank_id = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - @public val busy = Reg(Bool()) + // Connect to outputs + io.current_bank_id := current_bank_id + io.busy := busy + // State machine for read-modify-write val s_idle :: s_read :: s_accumulate :: s_write :: Nil = Enum(4) val state = RegInit(s_idle) @@ -57,6 +62,23 @@ class AccPipe(val b: GlobalConfig) extends Module { val acc_data = RegInit(0.U(b.memDomain.bankWidth.W)) val acc_mask = RegInit(VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B))) + // Default values for all outputs + io.write.req.ready := false.B + io.write.resp.valid := false.B + io.write.resp.bits.ok := false.B + + io.read.req.ready := false.B + io.read.resp.valid := false.B + io.read.resp.bits.data := 0.U + + io.sramWrite.req.valid := false.B + io.sramWrite.req.bits := 0.U.asTypeOf(io.sramWrite.req.bits) + io.sramWrite.resp.ready := false.B + + io.sramRead.req.valid := false.B + io.sramRead.req.bits.addr := 0.U + io.sramRead.resp.ready := false.B + // State machine logic when(state === s_idle) { when(io.write.req.valid) { @@ -68,35 +90,31 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramWrite.req.bits.mask := io.write.req.bits.mask io.write.req.ready := io.sramWrite.req.ready - io.write.resp.valid := io.sramWrite.req.ready - io.write.resp.bits.ok := io.sramWrite.req.ready - io.sramWrite.req.ready := io.write.resp.ready + // Forward write response from bank + io.write.resp.valid := io.sramWrite.resp.valid + io.write.resp.bits.ok := io.sramWrite.resp.bits.ok + io.sramWrite.resp.ready := io.write.resp.ready - when(io.sramWrite.req.ready) { + when(io.write.req.fire) { state := s_idle busy := false.B } }.otherwise { // Accumulator mode: start read-modify-write - io.sramRead.req.valid := true.B - io.sramRead.req.bits.addr := io.write.req.bits.addr - io.sramRead.req.bits.fromDMA := false.B - io.write.req.ready := io.sramRead.req.ready - - acc_addr := io.write.req.bits.addr - acc_data := io.write.req.bits.data - acc_mask := io.write.req.bits.mask - - state := s_read + io.sramRead.req.valid := true.B + io.sramRead.req.bits.addr := io.write.req.bits.addr + io.write.req.ready := io.sramRead.req.ready + acc_addr := io.write.req.bits.addr + acc_data := io.write.req.bits.data + acc_mask := io.write.req.bits.mask + state := s_read } }.elsewhen(io.read.req.valid) { // Pure read operation (not accumulation) - io.sramRead.req.valid := io.read.req.valid - io.sramRead.req.bits.addr := io.read.req.bits.addr - io.sramRead.req.bits.fromDMA := false.B - io.read.req.ready := io.sramRead.req.ready - - state := s_read + io.sramRead.req.valid := io.read.req.valid + io.sramRead.req.bits.addr := io.read.req.bits.addr + io.read.req.ready := io.sramRead.req.ready + state := s_read } }.elsewhen(state === s_read) { // Wait for read response @@ -105,10 +123,9 @@ class AccPipe(val b: GlobalConfig) extends Module { // If we got here from a read request, it's a pure read when(io.read.req.valid) { // Pure read: pass data back immediately - io.read.resp.valid := io.sramRead.resp.valid - io.read.resp.bits.data := io.sramRead.resp.bits.data - io.read.resp.bits.fromDMA := io.sramRead.resp.bits.fromDMA - io.sramRead.resp.ready := io.read.resp.ready + io.read.resp.valid := io.sramRead.resp.valid + io.read.resp.bits.data := io.sramRead.resp.bits.data + io.sramRead.resp.ready := io.read.resp.ready when(io.read.resp.ready) { state := s_idle @@ -132,24 +149,14 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramWrite.req.bits.data := acc_data io.sramWrite.req.bits.mask := acc_mask - io.write.resp.valid := io.sramWrite.req.ready - io.write.resp.bits.ok := io.sramWrite.req.ready - io.sramWrite.req.ready := io.write.resp.ready + // Forward write response from bank + io.write.resp.valid := io.sramWrite.resp.valid + io.write.resp.bits.ok := io.sramWrite.resp.bits.ok + io.sramWrite.resp.ready := io.write.resp.ready - when(io.sramWrite.req.ready) { + when(io.sramWrite.req.fire) { state := s_idle busy := false.B } } - - // Tie off unused signals in unused states - when(state === s_read) { - io.sramRead.resp.ready := true.B - }.otherwise { - io.sramRead.resp.ready := false.B - } - - when(state =/= s_write && state =/= s_idle) { - io.sramWrite.req.valid := false.B - } } diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala deleted file mode 100644 index 20220415..00000000 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/BankPipe.scala +++ /dev/null @@ -1,58 +0,0 @@ -package framework.memdomain.backend.accpipe - -import chisel3._ -import chisel3.util._ -import framework.top.GlobalConfig -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import chisel3.experimental.hierarchy.{instantiable, public} - -/** - * BankPipe: Bank Pipeline (直通，非流水线) - * Direct connection to SramBank for read and write operations - * Used for direct write/overwrite operations (non-accumulation) - * Can also serve as a bypass when AccPipe is not fully utilized - */ -@instantiable -class BankPipe(val b: GlobalConfig) extends Module { - - @public - val io = IO(new Bundle { - // Interface to SramBank - val sramRead = new SramReadIO(b) - val sramWrite = new SramWriteIO(b) - - // Interface from midend - val read = Flipped(new SramReadIO(b)) - val write = Flipped(new SramWriteIO(b)) - - // Control signals - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) - }) - - @public - val current_bank_id = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - @public - val busy = Reg(Bool()) - - // Update current_bank_id and busy signal - when(io.write.req.valid || io.read.req.valid) { - current_bank_id := io.bank_id - busy := true.B - }.otherwise { - busy := false.B - } - - // ----------------------------------------------------------------------------- - // Write path (直通) - // ----------------------------------------------------------------------------- - // Direct write: pass through to SramBank - io.sramWrite.req <> io.write.req - io.write.resp <> io.sramWrite.resp - - // ----------------------------------------------------------------------------- - // Read path (直通) - // ----------------------------------------------------------------------------- - // Direct read: pass through to SramBank - io.sramRead.req <> io.read.req - io.read.resp <> io.sramRead.resp -} diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala index dab214a5..64c6c337 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala @@ -12,9 +12,9 @@ import framework.top.GlobalConfig */ @instantiable class SramBank(val b: GlobalConfig) extends Module { - val aligned_to = 8 - val mask_len = (b.memDomain.bankWidth / (aligned_to * 8)) max 1 - val mask_elem = UInt((b.memDomain.bankWidth min (aligned_to * 8)).W) + // Use bankMaskLen from config instead of calculating + val mask_len = b.memDomain.bankMaskLen + val mask_elem = UInt((b.memDomain.bankWidth / mask_len).W) @public val io = IO(new Bundle { @@ -36,9 +36,8 @@ class SramBank(val b: GlobalConfig) extends Module { val ren = io.sramRead.req.fire val rdata = mem.read(raddr, ren) - io.sramRead.resp.valid := RegNext(ren) - io.sramRead.resp.bits.data := RegNext(rdata.asUInt) - io.sramRead.resp.bits.fromDMA := false.B + io.sramRead.resp.valid := RegNext(ren) + io.sramRead.resp.bits.data := RegNext(rdata.asUInt) // ----------------------------------------------------------------------------- // Write path @@ -52,4 +51,8 @@ class SramBank(val b: GlobalConfig) extends Module { io.sramWrite.req.bits.mask ) } + + // Write response - single cycle write + io.sramWrite.resp.valid := RegNext(io.sramWrite.req.fire) + io.sramWrite.resp.bits.ok := RegNext(io.sramWrite.req.fire) } diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala index 93e6356d..b566ee84 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala @@ -8,13 +8,11 @@ import framework.top.GlobalConfig * Generic SRAM interface definitions */ class SramReadReq(val b: GlobalConfig) extends Bundle { - val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) - val fromDMA = Bool() + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) } class SramReadResp(val b: GlobalConfig) extends Bundle { - val data = UInt(b.memDomain.bankWidth.W) - val fromDMA = Bool() + val data = UInt(b.memDomain.bankWidth.W) } class SramReadIO(val b: GlobalConfig) extends Bundle { @@ -35,6 +33,5 @@ class SramWriteIO(val b: GlobalConfig) extends Bundle { } class SramWriteResp(val b: GlobalConfig) extends Bundle { - val ok = Bool() - val fromDMA = Bool() + val ok = Bool() } diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala index 78f14504..de158be5 100644 --- a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -22,7 +22,7 @@ object MemDomainParam { implicit val rw: ReadWriter[MemDomainParam] = macroRW def apply(): MemDomainParam = { - val jsonStr = scala.io.Source.fromFile("arch/src/main/scala/framework/memdomain/configs/default.json").mkString + val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/memdomain/configs/default.json").mkString read[MemDomainParam](jsonStr) } diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index 3bba2e9a..65353590 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -4,8 +4,9 @@ "bankEntries": 128, "bankMaskLen": 16, "tlb_size": 4, + "dma_n_xacts": 8, "dma_maxbytes": 64, - "bankChannel": 8, + "bankChannel": 32, "max_in_flight_mem_reqs": 16, "dma_buswidth": 128, "memAddrLen": 32 diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala b/arch/src/main/scala/framework/memdomain/frontend/MemController.scala index a36e6da1..e67e26c8 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemController.scala @@ -3,10 +3,15 @@ package framework.memdomain.frontend import chisel3._ import chisel3.util._ import freechips.rocketchip.tile._ -import framework.memdomain.frontend.outside_channel.dma.{BBReadRequest, BBReadResponse, BBWriteRequest, BBWriteResponse} +import framework.memdomain.frontend.outside_channel.dma.{ + BBStreamReader, + BBStreamReaderParam, + BBStreamWriter, + BBStreamWriterParam +} import framework.memdomain.frontend.outside_channel.{MemLoader, MemStorer} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} -import freechips.rocketchip.tilelink.TLEdgeOut +import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} @@ -35,30 +40,19 @@ class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) } - // DMA interface - used by Outer DRAM controller - val intradma = new Bundle { - - val read = new Bundle { - val req = Decoupled(new BBReadRequest()) - val resp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) - } - - val write = new Bundle { - val req = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) - val resp = Flipped(Decoupled(new BBWriteResponse)) - } - - } - - // TLB interface - exposed externally for DMA modules (BBStreamReader/BBStreamWriter) - // TLB connection is managed internally, but interface needs to be exposed for external DMA - val tlb = Vec(2, Flipped(new BBTLBIO(b))) + // TLB interfaces for internal DMA modules (Reader/Writer) + // These are NOT exposed to outside - only PTW and TLB exception are exposed // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) val ptw = Vec(1, new BBTLBPTWIO(b)) // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) val tlbExp = Vec(1, new BBTLBExceptionIO) + + // TileLink physical connections for DMA (Reader/Writer) + val tl_reader = new TLBundle(edge.bundle) + val tl_writer = new TLBundle(edge.bundle) + // Busy signal - val busy = Output(Bool()) + val busy = Output(Bool()) }) val memDecoder: Instance[MemDomainDecoder] = Instantiate(new MemDomainDecoder(b)) @@ -66,10 +60,30 @@ class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val memLoader: Instance[MemLoader] = Instantiate(new MemLoader(b)) val memStorer: Instance[MemStorer] = Instantiate(new MemStorer(b)) val pmc: Instance[MemCyclePMC] = Instantiate(new MemCyclePMC(b)) + // TLB cluster - internal TLB management for DMA modules // Supports 2 clients: BBStreamReader (client 1) and BBStreamWriter (client 0) - val tlbCluster = - Instantiate(new BBTLBCluster(b)(edge)) + val tlbCluster = Instantiate(new BBTLBCluster(b)(edge)) + + // DMA Reader and Writer modules - handle actual DMA transfers + val readerParam = BBStreamReaderParam( + nXacts = b.memDomain.dma_n_xacts, + beatBits = b.memDomain.dma_buswidth, + maxBytes = b.memDomain.dma_maxbytes, + dataWidth = b.memDomain.dma_buswidth, + tledge = edge + ) + + val writerParam = BBStreamWriterParam( + nXacts = b.memDomain.dma_n_xacts, + beatBits = b.memDomain.dma_buswidth, + maxBytes = b.memDomain.dma_maxbytes, + dataWidth = b.memDomain.dma_buswidth, + tledge = edge + ) + + val reader: Instance[BBStreamReader] = Instantiate(new BBStreamReader(readerParam, b)) + val writer: Instance[BBStreamWriter] = Instantiate(new BBStreamWriter(writerParam, b)) // ----------------------------------------------------------------------------- // Global RS -> MemDecoder @@ -107,15 +121,24 @@ class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits - // Connect MemLoader and MemStorer to DMA interface - memLoader.io.dmaReq <> io.intradma.read.req - io.intradma.read.resp <> memLoader.io.dmaResp - memStorer.io.dmaReq <> io.intradma.write.req - io.intradma.write.resp <> memStorer.io.dmaResp + // Connect Reader and Writer to MemLoader and MemStorer + memLoader.io.dmaReq <> reader.io.req + reader.io.resp <> memLoader.io.dmaResp + memStorer.io.dmaReq <> writer.io.req + writer.io.resp <> memStorer.io.dmaResp - // TLB connection - internal TLB cluster connected to external DMA modules + // TLB connection - internal TLB cluster connected to DMA modules // Client 0: BBStreamWriter, Client 1: BBStreamReader - io.tlb <> tlbCluster.io.clients + // Insert pipeline registers to break combinational loops + tlbCluster.io.clients(1).req := RegNext(reader.io.tlb.req) + reader.io.tlb.resp := RegNext(tlbCluster.io.clients(1).resp) + + tlbCluster.io.clients(0).req := RegNext(writer.io.tlb.req) + writer.io.tlb.resp := RegNext(tlbCluster.io.clients(0).resp) + + // Connect DMA flush signals to TLB exceptions + reader.io.flush := io.tlbExp(0).flush() + writer.io.flush := io.tlbExp(0).flush() // PTW interface - connect to upper level page table walker io.ptw <> tlbCluster.io.ptw @@ -123,6 +146,10 @@ class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // TLB exception interface - connect to upper level for flush handling tlbCluster.io.exp <> io.tlbExp + // Connect TileLink physical ports from Reader/Writer to external interface + io.tl_reader <> reader.io.tl + io.tl_writer <> writer.io.tl + // Connect MemLoader and MemStorer to MemController's DMA interface memLoader.io.bankWrite <> io.interdma.bankWrite memStorer.io.bankRead <> io.interdma.bankRead diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index b36da430..32772968 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -98,6 +98,7 @@ class MemLoader(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.data := io.dmaResp.bits.data io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) io.bankWrite(i).io.req.bits.wmode := false.B // Load is always overwrite + io.bankWrite(i).io.resp.ready := false.B // Add missing resp.ready io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).bank_id := target_bank } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index d1addf33..0f703cea 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -77,11 +77,10 @@ class MemStorer(val b: GlobalConfig) extends Module { val target_row = sram_count for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) - io.bankRead(i).io.req.bits.addr := target_row - io.bankRead(i).io.req.bits.fromDMA := true.B - io.bankRead(i).rob_id := rob_id_reg - io.bankRead(i).bank_id := target_bank + io.bankRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) + io.bankRead(i).io.req.bits.addr := target_row + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).bank_id := target_bank } // Bank response processing diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala index 6d972021..b9b2bf53 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala @@ -42,9 +42,11 @@ class BBStreamReader(val parameter: BBStreamReaderParam, val b: GlobalConfig) ex val io = IO(new Bundle { val req = Flipped(Decoupled(new BBReadRequest())) val resp = Decoupled(new BBReadResponse(parameter.dataWidth)) - val tlb = new BBTLBIO(b) + val tlb = Flipped(new BBTLBIO(b)) val busy = Output(Bool()) val flush = Input(Bool()) + // TileLink physical connection + val tl = new TLBundle(parameter.tledge.bundle) }) val edge = parameter.tledge @@ -121,37 +123,44 @@ class BBStreamReader(val parameter: BBStreamReaderParam, val b: GlobalConfig) ex translate_q.io.enq <> tlb_q.io.deq translate_q.io.deq.ready := io.tlb.resp.fire || io.tlb.resp.bits.miss - // TileLink connection - using parameterized edge - val tl_a = Wire(Decoupled(get.cloneType)) - tl_a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss - tl_a.bits := translate_q.io.deq.bits.tl_a - tl_a.bits.address := io.tlb.resp.bits.paddr + // TileLink A channel (request) connection + io.tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss + io.tl.a.bits := translate_q.io.deq.bits.tl_a + io.tl.a.bits.address := io.tlb.resp.bits.paddr + translate_q.io.deq.ready := (io.tlb.resp.fire && !io.tlb.resp.bits.miss && io.tl.a.ready) || io.tlb.resp.bits.miss // Iteration counter for tracking number of requests val iter_counter = RegInit(0.U(10.W)) // Table for managing iteration counts val iter_mangage_table = RegInit(VecInit(Seq.fill(16)(0.U(10.W)))) // Iteration count management - update after each request - when(tl_a.fire) { + when(io.tl.a.fire) { iter_counter := iter_counter + 1.U iter_mangage_table(xactId) := iter_counter } - // Response processing - simplified without edge - io.resp.valid := io.tlb.resp.valid && !io.tlb.resp.bits.miss - io.resp.bits.data := DontCare + // TileLink D channel (response) processing + io.tl.d.ready := io.resp.ready + + io.resp.valid := io.tl.d.valid + io.resp.bits.data := io.tl.d.bits.data // Use source as address counter - io.resp.bits.addrcounter := iter_mangage_table(xactId) + io.resp.bits.addrcounter := iter_mangage_table(io.tl.d.bits.source) // Fix last signal: calculate using received byte count // Total byte count after receiving current beat val resp_bytes_end = bytesReceived + beatBytes.U - io.resp.bits.last := io.tlb.resp.valid && !io.tlb.resp.bits.miss && (resp_bytes_end >= req.len) + io.resp.bits.last := io.tl.d.valid && (resp_bytes_end >= req.len) // Update received byte count - when(io.tlb.resp.valid && !io.tlb.resp.bits.miss) { + when(io.tl.d.fire) { bytesReceived := bytesReceived + beatBytes.U } + // Tie off unused TileLink channels + io.tl.b.ready := true.B + io.tl.c.valid := false.B + io.tl.e.valid := false.B + // State machine io.req.ready := state === s_idle io.busy := xactBusy.orR || (state =/= s_idle) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala index c121b534..51ba17c5 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala @@ -40,9 +40,11 @@ class BBStreamWriter(val parameter: BBStreamWriterParam, val b: GlobalConfig) ex val io = IO(new Bundle { val req = Flipped(Decoupled(new BBWriteRequest(parameter.dataWidth))) val resp = Decoupled(new BBWriteResponse) - val tlb = new BBTLBIO(b) + val tlb = Flipped(new BBTLBIO(b)) val busy = Output(Bool()) val flush = Input(Bool()) + // TileLink physical connection + val tl = new TLBundle(parameter.tledge.bundle) }) val edge = parameter.tledge @@ -112,18 +114,24 @@ class BBStreamWriter(val parameter: BBStreamWriterParam, val b: GlobalConfig) ex val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq - translate_q.io.deq.ready := io.tlb.resp.valid || io.tlb.resp.bits.miss + translate_q.io.deq.ready := (io.tlb.resp.fire && !io.tlb.resp.bits.miss && io.tl.a.ready) || io.tlb.resp.bits.miss - // TileLink connection - using parameterized edge - val tl_a = Wire(Decoupled(selected_put.cloneType)) - tl_a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss - tl_a.bits := translate_q.io.deq.bits.tl_a - tl_a.bits.address := io.tlb.resp.bits.paddr + // TileLink A channel (request) connection + io.tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss + io.tl.a.bits := translate_q.io.deq.bits.tl_a + io.tl.a.bits.address := io.tlb.resp.bits.paddr - // Response processing - io.resp.valid := io.tlb.resp.valid && !io.tlb.resp.bits.miss + // TileLink D channel (response) processing + io.tl.d.ready := io.resp.ready + + io.resp.valid := io.tl.d.valid io.resp.bits.done := true.B + // Tie off unused TileLink channels + io.tl.b.ready := true.B + io.tl.c.valid := false.B + io.tl.e.valid := false.B + // State machine io.req.ready := state === s_idle io.busy := xactBusy.orR || (state =/= s_idle) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala index 0cea594d..785fa2e9 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala @@ -4,6 +4,8 @@ import chisel3._ import chisel3.util.{Decoupled, Valid} import chisel3.util.log2Ceil import framework.top.GlobalConfig +import freechips.rocketchip.rocket.{HStatus, MStatus} +import freechips.rocketchip.rocket.constants.MemoryOpConstants // TLB Exception types class TLBExceptions extends Bundle { @@ -12,15 +14,6 @@ class TLBExceptions extends Bundle { val inst = Bool() } -// MStatus - Simplified status register -class BBTLBMStatus(val xLen: Int) extends Bundle { - val prv = UInt(2.W) - val v = Bool() - val mxr = Bool() - val sum = Bool() - val debug = Bool() -} - // TLB Request class BBTLBReq(val lgMaxSize: Int, val vaddrBits: Int, val xLen: Int) extends Bundle { val vaddr = UInt(vaddrBits.W) @@ -29,7 +22,7 @@ class BBTLBReq(val lgMaxSize: Int, val vaddrBits: Int, val xLen: Int) extends Bu val cmd = Bits(5.W) // M_SZ = 5 val prv = UInt(2.W) // PRV.SZ = 2 val v = Bool() - val status = new BBTLBMStatus(xLen) + val status = new MStatus } // TLB Response @@ -118,28 +111,37 @@ class BBTLBPTWResp( val gpa_is_pte = Bool() } -// HStatus - Simplified hypervisor status -class BBTLBHStatus extends Bundle { - val vsxl = UInt(2.W) - val vtsr = Bool() - val vtw = Bool() - val vtvm = Bool() - val vgein = UInt(6.W) - val hu = Bool() +// Simplified CustomCSR IO wrapper - without Parameters dependency +class BBCustomCSRIO(val xLen: Int) extends Bundle { + val ren = Output(Bool()) + val wen = Output(Bool()) + val wdata = Output(UInt(xLen.W)) + val value = Output(UInt(xLen.W)) + val stall = Input(Bool()) + val set = Input(Bool()) + val sdata = Input(UInt(xLen.W)) +} + +// Simplified CustomCSRs Bundle - matches rocket-chip interface without Parameters +class BBCustomCSRs(val xLen: Int) extends Bundle { + // Empty by default - no custom CSRs defined + val csrs = Vec(0, new BBCustomCSRIO(xLen)) } -// PMP - Simplified Physical Memory Protection -class BBTLBPMP(val paddrBits: Int) extends Bundle { +// Simplified PMP - without Parameters dependency +class BBPMP(val paddrBits: Int) extends Bundle { val cfg = new Bundle { - val l = Bool() - val a = UInt(2.W) - val x = Bool() - val w = Bool() - val r = Bool() + val l = Bool() + val res = UInt(2.W) // Reserved field + val a = UInt(2.W) + val x = Bool() + val w = Bool() + val r = Bool() } - val addr = UInt((paddrBits - 2).W) // Assuming lgAlign = 2 + val addr = UInt((paddrBits - 2).W) + val mask = UInt(paddrBits.W) } // PTW IO @@ -149,18 +151,18 @@ class BBTLBPTWIO(val b: GlobalConfig) extends Bundle { val pgIdxBits = b.core.pgIdxBits val xLen = b.core.xLen val pgLevels = if (xLen == 32) 2 else 4 // Simplified: assume SV39 for 64-bit - val nPMPs = 16 // Fixed size, can be parameterized later - - val req = Decoupled(Valid(new BBTLBPTWReq(vaddrBits, pgIdxBits))) - val resp = Flipped(Valid(new BBTLBPTWResp(vaddrBits, paddrBits, pgIdxBits, pgLevels))) - val ptbr = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) - val hgatp = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) - val vsatp = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) - val status = Input(new BBTLBMStatus(xLen)) - val hstatus = Input(new BBTLBHStatus()) - val gstatus = Input(new BBTLBMStatus(xLen)) - val pmp = Input(Vec(nPMPs, new BBTLBPMP(paddrBits))) - // Note: customCSRs removed - not needed for our implementation + val nPMPs = b.core.nPMPs + + val req = Decoupled(Valid(new BBTLBPTWReq(vaddrBits, pgIdxBits))) + val resp = Flipped(Valid(new BBTLBPTWResp(vaddrBits, paddrBits, pgIdxBits, pgLevels))) + val ptbr = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) + val hgatp = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) + val vsatp = Input(new BBTLBPTBR(paddrBits, pgIdxBits, xLen)) + val status = Input(new MStatus) + val hstatus = Input(new HStatus) + val gstatus = Input(new MStatus) + val pmp = Input(Vec(nPMPs, new BBPMP(paddrBits))) + val customCSRs = Flipped(new BBCustomCSRs(xLen)) } // TLB Client IO (used in TLBCluster) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala index 7d3a3ed2..b666a993 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala @@ -19,7 +19,7 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo @public val io = IO(new Bundle { - val clients = Flipped(Vec(nClients, new BBTLBIO(b))) + val clients = Vec(nClients, new BBTLBIO(b)) val ptw = Vec(1, new BBTLBPTWIO(b)) // Shared TLB has only 1 PTW port val exp = Vec(1, new BBTLBExceptionIO) // Shared TLB has only 1 exception interface }) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala b/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala index d4bdc683..046a3270 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala @@ -20,13 +20,13 @@ class MemScheduler(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Input from frontend (MemController) + // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { - val bankRead = Vec(b.memDomain.bankNum, Flipped(new BankRead(b))) - val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) + val bankRead = Vec(b.memDomain.bankNum, new BankRead(b)) + val bankWrite = Vec(b.memDomain.bankNum, new BankWrite(b)) } - // Output to backend (MemManager) + // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) }) @@ -35,49 +35,14 @@ class MemScheduler(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Simple mapping: each channel handles requests for a specific bank // Channel ch handles bank (ch % bankNum) + // Since bankChannel == bankNum (both 32), this is a 1:1 mapping for (ch <- 0 until b.memDomain.bankChannel) { - val targetBank = (ch % b.memDomain.bankNum).U - val bankIdx = ch % b.memDomain.bankNum + val bankIdx = ch % b.memDomain.bankNum - // Default: no request - io.mem_req(ch).write.req.valid := false.B - io.mem_req(ch).read.req.valid := false.B - io.mem_req(ch).bank_id := targetBank - - // Connect write request - val writeValid = io.frontend.bankWrite(bankIdx).io.req.valid && - (io.frontend.bankWrite(bankIdx).bank_id === targetBank) - when(writeValid) { - io.mem_req(ch).write.req.valid := io.frontend.bankWrite(bankIdx).io.req.valid - io.mem_req(ch).write.req.bits := io.frontend.bankWrite(bankIdx).io.req.bits - io.frontend.bankWrite(bankIdx).io.req.ready := io.mem_req(ch).write.req.ready - io.frontend.bankWrite(bankIdx).io.resp.valid := io.mem_req(ch).write.resp.valid - io.frontend.bankWrite(bankIdx).io.resp.bits := io.mem_req(ch).write.resp.bits - io.mem_req(ch).write.resp.ready := io.frontend.bankWrite(bankIdx).io.resp.ready - io.mem_req(ch).write.req.bits.wmode := io.frontend.bankWrite(bankIdx).io.req.bits.wmode - io.mem_req(ch).bank_id := io.frontend.bankWrite(bankIdx).bank_id - }.otherwise { - io.frontend.bankWrite(bankIdx).io.req.ready := false.B - io.frontend.bankWrite(bankIdx).io.resp.valid := false.B - io.frontend.bankWrite(bankIdx).io.resp.ready := true.B - } - - // Connect read request - val readValid = io.frontend.bankRead(bankIdx).io.req.valid && - (io.frontend.bankRead(bankIdx).bank_id === targetBank) - when(readValid) { - io.mem_req(ch).read.req.valid := io.frontend.bankRead(bankIdx).io.req.valid - io.mem_req(ch).read.req.bits := io.frontend.bankRead(bankIdx).io.req.bits - io.frontend.bankRead(bankIdx).io.req.ready := io.mem_req(ch).read.req.ready - io.frontend.bankRead(bankIdx).io.resp.valid := io.mem_req(ch).read.resp.valid - io.frontend.bankRead(bankIdx).io.resp.bits := io.mem_req(ch).read.resp.bits - io.mem_req(ch).read.resp.ready := io.frontend.bankRead(bankIdx).io.resp.ready - io.mem_req(ch).bank_id := io.frontend.bankRead(bankIdx).bank_id - }.otherwise { - io.frontend.bankRead(bankIdx).io.req.ready := false.B - io.frontend.bankRead(bankIdx).io.resp.valid := false.B - io.frontend.bankRead(bankIdx).io.resp.ready := true.B - } + // Direct 1:1 connection + io.mem_req(ch).write <> io.frontend.bankWrite(bankIdx).io + io.mem_req(ch).read <> io.frontend.bankRead(bankIdx).io + io.mem_req(ch).bank_id := io.frontend.bankWrite(bankIdx).bank_id } } diff --git a/scripts/install-t1.sh b/scripts/install-t1.sh new file mode 100755 index 00000000..fede6ba7 --- /dev/null +++ b/scripts/install-t1.sh @@ -0,0 +1,36 @@ +#!/bin/bash + +# exit script if any command fails +set -e +set -o pipefail + +BBDIR=$(git rev-parse --show-toplevel) +T1DIR=${BBDIR}/arch/thirdparty/t1 + +source ${BBDIR}/scripts/utils.sh + +cd ${BBDIR} +source ${BBDIR}/env.sh + +if ! cargo --version > /dev/null 2>&1; then + echo "cargo is not installed, this shoule be installed at the install-doc step" + exit 1 +fi + +# To avoid the Buckyball project requiring root privileges, +# we opted for the slightly more cumbersome nix-user-chroot installation. +cargo install nix-user-chroot +mkdir -p -m 0755 ~/.nix +curl -L https://nixos.org/nix/install -o /tmp/nix-install.sh +nix-user-chroot ~/.nix bash /tmp/nix-install.sh + +# if you see the following error +# error: filesystem error: read_symlink: Invalid argument [/home/xxxx/.nix-profile] +# this means you may repeated the execution of this Nix installation. + + +# enable nix-command and flakes +nix-user-chroot ~/.nix bash -c 'mkdir -p ~/.config/nix && echo "experimental-features = nix-command flakes" > ~/.config/nix/nix.conf' +replace_content ${BBDIR}/env.sh install-nix "if [ -z \"\$IN_NIX_ENV\" ] && ! command -v nix > /dev/null 2>&1; then + IN_NIX_ENV=1 nix-user-chroot ~/.nix ${SHELL} -c \"source ${BBDIR}/env.sh && ${SHELL}\" +fi" "head" From cce29a9474222a19c22b7cdd3dcce539d513ff49 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 1 Jan 2026 18:55:00 +0800 Subject: [PATCH 021/238] [arch] feat: add common Router --- arch/src/main/scala/Util/README.md | 107 ------------------ .../scala/examples/toy/balldomain/DISA.scala | 26 ++--- .../toy/balldomain/DomainDecoder.scala | 19 +--- .../framework/balldomain/bbus/bbus.scala | 2 +- .../balldomain/bbus/cmdrouter/CmdRouter.scala | 10 +- .../balldomain/bbus/memrouter/memRouter.scala | 12 +- .../framework/balldomain/blink/baseball.scala | 1 - .../framework/balldomain/blink/blink.scala | 7 +- .../balldomain/configs/BallDomainParam.scala | 3 +- .../framework/balldomain/configs/default.json | 3 +- .../balldomain/prototype/relu/Relu.scala | 1 - .../balldomain/prototype/relu/ReluBall.scala | 6 - .../balldomain/prototype/vector/VecUnit.scala | 1 - .../scala/framework/balldomain/rs/rob.scala | 9 -- .../builtin/pipeline}/Pipeline.scala | 2 +- .../framework/builtin/router/Router.scala | 36 ++++++ .../framework/{ => builtin}/utils/Util.scala | 2 +- .../sequencer/decoder/DomainDecoder.scala | 2 - .../scala/framework/memdomain/MemDomain.scala | 20 ++-- .../main/scala/framework/memdomain/README.md | 4 +- .../{MemManager.scala => MemBackend.scala} | 4 +- ...{MemController.scala => MemFrontend.scala} | 35 ++---- .../frontend/outside_channel/dma/README.md | 10 +- ...BStreamReader.scala => StreamReader.scala} | 28 ++--- ...BStreamWriter.scala => StreamWriter.scala} | 31 ++--- .../{MemScheduler.scala => MemMidend.scala} | 6 +- .../main/scala/sims/verify/TargetConfig.scala | 4 - .../scala/sims/verilator/TargetConfig.scala | 4 - 28 files changed, 120 insertions(+), 275 deletions(-) delete mode 100644 arch/src/main/scala/Util/README.md rename arch/src/main/scala/{Util => framework/builtin/pipeline}/Pipeline.scala (98%) create mode 100644 arch/src/main/scala/framework/builtin/router/Router.scala rename arch/src/main/scala/framework/{ => builtin}/utils/Util.scala (99%) rename arch/src/main/scala/framework/memdomain/backend/{MemManager.scala => MemBackend.scala} (98%) rename arch/src/main/scala/framework/memdomain/frontend/{MemController.scala => MemFrontend.scala} (85%) rename arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/{BBStreamReader.scala => StreamReader.scala} (91%) rename arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/{BBStreamWriter.scala => StreamWriter.scala} (85%) rename arch/src/main/scala/framework/memdomain/midend/{MemScheduler.scala => MemMidend.scala} (91%) diff --git a/arch/src/main/scala/Util/README.md b/arch/src/main/scala/Util/README.md deleted file mode 100644 index 17a5e607..00000000 --- a/arch/src/main/scala/Util/README.md +++ /dev/null @@ -1,107 +0,0 @@ -# Buckyball Utility Library - -## Overview - -This directory contains general utility functions and helper modules in the Buckyball framework, primarily providing reusable hardware design components. Located at `arch/src/main/scala/Util`, it serves as the base utility layer throughout the architecture, providing common hardware building blocks for other modules. - -Main functionality includes: -- **Pipeline**: Pipeline control and management tools -- Common hardware design pattern implementations - -## Code Structure - -``` -Util/ -└── Pipeline.scala - Pipeline control implementation -``` - -### File Dependencies - -**Pipeline.scala** (Base utility layer) -- Provides general pipeline control logic -- Referenced by other modules requiring pipeline functionality -- Implements standard pipeline interfaces and control signals - -## Module Description - -### Pipeline.scala - -**Main functionality**: Provides general pipeline control and management functionality - -**Key components**: - -```scala -class Pipeline extends Module { - val io = IO(new Bundle { - val flush = Input(Bool()) - val stall = Input(Bool()) - val valid_in = Input(Bool()) - val ready_out = Output(Bool()) - val valid_out = Output(Bool()) - }) - - // Pipeline control logic - val pipeline_valid = RegInit(false.B) - - when(io.flush) { - pipeline_valid := false.B - }.elsewhen(!io.stall) { - pipeline_valid := io.valid_in - } - - io.ready_out := !io.stall - io.valid_out := pipeline_valid && !io.flush -} -``` - -**Pipeline control signals**: -- **flush**: Pipeline flush signal, clears all pipeline stages -- **stall**: Pipeline stall signal, maintains current state -- **valid_in**: Input data valid signal -- **ready_out**: Ready to receive new data signal -- **valid_out**: Output data valid signal - -**Inputs/Outputs**: -- Input: Control signals (flush, stall) and data valid signal -- Output: Pipeline state and data valid indication -- Edge cases: flush has higher priority than stall, ensuring correct pipeline behavior - -**Dependencies**: Chisel3 base library, standard Module and Bundle interfaces - -## Usage - -### Usage - -**Integrating pipeline control**: -```scala -class MyModule extends Module { - val pipeline = Module(new Pipeline) - - // Connect control signals - pipeline.io.flush := flush_condition - pipeline.io.stall := stall_condition - pipeline.io.valid_in := input_valid - - // Use pipeline output - val output_enable = pipeline.io.valid_out -} -``` - -### Design Patterns - -**Pipeline cascading**: -- Supports cascaded connection of multi-stage pipelines -- Provides standard ready/valid handshake protocol -- Ensures correctness and timing of data flow - -**Backpressure handling**: -- Implements standard backpressure propagation mechanism -- Supports pause and resume of upstream modules -- Guarantees no data loss or duplication - -### Notes - -1. **Timing constraints**: flush signal should be asserted synchronously at clock rising edge -2. **Reset behavior**: Pipeline should clear all valid bits on reset -3. **Combinational logic**: ready signal is combinational logic, avoid timing path issues -4. **Extensibility**: Design supports parameterized pipeline depth and data width diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index ec5575e9..01bff42c 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -4,17 +4,17 @@ import chisel3._ import chisel3.util._ object DISA { - val BB_BBFP_MUL = BitPat("b0011010") // 26 - val MATMUL_WS = BitPat("b0011011") // 27 - val MATMUL_WARP16_BITPAT = BitPat("b0100000") // 32 - val IM2COL = BitPat("b0100001") // 33 - val TRANSPOSE = BitPat("b0100010") // 34 - val RELU = BitPat("b0100110") // 38 - val BBUS_CONFIG = BitPat("b0100111") // 39 - val NNLUT = BitPat("b0101000") // 40 - val SNN = BitPat("b0101001") // 41 - val ABFT_SYSTOLIC = BitPat("b0101010") // 42 - val CONV = BitPat("b0101011") // 43 - val CIM = BitPat("b0101100") // 44 - val TRANSFER = BitPat("b0101101") // 45 + val BB_BBFP_MUL = BitPat("b0011010") // 26 + val MATMUL_WS = BitPat("b0011011") // 27 + val MATMUL_WARP16 = BitPat("b0100000") // 32 + val IM2COL = BitPat("b0100001") // 33 + val TRANSPOSE = BitPat("b0100010") // 34 + val RELU = BitPat("b0100110") // 38 + val CONCAT = BitPat("b0100111") // 39 + val NNLUT = BitPat("b0101000") // 40 + val SNN = BitPat("b0101001") // 41 + val ABFT_SYSTOLIC = BitPat("b0101010") // 42 + val CONV = BitPat("b0101011") // 43 + val CIM = BitPat("b0101100") // 44 + val TRANSFER = BitPat("b0101101") // 45 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index a2ba9970..0e70013e 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -78,19 +78,12 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { func7, ball_default_decode, Array( - MATMUL_WARP16_BITPAT -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), - BB_BBFP_MUL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 1.U, rs2(63, 16)), - MATMUL_WS -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 1.U, rs2(63, 16)), - IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), - TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), - RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 4.U, rs2(63, 16)), - BBUS_CONFIG -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), - NNLUT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 31.U, rs2(63, 16)), - SNN -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 7.U, rs2(63, 16)), - ABFT_SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 8.U, rs2(63, 16)), - CONV -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 9.U, rs2(63, 16)), - CIM -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 10.U, rs2(63, 16)), - TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) + MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), + IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), + TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), + RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 4.U, rs2(63, 16)), + CONCAT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), + TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) ) ) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 2b6d33c8..77664c8b 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -69,7 +69,7 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- - val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b, numBalls, b.memDomain.bankChannel)) + val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b)) memoryrouter.io.bbusConfig_i <> cmdRouter.io.bbusConfig_o // Direct connection from balls to memory router (no ToVirtualLine) diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala index 6766e152..0c656a0e 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala @@ -13,11 +13,12 @@ class CmdRouter(b: GlobalConfig, numBalls: Int) extends Module { @public val io = IO(new Bundle { - val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b)))) - val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(b)))) + val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b)))) + val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(b)))) + val cmdReq_o = Decoupled(new BallRsIssue(b)) + val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete(b))) + val ballIdle = Input(Vec(numBalls, Bool())) - val cmdReq_o = Decoupled(new BallRsIssue(b)) - val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete(b))) val bbusConfig_o = Decoupled(new BBusConfigIO(numBalls)) }) @@ -34,6 +35,7 @@ class CmdRouter(b: GlobalConfig, numBalls: Int) extends Module { io.bbusConfig_o.bits.src_bid := 0.U io.bbusConfig_o.bits.dst_bid := 0.U io.bbusConfig_o.bits.set := false.B + when(io.cmdReq_i(b.ballDomain.emptyBallid).valid) { io.bbusConfig_o.valid := true.B io.bbusConfig_o.bits.src_bid := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(5, 0) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 80071c9b..0c70d844 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -8,33 +8,28 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.top.GlobalConfig @instantiable -class MemRouter(val b: GlobalConfig, val numBalls: Int, val bbusChannel: Int) extends Module { +class MemRouter(val b: GlobalConfig) extends Module { + val bbusChannel = b.ballDomain.bbusChannel + val numBalls = b.ballDomain.ballNum @public val io = IO(new Bundle { - val bankRead_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankRead(b))) val bankWrite_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankWrite(b))) val bbusConfig_i = Flipped(Decoupled(new BBusConfigIO(numBalls))) - // Output: bbusChannel channels to MemDomain frontend val bankRead_o = Vec(bbusChannel, Flipped(new BankRead(b))) val bankWrite_o = Vec(bbusChannel, Flipped(new BankWrite(b))) - }) - // Initialize all output ports to default values - // TODO: Implement actual routing logic for (i <- 0 until bbusChannel) { - // BankRead outputs io.bankRead_o(i).io.req.valid := false.B io.bankRead_o(i).io.req.bits.addr := 0.U io.bankRead_o(i).io.resp.ready := false.B io.bankRead_o(i).rob_id := 0.U io.bankRead_o(i).bank_id := 0.U - // BankWrite outputs io.bankWrite_o(i).io.req.valid := false.B io.bankWrite_o(i).io.req.bits.addr := 0.U io.bankWrite_o(i).io.req.bits.data := 0.U @@ -45,7 +40,6 @@ class MemRouter(val b: GlobalConfig, val numBalls: Int, val bbusChannel: Int) ex io.bankWrite_o(i).bank_id := 0.U } - // Initialize input ready signals for (i <- 0 until numBalls) { for (j <- 0 until b.memDomain.bankNum) { io.bankRead_i(i)(j).io.req.ready := false.B diff --git a/arch/src/main/scala/framework/balldomain/blink/baseball.scala b/arch/src/main/scala/framework/balldomain/blink/baseball.scala index a133233b..efe51a34 100644 --- a/arch/src/main/scala/framework/balldomain/blink/baseball.scala +++ b/arch/src/main/scala/framework/balldomain/blink/baseball.scala @@ -3,7 +3,6 @@ package framework.balldomain.blink import chisel3._ import chisel3.util._ -// Base trait for Ball devices trait BallRegist { def Blink: BlinkIO def ballId: UInt diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index f7eac718..6269a37f 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -21,16 +21,14 @@ class Status extends Bundle { // BankRead with rob_id, bank_id class BankRead(val b: GlobalConfig) extends Bundle { val io = new SramReadIO(b) - // Input because the outer layer has Flipped val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) } // BankWrite with rob_id, bank_id -// wmode is in SramWriteIO.io.req.bits.wmode: true = accumulate (累加), false = overwrite (覆盖) +// wmode is in SramWriteIO.io.req.bits.wmode: true = accumulate, false = overwrite class BankWrite(val b: GlobalConfig) extends Bundle { val io = new SramWriteIO(b) - // Input because the outer layer has Flipped val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) } @@ -44,14 +42,11 @@ class BlinkIO(b: GlobalConfig) extends Bundle { val status = new Status } -// Standard interface for Ball devices -// bankEntries, bankWidth, bankMaskLen come from MemDomain, not BallDomain @instantiable class Blink(b: GlobalConfig) extends Module { @public val io = IO(new BlinkIO(b)) - // Convenience aliases for backward compatibility def cmdReq: DecoupledIO[BallRsIssue] = io.cmdReq def cmdResp: DecoupledIO[BallRsComplete] = io.cmdResp def bankRead: Vec[BankRead] = io.bankRead diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala index 426af5a6..20028956 100644 --- a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -15,7 +15,8 @@ case class BallIdMapping( case class BallDomainParam( ballNum: Int, emptyBallid: Int, - ballIdMappings: Seq[BallIdMapping]) + ballIdMappings: Seq[BallIdMapping], + bbusChannel: Int) object BallDomainParam { implicit val ballIdMappingRW: ReadWriter[BallIdMapping] = macroRW diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 52fb4ba7..1e557308 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -4,5 +4,6 @@ "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall"}, {"ballId": 1, "ballName": "EmptyBall"} - ] + ], + "bbusChannel": 10 } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 697e9935..c3b0eb32 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -14,7 +14,6 @@ import framework.balldomain.prototype.relu.configs.ReluBallParam @instantiable class PipelinedRelu(val b: GlobalConfig) extends Module { - // Get parameters from ball's own config JSON file val ballConfig = ReluBallParam() val InputNum = ballConfig.InputNum val inputWidth = ballConfig.inputWidth diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala index f1b99d73..a896b9c1 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala @@ -3,7 +3,6 @@ package framework.balldomain.prototype.relu import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters import framework.balldomain.blink.{BallRegist, BlinkIO} import framework.balldomain.prototype.relu.PipelinedRelu import framework.top.GlobalConfig @@ -19,17 +18,13 @@ class ReluBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { val io = IO(new BlinkIO(b)) val ballId = id.U - // Satisfy BallRegist requirements def Blink: BlinkIO = io - // Instantiate PipelinedRelu computation unit private val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(b)) - // Connect command interface reluUnit.io.cmdReq <> io.cmdReq reluUnit.io.cmdResp <> io.cmdResp - // Connect Bank read/write interface for (i <- 0 until b.memDomain.bankNum) { reluUnit.io.bankRead(i) <> io.bankRead(i).io io.bankRead(i).rob_id := io.cmdReq.bits.rob_id @@ -40,7 +35,6 @@ class ReluBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { io.bankWrite(i).io.req.bits.wmode := false.B // ReluBall uses overwrite mode } - // Pass through status signals io.status <> reluUnit.io.status } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index e0045334..55b82f1f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -14,7 +14,6 @@ import framework.balldomain.prototype.vector.configs.VectorBallParam @instantiable class VecUnit(val b: GlobalConfig) extends Module { - // Get parameters from ball's own config JSON file val ballConfig = VectorBallParam() val InputNum = ballConfig.lane val inputWidth = ballConfig.inputWidth diff --git a/arch/src/main/scala/framework/balldomain/rs/rob.scala b/arch/src/main/scala/framework/balldomain/rs/rob.scala index ad75bac8..37d2e0ca 100644 --- a/arch/src/main/scala/framework/balldomain/rs/rob.scala +++ b/arch/src/main/scala/framework/balldomain/rs/rob.scala @@ -148,15 +148,6 @@ class ROB(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Instruction commit - commit all completed instructions out-of-order // ----------------------------------------------------------------------------- - // When head instruction completes, automatically commit and move head pointer - // when(robValid(headPtr) && robComplete(headPtr)) { - // robValid(headPtr) := false.B - // robIssued(headPtr) := false.B - // robComplete(headPtr) := false.B - // headPtr := Mux(tailPtr === (parameter.rob_entries - 1).U, 0.U, tailPtr + 1.U) - // } // Sequential commit version - - // Commit all completed instructions for (i <- 0 until b.frontend.rob_entries) { when(robValid(i.U) && robComplete(i.U)) { robValid(i.U) := false.B diff --git a/arch/src/main/scala/Util/Pipeline.scala b/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala similarity index 98% rename from arch/src/main/scala/Util/Pipeline.scala rename to arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala index 55b0aded..783612bb 100644 --- a/arch/src/main/scala/Util/Pipeline.scala +++ b/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala @@ -1,4 +1,4 @@ -package Util +package framework.builtin.pipeline import chisel3._ import chisel3.util._ diff --git a/arch/src/main/scala/framework/builtin/router/Router.scala b/arch/src/main/scala/framework/builtin/router/Router.scala new file mode 100644 index 00000000..07900dc1 --- /dev/null +++ b/arch/src/main/scala/framework/builtin/router/Router.scala @@ -0,0 +1,36 @@ +package framework.builtin.router + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} + +/** + * Router: + * + * Input: valid signals for each input channel + * Output: source input channel ID for each output channel + */ +@instantiable +class Router(val numInputs: Int, val numOutputs: Int) extends Module { + val inputChannelIdWidth = log2Ceil(numInputs) + val outputChannelIdWidth = log2Ceil(numOutputs) + + @public + val io = IO(new Bundle { + val in = Vec(numInputs, Bool()) + val out = Vec(numOutputs, Decoupled(UInt(inputChannelIdWidth.W))) + }) + + // For each output channel, if ready, select an input with priority + for (outIdx <- 0 until numOutputs) { + // Count how many inputs are valid + val numValidInputs = PopCount(io.in) + + // Select one input with priority from all valid inputs + val selectedIdx = PriorityEncoder(io.in) + val hasValidInput = numValidInputs > 0.U + + io.out(outIdx).valid := hasValidInput && io.out(outIdx).ready + io.out(outIdx).bits := selectedIdx.asUInt.asTypeOf(io.out(outIdx).bits.cloneType) + } +} diff --git a/arch/src/main/scala/framework/utils/Util.scala b/arch/src/main/scala/framework/builtin/utils/Util.scala similarity index 99% rename from arch/src/main/scala/framework/utils/Util.scala rename to arch/src/main/scala/framework/builtin/utils/Util.scala index 77914c24..e0fd4dca 100644 --- a/arch/src/main/scala/framework/utils/Util.scala +++ b/arch/src/main/scala/framework/builtin/utils/Util.scala @@ -1,4 +1,4 @@ -package framework.utils +package framework.builtin.utils import chisel3._ import chisel3.util._ diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala index eb34d7e1..23239b0d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala @@ -13,12 +13,10 @@ import chisel3.experimental.hierarchy.{instantiable, public} */ object DomainDecoderParameter { - // Get all RVV instructions from our local database lazy val allInstructions: Seq[InstructionEncoding.Instruction] = { RVVInstructions.allInstructions } - // Create decoder parameter using our local instruction types lazy val decoderParam: DecoderParam = DecoderParam( fpuEnable = true, // Enable floating-point vector instructions zvbbEnable = true, // Enable vector bit manipulation diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 2fd4736c..82376170 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -7,13 +7,12 @@ import freechips.rocketchip.tile._ import framework.balldomain.blink.{BankRead, BankWrite} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.top.GlobalConfig -import framework.memdomain.frontend.MemController +import framework.memdomain.frontend.MemFrontend import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBPTWIO} - -import framework.memdomain.midend.MemScheduler -import framework.memdomain.backend.MemManager -import framework.top.GlobalConfig +import framework.memdomain.midend.MemMidend +import framework.memdomain.backend.MemBackend @instantiable class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { @@ -53,9 +52,9 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tl_writer = new TLBundle(edge.bundle) }) - val frontend: Instance[MemController] = Instantiate(new MemController(b)(edge)) - val midend: Instance[MemScheduler] = Instantiate(new MemScheduler(b)) - val backend: Instance[MemManager] = Instantiate(new MemManager(b)) + val frontend: Instance[MemFrontend] = Instantiate(new MemFrontend(b)(edge)) + val midend: Instance[MemMidend] = Instantiate(new MemMidend(b)) + val backend: Instance[MemBackend] = Instantiate(new MemBackend(b)) // ------------------------------------------------- // Connection with outside (all in frontend) @@ -82,10 +81,6 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ------------------------------------------------- // Internal Connection (frontend - midend - backend) // ------------------------------------------------- - // Frontend interdma (MemLoader/MemStorer) connects to midend - // MemLoader/MemStorer DMA operations also need to access banks - // For now we directly tie off interdma since ballDomain is the main data path - // TODO: Add multiplexing if interdma also needs bank access for (i <- 0 until b.memDomain.bankNum) { frontend.io.interdma.bankRead(i).io.req.ready := false.B frontend.io.interdma.bankRead(i).io.resp.valid := false.B @@ -96,6 +91,5 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { frontend.io.interdma.bankWrite(i).io.resp.bits := 0.U.asTypeOf(frontend.io.interdma.bankWrite(i).io.resp.bits) } - // Midend to Backend: route scheduled requests to memory manager midend.io.mem_req <> backend.io.mem_req } diff --git a/arch/src/main/scala/framework/memdomain/README.md b/arch/src/main/scala/framework/memdomain/README.md index 5e7f8b30..4a3ebf47 100644 --- a/arch/src/main/scala/framework/memdomain/README.md +++ b/arch/src/main/scala/framework/memdomain/README.md @@ -126,12 +126,12 @@ Main Memory ←→ DMA Engine ←→ MemController ←→ Scratchpad/Accumulator ### dma/ - DMA Engines -**BBStreamReader**: Streaming data reader +**StreamReader**: Streaming data reader - TileLink interface for memory access - TLB support for virtual addressing - Transaction ID management for multiple outstanding requests -**BBStreamWriter**: Streaming data writer +**StreamWriter**: Streaming data writer - Handles data alignment (16-byte aligned) - Generates byte masks for partial writes - TLB support diff --git a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala similarity index 98% rename from arch/src/main/scala/framework/memdomain/backend/MemManager.scala rename to arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 08363ad7..5df4efb9 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemManager.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -8,7 +8,7 @@ import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} import framework.memdomain.backend.accpipe.AccPipe /** - * MemManager: Backend memory manager + * MemBackend: Backend memory manager * Manages the physical memory resources (Scratchpad + Accumulator Banks) * * Features: @@ -24,7 +24,7 @@ class MemRequestIO(b: GlobalConfig) extends Bundle { } @instantiable -class MemManager(val b: GlobalConfig) extends Module { +class MemBackend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala similarity index 85% rename from arch/src/main/scala/framework/memdomain/frontend/MemController.scala rename to arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index e67e26c8..bac6e03f 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemController.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -3,12 +3,7 @@ package framework.memdomain.frontend import chisel3._ import chisel3.util._ import freechips.rocketchip.tile._ -import framework.memdomain.frontend.outside_channel.dma.{ - BBStreamReader, - BBStreamReaderParam, - BBStreamWriter, - BBStreamWriterParam -} +import framework.memdomain.frontend.outside_channel.dma.{StreamReader, StreamWriter} import framework.memdomain.frontend.outside_channel.{MemLoader, MemStorer} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} @@ -21,11 +16,11 @@ import framework.memdomain.frontend.cmd_channel.rs.MemReservationStation import framework.memdomain.utils.pmc.MemCyclePMC /** - * MemController: Controller that encapsulates scratchpad and accumulator + * MemFrontend: * Provides DMA interface and Ball Domain interface */ @instantiable -class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { +class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { @public val io = IO(new Bundle { @@ -62,28 +57,12 @@ class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val pmc: Instance[MemCyclePMC] = Instantiate(new MemCyclePMC(b)) // TLB cluster - internal TLB management for DMA modules - // Supports 2 clients: BBStreamReader (client 1) and BBStreamWriter (client 0) + // Supports 2 clients: StreamReader (client 1) and StreamWriter (client 0) val tlbCluster = Instantiate(new BBTLBCluster(b)(edge)) // DMA Reader and Writer modules - handle actual DMA transfers - val readerParam = BBStreamReaderParam( - nXacts = b.memDomain.dma_n_xacts, - beatBits = b.memDomain.dma_buswidth, - maxBytes = b.memDomain.dma_maxbytes, - dataWidth = b.memDomain.dma_buswidth, - tledge = edge - ) - - val writerParam = BBStreamWriterParam( - nXacts = b.memDomain.dma_n_xacts, - beatBits = b.memDomain.dma_buswidth, - maxBytes = b.memDomain.dma_maxbytes, - dataWidth = b.memDomain.dma_buswidth, - tledge = edge - ) - - val reader: Instance[BBStreamReader] = Instantiate(new BBStreamReader(readerParam, b)) - val writer: Instance[BBStreamWriter] = Instantiate(new BBStreamWriter(writerParam, b)) + val reader: Instance[StreamReader] = Instantiate(new StreamReader(b)(edge)) + val writer: Instance[StreamWriter] = Instantiate(new StreamWriter(b)(edge)) // ----------------------------------------------------------------------------- // Global RS -> MemDecoder @@ -128,7 +107,7 @@ class MemController(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { writer.io.resp <> memStorer.io.dmaResp // TLB connection - internal TLB cluster connected to DMA modules - // Client 0: BBStreamWriter, Client 1: BBStreamReader + // Client 0: StreamWriter, Client 1: StreamReader // Insert pipeline registers to break combinational loops tlbCluster.io.clients(1).req := RegNext(reader.io.tlb.req) reader.io.tlb.resp := RegNext(tlbCluster.io.clients(1).resp) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/README.md b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/README.md index 4aa264f3..dbdb263f 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/README.md +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/README.md @@ -5,8 +5,8 @@ DMA engine implementation for Buckyball's memory domain, located at `arch/src/main/scala/framework/builtin/memdomain/dma`. Provides high-performance memory data transfer services between main memory and on-chip storage. Main components: -- **BBStreamReader**: Streaming data reader for bulk reads from external memory -- **BBStreamWriter**: Streaming data writer for bulk writes to external memory +- **StreamReader**: Streaming data reader for bulk reads from external memory +- **StreamWriter**: Streaming data writer for bulk writes to external memory - **LocalAddr**: Local address management for Scratchpad and Accumulator mapping ## File Structure @@ -37,7 +37,7 @@ class BBWriteRequest(dataWidth: Int)(implicit p: Parameters) extends CoreBundle } ``` -### BBStreamReader +### StreamReader **State Machine**: ```scala @@ -68,7 +68,7 @@ io.tlb.req.bits.tlb_req.cmd := M_XRD // Read operation io.tlb.req.bits.status := tlb_q.io.deq.bits.status ``` -### BBStreamWriter +### StreamWriter **Put Operation Selection**: ```scala @@ -134,5 +134,5 @@ def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { 3. **TLB Integration**: Full virtual address translation support for user and kernel mode 4. **Pipeline Design**: Multiple pipeline stages including address translation, TileLink request, and response handling 5. **Error Handling**: TLB miss handling implemented, relies on upper layer software for access failures -6. **Performance**: BBStreamWriter supports full and partial write modes, automatically selects optimal TileLink operation based on mask +6. **Performance**: StreamWriter supports full and partial write modes, automatically selects optimal TileLink operation based on mask 7. **Configuration**: DMA engines support parametrized configuration of concurrent transactions, data width, max transfer bytes diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala similarity index 91% rename from arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index b9b2bf53..46412dc0 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -7,16 +7,14 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.{MStatus, M_XRD} import freechips.rocketchip.rocket.constants.MemoryOpConstants -import framework.utils.Util._ +import framework.builtin.utils.Util._ import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO import framework.top.GlobalConfig class BBReadRequest extends Bundle { val vaddr = UInt(64.W) - // Read length (bytes) val len = UInt(16.W) val status = new MStatus - // Stride (bytes) val stride = UInt(10.W) } @@ -26,32 +24,26 @@ class BBReadResponse(dataWidth: Int) extends Bundle { val addrcounter = UInt(10.W) } -case class BBStreamReaderParam( - nXacts: Int, - beatBits: Int, - maxBytes: Int, - dataWidth: Int, - tledge: TLEdgeOut) - @instantiable -class BBStreamReader(val parameter: BBStreamReaderParam, val b: GlobalConfig) extends Module { - +class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val vaddrBits = b.core.vaddrBits + val nXacts = b.memDomain.dma_n_xacts + val beatBits = b.memDomain.dma_buswidth + val maxBytes = b.memDomain.dma_maxbytes + val dataWidth = b.memDomain.dma_buswidth + val beatBytes = beatBits / 8 @public val io = IO(new Bundle { val req = Flipped(Decoupled(new BBReadRequest())) - val resp = Decoupled(new BBReadResponse(parameter.dataWidth)) + val resp = Decoupled(new BBReadResponse(dataWidth)) val tlb = Flipped(new BBTLBIO(b)) val busy = Output(Bool()) val flush = Input(Bool()) // TileLink physical connection - val tl = new TLBundle(parameter.tledge.bundle) + val tl = new TLBundle(edge.bundle) }) - val edge = parameter.tledge - val beatBytes = parameter.beatBits / 8 - val s_idle :: s_req_new_block :: Nil = Enum(2) val state = RegInit(s_idle) @@ -74,7 +66,7 @@ class BBStreamReader(val parameter: BBStreamReaderParam, val b: GlobalConfig) ex req_byte_end := req_byte_start + read_size // Transaction ID management - val xactBusy = RegInit(0.U(parameter.nXacts.W)) + val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) val xactId = OHToUInt(xactOnehot) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala similarity index 85% rename from arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala rename to arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index 51ba17c5..b1bd10d2 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/BBStreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -6,16 +6,14 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.{MStatus, M_XWR} -import framework.utils.Util._ +import framework.builtin.utils.Util._ import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO import framework.top.GlobalConfig class BBWriteRequest(dataWidth: Int) extends Bundle { val vaddr = UInt(64.W) val data = UInt(dataWidth.W) - // Write length (bytes) val len = UInt(16.W) - // Byte mask val mask = UInt((dataWidth / 8).W) val status = new MStatus } @@ -24,38 +22,33 @@ class BBWriteResponse extends Bundle { val done = Bool() } -case class BBStreamWriterParam( - nXacts: Int, - beatBits: Int, - maxBytes: Int, - dataWidth: Int, - tledge: TLEdgeOut) - @instantiable -class BBStreamWriter(val parameter: BBStreamWriterParam, val b: GlobalConfig) extends Module { +class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val vaddrBits = b.core.vaddrBits + val nXacts = b.memDomain.dma_n_xacts + val beatBits = b.memDomain.dma_buswidth + val maxBytes = b.memDomain.dma_maxbytes + val dataWidth = b.memDomain.dma_buswidth + val beatBytes = beatBits / 8 + @public val io = IO(new Bundle { - val req = Flipped(Decoupled(new BBWriteRequest(parameter.dataWidth))) + val req = Flipped(Decoupled(new BBWriteRequest(dataWidth))) val resp = Decoupled(new BBWriteResponse) val tlb = Flipped(new BBTLBIO(b)) val busy = Output(Bool()) val flush = Input(Bool()) - // TileLink physical connection - val tl = new TLBundle(parameter.tledge.bundle) + val tl = new TLBundle(edge.bundle) }) - val edge = parameter.tledge - val beatBytes = parameter.beatBits / 8 - val s_idle :: s_writing :: Nil = Enum(2) val state = RegInit(s_idle) - val req = Reg(new BBWriteRequest(parameter.dataWidth)) + val req = Reg(new BBWriteRequest(dataWidth)) - val xactBusy = RegInit(0.U(parameter.nXacts.W)) + val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) val xactId = OHToUInt(xactOnehot) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala similarity index 91% rename from arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala rename to arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 046a3270..216a1f19 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemScheduler.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -9,13 +9,13 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.memdomain.backend.MemRequestIO /** - * MemScheduler: Midend module for memory scheduling - * Connects MemController to MemManager + * MemMidend: Midend module for memory scheduling + * Connects MemFrontend to MemManager * * Basic direct connection: routes requests from frontend to backend channels */ @instantiable -class MemScheduler(val b: GlobalConfig) extends Module { +class MemMidend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index 841112a2..b9bfa25d 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -16,7 +16,6 @@ import framework.balldomain.prototype.vector.VecBall // import framework.balldomain.prototype.nnlut.NNLutBall // import framework.balldomain.prototype.nnlut.configs.NNLutConfig -// Ball type definitions sealed trait BallType case object VecBallType extends BallType case object MatrixBallType extends BallType @@ -25,13 +24,10 @@ case object Im2colBallType extends BallType case object ReluBallType extends BallType case object NNLutBallType extends BallType -// Config Key case object TargetBallKey extends Field[BallType](VecBallType) -// TargetBall - directly instantiate pre-packaged Ball class TargetBall(implicit b: GlobalConfig, p: Parameters) extends Module { - // Create BlinkIO with parameter val io = IO(new BlinkIO(b)) p(TargetBallKey) match { diff --git a/arch/src/main/scala/sims/verilator/TargetConfig.scala b/arch/src/main/scala/sims/verilator/TargetConfig.scala index dd0ea5cd..e103c4a0 100644 --- a/arch/src/main/scala/sims/verilator/TargetConfig.scala +++ b/arch/src/main/scala/sims/verilator/TargetConfig.scala @@ -1,14 +1,12 @@ package sims.verilator import chisel3._ -// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._ import _root_.circt.stage.ChiselStage import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.subsystem.InSubsystem -// Custom BootROM configuration, pointing to correct resource path class WithCustomBootROM extends Config((site, here, up) => { case BootROMLocated(InSubsystem) => Some(BootROMParams( @@ -29,7 +27,6 @@ class BuckyballGemminiVerilatorConfig ) object Elaborate extends App { - // Accept full config class name like "sims.verilator.BuckyballToyVerilatorConfig" if (args.isEmpty) { println("Usage: Elaborate [firtool-opts...]") println("Example: Elaborate sims.verilator.BuckyballToyVerilatorConfig") @@ -39,7 +36,6 @@ object Elaborate extends App { val configClassName = args(0) println(s"Elaborating with config class: $configClassName") - // Dynamically load the config class val config: Config = try { val configClass = Class.forName(configClassName) From 06f1149e6dceeb638cdb2cd0af10f40768f76090 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 1 Jan 2026 23:42:27 +0800 Subject: [PATCH 022/238] [arch] refactor: remove EmptyBall module and update BBus initialization --- .../examples/toy/balldomain/BallDomain.scala | 8 +-- .../toy/balldomain/DomainDecoder.scala | 13 ++--- .../toy/balldomain/bbus/busRegister.scala | 26 ++++------ .../toy/balldomain/emptyball/EmptyBall.scala | 49 ------------------- .../framework/balldomain/bbus/bbus.scala | 37 +++++--------- .../balldomain/bbus/cmdrouter/CmdRouter.scala | 18 ++----- .../balldomain/bbus/memrouter/memRouter.scala | 7 +-- .../balldomain/bbus/pmc/BallCyclePMC.scala | 6 ++- .../balldomain/configs/BallDomainParam.scala | 5 +- .../framework/balldomain/configs/default.json | 8 ++- .../memdomain/configs/MemDomainParam.scala | 5 +- .../framework/memdomain/configs/default.json | 7 ++- 12 files changed, 53 insertions(+), 136 deletions(-) delete mode 100644 arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index c1cea833..e8f64a27 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -13,6 +13,7 @@ import framework.balldomain.rs.BallReservationStation @instantiable class BallDomain(val b: GlobalConfig) extends Module { + val memChannel = b.memDomain.balldomainChannel @public val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(b)))) @@ -21,12 +22,13 @@ class BallDomain(val b: GlobalConfig) extends Module { val global_complete_o = IO(Decoupled(new GlobalRsComplete(b))) @public - val bankRead = IO(Vec(b.memDomain.bankNum, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(memChannel, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(b.memDomain.bankNum, Flipped(new BankWrite(b)))) + val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) + + require(b.memDomain.balldomainChannel == b.ballDomain.bbusChannel, "balldomainChannel must be equal to bbusChannel") - // Create new BBus module val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) val ballRs: Instance[BallReservationStation] = Instantiate(new BallReservationStation(b)) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 0e70013e..ef1031d6 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -10,9 +10,7 @@ import framework.top.GlobalConfig // Detailed decode output for Ball domain class BallDecodeCmd(numBanks: Int) extends Bundle { - // Ball ID - val bid = UInt(5.W) - + val bid = UInt(5.W) // Iteration count val iter = UInt(10.W) @@ -54,23 +52,18 @@ object BallDefaultConstants { @instantiable class BallDomainDecoder(val b: GlobalConfig) extends Module { import BallDefaultConstants._ - @public - val raw_cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) - + val raw_cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) @public val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum))) - val spAddrLen = 14 // b.spAddrLen replaced with constant - - // Only process ball instructions raw_cmd_i.ready := ball_decode_cmd_o.ready val func7 = raw_cmd_i.bits.raw_cmd.inst.funct val rs1 = raw_cmd_i.bits.raw_cmd.rs1 val rs2 = raw_cmd_i.bits.raw_cmd.rs2 - // Ball instruction decoding - now directly use rs1/rs2 as bank IDs + // Ball instruction decoding import BallDecodeFields._ val ball_default_decode = List(N, N, N, N, N, 0.U, 0.U, 0.U, DITER, DBID, DSPECIAL) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index e4f26570..d0623e86 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -3,15 +3,10 @@ package examples.toy.balldomain.bbus import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.instantiable -import org.chipsalliance.cde.config.Parameters import framework.top.GlobalConfig import framework.balldomain.bbus.BBus -import framework.balldomain.prototype.vector.configs.VectorBallParam -// import prototype.matrix.configs.MatrixConfig -// import prototype.im2col.configs.Im2colConfig -// import prototype.transpose.configs.TransposeConfig -// import prototype.relu.configs.ReluConfig -// import prototype.transfer.configs.TransferConfig +import framework.balldomain.blink.BallRegist +import framework.balldomain.prototype.vector.VecBall /** * BBusModule - Ball bus module that directly extends BBus @@ -20,14 +15,11 @@ import framework.balldomain.prototype.vector.configs.VectorBallParam class BBusModule(b: GlobalConfig) extends BBus( b, - // Define Ball device generators to register - Seq( - () => new framework.balldomain.prototype.vector.VecBall(b, 0), - // () => new prototype.matrix.MatrixBall(MatrixConfig.fromBallDomain(parameter), 1), - // () => new prototype.im2col.Im2colBall(Im2colConfig.fromBallDomain(parameter), 2), - // () => new prototype.transpose.TransposeBall(TransposeConfig.fromBallDomain(parameter), 3), - // () => new prototype.relu.ReluBall(ReluConfig.fromBallDomain(parameter), 4), - () => new examples.toy.balldomain.emptyball.EmptyBall(b, 1) - // () => new prototype.transfer.TransferBall(TransferConfig.fromBallDomain(parameter), 6) - ) + b.ballDomain.ballIdMappings.map { mapping => + val ballGenerator: () => BallRegist with Module = mapping.ballName match { + case "VecBall" => () => new VecBall(b, mapping.ballId) + case name => throw new IllegalArgumentException(s"Unknown ball name: $name") + } + ballGenerator + } ) {} diff --git a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala b/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala deleted file mode 100644 index 85c6c772..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/emptyball/EmptyBall.scala +++ /dev/null @@ -1,49 +0,0 @@ -package examples.toy.balldomain.emptyball - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import framework.top.GlobalConfig -import framework.balldomain.blink.{BallRegist, BlinkIO} - -@instantiable -class EmptyBall( - b: GlobalConfig, - id: Int) - extends Module - with BallRegist { - @public - val io = IO(new BlinkIO(b)) - val ballId = id.U - - def Blink: BlinkIO = io - - io.cmdResp.valid := RegNext(io.cmdReq.valid) - io.cmdResp.bits.rob_id := RegNext(io.cmdReq.bits.rob_id) - io.cmdReq.ready := true.B - - for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).io.req.valid := false.B - io.bankRead(i).io.req.bits.addr := 0.U - io.bankRead(i).io.resp.ready := false.B - io.bankRead(i).rob_id := 0.U - io.bankRead(i).bank_id := 0.U - - io.bankWrite(i).io.req.valid := false.B - io.bankWrite(i).io.req.bits.addr := 0.U - io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) - io.bankWrite(i).io.req.bits.wmode := false.B - io.bankWrite(i).io.resp.ready := false.B // Add missing resp.ready - io.bankWrite(i).rob_id := 0.U - io.bankWrite(i).bank_id := 0.U - } - io.status.ready := true.B - io.status.valid := io.cmdResp.valid - io.status.idle := false.B - io.status.init := false.B - io.status.running := false.B - io.status.iter := 0.U - io.status.complete := io.cmdResp.valid - -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 77664c8b..dfe82cd8 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -11,38 +11,33 @@ import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter import framework.balldomain.blink.{BankRead, BankWrite} -class BBusConfigIO(numBalls: Int) extends Bundle { - val src_bid = UInt(log2Ceil(numBalls).W) - val dst_bid = UInt(log2Ceil(numBalls).W) - val set = Bool() -} - /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices */ @instantiable class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module]) extends Module { - val numBalls = b.ballDomain.ballNum + val numBalls = b.ballDomain.ballNum + val bbusChannel = b.ballDomain.bbusChannel + @public val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) @public - val bankRead = IO(Vec(b.memDomain.bankNum, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(bbusChannel, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(b.memDomain.bankNum, Flipped(new BankWrite(b)))) + val bankWrite = IO(Vec(bbusChannel, Flipped(new BankWrite(b)))) // Instantiate all registered Balls - // Note: Since Instantiate requires 'new' expression and ballGenerators are functions, - // we use Module here. The balls themselves are @instantiable, but when instantiated - // from a function generator pattern, we use Module. This is acceptable as the balls - // are still properly instantiated and can be used with the hierarchy system. val balls = ballGenerators.map(gen => Module(gen())) + val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) + val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b)) + val pmc: Instance[BallCyclePMC] = Instantiate(new BallCyclePMC(b)) // ----------------------------------------------------------------------------- // cmd router // ----------------------------------------------------------------------------- - val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b, numBalls)) + val idle_ball = Wire(Vec(numBalls, Bool())) for (i <- 0 until numBalls) { idle_ball(i) := balls(i).Blink.cmdReq.ready @@ -54,27 +49,21 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module for (i <- 0 until numBalls) { balls(i).Blink.cmdReq.valid := cmdRouter.io.cmdReq_o.valid && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) balls(i).Blink.cmdReq.bits := cmdRouter.io.cmdReq_o.bits + + cmdRouter.io.cmdResp_i(i) <> balls(i).Blink.cmdResp } cmdRouter.io.cmdReq_o.ready := VecInit((0 until numBalls).map(i => balls(i).Blink.cmdReq.ready && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) )).asUInt.orR - for (i <- 0 until numBalls) { - cmdRouter.io.cmdResp_i(i) <> balls(i).Blink.cmdResp - } - cmdResp <> cmdRouter.io.cmdResp_o // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- - val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b)) - memoryrouter.io.bbusConfig_i <> cmdRouter.io.bbusConfig_o - - // Direct connection from balls to memory router (no ToVirtualLine) for (i <- 0 until numBalls) { - for (j <- 0 until b.memDomain.bankNum) { + for (j <- 0 until bbusChannel) { memoryrouter.io.bankRead_i(i)(j) <> balls(i).Blink.bankRead(j) memoryrouter.io.bankWrite_i(i)(j) <> balls(i).Blink.bankWrite(j) } @@ -86,8 +75,6 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- - val pmc = Module(new BallCyclePMC(b, numBalls)) - for (i <- 0 until numBalls) { pmc.io.cmdReq_i(i).valid := cmdRouter.io.cmdReq_i(i).fire pmc.io.cmdReq_i(i).bits := cmdRouter.io.cmdReq_i(i).bits diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala index 0c656a0e..f547371d 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala @@ -4,12 +4,12 @@ import chisel3._ import chisel3.util._ import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.bbus.BBusConfigIO import framework.balldomain.bbus.cmdrouter.CmdReqRouter import chisel3.experimental.hierarchy.{instantiable, public} @instantiable -class CmdRouter(b: GlobalConfig, numBalls: Int) extends Module { +class CmdRouter(val b: GlobalConfig) extends Module { + val numBalls = b.ballDomain.ballNum @public val io = IO(new Bundle { @@ -18,8 +18,7 @@ class CmdRouter(b: GlobalConfig, numBalls: Int) extends Module { val cmdReq_o = Decoupled(new BallRsIssue(b)) val cmdResp_o = Vec(numBalls, Decoupled(new BallRsComplete(b))) - val ballIdle = Input(Vec(numBalls, Bool())) - val bbusConfig_o = Decoupled(new BBusConfigIO(numBalls)) + val ballIdle = Input(Vec(numBalls, Bool())) }) val reqRouter = Module(new CmdReqRouter(b, numBalls)) @@ -31,15 +30,4 @@ class CmdRouter(b: GlobalConfig, numBalls: Int) extends Module { for (i <- 0 until numBalls) { io.cmdResp_o(i) <> io.cmdResp_i(i) } - io.bbusConfig_o.valid := false.B - io.bbusConfig_o.bits.src_bid := 0.U - io.bbusConfig_o.bits.dst_bid := 0.U - io.bbusConfig_o.bits.set := false.B - - when(io.cmdReq_i(b.ballDomain.emptyBallid).valid) { - io.bbusConfig_o.valid := true.B - io.bbusConfig_o.bits.src_bid := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(5, 0) - io.bbusConfig_o.bits.dst_bid := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(11, 6) - io.bbusConfig_o.bits.set := io.cmdReq_i(b.ballDomain.emptyBallid).bits.cmd.special(12, 12) - } } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 0c70d844..64f6e21d 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -3,8 +3,7 @@ package framework.balldomain.bbus.memrouter import chisel3._ import chisel3.util._ import framework.balldomain.blink.{BankRead, BankWrite} -import framework.balldomain.bbus.BBusConfigIO -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig @instantiable @@ -17,8 +16,6 @@ class MemRouter(val b: GlobalConfig) extends Module { val bankRead_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankRead(b))) val bankWrite_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankWrite(b))) - val bbusConfig_i = Flipped(Decoupled(new BBusConfigIO(numBalls))) - val bankRead_o = Vec(bbusChannel, Flipped(new BankRead(b))) val bankWrite_o = Vec(bbusChannel, Flipped(new BankWrite(b))) }) @@ -52,6 +49,4 @@ class MemRouter(val b: GlobalConfig) extends Module { } } - io.bbusConfig_i.ready := false.B - } diff --git a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala index b9264faf..2701bf7f 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala @@ -5,9 +5,13 @@ import chisel3.util._ import framework.top.GlobalConfig import framework.balldomain.rs.BallRsIssue import framework.balldomain.rs.BallRsComplete +import chisel3.experimental.hierarchy.{instantiable, public} -class BallCyclePMC(val b: GlobalConfig, val numBalls: Int) extends Module { +@instantiable +class BallCyclePMC(val b: GlobalConfig) extends Module { + val numBalls = b.ballDomain.ballNum + @public val io = IO(new Bundle { val cmdReq_i = Input(Vec(numBalls, Valid(new BallRsIssue(b)))) val cmdResp_o = Input(Vec(numBalls, Valid(new BallRsComplete(b)))) diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala index 20028956..558d690c 100644 --- a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -7,14 +7,15 @@ import upickle.default._ */ case class BallIdMapping( ballId: Int, - ballName: String) + ballName: String, + inBW: Int, + outBW: Int) /** * BallDomain参数 */ case class BallDomainParam( ballNum: Int, - emptyBallid: Int, ballIdMappings: Seq[BallIdMapping], bbusChannel: Int) diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 1e557308..dfecde10 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,9 +1,7 @@ { - "ballNum": 2, - "emptyBallid": 1, + "ballNum": 1, "ballIdMappings": [ - {"ballId": 0, "ballName": "VecBall"}, - {"ballId": 1, "ballName": "EmptyBall"} + {"ballId": 0, "ballName": "VecBall", "inBW": 32, "outBW": 32} ], - "bbusChannel": 10 + "bbusChannel": 6 } diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala index de158be5..5f5fde84 100644 --- a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -16,7 +16,10 @@ case class MemDomainParam( bankChannel: Int, max_in_flight_mem_reqs: Int, dma_buswidth: Int, - memAddrLen: Int) + memAddrLen: Int, + balldomainChannel: Int, + tmaReadChannel: Int, + tmaWriteChannel: Int) object MemDomainParam { implicit val rw: ReadWriter[MemDomainParam] = macroRW diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index 65353590..aea2199d 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -6,8 +6,11 @@ "tlb_size": 4, "dma_n_xacts": 8, "dma_maxbytes": 64, - "bankChannel": 32, + "bankChannel": 8, "max_in_flight_mem_reqs": 16, "dma_buswidth": 128, - "memAddrLen": 32 + "memAddrLen": 32, + "balldomainChannel": 6, + "tmaReadChannel": 4, + "tmaWriteChannel": 4 } From 88e31e4ad879c4d52934835fcac82bcbf04a9e6e Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 2 Jan 2026 02:53:29 +0800 Subject: [PATCH 023/238] [arch] feat: enhance BBus and MemRouter with dynamic bandwidth handling and add ReluBall support --- .../toy/balldomain/bbus/busRegister.scala | 6 +- .../framework/balldomain/bbus/bbus.scala | 16 +- .../balldomain/bbus/memrouter/memRouter.scala | 203 +++++++++++++++--- .../framework/balldomain/blink/baseball.scala | 4 +- .../framework/balldomain/blink/blink.scala | 12 +- .../framework/balldomain/configs/default.json | 2 +- .../balldomain/prototype/relu/ReluBall.scala | 27 ++- .../balldomain/prototype/vector/VecBall.scala | 35 +-- .../prototype/vector/VecLoadUnit.scala | 44 ++-- .../prototype/vector/VecStoreUnit.scala | 64 +++--- .../balldomain/prototype/vector/VecUnit.scala | 55 ++--- .../framework/builtin/router/Router.scala | 2 +- .../scala/framework/memdomain/MemDomain.scala | 5 +- .../memdomain/midend/MemMidend.scala | 19 +- .../main/scala/sims/verify/TargetConfig.scala | 67 +++--- 15 files changed, 374 insertions(+), 187 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index d0623e86..9e73854a 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -7,6 +7,7 @@ import framework.top.GlobalConfig import framework.balldomain.bbus.BBus import framework.balldomain.blink.BallRegist import framework.balldomain.prototype.vector.VecBall +import framework.balldomain.prototype.relu.ReluBall /** * BBusModule - Ball bus module that directly extends BBus @@ -17,8 +18,9 @@ class BBusModule(b: GlobalConfig) b, b.ballDomain.ballIdMappings.map { mapping => val ballGenerator: () => BallRegist with Module = mapping.ballName match { - case "VecBall" => () => new VecBall(b, mapping.ballId) - case name => throw new IllegalArgumentException(s"Unknown ball name: $name") + case "VecBall" => () => new VecBall(b) + case "ReluBall" => () => new ReluBall(b) + case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator } diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index dfe82cd8..f962ba41 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -62,13 +62,27 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- + // Connect each ball's bankRead/bankWrite based on its configured bandwidth + // All requests from balls will go through Router inside MemRouter + // and become bbusChannel outputs (not bankNum) for (i <- 0 until numBalls) { - for (j <- 0 until bbusChannel) { + val ballMapping = b.ballDomain.ballIdMappings(i) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + // Connect all input bandwidth channels (bankRead) to MemRouter + // MemRouter will use Router to route all ball requests to bbusChannel outputs + for (j <- 0 until inBW.min(b.memDomain.bankNum)) { memoryrouter.io.bankRead_i(i)(j) <> balls(i).Blink.bankRead(j) + } + + // Connect all output bandwidth channels (bankWrite) to MemRouter + for (j <- 0 until outBW.min(b.memDomain.bankNum)) { memoryrouter.io.bankWrite_i(i)(j) <> balls(i).Blink.bankWrite(j) } } + // MemRouter outputs bbusChannel channels (routed from all ball requests) bankRead <> memoryrouter.io.bankRead_o bankWrite <> memoryrouter.io.bankWrite_o diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 64f6e21d..8b871b83 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -3,14 +3,19 @@ package framework.balldomain.bbus.memrouter import chisel3._ import chisel3.util._ import framework.balldomain.blink.{BankRead, BankWrite} -import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig +import framework.builtin.router.Router @instantiable class MemRouter(val b: GlobalConfig) extends Module { val bbusChannel = b.ballDomain.bbusChannel val numBalls = b.ballDomain.ballNum + // Calculate total input channels from all balls + val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum + @public val io = IO(new Bundle { val bankRead_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankRead(b))) @@ -20,33 +25,183 @@ class MemRouter(val b: GlobalConfig) extends Module { val bankWrite_o = Vec(bbusChannel, Flipped(new BankWrite(b))) }) - for (i <- 0 until bbusChannel) { - io.bankRead_o(i).io.req.valid := false.B - io.bankRead_o(i).io.req.bits.addr := 0.U - io.bankRead_o(i).io.resp.ready := false.B - io.bankRead_o(i).rob_id := 0.U - io.bankRead_o(i).bank_id := 0.U - - io.bankWrite_o(i).io.req.valid := false.B - io.bankWrite_o(i).io.req.bits.addr := 0.U - io.bankWrite_o(i).io.req.bits.data := 0.U - io.bankWrite_o(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) - io.bankWrite_o(i).io.req.bits.wmode := false.B - io.bankWrite_o(i).io.resp.ready := false.B - io.bankWrite_o(i).rob_id := 0.U - io.bankWrite_o(i).bank_id := 0.U + // Build channel mappings at compile time + // Map flat index -> (ballIdx, channelIdx) + val readMapping: Seq[(Int, Int)] = { + var flatIdx = 0 + val mapping = scala.collection.mutable.ArrayBuffer[(Int, Int)]() + for (ballIdx <- 0 until numBalls) { + val inBW = b.ballDomain.ballIdMappings(ballIdx).inBW + for (chIdx <- 0 until inBW.min(b.memDomain.bankNum)) { + mapping += ((ballIdx, chIdx)) + flatIdx += 1 + } + } + mapping.toSeq + } + + val writeMapping: Seq[(Int, Int)] = { + var flatIdx = 0 + val mapping = scala.collection.mutable.ArrayBuffer[(Int, Int)]() + for (ballIdx <- 0 until numBalls) { + val outBW = b.ballDomain.ballIdMappings(ballIdx).outBW + for (chIdx <- 0 until outBW.min(b.memDomain.bankNum)) { + mapping += ((ballIdx, chIdx)) + flatIdx += 1 + } + } + mapping.toSeq } - for (i <- 0 until numBalls) { - for (j <- 0 until b.memDomain.bankNum) { - io.bankRead_i(i)(j).io.req.ready := false.B - io.bankRead_i(i)(j).io.resp.valid := false.B - io.bankRead_i(i)(j).io.resp.bits.data := 0.U + // Create valid signals for Router inputs + val readValidSignals = Wire(Vec(totalReadChannels, Bool())) + val writeValidSignals = Wire(Vec(totalWriteChannels, Bool())) + + for (i <- 0 until totalReadChannels) { + val (ballIdx, channelIdx) = readMapping(i) + readValidSignals(i) := io.bankRead_i(ballIdx)(channelIdx).io.req.valid + } + + for (i <- 0 until totalWriteChannels) { + val (ballIdx, channelIdx) = writeMapping(i) + writeValidSignals(i) := io.bankWrite_i(ballIdx)(channelIdx).io.req.valid + } + + // Instantiate Routers + val readRouter: Instance[Router] = Instantiate(new Router(totalReadChannels, bbusChannel)) + val writeRouter: Instance[Router] = Instantiate(new Router(totalWriteChannels, bbusChannel)) + + // Connect Router inputs (io.in is input, so we connect from Wire to it) + for (i <- 0 until totalReadChannels) { + readRouter.io.in(i) := readValidSignals(i) + } + for (i <- 0 until totalWriteChannels) { + writeRouter.io.in(i) := writeValidSignals(i) + } + + // Connect Router outputs to bankRead_o and bankWrite_o + for (outIdx <- 0 until bbusChannel) { + // Read routing - use MuxCase to select based on Router output + val readSelectedIdx = readRouter.io.out(outIdx).bits + val readCanTransmit = readRouter.io.out(outIdx).valid && io.bankRead_o(outIdx).io.req.ready + val readReqValidCases = readMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).io.req.valid + } + io.bankRead_o(outIdx).io.req.valid := MuxCase( + false.B, + readReqValidCases :+ (!readCanTransmit) -> false.B + ) + + val readReqBitsCases = readMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).io.req.bits + } + io.bankRead_o(outIdx).io.req.bits := MuxCase( + DontCare, + readReqBitsCases :+ (!readCanTransmit) -> 0.U.asTypeOf(io.bankRead_o(outIdx).io.req.bits.cloneType) + ) - io.bankWrite_i(i)(j).io.req.ready := false.B - io.bankWrite_i(i)(j).io.resp.valid := false.B - io.bankWrite_i(i)(j).io.resp.bits.ok := false.B + // Build MuxCase for read rob_id and bank_id + val readRobIdCases = readMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).rob_id } + io.bankRead_o(outIdx).rob_id := MuxCase(0.U, readRobIdCases) + + val readBankIdCases = readMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).bank_id + } + io.bankRead_o(outIdx).bank_id := MuxCase(0.U, readBankIdCases) + + // Connect read response back + // Only handle channels that are actually connected (in readMapping) + for ((mapping, flatIdx) <- readMapping.zipWithIndex) { + val (ballIdx, channelIdx) = mapping + when(readCanTransmit && readSelectedIdx === flatIdx.U) { + io.bankRead_i(ballIdx)(channelIdx).io.req.ready := io.bankRead_o(outIdx).io.req.ready + io.bankRead_i(ballIdx)(channelIdx).io.resp.valid := io.bankRead_o(outIdx).io.resp.valid + io.bankRead_i(ballIdx)(channelIdx).io.resp.bits := io.bankRead_o(outIdx).io.resp.bits + }.otherwise { + io.bankRead_i(ballIdx)(channelIdx).io.req.ready := false.B + io.bankRead_i(ballIdx)(channelIdx).io.resp.valid := false.B + io.bankRead_i(ballIdx)(channelIdx).io.resp.bits := 0.U.asTypeOf( + io.bankRead_i(ballIdx)(channelIdx).io.resp.bits.cloneType + ) + } + } + // resp.ready: bankRead_o is Flipped, so resp.ready is output (from internal), we drive it from bankRead_i + io.bankRead_o(outIdx).io.resp.ready := MuxCase( + false.B, + readMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (readCanTransmit && readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).io.resp.ready + } + ) + + // Write routing - similar to read + val writeSelectedIdx = writeRouter.io.out(outIdx).bits + val writeCanTransmit = writeRouter.io.out(outIdx).valid && io.bankWrite_o(outIdx).io.req.ready + + // Build MuxCase for write request (only valid and bits, ready is input) + val writeReqValidCases = writeMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).io.req.valid + } + io.bankWrite_o(outIdx).io.req.valid := MuxCase( + false.B, + writeReqValidCases :+ (!writeCanTransmit) -> false.B + ) + + val writeReqBitsCases = writeMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).io.req.bits + } + io.bankWrite_o(outIdx).io.req.bits := MuxCase( + DontCare, + writeReqBitsCases :+ (!writeCanTransmit) -> 0.U.asTypeOf(io.bankWrite_o(outIdx).io.req.bits.cloneType) + ) + + val writeRobIdCases = writeMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).rob_id + } + io.bankWrite_o(outIdx).rob_id := MuxCase(0.U, writeRobIdCases) + + val writeBankIdCases = writeMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).bank_id + } + io.bankWrite_o(outIdx).bank_id := MuxCase(0.U, writeBankIdCases) + + // Connect write response back + // Only handle channels that are actually connected (in writeMapping) + for ((mapping, flatIdx) <- writeMapping.zipWithIndex) { + val (ballIdx, channelIdx) = mapping + when(writeCanTransmit && writeSelectedIdx === flatIdx.U) { + io.bankWrite_i(ballIdx)(channelIdx).io.req.ready := io.bankWrite_o(outIdx).io.req.ready + io.bankWrite_i(ballIdx)(channelIdx).io.resp.valid := io.bankWrite_o(outIdx).io.resp.valid + io.bankWrite_i(ballIdx)(channelIdx).io.resp.bits := io.bankWrite_o(outIdx).io.resp.bits + }.otherwise { + io.bankWrite_i(ballIdx)(channelIdx).io.req.ready := false.B + io.bankWrite_i(ballIdx)(channelIdx).io.resp.valid := false.B + io.bankWrite_i(ballIdx)(channelIdx).io.resp.bits := 0.U.asTypeOf( + io.bankWrite_i(ballIdx)(channelIdx).io.resp.bits.cloneType + ) + } + } + io.bankWrite_o(outIdx).io.resp.ready := MuxCase( + false.B, + writeMapping.zipWithIndex.map { + case ((ballIdx, channelIdx), flatIdx) => + (writeCanTransmit && writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).io.resp.ready + } + ) + + // Router ready signals + readRouter.io.out(outIdx).ready := io.bankRead_o(outIdx).io.req.ready + writeRouter.io.out(outIdx).ready := io.bankWrite_o(outIdx).io.req.ready } } diff --git a/arch/src/main/scala/framework/balldomain/blink/baseball.scala b/arch/src/main/scala/framework/balldomain/blink/baseball.scala index efe51a34..672b0db4 100644 --- a/arch/src/main/scala/framework/balldomain/blink/baseball.scala +++ b/arch/src/main/scala/framework/balldomain/blink/baseball.scala @@ -4,6 +4,6 @@ import chisel3._ import chisel3.util._ trait BallRegist { - def Blink: BlinkIO - def ballId: UInt + def Blink: BlinkIO + // def ballId: UInt } diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index 6269a37f..bc3ecb01 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -34,18 +34,20 @@ class BankWrite(val b: GlobalConfig) extends Bundle { } // Blink IO Bundle - interface for Ball devices -class BlinkIO(b: GlobalConfig) extends Bundle { +// inBW: number of input bandwidth channels (bankRead) +// outBW: number of output bandwidth channels (bankWrite) +class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) val cmdResp = Decoupled(new BallRsComplete(b)) - val bankRead = Vec(b.memDomain.bankNum, Flipped(new BankRead(b))) - val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) val status = new Status } @instantiable -class Blink(b: GlobalConfig) extends Module { +class Blink(b: GlobalConfig, inBW: Int, outBW: Int) extends Module { @public - val io = IO(new BlinkIO(b)) + val io = IO(new BlinkIO(b, inBW, outBW)) def cmdReq: DecoupledIO[BallRsIssue] = io.cmdReq def cmdResp: DecoupledIO[BallRsComplete] = io.cmdResp diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index dfecde10..7c402728 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,7 +1,7 @@ { "ballNum": 1, "ballIdMappings": [ - {"ballId": 0, "ballName": "VecBall", "inBW": 32, "outBW": 32} + {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4} ], "bbusChannel": 6 } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala index a896b9c1..da9d14ef 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala @@ -13,10 +13,14 @@ import framework.top.GlobalConfig * then write back to Scratchpad. */ @instantiable -class ReluBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { +class ReluBall(val b: GlobalConfig) extends Module with BallRegist { + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "ReluBall") + .getOrElse(throw new IllegalArgumentException("ReluBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + @public - val io = IO(new BlinkIO(b)) - val ballId = id.U + val io = IO(new BlinkIO(b, inBW, outBW)) def Blink: BlinkIO = io @@ -25,14 +29,21 @@ class ReluBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { reluUnit.io.cmdReq <> io.cmdReq reluUnit.io.cmdResp <> io.cmdResp - for (i <- 0 until b.memDomain.bankNum) { + for (i <- 0 until inBW) { reluUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U + } + + for (i <- 0 until outBW) { reluUnit.io.bankWrite(i) <> io.bankWrite(i).io + } + + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + } + + for (i <- 0 until outBW) { io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := false.B // ReluBall uses overwrite mode + io.bankWrite(i).io.req.bits.wmode := false.B } io.status <> reluUnit.io.status diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala index eafdc52e..5f04a294 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala @@ -11,34 +11,39 @@ import framework.top.GlobalConfig * VecBall - A vector computation Ball that complies with the Blink protocol */ @instantiable -class VecBall(val b: GlobalConfig, id: Int) extends Module with BallRegist { +class VecBall(val b: GlobalConfig) extends Module with BallRegist { + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") + .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + @public - val io = IO(new BlinkIO(b)) - val ballId = id.U + val io = IO(new BlinkIO(b, inBW, outBW)) def Blink: BlinkIO = io - // Instantiate VecUnit val vecUnit: Instance[VecUnit] = Instantiate(new VecUnit(b)) - // Connect command interface vecUnit.io.cmdReq <> io.cmdReq vecUnit.io.cmdResp <> io.cmdResp - // Connect Bank interface - for (i <- 0 until b.memDomain.bankNum) { - vecUnit.io.bankRead(i) <> io.bankRead(i).io - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - io.bankRead(i).bank_id := i.U + for (i <- 0 until inBW) { + vecUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + vecUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := io.cmdReq.bits.rob_id + } - // VecUnit uses bankWrite for writes (accumulate mode) - vecUnit.io.bankWrite(i) <> io.bankWrite(i).io + for (i <- 0 until outBW) { io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id - io.bankWrite(i).bank_id := i.U - io.bankWrite(i).io.req.bits.wmode := true.B // VecBall uses accumulate mode for writes + io.bankWrite(i).io.req.bits.wmode := true.B } - // Connect Status signals - directly obtained from internal unit io.status <> vecUnit.io.status } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 61fef36a..f3dc1246 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -25,16 +25,28 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val bankWidth = b.memDomain.bankWidth val rob_id_width = log2Up(b.frontend.rob_entries) + // Get bandwidth from config (use first VecBall mapping) + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") + .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) + val inBW = ballMapping.inBW + @public val io = IO(new Bundle { - val bankReadReq = Vec(b.memDomain.bankNum, Decoupled(new SramReadReq(b))) - val bankReadResp = Vec(b.memDomain.bankNum, Flipped(Decoupled(new SramReadResp(b)))) + val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req(b))) val ld_ex_o = Decoupled(new ld_ex_req(b)) + // Output current op1_bank and op2_bank for bank_id setting + val op1_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val op2_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) }) - val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + + // Output op1_bank and op2_bank for bank_id setting + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val iter = RegInit(0.U(10.W)) @@ -51,7 +63,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val ld_ex_iter_reg = RegInit(0.U(10.W)) // Default assignment for each bank read request - for (i <- 0 until b.memDomain.bankNum) { + for (i <- 0 until inBW) { io.bankReadReq(i).valid := false.B io.bankReadReq(i).bits.addr := 0.U } @@ -81,12 +93,14 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // Send SRAM read request (only when output register is idle) // ----------------------------------------------------------------------------- when(state === busy && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - io.bankReadReq(op1_bank).valid := iter_counter < iter - io.bankReadReq(op1_bank).bits.addr := op1_addr + iter_counter - - io.bankReadReq(op2_bank).valid := iter_counter < iter - io.bankReadReq(op2_bank).bits.addr := op2_addr + iter_counter - iter_counter := iter_counter + 1.U + val op1_channel = op1_bank % inBW.U + val op2_channel = op2_bank % inBW.U + io.bankReadReq(op1_channel).valid := iter_counter < iter + io.bankReadReq(op1_channel).bits.addr := op1_addr + iter_counter + + io.bankReadReq(op2_channel).valid := iter_counter < iter + io.bankReadReq(op2_channel).bits.addr := op2_addr + iter_counter + iter_counter := iter_counter + 1.U } // ----------------------------------------------------------------------------- @@ -95,11 +109,13 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // ready signal for bankReadResp: can receive when there's no pending data or downstream has received /* io.bankReadResp.foreach { resp => resp.ready := !ld_ex_valid_reg || io.ld_ex_o.ready } */ // Receive SRAM data and cache to register - when(io.bankReadResp(op1_bank).valid && io.bankReadResp(op2_bank).valid && + val op1_channel = op1_bank % inBW.U + val op2_channel = op2_bank % inBW.U + when(io.bankReadResp(op1_channel).valid && io.bankReadResp(op2_channel).valid && (!ld_ex_valid_reg || io.ld_ex_o.ready) && (state === busy)) { ld_ex_valid_reg := true.B - ld_ex_op1_reg := io.bankReadResp(op1_bank).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - ld_ex_op2_reg := io.bankReadResp(op2_bank).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_op1_reg := io.bankReadResp(op1_channel).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_op2_reg := io.bankReadResp(op2_channel).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) ld_ex_iter_reg := iter_counter }.elsewhen(io.ld_ex_o.ready) { ld_ex_valid_reg := false.B diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 83658047..49bc6526 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -18,7 +18,6 @@ class ex_st_req(b: GlobalConfig) extends Bundle { val config = VectorBallParam() val InputNum = config.lane val accWidth = config.outputWidth - // Use accumulator type val rst = Vec(InputNum, UInt(accWidth.W)) val iter = UInt(10.W) } @@ -29,14 +28,22 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { val InputNum = config.lane val accWidth = config.outputWidth + // Get bandwidth from config (use first VecBall mapping) + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") + .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) + val outBW = ballMapping.outBW + @public val io = IO(new Bundle { val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req(b))) val ex_st_i = Flipped(Decoupled(new ex_st_req(b))) // Unified bank write interface (writes use accumulate mode) - val bankWrite = - Vec(b.memDomain.bankNum, Flipped(new SramWriteIO(b))) + // outBW channels share the data write + val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) + + // Output current wr_bank for bank_id setting + val wr_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) val cmdResp_o = Valid(new Bundle { val commit = Bool() }) }) @@ -76,43 +83,28 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { } val waddr = wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) when(io.ex_st_i.fire) { - for (i <- 0 until b.memDomain.bankNum / 2) { - when(waddr(0) === 0.U) { - io.bankWrite(i).req.valid := true.B - io.bankWrite(i).req.bits.addr := wr_bank_addr + (iter_counter(log2Ceil(InputNum) - 1, 0) >> 1.U) - - // Each accumulator bank stores InputNum/numBanks elements - val elementsPerBank = InputNum / b.memDomain.bankNum * 2 - val startIdx = i * elementsPerBank - val endIdx = startIdx + elementsPerBank - 1 - - // Pack corresponding elements into a UInt - val bankData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - io.bankWrite(i).req.bits.data := bankData - - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - }.otherwise { - io.bankWrite(i + b.memDomain.bankNum / 2).req.valid := true.B - io.bankWrite(i + b.memDomain.bankNum / 2).req.bits.addr := wr_bank_addr + (iter_counter( - log2Ceil(InputNum) - 1, - 0 - ) >> 1.U) - - // Each accumulator bank stores InputNum/numBanks elements - val elementsPerBank = InputNum / b.memDomain.bankNum * 2 - val startIdx = i * elementsPerBank - val endIdx = startIdx + elementsPerBank - 1 - - // Pack corresponding elements into a UInt - val bankData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - io.bankWrite(i + b.memDomain.bankNum / 2).req.bits.data := bankData - - io.bankWrite(i + b.memDomain.bankNum / 2).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - } + // Use all outBW channels to share the data write + // Each channel gets a portion of the data + for (i <- 0 until outBW) { + val elementsPerChannel = InputNum / outBW + val startIdx = i * elementsPerChannel + val endIdx = startIdx + elementsPerChannel - 1 + + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + + // Pack corresponding elements into a UInt + val channelData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) + io.bankWrite(i).req.bits.data := channelData + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + io.bankWrite(i).req.bits.wmode := true.B // Accumulate mode } iter_counter := iter_counter + 1.U } + // Output wr_bank for bank_id setting + io.wr_bank_o := wr_bank + // ----------------------------------------------------------------------------- // Reset iter counter, commit cmdResp, return to idle state // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index 55b82f1f..0411f973 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -9,7 +9,7 @@ import framework.balldomain.prototype.vector._ import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.top.GlobalConfig -import framework.balldomain.blink.Status +import framework.balldomain.blink.{BankRead, BankWrite, Status} import framework.balldomain.prototype.vector.configs.VectorBallParam @instantiable @@ -20,66 +20,71 @@ class VecUnit(val b: GlobalConfig) extends Module { val accWidth = ballConfig.outputWidth val bankWidth = b.memDomain.bankWidth + // Get bandwidth from config (use first VecBall mapping) + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") + .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + @public val io = IO(new Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) val cmdResp = Decoupled(new BallRsComplete(b)) - // Connect to unified bank read/write interface - val bankRead = Vec(b.memDomain.bankNum, Flipped(new SramReadIO(b))) - // Connect to unified bank write interface - val bankWrite = - Vec(b.memDomain.bankNum, Flipped(new SramWriteIO(b))) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) // Status output val status = new Status }) + val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(b)) + val VecLoadUnit: Instance[VecLoadUnit] = Instantiate(new VecLoadUnit(b)) + val VecEX: Instance[VecEXUnit] = Instantiate(new VecEXUnit(b)) + val VecStoreUnit: Instance[VecStoreUnit] = Instantiate(new VecStoreUnit(b)) + // ----------------------------------------------------------------------------- // VECCTRLUNIT // ----------------------------------------------------------------------------- - val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(b)) + VecCtrlUnit.io.cmdReq <> io.cmdReq io.cmdResp <> VecCtrlUnit.io.cmdResp_o // ----------------------------------------------------------------------------- // VECLOADUNIT // ----------------------------------------------------------------------------- - val VecLoadUnit: Instance[VecLoadUnit] = Instantiate(new VecLoadUnit(b)) + VecLoadUnit.io.ctrl_ld_i <> VecCtrlUnit.io.ctrl_ld_o - for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).req <> VecLoadUnit.io.bankReadReq(i) - VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).resp + for (i <- 0 until inBW) { + io.bankRead(i).io.req <> VecLoadUnit.io.bankReadReq(i) + VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).io.resp + // Set bank_id: channel 0 uses op1_bank, channel 1 uses op2_bank + if (i == 0) { + io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o + } else if (i == 1) { + io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o + } } // ----------------------------------------------------------------------------- // VECEX // ----------------------------------------------------------------------------- - val VecEX: Instance[VecEXUnit] = Instantiate(new VecEXUnit(b)) + VecEX.io.ctrl_ex_i <> VecCtrlUnit.io.ctrl_ex_o VecEX.io.ld_ex_i <> VecLoadUnit.io.ld_ex_o // ----------------------------------------------------------------------------- // VECSTOREUNIT // ----------------------------------------------------------------------------- - val VecStoreUnit: Instance[VecStoreUnit] = Instantiate(new VecStoreUnit(b)) VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o - for (i <- 0 until b.memDomain.bankNum) { - io.bankWrite(i) <> VecStoreUnit.io.bankWrite(i) + for (i <- 0 until outBW) { + io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) + // Set bank_id from VecStoreUnit + io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o -// ----------------------------------------------------------------------------- -// Set DontCare -// ----------------------------------------------------------------------------- - // for (i <- 0 until b.sp_banks) { - // io.sramWrite(i) := DontCare - // } - // for (i <- 0 until b.acc_banks) { - // io.accRead(i) := DontCare - // } - // ----------------------------------------------------------------------------- // Status tracking // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/builtin/router/Router.scala b/arch/src/main/scala/framework/builtin/router/Router.scala index 07900dc1..5600bb47 100644 --- a/arch/src/main/scala/framework/builtin/router/Router.scala +++ b/arch/src/main/scala/framework/builtin/router/Router.scala @@ -17,7 +17,7 @@ class Router(val numInputs: Int, val numOutputs: Int) extends Module { @public val io = IO(new Bundle { - val in = Vec(numInputs, Bool()) + val in = Input(Vec(numInputs, Bool())) val out = Vec(numOutputs, Decoupled(UInt(inputChannelIdWidth.W))) }) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 82376170..2be89a57 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -34,9 +34,10 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Bank interface for interaction with Ball Domain // BankRead/BankWrite are used with Flipped at Ball Device side // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) + // Use bbusChannel instead of bankNum to match BallDomain output val ballDomain = new Bundle { - val bankRead = Vec(b.memDomain.bankNum, new BankRead(b)) - val bankWrite = Vec(b.memDomain.bankNum, new BankWrite(b)) + val bankRead = Vec(b.ballDomain.bbusChannel, new BankRead(b)) + val bankWrite = Vec(b.ballDomain.bbusChannel, new BankWrite(b)) } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 216a1f19..15c5afdb 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -22,8 +22,8 @@ class MemMidend(val b: GlobalConfig) extends Module { // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { - val bankRead = Vec(b.memDomain.bankNum, new BankRead(b)) - val bankWrite = Vec(b.memDomain.bankNum, new BankWrite(b)) + val bankRead = Vec(b.ballDomain.bbusChannel, new BankRead(b)) + val bankWrite = Vec(b.ballDomain.bbusChannel, new BankWrite(b)) } // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here @@ -33,16 +33,15 @@ class MemMidend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Basic direct connection: route frontend requests to backend channels // ----------------------------------------------------------------------------- - // Simple mapping: each channel handles requests for a specific bank - // Channel ch handles bank (ch % bankNum) - // Since bankChannel == bankNum (both 32), this is a 1:1 mapping + // Map bbusChannel input channels to bankChannel output channels + // Each input channel is mapped to a backend channel based on modulo for (ch <- 0 until b.memDomain.bankChannel) { - val bankIdx = ch % b.memDomain.bankNum + val inputIdx = ch % b.ballDomain.bbusChannel - // Direct 1:1 connection - io.mem_req(ch).write <> io.frontend.bankWrite(bankIdx).io - io.mem_req(ch).read <> io.frontend.bankRead(bankIdx).io - io.mem_req(ch).bank_id := io.frontend.bankWrite(bankIdx).bank_id + // Map input channels to backend channels + io.mem_req(ch).write <> io.frontend.bankWrite(inputIdx).io + io.mem_req(ch).read <> io.frontend.bankRead(inputIdx).io + io.mem_req(ch).bank_id := io.frontend.bankWrite(inputIdx).bank_id } } diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index b9bfa25d..21b4b0da 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -2,19 +2,14 @@ package sims.verify import chisel3._ import _root_.circt.stage.ChiselStage -import org.chipsalliance.cde.config.{Config, Field, Parameters} import framework.top.GlobalConfig -import framework.balldomain.blink.BlinkIO +import framework.balldomain.blink.{BallRegist, BlinkIO} import framework.balldomain.prototype.vector.VecBall +import framework.balldomain.prototype.relu.ReluBall // import framework.balldomain.prototype.matrix.MatrixBall -// import framework.balldomain.prototype.matrix.configs.MatrixConfig // import framework.balldomain.prototype.transpose.TransposeBall -// import framework.balldomain.prototype.transpose.configs.TransposeConfig // import framework.balldomain.prototype.im2col.Im2colBall -// import framework.balldomain.prototype.im2col.configs.Im2colConfig -// import framework.balldomain.prototype.relu.ReluBall // import framework.balldomain.prototype.nnlut.NNLutBall -// import framework.balldomain.prototype.nnlut.configs.NNLutConfig sealed trait BallType case object VecBallType extends BallType @@ -24,46 +19,38 @@ case object Im2colBallType extends BallType case object ReluBallType extends BallType case object NNLutBallType extends BallType -case object TargetBallKey extends Field[BallType](VecBallType) +class TargetBall(ballType: BallType, b: GlobalConfig) extends Module { -class TargetBall(implicit b: GlobalConfig, p: Parameters) extends Module { + // Determine bandwidth from config first + val (inBW, outBW) = ballType match { + case VecBallType => + val mapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") + .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) + (mapping.inBW, mapping.outBW) + case ReluBallType => + val mapping = b.ballDomain.ballIdMappings.find(_.ballName == "ReluBall") + .getOrElse(throw new IllegalArgumentException("ReluBall not found in config")) + (mapping.inBW, mapping.outBW) + case _ => (2, 4) // Default bandwidth + } - val io = IO(new BlinkIO(b)) + val io = IO(new BlinkIO(b, inBW, outBW)) - p(TargetBallKey) match { + ballType match { case VecBallType => - val ball = Module(new VecBall(b, 0)) // Use id=0 for VecBall + val ball = Module(new VecBall(b)) io <> ball.io - case MatrixBallType => - // val ball = Module(new MatrixBall(MatrixConfig.fromBallDomain(ballParam), 0)) - // io <> ball.io - case Im2colBallType => - // val ball = Module(new Im2colBall(Im2colConfig.fromBallDomain(ballParam), 0)) - // io <> ball.io - case TransposeBallType => - // val ball = Module(new TransposeBall(TransposeConfig.fromBallDomain(ballParam), 0)) - // io <> ball.io case ReluBallType => - // val ball = Module(new ReluBall(ReluConfig.fromBallDomain(ballParam), 0)) - // io <> ball.io - case NNLutBallType => - // val ball = Module(new NNLutBall(NNLutConfig.fromBallDomain(ballParam), 0)) - // io <> ball.io + val ball = Module(new ReluBall(b)) + io <> ball.io + case MatrixBallType => throw new IllegalArgumentException("MatrixBall not implemented") + case Im2colBallType => throw new IllegalArgumentException("Im2colBall not implemented") + case TransposeBallType => throw new IllegalArgumentException("TransposeBall not implemented") + case NNLutBallType => throw new IllegalArgumentException("NNLutBall not implemented") case _ => throw new scala.MatchError("TargetBall does not handle this ball type") } } -class WithTargetBall(ballType: BallType) - extends Config((site, here, up) => { - case TargetBallKey => ballType - }) - -class CustomBallTopConfig(ballType: BallType) - extends Config( - // new WithBlink ++ - new WithTargetBall(ballType) - ) - object BallTopMain extends App { // Select Ball type from command line arguments @@ -86,12 +73,10 @@ object BallTopMain extends App { } } - implicit val b: GlobalConfig = GlobalConfig() - implicit val params: Parameters = new Config(new CustomBallTopConfig(ballType)) + val b: GlobalConfig = GlobalConfig() ChiselStage.emitSystemVerilogFile( - new TargetBall()(b, params), - // Remaining parameters passed to firtool + new TargetBall(ballType, b), firtoolOpts = args.drop(1), args = Array.empty ) From 57fb795f2c958e482649ee815b9fcbc7a0a67528 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 2 Jan 2026 15:41:09 +0800 Subject: [PATCH 024/238] [arch] refactor: streamline BBus and MemRouter for flat indexing and improve ReluBall integration --- .../framework/balldomain/bbus/bbus.scala | 15 +- .../balldomain/bbus/memrouter/memRouter.scala | 144 ++++++------------ .../balldomain/prototype/relu/Relu.scala | 137 ++++++++--------- .../balldomain/prototype/relu/ReluBall.scala | 14 +- .../balldomain/prototype/vector/VecBall.scala | 10 +- .../prototype/vector/VecLoadUnit.scala | 63 +++----- .../prototype/vector/VecStoreUnit.scala | 15 +- .../balldomain/prototype/vector/VecUnit.scala | 29 +++- .../framework/builtin/router/Router.scala | 8 +- 9 files changed, 177 insertions(+), 258 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index f962ba41..2f0f2112 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -65,20 +65,24 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module // Connect each ball's bankRead/bankWrite based on its configured bandwidth // All requests from balls will go through Router inside MemRouter // and become bbusChannel outputs (not bankNum) + // Build flat index mapping from ball+channel to flat index + var readFlatIdx = 0 + var writeFlatIdx = 0 for (i <- 0 until numBalls) { val ballMapping = b.ballDomain.ballIdMappings(i) val inBW = ballMapping.inBW val outBW = ballMapping.outBW // Connect all input bandwidth channels (bankRead) to MemRouter - // MemRouter will use Router to route all ball requests to bbusChannel outputs - for (j <- 0 until inBW.min(b.memDomain.bankNum)) { - memoryrouter.io.bankRead_i(i)(j) <> balls(i).Blink.bankRead(j) + for (j <- 0 until inBW) { + memoryrouter.io.bankRead_i(readFlatIdx) <> balls(i).Blink.bankRead(j) + readFlatIdx += 1 } // Connect all output bandwidth channels (bankWrite) to MemRouter - for (j <- 0 until outBW.min(b.memDomain.bankNum)) { - memoryrouter.io.bankWrite_i(i)(j) <> balls(i).Blink.bankWrite(j) + for (j <- 0 until outBW) { + memoryrouter.io.bankWrite_i(writeFlatIdx) <> balls(i).Blink.bankWrite(j) + writeFlatIdx += 1 } } @@ -92,7 +96,6 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module for (i <- 0 until numBalls) { pmc.io.cmdReq_i(i).valid := cmdRouter.io.cmdReq_i(i).fire pmc.io.cmdReq_i(i).bits := cmdRouter.io.cmdReq_i(i).bits - // Remove delay caused by RoB blocking preventing commit pmc.io.cmdResp_o(i).valid := cmdRouter.io.cmdResp_o(i).valid pmc.io.cmdResp_o(i).bits := cmdRouter.io.cmdResp_o(i).bits } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 8b871b83..705ddb3f 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -9,62 +9,31 @@ import framework.builtin.router.Router @instantiable class MemRouter(val b: GlobalConfig) extends Module { - val bbusChannel = b.ballDomain.bbusChannel - val numBalls = b.ballDomain.ballNum - - // Calculate total input channels from all balls + val bbusChannel = b.ballDomain.bbusChannel + val numBalls = b.ballDomain.ballNum val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum @public val io = IO(new Bundle { - val bankRead_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankRead(b))) - val bankWrite_i = Vec(numBalls, Vec(b.memDomain.bankNum, new BankWrite(b))) - + val bankRead_i = Vec(totalReadChannels, new BankRead(b)) + val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) val bankRead_o = Vec(bbusChannel, Flipped(new BankRead(b))) val bankWrite_o = Vec(bbusChannel, Flipped(new BankWrite(b))) }) - // Build channel mappings at compile time - // Map flat index -> (ballIdx, channelIdx) - val readMapping: Seq[(Int, Int)] = { - var flatIdx = 0 - val mapping = scala.collection.mutable.ArrayBuffer[(Int, Int)]() - for (ballIdx <- 0 until numBalls) { - val inBW = b.ballDomain.ballIdMappings(ballIdx).inBW - for (chIdx <- 0 until inBW.min(b.memDomain.bankNum)) { - mapping += ((ballIdx, chIdx)) - flatIdx += 1 - } - } - mapping.toSeq - } - - val writeMapping: Seq[(Int, Int)] = { - var flatIdx = 0 - val mapping = scala.collection.mutable.ArrayBuffer[(Int, Int)]() - for (ballIdx <- 0 until numBalls) { - val outBW = b.ballDomain.ballIdMappings(ballIdx).outBW - for (chIdx <- 0 until outBW.min(b.memDomain.bankNum)) { - mapping += ((ballIdx, chIdx)) - flatIdx += 1 - } - } - mapping.toSeq - } + // No need for mapping anymore - flat index directly corresponds to ball channels // Create valid signals for Router inputs val readValidSignals = Wire(Vec(totalReadChannels, Bool())) val writeValidSignals = Wire(Vec(totalWriteChannels, Bool())) for (i <- 0 until totalReadChannels) { - val (ballIdx, channelIdx) = readMapping(i) - readValidSignals(i) := io.bankRead_i(ballIdx)(channelIdx).io.req.valid + readValidSignals(i) := io.bankRead_i(i).io.req.valid } for (i <- 0 until totalWriteChannels) { - val (ballIdx, channelIdx) = writeMapping(i) - writeValidSignals(i) := io.bankWrite_i(ballIdx)(channelIdx).io.req.valid + writeValidSignals(i) := io.bankWrite_i(i).io.req.valid } // Instantiate Routers @@ -79,23 +48,33 @@ class MemRouter(val b: GlobalConfig) extends Module { writeRouter.io.in(i) := writeValidSignals(i) } + // Initialize all bankRead_i and bankWrite_i channels with defaults + for (i <- 0 until totalReadChannels) { + io.bankRead_i(i).io.req.ready := false.B + io.bankRead_i(i).io.resp.valid := false.B + io.bankRead_i(i).io.resp.bits := 0.U.asTypeOf(io.bankRead_i(i).io.resp.bits.cloneType) + } + for (i <- 0 until totalWriteChannels) { + io.bankWrite_i(i).io.req.ready := false.B + io.bankWrite_i(i).io.resp.valid := false.B + io.bankWrite_i(i).io.resp.bits := 0.U.asTypeOf(io.bankWrite_i(i).io.resp.bits.cloneType) + } + // Connect Router outputs to bankRead_o and bankWrite_o for (outIdx <- 0 until bbusChannel) { // Read routing - use MuxCase to select based on Router output val readSelectedIdx = readRouter.io.out(outIdx).bits val readCanTransmit = readRouter.io.out(outIdx).valid && io.bankRead_o(outIdx).io.req.ready - val readReqValidCases = readMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).io.req.valid + val readReqValidCases = (0 until totalReadChannels).map { flatIdx => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).io.req.valid } io.bankRead_o(outIdx).io.req.valid := MuxCase( false.B, readReqValidCases :+ (!readCanTransmit) -> false.B ) - val readReqBitsCases = readMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).io.req.bits + val readReqBitsCases = (0 until totalReadChannels).map { flatIdx => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).io.req.bits } io.bankRead_o(outIdx).io.req.bits := MuxCase( DontCare, @@ -103,99 +82,74 @@ class MemRouter(val b: GlobalConfig) extends Module { ) // Build MuxCase for read rob_id and bank_id - val readRobIdCases = readMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).rob_id + val readRobIdCases = (0 until totalReadChannels).map { flatIdx => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).rob_id } io.bankRead_o(outIdx).rob_id := MuxCase(0.U, readRobIdCases) - val readBankIdCases = readMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).bank_id + val readBankIdCases = (0 until totalReadChannels).map { flatIdx => + (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).bank_id } io.bankRead_o(outIdx).bank_id := MuxCase(0.U, readBankIdCases) - // Connect read response back - // Only handle channels that are actually connected (in readMapping) - for ((mapping, flatIdx) <- readMapping.zipWithIndex) { - val (ballIdx, channelIdx) = mapping + // Connect read response back - override defaults for selected channel + for (flatIdx <- 0 until totalReadChannels) { when(readCanTransmit && readSelectedIdx === flatIdx.U) { - io.bankRead_i(ballIdx)(channelIdx).io.req.ready := io.bankRead_o(outIdx).io.req.ready - io.bankRead_i(ballIdx)(channelIdx).io.resp.valid := io.bankRead_o(outIdx).io.resp.valid - io.bankRead_i(ballIdx)(channelIdx).io.resp.bits := io.bankRead_o(outIdx).io.resp.bits - }.otherwise { - io.bankRead_i(ballIdx)(channelIdx).io.req.ready := false.B - io.bankRead_i(ballIdx)(channelIdx).io.resp.valid := false.B - io.bankRead_i(ballIdx)(channelIdx).io.resp.bits := 0.U.asTypeOf( - io.bankRead_i(ballIdx)(channelIdx).io.resp.bits.cloneType - ) + io.bankRead_i(flatIdx).io.req.ready := io.bankRead_o(outIdx).io.req.ready + io.bankRead_i(flatIdx).io.resp.valid := io.bankRead_o(outIdx).io.resp.valid + io.bankRead_i(flatIdx).io.resp.bits := io.bankRead_o(outIdx).io.resp.bits } } // resp.ready: bankRead_o is Flipped, so resp.ready is output (from internal), we drive it from bankRead_i io.bankRead_o(outIdx).io.resp.ready := MuxCase( false.B, - readMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (readCanTransmit && readSelectedIdx === flatIdx.U) -> io.bankRead_i(ballIdx)(channelIdx).io.resp.ready + (0 until totalReadChannels).map { flatIdx => + (readCanTransmit && readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).io.resp.ready } ) - // Write routing - similar to read val writeSelectedIdx = writeRouter.io.out(outIdx).bits val writeCanTransmit = writeRouter.io.out(outIdx).valid && io.bankWrite_o(outIdx).io.req.ready // Build MuxCase for write request (only valid and bits, ready is input) - val writeReqValidCases = writeMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).io.req.valid + val writeReqValidCases = (0 until totalWriteChannels).map { flatIdx => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).io.req.valid } io.bankWrite_o(outIdx).io.req.valid := MuxCase( false.B, writeReqValidCases :+ (!writeCanTransmit) -> false.B ) - val writeReqBitsCases = writeMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).io.req.bits + val writeReqBitsCases = (0 until totalWriteChannels).map { flatIdx => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).io.req.bits } io.bankWrite_o(outIdx).io.req.bits := MuxCase( DontCare, writeReqBitsCases :+ (!writeCanTransmit) -> 0.U.asTypeOf(io.bankWrite_o(outIdx).io.req.bits.cloneType) ) - val writeRobIdCases = writeMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).rob_id + val writeRobIdCases = (0 until totalWriteChannels).map { flatIdx => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).rob_id } io.bankWrite_o(outIdx).rob_id := MuxCase(0.U, writeRobIdCases) - val writeBankIdCases = writeMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).bank_id + val writeBankIdCases = (0 until totalWriteChannels).map { flatIdx => + (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).bank_id } io.bankWrite_o(outIdx).bank_id := MuxCase(0.U, writeBankIdCases) - // Connect write response back - // Only handle channels that are actually connected (in writeMapping) - for ((mapping, flatIdx) <- writeMapping.zipWithIndex) { - val (ballIdx, channelIdx) = mapping + // Connect write response back - override defaults for selected channel + for (flatIdx <- 0 until totalWriteChannels) { when(writeCanTransmit && writeSelectedIdx === flatIdx.U) { - io.bankWrite_i(ballIdx)(channelIdx).io.req.ready := io.bankWrite_o(outIdx).io.req.ready - io.bankWrite_i(ballIdx)(channelIdx).io.resp.valid := io.bankWrite_o(outIdx).io.resp.valid - io.bankWrite_i(ballIdx)(channelIdx).io.resp.bits := io.bankWrite_o(outIdx).io.resp.bits - }.otherwise { - io.bankWrite_i(ballIdx)(channelIdx).io.req.ready := false.B - io.bankWrite_i(ballIdx)(channelIdx).io.resp.valid := false.B - io.bankWrite_i(ballIdx)(channelIdx).io.resp.bits := 0.U.asTypeOf( - io.bankWrite_i(ballIdx)(channelIdx).io.resp.bits.cloneType - ) + io.bankWrite_i(flatIdx).io.req.ready := io.bankWrite_o(outIdx).io.req.ready + io.bankWrite_i(flatIdx).io.resp.valid := io.bankWrite_o(outIdx).io.resp.valid + io.bankWrite_i(flatIdx).io.resp.bits := io.bankWrite_o(outIdx).io.resp.bits } } io.bankWrite_o(outIdx).io.resp.ready := MuxCase( false.B, - writeMapping.zipWithIndex.map { - case ((ballIdx, channelIdx), flatIdx) => - (writeCanTransmit && writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(ballIdx)(channelIdx).io.resp.ready + (0 until totalWriteChannels).map { flatIdx => + (writeCanTransmit && writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).io.resp.ready } ) diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index c3b0eb32..7a73764c 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -8,7 +8,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} import framework.balldomain.prototype.vector._ import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.blink.Status +import framework.balldomain.blink.{BankRead, BankWrite, Status} import framework.top.GlobalConfig import framework.balldomain.prototype.relu.configs.ReluBallParam @@ -19,74 +19,80 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { val inputWidth = ballConfig.inputWidth val bankWidth = b.memDomain.bankWidth + // Get bandwidth from config + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "ReluBall") + .getOrElse(throw new IllegalArgumentException("ReluBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + @public val io = IO(new Bundle { - // cmd interface - val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) - val cmdResp = Decoupled(new BallRsComplete(b)) - - // Connect to unified bank read/write interface - val bankRead = - Vec(b.memDomain.bankNum, Flipped(new SramReadIO(b))) + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new Status + }) - val bankWrite = Vec( - b.memDomain.bankNum, - Flipped(new SramWriteIO(b)) - ) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } - // Status output - val status = new Status - }) + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + } val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) val state = RegInit(idle) - // Store a row of split elements (InputNum elements) - // Store a InputNum x InputNum tile (perform element-wise ReLU then write back) val regArray = RegInit( VecInit(Seq.fill(InputNum)( VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) )) ) - // Counters val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(10.W)) - val cycle_reg = RegInit(0.U(6.W)) - // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) - - // Precompute write data + val waddr_reg = RegInit(0.U(10.W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val raddr_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(10.W)) + val cycle_reg = RegInit(0.U(6.W)) + val iterCnt = RegInit(0.U(32.W)) val writeDataReg = Reg(UInt(bankWidth.W)) val writeMaskReg = Reg(Vec(b.memDomain.bankMaskLen, UInt(1.W))) - // SRAM default assignment - for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).req.valid := false.B - io.bankRead(i).req.bits.addr := 0.U - io.bankRead(i).resp.ready := false.B + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + } + + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + } - io.bankWrite(i).req.valid := false.B - io.bankWrite(i).req.bits.addr := 0.U - io.bankWrite(i).req.bits.data := 0.U - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + for (i <- 0 until inBW) { + io.bankRead(i).bank_id := rbank_reg + } + for (i <- 0 until outBW) { + io.bankWrite(i).bank_id := wbank_reg } - // cmd interface default assignment io.cmdReq.ready := state === idle io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robid_reg + io.cmdResp.bits.rob_id := rob_id_reg - // State machine switch(state) { is(idle) { when(io.cmdReq.fire) { @@ -94,17 +100,13 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { readCounter := 0.U respCounter := 0.U writeCounter := 0.U - - robid_reg := io.cmdReq.bits.rob_id - // For ReLU, output write-back should use decoded wr_bank/addr, not op2_* fields - waddr_reg := 0.U // New ISA: all operations start from row 0 - wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := 0.U // New ISA: all operations start from row 0 - rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U + waddr_reg := 0.U + wbank_reg := io.cmdReq.bits.cmd.wr_bank + raddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + iter_reg := io.cmdReq.bits.cmd.iter + cycle_reg := (io.cmdReq.bits.cmd.iter +& (InputNum.U - 1.U)) / InputNum.U - 1.U } - when(cycle_reg =/= 0.U) { state := sRead readCounter := 0.U @@ -118,18 +120,14 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { is(sRead) { when(readCounter < InputNum.U) { - // Issue read request - readCounter := readCounter + 1.U - io.bankRead(rbank_reg).req.valid := true.B - io.bankRead(rbank_reg).req.bits.addr := raddr_reg + readCounter - + readCounter := readCounter + 1.U + io.bankRead(0).io.req.valid := true.B + io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter } - // Receive response, only raise ready when there are outstanding reads - val dataWord = io.bankRead(rbank_reg).resp.bits.data - // val hasOutstandingRead = readCounter =/= respCounter - io.bankRead(rbank_reg).resp.ready := true.B - when(io.bankRead(rbank_reg).resp.fire) { + val dataWord = io.bankRead(0).io.resp.bits.data + io.bankRead(0).io.resp.ready := true.B + when(io.bankRead(0).io.resp.fire) { for (col <- 0 until InputNum) { val hi = (col + 1) * inputWidth - 1 val lo = col * inputWidth @@ -143,9 +141,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { when(respCounter === InputNum.U) { state := sWrite - // Precompute first write data (row 0, concatenated by column) writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) - // Set write mask (write all) for (i <- 0 until b.memDomain.bankMaskLen) { writeMaskReg(i) := 1.U(1.W) } @@ -153,17 +149,15 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } is(sWrite) { - // Correctly use ready/valid handshake to advance writes, avoid dropped writes - io.bankWrite(wbank_reg).req.valid := writeCounter < InputNum.U - io.bankWrite(wbank_reg).req.bits.addr := waddr_reg + writeCounter - io.bankWrite(wbank_reg).req.bits.data := writeDataReg - io.bankWrite(wbank_reg).req.bits.mask := writeMaskReg + io.bankWrite(0).io.req.valid := writeCounter < InputNum.U + io.bankWrite(0).io.req.bits.addr := waddr_reg + writeCounter + io.bankWrite(0).io.req.bits.data := writeDataReg + io.bankWrite(0).io.req.bits.mask := writeMaskReg when(writeCounter === (InputNum - 1).U) { state := complete }.otherwise { writeCounter := writeCounter + 1.U - // Prepare next row's write data writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) } @@ -172,7 +166,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { is(complete) { when(cycle_reg === 0.U) { io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := robid_reg + io.cmdResp.bits.rob_id := rob_id_reg when(io.cmdResp.fire) { iterCnt := iterCnt + 1.U } @@ -181,7 +175,6 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } } - // Status signals io.status.ready := io.cmdReq.ready io.status.valid := io.cmdResp.valid io.status.idle := (state === idle) diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala index da9d14ef..7cd63bcb 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala @@ -24,25 +24,17 @@ class ReluBall(val b: GlobalConfig) extends Module with BallRegist { def Blink: BlinkIO = io - private val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(b)) + val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(b)) reluUnit.io.cmdReq <> io.cmdReq reluUnit.io.cmdResp <> io.cmdResp for (i <- 0 until inBW) { - reluUnit.io.bankRead(i) <> io.bankRead(i).io + reluUnit.io.bankRead(i) <> io.bankRead(i) } for (i <- 0 until outBW) { - reluUnit.io.bankWrite(i) <> io.bankWrite(i).io - } - - for (i <- 0 until inBW) { - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - } - - for (i <- 0 until outBW) { - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id + reluUnit.io.bankWrite(i) <> io.bankWrite(i) io.bankWrite(i).io.req.bits.wmode := false.B } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala index 5f04a294..f1ae02d7 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala @@ -8,7 +8,7 @@ import framework.balldomain.prototype.vector.VecUnit import framework.top.GlobalConfig /** - * VecBall - A vector computation Ball that complies with the Blink protocol + * VecBall */ @instantiable class VecBall(val b: GlobalConfig) extends Module with BallRegist { @@ -33,14 +33,6 @@ class VecBall(val b: GlobalConfig) extends Module with BallRegist { for (i <- 0 until outBW) { vecUnit.io.bankWrite(i) <> io.bankWrite(i) - } - - for (i <- 0 until inBW) { - io.bankRead(i).rob_id := io.cmdReq.bits.rob_id - } - - for (i <- 0 until outBW) { - io.bankWrite(i).rob_id := io.cmdReq.bits.rob_id io.bankWrite(i).io.req.bits.wmode := true.B } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index f3dc1246..a5ab6396 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -36,38 +36,31 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req(b))) val ld_ex_o = Decoupled(new ld_ex_req(b)) - // Output current op1_bank and op2_bank for bank_id setting val op1_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) val op2_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) }) - val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - - // Output op1_bank and op2_bank for bank_id setting - io.op1_bank_o := op1_bank - io.op2_bank_o := op2_bank - val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) - val mode = RegInit(0.U(1.W)) - + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) + val mode = RegInit(0.U(1.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) + val ld_ex_valid_reg = RegInit(false.B) + val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) + val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) + val ld_ex_iter_reg = RegInit(0.U(10.W)) - // Output register to break combinational logic loop - val ld_ex_valid_reg = RegInit(false.B) - val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) - val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) - val ld_ex_iter_reg = RegInit(0.U(10.W)) - - // Default assignment for each bank read request for (i <- 0 until inBW) { io.bankReadReq(i).valid := false.B io.bankReadReq(i).bits.addr := 0.U } + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank io.ctrl_ld_i.ready := state === idle // ----------------------------------------------------------------------------- @@ -90,38 +83,29 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { } when(mode === 0.U) { // ----------------------------------------------------------------------------- -// Send SRAM read request (only when output register is idle) +// Send SRAM read request // ----------------------------------------------------------------------------- when(state === busy && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - val op1_channel = op1_bank % inBW.U - val op2_channel = op2_bank % inBW.U - io.bankReadReq(op1_channel).valid := iter_counter < iter - io.bankReadReq(op1_channel).bits.addr := op1_addr + iter_counter - - io.bankReadReq(op2_channel).valid := iter_counter < iter - io.bankReadReq(op2_channel).bits.addr := op2_addr + iter_counter - iter_counter := iter_counter + 1.U + io.bankReadReq(0).valid := iter_counter < iter + io.bankReadReq(0).bits.addr := op1_addr + iter_counter + io.bankReadReq(1).valid := iter_counter < iter + io.bankReadReq(1).bits.addr := op2_addr + iter_counter + iter_counter := iter_counter + 1.U } // ----------------------------------------------------------------------------- -// SRAM returns data and passes to EX unit (use register to break combinational logic loop) +// SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- - // ready signal for bankReadResp: can receive when there's no pending data or downstream has received - /* io.bankReadResp.foreach { resp => resp.ready := !ld_ex_valid_reg || io.ld_ex_o.ready } */ - // Receive SRAM data and cache to register - val op1_channel = op1_bank % inBW.U - val op2_channel = op2_bank % inBW.U - when(io.bankReadResp(op1_channel).valid && io.bankReadResp(op2_channel).valid && + when(io.bankReadResp(0).valid && io.bankReadResp(1).valid && (!ld_ex_valid_reg || io.ld_ex_o.ready) && (state === busy)) { ld_ex_valid_reg := true.B - ld_ex_op1_reg := io.bankReadResp(op1_channel).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - ld_ex_op2_reg := io.bankReadResp(op2_channel).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_op2_reg := io.bankReadResp(1).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) ld_ex_iter_reg := iter_counter }.elsewhen(io.ld_ex_o.ready) { ld_ex_valid_reg := false.B } - // Output comes from register io.ld_ex_o.valid := ld_ex_valid_reg io.ld_ex_o.bits.op1 := ld_ex_op1_reg io.ld_ex_o.bits.op2 := ld_ex_op2_reg @@ -136,7 +120,6 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { iter_counter := 0.U } }.otherwise { - // Default assignment io.ld_ex_o.valid := false.B io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 49bc6526..8665ebae 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -37,22 +37,15 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { val io = IO(new Bundle { val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req(b))) val ex_st_i = Flipped(Decoupled(new ex_st_req(b))) - - // Unified bank write interface (writes use accumulate mode) - // outBW channels share the data write val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) - - // Output current wr_bank for bank_id setting val wr_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val cmdResp_o = Valid(new Bundle { val commit = Bool() }) }) - val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) - + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index 0411f973..efcaa096 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -6,7 +6,6 @@ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.balldomain.prototype.vector._ -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.top.GlobalConfig import framework.balldomain.blink.{BankRead, BankWrite, Status} @@ -28,16 +27,27 @@ class VecUnit(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) - val cmdResp = Decoupled(new BallRsComplete(b)) - + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) val bankRead = Vec(inBW, Flipped(new BankRead(b))) val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) - - // Status output - val status = new Status + val status = new Status }) + // Register to store rob_id when command is received + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + // Set rob_id for all bankRead and bankWrite channels from register + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + } + val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(b)) val VecLoadUnit: Instance[VecLoadUnit] = Instantiate(new VecLoadUnit(b)) val VecEX: Instance[VecEXUnit] = Instantiate(new VecEXUnit(b)) @@ -58,7 +68,6 @@ class VecUnit(val b: GlobalConfig) extends Module { for (i <- 0 until inBW) { io.bankRead(i).io.req <> VecLoadUnit.io.bankReadReq(i) VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).io.resp - // Set bank_id: channel 0 uses op1_bank, channel 1 uses op2_bank if (i == 0) { io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o } else if (i == 1) { @@ -79,6 +88,10 @@ class VecUnit(val b: GlobalConfig) extends Module { VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o for (i <- 0 until outBW) { + // VecUnit receives write requests from VecBall, forwards to VecStoreUnit + // io.bankWrite is Flipped(new BankWrite(b)) so io is output from VecUnit + // VecStoreUnit.io.bankWrite is Flipped(SramWriteIO) so it's input to VecStoreUnit + // Connect: VecUnit outputs to VecStoreUnit inputs io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) // Set bank_id from VecStoreUnit io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o diff --git a/arch/src/main/scala/framework/builtin/router/Router.scala b/arch/src/main/scala/framework/builtin/router/Router.scala index 5600bb47..921a63ba 100644 --- a/arch/src/main/scala/framework/builtin/router/Router.scala +++ b/arch/src/main/scala/framework/builtin/router/Router.scala @@ -21,14 +21,10 @@ class Router(val numInputs: Int, val numOutputs: Int) extends Module { val out = Vec(numOutputs, Decoupled(UInt(inputChannelIdWidth.W))) }) - // For each output channel, if ready, select an input with priority for (outIdx <- 0 until numOutputs) { - // Count how many inputs are valid val numValidInputs = PopCount(io.in) - - // Select one input with priority from all valid inputs - val selectedIdx = PriorityEncoder(io.in) - val hasValidInput = numValidInputs > 0.U + val selectedIdx = PriorityEncoder(io.in) + val hasValidInput = numValidInputs > 0.U io.out(outIdx).valid := hasValidInput && io.out(outIdx).ready io.out(outIdx).bits := selectedIdx.asUInt.asTypeOf(io.out(outIdx).bits.cloneType) From 06b38bc37595a10ad5d15297a79a78609516b9da Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 16:17:42 +0800 Subject: [PATCH 025/238] [arch] refactor: employ composition over inheritance to streamline the customisation of blink status signals. feat: add domain channels --- arch/src/main/scala/README.md | 2 +- .../examples/toy/balldomain/BallDomain.scala | 2 - .../examples/toy/balldomain/bbus/README.md | 10 +- .../toy/balldomain/bbus/busRegister.scala | 4 +- .../framework/balldomain/bbus/bbus.scala | 70 +++----- .../bbus/cmdrouter/CmdReqRouter.scala | 26 --- .../bbus/cmdrouter/CmdRespRouter.scala | 23 --- .../balldomain/bbus/cmdrouter/CmdRouter.scala | 13 +- .../balldomain/bbus/memrouter/Router.scala | 24 +++ .../bbus/memrouter/ballReqCtrl.scala | 13 ++ .../balldomain/bbus/memrouter/memRouter.scala | 155 ++---------------- .../framework/balldomain/blink/baseball.scala | 11 +- .../framework/balldomain/blink/blink.scala | 45 +++-- .../balldomain/configs/BallDomainParam.scala | 13 +- .../framework/balldomain/configs/default.json | 8 +- .../framework/balldomain/prototype/README.md | 14 +- .../balldomain/prototype/relu/Relu.scala | 23 +-- .../balldomain/prototype/relu/ReluBall.scala | 16 +- .../balldomain/prototype/vector/VecBall.scala | 15 +- .../balldomain/prototype/vector/VecUnit.scala | 21 +-- .../framework/builtin/router/Router.scala | 32 ---- .../scala/framework/memdomain/MemDomain.scala | 6 +- .../memdomain/backend/banks/SramBank.scala | 5 - .../memdomain/midend/MemMidend.scala | 6 +- .../framework/top/channels/Channel.scala | 31 ++++ .../framework/top/channels/headerBuffer.scala | 30 ++++ .../main/scala/sims/verify/TargetConfig.scala | 46 +++--- 27 files changed, 254 insertions(+), 410 deletions(-) delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala create mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala create mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala delete mode 100644 arch/src/main/scala/framework/builtin/router/Router.scala create mode 100644 arch/src/main/scala/framework/top/channels/Channel.scala create mode 100644 arch/src/main/scala/framework/top/channels/headerBuffer.scala diff --git a/arch/src/main/scala/README.md b/arch/src/main/scala/README.md index 19c450ef..28cc9d5e 100644 --- a/arch/src/main/scala/README.md +++ b/arch/src/main/scala/README.md @@ -18,7 +18,7 @@ Main functional modules include: ``` scala/ ├── framework/ - Buckyball core framework -│ ├── blink/ - Blink communication components +│ ├── blink/ - blink communication components │ ├── builtin/ - Built-in hardware components │ │ ├── frontend/ - Frontend processing components │ │ ├── memdomain/ - Memory domain implementation diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index e8f64a27..065b8b16 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -27,8 +27,6 @@ class BallDomain(val b: GlobalConfig) extends Module { @public val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) - require(b.memDomain.balldomainChannel == b.ballDomain.bbusChannel, "balldomainChannel must be equal to bbusChannel") - val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) val ballRs: Instance[BallReservationStation] = Instantiate(new BallReservationStation(b)) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/README.md b/arch/src/main/scala/examples/toy/balldomain/bbus/README.md index ad90e78d..9aca5eb0 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/README.md +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/README.md @@ -6,7 +6,7 @@ This directory contains the implementation of Buckyball's ball domain bus system This directory implements two core components: - **BallBus**: Ball domain bus main module, manages SRAM access by multiple Ball nodes -- **BBusRouter**: Bus router, provides routing functionality for Blink interface +- **BBusRouter**: Bus router, provides routing functionality for blink interface ## Code Structure @@ -25,7 +25,7 @@ bbus/ **router.scala** (Routing module) - Implements routing functionality based on BBusNode -- Provides Blink protocol interface encapsulation +- Provides blink protocol interface encapsulation ## Module Description @@ -67,7 +67,7 @@ class BallBus(maxReadBW: Int, maxWriteBW: Int, numBalls: Int) extends LazyModule ### router.scala -**Main functionality**: Bus router, provides routing functionality for Blink protocol interface +**Main functionality**: Bus router, provides routing functionality for blink protocol interface **Key components**: @@ -86,11 +86,11 @@ class BBusRouter extends LazyModule { **Routing functionality**: - Implements standard Ball node interface based on BBusNode -- Provides Blink protocol encapsulation and conversion +- Provides blink protocol encapsulation and conversion - Supports configurable read/write bandwidth parameters **Inputs/Outputs**: -- Input: Blink protocol interface +- Input: blink protocol interface - Output: BBusNode standard interface - Edge cases: Depends on validity of node.edges.in.head diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 9e73854a..d8cf9266 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -5,7 +5,7 @@ import chisel3.util._ import chisel3.experimental.hierarchy.instantiable import framework.top.GlobalConfig import framework.balldomain.bbus.BBus -import framework.balldomain.blink.BallRegist +import framework.balldomain.blink.HasBlink import framework.balldomain.prototype.vector.VecBall import framework.balldomain.prototype.relu.ReluBall @@ -17,7 +17,7 @@ class BBusModule(b: GlobalConfig) extends BBus( b, b.ballDomain.ballIdMappings.map { mapping => - val ballGenerator: () => BallRegist with Module = mapping.ballName match { + val ballGenerator: () => HasBlink with Module = mapping.ballName match { case "VecBall" => () => new VecBall(b) case "ReluBall" => () => new ReluBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 2f0f2112..62f97899 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -5,30 +5,40 @@ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.blink.BallRegist +import framework.balldomain.blink.HasBlink import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter import framework.balldomain.blink.{BankRead, BankWrite} +import framework.top.channels.ChannelIO /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices */ @instantiable -class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module]) extends Module { - val numBalls = b.ballDomain.ballNum - val bbusChannel = b.ballDomain.bbusChannel - +class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) extends Module { + val numBalls = b.ballDomain.ballNum + val bbusProducerChannels = b.ballDomain.bbusProducerChannels + val bbusConsumerChannels = b.ballDomain.bbusConsumerChannels + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + + // Rs - bbus - balls + @public + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) + @public + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) + // balls - bbus @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) + val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) + val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + // bbus - mem @public - val bankRead = IO(Vec(bbusChannel, Flipped(new BankRead(b)))) + val channelToMemDomain = IO(Vec(bbusProducerChannels, new ChannelIO(b))) @public - val bankWrite = IO(Vec(bbusChannel, Flipped(new BankWrite(b)))) + val channelFromMemDomain = IO(Vec(bbusConsumerChannels, Flipped(new ChannelIO(b)))) - // Instantiate all registered Balls val balls = ballGenerators.map(gen => Module(gen())) val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b)) @@ -38,23 +48,20 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module // cmd router // ----------------------------------------------------------------------------- - val idle_ball = Wire(Vec(numBalls, Bool())) - for (i <- 0 until numBalls) { - idle_ball(i) := balls(i).Blink.cmdReq.ready - } + val idle_ball = VecInit(balls.map(_.blink.cmdReq.ready)) cmdRouter.io.cmdReq_i <> cmdReq cmdRouter.io.ballIdle := idle_ball for (i <- 0 until numBalls) { - balls(i).Blink.cmdReq.valid := cmdRouter.io.cmdReq_o.valid && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) - balls(i).Blink.cmdReq.bits := cmdRouter.io.cmdReq_o.bits + balls(i).blink.cmdReq.valid := cmdRouter.io.cmdReq_o.valid && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) + balls(i).blink.cmdReq.bits := cmdRouter.io.cmdReq_o.bits - cmdRouter.io.cmdResp_i(i) <> balls(i).Blink.cmdResp + cmdRouter.io.cmdResp_i(i) <> balls(i).blink.cmdResp } cmdRouter.io.cmdReq_o.ready := VecInit((0 until numBalls).map(i => - balls(i).Blink.cmdReq.ready && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) + balls(i).blink.cmdReq.ready && (cmdRouter.io.cmdReq_o.bits.cmd.bid === i.U) )).asUInt.orR cmdResp <> cmdRouter.io.cmdResp_o @@ -62,33 +69,6 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => BallRegist with Module // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- - // Connect each ball's bankRead/bankWrite based on its configured bandwidth - // All requests from balls will go through Router inside MemRouter - // and become bbusChannel outputs (not bankNum) - // Build flat index mapping from ball+channel to flat index - var readFlatIdx = 0 - var writeFlatIdx = 0 - for (i <- 0 until numBalls) { - val ballMapping = b.ballDomain.ballIdMappings(i) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW - - // Connect all input bandwidth channels (bankRead) to MemRouter - for (j <- 0 until inBW) { - memoryrouter.io.bankRead_i(readFlatIdx) <> balls(i).Blink.bankRead(j) - readFlatIdx += 1 - } - - // Connect all output bandwidth channels (bankWrite) to MemRouter - for (j <- 0 until outBW) { - memoryrouter.io.bankWrite_i(writeFlatIdx) <> balls(i).Blink.bankWrite(j) - writeFlatIdx += 1 - } - } - - // MemRouter outputs bbusChannel channels (routed from all ball requests) - bankRead <> memoryrouter.io.bankRead_o - bankWrite <> memoryrouter.io.bankWrite_o // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala deleted file mode 100644 index 18c49dee..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdReqRouter.scala +++ /dev/null @@ -1,26 +0,0 @@ -package framework.balldomain.bbus.cmdrouter - -import chisel3._ -import chisel3.util._ -import framework.top.GlobalConfig -import framework.balldomain.rs.BallRsIssue - -class CmdReqRouter(val b: GlobalConfig, val numBalls: Int) extends Module { - - val io = IO(new Bundle { - val cmdReq_i = Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b)))) - val ballIdle = Input(Vec(numBalls, Bool())) - val cmdReq_o = Decoupled(new BallRsIssue(b)) - }) - - val arbiter = Module(new RRArbiter(new BallRsIssue(b), numBalls)) - - for (i <- 0 until numBalls) { - arbiter.io.in(i).valid := io.cmdReq_i(i).valid && io.ballIdle(i) - arbiter.io.in(i).bits := io.cmdReq_i(i).bits - io.cmdReq_i(i).ready := arbiter.io.in(i).ready && io.ballIdle(i) - } - - io.cmdReq_o <> arbiter.io.out - -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala deleted file mode 100644 index 4a14fec1..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRespRouter.scala +++ /dev/null @@ -1,23 +0,0 @@ -package framework.balldomain.bbus.cmdrouter - -import chisel3._ -import chisel3.util._ -import framework.top.GlobalConfig -import framework.balldomain.rs.BallRsComplete - -class CmdRespRouter(b: GlobalConfig, numBalls: Int) extends Module { - - val io = IO(new Bundle { - val cmdResp_i = Vec(numBalls, Flipped(Decoupled(new BallRsComplete(b)))) - val cmdResp_o = Decoupled(new BallRsComplete(b)) - }) - - val arbiter = Module(new RRArbiter(new BallRsComplete(b), numBalls)) - - for (i <- 0 until numBalls) { - arbiter.io.in(i) <> io.cmdResp_i(i) - } - - io.cmdResp_o <> arbiter.io.out - -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala index f547371d..8e1c0b3f 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala @@ -4,7 +4,6 @@ import chisel3._ import chisel3.util._ import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.bbus.cmdrouter.CmdReqRouter import chisel3.experimental.hierarchy.{instantiable, public} @instantiable @@ -21,11 +20,15 @@ class CmdRouter(val b: GlobalConfig) extends Module { val ballIdle = Input(Vec(numBalls, Bool())) }) - val reqRouter = Module(new CmdReqRouter(b, numBalls)) + val arbiter = Module(new RRArbiter(new BallRsIssue(b), numBalls)) - reqRouter.io.cmdReq_i <> io.cmdReq_i - reqRouter.io.ballIdle := io.ballIdle - io.cmdReq_o <> reqRouter.io.cmdReq_o + for (i <- 0 until numBalls) { + arbiter.io.in(i).valid := io.cmdReq_i(i).valid && io.ballIdle(i) + arbiter.io.in(i).bits := io.cmdReq_i(i).bits + io.cmdReq_i(i).ready := arbiter.io.in(i).ready && io.ballIdle(i) + } + + io.cmdReq_o <> arbiter.io.out for (i <- 0 until numBalls) { io.cmdResp_o(i) <> io.cmdResp_i(i) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala new file mode 100644 index 00000000..e2298922 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala @@ -0,0 +1,24 @@ +package framework.balldomain.bbus.memrouter + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} + +/** + * Router: + * + * Input: valid signals for each input channel and channel num requests + * Output: source input channel ID for each output channel + */ +@instantiable +class Router(val numInputs: Int, val numOutputs: Int, val maxPerChannelWidth: Int) extends Module { + val inputChannelIdWidth = log2Ceil(numInputs) + val outputChannelIdWidth = log2Ceil(numOutputs) + + @public + val io = IO(new Bundle { + val in = Flipped(Valid(Vec(numInputs, UInt(maxPerChannelWidth.W)))) + val out = Vec(numOutputs, Decoupled(UInt(inputChannelIdWidth.W))) + }) + +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala new file mode 100644 index 00000000..50b12476 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala @@ -0,0 +1,13 @@ +package framework.balldomain.bbus.memrouter + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.balldomain.blink.BankRead + +@instantiable +class BallReqCtrl(val b: GlobalConfig) extends Module { + @public + val io = IO(new Bundle {}) +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 705ddb3f..d00436df 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -5,157 +5,28 @@ import chisel3.util._ import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig -import framework.builtin.router.Router +import framework.balldomain.bbus.memrouter.Router @instantiable class MemRouter(val b: GlobalConfig) extends Module { - val bbusChannel = b.ballDomain.bbusChannel - val numBalls = b.ballDomain.ballNum - val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum - val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum + // balls - (readChannels/writeChannels) - bbus - (bbusChannel) - memdomain + val bbusProducerChannels = b.ballDomain.bbusProducerChannels + val bbusConsumerChannels = b.ballDomain.bbusConsumerChannels + val numBalls = b.ballDomain.ballNum + val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum + val maxPerChannelWidth = b.ballDomain.ballIdMappings.flatMap(m => Seq(m.inBW, m.outBW)).max @public val io = IO(new Bundle { val bankRead_i = Vec(totalReadChannels, new BankRead(b)) val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) - val bankRead_o = Vec(bbusChannel, Flipped(new BankRead(b))) - val bankWrite_o = Vec(bbusChannel, Flipped(new BankWrite(b))) + val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) + val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) }) - // No need for mapping anymore - flat index directly corresponds to ball channels - - // Create valid signals for Router inputs - val readValidSignals = Wire(Vec(totalReadChannels, Bool())) - val writeValidSignals = Wire(Vec(totalWriteChannels, Bool())) - - for (i <- 0 until totalReadChannels) { - readValidSignals(i) := io.bankRead_i(i).io.req.valid - } - - for (i <- 0 until totalWriteChannels) { - writeValidSignals(i) := io.bankWrite_i(i).io.req.valid - } - - // Instantiate Routers - val readRouter: Instance[Router] = Instantiate(new Router(totalReadChannels, bbusChannel)) - val writeRouter: Instance[Router] = Instantiate(new Router(totalWriteChannels, bbusChannel)) - - // Connect Router inputs (io.in is input, so we connect from Wire to it) - for (i <- 0 until totalReadChannels) { - readRouter.io.in(i) := readValidSignals(i) - } - for (i <- 0 until totalWriteChannels) { - writeRouter.io.in(i) := writeValidSignals(i) - } - - // Initialize all bankRead_i and bankWrite_i channels with defaults - for (i <- 0 until totalReadChannels) { - io.bankRead_i(i).io.req.ready := false.B - io.bankRead_i(i).io.resp.valid := false.B - io.bankRead_i(i).io.resp.bits := 0.U.asTypeOf(io.bankRead_i(i).io.resp.bits.cloneType) - } - for (i <- 0 until totalWriteChannels) { - io.bankWrite_i(i).io.req.ready := false.B - io.bankWrite_i(i).io.resp.valid := false.B - io.bankWrite_i(i).io.resp.bits := 0.U.asTypeOf(io.bankWrite_i(i).io.resp.bits.cloneType) - } - - // Connect Router outputs to bankRead_o and bankWrite_o - for (outIdx <- 0 until bbusChannel) { - // Read routing - use MuxCase to select based on Router output - val readSelectedIdx = readRouter.io.out(outIdx).bits - val readCanTransmit = readRouter.io.out(outIdx).valid && io.bankRead_o(outIdx).io.req.ready - val readReqValidCases = (0 until totalReadChannels).map { flatIdx => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).io.req.valid - } - io.bankRead_o(outIdx).io.req.valid := MuxCase( - false.B, - readReqValidCases :+ (!readCanTransmit) -> false.B - ) - - val readReqBitsCases = (0 until totalReadChannels).map { flatIdx => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).io.req.bits - } - io.bankRead_o(outIdx).io.req.bits := MuxCase( - DontCare, - readReqBitsCases :+ (!readCanTransmit) -> 0.U.asTypeOf(io.bankRead_o(outIdx).io.req.bits.cloneType) - ) - - // Build MuxCase for read rob_id and bank_id - val readRobIdCases = (0 until totalReadChannels).map { flatIdx => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).rob_id - } - io.bankRead_o(outIdx).rob_id := MuxCase(0.U, readRobIdCases) - - val readBankIdCases = (0 until totalReadChannels).map { flatIdx => - (readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).bank_id - } - io.bankRead_o(outIdx).bank_id := MuxCase(0.U, readBankIdCases) - - // Connect read response back - override defaults for selected channel - for (flatIdx <- 0 until totalReadChannels) { - when(readCanTransmit && readSelectedIdx === flatIdx.U) { - io.bankRead_i(flatIdx).io.req.ready := io.bankRead_o(outIdx).io.req.ready - io.bankRead_i(flatIdx).io.resp.valid := io.bankRead_o(outIdx).io.resp.valid - io.bankRead_i(flatIdx).io.resp.bits := io.bankRead_o(outIdx).io.resp.bits - } - } - // resp.ready: bankRead_o is Flipped, so resp.ready is output (from internal), we drive it from bankRead_i - io.bankRead_o(outIdx).io.resp.ready := MuxCase( - false.B, - (0 until totalReadChannels).map { flatIdx => - (readCanTransmit && readSelectedIdx === flatIdx.U) -> io.bankRead_i(flatIdx).io.resp.ready - } - ) - - val writeSelectedIdx = writeRouter.io.out(outIdx).bits - val writeCanTransmit = writeRouter.io.out(outIdx).valid && io.bankWrite_o(outIdx).io.req.ready - - // Build MuxCase for write request (only valid and bits, ready is input) - val writeReqValidCases = (0 until totalWriteChannels).map { flatIdx => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).io.req.valid - } - io.bankWrite_o(outIdx).io.req.valid := MuxCase( - false.B, - writeReqValidCases :+ (!writeCanTransmit) -> false.B - ) - - val writeReqBitsCases = (0 until totalWriteChannels).map { flatIdx => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).io.req.bits - } - io.bankWrite_o(outIdx).io.req.bits := MuxCase( - DontCare, - writeReqBitsCases :+ (!writeCanTransmit) -> 0.U.asTypeOf(io.bankWrite_o(outIdx).io.req.bits.cloneType) - ) - - val writeRobIdCases = (0 until totalWriteChannels).map { flatIdx => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).rob_id - } - io.bankWrite_o(outIdx).rob_id := MuxCase(0.U, writeRobIdCases) - - val writeBankIdCases = (0 until totalWriteChannels).map { flatIdx => - (writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).bank_id - } - io.bankWrite_o(outIdx).bank_id := MuxCase(0.U, writeBankIdCases) - - // Connect write response back - override defaults for selected channel - for (flatIdx <- 0 until totalWriteChannels) { - when(writeCanTransmit && writeSelectedIdx === flatIdx.U) { - io.bankWrite_i(flatIdx).io.req.ready := io.bankWrite_o(outIdx).io.req.ready - io.bankWrite_i(flatIdx).io.resp.valid := io.bankWrite_o(outIdx).io.resp.valid - io.bankWrite_i(flatIdx).io.resp.bits := io.bankWrite_o(outIdx).io.resp.bits - } - } - io.bankWrite_o(outIdx).io.resp.ready := MuxCase( - false.B, - (0 until totalWriteChannels).map { flatIdx => - (writeCanTransmit && writeSelectedIdx === flatIdx.U) -> io.bankWrite_i(flatIdx).io.resp.ready - } - ) - - // Router ready signals - readRouter.io.out(outIdx).ready := io.bankRead_o(outIdx).io.req.ready - writeRouter.io.out(outIdx).ready := io.bankWrite_o(outIdx).io.req.ready - } + val readRouter: Instance[Router] = Instantiate(new Router(totalReadChannels, bbusProducerChannels, maxPerChannelWidth)) + val writeRouter: Instance[Router] = + Instantiate(new Router(totalWriteChannels, bbusProducerChannels, maxPerChannelWidth)) } diff --git a/arch/src/main/scala/framework/balldomain/blink/baseball.scala b/arch/src/main/scala/framework/balldomain/blink/baseball.scala index 672b0db4..b00fc630 100644 --- a/arch/src/main/scala/framework/balldomain/blink/baseball.scala +++ b/arch/src/main/scala/framework/balldomain/blink/baseball.scala @@ -3,7 +3,12 @@ package framework.balldomain.blink import chisel3._ import chisel3.util._ -trait BallRegist { - def Blink: BlinkIO - // def ballId: UInt +// all balls must have a blink interface +trait HasBlink { + def blink: BlinkIO +} + +// can be customized by user to add additional status signals +trait HasBallStatus { + def status: BallStatus } diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index bc3ecb01..a0241718 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -7,25 +7,19 @@ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import chisel3.experimental.hierarchy.{instantiable, public} -// Ball device status bundle -class Status extends Bundle { - val ready = Output(Bool()) - val valid = Output(Bool()) - val idle = Output(Bool()) - val init = Output(Bool()) - val running = Output(Bool()) - val complete = Output(Bool()) - val iter = Output(UInt(32.W)) +class BallStatus extends Bundle { + val idle = Output(Bool()) + val running = Output(Bool()) } -// BankRead with rob_id, bank_id +// SRAMRead with rob_id, bank_id class BankRead(val b: GlobalConfig) extends Bundle { val io = new SramReadIO(b) val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) } -// BankWrite with rob_id, bank_id +// SRAMWrite with rob_id, bank_id // wmode is in SramWriteIO.io.req.bits.wmode: true = accumulate, false = overwrite class BankWrite(val b: GlobalConfig) extends Bundle { val io = new SramWriteIO(b) @@ -33,25 +27,24 @@ class BankWrite(val b: GlobalConfig) extends Bundle { val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) } -// Blink IO Bundle - interface for Ball devices -// inBW: number of input bandwidth channels (bankRead) -// outBW: number of output bandwidth channels (bankWrite) -class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle { +class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle with HasBallStatus { + + def status: BallStatus = new BallStatus() + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) val cmdResp = Decoupled(new BallRsComplete(b)) val bankRead = Vec(inBW, Flipped(new BankRead(b))) val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) - val status = new Status } -@instantiable -class Blink(b: GlobalConfig, inBW: Int, outBW: Int) extends Module { - @public - val io = IO(new BlinkIO(b, inBW, outBW)) +// @instantiable +// class blink(b: GlobalConfig, inBW: Int, outBW: Int) extends Module { +// @public +// val io = IO(new BlinkIO(b, inBW, outBW)) - def cmdReq: DecoupledIO[BallRsIssue] = io.cmdReq - def cmdResp: DecoupledIO[BallRsComplete] = io.cmdResp - def bankRead: Vec[BankRead] = io.bankRead - def bankWrite: Vec[BankWrite] = io.bankWrite - def status: Status = io.status -} +// def cmdReq: DecoupledIO[BallRsIssue] = io.cmdReq +// def cmdResp: DecoupledIO[BallRsComplete] = io.cmdResp +// def bankRead: Vec[BankRead] = io.bankRead +// def bankWrite: Vec[BankWrite] = io.bankWrite +// def status: BallStatus = io.status +// } diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala index 558d690c..34ffce08 100644 --- a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -2,22 +2,17 @@ package framework.balldomain.configs import upickle.default._ -/** - * Ball ID映射配置 - */ case class BallIdMapping( ballId: Int, ballName: String, inBW: Int, outBW: Int) -/** - * BallDomain参数 - */ case class BallDomainParam( - ballNum: Int, - ballIdMappings: Seq[BallIdMapping], - bbusChannel: Int) + ballNum: Int, + ballIdMappings: Seq[BallIdMapping], + bbusProducerChannels: Int, + bbusConsumerChannels: Int) object BallDomainParam { implicit val ballIdMappingRW: ReadWriter[BallIdMapping] = macroRW diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 7c402728..55b5b8c2 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,7 +1,9 @@ { - "ballNum": 1, + "ballNum": 2, "ballIdMappings": [ - {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4} + {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, + {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1} ], - "bbusChannel": 6 + "bbusProducerChannels": 6, + "bbusConsumerChannels": 6 } diff --git a/arch/src/main/scala/framework/balldomain/prototype/README.md b/arch/src/main/scala/framework/balldomain/prototype/README.md index 49acdb87..8e4f4579 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/README.md +++ b/arch/src/main/scala/framework/balldomain/prototype/README.md @@ -171,18 +171,18 @@ Support rich configuration parameters: ## Integration Method -### Blink Protocol Interface -All Ball accelerators implement the Blink protocol interface: +### blink Protocol Interface +All Ball accelerators implement the blink protocol interface: ```scala class CustomBall(implicit b: CustomBuckyballConfig, p: Parameters) extends Module with BallRegist { val io = IO(new BlinkIO) def ballId = .U - def Blink = // Implement Blink protocol + def blink = // Implement blink protocol } ``` -**Blink Interface Components**: +**blink Interface Components**: - **cmdReq**: Command request interface with rob_id tracking - **cmdResp**: Command response interface for completion signaling - **status**: Status signals (ready, valid, idle, complete) @@ -243,7 +243,7 @@ Each accelerator comes with corresponding test cases: **Steps**: 1. Implement Ball device with BallRegist trait -2. Define Blink protocol interfaces +2. Define blink protocol interfaces 3. Implement computation logic 4. Add SRAM access logic (respect bank constraints) 5. Register in BBus and Ball RS @@ -255,7 +255,7 @@ class NewBall(implicit b: CustomBuckyballConfig, p: Parameters) val io = IO(new BlinkIO) def ballId = .U - def Blink = io + def blink = io // State machine val sIdle :: sCompute :: sComplete :: Nil = Enum(3) @@ -314,7 +314,7 @@ class NewBall(implicit b: CustomBuckyballConfig, p: Parameters) - [ReLU Activation](relu/README.md) - ReLU implementation - [Transpose Operations](transpose/README.md) - Matrix transpose - [Vector Processing](vector/README.md) - Vector unit architecture -- [Blink Protocol](../framework/blink/README.md) - Ball protocol specification +- [blink Protocol](../framework/blink/README.md) - Ball protocol specification ## Future Enhancements diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 7a73764c..55df3dec 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -6,9 +6,8 @@ import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public} import framework.balldomain.prototype.vector._ -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.blink.{BankRead, BankWrite, Status} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.top.GlobalConfig import framework.balldomain.prototype.relu.configs.ReluBallParam @@ -31,7 +30,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { val cmdResp = Decoupled(new BallRsComplete(b)) val bankRead = Vec(inBW, Flipped(new BankRead(b))) val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) - val status = new Status + val status = new BallStatus }) val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) @@ -76,10 +75,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } for (i <- 0 until outBW) { - io.bankWrite(i).io.req.valid := false.B - io.bankWrite(i).io.req.bits.addr := 0.U - io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B // direct write mode } for (i <- 0 until inBW) { @@ -175,13 +175,8 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } } - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := (state === idle) - io.status.init := (state === sRead) && (respCounter < InputNum.U) - io.status.running := (state === sWrite) || ((state === sRead) && (respCounter === InputNum.U)) - io.status.complete := (state === complete) && io.cmdResp.fire - io.status.iter := iterCnt + io.status.idle := (state === idle) + io.status.running := (state === sRead) || (state === sWrite) when(reset.asBool) { for (i <- 0 until InputNum) { diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala index 7cd63bcb..d74f9108 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala @@ -3,26 +3,27 @@ package framework.balldomain.prototype.relu import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallRegist, BlinkIO} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} import framework.balldomain.prototype.relu.PipelinedRelu import framework.top.GlobalConfig /** - * ReluBall - A ReLU computation Ball that complies with the Blink protocol. + * ReluBall - A ReLU computation Ball that complies with the blink protocol. * Behavior: Read data from Scratchpad, perform element-wise ReLU (set negative values to 0), * then write back to Scratchpad. */ @instantiable -class ReluBall(val b: GlobalConfig) extends Module with BallRegist { - val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "ReluBall") +class ReluBall(val b: GlobalConfig) extends Module with HasBlink { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "ReluBall") .getOrElse(throw new IllegalArgumentException("ReluBall not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW @public val io = IO(new BlinkIO(b, inBW, outBW)) - def Blink: BlinkIO = io + def blink: BlinkIO = io val reluUnit: Instance[PipelinedRelu] = Instantiate(new PipelinedRelu(b)) @@ -35,7 +36,6 @@ class ReluBall(val b: GlobalConfig) extends Module with BallRegist { for (i <- 0 until outBW) { reluUnit.io.bankWrite(i) <> io.bankWrite(i) - io.bankWrite(i).io.req.bits.wmode := false.B } io.status <> reluUnit.io.status diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala index f1ae02d7..0b9e0bd6 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallRegist, BlinkIO} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} import framework.balldomain.prototype.vector.VecUnit import framework.top.GlobalConfig @@ -11,16 +11,18 @@ import framework.top.GlobalConfig * VecBall */ @instantiable -class VecBall(val b: GlobalConfig) extends Module with BallRegist { - val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") +class VecBall(val b: GlobalConfig) extends Module with HasBlink with HasBallStatus { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW @public val io = IO(new BlinkIO(b, inBW, outBW)) - def Blink: BlinkIO = io + def blink: BlinkIO = io + def status: BallStatus = io.status val vecUnit: Instance[VecUnit] = Instantiate(new VecUnit(b)) @@ -33,7 +35,6 @@ class VecBall(val b: GlobalConfig) extends Module with BallRegist { for (i <- 0 until outBW) { vecUnit.io.bankWrite(i) <> io.bankWrite(i) - io.bankWrite(i).io.req.bits.wmode := true.B } io.status <> vecUnit.io.status diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index efcaa096..9fee5f52 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -8,7 +8,7 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.balldomain.prototype.vector._ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.top.GlobalConfig -import framework.balldomain.blink.{BankRead, BankWrite, Status} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.balldomain.prototype.vector.configs.VectorBallParam @instantiable @@ -31,7 +31,7 @@ class VecUnit(val b: GlobalConfig) extends Module { val cmdResp = Decoupled(new BallRsComplete(b)) val bankRead = Vec(inBW, Flipped(new BankRead(b))) val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) - val status = new Status + val status = new BallStatus }) // Register to store rob_id when command is received @@ -88,13 +88,9 @@ class VecUnit(val b: GlobalConfig) extends Module { VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o for (i <- 0 until outBW) { - // VecUnit receives write requests from VecBall, forwards to VecStoreUnit - // io.bankWrite is Flipped(new BankWrite(b)) so io is output from VecUnit - // VecStoreUnit.io.bankWrite is Flipped(SramWriteIO) so it's input to VecStoreUnit - // Connect: VecUnit outputs to VecStoreUnit inputs io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) - // Set bank_id from VecStoreUnit - io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o + io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o + io.bankWrite(i).io.req.bits.wmode := true.B } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o @@ -117,11 +113,6 @@ class VecUnit(val b: GlobalConfig) extends Module { hasOutput := true.B } - io.status.ready := io.cmdReq.ready - io.status.valid := io.cmdResp.valid - io.status.idle := !hasInput && !hasOutput - io.status.init := hasInput && !hasOutput - io.status.running := hasOutput - io.status.complete := io.cmdResp.fire - io.status.iter := iterCnt + io.status.idle := !hasInput && !hasOutput + io.status.running := hasOutput } diff --git a/arch/src/main/scala/framework/builtin/router/Router.scala b/arch/src/main/scala/framework/builtin/router/Router.scala deleted file mode 100644 index 921a63ba..00000000 --- a/arch/src/main/scala/framework/builtin/router/Router.scala +++ /dev/null @@ -1,32 +0,0 @@ -package framework.builtin.router - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} - -/** - * Router: - * - * Input: valid signals for each input channel - * Output: source input channel ID for each output channel - */ -@instantiable -class Router(val numInputs: Int, val numOutputs: Int) extends Module { - val inputChannelIdWidth = log2Ceil(numInputs) - val outputChannelIdWidth = log2Ceil(numOutputs) - - @public - val io = IO(new Bundle { - val in = Input(Vec(numInputs, Bool())) - val out = Vec(numOutputs, Decoupled(UInt(inputChannelIdWidth.W))) - }) - - for (outIdx <- 0 until numOutputs) { - val numValidInputs = PopCount(io.in) - val selectedIdx = PriorityEncoder(io.in) - val hasValidInput = numValidInputs > 0.U - - io.out(outIdx).valid := hasValidInput && io.out(outIdx).ready - io.out(outIdx).bits := selectedIdx.asUInt.asTypeOf(io.out(outIdx).bits.cloneType) - } -} diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 2be89a57..f46b1d5c 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -34,10 +34,10 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Bank interface for interaction with Ball Domain // BankRead/BankWrite are used with Flipped at Ball Device side // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) - // Use bbusChannel instead of bankNum to match BallDomain output + // Use bbusProducerChannels and bbusConsumerChannels instead of bankNum to match BallDomain output val ballDomain = new Bundle { - val bankRead = Vec(b.ballDomain.bbusChannel, new BankRead(b)) - val bankWrite = Vec(b.ballDomain.bbusChannel, new BankWrite(b)) + val bankRead = Vec(b.ballDomain.bbusConsumerChannels, new BankRead(b)) + val bankWrite = Vec(b.ballDomain.bbusProducerChannels, new BankWrite(b)) } diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala index 64c6c337..65b2177d 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala @@ -12,24 +12,20 @@ import framework.top.GlobalConfig */ @instantiable class SramBank(val b: GlobalConfig) extends Module { - // Use bankMaskLen from config instead of calculating val mask_len = b.memDomain.bankMaskLen val mask_elem = UInt((b.memDomain.bankWidth / mask_len).W) @public val io = IO(new Bundle { - // Bank interface (connected to MemManager) val sramRead = new SramReadIO(b) val sramWrite = new SramWriteIO(b) }) - // SRAM memory val mem = SyncReadMem(b.memDomain.bankEntries, Vec(mask_len, mask_elem)) // ----------------------------------------------------------------------------- // Read path // ----------------------------------------------------------------------------- - // Bank read (single port - can't read and write simultaneously) io.sramRead.req.ready := !io.sramWrite.req.valid val raddr = io.sramRead.req.bits.addr @@ -52,7 +48,6 @@ class SramBank(val b: GlobalConfig) extends Module { ) } - // Write response - single cycle write io.sramWrite.resp.valid := RegNext(io.sramWrite.req.fire) io.sramWrite.resp.bits.ok := RegNext(io.sramWrite.req.fire) } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 15c5afdb..cc4142b0 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -22,8 +22,8 @@ class MemMidend(val b: GlobalConfig) extends Module { // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { - val bankRead = Vec(b.ballDomain.bbusChannel, new BankRead(b)) - val bankWrite = Vec(b.ballDomain.bbusChannel, new BankWrite(b)) + val bankRead = Vec(b.ballDomain.bbusConsumerChannels, new BankRead(b)) + val bankWrite = Vec(b.ballDomain.bbusProducerChannels, new BankWrite(b)) } // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here @@ -37,7 +37,7 @@ class MemMidend(val b: GlobalConfig) extends Module { // Each input channel is mapped to a backend channel based on modulo for (ch <- 0 until b.memDomain.bankChannel) { - val inputIdx = ch % b.ballDomain.bbusChannel + val inputIdx = ch % b.ballDomain.bbusConsumerChannels // Map input channels to backend channels io.mem_req(ch).write <> io.frontend.bankWrite(inputIdx).io diff --git a/arch/src/main/scala/framework/top/channels/Channel.scala b/arch/src/main/scala/framework/top/channels/Channel.scala new file mode 100644 index 00000000..1102966a --- /dev/null +++ b/arch/src/main/scala/framework/top/channels/Channel.scala @@ -0,0 +1,31 @@ +package framework.top.channels + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.top.channels.{HeaderBuffer, HeaderBufferData} + +class ChannelIO(val b: GlobalConfig) extends Bundle { + val producer = Flipped(Decoupled(UInt(b.memDomain.bankWidth.W))) + val consumer = Decoupled(UInt(b.memDomain.bankWidth.W)) + + val header = new Bundle { + val read = Output(new HeaderBufferData(b)) + val set = Flipped(Decoupled(new HeaderBufferData(b))) + } + +} + +@instantiable +class Channel(val b: GlobalConfig) extends Module { + @public + val io = IO(new ChannelIO(b)) + + val headerBuffer: Instance[HeaderBuffer] = Instantiate(new HeaderBuffer(b)) + + io.header.read := headerBuffer.io.read + headerBuffer.io.set <> io.header.set + + io.consumer <> io.producer +} diff --git a/arch/src/main/scala/framework/top/channels/headerBuffer.scala b/arch/src/main/scala/framework/top/channels/headerBuffer.scala new file mode 100644 index 00000000..ee06c505 --- /dev/null +++ b/arch/src/main/scala/framework/top/channels/headerBuffer.scala @@ -0,0 +1,30 @@ +package framework.top.channels + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +class HeaderBufferData(val b: GlobalConfig) extends Bundle { + val lock = Bool() + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) +} + +@instantiable +class HeaderBuffer(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val read = Output(new HeaderBufferData(b)) + val set = Flipped(Decoupled(new HeaderBufferData(b))) + }) + + val reg = Reg(new HeaderBufferData(b)) + + io.read := reg + io.set.ready := !reg.lock + when(io.set.fire) { + reg := io.set.bits + } +} diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index 21b4b0da..44f87b09 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -3,7 +3,7 @@ package sims.verify import chisel3._ import _root_.circt.stage.ChiselStage import framework.top.GlobalConfig -import framework.balldomain.blink.{BallRegist, BlinkIO} +import framework.balldomain.blink.{BlinkIO, HasBlink} import framework.balldomain.prototype.vector.VecBall import framework.balldomain.prototype.relu.ReluBall // import framework.balldomain.prototype.matrix.MatrixBall @@ -19,36 +19,34 @@ case object Im2colBallType extends BallType case object ReluBallType extends BallType case object NNLutBallType extends BallType -class TargetBall(ballType: BallType, b: GlobalConfig) extends Module { +class TargetBall(ballType: BallType, b: GlobalConfig) extends Module with HasBlink { - // Determine bandwidth from config first - val (inBW, outBW) = ballType match { - case VecBallType => - val mapping = b.ballDomain.ballIdMappings.find(_.ballName == "VecBall") - .getOrElse(throw new IllegalArgumentException("VecBall not found in config")) - (mapping.inBW, mapping.outBW) - case ReluBallType => - val mapping = b.ballDomain.ballIdMappings.find(_.ballName == "ReluBall") - .getOrElse(throw new IllegalArgumentException("ReluBall not found in config")) - (mapping.inBW, mapping.outBW) - case _ => (2, 4) // Default bandwidth - } - - val io = IO(new BlinkIO(b, inBW, outBW)) - - ballType match { - case VecBallType => - val ball = Module(new VecBall(b)) - io <> ball.io - case ReluBallType => - val ball = Module(new ReluBall(b)) - io <> ball.io + val ballName = ballType match { + case VecBallType => "VecBall" + case ReluBallType => "ReluBall" case MatrixBallType => throw new IllegalArgumentException("MatrixBall not implemented") case Im2colBallType => throw new IllegalArgumentException("Im2colBall not implemented") case TransposeBallType => throw new IllegalArgumentException("TransposeBall not implemented") case NNLutBallType => throw new IllegalArgumentException("NNLutBall not implemented") case _ => throw new scala.MatchError("TargetBall does not handle this ball type") } + + val mapping = b.ballDomain.ballIdMappings.find(_.ballName == ballName) + .getOrElse(throw new IllegalArgumentException(s"$ballName not found in config")) + val inBW = mapping.inBW + val outBW = mapping.outBW + + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + + val ball = ballType match { + case VecBallType => Module(new VecBall(b)) + case ReluBallType => Module(new ReluBall(b)) + case _ => throw new scala.MatchError("TargetBall does not handle this ball type") + } + + io <> ball.blink } object BallTopMain extends App { From 02354b2de05f1ba2ab026d7fa054a2c6945f3685 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 17:42:51 +0800 Subject: [PATCH 026/238] [arch] slightly update --- .../balldomain/bbus/memrouter/Router.scala | 24 ------------- .../bbus/memrouter/ballReqCtrl.scala | 13 +++++-- .../bbus/memrouter/ballRespCtrl.scala | 13 +++++++ .../balldomain/bbus/memrouter/memRouter.scala | 17 ++++++---- .../framework/balldomain/blink/bank.scala | 33 ++++++++++++++++++ .../framework/balldomain/blink/blink.scala | 34 ------------------- .../framework/balldomain/blink/status.scala | 9 +++++ 7 files changed, 76 insertions(+), 67 deletions(-) delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala create mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala create mode 100644 arch/src/main/scala/framework/balldomain/blink/bank.scala create mode 100644 arch/src/main/scala/framework/balldomain/blink/status.scala diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala deleted file mode 100644 index e2298922..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/Router.scala +++ /dev/null @@ -1,24 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} - -/** - * Router: - * - * Input: valid signals for each input channel and channel num requests - * Output: source input channel ID for each output channel - */ -@instantiable -class Router(val numInputs: Int, val numOutputs: Int, val maxPerChannelWidth: Int) extends Module { - val inputChannelIdWidth = log2Ceil(numInputs) - val outputChannelIdWidth = log2Ceil(numOutputs) - - @public - val io = IO(new Bundle { - val in = Flipped(Valid(Vec(numInputs, UInt(maxPerChannelWidth.W)))) - val out = Vec(numOutputs, Decoupled(UInt(inputChannelIdWidth.W))) - }) - -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala index 50b12476..44746161 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala @@ -4,10 +4,19 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig -import framework.balldomain.blink.BankRead +import framework.balldomain.blink.{MultiBankRead, MultiBankWrite} @instantiable class BallReqCtrl(val b: GlobalConfig) extends Module { + val numBalls = b.ballDomain.ballNum + @public - val io = IO(new Bundle {}) + val io = IO(new Bundle { + val readReq_i = Vec(numBalls, Flipped(new MultiBankRead(b, numBalls))) + val writeReq_i = Vec(numBalls, Flipped(new MultiBankWrite(b, numBalls))) + + val readReq_o = Vec(numBalls, new MultiBankRead(b, numBalls)) + val writeReq_o = Vec(numBalls, new MultiBankWrite(b, numBalls)) + }) + } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala new file mode 100644 index 00000000..c3778455 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala @@ -0,0 +1,13 @@ +package framework.balldomain.bbus.memrouter + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.balldomain.blink.BankRead + +@instantiable +class BallRespCtrl(val b: GlobalConfig) extends Module { + @public + val io = IO(new Bundle {}) +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index d00436df..59310b57 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -5,28 +5,31 @@ import chisel3.util._ import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig -import framework.balldomain.bbus.memrouter.Router @instantiable class MemRouter(val b: GlobalConfig) extends Module { // balls - (readChannels/writeChannels) - bbus - (bbusChannel) - memdomain + val numBalls = b.ballDomain.ballNum val bbusProducerChannels = b.ballDomain.bbusProducerChannels val bbusConsumerChannels = b.ballDomain.bbusConsumerChannels - val numBalls = b.ballDomain.ballNum val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum val maxPerChannelWidth = b.ballDomain.ballIdMappings.flatMap(m => Seq(m.inBW, m.outBW)).max @public val io = IO(new Bundle { - val bankRead_i = Vec(totalReadChannels, new BankRead(b)) + val bankRead_i = Vec(totalReadChannels, new BankRead(b)) + val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) + val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) - val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) }) - val readRouter: Instance[Router] = Instantiate(new Router(totalReadChannels, bbusProducerChannels, maxPerChannelWidth)) - val writeRouter: Instance[Router] = - Instantiate(new Router(totalWriteChannels, bbusProducerChannels, maxPerChannelWidth)) + val ballReqCtrl: Instance[BallReqCtrl] = Instantiate(new BallReqCtrl(b)) + +// ------------------------------------------------------------ +// BallReqCtrl +// ------------------------------------------------------------ + // 提取BallReqCtrl要的信息 } diff --git a/arch/src/main/scala/framework/balldomain/blink/bank.scala b/arch/src/main/scala/framework/balldomain/blink/bank.scala new file mode 100644 index 00000000..610011b9 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/blink/bank.scala @@ -0,0 +1,33 @@ +package framework.balldomain.blink + +import chisel3._ +import chisel3.util._ +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.memdomain.backend.banks.{SramReadReq, SramWriteReq} +import framework.top.GlobalConfig + +trait HasBankId { + val b: GlobalConfig + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) +} + +trait HasRobId { + val b: GlobalConfig + val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) +} + +class BankRead(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId { + val io = new SramReadIO(b) +} + +class BankWrite(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId { + val io = new SramWriteIO(b) +} + +class MultiBankRead(val b: GlobalConfig, BW: Int) extends Bundle with HasBankId with HasRobId { + val io = Vec(BW, new SramReadIO(b)) +} + +class MultiBankWrite(val b: GlobalConfig, BW: Int) extends Bundle with HasBankId with HasRobId { + val io = Vec(BW, new SramWriteIO(b)) +} diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index a0241718..9edff14c 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -4,31 +4,9 @@ import chisel3._ import chisel3.util._ import framework.top.GlobalConfig import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import chisel3.experimental.hierarchy.{instantiable, public} -class BallStatus extends Bundle { - val idle = Output(Bool()) - val running = Output(Bool()) -} - -// SRAMRead with rob_id, bank_id -class BankRead(val b: GlobalConfig) extends Bundle { - val io = new SramReadIO(b) - val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) -} - -// SRAMWrite with rob_id, bank_id -// wmode is in SramWriteIO.io.req.bits.wmode: true = accumulate, false = overwrite -class BankWrite(val b: GlobalConfig) extends Bundle { - val io = new SramWriteIO(b) - val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) -} - class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle with HasBallStatus { - def status: BallStatus = new BallStatus() val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) @@ -36,15 +14,3 @@ class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle with HasBal val bankRead = Vec(inBW, Flipped(new BankRead(b))) val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) } - -// @instantiable -// class blink(b: GlobalConfig, inBW: Int, outBW: Int) extends Module { -// @public -// val io = IO(new BlinkIO(b, inBW, outBW)) - -// def cmdReq: DecoupledIO[BallRsIssue] = io.cmdReq -// def cmdResp: DecoupledIO[BallRsComplete] = io.cmdResp -// def bankRead: Vec[BankRead] = io.bankRead -// def bankWrite: Vec[BankWrite] = io.bankWrite -// def status: BallStatus = io.status -// } diff --git a/arch/src/main/scala/framework/balldomain/blink/status.scala b/arch/src/main/scala/framework/balldomain/blink/status.scala new file mode 100644 index 00000000..843444a3 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/blink/status.scala @@ -0,0 +1,9 @@ +package framework.balldomain.blink + +import chisel3._ +import chisel3.util._ + +class BallStatus extends Bundle { + val idle = Output(Bool()) + val running = Output(Bool()) +} From 16a79daf6afd8c90bc6c89e0580410609dd592d0 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Sun, 4 Jan 2026 19:04:59 +0800 Subject: [PATCH 027/238] Fix some bugs --- .../scala/framework/balldomain/blink/blink.scala | 2 +- arch/src/main/scala/palladium/fpga/package.scala | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 arch/src/main/scala/palladium/fpga/package.scala diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index 9edff14c..3f63fcb8 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -7,7 +7,7 @@ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle with HasBallStatus { - def status: BallStatus = new BallStatus() + val status = new BallStatus() val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) val cmdResp = Decoupled(new BallRsComplete(b)) diff --git a/arch/src/main/scala/palladium/fpga/package.scala b/arch/src/main/scala/palladium/fpga/package.scala new file mode 100644 index 00000000..9b36bdd5 --- /dev/null +++ b/arch/src/main/scala/palladium/fpga/package.scala @@ -0,0 +1,16 @@ +package object palladium { + object fpga { + import org.chipsalliance.cde.config.{Config, Field} + + case object FPGAFrequencyKey extends Field[Double](100.0) // Default to 100MHz + case object VCU19PTweaksKey extends Field[Boolean](true) + + class WithFPGAFrequency(freqMHz: Double) extends Config((site, here, up) => { + case FPGAFrequencyKey => freqMHz + }) + + class WithVCU19PTweaks extends Config((site, here, up) => { + case VCU19PTweaksKey => true + }) + } +} \ No newline at end of file From 83965cbd011030b5739a7eb51b6a7ce652d6d821 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 19:27:33 +0800 Subject: [PATCH 028/238] [arch] feat: add channel peak --- .../scala/examples/toy/ToyBuckyBall.scala | 15 ++-- .../examples/toy/balldomain/BallDomain.scala | 5 ++ .../framework/balldomain/bbus/bbus.scala | 18 ++--- .../bbus/memrouter/ReadReqGen.scala | 72 +++++++++++++++++++ .../bbus/memrouter/ballReqCtrl.scala | 22 ------ .../bbus/memrouter/ballRespCtrl.scala | 13 ---- .../balldomain/bbus/memrouter/memRouter.scala | 27 +++++-- .../framework/balldomain/blink/bank.scala | 17 ++--- .../top/channels/BallMemChannel.scala | 32 +++++++++ .../main/scala/palladium/fpga/package.scala | 21 +++--- 10 files changed, 169 insertions(+), 73 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala create mode 100644 arch/src/main/scala/framework/top/channels/BallMemChannel.scala diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 1b3caf94..e38ac96b 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -18,6 +18,7 @@ import examples.toy.balldomain.BallDomain import framework.frontend.Frontend import framework.gpdomain.GpDomain import framework.memdomain.MemDomain +import framework.top.channels.{BallMemChannel, Channel, ChannelIO} class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) extends LazyRoCC(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { @@ -44,8 +45,7 @@ class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) override lazy val module = new ToyBuckyballModule(this) - // tlNode connects to mbus (bypassing L1 cache) - // This is where DMA traffic goes + // tlNode connects to mbus (bypassing L2 cache) override val tlNode = TLWidthWidget(b.memDomain.dma_buswidth / 8) := TLBuffer() := xbar_node // atlNode is not used (set to identity for compatibility) @@ -60,10 +60,11 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w val (tl_reader, edge_reader) = outer.reader_node.out(0) val (tl_writer, edge_writer) = outer.writer_node.out(0) - val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) - val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) - val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) - val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) + val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) + val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) + val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) + val ballMemChannel: Instance[BallMemChannel] = Instantiate(new BallMemChannel(b)) frontend.io.cmd.valid := io.cmd.valid frontend.io.cmd.bits.cmd := io.cmd.bits @@ -103,6 +104,8 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w ballDomain.bankRead <> memDomain.io.ballDomain.bankRead ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite + ballMemChannel.io <> ballDomain.ballMemChannel + // Connect TileLink DMA ports from MemDomain to LazyModule nodes tl_reader <> memDomain.io.tl_reader tl_writer <> memDomain.io.tl_writer diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 065b8b16..f66bb7c8 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -10,6 +10,7 @@ import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} import framework.balldomain.rs.BallReservationStation +import framework.top.channels.{BallMemChannelIO, ChannelIO} @instantiable class BallDomain(val b: GlobalConfig) extends Module { @@ -27,6 +28,9 @@ class BallDomain(val b: GlobalConfig) extends Module { @public val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) + @public + val ballMemChannel = IO(new BallMemChannelIO(b)) + val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) val ballRs: Instance[BallReservationStation] = Instantiate(new BallReservationStation(b)) @@ -61,6 +65,7 @@ class BallDomain(val b: GlobalConfig) extends Module { //--------------------------------------------------------------------------- bbus.bankRead <> bankRead bbus.bankWrite <> bankWrite + bbus.ballMemChannel <> ballMemChannel //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 62f97899..f49a0d28 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -10,7 +10,7 @@ import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter import framework.balldomain.blink.{BankRead, BankWrite} -import framework.top.channels.ChannelIO +import framework.top.channels.{BallMemChannelIO, ChannelIO} /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices @@ -25,19 +25,17 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) // Rs - bbus - balls @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) // balls - bbus @public - val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) // bbus - mem @public - val channelToMemDomain = IO(Vec(bbusProducerChannels, new ChannelIO(b))) - @public - val channelFromMemDomain = IO(Vec(bbusConsumerChannels, Flipped(new ChannelIO(b)))) + val ballMemChannel = IO(new BallMemChannelIO(b)) val balls = ballGenerators.map(gen => Module(gen())) val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) @@ -69,6 +67,10 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- + memoryrouter.io.bankRead_i <> bankRead + memoryrouter.io.bankWrite_i <> bankWrite + memoryrouter.io.peakChannelReq <> ballMemChannel.peakChannelReq + memoryrouter.io.freeChannelResp <> ballMemChannel.freeChannelResp // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala new file mode 100644 index 00000000..f2d04d08 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -0,0 +1,72 @@ +package framework.balldomain.bbus.memrouter + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.balldomain.blink.{BankRead} + +class ReadReq(val b: GlobalConfig) extends Bundle { + val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + val channel_num = UInt(log2Up(totalReadChannels).W) +} + +@instantiable +class ReadReqGen(val b: GlobalConfig) extends Module { + val ballIdMappings = b.ballDomain.ballIdMappings + val numBalls = b.ballDomain.ballNum + val totalReadChannels = ballIdMappings.map(_.inBW).sum + val numBanks = b.memDomain.bankNum + + @public + val io = IO(new Bundle { + val bank_read_i = Vec(totalReadChannels, Flipped(new BankRead(b))) + val read_req_o = Decoupled(new ReadReq(b)) + }) + + val reqGroups = (0 until numBalls).flatMap { ballId => + (0 until numBanks).map { bankId => + val ballOffset = ballIdMappings.take(ballId).map(_.inBW).sum + val ballInBW = ballIdMappings(ballId).inBW + val matchingChannels = (ballOffset until ballOffset + ballInBW).toSeq + + val hasReq = matchingChannels.map(ch => + io.bank_read_i(ch).io.req.valid && + io.bank_read_i(ch).ball_id === ballId.U && + io.bank_read_i(ch).bank_id === bankId.U + ).reduceOption(_ || _).getOrElse(false.B) + + val channelCount = PopCount(matchingChannels.map(ch => + io.bank_read_i(ch).io.req.valid && + io.bank_read_i(ch).ball_id === ballId.U && + io.bank_read_i(ch).bank_id === bankId.U + )) + + (hasReq, channelCount, bankId.U, ballId.U) + } + } + + val arb = Module(new Arbiter( + new Bundle { + val channel_num = UInt(log2Up(totalReadChannels + 1).W) + val bank_id = UInt(log2Up(numBanks).W) + val ball_id = UInt(log2Up(numBalls).W) + }, + reqGroups.length + )) + + for (i <- reqGroups.indices) { + arb.io.in(i).valid := reqGroups(i)._1 + arb.io.in(i).bits.channel_num := reqGroups(i)._2 + arb.io.in(i).bits.bank_id := reqGroups(i)._3 + arb.io.in(i).bits.ball_id := reqGroups(i)._4 + } + + io.read_req_o.valid := arb.io.out.valid + io.read_req_o.bits.bank_id := arb.io.out.bits.bank_id + io.read_req_o.bits.ball_id := arb.io.out.bits.ball_id + io.read_req_o.bits.channel_num := arb.io.out.bits.channel_num + arb.io.out.ready := io.read_req_o.ready +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala deleted file mode 100644 index 44746161..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballReqCtrl.scala +++ /dev/null @@ -1,22 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig -import framework.balldomain.blink.{MultiBankRead, MultiBankWrite} - -@instantiable -class BallReqCtrl(val b: GlobalConfig) extends Module { - val numBalls = b.ballDomain.ballNum - - @public - val io = IO(new Bundle { - val readReq_i = Vec(numBalls, Flipped(new MultiBankRead(b, numBalls))) - val writeReq_i = Vec(numBalls, Flipped(new MultiBankWrite(b, numBalls))) - - val readReq_o = Vec(numBalls, new MultiBankRead(b, numBalls)) - val writeReq_o = Vec(numBalls, new MultiBankWrite(b, numBalls)) - }) - -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala deleted file mode 100644 index c3778455..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ballRespCtrl.scala +++ /dev/null @@ -1,13 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig -import framework.balldomain.blink.BankRead - -@instantiable -class BallRespCtrl(val b: GlobalConfig) extends Module { - @public - val io = IO(new Bundle {}) -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 59310b57..9cdc477f 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -6,9 +6,16 @@ import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig +class PeakChannelReq(val b: GlobalConfig) extends Bundle { + val needed_channel_num = UInt(log2Up(b.ballDomain.ballIdMappings.map(_.inBW).sum + 1).W) +} + +class FreeChannelResp(val b: GlobalConfig) extends Bundle { + val is_free = Bool() +} + @instantiable class MemRouter(val b: GlobalConfig) extends Module { - // balls - (readChannels/writeChannels) - bbus - (bbusChannel) - memdomain val numBalls = b.ballDomain.ballNum val bbusProducerChannels = b.ballDomain.bbusProducerChannels val bbusConsumerChannels = b.ballDomain.bbusConsumerChannels @@ -23,13 +30,21 @@ class MemRouter(val b: GlobalConfig) extends Module { val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) + + val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) + val freeChannelResp = Decoupled(new FreeChannelResp(b)) }) - val ballReqCtrl: Instance[BallReqCtrl] = Instantiate(new BallReqCtrl(b)) + val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) + readReqGen.io.bank_read_i <> io.bankRead_i + + val hasReadReq = readReqGen.io.read_req_o.valid + val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free + val reqAccepted = isChannelFree -// ------------------------------------------------------------ -// BallReqCtrl -// ------------------------------------------------------------ - // 提取BallReqCtrl要的信息 + io.peakChannelReq.valid := hasReadReq + io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num + io.freeChannelResp.ready := hasReadReq + readReqGen.io.read_req_o.ready := reqAccepted } diff --git a/arch/src/main/scala/framework/balldomain/blink/bank.scala b/arch/src/main/scala/framework/balldomain/blink/bank.scala index 610011b9..701a3adc 100644 --- a/arch/src/main/scala/framework/balldomain/blink/bank.scala +++ b/arch/src/main/scala/framework/balldomain/blink/bank.scala @@ -16,18 +16,15 @@ trait HasRobId { val rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) } -class BankRead(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId { - val io = new SramReadIO(b) -} - -class BankWrite(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId { - val io = new SramWriteIO(b) +trait HasBallId { + val b: GlobalConfig + val ball_id = Input(UInt(log2Up(b.ballDomain.ballNum).W)) } -class MultiBankRead(val b: GlobalConfig, BW: Int) extends Bundle with HasBankId with HasRobId { - val io = Vec(BW, new SramReadIO(b)) +class BankRead(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId { + val io = new SramReadIO(b) } -class MultiBankWrite(val b: GlobalConfig, BW: Int) extends Bundle with HasBankId with HasRobId { - val io = Vec(BW, new SramWriteIO(b)) +class BankWrite(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId { + val io = new SramWriteIO(b) } diff --git a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala new file mode 100644 index 00000000..65d778bf --- /dev/null +++ b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala @@ -0,0 +1,32 @@ +package framework.top.channels + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} + +class BallMemChannelIO(val b: GlobalConfig) extends Bundle { + val channelToMemDomain = Vec(b.ballDomain.bbusProducerChannels, new ChannelIO(b)) + val channelFromMemDomain = Vec(b.ballDomain.bbusConsumerChannels, Flipped(new ChannelIO(b))) + + val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) + val freeChannelResp = Decoupled(new FreeChannelResp(b)) +} + +@instantiable +class BallMemChannel(val b: GlobalConfig) extends Module { + @public + val io = IO(new BallMemChannelIO(b)) + + val channelsToMem = (0 until b.ballDomain.bbusProducerChannels).map(_ => Instantiate(new Channel(b))) + val channelsFromMem = (0 until b.ballDomain.bbusConsumerChannels).map(_ => Instantiate(new Channel(b))) + + VecInit(channelsToMem.map(_.io)) <> io.channelToMemDomain + VecInit(channelsFromMem.map(_.io)) <> io.channelFromMemDomain + + val freeChannelCount = PopCount(io.channelToMemDomain.map(!_.header.read.lock)) + io.freeChannelResp.valid := io.peakChannelReq.valid + io.freeChannelResp.bits.is_free := freeChannelCount >= io.peakChannelReq.bits.needed_channel_num + io.peakChannelReq.ready := io.freeChannelResp.ready +} diff --git a/arch/src/main/scala/palladium/fpga/package.scala b/arch/src/main/scala/palladium/fpga/package.scala index 9b36bdd5..2ea3ec29 100644 --- a/arch/src/main/scala/palladium/fpga/package.scala +++ b/arch/src/main/scala/palladium/fpga/package.scala @@ -1,16 +1,21 @@ package object palladium { + object fpga { import org.chipsalliance.cde.config.{Config, Field} case object FPGAFrequencyKey extends Field[Double](100.0) // Default to 100MHz - case object VCU19PTweaksKey extends Field[Boolean](true) + case object VCU19PTweaksKey extends Field[Boolean](true) + + class WithFPGAFrequency(freqMHz: Double) + extends Config((site, here, up) => { + case FPGAFrequencyKey => freqMHz + }) - class WithFPGAFrequency(freqMHz: Double) extends Config((site, here, up) => { - case FPGAFrequencyKey => freqMHz - }) + class WithVCU19PTweaks + extends Config((site, here, up) => { + case VCU19PTweaksKey => true + }) - class WithVCU19PTweaks extends Config((site, here, up) => { - case VCU19PTweaksKey => true - }) } -} \ No newline at end of file + +} From d29ea17173d58793b88f1e449e3a23c4acae9174 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 19:34:19 +0800 Subject: [PATCH 029/238] [arch] refactor: update BallDomain and related modules to use top-level memory channel configurations --- .../examples/toy/balldomain/BallDomain.scala | 2 +- .../scala/framework/balldomain/bbus/bbus.scala | 4 ++-- .../balldomain/bbus/memrouter/memRouter.scala | 4 ++-- .../balldomain/configs/BallDomainParam.scala | 6 ++---- .../scala/framework/memdomain/MemDomain.scala | 4 ++-- .../memdomain/configs/MemDomainParam.scala | 1 - .../framework/memdomain/midend/MemMidend.scala | 6 +++--- .../main/scala/framework/top/GlobalConfig.scala | 7 +++++-- .../framework/top/channels/BallMemChannel.scala | 8 ++++---- .../scala/framework/top/configs/TopConfig.scala | 17 +++++++++++++++++ .../scala/framework/top/configs/default.json | 4 ++++ 11 files changed, 42 insertions(+), 21 deletions(-) create mode 100644 arch/src/main/scala/framework/top/configs/TopConfig.scala create mode 100644 arch/src/main/scala/framework/top/configs/default.json diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index f66bb7c8..ff6468a6 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -14,7 +14,7 @@ import framework.top.channels.{BallMemChannelIO, ChannelIO} @instantiable class BallDomain(val b: GlobalConfig) extends Module { - val memChannel = b.memDomain.balldomainChannel + val memChannel = b.top.ballMemChannelProducer @public val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(b)))) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index f49a0d28..188a7c15 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -18,8 +18,8 @@ import framework.top.channels.{BallMemChannelIO, ChannelIO} @instantiable class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) extends Module { val numBalls = b.ballDomain.ballNum - val bbusProducerChannels = b.ballDomain.bbusProducerChannels - val bbusConsumerChannels = b.ballDomain.bbusConsumerChannels + val bbusProducerChannels = b.top.ballMemChannelProducer + val bbusConsumerChannels = b.top.ballMemChannelConsumer val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 9cdc477f..ad012e42 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -17,8 +17,8 @@ class FreeChannelResp(val b: GlobalConfig) extends Bundle { @instantiable class MemRouter(val b: GlobalConfig) extends Module { val numBalls = b.ballDomain.ballNum - val bbusProducerChannels = b.ballDomain.bbusProducerChannels - val bbusConsumerChannels = b.ballDomain.bbusConsumerChannels + val bbusProducerChannels = b.top.ballMemChannelProducer + val bbusConsumerChannels = b.top.ballMemChannelConsumer val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum val maxPerChannelWidth = b.ballDomain.ballIdMappings.flatMap(m => Seq(m.inBW, m.outBW)).max diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala index 34ffce08..92090ece 100644 --- a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -9,10 +9,8 @@ case class BallIdMapping( outBW: Int) case class BallDomainParam( - ballNum: Int, - ballIdMappings: Seq[BallIdMapping], - bbusProducerChannels: Int, - bbusConsumerChannels: Int) + ballNum: Int, + ballIdMappings: Seq[BallIdMapping]) object BallDomainParam { implicit val ballIdMappingRW: ReadWriter[BallIdMapping] = macroRW diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index f46b1d5c..11b9129c 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -36,8 +36,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) // Use bbusProducerChannels and bbusConsumerChannels instead of bankNum to match BallDomain output val ballDomain = new Bundle { - val bankRead = Vec(b.ballDomain.bbusConsumerChannels, new BankRead(b)) - val bankWrite = Vec(b.ballDomain.bbusProducerChannels, new BankWrite(b)) + val bankRead = Vec(b.top.ballMemChannelConsumer, new BankRead(b)) + val bankWrite = Vec(b.top.ballMemChannelProducer, new BankWrite(b)) } diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala index 5f5fde84..c2872f7a 100644 --- a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -17,7 +17,6 @@ case class MemDomainParam( max_in_flight_mem_reqs: Int, dma_buswidth: Int, memAddrLen: Int, - balldomainChannel: Int, tmaReadChannel: Int, tmaWriteChannel: Int) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index cc4142b0..6728373a 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -22,8 +22,8 @@ class MemMidend(val b: GlobalConfig) extends Module { // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { - val bankRead = Vec(b.ballDomain.bbusConsumerChannels, new BankRead(b)) - val bankWrite = Vec(b.ballDomain.bbusProducerChannels, new BankWrite(b)) + val bankRead = Vec(b.top.ballMemChannelConsumer, new BankRead(b)) + val bankWrite = Vec(b.top.ballMemChannelProducer, new BankWrite(b)) } // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here @@ -37,7 +37,7 @@ class MemMidend(val b: GlobalConfig) extends Module { // Each input channel is mapped to a backend channel based on modulo for (ch <- 0 until b.memDomain.bankChannel) { - val inputIdx = ch % b.ballDomain.bbusConsumerChannels + val inputIdx = ch % b.top.ballMemChannelConsumer // Map input channels to backend channels io.mem_req(ch).write <> io.frontend.bankWrite(inputIdx).io diff --git a/arch/src/main/scala/framework/top/GlobalConfig.scala b/arch/src/main/scala/framework/top/GlobalConfig.scala index c2076461..ca167cf1 100644 --- a/arch/src/main/scala/framework/top/GlobalConfig.scala +++ b/arch/src/main/scala/framework/top/GlobalConfig.scala @@ -9,6 +9,7 @@ import framework.balldomain.configs.BallDomainParam import framework.balldomain.prototype.vector.configs.VectorBallParam import framework.balldomain.prototype.relu.configs.ReluBallParam import framework.core.configs.CoreParam +import framework.top.configs.TopConfig case class GlobalConfig( memDomain: MemDomainParam, @@ -17,7 +18,8 @@ case class GlobalConfig( ballDomain: BallDomainParam, vectorBall: VectorBallParam, reluBall: ReluBallParam, - core: CoreParam) + core: CoreParam, + top: TopConfig) extends SerializableModuleParameter object GlobalConfig { @@ -31,7 +33,8 @@ object GlobalConfig { ballDomain = BallDomainParam(), vectorBall = VectorBallParam(), reluBall = ReluBallParam(), - core = CoreParam() + core = CoreParam(), + top = TopConfig() ) } diff --git a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala index 65d778bf..b6220fc0 100644 --- a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala +++ b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala @@ -7,8 +7,8 @@ import framework.top.GlobalConfig import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} class BallMemChannelIO(val b: GlobalConfig) extends Bundle { - val channelToMemDomain = Vec(b.ballDomain.bbusProducerChannels, new ChannelIO(b)) - val channelFromMemDomain = Vec(b.ballDomain.bbusConsumerChannels, Flipped(new ChannelIO(b))) + val channelToMemDomain = Vec(b.top.ballMemChannelProducer, new ChannelIO(b)) + val channelFromMemDomain = Vec(b.top.ballMemChannelConsumer, Flipped(new ChannelIO(b))) val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) val freeChannelResp = Decoupled(new FreeChannelResp(b)) @@ -19,8 +19,8 @@ class BallMemChannel(val b: GlobalConfig) extends Module { @public val io = IO(new BallMemChannelIO(b)) - val channelsToMem = (0 until b.ballDomain.bbusProducerChannels).map(_ => Instantiate(new Channel(b))) - val channelsFromMem = (0 until b.ballDomain.bbusConsumerChannels).map(_ => Instantiate(new Channel(b))) + val channelsToMem = (0 until b.top.ballMemChannelProducer).map(_ => Instantiate(new Channel(b))) + val channelsFromMem = (0 until b.top.ballMemChannelConsumer).map(_ => Instantiate(new Channel(b))) VecInit(channelsToMem.map(_.io)) <> io.channelToMemDomain VecInit(channelsFromMem.map(_.io)) <> io.channelFromMemDomain diff --git a/arch/src/main/scala/framework/top/configs/TopConfig.scala b/arch/src/main/scala/framework/top/configs/TopConfig.scala new file mode 100644 index 00000000..31272bec --- /dev/null +++ b/arch/src/main/scala/framework/top/configs/TopConfig.scala @@ -0,0 +1,17 @@ +package framework.top.configs + +import upickle.default._ + +case class TopConfig( + ballMemChannelProducer: Int, + ballMemChannelConsumer: Int) + +object TopConfig { + implicit val rw: ReadWriter[TopConfig] = macroRW + + def apply(): TopConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/top/configs/default.json").mkString + read[TopConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/top/configs/default.json b/arch/src/main/scala/framework/top/configs/default.json new file mode 100644 index 00000000..52af17a0 --- /dev/null +++ b/arch/src/main/scala/framework/top/configs/default.json @@ -0,0 +1,4 @@ +{ + "ballMemChannelProducer": 6, + "ballMemChannelConsumer": 6 +} From 1e2febcb7ba3217815d1ad03497b43c95f52be76 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 20:19:06 +0800 Subject: [PATCH 030/238] [arch] feat: introduce ChannelMappingTable --- .../bbus/memrouter/ChannelMapping.scala | 36 +++++++++++++ .../bbus/memrouter/ReadReqGen.scala | 22 +++++--- .../balldomain/bbus/memrouter/memRouter.scala | 54 +++++++++++++++---- .../framework/balldomain/configs/default.json | 4 +- .../top/channels/BallMemChannel.scala | 54 +++++++++++++++++-- .../framework/top/channels/Channel.scala | 14 +---- 6 files changed, 147 insertions(+), 37 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala new file mode 100644 index 00000000..28cbfc22 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala @@ -0,0 +1,36 @@ +package framework.balldomain.bbus.memrouter + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +@instantiable +class ChannelMappingTable(val b: GlobalConfig) extends Module { + val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum + val bbusProducerChannels = b.top.ballMemChannelProducer + + @public + val io = IO(new Bundle { + + val write = Flipped(Decoupled(new Bundle { + val idx = UInt(log2Up(totalReadChannels).W) + val outCh = UInt(log2Up(bbusProducerChannels).W) + })) + + val routeMap = Output(Vec(totalReadChannels, UInt(log2Up(bbusProducerChannels).W))) + val routeValid = Output(Vec(totalReadChannels, Bool())) + }) + + val routeMap = Reg(Vec(totalReadChannels, UInt(log2Up(bbusProducerChannels).W))) + val routeValid = RegInit(VecInit(Seq.fill(totalReadChannels)(false.B))) + + when(io.write.fire) { + routeMap(io.write.bits.idx) := io.write.bits.outCh + routeValid(io.write.bits.idx) := true.B + } + + io.routeMap := routeMap + io.routeValid := routeValid + io.write.ready := true.B +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala index f2d04d08..4094cc49 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -11,6 +11,7 @@ class ReadReq(val b: GlobalConfig) extends Bundle { val bank_id = UInt(log2Up(b.memDomain.bankNum).W) val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) val channel_num = UInt(log2Up(totalReadChannels).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } @instantiable @@ -26,7 +27,7 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val read_req_o = Decoupled(new ReadReq(b)) }) - val reqGroups = (0 until numBalls).flatMap { ballId => + val reqGroupsWithRobId = (0 until numBalls).flatMap { ballId => (0 until numBanks).map { bankId => val ballOffset = ballIdMappings.take(ballId).map(_.inBW).sum val ballInBW = ballIdMappings(ballId).inBW @@ -44,7 +45,9 @@ class ReadReqGen(val b: GlobalConfig) extends Module { io.bank_read_i(ch).bank_id === bankId.U )) - (hasReq, channelCount, bankId.U, ballId.U) + val robId = io.bank_read_i(ballOffset).rob_id + + (hasReq, channelCount, bankId.U, ballId.U, robId) } } @@ -53,20 +56,23 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val channel_num = UInt(log2Up(totalReadChannels + 1).W) val bank_id = UInt(log2Up(numBanks).W) val ball_id = UInt(log2Up(numBalls).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) }, - reqGroups.length + reqGroupsWithRobId.length )) - for (i <- reqGroups.indices) { - arb.io.in(i).valid := reqGroups(i)._1 - arb.io.in(i).bits.channel_num := reqGroups(i)._2 - arb.io.in(i).bits.bank_id := reqGroups(i)._3 - arb.io.in(i).bits.ball_id := reqGroups(i)._4 + for (i <- reqGroupsWithRobId.indices) { + arb.io.in(i).valid := reqGroupsWithRobId(i)._1 + arb.io.in(i).bits.channel_num := reqGroupsWithRobId(i)._2 + arb.io.in(i).bits.bank_id := reqGroupsWithRobId(i)._3 + arb.io.in(i).bits.ball_id := reqGroupsWithRobId(i)._4 + arb.io.in(i).bits.rob_id := reqGroupsWithRobId(i)._5 } io.read_req_o.valid := arb.io.out.valid io.read_req_o.bits.bank_id := arb.io.out.bits.bank_id io.read_req_o.bits.ball_id := arb.io.out.bits.ball_id io.read_req_o.bits.channel_num := arb.io.out.bits.channel_num + io.read_req_o.bits.rob_id := arb.io.out.bits.rob_id arb.io.out.ready := io.read_req_o.ready } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index ad012e42..b7af28a8 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -8,10 +8,14 @@ import framework.top.GlobalConfig class PeakChannelReq(val b: GlobalConfig) extends Bundle { val needed_channel_num = UInt(log2Up(b.ballDomain.ballIdMappings.map(_.inBW).sum + 1).W) + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } class FreeChannelResp(val b: GlobalConfig) extends Bundle { - val is_free = Bool() + val is_free = Bool() + val channel_ids = Vec(b.top.ballMemChannelProducer, UInt(log2Up(b.top.ballMemChannelProducer).W)) + val channel_num = UInt(log2Up(b.top.ballMemChannelProducer + 1).W) } @instantiable @@ -35,16 +39,48 @@ class MemRouter(val b: GlobalConfig) extends Module { val freeChannelResp = Decoupled(new FreeChannelResp(b)) }) - val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) +//--------------------------------------------------------------------------- +// Read +//--------------------------------------------------------------------------- +// Step1: Generate read request + val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) + val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) readReqGen.io.bank_read_i <> io.bankRead_i - - val hasReadReq = readReqGen.io.read_req_o.valid - val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free - val reqAccepted = isChannelFree - +// Step2: Peek if there are enough free channels + val hasReadReq = readReqGen.io.read_req_o.valid io.peakChannelReq.valid := hasReadReq io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num - io.freeChannelResp.ready := hasReadReq + io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id + io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id +// Step3/1: if there are enough free channels, accept the request + val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free + io.freeChannelResp.ready := true.B + val dispatchChannels = io.freeChannelResp.bits.channel_ids + readReqGen.io.read_req_o.ready := isChannelFree +// Step3/2: if there are not enough free channels, continue to peek until there are enough free channels - readReqGen.io.read_req_o.ready := reqAccepted +// Step4: Set the channel mapping table + when(readReqGen.io.read_req_o.fire) { + var matchedCnt = 0.U + for (i <- 0 until totalReadChannels) { + val isMatch = io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && + io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && io.bankRead_i(i).io.req.valid + when(isMatch && matchedCnt < readReqGen.io.read_req_o.bits.channel_num) { + channelMappingTable.io.write.valid := true.B + channelMappingTable.io.write.bits.idx := i.U + channelMappingTable.io.write.bits.outCh := dispatchChannels(matchedCnt) + matchedCnt = matchedCnt + 1.U + } + } + } +// Step5: Dispatch the request to the channels + for (i <- 0 until totalReadChannels) { + when(channelMappingTable.io.routeValid(i)) { + val outCh = channelMappingTable.io.routeMap(i) + io.bankRead_o(outCh).io.req <> io.bankRead_i(i).io.req + io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id + io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id + io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id + } + } } diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 55b5b8c2..873524c2 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -3,7 +3,5 @@ "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1} - ], - "bbusProducerChannels": 6, - "bbusConsumerChannels": 6 + ] } diff --git a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala index b6220fc0..413782af 100644 --- a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala +++ b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala @@ -25,8 +25,54 @@ class BallMemChannel(val b: GlobalConfig) extends Module { VecInit(channelsToMem.map(_.io)) <> io.channelToMemDomain VecInit(channelsFromMem.map(_.io)) <> io.channelFromMemDomain - val freeChannelCount = PopCount(io.channelToMemDomain.map(!_.header.read.lock)) - io.freeChannelResp.valid := io.peakChannelReq.valid - io.freeChannelResp.bits.is_free := freeChannelCount >= io.peakChannelReq.bits.needed_channel_num - io.peakChannelReq.ready := io.freeChannelResp.ready + val headerBuffers = (0 until b.top.ballMemChannelProducer).map(_ => Instantiate(new HeaderBuffer(b))) + + val freeChannels = VecInit(headerBuffers.map(!_.io.read.lock)) + val freeChannelCount = PopCount(freeChannels) + val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num + + val selectedChannelIds = Wire(Vec(b.top.ballMemChannelProducer, UInt(log2Up(b.top.ballMemChannelProducer).W))) + val selectedMask = Wire(Vec(b.top.ballMemChannelProducer, Bool())) + + val masks = Wire(Vec(b.top.ballMemChannelProducer + 1, Vec(b.top.ballMemChannelProducer, Bool()))) + masks(0) := freeChannels + + for (i <- 0 until b.top.ballMemChannelProducer) { + val maskVec = masks(i) + val selOH = PriorityEncoderOH(maskVec.asUInt) + val selIdx = PriorityEncoder(maskVec.asUInt) + selectedMask(i) := maskVec.asUInt.orR && (i.U < io.peakChannelReq.bits.needed_channel_num) + selectedChannelIds(i) := Mux(selectedMask(i), selIdx, 0.U) + if (i < b.top.ballMemChannelProducer) { + masks(i + 1) := VecInit(maskVec.zip(selOH.asBools).map { case (free, sel) => free && !sel }) + } + } + + io.freeChannelResp.valid := io.peakChannelReq.valid + io.freeChannelResp.bits.is_free := hasEnoughChannels + io.freeChannelResp.bits.channel_ids := selectedChannelIds + io.freeChannelResp.bits.channel_num := io.peakChannelReq.bits.needed_channel_num + io.peakChannelReq.ready := io.freeChannelResp.ready + + when(io.peakChannelReq.fire && hasEnoughChannels) { + for (i <- 0 until b.top.ballMemChannelProducer) { + val isSelected = selectedMask.zip(selectedChannelIds).map { case (sel, id) => sel && (id === i.U) }.reduce(_ || _) + when(isSelected) { + val headerData = Wire(new HeaderBufferData(b)) + headerData.lock := true.B + headerData.rob_id := io.peakChannelReq.bits.rob_id + headerData.bank_id := io.peakChannelReq.bits.bank_id + headerBuffers(i).io.set.valid := true.B + headerBuffers(i).io.set.bits := headerData + }.otherwise { + headerBuffers(i).io.set.valid := false.B + headerBuffers(i).io.set.bits := DontCare + } + } + }.otherwise { + for (i <- 0 until b.top.ballMemChannelProducer) { + headerBuffers(i).io.set.valid := false.B + headerBuffers(i).io.set.bits := DontCare + } + } } diff --git a/arch/src/main/scala/framework/top/channels/Channel.scala b/arch/src/main/scala/framework/top/channels/Channel.scala index 1102966a..15d86745 100644 --- a/arch/src/main/scala/framework/top/channels/Channel.scala +++ b/arch/src/main/scala/framework/top/channels/Channel.scala @@ -2,19 +2,12 @@ package framework.top.channels import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig -import framework.top.channels.{HeaderBuffer, HeaderBufferData} class ChannelIO(val b: GlobalConfig) extends Bundle { val producer = Flipped(Decoupled(UInt(b.memDomain.bankWidth.W))) val consumer = Decoupled(UInt(b.memDomain.bankWidth.W)) - - val header = new Bundle { - val read = Output(new HeaderBufferData(b)) - val set = Flipped(Decoupled(new HeaderBufferData(b))) - } - } @instantiable @@ -22,10 +15,5 @@ class Channel(val b: GlobalConfig) extends Module { @public val io = IO(new ChannelIO(b)) - val headerBuffer: Instance[HeaderBuffer] = Instantiate(new HeaderBuffer(b)) - - io.header.read := headerBuffer.io.read - headerBuffer.io.set <> io.header.set - io.consumer <> io.producer } From 38ffc17c777040aa9df63c99c654c6c7b763b513 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 20:21:15 +0800 Subject: [PATCH 031/238] [arch] refactor: remove redundant ball_id, bank_id, and rob_id assignments in MemRouter --- .../scala/framework/balldomain/bbus/memrouter/memRouter.scala | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index b7af28a8..2ffd3396 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -78,9 +78,6 @@ class MemRouter(val b: GlobalConfig) extends Module { when(channelMappingTable.io.routeValid(i)) { val outCh = channelMappingTable.io.routeMap(i) io.bankRead_o(outCh).io.req <> io.bankRead_i(i).io.req - io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id - io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id - io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id } } } From d904ce5398ab6df97458dcd06d6d9d5dd874c74f Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 20:28:22 +0800 Subject: [PATCH 032/238] [arch] slightly update --- .../bbus/memrouter/ChannelMapping.scala | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala index 28cbfc22..b1ddb99f 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala @@ -7,23 +7,23 @@ import framework.top.GlobalConfig @instantiable class ChannelMappingTable(val b: GlobalConfig) extends Module { - val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum - val bbusProducerChannels = b.top.ballMemChannelProducer + val EntryNum = b.ballDomain.ballIdMappings.map(_.inBW).sum + val MappedChannels = b.top.ballMemChannelProducer @public val io = IO(new Bundle { val write = Flipped(Decoupled(new Bundle { - val idx = UInt(log2Up(totalReadChannels).W) - val outCh = UInt(log2Up(bbusProducerChannels).W) + val idx = UInt(log2Up(EntryNum).W) + val outCh = UInt(log2Up(MappedChannels).W) })) - val routeMap = Output(Vec(totalReadChannels, UInt(log2Up(bbusProducerChannels).W))) - val routeValid = Output(Vec(totalReadChannels, Bool())) + val routeMap = Output(Vec(EntryNum, UInt(log2Up(MappedChannels).W))) + val routeValid = Output(Vec(EntryNum, Bool())) }) - val routeMap = Reg(Vec(totalReadChannels, UInt(log2Up(bbusProducerChannels).W))) - val routeValid = RegInit(VecInit(Seq.fill(totalReadChannels)(false.B))) + val routeMap = Reg(Vec(EntryNum, UInt(log2Up(MappedChannels).W))) + val routeValid = RegInit(VecInit(Seq.fill(EntryNum)(false.B))) when(io.write.fire) { routeMap(io.write.bits.idx) := io.write.bits.outCh From f9b5fd0582563c72be01c29ffb532b10014fc997 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 20:52:11 +0800 Subject: [PATCH 033/238] [arch] feat: implement ChannelCluster and refactor BallMemChannel integration --- .../scala/examples/toy/ToyBuckyBall.scala | 26 +++++-- .../examples/toy/balldomain/BallDomain.scala | 19 ++++- .../framework/balldomain/bbus/bbus.scala | 42 ++++++++-- .../balldomain/bbus/memrouter/memRouter.scala | 3 + .../top/channels/BallMemChannel.scala | 78 ------------------- .../framework/top/channels/Channel.scala | 40 ++++++++-- .../top/channels/ChannelCluster.scala | 59 ++++++++++++++ 7 files changed, 169 insertions(+), 98 deletions(-) delete mode 100644 arch/src/main/scala/framework/top/channels/BallMemChannel.scala create mode 100644 arch/src/main/scala/framework/top/channels/ChannelCluster.scala diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index e38ac96b..0b78efee 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -18,7 +18,7 @@ import examples.toy.balldomain.BallDomain import framework.frontend.Frontend import framework.gpdomain.GpDomain import framework.memdomain.MemDomain -import framework.top.channels.{BallMemChannel, Channel, ChannelIO} +import framework.top.channels.{Channel, ChannelCluster, ChannelIO} class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) extends LazyRoCC(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { @@ -60,11 +60,12 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w val (tl_reader, edge_reader) = outer.reader_node.out(0) val (tl_writer, edge_writer) = outer.writer_node.out(0) - val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) - val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) - val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) - val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) - val ballMemChannel: Instance[BallMemChannel] = Instantiate(new BallMemChannel(b)) + val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) + val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) + val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) + val ballMemChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.ballMemChannelProducer)) + val memBallChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.ballMemChannelConsumer)) frontend.io.cmd.valid := io.cmd.valid frontend.io.cmd.bits.cmd := io.cmd.bits @@ -104,7 +105,18 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w ballDomain.bankRead <> memDomain.io.ballDomain.bankRead ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite - ballMemChannel.io <> ballDomain.ballMemChannel + // Connect BallMemChannelCluster + ballMemChannelCluster.io.channelIn <> ballDomain.ballMemChannel.channelIn + ballDomain.ballMemChannel.channelOut <> ballMemChannelCluster.io.channelOut + ballMemChannelCluster.io.peakChannelReq <> ballDomain.ballMemChannel.peakChannelReq + ballDomain.ballMemChannel.freeChannelResp <> ballMemChannelCluster.io.freeChannelResp + + // Connect MemBallChannelCluster + memBallChannelCluster.io.channelIn <> ballDomain.memBallChannelIn + ballDomain.memBallChannelOut <> memBallChannelCluster.io.channelOut + memBallChannelCluster.io.peakChannelReq.ready := true.B + memBallChannelCluster.io.freeChannelResp.valid := false.B + memBallChannelCluster.io.freeChannelResp.bits := DontCare // Connect TileLink DMA ports from MemDomain to LazyModule nodes tl_reader <> memDomain.io.tl_reader diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index ff6468a6..03423c8a 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -10,7 +10,8 @@ import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} import framework.balldomain.rs.BallReservationStation -import framework.top.channels.{BallMemChannelIO, ChannelIO} +import framework.top.channels.ChannelIO +import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} @instantiable class BallDomain(val b: GlobalConfig) extends Module { @@ -29,7 +30,19 @@ class BallDomain(val b: GlobalConfig) extends Module { val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) @public - val ballMemChannel = IO(new BallMemChannelIO(b)) + val ballMemChannel = IO(new Bundle { + // Output to channel.in (channel.in is Flipped, so this is ChannelIO) + val channelIn = Vec(memChannel, new ChannelIO(b)) + // Input from channel.out (channel.out is ChannelIO, so this is Flipped) + val channelOut = Vec(memChannel, Flipped(new ChannelIO(b))) + val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) + val freeChannelResp = Decoupled(new FreeChannelResp(b)) + }) + + @public + val memBallChannelIn = IO(Vec(b.top.ballMemChannelConsumer, Flipped(new ChannelIO(b)))) + @public + val memBallChannelOut = IO(Vec(b.top.ballMemChannelConsumer, new ChannelIO(b))) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) @@ -66,6 +79,8 @@ class BallDomain(val b: GlobalConfig) extends Module { bbus.bankRead <> bankRead bbus.bankWrite <> bankWrite bbus.ballMemChannel <> ballMemChannel + bbus.memBallChannelIn <> memBallChannelIn + bbus.memBallChannelOut <> memBallChannelOut //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 188a7c15..03edf5e4 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -10,7 +10,8 @@ import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter import framework.balldomain.blink.{BankRead, BankWrite} -import framework.top.channels.{BallMemChannelIO, ChannelIO} +import framework.top.channels.{Channel, ChannelIO} +import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices @@ -25,17 +26,31 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) // Rs - bbus - balls @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) // balls - bbus @public - val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + // bbus - mem + // Channel interface: bbus outputs to channel.in (in top level), receives from channel.out + @public + val ballMemChannel = IO(new Bundle { + // Output to channel.in (channel.in is Flipped, so this is ChannelIO) + val channelIn = Vec(bbusProducerChannels, new ChannelIO(b)) + // Input from channel.out (channel.out is ChannelIO, so this is Flipped) + val channelOut = Vec(bbusProducerChannels, Flipped(new ChannelIO(b))) + val peakChannelReq = Decoupled(new PeakChannelReq(b)) + val freeChannelResp = Flipped(Decoupled(new FreeChannelResp(b))) + }) + @public - val ballMemChannel = IO(new BallMemChannelIO(b)) + val memBallChannelIn = IO(Vec(bbusConsumerChannels, Flipped(new ChannelIO(b)))) + @public + val memBallChannelOut = IO(Vec(bbusConsumerChannels, new ChannelIO(b))) val balls = ballGenerators.map(gen => Module(gen())) val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) @@ -72,6 +87,21 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) memoryrouter.io.peakChannelReq <> ballMemChannel.peakChannelReq memoryrouter.io.freeChannelResp <> ballMemChannel.freeChannelResp + // Connect channel outputs (from channel.out in top level) to memory router + // Channels are unified, router handles routing to bankRead_o or bankWrite_o based on request type + // For now, we route to both and let router decide based on internal logic + // TODO: Router should determine read/write based on request metadata + for (i <- 0 until bbusProducerChannels) { + // Connect to both read and write outputs, router will select based on request type + memoryrouter.io.bankRead_o(i).io.req.valid := ballMemChannel.channelOut(i).data.valid + memoryrouter.io.bankRead_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits + memoryrouter.io.bankWrite_o(i).io.req.valid := ballMemChannel.channelOut(i).data.valid + memoryrouter.io.bankWrite_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits + ballMemChannel.channelOut(i).data.ready := memoryrouter.io.bankRead_o( + i + ).io.req.ready || memoryrouter.io.bankWrite_o(i).io.req.ready + } + // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 2ffd3396..b15583d5 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -78,6 +78,9 @@ class MemRouter(val b: GlobalConfig) extends Module { when(channelMappingTable.io.routeValid(i)) { val outCh = channelMappingTable.io.routeMap(i) io.bankRead_o(outCh).io.req <> io.bankRead_i(i).io.req + }.otherwise { + io.bankRead_i(i).io.req.ready := false.B + io.bankRead_i(i).io.req.bits := DontCare } } } diff --git a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala b/arch/src/main/scala/framework/top/channels/BallMemChannel.scala deleted file mode 100644 index 413782af..00000000 --- a/arch/src/main/scala/framework/top/channels/BallMemChannel.scala +++ /dev/null @@ -1,78 +0,0 @@ -package framework.top.channels - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig -import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} - -class BallMemChannelIO(val b: GlobalConfig) extends Bundle { - val channelToMemDomain = Vec(b.top.ballMemChannelProducer, new ChannelIO(b)) - val channelFromMemDomain = Vec(b.top.ballMemChannelConsumer, Flipped(new ChannelIO(b))) - - val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) - val freeChannelResp = Decoupled(new FreeChannelResp(b)) -} - -@instantiable -class BallMemChannel(val b: GlobalConfig) extends Module { - @public - val io = IO(new BallMemChannelIO(b)) - - val channelsToMem = (0 until b.top.ballMemChannelProducer).map(_ => Instantiate(new Channel(b))) - val channelsFromMem = (0 until b.top.ballMemChannelConsumer).map(_ => Instantiate(new Channel(b))) - - VecInit(channelsToMem.map(_.io)) <> io.channelToMemDomain - VecInit(channelsFromMem.map(_.io)) <> io.channelFromMemDomain - - val headerBuffers = (0 until b.top.ballMemChannelProducer).map(_ => Instantiate(new HeaderBuffer(b))) - - val freeChannels = VecInit(headerBuffers.map(!_.io.read.lock)) - val freeChannelCount = PopCount(freeChannels) - val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num - - val selectedChannelIds = Wire(Vec(b.top.ballMemChannelProducer, UInt(log2Up(b.top.ballMemChannelProducer).W))) - val selectedMask = Wire(Vec(b.top.ballMemChannelProducer, Bool())) - - val masks = Wire(Vec(b.top.ballMemChannelProducer + 1, Vec(b.top.ballMemChannelProducer, Bool()))) - masks(0) := freeChannels - - for (i <- 0 until b.top.ballMemChannelProducer) { - val maskVec = masks(i) - val selOH = PriorityEncoderOH(maskVec.asUInt) - val selIdx = PriorityEncoder(maskVec.asUInt) - selectedMask(i) := maskVec.asUInt.orR && (i.U < io.peakChannelReq.bits.needed_channel_num) - selectedChannelIds(i) := Mux(selectedMask(i), selIdx, 0.U) - if (i < b.top.ballMemChannelProducer) { - masks(i + 1) := VecInit(maskVec.zip(selOH.asBools).map { case (free, sel) => free && !sel }) - } - } - - io.freeChannelResp.valid := io.peakChannelReq.valid - io.freeChannelResp.bits.is_free := hasEnoughChannels - io.freeChannelResp.bits.channel_ids := selectedChannelIds - io.freeChannelResp.bits.channel_num := io.peakChannelReq.bits.needed_channel_num - io.peakChannelReq.ready := io.freeChannelResp.ready - - when(io.peakChannelReq.fire && hasEnoughChannels) { - for (i <- 0 until b.top.ballMemChannelProducer) { - val isSelected = selectedMask.zip(selectedChannelIds).map { case (sel, id) => sel && (id === i.U) }.reduce(_ || _) - when(isSelected) { - val headerData = Wire(new HeaderBufferData(b)) - headerData.lock := true.B - headerData.rob_id := io.peakChannelReq.bits.rob_id - headerData.bank_id := io.peakChannelReq.bits.bank_id - headerBuffers(i).io.set.valid := true.B - headerBuffers(i).io.set.bits := headerData - }.otherwise { - headerBuffers(i).io.set.valid := false.B - headerBuffers(i).io.set.bits := DontCare - } - } - }.otherwise { - for (i <- 0 until b.top.ballMemChannelProducer) { - headerBuffers(i).io.set.valid := false.B - headerBuffers(i).io.set.bits := DontCare - } - } -} diff --git a/arch/src/main/scala/framework/top/channels/Channel.scala b/arch/src/main/scala/framework/top/channels/Channel.scala index 15d86745..1a1a62b8 100644 --- a/arch/src/main/scala/framework/top/channels/Channel.scala +++ b/arch/src/main/scala/framework/top/channels/Channel.scala @@ -2,18 +2,48 @@ package framework.top.channels import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig +import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} class ChannelIO(val b: GlobalConfig) extends Bundle { - val producer = Flipped(Decoupled(UInt(b.memDomain.bankWidth.W))) - val consumer = Decoupled(UInt(b.memDomain.bankWidth.W)) + val data = Decoupled(UInt(b.memDomain.bankWidth.W)) } @instantiable class Channel(val b: GlobalConfig) extends Module { + @public - val io = IO(new ChannelIO(b)) + val io = IO(new Bundle { + val in = Flipped(new ChannelIO(b)) + val out = new ChannelIO(b) + + val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) + val freeChannelResp = Decoupled(new FreeChannelResp(b)) + }) + + val headerBuffer: Instance[HeaderBuffer] = Instantiate(new HeaderBuffer(b)) + + val isFree = !headerBuffer.io.read.lock + val hasEnoughChannel = isFree + + io.freeChannelResp.valid := io.peakChannelReq.valid + io.freeChannelResp.bits.is_free := hasEnoughChannel + io.freeChannelResp.bits.channel_ids := DontCare + io.freeChannelResp.bits.channel_num := 1.U + io.peakChannelReq.ready := io.freeChannelResp.ready + + when(io.peakChannelReq.fire && hasEnoughChannel) { + val headerData = Wire(new HeaderBufferData(b)) + headerData.lock := true.B + headerData.rob_id := io.peakChannelReq.bits.rob_id + headerData.bank_id := io.peakChannelReq.bits.bank_id + headerBuffer.io.set.valid := true.B + headerBuffer.io.set.bits := headerData + }.otherwise { + headerBuffer.io.set.valid := false.B + headerBuffer.io.set.bits := DontCare + } - io.consumer <> io.producer + io.out <> io.in } diff --git a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala new file mode 100644 index 00000000..d320b122 --- /dev/null +++ b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala @@ -0,0 +1,59 @@ +package framework.top.channels + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} + +class ChannelClusterIO(val b: GlobalConfig, numChannels: Int) extends Bundle { + val channelIn = Vec(numChannels, Flipped(new ChannelIO(b))) + val channelOut = Vec(numChannels, new ChannelIO(b)) + val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) + val freeChannelResp = Decoupled(new FreeChannelResp(b)) +} + +@instantiable +class ChannelCluster(val b: GlobalConfig, numChannels: Int) extends Module { + @public + val io = IO(new ChannelClusterIO(b, numChannels)) + + val channels = (0 until numChannels).map(_ => Instantiate(new Channel(b))) + + // Connect channels + for (i <- 0 until numChannels) { + channels(i).io.in <> io.channelIn(i) + channels(i).io.out <> io.channelOut(i) + channels(i).io.peakChannelReq.valid := io.peakChannelReq.valid + channels(i).io.peakChannelReq.bits := io.peakChannelReq.bits + channels(i).io.freeChannelResp.ready := true.B + } + + // Aggregate free channel responses + val freeChannels = VecInit(channels.map(ch => ch.io.freeChannelResp.bits.is_free)) + val freeChannelCount = PopCount(freeChannels) + val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num + + val selectedChannelIds = Wire(Vec(numChannels, UInt(log2Up(numChannels).W))) + val selectedMask = Wire(Vec(numChannels, Bool())) + + val masks = Wire(Vec(numChannels + 1, Vec(numChannels, Bool()))) + masks(0) := freeChannels + + for (i <- 0 until numChannels) { + val maskVec = masks(i) + val selOH = PriorityEncoderOH(maskVec.asUInt) + val selIdx = PriorityEncoder(maskVec.asUInt) + selectedMask(i) := maskVec.asUInt.orR && (i.U < io.peakChannelReq.bits.needed_channel_num) + selectedChannelIds(i) := Mux(selectedMask(i), selIdx, 0.U) + if (i < numChannels) { + masks(i + 1) := VecInit(maskVec.zip(selOH.asBools).map { case (free, sel) => free && !sel }) + } + } + + io.freeChannelResp.valid := io.peakChannelReq.valid + io.freeChannelResp.bits.is_free := hasEnoughChannels + io.freeChannelResp.bits.channel_ids := selectedChannelIds + io.freeChannelResp.bits.channel_num := io.peakChannelReq.bits.needed_channel_num + io.peakChannelReq.ready := io.freeChannelResp.ready +} From e33396aa15fe3182a0836cd7b34a1abe7258fb69 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 20:59:09 +0800 Subject: [PATCH 034/238] [arch] refactor: update BallDomain and related modules to use unified memory channel configurations --- .../scala/examples/toy/ToyBuckyBall.scala | 4 ++-- .../examples/toy/balldomain/BallDomain.scala | 6 +++--- .../framework/balldomain/bbus/bbus.scala | 4 ++-- .../bbus/memrouter/ChannelMapping.scala | 2 +- .../balldomain/bbus/memrouter/memRouter.scala | 19 ++++++++++--------- .../scala/framework/memdomain/MemDomain.scala | 4 ++-- .../memdomain/midend/MemMidend.scala | 6 +++--- .../framework/top/channels/Channel.scala | 12 +++++------- .../top/channels/ChannelCluster.scala | 1 - .../framework/top/configs/TopConfig.scala | 4 ++-- .../scala/framework/top/configs/default.json | 4 ++-- 11 files changed, 32 insertions(+), 34 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 0b78efee..75c9d145 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -64,8 +64,8 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) - val ballMemChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.ballMemChannelProducer)) - val memBallChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.ballMemChannelConsumer)) + val ballMemChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.ballMemChannelNum)) + val memBallChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.memBallChannelNum)) frontend.io.cmd.valid := io.cmd.valid frontend.io.cmd.bits.cmd := io.cmd.bits diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 03423c8a..26e35d39 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -15,7 +15,7 @@ import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} @instantiable class BallDomain(val b: GlobalConfig) extends Module { - val memChannel = b.top.ballMemChannelProducer + val memChannel = b.top.ballMemChannelNum @public val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(b)))) @@ -40,9 +40,9 @@ class BallDomain(val b: GlobalConfig) extends Module { }) @public - val memBallChannelIn = IO(Vec(b.top.ballMemChannelConsumer, Flipped(new ChannelIO(b)))) + val memBallChannelIn = IO(Vec(b.top.memBallChannelNum, Flipped(new ChannelIO(b)))) @public - val memBallChannelOut = IO(Vec(b.top.ballMemChannelConsumer, new ChannelIO(b))) + val memBallChannelOut = IO(Vec(b.top.memBallChannelNum, new ChannelIO(b))) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 03edf5e4..0f48e314 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -19,8 +19,8 @@ import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} @instantiable class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) extends Module { val numBalls = b.ballDomain.ballNum - val bbusProducerChannels = b.top.ballMemChannelProducer - val bbusConsumerChannels = b.top.ballMemChannelConsumer + val bbusProducerChannels = b.top.ballMemChannelNum + val bbusConsumerChannels = b.top.memBallChannelNum val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala index b1ddb99f..cd22c5a0 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala @@ -8,7 +8,7 @@ import framework.top.GlobalConfig @instantiable class ChannelMappingTable(val b: GlobalConfig) extends Module { val EntryNum = b.ballDomain.ballIdMappings.map(_.inBW).sum - val MappedChannels = b.top.ballMemChannelProducer + val MappedChannels = b.top.ballMemChannelNum @public val io = IO(new Bundle { diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index b15583d5..6834bc66 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -14,15 +14,15 @@ class PeakChannelReq(val b: GlobalConfig) extends Bundle { class FreeChannelResp(val b: GlobalConfig) extends Bundle { val is_free = Bool() - val channel_ids = Vec(b.top.ballMemChannelProducer, UInt(log2Up(b.top.ballMemChannelProducer).W)) - val channel_num = UInt(log2Up(b.top.ballMemChannelProducer + 1).W) + val channel_ids = Vec(b.top.ballMemChannelNum, UInt(log2Up(b.top.ballMemChannelNum).W)) + val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) } @instantiable class MemRouter(val b: GlobalConfig) extends Module { val numBalls = b.ballDomain.ballNum - val bbusProducerChannels = b.top.ballMemChannelProducer - val bbusConsumerChannels = b.top.ballMemChannelConsumer + val bbusProducerChannels = b.top.ballMemChannelNum + val bbusConsumerChannels = b.top.memBallChannelNum val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum val maxPerChannelWidth = b.ballDomain.ballIdMappings.flatMap(m => Seq(m.inBW, m.outBW)).max @@ -47,11 +47,12 @@ class MemRouter(val b: GlobalConfig) extends Module { val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) readReqGen.io.bank_read_i <> io.bankRead_i // Step2: Peek if there are enough free channels - val hasReadReq = readReqGen.io.read_req_o.valid - io.peakChannelReq.valid := hasReadReq - io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num - io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id - io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id + // val hasReadReq = readReqGen.io.read_req_o.valid + // io.peakChannelReq.valid := hasReadReq + // io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num + // io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id + // io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id + io.peakChannelReq <> readReqGen.io.read_req_o // Step3/1: if there are enough free channels, accept the request val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free io.freeChannelResp.ready := true.B diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 11b9129c..85eb5e07 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -36,8 +36,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) // Use bbusProducerChannels and bbusConsumerChannels instead of bankNum to match BallDomain output val ballDomain = new Bundle { - val bankRead = Vec(b.top.ballMemChannelConsumer, new BankRead(b)) - val bankWrite = Vec(b.top.ballMemChannelProducer, new BankWrite(b)) + val bankRead = Vec(b.top.memBallChannelNum, new BankRead(b)) + val bankWrite = Vec(b.top.ballMemChannelNum, new BankWrite(b)) } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 6728373a..003094a4 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -22,8 +22,8 @@ class MemMidend(val b: GlobalConfig) extends Module { // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { - val bankRead = Vec(b.top.ballMemChannelConsumer, new BankRead(b)) - val bankWrite = Vec(b.top.ballMemChannelProducer, new BankWrite(b)) + val bankRead = Vec(b.top.memBallChannelNum, new BankRead(b)) + val bankWrite = Vec(b.top.ballMemChannelNum, new BankWrite(b)) } // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here @@ -37,7 +37,7 @@ class MemMidend(val b: GlobalConfig) extends Module { // Each input channel is mapped to a backend channel based on modulo for (ch <- 0 until b.memDomain.bankChannel) { - val inputIdx = ch % b.top.ballMemChannelConsumer + val inputIdx = ch % b.top.memBallChannelNum // Map input channels to backend channels io.mem_req(ch).write <> io.frontend.bankWrite(inputIdx).io diff --git a/arch/src/main/scala/framework/top/channels/Channel.scala b/arch/src/main/scala/framework/top/channels/Channel.scala index 1a1a62b8..366156b5 100644 --- a/arch/src/main/scala/framework/top/channels/Channel.scala +++ b/arch/src/main/scala/framework/top/channels/Channel.scala @@ -30,16 +30,14 @@ class Channel(val b: GlobalConfig) extends Module { io.freeChannelResp.valid := io.peakChannelReq.valid io.freeChannelResp.bits.is_free := hasEnoughChannel io.freeChannelResp.bits.channel_ids := DontCare - io.freeChannelResp.bits.channel_num := 1.U + io.freeChannelResp.bits.channel_num := io.peakChannelReq.bits.needed_channel_num io.peakChannelReq.ready := io.freeChannelResp.ready when(io.peakChannelReq.fire && hasEnoughChannel) { - val headerData = Wire(new HeaderBufferData(b)) - headerData.lock := true.B - headerData.rob_id := io.peakChannelReq.bits.rob_id - headerData.bank_id := io.peakChannelReq.bits.bank_id - headerBuffer.io.set.valid := true.B - headerBuffer.io.set.bits := headerData + headerBuffer.io.set.valid := true.B + headerBuffer.io.set.bits.rob_id := io.peakChannelReq.bits.rob_id + headerBuffer.io.set.bits.bank_id := io.peakChannelReq.bits.bank_id + headerBuffer.io.set.bits.lock := true.B }.otherwise { headerBuffer.io.set.valid := false.B headerBuffer.io.set.bits := DontCare diff --git a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala index d320b122..9143781d 100644 --- a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala +++ b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala @@ -29,7 +29,6 @@ class ChannelCluster(val b: GlobalConfig, numChannels: Int) extends Module { channels(i).io.freeChannelResp.ready := true.B } - // Aggregate free channel responses val freeChannels = VecInit(channels.map(ch => ch.io.freeChannelResp.bits.is_free)) val freeChannelCount = PopCount(freeChannels) val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num diff --git a/arch/src/main/scala/framework/top/configs/TopConfig.scala b/arch/src/main/scala/framework/top/configs/TopConfig.scala index 31272bec..cbb493f4 100644 --- a/arch/src/main/scala/framework/top/configs/TopConfig.scala +++ b/arch/src/main/scala/framework/top/configs/TopConfig.scala @@ -3,8 +3,8 @@ package framework.top.configs import upickle.default._ case class TopConfig( - ballMemChannelProducer: Int, - ballMemChannelConsumer: Int) + ballMemChannelNum: Int, + memBallChannelNum: Int) object TopConfig { implicit val rw: ReadWriter[TopConfig] = macroRW diff --git a/arch/src/main/scala/framework/top/configs/default.json b/arch/src/main/scala/framework/top/configs/default.json index 52af17a0..a5888670 100644 --- a/arch/src/main/scala/framework/top/configs/default.json +++ b/arch/src/main/scala/framework/top/configs/default.json @@ -1,4 +1,4 @@ { - "ballMemChannelProducer": 6, - "ballMemChannelConsumer": 6 + "ballMemChannelNum": 6, + "memBallChannelNum": 6 } From 1b778494cd961e155b8336c5503e2f2fa399eb41 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 21:07:31 +0800 Subject: [PATCH 035/238] [arch] del: remove fpga package object --- .../main/scala/palladium/fpga/package.scala | 21 ------------------- 1 file changed, 21 deletions(-) delete mode 100644 arch/src/main/scala/palladium/fpga/package.scala diff --git a/arch/src/main/scala/palladium/fpga/package.scala b/arch/src/main/scala/palladium/fpga/package.scala deleted file mode 100644 index 2ea3ec29..00000000 --- a/arch/src/main/scala/palladium/fpga/package.scala +++ /dev/null @@ -1,21 +0,0 @@ -package object palladium { - - object fpga { - import org.chipsalliance.cde.config.{Config, Field} - - case object FPGAFrequencyKey extends Field[Double](100.0) // Default to 100MHz - case object VCU19PTweaksKey extends Field[Boolean](true) - - class WithFPGAFrequency(freqMHz: Double) - extends Config((site, here, up) => { - case FPGAFrequencyKey => freqMHz - }) - - class WithVCU19PTweaks - extends Config((site, here, up) => { - case VCU19PTweaksKey => true - }) - - } - -} From 83e3a0cb10dcdfdf08b7932a350df4219b23d679 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 4 Jan 2026 21:13:45 +0800 Subject: [PATCH 036/238] [arch] refactor: simplify BallDomain and BBus channel connections using ChannelClusterIO --- .../scala/examples/toy/ToyBuckyBall.scala | 8 ++--- .../examples/toy/balldomain/BallDomain.scala | 18 +++-------- .../framework/balldomain/bbus/bbus.scala | 31 +++++++------------ 3 files changed, 18 insertions(+), 39 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 75c9d145..67398f67 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -106,14 +106,10 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite // Connect BallMemChannelCluster - ballMemChannelCluster.io.channelIn <> ballDomain.ballMemChannel.channelIn - ballDomain.ballMemChannel.channelOut <> ballMemChannelCluster.io.channelOut - ballMemChannelCluster.io.peakChannelReq <> ballDomain.ballMemChannel.peakChannelReq - ballDomain.ballMemChannel.freeChannelResp <> ballMemChannelCluster.io.freeChannelResp + ballMemChannelCluster.io <> ballDomain.ballMemChannel // Connect MemBallChannelCluster - memBallChannelCluster.io.channelIn <> ballDomain.memBallChannelIn - ballDomain.memBallChannelOut <> memBallChannelCluster.io.channelOut + memBallChannelCluster.io <> ballDomain.memBallChannel memBallChannelCluster.io.peakChannelReq.ready := true.B memBallChannelCluster.io.freeChannelResp.valid := false.B memBallChannelCluster.io.freeChannelResp.bits := DontCare diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 26e35d39..efa3b858 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -10,7 +10,7 @@ import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} import framework.balldomain.rs.BallReservationStation -import framework.top.channels.ChannelIO +import framework.top.channels.{ChannelClusterIO, ChannelIO} import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} @instantiable @@ -30,19 +30,10 @@ class BallDomain(val b: GlobalConfig) extends Module { val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) @public - val ballMemChannel = IO(new Bundle { - // Output to channel.in (channel.in is Flipped, so this is ChannelIO) - val channelIn = Vec(memChannel, new ChannelIO(b)) - // Input from channel.out (channel.out is ChannelIO, so this is Flipped) - val channelOut = Vec(memChannel, Flipped(new ChannelIO(b))) - val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) - val freeChannelResp = Decoupled(new FreeChannelResp(b)) - }) + val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, memChannel))) @public - val memBallChannelIn = IO(Vec(b.top.memBallChannelNum, Flipped(new ChannelIO(b)))) - @public - val memBallChannelOut = IO(Vec(b.top.memBallChannelNum, new ChannelIO(b))) + val memBallChannel = IO(new ChannelClusterIO(b, b.top.memBallChannelNum)) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) @@ -79,8 +70,7 @@ class BallDomain(val b: GlobalConfig) extends Module { bbus.bankRead <> bankRead bbus.bankWrite <> bankWrite bbus.ballMemChannel <> ballMemChannel - bbus.memBallChannelIn <> memBallChannelIn - bbus.memBallChannelOut <> memBallChannelOut + bbus.memBallChannel <> memBallChannel //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 0f48e314..ba1b659c 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -10,7 +10,7 @@ import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.bbus.memrouter.MemRouter import framework.balldomain.blink.{BankRead, BankWrite} -import framework.top.channels.{Channel, ChannelIO} +import framework.top.channels.{Channel, ChannelClusterIO, ChannelIO} import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} /** @@ -18,11 +18,11 @@ import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} */ @instantiable class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) extends Module { - val numBalls = b.ballDomain.ballNum - val bbusProducerChannels = b.top.ballMemChannelNum - val bbusConsumerChannels = b.top.memBallChannelNum - val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum - val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + val numBalls = b.ballDomain.ballNum + val ballMemChannelNum = b.top.ballMemChannelNum + val memBallChannelNum = b.top.memBallChannelNum + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum // Rs - bbus - balls @public @@ -36,21 +36,14 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) // bbus - mem - // Channel interface: bbus outputs to channel.in (in top level), receives from channel.out + // Channel interface using ChannelClusterIO + // For ballMemChannel: bbus outputs to channel.in, receives from channel.out + // So we need Flipped because direction is reversed from ChannelClusterIO's perspective @public - val ballMemChannel = IO(new Bundle { - // Output to channel.in (channel.in is Flipped, so this is ChannelIO) - val channelIn = Vec(bbusProducerChannels, new ChannelIO(b)) - // Input from channel.out (channel.out is ChannelIO, so this is Flipped) - val channelOut = Vec(bbusProducerChannels, Flipped(new ChannelIO(b))) - val peakChannelReq = Decoupled(new PeakChannelReq(b)) - val freeChannelResp = Flipped(Decoupled(new FreeChannelResp(b))) - }) + val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, ballMemChannelNum))) @public - val memBallChannelIn = IO(Vec(bbusConsumerChannels, Flipped(new ChannelIO(b)))) - @public - val memBallChannelOut = IO(Vec(bbusConsumerChannels, new ChannelIO(b))) + val memBallChannel = IO(new ChannelClusterIO(b, memBallChannelNum)) val balls = ballGenerators.map(gen => Module(gen())) val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) @@ -91,7 +84,7 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) // Channels are unified, router handles routing to bankRead_o or bankWrite_o based on request type // For now, we route to both and let router decide based on internal logic // TODO: Router should determine read/write based on request metadata - for (i <- 0 until bbusProducerChannels) { + for (i <- 0 until ballMemChannelNum) { // Connect to both read and write outputs, router will select based on request type memoryrouter.io.bankRead_o(i).io.req.valid := ballMemChannel.channelOut(i).data.valid memoryrouter.io.bankRead_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits From 5758a611096417dad07e66703ac0bec5aa787771 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sun, 4 Jan 2026 22:13:07 +0800 Subject: [PATCH 037/238] [arch] fix: fix some bugs of the connection about memrouter --- .../scala/framework/balldomain/bbus/bbus.scala | 4 +--- .../balldomain/bbus/memrouter/memRouter.scala | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index ba1b659c..beed869e 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -90,9 +90,7 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) memoryrouter.io.bankRead_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits memoryrouter.io.bankWrite_o(i).io.req.valid := ballMemChannel.channelOut(i).data.valid memoryrouter.io.bankWrite_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits - ballMemChannel.channelOut(i).data.ready := memoryrouter.io.bankRead_o( - i - ).io.req.ready || memoryrouter.io.bankWrite_o(i).io.req.ready + ballMemChannel.channelOut(i).data.ready := memoryrouter.io.bankRead_o(i).io.req.ready || memoryrouter.io.bankWrite_o(i).io.req.ready } // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 6834bc66..7138420a 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -45,7 +45,15 @@ class MemRouter(val b: GlobalConfig) extends Module { // Step1: Generate read request val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) - readReqGen.io.bank_read_i <> io.bankRead_i + // readReqGen.io.bank_read_i := io.bankRead_i + for (i <- 0 until totalReadChannels) { + readReqGen.io.bank_read_i(i).ball_id := io.bankRead_i(i).ball_id + readReqGen.io.bank_read_i(i).bank_id := io.bankRead_i(i).bank_id + readReqGen.io.bank_read_i(i).rob_id := io.bankRead_i(i).rob_id + readReqGen.io.bank_read_i(i).req_valid := io.bankRead_i(i).io.req.valid + readReqGen.io.bank_read_i(i).req_addr := io.bankRead_i(i).io.req.bits.addr + } + // Step2: Peek if there are enough free channels // val hasReadReq = readReqGen.io.read_req_o.valid // io.peakChannelReq.valid := hasReadReq @@ -59,6 +67,9 @@ class MemRouter(val b: GlobalConfig) extends Module { val dispatchChannels = io.freeChannelResp.bits.channel_ids readReqGen.io.read_req_o.ready := isChannelFree // Step3/2: if there are not enough free channels, continue to peek until there are enough free channels + channelMappingTable.io.write.valid := false.B + channelMappingTable.io.write.bits.idx := 0.U + channelMappingTable.io.write.bits.outCh := 0.U // Step4: Set the channel mapping table when(readReqGen.io.read_req_o.fire) { @@ -81,7 +92,7 @@ class MemRouter(val b: GlobalConfig) extends Module { io.bankRead_o(outCh).io.req <> io.bankRead_i(i).io.req }.otherwise { io.bankRead_i(i).io.req.ready := false.B - io.bankRead_i(i).io.req.bits := DontCare + // io.bankRead_i(i).io.req.bits := DontCare } } } From 86cb20385de9653a722eb2e3b5b7faf50a172994 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sun, 4 Jan 2026 22:38:40 +0800 Subject: [PATCH 038/238] [arch] fix: fix some bugs of the connection about memroute againr --- .../framework/balldomain/bbus/memrouter/memRouter.scala | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 7138420a..39b09b1e 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -47,11 +47,10 @@ class MemRouter(val b: GlobalConfig) extends Module { val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) // readReqGen.io.bank_read_i := io.bankRead_i for (i <- 0 until totalReadChannels) { - readReqGen.io.bank_read_i(i).ball_id := io.bankRead_i(i).ball_id - readReqGen.io.bank_read_i(i).bank_id := io.bankRead_i(i).bank_id - readReqGen.io.bank_read_i(i).rob_id := io.bankRead_i(i).rob_id - readReqGen.io.bank_read_i(i).req_valid := io.bankRead_i(i).io.req.valid - readReqGen.io.bank_read_i(i).req_addr := io.bankRead_i(i).io.req.bits.addr + io.bankRead_i(i).ball_id := readReqGen.io.bank_read_i(i).ball_id + io.bankRead_i(i).rob_id := readReqGen.io.bank_read_i(i).rob_id + io.bankRead_i(i).io.req.valid := readReqGen.io.bank_read_i(i).io.req.valid + io.bankRead_i(i).io.req.bits := readReqGen.io.bank_read_i(i).io.req.bits } // Step2: Peek if there are enough free channels From a21572c46f59362bd892f8885d7ff4a03096393e Mon Sep 17 00:00:00 2001 From: SJM946 Date: Sun, 4 Jan 2026 23:53:30 +0800 Subject: [PATCH 039/238] [arch]Fix some initialization bugs --- .../scala/examples/toy/ToyBuckyBall.scala | 3 - .../examples/toy/balldomain/BallDomain.scala | 2 +- .../framework/balldomain/bbus/bbus.scala | 70 +++++++++++++++++-- .../balldomain/prototype/relu/Relu.scala | 5 +- .../balldomain/prototype/vector/VecUnit.scala | 4 +- .../frontend/outside_channel/MemLoader.scala | 5 +- .../frontend/outside_channel/MemStorer.scala | 1 + 7 files changed, 77 insertions(+), 13 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 67398f67..23b9b462 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -110,9 +110,6 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w // Connect MemBallChannelCluster memBallChannelCluster.io <> ballDomain.memBallChannel - memBallChannelCluster.io.peakChannelReq.ready := true.B - memBallChannelCluster.io.freeChannelResp.valid := false.B - memBallChannelCluster.io.freeChannelResp.bits := DontCare // Connect TileLink DMA ports from MemDomain to LazyModule nodes tl_reader <> memDomain.io.tl_reader diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index efa3b858..d07d4fbd 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -33,7 +33,7 @@ class BallDomain(val b: GlobalConfig) extends Module { val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, memChannel))) @public - val memBallChannel = IO(new ChannelClusterIO(b, b.top.memBallChannelNum)) + val memBallChannel = IO(Flipped(new ChannelClusterIO(b, b.top.memBallChannelNum))) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index beed869e..080923fc 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -23,7 +23,7 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val memBallChannelNum = b.top.memBallChannelNum val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum - + val memChannel = b.top.ballMemChannelNum // Rs - bbus - balls @public val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @@ -31,9 +31,9 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) // balls - bbus @public - val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(memChannel, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) // bbus - mem // Channel interface using ChannelClusterIO @@ -43,7 +43,7 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, ballMemChannelNum))) @public - val memBallChannel = IO(new ChannelClusterIO(b, memBallChannelNum)) + val memBallChannel = IO(Flipped(new ChannelClusterIO(b, memBallChannelNum))) val balls = ballGenerators.map(gen => Module(gen())) val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) @@ -72,6 +72,48 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) cmdResp <> cmdRouter.io.cmdResp_o +// Initialize bankRead and bankWrite ports with default values + for (i <- 0 until memChannel) { + bankRead(i).bank_id := 0.U + bankRead(i).rob_id := 0.U + bankRead(i).ball_id := 0.U + bankRead(i).io.req.valid := false.B + bankRead(i).io.req.bits.addr := 0.U + bankRead(i).io.resp.ready := false.B + + bankWrite(i).bank_id := 0.U + bankWrite(i).rob_id := 0.U + bankWrite(i).ball_id := 0.U + bankWrite(i).io.req.valid := false.B + bankWrite(i).io.req.bits.addr := 0.U + bankWrite(i).io.req.bits.mask := 0.U.asTypeOf(Vec(b.memDomain.bankMaskLen, Bool())) + bankWrite(i).io.req.bits.data := 0.U + bankWrite(i).io.req.bits.wmode := false.B + bankWrite(i).io.resp.ready := false.B + } + +// Initialize ballMemChannel and memBallChannel ports with default values + for (i <- 0 until ballMemChannelNum) { + ballMemChannel.channelIn(i).data.valid := false.B + ballMemChannel.channelIn(i).data.bits := 0.U + ballMemChannel.channelOut(i).data.ready := false.B + } + ballMemChannel.peakChannelReq.valid := false.B + ballMemChannel.peakChannelReq.bits.needed_channel_num := 0.U + ballMemChannel.peakChannelReq.bits.bank_id := 0.U + ballMemChannel.peakChannelReq.bits.rob_id := 0.U + ballMemChannel.freeChannelResp.ready := true.B + + for (i <- 0 until memBallChannelNum) { + memBallChannel.channelIn(i).data.valid := false.B + memBallChannel.channelIn(i).data.bits := 0.U + memBallChannel.channelOut(i).data.ready := false.B + } + memBallChannel.peakChannelReq.valid := false.B + memBallChannel.peakChannelReq.bits.needed_channel_num := 0.U + memBallChannel.peakChannelReq.bits.bank_id := 0.U + memBallChannel.peakChannelReq.bits.rob_id := 0.U + memBallChannel.freeChannelResp.ready := true.B // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- @@ -92,7 +134,6 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) memoryrouter.io.bankWrite_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits ballMemChannel.channelOut(i).data.ready := memoryrouter.io.bankRead_o(i).io.req.ready || memoryrouter.io.bankWrite_o(i).io.req.ready } - // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- @@ -103,4 +144,23 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) pmc.io.cmdResp_o(i).bits := cmdRouter.io.cmdResp_o(i).bits } +// Initialize balls' bankRead and bankWrite ports with default values + for (ball <- balls) { + val ballConfig = b.ballDomain.ballIdMappings.find(_.ballName == ball.getClass.getSimpleName) + val inBW = ballConfig.map(_.inBW).getOrElse(0) + val outBW = ballConfig.map(_.outBW).getOrElse(0) + + for (i <- 0 until inBW) { + ball.blink.bankRead(i).io.req.ready := false.B + ball.blink.bankRead(i).io.resp.valid := false.B + ball.blink.bankRead(i).io.resp.bits.data := 0.U + } + + for (i <- 0 until outBW) { + ball.blink.bankWrite(i).io.req.ready := false.B + ball.blink.bankWrite(i).io.resp.valid := false.B + ball.blink.bankWrite(i).io.resp.bits.ok := false.B + } + } + } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 55df3dec..0db2ce9e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -40,9 +40,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { for (i <- 0 until inBW) { io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U } val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) @@ -79,7 +81,8 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.addr := 0.U io.bankWrite(i).io.req.bits.data := 0.U io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) - io.bankWrite(i).io.req.bits.wmode := false.B // direct write mode + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B } for (i <- 0 until inBW) { diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index 9fee5f52..af505b2f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -40,12 +40,14 @@ class VecUnit(val b: GlobalConfig) extends Module { rob_id_reg := io.cmdReq.bits.rob_id } - // Set rob_id for all bankRead and bankWrite channels from register + // Set rob_id and ball_id for all bankRead and bankWrite channels from register for (i <- 0 until inBW) { io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U } val VecCtrlUnit: Instance[VecCtrlUnit] = Instantiate(new VecCtrlUnit(b)) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 32772968..d6def88c 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -97,10 +97,11 @@ class MemLoader(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.addr := target_row io.bankWrite(i).io.req.bits.data := io.dmaResp.bits.data io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - io.bankWrite(i).io.req.bits.wmode := false.B // Load is always overwrite - io.bankWrite(i).io.resp.ready := false.B // Add missing resp.ready + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).bank_id := target_bank + io.bankWrite(i).ball_id := 0.U } // Send completion signal - only send when last response is received diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 0f703cea..59f16b5b 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -81,6 +81,7 @@ class MemStorer(val b: GlobalConfig) extends Module { io.bankRead(i).io.req.bits.addr := target_row io.bankRead(i).rob_id := rob_id_reg io.bankRead(i).bank_id := target_bank + io.bankRead(i).ball_id := 0.U } // Bank response processing From 7f6ee9d012388b375d4d85358be6cd964df391a1 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 5 Jan 2026 00:35:19 +0800 Subject: [PATCH 040/238] [arch] fix: fix some bugs of the dead lock of channel module --- .../examples/toy/balldomain/BallDomain.scala | 4 +- .../top/channels/ChannelCluster.scala | 43 +++++++++++++------ .../framework/top/channels/headerBuffer.scala | 5 ++- 3 files changed, 36 insertions(+), 16 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index d07d4fbd..c7afd095 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -30,10 +30,10 @@ class BallDomain(val b: GlobalConfig) extends Module { val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) @public - val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, memChannel))) + val ballMemChannel = IO(Flipped(new ChannelClusterIO(b))) @public - val memBallChannel = IO(Flipped(new ChannelClusterIO(b, b.top.memBallChannelNum))) + val memBallChannel = IO(Flipped(new ChannelClusterIO(b))) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) diff --git a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala index 9143781d..573deac4 100644 --- a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala +++ b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala @@ -6,22 +6,22 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.top.GlobalConfig import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} -class ChannelClusterIO(val b: GlobalConfig, numChannels: Int) extends Bundle { - val channelIn = Vec(numChannels, Flipped(new ChannelIO(b))) - val channelOut = Vec(numChannels, new ChannelIO(b)) +class ChannelClusterIO(val b: GlobalConfig) extends Bundle { + val channelIn = Vec(b.top.ballMemChannelNum, Flipped(new ChannelIO(b))) + val channelOut = Vec(b.top.ballMemChannelNum, new ChannelIO(b)) val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) val freeChannelResp = Decoupled(new FreeChannelResp(b)) } @instantiable -class ChannelCluster(val b: GlobalConfig, numChannels: Int) extends Module { +class ChannelCluster(val b: GlobalConfig) extends Module { @public - val io = IO(new ChannelClusterIO(b, numChannels)) + val io = IO(new ChannelClusterIO(b)) - val channels = (0 until numChannels).map(_ => Instantiate(new Channel(b))) + val channels = (0 until b.top.ballMemChannelNum).map(_ => Instantiate(new Channel(b))) // Connect channels - for (i <- 0 until numChannels) { + for (i <- 0 until b.top.ballMemChannelNum) { channels(i).io.in <> io.channelIn(i) channels(i).io.out <> io.channelOut(i) channels(i).io.peakChannelReq.valid := io.peakChannelReq.valid @@ -33,23 +33,42 @@ class ChannelCluster(val b: GlobalConfig, numChannels: Int) extends Module { val freeChannelCount = PopCount(freeChannels) val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num - val selectedChannelIds = Wire(Vec(numChannels, UInt(log2Up(numChannels).W))) - val selectedMask = Wire(Vec(numChannels, Bool())) + val selectedChannelIds = Wire(Vec(b.top.ballMemChannelNum, UInt(log2Up(b.top.ballMemChannelNum).W))) + val selectedMask = Wire(Vec(b.top.ballMemChannelNum, Bool())) - val masks = Wire(Vec(numChannels + 1, Vec(numChannels, Bool()))) + val masks = Wire(Vec(b.top.ballMemChannelNum + 1, Vec(b.top.ballMemChannelNum, Bool()))) masks(0) := freeChannels - for (i <- 0 until numChannels) { + for (i <- 0 until b.top.ballMemChannelNum) { val maskVec = masks(i) val selOH = PriorityEncoderOH(maskVec.asUInt) val selIdx = PriorityEncoder(maskVec.asUInt) selectedMask(i) := maskVec.asUInt.orR && (i.U < io.peakChannelReq.bits.needed_channel_num) selectedChannelIds(i) := Mux(selectedMask(i), selIdx, 0.U) - if (i < numChannels) { + if (i < b.top.ballMemChannelNum) { masks(i + 1) := VecInit(maskVec.zip(selOH.asBools).map { case (free, sel) => free && !sel }) } } + // ----------------------------- + // Convert selectedChannelIds to "whether each channel is selected". + // ----------------------------- + val selectedPerChan = Wire(Vec(b.top.ballMemChannelNum, Bool())) + for (ch <- 0 until b.top.ballMemChannelNum) { + // If the ch appears in the list of selected ids (and the slot is valid), it is considered selected. + selectedPerChan(ch) := (0 until b.top.ballMemChannelNum).map { k => + selectedMask(k) && (selectedChannelIds(k) === ch.U) + }.reduce(_ || _) + } + + // Allocation is only truly "distributed" when the upstream handshake is successful and sufficient resources are available. + val doAlloc = io.peakChannelReq.valid && io.freeChannelResp.ready && hasEnoughChannels + +// Only raise the valid flag for the selected channel to avoid locking all channels simultaneously by firing. + for (i <- 0 until b.top.ballMemChannelNum) { + channels(i).io.peakChannelReq.valid := doAlloc && selectedPerChan(i) + } + io.freeChannelResp.valid := io.peakChannelReq.valid io.freeChannelResp.bits.is_free := hasEnoughChannels io.freeChannelResp.bits.channel_ids := selectedChannelIds diff --git a/arch/src/main/scala/framework/top/channels/headerBuffer.scala b/arch/src/main/scala/framework/top/channels/headerBuffer.scala index ee06c505..236cf261 100644 --- a/arch/src/main/scala/framework/top/channels/headerBuffer.scala +++ b/arch/src/main/scala/framework/top/channels/headerBuffer.scala @@ -20,10 +20,11 @@ class HeaderBuffer(val b: GlobalConfig) extends Module { val set = Flipped(Decoupled(new HeaderBufferData(b))) }) - val reg = Reg(new HeaderBufferData(b)) + val reg = RegInit(0.U.asTypeOf(new HeaderBufferData(b))) io.read := reg - io.set.ready := !reg.lock + io.set.ready := !reg.lock || (io.set.bits.lock === false.B) + when(io.set.fire) { reg := io.set.bits } From daf63e0a85df9d0d99abca866e66ea593c7ad9b0 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 5 Jan 2026 13:05:44 +0800 Subject: [PATCH 041/238] [arch]feat:add initialization of some val --- .../scala/framework/memdomain/backend/accpipe/AccPipe.scala | 3 +++ .../scala/framework/memdomain/backend/banks/SramBank.scala | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index c299375e..2bbeced6 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -79,6 +79,9 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramRead.req.bits.addr := 0.U io.sramRead.resp.ready := false.B + io.current_bank_id := 0.U + io.busy := false.B + // State machine logic when(state === s_idle) { when(io.write.req.valid) { diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala index 65b2177d..b4fd3848 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala @@ -40,7 +40,7 @@ class SramBank(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- io.sramWrite.req.ready := !io.sramRead.req.valid - when(io.sramWrite.req.valid) { + when(io.sramWrite.req.fire) { mem.write( io.sramWrite.req.bits.addr, io.sramWrite.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), From 17199428dbf4c5e75c37a8f0b66e86b98b255f7f Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 5 Jan 2026 13:47:44 +0800 Subject: [PATCH 042/238] [arch]fix: Fixed the bug where accpipe data was misread. --- .../memdomain/backend/accpipe/AccPipe.scala | 319 +++++++++++------- 1 file changed, 195 insertions(+), 124 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 2bbeced6..62ec9fb2 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -2,27 +2,36 @@ package framework.memdomain.backend.accpipe import chisel3._ import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} -import chisel3.experimental.hierarchy.{instantiable, public} /** * AccPipe: Accumulator Pipeline - * Handles read-modify-write operations for accumulation - * Separated from SramBank for flexibility + * - Direct write (wmode=0): write.req -> bank write -> forward resp + * - Accum write (wmode=1): bank read -> (old + new with mask) -> bank write -> forward resp + * - Read: bank read -> forward resp + * + * This version: + * - Uses correct IO directions based on your SramReadIO/SramWriteIO definitions + * - Uses strict Decoupled handshakes + * - Latches op type/address/data/mask + * - Latches old_data on read resp fire (no cross-state resp.bits usage) */ @instantiable class AccPipe(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Interface to SramBank - AccPipe sends requests to bank (sender perspective) - val sramRead = Flipped(new SramReadIO(b)) - val sramWrite = Flipped(new SramWriteIO(b)) + // Interface to SramBank + // Your SramReadIO/SramWriteIO are SLAVE-shaped (req is Flipped), so master must Flipped(...) + val sramRead = Flipped(new SramReadIO(b)) // AccPipe -> bank: req out, resp in + val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in - // Interface from midend - AccPipe receives requests (receiver perspective) - val read = new SramReadIO(b) - val write = new SramWriteIO(b) + // Interface from midend (AccPipe is slave) + val read = new SramReadIO(b) // midend -> AccPipe: req in, resp out + val write = new SramWriteIO(b) // midend -> AccPipe: req in, resp out // Control and status signals val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) @@ -30,136 +39,198 @@ class AccPipe(val b: GlobalConfig) extends Module { val busy = Output(Bool()) }) - // Internal registers - val current_bank_id = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - val busy = Reg(Bool()) - - // Connect to outputs - io.current_bank_id := current_bank_id - io.busy := busy - - // State machine for read-modify-write - val s_idle :: s_read :: s_accumulate :: s_write :: Nil = Enum(4) - val state = RegInit(s_idle) - - // Update current_bank_id and busy signal - when(state === s_idle) { - when(io.write.req.valid) { - current_bank_id := io.bank_id - busy := true.B - }.elsewhen(io.read.req.valid) { - current_bank_id := io.bank_id - busy := true.B - }.otherwise { - busy := false.B + // --------------------------------------------------------------------------- + // Latched transaction context + // --------------------------------------------------------------------------- + val curBankId = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + io.current_bank_id := curBankId + + val opIsRead = RegInit(false.B) // true: read transaction; false: write transaction + val opIsAccum = RegInit(false.B) // true only for write + wmode=1 + + val latAddr = RegInit(0.U(log2Ceil(b.memDomain.bankEntries).W)) + val latData = RegInit(0.U(b.memDomain.bankWidth.W)) + val latMask = RegInit(VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B))) + + val oldData = RegInit(0.U(b.memDomain.bankWidth.W)) + val resData = RegInit(0.U(b.memDomain.bankWidth.W)) + + // --------------------------------------------------------------------------- + // FSM + // --------------------------------------------------------------------------- + val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = + Enum(5) + val state = RegInit(s_idle) + + io.busy := (state =/= s_idle) + + // --------------------------------------------------------------------------- + // Defaults (avoid multi-drive) + // --------------------------------------------------------------------------- + // Midend side defaults + io.read.req.ready := false.B + io.read.resp.valid := false.B + io.read.resp.bits.data := 0.U + + io.write.req.ready := false.B + io.write.resp.valid := false.B + io.write.resp.bits.ok := false.B + + // Bank side defaults + io.sramRead.req.valid := false.B + io.sramRead.req.bits.addr := 0.U + io.sramRead.resp.ready := false.B + + io.sramWrite.req.valid := false.B + io.sramWrite.req.bits.addr := 0.U + io.sramWrite.req.bits.data := 0.U + io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + io.sramWrite.req.bits.wmode := false.B // IMPORTANT: write-back is a normal write + io.sramWrite.resp.ready := false.B + + // --------------------------------------------------------------------------- + // Helpers: masked accumulate (segment-wise) + // --------------------------------------------------------------------------- + private def maskedAccumulate(oldU: UInt, addU: UInt, maskV: Vec[Bool]): UInt = { + val segW = b.memDomain.bankWidth / b.memDomain.bankMaskLen + // Optional safety: if not divisible, elaboration will still succeed but behavior is wrong. + // You can assert if you want: + // require(b.memDomain.bankWidth % b.memDomain.bankMaskLen == 0, "bankWidth must be divisible by bankMaskLen") + + val oldVec = oldU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) + val addVec = addU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) + + val resVec = Wire(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) + for (i <- 0 until b.memDomain.bankMaskLen) { + resVec(i) := Mux(maskV(i), oldVec(i) + addVec(i), oldVec(i)) } - }.otherwise { - busy := true.B + resVec.asUInt } - // Pipeline registers - val acc_addr = RegInit(0.U(log2Ceil(b.memDomain.bankEntries).W)) - val acc_data = RegInit(0.U(b.memDomain.bankWidth.W)) - val acc_mask = RegInit(VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B))) - - // Default values for all outputs - io.write.req.ready := false.B - io.write.resp.valid := false.B - io.write.resp.bits.ok := false.B - - io.read.req.ready := false.B - io.read.resp.valid := false.B - io.read.resp.bits.data := 0.U - - io.sramWrite.req.valid := false.B - io.sramWrite.req.bits := 0.U.asTypeOf(io.sramWrite.req.bits) - io.sramWrite.resp.ready := false.B - - io.sramRead.req.valid := false.B - io.sramRead.req.bits.addr := 0.U - io.sramRead.resp.ready := false.B - - io.current_bank_id := 0.U - io.busy := false.B - - // State machine logic - when(state === s_idle) { - when(io.write.req.valid) { - // Direct write mode: pass through - when(!io.write.req.bits.wmode) { - io.sramWrite.req.valid := io.write.req.valid - io.sramWrite.req.bits.addr := io.write.req.bits.addr - io.sramWrite.req.bits.data := io.write.req.bits.data - io.sramWrite.req.bits.mask := io.write.req.bits.mask - io.write.req.ready := io.sramWrite.req.ready - - // Forward write response from bank - io.write.resp.valid := io.sramWrite.resp.valid - io.write.resp.bits.ok := io.sramWrite.resp.bits.ok - io.sramWrite.resp.ready := io.write.resp.ready - - when(io.write.req.fire) { - state := s_idle - busy := false.B + // --------------------------------------------------------------------------- + // FSM behavior + // --------------------------------------------------------------------------- + switch(state) { + is(s_idle) { + // Simple priority: write first, then read + // Only accept a request if we can immediately issue the corresponding bank req (bind ready to downstream ready). + when(io.write.req.valid) { + val isAccumW = io.write.req.bits.wmode + + when(isAccumW) { + // Need bank read req to start RMW + io.write.req.ready := io.sramRead.req.ready + when(io.write.req.fire) { + curBankId := io.bank_id + opIsRead := false.B + opIsAccum := true.B + latAddr := io.write.req.bits.addr + latData := io.write.req.bits.data + latMask := io.write.req.bits.mask + + // Issue bank read in same cycle (since fire implies sramRead.req.ready) + io.sramRead.req.valid := true.B + io.sramRead.req.bits.addr := io.write.req.bits.addr + + state := s_wait_read_resp + } + }.otherwise { + // Direct write: issue bank write req + io.write.req.ready := io.sramWrite.req.ready + when(io.write.req.fire) { + curBankId := io.bank_id + opIsRead := false.B + opIsAccum := false.B + latAddr := io.write.req.bits.addr + latData := io.write.req.bits.data + latMask := io.write.req.bits.mask + + io.sramWrite.req.valid := true.B + io.sramWrite.req.bits.addr := io.write.req.bits.addr + io.sramWrite.req.bits.data := io.write.req.bits.data + io.sramWrite.req.bits.mask := io.write.req.bits.mask + io.sramWrite.req.bits.wmode := false.B // direct write to bank + + state := s_wait_direct_write_resp + } + } + }.elsewhen(io.read.req.valid) { + // Read: issue bank read req + io.read.req.ready := io.sramRead.req.ready + when(io.read.req.fire) { + curBankId := io.bank_id + opIsRead := true.B + opIsAccum := false.B + latAddr := io.read.req.bits.addr + + io.sramRead.req.valid := true.B + io.sramRead.req.bits.addr := io.read.req.bits.addr + + state := s_wait_read_resp } - }.otherwise { - // Accumulator mode: start read-modify-write - io.sramRead.req.valid := true.B - io.sramRead.req.bits.addr := io.write.req.bits.addr - io.write.req.ready := io.sramRead.req.ready - acc_addr := io.write.req.bits.addr - acc_data := io.write.req.bits.data - acc_mask := io.write.req.bits.mask - state := s_read } - }.elsewhen(io.read.req.valid) { - // Pure read operation (not accumulation) - io.sramRead.req.valid := io.read.req.valid - io.sramRead.req.bits.addr := io.read.req.bits.addr - io.read.req.ready := io.sramRead.req.ready - state := s_read } - }.elsewhen(state === s_read) { - // Wait for read response - when(io.sramRead.resp.valid) { - // If we got here from a write request, it's accumulation - // If we got here from a read request, it's a pure read - when(io.read.req.valid) { - // Pure read: pass data back immediately + + is(s_wait_read_resp) { + when(opIsRead) { + // Pure read: directly forward bank resp -> midend resp with proper handshake io.read.resp.valid := io.sramRead.resp.valid io.read.resp.bits.data := io.sramRead.resp.bits.data io.sramRead.resp.ready := io.read.resp.ready - when(io.read.resp.ready) { + when(io.sramRead.resp.fire) { state := s_idle - busy := false.B + } + }.elsewhen(opIsAccum) { + // Accum path: always accept the bank resp (store old data), no dependency on midend ready here + io.sramRead.resp.ready := true.B + when(io.sramRead.resp.fire) { + oldData := io.sramRead.resp.bits.data + // Compute result right away and latch + resData := maskedAccumulate(io.sramRead.resp.bits.data, latData, latMask) + state := s_issue_write_back } }.otherwise { - // Accumulation: proceed to accumulate - state := s_accumulate + // Should not happen + state := s_idle } } - }.elsewhen(state === s_accumulate) { - // Accumulate: old_data + new_data - val new_data = io.sramRead.resp.bits.data + acc_data - acc_data := new_data - - state := s_write - }.elsewhen(state === s_write) { - // Write back accumulated result - io.sramWrite.req.valid := true.B - io.sramWrite.req.bits.addr := acc_addr - io.sramWrite.req.bits.data := acc_data - io.sramWrite.req.bits.mask := acc_mask - - // Forward write response from bank - io.write.resp.valid := io.sramWrite.resp.valid - io.write.resp.bits.ok := io.sramWrite.resp.bits.ok - io.sramWrite.resp.ready := io.write.resp.ready - - when(io.sramWrite.req.fire) { - state := s_idle - busy := false.B + + is(s_issue_write_back) { + // Issue bank write-back for accumulated result + io.sramWrite.req.valid := true.B + io.sramWrite.req.bits.addr := latAddr + io.sramWrite.req.bits.data := resData + io.sramWrite.req.bits.mask := latMask + io.sramWrite.req.bits.wmode := false.B // IMPORTANT: already accumulated in AccPipe + + when(io.sramWrite.req.fire) { + state := s_wait_write_resp + } + } + + is(s_wait_write_resp) { + // Forward bank write resp to midend write resp + io.write.resp.valid := io.sramWrite.resp.valid + io.write.resp.bits.ok := io.sramWrite.resp.bits.ok + io.sramWrite.resp.ready := io.write.resp.ready + + when(io.sramWrite.resp.fire) { + // Done + opIsAccum := false.B + state := s_idle + } + } + + is(s_wait_direct_write_resp) { + // Direct write: forward resp + io.write.resp.valid := io.sramWrite.resp.valid + io.write.resp.bits.ok := io.sramWrite.resp.bits.ok + io.sramWrite.resp.ready := io.write.resp.ready + + when(io.sramWrite.resp.fire) { + state := s_idle + } } } } From ab16d6313695adcb7f166bd2577a02710165988d Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 5 Jan 2026 15:09:15 +0800 Subject: [PATCH 043/238] [arch]fix:Fixed bugs in the memdomain backend and strictly controlled conflict issues. --- .../memdomain/backend/MemBackend.scala | 246 +++++++++++------- .../memdomain/backend/accpipe/AccPipe.scala | 8 +- 2 files changed, 159 insertions(+), 95 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 5df4efb9..2fb44ebc 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -2,25 +2,26 @@ package framework.memdomain.backend import chisel3._ import chisel3.util._ -import framework.top.GlobalConfig import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} + +import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} import framework.memdomain.backend.accpipe.AccPipe /** * MemBackend: Backend memory manager - * Manages the physical memory resources (Scratchpad + Accumulator Banks) * - * Features: - * - Instantiates bankNum SRAM banks and bankChannel AccPipes - * - Supports up to bankChannel concurrent bank accesses per cycle - * - All requests go through AccPipe, which handles both direct write mode and accumulator mode (read-modify-write) - * - Assert checks ensure no bank_id conflicts in the same cycle + * Key changes vs your version: + * 1) Fix MemRequestIO.bank_id direction (should be Input) + * 2) Remove illegal "accPipes.foreach init sram*" multi-driving + * 3) Routing does NOT depend on accPipe.busy (idle same-cycle issue) + * 4) Use accPipe.io.target_bank_id for same-cycle routing + * 5) Add cross read/write conflict assertions based on actual bank requests (valid-level, and fire-level optional) */ class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // Sender perspective: send write requests - val read = Flipped(new SramReadIO(b)) // Sender perspective: send read requests - val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output, should be Input } @instantiable @@ -28,7 +29,6 @@ class MemBackend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Interface from midend - MemManager routes requests to AccPipes val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) }) @@ -36,106 +36,166 @@ class MemBackend(val b: GlobalConfig) extends Module { val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) // ----------------------------------------------------------------------------- - // Request routing: All requests go through AccPipe + // Midend -> AccPipe // ----------------------------------------------------------------------------- - // Route all requests to AccPipe (AccPipe handles both wmode and read operations) for (i <- 0 until b.memDomain.bankChannel) { - accPipes(i).io.write <> io.mem_req(i).write - accPipes(i).io.read <> io.mem_req(i).read + accPipes(i).io.write <> io.mem_req(i).write + accPipes(i).io.read <> io.mem_req(i).read accPipes(i).io.bank_id := io.mem_req(i).bank_id } // ----------------------------------------------------------------------------- - // Bank conflict detection + // Create "return path" wires for each AccPipe (bank -> accPipe) + // We drive these wires exactly once in routing logic to avoid multi-drive. + // ----------------------------------------------------------------------------- + val rd_req_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) + val rd_resp_valid = Wire(Vec(b.memDomain.bankChannel, Bool())) + val rd_resp_data = Wire(Vec(b.memDomain.bankChannel, UInt(b.memDomain.bankWidth.W))) + val rd_resp_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) // accPipe -> bank + + val wr_req_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) + val wr_resp_valid = Wire(Vec(b.memDomain.bankChannel, Bool())) + val wr_resp_ok = Wire(Vec(b.memDomain.bankChannel, Bool())) + val wr_resp_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) // accPipe -> bank + + // Defaults: if a pipe is not selected by any bank this cycle, it sees "not ready / no response" + for (i <- 0 until b.memDomain.bankChannel) { + rd_req_ready(i) := false.B + rd_resp_valid(i) := false.B + rd_resp_data(i) := 0.U + wr_req_ready(i) := false.B + wr_resp_valid(i) := false.B + wr_resp_ok(i) := false.B + + // connect accPipe outputs that go to bank + rd_resp_ready(i) := accPipes(i).io.sramRead.resp.ready + wr_resp_ready(i) := accPipes(i).io.sramWrite.resp.ready + + // drive accPipe inputs from routing wires + accPipes(i).io.sramRead.req.ready := rd_req_ready(i) + accPipes(i).io.sramRead.resp.valid := rd_resp_valid(i) + accPipes(i).io.sramRead.resp.bits.data := rd_resp_data(i) + + accPipes(i).io.sramWrite.req.ready := wr_req_ready(i) + accPipes(i).io.sramWrite.resp.valid := wr_resp_valid(i) + accPipes(i).io.sramWrite.resp.bits.ok := wr_resp_ok(i) + } + + // ----------------------------------------------------------------------------- + // Conflict detection (better than original) + // 1) valid-level: if two pipes TRY to access same bank same cycle, assert + // 2) also add read-vs-write cross conflict + // NOTE: if you want fire-level only, see the optional section below. // ----------------------------------------------------------------------------- - // Check for bank_id conflicts across all requests (all go through AccPipe) for (i <- 0 until b.memDomain.bankChannel) { for (j <- (i + 1) until b.memDomain.bankChannel) { - // Check write conflicts - when(io.mem_req(i).write.req.valid && io.mem_req(j).write.req.valid) { - assert( - io.mem_req(i).bank_id =/= io.mem_req(j).bank_id, - s"[MemManager]: Write Bank ID conflict between request $i and $j" - ) + val wi = accPipes(i).io.sramWrite.req.valid + val wj = accPipes(j).io.sramWrite.req.valid + val ri = accPipes(i).io.sramRead.req.valid + val rj = accPipes(j).io.sramRead.req.valid + + val bi = accPipes(i).io.target_bank_id + val bj = accPipes(j).io.target_bank_id + + when(wi && wj) { + assert(bi =/= bj, s"[MemBackend] WRITE bank conflict between pipe $i and $j") + } + when(ri && rj) { + assert(bi =/= bj, s"[MemBackend] READ bank conflict between pipe $i and $j") } - // Check read conflicts - when(io.mem_req(i).read.req.valid && io.mem_req(j).read.req.valid) { - assert( - io.mem_req(i).bank_id =/= io.mem_req(j).bank_id, - s"[MemManager]: Read Bank ID conflict between request $i and $j" - ) + when(wi && rj) { + assert(bi =/= bj, s"[MemBackend] WRITE($i) vs READ($j) bank conflict") + } + when(ri && wj) { + assert(bi =/= bj, s"[MemBackend] READ($i) vs WRITE($j) bank conflict") } } } // ----------------------------------------------------------------------------- - // Initialize all AccPipe sram interfaces to default values + // Bank routing + // For each bank: + // - select at most one write requester (Mux1H) + // - select at most one read requester (Mux1H) + // - connect bank <-> selected accPipe using the per-pipe wires // ----------------------------------------------------------------------------- - accPipes.foreach { accPipe => - accPipe.io.sramWrite.req.ready := false.B - accPipe.io.sramWrite.resp.valid := false.B - accPipe.io.sramWrite.resp.bits.ok := false.B - - accPipe.io.sramRead.req.ready := false.B - accPipe.io.sramRead.resp.valid := false.B - accPipe.io.sramRead.resp.bits.data := 0.U + banks.zipWithIndex.foreach { case (bank, bankIdx) => + val bankId = bankIdx.U(log2Up(b.memDomain.bankNum).W) + + // ------------------------- + // WRITE routing + // ------------------------- + val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) + for (i <- 0 until b.memDomain.bankChannel) { + wMatch(i) := accPipes(i).io.sramWrite.req.valid && (accPipes(i).io.target_bank_id === bankId) + } + val wHas = wMatch.asUInt.orR + // stronger safety: at most 1 + assert(PopCount(wMatch) <= 1.U, s"[MemBackend] More than one WRITE match to bank $bankIdx") + + when(wHas) { + val selIdx = OHToUInt(wMatch) + // bank gets req from selected pipe + bank.io.sramWrite.req.valid := accPipes(selIdx).io.sramWrite.req.valid + bank.io.sramWrite.req.bits := accPipes(selIdx).io.sramWrite.req.bits + // selected pipe sees ready from bank + wr_req_ready(selIdx) := bank.io.sramWrite.req.ready + + // response path: selected pipe sees bank resp + wr_resp_valid(selIdx) := bank.io.sramWrite.resp.valid + wr_resp_ok(selIdx) := bank.io.sramWrite.resp.bits.ok + // bank sees ready from selected pipe + bank.io.sramWrite.resp.ready := wr_resp_ready(selIdx) + }.otherwise { + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) + bank.io.sramWrite.resp.ready := false.B + } + + // ------------------------- + // READ routing + // ------------------------- + val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) + for (i <- 0 until b.memDomain.bankChannel) { + rMatch(i) := accPipes(i).io.sramRead.req.valid && (accPipes(i).io.target_bank_id === bankId) + } + val rHas = rMatch.asUInt.orR + assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") + + when(rHas) { + val selIdx = OHToUInt(rMatch) + // bank gets req from selected pipe + bank.io.sramRead.req.valid := accPipes(selIdx).io.sramRead.req.valid + bank.io.sramRead.req.bits := accPipes(selIdx).io.sramRead.req.bits + // selected pipe sees ready from bank + rd_req_ready(selIdx) := bank.io.sramRead.req.ready + + // response path: selected pipe sees bank resp + rd_resp_valid(selIdx) := bank.io.sramRead.resp.valid + rd_resp_data(selIdx) := bank.io.sramRead.resp.bits.data + // bank sees ready from selected pipe + bank.io.sramRead.resp.ready := rd_resp_ready(selIdx) + }.otherwise { + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) + bank.io.sramRead.resp.ready := false.B + } } // ----------------------------------------------------------------------------- - // Bank routing and connection + // Optional: fire-level conflict assertions (stricter semantics) + // Enable if you prefer conflicts only when both actually handshake. // ----------------------------------------------------------------------------- - // Each bank connects to the AccPipe whose current_bank_id matches this bank's ID - // Since we have conflict detection, each bank can have at most one request per cycle - banks.zipWithIndex.foreach { - case (bank, bankIdx) => - val bank_id = bankIdx.U - - // Aggregate write requests from all AccPipes for this bank - val writeMatches = VecInit(accPipes.map { accPipe => - accPipe.io.sramWrite.req.valid && accPipe.io.busy && (accPipe.io.current_bank_id === bank_id) - }) - val hasWriteReq = writeMatches.asUInt.orR - - // Connect write - only one AccPipe can match per bank per cycle (conflict detection ensures this) - when(hasWriteReq) { - val matchedAccPipe = Mux1H(writeMatches.zip(accPipes).map { - case (isMatch, accPipe) => - isMatch -> accPipe.io.sramWrite - }) - bank.io.sramWrite.req.valid := matchedAccPipe.req.valid - bank.io.sramWrite.req.bits := matchedAccPipe.req.bits - matchedAccPipe.req.ready := bank.io.sramWrite.req.ready - matchedAccPipe.resp.valid := bank.io.sramWrite.resp.valid - matchedAccPipe.resp.bits := bank.io.sramWrite.resp.bits - bank.io.sramWrite.resp.ready := matchedAccPipe.resp.ready - }.otherwise { - bank.io.sramWrite.req.valid := false.B - bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) - bank.io.sramWrite.resp.ready := false.B - } - - // Aggregate read requests from all AccPipes for this bank - val readMatches = VecInit(accPipes.map { accPipe => - accPipe.io.sramRead.req.valid && accPipe.io.busy && (accPipe.io.current_bank_id === bank_id) - }) - val hasReadReq = readMatches.asUInt.orR - - // Connect read - only one AccPipe can match per bank per cycle - when(hasReadReq) { - val matchedAccPipe = Mux1H(readMatches.zip(accPipes).map { - case (isMatch, accPipe) => - isMatch -> accPipe.io.sramRead - }) - bank.io.sramRead.req.valid := matchedAccPipe.req.valid - bank.io.sramRead.req.bits := matchedAccPipe.req.bits - matchedAccPipe.req.ready := bank.io.sramRead.req.ready - matchedAccPipe.resp.valid := bank.io.sramRead.resp.valid - matchedAccPipe.resp.bits := bank.io.sramRead.resp.bits - bank.io.sramRead.resp.ready := matchedAccPipe.resp.ready - }.otherwise { - bank.io.sramRead.req.valid := false.B - bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) - bank.io.sramRead.resp.ready := false.B - } - } + // val wrFire = VecInit(accPipes.map(_.io.sramWrite.req.fire)) + // val rdFire = VecInit(accPipes.map(_.io.sramRead.req.fire)) + // for (i <- 0 until b.memDomain.bankChannel) { + // for (j <- (i + 1) until b.memDomain.bankChannel) { + // val bi = accPipes(i).io.target_bank_id + // val bj = accPipes(j).io.target_bank_id + // when(wrFire(i) && wrFire(j)) { assert(bi =/= bj) } + // when(rdFire(i) && rdFire(j)) { assert(bi =/= bj) } + // when(wrFire(i) && rdFire(j)) { assert(bi =/= bj) } + // when(rdFire(i) && wrFire(j)) { assert(bi =/= bj) } + // } + // } } diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 62ec9fb2..cebafd2a 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -35,7 +35,9 @@ class AccPipe(val b: GlobalConfig) extends Module { // Control and status signals val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) - val current_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + // in AccPipe IO bundle, add: + val target_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val busy = Output(Bool()) }) @@ -43,7 +45,9 @@ class AccPipe(val b: GlobalConfig) extends Module { // Latched transaction context // --------------------------------------------------------------------------- val curBankId = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - io.current_bank_id := curBankId + // target bank id for routing (combinational) + io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) + val opIsRead = RegInit(false.B) // true: read transaction; false: write transaction val opIsAccum = RegInit(false.B) // true only for write + wmode=1 From 9d7d9a2325a5edb51083d0a19f94ae5b0c198b4d Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 5 Jan 2026 19:00:47 +0800 Subject: [PATCH 044/238] Revert "[arch] fix: fix some bugs of the dead lock of channel module" This reverts commit 7f6ee9d012388b375d4d85358be6cd964df391a1. --- .../examples/toy/balldomain/BallDomain.scala | 4 +- .../top/channels/ChannelCluster.scala | 43 ++++++------------- .../framework/top/channels/headerBuffer.scala | 5 +-- 3 files changed, 16 insertions(+), 36 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index c7afd095..d07d4fbd 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -30,10 +30,10 @@ class BallDomain(val b: GlobalConfig) extends Module { val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) @public - val ballMemChannel = IO(Flipped(new ChannelClusterIO(b))) + val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, memChannel))) @public - val memBallChannel = IO(Flipped(new ChannelClusterIO(b))) + val memBallChannel = IO(Flipped(new ChannelClusterIO(b, b.top.memBallChannelNum))) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) diff --git a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala index 573deac4..9143781d 100644 --- a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala +++ b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala @@ -6,22 +6,22 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.top.GlobalConfig import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} -class ChannelClusterIO(val b: GlobalConfig) extends Bundle { - val channelIn = Vec(b.top.ballMemChannelNum, Flipped(new ChannelIO(b))) - val channelOut = Vec(b.top.ballMemChannelNum, new ChannelIO(b)) +class ChannelClusterIO(val b: GlobalConfig, numChannels: Int) extends Bundle { + val channelIn = Vec(numChannels, Flipped(new ChannelIO(b))) + val channelOut = Vec(numChannels, new ChannelIO(b)) val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) val freeChannelResp = Decoupled(new FreeChannelResp(b)) } @instantiable -class ChannelCluster(val b: GlobalConfig) extends Module { +class ChannelCluster(val b: GlobalConfig, numChannels: Int) extends Module { @public - val io = IO(new ChannelClusterIO(b)) + val io = IO(new ChannelClusterIO(b, numChannels)) - val channels = (0 until b.top.ballMemChannelNum).map(_ => Instantiate(new Channel(b))) + val channels = (0 until numChannels).map(_ => Instantiate(new Channel(b))) // Connect channels - for (i <- 0 until b.top.ballMemChannelNum) { + for (i <- 0 until numChannels) { channels(i).io.in <> io.channelIn(i) channels(i).io.out <> io.channelOut(i) channels(i).io.peakChannelReq.valid := io.peakChannelReq.valid @@ -33,42 +33,23 @@ class ChannelCluster(val b: GlobalConfig) extends Module { val freeChannelCount = PopCount(freeChannels) val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num - val selectedChannelIds = Wire(Vec(b.top.ballMemChannelNum, UInt(log2Up(b.top.ballMemChannelNum).W))) - val selectedMask = Wire(Vec(b.top.ballMemChannelNum, Bool())) + val selectedChannelIds = Wire(Vec(numChannels, UInt(log2Up(numChannels).W))) + val selectedMask = Wire(Vec(numChannels, Bool())) - val masks = Wire(Vec(b.top.ballMemChannelNum + 1, Vec(b.top.ballMemChannelNum, Bool()))) + val masks = Wire(Vec(numChannels + 1, Vec(numChannels, Bool()))) masks(0) := freeChannels - for (i <- 0 until b.top.ballMemChannelNum) { + for (i <- 0 until numChannels) { val maskVec = masks(i) val selOH = PriorityEncoderOH(maskVec.asUInt) val selIdx = PriorityEncoder(maskVec.asUInt) selectedMask(i) := maskVec.asUInt.orR && (i.U < io.peakChannelReq.bits.needed_channel_num) selectedChannelIds(i) := Mux(selectedMask(i), selIdx, 0.U) - if (i < b.top.ballMemChannelNum) { + if (i < numChannels) { masks(i + 1) := VecInit(maskVec.zip(selOH.asBools).map { case (free, sel) => free && !sel }) } } - // ----------------------------- - // Convert selectedChannelIds to "whether each channel is selected". - // ----------------------------- - val selectedPerChan = Wire(Vec(b.top.ballMemChannelNum, Bool())) - for (ch <- 0 until b.top.ballMemChannelNum) { - // If the ch appears in the list of selected ids (and the slot is valid), it is considered selected. - selectedPerChan(ch) := (0 until b.top.ballMemChannelNum).map { k => - selectedMask(k) && (selectedChannelIds(k) === ch.U) - }.reduce(_ || _) - } - - // Allocation is only truly "distributed" when the upstream handshake is successful and sufficient resources are available. - val doAlloc = io.peakChannelReq.valid && io.freeChannelResp.ready && hasEnoughChannels - -// Only raise the valid flag for the selected channel to avoid locking all channels simultaneously by firing. - for (i <- 0 until b.top.ballMemChannelNum) { - channels(i).io.peakChannelReq.valid := doAlloc && selectedPerChan(i) - } - io.freeChannelResp.valid := io.peakChannelReq.valid io.freeChannelResp.bits.is_free := hasEnoughChannels io.freeChannelResp.bits.channel_ids := selectedChannelIds diff --git a/arch/src/main/scala/framework/top/channels/headerBuffer.scala b/arch/src/main/scala/framework/top/channels/headerBuffer.scala index 236cf261..ee06c505 100644 --- a/arch/src/main/scala/framework/top/channels/headerBuffer.scala +++ b/arch/src/main/scala/framework/top/channels/headerBuffer.scala @@ -20,11 +20,10 @@ class HeaderBuffer(val b: GlobalConfig) extends Module { val set = Flipped(Decoupled(new HeaderBufferData(b))) }) - val reg = RegInit(0.U.asTypeOf(new HeaderBufferData(b))) + val reg = Reg(new HeaderBufferData(b)) io.read := reg - io.set.ready := !reg.lock || (io.set.bits.lock === false.B) - + io.set.ready := !reg.lock when(io.set.fire) { reg := io.set.bits } From 35c5a9ba3b43ee47367ec9bc885cde85cd5eb6e0 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Tue, 6 Jan 2026 00:02:14 +0800 Subject: [PATCH 045/238] [arch]Fix sone interface bugs in memrouter --- .../framework/balldomain/bbus/bbus.scala | 51 ++++--------------- .../bbus/memrouter/ReadReqGen.scala | 2 +- .../balldomain/bbus/memrouter/memRouter.scala | 49 ++++++++++-------- .../memdomain/backend/MemBackend.scala | 12 ++--- 4 files changed, 46 insertions(+), 68 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 080923fc..1217ec25 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -72,26 +72,6 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) cmdResp <> cmdRouter.io.cmdResp_o -// Initialize bankRead and bankWrite ports with default values - for (i <- 0 until memChannel) { - bankRead(i).bank_id := 0.U - bankRead(i).rob_id := 0.U - bankRead(i).ball_id := 0.U - bankRead(i).io.req.valid := false.B - bankRead(i).io.req.bits.addr := 0.U - bankRead(i).io.resp.ready := false.B - - bankWrite(i).bank_id := 0.U - bankWrite(i).rob_id := 0.U - bankWrite(i).ball_id := 0.U - bankWrite(i).io.req.valid := false.B - bankWrite(i).io.req.bits.addr := 0.U - bankWrite(i).io.req.bits.mask := 0.U.asTypeOf(Vec(b.memDomain.bankMaskLen, Bool())) - bankWrite(i).io.req.bits.data := 0.U - bankWrite(i).io.req.bits.wmode := false.B - bankWrite(i).io.resp.ready := false.B - } - // Initialize ballMemChannel and memBallChannel ports with default values for (i <- 0 until ballMemChannelNum) { ballMemChannel.channelIn(i).data.valid := false.B @@ -117,23 +97,11 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- - memoryrouter.io.bankRead_i <> bankRead - memoryrouter.io.bankWrite_i <> bankWrite + memoryrouter.io.bankRead_o <> bankRead + memoryrouter.io.bankWrite_o <> bankWrite memoryrouter.io.peakChannelReq <> ballMemChannel.peakChannelReq memoryrouter.io.freeChannelResp <> ballMemChannel.freeChannelResp - // Connect channel outputs (from channel.out in top level) to memory router - // Channels are unified, router handles routing to bankRead_o or bankWrite_o based on request type - // For now, we route to both and let router decide based on internal logic - // TODO: Router should determine read/write based on request metadata - for (i <- 0 until ballMemChannelNum) { - // Connect to both read and write outputs, router will select based on request type - memoryrouter.io.bankRead_o(i).io.req.valid := ballMemChannel.channelOut(i).data.valid - memoryrouter.io.bankRead_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits - memoryrouter.io.bankWrite_o(i).io.req.valid := ballMemChannel.channelOut(i).data.valid - memoryrouter.io.bankWrite_o(i).io.req.bits.addr := ballMemChannel.channelOut(i).data.bits - ballMemChannel.channelOut(i).data.ready := memoryrouter.io.bankRead_o(i).io.req.ready || memoryrouter.io.bankWrite_o(i).io.req.ready - } // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- @@ -144,22 +112,23 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) pmc.io.cmdResp_o(i).bits := cmdRouter.io.cmdResp_o(i).bits } -// Initialize balls' bankRead and bankWrite ports with default values +// Connect balls' bankRead and bankWrite to memrouter + var readChannelIdx = 0 + var writeChannelIdx = 0 + for (ball <- balls) { val ballConfig = b.ballDomain.ballIdMappings.find(_.ballName == ball.getClass.getSimpleName) val inBW = ballConfig.map(_.inBW).getOrElse(0) val outBW = ballConfig.map(_.outBW).getOrElse(0) for (i <- 0 until inBW) { - ball.blink.bankRead(i).io.req.ready := false.B - ball.blink.bankRead(i).io.resp.valid := false.B - ball.blink.bankRead(i).io.resp.bits.data := 0.U + memoryrouter.io.bankRead_i(readChannelIdx) <> ball.blink.bankRead(i) + readChannelIdx = readChannelIdx + 1 } for (i <- 0 until outBW) { - ball.blink.bankWrite(i).io.req.ready := false.B - ball.blink.bankWrite(i).io.resp.valid := false.B - ball.blink.bankWrite(i).io.resp.bits.ok := false.B + memoryrouter.io.bankWrite_i(writeChannelIdx) <> ball.blink.bankWrite(i) + writeChannelIdx = writeChannelIdx + 1 } } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala index 4094cc49..8dac23fc 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -23,7 +23,7 @@ class ReadReqGen(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val bank_read_i = Vec(totalReadChannels, Flipped(new BankRead(b))) + val bank_read_i = Vec(totalReadChannels, new BankRead(b)) val read_req_o = Decoupled(new ReadReq(b)) }) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 39b09b1e..af1caada 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -35,8 +35,8 @@ class MemRouter(val b: GlobalConfig) extends Module { val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) - val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) - val freeChannelResp = Decoupled(new FreeChannelResp(b)) + val peakChannelReq = Decoupled(new PeakChannelReq(b)) + val freeChannelResp = Flipped(Decoupled(new FreeChannelResp(b))) }) //--------------------------------------------------------------------------- @@ -47,19 +47,20 @@ class MemRouter(val b: GlobalConfig) extends Module { val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) // readReqGen.io.bank_read_i := io.bankRead_i for (i <- 0 until totalReadChannels) { - io.bankRead_i(i).ball_id := readReqGen.io.bank_read_i(i).ball_id - io.bankRead_i(i).rob_id := readReqGen.io.bank_read_i(i).rob_id - io.bankRead_i(i).io.req.valid := readReqGen.io.bank_read_i(i).io.req.valid - io.bankRead_i(i).io.req.bits := readReqGen.io.bank_read_i(i).io.req.bits + readReqGen.io.bank_read_i(i).ball_id := io.bankRead_i(i).ball_id + readReqGen.io.bank_read_i(i).rob_id:= io.bankRead_i(i).rob_id + readReqGen.io.bank_read_i(i).io.req.valid := io.bankRead_i(i).io.req.valid + readReqGen.io.bank_read_i(i).io.req.bits := io.bankRead_i(i).io.req.bits + io.bankRead_i(i).io.req.ready := readReqGen.io.bank_read_i(i).io.req.ready } // Step2: Peek if there are enough free channels - // val hasReadReq = readReqGen.io.read_req_o.valid - // io.peakChannelReq.valid := hasReadReq - // io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num - // io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id - // io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id - io.peakChannelReq <> readReqGen.io.read_req_o + val hasReadReq = readReqGen.io.read_req_o.valid + io.peakChannelReq.valid := hasReadReq + io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num + io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id + io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id + //io.peakChannelReq <> readReqGen.io.read_req_o // Step3/1: if there are enough free channels, accept the request val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free io.freeChannelResp.ready := true.B @@ -72,15 +73,23 @@ class MemRouter(val b: GlobalConfig) extends Module { // Step4: Set the channel mapping table when(readReqGen.io.read_req_o.fire) { - var matchedCnt = 0.U + val matchVec = VecInit((0 until totalReadChannels).map { i => + io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && + io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && + io.bankRead_i(i).io.req.valid + }) + val matchCount = PopCount(matchVec) + val channelNum = readReqGen.io.read_req_o.bits.channel_num + val dispatchCount = Mux(matchCount > channelNum, channelNum, matchCount) + for (i <- 0 until totalReadChannels) { - val isMatch = io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && - io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && io.bankRead_i(i).io.req.valid - when(isMatch && matchedCnt < readReqGen.io.read_req_o.bits.channel_num) { - channelMappingTable.io.write.valid := true.B - channelMappingTable.io.write.bits.idx := i.U - channelMappingTable.io.write.bits.outCh := dispatchChannels(matchedCnt) - matchedCnt = matchedCnt + 1.U + when(matchVec(i)) { + val priorMatchCount = PopCount(matchVec.take(i)) + when(priorMatchCount < dispatchCount) { + channelMappingTable.io.write.valid := true.B + channelMappingTable.io.write.bits.idx := i.U + channelMappingTable.io.write.bits.outCh := dispatchChannels(priorMatchCount) + } } } } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 2fb44ebc..e51e68f1 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -135,9 +135,9 @@ class MemBackend(val b: GlobalConfig) extends Module { when(wHas) { val selIdx = OHToUInt(wMatch) - // bank gets req from selected pipe - bank.io.sramWrite.req.valid := accPipes(selIdx).io.sramWrite.req.valid - bank.io.sramWrite.req.bits := accPipes(selIdx).io.sramWrite.req.bits + // bank gets req from selected pipe using Mux1H + bank.io.sramWrite.req.valid := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.valid)) + bank.io.sramWrite.req.bits := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.bits)) // selected pipe sees ready from bank wr_req_ready(selIdx) := bank.io.sramWrite.req.ready @@ -164,9 +164,9 @@ class MemBackend(val b: GlobalConfig) extends Module { when(rHas) { val selIdx = OHToUInt(rMatch) - // bank gets req from selected pipe - bank.io.sramRead.req.valid := accPipes(selIdx).io.sramRead.req.valid - bank.io.sramRead.req.bits := accPipes(selIdx).io.sramRead.req.bits + // bank gets req from selected pipe using Mux1H + bank.io.sramRead.req.valid := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.valid)) + bank.io.sramRead.req.bits := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.bits)) // selected pipe sees ready from bank rd_req_ready(selIdx) := bank.io.sramRead.req.ready From b404ad2f84316bd36c677d4b2775e7d87b41da23 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 6 Jan 2026 11:17:45 +0800 Subject: [PATCH 046/238] [arch]Fix:fix some bugs of memdomain --- .../main/scala/framework/memdomain/backend/MemBackend.scala | 3 ++- .../scala/framework/memdomain/backend/accpipe/AccPipe.scala | 4 +++- arch/src/main/scala/framework/top/channels/headerBuffer.scala | 4 ++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index e51e68f1..2c8e3d4c 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -21,9 +21,10 @@ import framework.memdomain.backend.accpipe.AccPipe class MemRequestIO(b: GlobalConfig) extends Bundle { val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output, should be Input + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output } + @instantiable class MemBackend(val b: GlobalConfig) extends Module { diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index cebafd2a..f320f601 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -46,7 +46,7 @@ class AccPipe(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- val curBankId = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) // target bank id for routing (combinational) - io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) + val opIsRead = RegInit(false.B) // true: read transaction; false: write transaction @@ -65,6 +65,8 @@ class AccPipe(val b: GlobalConfig) extends Module { val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = Enum(5) val state = RegInit(s_idle) + + io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) io.busy := (state =/= s_idle) diff --git a/arch/src/main/scala/framework/top/channels/headerBuffer.scala b/arch/src/main/scala/framework/top/channels/headerBuffer.scala index ee06c505..f6a90de7 100644 --- a/arch/src/main/scala/framework/top/channels/headerBuffer.scala +++ b/arch/src/main/scala/framework/top/channels/headerBuffer.scala @@ -20,10 +20,10 @@ class HeaderBuffer(val b: GlobalConfig) extends Module { val set = Flipped(Decoupled(new HeaderBufferData(b))) }) - val reg = Reg(new HeaderBufferData(b)) + val reg = RegInit(0.U.asTypeOf(new HeaderBufferData(b))) io.read := reg - io.set.ready := !reg.lock + io.set.ready := !reg.lock || (io.set.bits.lock === false.B) when(io.set.fire) { reg := io.set.bits } From 8dd289d6a3ff3ec98a6c4aa5cbd9921ef9c40bc6 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Tue, 6 Jan 2026 14:45:43 +0800 Subject: [PATCH 047/238] [arch]Fix interface initialazaiton bugs in memrouter --- .../bbus/memrouter/ReadReqGen.scala | 6 +++ .../balldomain/bbus/memrouter/memRouter.scala | 46 +++++++++++++++---- 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala index 8dac23fc..31427e9a 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -69,6 +69,12 @@ class ReadReqGen(val b: GlobalConfig) extends Module { arb.io.in(i).bits.rob_id := reqGroupsWithRobId(i)._5 } + for(i <- 0 until totalReadChannels) { + io.bank_read_i(i).io.req.ready := true.B + io.bank_read_i(i).io.resp.valid := false.B + io.bank_read_i(i).io.resp.bits := DontCare + } + io.read_req_o.valid := arb.io.out.valid io.read_req_o.bits.bank_id := arb.io.out.bits.bank_id io.read_req_o.bits.ball_id := arb.io.out.bits.ball_id diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index af1caada..f6eb8d0c 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -45,13 +45,10 @@ class MemRouter(val b: GlobalConfig) extends Module { // Step1: Generate read request val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) - // readReqGen.io.bank_read_i := io.bankRead_i + for (i <- 0 until totalReadChannels) { - readReqGen.io.bank_read_i(i).ball_id := io.bankRead_i(i).ball_id - readReqGen.io.bank_read_i(i).rob_id:= io.bankRead_i(i).rob_id - readReqGen.io.bank_read_i(i).io.req.valid := io.bankRead_i(i).io.req.valid - readReqGen.io.bank_read_i(i).io.req.bits := io.bankRead_i(i).io.req.bits - io.bankRead_i(i).io.req.ready := readReqGen.io.bank_read_i(i).io.req.ready + // Connect input fields from io.bankRead_i to readReqGen.io.bank_read_i + readReqGen.io.bank_read_i(i) <> io.bankRead_i(i) } // Step2: Peek if there are enough free channels @@ -93,14 +90,43 @@ class MemRouter(val b: GlobalConfig) extends Module { } } } + for (i <- 0 until bbusProducerChannels) { + io.bankRead_o(i).io.req.valid := false.B + io.bankRead_o(i).io.resp.ready := true.B + io.bankRead_o(i).io.req.bits := DontCare + io.bankRead_o(i).bank_id := DontCare + io.bankRead_o(i).ball_id := DontCare + io.bankRead_o(i).rob_id := DontCare + io.bankWrite_o(i).io.req.valid := false.B + io.bankWrite_o(i).io.resp.ready := true.B + io.bankWrite_o(i).io.req.bits := DontCare + io.bankWrite_o(i).bank_id := DontCare + io.bankWrite_o(i).ball_id := DontCare + io.bankWrite_o(i).rob_id := DontCare + } + io.bankWrite_i.map(_.io.req.ready := true.B) + io.bankWrite_i.map(_.io.resp.valid := false.B) + io.bankWrite_i.map(_.io.resp.bits := DontCare) + io.bankRead_i.map(_.io.req.ready := true.B) + io.bankRead_i.map(_.io.resp.valid := false.B) + io.bankRead_i.map(_.io.resp.bits := DontCare) + // Step5: Dispatch the request to the channels for (i <- 0 until totalReadChannels) { when(channelMappingTable.io.routeValid(i)) { val outCh = channelMappingTable.io.routeMap(i) + /* io.bankRead_o(outCh).io.req <> io.bankRead_i(i).io.req - }.otherwise { - io.bankRead_i(i).io.req.ready := false.B - // io.bankRead_i(i).io.req.bits := DontCare + io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id + io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id + io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id + io.bankWrite_o(outCh).io.req <> io.bankWrite_i(i).io.req + io.bankWrite_o(outCh).bank_id := io.bankWrite_i(i).bank_id + io.bankWrite_o(outCh).ball_id := io.bankWrite_i(i).ball_id + io.bankWrite_o(outCh).rob_id := io.bankWrite_i(i).rob_id + */ + io.bankRead_o(outCh) <> io.bankRead_i(i) + io.bankWrite_o(outCh) <> io.bankWrite_i(i) } } -} +} \ No newline at end of file From 8e3abab9569c5a5a478eddbcd9bd4cea09c40ec9 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 6 Jan 2026 15:07:07 +0800 Subject: [PATCH 048/238] [arch]fix:fix the circle of combination bug of accpipe --- .../memdomain/backend/accpipe/AccPipe.scala | 104 ++++++++---------- 1 file changed, 48 insertions(+), 56 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index f320f601..ee494665 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -118,62 +118,54 @@ class AccPipe(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- switch(state) { is(s_idle) { - // Simple priority: write first, then read - // Only accept a request if we can immediately issue the corresponding bank req (bind ready to downstream ready). - when(io.write.req.valid) { - val isAccumW = io.write.req.bits.wmode - - when(isAccumW) { - // Need bank read req to start RMW - io.write.req.ready := io.sramRead.req.ready - when(io.write.req.fire) { - curBankId := io.bank_id - opIsRead := false.B - opIsAccum := true.B - latAddr := io.write.req.bits.addr - latData := io.write.req.bits.data - latMask := io.write.req.bits.mask - - // Issue bank read in same cycle (since fire implies sramRead.req.ready) - io.sramRead.req.valid := true.B - io.sramRead.req.bits.addr := io.write.req.bits.addr - - state := s_wait_read_resp - } - }.otherwise { - // Direct write: issue bank write req - io.write.req.ready := io.sramWrite.req.ready - when(io.write.req.fire) { - curBankId := io.bank_id - opIsRead := false.B - opIsAccum := false.B - latAddr := io.write.req.bits.addr - latData := io.write.req.bits.data - latMask := io.write.req.bits.mask - - io.sramWrite.req.valid := true.B - io.sramWrite.req.bits.addr := io.write.req.bits.addr - io.sramWrite.req.bits.data := io.write.req.bits.data - io.sramWrite.req.bits.mask := io.write.req.bits.mask - io.sramWrite.req.bits.wmode := false.B // direct write to bank - - state := s_wait_direct_write_resp - } - } - }.elsewhen(io.read.req.valid) { - // Read: issue bank read req - io.read.req.ready := io.sramRead.req.ready - when(io.read.req.fire) { - curBankId := io.bank_id - opIsRead := true.B - opIsAccum := false.B - latAddr := io.read.req.bits.addr - - io.sramRead.req.valid := true.B - io.sramRead.req.bits.addr := io.read.req.bits.addr - - state := s_wait_read_resp - } + // Priority: write first, then read. + // IMPORTANT: never make req.valid depend on ready/fire; that can create combinational loops. + val writeValid = io.write.req.valid + val writeAccum = writeValid && io.write.req.bits.wmode + val writeDirect = writeValid && !io.write.req.bits.wmode + val readValid = !writeValid && io.read.req.valid + + // Downstream bank requests (valid depends only on upstream valid + state) + io.sramRead.req.valid := writeAccum || readValid + io.sramRead.req.bits.addr := Mux(writeAccum, io.write.req.bits.addr, io.read.req.bits.addr) + + io.sramWrite.req.valid := writeDirect + io.sramWrite.req.bits.addr := io.write.req.bits.addr + io.sramWrite.req.bits.data := io.write.req.bits.data + io.sramWrite.req.bits.mask := io.write.req.bits.mask + io.sramWrite.req.bits.wmode := false.B + + // Upstream ready is a function of the selected downstream ready + io.write.req.ready := Mux( + writeAccum, + io.sramRead.req.ready, + Mux(writeDirect, io.sramWrite.req.ready, false.B) + ) + io.read.req.ready := readValid && io.sramRead.req.ready + + // State transitions + latching on fire + when(writeAccum && io.sramRead.req.fire) { + curBankId := io.bank_id + opIsRead := false.B + opIsAccum := true.B + latAddr := io.write.req.bits.addr + latData := io.write.req.bits.data + latMask := io.write.req.bits.mask + state := s_wait_read_resp + }.elsewhen(writeDirect && io.sramWrite.req.fire) { + curBankId := io.bank_id + opIsRead := false.B + opIsAccum := false.B + latAddr := io.write.req.bits.addr + latData := io.write.req.bits.data + latMask := io.write.req.bits.mask + state := s_wait_direct_write_resp + }.elsewhen(readValid && io.sramRead.req.fire) { + curBankId := io.bank_id + opIsRead := true.B + opIsAccum := false.B + latAddr := io.read.req.bits.addr + state := s_wait_read_resp } } From 6824f780d0261fefc8a7390ffb19dee574766dc2 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 6 Jan 2026 16:45:21 +0800 Subject: [PATCH 049/238] [arch]fix:fix the bugs of toybuckyball --- .../scala/examples/toy/ToyBuckyBall.scala | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 23b9b462..53dcf40b 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -102,7 +102,35 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w gpDomain.io.global_issue_i <> frontend.io.gp_issue_o frontend.io.gp_complete_i <> gpDomain.io.global_complete_o - ballDomain.bankRead <> memDomain.io.ballDomain.bankRead + // Break potential combinational loops on bankRead by registering the req channel. + // IDs are queued alongside the req bits to keep them aligned through backpressure. + for (i <- 0 until b.top.memBallChannelNum) { + val bankReadReqWithIds = Wire(Decoupled(new Bundle { + val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) + val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) + val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) + val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) + })) + + bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid + bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id + bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id + bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id + bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits + ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready + + val bankReadReqQ = Queue(bankReadReqWithIds, 1) + + memDomain.io.ballDomain.bankRead(i).io.req.valid := bankReadReqQ.valid + memDomain.io.ballDomain.bankRead(i).io.req.bits := bankReadReqQ.bits.req + memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id + memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id + memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id + bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready + + ballDomain.bankRead(i).io.resp <> memDomain.io.ballDomain.bankRead(i).io.resp + } + ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite // Connect BallMemChannelCluster From 77a8d4081989b56875c74d126238df54809dc3ff Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 6 Jan 2026 18:20:09 +0800 Subject: [PATCH 050/238] [arch]fix:fix the potential problems of readreqgen module --- .../bbus/memrouter/ReadReqGen.scala | 41 +++--- .../balldomain/bbus/memrouter/memRouter.scala | 121 ++++++++++-------- 2 files changed, 91 insertions(+), 71 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala index 31427e9a..d5d62267 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -2,18 +2,26 @@ package framework.balldomain.bbus.memrouter import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig -import framework.balldomain.blink.{BankRead} class ReadReq(val b: GlobalConfig) extends Bundle { val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum val bank_id = UInt(log2Up(b.memDomain.bankNum).W) val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + // 按你的要求：不加 +1 val channel_num = UInt(log2Up(totalReadChannels).W) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } +// 统计探针：只带“统计需要的信息”，不带 ready/resp +class BankReadProbe(val b: GlobalConfig) extends Bundle { + val valid = Bool() + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) +} + @instantiable class ReadReqGen(val b: GlobalConfig) extends Module { val ballIdMappings = b.ballDomain.ballIdMappings @@ -21,9 +29,14 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val totalReadChannels = ballIdMappings.map(_.inBW).sum val numBanks = b.memDomain.bankNum + require( + ballIdMappings.forall(_.inBW > 0), + "ReadReqGen assumes every ball has at least one read channel (inBW > 0); otherwise robId indexing is invalid." + ) + @public val io = IO(new Bundle { - val bank_read_i = Vec(totalReadChannels, new BankRead(b)) + val bank_read_i = Input(Vec(totalReadChannels, new BankReadProbe(b))) val read_req_o = Decoupled(new ReadReq(b)) }) @@ -33,17 +46,14 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val ballInBW = ballIdMappings(ballId).inBW val matchingChannels = (ballOffset until ballOffset + ballInBW).toSeq - val hasReq = matchingChannels.map(ch => - io.bank_read_i(ch).io.req.valid && + val matchConds = matchingChannels.map { ch => + io.bank_read_i(ch).valid && io.bank_read_i(ch).ball_id === ballId.U && io.bank_read_i(ch).bank_id === bankId.U - ).reduceOption(_ || _).getOrElse(false.B) + } - val channelCount = PopCount(matchingChannels.map(ch => - io.bank_read_i(ch).io.req.valid && - io.bank_read_i(ch).ball_id === ballId.U && - io.bank_read_i(ch).bank_id === bankId.U - )) + val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) + val channelCount = PopCount(matchConds) val robId = io.bank_read_i(ballOffset).rob_id @@ -53,7 +63,8 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val arb = Module(new Arbiter( new Bundle { - val channel_num = UInt(log2Up(totalReadChannels + 1).W) + // 按你的要求：不加 +1，且和 ReadReq 保持一致 + val channel_num = UInt(log2Up(totalReadChannels).W) val bank_id = UInt(log2Up(numBanks).W) val ball_id = UInt(log2Up(numBalls).W) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) @@ -69,12 +80,6 @@ class ReadReqGen(val b: GlobalConfig) extends Module { arb.io.in(i).bits.rob_id := reqGroupsWithRobId(i)._5 } - for(i <- 0 until totalReadChannels) { - io.bank_read_i(i).io.req.ready := true.B - io.bank_read_i(i).io.resp.valid := false.B - io.bank_read_i(i).io.resp.bits := DontCare - } - io.read_req_o.valid := arb.io.out.valid io.read_req_o.bits.bank_id := arb.io.out.bits.bank_id io.read_req_o.bits.ball_id := arb.io.out.bits.ball_id diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index f6eb8d0c..acab7fd4 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -42,43 +42,46 @@ class MemRouter(val b: GlobalConfig) extends Module { //--------------------------------------------------------------------------- // Read //--------------------------------------------------------------------------- -// Step1: Generate read request +// Step1: Generate read request val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) - + for (i <- 0 until totalReadChannels) { - // Connect input fields from io.bankRead_i to readReqGen.io.bank_read_i - readReqGen.io.bank_read_i(i) <> io.bankRead_i(i) + readReqGen.io.bank_read_i(i).valid := io.bankRead_i(i).io.req.valid + readReqGen.io.bank_read_i(i).ball_id := io.bankRead_i(i).ball_id + readReqGen.io.bank_read_i(i).bank_id := io.bankRead_i(i).bank_id + readReqGen.io.bank_read_i(i).rob_id := io.bankRead_i(i).rob_id } // Step2: Peek if there are enough free channels - val hasReadReq = readReqGen.io.read_req_o.valid - io.peakChannelReq.valid := hasReadReq - io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num - io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id - io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id - //io.peakChannelReq <> readReqGen.io.read_req_o -// Step3/1: if there are enough free channels, accept the request + val hasReadReq = readReqGen.io.read_req_o.valid + io.peakChannelReq.valid := hasReadReq + io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num + io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id + io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id + +// Step3: accept the request only when enough channels val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free - io.freeChannelResp.ready := true.B - val dispatchChannels = io.freeChannelResp.bits.channel_ids + io.freeChannelResp.ready := true.B + val dispatchChannels = io.freeChannelResp.bits.channel_ids readReqGen.io.read_req_o.ready := isChannelFree -// Step3/2: if there are not enough free channels, continue to peek until there are enough free channels - channelMappingTable.io.write.valid := false.B - channelMappingTable.io.write.bits.idx := 0.U + +// 默认不写映射 + channelMappingTable.io.write.valid := false.B + channelMappingTable.io.write.bits.idx := 0.U channelMappingTable.io.write.bits.outCh := 0.U // Step4: Set the channel mapping table when(readReqGen.io.read_req_o.fire) { val matchVec = VecInit((0 until totalReadChannels).map { i => io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && - io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && + io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && io.bankRead_i(i).io.req.valid }) - val matchCount = PopCount(matchVec) - val channelNum = readReqGen.io.read_req_o.bits.channel_num + val matchCount = PopCount(matchVec) + val channelNum = readReqGen.io.read_req_o.bits.channel_num val dispatchCount = Mux(matchCount > channelNum, channelNum, matchCount) - + for (i <- 0 until totalReadChannels) { when(matchVec(i)) { val priorMatchCount = PopCount(matchVec.take(i)) @@ -90,43 +93,55 @@ class MemRouter(val b: GlobalConfig) extends Module { } } } - for (i <- 0 until bbusProducerChannels) { - io.bankRead_o(i).io.req.valid := false.B - io.bankRead_o(i).io.resp.ready := true.B - io.bankRead_o(i).io.req.bits := DontCare - io.bankRead_o(i).bank_id := DontCare - io.bankRead_o(i).ball_id := DontCare - io.bankRead_o(i).rob_id := DontCare - io.bankWrite_o(i).io.req.valid := false.B - io.bankWrite_o(i).io.resp.ready := true.B - io.bankWrite_o(i).io.req.bits := DontCare - io.bankWrite_o(i).bank_id := DontCare - io.bankWrite_o(i).ball_id := DontCare - io.bankWrite_o(i).rob_id := DontCare + +//-------------------- 默认值：输出端全空闲，输入端默认不 ready（避免吞请求） -------------------- + for (o <- 0 until bbusProducerChannels) { + io.bankRead_o(o).io.req.valid := false.B + io.bankRead_o(o).io.req.bits := DontCare + io.bankRead_o(o).io.resp.ready := true.B + io.bankRead_o(o).bank_id := DontCare + io.bankRead_o(o).ball_id := DontCare + io.bankRead_o(o).rob_id := DontCare + + io.bankWrite_o(o).io.req.valid := false.B + io.bankWrite_o(o).io.req.bits := DontCare + io.bankWrite_o(o).io.resp.ready := true.B + io.bankWrite_o(o).bank_id := DontCare + io.bankWrite_o(o).ball_id := DontCare + io.bankWrite_o(o).rob_id := DontCare } - io.bankWrite_i.map(_.io.req.ready := true.B) - io.bankWrite_i.map(_.io.resp.valid := false.B) - io.bankWrite_i.map(_.io.resp.bits := DontCare) - io.bankRead_i.map(_.io.req.ready := true.B) - io.bankRead_i.map(_.io.resp.valid := false.B) - io.bankRead_i.map(_.io.resp.bits := DontCare) - -// Step5: Dispatch the request to the channels + + // 输入端：默认不接受请求（等到被映射到 outCh 再根据 outCh.ready 回推） + for (i <- 0 until totalReadChannels) { + io.bankRead_i(i).io.req.ready := false.B + io.bankRead_i(i).io.resp.valid := false.B + io.bankRead_i(i).io.resp.bits := DontCare + } + +// Step5: Dispatch the request to the channels（显式连 req，并回推 ready） for (i <- 0 until totalReadChannels) { when(channelMappingTable.io.routeValid(i)) { val outCh = channelMappingTable.io.routeMap(i) - /* - io.bankRead_o(outCh).io.req <> io.bankRead_i(i).io.req - io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id - io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id - io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id - io.bankWrite_o(outCh).io.req <> io.bankWrite_i(i).io.req - io.bankWrite_o(outCh).bank_id := io.bankWrite_i(i).bank_id - io.bankWrite_o(outCh).ball_id := io.bankWrite_i(i).ball_id - io.bankWrite_o(outCh).rob_id := io.bankWrite_i(i).rob_id - */ - io.bankRead_o(outCh) <> io.bankRead_i(i) - io.bankWrite_o(outCh) <> io.bankWrite_i(i) + + // drive output req from selected input + io.bankRead_o(outCh).io.req.valid := io.bankRead_i(i).io.req.valid + io.bankRead_o(outCh).io.req.bits := io.bankRead_i(i).io.req.bits + io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id + io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id + io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id + + // backpressure back to input + io.bankRead_i(i).io.req.ready := io.bankRead_o(outCh).io.req.ready } } + +//--------------------------------------------------------------------------- +// Write: 你原代码这里还没理顺（读写索引空间不一致），我保持不动/默认不派发 +//--------------------------------------------------------------------------- + + for (i <- 0 until totalWriteChannels) { + io.bankWrite_i(i).io.req.ready := true.B + io.bankWrite_i(i).io.resp.valid := false.B + io.bankWrite_i(i).io.resp.bits := DontCare + } } \ No newline at end of file From ca2c912a1101e6fd71d2c0ec590747535a90ce68 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 7 Jan 2026 16:03:01 +0800 Subject: [PATCH 051/238] [arch]fix:fix some bugs of memrouter --- .../bbus/memrouter/ChannelMapping.scala | 44 ++++++++++--- .../balldomain/bbus/memrouter/memRouter.scala | 66 +++++++++++++------ 2 files changed, 82 insertions(+), 28 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala index cd22c5a0..640e1d31 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala @@ -10,13 +10,18 @@ class ChannelMappingTable(val b: GlobalConfig) extends Module { val EntryNum = b.ballDomain.ballIdMappings.map(_.inBW).sum val MappedChannels = b.top.ballMemChannelNum + // 多写口数量：与输出通道数一致（一次最多派发这么多条） + val WritePorts = MappedChannels + @public val io = IO(new Bundle { - - val write = Flipped(Decoupled(new Bundle { + val write = Flipped(Vec(WritePorts, Decoupled(new Bundle { val idx = UInt(log2Up(EntryNum).W) val outCh = UInt(log2Up(MappedChannels).W) - })) + }))) + + // 条目级清理：每个写口对应一条可能的派发通道（通常用 outCh 作为端口号） + val invalidate = Input(Vec(WritePorts, Valid(UInt(log2Up(EntryNum).W)))) val routeMap = Output(Vec(EntryNum, UInt(log2Up(MappedChannels).W))) val routeValid = Output(Vec(EntryNum, Bool())) @@ -25,12 +30,33 @@ class ChannelMappingTable(val b: GlobalConfig) extends Module { val routeMap = Reg(Vec(EntryNum, UInt(log2Up(MappedChannels).W))) val routeValid = RegInit(VecInit(Seq.fill(EntryNum)(false.B))) - when(io.write.fire) { - routeMap(io.write.bits.idx) := io.write.bits.outCh - routeValid(io.write.bits.idx) := true.B + for (w <- 0 until WritePorts) { + io.write(w).ready := true.B + + // 先处理清理：把对应 idx 的 valid 清掉 + when(io.invalidate(w).valid) { + routeValid(io.invalidate(w).bits) := false.B + } + + // 再处理写入：同拍既清又写时，让写入优先（最终为 valid=true） + when(io.write(w).fire) { + routeMap(io.write(w).bits.idx) := io.write(w).bits.outCh + routeValid(io.write(w).bits.idx) := true.B + } } - io.routeMap := routeMap - io.routeValid := routeValid - io.write.ready := true.B + io.routeMap := routeMap + io.routeValid := routeValid + + // Assert: in the same cycle, different write ports must not target the same idx + for (p <- 0 until WritePorts) { + for (q <- p + 1 until WritePorts) { + when(io.write(p).valid && io.write(q).valid) { + assert( + io.write(p).bits.idx =/= io.write(q).bits.idx, + "ChannelMappingTable: multiple write ports target the same idx in one cycle" + ) + } + } + } } diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index acab7fd4..9d199a14 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -7,7 +7,7 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.top.GlobalConfig class PeakChannelReq(val b: GlobalConfig) extends Bundle { - val needed_channel_num = UInt(log2Up(b.ballDomain.ballIdMappings.map(_.inBW).sum + 1).W) + val needed_channel_num = UInt(log2Up(b.ballDomain.ballIdMappings.map(_.inBW).sum).W) val bank_id = UInt(log2Up(b.memDomain.bankNum).W) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } @@ -42,7 +42,7 @@ class MemRouter(val b: GlobalConfig) extends Module { //--------------------------------------------------------------------------- // Read //--------------------------------------------------------------------------- -// Step1: Generate read request +// Step1: Generate read request (probe only) val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) @@ -66,29 +66,50 @@ class MemRouter(val b: GlobalConfig) extends Module { val dispatchChannels = io.freeChannelResp.bits.channel_ids readReqGen.io.read_req_o.ready := isChannelFree -// 默认不写映射 - channelMappingTable.io.write.valid := false.B - channelMappingTable.io.write.bits.idx := 0.U - channelMappingTable.io.write.bits.outCh := 0.U +// 默认不写映射/不清理（多写口：全部置空） + for (w <- 0 until bbusProducerChannels) { + channelMappingTable.io.write(w).valid := false.B + channelMappingTable.io.write(w).bits.idx := 0.U + channelMappingTable.io.write(w).bits.outCh := 0.U -// Step4: Set the channel mapping table + channelMappingTable.io.invalidate(w).valid := false.B + channelMappingTable.io.invalidate(w).bits := 0.U + } + +// Step4: Set the channel mapping table (batch write) when(readReqGen.io.read_req_o.fire) { val matchVec = VecInit((0 until totalReadChannels).map { i => io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && io.bankRead_i(i).io.req.valid }) - val matchCount = PopCount(matchVec) - val channelNum = readReqGen.io.read_req_o.bits.channel_num - val dispatchCount = Mux(matchCount > channelNum, channelNum, matchCount) + val matchCount = PopCount(matchVec) + val channelNum = readReqGen.io.read_req_o.bits.channel_num + + val portLimit = bbusProducerChannels.U + val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) + val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) + + // Assert: outCh used in this dispatch must be unique (no two inputs drive one output) + for (p <- 0 until bbusProducerChannels) { + for (q <- p + 1 until bbusProducerChannels) { + when((p.U < dispatchCount) && (q.U < dispatchCount)) { + assert( + dispatchChannels(p) =/= dispatchChannels(q), + "MemRouter: duplicate outCh in dispatchChannels within dispatchCount" + ) + } + } + } for (i <- 0 until totalReadChannels) { when(matchVec(i)) { val priorMatchCount = PopCount(matchVec.take(i)) when(priorMatchCount < dispatchCount) { - channelMappingTable.io.write.valid := true.B - channelMappingTable.io.write.bits.idx := i.U - channelMappingTable.io.write.bits.outCh := dispatchChannels(priorMatchCount) + // 第 k 个匹配输入 -> 第 k 个写口 + channelMappingTable.io.write(priorMatchCount).valid := true.B + channelMappingTable.io.write(priorMatchCount).bits.idx := i.U + channelMappingTable.io.write(priorMatchCount).bits.outCh := dispatchChannels(priorMatchCount) } } } @@ -111,34 +132,41 @@ class MemRouter(val b: GlobalConfig) extends Module { io.bankWrite_o(o).rob_id := DontCare } - // 输入端：默认不接受请求（等到被映射到 outCh 再根据 outCh.ready 回推） for (i <- 0 until totalReadChannels) { io.bankRead_i(i).io.req.ready := false.B io.bankRead_i(i).io.resp.valid := false.B io.bankRead_i(i).io.resp.bits := DontCare } -// Step5: Dispatch the request to the channels（显式连 req，并回推 ready） +// Step5: Dispatch the request to the channels + entry-level invalidation for (i <- 0 until totalReadChannels) { when(channelMappingTable.io.routeValid(i)) { val outCh = channelMappingTable.io.routeMap(i) - // drive output req from selected input io.bankRead_o(outCh).io.req.valid := io.bankRead_i(i).io.req.valid io.bankRead_o(outCh).io.req.bits := io.bankRead_i(i).io.req.bits io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id - // backpressure back to input io.bankRead_i(i).io.req.ready := io.bankRead_o(outCh).io.req.ready + + // 当该输入真正 fire（握手成功）后，清掉它的映射条目 + val didFire = io.bankRead_i(i).io.req.fire + for (o <- 0 until bbusProducerChannels) { + when(outCh === o.U) { + channelMappingTable.io.invalidate(o).valid := didFire + channelMappingTable.io.invalidate(o).bits := i.U + } + } } } + + //--------------------------------------------------------------------------- -// Write: 你原代码这里还没理顺（读写索引空间不一致），我保持不动/默认不派发 +// Write: 仍未路由（保持你当前的默认行为） //--------------------------------------------------------------------------- - for (i <- 0 until totalWriteChannels) { io.bankWrite_i(i).io.req.ready := true.B io.bankWrite_i(i).io.resp.valid := false.B From aae45992a5535ba479c203cfdb31c4b312ffc247 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Thu, 8 Jan 2026 11:22:18 +0800 Subject: [PATCH 052/238] [arch]feat:add writereqgen part for memrouter --- .../bbus/memrouter/ChannelMapping.scala | 4 +- .../bbus/memrouter/ReadReqGen.scala | 21 +- .../bbus/memrouter/WriteReqGen.scala | 89 +++++++ .../balldomain/bbus/memrouter/memRouter.scala | 252 ++++++++++++------ 4 files changed, 278 insertions(+), 88 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala index 640e1d31..ffac5a84 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala @@ -6,8 +6,8 @@ import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig @instantiable -class ChannelMappingTable(val b: GlobalConfig) extends Module { - val EntryNum = b.ballDomain.ballIdMappings.map(_.inBW).sum +class ChannelMappingTable(val b: GlobalConfig, val entryNum: Int) extends Module { + val EntryNum = entryNum val MappedChannels = b.top.ballMemChannelNum // 多写口数量：与输出通道数一致（一次最多派发这么多条） diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala index d5d62267..5a987717 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -6,15 +6,12 @@ import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig class ReadReq(val b: GlobalConfig) extends Bundle { - val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) - // 按你的要求：不加 +1 - val channel_num = UInt(log2Up(totalReadChannels).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } -// 统计探针：只带“统计需要的信息”，不带 ready/resp class BankReadProbe(val b: GlobalConfig) extends Bundle { val valid = Bool() val bank_id = UInt(log2Up(b.memDomain.bankNum).W) @@ -52,8 +49,11 @@ class ReadReqGen(val b: GlobalConfig) extends Module { io.bank_read_i(ch).bank_id === bankId.U } - val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) - val channelCount = PopCount(matchConds) + val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) + val channelCountRaw = PopCount(matchConds) + + val maxCh = b.top.ballMemChannelNum.U + val channelCount = Mux(channelCountRaw > maxCh, maxCh, channelCountRaw) val robId = io.bank_read_i(ballOffset).rob_id @@ -63,8 +63,7 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val arb = Module(new Arbiter( new Bundle { - // 按你的要求：不加 +1，且和 ReadReq 保持一致 - val channel_num = UInt(log2Up(totalReadChannels).W) + val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) val bank_id = UInt(log2Up(numBanks).W) val ball_id = UInt(log2Up(numBalls).W) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala new file mode 100644 index 00000000..933601ac --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala @@ -0,0 +1,89 @@ +package framework.balldomain.bbus.memrouter + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +class WriteReq(val b: GlobalConfig) extends Bundle { + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) +} + +class BankWriteProbe(val b: GlobalConfig) extends Bundle { + val valid = Bool() + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) +} + +@instantiable +class WriteReqGen(val b: GlobalConfig) extends Module { + val ballIdMappings = b.ballDomain.ballIdMappings + val numBalls = b.ballDomain.ballNum + val totalWriteChannels = ballIdMappings.map(_.outBW).sum + val numBanks = b.memDomain.bankNum + + require( + ballIdMappings.forall(_.outBW > 0), + "WriteReqGen assumes every ball has at least one write channel (outBW > 0); otherwise robId indexing is invalid." + ) + + @public + val io = IO(new Bundle { + val bank_write_i = Input(Vec(totalWriteChannels, new BankWriteProbe(b))) + val write_req_o = Decoupled(new WriteReq(b)) + }) + + val reqGroupsWithRobId = (0 until numBalls).flatMap { ballId => + (0 until numBanks).map { bankId => + val ballOffset = ballIdMappings.take(ballId).map(_.outBW).sum + val ballOutBW = ballIdMappings(ballId).outBW + val matchingChannels = (ballOffset until ballOffset + ballOutBW).toSeq + + val matchConds = matchingChannels.map { ch => + io.bank_write_i(ch).valid && + io.bank_write_i(ch).ball_id === ballId.U && + io.bank_write_i(ch).bank_id === bankId.U + } + + val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) + val channelCountRaw = PopCount(matchConds) + + val maxCh = b.top.ballMemChannelNum.U + val channelCount = Mux(channelCountRaw > maxCh, maxCh, channelCountRaw) + + val robId = io.bank_write_i(ballOffset).rob_id + + (hasReq, channelCount, bankId.U, ballId.U, robId) + } + } + + val arb = Module(new Arbiter( + new Bundle { + val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) + val bank_id = UInt(log2Up(numBanks).W) + val ball_id = UInt(log2Up(numBalls).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + }, + reqGroupsWithRobId.length + )) + + for (i <- reqGroupsWithRobId.indices) { + arb.io.in(i).valid := reqGroupsWithRobId(i)._1 + arb.io.in(i).bits.channel_num := reqGroupsWithRobId(i)._2 + arb.io.in(i).bits.bank_id := reqGroupsWithRobId(i)._3 + arb.io.in(i).bits.ball_id := reqGroupsWithRobId(i)._4 + arb.io.in(i).bits.rob_id := reqGroupsWithRobId(i)._5 + } + + io.write_req_o.valid := arb.io.out.valid + io.write_req_o.bits.bank_id := arb.io.out.bits.bank_id + io.write_req_o.bits.ball_id := arb.io.out.bits.ball_id + io.write_req_o.bits.channel_num := arb.io.out.bits.channel_num + io.write_req_o.bits.rob_id := arb.io.out.bits.rob_id + arb.io.out.ready := io.write_req_o.ready +} + diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index 9d199a14..a1f137f4 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -7,7 +7,7 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.top.GlobalConfig class PeakChannelReq(val b: GlobalConfig) extends Bundle { - val needed_channel_num = UInt(log2Up(b.ballDomain.ballIdMappings.map(_.inBW).sum).W) + val needed_channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) val bank_id = UInt(log2Up(b.memDomain.bankNum).W) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } @@ -20,17 +20,14 @@ class FreeChannelResp(val b: GlobalConfig) extends Bundle { @instantiable class MemRouter(val b: GlobalConfig) extends Module { - val numBalls = b.ballDomain.ballNum val bbusProducerChannels = b.top.ballMemChannelNum - val bbusConsumerChannels = b.top.memBallChannelNum val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum - val maxPerChannelWidth = b.ballDomain.ballIdMappings.flatMap(m => Seq(m.inBW, m.outBW)).max @public val io = IO(new Bundle { - val bankRead_i = Vec(totalReadChannels, new BankRead(b)) - val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) + val bankRead_i = Vec(totalReadChannels, new BankRead(b)) + val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) @@ -39,12 +36,14 @@ class MemRouter(val b: GlobalConfig) extends Module { val freeChannelResp = Flipped(Decoupled(new FreeChannelResp(b))) }) -//--------------------------------------------------------------------------- -// Read -//--------------------------------------------------------------------------- -// Step1: Generate read request (probe only) - val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) - val channelMappingTable: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b)) + // --------------------------------------------------------------------------- + // Step1: probe -> ReadReqGen / WriteReqGen + // --------------------------------------------------------------------------- + val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) + val writeReqGen: Instance[WriteReqGen] = Instantiate(new WriteReqGen(b)) + + val readMap: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b, totalReadChannels)) + val writeMap: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b, totalWriteChannels)) for (i <- 0 until totalReadChannels) { readReqGen.io.bank_read_i(i).valid := io.bankRead_i(i).io.req.valid @@ -52,81 +51,157 @@ class MemRouter(val b: GlobalConfig) extends Module { readReqGen.io.bank_read_i(i).bank_id := io.bankRead_i(i).bank_id readReqGen.io.bank_read_i(i).rob_id := io.bankRead_i(i).rob_id } + for (i <- 0 until totalWriteChannels) { + writeReqGen.io.bank_write_i(i).valid := io.bankWrite_i(i).io.req.valid + writeReqGen.io.bank_write_i(i).ball_id := io.bankWrite_i(i).ball_id + writeReqGen.io.bank_write_i(i).bank_id := io.bankWrite_i(i).bank_id + writeReqGen.io.bank_write_i(i).rob_id := io.bankWrite_i(i).rob_id + } + + // --------------------------------------------------------------------------- + // Step2: one allocator, RR choose read/write group + // --------------------------------------------------------------------------- + val hasReadReq = readReqGen.io.read_req_o.valid + val hasWriteReq = writeReqGen.io.write_req_o.valid + + val rrLastWasRead = RegInit(true.B) // 用于读写公平：true 表示上次发的是读 + + val chooseRead = WireDefault(false.B) + when(hasReadReq && !hasWriteReq) { + chooseRead := true.B + }.elsewhen(!hasReadReq && hasWriteReq) { + chooseRead := false.B + }.elsewhen(hasReadReq && hasWriteReq) { + chooseRead := !rrLastWasRead + } + + val chooseWrite = hasReadReq && hasWriteReq && !chooseRead || (!hasReadReq && hasWriteReq) -// Step2: Peek if there are enough free channels - val hasReadReq = readReqGen.io.read_req_o.valid - io.peakChannelReq.valid := hasReadReq - io.peakChannelReq.bits.needed_channel_num := readReqGen.io.read_req_o.bits.channel_num - io.peakChannelReq.bits.bank_id := readReqGen.io.read_req_o.bits.bank_id - io.peakChannelReq.bits.rob_id := readReqGen.io.read_req_o.bits.rob_id + io.peakChannelReq.valid := hasReadReq || hasWriteReq + io.peakChannelReq.bits.needed_channel_num := Mux(chooseRead, readReqGen.io.read_req_o.bits.channel_num, writeReqGen.io.write_req_o.bits.channel_num) + io.peakChannelReq.bits.bank_id := Mux(chooseRead, readReqGen.io.read_req_o.bits.bank_id, writeReqGen.io.write_req_o.bits.bank_id) + io.peakChannelReq.bits.rob_id := Mux(chooseRead, readReqGen.io.read_req_o.bits.rob_id, writeReqGen.io.write_req_o.bits.rob_id) -// Step3: accept the request only when enough channels - val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free - io.freeChannelResp.ready := true.B - val dispatchChannels = io.freeChannelResp.bits.channel_ids - readReqGen.io.read_req_o.ready := isChannelFree + // allocator 这里当“组合查询”用 + io.freeChannelResp.ready := true.B + val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free && io.peakChannelReq.valid + val dispatchChannels = io.freeChannelResp.bits.channel_ids -// 默认不写映射/不清理（多写口：全部置空） + readReqGen.io.read_req_o.ready := isChannelFree && chooseRead + writeReqGen.io.write_req_o.ready := isChannelFree && chooseWrite + + val didDispatchRead = readReqGen.io.read_req_o.fire + val didDispatchWrite = writeReqGen.io.write_req_o.fire + + when(didDispatchRead) { rrLastWasRead := true.B } + when(didDispatchWrite) { rrLastWasRead := false.B } + + // --------------------------------------------------------------------------- + // defaults: mapping write/invalidate off + // --------------------------------------------------------------------------- for (w <- 0 until bbusProducerChannels) { - channelMappingTable.io.write(w).valid := false.B - channelMappingTable.io.write(w).bits.idx := 0.U - channelMappingTable.io.write(w).bits.outCh := 0.U + readMap.io.write(w).valid := false.B + readMap.io.write(w).bits.idx := 0.U + readMap.io.write(w).bits.outCh := 0.U + readMap.io.invalidate(w).valid := false.B + readMap.io.invalidate(w).bits := 0.U - channelMappingTable.io.invalidate(w).valid := false.B - channelMappingTable.io.invalidate(w).bits := 0.U + writeMap.io.write(w).valid := false.B + writeMap.io.write(w).bits.idx := 0.U + writeMap.io.write(w).bits.outCh := 0.U + writeMap.io.invalidate(w).valid := false.B + writeMap.io.invalidate(w).bits := 0.U } -// Step4: Set the channel mapping table (batch write) - when(readReqGen.io.read_req_o.fire) { + // --------------------------------------------------------------------------- + // Step4: batch write mapping for chosen side + // --------------------------------------------------------------------------- + when(didDispatchRead) { val matchVec = VecInit((0 until totalReadChannels).map { i => io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && io.bankRead_i(i).io.req.valid }) - val matchCount = PopCount(matchVec) - val channelNum = readReqGen.io.read_req_o.bits.channel_num - - val portLimit = bbusProducerChannels.U - val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) + val matchCount = PopCount(matchVec) + val channelNum = readReqGen.io.read_req_o.bits.channel_num + val portLimit = bbusProducerChannels.U + val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) - - // Assert: outCh used in this dispatch must be unique (no two inputs drive one output) + for (p <- 0 until bbusProducerChannels) { for (q <- p + 1 until bbusProducerChannels) { when((p.U < dispatchCount) && (q.U < dispatchCount)) { assert( dispatchChannels(p) =/= dispatchChannels(q), - "MemRouter: duplicate outCh in dispatchChannels within dispatchCount" + "MemRouter(Read): duplicate outCh in dispatchChannels within dispatchCount" ) } } } + for (i <- 0 until totalReadChannels) { when(matchVec(i)) { val priorMatchCount = PopCount(matchVec.take(i)) when(priorMatchCount < dispatchCount) { - // 第 k 个匹配输入 -> 第 k 个写口 - channelMappingTable.io.write(priorMatchCount).valid := true.B - channelMappingTable.io.write(priorMatchCount).bits.idx := i.U - channelMappingTable.io.write(priorMatchCount).bits.outCh := dispatchChannels(priorMatchCount) + readMap.io.write(priorMatchCount).valid := true.B + readMap.io.write(priorMatchCount).bits.idx := i.U + readMap.io.write(priorMatchCount).bits.outCh := dispatchChannels(priorMatchCount) + } + } + } + } + + when(didDispatchWrite) { + val matchVec = VecInit((0 until totalWriteChannels).map { i => + io.bankWrite_i(i).ball_id === writeReqGen.io.write_req_o.bits.ball_id && + io.bankWrite_i(i).bank_id === writeReqGen.io.write_req_o.bits.bank_id && + io.bankWrite_i(i).io.req.valid + }) + + val matchCount = PopCount(matchVec) + val channelNum = writeReqGen.io.write_req_o.bits.channel_num + val portLimit = bbusProducerChannels.U + val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) + val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) + + for (p <- 0 until bbusProducerChannels) { + for (q <- p + 1 until bbusProducerChannels) { + when((p.U < dispatchCount) && (q.U < dispatchCount)) { + assert( + dispatchChannels(p) =/= dispatchChannels(q), + "MemRouter(Write): duplicate outCh in dispatchChannels within dispatchCount" + ) + } + } + } + + for (i <- 0 until totalWriteChannels) { + when(matchVec(i)) { + val priorMatchCount = PopCount(matchVec.take(i)) + when(priorMatchCount < dispatchCount) { + writeMap.io.write(priorMatchCount).valid := true.B + writeMap.io.write(priorMatchCount).bits.idx := i.U + writeMap.io.write(priorMatchCount).bits.outCh := dispatchChannels(priorMatchCount) } } } } -//-------------------- 默认值：输出端全空闲，输入端默认不 ready（避免吞请求） -------------------- + // --------------------------------------------------------------------------- + // defaults: out ports idle; in ports backpressured; resp invalid + // --------------------------------------------------------------------------- for (o <- 0 until bbusProducerChannels) { io.bankRead_o(o).io.req.valid := false.B io.bankRead_o(o).io.req.bits := DontCare - io.bankRead_o(o).io.resp.ready := true.B + io.bankRead_o(o).io.resp.ready := false.B io.bankRead_o(o).bank_id := DontCare io.bankRead_o(o).ball_id := DontCare io.bankRead_o(o).rob_id := DontCare io.bankWrite_o(o).io.req.valid := false.B io.bankWrite_o(o).io.req.bits := DontCare - io.bankWrite_o(o).io.resp.ready := true.B + io.bankWrite_o(o).io.resp.ready := false.B io.bankWrite_o(o).bank_id := DontCare io.bankWrite_o(o).ball_id := DontCare io.bankWrite_o(o).rob_id := DontCare @@ -137,39 +212,66 @@ class MemRouter(val b: GlobalConfig) extends Module { io.bankRead_i(i).io.resp.valid := false.B io.bankRead_i(i).io.resp.bits := DontCare } + for (i <- 0 until totalWriteChannels) { + io.bankWrite_i(i).io.req.ready := false.B + io.bankWrite_i(i).io.resp.valid := false.B + io.bankWrite_i(i).io.resp.bits := DontCare + } -// Step5: Dispatch the request to the channels + entry-level invalidation - for (i <- 0 until totalReadChannels) { - when(channelMappingTable.io.routeValid(i)) { - val outCh = channelMappingTable.io.routeMap(i) - - io.bankRead_o(outCh).io.req.valid := io.bankRead_i(i).io.req.valid - io.bankRead_o(outCh).io.req.bits := io.bankRead_i(i).io.req.bits - io.bankRead_o(outCh).bank_id := io.bankRead_i(i).bank_id - io.bankRead_o(outCh).ball_id := io.bankRead_i(i).ball_id - io.bankRead_o(outCh).rob_id := io.bankRead_i(i).rob_id - - io.bankRead_i(i).io.req.ready := io.bankRead_o(outCh).io.req.ready - - // 当该输入真正 fire（握手成功）后，清掉它的映射条目 - val didFire = io.bankRead_i(i).io.req.fire - for (o <- 0 until bbusProducerChannels) { - when(outCh === o.U) { - channelMappingTable.io.invalidate(o).valid := didFire - channelMappingTable.io.invalidate(o).bits := i.U - } + // --------------------------------------------------------------------------- + // Step5: route req/resp by outCh, invalidate on resp.fire + // --------------------------------------------------------------------------- + for (o <- 0 until bbusProducerChannels) { + val readIdxOH = VecInit((0 until totalReadChannels).map { i => + readMap.io.routeValid(i) && (readMap.io.routeMap(i) === o.U) + }) + val writeIdxOH = VecInit((0 until totalWriteChannels).map { i => + writeMap.io.routeValid(i) && (writeMap.io.routeMap(i) === o.U) + }) + + val hasRead = readIdxOH.asUInt.orR + val hasWrite = writeIdxOH.asUInt.orR + + assert(!(hasRead && hasWrite), "MemRouter: one outCh is mapped by both read and write") + + when(hasRead) { + val ridx = PriorityEncoder(readIdxOH.asUInt) + + io.bankRead_o(o).io.req.valid := io.bankRead_i(ridx).io.req.valid + io.bankRead_o(o).io.req.bits := io.bankRead_i(ridx).io.req.bits + io.bankRead_o(o).bank_id := io.bankRead_i(ridx).bank_id + io.bankRead_o(o).ball_id := io.bankRead_i(ridx).ball_id + io.bankRead_o(o).rob_id := io.bankRead_i(ridx).rob_id + + io.bankRead_i(ridx).io.req.ready := io.bankRead_o(o).io.req.ready + + io.bankRead_i(ridx).io.resp.valid := io.bankRead_o(o).io.resp.valid + io.bankRead_i(ridx).io.resp.bits := io.bankRead_o(o).io.resp.bits + io.bankRead_o(o).io.resp.ready := io.bankRead_i(ridx).io.resp.ready + + when(io.bankRead_o(o).io.resp.fire) { + readMap.io.invalidate(o).valid := true.B + readMap.io.invalidate(o).bits := ridx } - } - } + }.elsewhen(hasWrite) { + val widx = PriorityEncoder(writeIdxOH.asUInt) + io.bankWrite_o(o).io.req.valid := io.bankWrite_i(widx).io.req.valid + io.bankWrite_o(o).io.req.bits := io.bankWrite_i(widx).io.req.bits + io.bankWrite_o(o).bank_id := io.bankWrite_i(widx).bank_id + io.bankWrite_o(o).ball_id := io.bankWrite_i(widx).ball_id + io.bankWrite_o(o).rob_id := io.bankWrite_i(widx).rob_id + io.bankWrite_i(widx).io.req.ready := io.bankWrite_o(o).io.req.ready -//--------------------------------------------------------------------------- -// Write: 仍未路由（保持你当前的默认行为） -//--------------------------------------------------------------------------- - for (i <- 0 until totalWriteChannels) { - io.bankWrite_i(i).io.req.ready := true.B - io.bankWrite_i(i).io.resp.valid := false.B - io.bankWrite_i(i).io.resp.bits := DontCare + io.bankWrite_i(widx).io.resp.valid := io.bankWrite_o(o).io.resp.valid + io.bankWrite_i(widx).io.resp.bits := io.bankWrite_o(o).io.resp.bits + io.bankWrite_o(o).io.resp.ready := io.bankWrite_i(widx).io.resp.ready + + when(io.bankWrite_o(o).io.resp.fire) { + writeMap.io.invalidate(o).valid := true.B + writeMap.io.invalidate(o).bits := widx + } + } } } \ No newline at end of file From a4b9ce62ca41bd7542b6fb37114ef18e96fc1207 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Thu, 8 Jan 2026 15:22:42 +0800 Subject: [PATCH 053/238] [arch]fix:fix the potential probelmes of combination loops --- .../framework/balldomain/bbus/cmdrouter/CmdRouter.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala index 8e1c0b3f..2bddde4b 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala @@ -22,10 +22,12 @@ class CmdRouter(val b: GlobalConfig) extends Module { val arbiter = Module(new RRArbiter(new BallRsIssue(b), numBalls)) + val ballIdleR = RegNext(io.ballIdle, VecInit(Seq.fill(numBalls)(false.B))) + for (i <- 0 until numBalls) { - arbiter.io.in(i).valid := io.cmdReq_i(i).valid && io.ballIdle(i) + arbiter.io.in(i).valid := io.cmdReq_i(i).valid && ballIdleR(i) arbiter.io.in(i).bits := io.cmdReq_i(i).bits - io.cmdReq_i(i).ready := arbiter.io.in(i).ready && io.ballIdle(i) + io.cmdReq_i(i).ready := arbiter.io.in(i).ready && ballIdleR(i) } io.cmdReq_o <> arbiter.io.out From ecb79bb8c9344c1d85ca8e27ce87c8063e5e5c0a Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 10 Jan 2026 02:52:57 +0800 Subject: [PATCH 054/238] [arch] fix: fix mvin/mvout test bug --- bb-tests/workloads/src/CTest/toy/buckyball.c | 8 +++++ bb-tests/workloads/src/CTest/toy/buckyball.h | 2 ++ .../workloads/src/CTest/toy/mvin_mvout_test.c | 34 ++++++++----------- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/buckyball.c b/bb-tests/workloads/src/CTest/toy/buckyball.c index 3376770e..f86b9740 100644 --- a/bb-tests/workloads/src/CTest/toy/buckyball.c +++ b/bb-tests/workloads/src/CTest/toy/buckyball.c @@ -33,6 +33,14 @@ void init_u8_random_matrix(elem_t *matrix, int rows, int cols, int seed) { } } +// Initialize matrix with incrementing values for debugging +void init_u8_incremental_matrix(elem_t *matrix, int rows, int cols, + int start_value) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = (start_value + i) & 0xFF; // Keep values in 0-255 range + } +} + void init_u32_random_matrix(result_t *matrix, int rows, int cols, int seed) { srand(seed); for (int i = 0; i < rows * cols; i++) { diff --git a/bb-tests/workloads/src/CTest/toy/buckyball.h b/bb-tests/workloads/src/CTest/toy/buckyball.h index 129f7a4b..0ab1d148 100644 --- a/bb-tests/workloads/src/CTest/toy/buckyball.h +++ b/bb-tests/workloads/src/CTest/toy/buckyball.h @@ -44,6 +44,8 @@ void print_i32_matrix(const char *name, result_t *matrix, int rows, int cols); void print_i8_matrix(const char *name, elem_t *matrix, int rows, int cols); void init_u8_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_u8_incremental_matrix(elem_t *matrix, int rows, int cols, + int start_value); void init_u32_random_matrix(result_t *matrix, int rows, int cols, int seed); void init_i8_random_matrix(elem_t *matrix, int rows, int cols, int seed); void init_i32_random_matrix(result_t *matrix, int rows, int cols, int seed); diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index d9af25c7..0f905da5 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -5,29 +5,25 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) // Test matrices -static elem_t input_matrix_a[DIM * 1024] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * 1024] __attribute__((aligned(64))); -static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); -static elem_t a_transposed[DIM * 1024] __attribute__((aligned(64))); +static elem_t input_matrix[DIM * DIM] __attribute__((aligned(16))); +static elem_t output_matrix[DIM * DIM] __attribute__((aligned(16))); -int alternately_mvin_mvout_pressure_test() { +int mvin_mvout_simple_test() { for (int i = 0; i < 4; i++) { - init_u8_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); - uint32_t acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM, 1); - clear_u32_matrix(output_matrix, DIM, DIM); - acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); - bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); + init_u8_random_matrix(input_matrix, DIM, DIM, 111); + bb_mvin((uintptr_t)input_matrix, 0, DIM, 1); + clear_u8_matrix(output_matrix, DIM, DIM); bb_fence(); - if (!compare_u8_matrices(output_matrix, expected_matrix, DIM, DIM)) { - printf("Test mvin/mvout pressure %d FAILED\n", i); + bb_mvout((uintptr_t)output_matrix, 0, DIM, 1); + bb_fence(); + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { + printf("Test mvin/mvout simple %d FAILED\n", i); return 0; } else { - printf("Test mvin/mvout pressure %d PASSED\n", i); + printf("Test mvin/mvout simple %d PASSED\n", i); } } return 1; @@ -37,11 +33,11 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - int passed = alternately_mvin_mvout_pressure_test(); + int passed = mvin_mvout_simple_test(); if (passed) { - printf("Alternately mvin/mvout pressure test PASSED\n"); + printf("mvin/mvout simple test PASSED\n"); } else { - printf("Alternately mvin/mvout pressure test FAILED\n"); + printf("mvin/mvout simple test FAILED\n"); } #ifdef MULTICORE exit(0); From aea83c10861c18cc3e3a60545d1e09d4003edf5b Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 10 Jan 2026 23:01:23 +0800 Subject: [PATCH 055/238] [bebop] feat: bump bebop to the latest version. (testing workloads waits vmem branch to be merged) --- .gitmodules | 9 +- bebop | 1 + bebop/.gitignore | 3 - bebop/CMakeLists.txt | 0 bebop/README.md | 25 --- bebop/bebop/Cargo.toml | 16 -- bebop/bebop/rustfmt.toml | 23 -- bebop/bebop/src/bin/bebop.rs | 24 -- bebop/bebop/src/buckyball/config.rs | 16 -- .../src/buckyball/frontend/decoder/decoder.rs | 31 --- .../src/buckyball/frontend/decoder/mod.rs | 3 - .../domain_scheduler/domain_scheduler.rs | 38 ---- .../frontend/domain_scheduler/mod.rs | 3 - .../bebop/src/buckyball/frontend/frontend.rs | 174 --------------- bebop/bebop/src/buckyball/frontend/mod.rs | 11 - bebop/bebop/src/buckyball/frontend/rob/mod.rs | 3 - bebop/bebop/src/buckyball/frontend/rob/rob.rs | 66 ------ bebop/bebop/src/buckyball/frontend/rs/mod.rs | 3 - bebop/bebop/src/buckyball/frontend/rs/rs.rs | 29 --- .../src/buckyball/memdomain/bank/bank.rs | 141 ------------ .../bebop/src/buckyball/memdomain/bank/mod.rs | 2 - .../buckyball/memdomain/decoder/decoder.rs | 83 ------- .../src/buckyball/memdomain/decoder/mod.rs | 2 - .../src/buckyball/memdomain/memdomain.rs | 177 --------------- bebop/bebop/src/buckyball/memdomain/mod.rs | 13 -- .../memdomain/out_controller/controller.rs | 52 ----- .../buckyball/memdomain/out_controller/mod.rs | 2 - .../src/buckyball/memdomain/reader/mod.rs | 3 - .../src/buckyball/memdomain/reader/reader.rs | 60 ----- .../src/buckyball/memdomain/writer/mod.rs | 3 - .../src/buckyball/memdomain/writer/writer.rs | 53 ----- bebop/bebop/src/buckyball/mod.rs | 16 -- bebop/bebop/src/buckyball/top.rs | 163 -------------- bebop/bebop/src/builtin/event.rs | 91 -------- bebop/bebop/src/builtin/interface.rs | 49 ---- bebop/bebop/src/builtin/mod.rs | 9 - bebop/bebop/src/builtin/module.rs | 3 - bebop/bebop/src/builtin/sim.rs | 11 - bebop/bebop/src/lib.rs | 19 -- bebop/bebop/src/simulator/mod.rs | 7 - bebop/bebop/src/simulator/server/cmd.rs | 80 ------- bebop/bebop/src/simulator/server/dma.rs | 110 --------- bebop/bebop/src/simulator/server/mod.rs | 7 - bebop/bebop/src/simulator/server/server.rs | 128 ----------- .../bebop/src/simulator/server/socket/cmd.rs | 72 ------ .../bebop/src/simulator/server/socket/mod.rs | 8 - .../src/simulator/server/socket/protocol.rs | 36 --- .../bebop/src/simulator/server/socket/read.rs | 63 ------ .../src/simulator/server/socket/write.rs | 69 ------ bebop/bebop/src/simulator/simulator.rs | 76 ------- bebop/bebop/src/simulator/utils/log.rs | 57 ----- bebop/bebop/src/simulator/utils/log_config.rs | 38 ---- bebop/bebop/src/simulator/utils/mod.rs | 3 - bebop/host/CMakeLists.txt | 6 - bebop/host/gem5/CMakeLists.txt | 0 bebop/host/gem5/bebop.patch | 211 ------------------ bebop/host/gem5/gem5 | 1 - bebop/host/gem5/install-gem5.sh | 46 ---- bebop/host/install.sh | 11 - bebop/host/ipc/CMakeLists.txt | 28 --- bebop/host/ipc/include/ipc/socket.h | 120 ---------- bebop/host/ipc/src/socket/socket.cc | 173 -------------- bebop/host/ipc/src/socket/socket_cmd.cc | 45 ---- bebop/host/ipc/src/socket/socket_dma.cc | 104 --------- bebop/host/spike/CMakeLists.txt | 1 - bebop/host/spike/customext/CMakeLists.txt | 38 ---- bebop/host/spike/customext/include/bebop.h | 44 ---- bebop/host/spike/customext/include/common.h | 9 - bebop/host/spike/customext/src/bebop.cc | 124 ---------- bebop/host/spike/install-spike.sh | 26 --- bebop/host/spike/riscv-isa-sim | 1 - bebop/scripts/bebop_setup.sh | 26 --- 72 files changed, 4 insertions(+), 3194 deletions(-) create mode 160000 bebop delete mode 100644 bebop/.gitignore delete mode 100644 bebop/CMakeLists.txt delete mode 100644 bebop/README.md delete mode 100644 bebop/bebop/Cargo.toml delete mode 100644 bebop/bebop/rustfmt.toml delete mode 100644 bebop/bebop/src/bin/bebop.rs delete mode 100644 bebop/bebop/src/buckyball/config.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/decoder/decoder.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/decoder/mod.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/domain_scheduler/domain_scheduler.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/domain_scheduler/mod.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/frontend.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/mod.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/rob/mod.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/rob/rob.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/rs/mod.rs delete mode 100644 bebop/bebop/src/buckyball/frontend/rs/rs.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/bank/bank.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/bank/mod.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/decoder/decoder.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/decoder/mod.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/memdomain.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/mod.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/out_controller/controller.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/out_controller/mod.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/reader/mod.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/reader/reader.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/writer/mod.rs delete mode 100644 bebop/bebop/src/buckyball/memdomain/writer/writer.rs delete mode 100644 bebop/bebop/src/buckyball/mod.rs delete mode 100644 bebop/bebop/src/buckyball/top.rs delete mode 100644 bebop/bebop/src/builtin/event.rs delete mode 100644 bebop/bebop/src/builtin/interface.rs delete mode 100644 bebop/bebop/src/builtin/mod.rs delete mode 100644 bebop/bebop/src/builtin/module.rs delete mode 100644 bebop/bebop/src/builtin/sim.rs delete mode 100644 bebop/bebop/src/lib.rs delete mode 100644 bebop/bebop/src/simulator/mod.rs delete mode 100644 bebop/bebop/src/simulator/server/cmd.rs delete mode 100644 bebop/bebop/src/simulator/server/dma.rs delete mode 100644 bebop/bebop/src/simulator/server/mod.rs delete mode 100644 bebop/bebop/src/simulator/server/server.rs delete mode 100644 bebop/bebop/src/simulator/server/socket/cmd.rs delete mode 100644 bebop/bebop/src/simulator/server/socket/mod.rs delete mode 100644 bebop/bebop/src/simulator/server/socket/protocol.rs delete mode 100644 bebop/bebop/src/simulator/server/socket/read.rs delete mode 100644 bebop/bebop/src/simulator/server/socket/write.rs delete mode 100644 bebop/bebop/src/simulator/simulator.rs delete mode 100644 bebop/bebop/src/simulator/utils/log.rs delete mode 100644 bebop/bebop/src/simulator/utils/log_config.rs delete mode 100644 bebop/bebop/src/simulator/utils/mod.rs delete mode 100644 bebop/host/CMakeLists.txt delete mode 100644 bebop/host/gem5/CMakeLists.txt delete mode 100644 bebop/host/gem5/bebop.patch delete mode 160000 bebop/host/gem5/gem5 delete mode 100755 bebop/host/gem5/install-gem5.sh delete mode 100755 bebop/host/install.sh delete mode 100644 bebop/host/ipc/CMakeLists.txt delete mode 100644 bebop/host/ipc/include/ipc/socket.h delete mode 100644 bebop/host/ipc/src/socket/socket.cc delete mode 100644 bebop/host/ipc/src/socket/socket_cmd.cc delete mode 100644 bebop/host/ipc/src/socket/socket_dma.cc delete mode 100644 bebop/host/spike/CMakeLists.txt delete mode 100644 bebop/host/spike/customext/CMakeLists.txt delete mode 100644 bebop/host/spike/customext/include/bebop.h delete mode 100644 bebop/host/spike/customext/include/common.h delete mode 100644 bebop/host/spike/customext/src/bebop.cc delete mode 100755 bebop/host/spike/install-spike.sh delete mode 160000 bebop/host/spike/riscv-isa-sim delete mode 100755 bebop/scripts/bebop_setup.sh diff --git a/.gitmodules b/.gitmodules index 2c0e5f58..22a776d4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,12 +10,6 @@ [submodule "thirdparty/picker"] path = thirdparty/picker url = https://github.com/XS-MLVP/picker.git -[submodule "bebop/host/gem5/gem5"] - path = bebop/host/gem5/gem5 - url = https://github.com/gem5/gem5.git -[submodule "bebop/host/spike/riscv-isa-sim"] - path = bebop/host/spike/riscv-isa-sim - url = https://github.com/riscv-software-src/riscv-isa-sim [submodule "tools/palladium"] path = tools/palladium url = https://github.com/SEU-ACAL/awesome-palladium.git @@ -25,3 +19,6 @@ [submodule "arch/thirdparty/t1"] path = arch/thirdparty/t1 url = https://github.com/DangoSys/t1.git +[submodule "bebop"] + path = bebop + url = https://github.com/DangoSys/bebop.git diff --git a/bebop b/bebop new file mode 160000 index 00000000..20089f60 --- /dev/null +++ b/bebop @@ -0,0 +1 @@ +Subproject commit 20089f60d8dd7000bab8faa3fe9be26e62f5fc7d diff --git a/bebop/.gitignore b/bebop/.gitignore deleted file mode 100644 index b66ba4e3..00000000 --- a/bebop/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -target/ -Cargo.lock -build/ diff --git a/bebop/CMakeLists.txt b/bebop/CMakeLists.txt deleted file mode 100644 index e69de29b..00000000 diff --git a/bebop/README.md b/bebop/README.md deleted file mode 100644 index a4a3c76a..00000000 --- a/bebop/README.md +++ /dev/null @@ -1,25 +0,0 @@ -# bebop -A buckyball emulator written in Rust - - -### Quick start - -1. Activate the virtual environment -``` -source $BUCKYBALL_PATH/env.sh -``` - - - -3. Start the socket server -``` -./scripts/bebop_setup.sh -``` - -4. Run the program -``` -$BUCKYBALL_PATH/bebop/host/spike/riscv-isa-sim/install/bin/spike --extension=bebop --log-commits $BUCKYBALL_PATH/bb-tests/build/workloads/src/OpTest/gemmini/transpose-baremetal 2>/dev/null -``` diff --git a/bebop/bebop/Cargo.toml b/bebop/bebop/Cargo.toml deleted file mode 100644 index eaba853b..00000000 --- a/bebop/bebop/Cargo.toml +++ /dev/null @@ -1,16 +0,0 @@ -[package] -name = "bebop" -version = "0.1.0" -edition = "2021" - -[lib] -name = "bebop" -path = "src/lib.rs" - -[dependencies] -serde = { version = "1.0", features = ["derive"] } -serde_json = "1.0" - -[[bin]] -name = "bebop" -path = "src/bin/bebop.rs" diff --git a/bebop/bebop/rustfmt.toml b/bebop/bebop/rustfmt.toml deleted file mode 100644 index 5de02797..00000000 --- a/bebop/bebop/rustfmt.toml +++ /dev/null @@ -1,23 +0,0 @@ -# Rust code formatting configuration file (stable features only) -# More configuration options: https://rust-lang.github.io/rustfmt/ - -# Maximum width per line -max_width = 120 - -# Hard tab width -tab_spaces = 2 - -# Use field initialization shorthand -use_field_init_shorthand = true - -# Use small layout on small arrays -use_small_heuristics = "Default" - -# Match block trailing comma -match_block_trailing_comma = true - -# Newline style -newline_style = "Unix" - -# Edition -edition = "2021" diff --git a/bebop/bebop/src/bin/bebop.rs b/bebop/bebop/src/bin/bebop.rs deleted file mode 100644 index ee49378b..00000000 --- a/bebop/bebop/src/bin/bebop.rs +++ /dev/null @@ -1,24 +0,0 @@ -/// Bebop - Accelerator Simulator -/// -/// Main executable for running the Bebop accelerator simulator. -/// This program listens for custom instruction requests from Host -/// and simulates accelerator behavior. -use bebop::{log_info, Simulator, StepMode}; -use std::env; - -fn main() -> std::io::Result<()> { - let args: Vec = env::args().collect(); - let step_mode = if args.iter().any(|arg| arg == "--step" || arg == "-s") { - StepMode::Step - } else { - StepMode::Run - }; - - if step_mode == StepMode::Step { - log_info!("Bebop Accelerator Simulator (Step Mode)"); - log_info!("Commands: Enter=step, r=run, q=quit"); - } - - let simulator = Simulator::new("127.0.0.1", 9999, step_mode); - simulator.run() -} diff --git a/bebop/bebop/src/buckyball/config.rs b/bebop/bebop/src/buckyball/config.rs deleted file mode 100644 index 4bb942ff..00000000 --- a/bebop/bebop/src/buckyball/config.rs +++ /dev/null @@ -1,16 +0,0 @@ -#[derive(Clone, Debug)] -pub struct NpuConfig { - pub mem_size: usize, -} - -impl NpuConfig { - pub fn new() -> Self { - Self { mem_size: 1024 } - } -} - -impl Default for NpuConfig { - fn default() -> Self { - Self::new() - } -} diff --git a/bebop/bebop/src/buckyball/frontend/decoder/decoder.rs b/bebop/bebop/src/buckyball/frontend/decoder/decoder.rs deleted file mode 100644 index aa7c11a3..00000000 --- a/bebop/bebop/src/buckyball/frontend/decoder/decoder.rs +++ /dev/null @@ -1,31 +0,0 @@ -use crate::log_backward; - -pub struct Decoder { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub is_fence: bool, -} - -impl Decoder { - pub fn new() -> Self { - Self { funct: 0, xs1: 0, xs2: 0, is_fence: false } - } - - pub fn decode_cmd(&mut self, funct: u32, xs1: u64, xs2: u64) { - self.funct = funct; - self.xs1 = xs1; - self.xs2 = xs2; - self.is_fence = funct == 31; - if self.is_fence { - log_backward!("Fence instruction decoded!"); - } else { - log_backward!("Inst decode!"); - } - } - - pub fn print_status(&self) { - println!(" [Decoder] funct={}, xs1=0x{:x}, xs2=0x{:x}, is_fence={}", - self.funct, self.xs1, self.xs2, self.is_fence); - } -} diff --git a/bebop/bebop/src/buckyball/frontend/decoder/mod.rs b/bebop/bebop/src/buckyball/frontend/decoder/mod.rs deleted file mode 100644 index 32f89d6d..00000000 --- a/bebop/bebop/src/buckyball/frontend/decoder/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -mod decoder; - -pub use decoder::Decoder; diff --git a/bebop/bebop/src/buckyball/frontend/domain_scheduler/domain_scheduler.rs b/bebop/bebop/src/buckyball/frontend/domain_scheduler/domain_scheduler.rs deleted file mode 100644 index dfbd73c6..00000000 --- a/bebop/bebop/src/buckyball/frontend/domain_scheduler/domain_scheduler.rs +++ /dev/null @@ -1,38 +0,0 @@ -use crate::log_backward; - -pub struct DomainScheduler { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub rob_id: u64, - pub domain_id: u64, -} - -impl DomainScheduler { - pub fn new() -> Self { - Self { funct: 0, xs1: 0, xs2: 0, rob_id: 0, domain_id: 0 } - } - - pub fn dispatch_cmd(&mut self, funct: u32, xs1: u64, xs2: u64, rob_id: u64) { - self.funct = funct; - self.xs1 = xs1; - self.xs2 = xs2; - self.rob_id = rob_id; - - // Allocate domain_id based on instruction type: - // - funct=24 (mvin) or funct=25 (mvout) -> domain_id=0 (MemDomain) - // - Other instructions -> domain_id=1 (other domains) - self.domain_id = match funct { - 0 => 0, // unknown instruction - 24 | 25 => 1, // mvin/mvout -> MemDomain - _ => 2, // other instructions - }; - - log_backward!("Inst dispatch (funct={}, domain_id={})!", funct, self.domain_id); - } - - pub fn print_status(&self) { - println!(" [DomainScheduler] funct={}, xs1=0x{:x}, xs2=0x{:x}, rob_id={}, domain_id={}", - self.funct, self.xs1, self.xs2, self.rob_id, self.domain_id); - } -} diff --git a/bebop/bebop/src/buckyball/frontend/domain_scheduler/mod.rs b/bebop/bebop/src/buckyball/frontend/domain_scheduler/mod.rs deleted file mode 100644 index 96d4b93b..00000000 --- a/bebop/bebop/src/buckyball/frontend/domain_scheduler/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -mod domain_scheduler; - -pub use domain_scheduler::DomainScheduler; diff --git a/bebop/bebop/src/buckyball/frontend/frontend.rs b/bebop/bebop/src/buckyball/frontend/frontend.rs deleted file mode 100644 index 5b3df0ad..00000000 --- a/bebop/bebop/src/buckyball/frontend/frontend.rs +++ /dev/null @@ -1,174 +0,0 @@ -use crate::builtin::{Sim, EventQueue}; -use crate::buckyball::top::{MemCmd, CmdResponse}; -use super::{Decoder, Rob, Rs, DomainScheduler}; -use std::sync::mpsc::Sender; -use crate::{log_forward, log_error, log_tpc}; - -pub struct Frontend { - decoder: Decoder, - rob: Rob, - rs: Rs, - domain_scheduler: DomainScheduler, - pub event_queue: EventQueue, - - // Channel to send memory commands to MemDomain - mem_cmd_tx: Option>, - - // Channel to send command responses - cmd_response_tx: Option>, - - pub funct: u32, - pub xs1: u64, - pub xs2: u64, -} - -impl Frontend { - pub fn new() -> Self { - Self { - decoder: Decoder::new(), - rob: Rob::new(), - rs: Rs::new(), - domain_scheduler: DomainScheduler::new(), - event_queue: EventQueue::new(), - mem_cmd_tx: None, - cmd_response_tx: None, - - funct: 0, - xs1: 0, - xs2: 0, - } - } - - /// Set the memory command sender channel - pub fn set_mem_cmd_sender(&mut self, sender: Sender) { - self.mem_cmd_tx = Some(sender); - } - - /// Set the command response sender channel - pub fn set_cmd_response_sender(&mut self, sender: Sender) { - self.cmd_response_tx = Some(sender); - } - - pub fn rocc_cmd(&mut self) { - let funct = self.funct; - let xs1 = self.xs1; - let xs2 = self.xs2; - - self.event_queue.push("RoccCmd", move |frontend: &mut Frontend| { - frontend.decoder.decode_cmd(funct, xs1, xs2); - }); - log_forward!("Inst decode!"); - self.enter_rob(); - } - - pub fn enter_rob(&mut self) { - let funct = self.decoder.funct; - let xs1 = self.decoder.xs1; - let xs2 = self.decoder.xs2; - let is_fence = self.decoder.is_fence; - - self.event_queue.push("EnterRob", move |frontend: &mut Frontend| { - frontend.rob.enter_rob(funct, xs1, xs2, is_fence); - }); - log_forward!("Inst enter rob!"); - - // Fence instructions don't go through dispatch/issue - if !is_fence { - // Normal instructions: send cmd_response immediately after entering ROB - if let Some(ref tx) = self.cmd_response_tx { - let cmd_response = CmdResponse { result: 0 }; - if let Err(e) = tx.send(cmd_response) { - log_error!("Failed to send CmdResponse: {}", e); - } else { - log_tpc!("Normal instruction entered ROB, sending cmd_response immediately"); - } - } - } else { - // For fence, we'll send response when ROB is empty (checked in backward) - log_forward!("Fence instruction - will wait for ROB empty"); - } - - self.dispatch_cmd(); - - } - - pub fn dispatch_cmd(&mut self) { - let funct = self.rob.funct; - let xs1 = self.rob.xs1; - let xs2 = self.rob.xs2; - let rob_id = self.rob.rob_id; - - self.event_queue.push("DispatchCmd", move |frontend: &mut Frontend| { - frontend.domain_scheduler.dispatch_cmd(funct, xs1, xs2, rob_id); - }); - log_forward!("Inst dispatch!"); - self.issue_cmd(); - } - - pub fn issue_cmd(&mut self) { - let funct = self.domain_scheduler.funct; - let xs1 = self.domain_scheduler.xs1; - let xs2 = self.domain_scheduler.xs2; - let rob_id = self.domain_scheduler.rob_id; - let domain_id = self.domain_scheduler.domain_id; - - self.event_queue.push("IssueCmd", move |frontend: &mut Frontend| { - frontend.rs.issue_cmd(funct, xs1, xs2, rob_id, domain_id); - - // Send memory command to MemDomain if it's a memory operation (funct=24 or 25) - if domain_id == 1 { - if let Some(ref tx) = frontend.mem_cmd_tx { - let mem_cmd = MemCmd {funct, xs1, xs2, rob_id, domain_id}; - if let Err(e) = tx.send(mem_cmd) { - log_error!("Failed to send MemCmd to MemDomain: {}", e); - } else { - log_tpc!("Sent MemCmd to MemDomain: funct={}, rob_id={}, domain_id={}", funct, rob_id, domain_id); - } - } - } - }); - log_forward!("Inst issue!"); - } -} - -impl Sim for Frontend { - fn forward(&mut self) { - // self.rocc_cmd(); - // self.enter_rob(); - // self.dispatch_cmd(); - // self.issue_cmd(); - } - - fn backward(&mut self) { - // 反向出栈并处理：处理队列中的所有事件 - // 每个事件函数会接收 &mut self 作为参数 - // 临时取出队列以避免借用冲突 - let mut queue = std::mem::take(&mut self.event_queue); - queue.process_all(self); - self.event_queue = queue; - - // Check if fence instruction is ready (ROB is empty) - if let Some(fence_rob_id) = self.rob.check_fence_ready() { - if let Some(ref tx) = self.cmd_response_tx { - let cmd_response = CmdResponse { result: 0 }; - if let Err(e) = tx.send(cmd_response) { - log_error!("Failed to send CmdResponse for fence: {}", e); - } else { - log_tpc!("Fence instruction completed! fence_rob_id={}, sending cmd_response", fence_rob_id); - } - } - } - } - - fn module_name(&self) -> &str { - "Frontend" - } - - fn print_status(&self) { - println!(" [Frontend] Module Status:"); - self.decoder.print_status(); - self.rob.print_status(); - self.domain_scheduler.print_status(); - self.rs.print_status(); - } -} diff --git a/bebop/bebop/src/buckyball/frontend/mod.rs b/bebop/bebop/src/buckyball/frontend/mod.rs deleted file mode 100644 index 18755af6..00000000 --- a/bebop/bebop/src/buckyball/frontend/mod.rs +++ /dev/null @@ -1,11 +0,0 @@ -mod decoder; -mod frontend; -mod rob; -mod rs; -mod domain_scheduler; - -pub use decoder::Decoder; -pub use frontend::Frontend; -pub use rob::Rob; -pub use rs::Rs; -pub use domain_scheduler::DomainScheduler; diff --git a/bebop/bebop/src/buckyball/frontend/rob/mod.rs b/bebop/bebop/src/buckyball/frontend/rob/mod.rs deleted file mode 100644 index 0c2e91f8..00000000 --- a/bebop/bebop/src/buckyball/frontend/rob/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -mod rob; - -pub use rob::Rob; diff --git a/bebop/bebop/src/buckyball/frontend/rob/rob.rs b/bebop/bebop/src/buckyball/frontend/rob/rob.rs deleted file mode 100644 index edfe8fac..00000000 --- a/bebop/bebop/src/buckyball/frontend/rob/rob.rs +++ /dev/null @@ -1,66 +0,0 @@ -use crate::log_backward; - -pub struct Rob { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub rob_id: u64, - pub is_fence: bool, - pub pending_fence_rob_id: Option, - committed_rob_id: u64, -} - -impl Rob { - pub fn new() -> Self { - Self { - funct: 0, - xs1: 0, - xs2: 0, - rob_id: 0, - is_fence: false, - pending_fence_rob_id: None, - committed_rob_id: 0, - } - } - - pub fn enter_rob(&mut self, funct: u32, xs1: u64, xs2: u64, is_fence: bool) { - self.funct = funct; - self.xs1 = xs1; - self.xs2 = xs2; - self.is_fence = is_fence; - self.rob_id += 1; - - if is_fence { - self.pending_fence_rob_id = Some(self.rob_id); - log_backward!("Fence instruction entered ROB! rob_id={}", self.rob_id); - } else { - log_backward!("Inst enter rob!"); - } - } - - - - pub fn is_empty(&self) -> bool { - self.committed_rob_id >= self.rob_id - } - - pub fn commit_instruction(&mut self) { - self.committed_rob_id += 1; - } - - pub fn check_fence_ready(&mut self) -> Option { - if let Some(fence_rob_id) = self.pending_fence_rob_id { - if self.is_empty() { - log_backward!("Fence instruction ready! ROB is empty, fence_rob_id={}", fence_rob_id); - self.pending_fence_rob_id = None; - return Some(fence_rob_id); - } - } - None - } - - pub fn print_status(&self) { - println!(" [Rob] funct={}, xs1=0x{:x}, xs2=0x{:x}, rob_id={}, is_fence={}, pending_fence={:?}, committed={}", - self.funct, self.xs1, self.xs2, self.rob_id, self.is_fence, self.pending_fence_rob_id, self.committed_rob_id); - } -} diff --git a/bebop/bebop/src/buckyball/frontend/rs/mod.rs b/bebop/bebop/src/buckyball/frontend/rs/mod.rs deleted file mode 100644 index 5a89c733..00000000 --- a/bebop/bebop/src/buckyball/frontend/rs/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -mod rs; - -pub use rs::Rs; diff --git a/bebop/bebop/src/buckyball/frontend/rs/rs.rs b/bebop/bebop/src/buckyball/frontend/rs/rs.rs deleted file mode 100644 index 10a8f31e..00000000 --- a/bebop/bebop/src/buckyball/frontend/rs/rs.rs +++ /dev/null @@ -1,29 +0,0 @@ -use crate::log_backward; - -pub struct Rs { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub rob_id: u64, - pub domain_id: u64, -} - -impl Rs { - pub fn new() -> Self { - Self { funct: 0, xs1: 0, xs2: 0, rob_id: 0, domain_id: 0 } - } - - pub fn issue_cmd(&mut self, funct: u32, xs1: u64, xs2: u64, rob_id: u64, domain_id: u64) { - self.funct = funct; - self.xs1 = xs1; - self.xs2 = xs2; - self.rob_id = rob_id; - self.domain_id = domain_id; - log_backward!("Inst issue!"); - } - - pub fn print_status(&self) { - println!(" [Rs] funct={}, xs1=0x{:x}, xs2=0x{:x}, rob_id={}, domain_id={}", - self.funct, self.xs1, self.xs2, self.rob_id, self.domain_id); - } -} diff --git a/bebop/bebop/src/buckyball/memdomain/bank/bank.rs b/bebop/bebop/src/buckyball/memdomain/bank/bank.rs deleted file mode 100644 index 763b57fd..00000000 --- a/bebop/bebop/src/buckyball/memdomain/bank/bank.rs +++ /dev/null @@ -1,141 +0,0 @@ -// Bank operation state -use crate::log_backward; - -#[derive(Debug, Clone, Copy, PartialEq)] -pub enum BankState { - Idle, - SramReq, // Issuing SRAM request - SramWait, // Waiting for SRAM response -} - -// Bank configuration (unified for all banks) -const NUM_BANKS: usize = 12; // Total number of banks (e.g., 4 SP + 8 ACC) -const BANK_ENTRIES: usize = 4096; // Entries per bank -const ENTRY_BYTES: usize = 16; // 16 bytes per entry (128 bits) - -pub struct Bank { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub bank_id: u32, - - // State machine - pub state: BankState, - - // Cached instruction parameters - pub is_load: bool, - pub is_store: bool, - pub sp_bank: u32, - pub sp_bank_addr: u32, - pub iter: u32, - - // SRAM access tracking - pub sram_count: u32, // Current iteration counter - pub data_buffer: Vec, // Data buffer for streaming - - // Actual storage: Unified banks (NUM_BANKS x BANK_ENTRIES x ENTRY_BYTES) - banks: Vec>>, -} - -impl Bank { - pub fn new() -> Self { - // Initialize all banks: NUM_BANKS x BANK_ENTRIES x ENTRY_BYTES - let banks = (0..NUM_BANKS) - .map(|_| { - (0..BANK_ENTRIES) - .map(|_| vec![0u8; ENTRY_BYTES]) - .collect() - }) - .collect(); - - Self { - funct: 0, - xs1: 0, - xs2: 0, - bank_id: 0, - state: BankState::Idle, - is_load: false, - is_store: false, - sp_bank: 0, - sp_bank_addr: 0, - iter: 0, - sram_count: 0, - data_buffer: Vec::new(), - banks, - } - } - - pub fn bank_read(&mut self, sp_bank: u32, sp_bank_addr: u32, iter: u32) { - self.is_load = false; - self.is_store = true; - self.sp_bank = sp_bank; - self.sp_bank_addr = sp_bank_addr; - self.iter = iter; - - // Initialize state - self.state = BankState::SramReq; - self.sram_count = 0; - self.bank_id += 1; - - // MVOUT: Read data from bank (to DMA) - log_backward!( - "Bank READ: mvout (bank_id={}, bank={}, addr=0x{:x}, iter={})", - self.bank_id, self.sp_bank, self.sp_bank_addr, self.iter - ); - } - - /// Read one entry from bank - pub fn read_entry(&self, bank: u32, addr: u32) -> Vec { - let bank_idx = bank as usize; - let addr_idx = addr as usize; - - if bank_idx < NUM_BANKS && addr_idx < BANK_ENTRIES { - self.banks[bank_idx][addr_idx].clone() - } else { - log_backward!("Bank READ ERROR: addr out of range (bank={}, addr={})", bank, addr); - vec![0u8; ENTRY_BYTES] - } - } - - pub fn bank_write(&mut self, sp_bank: u32, sp_bank_addr: u32, iter: u32) { - self.is_load = true; - self.is_store = false; - self.sp_bank = sp_bank; - self.sp_bank_addr = sp_bank_addr; - self.iter = iter; - - // Initialize state - self.state = BankState::SramReq; - self.sram_count = 0; - self.bank_id += 1; - - // MVIN: Write data to bank (from DMA) - log_backward!( - "Bank WRITE: mvin (bank_id={}, bank={}, addr=0x{:x}, iter={})", - self.bank_id, self.sp_bank, self.sp_bank_addr, self.iter - ); - } - - /// Write one entry to bank - pub fn write_entry(&mut self, bank: u32, addr: u32, data: Vec) { - let bank_idx = bank as usize; - let addr_idx = addr as usize; - - if bank_idx < NUM_BANKS && addr_idx < BANK_ENTRIES { - // Ensure data is correct size - if data.len() == ENTRY_BYTES { - self.banks[bank_idx][addr_idx] = data; - log_backward!("Bank WRITE: bank[{}][0x{:x}] = {} bytes", bank, addr, ENTRY_BYTES); - } else { - log_backward!("Bank WRITE ERROR: data size mismatch (expected {}, got {})", ENTRY_BYTES, data.len()); - } - } else { - log_backward!("Bank WRITE ERROR: addr out of range (bank={}, addr={})", bank, addr); - } - } - - pub fn print_status(&self) { - println!(" [Bank] bank_id={}, state={:?}, sp_bank={}, sp_bank_addr=0x{:x}, iter={}", - self.bank_id, self.state, self.sp_bank, self.sp_bank_addr, self.iter); - } -} diff --git a/bebop/bebop/src/buckyball/memdomain/bank/mod.rs b/bebop/bebop/src/buckyball/memdomain/bank/mod.rs deleted file mode 100644 index d269ac13..00000000 --- a/bebop/bebop/src/buckyball/memdomain/bank/mod.rs +++ /dev/null @@ -1,2 +0,0 @@ -mod bank; -pub use bank::Bank; diff --git a/bebop/bebop/src/buckyball/memdomain/decoder/decoder.rs b/bebop/bebop/src/buckyball/memdomain/decoder/decoder.rs deleted file mode 100644 index d35581cf..00000000 --- a/bebop/bebop/src/buckyball/memdomain/decoder/decoder.rs +++ /dev/null @@ -1,83 +0,0 @@ -use crate::log_backward; - -pub struct Decoder { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - - // Decoded instruction fields - pub is_load: bool, - pub is_store: bool, - pub mem_addr: u64, // Memory address from xs1 (rs1[31:0]) - pub sp_addr: u32, // Scratchpad address (rs2[14:0]) - linear address - pub sp_bank: u32, // Bank ID extracted from sp_addr - pub sp_bank_addr: u32, // Address within bank extracted from sp_addr - pub iter: u32, // Number of iterations (rs2[24:15]) - pub stride: u32, // Stride/col_stride (rs2[33:24]) -} - -impl Decoder { - pub fn new() -> Self { - Self { - funct: 0, - xs1: 0, - xs2: 0, - is_load: false, - is_store: false, - mem_addr: 0, - sp_addr: 0, - sp_bank: 0, - sp_bank_addr: 0, - iter: 0, - stride: 0, - } - } - - pub fn decode_cmd(&mut self, funct: u32, xs1: u64, xs2: u64) { - self.funct = funct; - self.xs1 = xs1; - self.xs2 = xs2; - - // Decode instruction type - self.is_load = funct == 24; // mvin - self.is_store = funct == 25; // mvout - - // Parse xs1: memory address (DRAM address) - // rs1[31:0] = base_dram_addr - self.mem_addr = xs1 & 0xFFFFFFFF; - - // Parse xs2 fields (matching C implementation): - // rs2[14:0] = base_sp_addr (15 bits) - // rs2[24:15] = iter (10 bits) - // rs2[33:24] = col_stride/stride (10 bits) - self.sp_addr = (xs2 & 0x7FFF) as u32; // bits [14:0] - self.iter = ((xs2 >> 15) & 0x3FF) as u32; // bits [24:15] - self.stride = ((xs2 >> 24) & 0x3FF) as u32; // bits [33:24] - - // Parse sp_addr into bank and bank_addr - // Assuming: 12 banks total, 4096 entries per bank - // sp_bank_addr_bits = log2(4096) = 12 - // sp_bank_bits = log2(12) = 4 (rounded up) - const SP_BANK_ADDR_BITS: u32 = 12; - self.sp_bank_addr = self.sp_addr & ((1 << SP_BANK_ADDR_BITS) - 1); // bits [11:0] - self.sp_bank = self.sp_addr >> SP_BANK_ADDR_BITS; // bits [14:12] - - // funct=24: mvin, funct=25: mvout - match funct { - 24 => log_backward!( - "MemDomain decode: mvin (mem_addr=0x{:x}, sp_addr=0x{:x} [bank={}, addr=0x{:x}], iter={}, col_stride={})", - self.mem_addr, self.sp_addr, self.sp_bank, self.sp_bank_addr, self.iter, self.stride - ), - 25 => log_backward!( - "MemDomain decode: mvout (mem_addr=0x{:x}, sp_addr=0x{:x} [bank={}, addr=0x{:x}], iter={}, stride={})", - self.mem_addr, self.sp_addr, self.sp_bank, self.sp_bank_addr, self.iter, self.stride - ), - _ => log_backward!("MemDomain decode: unknown funct={}", funct), - } - } - - pub fn print_status(&self) { - println!(" [Decoder] funct={}, mem_addr=0x{:x}, sp_addr=0x{:x} [bank={}, addr=0x{:x}], iter={}, stride={}, is_load={}, is_store={}", - self.funct, self.mem_addr, self.sp_addr, self.sp_bank, self.sp_bank_addr, self.iter, self.stride, self.is_load, self.is_store); - } -} diff --git a/bebop/bebop/src/buckyball/memdomain/decoder/mod.rs b/bebop/bebop/src/buckyball/memdomain/decoder/mod.rs deleted file mode 100644 index 3df94419..00000000 --- a/bebop/bebop/src/buckyball/memdomain/decoder/mod.rs +++ /dev/null @@ -1,2 +0,0 @@ -mod decoder; -pub use decoder::Decoder; diff --git a/bebop/bebop/src/buckyball/memdomain/memdomain.rs b/bebop/bebop/src/buckyball/memdomain/memdomain.rs deleted file mode 100644 index 38e427c8..00000000 --- a/bebop/bebop/src/buckyball/memdomain/memdomain.rs +++ /dev/null @@ -1,177 +0,0 @@ -use crate::builtin::{Sim, EventQueue}; -use super::{Decoder, Reader, Writer, Bank, OutController}; -use crate::{log_forward}; -use crate::buckyball::top::{DmaRequest, DmaResponse}; -use std::sync::mpsc::{Sender, Receiver}; - -pub struct MemDomain { - decoder: Decoder, - reader: Reader, - writer: Writer, - bank: Bank, - out_ctrl: OutController, - pub event_queue: EventQueue, - - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub rob_id: u32, // ROB ID for tracking instruction completion - - // DMA channels - dma_req_tx: Option>, - dma_resp_rx: Option>, -} - -impl MemDomain { - pub fn new() -> Self { - Self { - decoder: Decoder::new(), - reader: Reader::new(), - writer: Writer::new(), - bank: Bank::new(), - out_ctrl: OutController::new(), - event_queue: EventQueue::new(), - - funct: 0, - xs1: 0, - xs2: 0, - rob_id: 0, - - dma_req_tx: None, - dma_resp_rx: None, - } - } - - pub fn set_dma_channels(&mut self, req_tx: Sender, resp_rx: Receiver) { - self.dma_req_tx = Some(req_tx.clone()); - self.dma_resp_rx = Some(resp_rx); - self.reader.set_dma_sender(req_tx.clone()); - self.writer.set_dma_sender(req_tx); - } - - pub fn mem_cmd(&mut self) { - let funct = self.funct; - let xs1 = self.xs1; - let xs2 = self.xs2; - - println!("[MemDomain] mem_cmd called: funct={}, xs1=0x{:x}, xs2=0x{:x}", funct, xs1, xs2); - - self.event_queue.push("MemCmd", move |memdomain: &mut MemDomain| { - memdomain.decoder.decode_cmd(funct, xs1, xs2); - }); - self.outside_schedule(funct); - } - - pub fn outside_schedule(&mut self, funct: u32) { - let mem_addr = self.decoder.mem_addr; - let is_load = self.decoder.is_load; - let is_store = self.decoder.is_store; - let bank_id = self.decoder.sp_bank; - let sp_bank_addr = self.decoder.sp_bank_addr; - let iter = self.decoder.iter; - let stride = self.decoder.stride; - - println!("[MemDomain] outside_schedule: is_load={}, is_store={}, mem_addr=0x{:x}", is_load, is_store, mem_addr); - - self.event_queue.push("ChooseDma", move |memdomain: &mut MemDomain| { - memdomain.out_ctrl.dma_schedule( bank_id, is_load, is_store, - mem_addr, sp_bank_addr, iter, stride); - }); - log_forward!("MemDomain: Drive DMA (mem_addr=0x{:x}, iter={}, stride={})", - mem_addr, iter, stride); - if funct == 24 { - println!("[MemDomain] Calling dma_read()"); - self.dma_read(); - } else if funct == 25 { - println!("[MemDomain] Calling dma_write()"); - self.dma_write(); - } else { - println!("[MemDomain] Not Calling dma"); - } - } - - pub fn dma_read(&mut self) { - // MVIN: DMA read from memory - let mem_addr = self.out_ctrl.mem_addr; - let iter = self.out_ctrl.iter; - let stride = self.out_ctrl.stride; - - println!("[MemDomain] dma_read: pushing DmaRead event to queue (mem_addr=0x{:x})", mem_addr); - - self.event_queue.push("DmaRead", move |memdomain: &mut MemDomain| { - println!("[MemDomain] DmaRead event executing, calling reader.dma_read()"); - memdomain.reader.dma_read(mem_addr, iter, stride); - }); - log_forward!("MemDomain: DMA read request"); - self.bank_write(); - } - - pub fn dma_write(&mut self) { - // MVOUT: First read from bank, then DMA write to memory - self.bank_read(); - - // MVOUT: DMA write to memory after reading from bank - let mem_addr = self.out_ctrl.mem_addr; - let iter = self.out_ctrl.iter; - let stride = self.out_ctrl.stride; - - self.event_queue.push("DmaWrite", move |memdomain: &mut MemDomain| { - memdomain.writer.dma_write(mem_addr, iter, stride); - }); - log_forward!("MemDomain: DMA write request"); - } - - pub fn bank_read(&mut self) { - // MVOUT: Read data from bank - let bank_id = self.out_ctrl.bank_id; - let sp_bank_addr = self.out_ctrl.sp_bank_addr; - let iter = self.out_ctrl.iter; - - self.event_queue.push("BankRead", move |memdomain: &mut MemDomain| { - memdomain.bank.bank_read(bank_id, sp_bank_addr, iter); - }); - log_forward!("MemDomain: Bank read for mvout"); - } - - pub fn bank_write(&mut self) { - // MVIN: Write data to bank from DMA - let bank_id = self.out_ctrl.bank_id; - let sp_bank_addr = self.out_ctrl.sp_bank_addr; - let iter = self.out_ctrl.iter; - - self.event_queue.push("BankWrite", move |memdomain: &mut MemDomain| { - memdomain.bank.bank_write(bank_id, sp_bank_addr, iter); - }); - log_forward!("MemDomain: Bank write for mvin"); - } - -} - -impl Sim for MemDomain { - fn forward(&mut self) { - // Forward phase is triggered by external command - // Actual forward logic is in mem_cmd() - } - - fn backward(&mut self) { - // Process all events in the queue (LIFO) - println!("[MemDomain] backward: processing event queue"); - let mut queue = std::mem::take(&mut self.event_queue); - queue.process_all(self); - self.event_queue = queue; - println!("[MemDomain] backward: event queue processed"); - } - - fn module_name(&self) -> &str { - "MemDomain" - } - - fn print_status(&self) { - println!(" [MemDomain] Module Status:"); - self.decoder.print_status(); - self.out_ctrl.print_status(); - self.reader.print_status(); - self.writer.print_status(); - self.bank.print_status(); - } -} diff --git a/bebop/bebop/src/buckyball/memdomain/mod.rs b/bebop/bebop/src/buckyball/memdomain/mod.rs deleted file mode 100644 index 279181ac..00000000 --- a/bebop/bebop/src/buckyball/memdomain/mod.rs +++ /dev/null @@ -1,13 +0,0 @@ -mod decoder; -mod reader; -mod writer; -mod bank; -mod out_controller; -mod memdomain; - -pub use decoder::Decoder; -pub use reader::Reader; -pub use writer::Writer; -pub use bank::Bank; -pub use out_controller::OutController; -pub use memdomain::MemDomain; diff --git a/bebop/bebop/src/buckyball/memdomain/out_controller/controller.rs b/bebop/bebop/src/buckyball/memdomain/out_controller/controller.rs deleted file mode 100644 index f66db95b..00000000 --- a/bebop/bebop/src/buckyball/memdomain/out_controller/controller.rs +++ /dev/null @@ -1,52 +0,0 @@ -use crate::log_backward; - -pub struct OutController { - pub bank_id: u32, - - // Completion tracking - pub is_load: bool, - pub is_store: bool, - pub mem_addr: u64, - pub sp_bank_addr: u32, - pub iter: u32, - pub stride: u32, - pub task_complete: bool, - pub rob_id: u32, // ROB ID for tracking instruction completion -} - -impl OutController { - pub fn new() -> Self { - Self { - bank_id: 0, - is_load: false, - is_store: false, - mem_addr: 0, - sp_bank_addr: 0, - iter: 0, - stride: 0, - task_complete: false, - rob_id: 0, - } - } - - pub fn dma_schedule(&mut self, bank_id: u32, is_load: bool, is_store: bool, - mem_addr: u64, sp_bank_addr: u32, iter: u32, stride: u32) { - - self.bank_id = bank_id; - - self.is_load = is_load; - self.is_store = is_store; - - self.mem_addr = mem_addr; - self.sp_bank_addr = sp_bank_addr; - self.iter = iter; - self.stride = stride; - } - - pub fn print_status(&self) { - println!(" [OutController] bank_id={}, task_complete={}, rob_id={}, op={}, mem_addr=0x{:x}, sp_bank_addr=0x{:x}, iter={}, stride={}", - self.bank_id, self.task_complete, self.rob_id, - if self.is_load { "mvin" } else if self.is_store { "mvout" } else { "idle" }, - self.mem_addr, self.sp_bank_addr, self.iter, self.stride); - } -} diff --git a/bebop/bebop/src/buckyball/memdomain/out_controller/mod.rs b/bebop/bebop/src/buckyball/memdomain/out_controller/mod.rs deleted file mode 100644 index 0c547d8a..00000000 --- a/bebop/bebop/src/buckyball/memdomain/out_controller/mod.rs +++ /dev/null @@ -1,2 +0,0 @@ -mod controller; -pub use controller::OutController; diff --git a/bebop/bebop/src/buckyball/memdomain/reader/mod.rs b/bebop/bebop/src/buckyball/memdomain/reader/mod.rs deleted file mode 100644 index 1661cf05..00000000 --- a/bebop/bebop/src/buckyball/memdomain/reader/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -mod reader; - -pub use reader::Reader; diff --git a/bebop/bebop/src/buckyball/memdomain/reader/reader.rs b/bebop/bebop/src/buckyball/memdomain/reader/reader.rs deleted file mode 100644 index edfb1594..00000000 --- a/bebop/bebop/src/buckyball/memdomain/reader/reader.rs +++ /dev/null @@ -1,60 +0,0 @@ -use crate::log_backward; -use crate::buckyball::top::DmaRequest; -use std::sync::mpsc::Sender; - -pub struct Reader { - pub mem_addr: u64, // Memory address from xs1 (rs1[31:0]) - // pub bank_id: u32, // Bank ID extracted from sp_addr - // pub bank_addr: u32, // Address within bank extracted from sp_addr - pub iter: u32, // Number of iterations (rs2[24:15]) - pub stride: u32, // Stride/col_stride (rs2[33:24]) - - dma_req_tx: Option>, -} - -impl Reader { - pub fn new() -> Self { - Self { - mem_addr: 0, - iter: 0, - stride: 0, - dma_req_tx: None, - } - } - - pub fn set_dma_sender(&mut self, sender: Sender) { - self.dma_req_tx = Some(sender); - } - - pub fn dma_read(&mut self, mem_addr: u64, iter: u32, stride: u32) { - self.mem_addr = mem_addr; - self.iter = iter; - self.stride = stride; - - println!("[Reader] dma_read called: mem_addr=0x{:x}, iter={}, stride={}", mem_addr, iter, stride); - - // Send DMA read request via channel - if let Some(ref tx) = self.dma_req_tx { - println!("[Reader] dma_req_tx channel exists, creating DmaRequest::Read"); - // For now, read 8 bytes (64-bit word) - if mem_addr == 0 { - eprintln!("[Reader] ERROR: mem_addr is 0!"); - return; - } - let req = DmaRequest::Read { addr: mem_addr, size: 8 }; - println!("[Reader] Sending DmaRequest::Read to channel..."); - if let Err(e) = tx.send(req) { - eprintln!("[Reader] ERROR: Failed to send DMA read request: {}", e); - } else { - println!("[Reader] SUCCESS: Sent DMA read request to channel: addr=0x{:x}, size=8", mem_addr); - } - } else { - println!("[Reader] ERROR: dma_req_tx channel is None!"); - } - } - - pub fn print_status(&self) { - println!(" [Reader] mem_addr=0x{:x}, iter={}, stride={}", - self.mem_addr, self.iter, self.stride); - } -} diff --git a/bebop/bebop/src/buckyball/memdomain/writer/mod.rs b/bebop/bebop/src/buckyball/memdomain/writer/mod.rs deleted file mode 100644 index d93ae306..00000000 --- a/bebop/bebop/src/buckyball/memdomain/writer/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -mod writer; - -pub use writer::Writer; diff --git a/bebop/bebop/src/buckyball/memdomain/writer/writer.rs b/bebop/bebop/src/buckyball/memdomain/writer/writer.rs deleted file mode 100644 index fbcb827e..00000000 --- a/bebop/bebop/src/buckyball/memdomain/writer/writer.rs +++ /dev/null @@ -1,53 +0,0 @@ -use crate::log_backward; -use crate::buckyball::top::DmaRequest; -use std::sync::mpsc::Sender; - -pub struct Writer { - pub mem_addr: u64, // Memory address from xs1 (rs1[31:0]) - pub bank_id: u32, // Bank ID extracted from sp_addr - pub bank_addr: u32, // Address within bank extracted from sp_addr - pub iter: u32, // Number of iterations (rs2[24:15]) - pub stride: u32, // Stride/col_stride (rs2[33:24]) - - dma_req_tx: Option>, -} - -impl Writer { - pub fn new() -> Self { - Self { - mem_addr: 0, - bank_id: 0, - bank_addr: 0, - iter: 0, - stride: 0, - dma_req_tx: None, - } - } - - pub fn set_dma_sender(&mut self, sender: Sender) { - self.dma_req_tx = Some(sender); - } - - pub fn dma_write(&mut self, mem_addr: u64, iter: u32, stride: u32) { - self.mem_addr = mem_addr; - self.iter = iter; - self.stride = stride; - - // Send DMA write request via channel - if let Some(ref tx) = self.dma_req_tx { - // For now, write dummy data (0x0) as 8 bytes (64-bit word) - // In a real implementation, this would read data from the bank - let req = DmaRequest::Write { addr: mem_addr, data: 0x0, size: 8 }; - if let Err(e) = tx.send(req) { - eprintln!("[Writer] Failed to send DMA write request: {}", e); - } else { - println!("[Writer] Sent DMA write request: addr=0x{:x}, data=0x0, size=8", mem_addr); - } - } - } - - pub fn print_status(&self) { - println!(" [Writer] mem_addr=0x{:x}, bank_id={}, bank_addr=0x{:x}, iter={}, stride={}", - self.mem_addr, self.bank_id, self.bank_addr, self.iter, self.stride); - } -} diff --git a/bebop/bebop/src/buckyball/mod.rs b/bebop/bebop/src/buckyball/mod.rs deleted file mode 100644 index 49b7f6af..00000000 --- a/bebop/bebop/src/buckyball/mod.rs +++ /dev/null @@ -1,16 +0,0 @@ -/// Buckyball - Core NPU modules -/// -/// - `top` - 顶层模块 -/// - `config` - NPU 配置 -/// - `frontend` - 前端模块 -/// - `memdomain` - 内存域模块 - -pub mod config; -pub mod frontend; -pub mod memdomain; -pub mod top; - -pub use crate::builtin::Sim; -pub use config::NpuConfig; -pub use memdomain::MemDomain; -pub use top::Top; diff --git a/bebop/bebop/src/buckyball/top.rs b/bebop/bebop/src/buckyball/top.rs deleted file mode 100644 index 5d4c8ee1..00000000 --- a/bebop/bebop/src/buckyball/top.rs +++ /dev/null @@ -1,163 +0,0 @@ -/// Top Module - NPU top-level -use crate::builtin::Sim; -use crate::buckyball::frontend::Frontend; -use crate::buckyball::memdomain::MemDomain; -use std::sync::mpsc::{channel, Receiver, Sender}; -use std::sync::{Arc, Mutex}; -use crate::log_tpc; - -/// RoCC command from host -pub struct RoccCmd { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, -} - -/// Command response notification (sent from Frontend to CmdHandler) -pub struct CmdResponse { - pub result: u64, -} - -/// Memory command sent from Frontend to MemDomain -#[derive(Debug, Clone)] -pub struct MemCmd { - pub funct: u32, - pub xs1: u64, - pub xs2: u64, - pub rob_id: u64, - pub domain_id: u64, -} - -/// DMA request types -#[derive(Debug, Clone)] -pub enum DmaRequest { - Read { addr: u64, size: u32 }, - Write { addr: u64, data: u64, size: u32 }, -} - -/// DMA response types -#[derive(Debug, Clone)] -pub enum DmaResponse { - ReadComplete { data: u64 }, - WriteComplete, - Error(String), -} - -/// Top - NPU top-level module -pub struct Top { - name: String, - frontend: Frontend, - memdomain: MemDomain, - - // RoCC command channel (host -> Top) - cmd_rx: Receiver, - cmd_tx: Sender, - - // Memory command channel (Frontend -> MemDomain) - #[allow(dead_code)] - mem_cmd_tx: Sender, - mem_cmd_rx: Receiver, - - // Command response channel (Frontend -> CmdHandler) - pub cmd_response_rx: Arc>>, - cmd_response_tx: Sender, - - // DMA request/response channels (MemDomain <-> ConnectionHandler) - pub dma_req_rx: Arc>>, - pub dma_resp_tx: Arc>>, -} - -impl Top { - pub fn new(name: impl Into) -> Self { - let (cmd_tx, cmd_rx) = channel(); - let (mem_cmd_tx, mem_cmd_rx) = channel(); - let (cmd_response_tx, cmd_response_rx) = channel(); - let (dma_req_tx, dma_req_rx) = channel(); - let (dma_resp_tx, dma_resp_rx) = channel(); - - let mut frontend = Frontend::new(); - frontend.set_mem_cmd_sender(mem_cmd_tx.clone()); - frontend.set_cmd_response_sender(cmd_response_tx.clone()); - - let mut memdomain = MemDomain::new(); - memdomain.set_dma_channels(dma_req_tx, dma_resp_rx); - - Self { - name: name.into(), - frontend, - memdomain, - cmd_rx, - cmd_tx, - mem_cmd_tx, - mem_cmd_rx, - cmd_response_rx: Arc::new(Mutex::new(cmd_response_rx)), - cmd_response_tx, - dma_req_rx: Arc::new(Mutex::new(dma_req_rx)), - dma_resp_tx: Arc::new(Mutex::new(dma_resp_tx)), - } - } - - pub fn frontend_cmd(&mut self, funct: u32, xs1: u64, xs2: u64) { - self.frontend.funct = funct; - self.frontend.xs1 = xs1; - self.frontend.xs2 = xs2; - self.frontend.rocc_cmd(); - } - - pub fn memdomain_cmd(&mut self, funct: u32, xs1: u64, xs2: u64, rob_id: u64, domain_id: u64) { - self.memdomain.funct = funct; - self.memdomain.xs1 = xs1; - self.memdomain.xs2 = xs2; - self.memdomain.mem_cmd(); - } - - /// Get a sender for sending RoCC commands - pub fn get_cmd_sender(&self) -> Sender { - self.cmd_tx.clone() - } - - /// Get command response receiver for CmdHandler - pub fn get_cmd_response_receiver(&self) -> Arc>> { - self.cmd_response_rx.clone() - } - - /// Get DMA channel handles for ConnectionHandler - pub fn get_dma_channels(&self) -> (Arc>>, Arc>>) { - (self.dma_req_rx.clone(), self.dma_resp_tx.clone()) - } -} - -impl Sim for Top { - fn forward(&mut self) { - // 1. Receive RoCC command from host - if let Ok(rocc_cmd) = self.cmd_rx.try_recv() { - self.frontend_cmd(rocc_cmd.funct, rocc_cmd.xs1, rocc_cmd.xs2); - } - - // 2. Check if Frontend sent memory commands to MemDomain - if let Ok(mem_cmd) = self.mem_cmd_rx.try_recv() { - log_tpc!("[Top] Received MemCmd from Frontend: funct={}, xs1=0x{:x}, xs2=0x{:x}, rob_id={}, domain_id={}", - mem_cmd.funct, mem_cmd.xs1, mem_cmd.xs2, mem_cmd.rob_id, mem_cmd.domain_id); - self.memdomain_cmd(mem_cmd.funct, mem_cmd.xs1, mem_cmd.xs2, mem_cmd.rob_id, mem_cmd.domain_id); - } - - // Debug: print queue status - self.frontend.event_queue.print_status("Frontend"); - self.memdomain.event_queue.print_status("MemDomain"); - } - - fn backward(&mut self) { - self.frontend.backward(); - self.memdomain.backward(); - - // Print all module status - println!("\n=== Module Status ==="); - self.frontend.print_status(); - self.memdomain.print_status(); - println!("====================\n"); - } - - fn module_name(&self) -> &str { - &self.name - } -} diff --git a/bebop/bebop/src/builtin/event.rs b/bebop/bebop/src/builtin/event.rs deleted file mode 100644 index 8066739f..00000000 --- a/bebop/bebop/src/builtin/event.rs +++ /dev/null @@ -1,91 +0,0 @@ -use std::collections::VecDeque; - -/// 事件结构：包含事件名称和回调函数 -struct EventItem { - name: String, - callback: Box, -} - -/// 事件队列，用于模块内部的事件管理 -/// 泛型参数 T 是事件回调函数接收的上下文类型（通常是模块自身） -/// 正向压栈（push），反向出栈（pop）并执行回调函数 -pub struct EventQueue { - queue: VecDeque>, -} - -impl EventQueue { - /// 创建新的事件队列 - pub fn new() -> Self { - Self { - queue: VecDeque::new(), - } - } - - /// 正向压栈：将事件函数压入队列尾部 - /// 事件函数接收一个可变引用参数，可以访问和修改模块状态 - pub fn push(&mut self, name: impl Into, event: F) - where - F: FnOnce(&mut T) + 'static, - { - self.queue.push_back(EventItem { - name: name.into(), - callback: Box::new(event), - }); - } - - /// 反向出栈并处理：从队列尾部弹出事件（LIFO）并执行函数 - pub fn pop_and_process(&mut self, context: &mut T) -> bool { - if let Some(event_item) = self.queue.pop_back() { - (event_item.callback)(context); // 执行事件函数，传入上下文 - true - } else { - false - } - } - - /// 处理队列中的所有事件 - pub fn process_all(&mut self, context: &mut T) { - while self.pop_and_process(context) {} - } - - /// 获取队列长度 - pub fn len(&self) -> usize { - self.queue.len() - } - - /// 检查队列是否为空 - pub fn is_empty(&self) -> bool { - self.queue.is_empty() - } - - /// 清空队列 - pub fn clear(&mut self) { - self.queue.clear(); - } - - /// 打印队列内部状态 - pub fn print_status(&self, module_name: &str) { - println!("╔═══════════════════════════════════════════════════════════════="); - println!("║ EventQueue Status - {}", module_name); - println!("╠═══════════════════════════════════════════════════════════════="); - println!("║ Queue Length: {}", self.queue.len()); - println!("║ Is Empty: {}", self.queue.is_empty()); - println!("║ Capacity: {}", self.queue.capacity()); - println!("╠═══════════════════════════════════════════════════════════════="); - if self.queue.is_empty() { - println!("║ [Queue is empty]"); - } else { - println!("║ Events in queue (from front to back):"); - for (idx, event_item) in self.queue.iter().enumerate() { - println!("║ [{}] {}", idx, event_item.name); - } - } - println!("╚═══════════════════════════════════════════════════════════════="); - } -} - -impl Default for EventQueue { - fn default() -> Self { - Self::new() - } -} diff --git a/bebop/bebop/src/builtin/interface.rs b/bebop/bebop/src/builtin/interface.rs deleted file mode 100644 index 3fc3ed25..00000000 --- a/bebop/bebop/src/builtin/interface.rs +++ /dev/null @@ -1,49 +0,0 @@ -/// 调用 Interface 的函数指针的宏 -/// -/// # 示例 -/// ``` -/// // 调用静态函数 -/// call_interface!(interface, fn(u32, u64, u64), arg1, arg2, arg3); -/// -/// // 调用方法（需要传入 self） -/// call_interface!(interface, fn(&mut Self, u32, u64, u64), &mut obj, arg1, arg2, arg3); -/// ``` -#[macro_export] -macro_rules! call_interface { - ($interface:expr, fn($($arg_type:ty),*) $(-> $ret:ty)?, $($arg:expr),*) => { - if !$interface.function.is_null() { - unsafe { - let f: fn($($arg_type),*) $(-> $ret)? = std::mem::transmute($interface.function); - f($($arg),*) - } - } - }; -} - -pub struct Interface { - pub name: String, - pub latency: u32, - pub ready: fn() -> bool, - pub function: *const (), -} - -impl Interface { - pub fn new(name: impl Into, latency: u32) -> Self { - fn default_ready() -> bool { true } - - Self { - name: name.into(), - latency, - ready: default_ready, - function: std::ptr::null(), - } - } - - pub fn ready(&self) -> bool { - (self.ready)() - } - - pub fn set_function(&mut self, f: *const ()) { - self.function = f; - } -} diff --git a/bebop/bebop/src/builtin/mod.rs b/bebop/bebop/src/builtin/mod.rs deleted file mode 100644 index 5962a0fb..00000000 --- a/bebop/bebop/src/builtin/mod.rs +++ /dev/null @@ -1,9 +0,0 @@ -pub mod module; -pub mod sim; -pub mod interface; -pub mod event; - -pub use module::Module; -pub use sim::Sim; -pub use interface::Interface; -pub use event::EventQueue; diff --git a/bebop/bebop/src/builtin/module.rs b/bebop/bebop/src/builtin/module.rs deleted file mode 100644 index 25482ae6..00000000 --- a/bebop/bebop/src/builtin/module.rs +++ /dev/null @@ -1,3 +0,0 @@ -pub trait Module { - fn module_name(&self) -> &str; -} diff --git a/bebop/bebop/src/builtin/sim.rs b/bebop/bebop/src/builtin/sim.rs deleted file mode 100644 index 24dc43bf..00000000 --- a/bebop/bebop/src/builtin/sim.rs +++ /dev/null @@ -1,11 +0,0 @@ -pub trait Sim { - fn module_name(&self) -> &str; - fn forward(&mut self); - fn backward(&mut self); - - /// Optional method to print module status - /// Override this to print module-specific state - fn print_status(&self) { - // Default: do nothing - } -} diff --git a/bebop/bebop/src/lib.rs b/bebop/bebop/src/lib.rs deleted file mode 100644 index 113d36ce..00000000 --- a/bebop/bebop/src/lib.rs +++ /dev/null @@ -1,19 +0,0 @@ -/// Bebop - Accelerator simulator for RISC-V host -/// -/// This library provides socket-based communication between host (RISC-V ISA simulator) -/// and custom accelerator implementations. -#[macro_use] -pub mod builtin; -pub mod buckyball; -#[macro_use] -pub mod simulator; - -// Re-export log configuration functions for convenience -pub use simulator::utils::log_config::{ - set_forward_log, set_backward_log, - is_forward_log_enabled, is_backward_log_enabled, - enable_all_logs, disable_all_logs, -}; - -pub use buckyball::{NpuConfig, Top}; -pub use simulator::{Simulator, StepMode}; diff --git a/bebop/bebop/src/simulator/mod.rs b/bebop/bebop/src/simulator/mod.rs deleted file mode 100644 index 4aca9248..00000000 --- a/bebop/bebop/src/simulator/mod.rs +++ /dev/null @@ -1,7 +0,0 @@ -/// Simulator module -#[macro_use] -pub mod utils; -pub mod server; -pub mod simulator; - -pub use simulator::{Simulator, StepMode}; diff --git a/bebop/bebop/src/simulator/server/cmd.rs b/bebop/bebop/src/simulator/server/cmd.rs deleted file mode 100644 index d83692ed..00000000 --- a/bebop/bebop/src/simulator/server/cmd.rs +++ /dev/null @@ -1,80 +0,0 @@ -/// CMD channel handler - receives RoCC commands from host and sends to Top -use std::io::{Read, Write}; -use std::net::TcpStream; -use std::sync::mpsc::{Sender, Receiver}; -use std::sync::{Arc, Mutex}; - -use crate::buckyball::top::{RoccCmd, CmdResponse}; -use super::socket::cmd::{CmdReq, CmdResp}; -use super::dma::DmaHandler; - -pub struct CmdHandler { - cmd_tx: Sender, - cmd_response_rx: Arc>>, -} - -impl CmdHandler { - pub fn new(cmd_tx: Sender, cmd_response_rx: Arc>>) -> Self { - Self { cmd_tx, cmd_response_rx } - } - - /// Handle a single CMD request - pub fn handle_cmd_request(&mut self, stream: &mut TcpStream, msg_type_val: u32, dma_handler: &mut DmaHandler) -> std::io::Result<()> { - // Read remaining CMD request bytes (already read 4 bytes for msg_type) - let mut remaining_bytes = [0u8; CmdReq::SIZE - 4]; - stream.read_exact(&mut remaining_bytes)?; - - // Reconstruct full message - let mut msg_bytes = [0u8; CmdReq::SIZE]; - msg_bytes[0..4].copy_from_slice(&msg_type_val.to_le_bytes()); - msg_bytes[4..].copy_from_slice(&remaining_bytes); - - // Parse CMD request - let cmd_req = CmdReq::from_bytes(&msg_bytes); - let funct = cmd_req.funct; - let xs1 = cmd_req.xs1; - let xs2 = cmd_req.xs2; - log_ipc!("[CMD] Received: funct={}, xs1=0x{:016x}, xs2=0x{:016x}", funct, xs1, xs2); - - // Forward command to Top via channel - let rocc_cmd = RoccCmd { funct, xs1, xs2 }; - if let Err(e) = self.cmd_tx.send(rocc_cmd) { - log_error!("[CMD] Failed to send to Top: {}", e); - return Err(std::io::Error::new(std::io::ErrorKind::BrokenPipe, e)); - } - - // Wait for cmd_response from Frontend - // While waiting, send any pending DMA requests - let result = loop { - // Try to send DMA requests (non-blocking) - dma_handler.try_send_dma_request(stream)?; - - // Try to receive cmd_response (non-blocking) - let response_rx = self.cmd_response_rx.lock().unwrap(); - match response_rx.try_recv() { - Ok(cmd_response) => { - log_ipc!("[CMD] Received cmd_response from Frontend: result=0x{:016x}", cmd_response.result); - break cmd_response.result; - } - Err(std::sync::mpsc::TryRecvError::Empty) => { - // No response yet, continue loop - drop(response_rx); - std::thread::sleep(std::time::Duration::from_micros(100)); - continue; - } - Err(std::sync::mpsc::TryRecvError::Disconnected) => { - log_error!("[CMD] cmd_response channel disconnected"); - return Err(std::io::Error::new(std::io::ErrorKind::BrokenPipe, "cmd_response channel disconnected")); - } - } - }; - - // Send CMD response to host - let cmd_resp = CmdResp::new(result); - let resp_bytes = cmd_resp.to_bytes(); - stream.write_all(&resp_bytes)?; - log_ipc!("[CMD] Sent response to host: result=0x{:016x}\n", result); - - Ok(()) - } -} diff --git a/bebop/bebop/src/simulator/server/dma.rs b/bebop/bebop/src/simulator/server/dma.rs deleted file mode 100644 index a5316c26..00000000 --- a/bebop/bebop/src/simulator/server/dma.rs +++ /dev/null @@ -1,110 +0,0 @@ -/// DMA channel handler - processes DMA requests from MemDomain and sends to host via TCP -use std::io::{Read, Write}; -use std::net::TcpStream; -use std::sync::mpsc::{Receiver, Sender}; -use std::sync::{Arc, Mutex}; - -use crate::buckyball::top::{DmaRequest, DmaResponse}; -use super::socket::read::{DmaReadReq, DmaReadResp}; -use super::socket::write::{DmaWriteReq, DmaWriteResp}; - -pub struct DmaHandler { - dma_req_rx: Arc>>, - dma_resp_tx: Arc>>, -} - -impl DmaHandler { - pub fn new( - dma_req_rx: Arc>>, - dma_resp_tx: Arc>>, - ) -> Self { - Self { - dma_req_rx, - dma_resp_tx, - } - } - - /// Try to send a DMA request to host (non-blocking check) - /// Returns true if a request was sent, false if no request available - pub fn try_send_dma_request(&mut self, stream: &mut TcpStream) -> std::io::Result { - // Non-blocking check for DMA request from MemDomain - let rx = self.dma_req_rx.lock().unwrap(); - match rx.try_recv() { - Ok(dma_req) => { - drop(rx); // Release lock before I/O - - match dma_req { - DmaRequest::Read { addr, size } => { - println!("[DMA] Sending Read request: addr=0x{:x}, size={}", addr, size); - let req = DmaReadReq::new(addr, size); - let req_bytes = req.to_bytes(); - stream.write_all(&req_bytes)?; - log_ipc!("[DMA] Read request sent: addr=0x{:x}, size={}", addr, size); - } - DmaRequest::Write { addr, data, size } => { - println!("[DMA] Sending Write request: addr=0x{:x}, data=0x{:x}, size={}", addr, data, size); - let req = DmaWriteReq::new(addr, data, size); - let req_bytes = req.to_bytes(); - stream.write_all(&req_bytes)?; - log_ipc!("[DMA] Write request sent: addr=0x{:x}, data=0x{:x}, size={}", addr, data, size); - } - } - Ok(true) - } - Err(std::sync::mpsc::TryRecvError::Empty) => { - Ok(false) // No request available - } - Err(std::sync::mpsc::TryRecvError::Disconnected) => { - Err(std::io::Error::new( - std::io::ErrorKind::BrokenPipe, - "DMA request channel disconnected", - )) - } - } - } - - /// Handle DMA read response from host - pub fn handle_dma_read_response(&mut self, stream: &mut TcpStream, msg_type_val: u32) -> std::io::Result<()> { - // Read remaining DMA read response bytes - let mut remaining_bytes = [0u8; DmaReadResp::SIZE - 4]; - stream.read_exact(&mut remaining_bytes)?; - - // Reconstruct full message - let mut msg_bytes = [0u8; DmaReadResp::SIZE]; - msg_bytes[0..4].copy_from_slice(&msg_type_val.to_le_bytes()); - msg_bytes[4..].copy_from_slice(&remaining_bytes); - - let resp = DmaReadResp::from_bytes(&msg_bytes); - let data = resp.data; - log_ipc!("[DMA] Read response received: data=0x{:x}\n", data); - - // Send response back to MemDomain via channel - let dma_resp = DmaResponse::ReadComplete { data }; - let tx = self.dma_resp_tx.lock().unwrap(); - if let Err(e) = tx.send(dma_resp) { - log_error!("[DMA] Failed to send response to MemDomain: {}", e); - return Err(std::io::Error::new(std::io::ErrorKind::BrokenPipe, e)); - } - - Ok(()) - } - - /// Handle DMA write response from host - pub fn handle_dma_write_response(&mut self, stream: &mut TcpStream, msg_type_val: u32) -> std::io::Result<()> { - // Read remaining DMA write response bytes - let mut remaining_bytes = [0u8; DmaWriteResp::SIZE - 4]; - stream.read_exact(&mut remaining_bytes)?; - - log_ipc!("[DMA] Write response received\n"); - - // Send response back to MemDomain via channel - let dma_resp = DmaResponse::WriteComplete; - let tx = self.dma_resp_tx.lock().unwrap(); - if let Err(e) = tx.send(dma_resp) { - log_error!("[DMA] Failed to send response to MemDomain: {}", e); - return Err(std::io::Error::new(std::io::ErrorKind::BrokenPipe, e)); - } - - Ok(()) - } -} diff --git a/bebop/bebop/src/simulator/server/mod.rs b/bebop/bebop/src/simulator/server/mod.rs deleted file mode 100644 index c926dd3d..00000000 --- a/bebop/bebop/src/simulator/server/mod.rs +++ /dev/null @@ -1,7 +0,0 @@ -/// Server module for handling host connections -mod cmd; -mod dma; -mod server; -mod socket; - -pub use server::SocketServer; diff --git a/bebop/bebop/src/simulator/server/server.rs b/bebop/bebop/src/simulator/server/server.rs deleted file mode 100644 index d3fb59b2..00000000 --- a/bebop/bebop/src/simulator/server/server.rs +++ /dev/null @@ -1,128 +0,0 @@ -/// TCP server for accepting host connections -use std::net::{TcpListener, TcpStream}; -use std::sync::mpsc::{Sender, Receiver}; -use std::sync::{Arc, Mutex}; -use std::thread; - -use super::cmd::CmdHandler; -use super::dma::DmaHandler; -use super::socket::protocol::MsgType; -use crate::buckyball::top::{RoccCmd, DmaRequest, DmaResponse, CmdResponse}; - -pub struct SocketServer { - host: String, - port: u16, - step_mode: bool, - cmd_tx: Sender, - cmd_response_rx: Arc>>, - dma_req_rx: Arc>>, - dma_resp_tx: Arc>>, -} - -impl SocketServer { - pub fn new( - host: impl Into, - port: u16, - step_mode: bool, - cmd_tx: Sender, - cmd_response_rx: Arc>>, - dma_req_rx: Arc>>, - dma_resp_tx: Arc>>, - ) -> Self { - Self { - host: host.into(), - port, - step_mode, - cmd_tx, - cmd_response_rx, - dma_req_rx, - dma_resp_tx, - } - } - - /// Start the server and listen for connections - pub fn run(&self) -> std::io::Result<()> { - let addr = format!("{}:{}", self.host, self.port); - - log_info!("Socket server starting..."); - log_info!(" Listening on: {}", addr); - log_info!("Waiting for host connections...\n"); - - let listener = TcpListener::bind(&addr)?; - log_info!("[Server] Listener ready on {}", addr); - - for stream in listener.incoming() { - match stream { - Ok(stream) => { - let cmd_tx = self.cmd_tx.clone(); - let cmd_response_rx = self.cmd_response_rx.clone(); - let dma_req_rx = self.dma_req_rx.clone(); - let dma_resp_tx = self.dma_resp_tx.clone(); - - thread::spawn(move || { - if let Err(e) = Self::handle_connection(stream, cmd_tx, cmd_response_rx, dma_req_rx, dma_resp_tx) { - log_error!("[Server] Connection handler error: {}", e); - } - }); - } - Err(e) => { - log_error!("[Server] Connection error: {}", e); - } - } - } - - Ok(()) - } - - /// Handle a single connection, dispatching messages to CMD or DMA handlers - fn handle_connection( - mut stream: TcpStream, - cmd_tx: Sender, - cmd_response_rx: Arc>>, - dma_req_rx: Arc>>, - dma_resp_tx: Arc>>, - ) -> std::io::Result<()> { - use std::io::Read; - - let peer_addr = stream.peer_addr()?; - log_info!("[Server] Connected from: {}", peer_addr); - - let mut cmd_handler = CmdHandler::new(cmd_tx, cmd_response_rx); - let mut dma_handler = DmaHandler::new(dma_req_rx, dma_resp_tx); - - loop { - // Read message from host (blocking) - let mut msg_type_bytes = [0u8; 4]; - match stream.read_exact(&mut msg_type_bytes) { - Ok(_) => { - let msg_type_val = u32::from_le_bytes(msg_type_bytes); - let msg_type = MsgType::from_u32(msg_type_val); - - match msg_type { - Some(MsgType::CmdReq) => { - cmd_handler.handle_cmd_request(&mut stream, msg_type_val, &mut dma_handler)?; - } - Some(MsgType::DmaReadResp) => { - dma_handler.handle_dma_read_response(&mut stream, msg_type_val)?; - } - Some(MsgType::DmaWriteResp) => { - dma_handler.handle_dma_write_response(&mut stream, msg_type_val)?; - } - _ => { - log_error!("[Server] Unknown message type: {}", msg_type_val); - return Err(std::io::Error::new(std::io::ErrorKind::InvalidData, "Unknown message type")); - } - } - } - Err(e) => { - if e.kind() == std::io::ErrorKind::UnexpectedEof { - log_info!("[Server] Client {} disconnected", peer_addr); - return Ok(()); - } else { - return Err(e); - } - } - } - } - } -} diff --git a/bebop/bebop/src/simulator/server/socket/cmd.rs b/bebop/bebop/src/simulator/server/socket/cmd.rs deleted file mode 100644 index f4766d06..00000000 --- a/bebop/bebop/src/simulator/server/socket/cmd.rs +++ /dev/null @@ -1,72 +0,0 @@ -/// CMD protocol definitions -use super::protocol::{MsgHeader, MsgType}; - -/// Command request from client (CMD path) - 24 bytes -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct CmdReq { - pub header: MsgHeader, // 8 bytes - pub funct: u32, // 4 bytes - pub padding: u32, // 4 bytes - pub xs1: u64, // 8 bytes - pub xs2: u64, // 8 bytes -} - -impl CmdReq { - pub const SIZE: usize = 32; // 8 + 4 + 4 + 8 + 8 - - pub fn from_bytes(bytes: &[u8; Self::SIZE]) -> Self { - let msg_type = u32::from_le_bytes([bytes[0], bytes[1], bytes[2], bytes[3]]); - let reserved = u32::from_le_bytes([bytes[4], bytes[5], bytes[6], bytes[7]]); - let funct = u32::from_le_bytes([bytes[8], bytes[9], bytes[10], bytes[11]]); - let padding = u32::from_le_bytes([bytes[12], bytes[13], bytes[14], bytes[15]]); - let xs1 = u64::from_le_bytes([ - bytes[16], bytes[17], bytes[18], bytes[19], bytes[20], bytes[21], bytes[22], bytes[23], - ]); - let xs2 = u64::from_le_bytes([ - bytes[24], bytes[25], bytes[26], bytes[27], bytes[28], bytes[29], bytes[30], bytes[31], - ]); - - Self { - header: MsgHeader { msg_type, reserved }, - funct, - padding, - xs1, - xs2, - } - } -} - -/// Command response from server (CMD path) - 16 bytes -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct CmdResp { - pub header: MsgHeader, // 8 bytes - pub result: u64, // 8 bytes -} - -impl CmdResp { - pub const SIZE: usize = 16; - - pub fn new(result: u64) -> Self { - Self { - header: MsgHeader { - msg_type: MsgType::CmdResp as u32, - reserved: 0, - }, - result, - } - } - - pub fn to_bytes(&self) -> [u8; Self::SIZE] { - let mut bytes = [0u8; Self::SIZE]; - bytes[0..4].copy_from_slice(&self.header.msg_type.to_le_bytes()); - bytes[4..8].copy_from_slice(&self.header.reserved.to_le_bytes()); - bytes[8..16].copy_from_slice(&self.result.to_le_bytes()); - bytes - } -} - -// Backward compatibility aliases -pub type SocketMsg = CmdReq; -pub type SocketResp = CmdResp; diff --git a/bebop/bebop/src/simulator/server/socket/mod.rs b/bebop/bebop/src/simulator/server/socket/mod.rs deleted file mode 100644 index 4bf719cb..00000000 --- a/bebop/bebop/src/simulator/server/socket/mod.rs +++ /dev/null @@ -1,8 +0,0 @@ -/// Socket communication module for host-Bebop interface -pub mod cmd; -pub mod protocol; -pub mod read; -pub mod write; - -pub use cmd::{CmdReq, CmdResp, SocketMsg, SocketResp}; -pub use protocol::MsgType; diff --git a/bebop/bebop/src/simulator/server/socket/protocol.rs b/bebop/bebop/src/simulator/server/socket/protocol.rs deleted file mode 100644 index 84b4e7c9..00000000 --- a/bebop/bebop/src/simulator/server/socket/protocol.rs +++ /dev/null @@ -1,36 +0,0 @@ -/// Message protocol definitions for host-Bebop communication -/// Matches the C++ structures in customext/include/socket.h - -/// Message types for socket communication -#[repr(u32)] -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub enum MsgType { - CmdReq = 0, // Command request from client - CmdResp = 1, // Command response from server - DmaReadReq = 2, // DMA read request from server - DmaReadResp = 3, // DMA read response from client - DmaWriteReq = 4, // DMA write request from server - DmaWriteResp = 5, // DMA write response from client -} - -impl MsgType { - pub fn from_u32(value: u32) -> Option { - match value { - 0 => Some(MsgType::CmdReq), - 1 => Some(MsgType::CmdResp), - 2 => Some(MsgType::DmaReadReq), - 3 => Some(MsgType::DmaReadResp), - 4 => Some(MsgType::DmaWriteReq), - 5 => Some(MsgType::DmaWriteResp), - _ => None, - } - } -} - -/// Common message header (8 bytes) -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct MsgHeader { - pub msg_type: u32, - pub reserved: u32, -} diff --git a/bebop/bebop/src/simulator/server/socket/read.rs b/bebop/bebop/src/simulator/server/socket/read.rs deleted file mode 100644 index a00671d4..00000000 --- a/bebop/bebop/src/simulator/server/socket/read.rs +++ /dev/null @@ -1,63 +0,0 @@ -/// DMA read protocol definitions -use super::protocol::{MsgHeader, MsgType}; - -/// DMA read request from server (DMA path) - 24 bytes -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct DmaReadReq { - pub header: MsgHeader, // 8 bytes - pub size: u32, // 4 bytes - pub padding: u32, // 4 bytes - pub addr: u64, // 8 bytes -} - -impl DmaReadReq { - pub const SIZE: usize = 24; - - pub fn new(addr: u64, size: u32) -> Self { - Self { - header: MsgHeader { - msg_type: MsgType::DmaReadReq as u32, - reserved: 0, - }, - size, - padding: 0, - addr, - } - } - - pub fn to_bytes(&self) -> [u8; Self::SIZE] { - let mut bytes = [0u8; Self::SIZE]; - bytes[0..4].copy_from_slice(&self.header.msg_type.to_le_bytes()); - bytes[4..8].copy_from_slice(&self.header.reserved.to_le_bytes()); - bytes[8..12].copy_from_slice(&self.size.to_le_bytes()); - bytes[12..16].copy_from_slice(&self.padding.to_le_bytes()); - bytes[16..24].copy_from_slice(&self.addr.to_le_bytes()); - bytes - } -} - -/// DMA read response from client (DMA path) - 16 bytes -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct DmaReadResp { - pub header: MsgHeader, // 8 bytes - pub data: u64, // 8 bytes -} - -impl DmaReadResp { - pub const SIZE: usize = 16; - - pub fn from_bytes(bytes: &[u8; Self::SIZE]) -> Self { - let msg_type = u32::from_le_bytes([bytes[0], bytes[1], bytes[2], bytes[3]]); - let reserved = u32::from_le_bytes([bytes[4], bytes[5], bytes[6], bytes[7]]); - let data = u64::from_le_bytes([ - bytes[8], bytes[9], bytes[10], bytes[11], bytes[12], bytes[13], bytes[14], bytes[15], - ]); - - Self { - header: MsgHeader { msg_type, reserved }, - data, - } - } -} diff --git a/bebop/bebop/src/simulator/server/socket/write.rs b/bebop/bebop/src/simulator/server/socket/write.rs deleted file mode 100644 index 4c24485e..00000000 --- a/bebop/bebop/src/simulator/server/socket/write.rs +++ /dev/null @@ -1,69 +0,0 @@ -/// DMA write protocol definitions -use super::protocol::{MsgHeader, MsgType}; - -/// DMA write request from server (DMA path) - 32 bytes -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct DmaWriteReq { - pub header: MsgHeader, // 8 bytes - pub size: u32, // 4 bytes - pub padding: u32, // 4 bytes - pub addr: u64, // 8 bytes - pub data: u64, // 8 bytes -} - -impl DmaWriteReq { - pub const SIZE: usize = 32; - - pub fn new(addr: u64, data: u64, size: u32) -> Self { - Self { - header: MsgHeader { - msg_type: MsgType::DmaWriteReq as u32, - reserved: 0, - }, - size, - padding: 0, - addr, - data, - } - } - - pub fn to_bytes(&self) -> [u8; Self::SIZE] { - let mut bytes = [0u8; Self::SIZE]; - bytes[0..4].copy_from_slice(&self.header.msg_type.to_le_bytes()); - bytes[4..8].copy_from_slice(&self.header.reserved.to_le_bytes()); - bytes[8..12].copy_from_slice(&self.size.to_le_bytes()); - bytes[12..16].copy_from_slice(&self.padding.to_le_bytes()); - bytes[16..24].copy_from_slice(&self.addr.to_le_bytes()); - bytes[24..32].copy_from_slice(&self.data.to_le_bytes()); - bytes - } -} - -/// DMA write response from client (DMA path) - 16 bytes -#[repr(C, packed)] -#[derive(Debug, Clone, Copy)] -pub struct DmaWriteResp { - pub header: MsgHeader, // 8 bytes - pub reserved: u64, // 8 bytes -} - -impl DmaWriteResp { - pub const SIZE: usize = 16; - - pub fn from_bytes(bytes: &[u8; Self::SIZE]) -> Self { - let msg_type = u32::from_le_bytes([bytes[0], bytes[1], bytes[2], bytes[3]]); - let reserved_header = u32::from_le_bytes([bytes[4], bytes[5], bytes[6], bytes[7]]); - let reserved = u64::from_le_bytes([ - bytes[8], bytes[9], bytes[10], bytes[11], bytes[12], bytes[13], bytes[14], bytes[15], - ]); - - Self { - header: MsgHeader { - msg_type, - reserved: reserved_header, - }, - reserved, - } - } -} diff --git a/bebop/bebop/src/simulator/simulator.rs b/bebop/bebop/src/simulator/simulator.rs deleted file mode 100644 index 746ce4ee..00000000 --- a/bebop/bebop/src/simulator/simulator.rs +++ /dev/null @@ -1,76 +0,0 @@ -/// Accelerator simulator with state management -use super::server::SocketServer; -use crate::buckyball::Top; -use crate::builtin::Sim; -use std::thread; - -/// Execution mode for the simulator -#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] -pub enum StepMode { - #[default] - Run, - Step, -} - -/// Accelerator simulator - drives Top module -pub struct Simulator { - host: String, - port: u16, - step_mode: StepMode, -} - -impl Simulator { - pub fn new(host: impl Into, port: u16, step_mode: StepMode) -> Self { - Self { - host: host.into(), - port, - step_mode, - } - } - - /// Run the simulator server - pub fn run(self) -> std::io::Result<()> { - let step_mode = matches!(self.step_mode, StepMode::Step); - let mut buckyball = Top::new("buckyball"); - let cmd_tx = buckyball.get_cmd_sender(); - let cmd_response_rx = buckyball.get_cmd_response_receiver(); - let (dma_req_rx, dma_resp_tx) = buckyball.get_dma_channels(); - - // Start server in background thread (lower priority) - let server = SocketServer::new(self.host, self.port, step_mode, cmd_tx, cmd_response_rx, dma_req_rx, dma_resp_tx); - thread::spawn(move || { - if let Err(e) = server.run() { - log_error!("Server error: {}", e); - } - }); - - // Run buckyball in main thread (high priority) - log_info!("Buckyball main loop started"); - - if step_mode { - // Step mode: wait for user input (press Enter) before each tick - log_info!("Running in STEP mode - press Enter to tick"); - use std::io::{self, BufRead}; - let stdin = io::stdin(); - let mut lines = stdin.lock().lines(); - - loop { - // Wait for Enter key - if lines.next().is_some() { - buckyball.forward(); - buckyball.backward(); - } else { - break; // EOF or error - } - } - } else { - // Free-running mode: tick as fast as possible - loop { - buckyball.forward(); - buckyball.backward(); - } - } - - Ok(()) - } -} diff --git a/bebop/bebop/src/simulator/utils/log.rs b/bebop/bebop/src/simulator/utils/log.rs deleted file mode 100644 index 769eaaaa..00000000 --- a/bebop/bebop/src/simulator/utils/log.rs +++ /dev/null @@ -1,57 +0,0 @@ -/// Logging utilities with colored output - -/// Print a log message with blue [Log] prefix -#[macro_export] -macro_rules! log_info { - ($($arg:tt)*) => { - println!("\x1b[34m[Log]\x1b[0m {}", format!($($arg)*)); - }; -} - -#[macro_export] -macro_rules! log_ipc { - ($($arg:tt)*) => { - println!("\x1b[32m[IPC]\x1b[0m {}", format!($($arg)*)); - }; -} - -/// Print an error message with red [Error] prefix -#[macro_export] -macro_rules! log_error { - ($($arg:tt)*) => { - eprintln!("\x1b[31m[Error]\x1b[0m {}", format!($($arg)*)); - }; -} - -/// Print an error message with red [Error] prefix -#[macro_export] -macro_rules! log_event { - ($($arg:tt)*) => { - println!("\x1b[33m[Event]\x1b[0m {}", format!($($arg)*)); - }; -} - -#[macro_export] -macro_rules! log_forward { - ($($arg:tt)*) => {{ - if $crate::simulator::utils::log_config::is_forward_log_enabled() { - println!("\x1b[33m[Forward]\x1b[0m {}", format!($($arg)*)); - } - }}; -} - -#[macro_export] -macro_rules! log_backward { - ($($arg:tt)*) => {{ - if $crate::simulator::utils::log_config::is_backward_log_enabled() { - println!("\x1b[33m[Backward]\x1b[0m {}", format!($($arg)*)); - } - }}; -} - -#[macro_export] -macro_rules! log_tpc { - ($($arg:tt)*) => {{ - println!("\x1b[35m[Tpc]\x1b[0m {}", format!($($arg)*)); - }}; -} diff --git a/bebop/bebop/src/simulator/utils/log_config.rs b/bebop/bebop/src/simulator/utils/log_config.rs deleted file mode 100644 index 3e2483c2..00000000 --- a/bebop/bebop/src/simulator/utils/log_config.rs +++ /dev/null @@ -1,38 +0,0 @@ -/// Global logging configuration -use std::sync::atomic::{AtomicBool, Ordering}; - -/// Global flags for controlling log output -static ENABLE_FORWARD_LOG: AtomicBool = AtomicBool::new(true); -static ENABLE_BACKWARD_LOG: AtomicBool = AtomicBool::new(true); - -/// Enable or disable forward phase logging -pub fn set_forward_log(enabled: bool) { - ENABLE_FORWARD_LOG.store(enabled, Ordering::Relaxed); -} - -/// Enable or disable backward phase logging -pub fn set_backward_log(enabled: bool) { - ENABLE_BACKWARD_LOG.store(enabled, Ordering::Relaxed); -} - -/// Check if forward logging is enabled -pub fn is_forward_log_enabled() -> bool { - ENABLE_FORWARD_LOG.load(Ordering::Relaxed) -} - -/// Check if backward logging is enabled -pub fn is_backward_log_enabled() -> bool { - ENABLE_BACKWARD_LOG.load(Ordering::Relaxed) -} - -/// Enable all phase logs -pub fn enable_all_logs() { - set_forward_log(true); - set_backward_log(true); -} - -/// Disable all phase logs -pub fn disable_all_logs() { - set_forward_log(false); - set_backward_log(false); -} diff --git a/bebop/bebop/src/simulator/utils/mod.rs b/bebop/bebop/src/simulator/utils/mod.rs deleted file mode 100644 index 7e0ea083..00000000 --- a/bebop/bebop/src/simulator/utils/mod.rs +++ /dev/null @@ -1,3 +0,0 @@ -#[macro_use] -pub mod log; -pub mod log_config; diff --git a/bebop/host/CMakeLists.txt b/bebop/host/CMakeLists.txt deleted file mode 100644 index 7b543000..00000000 --- a/bebop/host/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -cmake_minimum_required(VERSION 3.16) -project(bebop_host LANGUAGES C CXX) - -add_subdirectory(ipc) -add_subdirectory(spike) -# add_subdirectory(gem5) diff --git a/bebop/host/gem5/CMakeLists.txt b/bebop/host/gem5/CMakeLists.txt deleted file mode 100644 index e69de29b..00000000 diff --git a/bebop/host/gem5/bebop.patch b/bebop/host/gem5/bebop.patch deleted file mode 100644 index ee58851c..00000000 --- a/bebop/host/gem5/bebop.patch +++ /dev/null @@ -1,211 +0,0 @@ -diff --git a/SConstruct b/SConstruct -index a5802ad371..b3008bd565 100755 ---- a/SConstruct -+++ b/SConstruct -@@ -198,6 +198,15 @@ main = Environment(tools=[ - main.Tool(SCons.Tool.FindTool(['gcc', 'clang'], main)) - main.Tool(SCons.Tool.FindTool(['g++', 'clang++'], main)) - -+bebop_ipc_lib = environ.get('BEBOP_IPC_LIB') -+bebop_ipc_include = environ.get('BEBOP_IPC_INCLUDE') -+if bebop_ipc_lib: -+ print(f'Linking with bebop IPC library: {bebop_ipc_lib}') -+ main.Append(_LIBFLAGS=[bebop_ipc_lib]) -+if bebop_ipc_include: -+ print(f'Adding bebop IPC include path: {bebop_ipc_include}') -+ main.Append(CPPPATH=[bebop_ipc_include]) -+ - Export('main') - - from gem5_scons.util import get_termcap -diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc -index dc312b5f67..4e58948316 100644 ---- a/src/arch/riscv/faults.cc -+++ b/src/arch/riscv/faults.cc -@@ -31,6 +31,7 @@ - - #include "arch/riscv/faults.hh" - -+#include "arch/riscv/insts/custom.hh" - #include "arch/riscv/insts/static_inst.hh" - #include "arch/riscv/isa.hh" - #include "arch/riscv/mmu.hh" -@@ -286,6 +287,12 @@ void - UnknownInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) - { - auto *rsi = static_cast(inst.get()); -+ const uint8_t opcode = rsi->machInst.opcode; -+ // Handle custom-3 (opcode 0x7b) which conflicts with M5Op -+ if (opcode == 0x7b) { -+ handleRiscvCustomInstruction(tc, rsi->machInst, inst.get()); -+ return; -+ } - panic("Unknown instruction 0x%08x at pc %s", rsi->machInst, - tc->pcState()); - } -diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript -index 9694cc1405..8449eb7c80 100644 ---- a/src/arch/riscv/insts/SConscript -+++ b/src/arch/riscv/insts/SConscript -@@ -33,6 +33,7 @@ if not env['CONF']['USE_RISCV_ISA']: - Source('amo.cc', tags=['riscv isa']) - Source('bs.cc', tags=['riscv isa']) - Source('compressed.cc', tags=['riscv isa']) -+Source('custom.cc', tags=['riscv isa']) - Source('mem.cc', tags=['riscv isa']) - Source('standard.cc', tags=['riscv isa']) - Source('static_inst.cc', tags=['riscv isa']) -diff --git a/src/arch/riscv/insts/custom.cc b/src/arch/riscv/insts/custom.cc -new file mode 100644 -index 0000000000..e06548d6ec ---- /dev/null -+++ b/src/arch/riscv/insts/custom.cc -@@ -0,0 +1,83 @@ -+#include "arch/riscv/insts/custom.hh" -+ -+#include "ipc/socket.h" -+#include "arch/riscv/insts/static_inst.hh" -+#include "arch/riscv/pcstate.hh" -+#include "arch/riscv/regs/int.hh" -+#include "debug/Faults.hh" -+#include "mem/se_translating_port_proxy.hh" -+#include "sim/debug.hh" -+ -+namespace gem5 -+{ -+ -+namespace RiscvISA -+{ -+namespace -+{ -+ -+struct RoCCInstFields { -+ unsigned opcode : 7; -+ unsigned rd : 5; -+ unsigned xs2 : 1; -+ unsigned xs1 : 1; -+ unsigned xd : 1; -+ unsigned rs1 : 5; -+ unsigned rs2 : 5; -+ unsigned funct : 7; -+}; -+ -+union RoCCInst { -+ RoCCInstFields r; -+ uint32_t bits; -+}; -+ -+SocketClient &getSocketClient() { -+ static SocketClient client; -+ return client; -+} -+ -+} // anonymous namespace -+ -+void -+handleRiscvCustomInstruction(ThreadContext *tc, ExtMachInst instBits, -+ const StaticInst *inst) -+{ -+ RoCCInst rocc{}; -+ rocc.bits = instBits.instBits; -+ -+ RegVal xs1 = rocc.r.xs1 ? -+ tc->getReg(intRegClass[rocc.r.rs1]) : -+ static_cast(-1); -+ RegVal xs2 = rocc.r.xs2 ? -+ tc->getReg(intRegClass[rocc.r.rs2]) : -+ static_cast(-1); -+ -+ auto read_cb = [tc](uint64_t addr, uint32_t size) -> uint64_t { -+ SETranslatingPortProxy proxy(tc); -+ uint64_t value = 0; -+ proxy.readBlob(addr, reinterpret_cast(&value), size); -+ return value; -+ }; -+ -+ auto write_cb = [tc](uint64_t addr, uint64_t data, uint32_t size) { -+ SETranslatingPortProxy proxy(tc); -+ proxy.writeBlob(addr, reinterpret_cast(&data), size); -+ }; -+ -+ auto &client = getSocketClient(); -+ client.set_dma_callbacks(read_cb, write_cb); -+ uint64_t result = client.send_and_wait(rocc.r.funct, xs1, xs2); -+ client.set_dma_callbacks(dma_read_cb_t(), dma_write_cb_t()); -+ -+ if (rocc.r.xd) -+ tc->setReg(intRegClass[rocc.r.rd], result); -+ -+ auto pc_state = tc->pcState().as(); -+ inst->advancePC(pc_state); -+ tc->pcState(pc_state); -+} -+ -+} // namespace RiscvISA -+} // namespace gem5 -+ -diff --git a/src/arch/riscv/insts/custom.hh b/src/arch/riscv/insts/custom.hh -new file mode 100644 -index 0000000000..3e09b67199 ---- /dev/null -+++ b/src/arch/riscv/insts/custom.hh -@@ -0,0 +1,20 @@ -+#ifndef __ARCH_RISCV_CUSTOM_INST_HH__ -+#define __ARCH_RISCV_CUSTOM_INST_HH__ -+ -+#include "arch/riscv/types.hh" -+#include "cpu/static_inst.hh" -+#include "cpu/thread_context.hh" -+ -+namespace gem5 -+{ -+ -+namespace RiscvISA -+{ -+ -+void handleRiscvCustomInstruction(ThreadContext *tc, ExtMachInst instBits, -+ const StaticInst *inst); -+ -+} // namespace RiscvISA -+} // namespace gem5 -+ -+#endif // __ARCH_RISCV_CUSTOM_INST_HH__ -diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa -index 6235b34aee..678c3db2ea 100644 ---- a/src/arch/riscv/isa/decoder.isa -+++ b/src/arch/riscv/isa/decoder.isa -@@ -6360,6 +6360,22 @@ decode QUADRANT default Unknown::unknown() { - } - } - -+ // Custom instructions (bebop extension) -+ // custom-0 (opcode 0x0b), custom-1 (opcode 0x2b), custom-2 (opcode 0x5b) -+ format ROp { -+ 0x02: bebop_custom0({{ -+ handleRiscvCustomInstruction(xc->tcBase(), machInst, this); -+ }}); -+ 0x0a: bebop_custom1({{ -+ handleRiscvCustomInstruction(xc->tcBase(), machInst, this); -+ }}); -+ 0x16: bebop_custom2({{ -+ handleRiscvCustomInstruction(xc->tcBase(), machInst, this); -+ }}); -+ } -+ -+ // M5Op uses 0x1e which conflicts with custom-3 (opcode 0x7b) -+ // Keep M5Op for now, custom-3 handled in unknown fault if needed - 0x1e: M5Op::M5Op(); - } - } -diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa -index b4be0e4ac6..d4f27fb845 100644 ---- a/src/arch/riscv/isa/includes.isa -+++ b/src/arch/riscv/isa/includes.isa -@@ -53,6 +53,7 @@ output header {{ - #include "arch/riscv/insts/pseudo.hh" - #include "arch/riscv/insts/standard.hh" - #include "arch/riscv/insts/static_inst.hh" -+#include "arch/riscv/insts/custom.hh" - #include "arch/riscv/insts/unknown.hh" - #include "arch/riscv/insts/vector.hh" - #include "arch/riscv/insts/zcmp.hh" diff --git a/bebop/host/gem5/gem5 b/bebop/host/gem5/gem5 deleted file mode 160000 index ddd4ae35..00000000 --- a/bebop/host/gem5/gem5 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ddd4ae35adb0a3df1f1ba11e9a973a5c2f8c2944 diff --git a/bebop/host/gem5/install-gem5.sh b/bebop/host/gem5/install-gem5.sh deleted file mode 100755 index 8c9ed971..00000000 --- a/bebop/host/gem5/install-gem5.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env bash - -set -euo pipefail - -SCRIPT_DIR="$(dirname "$(realpath "$0")")" -HOST_ROOT=${SCRIPT_DIR}/.. -GEM5_ROOT=${SCRIPT_DIR}/gem5 -HOST_BUILD=${HOST_ROOT}/build -IPC_BUILD_LIB=${HOST_BUILD}/ipc -IPC_INCLUDE=${HOST_ROOT}/ipc/include - -cmake -S ${HOST_ROOT} -B ${HOST_BUILD} -cmake --build ${HOST_BUILD} --target bebop_ipc -j$(nproc) - - -# Install gem5 and integerate bebop into gem5 -# sudo apt install build-essential git m4 scons zlib1g zlib1g-dev \ -# libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \ -# python3-dev python-is-python3 libboost-all-dev pkg-config gcc-10 g++-10 \ -# python3-tk clang-format-18 -# cd $ROOT/thirdparty/gem5 -# export PKG_CONFIG_PATH=$CONDA_PREFIX/lib/pkgconfig:$PKG_CONFIG_PATH -# scons build/RISCV/gem5.opt -j $(nproc) LIBS="absl_log_internal_check_op \ - -cd ${GEM5_ROOT} -# Apply the patch to gem5 -git apply ${SCRIPT_DIR}/bebop.patch -# We need to update the patch in this way if we make changes to gem5 -# git add -A && git diff --cached > ../bebop.patch - -# Build gem5 -export PKG_CONFIG_PATH=${CONDA_PREFIX:-}/lib/pkgconfig:${PKG_CONFIG_PATH:-} -BEBOP_IPC_LIB=${IPC_BUILD_LIB}/libbebop_ipc.a \ - BEBOP_IPC_INCLUDE=${IPC_INCLUDE} \ - scons build/RISCV/gem5.opt -j $(nproc) \ - LIBS="absl_log_internal_check_op \ - absl_log_internal_conditions \ - absl_log_internal_message \ - absl_base \ - absl_raw_logging_internal \ - absl_strings \ - absl_throw_delegate \ - absl_string_view \ - absl_spinlock_wait \ - absl_int128 \ - absl_log_severity" diff --git a/bebop/host/install.sh b/bebop/host/install.sh deleted file mode 100755 index 245b31ad..00000000 --- a/bebop/host/install.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -set -e - -ROOT="$(dirname "$(realpath "$0")")" - -cd $ROOT -# git submodule update --init - -$ROOT/spike/install-spike.sh -$ROOT/gem5/install-gem5.sh diff --git a/bebop/host/ipc/CMakeLists.txt b/bebop/host/ipc/CMakeLists.txt deleted file mode 100644 index 01b57f18..00000000 --- a/bebop/host/ipc/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -set(BEBOP_IPC_SOURCES - src/socket/socket.cc - src/socket/socket_cmd.cc - src/socket/socket_dma.cc -) - -add_library(bebop_ipc STATIC ${BEBOP_IPC_SOURCES}) - -target_include_directories(bebop_ipc - PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/include - PRIVATE - $ENV{RISCV}/include -) - -set_target_properties(bebop_ipc PROPERTIES - OUTPUT_NAME "bebop_ipc" - POSITION_INDEPENDENT_CODE ON -) - -set(_bebop_ipc_install_dir ${CMAKE_INSTALL_RPATH}) -if(NOT _bebop_ipc_install_dir) - set(_bebop_ipc_install_dir $ENV{RISCV}/lib) -endif() - -install(TARGETS bebop_ipc - ARCHIVE DESTINATION ${_bebop_ipc_install_dir} -) diff --git a/bebop/host/ipc/include/ipc/socket.h b/bebop/host/ipc/include/ipc/socket.h deleted file mode 100644 index 9705f368..00000000 --- a/bebop/host/ipc/include/ipc/socket.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef IPC_SOCKET_H_ -#define IPC_SOCKET_H_ - -#include -#include - -// Socket configuration -#define SOCKET_PORT 9999 -#define SOCKET_HOST "127.0.0.1" - -// Message types for socket communication -enum socket_msg_type_t : uint32_t { - MSG_TYPE_CMD_REQ = 0, // Command request from client - MSG_TYPE_CMD_RESP = 1, // Command response from server - MSG_TYPE_DMA_READ_REQ = 2, // DMA read request from server - MSG_TYPE_DMA_READ_RESP = 3, // DMA read response from client - MSG_TYPE_DMA_WRITE_REQ = 4, // DMA write request from server - MSG_TYPE_DMA_WRITE_RESP = 5 // DMA write response from client -}; - -// Common message header -struct msg_header_t { - uint32_t msg_type; // socket_msg_type_t - uint32_t reserved; -}; - -// Command request from client (CMD path) -struct cmd_req_t { - msg_header_t header; // header.msg_type = MSG_TYPE_CMD_REQ - uint32_t funct; - uint32_t padding; - uint64_t xs1; - uint64_t xs2; -}; - -// Command response from server (CMD path) -struct cmd_resp_t { - msg_header_t header; // header.msg_type = MSG_TYPE_CMD_RESP - uint64_t result; -}; - -// DMA read request from server (DMA path) -struct dma_read_req_t { - msg_header_t header; // header.msg_type = MSG_TYPE_DMA_READ_REQ - uint32_t size; // Size in bytes (1, 2, 4, or 8) - uint32_t padding; - uint64_t addr; // Memory address -}; - -// DMA read response from client (DMA path) -struct dma_read_resp_t { - msg_header_t header; // header.msg_type = MSG_TYPE_DMA_READ_RESP - uint64_t data; // Read data -}; - -// DMA write request from server (DMA path) -struct dma_write_req_t { - msg_header_t header; // header.msg_type = MSG_TYPE_DMA_WRITE_REQ - uint32_t size; // Size in bytes (1, 2, 4, or 8) - uint32_t padding; - uint64_t addr; // Memory address - uint64_t data; // Write data -}; - -// DMA write response from client (DMA path) -struct dma_write_resp_t { - msg_header_t header; // header.msg_type = MSG_TYPE_DMA_WRITE_RESP - uint64_t reserved; // Reserved for future use -}; - -using dma_read_cb_t = std::function; -using dma_write_cb_t = - std::function; - -// Socket client class -class SocketClient { -public: - SocketClient(); - ~SocketClient(); - - // Initialize and connect to socket server - bool init(); - - // Close socket connection - void close(); - - // Register DMA callbacks - void set_dma_callbacks(dma_read_cb_t read_cb, dma_write_cb_t write_cb); - - // Send request and wait for response (handles DMA requests during wait) - uint64_t send_and_wait(uint32_t funct, uint64_t xs1, uint64_t xs2); - - // Check if socket is connected - bool is_connected() const { return socket_initialized; } - -private: - int sock_fd; - bool socket_initialized; - dma_read_cb_t dma_read_cb; - dma_write_cb_t dma_write_cb; - - // CMD path functions - bool send_cmd_request(const cmd_req_t &req); - bool recv_cmd_response(cmd_resp_t &resp); - - // DMA path functions - bool recv_dma_read_request(dma_read_req_t &req); - bool send_dma_read_response(const dma_read_resp_t &resp); - bool recv_dma_write_request(dma_write_req_t &req); - bool send_dma_write_response(const dma_write_resp_t &resp); - - // Low-level recv/send - bool recv_header(msg_header_t &header); - - // DMA handlers - uint64_t handle_dma_read(uint64_t addr, uint32_t size); - void handle_dma_write(uint64_t addr, uint64_t data, uint32_t size); -}; - -#endif // IPC_SOCKET_H_ diff --git a/bebop/host/ipc/src/socket/socket.cc b/bebop/host/ipc/src/socket/socket.cc deleted file mode 100644 index 87316791..00000000 --- a/bebop/host/ipc/src/socket/socket.cc +++ /dev/null @@ -1,173 +0,0 @@ -#include "ipc/socket.h" -#include -#include -#include -#include -#include -#include - -SocketClient::SocketClient() : sock_fd(-1), socket_initialized(false) {} - -SocketClient::~SocketClient() { close(); } - -bool SocketClient::init() { - if (socket_initialized) { - return true; - } - - sock_fd = socket(AF_INET, SOCK_STREAM, 0); - if (sock_fd < 0) { - fprintf(stderr, "Socket: Failed to create socket\n"); - return false; - } - - struct sockaddr_in server_addr; - memset(&server_addr, 0, sizeof(server_addr)); - server_addr.sin_family = AF_INET; - server_addr.sin_port = htons(SOCKET_PORT); - - if (inet_pton(AF_INET, SOCKET_HOST, &server_addr.sin_addr) <= 0) { - fprintf(stderr, "Socket: Invalid address/Address not supported\n"); - ::close(sock_fd); - sock_fd = -1; - return false; - } - - if (connect(sock_fd, (struct sockaddr *)&server_addr, sizeof(server_addr)) < - 0) { - fprintf(stderr, "Socket: Connection failed to %s:%d\n", SOCKET_HOST, - SOCKET_PORT); - ::close(sock_fd); - sock_fd = -1; - return false; - } - - socket_initialized = true; - printf("Socket: Connected to %s:%d\n", SOCKET_HOST, SOCKET_PORT); - return true; -} - -void SocketClient::close() { - if (sock_fd >= 0) { - ::close(sock_fd); - sock_fd = -1; - } - socket_initialized = false; -} - -void SocketClient::set_dma_callbacks(dma_read_cb_t read_cb, - dma_write_cb_t write_cb) { - dma_read_cb = std::move(read_cb); - dma_write_cb = std::move(write_cb); -} - -// Receive message header (peek first to get type) -bool SocketClient::recv_header(msg_header_t &header) { - if (sock_fd < 0) { - fprintf(stderr, "Socket: Not connected\n"); - return false; - } - - ssize_t received = recv(sock_fd, &header, sizeof(header), MSG_PEEK); - - if (received < 0) { - fprintf(stderr, "Socket: Failed to peek header\n"); - close(); - return false; - } else if (received == 0) { - fprintf(stderr, "Socket: Connection closed by remote\n"); - close(); - return false; - } - - return true; -} - -uint64_t SocketClient::send_and_wait(uint32_t funct, uint64_t xs1, - uint64_t xs2) { - // Auto-connect if not connected - if (!socket_initialized) { - if (!init()) { - return 0; - } - } - - // Prepare and send CMD request - cmd_req_t cmd_req; - cmd_req.header.msg_type = MSG_TYPE_CMD_REQ; - cmd_req.header.reserved = 0; - cmd_req.funct = funct; - cmd_req.padding = 0; - cmd_req.xs1 = xs1; - cmd_req.xs2 = xs2; - - if (!send_cmd_request(cmd_req)) { - return 0; - } - - // Loop to handle responses (CMD response or DMA requests) - while (true) { - // Peek message header to determine type - msg_header_t header; - if (!recv_header(header)) { - return 0; - } - - // Handle based on message type - if (header.msg_type == MSG_TYPE_CMD_RESP) { - // Receive CMD response - cmd_resp_t cmd_resp; - if (!recv_cmd_response(cmd_resp)) { - return 0; - } - return cmd_resp.result; - - } else if (header.msg_type == MSG_TYPE_DMA_READ_REQ) { - // Receive DMA read request - dma_read_req_t dma_read_req; - if (!recv_dma_read_request(dma_read_req)) { - return 0; - } - - // Handle DMA read - uint64_t read_data = - handle_dma_read(dma_read_req.addr, dma_read_req.size); - - // Send DMA read response - dma_read_resp_t dma_read_resp; - dma_read_resp.header.msg_type = MSG_TYPE_DMA_READ_RESP; - dma_read_resp.header.reserved = 0; - dma_read_resp.data = read_data; - - if (!send_dma_read_response(dma_read_resp)) { - return 0; - } - - } else if (header.msg_type == MSG_TYPE_DMA_WRITE_REQ) { - // Receive DMA write request - dma_write_req_t dma_write_req; - if (!recv_dma_write_request(dma_write_req)) { - return 0; - } - - // Handle DMA write - handle_dma_write(dma_write_req.addr, dma_write_req.data, - dma_write_req.size); - - // Send DMA write response - dma_write_resp_t dma_write_resp; - dma_write_resp.header.msg_type = MSG_TYPE_DMA_WRITE_RESP; - dma_write_resp.header.reserved = 0; - dma_write_resp.reserved = 0; - - if (!send_dma_write_response(dma_write_resp)) { - return 0; - } - - } else { - fprintf(stderr, "Socket: Unknown message type %d\n", header.msg_type); - close(); - return 0; - } - } -} diff --git a/bebop/host/ipc/src/socket/socket_cmd.cc b/bebop/host/ipc/src/socket/socket_cmd.cc deleted file mode 100644 index 88b65c3b..00000000 --- a/bebop/host/ipc/src/socket/socket_cmd.cc +++ /dev/null @@ -1,45 +0,0 @@ -#include "ipc/socket.h" -#include -#include - -// CMD path: send command request -bool SocketClient::send_cmd_request(const cmd_req_t &req) { - if (sock_fd < 0) { - fprintf(stderr, "Socket: Not connected, cannot send CMD request\n"); - return false; - } - - fprintf(stderr, "Socket: Sending CMD request: sizeof(req)=%zu, funct=%u\n", - sizeof(req), req.funct); - ssize_t sent = send(sock_fd, &req, sizeof(req), 0); - if (sent < 0) { - fprintf(stderr, "Socket: Failed to send CMD request\n"); - close(); - return false; - } - fprintf(stderr, "Socket: Sent %zd bytes\n", sent); - - return true; -} - -// CMD path: receive command response -bool SocketClient::recv_cmd_response(cmd_resp_t &resp) { - if (sock_fd < 0) { - fprintf(stderr, "Socket: Not connected, cannot receive CMD response\n"); - return false; - } - - ssize_t received = recv(sock_fd, &resp, sizeof(resp), 0); - - if (received < 0) { - fprintf(stderr, "Socket: Failed to receive CMD response\n"); - close(); - return false; - } else if (received == 0) { - fprintf(stderr, "Socket: Connection closed by remote\n"); - close(); - return false; - } - - return true; -} diff --git a/bebop/host/ipc/src/socket/socket_dma.cc b/bebop/host/ipc/src/socket/socket_dma.cc deleted file mode 100644 index d7febc4f..00000000 --- a/bebop/host/ipc/src/socket/socket_dma.cc +++ /dev/null @@ -1,104 +0,0 @@ -#include "ipc/socket.h" -#include -#include - -// DMA path: receive DMA read request -bool SocketClient::recv_dma_read_request(dma_read_req_t &req) { - if (sock_fd < 0) { - fprintf(stderr, "Socket: Not connected, cannot receive DMA read request\n"); - return false; - } - - ssize_t received = recv(sock_fd, &req, sizeof(req), 0); - - if (received < 0) { - fprintf(stderr, "Socket: Failed to receive DMA read request\n"); - close(); - return false; - } else if (received == 0) { - fprintf(stderr, "Socket: Connection closed by remote\n"); - close(); - return false; - } - - return true; -} - -// DMA path: send DMA read response -bool SocketClient::send_dma_read_response(const dma_read_resp_t &resp) { - if (sock_fd < 0) { - fprintf(stderr, "Socket: Not connected, cannot send DMA read response\n"); - return false; - } - - ssize_t sent = send(sock_fd, &resp, sizeof(resp), 0); - if (sent < 0) { - fprintf(stderr, "Socket: Failed to send DMA read response\n"); - close(); - return false; - } - - return true; -} - -// DMA path: receive DMA write request -bool SocketClient::recv_dma_write_request(dma_write_req_t &req) { - if (sock_fd < 0) { - fprintf(stderr, - "Socket: Not connected, cannot receive DMA write request\n"); - return false; - } - - ssize_t received = recv(sock_fd, &req, sizeof(req), 0); - - if (received < 0) { - fprintf(stderr, "Socket: Failed to receive DMA write request\n"); - close(); - return false; - } else if (received == 0) { - fprintf(stderr, "Socket: Connection closed by remote\n"); - close(); - return false; - } - - return true; -} - -// DMA path: send DMA write response -bool SocketClient::send_dma_write_response(const dma_write_resp_t &resp) { - if (sock_fd < 0) { - fprintf(stderr, "Socket: Not connected, cannot send DMA write response\n"); - return false; - } - - ssize_t sent = send(sock_fd, &resp, sizeof(resp), 0); - if (sent < 0) { - fprintf(stderr, "Socket: Failed to send DMA write response\n"); - close(); - return false; - } - - return true; -} - -// DMA handlers -uint64_t SocketClient::handle_dma_read(uint64_t addr, uint32_t size) { - if (!dma_read_cb) { - fprintf(stderr, "Socket: DMA read callback not set\n"); - return 0; - } - uint64_t value = dma_read_cb(addr, size); - printf("Socket: DMA read addr=0x%lx size=%d value=0x%lx\n", addr, size, - value); - return value; -} - -void SocketClient::handle_dma_write(uint64_t addr, uint64_t data, - uint32_t size) { - if (!dma_write_cb) { - fprintf(stderr, "Socket: DMA write callback not set\n"); - return; - } - dma_write_cb(addr, data, size); - printf("Socket: DMA write addr=0x%lx size=%d data=0x%lx\n", addr, size, data); -} diff --git a/bebop/host/spike/CMakeLists.txt b/bebop/host/spike/CMakeLists.txt deleted file mode 100644 index 0059c828..00000000 --- a/bebop/host/spike/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -add_subdirectory(customext) diff --git a/bebop/host/spike/customext/CMakeLists.txt b/bebop/host/spike/customext/CMakeLists.txt deleted file mode 100644 index 1c4f5c3d..00000000 --- a/bebop/host/spike/customext/CMakeLists.txt +++ /dev/null @@ -1,38 +0,0 @@ -cmake_minimum_required(VERSION 3.10) -project(bebop) - -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fPIC -O3") -set(SPIKE_ROOT "${CMAKE_CURRENT_SOURCE_DIR}/../riscv-isa-sim") -set(SPIKE_PREFIX "${SPIKE_ROOT}/install") - -set(SPIKE_INCLUDE "${SPIKE_PREFIX}/include") -set(SPIKE_LIB_DIR "${SPIKE_PREFIX}/lib") - -link_directories("${SPIKE_LIB_DIR}") -set(CMAKE_INSTALL_RPATH "${SPIKE_LIB_DIR}") -set(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE) - -set(BEBOP_INSTALL_LIB_DIR "${SPIKE_LIB_DIR}") - -add_library(bebop SHARED - src/bebop.cc -) - -if(NOT TARGET bebop_ipc) - add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../ipc - ${CMAKE_CURRENT_BINARY_DIR}/ipc) -endif() - - -target_include_directories(bebop PRIVATE - ${SPIKE_INCLUDE} - ${CMAKE_CURRENT_SOURCE_DIR}/include -) - -target_link_libraries(bebop PRIVATE bebop_ipc) - -set_target_properties(bebop PROPERTIES OUTPUT_NAME "bebop") - -install(TARGETS bebop - LIBRARY DESTINATION ${BEBOP_INSTALL_LIB_DIR} -) diff --git a/bebop/host/spike/customext/include/bebop.h b/bebop/host/spike/customext/include/bebop.h deleted file mode 100644 index 425a7f99..00000000 --- a/bebop/host/spike/customext/include/bebop.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef _BEBOP_H -#define _BEBOP_H - -#include "common.h" -#include -#include -#include -#include - -#define MAKECUSTOMFN(opcode) custom##opcode -#define CUSTOMFN(opcode) MAKECUSTOMFN(opcode) - -// Forward declaration -class SocketClient; - -struct bebop_state_t { - void reset(); - bool enable; - bool resetted = false; -}; - -class bebop_t : public extension_t { -public: - bebop_t(); - ~bebop_t(); - const char *name() const override { return "bebop"; } - - reg_t CUSTOMFN(XCUSTOM_ACC)(rocc_insn_t insn, reg_t xs1, reg_t xs2); - void set_processor(processor_t *p) { this->p = p; } - std::vector get_instructions(const processor_t &proc) override; - std::vector - get_disasms(const processor_t *proc = nullptr) override; - -private: - bebop_state_t bebop_state; - processor_t *p; - - // Socket client - std::unique_ptr socket_client; - template T read_from_dram(reg_t addr); - template void write_to_dram(reg_t addr, T data); -}; - -#endif // _BEBOP_H diff --git a/bebop/host/spike/customext/include/common.h b/bebop/host/spike/customext/include/common.h deleted file mode 100644 index 706a1269..00000000 --- a/bebop/host/spike/customext/include/common.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _COMMON_H -#define _COMMON_H - -#include -#include - -#define XCUSTOM_ACC 3 - -#endif // _COMMON_H diff --git a/bebop/host/spike/customext/src/bebop.cc b/bebop/host/spike/customext/src/bebop.cc deleted file mode 100644 index 7121d96f..00000000 --- a/bebop/host/spike/customext/src/bebop.cc +++ /dev/null @@ -1,124 +0,0 @@ -#include "bebop.h" -#include "ipc/socket.h" -#include -#include -#include -#include - -using namespace std; - -REGISTER_EXTENSION(bebop, []() { return new bebop_t; }) - -bebop_t::bebop_t() : socket_client(new SocketClient()) {} - -bebop_t::~bebop_t() { - // socket_client will be automatically destroyed -} - -#define dprintf(...) \ - { \ - if (p->get_log_commits_enabled()) \ - printf(__VA_ARGS__); \ - } - -template T bebop_t::read_from_dram(reg_t addr) { - T value = 0; - for (size_t byte_idx = 0; byte_idx < sizeof(T); ++byte_idx) { - value |= p->get_mmu()->load(addr + byte_idx) << (byte_idx * 8); - } - return value; -} - -template void bebop_t::write_to_dram(reg_t addr, T data) { - for (size_t byte_idx = 0; byte_idx < sizeof(T); ++byte_idx) { - p->get_mmu()->store(addr + byte_idx, - (data >> (byte_idx * 8)) & 0xFF); - } -} - -void bebop_state_t::reset() { - enable = true; - resetted = true; -} - -reg_t bebop_t::CUSTOMFN(XCUSTOM_ACC)(rocc_insn_t insn, reg_t xs1, reg_t xs2) { - - if (!bebop_state.resetted) { - bebop_state.reset(); - } - - auto read_cb = [this](uint64_t addr, uint32_t size) -> uint64_t { - switch (size) { - case 1: - return read_from_dram(addr); - case 2: - return read_from_dram(addr); - case 4: - return read_from_dram(addr); - case 8: - return read_from_dram(addr); - default: - fprintf(stderr, "bebop: Invalid DMA read size %u\n", size); - return 0; - } - }; - - auto write_cb = [this](uint64_t addr, uint64_t data, uint32_t size) { - switch (size) { - case 1: - write_to_dram(addr, static_cast(data)); - break; - case 2: - write_to_dram(addr, static_cast(data)); - break; - case 4: - write_to_dram(addr, static_cast(data)); - break; - case 8: - write_to_dram(addr, data); - break; - default: - fprintf(stderr, "bebop: Invalid DMA write size %u\n", size); - break; - } - }; - - socket_client->set_dma_callbacks(read_cb, write_cb); - - // Send socket request and wait for response - dprintf("bebop: Processing custom instruction with funct=%d\n", insn.funct); - reg_t result = socket_client->send_and_wait(insn.funct, xs1, xs2); - - dprintf("bebop: custom instruction funct=%d completed with result=0x%lx\n", - insn.funct, result); - - return result; -} - -static reg_t bebop_custom(processor_t *p, insn_t insn, reg_t pc) { - bebop_t *bebop = static_cast(p->get_extension("bebop")); - rocc_insn_union_t u; - state_t *state = p->get_state(); - bebop->set_processor(p); - u.i = insn; - reg_t xs1 = u.r.xs1 ? state->XPR[insn.rs1()] : -1; - reg_t xs2 = u.r.xs2 ? state->XPR[insn.rs2()] : -1; - reg_t xd = bebop->CUSTOMFN(XCUSTOM_ACC)(u.r, xs1, xs2); - if (u.r.xd) { - state->log_reg_write[insn.rd() << 4] = {xd, 0}; - state->XPR.write(insn.rd(), xd); - } - return pc + 4; -} - -std::vector bebop_t::get_instructions(const processor_t &proc) { - std::vector insns; - push_custom_insn(insns, ROCC_OPCODE3, ROCC_OPCODE_MASK, ILLEGAL_INSN_FUNC, - bebop_custom); - return insns; -} - -std::vector bebop_t::get_disasms(const processor_t *proc) { - std::vector insns; - return insns; -} diff --git a/bebop/host/spike/install-spike.sh b/bebop/host/spike/install-spike.sh deleted file mode 100755 index 79d8b816..00000000 --- a/bebop/host/spike/install-spike.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env bash - -set -euo pipefail - -SCRIPT_DIR="$(dirname "$(realpath "$0")")" -# HOST_ROOT="$(cd "${SCRIPT_DIR}/.." && pwd)" -SPIKE_SRC="${SCRIPT_DIR}/riscv-isa-sim" -SPIKE_BUILD="${SPIKE_SRC}/build" -SPIKE_INSTALL="${SPIKE_SRC}/install" -# HOST_BUILD="${HOST_ROOT}/build" - -mkdir -p "${SPIKE_BUILD}" -( - cd "${SPIKE_BUILD}" - ../configure --prefix="${SPIKE_INSTALL}" \ - --with-boost=no \ - --with-boost-asio=no \ - --with-boost-regex=no - make -j$(nproc) - make install -) - -cd ${SCRIPT_DIR} -mkdir -p build && cd build -cmake .. -make install diff --git a/bebop/host/spike/riscv-isa-sim b/bebop/host/spike/riscv-isa-sim deleted file mode 160000 index 88edb8b8..00000000 --- a/bebop/host/spike/riscv-isa-sim +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 88edb8b81383bf282949be30476c9e4d5459cec4 diff --git a/bebop/scripts/bebop_setup.sh b/bebop/scripts/bebop_setup.sh deleted file mode 100755 index 5827900a..00000000 --- a/bebop/scripts/bebop_setup.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash - -SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" -BEBOP_DIR="$(dirname "$SCRIPT_DIR")" -BEBOP_BIN="$BEBOP_DIR/bebop/target/release/bebop" - -cd "$BEBOP_DIR/bebop" -cargo build --release --bin bebop - -if [ $? -ne 0 ]; then - echo "Error: Failed to build bebop" - exit 1 -fi - -if netstat -tuln 2>/dev/null | grep -q ":9999 "; then - echo "Warning: Port 9999 is already in use" - echo "Please stop the existing process or change SOCKET_PORT" - exit 1 -fi - -echo "Starting Bebop simulator..." -echo "Listening on 127.0.0.1:9999" -echo "Press Ctrl+C to stop" -echo "" - -exec "$BEBOP_BIN" From f58fca0f833cab9e5b5fab9e470901dd902db82c Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 11 Jan 2026 17:27:16 +0800 Subject: [PATCH 056/238] [bb-tests/ctest] refactor: replace bb_mset for memory allocation consistency --- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 18 +-- bb-tests/workloads/lib/bbhw/isa/isa.h | 12 +- bb-tests/workloads/src/CTest/CMakeLists.txt | 2 + .../workloads/src/CTest/bebop/CMakeLists.txt | 115 ++++++++++++++++++ .../src/CTest/bebop/mvin_mvout_acc_test.c | 47 +++++++ .../src/CTest/bebop/mvin_mvout_mset_test.c | 48 ++++++++ .../src/CTest/bebop/mvin_mvout_test.c | 46 +++++++ .../workloads/src/CTest/toy/aligned_matmul.c | 2 +- .../src/CTest/toy/bbfp_matmul_random1.c | 2 +- .../src/CTest/toy/bbfp_matmul_random2.c | 2 +- .../src/CTest/toy/bbfp_matmul_random3.c | 2 +- bb-tests/workloads/src/CTest/toy/bbfpmatmul.c | 2 +- bb-tests/workloads/src/CTest/toy/bbfptest.c | 2 +- bb-tests/workloads/src/CTest/toy/cim_test.c | 2 +- .../workloads/src/CTest/toy/im2col_test.c | 2 +- .../src/CTest/toy/mvin_mvout_acc_test.c | 4 +- .../workloads/src/CTest/toy/tiled_matmul.c | 6 +- .../src/CTest/toy/transpose_matmul.c | 2 +- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 2 +- .../CTest/toy/vecunit_matmul_16xn_random1.c | 2 +- .../CTest/toy/vecunit_matmul_16xn_random2.c | 2 +- .../CTest/toy/vecunit_matmul_16xn_random3.c | 2 +- .../toy/vecunit_matmul_16xn_zero_random.c | 2 +- .../CTest/toy/vecunit_matmul_col_row_vector.c | 2 +- .../toy/vecunit_matmul_identity_random.c | 2 +- .../src/CTest/toy/vecunit_matmul_ones.c | 2 +- .../src/CTest/toy/vecunit_matmul_random1.c | 2 +- .../src/CTest/toy/vecunit_matmul_random2.c | 2 +- .../src/CTest/toy/vecunit_matmul_random3.c | 2 +- .../CTest/toy/vecunit_matmul_row_col_vector.c | 2 +- .../CTest/toy/vecunit_matmul_zero_random.c | 2 +- .../toy/vecunit_simple_nn_forward_pass_test.c | 2 +- 32 files changed, 303 insertions(+), 41 deletions(-) create mode 100644 bb-tests/workloads/src/CTest/bebop/CMakeLists.txt create mode 100644 bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c create mode 100644 bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c create mode 100644 bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index d1600937..4196cff4 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -5,14 +5,14 @@ #define BB_MSET_FUNC7 23 -#define bb_mset(relase_en, bank_id, alloc_en, bank_num, row, col) \ - ({ \ - BUCKYBALL_INSTRUCTION_R_R((FIELD(alloc_en, 0, 0) | FIELD(bank_id, 1, 13)), \ - (FIELD(relase_en, 0, 0) | \ - FIELD(bank_num, 1, 5) | FIELD(row, 6, 9) | \ - FIELD(col, 10, 17)), \ - BB_MSET_FUNC7); \ - (bank_id); \ - }) +#define bb_mset(relase_en, bank_id, alloc_en, row, col) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(relase_en, 0, 0) | FIELD(bank_id, 1, 13)), \ + (FIELD(alloc_en, 0, 0) | FIELD(row, 1, 5) | FIELD(col, 6, 13)), \ + BB_MSET_FUNC7) + +#define bb_mem_release(bank_id) bb_mset(1, bank_id, 0, 0, 0); + +#define bb_mem_alloc(row, col) bb_mset(0, 0, 1, row, col) #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index ae7eddfa..69b6194f 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -23,10 +23,14 @@ typedef int32_t result_t; // Generic RISC-V custom instruction macro #define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c2, x0, %0, %1" \ - : \ - : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ - : "memory") + ({ \ + unsigned long __result; \ + asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c3, %0, %1, %2" \ + : "=r"(__result) \ + : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ + : "memory"); \ + __result; \ + }) // Include all instruction definitions #include "23_mset.c" diff --git a/bb-tests/workloads/src/CTest/CMakeLists.txt b/bb-tests/workloads/src/CTest/CMakeLists.txt index 0a37b932..926585cb 100644 --- a/bb-tests/workloads/src/CTest/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/CMakeLists.txt @@ -1,7 +1,9 @@ set(CTEST_GEMMINI_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/gemmini) set(CTEST_TOY_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/toy) set(CTEST_RVV_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/rvv) +set(CTEST_BEBOP_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/bebop) add_subdirectory(gemmini) add_subdirectory(toy) add_subdirectory(rvv) +add_subdirectory(bebop) diff --git a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt new file mode 100644 index 00000000..2f115b39 --- /dev/null +++ b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt @@ -0,0 +1,115 @@ +set(ELF_CC "riscv64-unknown-elf-gcc") +set(LINUX_CC "riscv64-unknown-linux-gnu-g++") + +#------------------------------------------------------------------------------- +# Set baremetal compilation flags +#------------------------------------------------------------------------------- +set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany + -fno-builtin-printf -specs=htif_nano.specs -I${CTEST_TOY_WORKLOAD_DIR}) + +#------------------------------------------------------------------------------- +# Define common compilation step functions +#------------------------------------------------------------------------------- + +#------------------------------------------------------------------------------- +# Generate executables for different platforms +#------------------------------------------------------------------------------- +set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") +set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-g++") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gc") +# Generate Linux version executables +function(add_linux_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}-linux") + + add_executable(${EXECUTABLE} ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c) + target_include_directories(${EXECUTABLE} PRIVATE + ${WORKLOAD_LIB_DIR} + ) + # Ensure dependent libraries are built first and link merged library files + add_dependencies(${EXECUTABLE} bbhw-linux) + target_link_libraries(${EXECUTABLE} ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-linux.a) +endfunction() + +# Generate multicore baremetal version executables +function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}_multicore-baremetal") + + add_custom_command( + OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} + COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} ${CTEST_TOY_WORKLOAD_DIR}/start.S + -DMULTICORE=3 + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c + ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + -I${WORKLOAD_LIB_DIR} + ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a + DEPENDS ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_TOY_WORKLOAD_DIR}/start.S + ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a + COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + + add_custom_target(${TEST_NAME}_multicore_baremetal + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal ) +endfunction() + +# Generate singlecore baremetal version executables +function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}_singlecore-baremetal") + + add_custom_command( + OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} + COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c + ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + -I${WORKLOAD_LIB_DIR} + ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a + DEPENDS ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c + ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a + COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + + add_custom_target(${TEST_NAME}_singlecore_baremetal + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal + ) +endfunction() + +# Create cross-platform test targets +function(add_cross_platform_test_target TEST_NAME SOURCE_FILE) + add_linux_test_target(${TEST_NAME} ${SOURCE_FILE}) + add_multicore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) + add_singlecore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) + + # Create a master target that builds all platforms simultaneously + add_custom_target(${TEST_NAME} + DEPENDS ${TEST_NAME}-linux ${TEST_NAME}_multicore_baremetal ${TEST_NAME}_singlecore_baremetal + COMMENT "Building ${TEST_NAME} for all platforms" + ) +endfunction() + +#------------------------------------------------------------------------------- +# build linux version workload (current not supported) +#------------------------------------------------------------------------------- +set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${LINK_FLAGS}") + +# add_library(buckyball-lib STATIC ${CTEST_WORKLOAD_DIR}/buckyball.c) +# target_include_directories(buckyball-lib PRIVATE ${WORKLOAD_LIB_DIR}) + +#------------------------------------------------------------------------------- +# Build list - use cross-platform function to generate all test targets +#------------------------------------------------------------------------------- +add_cross_platform_test_target(ctest_mvin_mvout_bebop_test mvin_mvout_test.c) +add_cross_platform_test_target(ctest_mvin_mvout_mset_bebop_test mvin_mvout_mset_test.c) +add_cross_platform_test_target(ctest_mvin_mvout_acc_bebop_test mvin_mvout_acc_test.c) + +# Create master build target +add_custom_target(buckyball-CTest-bebop-build ALL DEPENDS + ctest_mvin_mvout_bebop_test + ctest_mvin_mvout_mset_bebop_test + ctest_mvin_mvout_acc_bebop_test + COMMENT "Building all workloads for Buckyball" + VERBATIM) diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c new file mode 100644 index 00000000..cfdec9b9 --- /dev/null +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c @@ -0,0 +1,47 @@ +#include "../toy/buckyball.h" +#include +#include +#include +#include +#include + +#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) + +// Test matrices +static int32_t input_matrix[DIM * DIM] __attribute__((aligned(16))); +static int32_t output_matrix[DIM * DIM] __attribute__((aligned(16))); + +int mvin_mvout_acc_test() { + for (int i = 0; i < 4; i++) { + init_i32_random_matrix(input_matrix, DIM, DIM, 111); + int acc_bank_id = bb_mem_alloc(1, 4); // row, col + bb_mvin((uintptr_t)input_matrix, acc_bank_id, DIM, 1); + clear_i32_matrix(output_matrix, DIM, DIM); + bb_fence(); + bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); + bb_fence(); + bb_mem_release(acc_bank_id); + if (!compare_i32_matrices(output_matrix, input_matrix, DIM, DIM)) { + printf("Test mvin/mvout simple %d FAILED\n", i); + return 0; + } else { + printf("Test mvin/mvout simple %d PASSED\n", i); + } + } + return 1; +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + int passed = mvin_mvout_acc_test(); + if (passed) { + printf("mvin/mvout simple test PASSED\n"); + } else { + printf("mvin/mvout simple test FAILED\n"); + } +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c new file mode 100644 index 00000000..9e4a5477 --- /dev/null +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c @@ -0,0 +1,48 @@ +#include "../toy/buckyball.h" +#include +#include +#include +#include +#include + +#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) +#define DIM2 1024 + +// Test matrices +static elem_t input_matrix[DIM * DIM2] __attribute__((aligned(16))); +static elem_t output_matrix[DIM * DIM2] __attribute__((aligned(16))); + +int mvin_mvout_simple_test() { + for (int i = 0; i < 4; i++) { + init_u8_random_matrix(input_matrix, DIM, DIM2, 111); + int vbank_id = bb_mem_alloc(1, 1); + bb_mvin((uintptr_t)input_matrix, vbank_id, DIM2, 1); + clear_u8_matrix(output_matrix, DIM, DIM2); + bb_fence(); + bb_mvout((uintptr_t)output_matrix, vbank_id, DIM2, 1); + bb_fence(); + bb_mem_release(vbank_id); + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM2)) { + printf("Test mvin/mvout simple %d FAILED\n", i); + return 0; + } else { + printf("Test mvin/mvout simple %d PASSED\n", i); + } + } + return 1; +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + int passed = mvin_mvout_simple_test(); + if (passed) { + printf("mvin/mvout simple test PASSED\n"); + } else { + printf("mvin/mvout simple test FAILED\n"); + } +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c new file mode 100644 index 00000000..09363ab9 --- /dev/null +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c @@ -0,0 +1,46 @@ +#include "../toy/buckyball.h" +#include +#include +#include +#include +#include + +#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) +#define DIM2 1024 + +// Test matrices +static elem_t input_matrix[DIM * DIM2] __attribute__((aligned(16))); +static elem_t output_matrix[DIM * DIM2] __attribute__((aligned(16))); + +int mvin_mvout_simple_test() { + for (int i = 0; i < 4; i++) { + init_u8_random_matrix(input_matrix, DIM, DIM2, 111); + bb_mvin((uintptr_t)input_matrix, 0, DIM2, 1); + clear_u8_matrix(output_matrix, DIM, DIM2); + bb_fence(); + bb_mvout((uintptr_t)output_matrix, 0, DIM2, 1); + bb_fence(); + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM2)) { + printf("Test mvin/mvout simple %d FAILED\n", i); + return 0; + } else { + printf("Test mvin/mvout simple %d PASSED\n", i); + } + } + return 1; +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + int passed = mvin_mvout_simple_test(); + if (passed) { + printf("mvin/mvout simple test PASSED\n"); + } else { + printf("mvin/mvout simple test FAILED\n"); + } +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index 6a69b237..535a4478 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -28,7 +28,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, op2_bank_id, DIM << 2, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c index 6daaf06e..e53fd22f 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c @@ -15,7 +15,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c index 566a0e30..72f11c48 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c @@ -15,7 +15,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c index 24b8b574..942ab318 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c @@ -15,7 +15,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c index 5d629872..128d82ad 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c +++ b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c @@ -49,7 +49,7 @@ int main() { // Move input to scratchpad uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)weight_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)input_matrix, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/bbfptest.c b/bb-tests/workloads/src/CTest/toy/bbfptest.c index 87a87e2b..b27bd632 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfptest.c +++ b/bb-tests/workloads/src/CTest/toy/bbfptest.c @@ -57,7 +57,7 @@ int main() { // Move input to scratchpad uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)input_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)weight_matrix, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/cim_test.c b/bb-tests/workloads/src/CTest/toy/cim_test.c index 98706480..2f8b2fd4 100644 --- a/bb-tests/workloads/src/CTest/toy/cim_test.c +++ b/bb-tests/workloads/src/CTest/toy/cim_test.c @@ -95,7 +95,7 @@ int run_test(const char *test_name, elem_t *op1, elem_t *op2, elem_t *result, cim_cpu_reference(op1, op2, expected_result, rows, cols, op_type); // Allocate accumulator bank - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); // Hardware computation hw_cim(test_name, op1, op2, result, rows, cols, op_type, acc_bank_id); diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 59351bc1..74a73a35 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -14,7 +14,7 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); uint64_t krow = 4; diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index fefae780..34a1f107 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -18,12 +18,12 @@ int acc_mvin_mvout_pressure_test() { for (int i = 0; i < 4; i++) { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); - uint32_t acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + uint32_t acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM << 2, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); - acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + acc_bank_id = bb_mem_alloc(1, 4); bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM << 2, 1); bb_fence(); if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { diff --git a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c index a359f906..0f84d366 100644 --- a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c @@ -23,7 +23,7 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -75,7 +75,7 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -139,7 +139,7 @@ int run_test(const char *test_name) { clear_u32_matrix(output_c, DIM_I, DIM_K); // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); // TODO: ACC overwrite write can skip this step bb_mvin((uintptr_t)output_c, acc_bank_id, DIM_I * DIM_K * 4 / DIM, 1); tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index 0a49d6f3..73e5facf 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); uint32_t col_stride = (size + DIM - 1) / DIM; for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index 4a13661d..511f0052 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 3d48e92c..cb0c8743 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -19,7 +19,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 4e16546f..8be3357d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index 9174666e..946f419d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index be8938f2..beefedc6 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index f13868e1..e2ce1d3b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -21,7 +21,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 0139d6ab..460c6393 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index dd86eae6..f7fa2e4e 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index 4aa03053..cb0c464a 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 10352d1f..1120d0eb 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index c6ac9b3d..071947a9 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index e2e949ee..56fa6c65 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index 77400b1a..a212e222 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -20,7 +20,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index 5c3132a7..b8aa8297 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -63,7 +63,7 @@ void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mset(0, 0, 1, 4, 1, 4); + int acc_bank_id = bb_mem_alloc(1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); From c9b48ffeb7f9e4e567e088f4e7958536c4da32c9 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 11 Jan 2026 17:40:01 +0800 Subject: [PATCH 057/238] [bb-tests/ctest] refactor: update memory allocation to use virtual bank ID --- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 2 +- bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c | 3 +-- bb-tests/workloads/lib/bbhw/isa/isa.h | 12 ++++-------- .../workloads/src/CTest/bebop/mvin_mvout_acc_test.c | 3 ++- .../workloads/src/CTest/bebop/mvin_mvout_mset_test.c | 3 ++- bb-tests/workloads/src/CTest/toy/aligned_matmul.c | 3 ++- .../workloads/src/CTest/toy/bbfp_matmul_random1.c | 3 ++- .../workloads/src/CTest/toy/bbfp_matmul_random2.c | 3 ++- .../workloads/src/CTest/toy/bbfp_matmul_random3.c | 3 ++- bb-tests/workloads/src/CTest/toy/bbfpmatmul.c | 3 ++- bb-tests/workloads/src/CTest/toy/bbfptest.c | 3 ++- bb-tests/workloads/src/CTest/toy/cim_test.c | 3 ++- bb-tests/workloads/src/CTest/toy/im2col_test.c | 3 ++- .../workloads/src/CTest/toy/mvin_mvout_acc_test.c | 6 ++++-- bb-tests/workloads/src/CTest/toy/tiled_matmul.c | 9 ++++++--- bb-tests/workloads/src/CTest/toy/transpose_matmul.c | 3 ++- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 3 ++- .../src/CTest/toy/vecunit_matmul_16xn_random1.c | 3 ++- .../src/CTest/toy/vecunit_matmul_16xn_random2.c | 3 ++- .../src/CTest/toy/vecunit_matmul_16xn_random3.c | 3 ++- .../src/CTest/toy/vecunit_matmul_16xn_zero_random.c | 3 ++- .../src/CTest/toy/vecunit_matmul_col_row_vector.c | 3 ++- .../src/CTest/toy/vecunit_matmul_identity_random.c | 3 ++- .../workloads/src/CTest/toy/vecunit_matmul_ones.c | 3 ++- .../workloads/src/CTest/toy/vecunit_matmul_random1.c | 3 ++- .../workloads/src/CTest/toy/vecunit_matmul_random2.c | 3 ++- .../workloads/src/CTest/toy/vecunit_matmul_random3.c | 3 ++- .../src/CTest/toy/vecunit_matmul_row_col_vector.c | 3 ++- .../src/CTest/toy/vecunit_matmul_zero_random.c | 3 ++- .../CTest/toy/vecunit_simple_nn_forward_pass_test.c | 3 ++- 30 files changed, 66 insertions(+), 41 deletions(-) diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index 4196cff4..6ee779d7 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -13,6 +13,6 @@ #define bb_mem_release(bank_id) bb_mset(1, bank_id, 0, 0, 0); -#define bb_mem_alloc(row, col) bb_mset(0, 0, 1, row, col) +#define bb_mem_alloc(bank_id, row, col) bb_mset(0, bank_id, 1, row, col) #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c index f1397080..91feb36a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c @@ -8,7 +8,6 @@ #define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(mode, 24, 24)), \ - BB_MUL_WARP16_FUNC7) + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_MUL_WARP16_FUNC7) #endif // _BB_MUL_WARP16_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 69b6194f..ae7eddfa 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -23,14 +23,10 @@ typedef int32_t result_t; // Generic RISC-V custom instruction macro #define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ - ({ \ - unsigned long __result; \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c3, %0, %1, %2" \ - : "=r"(__result) \ - : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ - : "memory"); \ - __result; \ - }) + asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c2, x0, %0, %1" \ + : \ + : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ + : "memory") // Include all instruction definitions #include "23_mset.c" diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c index cfdec9b9..0f1a9259 100644 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c @@ -14,7 +14,8 @@ static int32_t output_matrix[DIM * DIM] __attribute__((aligned(16))); int mvin_mvout_acc_test() { for (int i = 0; i < 4; i++) { init_i32_random_matrix(input_matrix, DIM, DIM, 111); - int acc_bank_id = bb_mem_alloc(1, 4); // row, col + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); // bank_id, row, col bb_mvin((uintptr_t)input_matrix, acc_bank_id, DIM, 1); clear_i32_matrix(output_matrix, DIM, DIM); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c index 9e4a5477..2f6b41e8 100644 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c @@ -15,7 +15,8 @@ static elem_t output_matrix[DIM * DIM2] __attribute__((aligned(16))); int mvin_mvout_simple_test() { for (int i = 0; i < 4; i++) { init_u8_random_matrix(input_matrix, DIM, DIM2, 111); - int vbank_id = bb_mem_alloc(1, 1); + int vbank_id = 2; // virtual bank id + bb_mem_alloc(vbank_id, 1, 1); bb_mvin((uintptr_t)input_matrix, vbank_id, DIM2, 1); clear_u8_matrix(output_matrix, DIM, DIM2); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index 535a4478..2cfa465d 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -28,7 +28,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, op2_bank_id, DIM << 2, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c index e53fd22f..ae3f4fb2 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c @@ -15,7 +15,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c index 72f11c48..2eb65070 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c @@ -15,7 +15,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c index 942ab318..ec1430ef 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c @@ -15,7 +15,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c index 128d82ad..7837e8c3 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c +++ b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c @@ -49,7 +49,8 @@ int main() { // Move input to scratchpad uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)weight_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)input_matrix, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/bbfptest.c b/bb-tests/workloads/src/CTest/toy/bbfptest.c index b27bd632..a3ac1731 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfptest.c +++ b/bb-tests/workloads/src/CTest/toy/bbfptest.c @@ -57,7 +57,8 @@ int main() { // Move input to scratchpad uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)input_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)weight_matrix, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/cim_test.c b/bb-tests/workloads/src/CTest/toy/cim_test.c index 2f8b2fd4..83c3ddb9 100644 --- a/bb-tests/workloads/src/CTest/toy/cim_test.c +++ b/bb-tests/workloads/src/CTest/toy/cim_test.c @@ -95,7 +95,8 @@ int run_test(const char *test_name, elem_t *op1, elem_t *op2, elem_t *result, cim_cpu_reference(op1, op2, expected_result, rows, cols, op_type); // Allocate accumulator bank - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); // Hardware computation hw_cim(test_name, op1, op2, result, rows, cols, op_type, acc_bank_id); diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 74a73a35..7b8be15f 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -14,7 +14,8 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); uint64_t krow = 4; diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index 34a1f107..c981757f 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -18,12 +18,14 @@ int acc_mvin_mvout_pressure_test() { for (int i = 0; i < 4; i++) { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); - uint32_t acc_bank_id = bb_mem_alloc(1, 4); + uint32_t acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM << 2, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); - acc_bank_id = bb_mem_alloc(1, 4); + acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM << 2, 1); bb_fence(); if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { diff --git a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c index 0f84d366..6f323859 100644 --- a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c @@ -23,7 +23,8 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -75,7 +76,8 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -139,7 +141,8 @@ int run_test(const char *test_name) { clear_u32_matrix(output_c, DIM_I, DIM_K); // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); // TODO: ACC overwrite write can skip this step bb_mvin((uintptr_t)output_c, acc_bank_id, DIM_I * DIM_K * 4 / DIM, 1); tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index 73e5facf..700c89b1 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -24,7 +24,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t col_stride = (size + DIM - 1) / DIM; for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index 511f0052..dfb8fb7e 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index cb0c8743..f7fb0100 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -19,7 +19,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 8be3357d..380bb0b8 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index 946f419d..ef890762 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index beefedc6..3e9d0e0d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index e2ce1d3b..8b9389d0 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -21,7 +21,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 460c6393..92f178ba 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index f7fa2e4e..292fea4b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index cb0c464a..e64cf487 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 1120d0eb..55621053 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 071947a9..27dd68c9 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index 56fa6c65..bf522d6f 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index a212e222..960e554c 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -20,7 +20,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index b8aa8297..03ffb4e5 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -63,7 +63,8 @@ void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 - int acc_bank_id = bb_mem_alloc(1, 4); + int acc_bank_id = 2; // virtual bank id + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); From cc9a24b2afe501da7caae8b14ee8ccc7c51b2201 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Thu, 22 Jan 2026 18:18:24 +0800 Subject: [PATCH 058/238] Fix some bugs and simplify the logic --- .../scala/examples/toy/ToyBuckyBall.scala | 18 +-- .../framework/balldomain/bbus/bbus.scala | 42 +++--- .../bbus/memrouter/ChannelMapping.scala | 12 +- .../bbus/memrouter/ReadReqGen.scala | 6 +- .../bbus/memrouter/WriteReqGen.scala | 7 +- .../balldomain/bbus/memrouter/memRouter.scala | 48 +++--- .../balldomain/prototype/relu/Relu.scala | 4 +- .../balldomain/prototype/vector/VecUnit.scala | 4 +- .../scala/framework/memdomain/MemDomain.scala | 19 +-- .../memdomain/backend/MemBackend.scala | 142 +++++++++--------- .../memdomain/backend/accpipe/AccPipe.scala | 52 +++---- .../framework/memdomain/configs/default.json | 2 +- .../memdomain/frontend/MemFrontend.scala | 4 +- .../cmd_channel/decoder/DomainDecoder.scala | 19 +-- .../frontend/outside_channel/MemLoader.scala | 25 ++- .../frontend/outside_channel/MemStorer.scala | 25 ++- .../outside_channel/dma/StreamReader.scala | 19 +-- .../memdomain/midend/MemMidend.scala | 17 ++- bb-tests/workloads/lib/bbhw/isa/24_mvin.c | 2 +- bb-tests/workloads/lib/bbhw/isa/25_mvout.c | 2 +- .../src/CTest/toy/vecunit_matmul_ones.c | 23 +-- 21 files changed, 247 insertions(+), 245 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 53dcf40b..7a1f212a 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -112,21 +112,21 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) })) - bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid - bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id - bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id - bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id - bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits + bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid + bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id + bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id + bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id + bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready val bankReadReqQ = Queue(bankReadReqWithIds, 1) memDomain.io.ballDomain.bankRead(i).io.req.valid := bankReadReqQ.valid memDomain.io.ballDomain.bankRead(i).io.req.bits := bankReadReqQ.bits.req - memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id - memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id - memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id - bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready + memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id + memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id + memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id + bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready ballDomain.bankRead(i).io.resp <> memDomain.io.ballDomain.bankRead(i).io.resp } diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 1217ec25..4e800087 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -23,17 +23,17 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val memBallChannelNum = b.top.memBallChannelNum val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum - val memChannel = b.top.ballMemChannelNum + val memChannel = b.top.ballMemChannelNum // Rs - bbus - balls @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) // balls - bbus @public - val bankRead = IO(Vec(memChannel, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(memChannel, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) + val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) // bbus - mem // Channel interface using ChannelClusterIO @@ -74,26 +74,26 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) // Initialize ballMemChannel and memBallChannel ports with default values for (i <- 0 until ballMemChannelNum) { - ballMemChannel.channelIn(i).data.valid := false.B - ballMemChannel.channelIn(i).data.bits := 0.U + ballMemChannel.channelIn(i).data.valid := false.B + ballMemChannel.channelIn(i).data.bits := 0.U ballMemChannel.channelOut(i).data.ready := false.B } ballMemChannel.peakChannelReq.valid := false.B ballMemChannel.peakChannelReq.bits.needed_channel_num := 0.U - ballMemChannel.peakChannelReq.bits.bank_id := 0.U - ballMemChannel.peakChannelReq.bits.rob_id := 0.U - ballMemChannel.freeChannelResp.ready := true.B + ballMemChannel.peakChannelReq.bits.bank_id := 0.U + ballMemChannel.peakChannelReq.bits.rob_id := 0.U + ballMemChannel.freeChannelResp.ready := true.B for (i <- 0 until memBallChannelNum) { - memBallChannel.channelIn(i).data.valid := false.B - memBallChannel.channelIn(i).data.bits := 0.U + memBallChannel.channelIn(i).data.valid := false.B + memBallChannel.channelIn(i).data.bits := 0.U memBallChannel.channelOut(i).data.ready := false.B } memBallChannel.peakChannelReq.valid := false.B memBallChannel.peakChannelReq.bits.needed_channel_num := 0.U - memBallChannel.peakChannelReq.bits.bank_id := 0.U - memBallChannel.peakChannelReq.bits.rob_id := 0.U - memBallChannel.freeChannelResp.ready := true.B + memBallChannel.peakChannelReq.bits.bank_id := 0.U + memBallChannel.peakChannelReq.bits.rob_id := 0.U + memBallChannel.freeChannelResp.ready := true.B // ----------------------------------------------------------------------------- // memory router // ----------------------------------------------------------------------------- @@ -113,19 +113,19 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) } // Connect balls' bankRead and bankWrite to memrouter - var readChannelIdx = 0 + var readChannelIdx = 0 var writeChannelIdx = 0 - + for (ball <- balls) { val ballConfig = b.ballDomain.ballIdMappings.find(_.ballName == ball.getClass.getSimpleName) - val inBW = ballConfig.map(_.inBW).getOrElse(0) - val outBW = ballConfig.map(_.outBW).getOrElse(0) - + val inBW = ballConfig.map(_.inBW).getOrElse(0) + val outBW = ballConfig.map(_.outBW).getOrElse(0) + for (i <- 0 until inBW) { memoryrouter.io.bankRead_i(readChannelIdx) <> ball.blink.bankRead(i) readChannelIdx = readChannelIdx + 1 } - + for (i <- 0 until outBW) { memoryrouter.io.bankWrite_i(writeChannelIdx) <> ball.blink.bankWrite(i) writeChannelIdx = writeChannelIdx + 1 diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala index ffac5a84..a3559cd2 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala @@ -15,10 +15,14 @@ class ChannelMappingTable(val b: GlobalConfig, val entryNum: Int) extends Module @public val io = IO(new Bundle { - val write = Flipped(Vec(WritePorts, Decoupled(new Bundle { - val idx = UInt(log2Up(EntryNum).W) - val outCh = UInt(log2Up(MappedChannels).W) - }))) + + val write = Flipped(Vec( + WritePorts, + Decoupled(new Bundle { + val idx = UInt(log2Up(EntryNum).W) + val outCh = UInt(log2Up(MappedChannels).W) + }) + )) // 条目级清理：每个写口对应一条可能的派发通道（通常用 outCh 作为端口号） val invalidate = Input(Vec(WritePorts, Valid(UInt(log2Up(EntryNum).W)))) diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala index 5a987717..a5941865 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala @@ -45,14 +45,14 @@ class ReadReqGen(val b: GlobalConfig) extends Module { val matchConds = matchingChannels.map { ch => io.bank_read_i(ch).valid && - io.bank_read_i(ch).ball_id === ballId.U && - io.bank_read_i(ch).bank_id === bankId.U + io.bank_read_i(ch).ball_id === ballId.U && + io.bank_read_i(ch).bank_id === bankId.U } val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) val channelCountRaw = PopCount(matchConds) - val maxCh = b.top.ballMemChannelNum.U + val maxCh = b.top.ballMemChannelNum.U val channelCount = Mux(channelCountRaw > maxCh, maxCh, channelCountRaw) val robId = io.bank_read_i(ballOffset).rob_id diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala index 933601ac..0b483bb7 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala @@ -45,14 +45,14 @@ class WriteReqGen(val b: GlobalConfig) extends Module { val matchConds = matchingChannels.map { ch => io.bank_write_i(ch).valid && - io.bank_write_i(ch).ball_id === ballId.U && - io.bank_write_i(ch).bank_id === bankId.U + io.bank_write_i(ch).ball_id === ballId.U && + io.bank_write_i(ch).bank_id === bankId.U } val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) val channelCountRaw = PopCount(matchConds) - val maxCh = b.top.ballMemChannelNum.U + val maxCh = b.top.ballMemChannelNum.U val channelCount = Mux(channelCountRaw > maxCh, maxCh, channelCountRaw) val robId = io.bank_write_i(ballOffset).rob_id @@ -86,4 +86,3 @@ class WriteReqGen(val b: GlobalConfig) extends Module { io.write_req_o.bits.rob_id := arb.io.out.bits.rob_id arb.io.out.ready := io.write_req_o.ready } - diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala index a1f137f4..56f9700d 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala @@ -26,8 +26,8 @@ class MemRouter(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val bankRead_i = Vec(totalReadChannels, new BankRead(b)) - val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) + val bankRead_i = Vec(totalReadChannels, new BankRead(b)) + val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) @@ -78,13 +78,25 @@ class MemRouter(val b: GlobalConfig) extends Module { val chooseWrite = hasReadReq && hasWriteReq && !chooseRead || (!hasReadReq && hasWriteReq) io.peakChannelReq.valid := hasReadReq || hasWriteReq - io.peakChannelReq.bits.needed_channel_num := Mux(chooseRead, readReqGen.io.read_req_o.bits.channel_num, writeReqGen.io.write_req_o.bits.channel_num) - io.peakChannelReq.bits.bank_id := Mux(chooseRead, readReqGen.io.read_req_o.bits.bank_id, writeReqGen.io.write_req_o.bits.bank_id) - io.peakChannelReq.bits.rob_id := Mux(chooseRead, readReqGen.io.read_req_o.bits.rob_id, writeReqGen.io.write_req_o.bits.rob_id) + io.peakChannelReq.bits.needed_channel_num := Mux( + chooseRead, + readReqGen.io.read_req_o.bits.channel_num, + writeReqGen.io.write_req_o.bits.channel_num + ) + io.peakChannelReq.bits.bank_id := Mux( + chooseRead, + readReqGen.io.read_req_o.bits.bank_id, + writeReqGen.io.write_req_o.bits.bank_id + ) + io.peakChannelReq.bits.rob_id := Mux( + chooseRead, + readReqGen.io.read_req_o.bits.rob_id, + writeReqGen.io.write_req_o.bits.rob_id + ) // allocator 这里当“组合查询”用 io.freeChannelResp.ready := true.B - val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free && io.peakChannelReq.valid + val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free && io.peakChannelReq.valid val dispatchChannels = io.freeChannelResp.bits.channel_ids readReqGen.io.read_req_o.ready := isChannelFree && chooseRead @@ -93,8 +105,8 @@ class MemRouter(val b: GlobalConfig) extends Module { val didDispatchRead = readReqGen.io.read_req_o.fire val didDispatchWrite = writeReqGen.io.write_req_o.fire - when(didDispatchRead) { rrLastWasRead := true.B } - when(didDispatchWrite) { rrLastWasRead := false.B } + when(didDispatchRead)(rrLastWasRead := true.B) + when(didDispatchWrite)(rrLastWasRead := false.B) // --------------------------------------------------------------------------- // defaults: mapping write/invalidate off @@ -123,10 +135,10 @@ class MemRouter(val b: GlobalConfig) extends Module { io.bankRead_i(i).io.req.valid }) - val matchCount = PopCount(matchVec) - val channelNum = readReqGen.io.read_req_o.bits.channel_num - val portLimit = bbusProducerChannels.U - val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) + val matchCount = PopCount(matchVec) + val channelNum = readReqGen.io.read_req_o.bits.channel_num + val portLimit = bbusProducerChannels.U + val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) for (p <- 0 until bbusProducerChannels) { @@ -159,10 +171,10 @@ class MemRouter(val b: GlobalConfig) extends Module { io.bankWrite_i(i).io.req.valid }) - val matchCount = PopCount(matchVec) - val channelNum = writeReqGen.io.write_req_o.bits.channel_num - val portLimit = bbusProducerChannels.U - val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) + val matchCount = PopCount(matchVec) + val channelNum = writeReqGen.io.write_req_o.bits.channel_num + val portLimit = bbusProducerChannels.U + val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) for (p <- 0 until bbusProducerChannels) { @@ -222,7 +234,7 @@ class MemRouter(val b: GlobalConfig) extends Module { // Step5: route req/resp by outCh, invalidate on resp.fire // --------------------------------------------------------------------------- for (o <- 0 until bbusProducerChannels) { - val readIdxOH = VecInit((0 until totalReadChannels).map { i => + val readIdxOH = VecInit((0 until totalReadChannels).map { i => readMap.io.routeValid(i) && (readMap.io.routeMap(i) === o.U) }) val writeIdxOH = VecInit((0 until totalWriteChannels).map { i => @@ -274,4 +286,4 @@ class MemRouter(val b: GlobalConfig) extends Module { } } } -} \ No newline at end of file +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 0db2ce9e..0cd0f726 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -39,11 +39,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } for (i <- 0 until inBW) { - io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).rob_id := rob_id_reg io.bankRead(i).ball_id := 0.U } for (i <- 0 until outBW) { - io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).ball_id := 0.U } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index af505b2f..e15c684d 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -42,11 +42,11 @@ class VecUnit(val b: GlobalConfig) extends Module { // Set rob_id and ball_id for all bankRead and bankWrite channels from register for (i <- 0 until inBW) { - io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).rob_id := rob_id_reg io.bankRead(i).ball_id := 0.U } for (i <- 0 until outBW) { - io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).ball_id := 0.U } diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 85eb5e07..1f9819be 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -76,21 +76,10 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl_writer <> frontend.io.tl_writer // Ball Domain interface connects directly to midend (Ball devices' read/write requests) - midend.io.frontend.bankRead <> io.ballDomain.bankRead - midend.io.frontend.bankWrite <> io.ballDomain.bankWrite - - // ------------------------------------------------- - // Internal Connection (frontend - midend - backend) - // ------------------------------------------------- - for (i <- 0 until b.memDomain.bankNum) { - frontend.io.interdma.bankRead(i).io.req.ready := false.B - frontend.io.interdma.bankRead(i).io.resp.valid := false.B - frontend.io.interdma.bankRead(i).io.resp.bits := 0.U.asTypeOf(frontend.io.interdma.bankRead(i).io.resp.bits) - - frontend.io.interdma.bankWrite(i).io.req.ready := false.B - frontend.io.interdma.bankWrite(i).io.resp.valid := false.B - frontend.io.interdma.bankWrite(i).io.resp.bits := 0.U.asTypeOf(frontend.io.interdma.bankWrite(i).io.resp.bits) - } + midend.io.balldomain.bankRead <> io.ballDomain.bankRead + midend.io.balldomain.bankWrite <> io.ballDomain.bankWrite + midend.io.frontend.bankRead <> frontend.io.interdma.bankRead + midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite midend.io.mem_req <> backend.io.mem_req } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 2c8e3d4c..0cb6e7cc 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -19,12 +19,11 @@ import framework.memdomain.backend.accpipe.AccPipe * 5) Add cross read/write conflict assertions based on actual bank requests (valid-level, and fire-level optional) */ class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output } - @instantiable class MemBackend(val b: GlobalConfig) extends Module { @@ -40,8 +39,8 @@ class MemBackend(val b: GlobalConfig) extends Module { // Midend -> AccPipe // ----------------------------------------------------------------------------- for (i <- 0 until b.memDomain.bankChannel) { - accPipes(i).io.write <> io.mem_req(i).write - accPipes(i).io.read <> io.mem_req(i).read + accPipes(i).io.write <> io.mem_req(i).write + accPipes(i).io.read <> io.mem_req(i).read accPipes(i).io.bank_id := io.mem_req(i).bank_id } @@ -73,13 +72,13 @@ class MemBackend(val b: GlobalConfig) extends Module { wr_resp_ready(i) := accPipes(i).io.sramWrite.resp.ready // drive accPipe inputs from routing wires - accPipes(i).io.sramRead.req.ready := rd_req_ready(i) - accPipes(i).io.sramRead.resp.valid := rd_resp_valid(i) - accPipes(i).io.sramRead.resp.bits.data := rd_resp_data(i) + accPipes(i).io.sramRead.req.ready := rd_req_ready(i) + accPipes(i).io.sramRead.resp.valid := rd_resp_valid(i) + accPipes(i).io.sramRead.resp.bits.data := rd_resp_data(i) - accPipes(i).io.sramWrite.req.ready := wr_req_ready(i) - accPipes(i).io.sramWrite.resp.valid := wr_resp_valid(i) - accPipes(i).io.sramWrite.resp.bits.ok := wr_resp_ok(i) + accPipes(i).io.sramWrite.req.ready := wr_req_ready(i) + accPipes(i).io.sramWrite.resp.valid := wr_resp_valid(i) + accPipes(i).io.sramWrite.resp.bits.ok := wr_resp_ok(i) } // ----------------------------------------------------------------------------- @@ -120,67 +119,68 @@ class MemBackend(val b: GlobalConfig) extends Module { // - select at most one read requester (Mux1H) // - connect bank <-> selected accPipe using the per-pipe wires // ----------------------------------------------------------------------------- - banks.zipWithIndex.foreach { case (bank, bankIdx) => - val bankId = bankIdx.U(log2Up(b.memDomain.bankNum).W) - - // ------------------------- - // WRITE routing - // ------------------------- - val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) - for (i <- 0 until b.memDomain.bankChannel) { - wMatch(i) := accPipes(i).io.sramWrite.req.valid && (accPipes(i).io.target_bank_id === bankId) - } - val wHas = wMatch.asUInt.orR - // stronger safety: at most 1 - assert(PopCount(wMatch) <= 1.U, s"[MemBackend] More than one WRITE match to bank $bankIdx") - - when(wHas) { - val selIdx = OHToUInt(wMatch) - // bank gets req from selected pipe using Mux1H - bank.io.sramWrite.req.valid := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.valid)) - bank.io.sramWrite.req.bits := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.bits)) - // selected pipe sees ready from bank - wr_req_ready(selIdx) := bank.io.sramWrite.req.ready - - // response path: selected pipe sees bank resp - wr_resp_valid(selIdx) := bank.io.sramWrite.resp.valid - wr_resp_ok(selIdx) := bank.io.sramWrite.resp.bits.ok - // bank sees ready from selected pipe - bank.io.sramWrite.resp.ready := wr_resp_ready(selIdx) - }.otherwise { - bank.io.sramWrite.req.valid := false.B - bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) - bank.io.sramWrite.resp.ready := false.B - } + banks.zipWithIndex.foreach { + case (bank, bankIdx) => + val bankId = bankIdx.U(log2Up(b.memDomain.bankNum).W) + + // ------------------------- + // WRITE routing + // ------------------------- + val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) + for (i <- 0 until b.memDomain.bankChannel) { + wMatch(i) := accPipes(i).io.sramWrite.req.valid && (accPipes(i).io.target_bank_id === bankId) + } + val wHas = wMatch.asUInt.orR + // stronger safety: at most 1 + assert(PopCount(wMatch) <= 1.U, s"[MemBackend] More than one WRITE match to bank $bankIdx") + + when(wHas) { + val selIdx = OHToUInt(wMatch) + // bank gets req from selected pipe using Mux1H + bank.io.sramWrite.req.valid := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.valid)) + bank.io.sramWrite.req.bits := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.bits)) + // selected pipe sees ready from bank + wr_req_ready(selIdx) := bank.io.sramWrite.req.ready + + // response path: selected pipe sees bank resp + wr_resp_valid(selIdx) := bank.io.sramWrite.resp.valid + wr_resp_ok(selIdx) := bank.io.sramWrite.resp.bits.ok + // bank sees ready from selected pipe + bank.io.sramWrite.resp.ready := wr_resp_ready(selIdx) + }.otherwise { + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) + bank.io.sramWrite.resp.ready := false.B + } - // ------------------------- - // READ routing - // ------------------------- - val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) - for (i <- 0 until b.memDomain.bankChannel) { - rMatch(i) := accPipes(i).io.sramRead.req.valid && (accPipes(i).io.target_bank_id === bankId) - } - val rHas = rMatch.asUInt.orR - assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") - - when(rHas) { - val selIdx = OHToUInt(rMatch) - // bank gets req from selected pipe using Mux1H - bank.io.sramRead.req.valid := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.valid)) - bank.io.sramRead.req.bits := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.bits)) - // selected pipe sees ready from bank - rd_req_ready(selIdx) := bank.io.sramRead.req.ready - - // response path: selected pipe sees bank resp - rd_resp_valid(selIdx) := bank.io.sramRead.resp.valid - rd_resp_data(selIdx) := bank.io.sramRead.resp.bits.data - // bank sees ready from selected pipe - bank.io.sramRead.resp.ready := rd_resp_ready(selIdx) - }.otherwise { - bank.io.sramRead.req.valid := false.B - bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) - bank.io.sramRead.resp.ready := false.B - } + // ------------------------- + // READ routing + // ------------------------- + val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) + for (i <- 0 until b.memDomain.bankChannel) { + rMatch(i) := accPipes(i).io.sramRead.req.valid && (accPipes(i).io.target_bank_id === bankId) + } + val rHas = rMatch.asUInt.orR + assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") + + when(rHas) { + val selIdx = OHToUInt(rMatch) + // bank gets req from selected pipe using Mux1H + bank.io.sramRead.req.valid := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.valid)) + bank.io.sramRead.req.bits := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.bits)) + // selected pipe sees ready from bank + rd_req_ready(selIdx) := bank.io.sramRead.req.ready + + // response path: selected pipe sees bank resp + rd_resp_valid(selIdx) := bank.io.sramRead.resp.valid + rd_resp_data(selIdx) := bank.io.sramRead.resp.bits.data + // bank sees ready from selected pipe + bank.io.sramRead.resp.ready := rd_resp_ready(selIdx) + }.otherwise { + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) + bank.io.sramRead.resp.ready := false.B + } } // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index ee494665..cca39372 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -26,19 +26,19 @@ class AccPipe(val b: GlobalConfig) extends Module { val io = IO(new Bundle { // Interface to SramBank // Your SramReadIO/SramWriteIO are SLAVE-shaped (req is Flipped), so master must Flipped(...) - val sramRead = Flipped(new SramReadIO(b)) // AccPipe -> bank: req out, resp in - val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in + val sramRead = Flipped(new SramReadIO(b)) // AccPipe -> bank: req out, resp in + val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in // Interface from midend (AccPipe is slave) - val read = new SramReadIO(b) // midend -> AccPipe: req in, resp out - val write = new SramWriteIO(b) // midend -> AccPipe: req in, resp out + val read = new SramReadIO(b) // midend -> AccPipe: req in, resp out + val write = new SramWriteIO(b) // midend -> AccPipe: req in, resp out // Control and status signals - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) // in AccPipe IO bundle, add: - val target_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val target_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val busy = Output(Bool()) + val busy = Output(Bool()) }) // --------------------------------------------------------------------------- @@ -47,8 +47,6 @@ class AccPipe(val b: GlobalConfig) extends Module { val curBankId = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) // target bank id for routing (combinational) - - val opIsRead = RegInit(false.B) // true: read transaction; false: write transaction val opIsAccum = RegInit(false.B) // true only for write + wmode=1 @@ -64,8 +62,8 @@ class AccPipe(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = Enum(5) - val state = RegInit(s_idle) - + val state = RegInit(s_idle) + io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) io.busy := (state =/= s_idle) @@ -74,25 +72,25 @@ class AccPipe(val b: GlobalConfig) extends Module { // Defaults (avoid multi-drive) // --------------------------------------------------------------------------- // Midend side defaults - io.read.req.ready := false.B - io.read.resp.valid := false.B - io.read.resp.bits.data := 0.U + io.read.req.ready := false.B + io.read.resp.valid := false.B + io.read.resp.bits.data := 0.U - io.write.req.ready := false.B - io.write.resp.valid := false.B - io.write.resp.bits.ok := false.B + io.write.req.ready := false.B + io.write.resp.valid := false.B + io.write.resp.bits.ok := false.B // Bank side defaults - io.sramRead.req.valid := false.B - io.sramRead.req.bits.addr := 0.U - io.sramRead.resp.ready := false.B + io.sramRead.req.valid := false.B + io.sramRead.req.bits.addr := 0.U + io.sramRead.resp.ready := false.B - io.sramWrite.req.valid := false.B - io.sramWrite.req.bits.addr := 0.U - io.sramWrite.req.bits.data := 0.U - io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) - io.sramWrite.req.bits.wmode := false.B // IMPORTANT: write-back is a normal write - io.sramWrite.resp.ready := false.B + io.sramWrite.req.valid := false.B + io.sramWrite.req.bits.addr := 0.U + io.sramWrite.req.bits.data := 0.U + io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + io.sramWrite.req.bits.wmode := false.B // IMPORTANT: write-back is a normal write + io.sramWrite.resp.ready := false.B // --------------------------------------------------------------------------- // Helpers: masked accumulate (segment-wise) @@ -141,7 +139,7 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramRead.req.ready, Mux(writeDirect, io.sramWrite.req.ready, false.B) ) - io.read.req.ready := readValid && io.sramRead.req.ready + io.read.req.ready := readValid && io.sramRead.req.ready // State transitions + latching on fire when(writeAccum && io.sramRead.req.fire) { diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index aea2199d..de38e5ec 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -6,7 +6,7 @@ "tlb_size": 4, "dma_n_xacts": 8, "dma_maxbytes": 64, - "bankChannel": 8, + "bankChannel": 7, "max_in_flight_mem_reqs": 16, "dma_buswidth": 128, "memAddrLen": 32, diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index bac6e03f..62319154 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -31,8 +31,8 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Bank read/write interface - used by load/store val interdma = new Bundle { - val bankRead = Vec(b.memDomain.bankNum, Flipped(new BankRead(b))) - val bankWrite = Vec(b.memDomain.bankNum, Flipped(new BankWrite(b))) + val bankRead = Flipped(new BankRead(b)) + val bankWrite = Flipped(new BankWrite(b)) } // TLB interfaces for internal DMA modules (Reader/Writer) diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index e709eeb6..9f09eb55 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -49,6 +49,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val bankAddrLen = log2Up(b.memDomain.bankEntries) val memAddrLen = b.memDomain.memAddrLen + val bankIdLen = log2Up(b.memDomain.bankNum) // Only process Mem instructions io.raw_cmd_i.ready := io.mem_decode_cmd_o.ready @@ -69,27 +70,27 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { Y, N, rs1(memAddrLen - 1, 0), - rs2(bankAddrLen - 1, 0), - rs2(bankAddrLen + 9, bankAddrLen), - rs2(63, bankAddrLen + 10), + rs2(bankIdLen - 1, 0), + rs2(9 + bankIdLen, bankIdLen), + rs2(63, 10 + bankIdLen), Y ), // mset MVIN_BITPAT -> List( Y, N, rs1(memAddrLen - 1, 0), - rs2(bankAddrLen - 1, 0), - rs2(bankAddrLen + 9, bankAddrLen), - rs2(63, bankAddrLen + 10), + rs2(bankIdLen - 1, 0), + rs2(9 + bankIdLen, bankIdLen), + rs2(63, 10 + bankIdLen), Y ), // mvin MVOUT_BITPAT -> List( N, Y, rs1(memAddrLen - 1, 0), - rs2(bankAddrLen - 1, 0), - rs2(bankAddrLen + 9, bankAddrLen), - rs2(63, bankAddrLen + 10), + rs2(bankIdLen - 1, 0), + rs2(9 + bankIdLen, bankIdLen), + rs2(63, 10 + bankIdLen), Y ) // mvout ) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index d6def88c..a865cfec 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -25,10 +25,7 @@ class MemLoader(val b: GlobalConfig) extends Module { val dmaResp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) // Connected to Bank write interface - val bankWrite = Vec( - b.memDomain.bankNum, - Flipped(new BankWrite(b)) - ) + val bankWrite = Flipped(new BankWrite(b)) }) @@ -92,17 +89,15 @@ class MemLoader(val b: GlobalConfig) extends Module { val target_bank = wr_bank_reg val target_row = io.dmaResp.bits.addrcounter - for (i <- 0 until b.memDomain.bankNum) { - io.bankWrite(i).io.req.valid := io.dmaResp.fire && (target_bank === i.U) - io.bankWrite(i).io.req.bits.addr := target_row - io.bankWrite(i).io.req.bits.data := io.dmaResp.bits.data - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - io.bankWrite(i).io.req.bits.wmode := false.B - io.bankWrite(i).io.resp.ready := false.B - io.bankWrite(i).rob_id := rob_id_reg - io.bankWrite(i).bank_id := target_bank - io.bankWrite(i).ball_id := 0.U - } + io.bankWrite.io.req.valid := io.dmaResp.fire && (target_bank === target_bank) + io.bankWrite.io.req.bits.addr := target_row + io.bankWrite.io.req.bits.data := io.dmaResp.bits.data + io.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + io.bankWrite.io.req.bits.wmode := false.B + io.bankWrite.io.resp.ready := false.B + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := target_bank + io.bankWrite.ball_id := 0.U // Send completion signal - only send when last response is received io.cmdResp.valid := io.dmaResp.fire && io.dmaResp.bits.last diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 59f16b5b..ee0d1090 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -29,10 +29,7 @@ class MemStorer(val b: GlobalConfig) extends Module { val dmaResp = Flipped(Decoupled(new BBWriteResponse)) // Connected to Bank read interface - val bankRead = Vec( - b.memDomain.bankNum, - Flipped(new BankRead(b)) - ) + val bankRead = Flipped(new BankRead(b)) }) @@ -76,17 +73,15 @@ class MemStorer(val b: GlobalConfig) extends Module { val target_bank = rd_bank_reg val target_row = sram_count - for (i <- 0 until b.memDomain.bankNum) { - io.bankRead(i).io.req.valid := (state === s_sram_req) && (target_bank === i.U) - io.bankRead(i).io.req.bits.addr := target_row - io.bankRead(i).rob_id := rob_id_reg - io.bankRead(i).bank_id := target_bank - io.bankRead(i).ball_id := 0.U - } + io.bankRead.io.req.valid := (state === s_sram_req) + io.bankRead.io.req.bits.addr := target_row + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U // Bank response processing - val bank_resp_valid = io.bankRead.map(_.io.resp.valid).reduce(_ || _) - val bank_resp_data = Mux1H(io.bankRead.map(_.io.resp.valid), io.bankRead.map(_.io.resp.bits.data)) + val bank_resp_valid = io.bankRead.io.resp.valid + val bank_resp_data = io.bankRead.io.resp.bits.data // Calculate memory address corresponding to current row val current_mem_addr = @@ -209,9 +204,9 @@ class MemStorer(val b: GlobalConfig) extends Module { io.dmaReq.bits.status := dma_req_status_reg // Connect Bank response ready signal - based on DMA ready state - io.bankRead.foreach(_.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait)) + io.bankRead.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait) // State transition and counter update - when(io.bankRead.map(_.io.req.fire).reduce(_ || _)) { + when(io.bankRead.io.req.fire) { state := s_dma_wait } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index 46412dc0..8ca18567 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -72,7 +72,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val xactBusy_fire = WireInit(false.B) val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) - val xactBusy_remove = ~Mux(io.tlb.resp.valid && !io.tlb.resp.bits.miss, (1.U << xactId).asUInt, 0.U) + val xactBusy_remove = ~Mux(io.tl.d.fire, (1.U << io.tl.d.bits.source).asUInt, 0.U) xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt // TileLink request construction - return to single beat requests to avoid address alignment issues @@ -104,22 +104,23 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.valid := tlb_q.io.deq.fire io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.passthrough := false.B + io.tlb.req.bits.passthrough := true.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XRD io.tlb.req.bits.prv := 3.U // Machine mode io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status - val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - translate_q.io.enq <> tlb_q.io.deq - translate_q.io.deq.ready := io.tlb.resp.fire || io.tlb.resp.bits.miss + tlb_q.io.deq.ready := true.B; + + /* val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq + * translate_q.io.deq.ready := io.tlb.resp.fire && !io.tlb.resp.bits.miss */ // TileLink A channel (request) connection - io.tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss - io.tl.a.bits := translate_q.io.deq.bits.tl_a - io.tl.a.bits.address := io.tlb.resp.bits.paddr - translate_q.io.deq.ready := (io.tlb.resp.fire && !io.tlb.resp.bits.miss && io.tl.a.ready) || io.tlb.resp.bits.miss + //for now, we just use the vaddr as the physical address to simplify the implementation + io.tl.a.valid := tlb_q.io.deq.fire + io.tl.a.bits := tlb_q.io.deq.bits.tl_a + io.tl.a.bits.address := tlb_q.io.deq.bits.vaddr // Iteration counter for tracking number of requests val iter_counter = RegInit(0.U(10.W)) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 003094a4..a6590102 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -22,6 +22,11 @@ class MemMidend(val b: GlobalConfig) extends Module { // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { + val bankRead = new BankRead(b) + val bankWrite = new BankWrite(b) + } + + val balldomain = new Bundle { val bankRead = Vec(b.top.memBallChannelNum, new BankRead(b)) val bankWrite = Vec(b.top.ballMemChannelNum, new BankWrite(b)) } @@ -36,12 +41,14 @@ class MemMidend(val b: GlobalConfig) extends Module { // Map bbusChannel input channels to bankChannel output channels // Each input channel is mapped to a backend channel based on modulo - for (ch <- 0 until b.memDomain.bankChannel) { - val inputIdx = ch % b.top.memBallChannelNum + for (ch <- 0 until b.top.memBallChannelNum) { // Map input channels to backend channels - io.mem_req(ch).write <> io.frontend.bankWrite(inputIdx).io - io.mem_req(ch).read <> io.frontend.bankRead(inputIdx).io - io.mem_req(ch).bank_id := io.frontend.bankWrite(inputIdx).bank_id + io.mem_req(ch).write <> io.balldomain.bankWrite(ch).io + io.mem_req(ch).read <> io.balldomain.bankRead(ch).io + io.mem_req(ch).bank_id := io.balldomain.bankWrite(ch).bank_id } + io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io + io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io + io.mem_req(b.top.memBallChannelNum).bank_id := io.frontend.bankWrite.bank_id } diff --git a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c index 533bb5a2..5bcba189 100644 --- a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c @@ -8,7 +8,7 @@ #define bb_mvin(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ FIELD(mem_addr, 0, 31), \ - (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 33)), \ + (FIELD(bank_id, 0, 4) | FIELD(depth, 5, 14) | FIELD(stride, 15, 33)), \ BB_MVIN_FUNC7) #endif // _BB_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c index 89db0c54..0be05635 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c @@ -8,7 +8,7 @@ #define bb_mvout(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ FIELD(mem_addr, 0, 31), \ - (FIELD(bank_id, 0, 7) | FIELD(depth, 8, 23) | FIELD(stride, 24, 33)), \ + (FIELD(bank_id, 0, 4) | FIELD(depth, 5, 14) | FIELD(stride, 14, 33)), \ BB_MVOUT_FUNC7) #endif // _BB_MVOUT_H_ diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 292fea4b..57c9c3ca 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); @@ -13,18 +13,18 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); + // transpose_u8_matrix(a, a_transposed, size, size); + // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + // bb_mem_alloc(acc_bank_id, 1, 4); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); @@ -34,8 +34,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); - cpu_matmul(a, b, expected_matrix, size, size, size); + // clear_u32_matrix(output_matrix, DIM, DIM); + // cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); @@ -47,8 +47,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } int test_ones() { - init_ones_matrix(input_matrix_a, DIM, DIM); - init_ones_matrix(input_matrix_b, DIM, DIM); + // init_ones_matrix(input_matrix_a, DIM, DIM); + // init_ones_matrix(input_matrix_b, DIM, DIM); return run_test("All-ones matrices", input_matrix_a, input_matrix_b, DIM); } @@ -57,6 +57,7 @@ int main() { multicore(MULTICORE); #endif int passed = test_ones(); + // printf("RS2:%x", (FIELD(0, 0, 4) | FIELD(16, 5, 14) | FIELD(1, 14, 33))); if (passed) { printf("vecunit_matmul_ones test PASSED\n"); return 0; From 18bd7deda029ef2c0dc36b3e51c513f529e72d07 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Thu, 22 Jan 2026 19:19:24 +0800 Subject: [PATCH 059/238] test --- test | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 test diff --git a/test b/test new file mode 100644 index 00000000..e69de29b From ec19a127d47edf7f4942630cd1d5cbecf2e71d82 Mon Sep 17 00:00:00 2001 From: "whmio0115@gmail.com" Date: Fri, 23 Jan 2026 22:29:58 +0800 Subject: [PATCH 060/238] [arch]Fix memdomain bugs, successfully finish running vecunit matmul ones test(only no assertations) --- .../prototype/vector/VecLoadUnit.scala | 2 +- .../memdomain/backend/MemBackend.scala | 37 +++++++++++-------- .../outside_channel/dma/StreamWriter.scala | 9 +++-- .../memdomain/midend/MemMidend.scala | 6 ++- 4 files changed, 32 insertions(+), 22 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index a5ab6396..14e2d43c 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -96,7 +96,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- - when(io.bankReadResp(0).valid && io.bankReadResp(1).valid && + when(io.bankReadResp(0).valid && (!ld_ex_valid_reg || io.ld_ex_o.ready) && (state === busy)) { ld_ex_valid_reg := true.B ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 0cb6e7cc..66a4e868 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -19,9 +19,10 @@ import framework.memdomain.backend.accpipe.AccPipe * 5) Add cross read/write conflict assertions based on actual bank requests (valid-level, and fire-level optional) */ class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val rbank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val wbank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output } @instantiable @@ -41,7 +42,7 @@ class MemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.write <> io.mem_req(i).write accPipes(i).io.read <> io.mem_req(i).read - accPipes(i).io.bank_id := io.mem_req(i).bank_id + accPipes(i).io.bank_id := io.mem_req(i).wbank_id } // ----------------------------------------------------------------------------- @@ -128,7 +129,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // ------------------------- val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) for (i <- 0 until b.memDomain.bankChannel) { - wMatch(i) := accPipes(i).io.sramWrite.req.valid && (accPipes(i).io.target_bank_id === bankId) + wMatch(i) := io.mem_req(i).wbank_id === bankId && io.mem_req(i).write.req.valid } val wHas = wMatch.asUInt.orR // stronger safety: at most 1 @@ -158,27 +159,33 @@ class MemBackend(val b: GlobalConfig) extends Module { // ------------------------- val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) for (i <- 0 until b.memDomain.bankChannel) { - rMatch(i) := accPipes(i).io.sramRead.req.valid && (accPipes(i).io.target_bank_id === bankId) + rMatch(i) := io.mem_req(i).rbank_id === bankId && io.mem_req(i).read.req.valid } val rHas = rMatch.asUInt.orR assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") + val selIdx = OHToUInt(rMatch) + val connectIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) + connectIdx := selIdx + when(rHas) { - val selIdx = OHToUInt(rMatch) + // bank gets req from selected pipe using Mux1H - bank.io.sramRead.req.valid := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.valid)) - bank.io.sramRead.req.bits := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.bits)) + bank.io.sramRead.req.valid := io.mem_req(selIdx).rbank_id === bankId + bank.io.sramRead.req.bits := io.mem_req(selIdx).read.req.bits // selected pipe sees ready from bank rd_req_ready(selIdx) := bank.io.sramRead.req.ready - + }.otherwise { + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) + } + when(bank.io.sramRead.resp.valid) { // response path: selected pipe sees bank resp - rd_resp_valid(selIdx) := bank.io.sramRead.resp.valid - rd_resp_data(selIdx) := bank.io.sramRead.resp.bits.data + io.mem_req(connectIdx).read.resp.valid := bank.io.sramRead.resp.valid + io.mem_req(connectIdx).read.resp.bits.data := bank.io.sramRead.resp.bits.data // bank sees ready from selected pipe - bank.io.sramRead.resp.ready := rd_resp_ready(selIdx) + bank.io.sramRead.resp.ready := io.mem_req(connectIdx).read.resp.ready }.otherwise { - bank.io.sramRead.req.valid := false.B - bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) bank.io.sramRead.resp.ready := false.B } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index b1bd10d2..f67bd618 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -54,7 +54,7 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val xactBusy_fire = WireInit(false.B) val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) - val xactBusy_remove = ~Mux(io.tlb.resp.valid && !io.tlb.resp.bits.miss, (1.U << xactId).asUInt, 0.U) + val xactBusy_remove = ~Mux(io.tl.d.fire, (1.U << io.tl.d.bits.source).asUInt, 0.U) xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt // Simplified: data is already aligned, directly construct TileLink request @@ -109,10 +109,11 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { translate_q.io.enq <> tlb_q.io.deq translate_q.io.deq.ready := (io.tlb.resp.fire && !io.tlb.resp.bits.miss && io.tl.a.ready) || io.tlb.resp.bits.miss + tlb_q.io.deq.ready := true.B; // TileLink A channel (request) connection - io.tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.bits.miss - io.tl.a.bits := translate_q.io.deq.bits.tl_a - io.tl.a.bits.address := io.tlb.resp.bits.paddr + io.tl.a.valid := tlb_q.io.deq.fire + io.tl.a.bits := tlb_q.io.deq.bits.tl_a + io.tl.a.bits.address := tlb_q.io.deq.bits.vaddr // TileLink D channel (response) processing io.tl.d.ready := io.resp.ready diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index a6590102..eaca4afe 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -46,9 +46,11 @@ class MemMidend(val b: GlobalConfig) extends Module { // Map input channels to backend channels io.mem_req(ch).write <> io.balldomain.bankWrite(ch).io io.mem_req(ch).read <> io.balldomain.bankRead(ch).io - io.mem_req(ch).bank_id := io.balldomain.bankWrite(ch).bank_id + io.mem_req(ch).rbank_id := io.balldomain.bankWrite(ch).bank_id + io.mem_req(ch).wbank_id := io.balldomain.bankWrite(ch).bank_id } io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io - io.mem_req(b.top.memBallChannelNum).bank_id := io.frontend.bankWrite.bank_id + io.mem_req(b.top.memBallChannelNum).rbank_id := io.frontend.bankWrite.bank_id + io.mem_req(b.top.memBallChannelNum).wbank_id := io.frontend.bankRead.bank_id } From ccab3c11f945151b8ae76115fecb88cdf80271b1 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Sun, 25 Jan 2026 23:14:55 +0800 Subject: [PATCH 061/238] [arch]Partly fix TLB bugs --- .../scala/framework/core/configs/default.json | 2 +- .../memdomain/frontend/MemFrontend.scala | 18 ++++++++++++++---- .../outside_channel/dma/StreamReader.scala | 9 +++++---- .../outside_channel/dma/StreamWriter.scala | 1 + .../frontend/outside_channel/tlb/BBTLBIO.scala | 4 ++-- .../outside_channel/tlb/TLBCluster.scala | 4 ++-- .../src/CTest/toy/vecunit_matmul_ones.c | 2 +- 7 files changed, 26 insertions(+), 14 deletions(-) diff --git a/arch/src/main/scala/framework/core/configs/default.json b/arch/src/main/scala/framework/core/configs/default.json index d3ba0329..2b35592d 100644 --- a/arch/src/main/scala/framework/core/configs/default.json +++ b/arch/src/main/scala/framework/core/configs/default.json @@ -3,6 +3,6 @@ "xLen": 64, "vaddrBits": 39, "paddrBits": 56, - "pgIdxBits": 12, + "pgIdxBits": 4, "nPMPs": 8 } diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 62319154..0a8d54e1 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -109,11 +109,21 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // TLB connection - internal TLB cluster connected to DMA modules // Client 0: StreamWriter, Client 1: StreamReader // Insert pipeline registers to break combinational loops - tlbCluster.io.clients(1).req := RegNext(reader.io.tlb.req) - reader.io.tlb.resp := RegNext(tlbCluster.io.clients(1).resp) + tlbCluster.io.clients(1).req.valid := RegNext(reader.io.tlb.req.valid) + tlbCluster.io.clients(1).req.bits := RegNext(reader.io.tlb.req.bits) + reader.io.tlb.req.ready := RegNext(tlbCluster.io.clients(1).req.ready) - tlbCluster.io.clients(0).req := RegNext(writer.io.tlb.req) - writer.io.tlb.resp := RegNext(tlbCluster.io.clients(0).resp) + reader.io.tlb.resp.valid := RegNext(tlbCluster.io.clients(1).resp.valid) + reader.io.tlb.resp.bits := RegNext(tlbCluster.io.clients(1).resp.bits) + tlbCluster.io.clients(1).resp.ready := RegNext(reader.io.tlb.resp.ready) + + tlbCluster.io.clients(0).req.valid := RegNext(writer.io.tlb.req.valid) + tlbCluster.io.clients(0).req.bits := RegNext(writer.io.tlb.req.bits) + writer.io.tlb.req.ready := RegNext(tlbCluster.io.clients(0).req.ready) + + writer.io.tlb.resp.valid := RegNext(tlbCluster.io.clients(0).resp.valid) + writer.io.tlb.resp.bits := RegNext(tlbCluster.io.clients(0).resp.bits) + tlbCluster.io.clients(0).resp.ready := RegNext(writer.io.tlb.resp.ready) // Connect DMA flush signals to TLB exceptions reader.io.flush := io.tlbExp(0).flush() diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index 8ca18567..ac6c1814 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -101,17 +101,17 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a - io.tlb.req.valid := tlb_q.io.deq.fire + io.tlb.req.valid := io.tlb.req.ready io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.passthrough := true.B + io.tlb.req.bits.passthrough := false.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XRD io.tlb.req.bits.prv := 3.U // Machine mode io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status - tlb_q.io.deq.ready := true.B; + tlb_q.io.deq.ready := !io.tlb.resp.bits.miss; /* val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq * translate_q.io.deq.ready := io.tlb.resp.fire && !io.tlb.resp.bits.miss */ @@ -120,7 +120,8 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { //for now, we just use the vaddr as the physical address to simplify the implementation io.tl.a.valid := tlb_q.io.deq.fire io.tl.a.bits := tlb_q.io.deq.bits.tl_a - io.tl.a.bits.address := tlb_q.io.deq.bits.vaddr + io.tl.a.bits.address := io.tlb.resp.bits.paddr + io.tlb.resp.ready := true.B; // Iteration counter for tracking number of requests val iter_counter = RegInit(0.U(10.W)) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index f67bd618..1bcb69f4 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -114,6 +114,7 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl.a.valid := tlb_q.io.deq.fire io.tl.a.bits := tlb_q.io.deq.bits.tl_a io.tl.a.bits.address := tlb_q.io.deq.bits.vaddr + io.tlb.resp.ready := true.B; // TileLink D channel (response) processing io.tl.d.ready := io.resp.ready diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala index 785fa2e9..ef7c3b59 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/BBTLBIO.scala @@ -168,6 +168,6 @@ class BBTLBPTWIO(val b: GlobalConfig) extends Bundle { // TLB Client IO (used in TLBCluster) class BBTLBIO(val b: GlobalConfig) extends Bundle { val lgMaxSize = log2Ceil(b.core.coreDataBytes) - val req = Flipped(Valid(new BBTLBReq(lgMaxSize, b.core.vaddrBits, b.core.xLen))) - val resp = Valid(new BBTLBResp(lgMaxSize, b.core.paddrBits, b.core.vaddrBits)) + val req = Flipped(Decoupled(new BBTLBReq(lgMaxSize, b.core.vaddrBits, b.core.xLen))) + val resp = Decoupled(new BBTLBResp(lgMaxSize, b.core.paddrBits, b.core.vaddrBits)) } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala index b666a993..4bad5709 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala @@ -84,6 +84,7 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo tlbArb.io.in(i).valid := client.req.valid && !l0_tlb_hit tlbArb.io.in(i).bits := client.req.bits + client.req.ready := tlbArb.io.in(i).ready val tlbReq = tlbArb.io.in(i).bits val tlbReqFire = tlbArb.io.in(i).fire @@ -97,7 +98,7 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo when(io.exp(0).flush()) { last_translated_valid := false.B } - + client.resp.bits.miss := tlb_io.resp.miss when(tlbReqFire) { client.resp.valid := !tlb_io.resp.miss client.resp.bits := tlb_io.resp @@ -105,7 +106,6 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo client.resp.valid := RegNext(!l0_tlb_hit) client.resp.bits := DontCare client.resp.bits.paddr := RegNext(l0_tlb_paddr) - client.resp.bits.miss := !RegNext(l0_tlb_hit) } } } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 57c9c3ca..ca1c16d5 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -47,7 +47,7 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } int test_ones() { - // init_ones_matrix(input_matrix_a, DIM, DIM); + init_ones_matrix(input_matrix_a, DIM, DIM); // init_ones_matrix(input_matrix_b, DIM, DIM); return run_test("All-ones matrices", input_matrix_a, input_matrix_b, DIM); } From 3f0ddd2cd1b509070cc652a921e7b86a322f1cdf Mon Sep 17 00:00:00 2001 From: SJM946 Date: Mon, 26 Jan 2026 00:03:22 +0800 Subject: [PATCH 062/238] [arch]Revert changes to default.json --- arch/src/main/scala/framework/core/configs/default.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/src/main/scala/framework/core/configs/default.json b/arch/src/main/scala/framework/core/configs/default.json index 2b35592d..d3ba0329 100644 --- a/arch/src/main/scala/framework/core/configs/default.json +++ b/arch/src/main/scala/framework/core/configs/default.json @@ -3,6 +3,6 @@ "xLen": 64, "vaddrBits": 39, "paddrBits": 56, - "pgIdxBits": 4, + "pgIdxBits": 12, "nPMPs": 8 } From 6081c4bddc4d4eadd8aad658aaa6c8278976bd27 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Mon, 26 Jan 2026 18:14:29 +0800 Subject: [PATCH 063/238] [arch]Fix TLB bugs, using paddr for now --- .../frontend/outside_channel/dma/StreamReader.scala | 4 ++-- .../frontend/outside_channel/dma/StreamWriter.scala | 13 +++++-------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index ac6c1814..96d51b36 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -104,10 +104,10 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.valid := io.tlb.req.ready io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.passthrough := false.B + io.tlb.req.bits.passthrough := true.B //use paddr for now io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XRD - io.tlb.req.bits.prv := 3.U // Machine mode + io.tlb.req.bits.prv := 3.U // Machine mode io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index 1bcb69f4..801cda02 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -95,25 +95,22 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a - io.tlb.req.valid := tlb_q.io.deq.valid + io.tlb.req.valid := io.tlb.req.ready io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.passthrough := false.B + io.tlb.req.bits.passthrough := true.B //use paddr for now io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XWR - io.tlb.req.bits.prv := 3.U // Machine mode + io.tlb.req.bits.prv := 3.U // Machine mode io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status - - val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - translate_q.io.enq <> tlb_q.io.deq - translate_q.io.deq.ready := (io.tlb.resp.fire && !io.tlb.resp.bits.miss && io.tl.a.ready) || io.tlb.resp.bits.miss + tlb_q.io.deq.ready := !io.tlb.resp.bits.miss; tlb_q.io.deq.ready := true.B; // TileLink A channel (request) connection io.tl.a.valid := tlb_q.io.deq.fire io.tl.a.bits := tlb_q.io.deq.bits.tl_a - io.tl.a.bits.address := tlb_q.io.deq.bits.vaddr + io.tl.a.bits.address := io.tlb.resp.bits.paddr io.tlb.resp.ready := true.B; // TileLink D channel (response) processing From d3c1b309d65dce969adfd495cc6a4d6d6f18b211 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 30 Jan 2026 04:59:35 +0800 Subject: [PATCH 064/238] [arch] Add AxisBundle class for blink interface --- .../balldomain/blink/axis/axis.scala | 41 +++++++++++++++++++ .../src/CTest/bebop/mvin_mvout_mset_test.c | 5 +-- .../src/CTest/bebop/mvin_mvout_test.c | 3 +- .../src/OpTest/gemmini/CMakeLists.txt | 3 +- bebop | 2 +- test | 0 6 files changed, 48 insertions(+), 6 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/blink/axis/axis.scala delete mode 100644 test diff --git a/arch/src/main/scala/framework/balldomain/blink/axis/axis.scala b/arch/src/main/scala/framework/balldomain/blink/axis/axis.scala new file mode 100644 index 00000000..347bc4fc --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/blink/axis/axis.scala @@ -0,0 +1,41 @@ +package framework.balldomain.blink.axis + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig + +/** + * AXI4-Stream style bundle. + * Source drives tvalid, tdata, tlast, tstrb, tid, tdest; sink drives tready. + * Use Flipped(AxisBundle(...)) for sink side. Transfer occurs when tvalid && tready. + * + * Signals: + * tvalid Source: this beat valid; tdata (and other payload) may be sampled. + * tready Sink: can accept this cycle; transfer completes when both high. + * tdata Payload, width dataWidth. + * tlast Packet end; high on final beat of a stream packet. + * tstrb Byte strobe: 1 bit per TDATA byte; 1 = valid, 0 = null/placeholder. + * tid Transaction ID: source/transaction identity for mux, reorder, or req–resp match. + * tdest Destination ID: routing target when multiplexing. + * + * @param dataWidth TDATA width (bits). tstrb length = (dataWidth/8).max(1). + * @param idWidth TID width; 0 = unused. + * @param destWidth TDEST width; 0 = unused. + */ +class AxisBundle( + val b: GlobalConfig, + val dataWidth: Int, + val idWidth: Int = 0, + val destWidth: Int = 0, + val offsetWidth: Int = 0) + extends Bundle { + val tdata = UInt(dataWidth.W) + val tlast = Bool() + val tstrb = UInt((dataWidth / 8).max(1).W) + val tid = UInt(idWidth.W) + val tdest = UInt(destWidth.W) + + val wmode = Bool() // true=accumulator mode, false=direct write mode + val offset = UInt(offsetWidth.W) + val rob_id = UInt(log2Ceil(b.frontend.rob_entries).W) +} diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c index 2f6b41e8..a0526404 100644 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c @@ -16,13 +16,12 @@ int mvin_mvout_simple_test() { for (int i = 0; i < 4; i++) { init_u8_random_matrix(input_matrix, DIM, DIM2, 111); int vbank_id = 2; // virtual bank id - bb_mem_alloc(vbank_id, 1, 1); + bb_mem_alloc(vbank_id, 4, 1); bb_mvin((uintptr_t)input_matrix, vbank_id, DIM2, 1); clear_u8_matrix(output_matrix, DIM, DIM2); - bb_fence(); bb_mvout((uintptr_t)output_matrix, vbank_id, DIM2, 1); - bb_fence(); bb_mem_release(vbank_id); + bb_fence(); if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM2)) { printf("Test mvin/mvout simple %d FAILED\n", i); return 0; diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c index 09363ab9..02a389dd 100644 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c @@ -15,10 +15,11 @@ static elem_t output_matrix[DIM * DIM2] __attribute__((aligned(16))); int mvin_mvout_simple_test() { for (int i = 0; i < 4; i++) { init_u8_random_matrix(input_matrix, DIM, DIM2, 111); + bb_mem_alloc(0, 1, 1); bb_mvin((uintptr_t)input_matrix, 0, DIM2, 1); clear_u8_matrix(output_matrix, DIM, DIM2); - bb_fence(); bb_mvout((uintptr_t)output_matrix, 0, DIM2, 1); + bb_mem_release(0); bb_fence(); if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM2)) { printf("Test mvin/mvout simple %d FAILED\n", i); diff --git a/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt b/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt index bc16b256..172ccf27 100644 --- a/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt @@ -62,6 +62,7 @@ function(add_linux_target TARGET_NAME MLIR_FILE) ${BUDDY_TRANSLATE} --buddy-to-llvmir | ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 -mattr=+buddyext,+D -float-abi=hard + -relocation-model=static -o ${OBJ_FILE} DEPENDS ${MLIR_FILE} COMMENT "Compiling ${MLIR_FILE} to Linux object file" @@ -70,7 +71,7 @@ function(add_linux_target TARGET_NAME MLIR_FILE) # Link xx-linux.o to xx-linux add_custom_command( OUTPUT ${EXECUTABLE} - COMMAND ${LINUX_CC} -O2 -static ${OBJ_FILE} -o ${EXECUTABLE} + COMMAND ${LINUX_CC} -O2 -static -Wl,--no-relax ${OBJ_FILE} -o ${EXECUTABLE} DEPENDS ${OBJ_FILE} COMMENT "Linking Linux executable: ${EXECUTABLE}" ) diff --git a/bebop b/bebop index 20089f60..51d6ad90 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 20089f60d8dd7000bab8faa3fe9be26e62f5fc7d +Subproject commit 51d6ad90f8dae28ae5572f934c54231aa32faa5e diff --git a/test b/test deleted file mode 100644 index e69de29b..00000000 From 513bc5a4d1e66478f07bd77af4c9386496599e60 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Fri, 30 Jan 2026 17:53:30 +0800 Subject: [PATCH 065/238] [arch]Remove memRouter and add mapping table for MemMidend --- .../scala/examples/toy/ToyBuckyBall.scala | 21 ++--- .../examples/toy/balldomain/BallDomain.scala | 17 ++-- .../framework/balldomain/bbus/bbus.scala | 69 +++----------- .../prototype/vector/VecLoadUnit.scala | 2 +- .../scala/framework/memdomain/MemDomain.scala | 6 +- .../memdomain/backend/MemBackend.scala | 17 ++-- .../memdomain/midend/MemMidend.scala | 89 ++++++++++++++++--- 7 files changed, 113 insertions(+), 108 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 7a1f212a..b5cb03a7 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -55,17 +55,16 @@ class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) with HasCoreParameters { import outer.b._ val b: GlobalConfig = outer.b - + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum // Get TileLink edges from reader and writer nodes val (tl_reader, edge_reader) = outer.reader_node.out(0) val (tl_writer, edge_writer) = outer.writer_node.out(0) - val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) - val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) - val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) - val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) - val ballMemChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.ballMemChannelNum)) - val memBallChannelCluster: Instance[ChannelCluster] = Instantiate(new ChannelCluster(b, b.top.memBallChannelNum)) + val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) + val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) + val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) frontend.io.cmd.valid := io.cmd.valid frontend.io.cmd.bits.cmd := io.cmd.bits @@ -104,7 +103,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w // Break potential combinational loops on bankRead by registering the req channel. // IDs are queued alongside the req bits to keep them aligned through backpressure. - for (i <- 0 until b.top.memBallChannelNum) { + for (i <- 0 until totalBallRead) { val bankReadReqWithIds = Wire(Decoupled(new Bundle { val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) @@ -133,12 +132,6 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) w ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite - // Connect BallMemChannelCluster - ballMemChannelCluster.io <> ballDomain.ballMemChannel - - // Connect MemBallChannelCluster - memBallChannelCluster.io <> ballDomain.memBallChannel - // Connect TileLink DMA ports from MemDomain to LazyModule nodes tl_reader <> memDomain.io.tl_reader tl_writer <> memDomain.io.tl_writer diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index d07d4fbd..e700f7e4 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -11,11 +11,12 @@ import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite} import framework.balldomain.rs.BallReservationStation import framework.top.channels.{ChannelClusterIO, ChannelIO} -import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} @instantiable class BallDomain(val b: GlobalConfig) extends Module { - val memChannel = b.top.ballMemChannelNum + val memChannel = b.top.ballMemChannelNum + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum @public val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(b)))) @@ -24,16 +25,10 @@ class BallDomain(val b: GlobalConfig) extends Module { val global_complete_o = IO(Decoupled(new GlobalRsComplete(b))) @public - val bankRead = IO(Vec(memChannel, Flipped(new BankRead(b)))) + val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) - - @public - val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, memChannel))) - - @public - val memBallChannel = IO(Flipped(new ChannelClusterIO(b, b.top.memBallChannelNum))) + val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) @@ -69,8 +64,6 @@ class BallDomain(val b: GlobalConfig) extends Module { //--------------------------------------------------------------------------- bbus.bankRead <> bankRead bbus.bankWrite <> bankWrite - bbus.ballMemChannel <> ballMemChannel - bbus.memBallChannel <> memBallChannel //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 4e800087..6945f548 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -8,47 +8,32 @@ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.blink.HasBlink import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter -import framework.balldomain.bbus.memrouter.MemRouter import framework.balldomain.blink.{BankRead, BankWrite} import framework.top.channels.{Channel, ChannelClusterIO, ChannelIO} -import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices */ @instantiable class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) extends Module { - val numBalls = b.ballDomain.ballNum - val ballMemChannelNum = b.top.ballMemChannelNum - val memBallChannelNum = b.top.memBallChannelNum - val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum - val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum - val memChannel = b.top.ballMemChannelNum + val numBalls = b.ballDomain.ballNum + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + // Rs - bbus - balls @public - val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) + val cmdReq = IO(Vec(numBalls, Flipped(Decoupled(new BallRsIssue(b))))) @public - val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) + val cmdResp = IO(Vec(numBalls, Decoupled(new BallRsComplete(b)))) // balls - bbus @public - val bankRead = IO(Vec(memChannel, Flipped(new BankRead(b)))) - @public - val bankWrite = IO(Vec(memChannel, Flipped(new BankWrite(b)))) - - // bbus - mem - // Channel interface using ChannelClusterIO - // For ballMemChannel: bbus outputs to channel.in, receives from channel.out - // So we need Flipped because direction is reversed from ChannelClusterIO's perspective - @public - val ballMemChannel = IO(Flipped(new ChannelClusterIO(b, ballMemChannelNum))) - + val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public - val memBallChannel = IO(Flipped(new ChannelClusterIO(b, memBallChannelNum))) + val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) val balls = ballGenerators.map(gen => Module(gen())) - val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) - val memoryrouter: Instance[MemRouter] = Instantiate(new MemRouter(b)) - val pmc: Instance[BallCyclePMC] = Instantiate(new BallCyclePMC(b)) + val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) + val pmc: Instance[BallCyclePMC] = Instantiate(new BallCyclePMC(b)) // ----------------------------------------------------------------------------- // cmd router @@ -72,36 +57,6 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) cmdResp <> cmdRouter.io.cmdResp_o -// Initialize ballMemChannel and memBallChannel ports with default values - for (i <- 0 until ballMemChannelNum) { - ballMemChannel.channelIn(i).data.valid := false.B - ballMemChannel.channelIn(i).data.bits := 0.U - ballMemChannel.channelOut(i).data.ready := false.B - } - ballMemChannel.peakChannelReq.valid := false.B - ballMemChannel.peakChannelReq.bits.needed_channel_num := 0.U - ballMemChannel.peakChannelReq.bits.bank_id := 0.U - ballMemChannel.peakChannelReq.bits.rob_id := 0.U - ballMemChannel.freeChannelResp.ready := true.B - - for (i <- 0 until memBallChannelNum) { - memBallChannel.channelIn(i).data.valid := false.B - memBallChannel.channelIn(i).data.bits := 0.U - memBallChannel.channelOut(i).data.ready := false.B - } - memBallChannel.peakChannelReq.valid := false.B - memBallChannel.peakChannelReq.bits.needed_channel_num := 0.U - memBallChannel.peakChannelReq.bits.bank_id := 0.U - memBallChannel.peakChannelReq.bits.rob_id := 0.U - memBallChannel.freeChannelResp.ready := true.B -// ----------------------------------------------------------------------------- -// memory router -// ----------------------------------------------------------------------------- - memoryrouter.io.bankRead_o <> bankRead - memoryrouter.io.bankWrite_o <> bankWrite - memoryrouter.io.peakChannelReq <> ballMemChannel.peakChannelReq - memoryrouter.io.freeChannelResp <> ballMemChannel.freeChannelResp - // ----------------------------------------------------------------------------- // PMC - Performance Monitor Counter // ----------------------------------------------------------------------------- @@ -122,12 +77,12 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val outBW = ballConfig.map(_.outBW).getOrElse(0) for (i <- 0 until inBW) { - memoryrouter.io.bankRead_i(readChannelIdx) <> ball.blink.bankRead(i) + bankRead(readChannelIdx) <> ball.blink.bankRead(i) readChannelIdx = readChannelIdx + 1 } for (i <- 0 until outBW) { - memoryrouter.io.bankWrite_i(writeChannelIdx) <> ball.blink.bankWrite(i) + bankWrite(writeChannelIdx) <> ball.blink.bankWrite(i) writeChannelIdx = writeChannelIdx + 1 } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 14e2d43c..47e69481 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -90,7 +90,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.bankReadReq(0).bits.addr := op1_addr + iter_counter io.bankReadReq(1).valid := iter_counter < iter io.bankReadReq(1).bits.addr := op2_addr + iter_counter - iter_counter := iter_counter + 1.U + iter_counter := Mux(io.bankReadReq(0).ready, iter_counter, iter_counter + 1.U) } // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 1f9819be..01fa9bb3 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -16,6 +16,8 @@ import framework.memdomain.backend.MemBackend @instantiable class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum @public val io = IO(new Bundle { @@ -36,8 +38,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) // Use bbusProducerChannels and bbusConsumerChannels instead of bankNum to match BallDomain output val ballDomain = new Bundle { - val bankRead = Vec(b.top.memBallChannelNum, new BankRead(b)) - val bankWrite = Vec(b.top.ballMemChannelNum, new BankWrite(b)) + val bankRead = Vec(totalBallRead, new BankRead(b)) + val bankWrite = Vec(totalBallWrite, new BankWrite(b)) } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 66a4e868..8ef52c0b 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -19,10 +19,9 @@ import framework.memdomain.backend.accpipe.AccPipe * 5) Add cross read/write conflict assertions based on actual bank requests (valid-level, and fire-level optional) */ class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val rbank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val wbank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) // FIX: was Output + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) } @instantiable @@ -42,7 +41,7 @@ class MemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.write <> io.mem_req(i).write accPipes(i).io.read <> io.mem_req(i).read - accPipes(i).io.bank_id := io.mem_req(i).wbank_id + accPipes(i).io.bank_id := io.mem_req(i).bank_id } // ----------------------------------------------------------------------------- @@ -129,7 +128,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // ------------------------- val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) for (i <- 0 until b.memDomain.bankChannel) { - wMatch(i) := io.mem_req(i).wbank_id === bankId && io.mem_req(i).write.req.valid + wMatch(i) := io.mem_req(i).bank_id === bankId && io.mem_req(i).write.req.valid } val wHas = wMatch.asUInt.orR // stronger safety: at most 1 @@ -159,10 +158,10 @@ class MemBackend(val b: GlobalConfig) extends Module { // ------------------------- val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) for (i <- 0 until b.memDomain.bankChannel) { - rMatch(i) := io.mem_req(i).rbank_id === bankId && io.mem_req(i).read.req.valid + rMatch(i) := io.mem_req(i).bank_id === bankId && io.mem_req(i).read.req.valid } val rHas = rMatch.asUInt.orR - assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") + //assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") val selIdx = OHToUInt(rMatch) val connectIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) @@ -171,7 +170,7 @@ class MemBackend(val b: GlobalConfig) extends Module { when(rHas) { // bank gets req from selected pipe using Mux1H - bank.io.sramRead.req.valid := io.mem_req(selIdx).rbank_id === bankId + bank.io.sramRead.req.valid := io.mem_req(selIdx).bank_id === bankId bank.io.sramRead.req.bits := io.mem_req(selIdx).read.req.bits // selected pipe sees ready from bank rd_req_ready(selIdx) := bank.io.sramRead.req.ready diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index eaca4afe..fbc36f1d 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -16,6 +16,8 @@ import framework.memdomain.backend.MemRequestIO */ @instantiable class MemMidend(val b: GlobalConfig) extends Module { + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum @public val io = IO(new Bundle { @@ -27,8 +29,8 @@ class MemMidend(val b: GlobalConfig) extends Module { } val balldomain = new Bundle { - val bankRead = Vec(b.top.memBallChannelNum, new BankRead(b)) - val bankWrite = Vec(b.top.ballMemChannelNum, new BankWrite(b)) + val bankRead = Vec(totalBallRead, new BankRead(b)) + val bankWrite = Vec(totalBallWrite, new BankWrite(b)) } // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here @@ -36,21 +38,82 @@ class MemMidend(val b: GlobalConfig) extends Module { }) // ----------------------------------------------------------------------------- - // Basic direct connection: route frontend requests to backend channels + // Mapping table for tracking balldomain requests // ----------------------------------------------------------------------------- - // Map bbusChannel input channels to bankChannel output channels - // Each input channel is mapped to a backend channel based on modulo + class MappingTableEntry extends Bundle { + val valid = Bool() + val isRead = Bool() + val id = UInt(log2Ceil(math.max(totalBallRead, totalBallWrite)).W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel - 1)(0.U.asTypeOf(new MappingTableEntry)))) - for (ch <- 0 until b.top.memBallChannelNum) { + def addEntry(idx: UInt, isRead: Bool, id: UInt): Unit = { + mappingTable(idx).valid := true.B + mappingTable(idx).isRead := isRead + mappingTable(idx).id := id + } - // Map input channels to backend channels - io.mem_req(ch).write <> io.balldomain.bankWrite(ch).io - io.mem_req(ch).read <> io.balldomain.bankRead(ch).io - io.mem_req(ch).rbank_id := io.balldomain.bankWrite(ch).bank_id - io.mem_req(ch).wbank_id := io.balldomain.bankWrite(ch).bank_id + def allocateChannel(): UInt = { + val freeChannels = mappingTable.map(entry => !entry.valid) + PriorityEncoder(freeChannels) } + + def isAllocated(isRead: Bool, id: UInt): Bool = + mappingTable.map(entry => entry.valid && entry.isRead === isRead && entry.id === id).reduce(_ || _) + + for (i <- 0 until totalBallRead) { + //Default values + io.balldomain.bankRead(i).io.req.ready := false.B + io.balldomain.bankRead(i).io.resp.valid := false.B; + io.balldomain.bankRead(i).io.resp.bits := DontCare + + when(io.balldomain.bankRead(i).io.req.valid && !isAllocated(true.B, i.U)) { + addEntry(allocateChannel(), true.B, i.U) + } + } + + for (i <- 0 until totalBallWrite) { + //Default values + io.balldomain.bankWrite(i).io.req.ready := false.B + io.balldomain.bankWrite(i).io.resp.valid := false.B; + io.balldomain.bankWrite(i).io.resp.bits := DontCare + //disable for now + + /* when(io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U)) { addEntry(allocateChannel(), + * false.B, i.U) } */ + } + + //Connect balldomain to backend + for (i <- 0 until b.top.memBallChannelNum) { + //Default values + io.mem_req(i).read.req.valid := false.B + io.mem_req(i).read.req.bits := DontCare + io.mem_req(i).read.resp.ready := false.B + io.mem_req(i).write.req.valid := false.B + io.mem_req(i).write.req.bits := DontCare + io.mem_req(i).write.resp.ready := false.B + io.mem_req(i).bank_id := 0.U + + val isRead = mappingTable(i).isRead + val ballRead = io.balldomain.bankRead(mappingTable(i).id).io + val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io + val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id + val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id + + when(mappingTable(i).valid) { + when(isRead) { + io.mem_req(i).read <> ballRead + io.mem_req(i).bank_id := rbank_id + }.otherwise { + io.mem_req(i).write <> ballWrite + io.mem_req(i).bank_id := wbank_id + } + } + } + + //Connect frontend to backend io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io - io.mem_req(b.top.memBallChannelNum).rbank_id := io.frontend.bankWrite.bank_id - io.mem_req(b.top.memBallChannelNum).wbank_id := io.frontend.bankRead.bank_id + io.mem_req(b.top.memBallChannelNum).bank_id := io.frontend.bankWrite.bank_id } From ec610a62df0428ebdde7e07bd81df648c6bf0eda Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 30 Jan 2026 18:21:08 +0800 Subject: [PATCH 066/238] [sims] feat: add cosimulation support --- arch/src/csrc/include/bdb.h | 10 +- arch/src/csrc/src/main.cc | 43 ++---- workflow/bbdev | 8 ++ workflow/steps/verilator/03_build_api_step.py | 5 +- .../steps/verilator/03_build_event_step.py | 28 +++- workflow/steps/verilator/04_cosim_api_step.py | 40 ++++++ .../steps/verilator/04_cosim_event_step.py | 124 ++++++++++++++++++ workflow/steps/verilator/05_run_api_step.py | 1 + 8 files changed, 217 insertions(+), 42 deletions(-) create mode 100644 workflow/steps/verilator/04_cosim_api_step.py create mode 100644 workflow/steps/verilator/04_cosim_event_step.py diff --git a/arch/src/csrc/include/bdb.h b/arch/src/csrc/include/bdb.h index e85ba802..b553189e 100644 --- a/arch/src/csrc/include/bdb.h +++ b/arch/src/csrc/include/bdb.h @@ -8,12 +8,14 @@ // verilator #include "verilated.h" // #include "verilated_vcd_c.h" -#include "VTestHarness.h" -#include "verilated_fst_c.h" -// ================ DataType ==================== +#ifdef COSIM +#include "VToyBuckyball.h" +#else +#include "VTestHarness.h" +#endif -// ================ RISCV CPU =================== +#include "verilated_fst_c.h" // ================ BDB Config =================== // VCD file path diff --git a/arch/src/csrc/src/main.cc b/arch/src/csrc/src/main.cc index 97c14f35..70e1a198 100644 --- a/arch/src/csrc/src/main.cc +++ b/arch/src/csrc/src/main.cc @@ -2,20 +2,18 @@ #include "utils/debug.h" #include "utils/macro.h" -// #include "../build/obj_dir/VTestHarness___024root.h" - -// #define MAX_SIM_TIME 50 Maximum simulation cycles vluint64_t sim_time = 0; - VerilatedContext *contextp = NULL; -// VerilatedVcdC *tfp = NULL; VerilatedFstC *tfp = NULL; + +#ifdef COSIM +static VToyBuckyball *top; +#else static VTestHarness *top; +#endif -// Record how many steps taken, useful for debugging when errors occur int bb_step = 1; -//================ SIM FUNCTION =====================// void step_and_dump_wave() { top->eval(); contextp->timeInc(1); @@ -26,15 +24,17 @@ void step_and_dump_wave() { void sim_init(int argc, char **argv) { contextp = new VerilatedContext; contextp->commandArgs(argc, argv); - // tfp = new VerilatedVcdC; tfp = new VerilatedFstC; + +#ifdef COSIM + top = new VToyBuckyball{contextp}; +#else top = new VTestHarness{contextp}; +#endif contextp->traceEverOn(true); top->trace(tfp, 0); - // tfp->open(vcd_path); - // Log("The waveform will be saved to the VCD file: %s", vcd_path); tfp->open(fst_path); Log("The waveform will be saved to the FST file: %s", fst_path); @@ -47,17 +47,12 @@ void sim_init(int argc, char **argv) { top->reset = 0; top->clock = 0; step_and_dump_wave(); - - // top->rootp->TestHarness__DOT__chiptop0__DOT__system__DOT__pbus__DOT__bootAddrReg - // = 0x80000000ULL; - // Low-level reset } void sim_exit() { contextp->timeInc(1); tfp->dump(contextp->time()); tfp->close(); - // printf("The wave data has been saved to the VCD file: %s\n", vcd_path); printf("The wave data has been saved to the FST file: %s\n", fst_path); exit(0); } @@ -67,30 +62,16 @@ void ball_exec_once() { step_and_dump_wave(); top->clock ^= 1; step_and_dump_wave(); - // top->rootp->TestHarness__DOT__chiptop0__DOT__system__DOT__pbus__DOT__bootAddrReg - // = 0x80000000ULL; +#ifndef COSIM if (top->io_success == 1) { printf("simulation success\n"); sim_exit(); } - // dump_gpr(); - // npc_step++; - // printf("bootAddrReg = 0x%x\n", - // top->rootp->TestHarness__DOT__chiptop0__DOT__system__DOT__pbus__DOT__bootAddrReg); - // Toggle twice to execute one instruction +#endif } -// void init_tet() { -// while (cpu_npc.pc != MEM_BASE) { -// // printf("%ld\n", cpu_npc.pc); -// npc_exec_once(); -// // npc_step--; -// } // PC advances until first instruction execution completes -// } - //================ main =====================// int main(int argc, char *argv[]) { - // Parse parameters here, including VCD path init_monitor(argc, argv); sim_init(argc, argv); bdb_mainloop(); diff --git a/workflow/bbdev b/workflow/bbdev index 293982bf..832f58f2 100755 --- a/workflow/bbdev +++ b/workflow/bbdev @@ -77,6 +77,14 @@ def parse_args(argv: list[str]) -> argparse.Namespace: metavar="ARGS", help='Integrated build+sim+run. Args: "--binary [--batch] [--job ]"', ) + verilator_group.add_argument( + "--cosim", + type=str, + nargs="?", + const="", + metavar="ARGS", + help='Run verilator cosimulation. Args: "--binary [--batch]"', + ) # ===== vcs subcommand ========================================================================= vcs_parser = subparsers.add_parser("vcs", help="vcs operations") diff --git a/workflow/steps/verilator/03_build_api_step.py b/workflow/steps/verilator/03_build_api_step.py index 659a6d25..2c77f19e 100644 --- a/workflow/steps/verilator/03_build_api_step.py +++ b/workflow/steps/verilator/03_build_api_step.py @@ -14,7 +14,10 @@ async def handler(req, context): body = req.get("body") or {} - data = {"jobs": body.get("jobs", 16)} + data = { + "jobs": body.get("jobs", 16), + "cosim": body.get("cosim", False), + } await context.emit({"topic": "verilator.build", "data": data}) # ================================================================================== diff --git a/workflow/steps/verilator/03_build_event_step.py b/workflow/steps/verilator/03_build_event_step.py index efe50dd4..1d5100e5 100644 --- a/workflow/steps/verilator/03_build_event_step.py +++ b/workflow/steps/verilator/03_build_event_step.py @@ -17,7 +17,7 @@ "name": "make build", "description": "build verilator executable", "subscribes": ["verilator.build"], - "emits": ["verilator.sim"], + "emits": ["verilator.sim", "verilator.cosim"], "flows": ["verilator"], } @@ -28,6 +28,7 @@ async def handler(data, context): build_dir = f"{arch_dir}/build" waveform_dir = f"{arch_dir}/waveform" log_dir = f"{arch_dir}/log" + cosim = data.get("cosim", False) # ================================================================================== # Execute operation @@ -45,23 +46,31 @@ async def handler(data, context): + glob.glob(f"{build_dir}/**/*.cpp", recursive=True) ) - # Setup paths + # Setup paths: fesvr from bebop/host/spike/riscv-isa-sim (install/include, install/lib) + bebop_isa_sim = f"{bbdir}/bebop/host/spike/riscv-isa-sim" inc_paths = [ os.environ.get("RISCV", "") + "/include" if os.environ.get("RISCV") else "", f"{arch_dir}/thirdparty/chipyard/tools/DRAMSim2", + f"{bebop_isa_sim}/install/include", build_dir, f"{arch_dir}/src/csrc/include", ] inc_flags = " ".join([f"-I{p}" for p in inc_paths if p]) - topname = "TestHarness" + if cosim: + topname = "ToyBuckyball" + else: + topname = "TestHarness" cflags = f"{inc_flags} -DTOP_NAME='\"V{topname}\"' -std=c++17 " + if cosim: + cflags += " -DCOSIM" ldflags = ( - f"-lreadline -ldramsim -lfesvr " + f"-lreadline -ldramsim -lfesvr -lstdc++ " f"-L{arch_dir}/thirdparty/chipyard/tools/DRAMSim2 " f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build " f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build/lib" + f"-L{bebop_isa_sim}/install/lib" ) obj_dir = f"{build_dir}/obj_dir" @@ -95,7 +104,7 @@ async def handler(data, context): stderr_prefix="verilator build", ) result = stream_run_logger( - cmd=f"make -C {obj_dir} -f V{topname}.mk {obj_dir}/V{topname}", + cmd=f"make -C {obj_dir} -f V{topname}.mk V{topname}", logger=context.logger, cwd=bbdir, stdout_prefix="verilator build", @@ -116,6 +125,13 @@ async def handler(data, context): # Continue routing # ================================================================================== if data.get("from_run_workflow"): - await context.emit({"topic": "verilator.sim", "data": {**data, "task": "run"}}) + if cosim: + await context.emit( + {"topic": "verilator.cosim", "data": {**data, "task": "run"}} + ) + else: + await context.emit( + {"topic": "verilator.sim", "data": {**data, "task": "run"}} + ) return diff --git a/workflow/steps/verilator/04_cosim_api_step.py b/workflow/steps/verilator/04_cosim_api_step.py new file mode 100644 index 00000000..cf0c2820 --- /dev/null +++ b/workflow/steps/verilator/04_cosim_api_step.py @@ -0,0 +1,40 @@ +import os +import sys +import asyncio +from utils.event_common import wait_for_result + +config = { + "type": "api", + "name": "Verilator Cosim", + "description": "run verilator cosimulation", + "path": "/verilator/cosim", + "method": "POST", + "emits": ["verilator.cosim"], + "flows": ["verilator"], +} + + +async def handler(req, context): + body = req.get("body") or {} + binary = body.get("binary", "") + batch = body.get("batch", False) + if not binary: + return { + "status": 400, + "body": { + "success": False, + "failure": True, + "returncode": 400, + "message": "binary parameter is required", + }, + } + + await context.emit({"topic": "verilator.cosim", "data": {**body, "task": "cosim"}}) + # ================================================================================== + # Wait for simulation result + # ================================================================================== + while True: + result = await wait_for_result(context) + if result is not None: + return result + await asyncio.sleep(1) diff --git a/workflow/steps/verilator/04_cosim_event_step.py b/workflow/steps/verilator/04_cosim_event_step.py new file mode 100644 index 00000000..66d26776 --- /dev/null +++ b/workflow/steps/verilator/04_cosim_event_step.py @@ -0,0 +1,124 @@ +import os +import subprocess +import sys +from datetime import datetime + +# Add the utils directory to the Python path +utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) +if utils_path not in sys.path: + sys.path.insert(0, utils_path) + +from utils.path import get_buckyball_path +from utils.stream_run import stream_run_logger +from utils.search_workload import search_workload +from utils.event_common import check_result + +config = { + "type": "event", + "name": "make cosim", + "description": "run cosimulation", + "subscribes": ["verilator.cosim"], + "emits": [], + "flows": ["verilator"], +} + + +async def handler(data, context): + # ================================================================================== + # Get simulation parameters + # ================================================================================== + bbdir = get_buckyball_path() + arch_dir = f"{bbdir}/arch" + build_dir = f"{arch_dir}/build" + + # Generate timestamp + timestamp = datetime.now().strftime("%Y-%m-%d-%H-%M") + + binary_name = data.get("binary", "") + success_result, failure_result = await check_result( + context, returncode=(binary_name == None), continue_run=True + ) + + binary_path = search_workload(f"{bbdir}/bb-tests/output/workloads/src", binary_name) + success_result, failure_result = await check_result( + context, returncode=(binary_path == None), continue_run=True + ) + if failure_result: + context.logger.error("binary not found", failure_result) + return + + # Create log and waveform directory + log_dir = f"{arch_dir}/log/{timestamp}-{binary_name}" + waveform_dir = f"{arch_dir}/waveform/{timestamp}-{binary_name}" + topname = "ToyBuckyball" + + os.makedirs(log_dir, exist_ok=True) + os.makedirs(waveform_dir, exist_ok=True) + + bin_path = f"{build_dir}/obj_dir/V{topname}" + batch = data.get("batch", False) + + # Create log and waveform file + log_path = f"{log_dir}/bdb.log" + fst_path = f"{waveform_dir}/waveform.fst" + # Remove old waveform file + subprocess.run(f"rm -f {waveform_dir}/waveform.vcd", shell=True, check=True) + + # ================================================================================== + # Execute simulation script with streaming output + # ================================================================================== + # batch_param = "True" if batch else "False" + # sim_cmd = f"./scripts/sim.sh {bin_path} {binary_path} {log_dir}/stdout.log \ + # {log_dir}/disasm.log {batch_param} {vcd_path} {log_path}" + sim_cmd = ( + f"{bin_path} +permissive +loadmem={binary_path} +loadmem_addr=800000000 " + f"{'+batch ' if batch else ''} " + f"+fst={fst_path} +log={log_path} +permissive-off " + f"{binary_path} > >(tee {log_dir}/stdout.log) 2> >(spike-dasm > {log_dir}/disasm.log)" + ) + script_dir = os.path.dirname(__file__) + + result = stream_run_logger( + cmd=sim_cmd, + logger=context.logger, + cwd=script_dir, + stdout_prefix="verilator sim", + stderr_prefix="verilator sim", + executable="bash", + ) + success_result, failure_result = await check_result( + context, returncode=result.returncode, continue_run=True + ) + if failure_result: + context.logger.error("sim failed", failure_result) + return + + if os.path.exists(f"{waveform_dir}/waveform.fst.heir"): + subprocess.run( + f"gtkwave -f {waveform_dir}/waveform.fst -H {waveform_dir}/waveform.fst.heir", + shell=True, + check=True, + ) + + # ================================================================================== + # Return simulation result + # ================================================================================== + # This is the end point of the run workflow, status will no longer be set to processing + success_result, failure_result = await check_result( + context, + result.returncode, + continue_run=False, + extra_fields={ + "task": "sim", + "binary": binary_path, + "log_dir": log_dir, + "waveform_dir": waveform_dir, + "timestamp": timestamp, + }, + ) + + # ================================================================================== + # Finish workflow + # ================================================================================== + + return diff --git a/workflow/steps/verilator/05_run_api_step.py b/workflow/steps/verilator/05_run_api_step.py index 77bf175d..b29f3508 100644 --- a/workflow/steps/verilator/05_run_api_step.py +++ b/workflow/steps/verilator/05_run_api_step.py @@ -20,6 +20,7 @@ async def handler(req, context): "config": body.get("config", "sims.verilator.BuckyballToyVerilatorConfig"), "jobs": body.get("jobs", "16"), "batch": body.get("batch", False), + "cosim": body.get("cosim", False), "from_run_workflow": True, } From f444a0ca659e4009a688ccd1a92834558b8832e5 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 30 Jan 2026 20:06:37 +0800 Subject: [PATCH 067/238] [sims] add cosim server --- arch/src/csrc/include/monitor/cosim.h | 160 ++++++++ arch/src/csrc/src/main.cc | 30 ++ arch/src/csrc/src/monitor/cosim/cosim.cc | 491 +++++++++++++++++++++++ bebop | 2 +- 4 files changed, 682 insertions(+), 1 deletion(-) create mode 100644 arch/src/csrc/include/monitor/cosim.h create mode 100644 arch/src/csrc/src/monitor/cosim/cosim.cc diff --git a/arch/src/csrc/include/monitor/cosim.h b/arch/src/csrc/include/monitor/cosim.h new file mode 100644 index 00000000..716c8a62 --- /dev/null +++ b/arch/src/csrc/include/monitor/cosim.h @@ -0,0 +1,160 @@ +#ifndef MONITOR_COSIM_H_ +#define MONITOR_COSIM_H_ + +#include +#include +#include +#include +#include +#include + +// Forward declaration for VToyBuckyball +class VToyBuckyball; + +// Socket protocol structures (match bebop/host/ipc/include/ipc/socket.h) +// Verilator uses different ports (7000-7002) to avoid conflict with Bebop's +// server (6000-6002) +#define SOCKET_CMD_PORT 7000 +#define SOCKET_DMA_READ_PORT 7001 +#define SOCKET_DMA_WRITE_PORT 7002 + +enum socket_msg_type_t : uint32_t { + MSG_TYPE_CMD_REQ = 0, + MSG_TYPE_CMD_RESP = 1, + MSG_TYPE_DMA_READ_REQ = 2, + MSG_TYPE_DMA_READ_RESP = 3, + MSG_TYPE_DMA_WRITE_REQ = 4, + MSG_TYPE_DMA_WRITE_RESP = 5 +}; + +struct msg_header_t { + uint32_t msg_type; + uint32_t reserved; +}; + +struct cmd_req_t { + msg_header_t header; + uint32_t funct; + uint32_t padding; + uint64_t xs1; + uint64_t xs2; +}; + +struct cmd_resp_t { + msg_header_t header; + uint64_t result; +}; + +struct dma_read_req_t { + msg_header_t header; + uint32_t size; + uint32_t padding; + uint64_t addr; +}; + +struct dma_read_resp_t { + msg_header_t header; + uint64_t data_lo; + uint64_t data_hi; +}; + +struct dma_write_req_t { + msg_header_t header; + uint32_t size; + uint32_t padding; + uint64_t addr; + uint64_t data_lo; + uint64_t data_hi; +}; + +struct dma_write_resp_t { + msg_header_t header; + uint64_t reserved; +}; + +// TileLink transaction for pending DMA requests +struct tilelink_transaction_t { + uint8_t opcode; // TileLink opcode (0/1=Put, 4=Get) + uint8_t source; // Transaction ID + uint32_t address; // Memory address + uint8_t size; // Transfer size (2^size bytes) + uint16_t mask; // Byte mask + uint64_t data_lo; // Data low 64 bits (for write) + uint64_t data_hi; // Data high 64 bits (for write) +}; + +// Cosim socket server for VToyBuckyball +class CosimServer { +public: + CosimServer(VToyBuckyball *dut); + ~CosimServer(); + + // Initialize socket servers and start listening + bool init(); + + // Shutdown all connections + void shutdown(); + + // Main update function - called each cycle to handle socket I/O and drive DUT + void update(); + + // Check if server is running + bool is_running() const { return server_running; } + +private: + VToyBuckyball *dut; + std::atomic server_running; + + // Socket file descriptors + int cmd_server_fd; + int dma_read_server_fd; + int dma_write_server_fd; + int cmd_client_fd; + int dma_read_client_fd; + int dma_write_client_fd; + + // Background threads for socket I/O + std::thread cmd_thread; + std::thread dma_read_thread; + std::thread dma_write_thread; + + // CMD queue (Bebop -> Verilator) + std::queue cmd_queue; + std::mutex cmd_mutex; + std::condition_variable cmd_cv; + + // TileLink request queue (Verilator -> Bebop) + std::queue tl_req_queue; + std::mutex tl_req_mutex; + + // TileLink response queue (Bebop -> Verilator) + std::queue tl_resp_queue; + std::mutex tl_resp_mutex; + + // Current CMD being processed + bool cmd_in_progress; + cmd_req_t current_cmd; + + // Socket thread functions + void cmd_server_thread(); + void dma_read_server_thread(); + void dma_write_server_thread(); + + // Socket helpers + int create_server_socket(int port); + int accept_client(int server_fd); + bool recv_all(int fd, void *buf, size_t len); + bool send_all(int fd, const void *buf, size_t len); + + // CMD processing + void handle_cmd_request(); + void drive_cmd_interface(); + + // TileLink/DMA processing + void sample_tilelink_request(); + void drive_tilelink_response(); + void process_dma_read_request(const tilelink_transaction_t &tx); + void process_dma_write_request(const tilelink_transaction_t &tx); +}; + +#endif // MONITOR_COSIM_H_ diff --git a/arch/src/csrc/src/main.cc b/arch/src/csrc/src/main.cc index 70e1a198..218e7b69 100644 --- a/arch/src/csrc/src/main.cc +++ b/arch/src/csrc/src/main.cc @@ -2,12 +2,17 @@ #include "utils/debug.h" #include "utils/macro.h" +#ifdef COSIM +#include "monitor/cosim.h" +#endif + vluint64_t sim_time = 0; VerilatedContext *contextp = NULL; VerilatedFstC *tfp = NULL; #ifdef COSIM static VToyBuckyball *top; +static CosimServer *cosim_server = NULL; #else static VTestHarness *top; #endif @@ -47,6 +52,15 @@ void sim_init(int argc, char **argv) { top->reset = 0; top->clock = 0; step_and_dump_wave(); + +#ifdef COSIM + // Initialize COSIM socket server + cosim_server = new CosimServer(top); + if (!cosim_server->init()) { + panic("Failed to initialize COSIM server"); + } + Log("COSIM mode: waiting for Bebop connection..."); +#endif } void sim_exit() { @@ -54,14 +68,30 @@ void sim_exit() { tfp->dump(contextp->time()); tfp->close(); printf("The wave data has been saved to the FST file: %s\n", fst_path); + +#ifdef COSIM + if (cosim_server) { + cosim_server->shutdown(); + delete cosim_server; + } +#endif + exit(0); } void ball_exec_once() { +#ifdef COSIM + // Update COSIM server (handle socket I/O and drive DUT signals) + if (cosim_server) { + cosim_server->update(); + } +#endif + top->clock ^= 1; step_and_dump_wave(); top->clock ^= 1; step_and_dump_wave(); + #ifndef COSIM if (top->io_success == 1) { printf("simulation success\n"); diff --git a/arch/src/csrc/src/monitor/cosim/cosim.cc b/arch/src/csrc/src/monitor/cosim/cosim.cc new file mode 100644 index 00000000..ac5b660b --- /dev/null +++ b/arch/src/csrc/src/monitor/cosim/cosim.cc @@ -0,0 +1,491 @@ +#ifdef COSIM + +#include "monitor/cosim.h" +#include "VToyBuckyball.h" +#include "utils/debug.h" +#include +#include +#include +#include +#include +#include +#include +#include + +CosimServer::CosimServer(VToyBuckyball *dut) + : dut(dut), server_running(false), cmd_server_fd(-1), + dma_read_server_fd(-1), dma_write_server_fd(-1), cmd_client_fd(-1), + dma_read_client_fd(-1), dma_write_client_fd(-1), cmd_in_progress(false) {} + +CosimServer::~CosimServer() { shutdown(); } + +bool CosimServer::init() { + Log("Initializing COSIM socket server..."); + + // Create server sockets + cmd_server_fd = create_server_socket(SOCKET_CMD_PORT); + dma_read_server_fd = create_server_socket(SOCKET_DMA_READ_PORT); + dma_write_server_fd = create_server_socket(SOCKET_DMA_WRITE_PORT); + + if (cmd_server_fd < 0 || dma_read_server_fd < 0 || dma_write_server_fd < 0) { + panic("Failed to create server sockets"); + return false; + } + + Log("Socket servers listening on ports %d, %d, %d", SOCKET_CMD_PORT, + SOCKET_DMA_READ_PORT, SOCKET_DMA_WRITE_PORT); + + server_running = true; + + // Start background threads + cmd_thread = std::thread(&CosimServer::cmd_server_thread, this); + dma_read_thread = std::thread(&CosimServer::dma_read_server_thread, this); + dma_write_thread = std::thread(&CosimServer::dma_write_server_thread, this); + + Log("COSIM server initialized successfully"); + return true; +} + +void CosimServer::shutdown() { + if (!server_running) + return; + + Log("Shutting down COSIM server..."); + server_running = false; + + // Wake up all threads + cmd_cv.notify_all(); + + // Close client connections + if (cmd_client_fd >= 0) + close(cmd_client_fd); + if (dma_read_client_fd >= 0) + close(dma_read_client_fd); + if (dma_write_client_fd >= 0) + close(dma_write_client_fd); + + // Close server sockets + if (cmd_server_fd >= 0) + close(cmd_server_fd); + if (dma_read_server_fd >= 0) + close(dma_read_server_fd); + if (dma_write_server_fd >= 0) + close(dma_write_server_fd); + + // Join threads + if (cmd_thread.joinable()) + cmd_thread.join(); + if (dma_read_thread.joinable()) + dma_read_thread.join(); + if (dma_write_thread.joinable()) + dma_write_thread.join(); + + Log("COSIM server shutdown complete"); +} + +int CosimServer::create_server_socket(int port) { + int fd = socket(AF_INET, SOCK_STREAM, 0); + if (fd < 0) { + panic("socket() failed: %s", strerror(errno)); + return -1; + } + + // Set SO_REUSEADDR + int opt = 1; + if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt)) < 0) { + panic("setsockopt() failed: %s", strerror(errno)); + close(fd); + return -1; + } + + // Bind + struct sockaddr_in addr; + memset(&addr, 0, sizeof(addr)); + addr.sin_family = AF_INET; + addr.sin_addr.s_addr = INADDR_ANY; + addr.sin_port = htons(port); + + if (bind(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) { + panic("bind() failed on port %d: %s", port, strerror(errno)); + close(fd); + return -1; + } + + // Listen + if (listen(fd, 1) < 0) { + panic("listen() failed: %s", strerror(errno)); + close(fd); + return -1; + } + + return fd; +} + +int CosimServer::accept_client(int server_fd) { + struct sockaddr_in client_addr; + socklen_t client_len = sizeof(client_addr); + int client_fd = + accept(server_fd, (struct sockaddr *)&client_addr, &client_len); + if (client_fd < 0) { + panic("accept() failed: %s", strerror(errno)); + return -1; + } + Log("Accepted client connection from %s:%d", inet_ntoa(client_addr.sin_addr), + ntohs(client_addr.sin_port)); + + // Set TCP_NODELAY to disable Nagle's algorithm + int opt = 1; + if (setsockopt(client_fd, IPPROTO_TCP, TCP_NODELAY, &opt, sizeof(opt)) < 0) { + Log("Failed to set TCP_NODELAY: %s", strerror(errno)); + } + + return client_fd; +} + +bool CosimServer::recv_all(int fd, void *buf, size_t len) { + size_t received = 0; + while (received < len) { + ssize_t n = recv(fd, (char *)buf + received, len - received, 0); + if (n <= 0) { + if (n < 0) + panic("recv() failed: %s", strerror(errno)); + return false; + } + received += n; + } + return true; +} + +bool CosimServer::send_all(int fd, const void *buf, size_t len) { + size_t sent = 0; + while (sent < len) { + ssize_t n = send(fd, (const char *)buf + sent, len - sent, 0); + if (n <= 0) { + if (n < 0) + panic("send() failed: %s", strerror(errno)); + return false; + } + sent += n; + } + return true; +} + +// ============ CMD Server Thread ============ +void CosimServer::cmd_server_thread() { + Log("CMD server thread started"); + + // Accept client connection + cmd_client_fd = accept_client(cmd_server_fd); + if (cmd_client_fd < 0) + return; + + // Process CMD requests + while (server_running) { + cmd_req_t req; + if (!recv_all(cmd_client_fd, &req, sizeof(req))) { + Log("CMD client disconnected"); + break; + } + + if (req.header.msg_type != MSG_TYPE_CMD_REQ) { + panic("Invalid CMD message type: %u", req.header.msg_type); + continue; + } + + // Enqueue CMD request + { + std::lock_guard lock(cmd_mutex); + cmd_queue.push(req); + } + cmd_cv.notify_one(); + + // Wait for CMD completion (io_busy goes low) + // The response will be sent from the main update loop + } + + Log("CMD server thread exiting"); +} + +// ============ DMA Read Server Thread ============ +void CosimServer::dma_read_server_thread() { + Log("DMA Read server thread started"); + + // Accept client connection + dma_read_client_fd = accept_client(dma_read_server_fd); + if (dma_read_client_fd < 0) + return; + Log("DMA Read client accepted"); + + // Process DMA read responses from client + while (server_running) { + Log("DMA Read thread: waiting for response..."); + dma_read_resp_t resp; + // Use non-blocking recv to avoid deadlock + int flags = fcntl(dma_read_client_fd, F_GETFL, 0); + fcntl(dma_read_client_fd, F_SETFL, flags | O_NONBLOCK); + + ssize_t n = recv(dma_read_client_fd, &resp, sizeof(resp), 0); + + fcntl(dma_read_client_fd, F_SETFL, flags); + + if (n > 0) { + Log("DMA Read thread: received msg_type=%u, size=%ld", + resp.header.msg_type, n); + + if (resp.header.msg_type == MSG_TYPE_DMA_READ_RESP) { + // Enqueue TileLink response + tilelink_transaction_t tx; + tx.opcode = 1; // AccessAckData + tx.data_lo = resp.data_lo; + tx.data_hi = resp.data_hi; + + { + std::lock_guard lock(tl_resp_mutex); + tl_resp_queue.push(tx); + } + } else { + panic("Invalid DMA Read response type: %u", resp.header.msg_type); + } + } else if (n == 0) { + Log("DMA Read client disconnected"); + break; + } else if (errno != EAGAIN && errno != EWOULDBLOCK) { + Log("DMA Read recv error: %s", strerror(errno)); + break; + } + + // Sleep briefly to avoid busy-waiting + usleep(100); + } + + Log("DMA Read server thread exiting"); +} + +// ============ DMA Write Server Thread ============ +void CosimServer::dma_write_server_thread() { + Log("DMA Write server thread started"); + + // Accept client connection + dma_write_client_fd = accept_client(dma_write_server_fd); + if (dma_write_client_fd < 0) + return; + + // Process DMA write responses from client + while (server_running) { + dma_write_resp_t resp; + // Use non-blocking recv to avoid deadlock + int flags = fcntl(dma_write_client_fd, F_GETFL, 0); + fcntl(dma_write_client_fd, F_SETFL, flags | O_NONBLOCK); + + ssize_t n = recv(dma_write_client_fd, &resp, sizeof(resp), 0); + + fcntl(dma_write_client_fd, F_SETFL, flags); + + if (n > 0) { + Log("DMA Write thread: received msg_type=%u", resp.header.msg_type); + + if (resp.header.msg_type == MSG_TYPE_DMA_WRITE_RESP) { + // Enqueue TileLink response + tilelink_transaction_t tx; + tx.opcode = 0; // AccessAck + + { + std::lock_guard lock(tl_resp_mutex); + tl_resp_queue.push(tx); + } + } else { + panic("Invalid DMA Write response type: %u", resp.header.msg_type); + } + } else if (n == 0) { + Log("DMA Write client disconnected"); + break; + } else if (errno != EAGAIN && errno != EWOULDBLOCK) { + Log("DMA Write recv error: %s", strerror(errno)); + break; + } + + // Sleep briefly to avoid busy-waiting + usleep(100); + } + + Log("DMA Write server thread exiting"); +} + +// ============ Main Update (called each cycle) ============ +void CosimServer::update() { + // 1. Drive CMD interface (io_cmd_*) + drive_cmd_interface(); + + // 2. Sample TileLink requests (auto_widget_anon_out_a_*) + sample_tilelink_request(); + + // 3. Drive TileLink responses (auto_widget_anon_out_d_*) + drive_tilelink_response(); +} + +void CosimServer::drive_cmd_interface() { + // Check if there's a pending CMD request + if (!cmd_in_progress) { + std::lock_guard lock(cmd_mutex); + if (!cmd_queue.empty()) { + current_cmd = cmd_queue.front(); + cmd_queue.pop(); + cmd_in_progress = true; + + // Drive io_cmd signals + dut->io_cmd_valid = 1; + dut->io_cmd_bits_inst_funct = current_cmd.funct & 0x7F; + dut->io_cmd_bits_rs1 = current_cmd.xs1; + dut->io_cmd_bits_rs2 = current_cmd.xs2; + + Log("CMD Request: funct=%u, xs1=0x%lx, xs2=0x%lx", current_cmd.funct, + current_cmd.xs1, current_cmd.xs2); + } else { + // No pending CMD, clear io_cmd_valid + dut->io_cmd_valid = 0; + } + } else { + // CMD in progress, check if accelerator is ready + if (dut->io_cmd_ready == 1) { + // CMD accepted, clear valid + dut->io_cmd_valid = 0; + cmd_in_progress = false; + + // Send response immediately + cmd_resp_t resp; + resp.header.msg_type = MSG_TYPE_CMD_RESP; + resp.header.reserved = 0; + resp.result = 1; // Success + + if (cmd_client_fd >= 0) { + send_all(cmd_client_fd, &resp, sizeof(resp)); + } + + Log("CMD Response: result=0x%lx", resp.result); + } + } +} + +void CosimServer::sample_tilelink_request() { + // Check if TileLink Channel A has a valid request + static int no_request_count = 0; + + if (dut->auto_widget_anon_out_a_valid == 1) { + tilelink_transaction_t tx; + tx.opcode = dut->auto_widget_anon_out_a_bits_opcode; + tx.source = dut->auto_widget_anon_out_a_bits_source; + tx.address = dut->auto_widget_anon_out_a_bits_address; + tx.size = dut->auto_widget_anon_out_a_bits_size; + tx.mask = dut->auto_widget_anon_out_a_bits_mask; + + // Read data from 128-bit VlWide array (4 x 32-bit words) + // VlWide<4> means 4 words of 32 bits each = 128 bits total + uint32_t *data_words = dut->auto_widget_anon_out_a_bits_data; + tx.data_lo = ((uint64_t)data_words[1] << 32) | (uint64_t)data_words[0]; + tx.data_hi = ((uint64_t)data_words[3] << 32) | (uint64_t)data_words[2]; + + Log("TileLink Request: opcode=%u, addr=0x%x, size=%u, source=%u, ready=%d", + tx.opcode, tx.address, tx.size, tx.source, + dut->auto_widget_anon_out_a_ready); + + no_request_count = 0; + + // Process based on opcode + if (tx.opcode == 4) { + // Get (Read) + process_dma_read_request(tx); + } else if (tx.opcode == 0 || tx.opcode == 1) { + // PutFullData or PutPartialData (Write) + process_dma_write_request(tx); + } + + // Set ready after handling + dut->auto_widget_anon_out_a_ready = 1; + } else { + // No request + if (++no_request_count % 100 == 0) { + Log("No TileLink requests yet (valid=%d, ready=%d)", + dut->auto_widget_anon_out_a_valid, dut->auto_widget_anon_out_a_ready); + } + dut->auto_widget_anon_out_a_ready = 1; + } +} + +void CosimServer::drive_tilelink_response() { + // Check if there's a pending TileLink response + std::lock_guard lock(tl_resp_mutex); + if (!tl_resp_queue.empty() && dut->auto_widget_anon_out_d_ready == 1) { + tilelink_transaction_t tx = tl_resp_queue.front(); + tl_resp_queue.pop(); + + // Drive Channel D signals + dut->auto_widget_anon_out_d_valid = 1; + dut->auto_widget_anon_out_d_bits_opcode = tx.opcode; + dut->auto_widget_anon_out_d_bits_source = tx.source; + + if (tx.opcode == 1) { + // AccessAckData (read response) + // Write data to 128-bit VlWide array (4 x 32-bit words) + uint32_t *data_words = dut->auto_widget_anon_out_d_bits_data; + data_words[0] = (uint32_t)(tx.data_lo & 0xFFFFFFFF); + data_words[1] = (uint32_t)(tx.data_lo >> 32); + data_words[2] = (uint32_t)(tx.data_hi & 0xFFFFFFFF); + data_words[3] = (uint32_t)(tx.data_hi >> 32); + Log("TileLink Response: opcode=%u (AckData), data=0x%lx%lx", tx.opcode, + tx.data_hi, tx.data_lo); + } else { + // AccessAck (write response) + Log("TileLink Response: opcode=%u (Ack)", tx.opcode); + } + } else { + // No pending response + dut->auto_widget_anon_out_d_valid = 0; + } +} + +void CosimServer::process_dma_read_request(const tilelink_transaction_t &tx) { + // Send DMA read request to client + dma_read_req_t req; + req.header.msg_type = MSG_TYPE_DMA_READ_REQ; + req.header.reserved = 0; + req.addr = tx.address; + req.size = 1 << tx.size; // Convert 2^size to bytes + req.padding = 0; + + Log("process_dma_read_request: about to send request, fd=%d", + dma_read_client_fd); + if (dma_read_client_fd >= 0) { + Log("process_dma_read_request: sending request..."); + // Disable Nagle's algorithm to ensure immediate transmission + int opt = 1; + setsockopt(dma_read_client_fd, IPPROTO_TCP, TCP_NODELAY, &opt, sizeof(opt)); + send_all(dma_read_client_fd, &req, sizeof(req)); + Log("process_dma_read_request: request sent: addr=0x%lx, size=%u", req.addr, + req.size); + } else { + Log("process_dma_read_request: dma_read_client_fd is invalid!"); + } + + // Response will be handled in dma_read_server_thread +} + +void CosimServer::process_dma_write_request(const tilelink_transaction_t &tx) { + // Send DMA write request to client + dma_write_req_t req; + req.header.msg_type = MSG_TYPE_DMA_WRITE_REQ; + req.header.reserved = 0; + req.addr = tx.address; + req.size = 1 << tx.size; // Convert 2^size to bytes + req.padding = 0; + req.data_lo = tx.data_lo; + req.data_hi = tx.data_hi; + + if (dma_write_client_fd >= 0) { + send_all(dma_write_client_fd, &req, sizeof(req)); + Log("DMA Write Request: addr=0x%lx, size=%u, data=0x%lx%lx", req.addr, + req.size, req.data_hi, req.data_lo); + } + + // Response will be handled in dma_write_server_thread +} +#endif diff --git a/bebop b/bebop index 51d6ad90..bbd5af60 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 51d6ad90f8dae28ae5572f934c54231aa32faa5e +Subproject commit bbd5af609d0d15cd297314cef072ef2dd199e134 From 79b7386f36517fd5380e3d3a865a4b7b2f5047e9 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Fri, 30 Jan 2026 22:59:36 +0800 Subject: [PATCH 068/238] [arch]Fix some TLB/reader/writer bugs --- .../memdomain/frontend/MemFrontend.scala | 24 +++++----- .../outside_channel/dma/StreamReader.scala | 8 ++-- .../outside_channel/dma/StreamWriter.scala | 38 ++++++---------- .../frontend/outside_channel/tlb/TLB.scala | 45 ++++++++++--------- .../outside_channel/tlb/TLBCluster.scala | 25 +++++------ 5 files changed, 64 insertions(+), 76 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 0a8d54e1..82f23b07 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -109,21 +109,21 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // TLB connection - internal TLB cluster connected to DMA modules // Client 0: StreamWriter, Client 1: StreamReader // Insert pipeline registers to break combinational loops - tlbCluster.io.clients(1).req.valid := RegNext(reader.io.tlb.req.valid) - tlbCluster.io.clients(1).req.bits := RegNext(reader.io.tlb.req.bits) - reader.io.tlb.req.ready := RegNext(tlbCluster.io.clients(1).req.ready) + tlbCluster.io.clients(1).req.valid := reader.io.tlb.req.valid + tlbCluster.io.clients(1).req.bits := reader.io.tlb.req.bits + reader.io.tlb.req.ready := tlbCluster.io.clients(1).req.ready - reader.io.tlb.resp.valid := RegNext(tlbCluster.io.clients(1).resp.valid) - reader.io.tlb.resp.bits := RegNext(tlbCluster.io.clients(1).resp.bits) - tlbCluster.io.clients(1).resp.ready := RegNext(reader.io.tlb.resp.ready) + reader.io.tlb.resp.valid := tlbCluster.io.clients(1).resp.valid + reader.io.tlb.resp.bits := tlbCluster.io.clients(1).resp.bits + tlbCluster.io.clients(1).resp.ready := reader.io.tlb.resp.ready - tlbCluster.io.clients(0).req.valid := RegNext(writer.io.tlb.req.valid) - tlbCluster.io.clients(0).req.bits := RegNext(writer.io.tlb.req.bits) - writer.io.tlb.req.ready := RegNext(tlbCluster.io.clients(0).req.ready) + tlbCluster.io.clients(0).req.valid := writer.io.tlb.req.valid + tlbCluster.io.clients(0).req.bits := writer.io.tlb.req.bits + writer.io.tlb.req.ready := tlbCluster.io.clients(0).req.ready - writer.io.tlb.resp.valid := RegNext(tlbCluster.io.clients(0).resp.valid) - writer.io.tlb.resp.bits := RegNext(tlbCluster.io.clients(0).resp.bits) - tlbCluster.io.clients(0).resp.ready := RegNext(writer.io.tlb.resp.ready) + writer.io.tlb.resp.valid := tlbCluster.io.clients(0).resp.valid + writer.io.tlb.resp.bits := tlbCluster.io.clients(0).resp.bits + tlbCluster.io.clients(0).resp.ready := writer.io.tlb.resp.ready // Connect DMA flush signals to TLB exceptions reader.io.flush := io.tlbExp(0).flush() diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index 96d51b36..56c755db 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -101,7 +101,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a - io.tlb.req.valid := io.tlb.req.ready + io.tlb.req.valid := tlb_q.io.deq.valid && (state === s_req_new_block) io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr io.tlb.req.bits.passthrough := true.B //use paddr for now @@ -111,14 +111,14 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status - tlb_q.io.deq.ready := !io.tlb.resp.bits.miss; + tlb_q.io.deq.ready := io.tlb.resp.valid; /* val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq * translate_q.io.deq.ready := io.tlb.resp.fire && !io.tlb.resp.bits.miss */ // TileLink A channel (request) connection //for now, we just use the vaddr as the physical address to simplify the implementation - io.tl.a.valid := tlb_q.io.deq.fire + io.tl.a.valid := io.tlb.resp.valid && (state === s_req_new_block) io.tl.a.bits := tlb_q.io.deq.bits.tl_a io.tl.a.bits.address := io.tlb.resp.bits.paddr io.tlb.resp.ready := true.B; @@ -173,7 +173,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Use actual requested byte count bytesRequested := bytesRequested + read_size // Check if more requests need to be sent - when(bytesRequested + read_size >= req.len) { + when(bytesRequested >= req.len) { // All requests sent state := s_idle }.otherwise { diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index 801cda02..fb2fe7ad 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -44,9 +44,6 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { }) val s_idle :: s_writing :: Nil = Enum(2) - val state = RegInit(s_idle) - - val req = Reg(new BBWriteRequest(dataWidth)) val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) @@ -59,21 +56,21 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Simplified: data is already aligned, directly construct TileLink request val lg_beat_bytes = log2Ceil(beatBytes) - val use_put_full = req.mask === ~0.U(beatBytes.W) + val use_put_full = io.req.bits.mask === ~0.U(beatBytes.W) val putFull = edge.Put( fromSource = xactId, toAddress = 0.U, lgSize = lg_beat_bytes.U, - data = req.data + data = io.req.bits.data )._2 val putPartial = edge.Put( fromSource = xactId, toAddress = 0.U, lgSize = lg_beat_bytes.U, - data = req.data, - mask = req.mask + data = io.req.bits.data, + mask = io.req.bits.mask )._2 val selected_put = Mux(use_put_full, putFull, putPartial) @@ -87,15 +84,15 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) xactBusy_fire := untranslated_a.fire - untranslated_a.valid := state === s_writing && !xactBusy.andR + untranslated_a.valid := !xactBusy.andR && io.req.valid untranslated_a.bits.tl_a := selected_put - untranslated_a.bits.vaddr := req.vaddr - untranslated_a.bits.status := req.status + untranslated_a.bits.vaddr := io.req.bits.vaddr + untranslated_a.bits.status := io.req.bits.status val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a - io.tlb.req.valid := io.tlb.req.ready + io.tlb.req.valid := tlb_q.io.deq.valid io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr io.tlb.req.bits.passthrough := true.B //use paddr for now @@ -104,14 +101,13 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.bits.prv := 3.U // Machine mode io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status - tlb_q.io.deq.ready := !io.tlb.resp.bits.miss; + tlb_q.io.deq.ready := io.tlb.resp.valid && tlb_q.io.deq.valid - tlb_q.io.deq.ready := true.B; // TileLink A channel (request) connection - io.tl.a.valid := tlb_q.io.deq.fire + io.tl.a.valid := io.tlb.resp.valid && tlb_q.io.deq.valid io.tl.a.bits := tlb_q.io.deq.bits.tl_a io.tl.a.bits.address := io.tlb.resp.bits.paddr - io.tlb.resp.ready := true.B; + io.tlb.resp.ready := true.B // TileLink D channel (response) processing io.tl.d.ready := io.resp.ready @@ -125,15 +121,7 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl.e.valid := false.B // State machine - io.req.ready := state === s_idle - io.busy := xactBusy.orR || (state =/= s_idle) - - when(io.req.fire) { - req := io.req.bits - state := s_writing - } + io.req.ready := !xactBusy.andR + io.busy := xactBusy.orR - when(untranslated_a.fire) { - state := s_idle - } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala index 224d56d4..5f72daf5 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala @@ -18,7 +18,7 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { @public val io = IO(new Bundle { val req = Flipped(Decoupled(new BBTLBReq(lgMaxSize, vaddrBits, b.core.xLen))) - val resp = Output(new BBTLBResp(lgMaxSize, paddrBits, vaddrBits)) + val resp = Decoupled(new BBTLBResp(lgMaxSize, paddrBits, vaddrBits)) val ptw = new BBTLBPTWIO(b) val sfence = Flipped(Valid(Bool())) // Simplified flush signal val kill = Input(Bool()) @@ -136,25 +136,26 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { Cat(hitEntry.ppn, pgIdx) ) - io.resp.miss := tlbMiss || (state === s_wait) - io.resp.paddr := paddr(paddrBits - 1, 0) - io.resp.gpa := 0.U - io.resp.gpa_is_pte := false.B - io.resp.pf.ld := hitEntry.pf - io.resp.pf.st := hitEntry.pf - io.resp.pf.inst := hitEntry.pf - io.resp.gf.ld := false.B - io.resp.gf.st := false.B - io.resp.gf.inst := false.B - io.resp.ae.ld := hitEntry.ae_final - io.resp.ae.st := hitEntry.ae_final - io.resp.ae.inst := hitEntry.ae_final - io.resp.ma.ld := false.B - io.resp.ma.st := false.B - io.resp.ma.inst := false.B - io.resp.cacheable := hitEntry.cacheable - io.resp.must_alloc := false.B - io.resp.prefetchable := hitEntry.cacheable - io.resp.size := io.req.bits.size - io.resp.cmd := io.req.bits.cmd + io.resp.valid := io.req.valid && state === s_ready + io.resp.bits.miss := tlbMiss || (state === s_wait) + io.resp.bits.paddr := paddr(paddrBits - 1, 0) + io.resp.bits.gpa := 0.U + io.resp.bits.gpa_is_pte := false.B + io.resp.bits.pf.ld := hitEntry.pf + io.resp.bits.pf.st := hitEntry.pf + io.resp.bits.pf.inst := hitEntry.pf + io.resp.bits.gf.ld := false.B + io.resp.bits.gf.st := false.B + io.resp.bits.gf.inst := false.B + io.resp.bits.ae.ld := hitEntry.ae_final + io.resp.bits.ae.st := hitEntry.ae_final + io.resp.bits.ae.inst := hitEntry.ae_final + io.resp.bits.ma.ld := false.B + io.resp.bits.ma.st := false.B + io.resp.bits.ma.inst := false.B + io.resp.bits.cacheable := hitEntry.cacheable + io.resp.bits.must_alloc := false.B + io.resp.bits.prefetchable := hitEntry.cacheable + io.resp.bits.size := io.req.bits.size + io.resp.bits.cmd := io.req.bits.cmd } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala index 4bad5709..e4b7ba26 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala @@ -52,10 +52,10 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo // Exception detection val isRead = tlbArbOut.bits.cmd(0) === 0.U - val exception = tlbArbOut.valid && !tlb_io.resp.miss && Mux( + val exception = tlbArbOut.valid && !tlb_io.resp.bits.miss && Mux( isRead, - tlb_io.resp.pf.ld || tlb_io.resp.ae.ld || tlb_io.resp.gf.ld, - tlb_io.resp.pf.st || tlb_io.resp.ae.st || tlb_io.resp.gf.st + tlb_io.resp.bits.pf.ld || tlb_io.resp.bits.ae.ld || tlb_io.resp.bits.gf.ld, + tlb_io.resp.bits.pf.st || tlb_io.resp.bits.ae.st || tlb_io.resp.bits.gf.st ) when(exception) { @@ -82,30 +82,29 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo last_translated_valid && ((client.req.bits.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt) val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.vaddr(pgIdxBits - 1, 0)) - tlbArb.io.in(i).valid := client.req.valid && !l0_tlb_hit + tlbArb.io.in(i).valid := client.req.valid tlbArb.io.in(i).bits := client.req.bits client.req.ready := tlbArb.io.in(i).ready val tlbReq = tlbArb.io.in(i).bits val tlbReqFire = tlbArb.io.in(i).fire - when(tlbReqFire && !tlb_io.resp.miss) { + when(tlbReqFire && !tlb_io.resp.bits.miss) { last_translated_valid := true.B last_translated_vpn := tlbReq.vaddr - last_translated_ppn := tlb_io.resp.paddr + last_translated_ppn := tlb_io.resp.bits.paddr } when(io.exp(0).flush()) { last_translated_valid := false.B } - client.resp.bits.miss := tlb_io.resp.miss - when(tlbReqFire) { - client.resp.valid := !tlb_io.resp.miss - client.resp.bits := tlb_io.resp + client.resp.bits.miss := tlb_io.resp.bits.miss + when(client.req.valid || tlb.io.resp.valid) { + client.resp <> tlb_io.resp }.otherwise { - client.resp.valid := RegNext(!l0_tlb_hit) - client.resp.bits := DontCare - client.resp.bits.paddr := RegNext(l0_tlb_paddr) + client.resp.valid := false.B + client.resp.bits := DontCare + tlb_io.resp.ready := false.B } } } From 0d36b0e11293f9597fdb8ba113da9e6e18be3453 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 2 Feb 2026 19:40:47 +0800 Subject: [PATCH 069/238] [arch] refactor: rewrite RoCC command feat: add more sequencer part into GP domain --- .../scala/examples/toy/CustomConfigs.scala | 5 +- .../scala/examples/toy/ToyBuckyBall.scala | 12 +- .../examples/toy/balldomain/BallDomain.scala | 6 +- .../toy/balldomain/DomainDecoder.scala | 12 +- .../framework/core/rocket/LazyRoCCBB.scala | 34 +- .../framework/core/rocket/RocketCoreBB.scala | 20 +- .../framework/core/rocket/RocketTileBB.scala | 24 +- .../frontend/decoder/GobalDecoder.scala | 8 +- .../globalrs/GlobalReservationStation.scala | 2 +- .../scala/framework/gpdomain/GPDomain.scala | 7 +- .../gpdomain/configs/GpDomainParam.scala | 13 +- .../framework/gpdomain/configs/default.json | 7 +- .../gpdomain/sequencer/Bundles.scala | 300 ++++++++++++++++++ .../gpdomain/sequencer/Sequencer.scala | 259 +++++++++++++++ .../gpdomain/sequencer/TokenManager.scala | 106 +++++++ .../sequencer/decoder/DomainDecoder.scala | 4 +- .../gpdomain/sequencer/package.scala | 96 ++++++ .../memdomain/frontend/MemFrontend.scala | 6 +- .../cmd_channel/decoder/DomainDecoder.scala | 14 +- 19 files changed, 862 insertions(+), 73 deletions(-) create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/Bundles.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/TokenManager.scala create mode 100644 arch/src/main/scala/framework/gpdomain/sequencer/package.scala diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 1c61c600..36bff667 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -3,20 +3,19 @@ package examples.toy import org.chipsalliance.cde.config.{Config, Field, Parameters} import chisel3._ import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.subsystem.SystemBusKey import freechips.rocketchip.tile._ import examples.toy.ToyBuckyball import framework.top.GlobalConfig +import framework.core.rocket.BuildRoCCBB object BuckyballToyConfig { - // 简化：直接使用GlobalConfig() val defaultConfig = GlobalConfig() } class BuckyballCustomConfig( buckyballConfig: GlobalConfig = GlobalConfig()) extends Config((site, here, up) => { - case BuildRoCC => up(BuildRoCC) ++ Seq { + case BuildRoCCBB => up(BuildRoCCBB) ++ Seq { (p: Parameters) => implicit val q = p val buckyball = LazyModule(new ToyBuckyball(buckyballConfig)(q)) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index b5cb03a7..a515b214 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -8,10 +8,10 @@ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.tile.{HasCoreParameters, LazyRoCC, LazyRoCCModuleImp, OpcodeSet, TileKey} +import freechips.rocketchip.tile.{HasCoreParameters, OpcodeSet, TileKey} +import framework.core.rocket.{LazyRoCCBB, LazyRoCCModuleImpBB} import freechips.rocketchip.tilelink._ -import freechips.rocketchip.tile.{LazyRoCC, LazyRoCCModuleImp} import chisel3.experimental.hierarchy.{Instance, Instantiate} import framework.top.GlobalConfig import examples.toy.balldomain.BallDomain @@ -21,12 +21,8 @@ import framework.memdomain.MemDomain import framework.top.channels.{Channel, ChannelCluster, ChannelIO} class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) - extends LazyRoCC(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { + extends LazyRoCCBB(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { - // the width of core's register file - val xLen = p(TileKey).core.xLen - - // DMA nodes for read and write paths val reader_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "bb-dma-reader", sourceId = freechips.rocketchip.diplomacy.IdRange(0, b.memDomain.dma_n_xacts) @@ -52,7 +48,7 @@ class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) override val atlNode = TLIdentityNode() } -class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImp(outer) with HasCoreParameters { +class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) with HasCoreParameters { import outer.b._ val b: GlobalConfig = outer.b val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index e700f7e4..aeeb961a 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -39,9 +39,9 @@ class BallDomain(val b: GlobalConfig) extends Module { //--------------------------------------------------------------------------- // Convert global RS issue to Decoder input format - ballDecoder.raw_cmd_i.valid := global_issue_i.valid - ballDecoder.raw_cmd_i.bits := global_issue_i.bits.cmd - global_issue_i.ready := ballDecoder.raw_cmd_i.ready + ballDecoder.cmd_i.valid := global_issue_i.valid + ballDecoder.cmd_i.bits := global_issue_i.bits.cmd + global_issue_i.ready := ballDecoder.cmd_i.ready //--------------------------------------------------------------------------- // Decoder -> Local BallRS (multi-channel issue to each Ball device) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index ef1031d6..34bf2caf 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -53,15 +53,15 @@ object BallDefaultConstants { class BallDomainDecoder(val b: GlobalConfig) extends Module { import BallDefaultConstants._ @public - val raw_cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) + val cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) @public val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum))) - raw_cmd_i.ready := ball_decode_cmd_o.ready + cmd_i.ready := ball_decode_cmd_o.ready - val func7 = raw_cmd_i.bits.raw_cmd.inst.funct - val rs1 = raw_cmd_i.bits.raw_cmd.rs1 - val rs2 = raw_cmd_i.bits.raw_cmd.rs2 + val func7 = cmd_i.bits.cmd.funct + val rs1 = cmd_i.bits.cmd.rs1Data + val rs2 = cmd_i.bits.cmd.rs2Data // Ball instruction decoding import BallDecodeFields._ @@ -83,7 +83,7 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Output assignment // ----------------------------------------------------------------------------- - ball_decode_cmd_o.valid := raw_cmd_i.valid && (raw_cmd_i.bits.domain_id === DomainId.BALL) + ball_decode_cmd_o.valid := cmd_i.valid && (cmd_i.bits.domain_id === DomainId.BALL) ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) diff --git a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala index 688951ff..0f2628c7 100644 --- a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala +++ b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala @@ -5,8 +5,6 @@ package framework.core.rocket import chisel3._ import chisel3.util._ -import chisel3.experimental.IntParam - import freechips.rocketchip.rocket._ import freechips.rocketchip.tile._ @@ -26,14 +24,24 @@ import freechips.rocketchip.rocket.{ TLBPTWIO } import freechips.rocketchip.tilelink.{TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters, TLNode} -import freechips.rocketchip.util.InOrderArbiter +import freechips.rocketchip.util.{BooleanToAugmentedBoolean, InOrderArbiter} + +case object BuildRoCCBB extends Field[Seq[Parameters => LazyRoCCBB]](Nil) // Custom simplified RoCC types without implicit Parameters class RoCCCommandBB(xLen: Int = 64) extends Bundle { - val inst = new RoCCInstruction - val rs1 = Bits(xLen.W) - val rs2 = Bits(xLen.W) - val status = new MStatus + val raw_inst = UInt(32.W) + val funct = UInt(7.W) + val rs2 = Bits(5.W) + val rs1 = Bits(5.W) + val xd = Bool() + val xs1 = Bool() + val xs2 = Bool() + val rd = Bits(5.W) + val opcode = UInt(7.W) + val rs1Data = UInt(xLen.W) + val rs2Data = UInt(xLen.W) + // val status = new MStatus // Reserved - removed as unused } class RoCCResponseBB(xLen: Int = 64) extends Bundle { @@ -81,7 +89,13 @@ class LazyRoCCModuleImpBB(outer: LazyRoCCBB) extends LazyModuleImp(outer) { /** Mixins for including RoCC * */ trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => - val roccs = p(BuildRoCC).map(_(p)) + override def usingRoCC: Boolean = !p(BuildRoCCBB).isEmpty + + override def dcacheArbPorts: Int = + 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCCBB).size + + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt + + val roccs = p(BuildRoCCBB).map(_(p)) val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs require( roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, @@ -98,7 +112,7 @@ trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => trait HasLazyRoCCModuleBB extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImpBB => val (respArb, cmdRouter) = if (outer.roccs.nonEmpty) { - val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) + val respArb = Module(new RRArbiter(new RoCCResponseBB(coreParams.xLen), outer.roccs.size)) // Get usingRVVRoCC from tile parameters val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) @@ -131,7 +145,7 @@ class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implic val cmd = Queue(io.in) // Check which opcodes match - val opcodeMatches = opcodes.map(opcode => opcode.matches(cmd.bits.inst.opcode)) + val opcodeMatches = opcodes.map(opcode => opcode.matches(cmd.bits.opcode)) val anyMatch = opcodeMatches.reduce(_ || _) val cmdReadys = io.out.zip(opcodeMatches).zipWithIndex.map { diff --git a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala index d8954479..12e5fa5f 100644 --- a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala @@ -1228,12 +1228,20 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall - io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common - io.rocc.exception := wb_xcpt && csr.io.status.xs.orR - io.rocc.cmd.bits.status := csr.io.status - io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) - io.rocc.cmd.bits.rs1 := wb_reg_wdata - io.rocc.cmd.bits.rs2 := wb_reg_rs2 + io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common + io.rocc.exception := wb_xcpt && csr.io.status.xs.orR + io.rocc.cmd.bits.raw_inst := wb_reg_inst + val inst_bits = wb_reg_inst.asTypeOf(new RoCCInstruction()) + io.rocc.cmd.bits.funct := inst_bits.funct + io.rocc.cmd.bits.rs2 := inst_bits.rs2 + io.rocc.cmd.bits.rs1 := inst_bits.rs1 + io.rocc.cmd.bits.xd := inst_bits.xd + io.rocc.cmd.bits.xs1 := inst_bits.xs1 + io.rocc.cmd.bits.xs2 := inst_bits.xs2 + io.rocc.cmd.bits.rd := inst_bits.rd + io.rocc.cmd.bits.opcode := inst_bits.opcode + io.rocc.cmd.bits.rs1Data := wb_reg_wdata + io.rocc.cmd.bits.rs2Data := wb_reg_rs2 // gate the clock val unpause = diff --git a/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala b/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala index 856bbc91..4a1614b6 100644 --- a/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala +++ b/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala @@ -78,12 +78,12 @@ class RocketTileBB private ( extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications - with HasLazyRoCC // Use standard HasLazyRoCC instead of HasLazyRoCCBB + with HasLazyRoCCBB with HasHellaCache with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly def this( - params: RocketTileParamsBB, + params: RocketTileParamsBB, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl )( @@ -189,21 +189,17 @@ class RocketTileBB private ( class RocketTileModuleImpBB(outer: RocketTileBB) extends BaseTileModuleImp(outer) with HasFpuOptBB - with HasLazyRoCCModuleBB // Use HasLazyRoCCModuleBB but with standard RoCC types + with HasLazyRoCCModuleBB with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) - val core = Module(new RocketBB(outer)(outer.p)) - // Create RocketBB with modified parameters that include BuildRoCCBB as BuildRoCC - // We override the useRoCC and dcacheArbPorts to include BuildRoCCBB - // if we override after in RocketTileBB it will be too late - // that other modules like dcache will use the original parameters - // ================================================================================= - // implicit val modifiedP: Parameters = outer.p.alterMap(Map( - // BuildRoCC -> (outer.p(BuildRoCC) ++ outer.p(BuildRoCCBB)) - // )) - // val core = Module(new RocketBB(outer)(modifiedP)) - // ================================================================================= + val modifiedP = outer.p.alterMap(Map( + BuildRoCC -> (outer.p(BuildRoCC) ++ outer.p(BuildRoCCBB).map(f => + (p: Parameters) => f(p).asInstanceOf[freechips.rocketchip.tile.LazyRoCC] + )) + )) + + val core = Module(new RocketBB(outer)(modifiedP)) outer.vector_unit.foreach { v => core.io.vector.get <> v.module.io.core v.module.io.tlb <> outer.dcache.module.io.tlb_port diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index faa78e75..72b6170a 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -20,7 +20,7 @@ class BuckyballRawCmd(val b: GlobalConfig) extends Bundle { class PostGDCmd(b: GlobalConfig) extends Bundle { val domain_id = UInt(4.W) - val raw_cmd = new RoCCCommandBB(b.core.xLen) + val cmd = new RoCCCommandBB(b.core.xLen) } @instantiable @@ -39,8 +39,8 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { // If reservation station is blocked, id_i is also blocked io.id_i.ready := io.id_o.ready - val func7 = io.id_i.bits.cmd.inst.funct - val opcode = io.id_i.bits.cmd.inst.opcode + val func7 = io.id_i.bits.cmd.funct + val opcode = io.id_i.bits.cmd.opcode // Instruction type determination: distinguish Ball, Mem, Fence, GP (RVV) instructions val is_mem_inst = (func7 === MVIN_BITPAT) || @@ -70,5 +70,5 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { // Output control io.id_o.valid := io.id_i.valid io.id_o.bits.domain_id := domain_id - io.id_o.bits.raw_cmd := io.id_i.bits.cmd + io.id_o.bits.cmd := io.id_i.bits.cmd } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 9a533e35..ec47b5d7 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -61,7 +61,7 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- val fenceActive = RegInit(false.B) // Cannot use fire, would form a loop - val func7 = io.global_decode_cmd_i.bits.raw_cmd.inst.funct + val func7 = io.global_decode_cmd_i.bits.cmd.funct val isFenceCmd = io.global_decode_cmd_i.valid && (func7 === FENCE_BITPAT) val robEmpty = rob.io.empty diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index bfe6889f..8985787f 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -13,9 +13,8 @@ class GpDomain(val b: GlobalConfig) extends Module { val io = IO(new Bundle { val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) val global_complete_o = Decoupled(new GlobalRsComplete(b)) - // Status signal - val busy = Output(Bool()) + val busy = Output(Bool()) }) io.global_issue_i.ready := io.global_complete_o.ready @@ -25,8 +24,8 @@ class GpDomain(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- val decoder: Instance[framework.gpdomain.sequencer.decoder.DomainDecoder] = Instantiate(new framework.gpdomain.sequencer.decoder.DomainDecoder(b)) - // Extract raw_cmd from PostGDCmd - decoder.io.inst_i <> io.global_issue_i.bits.cmd.raw_cmd + // Extract raw_inst from PostGDCmd + decoder.io.inst_i <> io.global_issue_i.bits.cmd.cmd val decoded = decoder.io.decoded_o io.global_complete_o.valid := io.global_issue_i.valid diff --git a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala index 267811ad..405bde98 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala +++ b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala @@ -6,7 +6,18 @@ import upickle.default._ * GpDomain参数 */ case class GpDomainParam( - placeholder: Int) + /** Number of lanes in the GP domain */ + laneNumber: Int, + /** Chaining size for instruction scheduling */ + chainingSize: Int, + /** Vector length in bits */ + vLen: Int, + /** Data length per lane in bits */ + dLen: Int, + /** Element length in bits */ + eLen: Int, + /** Lane scale factor */ + laneScale: Int) object GpDomainParam { implicit val rw: ReadWriter[GpDomainParam] = macroRW diff --git a/arch/src/main/scala/framework/gpdomain/configs/default.json b/arch/src/main/scala/framework/gpdomain/configs/default.json index 36280ff7..e8322624 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/default.json +++ b/arch/src/main/scala/framework/gpdomain/configs/default.json @@ -1,3 +1,8 @@ { - "placeholder": 0 + "laneNumber": 4, + "chainingSize": 4, + "vLen": 1024, + "dLen": 128, + "eLen": 32, + "laneScale": 4 } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/Bundles.scala b/arch/src/main/scala/framework/gpdomain/sequencer/Bundles.scala new file mode 100644 index 00000000..db83becb --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/Bundles.scala @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu +// Port to buckyball framework + +package framework.gpdomain.sequencer + +import chisel3._ +import chisel3.util._ +import chisel3.util.experimental.decode.DecodeBundle +import framework.gpdomain.sequencer.decoder.{Decoder, DomainDecoderParameter} + +/** CSR Interface from Scalar Core */ +class CSRInterface(vlWidth: Int) extends Bundle { + + /** Vector Length Register `vl` */ + val vl: UInt = UInt(vlWidth.W) + + /** Vector Start Index CSR `vstart` */ + val vStart: UInt = UInt(vlWidth.W) + + /** Vector Register Grouping `vlmul[2:0]` subfield of `vtype` */ + val vlmul: UInt = UInt(3.W) + + /** Vector Selected Element Width `vsew[2:0]` subfield of `vtype` */ + val vSew: UInt = UInt(2.W) + + /** Vector Fixed-Point Rounding Mode Register `vxrm` */ + val vxrm: UInt = UInt(2.W) + + /** Floating-point rounding mode */ + val frm: UInt = UInt(3.W) + + /** Vector Tail Agnostic */ + val vta: Bool = Bool() + + /** Vector Mask Agnostic */ + val vma: Bool = Bool() +} + +/** Instruction record for tracking issued instructions */ +class InstructionRecord(instructionIndexWidth: Int) extends Bundle { + + /** Index of this instruction, maintained by instruction counter */ + val instructionIndex: UInt = UInt(instructionIndexWidth.W) + + /** Whether instruction is load/store */ + val isLoadStore: Bool = Bool() + + /** Whether instruction is mask type */ + val maskType: Bool = Bool() + + val gather: Bool = Bool() + val pop: Bool = Bool() +} + +/** Instruction execution state */ +class InstructionState extends Bundle { + + /** Wait for last signal from each lane */ + val wLast: Bool = Bool() + + /** The slot is idle */ + val idle: Bool = Bool() + + /** Used for mask unit, schedule mask unit to execute */ + val wMaskUnitLast: Bool = Bool() + + /** Used for instruction commit */ + val sCommit: Bool = Bool() +} + +/** Instruction control state for each slot */ +class InstructionControl(instIndexWidth: Int, laneSize: Int) extends Bundle { + + /** Metadata for this instruction */ + val record: InstructionRecord = new InstructionRecord(instIndexWidth) + + /** Control state to record the current execution state */ + val state: InstructionState = new InstructionState + + /** Tag for recording each lane is finished for this instruction */ + val endTag: Vec[Bool] = Vec(laneSize + 1, Bool()) + + /** Fixed-point saturation flag */ + val vxsat: Bool = Bool() +} + +/** Issue token for token manager */ +class IssueToken(instructionIndexBits: Int) extends Bundle { + val instructionIndex: UInt = UInt(instructionIndexBits.W) + val writeV0: Bool = Bool() + val useV0AsMask: Bool = Bool() + val isLoadStore: Bool = Bool() + val toLane: Bool = Bool() + val toMask: Bool = Bool() +} + +/** Instruction pipe bundle for queuing */ +class InstructionPipeBundle( + xLen: Int, + vLen: Int, + instructionIndexBits: Int, + vlMaxBits: Int) + extends Bundle { + val instruction: UInt = UInt(32.W) + val rs1Data: UInt = UInt(xLen.W) + val rs2Data: UInt = UInt(xLen.W) + val vl: UInt = UInt(32.W) + val vstart: UInt = UInt(32.W) + val vtype: UInt = UInt(32.W) + val decodeResult: DecodeBundle = Decoder.bundle(DomainDecoderParameter.decoderParam).cloneType + val instructionIndex: UInt = UInt(instructionIndexBits.W) + val vdIsV0: Bool = Bool() + val writeByte: UInt = UInt(vlMaxBits.W) +} + +// ============================================================================ +// VRF Related Bundles +// ============================================================================ + +/** Request to access VRF in each lanes */ +class VRFReadRequest(regNumBits: Int, offsetBits: Int, instructionIndexBits: Int) extends Bundle { + + /** address to access VRF (v0, v1, v2, ...) */ + val vs: UInt = UInt(regNumBits.W) + + /** read vs1 vs2 vd? */ + val readSource: UInt = UInt(2.W) + + /** the offset of VRF access */ + val offset: UInt = UInt(offsetBits.W) + + /** index for record the age of instruction, designed for handling RAW hazard */ + val instructionIndex: UInt = UInt(instructionIndexBits.W) +} + +class VRFWriteRequest( + regNumBits: Int, + offsetBits: Int, + instructionIndexSize: Int, + dataPathWidth: Int) + extends Bundle { + + /** address to access VRF (v0, v1, v2, ...) */ + val vd: UInt = UInt(regNumBits.W) + + /** the offset of VRF access */ + val offset: UInt = UInt(offsetBits.W) + + /** write mask in byte */ + val mask: UInt = UInt((dataPathWidth / 8).W) + + /** data to write to VRF */ + val data: UInt = UInt(dataPathWidth.W) + + /** this is the last write of this instruction */ + val last: Bool = Bool() + + /** used to update the record in VRF */ + val instructionIndex: UInt = UInt(instructionIndexSize.W) +} + +class V0Update(datapathWidth: Int, vrfOffsetBits: Int) extends Bundle { + val data: UInt = UInt(datapathWidth.W) + val offset: UInt = UInt(vrfOffsetBits.W) + val mask: UInt = UInt((datapathWidth / 8).W) +} + +// ============================================================================ +// Lane Related Bundles +// ============================================================================ + +/** Request from sequencer to lane */ +class LaneRequest( + instructionIndexBits: Int, + datapathWidth: Int, + vlMaxBits: Int, + laneNumber: Int, + dataPathByteWidth: Int) + extends Bundle { + val instructionIndex: UInt = UInt(instructionIndexBits.W) + + // decode + val decodeResult: DecodeBundle = Decoder.bundle(DomainDecoderParameter.decoderParam).cloneType + val loadStore: Bool = Bool() + val issueInst: Bool = Bool() + val store: Bool = Bool() + val special: Bool = Bool() + val lsWholeReg: Bool = Bool() + + // instruction + val vs1: UInt = UInt(5.W) + val vs2: UInt = UInt(5.W) + val vd: UInt = UInt(5.W) + + val loadStoreEEW: UInt = UInt(2.W) + val mask: Bool = Bool() + val segment: UInt = UInt(3.W) + + /** data of rs1 */ + val readFromScalar: UInt = UInt(datapathWidth.W) + + val csrInterface: CSRInterface = new CSRInterface(vlMaxBits) + + val writeCount: UInt = UInt((vlMaxBits - log2Ceil(laneNumber) - log2Ceil(dataPathByteWidth)).W) + + val maskE0: Bool = Bool() +} + +class LaneResponse(chaining1HBits: Int, vlMaxBits: Int) extends Bundle { + val instructionFinished: UInt = UInt(chaining1HBits.W) + val vxsatReport: UInt = UInt(chaining1HBits.W) + val popCount: UInt = UInt(vlMaxBits.W) +} + +class LaneResponseFeedback(instructionIndexBits: Int) extends Bundle { + + /** which instruction is the source of this transaction */ + val instructionIndex: UInt = UInt(instructionIndexBits.W) + + /** for instructions that might finish in other lanes */ + val complete: Bool = Bool() +} + +// ============================================================================ +// Mask Related Bundles +// ============================================================================ + +class MaskRequest(maskGroupSizeBits: Int) extends Bundle { + + /** select which mask group */ + val maskSelect: UInt = UInt(maskGroupSizeBits.W) + + /** The sew of instruction which is requesting for mask */ + val maskSelectSew: UInt = UInt(2.W) + + val slide: Bool = Bool() +} + +class MaskRequestAck(maskGroupWidth: Int) extends Bundle { + val data: UInt = UInt(maskGroupWidth.W) +} + +class MaskUnitExeReq( + eLen: Int, + datapathWidth: Int, + instructionIndexBits: Int, + fpuEnable: Boolean) + extends Bundle { + val source1: UInt = UInt(datapathWidth.W) + val source2: UInt = UInt(datapathWidth.W) + val index: UInt = UInt(instructionIndexBits.W) + val ffo: UInt = UInt((datapathWidth / eLen).W) + val fpReduceValid: Option[UInt] = Option.when(fpuEnable)(UInt((datapathWidth / eLen).W)) + val maskRequestToLSU: Bool = Bool() +} + +// ============================================================================ +// LSU Related Bundles +// ============================================================================ + +class LSUInstructionInformation extends Bundle { + val nf: UInt = UInt(3.W) + val mew: Bool = Bool() + val mop: UInt = UInt(2.W) + val lumop: UInt = UInt(5.W) + val eew: UInt = UInt(2.W) + val vs3: UInt = UInt(5.W) + val isStore: Bool = Bool() + val maskedLoadStore: Bool = Bool() + + def fof: Bool = mop === 0.U && lumop(4) && !isStore +} + +class LSURequest(dataWidth: Int, chainingSize: Int) extends Bundle { + val instructionInformation: LSUInstructionInformation = new LSUInstructionInformation + val rs1Data: UInt = UInt(dataWidth.W) + val rs2Data: UInt = UInt(dataWidth.W) + val instructionIndex: UInt = UInt((log2Ceil(chainingSize) + 1).W) +} + +class LSURequestInterface(dataWidth: Int, chainingSize: Int, vlWidth: Int) extends Bundle { + val request: LSURequest = new LSURequest(dataWidth, chainingSize) + val csrInterface: CSRInterface = new CSRInterface(vlWidth) +} + +// ============================================================================ +// Common Bundles +// ============================================================================ + +class LastReportBundle(chaining1HBits: Int) extends Bundle { + val last: UInt = UInt(chaining1HBits.W) +} + +class WriteCountReport(vLen: Int, laneNumber: Int, instSize: Int) extends Bundle { + val count: UInt = UInt(log2Ceil(vLen / laneNumber).W) + val instructionIndex: UInt = UInt(instSize.W) +} + +final class EmptyBundle extends Bundle diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala b/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala new file mode 100644 index 00000000..81ba1266 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu +// Port to buckyball framework + +package framework.gpdomain.sequencer + +import chisel3._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.util._ +import chisel3.util.experimental.decode.DecodeBundle +import framework.top.GlobalConfig +import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.gpdomain.sequencer.decoder.{Decoder, DomainDecoder} + +/** + * Sequencer for GP Domain + * + * Handles instruction issue, scheduling, token management, and coordination + * between lanes, LSU, and mask unit. + * + * Ported from T1's sequencer logic + */ +@instantiable +class Sequencer(val b: GlobalConfig) extends Module { + val chainingSize = b.gpDomain.chainingSize + val laneNumber = b.gpDomain.laneNumber + val vLen = b.gpDomain.vLen + val dLen = b.gpDomain.dLen + val eLen = b.gpDomain.eLen + val xLen = 32 // Fixed to 32 for now + + val instructionIndexBits = log2Ceil(chainingSize) + 1 + val chaining1HBits = 2 << log2Ceil(chainingSize) + val datapathWidth = b.gpDomain.laneScale * eLen + val vlMaxBits = log2Ceil(vLen * 8 / 8) + 1 // vLen in bits / sewMin + val regNumBits = 5 // 32 vector registers + val vrfOffsetBits = log2Ceil(vLen / datapathWidth / laneNumber) + + @public + val io = IO(new Bundle { + // Interface with global RS + val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) + val global_complete_o = Decoupled(new GlobalRsComplete(b)) + + // TODO: Interface with lanes (placeholder) + // val laneRequest = Vec(laneNumber, Decoupled(new LaneRequest(...))) + // val laneResponse = Vec(laneNumber, Flipped(Decoupled(new LaneResponse(...)))) + + // TODO: Interface with LSU (placeholder) + // val lsuRequest = Decoupled(new LSURequestInterface(...)) + // val lsuReport = Flipped(Decoupled(new LastReportBundle(...))) + + // TODO: Interface with mask unit (placeholder) + // val maskUnitRequest = Decoupled(new MaskUnitExeReq(...)) + // val maskUnitReport = Flipped(Decoupled(new LastReportBundle(...))) + + // Status + val busy = Output(Bool()) + }) + + // =========================================================================== + // Decoder + // =========================================================================== + val decoder: Instance[DomainDecoder] = Instantiate(new DomainDecoder(b)) + decoder.io.inst_i := io.global_issue_i.bits.cmd.cmd + val decoded = decoder.io.decoded_o + + // =========================================================================== + // Token Manager + // =========================================================================== + val tokenManager: Instance[TokenManager] = Instantiate(new TokenManager(b)) + + // =========================================================================== + // Instruction Counter + // =========================================================================== + val instructionCounter: UInt = RegInit(0.U(instructionIndexBits.W)) + val nextInstructionCounter: UInt = instructionCounter + 1.U + + // =========================================================================== + // Request Register (1-deep queue) + // =========================================================================== + val requestReg: ValidIO[InstructionPipeBundle] = RegInit( + 0.U.asTypeOf(Valid(new InstructionPipeBundle(xLen, vLen, instructionIndexBits, vlMaxBits))) + ) + + val requestRegDequeue = Wire(Decoupled(io.global_issue_i.bits.cloneType)) + + // Latch instruction when issued + when(io.global_issue_i.fire) { + requestReg.bits.instruction := io.global_issue_i.bits.cmd.cmd.raw_inst + requestReg.bits.rs1Data := io.global_issue_i.bits.cmd.cmd.rs1Data + requestReg.bits.rs2Data := io.global_issue_i.bits.cmd.cmd.rs2Data + requestReg.bits.vl := 0.U // TODO: extract from CSR + requestReg.bits.vstart := 0.U // TODO: extract from CSR + requestReg.bits.vtype := 0.U // TODO: extract from CSR + requestReg.bits.decodeResult := decoded + requestReg.bits.instructionIndex := instructionCounter + requestReg.bits.vdIsV0 := (io.global_issue_i.bits.cmd.cmd.raw_inst(11, 7) === 0.U) && + (io.global_issue_i.bits.cmd.cmd.raw_inst(6) || !io.global_issue_i.bits.cmd.cmd.raw_inst(5)) + requestReg.bits.writeByte := 0.U // TODO: calculate based on vl and sew + + instructionCounter := nextInstructionCounter + } + + // Request register valid update + requestReg.valid := Mux( + io.global_issue_i.fire ^ requestRegDequeue.fire, + io.global_issue_i.fire, + requestReg.valid + ) + + // Manually maintain dequeue interface + requestRegDequeue.bits := io.global_issue_i.bits + requestRegDequeue.valid := requestReg.valid + + // Decode result alias + val decodeResult: DecodeBundle = requestReg.bits.decodeResult + + // Instruction type detection + val isLoadStoreType: Bool = !requestRegDequeue.bits.cmd.cmd.raw_inst(6) && requestRegDequeue.valid + val isStoreType: Bool = !requestRegDequeue.bits.cmd.cmd.raw_inst(6) && requestRegDequeue.bits.cmd.cmd.raw_inst(5) + val maskType: Bool = !requestRegDequeue.bits.cmd.cmd.raw_inst(25) + + // =========================================================================== + // Instruction Slots (State Machine Registers) + // =========================================================================== + val instructionFinished: Vec[Vec[Bool]] = Wire(Vec(laneNumber, Vec(chainingSize, Bool()))) + val vxsatReportVec: Vec[UInt] = Wire(Vec(laneNumber, UInt(chainingSize.W))) + val vxsatReport = vxsatReportVec.reduce(_ | _) + + // Initialize dummy values (will be connected to lanes later) + instructionFinished.foreach(_.foreach(_ := false.B)) + vxsatReportVec.foreach(_ := 0.U) + + val slots: Seq[InstructionControl] = Seq.tabulate(chainingSize) { index => + val control = RegInit( + (-1.S(new InstructionControl(instructionIndexBits, laneNumber).getWidth.W)) + .asTypeOf(new InstructionControl(instructionIndexBits, laneNumber)) + ) + + // Execution finished check + val laneAndLSUFinish: Bool = control.endTag.asUInt.andR + val v0WriteFinish = !ohCheck(tokenManager.v0WriteValid, control.record.instructionIndex, chainingSize) + + // LSU finished (placeholder) + val lsuFinished: Bool = false.B // TODO: connect to LSU + val vxsatUpdate = ohCheck(vxsatReport, control.record.instructionIndex, chainingSize) + + // Instruction allocation to this slot + val instructionToSlotOH: UInt = Wire(UInt(chainingSize.W)) + when(instructionToSlotOH(index)) { + // Instruction metadata + control.record.instructionIndex := requestReg.bits.instructionIndex + control.record.isLoadStore := isLoadStoreType + control.record.maskType := maskType + control.record.gather := false.B // TODO: decode + control.record.pop := false.B // TODO: decode + + // Control signals + control.state.idle := false.B + control.state.wLast := false.B + control.state.sCommit := false.B + control.state.wMaskUnitLast := true.B // TODO: check maskUnit requirement + + control.vxsat := false.B + + // Initialize endTag + control.endTag := VecInit(Seq.fill(laneNumber)(false.B) :+ !isLoadStoreType) + }.otherwise { + // State machine updates + when(laneAndLSUFinish && v0WriteFinish) { + control.state.wLast := true.B + } + + // TODO: Add retire logic + // when(responseCounter === control.record.instructionIndex && retire) { + // control.state.sCommit := true.B + // } + + when(control.state.sCommit && control.state.wMaskUnitLast) { + control.state.idle := true.B + } + + // Update endTag from lanes + control.endTag.zip(instructionFinished.map(_(index)) :+ lsuFinished).foreach { + case (d, c) => + d := d || c + } + + when(vxsatUpdate) { + control.vxsat := true.B + } + } + + control + } + + // =========================================================================== + // Slot Allocation Logic + // =========================================================================== + val slotFree: Vec[Bool] = VecInit(slots.map(_.state.idle)) + val allSlotFree: Bool = slotFree.asUInt.andR + val freeOR: Bool = slotFree.asUInt.orR + + // Special instructions go to last slot + val specialInstruction: Bool = false.B // TODO: decode special instructions + val slotReady: Bool = Mux(specialInstruction, slots.last.state.idle, freeOR) + + // Select slot for new instruction + val instructionToSlotOH: UInt = Mux( + specialInstruction, + UIntToOH(chainingSize.U), + PriorityEncoderOH(slotFree.asUInt) + ) + + // =========================================================================== + // Token Manager Connections + // =========================================================================== + tokenManager.instructionIssue.valid := requestRegDequeue.valid + tokenManager.instructionIssue.bits.instructionIndex := requestReg.bits.instructionIndex + tokenManager.instructionIssue.bits.writeV0 := requestReg.bits.vdIsV0 + tokenManager.instructionIssue.bits.useV0AsMask := maskType + tokenManager.instructionIssue.bits.isLoadStore := isLoadStoreType + tokenManager.instructionIssue.bits.toLane := !isLoadStoreType + tokenManager.instructionIssue.bits.toMask := false.B // TODO: detect mask unit instructions + + // LSU write v0 connections (placeholder) + tokenManager.lsuWriteV0.foreach { port => + port.valid := false.B + port.bits := 0.U + } + + // Instruction finish signals (placeholder) + tokenManager.instructionFinish.foreach(_ := 0.U) + tokenManager.maskUnitFree := true.B + + // =========================================================================== + // Issue Logic + // =========================================================================== + // Can issue when: + // 1. There's a free slot + // 2. Token manager allows (no v0 conflicts) + // 3. All lanes are ready (TODO) + val canIssue: Bool = slotReady && tokenManager.issueAllow + + io.global_issue_i.ready := canIssue && io.global_complete_o.ready + requestRegDequeue.ready := canIssue + + // =========================================================================== + // Completion Logic (Placeholder) + // =========================================================================== + io.global_complete_o.valid := io.global_issue_i.valid + io.global_complete_o.bits.rob_id := io.global_issue_i.bits.rob_id + + // =========================================================================== + // Status + // =========================================================================== + io.busy := !allSlotFree +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/TokenManager.scala b/arch/src/main/scala/framework/gpdomain/sequencer/TokenManager.scala new file mode 100644 index 00000000..84897bd4 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/TokenManager.scala @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu +// Port to buckyball framework + +package framework.gpdomain.sequencer + +import chisel3._ +import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.util._ +import framework.top.GlobalConfig + +object TokenManagerUtil { + + /** Convert index to one-hot encoding */ + def indexToOH(index: UInt, chainingSize: Int): UInt = + UIntToOH(index(log2Ceil(chainingSize), 0)) + + /** Conditional mask application */ + def maskAnd(mask: Bool, data: Data): Data = + Mux(mask, data, 0.U.asTypeOf(data)) +} + +@instantiable +class TokenManager(b: GlobalConfig) extends Module { + import TokenManagerUtil._ + + val chainingSize = b.gpDomain.chainingSize + val laneNumber = b.gpDomain.laneNumber + val instructionIndexBits = log2Ceil(chainingSize) + 1 + val chaining1HBits = 2 << log2Ceil(chainingSize) + + @public + val instructionIssue: ValidIO[IssueToken] = IO(Flipped(Valid(new IssueToken(instructionIndexBits)))) + + @public + val lsuWriteV0: Vec[ValidIO[UInt]] = IO( + Vec(laneNumber, Flipped(Valid(UInt(instructionIndexBits.W)))) + ) + + @public + val issueAllow: Bool = IO(Output(Bool())) + + @public + val instructionFinish: Vec[UInt] = IO(Vec(laneNumber, Input(UInt(chaining1HBits.W)))) + + @public + val v0WriteValid = IO(Output(UInt(chaining1HBits.W))) + + @public + val maskUnitFree: Bool = IO(Input(Bool())) + + val issueIndex1H: UInt = indexToOH(instructionIssue.bits.instructionIndex, chainingSize) + + // Boolean type token clear & set + def updateBooleanToken(set: UInt, clear: UInt): UInt = { + VecInit(Seq.tabulate(chaining1HBits) { chainingIndex => + val res = RegInit(false.B) + when(set(chainingIndex) || clear(chainingIndex)) { + res := set(chainingIndex) + } + res + }).asUInt + } + + // v0 write token + val v0WriteValidVec: Seq[UInt] = Seq.tabulate(laneNumber) { laneIndex => + val lsuWriteSet = maskAnd( + lsuWriteV0(laneIndex).valid, + indexToOH(lsuWriteV0(laneIndex).bits, chainingSize) + ).asUInt + val v0WriteIssue = + instructionIssue.valid && instructionIssue.bits.writeV0 && (instructionIssue.bits.toLane || instructionIssue.bits.isLoadStore) + val clear: UInt = instructionFinish(laneIndex) + val updateOH = maskAnd(v0WriteIssue, issueIndex1H).asUInt + updateBooleanToken(updateOH | lsuWriteSet, clear) + } + + val useV0AsMaskToken: UInt = Seq + .tabulate(laneNumber) { laneIndex => + val useV0Issue = instructionIssue.valid && instructionIssue.bits.useV0AsMask && + instructionIssue.bits.toLane + val clear: UInt = instructionFinish(laneIndex) + val updateOH = maskAnd(useV0Issue, issueIndex1H).asUInt + updateBooleanToken(updateOH, clear) + } + .reduce(_ | _) + + val maskUnitWriteV0: Bool = { + val set = instructionIssue.valid && instructionIssue.bits.writeV0 && instructionIssue.bits.toMask + val clear = maskUnitFree + val res = RegInit(false.B) + when(set || clear) { + res := set + } + res + } + + v0WriteValid := v0WriteValidVec.reduce(_ | _) + + // v0 read-write conflict + val v0Conflict: Bool = + (instructionIssue.bits.writeV0 && useV0AsMaskToken.orR) || + (instructionIssue.bits.useV0AsMask && (v0WriteValid.orR || maskUnitWriteV0)) + + issueAllow := !v0Conflict +} diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala index 23239b0d..91cfa20d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala @@ -49,8 +49,8 @@ class DomainDecoder(val b: GlobalConfig) extends Module { val decode = Decoder.decode(decoderParam) // Decode the incoming instruction - // RoCCCommandBB has 'inst' field (RoCCInstruction Bundle), need to convert to UInt - val inst = io.inst_i.inst.asUInt + // RoCCCommandBB has 'raw_inst' field containing the raw 32-bit instruction + val inst = io.inst_i.raw_inst io.decoded_o := decode(inst) } diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/package.scala b/arch/src/main/scala/framework/gpdomain/sequencer/package.scala new file mode 100644 index 00000000..4b0f9fd7 --- /dev/null +++ b/arch/src/main/scala/framework/gpdomain/sequencer/package.scala @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu +// Port to buckyball framework + +package framework.gpdomain + +import chisel3._ +import chisel3.util._ + +package object sequencer { + + /** Find first one */ + def ffo(input: UInt): UInt = + ((~(scanLeftOr(input) << 1)).asUInt & input)(input.getWidth - 1, 0) + + /** Conditional mask application */ + def maskAnd(mask: Bool, data: Data): Data = + Mux(mask, data, 0.U.asTypeOf(data)) + + /** Enable/disable mask */ + def maskEnable(enable: Bool, mask: UInt): UInt = + Mux(enable, mask, (-1.S(mask.getWidth.W)).asUInt.asTypeOf(mask)) + + /** Convert index to one-hot encoding */ + def indexToOH(index: UInt, chainingSize: Int): UInt = + UIntToOH(index(log2Ceil(chainingSize), 0)) + + /** Check if index matches in one-hot encoded lastReport */ + def ohCheck(lastReport: UInt, index: UInt, chainingSize: Int): Bool = + (indexToOH(index, chainingSize) & lastReport).orR + + /** Instruction index comparison: a < b */ + def instIndexL(a: UInt, b: UInt): Bool = { + require(a.getWidth == b.getWidth) + (a(a.getWidth - 2, 0) < b(b.getWidth - 2, 0)) ^ a(a.getWidth - 1) ^ b(b.getWidth - 1) + } + + /** Instruction index comparison: a <= b */ + def instIndexLE(a: UInt, b: UInt): Bool = { + require(a.getWidth == b.getWidth) + a === b || instIndexL(a, b) + } + + /** Cut UInt into equal width pieces */ + def cutUInt(data: UInt, width: Int): Vec[UInt] = { + require(data.getWidth % width == 0) + VecInit(Seq.tabulate(data.getWidth / width) { groupIndex => + data(groupIndex * width + width - 1, groupIndex * width) + }) + } + + /** Cut UInt into specified number of pieces */ + def cutUIntBySize(data: UInt, size: Int): Vec[UInt] = { + require(data.getWidth % size == 0) + val width: Int = data.getWidth / size + cutUInt(data, width) + } + + /** Change UInt size with optional sign extension */ + def changeUIntSize(data: UInt, size: Int, sign: Boolean = false): UInt = { + if (data.getWidth >= size) { + data(size - 1, 0) + } else { + val extend = if (sign) data(data.getWidth - 1) else false.B + Fill(size - data.getWidth, extend) ## data + } + } + + /** Carry-save adder 3:2 compressor */ + def csa32(s: UInt, c: UInt, a: UInt): (UInt, UInt) = { + val xor = s ^ c + val so = xor ^ a + val co = (xor & a) | (s & c) + (so, co) + } + + /** Multi-lane shifter */ + def multiShifter(right: Boolean, multiSize: Int)(data: UInt, shifterSize: UInt): UInt = { + VecInit( + data.asBools + .grouped(multiSize) + .toSeq + .transpose + .map { dataGroup => + if (right) { + (VecInit(dataGroup).asUInt >> shifterSize).asBools + } else { + (VecInit(dataGroup).asUInt << shifterSize).asBools + } + } + .transpose + .map(VecInit(_).asUInt) + ).asUInt + } + +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 82f23b07..57169811 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -67,9 +67,9 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ----------------------------------------------------------------------------- // Global RS -> MemDecoder // ----------------------------------------------------------------------------- - memDecoder.io.raw_cmd_i.valid := io.global_issue_i.valid - memDecoder.io.raw_cmd_i.bits := io.global_issue_i.bits.cmd - io.global_issue_i.ready := memDecoder.io.raw_cmd_i.ready + memDecoder.io.cmd_i.valid := io.global_issue_i.valid + memDecoder.io.cmd_i.bits := io.global_issue_i.bits.cmd + io.global_issue_i.ready := memDecoder.io.cmd_i.ready // ----------------------------------------------------------------------------- // MemDecoder -> MemReservationStation diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index 9f09eb55..d756d8a1 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -43,7 +43,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val raw_cmd_i = Flipped(Decoupled(new PostGDCmd(b))) + val cmd_i = Flipped(Decoupled(new PostGDCmd(b))) val mem_decode_cmd_o = Decoupled(new MemDecodeCmd(b)) }) @@ -52,11 +52,11 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val bankIdLen = log2Up(b.memDomain.bankNum) // Only process Mem instructions - io.raw_cmd_i.ready := io.mem_decode_cmd_o.ready + io.cmd_i.ready := io.mem_decode_cmd_o.ready - val func7 = io.raw_cmd_i.bits.raw_cmd.inst.funct - val rs1 = io.raw_cmd_i.bits.raw_cmd.rs1 - val rs2 = io.raw_cmd_i.bits.raw_cmd.rs2 + val func7 = io.cmd_i.bits.cmd.funct + val rs1 = io.cmd_i.bits.cmd.rs1Data + val rs2 = io.cmd_i.bits.cmd.rs2Data // Load/Store instruction decoding import LSDecodeFields._ @@ -97,7 +97,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { ) assert( - !(io.raw_cmd_i.fire && !ls_decode_list(LSDecodeFields.VALID.id).asBool), + !(io.cmd_i.fire && !ls_decode_list(LSDecodeFields.VALID.id).asBool), s"MemDomainDecoder: Invalid command opcode, func7 = 0x%x\n", func7 ) @@ -105,7 +105,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Output assignment // ----------------------------------------------------------------------------- - io.mem_decode_cmd_o.valid := io.raw_cmd_i.valid && (io.raw_cmd_i.bits.domain_id === DomainId.MEM) + io.mem_decode_cmd_o.valid := io.cmd_i.valid && (io.cmd_i.bits.domain_id === DomainId.MEM) io.mem_decode_cmd_o.bits.is_load := Mux( io.mem_decode_cmd_o.valid, From 4771e886b2701fe1528854c3d836ca791d7d2f08 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Mon, 2 Feb 2026 22:03:30 +0800 Subject: [PATCH 070/238] [arch]Rewrite mapping table allocating logic --- .../prototype/vector/VecLoadUnit.scala | 2 +- .../balldomain/prototype/vector/VecUnit.scala | 2 +- .../memdomain/midend/MemMidend.scala | 150 ++++++++++++------ 3 files changed, 107 insertions(+), 47 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 47e69481..791dc37c 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -90,7 +90,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.bankReadReq(0).bits.addr := op1_addr + iter_counter io.bankReadReq(1).valid := iter_counter < iter io.bankReadReq(1).bits.addr := op2_addr + iter_counter - iter_counter := Mux(io.bankReadReq(0).ready, iter_counter, iter_counter + 1.U) + iter_counter := Mux(io.bankReadReq(0).ready && io.bankReadReq(1).ready, iter_counter + 1.U, iter_counter) } // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index e15c684d..a7dc5756 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -91,7 +91,7 @@ class VecUnit(val b: GlobalConfig) extends Module { VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o for (i <- 0 until outBW) { io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) - io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o + io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o + i.U io.bankWrite(i).io.req.bits.wmode := true.B } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index fbc36f1d..65ee435d 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -5,24 +5,18 @@ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import framework.top.GlobalConfig import framework.balldomain.blink.{BankRead, BankWrite} -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import framework.memdomain.backend.MemRequestIO -/** - * MemMidend: Midend module for memory scheduling - * Connects MemFrontend to MemManager - * - * Basic direct connection: routes requests from frontend to backend channels - */ @instantiable class MemMidend(val b: GlobalConfig) extends Module { val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + val numChannels = b.memDomain.bankChannel - 1 // Reserve one for frontend @public val io = IO(new Bundle { - // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { val bankRead = new BankRead(b) val bankWrite = new BankWrite(b) @@ -33,12 +27,11 @@ class MemMidend(val b: GlobalConfig) extends Module { val bankWrite = Vec(totalBallWrite, new BankWrite(b)) } - // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) }) // ----------------------------------------------------------------------------- - // Mapping table for tracking balldomain requests + // Mapping table // ----------------------------------------------------------------------------- class MappingTableEntry extends Bundle { val valid = Bool() @@ -46,46 +39,90 @@ class MemMidend(val b: GlobalConfig) extends Module { val id = UInt(log2Ceil(math.max(totalBallRead, totalBallWrite)).W) } - val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel - 1)(0.U.asTypeOf(new MappingTableEntry)))) - - def addEntry(idx: UInt, isRead: Bool, id: UInt): Unit = { - mappingTable(idx).valid := true.B - mappingTable(idx).isRead := isRead - mappingTable(idx).id := id - } - - def allocateChannel(): UInt = { - val freeChannels = mappingTable.map(entry => !entry.valid) - PriorityEncoder(freeChannels) - } + val mappingTable = RegInit(VecInit(Seq.fill(numChannels)(0.U.asTypeOf(new MappingTableEntry)))) def isAllocated(isRead: Bool, id: UInt): Bool = mappingTable.map(entry => entry.valid && entry.isRead === isRead && entry.id === id).reduce(_ || _) + // ----------------------------------------------------------------------------- + // Core logic: multi-channel parallel allocation + // ----------------------------------------------------------------------------- + + // 1. Get which channels are free at cycle start (Bitmap) + // use wire to propagate allocation within the cycle + val initialFreeMask = VecInit(mappingTable.map(!_.valid)).asUInt + + var currentFreeMask = initialFreeMask + + // Define request object collection for unified iteration + // Contains: (ReqValid, IsRead, ID, ReqReadyPtr) + case class RequestCandidate( + valid: Bool, + isRead: Bool, + id: Int, + ready: Bool) + + val candidates = scala.collection.mutable.ArrayBuffer[RequestCandidate]() + + // Collect read requests for (i <- 0 until totalBallRead) { - //Default values + // Default value io.balldomain.bankRead(i).io.req.ready := false.B - io.balldomain.bankRead(i).io.resp.valid := false.B; + io.balldomain.bankRead(i).io.resp.valid := false.B io.balldomain.bankRead(i).io.resp.bits := DontCare - when(io.balldomain.bankRead(i).io.req.valid && !isAllocated(true.B, i.U)) { - addEntry(allocateChannel(), true.B, i.U) - } + candidates += RequestCandidate( + io.balldomain.bankRead(i).io.req.valid, + true.B, + i, + io.balldomain.bankRead(i).io.req.ready + ) } + // Collect write requests for (i <- 0 until totalBallWrite) { - //Default values io.balldomain.bankWrite(i).io.req.ready := false.B - io.balldomain.bankWrite(i).io.resp.valid := false.B; + io.balldomain.bankWrite(i).io.resp.valid := false.B io.balldomain.bankWrite(i).io.resp.bits := DontCare - //disable for now - /* when(io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U)) { addEntry(allocateChannel(), - * false.B, i.U) } */ + candidates += RequestCandidate( + io.balldomain.bankWrite(i).io.req.valid, + false.B, + i, + io.balldomain.bankWrite(i).io.req.ready + ) + } - //Connect balldomain to backend - for (i <- 0 until b.top.memBallChannelNum) { + for (cand <- candidates) { + val needsAlloc = cand.valid && !isAllocated(cand.isRead, cand.id.U) + val hasSpace = currentFreeMask.orR // 检查当前掩码中是否还有1 + + when(needsAlloc && hasSpace) { + // Find lowest '1' in current mask (first free channel) + val allocIdx = PriorityEncoder(currentFreeMask) + + mappingTable(allocIdx).valid := true.B + mappingTable(allocIdx).isRead := cand.isRead + mappingTable(allocIdx).id := cand.id.U + + cand.ready := true.B + } + + // Key step: update mask, clear allocated bit + // Logic generates hardware: next request sees current Mask minus allocIdx + // Note: PriorityEncoder and shift operations are hardware logic + val allocIdxWire = PriorityEncoder(currentFreeMask) + // If needsAlloc is true, clear that bit; otherwise keep unchanged + val nextMask = Mux(needsAlloc && hasSpace, currentFreeMask & ~(1.U(numChannels.W) << allocIdxWire), currentFreeMask) + + currentFreeMask = nextMask + } + + // ----------------------------------------------------------------------------- + // Backend Connection + // ----------------------------------------------------------------------------- + for (i <- 0 until numChannels) { //Default values io.mem_req(i).read.req.valid := false.B io.mem_req(i).read.req.bits := DontCare @@ -95,14 +132,17 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).write.resp.ready := false.B io.mem_req(i).bank_id := 0.U - val isRead = mappingTable(i).isRead - val ballRead = io.balldomain.bankRead(mappingTable(i).id).io - val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io - val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id - val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id + val entry = mappingTable(i) + + // Only connect when entry is valid + when(entry.valid) { - when(mappingTable(i).valid) { - when(isRead) { + val ballRead = io.balldomain.bankRead(entry.id).io + val ballWrite = io.balldomain.bankWrite(entry.id).io + val rbank_id = io.balldomain.bankRead(entry.id).bank_id + val wbank_id = io.balldomain.bankWrite(entry.id).bank_id + + when(entry.isRead) { io.mem_req(i).read <> ballRead io.mem_req(i).bank_id := rbank_id }.otherwise { @@ -112,8 +152,28 @@ class MemMidend(val b: GlobalConfig) extends Module { } } - //Connect frontend to backend - io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io - io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io - io.mem_req(b.top.memBallChannelNum).bank_id := io.frontend.bankWrite.bank_id + // Connect frontend to the last channel + val frontendCh = b.top.memBallChannelNum + io.mem_req(frontendCh).write <> io.frontend.bankWrite.io + io.mem_req(frontendCh).read <> io.frontend.bankRead.io + io.mem_req(frontendCh).bank_id := io.frontend.bankWrite.bank_id + + //Mapping table release + for (i <- 0 until numChannels) { + val releaseCounter = RegInit(0.U(5.W)) + + when(mappingTable(i).valid && !(io.mem_req(i).read.resp.valid || + io.mem_req(i).write.resp.valid || io.mem_req(i).read.req.valid || + io.mem_req(i).write.req.valid)) { + releaseCounter := releaseCounter + 1.U + + when(releaseCounter === 16.U) { + releaseCounter := 0.U + mappingTable(i).valid := false.B + mappingTable(i).isRead := false.B + mappingTable(i).id := 0.U + } + + } + } } From d18df9f7d053fc0524c349ebffa8a54dabdb2f3f Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 2 Feb 2026 22:21:35 +0800 Subject: [PATCH 071/238] [nix] feat: init Nix Flake support --- README.md | 10 ++++++++-- flake.lock | 27 +++++++++++++++++++++++++++ flake.nix | 30 ++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 2 deletions(-) create mode 100644 flake.lock create mode 100644 flake.nix diff --git a/README.md b/README.md index 1c4a850e..e666062a 100644 --- a/README.md +++ b/README.md @@ -69,7 +69,13 @@ Run Verilator simulation test to verify installation: bbdev verilator --run '--jobs 16 --binary ctest_vecunit_matmul_ones_singlecore-baremetal --config sims.verilator.BuckyballToyVerilatorConfig --batch' ``` -### Docker Quick Experience +### Installation in nix +We use Nix Flake as our alternative build system. If you have not installed nix, install it following the [guide](https://nix.dev/manual/nix/2.28/installation/installing-binary.html), and enable flake following the [wiki](https://nixos.wiki/wiki/Flakes#Enable_flakes). Or you can try the [installer](https://github.com/DeterminateSystems/nix-installer) provided by Determinate Systems, which enables flake by default. + + +> Nix Installation is still woeking in progress + + ### Buckyball as a library We support providing a streamlined version of buckyball installation, integrated as a generator within Chipyard. diff --git a/flake.lock b/flake.lock new file mode 100644 index 00000000..b8b992e7 --- /dev/null +++ b/flake.lock @@ -0,0 +1,27 @@ +{ + "nodes": { + "nixpkgs": { + "locked": { + "lastModified": 1769789167, + "narHash": "sha256-kKB3bqYJU5nzYeIROI82Ef9VtTbu4uA3YydSk/Bioa8=", + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "62c8382960464ceb98ea593cb8321a2cf8f9e3e5", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixos-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "root": { + "inputs": { + "nixpkgs": "nixpkgs" + } + } + }, + "root": "root", + "version": 7 +} diff --git a/flake.nix b/flake.nix new file mode 100644 index 00000000..a4883caa --- /dev/null +++ b/flake.nix @@ -0,0 +1,30 @@ +{ + description = "Development environment for Buckyball with Verilator"; + + inputs = { + nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; + }; + + outputs = { self, nixpkgs }: + let + systems = [ "x86_64-linux" "aarch64-linux" "x86_64-darwin" "aarch64-darwin" ]; + forEachSystem = f: nixpkgs.lib.genAttrs systems (system: f system); + in + { + devShells = forEachSystem (system: + let + pkgs = import nixpkgs { inherit system; }; + in + { + default = pkgs.mkShell { + packages = [ pkgs.verilator ]; + + shellHook = '' + echo "Verilator development environment" + verilator --version + ''; + }; + } + ); + }; +} From 8ca9697f3fb943e8e08d43f5355ebb0a690a0b36 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Feb 2026 00:10:41 +0800 Subject: [PATCH 072/238] [nix] wip: nix installation update --- flake.nix | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/flake.nix b/flake.nix index a4883caa..f878fc20 100644 --- a/flake.nix +++ b/flake.nix @@ -17,11 +17,25 @@ in { default = pkgs.mkShell { - packages = [ pkgs.verilator ]; + packages = [ + # Fast and robust (System)Verilog simulator/compiler and linter + pkgs.verilator + + # RISC-V embedded toolchain (bare metal) + pkgs.pkgsCross.riscv64-embedded.buildPackages.gcc + + # RISC-V Linux toolchain + pkgs.pkgsCross.riscv64.buildPackages.gcc + + # Build tool for Scala, Java and more + pkgs.mill + ]; shellHook = '' - echo "Verilator development environment" - verilator --version + echo "Verilator: $(verilator --version 2>&1 | head -1)" + echo "RISC-V Embedded GCC: $(riscv64-none-elf-gcc --version 2>&1 | head -1)" + echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" + echo "Mill: cd arch && $(mill --version 2>&1 | head -1) && cd .." ''; }; } From ea14ac93c128cf902ea91ca0db7f54d42dcea0eb Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Feb 2026 01:07:43 +0800 Subject: [PATCH 073/238] [nix] wip: nix installation update --- .gitignore | 3 ++ flake.lock | 33 ++++++++++++++++++++ flake.nix | 56 ++++++++++++++++++++++------------ scripts/nix/build-bebop.nix | 9 ++++++ scripts/nix/build-chipyard.nix | 15 +++++++++ scripts/nix/overlay.nix | 5 +++ 6 files changed, 102 insertions(+), 19 deletions(-) create mode 100644 scripts/nix/build-bebop.nix create mode 100644 scripts/nix/build-chipyard.nix create mode 100644 scripts/nix/overlay.nix diff --git a/.gitignore b/.gitignore index 8f99e267..83ce949b 100644 --- a/.gitignore +++ b/.gitignore @@ -4,6 +4,9 @@ .motia/ .cursor/ .bsp/ +out/ +result/ + CLAUDE.local.md node_modules/ env.sh diff --git a/flake.lock b/flake.lock index b8b992e7..05ddea73 100644 --- a/flake.lock +++ b/flake.lock @@ -1,5 +1,22 @@ { "nodes": { + "flake-utils": { + "inputs": { + "systems": "systems" + }, + "locked": { + "lastModified": 1731533236, + "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=", + "owner": "numtide", + "repo": "flake-utils", + "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b", + "type": "github" + }, + "original": { + "id": "flake-utils", + "type": "indirect" + } + }, "nixpkgs": { "locked": { "lastModified": 1769789167, @@ -18,8 +35,24 @@ }, "root": { "inputs": { + "flake-utils": "flake-utils", "nixpkgs": "nixpkgs" } + }, + "systems": { + "locked": { + "lastModified": 1681028828, + "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", + "owner": "nix-systems", + "repo": "default", + "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "type": "github" + }, + "original": { + "owner": "nix-systems", + "repo": "default", + "type": "github" + } } }, "root": "root", diff --git a/flake.nix b/flake.nix index f878fc20..274adb03 100644 --- a/flake.nix +++ b/flake.nix @@ -3,42 +3,60 @@ inputs = { nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; + # flake-utils.url = "github:numtide/flake-utils"; }; - outputs = { self, nixpkgs }: + outputs = { self, nixpkgs, flake-utils }@inputs: let - systems = [ "x86_64-linux" "aarch64-linux" "x86_64-darwin" "aarch64-darwin" ]; - forEachSystem = f: nixpkgs.lib.genAttrs systems (system: f system); + overlay = import ./scripts/nix/overlay.nix; in - { - devShells = forEachSystem (system: + flake-utils.lib.eachDefaultSystem + (system: let - pkgs = import nixpkgs { inherit system; }; + pkgs = import nixpkgs { overlays = [ overlay ]; inherit system; }; in { - default = pkgs.mkShell { - packages = [ - # Fast and robust (System)Verilog simulator/compiler and linter - pkgs.verilator + legacyPackages = pkgs; - # RISC-V embedded toolchain (bare metal) - pkgs.pkgsCross.riscv64-embedded.buildPackages.gcc + # nix build + packages.default = pkgs.buildEnv { + name = "buckyball-environment"; + paths = with pkgs; [ + # Chipyard tools + chipyard.verilator + chipyard.riscv-embedded-gcc + chipyard.riscv-linux-gcc + chipyard.mill - # RISC-V Linux toolchain - pkgs.pkgsCross.riscv64.buildPackages.gcc - - # Build tool for Scala, Java and more - pkgs.mill + # Bebop tools + bebop.rustc + bebop.cargo + bebop.rustfmt + bebop.clippy ]; + }; + # nix develop + devShells.default = pkgs.mkShell { shellHook = '' + if [ -d "$PWD/result/bin" ]; then + export PATH="$PWD/result/bin:$PATH" + echo "Activated environment" + else + echo "Warning: result/bin not found. Run 'nix build' first." + fi + echo "==========================================" + echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" echo "RISC-V Embedded GCC: $(riscv64-none-elf-gcc --version 2>&1 | head -1)" echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" - echo "Mill: cd arch && $(mill --version 2>&1 | head -1) && cd .." + echo "Mill: $(mill --version 2>&1 | head -1)" + echo "==========================================" ''; }; } - ); + ) // { + inherit inputs; + overlays.default = overlay; }; } diff --git a/scripts/nix/build-bebop.nix b/scripts/nix/build-bebop.nix new file mode 100644 index 00000000..c17c8b40 --- /dev/null +++ b/scripts/nix/build-bebop.nix @@ -0,0 +1,9 @@ +{ pkgs }: + +{ + # Rust toolchain + rustc = pkgs.rustc; + cargo = pkgs.cargo; + rustfmt = pkgs.rustfmt; + clippy = pkgs.clippy; +} diff --git a/scripts/nix/build-chipyard.nix b/scripts/nix/build-chipyard.nix new file mode 100644 index 00000000..438b329c --- /dev/null +++ b/scripts/nix/build-chipyard.nix @@ -0,0 +1,15 @@ +{ pkgs }: + +{ + # Fast and robust (System)Verilog simulator/compiler and linter + verilator = pkgs.verilator; + + # RISC-V embedded toolchain (bare metal) + riscv-embedded-gcc = pkgs.pkgsCross.riscv64-embedded.buildPackages.gcc; + + # RISC-V Linux toolchain + riscv-linux-gcc = pkgs.pkgsCross.riscv64.buildPackages.gcc; + + # Build tool for Scala, Java and more + mill = pkgs.mill; +} diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix new file mode 100644 index 00000000..767b8eee --- /dev/null +++ b/scripts/nix/overlay.nix @@ -0,0 +1,5 @@ +final: prev: +{ + chipyard = final.callPackage ./build-chipyard.nix { }; + bebop = final.callPackage ./build-bebop.nix { }; +} From 20e745c7208969043fdeebe0c81a2a548bf69687 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Feb 2026 02:38:28 +0800 Subject: [PATCH 074/238] [nix] feat: update Nix environment setup del: remove Docker support --- .gitignore | 2 +- README.md | 19 +- flake.lock | 6 +- flake.nix | 36 +- scripts/docker/.dockerignore | 60 - scripts/docker/Dockerfile | 43 - scripts/docker/README.md | 80 - scripts/docker/docker-compose.yml | 20 - scripts/nix/build-all.sh | 176 + scripts/nix/build-env-bbdev.nix | 15 + .../{build-bebop.nix => build-env-bebop.nix} | 0 ...ld-chipyard.nix => build-env-chipyard.nix} | 3 +- scripts/nix/build-env-doc.nix | 12 + scripts/nix/build-env-python.nix | 48 + scripts/nix/build-env-scala.nix | 12 + scripts/nix/overlay.nix | 8 +- workflow/.gitignore | 4 +- workflow/package-lock.json | 9627 +++++++++++++++++ workflow/package.json | 28 + 19 files changed, 9972 insertions(+), 227 deletions(-) delete mode 100644 scripts/docker/.dockerignore delete mode 100644 scripts/docker/Dockerfile delete mode 100644 scripts/docker/README.md delete mode 100644 scripts/docker/docker-compose.yml create mode 100644 scripts/nix/build-all.sh create mode 100644 scripts/nix/build-env-bbdev.nix rename scripts/nix/{build-bebop.nix => build-env-bebop.nix} (100%) rename scripts/nix/{build-chipyard.nix => build-env-chipyard.nix} (84%) create mode 100644 scripts/nix/build-env-doc.nix create mode 100644 scripts/nix/build-env-python.nix create mode 100644 scripts/nix/build-env-scala.nix create mode 100644 workflow/package-lock.json create mode 100644 workflow/package.json diff --git a/.gitignore b/.gitignore index 83ce949b..7da0902b 100644 --- a/.gitignore +++ b/.gitignore @@ -5,7 +5,7 @@ .cursor/ .bsp/ out/ -result/ +result CLAUDE.local.md node_modules/ diff --git a/README.md b/README.md index e666062a..8919f939 100644 --- a/README.md +++ b/README.md @@ -72,18 +72,17 @@ bbdev verilator --run '--jobs 16 --binary ctest_vecunit_matmul_ones_singlecore-b ### Installation in nix We use Nix Flake as our alternative build system. If you have not installed nix, install it following the [guide](https://nix.dev/manual/nix/2.28/installation/installing-binary.html), and enable flake following the [wiki](https://nixos.wiki/wiki/Flakes#Enable_flakes). Or you can try the [installer](https://github.com/DeterminateSystems/nix-installer) provided by Determinate Systems, which enables flake by default. +```bash +git clone https://github.com/DangoSys/buckyball.git +cd buckyball +./scripts/nix/build-all.sh +``` -> Nix Installation is still woeking in progress - - ### Buckyball as a library We support providing a streamlined version of buckyball installation, integrated as a generator within Chipyard. diff --git a/flake.lock b/flake.lock index 05ddea73..b9182344 100644 --- a/flake.lock +++ b/flake.lock @@ -19,11 +19,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1769789167, - "narHash": "sha256-kKB3bqYJU5nzYeIROI82Ef9VtTbu4uA3YydSk/Bioa8=", + "lastModified": 1770019141, + "narHash": "sha256-VKS4ZLNx4PNrABoB0L8KUpc1fE7CLpQXQs985tGfaCU=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "62c8382960464ceb98ea593cb8321a2cf8f9e3e5", + "rev": "cb369ef2efd432b3cdf8622b0ffc0a97a02f3137", "type": "github" }, "original": { diff --git a/flake.nix b/flake.nix index 274adb03..0bfadc4f 100644 --- a/flake.nix +++ b/flake.nix @@ -26,13 +26,33 @@ chipyard.verilator chipyard.riscv-embedded-gcc chipyard.riscv-linux-gcc - chipyard.mill + + # python environment + python.python3Packages # Bebop tools bebop.rustc bebop.cargo bebop.rustfmt bebop.clippy + + # Workflow dev tools + bbdev.nodejs + bbdev.gcc + bbdev.gnumake + bbdev.pkg-config + + # Scala tools + scala.mill + scala.scalafmt + scala.coursier + + # Documentation tools + doc.mdbook + doc.mdbook-linkcheck + doc.mdbook-pdf + doc.mdbook-toc + doc.mdbook-mermaid ]; }; @@ -41,17 +61,25 @@ shellHook = '' if [ -d "$PWD/result/bin" ]; then export PATH="$PWD/result/bin:$PATH" - echo "Activated environment" + echo "================= Buckyball Environment Activated =========================" else echo "Warning: result/bin not found. Run 'nix build' first." fi - echo "==========================================" + + export BUDDY_MLIR_BUILD_DIR="$PWD/compiler/build" + export LLVM_MLIR_BUILD_DIR="$PWD/compiler/llvm/build" + export PYTHONPATH="$PWD/compiler/llvm/build/tools/mlir/python_packages/mlir_core:$PWD/compiler/build/python_packages:$PYTHONPATH" + export PATH="$PWD/workflow:$PATH" + echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" echo "RISC-V Embedded GCC: $(riscv64-none-elf-gcc --version 2>&1 | head -1)" echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" echo "Mill: $(mill --version 2>&1 | head -1)" - echo "==========================================" + echo "Cargo: $(cargo --version 2>&1 | head -1)" + echo "npm: $(npm --version 2>&1 | head -1)" + echo "bbdev: $(which bbdev)" + echo "===========================================================================" ''; }; } diff --git a/scripts/docker/.dockerignore b/scripts/docker/.dockerignore deleted file mode 100644 index dd935bda..00000000 --- a/scripts/docker/.dockerignore +++ /dev/null @@ -1,60 +0,0 @@ -# Git -.git -.gitignore -.gitmodules - -# Docker -docker/ -Dockerfile* -docker-compose* - -# IDE -.vscode/ -.idea/ -*.swp -*.swo - -# OS -.DS_Store -Thumbs.db - -# Logs -*.log -logs/ - -# Runtime data -pids -*.pid -*.seed -*.pid.lock - -# Coverage directory used by tools like istanbul -coverage/ - -# Dependency directories -node_modules/ -jspm_packages/ - -# Optional npm cache directory -.npm - -# Optional REPL history -.node_repl_history - -# Output of 'npm pack' -*.tgz - -# Yarn Integrity file -.yarn-integrity - -# dotenv environment variables file -.env - -# Build outputs -dist/ -build/ -target/ - -# Temporary folders -tmp/ -temp/ diff --git a/scripts/docker/Dockerfile b/scripts/docker/Dockerfile deleted file mode 100644 index d149120f..00000000 --- a/scripts/docker/Dockerfile +++ /dev/null @@ -1,43 +0,0 @@ -FROM ubuntu:20.04 - -# Set environment variables -ENV DEBIAN_FRONTEND=noninteractive -ENV PYTHONUNBUFFERED=1 - -# Install system dependencies -RUN apt-get update && apt-get install -y \ - curl \ - wget \ - git \ - build-essential \ - python3 \ - python3-pip \ - python3-venv \ - nodejs \ - npm \ - openjdk-11-jdk \ - scala \ - && rm -rf /var/lib/apt/lists/* - -# Set working directory -WORKDIR /buckyball - -# Copy project files -COPY . /buckyball/ - -# Install Python dependencies (if requirements.txt exists) -# RUN if [ -f requirements.txt ]; then pip3 install -r requirements.txt; fi - -# Install Node.js dependencies (if package.json exists) -# RUN if [ -f package.json ]; then npm install; fi - -# Create a non-root user -RUN useradd -m -u 1000 bb && \ - chown -R bb:bb /buckyball -USER bb - -# Expose common development ports -EXPOSE 3000 8080 8000 - -# Set default command -CMD ["/bin/bash"] diff --git a/scripts/docker/README.md b/scripts/docker/README.md deleted file mode 100644 index 2e41b5d5..00000000 --- a/scripts/docker/README.md +++ /dev/null @@ -1,80 +0,0 @@ -# Buckyball Docker Environment - -This directory contains Docker configurations for running the Buckyball project. - -## File Description - -- `Dockerfile`: Main Docker image build file -- `docker-compose.yml`: Docker Compose configuration file for managing containers -- `.dockerignore`: Specifies which files should not be copied into the Docker container -- `README.md`: This documentation file - -## Environment Requirements - -- Docker Engine 20.10+ -- Docker Compose 2.0+ - -## Quick Start - -### 1. Build Image - -```bash -# Execute from project root directory -docker build -f docker/Dockerfile -t buckyball-dev . -``` - -### 2. Start Environment Using Docker Compose - -```bash -# Execute from docker directory -cd docker -docker-compose up -d -``` - -### 3. Enter Container - -```bash -# Enter running container -docker exec -it buckyball-dev bash -``` - -## Detailed Usage Instructions - -### Using Docker Compose - -1. **Start Environment**: -```bash -cd docker -docker-compose up -d -``` - -2. **Check Container Status**: -```bash -docker-compose ps -``` - -3. **Enter Container**: -```bash -docker-compose exec buckyball bash -``` - -4. **Stop Environment**: -```bash -docker-compose down -``` - -5. **Rebuild and Start**: -```bash -docker-compose up --build -d -``` - -## Common Issues - -1. When executing `docker-compose up -d`, the following error occurs: -``` -permission denied while trying to connect to the Docker daemon socket at unix:///var/run/docker.sock: Get "http://%2Fvar%2Frun%2Fdocker.sock/v1.45/containers/json?all=1&filters=%7B%22label%22%3A%7B%22com.docker.compose.config-hash%22%3Atrue%2C%22com.docker.compose.project%3Ddocker%22%3Atrue%7D%7D": dial unix /var/run/docker.sock: connect: permission denied -``` -Execute the following command and logout and login again: -``` -sudo usermod -aG docker $USER -``` diff --git a/scripts/docker/docker-compose.yml b/scripts/docker/docker-compose.yml deleted file mode 100644 index 1ef2681e..00000000 --- a/scripts/docker/docker-compose.yml +++ /dev/null @@ -1,20 +0,0 @@ -services: - buckyball: - build: - context: .. - dockerfile: docker/Dockerfile - container_name: bb-dev - volumes: - - ..:/buckyball - ports: - - "3000:3000" - - "8080:8080" - - "8000:8000" - environment: - - NODE_ENV=development - - PYTHONPATH=/buckyball - working_dir: /buckyball - stdin_open: true - tty: true - command: /bin/bash - image: buckyball:latest diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh new file mode 100644 index 00000000..5691303a --- /dev/null +++ b/scripts/nix/build-all.sh @@ -0,0 +1,176 @@ +#!/usr/bin/env bash + +# exit script if any command fails +set -e +set -o pipefail + +BBDIR=$(git rev-parse --show-toplevel) + +source ${BBDIR}/scripts/utils.sh + +usage() { + echo "Usage: ${0} [OPTIONS] " + echo "" + echo "Helper script to fully initialize repository that wraps other scripts." + echo "By default it initializes/installs things in the following order:" + echo " 1. Setup workflow management system" + echo " 2. Buckyball submodules" + echo " 3. Toolchain installation" + echo " 4. Compiler (buddy-mlir) pre-compile sources" + echo " 5. bb-tests (workloads) pre-compile sources" + echo " 6. Install Chipyard and Firesim" + echo " 7. Buckyball pre-compile sources" + echo " 8. Setup document management system" + echo " 9. Install func-sim" + echo " 10. Runs repository clean-up" + echo "" + echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" + echo "" + echo "Options" + echo " --help -h : Display this message" + echo " --verbose -v : Verbose printout" + echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')." + echo " --admin : Add this option to install the admin tools (You dont need do this)." + + exit "$1" +} + +SKIP_LIST=() +VERBOSE_FLAG="" +INSTALL_IN_NIX=0 + +while [ "$1" != "" ]; +do + case $1 in + -h | --help ) + usage 3 ;; + --verbose | -v) + VERBOSE_FLAG=$1 + set -x ;; + --skip | -s) + shift + SKIP_LIST+=(${1}) ;; + --install-in-nix) + INSTALL_IN_NIX=1 ;; + * ) + echo "Error: invalid option $1" >&2 + usage 1 ;; + esac + shift +done + +# return true if the arg is not found in the SKIP_LIST +run_step() { + local value=$1 + [[ ! " ${SKIP_LIST[*]} " =~ " ${value} " ]] +} + +function begin_step +{ + thisStepNum=$1; + thisStepDesc=$2; + + # Color codes + local BLUE='\033[0;34m' + local GREEN='\033[0;32m' + local YELLOW='\033[1;33m' + local NC='\033[0m' # No Color + + echo -e "${BLUE} =========================================================================" + echo -e "${GREEN} ==== BUCKYBALL SETUP STEP ${YELLOW}$thisStepNum${GREEN}: ${YELLOW}$thisStepDesc${GREEN} " + echo -e "${BLUE} =========================================================================" + echo -e "${NC}" +} + +begin_step "0-1" "submodules init" +git submodule update --init + +begin_step "0-2" "Nix environment setup" +cd ${BBDIR} +nix build + +if [ "${INSTALL_IN_NIX}" = "0" ]; then + SKIP_ARGS="" + for skip in "${SKIP_LIST[@]}"; do + SKIP_ARGS="${SKIP_ARGS} -s ${skip}" + done + exec nix develop --command bash ${BBDIR}/scripts/nix/build-all.sh --install-in-nix ${SKIP_ARGS} ${VERBOSE_FLAG} +fi + +if run_step "1"; then + begin_step "1" "Compiler (buddy-mlir) pre-compile sources" + cd ${BBDIR}/compiler + git submodule update --init llvm + + mkdir -p llvm/build && cd llvm/build + cmake -G Ninja ../llvm \ + -DLLVM_ENABLE_PROJECTS="mlir;clang" \ + -DLLVM_TARGETS_TO_BUILD="host;RISCV" \ + -DLLVM_ENABLE_ASSERTIONS=ON \ + -DCMAKE_BUILD_TYPE=RELEASE \ + -DMLIR_ENABLE_BINDINGS_PYTHON=ON \ + -DPython3_EXECUTABLE=$(which python3) + ninja #check-mlir check-clang + + cd ${BBDIR}/compiler + mkdir -p build && cd build + cmake -G Ninja .. \ + -DMLIR_DIR=$PWD/../llvm/build/lib/cmake/mlir \ + -DLLVM_DIR=$PWD/../llvm/build/lib/cmake/llvm \ + -DLLVM_ENABLE_ASSERTIONS=ON \ + -DCMAKE_BUILD_TYPE=RELEASE \ + -DBUDDY_MLIR_ENABLE_PYTHON_PACKAGES=ON \ + -DPython3_EXECUTABLE=$(which python3) \ + -DPython_EXECUTABLE=$(which python3) \ + -DCMAKE_EXPORT_COMPILE_COMMANDS=ON + ninja + #ninja check-buddy +fi + +if run_step "2"; then + begin_step "2" "Install bebop" + # ${BBDIR}/scripts/install-bebop.sh + echo "bebop is not installed" +fi + +if run_step "3"; then + begin_step "3" "bb-tests (workloads) pre-compile sources" + cd ${BBDIR}/bb-tests + mkdir -p build && cd build + cmake -G Ninja ../ + ninja -j$(nproc) +fi + +if run_step "4"; then + begin_step "4" "Install requirements for sardine" + npm install --prefix ${BBDIR}/bb-tests/sardine allure-commandline +fi + + +if run_step "5"; then + begin_step "5" "Install document management system" + mdbook-mermaid install ${BBDIR}/docs/bb-note/ +fi + +if run_step "6"; then + begin_step "6" "Init workflow management system" + cd ${BBDIR}/workflow + export USE_SYSTEMD=no + npm init -y + npm install motia@0.13.0-beta.161 + npx motia create -t python + + cd ${BBDIR}/workflow/steps && rm *.{py,json} || true + cd ${BBDIR}/workflow/steps && rm -r src/ || true + cd ${BBDIR}/workflow/steps && rm -r petstore/ || true + cd ${BBDIR}/workflow && rm -r src/ || true + cd ${BBDIR}/workflow && rm -r tutorial/ || true + cd ${BBDIR}/workflow && rm *.{md,tsx,rdb} || true +fi + +if run_step "9"; then + begin_step "9" "Install pre-commit hooks" + pre-commit install +fi + +begin_step "END" "Setup completed successfully!" diff --git a/scripts/nix/build-env-bbdev.nix b/scripts/nix/build-env-bbdev.nix new file mode 100644 index 00000000..bf470b70 --- /dev/null +++ b/scripts/nix/build-env-bbdev.nix @@ -0,0 +1,15 @@ +{ pkgs }: + +{ + # Node.js environment + nodejs = pkgs.nodejs_20; + npm = pkgs.nodejs_20; + + # Build tools (for compiling native modules) + gcc = pkgs.gcc; + gnumake = pkgs.gnumake; + pkg-config = pkgs.pkg-config; + + # System dependencies + systemd = pkgs.systemd; +} diff --git a/scripts/nix/build-bebop.nix b/scripts/nix/build-env-bebop.nix similarity index 100% rename from scripts/nix/build-bebop.nix rename to scripts/nix/build-env-bebop.nix diff --git a/scripts/nix/build-chipyard.nix b/scripts/nix/build-env-chipyard.nix similarity index 84% rename from scripts/nix/build-chipyard.nix rename to scripts/nix/build-env-chipyard.nix index 438b329c..468411d5 100644 --- a/scripts/nix/build-chipyard.nix +++ b/scripts/nix/build-env-chipyard.nix @@ -10,6 +10,5 @@ # RISC-V Linux toolchain riscv-linux-gcc = pkgs.pkgsCross.riscv64.buildPackages.gcc; - # Build tool for Scala, Java and more - mill = pkgs.mill; + } diff --git a/scripts/nix/build-env-doc.nix b/scripts/nix/build-env-doc.nix new file mode 100644 index 00000000..02799b16 --- /dev/null +++ b/scripts/nix/build-env-doc.nix @@ -0,0 +1,12 @@ +{ pkgs }: + +{ + # Rust documentation generator + mdbook = pkgs.mdbook; + + # mdbook plugins + mdbook-linkcheck = pkgs.mdbook-linkcheck; + mdbook-pdf = pkgs.mdbook-pdf; + mdbook-toc = pkgs.mdbook-toc; + mdbook-mermaid = pkgs.mdbook-mermaid; +} diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix new file mode 100644 index 00000000..0c7feec6 --- /dev/null +++ b/scripts/nix/build-env-python.nix @@ -0,0 +1,48 @@ +{ pkgs }: + +{ + # Python and pip packages + python3 = pkgs.python3; + + # Python packages + python3Packages = pkgs.python3.withPackages (ps: with ps; [ + # bbdev + python-dotenv + httpx + mcp + redis + httpx-sse + requests + + # pre-commit hooks + pre-commit-hooks + + # compiler + torch + numpy + transformers + tokenizers + sentencepiece + accelerate + protobuf + pybind11 + torchvision + tabulate + datasets + soundfile + librosa + pyyaml + certifi + idna + diffusers + nanobind + + # testing (sardine) + pytest + pytest-html + pytest-xdist + pytest-cov + allure-pytest + colorlog + ]); +} diff --git a/scripts/nix/build-env-scala.nix b/scripts/nix/build-env-scala.nix new file mode 100644 index 00000000..6d27ee67 --- /dev/null +++ b/scripts/nix/build-env-scala.nix @@ -0,0 +1,12 @@ +{ pkgs }: + +{ + # Build tool for Scala, Java and more + mill = pkgs.mill; + + # Scala formatter + scalafmt = pkgs.scalafmt; + + # Coursier - Scala dependency manager and launcher + coursier = pkgs.coursier; +} diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 767b8eee..60aa6f80 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -1,5 +1,9 @@ final: prev: { - chipyard = final.callPackage ./build-chipyard.nix { }; - bebop = final.callPackage ./build-bebop.nix { }; + chipyard = final.callPackage ./build-env-chipyard.nix { }; + bebop = final.callPackage ./build-env-bebop.nix { }; + bbdev = final.callPackage ./build-env-bbdev.nix { }; + python = final.callPackage ./build-env-python.nix { }; + scala = final.callPackage ./build-env-scala.nix { }; + doc = final.callPackage ./build-env-doc.nix { }; } diff --git a/workflow/.gitignore b/workflow/.gitignore index 37fafeda..ddc6dc3c 100644 --- a/workflow/.gitignore +++ b/workflow/.gitignore @@ -8,8 +8,8 @@ dist *.pyc *.json motia-workbench.json -package-lock.json -package.json +# package-lock.json +# package.json types.d.ts appendonlydir/ dump.rdb diff --git a/workflow/package-lock.json b/workflow/package-lock.json new file mode 100644 index 00000000..6e6666bc --- /dev/null +++ b/workflow/package-lock.json @@ -0,0 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"generate-types": "motia generate-types", + "build": "motia build", + "clean": "rm -rf dist node_modules python_modules .motia .mermaid" + }, + "keywords": [ + "motia" + ], + "dependencies": { + "@motiadev/core": "^0.13.0", + "@motiadev/plugin-endpoint": "^0.13.0", + "@motiadev/plugin-logs": "^0.13.0", + "@motiadev/plugin-observability": "^0.13.0", + "@motiadev/plugin-states": "^0.13.0", + "motia": "^0.13.0", + "zod": "^4.1.12" + }, + "devDependencies": { + "@types/react": "^19.1.1", + "ts-node": "^10.9.2", + "typescript": "^5.7.3" + } +} From 97255b50ad7412de6e13419c79720bbd5d9d0330 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Feb 2026 05:36:40 +0800 Subject: [PATCH 075/238] [nix] fix: fix bugs in build-all.sh --- README.md | 2 +- flake.nix | 2 +- scripts/nix/build-all.sh | 28 +++++++++++---------------- scripts/nix/build-env-chipyard.nix | 31 ++++++++++++++++++++++++++---- 4 files changed, 40 insertions(+), 23 deletions(-) mode change 100644 => 100755 scripts/nix/build-all.sh diff --git a/README.md b/README.md index 8919f939..b797938d 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,7 @@ cd buckyball ./scripts/nix/build-all.sh ``` -After this one-time installation, you can enter the environment anytime by running: +After the first time installation, you can enter the environment anytime by running: ```bash nix develop ``` diff --git a/flake.nix b/flake.nix index 0bfadc4f..65dfbd6f 100644 --- a/flake.nix +++ b/flake.nix @@ -73,7 +73,7 @@ echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" - echo "RISC-V Embedded GCC: $(riscv64-none-elf-gcc --version 2>&1 | head -1)" + echo "RISC-V Embedded GCC: $(riscv64-unknown-elf-gcc --version 2>&1 | head -1)" echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" echo "Mill: $(mill --version 2>&1 | head -1)" echo "Cargo: $(cargo --version 2>&1 | head -1)" diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh old mode 100644 new mode 100755 index 5691303a..dad70ea2 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -13,16 +13,11 @@ usage() { echo "" echo "Helper script to fully initialize repository that wraps other scripts." echo "By default it initializes/installs things in the following order:" - echo " 1. Setup workflow management system" - echo " 2. Buckyball submodules" - echo " 3. Toolchain installation" - echo " 4. Compiler (buddy-mlir) pre-compile sources" - echo " 5. bb-tests (workloads) pre-compile sources" - echo " 6. Install Chipyard and Firesim" - echo " 7. Buckyball pre-compile sources" - echo " 8. Setup document management system" - echo " 9. Install func-sim" - echo " 10. Runs repository clean-up" + echo " 1. Compiler (buddy-mlir) pre-compile sources" + echo " 2. bb-tests (workloads) pre-compile sources" + echo " 3. Install document management system" + echo " 4. Install workflow management system" + echo " 5. Install pre-commit hooks" echo "" echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" echo "" @@ -30,7 +25,6 @@ usage() { echo " --help -h : Display this message" echo " --verbose -v : Verbose printout" echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')." - echo " --admin : Add this option to install the admin tools (You dont need do this)." exit "$1" } @@ -84,6 +78,7 @@ function begin_step begin_step "0-1" "submodules init" git submodule update --init +cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init begin_step "0-2" "Nix environment setup" cd ${BBDIR} @@ -123,8 +118,7 @@ if run_step "1"; then -DPython3_EXECUTABLE=$(which python3) \ -DPython_EXECUTABLE=$(which python3) \ -DCMAKE_EXPORT_COMPILE_COMMANDS=ON - ninja - #ninja check-buddy + ninja # check-buddy fi if run_step "2"; then @@ -137,8 +131,8 @@ if run_step "3"; then begin_step "3" "bb-tests (workloads) pre-compile sources" cd ${BBDIR}/bb-tests mkdir -p build && cd build - cmake -G Ninja ../ - ninja -j$(nproc) + cmake -G Ninja .. + ninja fi if run_step "4"; then @@ -168,8 +162,8 @@ if run_step "6"; then cd ${BBDIR}/workflow && rm *.{md,tsx,rdb} || true fi -if run_step "9"; then - begin_step "9" "Install pre-commit hooks" +if run_step "7"; then + begin_step "7" "Install pre-commit hooks" pre-commit install fi diff --git a/scripts/nix/build-env-chipyard.nix b/scripts/nix/build-env-chipyard.nix index 468411d5..573066fb 100644 --- a/scripts/nix/build-env-chipyard.nix +++ b/scripts/nix/build-env-chipyard.nix @@ -4,11 +4,34 @@ # Fast and robust (System)Verilog simulator/compiler and linter verilator = pkgs.verilator; - # RISC-V embedded toolchain (bare metal) - riscv-embedded-gcc = pkgs.pkgsCross.riscv64-embedded.buildPackages.gcc; + # RISC-V embedded toolchain (bare metal), with riscv64-unknown-elf-* symlinks + riscv-embedded-gcc = pkgs.symlinkJoin { + name = "riscv64-unknown-elf-gcc"; + paths = [ pkgs.pkgsCross.riscv64-embedded.buildPackages.gcc ]; + postBuild = '' + cd $out/bin + for f in riscv64-none-elf-*; do + [ -e "$f" ] || continue + newname=''${f/riscv64-none-elf/riscv64-unknown-elf} + ln -sf "$f" "$newname" + done + ''; + }; - # RISC-V Linux toolchain - riscv-linux-gcc = pkgs.pkgsCross.riscv64.buildPackages.gcc; + # RISC-V Linux toolchain (full stdenv.cc with static libc for -static linking) + riscv-linux-gcc = let + cc = pkgs.pkgsCross.riscv64.stdenv.cc; + libcStatic = pkgs.pkgsCross.riscv64.stdenv.cc.libc.static; + in pkgs.runCommand "riscv64-linux-gnu-toolchain" {} '' + mkdir -p $out/bin + for f in ${cc}/bin/riscv64-unknown-linux-gnu-*; do + [ -e "$f" ] || continue + name=$(basename "$f") + echo '#!${pkgs.stdenv.shell}' > $out/bin/$name + echo 'exec "'"$f"'" -L${libcStatic}/lib "$@"' >> $out/bin/$name + chmod +x $out/bin/$name + done + ''; } From 1065605fefa1e73a20cf29dee2c58984318f76f4 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 3 Feb 2026 15:14:27 +0800 Subject: [PATCH 076/238] [arch]fix: fix bugs of bankwriting in memdomain --- .../memdomain/backend/MemBackend.scala | 58 +++++---- .../memdomain/backend/accpipe/AccPipe.scala | 7 +- .../frontend/outside_channel/MemLoader.scala | 116 ++++++++++-------- .../memdomain/midend/MemMidend.scala | 4 +- 4 files changed, 107 insertions(+), 78 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 8ef52c0b..964f02ac 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -119,38 +119,54 @@ class MemBackend(val b: GlobalConfig) extends Module { // - select at most one read requester (Mux1H) // - connect bank <-> selected accPipe using the per-pipe wires // ----------------------------------------------------------------------------- - banks.zipWithIndex.foreach { + banks.zipWithIndex.foreach { case (bank, bankIdx) => val bankId = bankIdx.U(log2Up(b.memDomain.bankNum).W) - // ------------------------- - // WRITE routing - // ------------------------- + // ========================================================= + // WRITE routing (req: combinational; resp: owner-registered) + // ========================================================= val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) for (i <- 0 until b.memDomain.bankChannel) { - wMatch(i) := io.mem_req(i).bank_id === bankId && io.mem_req(i).write.req.valid + wMatch(i) := (accPipes(i).io.target_bank_id === bankId) && + accPipes(i).io.sramWrite.req.valid } - val wHas = wMatch.asUInt.orR - // stronger safety: at most 1 + val wHas = wMatch.asUInt.orR + val wSel = OHToUInt(wMatch) assert(PopCount(wMatch) <= 1.U, s"[MemBackend] More than one WRITE match to bank $bankIdx") + // owner regs for write resp + val wOwnerValid = RegInit(false.B) + val wOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) + + // default bank write req + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) + + // issue req from selected pipe when(wHas) { - val selIdx = OHToUInt(wMatch) - // bank gets req from selected pipe using Mux1H - bank.io.sramWrite.req.valid := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.valid)) + bank.io.sramWrite.req.valid := true.B bank.io.sramWrite.req.bits := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.bits)) - // selected pipe sees ready from bank - wr_req_ready(selIdx) := bank.io.sramWrite.req.ready + // ready to selected pipe + wr_req_ready(wSel) := bank.io.sramWrite.req.ready - // response path: selected pipe sees bank resp - wr_resp_valid(selIdx) := bank.io.sramWrite.resp.valid - wr_resp_ok(selIdx) := bank.io.sramWrite.resp.bits.ok - // bank sees ready from selected pipe - bank.io.sramWrite.resp.ready := wr_resp_ready(selIdx) - }.otherwise { - bank.io.sramWrite.req.valid := false.B - bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) - bank.io.sramWrite.resp.ready := false.B + when(bank.io.sramWrite.req.fire) { + wOwnerValid := true.B + wOwnerIdx := wSel + } + } + + // resp routes by owner (NOT by wHas) + // drive selected pipe resp wires + when(wOwnerValid) { + wr_resp_valid(wOwnerIdx) := bank.io.sramWrite.resp.valid + wr_resp_ok(wOwnerIdx) := bank.io.sramWrite.resp.bits.ok + } + // ready from owner pipe + bank.io.sramWrite.resp.ready := Mux(wOwnerValid, wr_resp_ready(wOwnerIdx), false.B) + + when(bank.io.sramWrite.resp.fire && wOwnerValid) { + wOwnerValid := false.B } // ------------------------- diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index cca39372..36ac7d77 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -60,9 +60,8 @@ class AccPipe(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- // FSM // --------------------------------------------------------------------------- - val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = - Enum(5) - val state = RegInit(s_idle) + val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = Enum(5) + val state = RegInit(s_idle) io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) @@ -99,7 +98,7 @@ class AccPipe(val b: GlobalConfig) extends Module { val segW = b.memDomain.bankWidth / b.memDomain.bankMaskLen // Optional safety: if not divisible, elaboration will still succeed but behavior is wrong. // You can assert if you want: - // require(b.memDomain.bankWidth % b.memDomain.bankMaskLen == 0, "bankWidth must be divisible by bankMaskLen") + require(b.memDomain.bankWidth % b.memDomain.bankMaskLen == 0, "bankWidth must be divisible by bankMaskLen") val oldVec = oldU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) val addVec = addU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index a865cfec..2df5f4e2 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -16,38 +16,69 @@ class MemLoader(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - // Load instruction from ReservationStation val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) - // Completion signal sent to ReservationStation val cmdResp = Decoupled(new MemRsComplete(b)) - // Direct connection to DMA read interface + val dmaReq = Decoupled(new BBReadRequest()) val dmaResp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) - // Connected to Bank write interface val bankWrite = Flipped(new BankWrite(b)) - }) val s_idle :: s_dma_req :: s_dma_wait :: Nil = Enum(3) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) - // Cache mem_addr val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) - // Cache iteration count val iter_reg = Reg(UInt(10.W)) - // Count number of responses received, supports up to 16 responses - val resp_count = Reg(UInt(log2Up(16).W)) + val resp_count = RegInit(0.U(log2Up(16).W)) + val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) + val stride_reg = Reg(UInt(10.W)) + + // ----------------------------- + // pending latch for 1-beat DMA -> bankWrite + // ----------------------------- + val pending = RegInit(false.B) + val latRow = Reg(UInt(log2Up(b.memDomain.bankEntries).W)) + val latData = Reg(UInt(b.memDomain.bankWidth.W)) + val latLast = RegInit(false.B) + + // ----------------------------- + // defaults + // ----------------------------- + io.cmdReq.ready := (state === s_idle) + + io.dmaReq.valid := (state === s_dma_req) + io.dmaReq.bits.vaddr := mem_addr_reg + io.dmaReq.bits.len := iter_reg * (b.memDomain.bankWidth / 8).U + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + io.dmaReq.bits.stride := stride_reg - // Cache decoded bank information - val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - // Cache stride - val stride_reg = Reg(UInt(10.W)) + // only accept DMA beat when waiting AND no pending beat buffered + io.dmaResp.ready := (state === s_dma_wait) && !pending - // Receive load instruction - io.cmdReq.ready := state === s_idle + // bank write request driven from pending + io.bankWrite.io.req.valid := pending + io.bankWrite.io.req.bits.addr := latRow + io.bankWrite.io.req.bits.data := latData + io.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + io.bankWrite.io.req.bits.wmode := false.B + + // IMPORTANT: always ready for write response (avoid deadlock) + io.bankWrite.io.resp.ready := true.B + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := wr_bank_reg + io.bankWrite.ball_id := 0.U + + // cmdResp defaults + io.cmdResp.valid := false.B + io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) + io.cmdResp.bits.rob_id := rob_id_reg + + // ----------------------------- + // Receive load instruction + // ----------------------------- when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { state := s_dma_req rob_id_reg := io.cmdReq.bits.rob_id @@ -56,50 +87,33 @@ class MemLoader(val b: GlobalConfig) extends Module { wr_bank_reg := io.cmdReq.bits.cmd.bank_id stride_reg := io.cmdReq.bits.cmd.special(10, 0) resp_count := 0.U + pending := false.B + latLast := false.B } - // Issue DMA read request - read iter_reg rows of data - io.dmaReq.valid := state === s_dma_req - io.dmaReq.bits.vaddr := mem_addr_reg - // Byte count of iter rows of data - io.dmaReq.bits.len := iter_reg * (b.memDomain.bankWidth / 8).U - // Simplified: use default status - io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) - io.dmaReq.bits.stride := stride_reg - + // DMA req accepted when(io.dmaReq.fire) { - state := s_dma_wait - // Reset response counter + state := s_dma_wait resp_count := 0.U } - // Wait for DMA response - io.dmaResp.ready := state === s_dma_wait - + // Latch DMA beat into pending buffer when(io.dmaResp.fire) { + pending := true.B + latRow := io.dmaResp.bits.addrcounter + latData := io.dmaResp.bits.data + latLast := io.dmaResp.bits.last + } + + // When bankWrite request handshakes, consume pending beat + when(io.bankWrite.io.req.fire) { + pending := false.B resp_count := resp_count + 1.U - // Return to idle state when last response is received - when(io.dmaResp.bits.last) { + + when(latLast) { + // command complete only when last beat has been accepted by bank write state := s_idle + io.cmdResp.valid := true.B } } - - // Stream write to SRAM - write immediately upon receiving each response - // All responses write to the same bank, starting from row 0 - val target_bank = wr_bank_reg - val target_row = io.dmaResp.bits.addrcounter - - io.bankWrite.io.req.valid := io.dmaResp.fire && (target_bank === target_bank) - io.bankWrite.io.req.bits.addr := target_row - io.bankWrite.io.req.bits.data := io.dmaResp.bits.data - io.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - io.bankWrite.io.req.bits.wmode := false.B - io.bankWrite.io.resp.ready := false.B - io.bankWrite.rob_id := rob_id_reg - io.bankWrite.bank_id := target_bank - io.bankWrite.ball_id := 0.U - - // Send completion signal - only send when last response is received - io.cmdResp.valid := io.dmaResp.fire && io.dmaResp.bits.last - io.cmdResp.bits.rob_id := rob_id_reg } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 65ee435d..ad59b642 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -126,10 +126,10 @@ class MemMidend(val b: GlobalConfig) extends Module { //Default values io.mem_req(i).read.req.valid := false.B io.mem_req(i).read.req.bits := DontCare - io.mem_req(i).read.resp.ready := false.B + io.mem_req(i).read.resp.ready := true.B io.mem_req(i).write.req.valid := false.B io.mem_req(i).write.req.bits := DontCare - io.mem_req(i).write.resp.ready := false.B + io.mem_req(i).write.resp.ready := true.B io.mem_req(i).bank_id := 0.U val entry = mappingTable(i) From c18a8fca21cdca285f409f43d2ef3b8c168e8715 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 3 Feb 2026 15:55:04 +0800 Subject: [PATCH 077/238] [arch]fix: fix bugs of error addr from dma --- .../outside_channel/dma/StreamReader.scala | 107 ++++++++---------- 1 file changed, 45 insertions(+), 62 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index 56c755db..db82905e 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -2,10 +2,9 @@ package framework.memdomain.frontend.outside_channel.dma import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.{MStatus, M_XRD} -import freechips.rocketchip.rocket.constants.MemoryOpConstants import framework.builtin.utils.Util._ import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO @@ -21,7 +20,7 @@ class BBReadRequest extends Bundle { class BBReadResponse(dataWidth: Int) extends Bundle { val data = UInt(dataWidth.W) val last = Bool() - val addrcounter = UInt(10.W) + val addrcounter = UInt(10.W) // will be beat index: 0,1,2,... } @instantiable @@ -40,31 +39,25 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tlb = Flipped(new BBTLBIO(b)) val busy = Output(Bool()) val flush = Input(Bool()) - // TileLink physical connection val tl = new TLBundle(edge.bundle) }) val s_idle :: s_req_new_block :: Nil = Enum(2) - val state = RegInit(s_idle) + val state = RegInit(s_idle) - val req = Reg(new BBReadRequest()) - // Number of bytes requested - val bytesRequested = Reg(UInt(16.W)) - // Number of bytes received - val bytesReceived = Reg(UInt(16.W)) - val bytesLeft = req.len - bytesRequested + val req = Reg(new BBReadRequest()) + + // Number of bytes requested (A sent) + val bytesRequested = RegInit(0.U(16.W)) + // Number of bytes received (D accepted) + val bytesReceived = RegInit(0.U(16.W)) + + val bytesLeft = req.len - bytesRequested // Select request size - simplified version, fixed use of beatBytes val read_size = minOf(beatBytes.U, bytesLeft) val read_vaddr = req.vaddr + bytesRequested * req.stride - // Track byte range corresponding to each request for correct last signal calculation - // Starting byte position of current request - val req_byte_start = Reg(UInt(16.W)) - // Ending byte position of current request - val req_byte_end = Wire(UInt(16.W)) - req_byte_end := req_byte_start + read_size - // Transaction ID management val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) @@ -75,15 +68,14 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val xactBusy_remove = ~Mux(io.tl.d.fire, (1.U << io.tl.d.bits.source).asUInt, 0.U) xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt - // TileLink request construction - return to single beat requests to avoid address alignment issues + // TileLink request construction - single beat val get = edge.Get( fromSource = xactId, - toAddress = 0.U, - // Request only one beat each time - lgSize = log2Ceil(beatBytes).U + toAddress = 0.U, + lgSize = log2Ceil(beatBytes).U )._2 - // TLB processing pipeline - simplified based on Gemmini + // TLB processing pipeline class TLBundleAWithInfo extends Bundle { val tl_a = get.cloneType val vaddr = Output(UInt(vaddrBits.W)) @@ -97,55 +89,48 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { untranslated_a.bits.vaddr := read_vaddr untranslated_a.bits.status := req.status - // Simplified: no retry mechanism, direct connection + // 1-deep queue to break comb paths val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) tlb_q.io.enq <> untranslated_a io.tlb.req.valid := tlb_q.io.deq.valid && (state === s_req_new_block) io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.passthrough := true.B //use paddr for now + io.tlb.req.bits.passthrough := true.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XRD - io.tlb.req.bits.prv := 3.U // Machine mode + io.tlb.req.bits.prv := 3.U io.tlb.req.bits.v := false.B io.tlb.req.bits.status := tlb_q.io.deq.bits.status - tlb_q.io.deq.ready := io.tlb.resp.valid; + // consume tlb_q when tlb resp valid + tlb_q.io.deq.ready := io.tlb.resp.valid - /* val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) translate_q.io.enq <> tlb_q.io.deq - * translate_q.io.deq.ready := io.tlb.resp.fire && !io.tlb.resp.bits.miss */ - - // TileLink A channel (request) connection - //for now, we just use the vaddr as the physical address to simplify the implementation + // TileLink A channel io.tl.a.valid := io.tlb.resp.valid && (state === s_req_new_block) io.tl.a.bits := tlb_q.io.deq.bits.tl_a io.tl.a.bits.address := io.tlb.resp.bits.paddr - io.tlb.resp.ready := true.B; + io.tlb.resp.ready := true.B - // Iteration counter for tracking number of requests - val iter_counter = RegInit(0.U(10.W)) - // Table for managing iteration counts - val iter_mangage_table = RegInit(VecInit(Seq.fill(16)(0.U(10.W)))) - // Iteration count management - update after each request - when(io.tl.a.fire) { - iter_counter := iter_counter + 1.U - iter_mangage_table(xactId) := iter_counter - } - - // TileLink D channel (response) processing + // ----------------------------- + // D channel -> resp + // ----------------------------- + // Backpressure from resp to TileLink D io.tl.d.ready := io.resp.ready - io.resp.valid := io.tl.d.valid - io.resp.bits.data := io.tl.d.bits.data - // Use source as address counter - io.resp.bits.addrcounter := iter_mangage_table(io.tl.d.bits.source) - // Fix last signal: calculate using received byte count - // Total byte count after receiving current beat + io.resp.valid := io.tl.d.valid + io.resp.bits.data := io.tl.d.bits.data + + // ✅ FIX: addrcounter = beat index in receive order (0,1,2,...) + // Current beat index before consuming this beat: + val beatIndex = (bytesReceived >> log2Ceil(beatBytes)).asUInt + io.resp.bits.addrcounter := beatIndex(9, 0) + + // last flag based on total bytes after this beat val resp_bytes_end = bytesReceived + beatBytes.U io.resp.bits.last := io.tl.d.valid && (resp_bytes_end >= req.len) - // Update received byte count + // Update received bytes when we actually accept a beat when(io.tl.d.fire) { bytesReceived := bytesReceived + beatBytes.U } @@ -155,29 +140,27 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl.c.valid := false.B io.tl.e.valid := false.B + // ----------------------------- // State machine - io.req.ready := state === s_idle + // ----------------------------- + io.req.ready := (state === s_idle) io.busy := xactBusy.orR || (state =/= s_idle) when(io.req.fire) { req := io.req.bits bytesRequested := 0.U - // Reset received byte count bytesReceived := 0.U - // Reset iteration counter - iter_counter := 0.U state := s_req_new_block } - when(untranslated_a.fire) { - // Use actual requested byte count - bytesRequested := bytesRequested + read_size - // Check if more requests need to be sent - when(bytesRequested >= req.len) { - // All requests sent + // IMPORTANT: bytesRequested should advance only when A actually fires + when(io.tl.a.fire) { + val nextBytesRequested = bytesRequested + read_size + bytesRequested := nextBytesRequested + + when(nextBytesRequested >= req.len) { state := s_idle }.otherwise { - // Continue sending next request state := s_req_new_block } } From c6f78047dfb63996c4666ea74ddee5ee5a032c81 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Tue, 3 Feb 2026 18:26:38 +0800 Subject: [PATCH 078/238] [arch] Fix read request bug --- .../main/scala/examples/toy/ToyBuckyBall.scala | 2 +- .../framework/memdomain/backend/MemBackend.scala | 16 ++++++++-------- .../memdomain/backend/accpipe/AccPipe.scala | 4 ++-- .../frontend/outside_channel/MemLoader.scala | 12 ++++++------ .../framework/memdomain/midend/MemMidend.scala | 4 ++-- 5 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index a515b214..3269a995 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -114,7 +114,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready - val bankReadReqQ = Queue(bankReadReqWithIds, 1) + val bankReadReqQ = Queue(bankReadReqWithIds, 8) memDomain.io.ballDomain.bankRead(i).io.req.valid := bankReadReqQ.valid memDomain.io.ballDomain.bankRead(i).io.req.bits := bankReadReqQ.bits.req diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 964f02ac..11ec5400 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -119,7 +119,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // - select at most one read requester (Mux1H) // - connect bank <-> selected accPipe using the per-pipe wires // ----------------------------------------------------------------------------- - banks.zipWithIndex.foreach { + banks.zipWithIndex.foreach { case (bank, bankIdx) => val bankId = bankIdx.U(log2Up(b.memDomain.bankNum).W) @@ -129,10 +129,10 @@ class MemBackend(val b: GlobalConfig) extends Module { val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) for (i <- 0 until b.memDomain.bankChannel) { wMatch(i) := (accPipes(i).io.target_bank_id === bankId) && - accPipes(i).io.sramWrite.req.valid + accPipes(i).io.sramWrite.req.valid } - val wHas = wMatch.asUInt.orR - val wSel = OHToUInt(wMatch) + val wHas = wMatch.asUInt.orR + val wSel = OHToUInt(wMatch) assert(PopCount(wMatch) <= 1.U, s"[MemBackend] More than one WRITE match to bank $bankIdx") // owner regs for write resp @@ -181,15 +181,15 @@ class MemBackend(val b: GlobalConfig) extends Module { val selIdx = OHToUInt(rMatch) val connectIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) - connectIdx := selIdx - + connectIdx := selIdx + // selected pipe sees ready from bank + rd_req_ready(selIdx) := bank.io.sramRead.req.ready when(rHas) { // bank gets req from selected pipe using Mux1H bank.io.sramRead.req.valid := io.mem_req(selIdx).bank_id === bankId bank.io.sramRead.req.bits := io.mem_req(selIdx).read.req.bits - // selected pipe sees ready from bank - rd_req_ready(selIdx) := bank.io.sramRead.req.ready + }.otherwise { bank.io.sramRead.req.valid := false.B bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 36ac7d77..e8bf05eb 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -61,7 +61,7 @@ class AccPipe(val b: GlobalConfig) extends Module { // FSM // --------------------------------------------------------------------------- val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = Enum(5) - val state = RegInit(s_idle) + val state = RegInit(s_idle) io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) @@ -110,6 +110,7 @@ class AccPipe(val b: GlobalConfig) extends Module { resVec.asUInt } + io.read.req.ready := io.sramRead.req.ready // --------------------------------------------------------------------------- // FSM behavior // --------------------------------------------------------------------------- @@ -138,7 +139,6 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramRead.req.ready, Mux(writeDirect, io.sramWrite.req.ready, false.B) ) - io.read.req.ready := readValid && io.sramRead.req.ready // State transitions + latching on fire when(writeAccum && io.sramRead.req.fire) { diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 2df5f4e2..236a7922 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -26,7 +26,7 @@ class MemLoader(val b: GlobalConfig) extends Module { }) val s_idle :: s_dma_req :: s_dma_wait :: Nil = Enum(3) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) @@ -72,8 +72,8 @@ class MemLoader(val b: GlobalConfig) extends Module { io.bankWrite.ball_id := 0.U // cmdResp defaults - io.cmdResp.valid := false.B - io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) + io.cmdResp.valid := false.B + io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) io.cmdResp.bits.rob_id := rob_id_reg // ----------------------------- @@ -93,7 +93,7 @@ class MemLoader(val b: GlobalConfig) extends Module { // DMA req accepted when(io.dmaReq.fire) { - state := s_dma_wait + state := s_dma_wait resp_count := 0.U } @@ -107,12 +107,12 @@ class MemLoader(val b: GlobalConfig) extends Module { // When bankWrite request handshakes, consume pending beat when(io.bankWrite.io.req.fire) { - pending := false.B + pending := false.B resp_count := resp_count + 1.U when(latLast) { // command complete only when last beat has been accepted by bank write - state := s_idle + state := s_idle io.cmdResp.valid := true.B } } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index ad59b642..693718c7 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -67,7 +67,7 @@ class MemMidend(val b: GlobalConfig) extends Module { // Collect read requests for (i <- 0 until totalBallRead) { // Default value - io.balldomain.bankRead(i).io.req.ready := false.B + io.balldomain.bankRead(i).io.req.ready := !mappingTable.map(_.valid).reduce(_ || _) io.balldomain.bankRead(i).io.resp.valid := false.B io.balldomain.bankRead(i).io.resp.bits := DontCare @@ -81,7 +81,7 @@ class MemMidend(val b: GlobalConfig) extends Module { // Collect write requests for (i <- 0 until totalBallWrite) { - io.balldomain.bankWrite(i).io.req.ready := false.B + io.balldomain.bankWrite(i).io.req.ready := !mappingTable.map(_.valid).reduce(_ || _) io.balldomain.bankWrite(i).io.resp.valid := false.B io.balldomain.bankWrite(i).io.resp.bits := DontCare From 434e84b77dbad0f7bc7973293e3d4b095f8d2bca Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Tue, 3 Feb 2026 21:20:07 +0800 Subject: [PATCH 079/238] [arch]fix:fix some bugs of bankreading in memdomain --- .../memdomain/backend/MemBackend.scala | 75 +++++++++---------- .../memdomain/midend/MemMidend.scala | 4 +- 2 files changed, 37 insertions(+), 42 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 11ec5400..235af873 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -169,56 +169,49 @@ class MemBackend(val b: GlobalConfig) extends Module { wOwnerValid := false.B } - // ------------------------- - // READ routing - // ------------------------- + // ========================================================= + // READ routing (req: combinational; resp: owner-registered) + // ========================================================= val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) + // owner regs for read resp + val rOwnerValid = RegInit(false.B) + val rOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) + val canAcceptRead = !rOwnerValid for (i <- 0 until b.memDomain.bankChannel) { - rMatch(i) := io.mem_req(i).bank_id === bankId && io.mem_req(i).read.req.valid + rMatch(i) := canAcceptRead && (accPipes(i).io.target_bank_id === bankId) && accPipes(i).io.sramRead.req.valid } val rHas = rMatch.asUInt.orR - //assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") + val rSel = OHToUInt(rMatch) + // stronger safety: at most 1 + assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") + + // default bank read req + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) - val selIdx = OHToUInt(rMatch) - val connectIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) - connectIdx := selIdx - // selected pipe sees ready from bank - rd_req_ready(selIdx) := bank.io.sramRead.req.ready + // issue req from selected pipe when(rHas) { + bank.io.sramRead.req.valid := true.B + bank.io.sramRead.req.bits := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.bits)) + // ready to selected pipe + rd_req_ready(rSel) := bank.io.sramRead.req.ready - // bank gets req from selected pipe using Mux1H - bank.io.sramRead.req.valid := io.mem_req(selIdx).bank_id === bankId - bank.io.sramRead.req.bits := io.mem_req(selIdx).read.req.bits + when(bank.io.sramRead.req.fire) { + rOwnerValid := true.B + rOwnerIdx := rSel + } + } - }.otherwise { - bank.io.sramRead.req.valid := false.B - bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) + // resp routes by owner (NOT by rHas) + when(rOwnerValid) { + rd_resp_valid(rOwnerIdx) := bank.io.sramRead.resp.valid + rd_resp_data(rOwnerIdx) := bank.io.sramRead.resp.bits.data } - when(bank.io.sramRead.resp.valid) { - // response path: selected pipe sees bank resp - io.mem_req(connectIdx).read.resp.valid := bank.io.sramRead.resp.valid - io.mem_req(connectIdx).read.resp.bits.data := bank.io.sramRead.resp.bits.data - // bank sees ready from selected pipe - bank.io.sramRead.resp.ready := io.mem_req(connectIdx).read.resp.ready - }.otherwise { - bank.io.sramRead.resp.ready := false.B + // bank sees ready from owner pipe + bank.io.sramRead.resp.ready := Mux(rOwnerValid, rd_resp_ready(rOwnerIdx), false.B) + + when(bank.io.sramRead.resp.fire && rOwnerValid) { + rOwnerValid := false.B } } - - // ----------------------------------------------------------------------------- - // Optional: fire-level conflict assertions (stricter semantics) - // Enable if you prefer conflicts only when both actually handshake. - // ----------------------------------------------------------------------------- - // val wrFire = VecInit(accPipes.map(_.io.sramWrite.req.fire)) - // val rdFire = VecInit(accPipes.map(_.io.sramRead.req.fire)) - // for (i <- 0 until b.memDomain.bankChannel) { - // for (j <- (i + 1) until b.memDomain.bankChannel) { - // val bi = accPipes(i).io.target_bank_id - // val bj = accPipes(j).io.target_bank_id - // when(wrFire(i) && wrFire(j)) { assert(bi =/= bj) } - // when(rdFire(i) && rdFire(j)) { assert(bi =/= bj) } - // when(wrFire(i) && rdFire(j)) { assert(bi =/= bj) } - // when(rdFire(i) && wrFire(j)) { assert(bi =/= bj) } - // } - // } } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 693718c7..376e7770 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -142,6 +142,7 @@ class MemMidend(val b: GlobalConfig) extends Module { val rbank_id = io.balldomain.bankRead(entry.id).bank_id val wbank_id = io.balldomain.bankWrite(entry.id).bank_id + when(entry.isRead) { io.mem_req(i).read <> ballRead io.mem_req(i).bank_id := rbank_id @@ -156,7 +157,8 @@ class MemMidend(val b: GlobalConfig) extends Module { val frontendCh = b.top.memBallChannelNum io.mem_req(frontendCh).write <> io.frontend.bankWrite.io io.mem_req(frontendCh).read <> io.frontend.bankRead.io - io.mem_req(frontendCh).bank_id := io.frontend.bankWrite.bank_id + io.mem_req(frontendCh).bank_id := Mux(io.frontend.bankRead.io.req.valid, io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id) + //Mapping table release for (i <- 0 until numChannels) { From 4b7c13db89c7d48ca6f43f04afbd188ab6d6b2af Mon Sep 17 00:00:00 2001 From: SJM946 Date: Tue, 3 Feb 2026 22:11:59 +0800 Subject: [PATCH 080/238] [arch] Fix vecunit read resp bug --- .../prototype/vector/VecLoadUnit.scala | 31 +++++++++---------- .../memdomain/backend/MemBackend.scala | 6 ++-- .../memdomain/backend/banks/SramBank.scala | 2 +- .../outside_channel/dma/StreamReader.scala | 6 ++-- .../memdomain/midend/MemMidend.scala | 16 +++++++--- .../src/CTest/toy/vecunit_matmul_ones.c | 2 +- 6 files changed, 34 insertions(+), 29 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 791dc37c..1ee2d621 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -96,28 +96,27 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- - when(io.bankReadResp(0).valid && - (!ld_ex_valid_reg || io.ld_ex_o.ready) && (state === busy)) { - ld_ex_valid_reg := true.B - ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - ld_ex_op2_reg := io.bankReadResp(1).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - ld_ex_iter_reg := iter_counter - }.elsewhen(io.ld_ex_o.ready) { - ld_ex_valid_reg := false.B + when(io.bankReadResp(0).valid && io.bankReadResp(1).valid) { + io.ld_ex_o.valid := true.B + io.ld_ex_o.bits.op1 := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.ld_ex_o.bits.op2 := io.bankReadResp(1).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_iter_reg := ld_ex_iter_reg + 1.U + io.ld_ex_o.bits.iter := ld_ex_iter_reg + }.otherwise { + io.ld_ex_o.valid := false.B + io.ld_ex_o.bits.iter := 0.U + io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) } - io.ld_ex_o.valid := ld_ex_valid_reg - io.ld_ex_o.bits.op1 := ld_ex_op1_reg - io.ld_ex_o.bits.op2 := ld_ex_op2_reg - io.ld_ex_o.bits.iter := ld_ex_iter_reg - // ----------------------------------------------------------------------------- // Reset iter_counter and return to idle state // ----------------------------------------------------------------------------- - when(state === busy && iter_counter === iter && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - state := idle - iter_counter := 0.U + when(state === busy && ld_ex_iter_reg === iter && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { + state := idle + iter_counter := 0.U + ld_ex_iter_reg := 0.U } }.otherwise { io.ld_ex_o.valid := false.B diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 235af873..3d4392ce 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -172,10 +172,10 @@ class MemBackend(val b: GlobalConfig) extends Module { // ========================================================= // READ routing (req: combinational; resp: owner-registered) // ========================================================= - val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) + val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) // owner regs for read resp - val rOwnerValid = RegInit(false.B) - val rOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) + val rOwnerValid = RegInit(false.B) + val rOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) val canAcceptRead = !rOwnerValid for (i <- 0 until b.memDomain.bankChannel) { rMatch(i) := canAcceptRead && (accPipes(i).io.target_bank_id === bankId) && accPipes(i).io.sramRead.req.valid diff --git a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala index b4fd3848..bf25b6a4 100644 --- a/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala +++ b/arch/src/main/scala/framework/memdomain/backend/banks/SramBank.scala @@ -33,7 +33,7 @@ class SramBank(val b: GlobalConfig) extends Module { val rdata = mem.read(raddr, ren) io.sramRead.resp.valid := RegNext(ren) - io.sramRead.resp.bits.data := RegNext(rdata.asUInt) + io.sramRead.resp.bits.data := rdata.asUInt // ----------------------------------------------------------------------------- // Write path diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index db82905e..ee52c839 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -43,7 +43,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { }) val s_idle :: s_req_new_block :: Nil = Enum(2) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val req = Reg(new BBReadRequest()) @@ -71,8 +71,8 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // TileLink request construction - single beat val get = edge.Get( fromSource = xactId, - toAddress = 0.U, - lgSize = log2Ceil(beatBytes).U + toAddress = 0.U, + lgSize = log2Ceil(beatBytes).U )._2 // TLB processing pipeline diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 376e7770..de58511e 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -142,13 +142,16 @@ class MemMidend(val b: GlobalConfig) extends Module { val rbank_id = io.balldomain.bankRead(entry.id).bank_id val wbank_id = io.balldomain.bankWrite(entry.id).bank_id - when(entry.isRead) { io.mem_req(i).read <> ballRead - io.mem_req(i).bank_id := rbank_id + io.mem_req(i).bank_id := rbank_id + io.mem_req(i).read.req.valid := RegNext(ballRead.req.valid) + io.mem_req(i).read.req.bits := RegNext(ballRead.req.bits) }.otherwise { io.mem_req(i).write <> ballWrite - io.mem_req(i).bank_id := wbank_id + io.mem_req(i).bank_id := wbank_id + io.mem_req(i).write.req.valid := RegNext(ballWrite.req.valid) + io.mem_req(i).write.req.bits := RegNext(ballWrite.req.bits) } } } @@ -157,8 +160,11 @@ class MemMidend(val b: GlobalConfig) extends Module { val frontendCh = b.top.memBallChannelNum io.mem_req(frontendCh).write <> io.frontend.bankWrite.io io.mem_req(frontendCh).read <> io.frontend.bankRead.io - io.mem_req(frontendCh).bank_id := Mux(io.frontend.bankRead.io.req.valid, io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id) - + io.mem_req(frontendCh).bank_id := Mux( + io.frontend.bankRead.io.req.valid, + io.frontend.bankRead.bank_id, + io.frontend.bankWrite.bank_id + ) //Mapping table release for (i <- 0 until numChannels) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index ca1c16d5..e9fbe37d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -48,7 +48,7 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { int test_ones() { init_ones_matrix(input_matrix_a, DIM, DIM); - // init_ones_matrix(input_matrix_b, DIM, DIM); + init_ones_matrix(input_matrix_b, DIM, DIM); return run_test("All-ones matrices", input_matrix_a, input_matrix_b, DIM); } From df4a9fe87c011a0b32d54aa77c685faa332e744f Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 4 Feb 2026 14:32:31 +0800 Subject: [PATCH 081/238] [arch]improve:improve the robust of bankreading --- .../frontend/outside_channel/MemStorer.scala | 363 +++++++++--------- .../outside_channel/dma/StreamWriter.scala | 134 ++++--- bb-tests/workloads/lib/bbhw/isa/25_mvout.c | 2 +- 3 files changed, 248 insertions(+), 251 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index ee0d1090..26ee5782 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -5,7 +5,6 @@ import chisel3.util._ import framework.top.GlobalConfig import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import freechips.rocketchip.rocket.MStatus -import framework.memdomain.backend.banks.SramReadIO import framework.memdomain.frontend.outside_channel.dma.{BBWriteRequest, BBWriteResponse} import framework.balldomain.blink.BankRead import chisel3.experimental.hierarchy.{instantiable, public} @@ -13,269 +12,253 @@ import chisel3.experimental.hierarchy.{instantiable, public} @instantiable class MemStorer(val b: GlobalConfig) extends Module { val rob_id_width = log2Up(b.frontend.rob_entries) - // Byte count of one row of data - val line_bytes = b.memDomain.bankWidth / 8 - // 16-byte alignment - val align_bytes = 16 + + // One bank line bytes + private val line_bytes = (b.memDomain.bankWidth / 8) + // We pack/send 16B aligned beats to DMA + private val align_bytes = 16 @public val io = IO(new Bundle { - // Store instruction from ReservationStation val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) - // Completion signal sent to ReservationStation val cmdResp = Decoupled(new MemRsComplete(b)) - // Direct connection to DMA write interface + val dmaReq = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) val dmaResp = Flipped(Decoupled(new BBWriteResponse)) - // Connected to Bank read interface val bankRead = Flipped(new BankRead(b)) - }) - val s_idle :: s_sram_req :: s_dma_wait :: Nil = Enum(3) - val state = RegInit(s_idle) + // ----------------------------- + // State + // ----------------------------- + val s_idle :: s_issue_sram_req :: s_wait_sram_resp :: s_have_sram_beat :: s_push_dma :: s_done :: Nil = Enum(6) + val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) - val iter_reg = Reg(UInt(10.W)) - val sram_count = Reg(UInt(10.W)) - // Cache stride - val stride_reg = Reg(UInt(10.W)) - // Cache decoded bank information - val rd_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - - // Data buffer related registers - // 16-byte buffer - val data_buffer = Reg(UInt((align_bytes * 8).W)) - // Number of valid bytes in buffer - val buffer_valid_bytes = Reg(UInt(log2Ceil(align_bytes + 1).W)) - // Starting address corresponding to buffer - val buffer_start_addr = Reg(UInt(b.memDomain.memAddrLen.W)) - - // Receive store instruction - io.cmdReq.ready := state === s_idle + val mem_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) + val iter_reg = RegInit(0.U(10.W)) + val stride_reg = RegInit(0.U(10.W)) + val rd_bank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + + // which SRAM "row" we are reading (0..iter-1) + val sram_row = RegInit(0.U(10.W)) + + // ----------------------------- + // Pending buffer for SRAM resp + // ----------------------------- + val pending = RegInit(false.B) + val pendData = Reg(UInt(b.memDomain.bankWidth.W)) + val pendIsLast = RegInit(false.B) + + // ----------------------------- + // Optional: simple 16B align/merge support (keep your original intent) + // We'll keep a small byte buffer for unaligned head/tail. + // ----------------------------- + val data_buffer = RegInit(0.U((align_bytes * 8).W)) // 16B + val buffer_valid_bytes = RegInit(0.U(log2Ceil(align_bytes + 1).W)) + val buffer_start_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) + + // Convenience + val target_bank = rd_bank_reg + + // ----------------------------- + // Cmd accept + // ----------------------------- + io.cmdReq.ready := (state === s_idle) when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { - state := s_sram_req rob_id_reg := io.cmdReq.bits.rob_id mem_addr_reg := io.cmdReq.bits.cmd.mem_addr iter_reg := io.cmdReq.bits.cmd.iter rd_bank_reg := io.cmdReq.bits.cmd.bank_id - sram_count := 0.U stride_reg := io.cmdReq.bits.cmd.special(10, 0) - // Initialize buffer state + sram_row := 0.U + + pending := false.B + data_buffer := 0.U buffer_valid_bytes := 0.U - } + buffer_start_addr := 0.U - // Stream read SRAM data - // All reads come from the same bank, starting from row 0 - val target_bank = rd_bank_reg - val target_row = sram_count + state := s_issue_sram_req + } - io.bankRead.io.req.valid := (state === s_sram_req) - io.bankRead.io.req.bits.addr := target_row - io.bankRead.rob_id := rob_id_reg - io.bankRead.bank_id := target_bank - io.bankRead.ball_id := 0.U + // ----------------------------- + // SRAM read request + // ----------------------------- + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U + + io.bankRead.io.req.valid := (state === s_issue_sram_req) + io.bankRead.io.req.bits.addr := sram_row + + // IMPORTANT: + // SRAMBank read resp is a 1-cycle pulse, so we must ALWAYS be ready to take it, + // but only if we don't already hold a pending beat. + io.bankRead.io.resp.ready := !pending + + when(state === s_issue_sram_req) { + // Once request handshakes, wait for resp + when(io.bankRead.io.req.fire) { + state := s_wait_sram_resp + } + } - // Bank response processing - val bank_resp_valid = io.bankRead.io.resp.valid - val bank_resp_data = io.bankRead.io.resp.bits.data + // ----------------------------- + // Latch SRAM resp into pending (never drop it) + // ----------------------------- + val bank_resp_fire = io.bankRead.io.resp.fire + when(bank_resp_fire) { + pending := true.B + pendData := io.bankRead.io.resp.bits.data + pendIsLast := (sram_row + 1.U >= iter_reg) && (iter_reg =/= 0.U) // last row beat + state := s_have_sram_beat + } - // Calculate memory address corresponding to current row + // ----------------------------- + // Address calculation (same as your pattern, but use sram_row) + // NOTE: you used a 2D style addressing with stride; keep same formula. + // ----------------------------- val current_mem_addr = - mem_addr_reg + sram_count(1, 0) * line_bytes.U + ((sram_count >> 2) << 2) * stride_reg * line_bytes.U - // Lower 4 bits of address, 0 when 16-byte aligned - val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) - val aligned_addr = - Cat(current_mem_addr(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) - val is_aligned = addr_offset === 0.U - dontTouch(is_aligned) - dontTouch(aligned_addr) - - // Data merge logic (line_bytes = 16 bytes) - val incoming_data = bank_resp_data.asUInt - // Always 16 bytes - val incoming_bytes = 16.U - - // Data merged into buffer + mem_addr_reg + + sram_row(1, 0) * line_bytes.U + + ((sram_row >> 2) << 2) * stride_reg * line_bytes.U + + val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) + val aligned_addr = Cat( + current_mem_addr(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), + 0.U(log2Ceil(align_bytes).W) + ) + + // ----------------------------- + // Merge logic (kept compatible with your original behavior) + // incoming_data is always 16 bytes (bankWidth==128 in your waveforms) + // ----------------------------- + val incoming_data = pendData + val incoming_bytes = align_bytes.U + val merged_data = Wire(UInt((align_bytes * 8).W)) val total_valid_bytes = Wire(UInt(log2Ceil(align_bytes * 2).W)) - val is_last_iter = (sram_count >= (iter_reg - 1.U) && iter_reg > 0.U) || iter_reg === 0.U when(buffer_valid_bytes === 0.U) { - // Buffer is empty when(addr_offset === 0.U) { - // Address is aligned, use data directly merged_data := incoming_data total_valid_bytes := incoming_bytes }.otherwise { - // Address not aligned, first time: use low bits of new data as high bits of send data, pad low bits with 0 - val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) + // first unaligned: send high part, pad low with 0 + val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) merged_data := new_data_low << (addr_offset * 8.U) total_valid_bytes := align_bytes.U } }.otherwise { - // Buffer has data, concatenate: low bits of new data as high bits + buffer data as low bits - val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) + val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) merged_data := (new_data_low << (addr_offset * 8.U)) | data_buffer - // Always 16 bytes total_valid_bytes := align_bytes.U } - // Send logic: except for last iteration, can always fill 16 bytes val can_send_full_line = total_valid_bytes >= align_bytes.U - val send_bytes = Mux(can_send_full_line, align_bytes.U, total_valid_bytes) - // Determine send address - always use aligned address + // send address (aligned) val send_addr = Mux( buffer_valid_bytes === 0.U, aligned_addr, Cat(buffer_start_addr(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W)) ) - // DMA request logic - val should_send_normal = bank_resp_valid && can_send_full_line - val should_send_first_unaligned = bank_resp_valid && (buffer_valid_bytes === 0.U && addr_offset =/= 0.U) - val should_send_last = bank_resp_valid && is_last_iter && !can_send_full_line - val should_send = should_send_normal || should_send_first_unaligned || should_send_last - - // Add a flag to track whether all data has been processed - // Completion detection logic - supports two cases: - // 1. Clean data completion (fully aligned case) - val aligned_completion = buffer_valid_bytes === 0.U && is_last_iter - // 2. Remaining data needs to be sent (unaligned case) - // Has remaining data - val has_remaining_data_completion = buffer_valid_bytes > 0.U && is_last_iter - val unaligned_completion_final_send = has_remaining_data_completion && !bank_resp_valid - - // Generate mask + // send mask val send_mask = Wire(UInt(align_bytes.W)) when(buffer_valid_bytes === 0.U && addr_offset =/= 0.U) { - // First unaligned: send high bits of new data, mask on high bits val valid_bytes = align_bytes.U - addr_offset - // 0xFF00 (if addr_offset=8) send_mask := ((1.U << valid_bytes) - 1.U) << addr_offset }.elsewhen(buffer_valid_bytes > 0.U && can_send_full_line) { - // Middle concatenation: send full 16 bytes - send_mask := ~0.U(align_bytes.W) // 0xFFFF - }.elsewhen(unaligned_completion_final_send) { - // Last send remaining buffer data: buffer data in low bits - send_mask := (1.U << buffer_valid_bytes) - 1.U // 0x00FF + send_mask := ~0.U(align_bytes.W) }.otherwise { - // Aligned case: full data - send_mask := ~0.U(align_bytes.W) // 0xFFFF - } - - // DMA request signal control logic - can only update when DMA is ready - val dma_req_valid_reg = RegInit(false.B) - val dma_req_vaddr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) - val dma_req_data_reg = RegInit(0.U((align_bytes * 8).W)) - val dma_req_len_reg = RegInit(0.U(8.W)) - val dma_req_mask_reg = RegInit(0.U(align_bytes.W)) - val dma_req_status_reg = RegInit(0.U.asTypeOf(new MStatus)) - - // Calculate DMA request signals - val dma_req_valid_next = - (should_send || unaligned_completion_final_send) && (state === s_sram_req || state === s_dma_wait) - val dma_req_vaddr_next = Mux(unaligned_completion_final_send, buffer_start_addr, send_addr) - val dma_req_data_next = Mux(unaligned_completion_final_send, data_buffer, merged_data) - val dma_req_len_next = align_bytes.U - val dma_req_mask_next = Mux(unaligned_completion_final_send, (1.U << buffer_valid_bytes) - 1.U, send_mask) - val dma_req_status_next = 0.U.asTypeOf(new MStatus) - - // Only update registers when DMA is ready - when(io.dmaReq.ready) { - dma_req_valid_reg := dma_req_valid_next - dma_req_vaddr_reg := dma_req_vaddr_next - dma_req_data_reg := dma_req_data_next - dma_req_len_reg := dma_req_len_next - dma_req_mask_reg := dma_req_mask_next - dma_req_status_reg := dma_req_status_next + send_mask := ~0.U(align_bytes.W) } - // Connect to DMA interface - io.dmaReq.valid := dma_req_valid_reg - io.dmaReq.bits.vaddr := dma_req_vaddr_reg - io.dmaReq.bits.data := dma_req_data_reg - io.dmaReq.bits.len := dma_req_len_reg - io.dmaReq.bits.mask := dma_req_mask_reg - io.dmaReq.bits.status := dma_req_status_reg - - // Connect Bank response ready signal - based on DMA ready state - io.bankRead.io.resp.ready := io.dmaReq.ready && (state === s_sram_req || state === s_dma_wait) - // State transition and counter update - when(io.bankRead.io.req.fire) { - state := s_dma_wait - } + // ----------------------------- + // DMA request (Decoupled correct): hold valid until fire + // ----------------------------- + val dma_v = RegInit(false.B) + val dma_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) + val dma_data = RegInit(0.U((align_bytes * 8).W)) + val dma_mask = RegInit(0.U(align_bytes.W)) + + io.dmaReq.valid := dma_v + io.dmaReq.bits.vaddr := dma_addr + io.dmaReq.bits.data := dma_data + io.dmaReq.bits.len := align_bytes.U + io.dmaReq.bits.mask := dma_mask + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + + // By default we don't care dmaResp in this simple model + io.dmaResp.ready := true.B - when(io.dmaReq.fire) { - when(!unaligned_completion_final_send) { - sram_count := sram_count + 1.U + // When we have a pending SRAM beat, prepare one DMA beat (and keep it until fire) + when(state === s_have_sram_beat) { + // Only arm dma_v if not already armed + when(!dma_v) { + dma_v := true.B + dma_addr := send_addr + dma_data := merged_data + dma_mask := send_mask + state := s_push_dma } + } - // Update buffer state - when(addr_offset =/= 0.U && bank_resp_valid) { - // Unaligned case: cache high bits of new data - // Cache is the high bits part - val remaining_bytes = align_bytes.U - addr_offset - data_buffer := incoming_data >> (addr_offset * 8.U) - buffer_valid_bytes := remaining_bytes - // Update buffer corresponding address (point to next 16-byte aligned address) - when(buffer_valid_bytes === 0.U) { - buffer_start_addr := aligned_addr + align_bytes.U + // When DMA accepts the beat, consume pending and move forward + when(state === s_push_dma) { + when(io.dmaReq.fire) { + dma_v := false.B + + // Update buffer state like your original: + when(addr_offset =/= 0.U) { + val remaining_bytes = align_bytes.U - addr_offset + data_buffer := incoming_data >> (addr_offset * 8.U) + buffer_valid_bytes := remaining_bytes + when(buffer_valid_bytes === 0.U) { + buffer_start_addr := aligned_addr + align_bytes.U + }.otherwise { + buffer_start_addr := buffer_start_addr + align_bytes.U + } }.otherwise { - buffer_start_addr := buffer_start_addr + align_bytes.U + // aligned: clear buffer if it was used + when(buffer_valid_bytes > 0.U && can_send_full_line) { + buffer_valid_bytes := 0.U + data_buffer := 0.U + } } - }.elsewhen(unaligned_completion_final_send) { - // Sent final remaining data, clear buffer - buffer_valid_bytes := 0.U - }.otherwise { - // In aligned case, if previous buffer data was merged and sent, need to clear buffer - when(buffer_valid_bytes > 0.U && can_send_full_line && bank_resp_valid) { - buffer_valid_bytes := 0.U + + // Mark current beat consumed + pending := false.B + + // advance row + when(iter_reg =/= 0.U) { + sram_row := sram_row + 1.U } - } - // Fix state transition logic - when(unaligned_completion_final_send) { - // Only return to idle after unaligned_completion_final_send completes - state := s_idle - }.elsewhen(aligned_completion) { - // All data has been sent - state := s_idle - }.elsewhen(sram_count + 1.U >= iter_reg && iter_reg > 0.U) { - // Iteration ended, but there may still be buffer data to send - when(buffer_valid_bytes > 0.U) { - // Maintain state, wait for unaligned_completion_final_send - state := s_dma_wait + // finish condition + when(pendIsLast || iter_reg === 0.U) { + state := s_done }.otherwise { - state := s_idle + state := s_issue_sram_req } - }.elsewhen(iter_reg === 0.U) { - state := s_idle - }.otherwise { - state := s_sram_req } } - // Wait for DMA to truly complete - io.dmaResp.ready := true.B - - // Fix completion signal logic - only issue completion signal after all data transfer is truly complete - val task_complete = RegInit(false.B) - when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { - task_complete := false.B - }.elsewhen(io.dmaReq.fire && (unaligned_completion_final_send || aligned_completion)) { - task_complete := true.B + // If we are waiting for SRAM resp (but resp will pulse), just stay here + when(state === s_wait_sram_resp) { + // nothing; latch happens in bank_resp_fire block above } - io.cmdResp.valid := task_complete && (state === s_idle) + // ----------------------------- + // Completion + // ----------------------------- + io.cmdResp.valid := (state === s_done) io.cmdResp.bits.rob_id := rob_id_reg - // Reset flag after sending completion signal when(io.cmdResp.fire) { - task_complete := false.B + state := s_idle } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index fb2fe7ad..3f5df024 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -2,11 +2,9 @@ package framework.memdomain.frontend.outside_channel.dma import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.{MStatus, M_XWR} - -import framework.builtin.utils.Util._ import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO import framework.top.GlobalConfig @@ -26,12 +24,10 @@ class BBWriteResponse extends Bundle { class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val vaddrBits = b.core.vaddrBits - - val nXacts = b.memDomain.dma_n_xacts val beatBits = b.memDomain.dma_buswidth - val maxBytes = b.memDomain.dma_maxbytes val dataWidth = b.memDomain.dma_buswidth val beatBytes = beatBits / 8 + val lgBeat = log2Ceil(beatBytes) @public val io = IO(new Bundle { @@ -43,85 +39,103 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tl = new TLBundle(edge.bundle) }) - val s_idle :: s_writing :: Nil = Enum(2) + // --------------------------------------------------------------------------- + // Strict single-outstanding writer with PROPER handshakes + // --------------------------------------------------------------------------- + // NOTE: current TLB/Cluster returns resp combinationally in the same cycle as req.valid + // (see StreamReader usage). So we must NOT "fire req then wait for resp". + val s_idle :: s_tlb_req :: s_wait_d :: s_resp :: Nil = Enum(4) + val state = RegInit(s_idle) + + val reqReg = Reg(new BBWriteRequest(dataWidth)) - val xactBusy = RegInit(0.U(nXacts.W)) - val xactOnehot = PriorityEncoderOH(~xactBusy) - val xactId = OHToUInt(xactOnehot) + // single outstanding => fixed source id 0 + val xactId = 0.U(io.tl.a.bits.source.getWidth.W) - val xactBusy_fire = WireInit(false.B) - val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) - val xactBusy_remove = ~Mux(io.tl.d.fire, (1.U << io.tl.d.bits.source).asUInt, 0.U) - xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt + // ----------------------- + // Accept one request + // ----------------------- + io.req.ready := (state === s_idle) + + when(io.req.fire) { + reqReg := io.req.bits + state := s_tlb_req + } - // Simplified: data is already aligned, directly construct TileLink request - val lg_beat_bytes = log2Ceil(beatBytes) - val use_put_full = io.req.bits.mask === ~0.U(beatBytes.W) + // ----------------------- + // Construct TileLink Put from LATCHED request + // ----------------------- + val use_put_full = reqReg.mask === ~0.U(beatBytes.W) val putFull = edge.Put( fromSource = xactId, - toAddress = 0.U, - lgSize = lg_beat_bytes.U, - data = io.req.bits.data + toAddress = 0.U, // overwritten later + lgSize = lgBeat.U, + data = reqReg.data )._2 val putPartial = edge.Put( fromSource = xactId, - toAddress = 0.U, - lgSize = lg_beat_bytes.U, - data = io.req.bits.data, - mask = io.req.bits.mask + toAddress = 0.U, // overwritten later + lgSize = lgBeat.U, + data = reqReg.data, + mask = reqReg.mask )._2 - val selected_put = Mux(use_put_full, putFull, putPartial) - - // TLB processing pipeline - class TLBundleAWithInfo extends Bundle { - val tl_a = selected_put.cloneType - val vaddr = Output(UInt(vaddrBits.W)) - val status = Output(new MStatus) - } - - val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) - xactBusy_fire := untranslated_a.fire - untranslated_a.valid := !xactBusy.andR && io.req.valid - untranslated_a.bits.tl_a := selected_put - untranslated_a.bits.vaddr := io.req.bits.vaddr - untranslated_a.bits.status := io.req.bits.status - - val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - tlb_q.io.enq <> untranslated_a + val putMsg = Wire(putFull.cloneType) + putMsg := Mux(use_put_full, putFull, putPartial) - io.tlb.req.valid := tlb_q.io.deq.valid + // ----------------------- + // TLB handshake (req.fire -> wait resp.valid) + // ----------------------- + io.tlb.req.valid := (state === s_tlb_req) io.tlb.req.bits := DontCare - io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr - io.tlb.req.bits.passthrough := true.B //use paddr for now + io.tlb.req.bits.vaddr := reqReg.vaddr + io.tlb.req.bits.passthrough := true.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XWR - io.tlb.req.bits.prv := 3.U // Machine mode + io.tlb.req.bits.prv := 3.U io.tlb.req.bits.v := false.B - io.tlb.req.bits.status := tlb_q.io.deq.bits.status - tlb_q.io.deq.ready := io.tlb.resp.valid && tlb_q.io.deq.valid + io.tlb.req.bits.status := reqReg.status - // TileLink A channel (request) connection - io.tl.a.valid := io.tlb.resp.valid && tlb_q.io.deq.valid - io.tl.a.bits := tlb_q.io.deq.bits.tl_a + // We only "consume" the tlb response when we actually send A. + // This matches StreamReader: resp.valid is treated as a combinational translate result. + io.tlb.resp.ready := (state === s_tlb_req) && io.tl.a.ready + + // ----------------------- + // TileLink A channel (only when tlb resp is present) + // ----------------------- + io.tl.a.valid := (state === s_tlb_req) && io.tlb.resp.valid + io.tl.a.bits := putMsg io.tl.a.bits.address := io.tlb.resp.bits.paddr - io.tlb.resp.ready := true.B - // TileLink D channel (response) processing - io.tl.d.ready := io.resp.ready + when(state === s_tlb_req && io.tl.a.fire) { + state := s_wait_d + } + + // ----------------------- + // TileLink D channel (ack) + // ----------------------- + io.tl.d.ready := (state === s_wait_d) - io.resp.valid := io.tl.d.valid + // upper response + io.resp.valid := (state === s_resp) io.resp.bits.done := true.B - // Tie off unused TileLink channels + when(state === s_wait_d && io.tl.d.fire) { + state := s_resp + } + + when(state === s_resp && io.resp.fire) { + state := s_idle + } + + // ----------------------- + // Tie off unused TL channels + // ----------------------- io.tl.b.ready := true.B io.tl.c.valid := false.B io.tl.e.valid := false.B - // State machine - io.req.ready := !xactBusy.andR - io.busy := xactBusy.orR - + io.busy := (state =/= s_idle) } diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c index 0be05635..5ee847dc 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c @@ -8,7 +8,7 @@ #define bb_mvout(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ FIELD(mem_addr, 0, 31), \ - (FIELD(bank_id, 0, 4) | FIELD(depth, 5, 14) | FIELD(stride, 14, 33)), \ + (FIELD(bank_id, 0, 4) | FIELD(depth, 5, 14) | FIELD(stride, 15, 33)), \ BB_MVOUT_FUNC7) #endif // _BB_MVOUT_H_ From 14b470fab676badea104d1ee5492d5bd2b00928c Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 4 Feb 2026 18:41:57 +0800 Subject: [PATCH 082/238] [nix] feat: add htif env into nix --- bb-tests/workloads/CMakeLists.txt | 1 + .../workloads/src/CTest/bebop/CMakeLists.txt | 3 +- .../src/CTest/gemmini/CMakeLists.txt | 2 +- .../workloads/src/CTest/rvv/CMakeLists.txt | 2 +- .../workloads/src/CTest/toy/CMakeLists.txt | 2 +- .../src/OpTest/gemmini/CMakeLists.txt | 2 +- .../workloads/src/OpTest/toy/CMakeLists.txt | 4 +- .../workloads/src/tutorial/CMakeLists.txt | 2 +- flake.nix | 4 + scripts/nix/build-all.sh | 50 ++++++++---- scripts/nix/build-env-chipyard.nix | 79 ++++++++++++++++++- 11 files changed, 127 insertions(+), 24 deletions(-) diff --git a/bb-tests/workloads/CMakeLists.txt b/bb-tests/workloads/CMakeLists.txt index 2939e206..8f4e3d0d 100644 --- a/bb-tests/workloads/CMakeLists.txt +++ b/bb-tests/workloads/CMakeLists.txt @@ -24,6 +24,7 @@ set(LLVM_BUILD_DIR ${BUDDY_MLIR_DIR}/llvm/build) set(ELF_CC ${RISCV_GNU_TOOLCHAIN}/bin/riscv64-unknown-elf-gcc) set(LINUX_CC ${RISCV_GNU_TOOLCHAIN}/bin/riscv64-unknown-linux-gnu-gcc) +set(HTIF_DIR ${RISCV_GNU_TOOLCHAIN}/riscv64-unknown-elf/lib) set(BUILD_BIN_DIR ${WORKLOAD_DIR}/../build/workloads) set(OUTPUT_BIN_DIR ${WORKLOAD_DIR}/../output/workloads) diff --git a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt index 2f115b39..1db5a714 100644 --- a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt @@ -5,7 +5,8 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") # Set baremetal compilation flags #------------------------------------------------------------------------------- set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf -specs=htif_nano.specs -I${CTEST_TOY_WORKLOAD_DIR}) + -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} + -I${CTEST_TOY_WORKLOAD_DIR}) #------------------------------------------------------------------------------- # Define common compilation step functions diff --git a/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt b/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt index 340a2bff..bab7a611 100644 --- a/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt @@ -7,7 +7,7 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -std=gnu99 -ffast-math -fno-builtin-printf -fno-tree-loop-distribute-patterns -DBAREMETAL=1 -DPREALLOCATE=1 -DMULTITHREAD=1 -DPRINT_TILE=0 - -specs=htif_nano.specs -I${CTEST_GEMMINI_WORKLOAD_DIR}) + -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} -I${CTEST_GEMMINI_WORKLOAD_DIR}) # Link libraries set(LINK_LIBS -lm -lgcc) diff --git a/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt b/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt index bdbe515f..24f20150 100644 --- a/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt @@ -5,7 +5,7 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") # Set baremetal compilation flags with RVV support #------------------------------------------------------------------------------- set(C_FLAGS -g -fno-common -O1 -static -march=rv64gcv -mabi=lp64d -mcmodel=medany - -fno-builtin-printf -specs=htif_nano.specs) + -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} ) #------------------------------------------------------------------------------- # Define common compilation step functions diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index db1c5816..af3548e8 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -5,7 +5,7 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") # Set baremetal compilation flags #------------------------------------------------------------------------------- set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf -specs=htif_nano.specs -I${CTEST_TOY_WORKLOAD_DIR}) + -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} -I${CTEST_TOY_WORKLOAD_DIR}) #------------------------------------------------------------------------------- # Define common compilation step functions diff --git a/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt b/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt index 172ccf27..23b2c5a0 100644 --- a/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt @@ -34,7 +34,7 @@ function(add_baremetal_target TARGET_NAME MLIR_FILE) add_custom_command( OUTPUT ${EXECUTABLE} - COMMAND ${ELF_CC} -O2 -static -specs=htif_nano.specs + COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} ${OBJ_FILE} -o ${EXECUTABLE} DEPENDS ${OBJ_FILE} COMMENT "Linking baremetal executable: ${EXECUTABLE}" diff --git a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt index 2f5f306e..cdce50b0 100644 --- a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt @@ -26,7 +26,7 @@ # add_custom_command( # OUTPUT ${EXECUTABLE} -# COMMAND ${ELF_CC} -O2 -static -specs=htif_nano.specs +# COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs # ${OBJ_FILE} -o ${EXECUTABLE} # DEPENDS ${OBJ_FILE} # COMMENT "Linking baremetal executable: ${EXECUTABLE}" @@ -61,7 +61,7 @@ # add_custom_command( # OUTPUT ${EXECUTABLE} -# COMMAND ${ELF_CC} -O2 -static -specs=htif_nano.specs +# COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs # ${OBJ_FILE} -o ${EXECUTABLE} # DEPENDS ${OBJ_FILE} # COMMENT "Linking baremetal executable: ${EXECUTABLE}" diff --git a/bb-tests/workloads/src/tutorial/CMakeLists.txt b/bb-tests/workloads/src/tutorial/CMakeLists.txt index 273011f6..7f31808a 100644 --- a/bb-tests/workloads/src/tutorial/CMakeLists.txt +++ b/bb-tests/workloads/src/tutorial/CMakeLists.txt @@ -20,7 +20,7 @@ add_custom_target(tutorial-linux-build ALL DEPENDS set(ELF_CC "riscv64-unknown-elf-gcc") set(C_FLAGS -std=c11 -g -fno-common -O2 -static - -fno-builtin-printf -specs=htif_nano.specs) + -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR}) add_custom_target(tutorial-baremetal-build ALL COMMAND ${ELF_CC} ${C_FLAGS} -o tutorial-baremetal ${TUTORIAL_WORKLOAD_DIR}/tutorial.c diff --git a/flake.nix b/flake.nix index 65dfbd6f..732006a4 100644 --- a/flake.nix +++ b/flake.nix @@ -70,6 +70,8 @@ export LLVM_MLIR_BUILD_DIR="$PWD/compiler/llvm/build" export PYTHONPATH="$PWD/compiler/llvm/build/tools/mlir/python_packages/mlir_core:$PWD/compiler/build/python_packages:$PYTHONPATH" export PATH="$PWD/workflow:$PATH" + export RISCV="$PWD/result" + export PATH="$PWD/thirdparty/libgloss/install/lib:$PATH" echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" @@ -79,6 +81,8 @@ echo "Cargo: $(cargo --version 2>&1 | head -1)" echo "npm: $(npm --version 2>&1 | head -1)" echo "bbdev: $(which bbdev)" + echo "RISCV: $RISCV" + echo "LIBGLOSS: $(whereis htif_nano.specs)" echo "===========================================================================" ''; }; diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index dad70ea2..1d5fedfa 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -78,7 +78,7 @@ function begin_step begin_step "0-1" "submodules init" git submodule update --init -cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init +cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init generators/* tools/* begin_step "0-2" "Nix environment setup" cd ${BBDIR} @@ -93,7 +93,29 @@ if [ "${INSTALL_IN_NIX}" = "0" ]; then fi if run_step "1"; then - begin_step "1" "Compiler (buddy-mlir) pre-compile sources" + begin_step "1" "riscv-tools setup" + cd ${BBDIR}/thirdparty/libgloss + mkdir -p build && cd build + CC=riscv64-unknown-elf-gcc ../configure \ + --prefix=${RISCV}/lib \ + --host=riscv64-unknown-elf + make + make install + # INSTALL_DIR=${RISCV}/lib + # mkdir -p ${INSTALL_DIR}/lib + # find . -name "libgloss_htif.a" | while read -r lib; do + # subdir=$(dirname "$lib" | sed 's|^\./||') + # [ "$subdir" = "build" ] && subdir="" + # dest=${INSTALL_DIR}/lib/${subdir} + # mkdir -p "$dest" + # cp "$lib" "$dest/" + # cp ../util/htif_nano.specs ../util/htif.ld ../util/htif.specs \ + # ../util/htif_wrap.specs ../util/htif_argv.specs "$dest/" 2>/dev/null || true + # done +fi + +if run_step "2"; then + begin_step "2" "Compiler (buddy-mlir) pre-compile sources" cd ${BBDIR}/compiler git submodule update --init llvm @@ -121,33 +143,33 @@ if run_step "1"; then ninja # check-buddy fi -if run_step "2"; then - begin_step "2" "Install bebop" +if run_step "3"; then + begin_step "3" "Install bebop" # ${BBDIR}/scripts/install-bebop.sh echo "bebop is not installed" fi -if run_step "3"; then - begin_step "3" "bb-tests (workloads) pre-compile sources" +if run_step "4"; then + begin_step "4" "bb-tests (workloads) pre-compile sources" cd ${BBDIR}/bb-tests mkdir -p build && cd build cmake -G Ninja .. ninja fi -if run_step "4"; then - begin_step "4" "Install requirements for sardine" +if run_step "5"; then + begin_step "5" "Install requirements for sardine" npm install --prefix ${BBDIR}/bb-tests/sardine allure-commandline fi -if run_step "5"; then - begin_step "5" "Install document management system" +if run_step "6"; then + begin_step "6" "Install document management system" mdbook-mermaid install ${BBDIR}/docs/bb-note/ fi -if run_step "6"; then - begin_step "6" "Init workflow management system" +if run_step "7"; then + begin_step "7" "Init workflow management system" cd ${BBDIR}/workflow export USE_SYSTEMD=no npm init -y @@ -162,8 +184,8 @@ if run_step "6"; then cd ${BBDIR}/workflow && rm *.{md,tsx,rdb} || true fi -if run_step "7"; then - begin_step "7" "Install pre-commit hooks" +if run_step "8"; then + begin_step "8" "Install pre-commit hooks" pre-commit install fi diff --git a/scripts/nix/build-env-chipyard.nix b/scripts/nix/build-env-chipyard.nix index 573066fb..59d60464 100644 --- a/scripts/nix/build-env-chipyard.nix +++ b/scripts/nix/build-env-chipyard.nix @@ -1,13 +1,88 @@ { pkgs }: +let + # Build newlib-nano with size optimization flags + newlib-nano = pkgs.pkgsCross.riscv64-embedded.newlib.overrideAttrs (oldAttrs: { + pname = "newlib-nano"; + configureFlags = oldAttrs.configureFlags or [] ++ [ + "--enable-newlib-nano-malloc" + "--enable-newlib-nano-formatted-io" + "--enable-newlib-reent-small" + "--disable-newlib-fvwrite-in-streamio" + "--disable-newlib-fseek-optimization" + "--disable-newlib-wide-orient" + "--disable-newlib-unbuf-stream-opt" + "--enable-lite-exit" + "--enable-newlib-global-atexit" + ]; + CFLAGS_FOR_TARGET = "-Os -ffunction-sections -fdata-sections -mcmodel=medany"; + }); + + # Create a custom cross system with newlib-nano + riscv64EmbeddedWithNano = pkgs.pkgsCross.riscv64-embedded.stdenv.targetPlatform // { + libc = "newlib-nano"; + }; + + # Build the toolchain with the custom platform + pkgsCrossWithNano = import pkgs.path { + inherit (pkgs) system; + crossSystem = riscv64EmbeddedWithNano; + overlays = [ + (self: super: { + newlib = newlib-nano; + }) + ]; + }; + + # Build libgloss-htif library from upstream + libgloss-htif = pkgs.stdenv.mkDerivation { + pname = "libgloss-htif"; + version = "0.1"; + + src = pkgs.fetchFromGitHub { + owner = "ucb-bar"; + repo = "libgloss-htif"; + rev = "master"; + sha256 = "sha256-FXuN1xK5133QqoHI4EG7mvhk7K8J6//ar7Y1+IUPER0="; + }; + + nativeBuildInputs = [ pkgsCrossWithNano.buildPackages.gcc ]; + + configureFlags = [ + "--host=riscv64-unknown-elf" + ]; + + preConfigure = '' + export CC=riscv64-none-elf-gcc + export AR=riscv64-none-elf-ar + export RANLIB=riscv64-none-elf-ranlib + ''; + + enableParallelBuilding = true; + + installPhase = '' + mkdir -p $out/riscv64-unknown-elf/lib + + # Install library and specs files manually to bypass the Makefile check + install -m 644 libgloss_htif.a $out/riscv64-unknown-elf/lib/ + install -m 644 util/htif.specs $out/riscv64-unknown-elf/lib/ + install -m 644 util/htif_nano.specs $out/riscv64-unknown-elf/lib/ + install -m 644 util/htif_wrap.specs $out/riscv64-unknown-elf/lib/ + install -m 644 util/htif_argv.specs $out/riscv64-unknown-elf/lib/ + install -m 644 util/htif.ld $out/riscv64-unknown-elf/lib/ + ''; + }; +in + { # Fast and robust (System)Verilog simulator/compiler and linter verilator = pkgs.verilator; # RISC-V embedded toolchain (bare metal), with riscv64-unknown-elf-* symlinks + # Now includes newlib-nano and libgloss-htif support riscv-embedded-gcc = pkgs.symlinkJoin { name = "riscv64-unknown-elf-gcc"; - paths = [ pkgs.pkgsCross.riscv64-embedded.buildPackages.gcc ]; + paths = [ pkgsCrossWithNano.buildPackages.gcc libgloss-htif ]; postBuild = '' cd $out/bin for f in riscv64-none-elf-*; do @@ -18,7 +93,7 @@ ''; }; - # RISC-V Linux toolchain (full stdenv.cc with static libc for -static linking) + # RISC-V Linux toolchain riscv-linux-gcc = let cc = pkgs.pkgsCross.riscv64.stdenv.cc; libcStatic = pkgs.pkgsCross.riscv64.stdenv.cc.libc.static; From fd2e510c3fcd0d31fcb45174feb0fcdfc6131e64 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Thu, 5 Feb 2026 21:39:54 +0800 Subject: [PATCH 083/238] [arch] Add acc config inst --- .../scala/framework/memdomain/MemDomain.scala | 1 + .../memdomain/backend/MemBackend.scala | 11 +++--- .../memdomain/backend/accpipe/AccPipe.scala | 8 +--- .../memdomain/frontend/MemFrontend.scala | 12 ++++-- .../cmd_channel/decoder/DomainDecoder.scala | 23 +++++++---- .../cmd_channel/rs/reservationStation.scala | 16 +++++++- .../outside_channel/MemConfiger.scala | 39 +++++++++++++++++++ .../frontend/outside_channel/MemStorer.scala | 33 ++++++++-------- .../outside_channel/dma/StreamWriter.scala | 18 ++++----- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 2 + .../src/CTest/toy/vecunit_matmul_ones.c | 2 + 11 files changed, 116 insertions(+), 49 deletions(-) create mode 100644 arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 01fa9bb3..3f6f4605 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -84,4 +84,5 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite midend.io.mem_req <> backend.io.mem_req + backend.io.acc_config <> frontend.io.acc_config } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 3d4392ce..681e32c5 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -29,7 +29,8 @@ class MemBackend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val acc_config = Input(UInt(b.memDomain.bankNum.W)) }) val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) @@ -42,6 +43,8 @@ class MemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.write <> io.mem_req(i).write accPipes(i).io.read <> io.mem_req(i).read accPipes(i).io.bank_id := io.mem_req(i).bank_id + val bank_id = io.mem_req(i).bank_id + accPipes(i).io.is_acc := io.acc_config(bank_id) } // ----------------------------------------------------------------------------- @@ -178,7 +181,7 @@ class MemBackend(val b: GlobalConfig) extends Module { val rOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) val canAcceptRead = !rOwnerValid for (i <- 0 until b.memDomain.bankChannel) { - rMatch(i) := canAcceptRead && (accPipes(i).io.target_bank_id === bankId) && accPipes(i).io.sramRead.req.valid + rMatch(i) := (accPipes(i).io.target_bank_id === bankId) && accPipes(i).io.sramRead.req.valid } val rHas = rMatch.asUInt.orR val rSel = OHToUInt(rMatch) @@ -210,8 +213,6 @@ class MemBackend(val b: GlobalConfig) extends Module { // bank sees ready from owner pipe bank.io.sramRead.resp.ready := Mux(rOwnerValid, rd_resp_ready(rOwnerIdx), false.B) - when(bank.io.sramRead.resp.fire && rOwnerValid) { - rOwnerValid := false.B - } + /* when(bank.io.sramRead.resp.fire && rOwnerValid) { rOwnerValid := false.B } */ } } diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index e8bf05eb..8d052283 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -35,6 +35,7 @@ class AccPipe(val b: GlobalConfig) extends Module { // Control and status signals val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val is_acc = Input(Bool()) // in AccPipe IO bundle, add: val target_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) @@ -126,6 +127,7 @@ class AccPipe(val b: GlobalConfig) extends Module { // Downstream bank requests (valid depends only on upstream valid + state) io.sramRead.req.valid := writeAccum || readValid io.sramRead.req.bits.addr := Mux(writeAccum, io.write.req.bits.addr, io.read.req.bits.addr) + io.read.resp <> io.sramRead.resp io.sramWrite.req.valid := writeDirect io.sramWrite.req.bits.addr := io.write.req.bits.addr @@ -157,12 +159,6 @@ class AccPipe(val b: GlobalConfig) extends Module { latData := io.write.req.bits.data latMask := io.write.req.bits.mask state := s_wait_direct_write_resp - }.elsewhen(readValid && io.sramRead.req.fire) { - curBankId := io.bank_id - opIsRead := true.B - opIsAccum := false.B - latAddr := io.read.req.bits.addr - state := s_wait_read_resp } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 57169811..ffea3e87 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import freechips.rocketchip.tile._ import framework.memdomain.frontend.outside_channel.dma.{StreamReader, StreamWriter} -import framework.memdomain.frontend.outside_channel.{MemLoader, MemStorer} +import framework.memdomain.frontend.outside_channel.{MemConfiger, MemLoader, MemStorer} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} @@ -46,6 +46,8 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tl_reader = new TLBundle(edge.bundle) val tl_writer = new TLBundle(edge.bundle) + val acc_config = Output(UInt(b.memDomain.bankNum.W)) + // Busy signal val busy = Output(Bool()) }) @@ -61,8 +63,9 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tlbCluster = Instantiate(new BBTLBCluster(b)(edge)) // DMA Reader and Writer modules - handle actual DMA transfers - val reader: Instance[StreamReader] = Instantiate(new StreamReader(b)(edge)) - val writer: Instance[StreamWriter] = Instantiate(new StreamWriter(b)(edge)) + val reader: Instance[StreamReader] = Instantiate(new StreamReader(b)(edge)) + val writer: Instance[StreamWriter] = Instantiate(new StreamWriter(b)(edge)) + val configer: Instance[MemConfiger] = Instantiate(new MemConfiger(b)) // ----------------------------------------------------------------------------- // Global RS -> MemDecoder @@ -70,6 +73,7 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { memDecoder.io.cmd_i.valid := io.global_issue_i.valid memDecoder.io.cmd_i.bits := io.global_issue_i.bits.cmd io.global_issue_i.ready := memDecoder.io.cmd_i.ready + io.acc_config := configer.io.acc_config // ----------------------------------------------------------------------------- // MemDecoder -> MemReservationStation @@ -85,8 +89,10 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ----------------------------------------------------------------------------- memLoader.io.cmdReq <> memRs.io.issue_o.ld memStorer.io.cmdReq <> memRs.io.issue_o.st + configer.io.cmdReq <> memRs.io.issue_o.cf memRs.io.commit_i.ld <> memLoader.io.cmdResp memRs.io.commit_i.st <> memStorer.io.cmdResp + memRs.io.commit_i.cf <> configer.io.cmdResp //----------------------------------------------------------------------------- // PMC - Performance Monitor Counter diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index d756d8a1..1124b781 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -10,8 +10,10 @@ import chisel3.experimental.hierarchy.{instantiable, public} // Detailed decode output for Mem domain class MemDecodeCmd(b: GlobalConfig) extends Bundle { - val is_load = Bool() - val is_store = Bool() + val is_load = Bool() + val is_store = Bool() + val is_config = Bool() + // Memory address val mem_addr = UInt(b.memDomain.memAddrLen.W) // Iteration count @@ -67,12 +69,12 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { ls_default_decode, Array( MSET_BITPAT -> List( - Y, + N, N, rs1(memAddrLen - 1, 0), rs2(bankIdLen - 1, 0), rs2(9 + bankIdLen, bankIdLen), - rs2(63, 10 + bankIdLen), + rs2(39, 0), Y ), // mset MVIN_BITPAT -> List( @@ -107,22 +109,27 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- io.mem_decode_cmd_o.valid := io.cmd_i.valid && (io.cmd_i.bits.domain_id === DomainId.MEM) - io.mem_decode_cmd_o.bits.is_load := Mux( + io.mem_decode_cmd_o.bits.is_load := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.LD_EN.id).asBool, false.B ) - io.mem_decode_cmd_o.bits.is_store := Mux( + io.mem_decode_cmd_o.bits.is_store := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.ST_EN.id).asBool, false.B ) - io.mem_decode_cmd_o.bits.mem_addr := Mux( + io.mem_decode_cmd_o.bits.is_config := Mux( + io.mem_decode_cmd_o.valid, + func7 === MSET_BITPAT, + false.B + ) + io.mem_decode_cmd_o.bits.mem_addr := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.MEMADDR.id).asUInt, 0.U(b.memDomain.memAddrLen.W) ) - io.mem_decode_cmd_o.bits.iter := Mux( + io.mem_decode_cmd_o.bits.iter := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.ITER.id).asUInt, 0.U(10.W) diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala index 55d600d3..9769f09f 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala @@ -23,12 +23,14 @@ class MemRsComplete(val b: GlobalConfig) extends Bundle { class MemIssueInterface(val b: GlobalConfig) extends Bundle { val ld = Decoupled(new MemRsIssue(b)) val st = Decoupled(new MemRsIssue(b)) + val cf = Decoupled(new MemRsIssue(b)) } // Mem domain completion interface combination (Load + Store) class MemCommitInterface(val b: GlobalConfig) extends Bundle { val ld = Flipped(Decoupled(new MemRsComplete(b))) val st = Flipped(Decoupled(new MemRsComplete(b))) + val cf = Flipped(Decoupled(new MemRsComplete(b))) } // Local Mem reservation station - simple FIFO scheduler @@ -82,15 +84,21 @@ class MemReservationStation(val b: GlobalConfig) extends Module { io.issue_o.st.bits.cmd := headEntry.cmd io.issue_o.st.bits.rob_id := headEntry.rob_id + // Config issue + io.issue_o.cf.valid := fifo.io.deq.valid && headEntry.cmd.is_config + io.issue_o.cf.bits.cmd := headEntry.cmd + io.issue_o.cf.bits.rob_id := headEntry.rob_id + // FIFO deq.ready - can only dequeue when target unit is ready fifo.io.deq.ready := (headEntry.cmd.is_load && io.issue_o.ld.ready) || - (headEntry.cmd.is_store && io.issue_o.st.ready) + (headEntry.cmd.is_store && io.issue_o.st.ready) || + (headEntry.cmd.is_config && io.issue_o.cf.ready) // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), 2)) + val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), 3)) completeArb.io.in(0).valid := io.commit_i.ld.valid completeArb.io.in(0).bits := io.commit_i.ld.bits.rob_id @@ -100,6 +108,10 @@ class MemReservationStation(val b: GlobalConfig) extends Module { completeArb.io.in(1).bits := io.commit_i.st.bits.rob_id io.commit_i.st.ready := completeArb.io.in(1).ready + completeArb.io.in(2).valid := io.commit_i.cf.valid + completeArb.io.in(2).bits := io.commit_i.cf.bits.rob_id + io.commit_i.cf.ready := completeArb.io.in(2).ready + // Forward completion signal (with global rob_id) io.complete_o.valid := completeArb.io.out.valid io.complete_o.bits.rob_id := completeArb.io.out.bits diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala new file mode 100644 index 00000000..62548bb0 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -0,0 +1,39 @@ +package framework.memdomain.frontend.outside_channel + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig +import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} +import chisel3.experimental.hierarchy.{instantiable, public} + +@instantiable +class MemConfiger(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) + + // One bank line bytes + private val line_bytes = b.memDomain.bankWidth / 8 + // We pack/send 16B aligned beats to DMA + private val align_bytes = 16 + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) + val cmdResp = Decoupled(new MemRsComplete(b)) + + val acc_config = Output(UInt(b.memDomain.bankNum.W)) + }) + + val acc_config_reg = RegInit(0.U(b.memDomain.bankNum.W)) + + when(io.cmdReq.valid) { + acc_config_reg := io.cmdReq.bits.cmd.special(b.memDomain.bankNum - 1, 0) + + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id + }.otherwise { + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + } + io.cmdReq.ready := true.B + io.acc_config := acc_config_reg +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 26ee5782..57ae8222 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -14,7 +14,7 @@ class MemStorer(val b: GlobalConfig) extends Module { val rob_id_width = log2Up(b.frontend.rob_entries) // One bank line bytes - private val line_bytes = (b.memDomain.bankWidth / 8) + private val line_bytes = b.memDomain.bankWidth / 8 // We pack/send 16B aligned beats to DMA private val align_bytes = 16 @@ -33,7 +33,7 @@ class MemStorer(val b: GlobalConfig) extends Module { // State // ----------------------------- val s_idle :: s_issue_sram_req :: s_wait_sram_resp :: s_have_sram_beat :: s_push_dma :: s_done :: Nil = Enum(6) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val mem_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) @@ -47,9 +47,9 @@ class MemStorer(val b: GlobalConfig) extends Module { // ----------------------------- // Pending buffer for SRAM resp // ----------------------------- - val pending = RegInit(false.B) - val pendData = Reg(UInt(b.memDomain.bankWidth.W)) - val pendIsLast = RegInit(false.B) + val pending = RegInit(false.B) + val pendData = Reg(UInt(b.memDomain.bankWidth.W)) + val pendIsLast = RegInit(false.B) // ----------------------------- // Optional: simple 16B align/merge support (keep your original intent) @@ -68,19 +68,19 @@ class MemStorer(val b: GlobalConfig) extends Module { io.cmdReq.ready := (state === s_idle) when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { - rob_id_reg := io.cmdReq.bits.rob_id - mem_addr_reg := io.cmdReq.bits.cmd.mem_addr - iter_reg := io.cmdReq.bits.cmd.iter - rd_bank_reg := io.cmdReq.bits.cmd.bank_id - stride_reg := io.cmdReq.bits.cmd.special(10, 0) - sram_row := 0.U + rob_id_reg := io.cmdReq.bits.rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + iter_reg := io.cmdReq.bits.cmd.iter + rd_bank_reg := io.cmdReq.bits.cmd.bank_id + stride_reg := io.cmdReq.bits.cmd.special(10, 0) + sram_row := 0.U pending := false.B data_buffer := 0.U buffer_valid_bytes := 0.U buffer_start_addr := 0.U - state := s_issue_sram_req + state := s_issue_sram_req } // ----------------------------- @@ -125,7 +125,8 @@ class MemStorer(val b: GlobalConfig) extends Module { sram_row(1, 0) * line_bytes.U + ((sram_row >> 2) << 2) * stride_reg * line_bytes.U - val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) + val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) + val aligned_addr = Cat( current_mem_addr(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), 0.U(log2Ceil(align_bytes).W) @@ -147,12 +148,12 @@ class MemStorer(val b: GlobalConfig) extends Module { total_valid_bytes := incoming_bytes }.otherwise { // first unaligned: send high part, pad low with 0 - val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) + val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) merged_data := new_data_low << (addr_offset * 8.U) total_valid_bytes := align_bytes.U } }.otherwise { - val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) + val new_data_low = incoming_data & ((1.U << (addr_offset * 8.U)) - 1.U) merged_data := (new_data_low << (addr_offset * 8.U)) | data_buffer total_valid_bytes := align_bytes.U } @@ -180,7 +181,7 @@ class MemStorer(val b: GlobalConfig) extends Module { // ----------------------------- // DMA request (Decoupled correct): hold valid until fire // ----------------------------- - val dma_v = RegInit(false.B) + val dma_v = RegInit(false.B) val dma_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) val dma_data = RegInit(0.U((align_bytes * 8).W)) val dma_mask = RegInit(0.U(align_bytes.W)) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index 3f5df024..b6c93c97 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -45,9 +45,9 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // NOTE: current TLB/Cluster returns resp combinationally in the same cycle as req.valid // (see StreamReader usage). So we must NOT "fire req then wait for resp". val s_idle :: s_tlb_req :: s_wait_d :: s_resp :: Nil = Enum(4) - val state = RegInit(s_idle) + val state = RegInit(s_idle) - val reqReg = Reg(new BBWriteRequest(dataWidth)) + val reqReg = Reg(new BBWriteRequest(dataWidth)) // single outstanding => fixed source id 0 val xactId = 0.U(io.tl.a.bits.source.getWidth.W) @@ -69,17 +69,17 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val putFull = edge.Put( fromSource = xactId, - toAddress = 0.U, // overwritten later - lgSize = lgBeat.U, - data = reqReg.data + toAddress = 0.U, // overwritten later + lgSize = lgBeat.U, + data = reqReg.data )._2 val putPartial = edge.Put( fromSource = xactId, - toAddress = 0.U, // overwritten later - lgSize = lgBeat.U, - data = reqReg.data, - mask = reqReg.mask + toAddress = 0.U, // overwritten later + lgSize = lgBeat.U, + data = reqReg.data, + mask = reqReg.mask )._2 val putMsg = Wire(putFull.cloneType) diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index 6ee779d7..382a4ab0 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -15,4 +15,6 @@ #define bb_mem_alloc(bank_id, row, col) bb_mset(0, bank_id, 1, row, col) +#define bb_acc_config(acc_mask) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(acc_mask, 0, 0), BB_MSET_FUNC7) #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index e9fbe37d..f9ed830b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -26,6 +26,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + bb_acc_config(0x0000003C); + bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); From c770fd7464d85b1ca5710d91b226cded1647dd33 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Fri, 6 Feb 2026 15:58:43 +0800 Subject: [PATCH 084/238] [arch]fix :fix the bug of reludecode and improve ctest --- .../toy/balldomain/DomainDecoder.scala | 2 +- bb-tests/workloads/src/CTest/toy/relu_test.c | 116 ++++++++++++------ docs/bb-note/src/tutorial/tutorial.md | 2 +- 3 files changed, 78 insertions(+), 42 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 34bf2caf..61b8011f 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -72,9 +72,9 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { ball_default_decode, Array( MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), + RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 1.U, rs2(63, 16)), IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), - RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 4.U, rs2(63, 16)), CONCAT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) ) diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index eb9ab523..04475282 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -5,38 +5,98 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 // 强制 16x16 + +// ======================= +// 固定输入矩阵（4行周期） +// ======================= +static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))) = { + // ---- Cycle 1 ---- + // Row1 + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + // Row2 + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + // Row3 + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + // Row4 + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 2 ---- + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 3 ---- + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 4 ---- + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38 +}; + +// ======================= +// 直接写死 ReLU 结果 +// ======================= +static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { + // ---- Cycle 1 ---- + 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, + 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, + 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, + 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 2 ---- + 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, + 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, + 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, + 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 3 ---- + 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, + 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, + 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, + 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 4 ---- + 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, + 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, + 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, + 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38 +}; -static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))); static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); -// Used to verify content in SPAD after MVIN -// Expected: provide a ReLU flow similar to TRANSPOSE -// Currently bbhw/isa does not have bb_relu high-level API, this example uses -// the same move-in->execute->fence flow as transpose. Need to add -// bb_relu(op1_addr, wr_addr, iter) wrapper in bbhw implementation -// (func7=RELU_FUNC7). -void hw_relu(const char *test_name, elem_t *a, result_t *b, int size) { - // Source operand in spad bank 0, write target in spad bank 1 +// ======================= +// HW ReLU Flow（保持不变） +// ======================= +void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - // Move input into scratchpad bank0, starting at offset 0, iterate size times - // row-wise bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); - // Call ReLU instruction + bb_relu(op1_bank_id, wr_bank_id, size); bb_fence(); + bb_mvout((uintptr_t)b, wr_bank_id, size, 1); } + +// ======================= +// 测试函数（去掉 CPU 计算） +// ======================= int run_test(const char *test_name, elem_t *a, int size) { clear_i8_matrix(output_matrix, size, size); - cpu_relu(a, expected_matrix, size, size); + hw_relu(test_name, a, output_matrix, size); + if (compare_i8_matrices(output_matrix, expected_matrix, size, size)) { printf("%s compare test PASSED\n", test_name); return 1; @@ -46,36 +106,12 @@ int run_test(const char *test_name, elem_t *a, int size) { } } -int relu_cpu_reference(elem_t *input, elem_t *output, int size) { - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - elem_t val = input[i * size + j]; - output[i * size + j] = (val < 0) ? 0 : val; - } - } - return 1; -} int test_relu(int seed) { - init_i8_random_matrix(input_matrix, DIM, DIM, seed); - // // CPU TEST BEGIN - // // Measure cycles for the CPU ReLU reference implementation - // unsigned long long start = read_rdcycle(); - // // CPU verification - // int ok = relu_cpu_reference(input_matrix_a, output_matrix_b, DIM); - // unsigned long long end = read_rdcycle(); - // unsigned long long cycles = end - start; - // /* Print as hex high/low 32-bit parts to avoid embedded printf lacking - // full long long support. This produces a stable, greppable output. */ - // uint32_t lo = (uint32_t)(cycles & 0xffffffffULL); - // uint32_t hi = (uint32_t)(cycles >> 32); - // printf("BB_CYCLES_RELU: 0x%08x%08x\n", hi, lo); - // return ok; - // // CPU TEST END return run_test("ReLU", input_matrix, DIM); - // ReLUBall test code, need to comment out the code block above } + int main() { #ifdef MULTICORE multicore(MULTICORE); diff --git a/docs/bb-note/src/tutorial/tutorial.md b/docs/bb-note/src/tutorial/tutorial.md index 044e05be..f70aa591 100644 --- a/docs/bb-note/src/tutorial/tutorial.md +++ b/docs/bb-note/src/tutorial/tutorial.md @@ -248,7 +248,7 @@ If `bbdev verilator --verilog` reports an error after execution, this means hard ### Step 3: Run simulation ``` -bbdev verilator --run '--jobs 16 --binary ctest_relu_test_singlecore-baremetal --batch' +bbdev verilator --run '--jobs 16 --binary ctest_relu_test_singlecore-baremetal --config sims.verilator.BuckyballToyVerilatorConfig --batch' ``` If `bbdev verilator --verilog` reports an error after execution, this means the hardware system has timeout, deadlock and other issues, please check **I. Writing Chisel Hardware Module** related files. From 1bdc23bd2672df66f270539c3910843a926eb86f Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Fri, 6 Feb 2026 22:35:44 +0800 Subject: [PATCH 085/238] [arch]fix:fix bugs of streamreader and add transposeball --- .../toy/balldomain/DomainDecoder.scala | 4 +- .../toy/balldomain/bbus/busRegister.scala | 2 + .../framework/balldomain/configs/default.json | 5 +- .../balldomain/prototype/transpose/README.md | 115 ++++++++++++ .../prototype/transpose/Transpose.scala | 174 ++++++++++++++++++ .../prototype/transpose/TransposeBall.scala | 39 ++++ .../configs/TransposeBallParam.scala | 21 +++ .../prototype/transpose/configs/default.json | 4 + .../memdomain/backend/accpipe/AccPipe.scala | 10 +- .../frontend/outside_channel/MemLoader.scala | 16 +- .../outside_channel/dma/StreamReader.scala | 145 ++++++--------- 11 files changed, 433 insertions(+), 102 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/transpose/README.md create mode 100644 arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/transpose/configs/default.json diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 61b8011f..692ef5b9 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -73,8 +73,8 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { Array( MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 1.U, rs2(63, 16)), - IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), - TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), + TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), + IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), CONCAT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) ) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index d8cf9266..4b5981fb 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -8,6 +8,7 @@ import framework.balldomain.bbus.BBus import framework.balldomain.blink.HasBlink import framework.balldomain.prototype.vector.VecBall import framework.balldomain.prototype.relu.ReluBall +import framework.balldomain.prototype.transpose.TransposeBall /** * BBusModule - Ball bus module that directly extends BBus @@ -20,6 +21,7 @@ class BBusModule(b: GlobalConfig) val ballGenerator: () => HasBlink with Module = mapping.ballName match { case "VecBall" => () => new VecBall(b) case "ReluBall" => () => new ReluBall(b) + case "TransposeBall" => () => new TransposeBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 873524c2..0d13d0b6 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,7 +1,8 @@ { - "ballNum": 2, + "ballNum": 3, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, - {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1} + {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, + {"ballId": 1, "ballName": "TransposeBall", "inBW": 1, "outBW": 1} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/README.md b/arch/src/main/scala/framework/balldomain/prototype/transpose/README.md new file mode 100644 index 00000000..3c01b53d --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/README.md @@ -0,0 +1,115 @@ +# Matrix Transpose Accelerator + +## Overview + +This directory implements Buckyball's matrix transpose accelerator for matrix transpose operations. Located at `arch/src/main/scala/prototype/transpose`, it serves as a matrix transpose accelerator supporting pipelined transpose operations. + +Core components: +- **Transpose.scala**: Pipelined transposer implementation + +## Code Structure + +``` +transpose/ +└── Transpose.scala - Pipelined transposer +``` + +### Module Responsibilities + +**Transpose.scala** (Transpose implementation layer) +- Implements PipelinedTransposer module +- Manages matrix data read, transpose, and write-back +- Provides Ball domain command interface + +## Module Description + +### Transpose.scala + +**Main functionality**: Implements pipelined matrix transpose operation + +**State machine definition**: +```scala +val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) +val state = RegInit(idle) +``` + +**Storage structure**: +```scala +// Matrix storage register (veclane x veclane) +val regArray = Reg(Vec(b.veclane, Vec(b.veclane, UInt(b.inputType.getWidth.W)))) +``` + +**Counter management**: +```scala +val readCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) +val respCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) +val writeCounter = RegInit(0.U(log2Ceil(b.veclane + 1).W)) +``` + +**Instruction registers**: +```scala +val robid_reg = RegInit(0.U(10.W)) // ROB ID +val waddr_reg = RegInit(0.U(10.W)) // Write address +val wbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) // Write bank +val raddr_reg = RegInit(0.U(10.W)) // Read address +val rbank_reg = RegInit(0.U(log2Up(b.sp_banks).W)) // Read bank +val iter_reg = RegInit(0.U(10.W)) // Iteration count +``` + +**Interface definition**: +```scala +val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue)) + val cmdResp = Decoupled(new BallRsComplete) + val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(...))) + val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(...))) +}) +``` + +**Processing flow**: +1. **idle**: Wait for command, parse transpose parameters +2. **sRead**: Read matrix data row by row into register array +3. **sWrite**: Write transposed data column by column +4. **complete**: Send completion signal + +**Transpose algorithm**: +- Uses veclane×veclane register array to store matrix +- Reads row-wise, writes column-wise to implement transpose +- Supports block-wise transpose for matrices of arbitrary size + +## Usage + +### Implementation Details + +**State machine**: +```scala +val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) +``` +- `idle`: Wait for instruction +- `sRead`: Read matrix data +- `sWrite`: Write transpose result +- `complete`: Complete and respond + +**Register array**: +```scala +val regArray = Reg(Vec(b.veclane, Vec(b.veclane, UInt(b.inputType.getWidth.W)))) +``` +Uses veclane×veclane register array to cache matrix data. + +**Transpose operation**: +- Read phase: Read data row by row into `regArray(row)(col)` +- Write phase: Read `regArray(i)(col)` column by column to form new rows for writing + +### Configuration Parameters + +**Matrix size**: Determined by b.veclane parameter +**Data width**: Determined by b.inputType.getWidth +**Bank configuration**: Supports multi-bank SRAM access + +### Notes + +1. **Matrix size limitation**: Maximum support for veclane×veclane matrices +2. **Memory bandwidth**: Transpose operation has high memory bandwidth requirements +3. **Register overhead**: Requires veclane² registers to store matrix +4. **Address calculation**: Transposed address calculation needs to be handled correctly +5. **Pipeline control**: Read/write counters need to be synchronized correctly diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala new file mode 100644 index 00000000..cb09d024 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -0,0 +1,174 @@ +package framework.balldomain.prototype.transpose + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} + +import framework.balldomain.prototype.vector._ +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.top.GlobalConfig +import framework.balldomain.prototype.transpose.configs.TransposeBallParam + +@instantiable +class Transpose(val b: GlobalConfig) extends Module { + val ballConfig = TransposeBallParam() + val InputNum = ballConfig.InputNum + val inputWidth = ballConfig.inputWidth + val bankWidth = b.memDomain.bankWidth + + // Get bandwidth from config + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "TransposeBall") + .getOrElse(throw new IllegalArgumentException("TransposeBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + } + +val idle :: compute :: Nil = Enum(2) + val state = RegInit(idle) + + // Matrix storage register (veclane x veclane) + val regArray = Reg(Vec(2*InputNum, Vec(InputNum, UInt(inputWidth.W)))) + + // Counters + val readCounter = RegInit(0.U(10.W)) + val respCounter = RegInit(0.U(10.W)) + val writeCounter = RegInit(0.U(10.W)) + val respWaitcounter = RegInit(0.U(10.W)) + val writeHeadptr = RegInit(0.U(10.W)) + val writeTailptr = RegInit(0.U(10.W)) + + // Instruction registers + val robid_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(10.W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val raddr_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(10.W)) + val write_iter_reg = RegInit(0.U(10.W)) + val mode_reg = RegInit(0.U(1.W)) + + + // Precompute write data + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(b.memDomain.bankMaskLen, UInt(1.W))) + + val start_write = RegInit(false.B) + // SRAM default assignment + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + } + + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B + } + + for (i <- 0 until inBW) { + io.bankRead(i).bank_id := rbank_reg + } + for (i <- 0 until outBW) { + io.bankWrite(i).bank_id := wbank_reg + } + + // cmd interface default assignment + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + when(state === idle && io.cmdReq.fire){ + state := compute + readCounter := 0.U + respCounter := 0.U + respWaitcounter := io.cmdReq.bits.cmd.iter + respWaitcounter + + robid_reg := io.cmdReq.bits.rob_id + waddr_reg := 0.U + wbank_reg := io.cmdReq.bits.cmd.wr_bank + raddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + iter_reg := io.cmdReq.bits.cmd.iter + mode_reg := io.cmdReq.bits.cmd.special(0) + } + // read req + when(((mode_reg === 1.U) &&(state === compute) && RegNext(io.bankWrite(0).io.req.ready))|| + ((mode_reg === 0.U) && (state === compute))){ + readCounter := readCounter + 1.U + io.bankRead(0).io.req.valid := readCounter < iter_reg + io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter + state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) + } + io.cmdResp.valid := (readCounter >= (iter_reg - 1.U)) && (state === compute) + io.cmdResp.bits.rob_id := robid_reg + + // read resp + io.bankRead(0).io.resp.ready := true.B + val dataWord = io.bankRead(0).io.resp.bits.data + val row = respCounter(4,0) + when(io.bankRead(0).io.resp.fire && respWaitcounter > 0.U){ + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + regArray(row)(col) := dataWord(hi, lo) + } + respCounter := Mux(respCounter === iter_reg - 1.U, 0.U, respCounter + 1.U) + writeHeadptr := Mux(writeHeadptr === 2.U* InputNum.U - 1.U, 0.U, writeHeadptr + 1.U) + respWaitcounter := Mux(state === idle && io.cmdReq.fire, io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, respWaitcounter - 1.U) + } + + // write req + val wreg = RegInit(0.U(10.W)) + val array_full = ((writeTailptr < InputNum.U) && (writeHeadptr >= InputNum.U)) || + ((writeTailptr >= InputNum.U) && (writeHeadptr < InputNum.U)) + when(writeCounter === iter_reg - 1.U){ + start_write := false.B + }.elsewhen( array_full && !start_write){ + start_write := true.B + wreg := waddr_reg + write_iter_reg := iter_reg + }.otherwise{ + start_write := start_write + } + + when(start_write){ + io.bankWrite(0).io.req.valid := true.B + io.bankWrite(0).io.req.bits.addr := wreg + writeCounter + io.bankWrite(0).io.req.bits.data := Mux( writeCounter(4) === 0.U, Cat((0 until InputNum).reverse.map(i => regArray(i)(writeCounter(3,0)))) , + Cat((0 until InputNum).reverse.map(i => regArray(i + InputNum)(writeCounter(3,0))))) + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) + writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U,writeCounter + 1.U) + writeTailptr := Mux(writeTailptr === 2.U* InputNum.U - 1.U, 0.U, writeTailptr + 1.U) + } + // Status signals + io.status.idle := state === idle + io.status.running := state === compute +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala new file mode 100644 index 00000000..292a1d74 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala @@ -0,0 +1,39 @@ +package framework.balldomain.prototype.transpose + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.prototype.transpose.Transpose +import framework.top.GlobalConfig + + +@instantiable +class TransposeBall(val b: GlobalConfig) extends Module with HasBlink { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "TransposeBall") + .getOrElse(throw new IllegalArgumentException("TransposeBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + + val transposeUnit: Instance[Transpose] = Instantiate(new Transpose(b)) + + transposeUnit.io.cmdReq <> io.cmdReq + transposeUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + transposeUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + transposeUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + io.status <> transposeUnit.io.status + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala new file mode 100644 index 00000000..87389adc --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala @@ -0,0 +1,21 @@ +package framework.balldomain.prototype.transpose.configs + +import upickle.default._ + +/** + * TransposeBall参数 + */ +case class TransposeBallParam( + InputNum: Int, + inputWidth: Int) + +object TransposeBallParam { + implicit val rw: ReadWriter[TransposeBallParam] = macroRW + + def apply(): TransposeBallParam = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/framework/balldomain/prototype/transpose/configs/default.json").mkString + read[TransposeBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/default.json new file mode 100644 index 00000000..a4552216 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/default.json @@ -0,0 +1,4 @@ +{ + "InputNum": 16, + "inputWidth": 8 +} diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 8d052283..fc02a4fd 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -130,9 +130,9 @@ class AccPipe(val b: GlobalConfig) extends Module { io.read.resp <> io.sramRead.resp io.sramWrite.req.valid := writeDirect - io.sramWrite.req.bits.addr := io.write.req.bits.addr - io.sramWrite.req.bits.data := io.write.req.bits.data - io.sramWrite.req.bits.mask := io.write.req.bits.mask + io.sramWrite.req.bits.addr := 0.U + io.sramWrite.req.bits.data := 0.U + io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) io.sramWrite.req.bits.wmode := false.B // Upstream ready is a function of the selected downstream ready @@ -215,6 +215,10 @@ class AccPipe(val b: GlobalConfig) extends Module { is(s_wait_direct_write_resp) { // Direct write: forward resp + io.sramWrite.req.valid := true.B + io.sramWrite.req.bits.addr := io.write.req.bits.addr + io.sramWrite.req.bits.data := io.write.req.bits.data + io.sramWrite.req.bits.mask := io.write.req.bits.mask io.write.resp.valid := io.sramWrite.resp.valid io.write.resp.bits.ok := io.sramWrite.resp.bits.ok io.sramWrite.resp.ready := io.write.resp.ready diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 236a7922..78fa55d9 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -25,7 +25,7 @@ class MemLoader(val b: GlobalConfig) extends Module { val bankWrite = Flipped(new BankWrite(b)) }) - val s_idle :: s_dma_req :: s_dma_wait :: Nil = Enum(3) + val s_idle :: s_dma_req :: s_dma_wait :: s_done :: Nil = Enum(4) val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) @@ -33,7 +33,7 @@ class MemLoader(val b: GlobalConfig) extends Module { val iter_reg = Reg(UInt(10.W)) val resp_count = RegInit(0.U(log2Up(16).W)) val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - val stride_reg = Reg(UInt(10.W)) + val stride_reg = Reg(UInt(11.W)) // ----------------------------- // pending latch for 1-beat DMA -> bankWrite @@ -71,8 +71,8 @@ class MemLoader(val b: GlobalConfig) extends Module { io.bankWrite.bank_id := wr_bank_reg io.bankWrite.ball_id := 0.U - // cmdResp defaults - io.cmdResp.valid := false.B + // cmdResp (Decoupled): hold valid until accepted + io.cmdResp.valid := (state === s_done) io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) io.cmdResp.bits.rob_id := rob_id_reg @@ -85,6 +85,7 @@ class MemLoader(val b: GlobalConfig) extends Module { mem_addr_reg := io.cmdReq.bits.cmd.mem_addr iter_reg := io.cmdReq.bits.cmd.iter wr_bank_reg := io.cmdReq.bits.cmd.bank_id + // BBReadRequest.stride is 10 bits wide stride_reg := io.cmdReq.bits.cmd.special(10, 0) resp_count := 0.U pending := false.B @@ -112,8 +113,11 @@ class MemLoader(val b: GlobalConfig) extends Module { when(latLast) { // command complete only when last beat has been accepted by bank write - state := s_idle - io.cmdResp.valid := true.B + state := s_done } } + + when(state === s_done && io.cmdResp.fire) { + state := s_idle + } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index ee52c839..aae62df5 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -6,7 +6,6 @@ import chisel3.experimental.hierarchy.{instantiable, public} import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.{MStatus, M_XRD} -import framework.builtin.utils.Util._ import framework.memdomain.frontend.outside_channel.tlb.BBTLBIO import framework.top.GlobalConfig @@ -14,154 +13,122 @@ class BBReadRequest extends Bundle { val vaddr = UInt(64.W) val len = UInt(16.W) val status = new MStatus - val stride = UInt(10.W) + val stride = UInt(10.W) // 暂时不用 } class BBReadResponse(dataWidth: Int) extends Bundle { val data = UInt(dataWidth.W) val last = Bool() - val addrcounter = UInt(10.W) // will be beat index: 0,1,2,... + val addrcounter = UInt(10.W) } @instantiable class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { - val vaddrBits = b.core.vaddrBits - val nXacts = b.memDomain.dma_n_xacts + val beatBits = b.memDomain.dma_buswidth - val maxBytes = b.memDomain.dma_maxbytes - val dataWidth = b.memDomain.dma_buswidth val beatBytes = beatBits / 8 @public val io = IO(new Bundle { val req = Flipped(Decoupled(new BBReadRequest())) - val resp = Decoupled(new BBReadResponse(dataWidth)) + val resp = Decoupled(new BBReadResponse(beatBits)) val tlb = Flipped(new BBTLBIO(b)) val busy = Output(Bool()) val flush = Input(Bool()) val tl = new TLBundle(edge.bundle) }) - val s_idle :: s_req_new_block :: Nil = Enum(2) - val state = RegInit(s_idle) + //------------------------------------------------------------ + // FSM + //------------------------------------------------------------ + + val s_idle :: s_run :: Nil = Enum(2) + val state = RegInit(s_idle) - val req = Reg(new BBReadRequest()) + val reqReg = Reg(new BBReadRequest()) - // Number of bytes requested (A sent) val bytesRequested = RegInit(0.U(16.W)) - // Number of bytes received (D accepted) val bytesReceived = RegInit(0.U(16.W)) - val bytesLeft = req.len - bytesRequested - - // Select request size - simplified version, fixed use of beatBytes - val read_size = minOf(beatBytes.U, bytesLeft) - val read_vaddr = req.vaddr + bytesRequested * req.stride - - // Transaction ID management - val xactBusy = RegInit(0.U(nXacts.W)) - val xactOnehot = PriorityEncoderOH(~xactBusy) - val xactId = OHToUInt(xactOnehot) - - val xactBusy_fire = WireInit(false.B) - val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) - val xactBusy_remove = ~Mux(io.tl.d.fire, (1.U << io.tl.d.bits.source).asUInt, 0.U) - xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt - - // TileLink request construction - single beat + val inflight = RegInit(false.B) + val read_vaddr = reqReg.vaddr + bytesRequested val get = edge.Get( - fromSource = xactId, - toAddress = 0.U, - lgSize = log2Ceil(beatBytes).U + fromSource = 0.U, + toAddress = 0.U, + lgSize = log2Ceil(beatBytes).U )._2 - // TLB processing pipeline - class TLBundleAWithInfo extends Bundle { - val tl_a = get.cloneType - val vaddr = Output(UInt(vaddrBits.W)) - val status = Output(new MStatus) - } - - val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) - xactBusy_fire := untranslated_a.fire && state === s_req_new_block - untranslated_a.valid := state === s_req_new_block && !xactBusy.andR - untranslated_a.bits.tl_a := get - untranslated_a.bits.vaddr := read_vaddr - untranslated_a.bits.status := req.status - // 1-deep queue to break comb paths - val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe = true)) - tlb_q.io.enq <> untranslated_a + io.tlb.req.valid := + (state === s_run) && + (bytesRequested < reqReg.len) && + !inflight - io.tlb.req.valid := tlb_q.io.deq.valid && (state === s_req_new_block) - io.tlb.req.bits := DontCare - io.tlb.req.bits.vaddr := tlb_q.io.deq.bits.vaddr + io.tlb.req.bits := DontCare + io.tlb.req.bits.vaddr := read_vaddr io.tlb.req.bits.passthrough := true.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XRD io.tlb.req.bits.prv := 3.U io.tlb.req.bits.v := false.B - io.tlb.req.bits.status := tlb_q.io.deq.bits.status + io.tlb.req.bits.status := reqReg.status - // consume tlb_q when tlb resp valid - tlb_q.io.deq.ready := io.tlb.resp.valid - // TileLink A channel - io.tl.a.valid := io.tlb.resp.valid && (state === s_req_new_block) - io.tl.a.bits := tlb_q.io.deq.bits.tl_a + io.tl.a.valid := + io.tlb.resp.valid && + !inflight + + io.tl.a.bits := get io.tl.a.bits.address := io.tlb.resp.bits.paddr - io.tlb.resp.ready := true.B - // ----------------------------- - // D channel -> resp - // ----------------------------- - // Backpressure from resp to TileLink D + io.tlb.resp.ready := io.tl.a.ready && !inflight + + when(io.tl.a.fire) { + inflight := true.B + bytesRequested := bytesRequested + beatBytes.U + } + + //------------------------------------------------------------ + // TL D → Response + //------------------------------------------------------------ + io.tl.d.ready := io.resp.ready - io.resp.valid := io.tl.d.valid + io.resp.valid := io.tl.d.valid io.resp.bits.data := io.tl.d.bits.data - // ✅ FIX: addrcounter = beat index in receive order (0,1,2,...) - // Current beat index before consuming this beat: - val beatIndex = (bytesReceived >> log2Ceil(beatBytes)).asUInt - io.resp.bits.addrcounter := beatIndex(9, 0) + val beatCountResp = bytesReceived >> log2Ceil(beatBytes) + io.resp.bits.addrcounter := beatCountResp(9,0) - // last flag based on total bytes after this beat - val resp_bytes_end = bytesReceived + beatBytes.U - io.resp.bits.last := io.tl.d.valid && (resp_bytes_end >= req.len) + io.resp.bits.last := + (bytesReceived + beatBytes.U >= reqReg.len) - // Update received bytes when we actually accept a beat when(io.tl.d.fire) { + inflight := false.B bytesReceived := bytesReceived + beatBytes.U } - // Tie off unused TileLink channels + + io.tl.b.ready := true.B io.tl.c.valid := false.B io.tl.e.valid := false.B - // ----------------------------- - // State machine - // ----------------------------- + + io.req.ready := (state === s_idle) - io.busy := xactBusy.orR || (state =/= s_idle) + + io.busy := (state =/= s_idle) || inflight when(io.req.fire) { - req := io.req.bits + reqReg := io.req.bits bytesRequested := 0.U bytesReceived := 0.U - state := s_req_new_block + inflight := false.B + state := s_run } - // IMPORTANT: bytesRequested should advance only when A actually fires - when(io.tl.a.fire) { - val nextBytesRequested = bytesRequested + read_size - bytesRequested := nextBytesRequested - - when(nextBytesRequested >= req.len) { - state := s_idle - }.otherwise { - state := s_req_new_block - } + when(state === s_run && bytesReceived >= reqReg.len) { + state := s_idle } } From 67b719f602476b8644435e55e7e30d98db54e5b8 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 9 Feb 2026 19:26:56 +0800 Subject: [PATCH 086/238] [arch] fix:fix bugs of reluball --- .../balldomain/prototype/relu/Relu.scala | 37 ++- .../memdomain/backend/accpipe/AccPipe.scala | 39 ++- .../memdomain/midend/MemMidend.scala | 273 +++++++++++------- 3 files changed, 213 insertions(+), 136 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 0cd0f726..2f80e37e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -122,14 +122,17 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } is(sRead) { - when(readCounter < InputNum.U) { - readCounter := readCounter + 1.U - io.bankRead(0).io.req.valid := true.B - io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter + io.bankRead(0).io.resp.ready := true.B + + io.bankRead(0).io.req.valid := (readCounter < InputNum.U) + io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter + + when(io.bankRead(0).io.req.fire) { + readCounter := readCounter + 1.U } val dataWord = io.bankRead(0).io.resp.bits.data - io.bankRead(0).io.resp.ready := true.B + when(io.bankRead(0).io.resp.fire) { for (col <- 0 until InputNum) { val hi = (col + 1) * inputWidth - 1 @@ -142,7 +145,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { respCounter := respCounter + 1.U } - when(respCounter === InputNum.U) { + when(respCounter === (InputNum-1).U) { state := sWrite writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) for (i <- 0 until b.memDomain.bankMaskLen) { @@ -152,21 +155,27 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } is(sWrite) { - io.bankWrite(0).io.req.valid := writeCounter < InputNum.U + val hasMore = writeCounter < InputNum.U + + io.bankWrite(0).io.req.valid := hasMore io.bankWrite(0).io.req.bits.addr := waddr_reg + writeCounter io.bankWrite(0).io.req.bits.data := writeDataReg io.bankWrite(0).io.req.bits.mask := writeMaskReg - - when(writeCounter === (InputNum - 1).U) { - state := complete - }.otherwise { - writeCounter := writeCounter + 1.U - writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(writeCounter + 1.U)(j))) + io.bankWrite(0).io.resp.ready := true.B + + when(io.bankWrite(0).io.req.fire) { + when(writeCounter === (InputNum - 1).U) { + state := complete + }.otherwise { + val nextCnt = writeCounter + 1.U + writeCounter := nextCnt + writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(nextCnt)(j))) + } } - } is(complete) { + io.bankWrite(0).io.resp.ready := true.B when(cycle_reg === 0.U) { io.cmdResp.valid := true.B io.cmdResp.bits.rob_id := rob_id_reg diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index fc02a4fd..3a4790f4 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -36,7 +36,6 @@ class AccPipe(val b: GlobalConfig) extends Module { // Control and status signals val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) val is_acc = Input(Bool()) - // in AccPipe IO bundle, add: val target_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) val busy = Output(Bool()) @@ -46,7 +45,6 @@ class AccPipe(val b: GlobalConfig) extends Module { // Latched transaction context // --------------------------------------------------------------------------- val curBankId = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - // target bank id for routing (combinational) val opIsRead = RegInit(false.B) // true: read transaction; false: write transaction val opIsAccum = RegInit(false.B) // true only for write + wmode=1 @@ -61,12 +59,12 @@ class AccPipe(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- // FSM // --------------------------------------------------------------------------- - val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = Enum(5) - val state = RegInit(s_idle) + val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = + Enum(5) + val state = RegInit(s_idle) io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) - - io.busy := (state =/= s_idle) + io.busy := (state =/= s_idle) // --------------------------------------------------------------------------- // Defaults (avoid multi-drive) @@ -97,9 +95,10 @@ class AccPipe(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- private def maskedAccumulate(oldU: UInt, addU: UInt, maskV: Vec[Bool]): UInt = { val segW = b.memDomain.bankWidth / b.memDomain.bankMaskLen - // Optional safety: if not divisible, elaboration will still succeed but behavior is wrong. - // You can assert if you want: - require(b.memDomain.bankWidth % b.memDomain.bankMaskLen == 0, "bankWidth must be divisible by bankMaskLen") + require( + b.memDomain.bankWidth % b.memDomain.bankMaskLen == 0, + "bankWidth must be divisible by bankMaskLen" + ) val oldVec = oldU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) val addVec = addU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) @@ -111,7 +110,9 @@ class AccPipe(val b: GlobalConfig) extends Module { resVec.asUInt } + // Read req ready is driven by downstream read-req ready (when active) io.read.req.ready := io.sramRead.req.ready + // --------------------------------------------------------------------------- // FSM behavior // --------------------------------------------------------------------------- @@ -129,10 +130,11 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramRead.req.bits.addr := Mux(writeAccum, io.write.req.bits.addr, io.read.req.bits.addr) io.read.resp <> io.sramRead.resp + // FIX#1: direct write must pass-through addr/data/mask in the SAME cycle io.sramWrite.req.valid := writeDirect - io.sramWrite.req.bits.addr := 0.U - io.sramWrite.req.bits.data := 0.U - io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + io.sramWrite.req.bits.addr := io.write.req.bits.addr + io.sramWrite.req.bits.data := io.write.req.bits.data + io.sramWrite.req.bits.mask := io.write.req.bits.mask io.sramWrite.req.bits.wmode := false.B // Upstream ready is a function of the selected downstream ready @@ -177,12 +179,10 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramRead.resp.ready := true.B when(io.sramRead.resp.fire) { oldData := io.sramRead.resp.bits.data - // Compute result right away and latch resData := maskedAccumulate(io.sramRead.resp.bits.data, latData, latMask) state := s_issue_write_back } }.otherwise { - // Should not happen state := s_idle } } @@ -193,7 +193,7 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramWrite.req.bits.addr := latAddr io.sramWrite.req.bits.data := resData io.sramWrite.req.bits.mask := latMask - io.sramWrite.req.bits.wmode := false.B // IMPORTANT: already accumulated in AccPipe + io.sramWrite.req.bits.wmode := false.B when(io.sramWrite.req.fire) { state := s_wait_write_resp @@ -207,18 +207,13 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramWrite.resp.ready := io.write.resp.ready when(io.sramWrite.resp.fire) { - // Done opIsAccum := false.B state := s_idle } } is(s_wait_direct_write_resp) { - // Direct write: forward resp - io.sramWrite.req.valid := true.B - io.sramWrite.req.bits.addr := io.write.req.bits.addr - io.sramWrite.req.bits.data := io.write.req.bits.data - io.sramWrite.req.bits.mask := io.write.req.bits.mask + // FIX#2: do NOT re-issue write req here; only wait/forward the response io.write.resp.valid := io.sramWrite.resp.valid io.write.resp.bits.ok := io.sramWrite.resp.bits.ok io.sramWrite.resp.ready := io.write.resp.ready @@ -228,4 +223,4 @@ class AccPipe(val b: GlobalConfig) extends Module { } } } -} +} \ No newline at end of file diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index de58511e..9e09ea33 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -2,7 +2,6 @@ package framework.memdomain.midend import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters import framework.top.GlobalConfig import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public} @@ -36,123 +35,196 @@ class MemMidend(val b: GlobalConfig) extends Module { class MappingTableEntry extends Bundle { val valid = Bool() val isRead = Bool() - val id = UInt(log2Ceil(math.max(totalBallRead, totalBallWrite)).W) + val id = UInt(log2Ceil(math.max(1, math.max(totalBallRead, totalBallWrite))).W) } val mappingTable = RegInit(VecInit(Seq.fill(numChannels)(0.U.asTypeOf(new MappingTableEntry)))) - def isAllocated(isRead: Bool, id: UInt): Bool = - mappingTable.map(entry => entry.valid && entry.isRead === isRead && entry.id === id).reduce(_ || _) - // ----------------------------------------------------------------------------- - // Core logic: multi-channel parallel allocation + // Core logic: allocate + same-cycle bypass routing // ----------------------------------------------------------------------------- + private val chSelW = math.max(1, log2Ceil(numChannels)) + + // Free mask at cycle start + val freeMask0 = VecInit(mappingTable.map(!_.valid)).asUInt + + // Detect existing mappings (logical port -> physical channel) + val readMapped = Wire(Vec(totalBallRead, Bool())) + val readMappedCh = Wire(Vec(totalBallRead, UInt(chSelW.W))) + for (rid <- 0 until totalBallRead) { + val hits = VecInit((0 until numChannels).map { ch => + mappingTable(ch).valid && mappingTable(ch).isRead && (mappingTable(ch).id === rid.U) + }) + readMapped(rid) := hits.asUInt.orR + if (numChannels == 1) readMappedCh(rid) := 0.U else readMappedCh(rid) := OHToUInt(hits) + } - // 1. Get which channels are free at cycle start (Bitmap) - // use wire to propagate allocation within the cycle - val initialFreeMask = VecInit(mappingTable.map(!_.valid)).asUInt - - var currentFreeMask = initialFreeMask - - // Define request object collection for unified iteration - // Contains: (ReqValid, IsRead, ID, ReqReadyPtr) - case class RequestCandidate( - valid: Bool, - isRead: Bool, - id: Int, - ready: Bool) - - val candidates = scala.collection.mutable.ArrayBuffer[RequestCandidate]() - - // Collect read requests - for (i <- 0 until totalBallRead) { - // Default value - io.balldomain.bankRead(i).io.req.ready := !mappingTable.map(_.valid).reduce(_ || _) - io.balldomain.bankRead(i).io.resp.valid := false.B - io.balldomain.bankRead(i).io.resp.bits := DontCare - - candidates += RequestCandidate( - io.balldomain.bankRead(i).io.req.valid, - true.B, - i, - io.balldomain.bankRead(i).io.req.ready - ) + val writeMapped = Wire(Vec(totalBallWrite, Bool())) + val writeMappedCh = Wire(Vec(totalBallWrite, UInt(chSelW.W))) + for (wid <- 0 until totalBallWrite) { + val hits = VecInit((0 until numChannels).map { ch => + mappingTable(ch).valid && !mappingTable(ch).isRead && (mappingTable(ch).id === wid.U) + }) + writeMapped(wid) := hits.asUInt.orR + if (numChannels == 1) writeMappedCh(wid) := 0.U else writeMappedCh(wid) := OHToUInt(hits) } - // Collect write requests - for (i <- 0 until totalBallWrite) { - io.balldomain.bankWrite(i).io.req.ready := !mappingTable.map(_.valid).reduce(_ || _) - io.balldomain.bankWrite(i).io.resp.valid := false.B - io.balldomain.bankWrite(i).io.resp.bits := DontCare + // Allocate unmapped requests onto free channels (combinational chaining, deterministic priority) + val readAlloc = Wire(Vec(totalBallRead, Bool())) + val readAllocCh = Wire(Vec(totalBallRead, UInt(chSelW.W))) + for (i <- 0 until totalBallRead) { readAlloc(i) := false.B; readAllocCh(i) := 0.U } + + val writeAlloc = Wire(Vec(totalBallWrite, Bool())) + val writeAllocCh = Wire(Vec(totalBallWrite, UInt(chSelW.W))) + for (i <- 0 until totalBallWrite) { writeAlloc(i) := false.B; writeAllocCh(i) := 0.U } + + var freeMask = freeMask0 + + for (rid <- 0 until totalBallRead) { + val canAlloc = io.balldomain.bankRead(rid).io.req.valid && !readMapped(rid) && freeMask.orR + val chosenCh = if (numChannels == 1) 0.U(chSelW.W) else PriorityEncoder(freeMask) + readAlloc(rid) := canAlloc + readAllocCh(rid) := chosenCh + freeMask = Mux(canAlloc, freeMask & ~(1.U(numChannels.W) << chosenCh), freeMask) + } + + for (wid <- 0 until totalBallWrite) { + val canAlloc = io.balldomain.bankWrite(wid).io.req.valid && !writeMapped(wid) && freeMask.orR + val chosenCh = if (numChannels == 1) 0.U(chSelW.W) else PriorityEncoder(freeMask) + writeAlloc(wid) := canAlloc + writeAllocCh(wid) := chosenCh + freeMask = Mux(canAlloc, freeMask & ~(1.U(numChannels.W) << chosenCh), freeMask) + } - candidates += RequestCandidate( - io.balldomain.bankWrite(i).io.req.valid, - false.B, - i, - io.balldomain.bankWrite(i).io.req.ready + // ----------------------------------------------------------------------------- + // Backend Connection (static LHS, no dynamic LHS assigns) + // ----------------------------------------------------------------------------- + for (ch <- 0 until numChannels) { + io.mem_req(ch).read.req.valid := false.B + io.mem_req(ch).read.req.bits := DontCare + io.mem_req(ch).read.resp.ready := true.B + io.mem_req(ch).write.req.valid := false.B + io.mem_req(ch).write.req.bits := DontCare + io.mem_req(ch).write.resp.ready := true.B + io.mem_req(ch).bank_id := 0.U + } + + // Default resp to ports (each port gets muxed resp from its selected channel) + for (rid <- 0 until totalBallRead) { + io.balldomain.bankRead(rid).io.resp.valid := false.B + io.balldomain.bankRead(rid).io.resp.bits := DontCare + } + for (wid <- 0 until totalBallWrite) { + io.balldomain.bankWrite(wid).io.resp.valid := false.B + io.balldomain.bankWrite(wid).io.resp.bits := DontCare + } + + // Per-port selection: mapped channel wins; otherwise same-cycle allocated channel + val readActive = Wire(Vec(totalBallRead, Bool())) + val readSelCh = Wire(Vec(totalBallRead, UInt(chSelW.W))) + for (rid <- 0 until totalBallRead) { + readActive(rid) := readMapped(rid) || readAlloc(rid) + readSelCh(rid) := Mux(readMapped(rid), readMappedCh(rid), readAllocCh(rid)) + + val mappedReady = io.mem_req(readMappedCh(rid)).read.req.ready + val allocReady = io.mem_req(readAllocCh(rid)).read.req.ready + io.balldomain.bankRead(rid).io.req.ready := Mux( + readMapped(rid), + mappedReady, + Mux(readAlloc(rid), allocReady, false.B) ) + io.balldomain.bankRead(rid).io.resp.valid := readActive(rid) && io.mem_req(readSelCh(rid)).read.resp.valid + io.balldomain.bankRead(rid).io.resp.bits := io.mem_req(readSelCh(rid)).read.resp.bits } - for (cand <- candidates) { - val needsAlloc = cand.valid && !isAllocated(cand.isRead, cand.id.U) - val hasSpace = currentFreeMask.orR // 检查当前掩码中是否还有1 + val writeActive = Wire(Vec(totalBallWrite, Bool())) + val writeSelCh = Wire(Vec(totalBallWrite, UInt(chSelW.W))) + for (wid <- 0 until totalBallWrite) { + writeActive(wid) := writeMapped(wid) || writeAlloc(wid) + writeSelCh(wid) := Mux(writeMapped(wid), writeMappedCh(wid), writeAllocCh(wid)) + + val mappedReady = io.mem_req(writeMappedCh(wid)).write.req.ready + val allocReady = io.mem_req(writeAllocCh(wid)).write.req.ready + io.balldomain.bankWrite(wid).io.req.ready := Mux( + writeMapped(wid), + mappedReady, + Mux(writeAlloc(wid), allocReady, false.B) + ) - when(needsAlloc && hasSpace) { - // Find lowest '1' in current mask (first free channel) - val allocIdx = PriorityEncoder(currentFreeMask) + io.balldomain.bankWrite(wid).io.resp.valid := writeActive(wid) && io.mem_req(writeSelCh(wid)).write.resp.valid + io.balldomain.bankWrite(wid).io.resp.bits := io.mem_req(writeSelCh(wid)).write.resp.bits + } - mappingTable(allocIdx).valid := true.B - mappingTable(allocIdx).isRead := cand.isRead - mappingTable(allocIdx).id := cand.id.U + // Per-channel serving: mapped first; if unmapped, allow same-cycle allocated request to bypass + val chServeReadMapped = Wire(Vec(numChannels, Bool())) + val chServeWriteMapped = Wire(Vec(numChannels, Bool())) + for (ch <- 0 until numChannels) { + chServeReadMapped(ch) := mappingTable(ch).valid && mappingTable(ch).isRead + chServeWriteMapped(ch) := mappingTable(ch).valid && !mappingTable(ch).isRead + } - cand.ready := true.B - } + val chServeReadAlloc = Wire(Vec(numChannels, Bool())) + val chServeWriteAlloc = Wire(Vec(numChannels, Bool())) + val chAllocReadId = Wire(Vec(numChannels, UInt(log2Ceil(math.max(1, totalBallRead)).W))) + val chAllocWriteId = Wire(Vec(numChannels, UInt(log2Ceil(math.max(1, totalBallWrite)).W))) + for (ch <- 0 until numChannels) { + chServeReadAlloc(ch) := false.B + chServeWriteAlloc(ch) := false.B + chAllocReadId(ch) := 0.U + chAllocWriteId(ch) := 0.U + } - // Key step: update mask, clear allocated bit - // Logic generates hardware: next request sees current Mask minus allocIdx - // Note: PriorityEncoder and shift operations are hardware logic - val allocIdxWire = PriorityEncoder(currentFreeMask) - // If needsAlloc is true, clear that bit; otherwise keep unchanged - val nextMask = Mux(needsAlloc && hasSpace, currentFreeMask & ~(1.U(numChannels.W) << allocIdxWire), currentFreeMask) + for (rid <- 0 until totalBallRead) { + when(readAlloc(rid)) { + chServeReadAlloc(readAllocCh(rid)) := true.B + chAllocReadId(readAllocCh(rid)) := rid.U + } + } + for (wid <- 0 until totalBallWrite) { + when(writeAlloc(wid)) { + chServeWriteAlloc(writeAllocCh(wid)) := true.B + chAllocWriteId(writeAllocCh(wid)) := wid.U + } + } - currentFreeMask = nextMask + for (ch <- 0 until numChannels) { + val serveMapped = mappingTable(ch).valid + val serveRead = chServeReadMapped(ch) || (!serveMapped && chServeReadAlloc(ch)) + val serveWrite = chServeWriteMapped(ch) || (!serveMapped && chServeWriteAlloc(ch)) + + when(serveRead) { + val ridSel = Mux(chServeReadMapped(ch), mappingTable(ch).id, chAllocReadId(ch)) + + io.mem_req(ch).read.req.valid := io.balldomain.bankRead(ridSel).io.req.valid + io.mem_req(ch).read.req.bits := io.balldomain.bankRead(ridSel).io.req.bits + io.mem_req(ch).read.resp.ready := io.balldomain.bankRead(ridSel).io.resp.ready + io.mem_req(ch).bank_id := io.balldomain.bankRead(ridSel).bank_id + }.elsewhen(serveWrite) { + val widSel = Mux(chServeWriteMapped(ch), mappingTable(ch).id, chAllocWriteId(ch)) + + io.mem_req(ch).write.req.valid := io.balldomain.bankWrite(widSel).io.req.valid + io.mem_req(ch).write.req.bits := io.balldomain.bankWrite(widSel).io.req.bits + io.mem_req(ch).write.resp.ready := io.balldomain.bankWrite(widSel).io.resp.ready + io.mem_req(ch).bank_id := io.balldomain.bankWrite(widSel).bank_id + } } - // ----------------------------------------------------------------------------- - // Backend Connection - // ----------------------------------------------------------------------------- - for (i <- 0 until numChannels) { - //Default values - io.mem_req(i).read.req.valid := false.B - io.mem_req(i).read.req.bits := DontCare - io.mem_req(i).read.resp.ready := true.B - io.mem_req(i).write.req.valid := false.B - io.mem_req(i).write.req.bits := DontCare - io.mem_req(i).write.resp.ready := true.B - io.mem_req(i).bank_id := 0.U - - val entry = mappingTable(i) - - // Only connect when entry is valid - when(entry.valid) { - - val ballRead = io.balldomain.bankRead(entry.id).io - val ballWrite = io.balldomain.bankWrite(entry.id).io - val rbank_id = io.balldomain.bankRead(entry.id).bank_id - val wbank_id = io.balldomain.bankWrite(entry.id).bank_id - - when(entry.isRead) { - io.mem_req(i).read <> ballRead - io.mem_req(i).bank_id := rbank_id - io.mem_req(i).read.req.valid := RegNext(ballRead.req.valid) - io.mem_req(i).read.req.bits := RegNext(ballRead.req.bits) - }.otherwise { - io.mem_req(i).write <> ballWrite - io.mem_req(i).bank_id := wbank_id - io.mem_req(i).write.req.valid := RegNext(ballWrite.req.valid) - io.mem_req(i).write.req.bits := RegNext(ballWrite.req.bits) - } + // Commit mappingTable only when request actually fires into backend + for (rid <- 0 until totalBallRead) { + when(readAlloc(rid) && io.balldomain.bankRead(rid).io.req.fire) { + val ch = readAllocCh(rid) + mappingTable(ch).valid := true.B + mappingTable(ch).isRead := true.B + mappingTable(ch).id := rid.U + } + } + for (wid <- 0 until totalBallWrite) { + when(writeAlloc(wid) && io.balldomain.bankWrite(wid).io.req.fire) { + val ch = writeAllocCh(wid) + mappingTable(ch).valid := true.B + mappingTable(ch).isRead := false.B + mappingTable(ch).id := wid.U } } @@ -166,7 +238,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.frontend.bankWrite.bank_id ) - //Mapping table release + // Mapping table release for (i <- 0 until numChannels) { val releaseCounter = RegInit(0.U(5.W)) @@ -181,7 +253,8 @@ class MemMidend(val b: GlobalConfig) extends Module { mappingTable(i).isRead := false.B mappingTable(i).id := 0.U } - + }.otherwise { + releaseCounter := 0.U } } -} +} \ No newline at end of file From a51f257ab761b0c8cb51c7bc5a5ec7c75eb3a18d Mon Sep 17 00:00:00 2001 From: SJM946 Date: Tue, 10 Feb 2026 10:14:26 +0800 Subject: [PATCH 087/238] [arch] Remove acc config inst, add vbank config inst, rewrite memBankend/accPipe and add mappingtable for vbank to pbank(acc functions not currently implemented) --- .../toy/balldomain/DomainDecoder.scala | 2 +- .../toy/balldomain/bbus/busRegister.scala | 6 +- .../balldomain/prototype/relu/Relu.scala | 10 +- .../prototype/transpose/Transpose.scala | 96 ++++--- .../prototype/transpose/TransposeBall.scala | 1 - .../scala/framework/memdomain/MemDomain.scala | 2 +- .../memdomain/backend/MemBackend.scala | 259 +++++++----------- .../memdomain/backend/accpipe/AccPipe.scala | 200 ++------------ .../memdomain/frontend/MemFrontend.scala | 6 +- .../cmd_channel/decoder/DomainDecoder.scala | 2 +- .../outside_channel/MemConfiger.scala | 28 +- .../frontend/outside_channel/MemLoader.scala | 2 +- .../outside_channel/dma/StreamReader.scala | 41 ++- .../memdomain/midend/MemMidend.scala | 6 +- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 6 +- .../src/CTest/toy/vecunit_matmul_ones.c | 8 +- 16 files changed, 222 insertions(+), 453 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 692ef5b9..930bf3f6 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -71,7 +71,7 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { func7, ball_default_decode, Array( - MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), + MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs2(7, 0), rs2(15, 8), 0.U, rs2(63, 16)), RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 1.U, rs2(63, 16)), TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 4b5981fb..4defb441 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -19,10 +19,10 @@ class BBusModule(b: GlobalConfig) b, b.ballDomain.ballIdMappings.map { mapping => val ballGenerator: () => HasBlink with Module = mapping.ballName match { - case "VecBall" => () => new VecBall(b) - case "ReluBall" => () => new ReluBall(b) + case "VecBall" => () => new VecBall(b) + case "ReluBall" => () => new ReluBall(b) case "TransposeBall" => () => new TransposeBall(b) - case name => throw new IllegalArgumentException(s"Unknown ball name: $name") + case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 2f80e37e..d70b3e67 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -124,7 +124,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { is(sRead) { io.bankRead(0).io.resp.ready := true.B - io.bankRead(0).io.req.valid := (readCounter < InputNum.U) + io.bankRead(0).io.req.valid := (readCounter < InputNum.U) io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter when(io.bankRead(0).io.req.fire) { @@ -145,7 +145,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { respCounter := respCounter + 1.U } - when(respCounter === (InputNum-1).U) { + when(respCounter === (InputNum - 1).U) { state := sWrite writeDataReg := Cat((0 until InputNum).reverse.map(j => regArray(0)(j))) for (i <- 0 until b.memDomain.bankMaskLen) { @@ -161,8 +161,8 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { io.bankWrite(0).io.req.bits.addr := waddr_reg + writeCounter io.bankWrite(0).io.req.bits.data := writeDataReg io.bankWrite(0).io.req.bits.mask := writeMaskReg - io.bankWrite(0).io.resp.ready := true.B - + io.bankWrite(0).io.resp.ready := true.B + when(io.bankWrite(0).io.req.fire) { when(writeCounter === (InputNum - 1).U) { state := complete @@ -183,7 +183,7 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { iterCnt := iterCnt + 1.U } } - state := idle + state := idle } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index cb09d024..c9eb6a7f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -47,30 +47,29 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).ball_id := 0.U } -val idle :: compute :: Nil = Enum(2) - val state = RegInit(idle) + val idle :: compute :: Nil = Enum(2) + val state = RegInit(idle) // Matrix storage register (veclane x veclane) - val regArray = Reg(Vec(2*InputNum, Vec(InputNum, UInt(inputWidth.W)))) + val regArray = Reg(Vec(2 * InputNum, Vec(InputNum, UInt(inputWidth.W)))) // Counters - val readCounter = RegInit(0.U(10.W)) - val respCounter = RegInit(0.U(10.W)) - val writeCounter = RegInit(0.U(10.W)) + val readCounter = RegInit(0.U(10.W)) + val respCounter = RegInit(0.U(10.W)) + val writeCounter = RegInit(0.U(10.W)) val respWaitcounter = RegInit(0.U(10.W)) - val writeHeadptr = RegInit(0.U(10.W)) - val writeTailptr = RegInit(0.U(10.W)) + val writeHeadptr = RegInit(0.U(10.W)) + val writeTailptr = RegInit(0.U(10.W)) // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(10.W)) + val robid_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(10.W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val raddr_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(10.W)) val write_iter_reg = RegInit(0.U(10.W)) - val mode_reg = RegInit(0.U(1.W)) - + val mode_reg = RegInit(0.U(1.W)) // Precompute write data val writeDataReg = Reg(UInt(bankWidth.W)) @@ -104,11 +103,11 @@ val idle :: compute :: Nil = Enum(2) io.cmdReq.ready := state === idle io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := rob_id_reg - - when(state === idle && io.cmdReq.fire){ - state := compute - readCounter := 0.U - respCounter := 0.U + + when(state === idle && io.cmdReq.fire) { + state := compute + readCounter := 0.U + respCounter := 0.U respWaitcounter := io.cmdReq.bits.cmd.iter + respWaitcounter robid_reg := io.cmdReq.bits.rob_id @@ -120,12 +119,12 @@ val idle :: compute :: Nil = Enum(2) mode_reg := io.cmdReq.bits.cmd.special(0) } // read req - when(((mode_reg === 1.U) &&(state === compute) && RegNext(io.bankWrite(0).io.req.ready))|| - ((mode_reg === 0.U) && (state === compute))){ - readCounter := readCounter + 1.U - io.bankRead(0).io.req.valid := readCounter < iter_reg - io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter - state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) + when(((mode_reg === 1.U) && (state === compute) && RegNext(io.bankWrite(0).io.req.ready)) || + ((mode_reg === 0.U) && (state === compute))) { + readCounter := readCounter + 1.U + io.bankRead(0).io.req.valid := readCounter < iter_reg + io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter + state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) } io.cmdResp.valid := (readCounter >= (iter_reg - 1.U)) && (state === compute) io.cmdResp.bits.rob_id := robid_reg @@ -133,42 +132,49 @@ val idle :: compute :: Nil = Enum(2) // read resp io.bankRead(0).io.resp.ready := true.B val dataWord = io.bankRead(0).io.resp.bits.data - val row = respCounter(4,0) - when(io.bankRead(0).io.resp.fire && respWaitcounter > 0.U){ + val row = respCounter(4, 0) + when(io.bankRead(0).io.resp.fire && respWaitcounter > 0.U) { for (col <- 0 until InputNum) { val hi = (col + 1) * inputWidth - 1 val lo = col * inputWidth regArray(row)(col) := dataWord(hi, lo) } respCounter := Mux(respCounter === iter_reg - 1.U, 0.U, respCounter + 1.U) - writeHeadptr := Mux(writeHeadptr === 2.U* InputNum.U - 1.U, 0.U, writeHeadptr + 1.U) - respWaitcounter := Mux(state === idle && io.cmdReq.fire, io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, respWaitcounter - 1.U) + writeHeadptr := Mux(writeHeadptr === 2.U * InputNum.U - 1.U, 0.U, writeHeadptr + 1.U) + respWaitcounter := Mux( + state === idle && io.cmdReq.fire, + io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, + respWaitcounter - 1.U + ) } // write req - val wreg = RegInit(0.U(10.W)) + val wreg = RegInit(0.U(10.W)) val array_full = ((writeTailptr < InputNum.U) && (writeHeadptr >= InputNum.U)) || - ((writeTailptr >= InputNum.U) && (writeHeadptr < InputNum.U)) - when(writeCounter === iter_reg - 1.U){ + ((writeTailptr >= InputNum.U) && (writeHeadptr < InputNum.U)) + when(writeCounter === iter_reg - 1.U) { start_write := false.B - }.elsewhen( array_full && !start_write){ - start_write := true.B - wreg := waddr_reg + }.elsewhen(array_full && !start_write) { + start_write := true.B + wreg := waddr_reg write_iter_reg := iter_reg - }.otherwise{ + }.otherwise { start_write := start_write } - when(start_write){ + when(start_write) { io.bankWrite(0).io.req.valid := true.B io.bankWrite(0).io.req.bits.addr := wreg + writeCounter - io.bankWrite(0).io.req.bits.data := Mux( writeCounter(4) === 0.U, Cat((0 until InputNum).reverse.map(i => regArray(i)(writeCounter(3,0)))) , - Cat((0 until InputNum).reverse.map(i => regArray(i + InputNum)(writeCounter(3,0))))) + io.bankWrite(0).io.req.bits.data := Mux( + writeCounter(4) === 0.U, + Cat((0 until InputNum).reverse.map(i => regArray(i)(writeCounter(3, 0)))), + Cat((0 until InputNum).reverse.map(i => regArray(i + InputNum)(writeCounter(3, 0)))) + ) io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) - writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U,writeCounter + 1.U) - writeTailptr := Mux(writeTailptr === 2.U* InputNum.U - 1.U, 0.U, writeTailptr + 1.U) + writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U, writeCounter + 1.U) + writeTailptr := Mux(writeTailptr === 2.U * InputNum.U - 1.U, 0.U, writeTailptr + 1.U) } - // Status signals - io.status.idle := state === idle + // Status signals + io.status.idle := state === idle io.status.running := state === compute } diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala index 292a1d74..6ce8623f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala @@ -7,7 +7,6 @@ import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} import framework.balldomain.prototype.transpose.Transpose import framework.top.GlobalConfig - @instantiable class TransposeBall(val b: GlobalConfig) extends Module with HasBlink { diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 3f6f4605..b5cff894 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -84,5 +84,5 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite midend.io.mem_req <> backend.io.mem_req - backend.io.acc_config <> frontend.io.acc_config + backend.io.config <> frontend.io.config } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 681e32c5..06901cc4 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -3,21 +3,11 @@ package framework.memdomain.backend import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} - +import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} import framework.memdomain.backend.accpipe.AccPipe -/** - * MemBackend: Backend memory manager - * - * Key changes vs your version: - * 1) Fix MemRequestIO.bank_id direction (should be Input) - * 2) Remove illegal "accPipes.foreach init sram*" multi-driving - * 3) Routing does NOT depend on accPipe.busy (idle same-cycle issue) - * 4) Use accPipe.io.target_bank_id for same-cycle routing - * 5) Add cross read/write conflict assertions based on actual bank requests (valid-level, and fire-level optional) - */ class MemRequestIO(b: GlobalConfig) extends Bundle { val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend val read = Flipped(new SramReadIO(b)) // midend sends read req into backend @@ -29,190 +19,125 @@ class MemBackend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) - val acc_config = Input(UInt(b.memDomain.bankNum.W)) + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val config = Flipped(Decoupled(new MemConfigerIO(b))) }) val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) // ----------------------------------------------------------------------------- - // Midend -> AccPipe + // Mapping table/ Free List + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + val valid = Bool() + val vbank_id = UInt(5.W) + val is_acc = Bool() + val acc_group_id = UInt(3.W) + val channel_id = UInt(log2Ceil(b.memDomain.bankChannel).W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) + + def isAllocated(vbank_id: UInt): Bool = + mappingTable.map(_.vbank_id === vbank_id).reduce(_ || _) + + def addEntry( + vbank_id: UInt, + pbank_id: UInt, + is_acc: Bool, + acc_group_id: UInt + ): Unit = { + val entry = mappingTable(pbank_id) + entry.valid := true.B + entry.vbank_id := vbank_id + entry.is_acc := is_acc + entry.acc_group_id := acc_group_id + } + + def deleteEntry(vbank_id: UInt): Unit = { + val entry = mappingTable(vbank_id) + entry.valid := false.B + entry.vbank_id := 0.U + entry.is_acc := false.B + entry.acc_group_id := 0.U + } + + def getFreePbankId(): UInt = { + val freePbankId = mappingTable.indexWhere(_.valid === false.B) + freePbankId + } + + // ----------------------------------------------------------------------------- + // Default Value // ----------------------------------------------------------------------------- + for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.write <> io.mem_req(i).write accPipes(i).io.read <> io.mem_req(i).read accPipes(i).io.bank_id := io.mem_req(i).bank_id - val bank_id = io.mem_req(i).bank_id - accPipes(i).io.is_acc := io.acc_config(bank_id) + + accPipes(i).io.sramRead.req.ready := true.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare + + accPipes(i).io.sramWrite.req.ready := true.B + accPipes(i).io.sramWrite.resp.valid := false.B + accPipes(i).io.sramWrite.resp.bits := DontCare + + accPipes(i).io.is_acc := false.B } - // ----------------------------------------------------------------------------- - // Create "return path" wires for each AccPipe (bank -> accPipe) - // We drive these wires exactly once in routing logic to avoid multi-drive. - // ----------------------------------------------------------------------------- - val rd_req_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) - val rd_resp_valid = Wire(Vec(b.memDomain.bankChannel, Bool())) - val rd_resp_data = Wire(Vec(b.memDomain.bankChannel, UInt(b.memDomain.bankWidth.W))) - val rd_resp_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) // accPipe -> bank + io.config.ready := true.B - val wr_req_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) - val wr_resp_valid = Wire(Vec(b.memDomain.bankChannel, Bool())) - val wr_resp_ok = Wire(Vec(b.memDomain.bankChannel, Bool())) - val wr_resp_ready = Wire(Vec(b.memDomain.bankChannel, Bool())) // accPipe -> bank + banks.zipWithIndex.foreach { + case (bank, i) => + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := DontCare + bank.io.sramRead.resp.ready := true.B + + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := DontCare + bank.io.sramWrite.resp.ready := true.B - // Defaults: if a pipe is not selected by any bank this cycle, it sees "not ready / no response" - for (i <- 0 until b.memDomain.bankChannel) { - rd_req_ready(i) := false.B - rd_resp_valid(i) := false.B - rd_resp_data(i) := 0.U - wr_req_ready(i) := false.B - wr_resp_valid(i) := false.B - wr_resp_ok(i) := false.B - - // connect accPipe outputs that go to bank - rd_resp_ready(i) := accPipes(i).io.sramRead.resp.ready - wr_resp_ready(i) := accPipes(i).io.sramWrite.resp.ready - - // drive accPipe inputs from routing wires - accPipes(i).io.sramRead.req.ready := rd_req_ready(i) - accPipes(i).io.sramRead.resp.valid := rd_resp_valid(i) - accPipes(i).io.sramRead.resp.bits.data := rd_resp_data(i) - - accPipes(i).io.sramWrite.req.ready := wr_req_ready(i) - accPipes(i).io.sramWrite.resp.valid := wr_resp_valid(i) - accPipes(i).io.sramWrite.resp.bits.ok := wr_resp_ok(i) } // ----------------------------------------------------------------------------- - // Conflict detection (better than original) - // 1) valid-level: if two pipes TRY to access same bank same cycle, assert - // 2) also add read-vs-write cross conflict - // NOTE: if you want fire-level only, see the optional section below. + // Bank Alloc/Release // ----------------------------------------------------------------------------- - for (i <- 0 until b.memDomain.bankChannel) { - for (j <- (i + 1) until b.memDomain.bankChannel) { - val wi = accPipes(i).io.sramWrite.req.valid - val wj = accPipes(j).io.sramWrite.req.valid - val ri = accPipes(i).io.sramRead.req.valid - val rj = accPipes(j).io.sramRead.req.valid - val bi = accPipes(i).io.target_bank_id - val bj = accPipes(j).io.target_bank_id + when(io.config.valid && !io.config.bits.is_acc) { + when(io.config.bits.alloc) { + val pbank_id = getFreePbankId() + addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_acc, 0.U) + }.otherwise { + deleteEntry(io.config.bits.vbank_id) + } + } - when(wi && wj) { - assert(bi =/= bj, s"[MemBackend] WRITE bank conflict between pipe $i and $j") - } - when(ri && rj) { - assert(bi =/= bj, s"[MemBackend] READ bank conflict between pipe $i and $j") - } - when(wi && rj) { - assert(bi =/= bj, s"[MemBackend] WRITE($i) vs READ($j) bank conflict") - } - when(ri && wj) { - assert(bi =/= bj, s"[MemBackend] READ($i) vs WRITE($j) bank conflict") + when(io.config.valid && io.config.bits.is_acc) {} + + for (i <- 0 until b.memDomain.bankChannel) { + for (j <- 0 until b.memDomain.bankNum) { + when((io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid) && + mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id)) { + mappingTable(j).channel_id := i.U } } } // ----------------------------------------------------------------------------- - // Bank routing - // For each bank: - // - select at most one write requester (Mux1H) - // - select at most one read requester (Mux1H) - // - connect bank <-> selected accPipe using the per-pipe wires + // Connect AccPipe and Banks // ----------------------------------------------------------------------------- banks.zipWithIndex.foreach { - case (bank, bankIdx) => - val bankId = bankIdx.U(log2Up(b.memDomain.bankNum).W) - - // ========================================================= - // WRITE routing (req: combinational; resp: owner-registered) - // ========================================================= - val wMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) - for (i <- 0 until b.memDomain.bankChannel) { - wMatch(i) := (accPipes(i).io.target_bank_id === bankId) && - accPipes(i).io.sramWrite.req.valid + case (bank, pBankId) => + accPipes.zipWithIndex.foreach { + case (accPipe, accPipeId) => + when(mappingTable(pBankId).valid && (mappingTable(pBankId).channel_id === accPipeId.U)) { + bank.io.sramRead <> accPipe.io.sramRead + bank.io.sramWrite <> accPipe.io.sramWrite + + } } - val wHas = wMatch.asUInt.orR - val wSel = OHToUInt(wMatch) - assert(PopCount(wMatch) <= 1.U, s"[MemBackend] More than one WRITE match to bank $bankIdx") - - // owner regs for write resp - val wOwnerValid = RegInit(false.B) - val wOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) - - // default bank write req - bank.io.sramWrite.req.valid := false.B - bank.io.sramWrite.req.bits := 0.U.asTypeOf(bank.io.sramWrite.req.bits) - - // issue req from selected pipe - when(wHas) { - bank.io.sramWrite.req.valid := true.B - bank.io.sramWrite.req.bits := Mux1H(wMatch, accPipes.map(_.io.sramWrite.req.bits)) - // ready to selected pipe - wr_req_ready(wSel) := bank.io.sramWrite.req.ready - - when(bank.io.sramWrite.req.fire) { - wOwnerValid := true.B - wOwnerIdx := wSel - } - } - - // resp routes by owner (NOT by wHas) - // drive selected pipe resp wires - when(wOwnerValid) { - wr_resp_valid(wOwnerIdx) := bank.io.sramWrite.resp.valid - wr_resp_ok(wOwnerIdx) := bank.io.sramWrite.resp.bits.ok - } - // ready from owner pipe - bank.io.sramWrite.resp.ready := Mux(wOwnerValid, wr_resp_ready(wOwnerIdx), false.B) - - when(bank.io.sramWrite.resp.fire && wOwnerValid) { - wOwnerValid := false.B - } - - // ========================================================= - // READ routing (req: combinational; resp: owner-registered) - // ========================================================= - val rMatch = Wire(Vec(b.memDomain.bankChannel, Bool())) - // owner regs for read resp - val rOwnerValid = RegInit(false.B) - val rOwnerIdx = RegInit(0.U(log2Up(b.memDomain.bankChannel).W)) - val canAcceptRead = !rOwnerValid - for (i <- 0 until b.memDomain.bankChannel) { - rMatch(i) := (accPipes(i).io.target_bank_id === bankId) && accPipes(i).io.sramRead.req.valid - } - val rHas = rMatch.asUInt.orR - val rSel = OHToUInt(rMatch) - // stronger safety: at most 1 - assert(PopCount(rMatch) <= 1.U, s"[MemBackend] More than one READ match to bank $bankIdx") - - // default bank read req - bank.io.sramRead.req.valid := false.B - bank.io.sramRead.req.bits := 0.U.asTypeOf(bank.io.sramRead.req.bits) - - // issue req from selected pipe - when(rHas) { - bank.io.sramRead.req.valid := true.B - bank.io.sramRead.req.bits := Mux1H(rMatch, accPipes.map(_.io.sramRead.req.bits)) - // ready to selected pipe - rd_req_ready(rSel) := bank.io.sramRead.req.ready - - when(bank.io.sramRead.req.fire) { - rOwnerValid := true.B - rOwnerIdx := rSel - } - } - - // resp routes by owner (NOT by rHas) - when(rOwnerValid) { - rd_resp_valid(rOwnerIdx) := bank.io.sramRead.resp.valid - rd_resp_data(rOwnerIdx) := bank.io.sramRead.resp.bits.data - } - // bank sees ready from owner pipe - bank.io.sramRead.resp.ready := Mux(rOwnerValid, rd_resp_ready(rOwnerIdx), false.B) - - /* when(bank.io.sramRead.resp.fire && rOwnerValid) { rOwnerValid := false.B } */ } } diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 3a4790f4..282d198c 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -34,193 +34,25 @@ class AccPipe(val b: GlobalConfig) extends Module { val write = new SramWriteIO(b) // midend -> AccPipe: req in, resp out // Control and status signals - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) - val is_acc = Input(Bool()) - val target_bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val is_acc = Input(Bool()) + + val vbank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val acc_group_id = Output(UInt(2.W)) val busy = Output(Bool()) }) - // --------------------------------------------------------------------------- - // Latched transaction context - // --------------------------------------------------------------------------- - val curBankId = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - - val opIsRead = RegInit(false.B) // true: read transaction; false: write transaction - val opIsAccum = RegInit(false.B) // true only for write + wmode=1 - - val latAddr = RegInit(0.U(log2Ceil(b.memDomain.bankEntries).W)) - val latData = RegInit(0.U(b.memDomain.bankWidth.W)) - val latMask = RegInit(VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B))) - - val oldData = RegInit(0.U(b.memDomain.bankWidth.W)) - val resData = RegInit(0.U(b.memDomain.bankWidth.W)) - - // --------------------------------------------------------------------------- - // FSM - // --------------------------------------------------------------------------- - val s_idle :: s_wait_read_resp :: s_issue_write_back :: s_wait_write_resp :: s_wait_direct_write_resp :: Nil = - Enum(5) - val state = RegInit(s_idle) - - io.target_bank_id := Mux(state === s_idle, io.bank_id, curBankId) - io.busy := (state =/= s_idle) - - // --------------------------------------------------------------------------- - // Defaults (avoid multi-drive) - // --------------------------------------------------------------------------- - // Midend side defaults - io.read.req.ready := false.B - io.read.resp.valid := false.B - io.read.resp.bits.data := 0.U - - io.write.req.ready := false.B - io.write.resp.valid := false.B - io.write.resp.bits.ok := false.B - - // Bank side defaults - io.sramRead.req.valid := false.B - io.sramRead.req.bits.addr := 0.U - io.sramRead.resp.ready := false.B - - io.sramWrite.req.valid := false.B - io.sramWrite.req.bits.addr := 0.U - io.sramWrite.req.bits.data := 0.U - io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) - io.sramWrite.req.bits.wmode := false.B // IMPORTANT: write-back is a normal write - io.sramWrite.resp.ready := false.B - - // --------------------------------------------------------------------------- - // Helpers: masked accumulate (segment-wise) - // --------------------------------------------------------------------------- - private def maskedAccumulate(oldU: UInt, addU: UInt, maskV: Vec[Bool]): UInt = { - val segW = b.memDomain.bankWidth / b.memDomain.bankMaskLen - require( - b.memDomain.bankWidth % b.memDomain.bankMaskLen == 0, - "bankWidth must be divisible by bankMaskLen" - ) - - val oldVec = oldU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) - val addVec = addU.asTypeOf(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) - - val resVec = Wire(Vec(b.memDomain.bankMaskLen, UInt(segW.W))) - for (i <- 0 until b.memDomain.bankMaskLen) { - resVec(i) := Mux(maskV(i), oldVec(i) + addVec(i), oldVec(i)) - } - resVec.asUInt - } - - // Read req ready is driven by downstream read-req ready (when active) - io.read.req.ready := io.sramRead.req.ready - - // --------------------------------------------------------------------------- - // FSM behavior - // --------------------------------------------------------------------------- - switch(state) { - is(s_idle) { - // Priority: write first, then read. - // IMPORTANT: never make req.valid depend on ready/fire; that can create combinational loops. - val writeValid = io.write.req.valid - val writeAccum = writeValid && io.write.req.bits.wmode - val writeDirect = writeValid && !io.write.req.bits.wmode - val readValid = !writeValid && io.read.req.valid - - // Downstream bank requests (valid depends only on upstream valid + state) - io.sramRead.req.valid := writeAccum || readValid - io.sramRead.req.bits.addr := Mux(writeAccum, io.write.req.bits.addr, io.read.req.bits.addr) - io.read.resp <> io.sramRead.resp - - // FIX#1: direct write must pass-through addr/data/mask in the SAME cycle - io.sramWrite.req.valid := writeDirect - io.sramWrite.req.bits.addr := io.write.req.bits.addr - io.sramWrite.req.bits.data := io.write.req.bits.data - io.sramWrite.req.bits.mask := io.write.req.bits.mask - io.sramWrite.req.bits.wmode := false.B - - // Upstream ready is a function of the selected downstream ready - io.write.req.ready := Mux( - writeAccum, - io.sramRead.req.ready, - Mux(writeDirect, io.sramWrite.req.ready, false.B) - ) - - // State transitions + latching on fire - when(writeAccum && io.sramRead.req.fire) { - curBankId := io.bank_id - opIsRead := false.B - opIsAccum := true.B - latAddr := io.write.req.bits.addr - latData := io.write.req.bits.data - latMask := io.write.req.bits.mask - state := s_wait_read_resp - }.elsewhen(writeDirect && io.sramWrite.req.fire) { - curBankId := io.bank_id - opIsRead := false.B - opIsAccum := false.B - latAddr := io.write.req.bits.addr - latData := io.write.req.bits.data - latMask := io.write.req.bits.mask - state := s_wait_direct_write_resp - } - } - - is(s_wait_read_resp) { - when(opIsRead) { - // Pure read: directly forward bank resp -> midend resp with proper handshake - io.read.resp.valid := io.sramRead.resp.valid - io.read.resp.bits.data := io.sramRead.resp.bits.data - io.sramRead.resp.ready := io.read.resp.ready - - when(io.sramRead.resp.fire) { - state := s_idle - } - }.elsewhen(opIsAccum) { - // Accum path: always accept the bank resp (store old data), no dependency on midend ready here - io.sramRead.resp.ready := true.B - when(io.sramRead.resp.fire) { - oldData := io.sramRead.resp.bits.data - resData := maskedAccumulate(io.sramRead.resp.bits.data, latData, latMask) - state := s_issue_write_back - } - }.otherwise { - state := s_idle - } - } - - is(s_issue_write_back) { - // Issue bank write-back for accumulated result - io.sramWrite.req.valid := true.B - io.sramWrite.req.bits.addr := latAddr - io.sramWrite.req.bits.data := resData - io.sramWrite.req.bits.mask := latMask - io.sramWrite.req.bits.wmode := false.B - - when(io.sramWrite.req.fire) { - state := s_wait_write_resp - } - } - - is(s_wait_write_resp) { - // Forward bank write resp to midend write resp - io.write.resp.valid := io.sramWrite.resp.valid - io.write.resp.bits.ok := io.sramWrite.resp.bits.ok - io.sramWrite.resp.ready := io.write.resp.ready - - when(io.sramWrite.resp.fire) { - opIsAccum := false.B - state := s_idle - } - } - - is(s_wait_direct_write_resp) { - // FIX#2: do NOT re-issue write req here; only wait/forward the response - io.write.resp.valid := io.sramWrite.resp.valid - io.write.resp.bits.ok := io.sramWrite.resp.bits.ok - io.sramWrite.resp.ready := io.write.resp.ready + val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val acc_group_id_reg = RegInit(0.U(2.W)) + io.vbank_id := vbank_id_reg + io.acc_group_id := acc_group_id_reg - when(io.sramWrite.resp.fire) { - state := s_idle - } - } + when(io.sramRead.req.valid || io.sramWrite.req.valid) { + vbank_id_reg := io.bank_id + acc_group_id_reg := io.acc_group_id } -} \ No newline at end of file + io.sramRead <> io.read + io.sramWrite <> io.write + io.busy := false.B +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index ffea3e87..5f21d833 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import freechips.rocketchip.tile._ import framework.memdomain.frontend.outside_channel.dma.{StreamReader, StreamWriter} -import framework.memdomain.frontend.outside_channel.{MemConfiger, MemLoader, MemStorer} +import framework.memdomain.frontend.outside_channel.{MemConfiger, MemConfigerIO, MemLoader, MemStorer} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} @@ -46,7 +46,7 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val tl_reader = new TLBundle(edge.bundle) val tl_writer = new TLBundle(edge.bundle) - val acc_config = Output(UInt(b.memDomain.bankNum.W)) + val config = Decoupled(new MemConfigerIO(b)) // Busy signal val busy = Output(Bool()) @@ -73,7 +73,7 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { memDecoder.io.cmd_i.valid := io.global_issue_i.valid memDecoder.io.cmd_i.bits := io.global_issue_i.bits.cmd io.global_issue_i.ready := memDecoder.io.cmd_i.ready - io.acc_config := configer.io.acc_config + io.config <> configer.io.config // ----------------------------------------------------------------------------- // MemDecoder -> MemReservationStation diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index 1124b781..b36053f2 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -74,7 +74,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs1(memAddrLen - 1, 0), rs2(bankIdLen - 1, 0), rs2(9 + bankIdLen, bankIdLen), - rs2(39, 0), + rs2(39 + bankIdLen, bankIdLen), Y ), // mset MVIN_BITPAT -> List( diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 62548bb0..37fdbc99 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -6,34 +6,42 @@ import framework.top.GlobalConfig import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} +class MemConfigerIO(val b: GlobalConfig) extends Bundle { + val vbank_id = Output(UInt(8.W)) + val is_acc = Output(Bool()) + val alloc = Output(Bool()) +} + @instantiable class MemConfiger(val b: GlobalConfig) extends Module { - val rob_id_width = log2Up(b.frontend.rob_entries) - // One bank line bytes - private val line_bytes = b.memDomain.bankWidth / 8 - // We pack/send 16B aligned beats to DMA - private val align_bytes = 16 + val rob_id_width = log2Up(b.frontend.rob_entries) @public val io = IO(new Bundle { val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) val cmdResp = Decoupled(new MemRsComplete(b)) - val acc_config = Output(UInt(b.memDomain.bankNum.W)) + val config = Decoupled(new MemConfigerIO(b)) }) - val acc_config_reg = RegInit(0.U(b.memDomain.bankNum.W)) - when(io.cmdReq.valid) { - acc_config_reg := io.cmdReq.bits.cmd.special(b.memDomain.bankNum - 1, 0) + io.config.bits.is_acc := io.cmdReq.bits.cmd.special(0) + io.config.bits.alloc := io.cmdReq.bits.cmd.special(1) + io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id + io.config.valid := true.B io.cmdResp.valid := true.B io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id }.otherwise { + io.config.bits.is_acc := false.B + io.config.bits.alloc := false.B + io.config.bits.vbank_id := 0.U(8.W) + io.config.valid := false.B + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + } io.cmdReq.ready := true.B - io.acc_config := acc_config_reg } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 78fa55d9..032baaf0 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -26,7 +26,7 @@ class MemLoader(val b: GlobalConfig) extends Module { }) val s_idle :: s_dma_req :: s_dma_wait :: s_done :: Nil = Enum(4) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index aae62df5..621d0782 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -13,7 +13,7 @@ class BBReadRequest extends Bundle { val vaddr = UInt(64.W) val len = UInt(16.W) val status = new MStatus - val stride = UInt(10.W) // 暂时不用 + val stride = UInt(10.W) // 暂时不用 } class BBReadResponse(dataWidth: Int) extends Bundle { @@ -43,28 +43,28 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { //------------------------------------------------------------ val s_idle :: s_run :: Nil = Enum(2) - val state = RegInit(s_idle) + val state = RegInit(s_idle) val reqReg = Reg(new BBReadRequest()) val bytesRequested = RegInit(0.U(16.W)) val bytesReceived = RegInit(0.U(16.W)) - val inflight = RegInit(false.B) + val inflight = RegInit(false.B) val read_vaddr = reqReg.vaddr + bytesRequested + val get = edge.Get( fromSource = 0.U, - toAddress = 0.U, - lgSize = log2Ceil(beatBytes).U + toAddress = 0.U, + lgSize = log2Ceil(beatBytes).U )._2 - io.tlb.req.valid := (state === s_run) && - (bytesRequested < reqReg.len) && - !inflight + (bytesRequested < reqReg.len) && + !inflight - io.tlb.req.bits := DontCare + io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := read_vaddr io.tlb.req.bits.passthrough := true.B io.tlb.req.bits.size := 0.U @@ -73,18 +73,17 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.bits.v := false.B io.tlb.req.bits.status := reqReg.status - io.tl.a.valid := io.tlb.resp.valid && - !inflight + !inflight - io.tl.a.bits := get + io.tl.a.bits := get io.tl.a.bits.address := io.tlb.resp.bits.paddr io.tlb.resp.ready := io.tl.a.ready && !inflight when(io.tl.a.fire) { - inflight := true.B + inflight := true.B bytesRequested := bytesRequested + beatBytes.U } @@ -94,38 +93,34 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl.d.ready := io.resp.ready - io.resp.valid := io.tl.d.valid + io.resp.valid := io.tl.d.valid io.resp.bits.data := io.tl.d.bits.data val beatCountResp = bytesReceived >> log2Ceil(beatBytes) - io.resp.bits.addrcounter := beatCountResp(9,0) + io.resp.bits.addrcounter := beatCountResp(9, 0) io.resp.bits.last := (bytesReceived + beatBytes.U >= reqReg.len) when(io.tl.d.fire) { - inflight := false.B + inflight := false.B bytesReceived := bytesReceived + beatBytes.U } - - io.tl.b.ready := true.B io.tl.c.valid := false.B io.tl.e.valid := false.B - - io.req.ready := (state === s_idle) io.busy := (state =/= s_idle) || inflight when(io.req.fire) { - reqReg := io.req.bits + reqReg := io.req.bits bytesRequested := 0.U bytesReceived := 0.U - inflight := false.B - state := s_run + inflight := false.B + state := s_run } when(state === s_run && bytesReceived >= reqReg.len) { diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 9e09ea33..8d8a271c 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -55,7 +55,7 @@ class MemMidend(val b: GlobalConfig) extends Module { val hits = VecInit((0 until numChannels).map { ch => mappingTable(ch).valid && mappingTable(ch).isRead && (mappingTable(ch).id === rid.U) }) - readMapped(rid) := hits.asUInt.orR + readMapped(rid) := hits.asUInt.orR if (numChannels == 1) readMappedCh(rid) := 0.U else readMappedCh(rid) := OHToUInt(hits) } @@ -65,7 +65,7 @@ class MemMidend(val b: GlobalConfig) extends Module { val hits = VecInit((0 until numChannels).map { ch => mappingTable(ch).valid && !mappingTable(ch).isRead && (mappingTable(ch).id === wid.U) }) - writeMapped(wid) := hits.asUInt.orR + writeMapped(wid) := hits.asUInt.orR if (numChannels == 1) writeMappedCh(wid) := 0.U else writeMappedCh(wid) := OHToUInt(hits) } @@ -257,4 +257,4 @@ class MemMidend(val b: GlobalConfig) extends Module { releaseCounter := 0.U } } -} \ No newline at end of file +} diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index 382a4ab0..483bd555 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -15,6 +15,8 @@ #define bb_mem_alloc(bank_id, row, col) bb_mset(0, bank_id, 1, row, col) -#define bb_acc_config(acc_mask) \ - BUCKYBALL_INSTRUCTION_R_R(0, FIELD(acc_mask, 0, 0), BB_MSET_FUNC7) +#define bb_vbank_config(bank_id, is_acc, alloc) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, FIELD(bank_id, 0, 4) | FIELD(is_acc, 5, 5) | FIELD(alloc, 6, 6), \ + BB_MSET_FUNC7) #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index f9ed830b..d8332454 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -23,15 +23,17 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id // bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); - bb_acc_config(0x0000003C); - bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + // bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } From da2d09a11e0efa63ff5f7852e3f16e0e6dc571b1 Mon Sep 17 00:00:00 2001 From: SJM946 Date: Tue, 10 Feb 2026 16:41:12 +0800 Subject: [PATCH 088/238] [arch] Fix memBackend bugs --- .../main/scala/framework/memdomain/backend/MemBackend.scala | 5 +++++ bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 06901cc4..ad01528c 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -135,7 +135,12 @@ class MemBackend(val b: GlobalConfig) extends Module { case (accPipe, accPipeId) => when(mappingTable(pBankId).valid && (mappingTable(pBankId).channel_id === accPipeId.U)) { bank.io.sramRead <> accPipe.io.sramRead + bank.io.sramRead.req.valid := RegNext(accPipe.io.sramRead.req.valid) + bank.io.sramRead.req.bits := RegNext(accPipe.io.sramRead.req.bits) + bank.io.sramWrite <> accPipe.io.sramWrite + bank.io.sramWrite.req.valid := RegNext(accPipe.io.sramWrite.req.valid) + bank.io.sramWrite.req.bits := RegNext(accPipe.io.sramWrite.req.bits) } } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index d8332454..7869cc83 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -51,8 +51,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } int test_ones() { - init_ones_matrix(input_matrix_a, DIM, DIM); - init_ones_matrix(input_matrix_b, DIM, DIM); + init_sequence_matrix(input_matrix_a, DIM, DIM); + init_sequence_matrix(input_matrix_b, DIM, DIM); return run_test("All-ones matrices", input_matrix_a, input_matrix_b, DIM); } From 2b37c89d869f426af77582b2dfa40ef652195023 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 11 Feb 2026 17:33:17 +0800 Subject: [PATCH 089/238] [arch]fix:fix some bugs of transposeball --- .../toy/balldomain/DomainDecoder.scala | 4 +- .../prototype/transpose/Transpose.scala | 314 ++++++++++++------ .../workloads/lib/bbhw/isa/34_transpose.c | 2 +- .../workloads/src/CTest/toy/transpose_test.c | 79 ++++- 4 files changed, 284 insertions(+), 115 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 692ef5b9..f2efb998 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -73,7 +73,9 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { Array( MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 0.U, rs2(63, 16)), RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 1.U, rs2(63, 16)), - TRANSPOSE -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), + // Transpose only reads op1 and writes wr_bank; it does NOT consume op2. + // Enabling op2 here can stall/abort when op2_bank defaults to op1_bank. + TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), CONCAT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index cb09d024..db5d727c 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -3,11 +3,11 @@ package framework.balldomain.prototype.transpose import chisel3._ import chisel3.util._ import chisel3.stage._ -import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.hierarchy.{ instantiable, public } import framework.balldomain.prototype.vector._ -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.balldomain.rs.{ BallRsComplete, BallRsIssue } +import framework.balldomain.blink.{ BallStatus, BankRead, BankWrite } import framework.top.GlobalConfig import framework.balldomain.prototype.transpose.configs.TransposeBallParam @@ -18,11 +18,11 @@ class Transpose(val b: GlobalConfig) extends Module { val inputWidth = ballConfig.inputWidth val bankWidth = b.memDomain.bankWidth - // Get bandwidth from config - val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "TransposeBall") + val ballMapping = b.ballDomain.ballIdMappings + .find(_.ballName == "TransposeBall") .getOrElse(throw new IllegalArgumentException("TransposeBall not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW @public val io = IO(new Bundle { @@ -33,10 +33,11 @@ class Transpose(val b: GlobalConfig) extends Module { val status = new BallStatus }) + // ------------------------------- + // ROB / IDs + // ------------------------------- val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id - } + when(io.cmdReq.fire) { rob_id_reg := io.cmdReq.bits.rob_id } for (i <- 0 until inBW) { io.bankRead(i).rob_id := rob_id_reg @@ -47,43 +48,47 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).ball_id := 0.U } -val idle :: compute :: Nil = Enum(2) + // ------------------------------- + // State + // ------------------------------- + val idle :: compute :: Nil = Enum(2) val state = RegInit(idle) - // Matrix storage register (veclane x veclane) - val regArray = Reg(Vec(2*InputNum, Vec(InputNum, UInt(inputWidth.W)))) + // ------------------------------- + // Ping-pong row buffers: + // 2 blocks, each stores InputNum rows, each row has InputNum elems + // ------------------------------- + val regArray = Reg(Vec(2 * InputNum, Vec(InputNum, UInt(inputWidth.W)))) - // Counters - val readCounter = RegInit(0.U(10.W)) - val respCounter = RegInit(0.U(10.W)) - val writeCounter = RegInit(0.U(10.W)) - val respWaitcounter = RegInit(0.U(10.W)) - val writeHeadptr = RegInit(0.U(10.W)) - val writeTailptr = RegInit(0.U(10.W)) + // which block are we filling / draining + val fillSel = RegInit(0.U(1.W)) // 0 or 1 + val drainSel = RegInit(0.U(1.W)) // 0 or 1 + val blockFull = RegInit(VecInit(Seq.fill(2)(false.B))) + val fillRowIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // 0..InputNum + val drainColIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // 0..InputNum + val draining = RegInit(false.B) - // Instruction registers - val robid_reg = RegInit(0.U(10.W)) - val waddr_reg = RegInit(0.U(10.W)) - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val raddr_reg = RegInit(0.U(10.W)) - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(10.W)) - val write_iter_reg = RegInit(0.U(10.W)) - val mode_reg = RegInit(0.U(1.W)) + // total progress counters (STRICTLY via fire) + val readReqCnt = RegInit(0.U(32.W)) + val readRespCnt = RegInit(0.U(32.W)) + val writeReqCnt = RegInit(0.U(32.W)) + // command fields + val raddr_reg = RegInit(0.U(32.W)) + val waddr_reg = RegInit(0.U(32.W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(32.W)) - // Precompute write data - val writeDataReg = Reg(UInt(bankWidth.W)) - val writeMaskReg = Reg(Vec(b.memDomain.bankMaskLen, UInt(1.W))) - - val start_write = RegInit(false.B) - // SRAM default assignment + // ------------------------------- + // Default IO assignments + // ------------------------------- for (i <- 0 until inBW) { io.bankRead(i).io.req.valid := false.B io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).bank_id := rbank_reg } - for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B io.bankWrite(i).io.req.bits.addr := 0.U @@ -91,84 +96,177 @@ val idle :: compute :: Nil = Enum(2) io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) io.bankWrite(i).io.req.bits.wmode := false.B io.bankWrite(i).io.resp.ready := false.B + io.bankWrite(i).bank_id := wbank_reg } - for (i <- 0 until inBW) { - io.bankRead(i).bank_id := rbank_reg - } - for (i <- 0 until outBW) { - io.bankWrite(i).bank_id := wbank_reg - } - - // cmd interface default assignment - io.cmdReq.ready := state === idle + io.cmdReq.ready := (state === idle) io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := rob_id_reg - - when(state === idle && io.cmdReq.fire){ - state := compute - readCounter := 0.U - respCounter := 0.U - respWaitcounter := io.cmdReq.bits.cmd.iter + respWaitcounter - - robid_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U - wbank_reg := io.cmdReq.bits.cmd.wr_bank - raddr_reg := 0.U - rbank_reg := io.cmdReq.bits.cmd.op1_bank - iter_reg := io.cmdReq.bits.cmd.iter - mode_reg := io.cmdReq.bits.cmd.special(0) - } - // read req - when(((mode_reg === 1.U) &&(state === compute) && RegNext(io.bankWrite(0).io.req.ready))|| - ((mode_reg === 0.U) && (state === compute))){ - readCounter := readCounter + 1.U - io.bankRead(0).io.req.valid := readCounter < iter_reg - io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter - state := Mux((readCounter >= iter_reg - 1.U) && io.cmdResp.ready, idle, state) - } - io.cmdResp.valid := (readCounter >= (iter_reg - 1.U)) && (state === compute) - io.cmdResp.bits.rob_id := robid_reg - - // read resp - io.bankRead(0).io.resp.ready := true.B - val dataWord = io.bankRead(0).io.resp.bits.data - val row = respCounter(4,0) - when(io.bankRead(0).io.resp.fire && respWaitcounter > 0.U){ - for (col <- 0 until InputNum) { - val hi = (col + 1) * inputWidth - 1 - val lo = col * inputWidth - regArray(row)(col) := dataWord(hi, lo) + + // Always consume responses to avoid downstream backpressure deadlocks + io.bankRead(0).io.resp.ready := (state === compute) + io.bankWrite(0).io.resp.ready := (state === compute) + + // ------------------------------- + // Helpers + // ------------------------------- + def blockBase(sel: UInt): UInt = Mux(sel === 0.U, 0.U, InputNum.U) + + // "space available" means at least one block is not full + val hasFreeBlock = !(blockFull(0) && blockFull(1)) + + // ------------------------------- + // Main FSM + // ------------------------------- + switch(state) { + is(idle) { + // reset runtime flags (not mandatory, but keeps things clean) + when(io.cmdReq.fire) { + state := compute + + raddr_reg := 0.U + waddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + wbank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter + + readReqCnt := 0.U + readRespCnt := 0.U + writeReqCnt := 0.U + + fillSel := 0.U + drainSel := 0.U + blockFull := VecInit(Seq.fill(2)(false.B)) + fillRowIdx := 0.U + draining := false.B + drainColIdx := 0.U + } } - respCounter := Mux(respCounter === iter_reg - 1.U, 0.U, respCounter + 1.U) - writeHeadptr := Mux(writeHeadptr === 2.U* InputNum.U - 1.U, 0.U, writeHeadptr + 1.U) - respWaitcounter := Mux(state === idle && io.cmdReq.fire, io.cmdReq.bits.cmd.iter + respWaitcounter - 1.U, respWaitcounter - 1.U) - } - // write req - val wreg = RegInit(0.U(10.W)) - val array_full = ((writeTailptr < InputNum.U) && (writeHeadptr >= InputNum.U)) || - ((writeTailptr >= InputNum.U) && (writeHeadptr < InputNum.U)) - when(writeCounter === iter_reg - 1.U){ - start_write := false.B - }.elsewhen( array_full && !start_write){ - start_write := true.B - wreg := waddr_reg - write_iter_reg := iter_reg - }.otherwise{ - start_write := start_write - } + is(compute) { + // --------------------------- + // 1) READ REQ generation + // Only issue a read when: + // - still need reads (readReqCnt < iter_reg) + // - there is space in buffers (not both blocks full) + // - downstream ready handshake ok (via fire) + // --------------------------- + val wantRead = (readReqCnt < iter_reg) && hasFreeBlock + io.bankRead(0).io.req.valid := wantRead + io.bankRead(0).io.req.bits.addr := raddr_reg + readReqCnt + + when(io.bankRead(0).io.req.fire) { + readReqCnt := readReqCnt + 1.U + } + + // --------------------------- + // 2) READ RESP handling (fill ping-pong block) + // Only advance fillRowIdx/blockFull on resp.fire + // --------------------------- + when(io.bankRead(0).io.resp.fire) { + val dataWord = io.bankRead(0).io.resp.bits.data + val base = blockBase(fillSel) + val rowIdx = base + fillRowIdx + + for (col <- 0 until InputNum) { + val hi = (col + 1) * inputWidth - 1 + val lo = col * inputWidth + regArray(rowIdx)(col) := dataWord(hi, lo) + } + + readRespCnt := readRespCnt + 1.U + + when(fillRowIdx === (InputNum - 1).U) { + // this block becomes full + blockFull(fillSel) := true.B + fillRowIdx := 0.U + + // switch to the other block if it is not full + when(!blockFull(~fillSel)) { + fillSel := ~fillSel + } + }.otherwise { + fillRowIdx := fillRowIdx + 1.U + } + } + + // --------------------------- + // 3) Start draining (writing) when not already draining + // --------------------------- + when(!draining) { + when(blockFull(drainSel) && (writeReqCnt < iter_reg)) { + draining := true.B + drainColIdx := 0.U + }.elsewhen(blockFull(~drainSel) && (writeReqCnt < iter_reg)) { + // if current drainSel block not full but the other is, swap + drainSel := ~drainSel + draining := true.B + drainColIdx := 0.U + } + } - when(start_write){ - io.bankWrite(0).io.req.valid := true.B - io.bankWrite(0).io.req.bits.addr := wreg + writeCounter - io.bankWrite(0).io.req.bits.data := Mux( writeCounter(4) === 0.U, Cat((0 until InputNum).reverse.map(i => regArray(i)(writeCounter(3,0)))) , - Cat((0 until InputNum).reverse.map(i => regArray(i + InputNum)(writeCounter(3,0))))) - io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) - writeCounter := Mux(writeCounter === write_iter_reg - 1.U, 0.U,writeCounter + 1.U) - writeTailptr := Mux(writeTailptr === 2.U* InputNum.U - 1.U, 0.U, writeTailptr + 1.U) + // --------------------------- + // 4) WRITE REQ generation (transpose) + // Only advance drainColIdx / writeReqCnt on req.fire + // --------------------------- + when(draining) { + val base = blockBase(drainSel) + + // compose one output row = one column of input block + val col = drainColIdx + val packed = Cat((0 until InputNum).reverse.map { r => + regArray(base + r.U)(col) + }) + + val hasMoreWrite = (drainColIdx < InputNum.U) && (writeReqCnt < iter_reg) + io.bankWrite(0).io.req.valid := hasMoreWrite + io.bankWrite(0).io.req.bits.addr := waddr_reg + writeReqCnt + io.bankWrite(0).io.req.bits.data := packed + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) + + when(io.bankWrite(0).io.req.fire) { + writeReqCnt := writeReqCnt + 1.U + + when(drainColIdx === (InputNum - 1).U) { + // finished draining this block + draining := false.B + blockFull(drainSel) := false.B + drainSel := ~drainSel + + // move write base address by InputNum for next block’s outputs + waddr_reg := waddr_reg + InputNum.U + // move read base address too, purely optional; we already use readReqCnt for addr + // raddr_reg := raddr_reg + InputNum.U + }.otherwise { + drainColIdx := drainColIdx + 1.U + } + } + } + + // --------------------------- + // 5) Completion condition (NO early complete) + // Must ensure: + // - all read req issued + // - all read resp received + // - all write req issued + // - no blocks full, not draining + // --------------------------- + val done = + (readReqCnt === iter_reg) && + (readRespCnt === iter_reg) && + (writeReqCnt === iter_reg) && + !blockFull(0) && !blockFull(1) && + !draining + + io.cmdResp.valid := done + io.cmdResp.bits.rob_id := rob_id_reg + + when(done && io.cmdResp.fire) { + state := idle + } + } } - // Status signals - io.status.idle := state === idle - io.status.running := state === compute + + io.status.idle := (state === idle) + io.status.running := (state === compute) } diff --git a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c index 88af6fe4..2eb82912 100644 --- a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c +++ b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c @@ -8,6 +8,6 @@ #define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(iter, 0, 15) | FIELD(mode, 16, 16)), BB_TRANSPOSE_FUNC7) + (FIELD(iter, 8, 15) | FIELD(mode, 16, 16)), BB_TRANSPOSE_FUNC7) #endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index c6e4c305..aa002ef6 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -4,9 +4,71 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))) = { + // ---- Cycle 1 ---- + // Row1 + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + // Row2 + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + // Row3 + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + // Row4 + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 2 ---- + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 3 ---- + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + + // ---- Cycle 4 ---- + -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38 +}; +static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { + // Row 1 of A^T (col 1 of A) + -7,-17,-27,-37, -7,-17,-27,-37, -7,-17,-27,-37, -7,-17,-27,-37, + // Row 2 + -6,-16,-26,-36, -6,-16,-26,-36, -6,-16,-26,-36, -6,-16,-26,-36, + // Row 3 + -5,-15,-25,-35, -5,-15,-25,-35, -5,-15,-25,-35, -5,-15,-25,-35, + // Row 4 + -4,-14,-24,-34, -4,-14,-24,-34, -4,-14,-24,-34, -4,-14,-24,-34, + // Row 5 + -3,-13,-23,-33, -3,-13,-23,-33, -3,-13,-23,-33, -3,-13,-23,-33, + // Row 6 + -2,-12,-22,-32, -2,-12,-22,-32, -2,-12,-22,-32, -2,-12,-22,-32, + // Row 7 + -1,-11,-21,-31, -1,-11,-21,-31, -1,-11,-21,-31, -1,-11,-21,-31, + // Row 8 + 0, 10, 20, 30, 0, 10, 20, 30, 0, 10, 20, 30, 0, 10, 20, 30, + // Row 9 + 1, 11, 21, 31, 1, 11, 21, 31, 1, 11, 21, 31, 1, 11, 21, 31, + // Row 10 + 2, 12, 22, 32, 2, 12, 22, 32, 2, 12, 22, 32, 2, 12, 22, 32, + // Row 11 + 3, 13, 23, 33, 3, 13, 23, 33, 3, 13, 23, 33, 3, 13, 23, 33, + // Row 12 + 4, 14, 24, 34, 4, 14, 24, 34, 4, 14, 24, 34, 4, 14, 24, 34, + // Row 13 + 5, 15, 25, 35, 5, 15, 25, 35, 5, 15, 25, 35, 5, 15, 25, 35, + // Row 14 + 6, 16, 26, 36, 6, 16, 26, 36, 6, 16, 26, 36, 6, 16, 26, 36, + // Row 15 + 7, 17, 27, 37, 7, 17, 27, 37, 7, 17, 27, 37, 7, 17, 27, 37, + // Row 16 + 8, 18, 28, 38, 8, 18, 28, 38, 8, 18, 28, 38, 8, 18, 28, 38 +}; static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { @@ -19,16 +81,23 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { bb_fence(); bb_transpose(op1_bank_id, op2_bank_id, size, 0); bb_fence(); + bb_mvout((uintptr_t)b,op2_bank_id, size, 1); } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { hw_transpose(test_name, a, b, size); - return 1; + if (compare_i8_matrices(output_matrix_b, expected_matrix, size, size)) { + printf("%s compare test PASSED\n", test_name); + return 1; + } else { + printf("%s compare test FAILED\n", test_name); + return 0; + } } int test_transpose() { - init_sequence_matrix(input_matrix_a, DIM, DIM); - return run_test("Im2col", input_matrix_a, output_matrix_b, DIM); + // init_sequence_matrix(input_matrix_a, DIM, DIM); + return run_test("transpose", input_matrix_a, output_matrix_b, DIM); } int main() { From 77af77b7eb2eeac05d59482491b9c4c31ac19cdb Mon Sep 17 00:00:00 2001 From: SJM946 Date: Wed, 11 Feb 2026 23:07:43 +0800 Subject: [PATCH 090/238] [arch] Add acc_group_id signal for acc control --- .../scala/examples/toy/ToyBuckyBall.scala | 23 ++++--- .../framework/balldomain/blink/bank.scala | 9 ++- .../balldomain/prototype/relu/Relu.scala | 6 +- .../prototype/transpose/Transpose.scala | 35 +++++----- .../balldomain/prototype/vector/VecUnit.scala | 9 ++- .../memdomain/backend/MemBackend.scala | 48 +++++++------ .../memdomain/backend/accpipe/AccPipe.scala | 13 ---- .../outside_channel/MemConfiger.scala | 69 ++++++++++++++----- .../frontend/outside_channel/MemLoader.scala | 7 +- .../frontend/outside_channel/MemStorer.scala | 7 +- .../memdomain/midend/MemMidend.scala | 10 ++- 11 files changed, 144 insertions(+), 92 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 3269a995..3713f9d9 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -101,18 +101,20 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) // IDs are queued alongside the req bits to keep them aligned through backpressure. for (i <- 0 until totalBallRead) { val bankReadReqWithIds = Wire(Decoupled(new Bundle { - val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) - val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) - val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) - val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) + val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) + val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) + val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) + val acc_group_id = chiselTypeOf(ballDomain.bankRead(i).acc_group_id) + val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) })) - bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid - bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id - bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id - bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id - bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits - ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready + bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid + bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id + bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id + bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id + bankReadReqWithIds.bits.acc_group_id := ballDomain.bankRead(i).acc_group_id + bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits + ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready val bankReadReqQ = Queue(bankReadReqWithIds, 8) @@ -121,6 +123,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id + memDomain.io.ballDomain.bankRead(i).acc_group_id := bankReadReqQ.bits.acc_group_id bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready ballDomain.bankRead(i).io.resp <> memDomain.io.ballDomain.bankRead(i).io.resp diff --git a/arch/src/main/scala/framework/balldomain/blink/bank.scala b/arch/src/main/scala/framework/balldomain/blink/bank.scala index 701a3adc..ff89c2f8 100644 --- a/arch/src/main/scala/framework/balldomain/blink/bank.scala +++ b/arch/src/main/scala/framework/balldomain/blink/bank.scala @@ -21,10 +21,15 @@ trait HasBallId { val ball_id = Input(UInt(log2Up(b.ballDomain.ballNum).W)) } -class BankRead(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId { +trait HasAccGroupId { + val b: GlobalConfig + val acc_group_id = Input(UInt(3.W)) +} + +class BankRead(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId with HasAccGroupId { val io = new SramReadIO(b) } -class BankWrite(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId { +class BankWrite(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId with HasAccGroupId { val io = new SramWriteIO(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index d70b3e67..3addce84 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -86,10 +86,12 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } for (i <- 0 until inBW) { - io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).acc_group_id := 0.U } for (i <- 0 until outBW) { - io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).acc_group_id := 0.U } io.cmdReq.ready := state === idle diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index db5d727c..23265be0 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -3,11 +3,11 @@ package framework.balldomain.prototype.transpose import chisel3._ import chisel3.util._ import chisel3.stage._ -import chisel3.experimental.hierarchy.{ instantiable, public } +import chisel3.experimental.hierarchy.{instantiable, public} import framework.balldomain.prototype.vector._ -import framework.balldomain.rs.{ BallRsComplete, BallRsIssue } -import framework.balldomain.blink.{ BallStatus, BankRead, BankWrite } +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.top.GlobalConfig import framework.balldomain.prototype.transpose.configs.TransposeBallParam @@ -21,6 +21,7 @@ class Transpose(val b: GlobalConfig) extends Module { val ballMapping = b.ballDomain.ballIdMappings .find(_.ballName == "TransposeBall") .getOrElse(throw new IllegalArgumentException("TransposeBall not found in config")) + val inBW = ballMapping.inBW val outBW = ballMapping.outBW @@ -37,7 +38,7 @@ class Transpose(val b: GlobalConfig) extends Module { // ROB / IDs // ------------------------------- val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - when(io.cmdReq.fire) { rob_id_reg := io.cmdReq.bits.rob_id } + when(io.cmdReq.fire)(rob_id_reg := io.cmdReq.bits.rob_id) for (i <- 0 until inBW) { io.bankRead(i).rob_id := rob_id_reg @@ -52,7 +53,7 @@ class Transpose(val b: GlobalConfig) extends Module { // State // ------------------------------- val idle :: compute :: Nil = Enum(2) - val state = RegInit(idle) + val state = RegInit(idle) // ------------------------------- // Ping-pong row buffers: @@ -61,8 +62,8 @@ class Transpose(val b: GlobalConfig) extends Module { val regArray = Reg(Vec(2 * InputNum, Vec(InputNum, UInt(inputWidth.W)))) // which block are we filling / draining - val fillSel = RegInit(0.U(1.W)) // 0 or 1 - val drainSel = RegInit(0.U(1.W)) // 0 or 1 + val fillSel = RegInit(0.U(1.W)) // 0 or 1 + val drainSel = RegInit(0.U(1.W)) // 0 or 1 val blockFull = RegInit(VecInit(Seq.fill(2)(false.B))) val fillRowIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // 0..InputNum val drainColIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // 0..InputNum @@ -88,6 +89,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.resp.ready := false.B io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).acc_group_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B @@ -97,6 +99,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.wmode := false.B io.bankWrite(i).io.resp.ready := false.B io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).acc_group_id := 0.U } io.cmdReq.ready := (state === idle) @@ -122,13 +125,13 @@ class Transpose(val b: GlobalConfig) extends Module { is(idle) { // reset runtime flags (not mandatory, but keeps things clean) when(io.cmdReq.fire) { - state := compute + state := compute - raddr_reg := 0.U - waddr_reg := 0.U - rbank_reg := io.cmdReq.bits.cmd.op1_bank - wbank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter + raddr_reg := 0.U + waddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + wbank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter readReqCnt := 0.U readRespCnt := 0.U @@ -213,7 +216,7 @@ class Transpose(val b: GlobalConfig) extends Module { val base = blockBase(drainSel) // compose one output row = one column of input block - val col = drainColIdx + val col = drainColIdx val packed = Cat((0 until InputNum).reverse.map { r => regArray(base + r.U)(col) }) @@ -229,9 +232,9 @@ class Transpose(val b: GlobalConfig) extends Module { when(drainColIdx === (InputNum - 1).U) { // finished draining this block - draining := false.B + draining := false.B blockFull(drainSel) := false.B - drainSel := ~drainSel + drainSel := ~drainSel // move write base address by InputNum for next block’s outputs waddr_reg := waddr_reg + InputNum.U diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index a7dc5756..74923a14 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -71,9 +71,11 @@ class VecUnit(val b: GlobalConfig) extends Module { io.bankRead(i).io.req <> VecLoadUnit.io.bankReadReq(i) VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).io.resp if (i == 0) { - io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o + io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o + io.bankRead(i).acc_group_id := 0.U } else if (i == 1) { - io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o + io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o + io.bankRead(i).acc_group_id := 0.U } } @@ -91,8 +93,9 @@ class VecUnit(val b: GlobalConfig) extends Module { VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o for (i <- 0 until outBW) { io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) - io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o + i.U + io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o io.bankWrite(i).io.req.bits.wmode := true.B + io.bankWrite(i).acc_group_id := i.U } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index ad01528c..299de8a0 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -9,9 +9,10 @@ import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} import framework.memdomain.backend.accpipe.AccPipe class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val acc_group_id = Output(UInt(3.W)) } @instantiable @@ -61,6 +62,7 @@ class MemBackend(val b: GlobalConfig) extends Module { entry.vbank_id := 0.U entry.is_acc := false.B entry.acc_group_id := 0.U + entry.channel_id := 0.U } def getFreePbankId(): UInt = { @@ -85,7 +87,6 @@ class MemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.sramWrite.resp.valid := false.B accPipes(i).io.sramWrite.resp.bits := DontCare - accPipes(i).io.is_acc := false.B } io.config.ready := true.B @@ -106,26 +107,15 @@ class MemBackend(val b: GlobalConfig) extends Module { // Bank Alloc/Release // ----------------------------------------------------------------------------- - when(io.config.valid && !io.config.bits.is_acc) { + when(io.config.valid) { when(io.config.bits.alloc) { val pbank_id = getFreePbankId() - addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_acc, 0.U) + addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_acc, io.config.bits.acc_group_id) }.otherwise { deleteEntry(io.config.bits.vbank_id) } } - when(io.config.valid && io.config.bits.is_acc) {} - - for (i <- 0 until b.memDomain.bankChannel) { - for (j <- 0 until b.memDomain.bankNum) { - when((io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid) && - mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id)) { - mappingTable(j).channel_id := i.U - } - } - } - // ----------------------------------------------------------------------------- // Connect AccPipe and Banks // ----------------------------------------------------------------------------- @@ -135,14 +125,30 @@ class MemBackend(val b: GlobalConfig) extends Module { case (accPipe, accPipeId) => when(mappingTable(pBankId).valid && (mappingTable(pBankId).channel_id === accPipeId.U)) { bank.io.sramRead <> accPipe.io.sramRead - bank.io.sramRead.req.valid := RegNext(accPipe.io.sramRead.req.valid) - bank.io.sramRead.req.bits := RegNext(accPipe.io.sramRead.req.bits) + //bank.io.sramRead.req.valid := RegNext(accPipe.io.sramRead.req.valid) + //bank.io.sramRead.req.bits := RegNext(accPipe.io.sramRead.req.bits) bank.io.sramWrite <> accPipe.io.sramWrite - bank.io.sramWrite.req.valid := RegNext(accPipe.io.sramWrite.req.valid) - bank.io.sramWrite.req.bits := RegNext(accPipe.io.sramWrite.req.bits) + //bank.io.sramWrite.req.valid := RegNext(accPipe.io.sramWrite.req.valid) + //bank.io.sramWrite.req.bits := RegNext(accPipe.io.sramWrite.req.bits) } } } + + for (i <- 0 until b.memDomain.bankChannel) { + for (j <- 0 until b.memDomain.bankNum) { + + when((io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid) && + mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + (!mappingTable(j).is_acc || + mappingTable(j).is_acc && (mappingTable(j).acc_group_id === io.mem_req(i).acc_group_id))) { + + mappingTable(j).channel_id := i.U + banks(j).io.sramRead <> accPipes(i).io.sramRead + banks(j).io.sramWrite <> accPipes(i).io.sramWrite + } + } + } + } diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 282d198c..0c40a5a1 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -35,23 +35,10 @@ class AccPipe(val b: GlobalConfig) extends Module { // Control and status signals val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) - val is_acc = Input(Bool()) - - val vbank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val acc_group_id = Output(UInt(2.W)) val busy = Output(Bool()) }) - val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val acc_group_id_reg = RegInit(0.U(2.W)) - io.vbank_id := vbank_id_reg - io.acc_group_id := acc_group_id_reg - - when(io.sramRead.req.valid || io.sramWrite.req.valid) { - vbank_id_reg := io.bank_id - acc_group_id_reg := io.acc_group_id - } io.sramRead <> io.read io.sramWrite <> io.write io.busy := false.B diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 37fdbc99..4fc9e819 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -7,9 +7,10 @@ import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} class MemConfigerIO(val b: GlobalConfig) extends Bundle { - val vbank_id = Output(UInt(8.W)) - val is_acc = Output(Bool()) - val alloc = Output(Bool()) + val vbank_id = Output(UInt(8.W)) + val is_acc = Output(Bool()) + val alloc = Output(Bool()) + val acc_group_id = Output(UInt(3.W)) } @instantiable @@ -25,23 +26,55 @@ class MemConfiger(val b: GlobalConfig) extends Module { val config = Decoupled(new MemConfigerIO(b)) }) - when(io.cmdReq.valid) { - io.config.bits.is_acc := io.cmdReq.bits.cmd.special(0) - io.config.bits.alloc := io.cmdReq.bits.cmd.special(1) - io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id - io.config.valid := true.B + val idle :: config :: Nil = Enum(2) + val state = RegInit(idle) + val is_acc_reg = RegInit(false.B) + val alloc_reg = RegInit(false.B) + val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val counter = RegInit(0.U(4.W)) - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id - }.otherwise { - io.config.bits.is_acc := false.B - io.config.bits.alloc := false.B - io.config.bits.vbank_id := 0.U(8.W) - io.config.valid := false.B + io.config.bits.is_acc := false.B + io.config.bits.alloc := false.B + io.config.bits.vbank_id := 0.U(8.W) + io.config.bits.acc_group_id := 0.U(3.W) + io.config.valid := false.B + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + + when(state === idle) { + when(io.cmdReq.valid) { + when(io.cmdReq.bits.cmd.special(0)) { //is acc + state := config + is_acc_reg := io.cmdReq.bits.cmd.special(0) + alloc_reg := io.cmdReq.bits.cmd.special(1) + vbank_id_reg := io.cmdReq.bits.cmd.bank_id + rob_id_reg := io.cmdReq.bits.rob_id - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + }.otherwise { //not acc + io.config.bits.alloc := io.cmdReq.bits.cmd.special(1) + io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id + io.config.valid := true.B + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id + } + } + + }.otherwise { + when(counter < 4.U) { + io.config.bits.is_acc := is_acc_reg + io.config.bits.alloc := alloc_reg + io.config.bits.vbank_id := vbank_id_reg + io.config.bits.acc_group_id := counter + io.config.valid := true.B + counter := counter + 1.U + }.otherwise { + state := idle + counter := 0.U + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + } } - io.cmdReq.ready := true.B + io.cmdReq.ready := state === idle } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 032baaf0..b909d384 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -67,9 +67,10 @@ class MemLoader(val b: GlobalConfig) extends Module { // IMPORTANT: always ready for write response (avoid deadlock) io.bankWrite.io.resp.ready := true.B - io.bankWrite.rob_id := rob_id_reg - io.bankWrite.bank_id := wr_bank_reg - io.bankWrite.ball_id := 0.U + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := wr_bank_reg + io.bankWrite.ball_id := 0.U + io.bankWrite.acc_group_id := 0.U // cmdResp (Decoupled): hold valid until accepted io.cmdResp.valid := (state === s_done) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 57ae8222..42452611 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -86,9 +86,10 @@ class MemStorer(val b: GlobalConfig) extends Module { // ----------------------------- // SRAM read request // ----------------------------- - io.bankRead.rob_id := rob_id_reg - io.bankRead.bank_id := target_bank - io.bankRead.ball_id := 0.U + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U + io.bankRead.acc_group_id := 0.U io.bankRead.io.req.valid := (state === s_issue_sram_req) io.bankRead.io.req.bits.addr := sram_row diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 8d8a271c..cc2b2d2b 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -107,6 +107,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(ch).write.req.bits := DontCare io.mem_req(ch).write.resp.ready := true.B io.mem_req(ch).bank_id := 0.U + io.mem_req(ch).acc_group_id := 0.U } // Default resp to ports (each port gets muxed resp from its selected channel) @@ -200,6 +201,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(ch).read.req.bits := io.balldomain.bankRead(ridSel).io.req.bits io.mem_req(ch).read.resp.ready := io.balldomain.bankRead(ridSel).io.resp.ready io.mem_req(ch).bank_id := io.balldomain.bankRead(ridSel).bank_id + io.mem_req(ch).acc_group_id := io.balldomain.bankRead(ridSel).acc_group_id }.elsewhen(serveWrite) { val widSel = Mux(chServeWriteMapped(ch), mappingTable(ch).id, chAllocWriteId(ch)) @@ -207,6 +209,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(ch).write.req.bits := io.balldomain.bankWrite(widSel).io.req.bits io.mem_req(ch).write.resp.ready := io.balldomain.bankWrite(widSel).io.resp.ready io.mem_req(ch).bank_id := io.balldomain.bankWrite(widSel).bank_id + io.mem_req(ch).acc_group_id := io.balldomain.bankWrite(widSel).acc_group_id } } @@ -232,11 +235,16 @@ class MemMidend(val b: GlobalConfig) extends Module { val frontendCh = b.top.memBallChannelNum io.mem_req(frontendCh).write <> io.frontend.bankWrite.io io.mem_req(frontendCh).read <> io.frontend.bankRead.io - io.mem_req(frontendCh).bank_id := Mux( + io.mem_req(frontendCh).bank_id := Mux( io.frontend.bankRead.io.req.valid, io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id ) + io.mem_req(frontendCh).acc_group_id := Mux( + io.frontend.bankRead.io.req.valid, + io.frontend.bankRead.acc_group_id, + io.frontend.bankWrite.acc_group_id + ) // Mapping table release for (i <- 0 until numChannels) { From 11e7eee9ec9e315028f76bcc9fe7442f9c334fbe Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 11 Feb 2026 23:11:24 +0800 Subject: [PATCH 091/238] [arch]add:add im2colBall --- .../toy/balldomain/bbus/busRegister.scala | 2 + .../framework/balldomain/configs/default.json | 5 +- .../balldomain/prototype/im2col/Im2col.scala | 212 ++++++++++++++++++ .../prototype/im2col/Im2colBall.scala | 44 ++++ .../balldomain/prototype/im2col/README.md | 111 +++++++++ .../im2col/configs/Im2colBallParam.scala | 21 ++ .../prototype/im2col/configs/default.json | 4 + 7 files changed, 397 insertions(+), 2 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/README.md create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/configs/default.json diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 4defb441..8fc8664d 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -9,6 +9,7 @@ import framework.balldomain.blink.HasBlink import framework.balldomain.prototype.vector.VecBall import framework.balldomain.prototype.relu.ReluBall import framework.balldomain.prototype.transpose.TransposeBall +import framework.balldomain.prototype.im2col.Im2colBall /** * BBusModule - Ball bus module that directly extends BBus @@ -22,6 +23,7 @@ class BBusModule(b: GlobalConfig) case "VecBall" => () => new VecBall(b) case "ReluBall" => () => new ReluBall(b) case "TransposeBall" => () => new TransposeBall(b) + case "Im2colBall" => () => new Im2colBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 0d13d0b6..d3288286 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,8 +1,9 @@ { - "ballNum": 3, + "ballNum": 4, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, - {"ballId": 1, "ballName": "TransposeBall", "inBW": 1, "outBW": 1} + {"ballId": 2, "ballName": "TransposeBall", "inBW": 1, "outBW": 1}, + {"ballId": 3, "ballName": "Im2colBall", "inBW": 1, "outBW": 1} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala new file mode 100644 index 00000000..4d0bfaf5 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -0,0 +1,212 @@ +package framework.balldomain.prototype.im2col + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} + +import framework.balldomain.prototype.vector._ +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.top.GlobalConfig +import framework.balldomain.prototype.im2col.configs.Im2colBallParam + + +@instantiable +class Im2col(val b: GlobalConfig) extends Module{ + val ballConfig = Im2colBallParam() + val InputNum = ballConfig.InputNum + val inputWidth = ballConfig.inputWidth + val bankWidth = b.memDomain.bankWidth + + // Get bandwidth from config + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "Im2colBall") + .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + // State definitions + val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) + // Current state register + val state = RegInit(idle) + // Conversion buffer + val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(InputNum)(0.U(inputWidth.W)))))) + // Row pointer marking top-left corner of convolution window + val rowptr = RegInit(0.U(10.W)) + // Column pointer marking top-left corner of convolution window + val colptr = RegInit(0.U(5.W)) + // Request counter in read state + val reqcounter = RegInit(0.U(5.W)) + // Response counter in read state + val respcounter = RegInit(0.U(5.W)) + // Store current instruction's RoB ID + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + // Store kernel row count + val krow_reg = RegInit(0.U(log2Up(InputNum).W)) + // Store kernel column count + val kcol_reg = RegInit(0.U(log2Up(InputNum).W)) + // Store input matrix row count + val inrow_reg = RegInit(0.U(10.W)) + // Store input matrix column count + val incol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) + // Store starting column number + val startcol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) + // Store starting row number + val startrow_reg = RegInit(0.U(10.W)) + // Store write starting address + val waddr_reg = RegInit(0.U(10.W)) + // Store write bank + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + // Store read starting address + val raddr_reg = RegInit(0.U(10.W)) + // Store read bank + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + // Batch iteration counter + val iterCnt = RegInit(0.U(32.W)) + + + // SRAM default assignment + for(i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := (state === read) || (state === read_and_convert) + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + } + for(i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := true.B + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + } + // cmd interface default assignment + io.cmdReq.ready := true.B + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + val rowcnt = rowptr - startrow_reg + val colcnt = colptr - startcol_reg + val rowmax = inrow_reg - krow_reg + val colmax = incol_reg - kcol_reg + + switch(state) { + // Idle state, waiting for instruction + is(idle) { + // Instruction arrives, initialize registers + when(io.cmdReq.fire) { + state := read + rowptr := io.cmdReq.bits.cmd.special(37,28) + colptr := io.cmdReq.bits.cmd.special(27,23) + reqcounter := 0.U + respcounter:= 0.U + // Kernel column count + kcol_reg := io.cmdReq.bits.cmd.special(3,0) + // Kernel row count + krow_reg := io.cmdReq.bits.cmd.special(7,4) + // Input matrix column count + incol_reg := io.cmdReq.bits.cmd.special(12,8) + // Input matrix row count + inrow_reg := io.cmdReq.bits.cmd.special(22,13) + // Starting column number + startcol_reg := io.cmdReq.bits.cmd.special(27,23) + // Starting row number + startrow_reg := io.cmdReq.bits.cmd.special(37,28) + rob_id_reg := io.cmdReq.bits.rob_id + waddr_reg := 0.U + wbank_reg := io.cmdReq.bits.cmd.op2_bank + raddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + } + } + // Read part of data, fill ConvertBuffer + is(read) { + // Send read request + when(reqcounter < krow_reg) { + reqcounter := reqcounter + 1.U + io.bankRead(rbank_reg).io.req.valid := true.B + io.bankRead(rbank_reg).io.req.bits.addr := raddr_reg + reqcounter + startrow_reg + } + // Process read response and store in ConvertBuffer + when(io.bankRead(rbank_reg).io.resp.fire) { + ConvertBuffer(respcounter) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + respcounter := respcounter + 1.U + } + // Determine whether to transition state + state := Mux(respcounter === krow_reg, read_and_convert, read) + + } + // Convert data and read remaining data, write back to spad + is(read_and_convert) { + // Move pointer + when(colptr <= colmax && rowptr <= rowmax) { + colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) + io.bankWrite(wbank_reg).io.req.valid := true.B + io.bankWrite(wbank_reg).io.req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt + io.bankWrite(wbank_reg).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) + io.bankWrite(wbank_reg).io.req.bits.data := { + + val window = Wire(Vec(InputNum, UInt(inputWidth.W))) + // Initialize all to 0 first + for (i <- 0 until InputNum) { + window(i) := 0.U + } + + // Fill window data + for (i <- 0 until 4; j <- 0 until 4) { + when(i.U < krow_reg && j.U < kcol_reg) { + val bufferRow = (rowcnt + i.U) % krow_reg + val bufferCol = (colptr + j.U) % incol_reg + window((i.U * kcol_reg) + j.U) := ConvertBuffer(bufferRow)(bufferCol) + }.otherwise { + window((i.U * kcol_reg) + j.U) := 0.U + } + } + + // Rearrange data + // For example, for klen_reg=3, combine (00)(01)(02)(10)(11)(12)(20)(21)(22) + Cat((0 until InputNum).map(i => window(i)).reverse) + } + } + // Send read request early + when(colptr === colmax - 1.U){ + io.bankRead(rbank_reg).io.req.valid := true.B + io.bankRead(rbank_reg).io.req.bits.addr := raddr_reg + krow_reg + rowptr + } + // Process read response and store in ConvertBuffer + when(io.bankRead(rbank_reg).io.resp.fire){ + ConvertBuffer(rowcnt % krow_reg) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + rowptr := rowptr + 1.U + } + // Determine whether to transition state + state := Mux(rowptr === rowmax && colptr === colmax, complete, read_and_convert) + } + // Complete state, send completion signal + is(complete) { + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + state := idle + when(io.cmdResp.fire) { + iterCnt := iterCnt + 1.U + } + } + } + + // Status signals + io.status.idle := (state === idle) + io.status.running := (state === read_and_convert) +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala new file mode 100644 index 00000000..14b4aa4f --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala @@ -0,0 +1,44 @@ +package framework.balldomain.prototype.im2col + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.prototype.im2col.Im2col +import framework.top.GlobalConfig + +/** + * Im2colBall - An Im2col computation Ball that complies with the Blink protocol + */ +class Im2colBall(val b: GlobalConfig) extends Module with HasBlink { + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "Im2colBall") + .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + + // Instantiate Im2col + val im2colUnit :Instance[Im2col] = Instantiate(new Im2col(b)) + + // Connect command interface + im2colUnit.io.cmdReq <> io.cmdReq + im2colUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + im2colUnit.io.bankRead(i) <> io.bankRead(i) + } + + // Connect SRAM write interface - Im2col needs to write to scratchpad + for (i <- 0 until outBW) { + im2colUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + + // Connect Status signals - directly obtained from internal unit + io.status <> im2colUnit.io.status + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/README.md b/arch/src/main/scala/framework/balldomain/prototype/im2col/README.md new file mode 100644 index 00000000..71f5c5c1 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/README.md @@ -0,0 +1,111 @@ +# Im2col Image Processing Accelerator + +## Overview + +This directory implements Buckyball's Im2col operation accelerator for image-to-column matrix conversion in convolutional neural networks. Located at `arch/src/main/scala/prototype/im2col`, it serves as an image processing accelerator that converts convolution operations to matrix multiplication operations to improve computational efficiency. + +Core components: +- **im2col.scala**: Im2col accelerator main implementation + +## Code Structure + +``` +im2col/ +└── im2col.scala - Im2col accelerator implementation +``` + +### Module Responsibilities + +**Im2col.scala** (Accelerator implementation layer) +- Implements image-to-column matrix conversion logic +- Manages SRAM read/write operations +- Provides Ball domain command interface + +## Module Description + +### im2col.scala + +**Main functionality**: Implements sliding convolution window and data rearrangement + +**State machine definition**: +```scala +val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) +val state = RegInit(idle) +``` + +**Key registers**: +```scala +val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(b.veclane)(0.U(b.inputType.getWidth.W)))))) +val rowptr = RegInit(0.U(10.W)) // Convolution window top-left row pointer +val colptr = RegInit(0.U(5.W)) // Convolution window top-left column pointer +val krow_reg = RegInit(0.U(log2Up(b.veclane).W)) // Convolution kernel row count +val kcol_reg = RegInit(0.U(log2Up(b.veclane).W)) // Convolution kernel column count +``` + +**Command parsing**: +```scala +when(io.cmdReq.fire) { + rowptr := io.cmdReq.bits.cmd.special(37,28) // Start row + colptr := io.cmdReq.bits.cmd.special(27,23) // Start column + kcol_reg := io.cmdReq.bits.cmd.special(3,0) // Convolution kernel column count + krow_reg := io.cmdReq.bits.cmd.special(7,4) // Convolution kernel row count + incol_reg := io.cmdReq.bits.cmd.special(12,8) // Input matrix column count + inrow_reg := io.cmdReq.bits.cmd.special(22,13) // Input matrix row count +} +``` + +**Data conversion logic**: +```scala +// Fill window data +for (i <- 0 until 4; j <- 0 until 4) { + when(i.U < krow_reg && j.U < kcol_reg) { + val bufferRow = (rowcnt + i.U) % krow_reg + val bufferCol = (colptr + j.U) % incol_reg + window((i.U * kcol_reg) + j.U) := ConvertBuffer(bufferRow)(bufferCol) + }.otherwise { + window((i.U * kcol_reg) + j.U) := 0.U + } +} +``` + +**SRAM interface**: +```scala +val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue)) + val cmdResp = Decoupled(new BallRsComplete) + val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(...))) + val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(...))) +}) +``` + +**Processing flow**: +1. **idle**: Wait for command, parse convolution parameters +2. **read**: Read initial convolution kernel-sized data into buffer +3. **read_and_convert**: Slide window, convert data and write back +4. **complete**: Send completion signal + +**Inputs/Outputs**: +- Input: Ball domain commands containing convolution parameters and address information +- Output: Converted column matrix data, completion signal +- Edge cases: Fill zero values when handling boundaries + +## Usage + +### Algorithm Principle + +**Im2col conversion**: Convert convolution operation to matrix multiplication +- Input: H×W image, K×K convolution kernel +- Output: (H-K+1)×(W-K+1) windows of size K×K, expanded as column vectors + +**Sliding window**: +- Slide convolution window in row-major order +- Each window position generates a column vector +- Uses circular buffer to optimize memory access + +### Notes + +1. **Buffer management**: Uses 4×veclane conversion buffer to store window data +2. **Boundary handling**: Fill zero values for positions beyond image boundaries +3. **Address calculation**: Supports configurable start address and bank selection +4. **Pipeline optimization**: Prefetch next row read requests during conversion +5. **Parameter limitation**: Maximum support for 4×4 convolution kernel size diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala new file mode 100644 index 00000000..db53bae3 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala @@ -0,0 +1,21 @@ +package framework.balldomain.prototype.im2col.configs + +import upickle.default._ + +/** + * Im2colBall参数 + */ +case class Im2colBallParam( + InputNum: Int, + inputWidth: Int) + +object Im2colBallParam { + implicit val rw: ReadWriter[Im2colBallParam] = macroRW + + def apply(): Im2colBallParam = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/framework/balldomain/prototype/im2col/configs/default.json").mkString + read[Im2colBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/default.json new file mode 100644 index 00000000..a4552216 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/default.json @@ -0,0 +1,4 @@ +{ + "InputNum": 16, + "inputWidth": 8 +} From 60c58946a1efaf501a1b3107526b193e217a57fa Mon Sep 17 00:00:00 2001 From: SJM946 Date: Thu, 12 Feb 2026 21:46:59 +0800 Subject: [PATCH 092/238] [arch] Rewrite AccPipe and finish acc control in MemBackend --- .../balldomain/prototype/im2col/Im2col.scala | 154 +++++++++--------- .../prototype/im2col/Im2colBall.scala | 3 +- .../memdomain/backend/MemBackend.scala | 7 +- .../memdomain/backend/accpipe/AccPipe.scala | 42 +++++ .../frontend/outside_channel/MemStorer.scala | 2 +- .../src/CTest/toy/vecunit_matmul_ones.c | 2 +- 6 files changed, 129 insertions(+), 81 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index 4d0bfaf5..67c262fc 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -11,9 +11,8 @@ import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.top.GlobalConfig import framework.balldomain.prototype.im2col.configs.Im2colBallParam - @instantiable -class Im2col(val b: GlobalConfig) extends Module{ +class Im2col(val b: GlobalConfig) extends Module { val ballConfig = Im2colBallParam() val InputNum = ballConfig.InputNum val inputWidth = ballConfig.inputWidth @@ -24,8 +23,8 @@ class Im2col(val b: GlobalConfig) extends Module{ .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) val inBW = ballMapping.inBW val outBW = ballMapping.outBW - - @public + + @public val io = IO(new Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) val cmdResp = Decoupled(new BallRsComplete(b)) @@ -37,66 +36,67 @@ class Im2col(val b: GlobalConfig) extends Module{ // State definitions val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) // Current state register - val state = RegInit(idle) + val state = RegInit(idle) // Conversion buffer - val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(InputNum)(0.U(inputWidth.W)))))) + val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(InputNum)(0.U(inputWidth.W)))))) // Row pointer marking top-left corner of convolution window - val rowptr = RegInit(0.U(10.W)) + val rowptr = RegInit(0.U(10.W)) // Column pointer marking top-left corner of convolution window - val colptr = RegInit(0.U(5.W)) + val colptr = RegInit(0.U(5.W)) // Request counter in read state - val reqcounter = RegInit(0.U(5.W)) + val reqcounter = RegInit(0.U(5.W)) // Response counter in read state - val respcounter = RegInit(0.U(5.W)) + val respcounter = RegInit(0.U(5.W)) // Store current instruction's RoB ID - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) // Store kernel row count - val krow_reg = RegInit(0.U(log2Up(InputNum).W)) + val krow_reg = RegInit(0.U(log2Up(InputNum).W)) // Store kernel column count - val kcol_reg = RegInit(0.U(log2Up(InputNum).W)) + val kcol_reg = RegInit(0.U(log2Up(InputNum).W)) // Store input matrix row count - val inrow_reg = RegInit(0.U(10.W)) + val inrow_reg = RegInit(0.U(10.W)) // Store input matrix column count - val incol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) + val incol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) // Store starting column number - val startcol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) + val startcol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) // Store starting row number - val startrow_reg = RegInit(0.U(10.W)) + val startrow_reg = RegInit(0.U(10.W)) // Store write starting address - val waddr_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(10.W)) // Store write bank - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) // Store read starting address - val raddr_reg = RegInit(0.U(10.W)) + val raddr_reg = RegInit(0.U(10.W)) // Store read bank - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) - + val iterCnt = RegInit(0.U(32.W)) // SRAM default assignment - for(i <- 0 until inBW) { - io.bankRead(i).io.req.valid := false.B - io.bankRead(i).io.req.bits.addr := 0.U - io.bankRead(i).io.resp.ready := (state === read) || (state === read_and_convert) - io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).rob_id := rob_id_reg - io.bankRead(i).ball_id := 0.U + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := (state === read) || (state === read_and_convert) + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + io.bankRead(i).acc_group_id := 0.U } - for(i <- 0 until outBW) { - io.bankWrite(i).io.req.valid := false.B - io.bankWrite(i).io.req.bits.addr := 0.U - io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) - io.bankWrite(i).io.req.bits.wmode := false.B - io.bankWrite(i).io.resp.ready := true.B - io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).rob_id := rob_id_reg - io.bankWrite(i).ball_id := 0.U + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := true.B + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).acc_group_id := 0.U } // cmd interface default assignment io.cmdReq.ready := true.B - io.cmdResp.valid := false.B + io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := rob_id_reg val rowcnt = rowptr - startrow_reg @@ -109,42 +109,42 @@ class Im2col(val b: GlobalConfig) extends Module{ is(idle) { // Instruction arrives, initialize registers when(io.cmdReq.fire) { - state := read - rowptr := io.cmdReq.bits.cmd.special(37,28) - colptr := io.cmdReq.bits.cmd.special(27,23) - reqcounter := 0.U - respcounter:= 0.U + state := read + rowptr := io.cmdReq.bits.cmd.special(37, 28) + colptr := io.cmdReq.bits.cmd.special(27, 23) + reqcounter := 0.U + respcounter := 0.U // Kernel column count - kcol_reg := io.cmdReq.bits.cmd.special(3,0) + kcol_reg := io.cmdReq.bits.cmd.special(3, 0) // Kernel row count - krow_reg := io.cmdReq.bits.cmd.special(7,4) + krow_reg := io.cmdReq.bits.cmd.special(7, 4) // Input matrix column count - incol_reg := io.cmdReq.bits.cmd.special(12,8) + incol_reg := io.cmdReq.bits.cmd.special(12, 8) // Input matrix row count - inrow_reg := io.cmdReq.bits.cmd.special(22,13) + inrow_reg := io.cmdReq.bits.cmd.special(22, 13) // Starting column number - startcol_reg := io.cmdReq.bits.cmd.special(27,23) + startcol_reg := io.cmdReq.bits.cmd.special(27, 23) // Starting row number - startrow_reg := io.cmdReq.bits.cmd.special(37,28) - rob_id_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U - wbank_reg := io.cmdReq.bits.cmd.op2_bank - raddr_reg := 0.U - rbank_reg := io.cmdReq.bits.cmd.op1_bank + startrow_reg := io.cmdReq.bits.cmd.special(37, 28) + rob_id_reg := io.cmdReq.bits.rob_id + waddr_reg := 0.U + wbank_reg := io.cmdReq.bits.cmd.op2_bank + raddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank } } // Read part of data, fill ConvertBuffer is(read) { // Send read request when(reqcounter < krow_reg) { - reqcounter := reqcounter + 1.U + reqcounter := reqcounter + 1.U io.bankRead(rbank_reg).io.req.valid := true.B io.bankRead(rbank_reg).io.req.bits.addr := raddr_reg + reqcounter + startrow_reg } // Process read response and store in ConvertBuffer when(io.bankRead(rbank_reg).io.resp.fire) { - ConvertBuffer(respcounter) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - respcounter := respcounter + 1.U + ConvertBuffer(respcounter) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + respcounter := respcounter + 1.U } // Determine whether to transition state state := Mux(respcounter === krow_reg, read_and_convert, read) @@ -154,7 +154,7 @@ class Im2col(val b: GlobalConfig) extends Module{ is(read_and_convert) { // Move pointer when(colptr <= colmax && rowptr <= rowmax) { - colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) + colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) io.bankWrite(wbank_reg).io.req.valid := true.B io.bankWrite(wbank_reg).io.req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt io.bankWrite(wbank_reg).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) @@ -163,11 +163,14 @@ class Im2col(val b: GlobalConfig) extends Module{ val window = Wire(Vec(InputNum, UInt(inputWidth.W))) // Initialize all to 0 first for (i <- 0 until InputNum) { - window(i) := 0.U + window(i) := 0.U } // Fill window data - for (i <- 0 until 4; j <- 0 until 4) { + for { + i <- 0 until 4 + j <- 0 until 4 + } { when(i.U < krow_reg && j.U < kcol_reg) { val bufferRow = (rowcnt + i.U) % krow_reg val bufferCol = (colptr + j.U) % incol_reg @@ -183,30 +186,33 @@ class Im2col(val b: GlobalConfig) extends Module{ } } // Send read request early - when(colptr === colmax - 1.U){ + when(colptr === colmax - 1.U) { io.bankRead(rbank_reg).io.req.valid := true.B io.bankRead(rbank_reg).io.req.bits.addr := raddr_reg + krow_reg + rowptr } // Process read response and store in ConvertBuffer - when(io.bankRead(rbank_reg).io.resp.fire){ - ConvertBuffer(rowcnt % krow_reg) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - rowptr := rowptr + 1.U + when(io.bankRead(rbank_reg).io.resp.fire) { + ConvertBuffer(rowcnt % krow_reg) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec( + InputNum, + UInt(inputWidth.W) + )) + rowptr := rowptr + 1.U } // Determine whether to transition state state := Mux(rowptr === rowmax && colptr === colmax, complete, read_and_convert) } // Complete state, send completion signal is(complete) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := rob_id_reg - state := idle - when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U - } + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + state := idle + when(io.cmdResp.fire) { + iterCnt := iterCnt + 1.U + } } } // Status signals - io.status.idle := (state === idle) + io.status.idle := (state === idle) io.status.running := (state === read_and_convert) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala index 14b4aa4f..dce1c8ae 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala @@ -22,7 +22,7 @@ class Im2colBall(val b: GlobalConfig) extends Module with HasBlink { def blink: BlinkIO = io // Instantiate Im2col - val im2colUnit :Instance[Im2col] = Instantiate(new Im2col(b)) + val im2colUnit: Instance[Im2col] = Instantiate(new Im2col(b)) // Connect command interface im2colUnit.io.cmdReq <> io.cmdReq @@ -37,7 +37,6 @@ class Im2colBall(val b: GlobalConfig) extends Module with HasBlink { im2colUnit.io.bankWrite(i) <> io.bankWrite(i) } - // Connect Status signals - directly obtained from internal unit io.status <> im2colUnit.io.status diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 299de8a0..4c24aeb9 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -28,7 +28,7 @@ class MemBackend(val b: GlobalConfig) extends Module { val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) // ----------------------------------------------------------------------------- - // Mapping table/ Free List + // Mapping table // ----------------------------------------------------------------------------- class MappingTableEntry extends Bundle { val valid = Bool() @@ -40,8 +40,8 @@ class MemBackend(val b: GlobalConfig) extends Module { val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) - def isAllocated(vbank_id: UInt): Bool = - mappingTable.map(_.vbank_id === vbank_id).reduce(_ || _) + def isAcc(vbank_id: UInt): Bool = + mappingTable.map(entry => entry.vbank_id === vbank_id && entry.is_acc).reduce(_ || _) def addEntry( vbank_id: UInt, @@ -87,6 +87,7 @@ class MemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.sramWrite.resp.valid := false.B accPipes(i).io.sramWrite.resp.bits := DontCare + accPipes(i).io.is_acc := isAcc(io.mem_req(i).bank_id) } io.config.ready := true.B diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 0c40a5a1..19fe662c 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -35,11 +35,53 @@ class AccPipe(val b: GlobalConfig) extends Module { // Control and status signals val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val is_acc = Input(Bool()) val busy = Output(Bool()) }) + val read :: write :: Nil = Enum(2) + val state = RegInit(read) + io.sramRead <> io.read io.sramWrite <> io.write + + when(io.is_acc) { + io.sramRead.req.bits.addr := io.read.req.bits.addr(log2Ceil(b.memDomain.bankEntries) - 1, 2) + } + + val acc_data_reg = RegInit(0.U(b.memDomain.bankWidth.W)) + val acc_mask_reg = RegInit(VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B))) + val acc_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) + + switch(state) { + is(read) { + when(io.write.req.valid && io.write.req.bits.wmode) { + state := write + acc_data_reg := io.write.req.bits.data + acc_mask_reg := io.write.req.bits.mask + acc_addr_reg := io.write.req.bits.addr + io.sramRead.req.bits.addr := io.write.req.bits.addr + io.sramRead.req.valid := true.B + + io.sramWrite.req.valid := false.B + io.sramWrite.req.bits := DontCare + } + } + is(write) { + when(io.sramRead.resp.valid) { + state := read + io.sramWrite.req.bits.addr := acc_addr_reg + io.sramWrite.req.bits.data := acc_data_reg + io.sramRead.resp.bits.data + io.sramWrite.req.bits.mask := acc_mask_reg + io.sramWrite.req.bits.wmode := true.B + io.sramWrite.req.valid := true.B + + io.sramRead.req.valid := false.B + io.sramRead.req.bits := DontCare + } + } + } + io.busy := false.B } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 42452611..37f3b9d5 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -89,7 +89,7 @@ class MemStorer(val b: GlobalConfig) extends Module { io.bankRead.rob_id := rob_id_reg io.bankRead.bank_id := target_bank io.bankRead.ball_id := 0.U - io.bankRead.acc_group_id := 0.U + io.bankRead.acc_group_id := sram_row(1, 0) io.bankRead.io.req.valid := (state === s_issue_sram_req) io.bankRead.io.req.bits.addr := sram_row diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 7869cc83..01fd025a 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -33,7 +33,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); - // bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } From c0a1edd71bd6ead129f7e4f761b61c9048f0e870 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Feb 2026 23:57:39 +0800 Subject: [PATCH 093/238] feat: add bebop nix support feat: add GitHub Actions workflow for Nix builds --- .github/workflows/nix.yml | 16 +++++ .../frontend/outside_channel/MemStorer.scala | 1 - bebop | 2 +- flake.lock | 61 ++++++++++++++++ flake.nix | 38 ++++++---- scripts/nix/build-all.sh | 11 --- scripts/nix/build-env-bebop.nix | 8 ++- ...d-env-chipyard.nix => build-env-riscv.nix} | 5 -- scripts/nix/build-env-scala.nix | 26 ++++++- scripts/nix/build-env-tools.nix | 6 ++ scripts/nix/overlay.nix | 7 +- verify/.gitignore | 2 - verify/Adder/Adder.v | 35 --------- verify/Adder/example.py | 71 ------------------- verify/Adder/verilator.sh | 26 ------- verify/run.sh | 5 -- 16 files changed, 145 insertions(+), 175 deletions(-) create mode 100644 .github/workflows/nix.yml rename scripts/nix/{build-env-chipyard.nix => build-env-riscv.nix} (97%) create mode 100644 scripts/nix/build-env-tools.nix delete mode 100644 verify/.gitignore delete mode 100644 verify/Adder/Adder.v delete mode 100644 verify/Adder/example.py delete mode 100755 verify/Adder/verilator.sh delete mode 100755 verify/run.sh diff --git a/.github/workflows/nix.yml b/.github/workflows/nix.yml new file mode 100644 index 00000000..5ee848b5 --- /dev/null +++ b/.github/workflows/nix.yml @@ -0,0 +1,16 @@ +name: Nix + +on: + pull_request: + push: + branches: [main] + +jobs: + build: + name: Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: DeterminateSystems/determinate-nix-action@v3 + - name: Build Buckyball + run: nix build diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 37f3b9d5..ee205c3e 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -94,7 +94,6 @@ class MemStorer(val b: GlobalConfig) extends Module { io.bankRead.io.req.valid := (state === s_issue_sram_req) io.bankRead.io.req.bits.addr := sram_row - // IMPORTANT: // SRAMBank read resp is a 1-cycle pulse, so we must ALWAYS be ready to take it, // but only if we don't already hold a pending beat. io.bankRead.io.resp.ready := !pending diff --git a/bebop b/bebop index bbd5af60..6ed2be07 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit bbd5af609d0d15cd297314cef072ef2dd199e134 +Subproject commit 6ed2be07e6b5a3a88cd8592fb0c4517d86370002 diff --git a/flake.lock b/flake.lock index b9182344..b776f047 100644 --- a/flake.lock +++ b/flake.lock @@ -1,5 +1,31 @@ { "nodes": { + "bebop": { + "inputs": { + "flake-utils": [ + "flake-utils" + ], + "gem5-src": "gem5-src", + "nixpkgs": [ + "nixpkgs" + ], + "spike-src": "spike-src" + }, + "locked": { + "lastModified": 1770831670, + "narHash": "sha256-AyTkiYE6TIxq1KVi7EixdPScmtcY4LmbGpPUR0NvCII=", + "owner": "DangoSys", + "repo": "bebop", + "rev": "5f65c8f264b176845924c1ec17935ae4c3e103d7", + "type": "github" + }, + "original": { + "owner": "DangoSys", + "repo": "bebop", + "rev": "5f65c8f264b176845924c1ec17935ae4c3e103d7", + "type": "github" + } + }, "flake-utils": { "inputs": { "systems": "systems" @@ -17,6 +43,23 @@ "type": "indirect" } }, + "gem5-src": { + "flake": false, + "locked": { + "lastModified": 1754946347, + "narHash": "sha256-cvJMe6VEKUE1vnS/IvZR2pBDvgw5KMaUBjx6ouUgmo4=", + "owner": "gem5", + "repo": "gem5", + "rev": "ddd4ae35adb0a3df1f1ba11e9a973a5c2f8c2944", + "type": "github" + }, + "original": { + "owner": "gem5", + "repo": "gem5", + "rev": "ddd4ae35adb0a3df1f1ba11e9a973a5c2f8c2944", + "type": "github" + } + }, "nixpkgs": { "locked": { "lastModified": 1770019141, @@ -35,10 +78,28 @@ }, "root": { "inputs": { + "bebop": "bebop", "flake-utils": "flake-utils", "nixpkgs": "nixpkgs" } }, + "spike-src": { + "flake": false, + "locked": { + "lastModified": 1766824496, + "narHash": "sha256-GysjOv1077ogF2ajkcQpw7TX4KKrbCIwz9jFst24LoI=", + "owner": "riscv-software-src", + "repo": "riscv-isa-sim", + "rev": "45fe6c110aed80d5689752236ba0a668f093ce48", + "type": "github" + }, + "original": { + "owner": "riscv-software-src", + "repo": "riscv-isa-sim", + "rev": "45fe6c110aed80d5689752236ba0a668f093ce48", + "type": "github" + } + }, "systems": { "locked": { "lastModified": 1681028828, diff --git a/flake.nix b/flake.nix index 732006a4..5c491c40 100644 --- a/flake.nix +++ b/flake.nix @@ -4,15 +4,19 @@ inputs = { nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; # flake-utils.url = "github:numtide/flake-utils"; + bebop = { + url = "github:DangoSys/bebop/5f65c8f264b176845924c1ec17935ae4c3e103d7"; + inputs.nixpkgs.follows = "nixpkgs"; + inputs.flake-utils.follows = "flake-utils"; + }; }; - outputs = { self, nixpkgs, flake-utils }@inputs: - let - overlay = import ./scripts/nix/overlay.nix; - in + outputs = { self, nixpkgs, flake-utils, bebop }@inputs: flake-utils.lib.eachDefaultSystem (system: let + bebopPkgs = bebop.packages.${system}; + overlay = import ./scripts/nix/overlay.nix { inherit bebopPkgs; }; pkgs = import nixpkgs { overlays = [ overlay ]; inherit system; }; in { @@ -22,19 +26,24 @@ packages.default = pkgs.buildEnv { name = "buckyball-environment"; paths = with pkgs; [ - # Chipyard tools - chipyard.verilator - chipyard.riscv-embedded-gcc - chipyard.riscv-linux-gcc + tools.verilator + + # RISC-V toolchain + riscv.riscv-embedded-gcc + riscv.riscv-linux-gcc # python environment python.python3Packages # Bebop tools - bebop.rustc - bebop.cargo - bebop.rustfmt - bebop.clippy + pkgs.bebop.rustc + pkgs.bebop.cargo + pkgs.bebop.rustfmt + pkgs.bebop.clippy + pkgs.bebop.bebop + pkgs.bebop.bebopHost + pkgs.bebop.spike + pkgs.bebop.gem5 # Workflow dev tools bbdev.nodejs @@ -77,18 +86,19 @@ echo "Verilator: $(verilator --version 2>&1 | head -1)" echo "RISC-V Embedded GCC: $(riscv64-unknown-elf-gcc --version 2>&1 | head -1)" echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" + echo "Bebop: $(which bebop)" + echo "Spike: $(which spike)" + echo "Bebop Gem5: $(which gem5.opt)" echo "Mill: $(mill --version 2>&1 | head -1)" echo "Cargo: $(cargo --version 2>&1 | head -1)" echo "npm: $(npm --version 2>&1 | head -1)" echo "bbdev: $(which bbdev)" echo "RISCV: $RISCV" - echo "LIBGLOSS: $(whereis htif_nano.specs)" echo "===========================================================================" ''; }; } ) // { inherit inputs; - overlays.default = overlay; }; } diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 1d5fedfa..c30276a6 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -101,17 +101,6 @@ if run_step "1"; then --host=riscv64-unknown-elf make make install - # INSTALL_DIR=${RISCV}/lib - # mkdir -p ${INSTALL_DIR}/lib - # find . -name "libgloss_htif.a" | while read -r lib; do - # subdir=$(dirname "$lib" | sed 's|^\./||') - # [ "$subdir" = "build" ] && subdir="" - # dest=${INSTALL_DIR}/lib/${subdir} - # mkdir -p "$dest" - # cp "$lib" "$dest/" - # cp ../util/htif_nano.specs ../util/htif.ld ../util/htif.specs \ - # ../util/htif_wrap.specs ../util/htif_argv.specs "$dest/" 2>/dev/null || true - # done fi if run_step "2"; then diff --git a/scripts/nix/build-env-bebop.nix b/scripts/nix/build-env-bebop.nix index c17c8b40..3f0b2c92 100644 --- a/scripts/nix/build-env-bebop.nix +++ b/scripts/nix/build-env-bebop.nix @@ -1,4 +1,4 @@ -{ pkgs }: +{ pkgs, bebopPkgs ? {} }: { # Rust toolchain @@ -6,4 +6,10 @@ cargo = pkgs.cargo; rustfmt = pkgs.rustfmt; clippy = pkgs.clippy; + + # Bebop packages (from bebop flake) + bebop = bebopPkgs.bebop or null; + bebopHost = bebopPkgs.host or null; + spike = bebopPkgs.spike or null; + gem5 = bebopPkgs.gem5 or null; } diff --git a/scripts/nix/build-env-chipyard.nix b/scripts/nix/build-env-riscv.nix similarity index 97% rename from scripts/nix/build-env-chipyard.nix rename to scripts/nix/build-env-riscv.nix index 59d60464..fbedd598 100644 --- a/scripts/nix/build-env-chipyard.nix +++ b/scripts/nix/build-env-riscv.nix @@ -75,9 +75,6 @@ let in { - # Fast and robust (System)Verilog simulator/compiler and linter - verilator = pkgs.verilator; - # RISC-V embedded toolchain (bare metal), with riscv64-unknown-elf-* symlinks # Now includes newlib-nano and libgloss-htif support riscv-embedded-gcc = pkgs.symlinkJoin { @@ -107,6 +104,4 @@ in chmod +x $out/bin/$name done ''; - - } diff --git a/scripts/nix/build-env-scala.nix b/scripts/nix/build-env-scala.nix index 6d27ee67..3a806a32 100644 --- a/scripts/nix/build-env-scala.nix +++ b/scripts/nix/build-env-scala.nix @@ -1,8 +1,32 @@ { pkgs }: +let + millVersion = "0.11.4"; + millBinary = pkgs.fetchurl { + url = "https://github.com/com-lihaoyi/mill/releases/download/${millVersion}/${millVersion}"; + sha256 = "1swayysb1baqk7zhrlzvikd4plqznaa0nkx2bwc57dvwxp06whz2"; + }; + mill = pkgs.stdenv.mkDerivation { + name = "mill-${millVersion}"; + src = millBinary; + dontUnpack = true; + nativeBuildInputs = [ pkgs.makeWrapper ]; + installPhase = '' + mkdir -p $out/bin + cp $src $out/bin/mill + chmod +x $out/bin/mill + ''; + meta = with pkgs.lib; { + description = "Mill build tool ${millVersion}"; + homepage = "https://github.com/com-lihaoyi/mill"; + license = licenses.asl20; + platforms = platforms.all; + }; + }; +in { # Build tool for Scala, Java and more - mill = pkgs.mill; + inherit mill; # Scala formatter scalafmt = pkgs.scalafmt; diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix new file mode 100644 index 00000000..f351449e --- /dev/null +++ b/scripts/nix/build-env-tools.nix @@ -0,0 +1,6 @@ +{ pkgs }: + +{ + verilator = pkgs.verilator; + +} diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 60aa6f80..4d3edebc 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -1,7 +1,10 @@ +{ bebopPkgs }: + final: prev: { - chipyard = final.callPackage ./build-env-chipyard.nix { }; - bebop = final.callPackage ./build-env-bebop.nix { }; + riscv = final.callPackage ./build-env-riscv.nix { }; + tools = final.callPackage ./build-env-tools.nix { }; + bebop = final.callPackage ./build-env-bebop.nix { inherit bebopPkgs; }; bbdev = final.callPackage ./build-env-bbdev.nix { }; python = final.callPackage ./build-env-python.nix { }; scala = final.callPackage ./build-env-scala.nix { }; diff --git a/verify/.gitignore b/verify/.gitignore deleted file mode 100644 index ab52b538..00000000 --- a/verify/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -dut/ -out/ diff --git a/verify/Adder/Adder.v b/verify/Adder/Adder.v deleted file mode 100644 index ae53970d..00000000 --- a/verify/Adder/Adder.v +++ /dev/null @@ -1,35 +0,0 @@ -// A verilog 128-bit full adder with carry in and carry out - -module Adder #( - parameter WIDTH = 128 -) ( - input [WIDTH-1:0] a, - input [WIDTH-1:0] b, - input cin, - output [WIDTH-1:0] sum, - output cout -); - -assign {cout, sum} = a + b + cin; - -endmodule - -module Adder_128 ( - input [127:0] a, - input [127:0] b, - input cin, - output [127:0] sum, - output cout -); - - Adder #( - .WIDTH(128) - ) adder ( - .a(a), - .b(b), - .cin(cin), - .sum(sum), - .cout(cout) - ); - -endmodule diff --git a/verify/Adder/example.py b/verify/Adder/example.py deleted file mode 100644 index 93af1fcd..00000000 --- a/verify/Adder/example.py +++ /dev/null @@ -1,71 +0,0 @@ -try: - from UT_Adder import * -except Exception as e: - try: - from Adder import * - except Exception as e: - from __init__ import * - -import random - - -class input_t: - def __init__(self, a, b, cin): - self.a = a - self.b = b - self.cin = cin - - -class output_t: - def __init__(self): - self.sum = 0 - self.cout = 0 - - -def random_int(): - return random.randint(-(2**127), 2**127 - 1) & ((1 << 128) - 1) - - -def as_uint(x, nbits): - return x & ((1 << nbits) - 1) - - -def main(): - dut = DUTAdder() # Assuming USE_VERILATOR - - print("Initialized UTAdder") - dut.RefreshComb() - dut.dut.PauseWaveformDump() - - for c in range(11451): - i = input_t(random_int(), random_int(), random_int() & 1) - o_dut, o_ref = output_t(), output_t() - - def dut_cal(): - dut.a.value, dut.b.value, dut.cin.value = i.a, i.b, i.cin - dut.Step(1) - o_dut.sum = dut.sum.value - o_dut.cout = dut.cout.value - - def ref_cal(): - sum = as_uint(i.a + i.b + i.cin, 128 + 1) - o_ref.sum = as_uint(sum, 128) - o_ref.cout = as_uint(sum >> 128, 1) - - dut_cal() - ref_cal() - - print(f"[cycle {dut.xclock.clk}] a=0x{i.a:x}, b=0x{i.b:x}, cin=0x{i.cin:x}") - print(f"DUT: sum=0x{o_dut.sum:x}, cout=0x{o_dut.cout:x}") - print(f"REF: sum=0x{o_ref.sum:x}, cout=0x{o_ref.cout:x}") - - assert o_dut.sum == o_ref.sum, "sum mismatch" - if c == 11401: - dut.dut.ResumeWaveformDump() - - print("Test Passed, destroy UTAdder") - dut.Finish() # When using VCS, DUT.Finish() will exit the program, so it should be the last line of the program - - -if __name__ == "__main__": - main() diff --git a/verify/Adder/verilator.sh b/verify/Adder/verilator.sh deleted file mode 100755 index 25e06bb2..00000000 --- a/verify/Adder/verilator.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash - -BBDIR=$(git rev-parse --show-toplevel) - -VERIFY_WORKSPACE=$BBDIR/verify -PICKERDIR=$BBDIR/thirdparty/picker - -if ! command -v verible-verilog-syntax &> /dev/null -then - echo "verible could not be found" - echo "please add verible-verilog-syntax into path first" - echo "https://chipsalliance.github.io/verible/verilog_syntax.html" - echo "https://github.com/chipsalliance/verible/releases/tag/v0.0-3428-gcfcbb82b" - exit -fi - -rm -rf $VERIFY_WORKSPACE/out/ -picker export Adder.v --autobuild false -w Adder.fst --sname Adder --tdir $VERIFY_WORKSPACE/out/Adder --sdir $PICKERDIR/template $@ -# if python in $@, then it will generate python binding -if [[ $@ == *"python"* ]]; then - cp $VERIFY_WORKSPACE/Adder/example.py $VERIFY_WORKSPACE/out/Adder/python/ -else - echo "unsupport" -fi - -cd $VERIFY_WORKSPACE/out/Adder && make EXAMPLE=ON diff --git a/verify/run.sh b/verify/run.sh deleted file mode 100755 index 729ece1e..00000000 --- a/verify/run.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/bash - -VERIFY_WORKSPACE="$(dirname "$(realpath "$0")")" - -bbdev verilator --verilog "--balltype vecball --output_dir $VERIFY_WORKSPACE/dut/" From 8220eeda633f6ad661b2bd0a7d598e655fc9c6cb Mon Sep 17 00:00:00 2001 From: SJM946 Date: Fri, 13 Feb 2026 00:29:57 +0800 Subject: [PATCH 094/238] [arch] Fix some bugs and simplify the logic in MemBackend --- .../memdomain/backend/MemBackend.scala | 27 ++-------- .../memdomain/backend/accpipe/AccPipe.scala | 51 ++++++++++++------- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 4c24aeb9..de0dc0e1 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -75,9 +75,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- for (i <- 0 until b.memDomain.bankChannel) { - accPipes(i).io.write <> io.mem_req(i).write - accPipes(i).io.read <> io.mem_req(i).read - accPipes(i).io.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req <> io.mem_req(i) accPipes(i).io.sramRead.req.ready := true.B accPipes(i).io.sramRead.resp.valid := false.B @@ -120,30 +118,15 @@ class MemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Connect AccPipe and Banks // ----------------------------------------------------------------------------- - banks.zipWithIndex.foreach { - case (bank, pBankId) => - accPipes.zipWithIndex.foreach { - case (accPipe, accPipeId) => - when(mappingTable(pBankId).valid && (mappingTable(pBankId).channel_id === accPipeId.U)) { - bank.io.sramRead <> accPipe.io.sramRead - //bank.io.sramRead.req.valid := RegNext(accPipe.io.sramRead.req.valid) - //bank.io.sramRead.req.bits := RegNext(accPipe.io.sramRead.req.bits) - - bank.io.sramWrite <> accPipe.io.sramWrite - //bank.io.sramWrite.req.valid := RegNext(accPipe.io.sramWrite.req.valid) - //bank.io.sramWrite.req.bits := RegNext(accPipe.io.sramWrite.req.bits) - - } - } - } for (i <- 0 until b.memDomain.bankChannel) { + val hasReq = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid for (j <- 0 until b.memDomain.bankNum) { - when((io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid) && - mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + when((hasReq || RegNext(hasReq)) && + mappingTable(j).valid && (mappingTable(j).vbank_id === accPipes(i).io.bank_id) && (!mappingTable(j).is_acc || - mappingTable(j).is_acc && (mappingTable(j).acc_group_id === io.mem_req(i).acc_group_id))) { + mappingTable(j).is_acc && (mappingTable(j).acc_group_id === accPipes(i).io.acc_group_id))) { mappingTable(j).channel_id := i.U banks(j).io.sramRead <> accPipes(i).io.sramRead diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 19fe662c..16d6be70 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -6,6 +6,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.memdomain.backend.MemRequestIO /** * AccPipe: Accumulator Pipeline @@ -29,25 +30,41 @@ class AccPipe(val b: GlobalConfig) extends Module { val sramRead = Flipped(new SramReadIO(b)) // AccPipe -> bank: req out, resp in val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in - // Interface from midend (AccPipe is slave) - val read = new SramReadIO(b) // midend -> AccPipe: req in, resp out - val write = new SramWriteIO(b) // midend -> AccPipe: req in, resp out - - // Control and status signals - val bank_id = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val mem_req = Flipped(new MemRequestIO(b)) val is_acc = Input(Bool()) - val busy = Output(Bool()) + val busy = Output(Bool()) + val acc_group_id = Output(UInt(3.W)) + val bank_id = Output(UInt(b.memDomain.bankNum.W)) }) val read :: write :: Nil = Enum(2) val state = RegInit(read) - io.sramRead <> io.read - io.sramWrite <> io.write + io.sramRead <> io.mem_req.read + io.sramWrite <> io.mem_req.write + //Read Acc when(io.is_acc) { - io.sramRead.req.bits.addr := io.read.req.bits.addr(log2Ceil(b.memDomain.bankEntries) - 1, 2) + io.sramRead.req.bits.addr := io.mem_req.read.req.bits.addr(log2Ceil(b.memDomain.bankEntries) - 1, 2) + } + + //Acc_group_id output + val acc_group_id_reg = RegInit(0.U(3.W)) + when(io.mem_req.read.req.valid || io.mem_req.write.req.valid) { + io.acc_group_id := io.mem_req.acc_group_id + acc_group_id_reg := io.mem_req.acc_group_id + }.otherwise { + io.acc_group_id := acc_group_id_reg + } + + //Bank_id output + val bank_id_reg = RegInit(0.U(b.memDomain.bankNum.W)) + when(io.mem_req.read.req.valid || io.mem_req.write.req.valid) { + bank_id_reg := io.mem_req.bank_id + io.bank_id := io.mem_req.bank_id + }.otherwise { + io.bank_id := bank_id_reg } val acc_data_reg = RegInit(0.U(b.memDomain.bankWidth.W)) @@ -55,20 +72,20 @@ class AccPipe(val b: GlobalConfig) extends Module { val acc_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) switch(state) { - is(read) { - when(io.write.req.valid && io.write.req.bits.wmode) { + is(read) { //Stage 1: Read Acc Data + when(io.mem_req.write.req.valid && io.mem_req.write.req.bits.wmode) { state := write - acc_data_reg := io.write.req.bits.data - acc_mask_reg := io.write.req.bits.mask - acc_addr_reg := io.write.req.bits.addr - io.sramRead.req.bits.addr := io.write.req.bits.addr + acc_data_reg := io.mem_req.write.req.bits.data + acc_mask_reg := io.mem_req.write.req.bits.mask + acc_addr_reg := io.mem_req.write.req.bits.addr + io.sramRead.req.bits.addr := io.mem_req.write.req.bits.addr io.sramRead.req.valid := true.B io.sramWrite.req.valid := false.B io.sramWrite.req.bits := DontCare } } - is(write) { + is(write) { //Stage 2: Write Acc Data when(io.sramRead.resp.valid) { state := read io.sramWrite.req.bits.addr := acc_addr_reg From 714326b22578bfe8fb5388d7b87a402e73590897 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Fri, 13 Feb 2026 16:02:41 +0800 Subject: [PATCH 095/238] [arch]fix:fix bugs of lost data of last line in backend --- .../memdomain/backend/MemBackend.scala | 32 ++++++++++++------- bb-tests/workloads/src/CTest/toy/relu_test.c | 3 ++ 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index de0dc0e1..7f92e799 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -41,7 +41,7 @@ class MemBackend(val b: GlobalConfig) extends Module { val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) def isAcc(vbank_id: UInt): Bool = - mappingTable.map(entry => entry.vbank_id === vbank_id && entry.is_acc).reduce(_ || _) + mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && entry.is_acc).reduce(_ || _) def addEntry( vbank_id: UInt, @@ -54,6 +54,7 @@ class MemBackend(val b: GlobalConfig) extends Module { entry.vbank_id := vbank_id entry.is_acc := is_acc entry.acc_group_id := acc_group_id + entry.channel_id := 0.U } def deleteEntry(vbank_id: UInt): Unit = { @@ -75,13 +76,16 @@ class MemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- for (i <- 0 until b.memDomain.bankChannel) { - accPipes(i).io.mem_req <> io.mem_req(i) + accPipes(i).io.write <> io.mem_req(i).write + accPipes(i).io.read <> io.mem_req(i).read + accPipes(i).io.bank_id := io.mem_req(i).bank_id - accPipes(i).io.sramRead.req.ready := true.B - accPipes(i).io.sramRead.resp.valid := false.B - accPipes(i).io.sramRead.resp.bits := DontCare + // Bank-side defaults (only driven when a bank is actually connected) + accPipes(i).io.sramRead.req.ready := false.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare - accPipes(i).io.sramWrite.req.ready := true.B + accPipes(i).io.sramWrite.req.ready := false.B accPipes(i).io.sramWrite.resp.valid := false.B accPipes(i).io.sramWrite.resp.bits := DontCare @@ -118,17 +122,23 @@ class MemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Connect AccPipe and Banks // ----------------------------------------------------------------------------- - for (i <- 0 until b.memDomain.bankChannel) { val hasReq = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid for (j <- 0 until b.memDomain.bankNum) { - when((hasReq || RegNext(hasReq)) && - mappingTable(j).valid && (mappingTable(j).vbank_id === accPipes(i).io.bank_id) && + val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + val hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && (!mappingTable(j).is_acc || - mappingTable(j).is_acc && (mappingTable(j).acc_group_id === accPipes(i).io.acc_group_id))) { + (mappingTable(j).is_acc && (mappingTable(j).acc_group_id === io.mem_req(i).acc_group_id))) + + // Hold connection for one extra cycle to cover SramBank's 1-cycle resp pulse. + // Gate the hold with the latched channel_id to avoid a different channel stealing the resp. + val hold_one = RegNext(hit_bank && req_valid, init = false.B) && (mappingTable(j).channel_id === i.U) - mappingTable(j).channel_id := i.U + when((hit_bank && req_valid) || hold_one) { + when(hit_bank && req_valid) { + mappingTable(j).channel_id := i.U + } banks(j).io.sramRead <> accPipes(i).io.sramRead banks(j).io.sramWrite <> accPipes(i).io.sramWrite } diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index 04475282..56aa97ed 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -79,6 +79,9 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(wr_bank_id, 0, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); From 55a4aa17c9b51509c23d9f13140a773f214f227f Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Fri, 13 Feb 2026 16:24:10 +0800 Subject: [PATCH 096/238] [arch]fix:fix dead error of compling --- .../scala/framework/memdomain/backend/MemBackend.scala | 7 ++++--- bb-tests/workloads/src/CTest/toy/transpose_test.c | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 7f92e799..59701a75 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -76,9 +76,10 @@ class MemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- for (i <- 0 until b.memDomain.bankChannel) { - accPipes(i).io.write <> io.mem_req(i).write - accPipes(i).io.read <> io.mem_req(i).read - accPipes(i).io.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.write <> io.mem_req(i).write + accPipes(i).io.mem_req.read <> io.mem_req(i).read + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.acc_group_id := io.mem_req(i).acc_group_id // Bank-side defaults (only driven when a bank is actually connected) accPipes(i).io.sramRead.req.ready := false.B diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index aa002ef6..3c013913 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -77,6 +77,9 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); bb_transpose(op1_bank_id, op2_bank_id, size, 0); From 7b561cf12826a11b074d94581da63c917fc7e2aa Mon Sep 17 00:00:00 2001 From: SJM946 Date: Fri, 13 Feb 2026 20:48:44 +0800 Subject: [PATCH 097/238] [arch] Fix some bugs in VecUnit, successfully finish running vecunit_matmul_16x16 --- .../prototype/vector/VecEXUnit.scala | 3 + .../prototype/vector/VecLoadUnit.scala | 2 +- .../prototype/vector/VecStoreUnit.scala | 72 +++++++++++++------ .../memdomain/backend/MemBackend.scala | 10 +-- .../src/CTest/toy/vecunit_matmul_ones.c | 3 +- 5 files changed, 62 insertions(+), 28 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala index f025af87..cc7797ca 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala @@ -63,6 +63,9 @@ class VecEXUnit(val b: GlobalConfig) extends Module { threadId := 0.U // Use thread 0 for computation state := busy } + when(io.ld_ex_i.fire) { + threadId := Mux(threadId === (config.numMulThreads - 1).U, 0.U, threadId + 1.U) + } // ----------------------------------------------------------------------------- // Accept read results from load unit and perform computation diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 1ee2d621..8fa0c28e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -85,7 +85,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Send SRAM read request // ----------------------------------------------------------------------------- - when(state === busy && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { + when(state === busy && io.ld_ex_o.ready) { io.bankReadReq(0).valid := iter_counter < iter io.bankReadReq(0).bits.addr := op1_addr + iter_counter io.bankReadReq(1).valid := iter_counter < iter diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 8665ebae..d70947cf 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -22,6 +22,13 @@ class ex_st_req(b: GlobalConfig) extends Bundle { val iter = UInt(10.W) } +class BankWriteEntry(b: GlobalConfig) extends Bundle { + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val data = UInt(b.memDomain.bankWidth.W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val wmode = Bool() +} + @instantiable class VecStoreUnit(val b: GlobalConfig) extends Module { val config = VectorBallParam() @@ -49,6 +56,8 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) + val writeQueues = VecInit(Seq.fill(outBW)(Module(new Queue(new BankWriteEntry(b), 16)).io)) + // ----------------------------------------------------------------------------- // Set registers when Ctrl instruction arrives // ----------------------------------------------------------------------------- @@ -63,45 +72,68 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { } // ----------------------------------------------------------------------------- -// Accept computation results from EX unit and perform write-back +// Accept computation results from EX unit and push to write queues // ----------------------------------------------------------------------------- - io.ex_st_i.ready := state === busy - io.bankWrite.foreach { acc => - acc.req.valid := false.B - acc.req.bits.addr := 0.U - acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) - acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) - acc.req.bits.wmode := false.B // Default: direct write mode - acc.resp.ready := false.B // Default: not ready for response + io.ex_st_i.ready := state === busy && writeQueues.forall(_.enq.ready) + + for (i <- 0 until outBW) { + writeQueues(i).enq.valid := false.B + writeQueues(i).enq.bits := DontCare } - val waddr = wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + when(io.ex_st_i.fire) { - // Use all outBW channels to share the data write - // Each channel gets a portion of the data for (i <- 0 until outBW) { val elementsPerChannel = InputNum / outBW val startIdx = i * elementsPerChannel val endIdx = startIdx + elementsPerChannel - 1 - io.bankWrite(i).req.valid := true.B - io.bankWrite(i).req.bits.addr := wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + val entry = Wire(new BankWriteEntry(b)) + entry.addr := wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + entry.data := Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) + entry.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + entry.wmode := true.B - // Pack corresponding elements into a UInt - val channelData = Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - io.bankWrite(i).req.bits.data := channelData - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - io.bankWrite(i).req.bits.wmode := true.B // Accumulate mode + writeQueues(i).enq.valid := true.B + writeQueues(i).enq.bits := entry } iter_counter := iter_counter + 1.U } +// ----------------------------------------------------------------------------- +// Drain write queues to bankWrite interface +// ----------------------------------------------------------------------------- + io.bankWrite.foreach { acc => + acc.req.valid := false.B + acc.req.bits.addr := 0.U + acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) + acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + acc.req.bits.wmode := false.B + acc.resp.ready := false.B + } + + for (i <- 0 until outBW) { + writeQueues(i).deq.ready := false.B + + when(writeQueues(i).deq.valid) { + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := writeQueues(i).deq.bits.addr + io.bankWrite(i).req.bits.data := writeQueues(i).deq.bits.data + io.bankWrite(i).req.bits.mask := writeQueues(i).deq.bits.mask + io.bankWrite(i).req.bits.wmode := writeQueues(i).deq.bits.wmode + writeQueues(i).deq.ready := io.bankWrite(i).req.ready + } + } + // Output wr_bank for bank_id setting io.wr_bank_o := wr_bank // ----------------------------------------------------------------------------- // Reset iter counter, commit cmdResp, return to idle state // ----------------------------------------------------------------------------- - when(state === busy && iter_counter >= iter) { + val allQueuesEmpty = writeQueues.forall(q => !q.deq.valid) + val allDataEnqueued = state === busy && iter_counter >= iter + + when(allDataEnqueued && allQueuesEmpty) { state := idle io.cmdResp_o.valid := true.B io.cmdResp_o.bits.commit := true.B diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 59701a75..3a7c359a 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -78,13 +78,13 @@ class MemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read - accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id accPipes(i).io.mem_req.acc_group_id := io.mem_req(i).acc_group_id // Bank-side defaults (only driven when a bank is actually connected) - accPipes(i).io.sramRead.req.ready := false.B - accPipes(i).io.sramRead.resp.valid := false.B - accPipes(i).io.sramRead.resp.bits := DontCare + accPipes(i).io.sramRead.req.ready := false.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare accPipes(i).io.sramWrite.req.ready := false.B accPipes(i).io.sramWrite.resp.valid := false.B @@ -128,7 +128,7 @@ class MemBackend(val b: GlobalConfig) extends Module { for (j <- 0 until b.memDomain.bankNum) { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid - val hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + val hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && (!mappingTable(j).is_acc || (mappingTable(j).is_acc && (mappingTable(j).acc_group_id === io.mem_req(i).acc_group_id))) diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 01fd025a..6f83cc88 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -38,8 +38,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - // clear_u32_matrix(output_matrix, DIM, DIM); - // cpu_matmul(a, b, expected_matrix, size, size, size); + cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); From 3657cbccd575d62ea8db4681098562a7cd3041f0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 00:51:43 +0800 Subject: [PATCH 098/238] [scripts] del: remove old build system. ATTENTION: this update need repo reinstall [workloads] del: remove obsolete legacy libhw libraries and those no longer maintained workloads. [repo] del: remove outdated submodules from .gitmodules [repo] feat: mill version (0.11.4 -> 0.11.12) [nix] refactor: design a two-staged nix installation (combine nix build and nix develop shellhook) --- .github/workflows/{nix.yml => build.yml} | 4 +- .github/workflows/pr.yml | 14 +- .gitmodules | 15 +- README.md | 53 +- arch/.mill-version | 2 +- arch/build.sbt | 5 +- arch/build.sc | 2 +- bb-tests/sardine/package-lock.json | 1 + bb-tests/sardine/run_tests.py | 2 +- bb-tests/workloads/lib/bbhw/CMakeLists.txt | 43 +- .../workloads/lib/bbhw/isa/CMakeLists.txt | 53 - .../workloads/lib/bbhw/mem/CMakeLists.txt | 53 - .../workloads/src/CTest/bebop/CMakeLists.txt | 14 +- .../src/CTest/gemmini/CMakeLists.txt | 11 +- .../workloads/src/CTest/toy/CMakeLists.txt | 18 +- bb-tests/workloads/src/CTest/toy/cim_test.c | 173 - bb-tests/workloads/src/CTest/toy/nnlut_test.c | 110 - bb-tests/workloads/src/CTest/toy/snn_test.c | 112 - bbdev | 1 + compiler | 2 +- evals/.gitignore | 0 evals/run-dc.sh | 150 - flake.lock | 64 +- flake.nix | 42 +- scripts/env-exit.sh | 5 - scripts/init-as-lib.sh | 0 scripts/init.sh | 184 - scripts/install-bebop.sh | 9 - scripts/install-compiler.sh | 50 - scripts/install-doc.sh | 23 - scripts/install-pre-commit.sh | 30 - scripts/install-scalafmt.sh | 25 - scripts/install-t1.sh | 36 - scripts/install-verify-tools.sh | 36 - scripts/install-workflow.sh | 50 - scripts/nix/build-all.sh | 75 +- scripts/nix/build-env-bbdev.nix | 9 +- scripts/nix/build-env-bebop.nix | 10 +- scripts/nix/build-env-clibs.nix | 10 + scripts/nix/build-env-tools.nix | 12 +- scripts/nix/overlay.nix | 11 +- scripts/replace-content.py | 72 - scripts/utils.sh | 19 - sourceme.sh | 44 + {tools => thirdparty}/palladium | 0 thirdparty/picker | 1 - tools/mill/.gitignore | 1 - tools/mill/install-mill.sh | 21 - workflow/.gitignore | 21 - workflow/bbdev | 533 - workflow/mcp-server/README.md | 35 - workflow/mcp-server/server.py | 47 - workflow/mcp-server/tools.py | 480 - workflow/motia.config.ts | 9 - workflow/package-lock.json | 9627 ----------------- workflow/package.json | 28 - workflow/prompts/doc/common/standards.md | 28 - workflow/prompts/doc/customext-doc.md | 41 - workflow/prompts/doc/rtl-doc.md | 38 - workflow/prompts/doc/sardine-doc.md | 41 - workflow/prompts/doc/script-doc.md | 41 - workflow/prompts/doc/sim-doc.md | 41 - workflow/prompts/doc/uvbb-doc.md | 41 - workflow/prompts/doc/workflow-doc.md | 41 - workflow/prompts/doc/workloads-doc.md | 41 - workflow/prompts/new-ball.md | 17 - workflow/prompts/new-spec.md | 911 -- workflow/requirements.txt | 2 - workflow/steps/agent/.gitignore | 1 - workflow/steps/agent/01_agent_api_step.py | 63 - workflow/steps/agent/01_agent_event_step.py | 154 - workflow/steps/agent/README.md | 40 - workflow/steps/agent/example_prompt.md | 22 - .../steps/agent/example_refactor_prompt.md | 37 - workflow/steps/agent/test_code_agent.sh | 90 - workflow/steps/compiler/01_build_api_step.py | 26 - .../steps/compiler/01_build_event_step.py | 56 - workflow/steps/compiler/README.md | 33 - workflow/steps/doc-agent/.env | 2 - .../steps/doc-agent/00_doc_agent_api_step.py | 112 - .../doc-agent/01_doc_agent_event_step.py | 195 - workflow/steps/doc-agent/README.md | 46 - workflow/steps/doc-agent/doc_agent_README.md | 401 - .../doc-agent/doc_integration_event_step.py | 122 - workflow/steps/doc-agent/doc_utils.py | 78 - workflow/steps/doc-agent/link_manager.py | 103 - workflow/steps/doc-agent/summary_manager.py | 111 - workflow/steps/firesim/.gitignore | 1 - .../firesim/01_buildbitstream_api_step.py | 26 - .../firesim/01_buildbitstream_event_step.py | 54 - .../steps/firesim/02_infrasetup_api_step.py | 27 - .../steps/firesim/02_infrasetup_event_step.py | 56 - .../steps/firesim/03_runworkload_api_step.py | 27 - .../firesim/03_runworkload_event_step.py | 56 - workflow/steps/firesim/README.md | 59 - .../firesim/scripts/makefrag/firesim/build.mk | 56 - .../scripts/makefrag/firesim/config.mk | 30 - .../scripts/makefrag/firesim/driver.mk | 70 - .../scripts/makefrag/firesim/metasim.mk | 140 - .../firesim/scripts/yaml/config_build.yaml | 44 - .../scripts/yaml/config_build_recipes.yaml | 64 - .../firesim/scripts/yaml/config_hwdb.yaml | 43 - .../firesim/scripts/yaml/config_runtime.yaml | 110 - workflow/steps/marshal/.gitignore | 1 - workflow/steps/marshal/01_build_api_step.py | 25 - workflow/steps/marshal/01_build_event_step.py | 70 - workflow/steps/marshal/02_launch_api_step.py | 26 - .../steps/marshal/02_launch_event_step.py | 50 - workflow/steps/marshal/README.md | 53 - .../steps/marshal/scripts/interactive.json | 9 - .../marshal/scripts/interactive/host-init.sh | 20 - workflow/steps/marshal/scripts/marshal | 1 - .../steps/marshal/scripts/marshal-config.yaml | 2 - .../steps/palladium/01_verilog_api_step.py | 46 - .../steps/palladium/01_verilog_event_step.py | 184 - workflow/steps/sardine/01_run_api_step.py | 42 - workflow/steps/sardine/01_run_event_step.py | 56 - workflow/steps/sardine/README.md | 34 - workflow/steps/tools/README.md | 435 - workflow/steps/tools/__init__.py | 84 - workflow/steps/tools/agent_tools.py | 129 - workflow/steps/tools/base.py | 114 - workflow/steps/tools/deepwiki_tools.py | 327 - workflow/steps/tools/file_tools.py | 359 - workflow/steps/tools/presets.py | 106 - workflow/steps/tools/registry.py | 131 - workflow/steps/tools/workflow_tools.py | 71 - workflow/steps/uvm/01_builddut_api_step.py | 27 - workflow/steps/uvm/01_builddut_event_step.py | 61 - workflow/steps/uvm/03_build_api_step.py | 27 - workflow/steps/uvm/03_build_event_step.py | 109 - workflow/steps/uvm/README.md | 61 - workflow/steps/verilator/01_clean_api_step.py | 26 - .../steps/verilator/01_clean_event_step.py | 57 - .../steps/verilator/02_verilog_api_step.py | 46 - .../steps/verilator/02_verilog_event_step.py | 93 - workflow/steps/verilator/03_build_api_step.py | 30 - .../steps/verilator/03_build_event_step.py | 137 - workflow/steps/verilator/04_cosim_api_step.py | 40 - .../steps/verilator/04_cosim_event_step.py | 124 - workflow/steps/verilator/04_sim_api_step.py | 40 - workflow/steps/verilator/04_sim_event_step.py | 124 - workflow/steps/verilator/05_run_api_step.py | 53 - workflow/steps/verilator/README.md | 197 - workflow/steps/workload/01_buidl_api_step.py | 38 - .../steps/workload/01_build_event_step.py | 61 - workflow/steps/workload/README.md | 39 - workflow/utils/__init__.py | 10 - workflow/utils/event_common.py | 111 - workflow/utils/path.py | 6 - workflow/utils/port.py | 16 - workflow/utils/search_workload.py | 72 - workflow/utils/stream_run.py | 172 - workflow/vscode | 1 - 154 files changed, 154 insertions(+), 20294 deletions(-) rename .github/workflows/{nix.yml => build.yml} (82%) delete mode 100644 bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt delete mode 100644 bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt delete mode 100644 bb-tests/workloads/src/CTest/toy/cim_test.c delete mode 100644 bb-tests/workloads/src/CTest/toy/nnlut_test.c delete mode 100644 bb-tests/workloads/src/CTest/toy/snn_test.c create mode 160000 bbdev delete mode 100644 evals/.gitignore delete mode 100755 evals/run-dc.sh delete mode 100755 scripts/env-exit.sh delete mode 100755 scripts/init-as-lib.sh delete mode 100755 scripts/init.sh delete mode 100755 scripts/install-bebop.sh delete mode 100755 scripts/install-compiler.sh delete mode 100755 scripts/install-doc.sh delete mode 100755 scripts/install-pre-commit.sh delete mode 100755 scripts/install-scalafmt.sh delete mode 100755 scripts/install-t1.sh delete mode 100755 scripts/install-verify-tools.sh delete mode 100755 scripts/install-workflow.sh create mode 100644 scripts/nix/build-env-clibs.nix delete mode 100755 scripts/replace-content.py delete mode 100644 scripts/utils.sh create mode 100644 sourceme.sh rename {tools => thirdparty}/palladium (100%) delete mode 160000 thirdparty/picker delete mode 100644 tools/mill/.gitignore delete mode 100755 tools/mill/install-mill.sh delete mode 100644 workflow/.gitignore delete mode 100755 workflow/bbdev delete mode 100644 workflow/mcp-server/README.md delete mode 100644 workflow/mcp-server/server.py delete mode 100644 workflow/mcp-server/tools.py delete mode 100644 workflow/motia.config.ts delete mode 100644 workflow/package-lock.json delete mode 100644 workflow/package.json delete mode 100644 workflow/prompts/doc/common/standards.md delete mode 100644 workflow/prompts/doc/customext-doc.md delete mode 100644 workflow/prompts/doc/rtl-doc.md delete mode 100644 workflow/prompts/doc/sardine-doc.md delete mode 100644 workflow/prompts/doc/script-doc.md delete mode 100644 workflow/prompts/doc/sim-doc.md delete mode 100644 workflow/prompts/doc/uvbb-doc.md delete mode 100644 workflow/prompts/doc/workflow-doc.md delete mode 100644 workflow/prompts/doc/workloads-doc.md delete mode 100644 workflow/prompts/new-ball.md delete mode 100644 workflow/prompts/new-spec.md delete mode 100644 workflow/requirements.txt delete mode 100644 workflow/steps/agent/.gitignore delete mode 100644 workflow/steps/agent/01_agent_api_step.py delete mode 100644 workflow/steps/agent/01_agent_event_step.py delete mode 100644 workflow/steps/agent/README.md delete mode 100644 workflow/steps/agent/example_prompt.md delete mode 100644 workflow/steps/agent/example_refactor_prompt.md delete mode 100755 workflow/steps/agent/test_code_agent.sh delete mode 100644 workflow/steps/compiler/01_build_api_step.py delete mode 100644 workflow/steps/compiler/01_build_event_step.py delete mode 100644 workflow/steps/compiler/README.md delete mode 100644 workflow/steps/doc-agent/.env delete mode 100644 workflow/steps/doc-agent/00_doc_agent_api_step.py delete mode 100644 workflow/steps/doc-agent/01_doc_agent_event_step.py delete mode 100644 workflow/steps/doc-agent/README.md delete mode 100644 workflow/steps/doc-agent/doc_agent_README.md delete mode 100644 workflow/steps/doc-agent/doc_integration_event_step.py delete mode 100644 workflow/steps/doc-agent/doc_utils.py delete mode 100644 workflow/steps/doc-agent/link_manager.py delete mode 100644 workflow/steps/doc-agent/summary_manager.py delete mode 100644 workflow/steps/firesim/.gitignore delete mode 100644 workflow/steps/firesim/01_buildbitstream_api_step.py delete mode 100644 workflow/steps/firesim/01_buildbitstream_event_step.py delete mode 100644 workflow/steps/firesim/02_infrasetup_api_step.py delete mode 100644 workflow/steps/firesim/02_infrasetup_event_step.py delete mode 100644 workflow/steps/firesim/03_runworkload_api_step.py delete mode 100644 workflow/steps/firesim/03_runworkload_event_step.py delete mode 100644 workflow/steps/firesim/README.md delete mode 100644 workflow/steps/firesim/scripts/makefrag/firesim/build.mk delete mode 100644 workflow/steps/firesim/scripts/makefrag/firesim/config.mk delete mode 100644 workflow/steps/firesim/scripts/makefrag/firesim/driver.mk delete mode 100644 workflow/steps/firesim/scripts/makefrag/firesim/metasim.mk delete mode 100644 workflow/steps/firesim/scripts/yaml/config_build.yaml delete mode 100644 workflow/steps/firesim/scripts/yaml/config_build_recipes.yaml delete mode 100644 workflow/steps/firesim/scripts/yaml/config_hwdb.yaml delete mode 100644 workflow/steps/firesim/scripts/yaml/config_runtime.yaml delete mode 100644 workflow/steps/marshal/.gitignore delete mode 100644 workflow/steps/marshal/01_build_api_step.py delete mode 100644 workflow/steps/marshal/01_build_event_step.py delete mode 100644 workflow/steps/marshal/02_launch_api_step.py delete mode 100644 workflow/steps/marshal/02_launch_event_step.py delete mode 100644 workflow/steps/marshal/README.md delete mode 100644 workflow/steps/marshal/scripts/interactive.json delete mode 100755 workflow/steps/marshal/scripts/interactive/host-init.sh delete mode 120000 workflow/steps/marshal/scripts/marshal delete mode 100644 workflow/steps/marshal/scripts/marshal-config.yaml delete mode 100644 workflow/steps/palladium/01_verilog_api_step.py delete mode 100644 workflow/steps/palladium/01_verilog_event_step.py delete mode 100644 workflow/steps/sardine/01_run_api_step.py delete mode 100644 workflow/steps/sardine/01_run_event_step.py delete mode 100644 workflow/steps/sardine/README.md delete mode 100644 workflow/steps/tools/README.md delete mode 100644 workflow/steps/tools/__init__.py delete mode 100644 workflow/steps/tools/agent_tools.py delete mode 100644 workflow/steps/tools/base.py delete mode 100644 workflow/steps/tools/deepwiki_tools.py delete mode 100644 workflow/steps/tools/file_tools.py delete mode 100644 workflow/steps/tools/presets.py delete mode 100644 workflow/steps/tools/registry.py delete mode 100644 workflow/steps/tools/workflow_tools.py delete mode 100644 workflow/steps/uvm/01_builddut_api_step.py delete mode 100644 workflow/steps/uvm/01_builddut_event_step.py delete mode 100644 workflow/steps/uvm/03_build_api_step.py delete mode 100644 workflow/steps/uvm/03_build_event_step.py delete mode 100644 workflow/steps/uvm/README.md delete mode 100644 workflow/steps/verilator/01_clean_api_step.py delete mode 100644 workflow/steps/verilator/01_clean_event_step.py delete mode 100644 workflow/steps/verilator/02_verilog_api_step.py delete mode 100644 workflow/steps/verilator/02_verilog_event_step.py delete mode 100644 workflow/steps/verilator/03_build_api_step.py delete mode 100644 workflow/steps/verilator/03_build_event_step.py delete mode 100644 workflow/steps/verilator/04_cosim_api_step.py delete mode 100644 workflow/steps/verilator/04_cosim_event_step.py delete mode 100644 workflow/steps/verilator/04_sim_api_step.py delete mode 100644 workflow/steps/verilator/04_sim_event_step.py delete mode 100644 workflow/steps/verilator/05_run_api_step.py delete mode 100644 workflow/steps/verilator/README.md delete mode 100644 workflow/steps/workload/01_buidl_api_step.py delete mode 100644 workflow/steps/workload/01_build_event_step.py delete mode 100644 workflow/steps/workload/README.md delete mode 100644 workflow/utils/__init__.py delete mode 100644 workflow/utils/event_common.py delete mode 100644 workflow/utils/path.py delete mode 100644 workflow/utils/port.py delete mode 100644 workflow/utils/search_workload.py delete mode 100644 workflow/utils/stream_run.py delete mode 160000 workflow/vscode diff --git a/.github/workflows/nix.yml b/.github/workflows/build.yml similarity index 82% rename from .github/workflows/nix.yml rename to .github/workflows/build.yml index 5ee848b5..5ad32e7b 100644 --- a/.github/workflows/nix.yml +++ b/.github/workflows/build.yml @@ -1,4 +1,4 @@ -name: Nix +name: Build on: pull_request: @@ -13,4 +13,4 @@ jobs: - uses: actions/checkout@v4 - uses: DeterminateSystems/determinate-nix-action@v3 - name: Build Buckyball - run: nix build + run: ./scripts/nix/build-all.sh diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 37ff57ba..0f634ccc 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -10,6 +10,9 @@ jobs: name: PR Test runs-on: cpu-server steps: + - uses: actions/checkout@v4 + - uses: DeterminateSystems/determinate-nix-action@v3 + - name: Print information run: | echo "🎉 The job was automatically triggered by a ${{ github.event_name }} event." @@ -20,9 +23,6 @@ jobs: - name: Pull from the repository shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec - setproxy git fetch origin +refs/pull/${{ github.event.pull_request.number }}/head:refs/remotes/origin/pr/${{ github.event.pull_request.number }} git clean -fd git reset --hard ${{ github.sha }} @@ -30,24 +30,18 @@ jobs: - name: Build Workloads shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec bbdev workload --build - name: Build Verilator shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec bbdev verilator --clean - bbdev verilator --verilog + bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' bbdev verilator --build '--jobs 16' - name: Smoke Test shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec bbdev sardine --run '--workload ctest' - run: echo "🍏 PR Test is ${{ job.status }}." diff --git a/.gitmodules b/.gitmodules index 22a776d4..d93de6ca 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,15 +4,6 @@ [submodule "arch/thirdparty/chipyard"] path = arch/thirdparty/chipyard url = https://github.com/ucb-bar/chipyard.git -[submodule "workflow/vscode"] - path = workflow/vscode - url = https://github.com/DangoSys/buckyball-vscode.git -[submodule "thirdparty/picker"] - path = thirdparty/picker - url = https://github.com/XS-MLVP/picker.git -[submodule "tools/palladium"] - path = tools/palladium - url = https://github.com/SEU-ACAL/awesome-palladium.git [submodule "compiler"] path = compiler url = https://github.com/DangoSys/bb-compiler.git @@ -22,3 +13,9 @@ [submodule "bebop"] path = bebop url = https://github.com/DangoSys/bebop.git +[submodule "bbdev"] + path = bbdev + url = https://github.com/DangoSys/bbdev.git +[submodule "thirdparty/palladium"] + path = thirdparty/palladium + url = https://github.com/SEU-ACAL/awesome-palladium.git diff --git a/README.md b/README.md index b797938d..0dea00bd 100644 --- a/README.md +++ b/README.md @@ -21,68 +21,35 @@ The buckyball framework provides a complete hardware design, simulation verifica ## Quick Start -### Environment Dependencies - -Before getting started, please ensure your system meets the following dependency requirements: - -**Required Software**: -- Anaconda/Miniconda (Python environment management) -- Ninja Build System -- GTKWave (waveform viewer) -- Bash Shell environment (doesn't need to be the primary shell) - -**Installing Dependencies**: -```bash -# Install Anaconda -# Download from: https://www.anaconda.com/download/ - -# Install system tools -sudo apt install ninja-build gtkwave - -# Optional: FireSim passwordless configuration -# Add to /etc/sudoers: user_name ALL=(ALL) NOPASSWD:ALL -``` +### Installation in nix +We use Nix Flake as our mainly build system. If you have not installed nix, install it following the [guide](https://nix.dev/manual/nix/2.28/installation/installing-binary.html), and enable flake following the [wiki](https://nixos.wiki/wiki/Flakes#Enable_flakes). Or you can try the [installer](https://github.com/DeterminateSystems/nix-installer) provided by Determinate Systems, which enables flake by default. -### Source Build **1. Clone Repository** + ```bash git clone https://github.com/DangoSys/buckyball.git -cd buckyball ``` **2. Initialize Environment** ```bash -./scripts/init.sh +cd buckyball +./scripts/nix/build-all.sh ``` -*Note: Initialization takes approximately 3 hours, including dependency downloads and compilation* -**3. Environment Activation** +After the first time installation, you can enter the environment anytime by running: + ```bash -source buckyball/env.sh +nix develop ``` -**4. Verify Installation** +**3. Verify Installation** Run Verilator simulation test to verify installation: ```bash bbdev verilator --run '--jobs 16 --binary ctest_vecunit_matmul_ones_singlecore-baremetal --config sims.verilator.BuckyballToyVerilatorConfig --batch' ``` -### Installation in nix -We use Nix Flake as our alternative build system. If you have not installed nix, install it following the [guide](https://nix.dev/manual/nix/2.28/installation/installing-binary.html), and enable flake following the [wiki](https://nixos.wiki/wiki/Flakes#Enable_flakes). Or you can try the [installer](https://github.com/DeterminateSystems/nix-installer) provided by Determinate Systems, which enables flake by default. - -```bash -git clone https://github.com/DangoSys/buckyball.git -cd buckyball -./scripts/nix/build-all.sh -``` - -After the first time installation, you can enter the environment anytime by running: -```bash -nix develop -``` - ### Buckyball as a library We support providing a streamlined version of buckyball installation, integrated as a generator within Chipyard. @@ -93,7 +60,7 @@ nix develop > We do not provide support for this version as it is not a stable release. -## Quick Tutorial +## Tutorial You can start to learn ball and blink from [here](https://github.com/DangoSys/buckyball/blob/main/docs/bb-note/src/tutorial/tutorial.md) ## Additional Resources diff --git a/arch/.mill-version b/arch/.mill-version index 35ad3442..bd0119f9 100644 --- a/arch/.mill-version +++ b/arch/.mill-version @@ -1 +1 @@ -0.11.4 +0.11.12 diff --git a/arch/build.sbt b/arch/build.sbt index 23bec3b2..19c9d68a 100644 --- a/arch/build.sbt +++ b/arch/build.sbt @@ -34,9 +34,8 @@ lazy val scalaTestSettings = Seq( // ------------------------------------------------------------------------------ lazy val chipyard = ProjectRef(file("thirdparty/chipyard"), "chipyard") lazy val firechip = ProjectRef(file("thirdparty/chipyard"), "firechip") - -// Palladium FPGA subproject (external reference) -lazy val palladium = ProjectRef(file("../tools/palladium"), "palladium") +// Palladium FPGA subproject +lazy val palladium = ProjectRef(file("../thirdparty/palladium"), "palladium") // ------------------------------------------------------------------------------ // Project Settings diff --git a/arch/build.sc b/arch/build.sc index 2b772c37..574a3fae 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -933,7 +933,7 @@ object fpga_shells extends SbtModule { // Palladium FPGA subproject (external reference) object palladium extends SbtModule { - override def millSourcePath = os.pwd / os.up / "tools" / "palladium" + override def millSourcePath = os.pwd / os.up / "thirdparty" / "palladium" override def scalaVersion = "2.13.12" // Add chipyard and fpga_shells as dependencies diff --git a/bb-tests/sardine/package-lock.json b/bb-tests/sardine/package-lock.json index 7ab7d6c7..3d59121d 100644 --- a/bb-tests/sardine/package-lock.json +++ b/bb-tests/sardine/package-lock.json @@ -13,6 +13,7 @@ "version": "2.36.0", "resolved": "https://registry.npmjs.org/allure-commandline/-/allure-commandline-2.36.0.tgz", "integrity": "sha512-ls/4fk2Psv2Tu2PbWFrQPmUnm3gmmO9MBan4MuPWwqdkJPEmln2KRwtvtWYr9Av+e5AnFK1fGXWVyxqJIPiPwA==", + "license": "Apache-2.0", "bin": { "allure": "bin/allure" } diff --git a/bb-tests/sardine/run_tests.py b/bb-tests/sardine/run_tests.py index ef8bf450..88096914 100644 --- a/bb-tests/sardine/run_tests.py +++ b/bb-tests/sardine/run_tests.py @@ -76,7 +76,7 @@ def run_pytest(args=None, use_allure=False): reports_dir.mkdir(exist_ok=True) # Build pytest command - cmd = ["python", "-m", "pytest", "-s", "-v", "-n", "auto"] + cmd = ["python3", "-m", "pytest", "-s", "-v", "-n", "auto"] # 检查 Allure 是否已安装 if use_allure: diff --git a/bb-tests/workloads/lib/bbhw/CMakeLists.txt b/bb-tests/workloads/lib/bbhw/CMakeLists.txt index 90e67f68..74c30af2 100644 --- a/bb-tests/workloads/lib/bbhw/CMakeLists.txt +++ b/bb-tests/workloads/lib/bbhw/CMakeLists.txt @@ -1,41 +1,2 @@ -#------------------------------------------------------------------------------- -# Add subdirectories -#------------------------------------------------------------------------------- -add_subdirectory(mem) -add_subdirectory(isa) - -#------------------------------------------------------------------------------- -# Combine final library - only responsible for linking submodules -#------------------------------------------------------------------------------- - -# 1. Linux version - merge Linux versions of submodules -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-linux.a - COMMAND ${CMAKE_COMMAND} -E make_directory temp_extract_linux - COMMAND ${CMAKE_COMMAND} -E chdir temp_extract_linux ar x ../mem/libbbmem-linux.a - COMMAND ${CMAKE_COMMAND} -E chdir temp_extract_linux ar x ../isa/libbbisa-linux.a - COMMAND ar rcs libbbhw-linux.a temp_extract_linux/*.o - COMMAND ranlib libbbhw-linux.a - COMMAND ${CMAKE_COMMAND} -E remove_directory temp_extract_linux - DEPENDS bbisa-linux-build bbmem-linux-build - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Combining RISC-V Linux version of bbhw library" -) - -add_custom_target(bbhw-linux ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-linux.a) - -# 2. Baremetal version - merge Baremetal versions of submodules -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-baremetal.a - COMMAND ${CMAKE_COMMAND} -E make_directory temp_extract_baremetal - COMMAND ${CMAKE_COMMAND} -E chdir temp_extract_baremetal ar x ../mem/libbbmem-baremetal.a - COMMAND ${CMAKE_COMMAND} -E chdir temp_extract_baremetal ar x ../isa/libbbisa-baremetal.a - COMMAND ar rcs libbbhw-baremetal.a temp_extract_baremetal/*.o - COMMAND ranlib libbbhw-baremetal.a - COMMAND ${CMAKE_COMMAND} -E remove_directory temp_extract_baremetal - DEPENDS bbisa-baremetal-build bbmem-baremetal-build - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Combining RISC-V Baremetal version of bbhw library" -) - -add_custom_target(bbhw-baremetal ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbhw-baremetal.a) +# bbhw is header-only: isa.h and mem.h provide macros (inline asm), no library to build. +# Include path is WORKLOAD_LIB_DIR (workloads/lib), so #include works. diff --git a/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt b/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt deleted file mode 100644 index 46351c67..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# ISA submodule library - -file(GLOB ISA_C_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/*.c") - -# 1. Linux version -add_library(bbisa-linux STATIC IMPORTED) -set_target_properties(bbisa-linux PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a) - -set(LINUX_OBJS "") -foreach(src ${ISA_C_SOURCES}) - get_filename_component(name ${src} NAME_WE) - set(obj "${CMAKE_CURRENT_BINARY_DIR}/linux-${name}.o") - list(APPEND LINUX_OBJS ${obj}) - add_custom_command( - OUTPUT ${obj} - COMMAND riscv64-unknown-linux-gnu-gcc -c ${src} -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../mem -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} - DEPENDS ${src} - COMMENT "Compiling ${name}.c for Linux" - ) -endforeach() - -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a - COMMAND riscv64-unknown-linux-gnu-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a ${LINUX_OBJS} - DEPENDS ${LINUX_OBJS} - COMMENT "Building RISC-V Linux version of ISA library" -) -add_custom_target(bbisa-linux-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-linux.a) - -# 2. Baremetal version -add_library(bbisa-baremetal STATIC IMPORTED) -set_target_properties(bbisa-baremetal PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a) - -set(BAREMETAL_OBJS "") -foreach(src ${ISA_C_SOURCES}) - get_filename_component(name ${src} NAME_WE) - set(obj "${CMAKE_CURRENT_BINARY_DIR}/baremetal-${name}.o") - list(APPEND BAREMETAL_OBJS ${obj}) - add_custom_command( - OUTPUT ${obj} - COMMAND riscv64-unknown-elf-gcc -c ${src} -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../mem -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} - DEPENDS ${src} - COMMENT "Compiling ${name}.c for Baremetal" - ) -endforeach() - -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a - COMMAND riscv64-unknown-elf-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a ${BAREMETAL_OBJS} - DEPENDS ${BAREMETAL_OBJS} - COMMENT "Building RISC-V Baremetal version of ISA library" -) -add_custom_target(bbisa-baremetal-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbisa-baremetal.a) diff --git a/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt b/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt deleted file mode 100644 index 4057b4aa..00000000 --- a/bb-tests/workloads/lib/bbhw/mem/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# MEM submodule library - -file(GLOB MEM_C_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/*.c") - -# 1. Linux version -add_library(bbmem-linux STATIC IMPORTED) -set_target_properties(bbmem-linux PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a) - -set(LINUX_OBJS "") -foreach(src ${MEM_C_SOURCES}) - get_filename_component(name ${src} NAME_WE) - set(obj "${CMAKE_CURRENT_BINARY_DIR}/linux-${name}.o") - list(APPEND LINUX_OBJS ${obj}) - add_custom_command( - OUTPUT ${obj} - COMMAND riscv64-unknown-linux-gnu-gcc -c ${src} -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../isa -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} - DEPENDS ${src} - COMMENT "Compiling ${name}.c for Linux" - ) -endforeach() - -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a - COMMAND riscv64-unknown-linux-gnu-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a ${LINUX_OBJS} - DEPENDS ${LINUX_OBJS} - COMMENT "Building RISC-V Linux version of MEM library" -) -add_custom_target(bbmem-linux-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-linux.a) - -# 2. Baremetal version -add_library(bbmem-baremetal STATIC IMPORTED) -set_target_properties(bbmem-baremetal PROPERTIES IMPORTED_LOCATION ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a) - -set(BAREMETAL_OBJS "") -foreach(src ${MEM_C_SOURCES}) - get_filename_component(name ${src} NAME_WE) - set(obj "${CMAKE_CURRENT_BINARY_DIR}/baremetal-${name}.o") - list(APPEND BAREMETAL_OBJS ${obj}) - add_custom_command( - OUTPUT ${obj} - COMMAND riscv64-unknown-elf-gcc -c ${src} -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/../isa -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o ${obj} - DEPENDS ${src} - COMMENT "Compiling ${name}.c for Baremetal" - ) -endforeach() - -add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a - COMMAND riscv64-unknown-elf-ar rcs ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a ${BAREMETAL_OBJS} - DEPENDS ${BAREMETAL_OBJS} - COMMENT "Building RISC-V Baremetal version of MEM library" -) -add_custom_target(bbmem-baremetal-build ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/libbbmem-baremetal.a) diff --git a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt index 1db5a714..edc9eb6b 100644 --- a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt @@ -5,7 +5,7 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") # Set baremetal compilation flags #------------------------------------------------------------------------------- set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} + -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} -I${CTEST_TOY_WORKLOAD_DIR}) #------------------------------------------------------------------------------- @@ -27,9 +27,6 @@ function(add_linux_test_target TEST_NAME SOURCE_FILE) target_include_directories(${EXECUTABLE} PRIVATE ${WORKLOAD_LIB_DIR} ) - # Ensure dependent libraries are built first and link merged library files - add_dependencies(${EXECUTABLE} bbhw-linux) - target_link_libraries(${EXECUTABLE} ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-linux.a) endfunction() # Generate multicore baremetal version executables @@ -43,16 +40,14 @@ function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a DEPENDS ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/start.S - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) add_custom_target(${TEST_NAME}_multicore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal ) + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) endfunction() # Generate singlecore baremetal version executables @@ -65,17 +60,14 @@ function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a DEPENDS ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) add_custom_target(${TEST_NAME}_singlecore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal - ) + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) endfunction() # Create cross-platform test targets diff --git a/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt b/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt index bab7a611..654003c9 100644 --- a/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt @@ -33,11 +33,7 @@ function(add_linux_test_target TEST_NAME SOURCE_FILE) ${WORKLOAD_LIB_DIR} ${CTEST_GEMMINI_WORKLOAD_DIR} ) - # Ensure dependent libraries are built first and link merged library files - add_dependencies(${EXECUTABLE} bbhw-linux) - target_link_libraries(${EXECUTABLE} - m - ) + target_link_libraries(${EXECUTABLE} m) endfunction() # Generate multicore baremetal version executables @@ -58,7 +54,7 @@ function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) ) add_custom_target(${TEST_NAME}_multicore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal) + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) endfunction() # Generate singlecore baremetal version executables @@ -77,8 +73,7 @@ function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) ) add_custom_target(${TEST_NAME}_singlecore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal - ) + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) endfunction() # Create cross-platform test targets diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index af3548e8..91e898c2 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -26,9 +26,6 @@ function(add_linux_test_target TEST_NAME SOURCE_FILE) target_include_directories(${EXECUTABLE} PRIVATE ${WORKLOAD_LIB_DIR} ) - # Ensure dependent libraries are built first and link merged library files - add_dependencies(${EXECUTABLE} bbhw-linux) - target_link_libraries(${EXECUTABLE} ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-linux.a) endfunction() # Generate multicore baremetal version executables @@ -42,16 +39,14 @@ function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a DEPENDS ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/start.S - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) add_custom_target(${TEST_NAME}_multicore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal ) + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) endfunction() # Generate singlecore baremetal version executables @@ -64,17 +59,14 @@ function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a DEPENDS ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c - ${CMAKE_BINARY_DIR}/workloads/lib/bbhw/libbbhw-baremetal.a COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) add_custom_target(${TEST_NAME}_singlecore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} bbhw-baremetal - ) + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) endfunction() # Create cross-platform test targets @@ -127,11 +119,8 @@ add_cross_platform_test_target(ctest_transpose_test transpose_test.c) add_cross_platform_test_target(ctest_transpose_matmul transpose_matmul.c) add_cross_platform_test_target(ctest_tiled_matmul tiled_matmul.c) add_cross_platform_test_target(ctest_relu_test relu_test.c) -add_cross_platform_test_target(ctest_nnlut_test nnlut_test.c) -add_cross_platform_test_target(ctest_snn_test snn_test.c) add_cross_platform_test_target(ctest_abft_systolic_test abft_systolic_test.c) add_cross_platform_test_target(ctest_conv_test conv_test.c) -add_cross_platform_test_target(ctest_cim_test cim_test.c) add_cross_platform_test_target(ctest_transfer_test transfer_test.c) add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) @@ -162,11 +151,8 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_transpose_matmul ctest_tiled_matmul ctest_relu_test - ctest_nnlut_test - ctest_snn_test ctest_abft_systolic_test ctest_conv_test - ctest_cim_test ctest_transfer_test ctest_vsetvli COMMENT "Building all workloads for Buckyball" diff --git a/bb-tests/workloads/src/CTest/toy/cim_test.c b/bb-tests/workloads/src/CTest/toy/cim_test.c deleted file mode 100644 index 83c3ddb9..00000000 --- a/bb-tests/workloads/src/CTest/toy/cim_test.c +++ /dev/null @@ -1,173 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -#define OP1_SIZE 64 -#define OP2_SIZE 64 -#define RESULT_SIZE 64 - -static elem_t operand1[OP1_SIZE] __attribute__((aligned(64))); -static elem_t operand2[OP2_SIZE] __attribute__((aligned(64))); -static elem_t result[RESULT_SIZE] __attribute__((aligned(64))); -static elem_t expected_result[RESULT_SIZE] __attribute__((aligned(64))); - -// CPU reference computation for CIM operations -int cim_cpu_reference(elem_t *op1, elem_t *op2, elem_t *result, int rows, - int cols, int op_type) { - // op_type: 0=matmul, 1=add, 2=mul - if (op_type == 0) { - // Matrix multiplication: result = op1 * op2 - // Assume op1 is rows x cols, op2 is cols x cols - for (int i = 0; i < rows; i++) { - for (int j = 0; j < cols; j++) { - int32_t sum = 0; - for (int k = 0; k < cols; k++) { - sum += (int32_t)op1[i * cols + k] * (int32_t)op2[k * cols + j]; - } - // Clamp to int8_t range - if (sum > 127) { - result[i * cols + j] = 127; - } else if (sum < -128) { - result[i * cols + j] = -128; - } else { - result[i * cols + j] = (elem_t)sum; - } - } - } - } else if (op_type == 1) { - // Element-wise addition - for (int i = 0; i < rows * cols; i++) { - int32_t sum = (int32_t)op1[i] + (int32_t)op2[i]; - if (sum > 127) { - result[i] = 127; - } else if (sum < -128) { - result[i] = -128; - } else { - result[i] = (elem_t)sum; - } - } - } else if (op_type == 2) { - // Element-wise multiplication - for (int i = 0; i < rows * cols; i++) { - int32_t prod = (int32_t)op1[i] * (int32_t)op2[i]; - if (prod > 127) { - result[i] = 127; - } else if (prod < -128) { - result[i] = -128; - } else { - result[i] = (elem_t)prod; - } - } - } - return 1; -} - -void hw_cim(const char *test_name, elem_t *op1, elem_t *op2, elem_t *result, - int rows, int cols, int op_type, int acc_bank_id) { - // Operand 1 in spad bank 0, operand 2 in spad bank 1, result in spad bank 2 - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - // Move operand 1 into scratchpad - bb_mvin((uintptr_t)op1, op1_bank_id, OP1_SIZE, 1); - bb_fence(); - - // Move operand 2 into scratchpad - bb_mvin((uintptr_t)op2, op2_bank_id, OP2_SIZE, 1); - bb_fence(); - - // Call CIM instruction - // iter is the number of iterations (simplified: use rows*cols for now) - uint32_t iter = rows * cols; - bb_cim(op1_bank_id, op2_bank_id, acc_bank_id, iter, rows, cols, op_type); - bb_fence(); - - // Result will be moved back in run_test for verification -} - -int run_test(const char *test_name, elem_t *op1, elem_t *op2, elem_t *result, - int rows, int cols, int op_type) { - // CPU reference computation - cim_cpu_reference(op1, op2, expected_result, rows, cols, op_type); - - // Allocate accumulator bank - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - - // Hardware computation - hw_cim(test_name, op1, op2, result, rows, cols, op_type, acc_bank_id); - - // Move result back from scratchpad for verification - bb_mvout((uintptr_t)result, acc_bank_id, RESULT_SIZE, 1); - bb_fence(); - - // Verify results - int passed = 1; - for (int i = 0; i < rows; i++) { - for (int j = 0; j < cols; j++) { - int idx = i * cols + j; - if (result[idx] != expected_result[idx]) { - printf("Mismatch at [%d][%d]: expected %d, got %d\n", i, j, - expected_result[idx], result[idx]); - passed = 0; - } - } - } - - return passed; -} - -int test_cim(int seed) { - // Initialize operands with random values (8x8 matrices) - int rows = 8; - int cols = 8; - for (int i = 0; i < OP1_SIZE; i++) { - operand1[i] = (elem_t)(rand() % 256 - 128); - } - for (int i = 0; i < OP2_SIZE; i++) { - operand2[i] = (elem_t)(rand() % 256 - 128); - } - - // Test matrix multiplication (op_type = 0) - int passed = - run_test("CIM-MATMUL", operand1, operand2, result, rows, cols, 0); - if (!passed) { - return 0; - } - - // Test element-wise addition (op_type = 1) - passed = run_test("CIM-ADD", operand1, operand2, result, rows, cols, 1); - if (!passed) { - return 0; - } - - // Test element-wise multiplication (op_type = 2) - passed = run_test("CIM-MUL", operand1, operand2, result, rows, cols, 2); - if (!passed) { - return 0; - } - - return passed; -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - - int passed = test_cim(5); - if (passed) { - printf("CIM test PASSED!!!!\n"); - } else { - printf("CIM test FAILED\n"); - } - return (!passed); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/nnlut_test.c b/bb-tests/workloads/src/CTest/toy/nnlut_test.c deleted file mode 100644 index 677bde12..00000000 --- a/bb-tests/workloads/src/CTest/toy/nnlut_test.c +++ /dev/null @@ -1,110 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); - -// Simple LUT for reference (256 entries) -static elem_t cpu_lut[256]; - -void init_lut() { - // Initialize a simple LUT: identity function with saturation - // In real NN-LUT, this would contain pre-computed activation function values - for (int i = 0; i < 256; i++) { - int val = (int8_t)i; - if (val < -128) { - cpu_lut[i] = -128; - } else if (val > 127) { - cpu_lut[i] = 127; - } else { - cpu_lut[i] = val; - } - } -} - -void hw_nnlut(const char *test_name, elem_t *a, elem_t *b, int size) { - // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_bank_id = 0; - uint32_t wr_bank_id = 1; - // Move input into scratchpad bank0, starting at offset 0, iterate size times - // row-wise - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_fence(); - // Call NN-LUT instruction - bb_nnlut(op1_bank_id, wr_bank_id, size); - bb_fence(); - - // Result will be moved back in run_test for verification -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - // CPU reference computation - nnlut_cpu_reference(a, b, size); - - // Hardware computation - hw_nnlut(test_name, a, b, size); - - // Move result back from scratchpad for verification - uint32_t wr_bank_id = 1; - bb_mvout((uintptr_t)output_matrix_b, wr_bank_id, size, 1); - bb_fence(); - - // Verify results - int passed = 1; - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - int idx = i * size + j; - if (output_matrix_b[idx] != b[idx]) { - printf("Mismatch at [%d][%d]: expected %d, got %d\n", i, j, b[idx], - output_matrix_b[idx]); - passed = 0; - } - } - } - - return passed; -} - -int nnlut_cpu_reference(elem_t *input, elem_t *output, int size) { - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - elem_t val = input[i * size + j]; - // Convert to unsigned index (0-255) - uint8_t idx = (uint8_t)val; - output[i * size + j] = cpu_lut[idx]; - } - } - return 1; -} - -int test_nnlut(int seed) { - init_lut(); - init_i8_random_matrix(input_matrix_a, DIM, DIM, seed); - - // Run hardware test with verification - return run_test("NN-LUT", input_matrix_a, output_matrix_b, DIM); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - - int passed = test_nnlut(5); - if (passed) { - printf("NN-LUT test PASSED!!!!\n"); - } else { - printf("NN-LUT test FAILED\n"); - } - return (!passed); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/snn_test.c b/bb-tests/workloads/src/CTest/toy/snn_test.c deleted file mode 100644 index 9c6d9ef4..00000000 --- a/bb-tests/workloads/src/CTest/toy/snn_test.c +++ /dev/null @@ -1,112 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t output_matrix_b[DIM * DIM] __attribute__((aligned(64))); - -// Simple LIF neuron model for CPU reference -int snn_cpu_reference(elem_t *input, elem_t *output, int size, - uint8_t threshold, uint8_t leak_factor) { - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - int val = (int8_t)input[i * size + j]; - - // Apply leak: multiply by leak_factor, then divide by 256 - int leaked = (val * (int)leak_factor) >> 8; - - // Fire condition: if leaked >= threshold, output threshold, else output - // leaked Clamp to threshold range - if (leaked >= (int)threshold) { - output[i * size + j] = (elem_t)threshold; - } else if (leaked < -(int)threshold) { - output[i * size + j] = (elem_t)(-threshold); - } else { - output[i * size + j] = (elem_t)leaked; - } - } - } - return 1; -} - -void hw_snn(const char *test_name, elem_t *a, elem_t *b, int size, - uint8_t threshold, uint8_t leak_factor) { - // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_bank_id = 0; - uint32_t wr_bank_id = 1; - - // Move input into scratchpad bank0, starting at offset 0, iterate size times - // row-wise - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_fence(); - // Call SNN instruction - bb_snn(op1_bank_id, wr_bank_id, size, threshold, leak_factor); - bb_fence(); - - // Result will be moved back in run_test for verification -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size, - uint8_t threshold, uint8_t leak_factor) { - // CPU reference computation - snn_cpu_reference(a, b, size, threshold, leak_factor); - - // Hardware computation - hw_snn(test_name, a, b, size, threshold, leak_factor); - - // Move result back from scratchpad for verification - uint32_t wr_bank_id = 1; - bb_mvout((uintptr_t)output_matrix_b, wr_bank_id, size, 1); - bb_fence(); - - // Verify results - int passed = 1; - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - int idx = i * size + j; - if (output_matrix_b[idx] != b[idx]) { - printf("Mismatch at [%d][%d]: expected %d, got %d\n", i, j, b[idx], - output_matrix_b[idx]); - passed = 0; - } - } - } - - return passed; -} - -int test_snn(int seed) { - // Initialize input matrix with random values - init_i8_random_matrix(input_matrix_a, DIM, DIM, seed); - - // Test with default parameters: threshold=127, leak_factor=240 - uint8_t threshold = 127; - uint8_t leak_factor = 240; // 240/256 ≈ 0.9375 - - // Run hardware test with verification - return run_test("SNN", input_matrix_a, output_matrix_b, DIM, threshold, - leak_factor); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - - int passed = test_snn(5); - if (passed) { - printf("SNN test PASSED!!!!\n"); - } else { - printf("SNN test FAILED\n"); - } - return (!passed); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bbdev b/bbdev new file mode 160000 index 00000000..a97a1977 --- /dev/null +++ b/bbdev @@ -0,0 +1 @@ +Subproject commit a97a1977dcd125e3a4b89f0b2cb3a09a022cda0c diff --git a/compiler b/compiler index b709653f..1a3d0383 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit b709653f56d2aec77491f74be5f485cb912c80bb +Subproject commit 1a3d038338e5251ed191506674544630efc2ecf8 diff --git a/evals/.gitignore b/evals/.gitignore deleted file mode 100644 index e69de29b..00000000 diff --git a/evals/run-dc.sh b/evals/run-dc.sh deleted file mode 100755 index 1353c978..00000000 --- a/evals/run-dc.sh +++ /dev/null @@ -1,150 +0,0 @@ -#!/bin/bash - -# exit script if any command fails -set -e -set -o pipefail - - -# DigitalTop -while [[ $# -gt 0 ]]; do - case $1 in - --srcdir) - SRC_DIR="$2" - shift 2 - ;; - --top) - TOP_MODULE="$2" - shift 2 - ;; - *) - echo "Unknown option: $1" - echo "Usage: $0 --srcdir --top [top_module](Optional)" - echo "Example: $0 --srcdir arch/VecBall_1 --top VecBall_1" - exit 1 - ;; - esac -done - -if [ -z "$SRC_DIR" ]; then - echo "Error: Missing required parameter: srcdir" - echo "Usage: $0 --srcdir --top [top_module](Optional)" - echo "Example: $0 --srcdir arch/VecBall_1 --top VecBall_1" - exit 1 -fi - - - -CYDIR=$(git rev-parse --show-toplevel) - -WORK_DIR="${CYDIR}/bb-tests/output/dc" -DESIGN_DIR="${CYDIR}/bb-tests/output/dc/design" -REPORT_DIR="${CYDIR}/bb-tests/output/dc/reports" -TMP_DIR="${CYDIR}/bb-tests/output/dc/tmp" -TCL_FILE="${CYDIR}/bb-tests/output/dc/dc_script.tcl" -DB_FILE="/opt/dc/lib/TSMCHOME/SRAM_m4swbsoffg0p99v0c/" - -mkdir -p $WORK_DIR -mkdir -p $DESIGN_DIR -mkdir -p $REPORT_DIR -mkdir -p $TMP_DIR - -#------------------------------------------------------------------- -# Step0 Execute build Verilator -#------------------------------------------------------------------- -# ${CYDIR}/voyager-test/scripts/build-verilator.sh --config ${CONFIG} - -#------------------------------------------------------------------- -# Step1 Copy Verilog files for corresponding Config to work directory -#------------------------------------------------------------------- -DESIGN_SOURCE_DIR="${CYDIR}/${SRC_DIR}" -rm -rf ${DESIGN_DIR}/* -cp -r ${DESIGN_SOURCE_DIR}/* ${DESIGN_DIR}/ - -#------------------------------------------------------------------- -# Step2 Replace SRAM -#------------------------------------------------------------------- -# echo "Checking SRAM File..." -# python ${CYDIR}/voyager-test/scripts/read_json.py $DB_FILE $DESIGN_DIR "/home/hxm123/tapeout-Voyager/sims/verilator/generated-src/chipyard.harness.TestHarness.GemminiRocketConfig/gen-collateral/metadata/seq_mems.json" - -#------------------------------------------------------------------- -# Step3 Write tcl script -#------------------------------------------------------------------- - - -# Format file paths as Tcl required string (space-separated) -tcl_db_list="" - - -cat > $TCL_FILE << EOF -# Set search path -set search_path [list . $DESIGN_DIR] -define_design_lib work -path $TMP_DIR - -set target_library "$tcl_db_list\ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_basic.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ccs.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ecsm.db \ -" -set link_library "$tcl_db_list\ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_basic.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ccs.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ecsm.db \ -" - -# Read design files -set file_list [glob -nocomplain -directory $DESIGN_DIR *.sv ] -analyze -format sverilog \$file_list -elaborate $TOP_MODULE - -# Set top module name -set current_design "$TOP_MODULE" - -# Link design -link - -create_clock -name clk1 -period 2 [get_ports clock] - -set_clock_uncertainty 0.6 [get_clocks clock] - -set_input_delay 1.2 -clock clk1 [remove_from_collection [all_inputs] [get_ports clock]] -set_output_delay 0.6 -clock clk1 [all_outputs] - -# Same frequency same phase - -set_clock_equivalence clk1 - -# Output load - -set_load 0.08 [all_outputs] - -set_input_transition 0.2 [remove_from_collection [all_inputs] [get_ports clock]] - -set_clock_transition 0.08 [get_clocks clk1] - - - -compile_ultra -scan -write -format ddc -hierarchy -output $REPORT_DIR/design_compiled.ddc - -# Generate reports -report_area -hierarchy -nosplit > $REPORT_DIR/area.rpt -report_timing > $REPORT_DIR/timing.rpt -report_power -hierarchy > $REPORT_DIR/power.rpt - -# Save netlist -write -format verilog -output $REPORT_DIR/netlist.v - -# Exit -exit -EOF - -#------------------------------------------------------------------- -# Step4 Run DC -#------------------------------------------------------------------- -echo "Running DC synthesis for design: ${CONFIG}, top module: $TOP_MODULE" -dc_shell -f $TCL_FILE - -# rm $TCL_FILE -rm -rf ${CYDIR}/alib-52 - -echo "Synthesis completed. Reports are available in $REPORT_DIR directory." diff --git a/flake.lock b/flake.lock index b776f047..91ac58d3 100644 --- a/flake.lock +++ b/flake.lock @@ -1,31 +1,5 @@ { "nodes": { - "bebop": { - "inputs": { - "flake-utils": [ - "flake-utils" - ], - "gem5-src": "gem5-src", - "nixpkgs": [ - "nixpkgs" - ], - "spike-src": "spike-src" - }, - "locked": { - "lastModified": 1770831670, - "narHash": "sha256-AyTkiYE6TIxq1KVi7EixdPScmtcY4LmbGpPUR0NvCII=", - "owner": "DangoSys", - "repo": "bebop", - "rev": "5f65c8f264b176845924c1ec17935ae4c3e103d7", - "type": "github" - }, - "original": { - "owner": "DangoSys", - "repo": "bebop", - "rev": "5f65c8f264b176845924c1ec17935ae4c3e103d7", - "type": "github" - } - }, "flake-utils": { "inputs": { "systems": "systems" @@ -39,24 +13,8 @@ "type": "github" }, "original": { - "id": "flake-utils", - "type": "indirect" - } - }, - "gem5-src": { - "flake": false, - "locked": { - "lastModified": 1754946347, - "narHash": "sha256-cvJMe6VEKUE1vnS/IvZR2pBDvgw5KMaUBjx6ouUgmo4=", - "owner": "gem5", - "repo": "gem5", - "rev": "ddd4ae35adb0a3df1f1ba11e9a973a5c2f8c2944", - "type": "github" - }, - "original": { - "owner": "gem5", - "repo": "gem5", - "rev": "ddd4ae35adb0a3df1f1ba11e9a973a5c2f8c2944", + "owner": "numtide", + "repo": "flake-utils", "type": "github" } }, @@ -78,28 +36,10 @@ }, "root": { "inputs": { - "bebop": "bebop", "flake-utils": "flake-utils", "nixpkgs": "nixpkgs" } }, - "spike-src": { - "flake": false, - "locked": { - "lastModified": 1766824496, - "narHash": "sha256-GysjOv1077ogF2ajkcQpw7TX4KKrbCIwz9jFst24LoI=", - "owner": "riscv-software-src", - "repo": "riscv-isa-sim", - "rev": "45fe6c110aed80d5689752236ba0a668f093ce48", - "type": "github" - }, - "original": { - "owner": "riscv-software-src", - "repo": "riscv-isa-sim", - "rev": "45fe6c110aed80d5689752236ba0a668f093ce48", - "type": "github" - } - }, "systems": { "locked": { "lastModified": 1681028828, diff --git a/flake.nix b/flake.nix index 5c491c40..82007866 100644 --- a/flake.nix +++ b/flake.nix @@ -3,20 +3,14 @@ inputs = { nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; - # flake-utils.url = "github:numtide/flake-utils"; - bebop = { - url = "github:DangoSys/bebop/5f65c8f264b176845924c1ec17935ae4c3e103d7"; - inputs.nixpkgs.follows = "nixpkgs"; - inputs.flake-utils.follows = "flake-utils"; - }; + flake-utils.url = "github:numtide/flake-utils"; }; - outputs = { self, nixpkgs, flake-utils, bebop }@inputs: + outputs = { self, nixpkgs, flake-utils }@inputs: flake-utils.lib.eachDefaultSystem (system: let - bebopPkgs = bebop.packages.${system}; - overlay = import ./scripts/nix/overlay.nix { inherit bebopPkgs; }; + overlay = import ./scripts/nix/overlay.nix; pkgs = import nixpkgs { overlays = [ overlay ]; inherit system; }; in { @@ -35,22 +29,25 @@ # python environment python.python3Packages - # Bebop tools - pkgs.bebop.rustc - pkgs.bebop.cargo - pkgs.bebop.rustfmt - pkgs.bebop.clippy - pkgs.bebop.bebop - pkgs.bebop.bebopHost - pkgs.bebop.spike - pkgs.bebop.gem5 + # Bebop dependencies (rust toolchain) + bebop.rustc + bebop.cargo + bebop.rustfmt + bebop.clippy - # Workflow dev tools + # bbdev dependencies bbdev.nodejs + bbdev.pnpm bbdev.gcc bbdev.gnumake bbdev.pkg-config + # C libraries (headers + link libs) + clibs.zlib-dev + clibs.zlib + clibs.readline-dev + clibs.readline + # Scala tools scala.mill scala.scalafmt @@ -75,12 +72,7 @@ echo "Warning: result/bin not found. Run 'nix build' first." fi - export BUDDY_MLIR_BUILD_DIR="$PWD/compiler/build" - export LLVM_MLIR_BUILD_DIR="$PWD/compiler/llvm/build" - export PYTHONPATH="$PWD/compiler/llvm/build/tools/mlir/python_packages/mlir_core:$PWD/compiler/build/python_packages:$PYTHONPATH" - export PATH="$PWD/workflow:$PATH" - export RISCV="$PWD/result" - export PATH="$PWD/thirdparty/libgloss/install/lib:$PATH" + source "$PWD/sourceme.sh" echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" diff --git a/scripts/env-exit.sh b/scripts/env-exit.sh deleted file mode 100755 index 9ea2ddc1..00000000 --- a/scripts/env-exit.sh +++ /dev/null @@ -1,5 +0,0 @@ -# conda exit -# conda deactivate - -# path -export PATH=$(echo $PATH | tr ':' '\n' | grep -v buckyball | tr '\n' ':' | sed 's/:$//') diff --git a/scripts/init-as-lib.sh b/scripts/init-as-lib.sh deleted file mode 100755 index e69de29b..00000000 diff --git a/scripts/init.sh b/scripts/init.sh deleted file mode 100755 index 809b7588..00000000 --- a/scripts/init.sh +++ /dev/null @@ -1,184 +0,0 @@ -#!/usr/bin/env bash - -# exit script if any command fails -set -e -set -o pipefail - -BBDIR=$(git rev-parse --show-toplevel) - -source ${BBDIR}/scripts/utils.sh - -usage() { - echo "Usage: ${0} [OPTIONS] " - echo "" - echo "Helper script to fully initialize repository that wraps other scripts." - echo "By default it initializes/installs things in the following order:" - echo " 1. Setup workflow management system" - echo " 2. Buckyball submodules" - echo " 3. Toolchain installation" - echo " 4. Compiler (buddy-mlir) pre-compile sources" - echo " 5. bb-tests (workloads) pre-compile sources" - echo " 6. Install Chipyard and Firesim" - echo " 7. Buckyball pre-compile sources" - echo " 8. Setup document management system" - echo " 9. Install func-sim" - echo " 10. Runs repository clean-up" - echo "" - echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" - echo "" - echo "Options" - echo " --help -h : Display this message" - echo " --verbose -v : Verbose printout" - echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')." - echo " --admin : Add this option to install the admin tools (You dont need do this)." - echo " --conda-env-name : Add this option to specify the conda environment name. Default is buckyball." - - exit "$1" -} - -SKIP_LIST=() -VERBOSE_FLAG="" -ADMIN_MODE=false -CONDA_ENV_NAME="buckyball" - -while [ "$1" != "" ]; -do - case $1 in - -h | --help ) - usage 3 ;; - --verbose | -v) - VERBOSE_FLAG=$1 - set -x ;; - --skip | -s) - shift - SKIP_LIST+=(${1}) ;; - --admin) - ADMIN_MODE=true ;; - --conda-env-name) - shift - CONDA_ENV_NAME=${1} ;; - * ) - echo "Error: invalid option $1" >&2 - usage 1 ;; - esac - shift -done - -# return true if the arg is not found in the SKIP_LIST -run_step() { - local value=$1 - [[ ! " ${SKIP_LIST[*]} " =~ " ${value} " ]] -} - -function begin_step -{ - thisStepNum=$1; - thisStepDesc=$2; - - # Color codes - local BLUE='\033[0;34m' - local GREEN='\033[0;32m' - local YELLOW='\033[1;33m' - local NC='\033[0m' # No Color - - echo -e "${BLUE} =========================================================================" - echo -e "${GREEN} ==== BUCKYBALL SETUP STEP ${YELLOW}$thisStepNum${GREEN}: ${YELLOW}$thisStepDesc${GREEN} " - echo -e "${BLUE} =========================================================================" - echo -e "${NC}" -} - -if run_step "0"; then - begin_step "0" "init env.sh" - replace_content ${BBDIR}/env.sh base-conda-setup "source $(conda info --base)/etc/profile.d/conda.sh" -fi - -if run_step "1"; then - begin_step "1" "submodules init" - git submodule update --init - replace_content ${BBDIR}/arch/thirdparty/chipyard/env.sh base-conda-setup "source $(conda info --base)/etc/profile.d/conda.sh" -fi - -# setup and install chipyard environment -if run_step "2"; then - begin_step "2" "Chipyard environment setup" - cd ${BBDIR}/arch/thirdparty/chipyard && ./build-setup.sh --conda-env-name ${CONDA_ENV_NAME} - cp ${BBDIR}/arch/thirdparty/chipyard/env.sh ${BBDIR}/env.sh - replace_content ${BBDIR}/env.sh build-setup-conda "conda activate ${CONDA_ENV_NAME} -source ${BBDIR}/arch/thirdparty/chipyard/scripts/fix-open-files.sh" - replace_content ${BBDIR}/env.sh bb-dir-helper "export BB_DIR=${BBDIR}" -fi - -if run_step "3"; then - begin_step "3" "Compiler (buddy-mlir) pre-compile sources" - cd ${BBDIR} - source ${BBDIR}/env.sh - ./scripts/install-compiler.sh -fi - -if run_step "4"; then - begin_step "4" "Install bebop" - source ${BBDIR}/env.sh - # ${BBDIR}/scripts/install-bebop.sh - echo "bebop is not installed" -fi - -if run_step "5"; then - begin_step "5" "bb-tests (workloads) pre-compile sources" - source ${BBDIR}/env.sh - cd ${BBDIR}/bb-tests - mkdir -p build && cd build - cmake -G Ninja ../ - ninja -j$(nproc) -fi - -if run_step "6"; then - begin_step "6" "Install requirements for sardine" - source ${BBDIR}/env.sh - pip install -r ${BBDIR}/bb-tests/sardine/requirements.txt - npm install --prefix ${BBDIR}/bb-tests/sardine allure-commandline -fi - - -if run_step "7"; then - begin_step "7" "Install document management system" - source ${BBDIR}/env.sh - ${BBDIR}/scripts/install-doc.sh -fi - -if run_step "8"; then - begin_step "8" "Init workflow management system" - source ${BBDIR}/env.sh - ${BBDIR}/scripts/install-workflow.sh -fi - -if run_step "9"; then - begin_step "9" "Install mill" - source ${BBDIR}/env.sh - cd ${BBDIR}/tools/mill - ./install-mill.sh -fi - -if run_step "10"; then - begin_step "10" "install fmt tools" - source ${BBDIR}/env.sh - cd ${BBDIR} - ${BBDIR}/scripts/install-scalafmt.sh -fi - -if run_step "11"; then - begin_step "11" "Install pre-commit" - source ${BBDIR}/env.sh - # ${BBDIR}/scripts/install-pre-commit.sh - pip install pre-commit - cd ${BBDIR} - pre-commit install -fi - -# if run_step "12"; then -# begin_step "12" "Install verify tools" -# source ${BBDIR}/env.sh -# # ${BBDIR}/scripts/install-verify-tools.sh -# echo "veriy toolchain is not installed" -# fi - -begin_step "END" "Setup completed successfully!" diff --git a/scripts/install-bebop.sh b/scripts/install-bebop.sh deleted file mode 100755 index 6e89ddc0..00000000 --- a/scripts/install-bebop.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/bash - -set -e - -BBDIR=$(git rev-parse --show-toplevel) -source ${BBDIR}/scripts/utils.sh - -cd $BBDIR/bebop -./host/install.sh diff --git a/scripts/install-compiler.sh b/scripts/install-compiler.sh deleted file mode 100755 index 72e728c4..00000000 --- a/scripts/install-compiler.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env bash - -# exit script if any command fails -set -e -set -o pipefail - -BBDIR=$(git rev-parse --show-toplevel) -BUDDY_MLIR_DIR=${BBDIR}/compiler - -# get helpful utilities -source ${BBDIR}/scripts/utils.sh - -source ${BBDIR}/env.sh -pip install -r ${BUDDY_MLIR_DIR}/requirements.txt - -cd ${BUDDY_MLIR_DIR} -git submodule update --init llvm - -mkdir -p llvm/build && cd llvm/build -cmake -G Ninja ../llvm \ - -DLLVM_ENABLE_PROJECTS="mlir;clang" \ - -DLLVM_TARGETS_TO_BUILD="host;RISCV" \ - -DLLVM_ENABLE_ASSERTIONS=ON \ - -DCMAKE_BUILD_TYPE=RELEASE \ - -DMLIR_ENABLE_BINDINGS_PYTHON=ON \ - -DPython3_EXECUTABLE=$(which python3) -ninja #check-mlir check-clang - -cd ${BUDDY_MLIR_DIR} -mkdir -p build && cd build -cmake -G Ninja .. \ - -DMLIR_DIR=$PWD/../llvm/build/lib/cmake/mlir \ - -DLLVM_DIR=$PWD/../llvm/build/lib/cmake/llvm \ - -DLLVM_ENABLE_ASSERTIONS=ON \ - -DCMAKE_BUILD_TYPE=RELEASE \ - -DBUDDY_MLIR_ENABLE_PYTHON_PACKAGES=ON \ - -DPython3_EXECUTABLE=$(which python3) \ - -DPython_EXECUTABLE=$(which python3) \ - -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -ninja -#ninja check-buddy - -replace_content ${BBDIR}/env.sh install-compiler "# line auto-generated by $0 -export BUDDY_MLIR_BUILD_DIR=${BUDDY_MLIR_DIR}/build -export LLVM_MLIR_BUILD_DIR=${BUDDY_MLIR_DIR}/llvm/build -export PYTHONPATH=${BUDDY_MLIR_DIR}/llvm/build/tools/mlir/python_packages/mlir_core:${BUDDY_MLIR_DIR}/build/python_packages:\${PYTHONPATH}" - -export BUDDY_MLIR_BUILD_DIR=${BUDDY_MLIR_DIR}/build -export LLVM_MLIR_BUILD_DIR=${BUDDY_MLIR_DIR}/llvm/build -export PYTHONPATH=${BUDDY_MLIR_DIR}/llvm/build/tools/mlir/python_packages/mlir_core:${BUDDY_MLIR_DIR}/build/python_packages:${PYTHONPATH} diff --git a/scripts/install-doc.sh b/scripts/install-doc.sh deleted file mode 100755 index 278d4441..00000000 --- a/scripts/install-doc.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -set -e - -BBDIR=$(git rev-parse --show-toplevel) -source ${BBDIR}/scripts/utils.sh - -# install rustup -curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y -source $HOME/.cargo/env - -replace_content ${BBDIR}/env.sh bb-doc-server "source $HOME/.cargo/env" - -# install mdbook and mdbook-linkcheck -cargo install mdbook -cargo install mdbook-linkcheck -cargo install mdbook-pdf -cargo install mdbook-toc -cargo install mdbook-mermaid - -mdbook-mermaid install ${BBDIR}/docs/bb-note/ - -# mdbook serve --open -p 3001 diff --git a/scripts/install-pre-commit.sh b/scripts/install-pre-commit.sh deleted file mode 100755 index 5c17b388..00000000 --- a/scripts/install-pre-commit.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env bash -set -e - -BBDIR=$(git rev-parse --show-toplevel) -source ${BBDIR}/scripts/utils.sh - -# Check if scalafmt is already installed -if command -v scalafmt &> /dev/null; then - echo "scalafmt is already installed" - scalafmt --version - exit 0 -fi - -# If not, install coursier and scalafmt -if ! command -v cs &> /dev/null; then - echo "Installing coursier..." - curl -fL https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-linux.gz | gzip -d > cs - chmod +x cs && ./cs setup --yes - rm -f cs -fi - -replace_content ${BBDIR}/env.sh install-pre-commit "export PATH=$HOME/.local/share/coursier/bin:\$PATH" - -# Install scalafmt -echo "Installing scalafmt..." -cs install scalafmt - -echo "Installation complete!" -echo "scalafmt version:" -scalafmt --version diff --git a/scripts/install-scalafmt.sh b/scripts/install-scalafmt.sh deleted file mode 100755 index 51605bb9..00000000 --- a/scripts/install-scalafmt.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env bash -set -e - -BBDIR=$(git rev-parse --show-toplevel) -source ${BBDIR}/scripts/utils.sh - -INSTALL_DIR="${HOME}/.local/bin" -mkdir -p "${INSTALL_DIR}" - -SCALAFMT_VERSION=$(grep "^version" ${BBDIR}/arch/.scalafmt.conf 2>/dev/null | sed 's/version = //;s/"//g' | tr -d ' ' || echo "3.9.6") - -if command -v cs &> /dev/null; then - cs install scalafmt:${SCALAFMT_VERSION} --install-dir "${INSTALL_DIR}" -else - echo "Downloading coursier..." - curl -fL https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-linux.gz | gzip -d > /tmp/cs - chmod +x /tmp/cs - /tmp/cs install scalafmt:${SCALAFMT_VERSION} --install-dir "${INSTALL_DIR}" - rm /tmp/cs -fi - -replace_content ${BBDIR}/env.sh install-scalafmt "# line auto-generated by $0 -export PATH=${INSTALL_DIR}:\${PATH}" - -echo "✓ Scalafmt ${SCALAFMT_VERSION} installed to ${INSTALL_DIR}" diff --git a/scripts/install-t1.sh b/scripts/install-t1.sh deleted file mode 100755 index fede6ba7..00000000 --- a/scripts/install-t1.sh +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/bash - -# exit script if any command fails -set -e -set -o pipefail - -BBDIR=$(git rev-parse --show-toplevel) -T1DIR=${BBDIR}/arch/thirdparty/t1 - -source ${BBDIR}/scripts/utils.sh - -cd ${BBDIR} -source ${BBDIR}/env.sh - -if ! cargo --version > /dev/null 2>&1; then - echo "cargo is not installed, this shoule be installed at the install-doc step" - exit 1 -fi - -# To avoid the Buckyball project requiring root privileges, -# we opted for the slightly more cumbersome nix-user-chroot installation. -cargo install nix-user-chroot -mkdir -p -m 0755 ~/.nix -curl -L https://nixos.org/nix/install -o /tmp/nix-install.sh -nix-user-chroot ~/.nix bash /tmp/nix-install.sh - -# if you see the following error -# error: filesystem error: read_symlink: Invalid argument [/home/xxxx/.nix-profile] -# this means you may repeated the execution of this Nix installation. - - -# enable nix-command and flakes -nix-user-chroot ~/.nix bash -c 'mkdir -p ~/.config/nix && echo "experimental-features = nix-command flakes" > ~/.config/nix/nix.conf' -replace_content ${BBDIR}/env.sh install-nix "if [ -z \"\$IN_NIX_ENV\" ] && ! command -v nix > /dev/null 2>&1; then - IN_NIX_ENV=1 nix-user-chroot ~/.nix ${SHELL} -c \"source ${BBDIR}/env.sh && ${SHELL}\" -fi" "head" diff --git a/scripts/install-verify-tools.sh b/scripts/install-verify-tools.sh deleted file mode 100755 index 1e7c056a..00000000 --- a/scripts/install-verify-tools.sh +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/bash - -BBDIR=$(git rev-parse --show-toplevel) -source ${BBDIR}/scripts/utils.sh - -if [ -z "$CONDA_PREFIX" ]; then - echo "CONDA environment is not set, please source the env.sh" - exit 1 -else - PREFIX=$CONDA_PREFIX/picker - echo "Picker will be installed to $PREFIX" -fi - -# ================================================================== -# install picker -# ================================================================== - -# === install dependencies for picker -mkdir -p $BBDIR/tmp && cd $BBDIR/tmp -wget "https://github.com/chipsalliance/verible/releases/download/v0.0-4007-g98bdb38a/verible-v0.0-4007-g98bdb38a-linux-static-x86_64.tar.gz" -tar -xzf verible-v0.0-4007-g98bdb38a-linux-static-x86_64.tar.gz -mv verible-v0.0-4007-g98bdb38a/bin/* $PREFIX -cd $BBDIR && rm -rf $BBDIR/tmp - -conda install swig=4.2.0 -y - -# === install picker -cd $BBDIR/thirdparty/picker -make init - -cd $BBDIR/thirdparty/picker -make -j$(nproc) ARGS="-DCMAKE_INSTALL_PREFIX=$PREFIX" -sudo -E make install - -replace_content ${BBDIR}/env.sh picker-install "\ -export PATH=$PREFIX/bin:\$PATH" diff --git a/scripts/install-workflow.sh b/scripts/install-workflow.sh deleted file mode 100755 index 0b64e17e..00000000 --- a/scripts/install-workflow.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/bash - -# exit script if any command fails -set -e -set -o pipefail - -BBDIR=$(git rev-parse --show-toplevel) - -source ${BBDIR}/scripts/utils.sh - -cd ${BBDIR} -replace_content ${BBDIR}/env.sh install-workflow "export PATH=${BBDIR}/workflow:\$PATH" -source ${BBDIR}/env.sh - -# lower node veersion is not supported for motia -conda install -c conda-forge nodejs=20 -y -# conda install -c conda-forge redis -y -pip install python-dotenv -pip install httpx - -cd ${BBDIR}/workflow -ln -s ${CONDA_PREFIX} ./python_modules || true - -cd ${BBDIR}/workflow -# if package.json does not exist, create and install motia -# if [ ! -f package.json ]; then - # install system dependencies for compiling Redis (redis-memory-server requires) -# if command -v apt-get &> /dev/null; then -# sudo apt-get update -qq -# sudo apt-get install -y libsystemd-dev build-essential || true -# fi -# npm init -y -# npm install motia@0.13.0-beta.161 -# fi -export USE_SYSTEMD=no -npm init -y -npm install motia@0.13.0-beta.161 -npx motia create -t python - -cd ${BBDIR}/workflow/steps && rm *.{py,json} || true -cd ${BBDIR}/workflow/steps && rm -r src/ || true -cd ${BBDIR}/workflow/steps && rm -r petstore/ || true -cd ${BBDIR}/workflow && rm -r src/ || true -cd ${BBDIR}/workflow && rm -r tutorial/ || true -cd ${BBDIR}/workflow && rm *.{md,tsx,rdb} || true - -# install MCP -pip install mcp -pip install redis -pip install httpx_sse diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index c30276a6..9b7dcba6 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -6,26 +6,22 @@ set -o pipefail BBDIR=$(git rev-parse --show-toplevel) -source ${BBDIR}/scripts/utils.sh - usage() { echo "Usage: ${0} [OPTIONS] " echo "" echo "Helper script to fully initialize repository that wraps other scripts." echo "By default it initializes/installs things in the following order:" - echo " 1. Compiler (buddy-mlir) pre-compile sources" - echo " 2. bb-tests (workloads) pre-compile sources" - echo " 3. Install document management system" - echo " 4. Install workflow management system" - echo " 5. Install pre-commit hooks" + echo " 1. bbdev install" + echo " 2. Compiler installation" + echo " 3. RTL pre-compile sources" + echo " 4. workloads pre-compile sources" + echo " 5. pre-commit hooks installation" echo "" echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" echo "" echo "Options" echo " --help -h : Display this message" - echo " --verbose -v : Verbose printout" echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')." - exit "$1" } @@ -93,18 +89,20 @@ if [ "${INSTALL_IN_NIX}" = "0" ]; then fi if run_step "1"; then - begin_step "1" "riscv-tools setup" - cd ${BBDIR}/thirdparty/libgloss - mkdir -p build && cd build - CC=riscv64-unknown-elf-gcc ../configure \ - --prefix=${RISCV}/lib \ - --host=riscv64-unknown-elf - make - make install + begin_step "1" "bbdev install" + + echo "Installing bbdev node dependencies..." + cd ${BBDIR}/bbdev/api + pnpm install --frozen-lockfile 2>/dev/null || pnpm install + + # Setup python_modules for Motia + # Python deps are managed by Nix (overlay.nix), just need the venv structure + echo "Setting up bbdev Python environment..." + python3 -m venv --without-pip --system-site-packages "${BBDIR}/bbdev/api/python_modules" fi if run_step "2"; then - begin_step "2" "Compiler (buddy-mlir) pre-compile sources" + begin_step "2" "Compiler installation" cd ${BBDIR}/compiler git submodule update --init llvm @@ -133,48 +131,17 @@ if run_step "2"; then fi if run_step "3"; then - begin_step "3" "Install bebop" - # ${BBDIR}/scripts/install-bebop.sh - echo "bebop is not installed" + begin_step "3" "arch pre-compile sources" + bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' fi if run_step "4"; then - begin_step "4" "bb-tests (workloads) pre-compile sources" - cd ${BBDIR}/bb-tests - mkdir -p build && cd build - cmake -G Ninja .. - ninja + begin_step "4" "bb-tests pre-compile sources" + bbdev workload --build fi if run_step "5"; then - begin_step "5" "Install requirements for sardine" - npm install --prefix ${BBDIR}/bb-tests/sardine allure-commandline -fi - - -if run_step "6"; then - begin_step "6" "Install document management system" - mdbook-mermaid install ${BBDIR}/docs/bb-note/ -fi - -if run_step "7"; then - begin_step "7" "Init workflow management system" - cd ${BBDIR}/workflow - export USE_SYSTEMD=no - npm init -y - npm install motia@0.13.0-beta.161 - npx motia create -t python - - cd ${BBDIR}/workflow/steps && rm *.{py,json} || true - cd ${BBDIR}/workflow/steps && rm -r src/ || true - cd ${BBDIR}/workflow/steps && rm -r petstore/ || true - cd ${BBDIR}/workflow && rm -r src/ || true - cd ${BBDIR}/workflow && rm -r tutorial/ || true - cd ${BBDIR}/workflow && rm *.{md,tsx,rdb} || true -fi - -if run_step "8"; then - begin_step "8" "Install pre-commit hooks" + begin_step "5" "pre-commit hooks installation" pre-commit install fi diff --git a/scripts/nix/build-env-bbdev.nix b/scripts/nix/build-env-bbdev.nix index bf470b70..ee47f422 100644 --- a/scripts/nix/build-env-bbdev.nix +++ b/scripts/nix/build-env-bbdev.nix @@ -1,15 +1,12 @@ { pkgs }: { - # Node.js environment - nodejs = pkgs.nodejs_20; - npm = pkgs.nodejs_20; + # Node.js environment (for bbdev Motia backend) + nodejs = pkgs.nodejs_22; + pnpm = pkgs.nodePackages.pnpm; # Build tools (for compiling native modules) gcc = pkgs.gcc; gnumake = pkgs.gnumake; pkg-config = pkgs.pkg-config; - - # System dependencies - systemd = pkgs.systemd; } diff --git a/scripts/nix/build-env-bebop.nix b/scripts/nix/build-env-bebop.nix index 3f0b2c92..2bcf3b8d 100644 --- a/scripts/nix/build-env-bebop.nix +++ b/scripts/nix/build-env-bebop.nix @@ -1,15 +1,9 @@ -{ pkgs, bebopPkgs ? {} }: +{ pkgs }: { - # Rust toolchain + # Rust toolchain (for building bebop) rustc = pkgs.rustc; cargo = pkgs.cargo; rustfmt = pkgs.rustfmt; clippy = pkgs.clippy; - - # Bebop packages (from bebop flake) - bebop = bebopPkgs.bebop or null; - bebopHost = bebopPkgs.host or null; - spike = bebopPkgs.spike or null; - gem5 = bebopPkgs.gem5 or null; } diff --git a/scripts/nix/build-env-clibs.nix b/scripts/nix/build-env-clibs.nix new file mode 100644 index 00000000..fa452534 --- /dev/null +++ b/scripts/nix/build-env-clibs.nix @@ -0,0 +1,10 @@ +{ pkgs }: + +{ + # C libraries needed by Verilator build + zlib-dev = pkgs.zlib.dev; + zlib = pkgs.zlib; + # C libraries needed by bdb debugger + readline-dev = pkgs.readline.dev; + readline = pkgs.readline; +} diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index f351449e..285171ed 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -1,6 +1,14 @@ { pkgs }: { - verilator = pkgs.verilator; - + # Pin to Verilator 5.022 2024-02-24 (nixpkgs-unstable ships 5.044) + verilator = pkgs.verilator.overrideAttrs (old: { + version = "5.022"; + src = pkgs.fetchurl { + url = "https://github.com/verilator/verilator/archive/refs/tags/v5.022.tar.gz"; + hash = "sha256-PC9TOPS2zn4vR6FCQBrN0Yy/TF2gYJJhjW0DbAr+8S0="; + }; + sourceRoot = "verilator-5.022"; + doCheck = false; + }); } diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 4d3edebc..93f4af3f 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -1,12 +1,11 @@ -{ bebopPkgs }: - final: prev: { - riscv = final.callPackage ./build-env-riscv.nix { }; - tools = final.callPackage ./build-env-tools.nix { }; - bebop = final.callPackage ./build-env-bebop.nix { inherit bebopPkgs; }; bbdev = final.callPackage ./build-env-bbdev.nix { }; + bebop = final.callPackage ./build-env-bebop.nix { }; + clibs = final.callPackage ./build-env-clibs.nix { }; + doc = final.callPackage ./build-env-doc.nix { }; python = final.callPackage ./build-env-python.nix { }; + riscv = final.callPackage ./build-env-riscv.nix { }; scala = final.callPackage ./build-env-scala.nix { }; - doc = final.callPackage ./build-env-doc.nix { }; + tools = final.callPackage ./build-env-tools.nix { }; } diff --git a/scripts/replace-content.py b/scripts/replace-content.py deleted file mode 100755 index e55bc993..00000000 --- a/scripts/replace-content.py +++ /dev/null @@ -1,72 +0,0 @@ -#!/usr/bin/env python3 - -# Replace text in a file given a key identifying a block to replace. -# If the file doesn't exist, create it. -# -# args -# $1 - file to replace text in -# $2 - key used to find block of text to replace -# $3 - text to fill in block that is replaced -# $4 - position to add if block not found: "head" or "tail" (default: "tail") - -import re -import sys - - -def CY_INITIALIZE_RE_BLOCK(k): - return ( - r"^# >>> " + f"{k}" + r" initialize >>>(?:\n|\r\n)" - r"([\s\S]*?)" - r"# <<< " + f"{k}" + r" initialize <<<(?:\n|\r\n)?" - ) - - -def CY_INITIALIZE_START_TOKEN(k): - return "# >>> " + f"{k}" + " initialize >>>" - - -def CY_INITIALIZE_END_TOKEN(k): - return "# <<< " + f"{k}" + " initialize <<<" - - -# ------------------------------ - -try: - with open(sys.argv[1]) as fh: - fh_content = fh.read() -except FileNotFoundError: - fh_content = "" -except Exception: - raise - -initialize_comment_key = sys.argv[2] -inner_contents = ( - CY_INITIALIZE_START_TOKEN(initialize_comment_key) - + "\n" - + sys.argv[3] - + "\n" - + CY_INITIALIZE_END_TOKEN(initialize_comment_key) - + "\n" -) - -# ------------------------------ - -replace_str = "__CY_REPLACE_ME_123__" -fh_content = re.sub( - CY_INITIALIZE_RE_BLOCK(initialize_comment_key), - replace_str, - fh_content, - flags=re.MULTILINE, -) -# TODO: maybe remove all but last of replace_str, if there's more than one occurrence -fh_content = fh_content.replace(replace_str, inner_contents) - -if CY_INITIALIZE_START_TOKEN(initialize_comment_key) not in fh_content: - position = sys.argv[4] if len(sys.argv) > 4 else "tail" - if position == "head": - fh_content = "%s\n%s" % (inner_contents, fh_content) - else: - fh_content += "\n%s\n" % inner_contents - -with open(sys.argv[1], "w") as fh: - fh.write(fh_content) diff --git a/scripts/utils.sh b/scripts/utils.sh deleted file mode 100644 index 522675cb..00000000 --- a/scripts/utils.sh +++ /dev/null @@ -1,19 +0,0 @@ -#!/bin/bash - - -####################################### -# Wrapper around replace-content.py. -# For a file ($1), write out text ($3) into it -# replacing any area designated by $2. -####################################### -function replace_content -{ - # If BASH_SOURCE is undefined, we may be running under zsh, in that case - # provide a zsh-compatible alternative - DIR="$(dirname "$(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}")")" - file="$1" - shift - key="$1" - shift - $DIR/replace-content.py "$file" "$key" "$@" -} diff --git a/sourceme.sh b/sourceme.sh new file mode 100644 index 00000000..5ad7ccef --- /dev/null +++ b/sourceme.sh @@ -0,0 +1,44 @@ +#!/usr/bin/env bash +# Source this file to add result/bin to PATH (requires 'nix build' first). +# This file is used to source the environment variables when you enter the +# buckyball environment ('nix develop' or just get environment variables). + +BBDIR=$(dirname "$(readlink -f "${BASH_SOURCE[0]}")") +RESULT_PATH="${BBDIR}/result" + +if [ ! -d "$RESULT_PATH" ]; then + echo "Warning: result not found at $RESULT_PATH. Run 'nix build' first." >&2 + return 1 2>/dev/null || exit 1 +fi + +#===----------------------------------------------------------------------------=== +# Source each submodule's ShellHooks +#===----------------------------------------------------------------------------=== +# source "${BBDIR}/bbdev/nix/init.sh" + +#===----------------------------------------------------------------------------=== +# Source Environment Variables +#===----------------------------------------------------------------------------=== +export BUDDY_MLIR_BUILD_DIR="${BBDIR}/compiler/build" +export LLVM_MLIR_BUILD_DIR="${BBDIR}/compiler/llvm/build" +export PYTHONPATH="${BBDIR}/compiler/llvm/build/tools/mlir/python_packages/mlir_core:${BBDIR}/compiler/build/python_packages:$PYTHONPATH" +export RISCV="${BBDIR}/result" +export PATH="${BBDIR}/thirdparty/libgloss/install/lib:$PATH" + +#===----------------------------------------------------------------------------=== +# Export each submodule's PATH +#===----------------------------------------------------------------------------=== +export PATH="${RESULT_PATH}/riscv64-unknown-elf/lib:${PATH}" +export PATH="${RESULT_PATH}/bin:${PATH}" + +# bebop / spike / gem5 (local builds) +export PATH="${BBDIR}/bebop/bebop/target/release:${PATH}" +export PATH="${BBDIR}/bebop/host/spike/riscv-isa-sim/install/bin:${PATH}" +export PATH="${BBDIR}/bebop/host/gem5/gem5/build/RISCV:${PATH}" + +# bbdev CLI and Python utils +export PATH="${BBDIR}/bbdev:${PATH}" +export PYTHONPATH="${BBDIR}/bbdev/api:${PYTHONPATH}" + +# sardine +export PYTHONPATH="${BBDIR}/lib/python3.13/site-packages:${PYTHONPATH}" diff --git a/tools/palladium b/thirdparty/palladium similarity index 100% rename from tools/palladium rename to thirdparty/palladium diff --git a/thirdparty/picker b/thirdparty/picker deleted file mode 160000 index b3b96016..00000000 --- a/thirdparty/picker +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b3b960163cea9ddeeab3ec4852931021c1e1471d diff --git a/tools/mill/.gitignore b/tools/mill/.gitignore deleted file mode 100644 index 50519060..00000000 --- a/tools/mill/.gitignore +++ /dev/null @@ -1 +0,0 @@ -mill diff --git a/tools/mill/install-mill.sh b/tools/mill/install-mill.sh deleted file mode 100755 index 0838e989..00000000 --- a/tools/mill/install-mill.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/bash - -set -e - -BBDIR=$(git rev-parse --show-toplevel) -MILL_DIR=$BBDIR/tools/mill - -# Install Mill -curl -L https://raw.githubusercontent.com/lefou/millw/0.4.11/millw > $MILL_DIR/mill && chmod +x $MILL_DIR/mill - -# Add Mill to PATH -source $BBDIR/scripts/utils.sh - -replace_content ${BBDIR}/env.sh "install-mill.sh" "export PATH=${BBDIR}/tools/mill:\$PATH" -source ${BBDIR}/env.sh -# export PATH=${BBDIR}/tools/mill:\$PATH -# echo "#mill path" >> ~/.${SHELL##*/}rc -# echo "export PATH=\"${BBDIR}/tools/mill:\$PATH\"" >> ~/.${SHELL##*/}rc - -# Verify installation -# mill --version diff --git a/workflow/.gitignore b/workflow/.gitignore deleted file mode 100644 index ddc6dc3c..00000000 --- a/workflow/.gitignore +++ /dev/null @@ -1,21 +0,0 @@ -node_modules -python_modules -.venv -venv -.motia -.mermaid -dist -*.pyc -*.json -motia-workbench.json -# package-lock.json -# package.json -types.d.ts -appendonlydir/ -dump.rdb -services/ -*.log -output/ - -.cursor/ -.claude/ diff --git a/workflow/bbdev b/workflow/bbdev deleted file mode 100755 index 832f58f2..00000000 --- a/workflow/bbdev +++ /dev/null @@ -1,533 +0,0 @@ -#! /usr/bin/env python3 - -import sys -import argparse -import subprocess -import os -import shlex -import json -import time -import requests - -from utils import find_available_port - -workflow_dir = os.path.dirname(os.path.abspath(__file__)) - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser( - prog="bbdev", - description="Development tool for buckyball project", - formatter_class=argparse.RawTextHelpFormatter, - ) - - # Global parameters - parser.add_argument( - "--port", type=int, default=None, help="Port for dev server (default: None)" - ) - parser.add_argument("--server", action="store_true", help="server mode") - - # Subcommand parser - subparsers = parser.add_subparsers(dest="command", help="Available commands") - - # ===== start subcommand ============================================================================== - start_parser = subparsers.add_parser("start", help="Start dev server") - - # ===== stop subcommand ============================================================================== - stop_parser = subparsers.add_parser("stop", help="Stop dev server") - stop_group = stop_parser.add_mutually_exclusive_group(required=False) - stop_group.add_argument("--all", action="store_true", help="Stop all servers") - - # ===== verilator subcommand ========================================================================= - verilator_parser = subparsers.add_parser("verilator", help="Verilator operations") - # Mutually exclusive option group for verilator - only one operation can be selected - verilator_group = verilator_parser.add_mutually_exclusive_group(required=True) - verilator_group.add_argument( - "--clean", action="store_true", help="Clean verilator build directory" - ) - verilator_group.add_argument( - "--verilog", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Generate verilog files from chisel. Args: "[--balltype ] [--job ] [--batch]"', - ) - verilator_group.add_argument( - "--build", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Build verilator simulation executable. Args: "[--job ]"', - ) - verilator_group.add_argument( - "--sim", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Run verilator simulation. Args: "--binary [--batch]"', - ) - verilator_group.add_argument( - "--run", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Integrated build+sim+run. Args: "--binary [--batch] [--job ]"', - ) - verilator_group.add_argument( - "--cosim", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Run verilator cosimulation. Args: "--binary [--batch]"', - ) - - # ===== vcs subcommand ========================================================================= - vcs_parser = subparsers.add_parser("vcs", help="vcs operations") - # Mutually exclusive option group for vcs - only one operation can be selected - vcs_group = vcs_parser.add_mutually_exclusive_group(required=True) - vcs_group.add_argument( - "--clean", action="store_true", help="Clean vcs build directory" - ) - vcs_group.add_argument( - "--verilog", action="store_true", help="Generate verilog files" - ) - vcs_group.add_argument( - "--build", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Build vcs simulation executable. Args: "[--job ]"', - ) - vcs_group.add_argument( - "--sim", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Run vcs simulation. Args: "--binary [--batch]"', - ) - vcs_group.add_argument( - "--run", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Integrated build+sim+run. Args: "--binary [--batch] [--job ]"', - ) - - # ===== sardine subcommand ========================================================================= - sardine_parser = subparsers.add_parser("sardine", help="sardine operations") - sardine_group = sardine_parser.add_mutually_exclusive_group(required=True) - sardine_group.add_argument( - "--run", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Run sardine. Args: "--workload "', - ) - - # ===== agent subcommand ========================================================================= - agent_parser = subparsers.add_parser("agent", help="agent operations") - agent_group = agent_parser.add_mutually_exclusive_group(required=True) - agent_group.add_argument( - "--chat", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Run agent. Args: "--message ", "--model "', - ) - - # ===== workload subcommand ========================================================================= - workload_parser = subparsers.add_parser("workload", help="workload operations") - workload_group = workload_parser.add_mutually_exclusive_group(required=True) - workload_group.add_argument( - "--build", - type=str, - nargs="?", - const="", - metavar="ARGS", - help="Build workload. ", - ) - - # ===== doc subcommand ========================================================================= - doc_parser = subparsers.add_parser("doc", help="doc operations") - doc_group = doc_parser.add_mutually_exclusive_group(required=True) - doc_group.add_argument("--deploy", action="store_true", help="Deploy doc. ") - - # ===== marshal subcommand ========================================================================= - marshal_parser = subparsers.add_parser("marshal", help="marshal operations") - marshal_group = marshal_parser.add_mutually_exclusive_group(required=True) - marshal_group.add_argument( - "--build", type=str, nargs="?", const="", metavar="ARGS", help="Build marshal. " - ) - marshal_group.add_argument( - "--launch", - type=str, - nargs="?", - const="", - metavar="ARGS", - help="Launch marshal. ", - ) - - # ===== firesim subcommand ========================================================================= - firesim_parser = subparsers.add_parser("firesim", help="firesim operations") - firesim_group = firesim_parser.add_mutually_exclusive_group(required=True) - firesim_group.add_argument( - "--buildbitstream", - type=str, - nargs="?", - const="", - metavar="ARGS", - help="Build bitstream. ", - ) - firesim_group.add_argument( - "--infrasetup", - type=str, - nargs="?", - const="", - metavar="ARGS", - help="Infrasetup. ", - ) - firesim_group.add_argument( - "--runworkload", - type=str, - nargs="?", - const="", - metavar="ARGS", - help="Run workload. ", - ) - - # ===== compiler subcommand ========================================================================= - compiler_parser = subparsers.add_parser("compiler", help="compiler operations") - compiler_group = compiler_parser.add_mutually_exclusive_group(required=True) - compiler_group.add_argument( - "--build", - type=str, - nargs="?", - const="", - metavar="ARGS", - help="Build compiler. ", - ) - - # ===== funcsim subcommand ========================================================================= - funcsim_parser = subparsers.add_parser("funcsim", help="funcsim operations") - funcsim_group = funcsim_parser.add_mutually_exclusive_group(required=True) - funcsim_group.add_argument( - "--build", type=str, nargs="?", const="", metavar="ARGS", help="Build funcsim. " - ) - funcsim_group.add_argument( - "--sim", type=str, nargs="?", const="", metavar="ARGS", help="Sim funcsim. " - ) - - # ===== uvm subcommand ========================================================================= - uvm_parser = subparsers.add_parser("uvm", help="uvm operations") - uvm_group = uvm_parser.add_mutually_exclusive_group(required=True) - uvm_group.add_argument( - "--builddut", type=str, nargs="?", const="", metavar="ARGS", help="Build dut. " - ) - uvm_group.add_argument( - "--build", type=str, nargs="?", const="", metavar="ARGS", help="Build uvm. " - ) - - # ===== palladium subcommand =================================================================== - palladium_parser = subparsers.add_parser("palladium", help="palladium operations") - palladium_group = palladium_parser.add_mutually_exclusive_group(required=True) - palladium_group.add_argument( - "--verilog", - type=str, - nargs="?", - const="", - metavar="ARGS", - help='Generate verilog files from chisel. Args example: "[--config sims.palladium.BuckyballToyP2EConfig]"', - ) - - # Parse arguments, allowing unknown arguments (so --port can work in subcommands) - args, unknown = parser.parse_known_args(argv) - - # If --port and --server are in unknown arguments, handle them manually - while unknown: - found = False - for i in range(len(unknown)): - if unknown[i] == "--port": - try: - args.port = int(unknown[i + 1]) - unknown = unknown[i + 2 :] # Remove processed arguments - found = True - break - except (ValueError, IndexError): - break - if unknown[i] == "--server": - args.server = True - unknown = unknown[i + 1 :] # Remove processed arguments - found = True - break - if not found: - break - # If there are other unknown arguments, throw error - if unknown: - parser.error(f"unrecognized arguments: {' '.join(unknown)}") - - return args - - -def extract_command_info(args): - """Generic command info extractor, applicable to all commands""" - # Basic return structure - result = {"command": getattr(args, "command", None), "operation": None, "args": {}} - - # Dynamically extract operation type (iterate through all attributes of args) - for attr_name in dir(args): - # Skip built-in attributes and known non-operation attributes - if attr_name.startswith("_") or attr_name in ["command", "port"]: - continue - - attr_value = getattr(args, attr_name) - # Find attributes with value True or non-empty string (skip None and False) - if attr_value is not None and attr_value is not False: - result["operation"] = attr_name - if attr_value is True: - # Boolean operations, such as --clean, --verilog - result["args"] = {} - else: - # Operations with arguments, such as --sim "arg_string" - # Parse argument string - args_dict = {} - if attr_value: - try: - # use shlex to parse args - arg_tokens = shlex.split(attr_value) - i = 0 - while i < len(arg_tokens): - token = arg_tokens[i] - if token.startswith("--"): - # long option - option_name = token[2:] # remove -- - if i + 1 < len(arg_tokens) and not arg_tokens[ - i + 1 - ].startswith("-"): - # next token is value - args_dict[option_name] = arg_tokens[i + 1] - i += 2 - else: - # boolean flag - args_dict[option_name] = True - i += 1 - elif token.startswith("-") and len(token) == 2: - # short option - option_name = token[1:] # remove - - if i + 1 < len(arg_tokens) and not arg_tokens[ - i + 1 - ].startswith("-"): - # next token is value - args_dict[option_name] = arg_tokens[i + 1] - i += 2 - else: - # boolean flag - args_dict[option_name] = True - i += 1 - else: - # position argument, skip - i += 1 - except ValueError as e: - print(f"Error parsing arguments: {e}") - result["args"] = args_dict - break - - return result - - -if __name__ == "__main__": - args = parse_args(sys.argv[1:]) - cmd_info = extract_command_info(args) - - # print(f"Command: {cmd_info['command']}") - # print(f"Operation: {cmd_info['operation']}") - # print(f"Arguments: {cmd_info['args']}") - - # ================================================================================== - # Two modes: server mode and script mode - # - # server mode: Manually start/stop server, can visualize and access workflows through browser - # script mode: Automatically assign port, start service when task begins, stop service when task ends - # ================================================================================== - if args.server: - if cmd_info["command"] == "start": - print(f"Starting dev server on port {args.port}") - subprocess.run( - ["npx", "motia", "dev", "--port", str(args.port)], - cwd=workflow_dir, - check=True, - ) - - elif cmd_info["command"] == "stop": - if cmd_info["operation"] == "all": - print("Stopping all servers") - subprocess.run( - "kill -9 $(ps aux | grep '[m]otia' | awk '{print $2}')", - shell=True, - check=False, - text=True, - ) - else: - print(f"Stopping server on port {args.port}") - subprocess.run( - f"kill -TERM $(lsof -t -i :{args.port})", - shell=True, - check=False, - text=True, - ) - - elif cmd_info["command"] in [ - "verilator", - "vcs", - "sardine", - "agent", - "workload", - "doc", - "marshal", - "firesim", - "compiler", - "funcsim", - "uvm", - "palladium", - ]: - api_path = f"/{cmd_info['command']}/{cmd_info['operation']}" - json_data = json.dumps(cmd_info["args"]) - subprocess.run( - [ - "curl", - "-X", - "POST", - f"http://localhost:{args.port}{api_path}", - "-H", - "Content-Type: application/json", - "-d", - json_data, - ], - cwd=workflow_dir, - check=True, - ) - else: - print(f"Unknown command: {cmd_info['command']}") - print( - "Available commands: start, stop, verilator, vcs, sardine, agent, \ - workload, doc, marshal, firesim, compiler, funcsim, uvm" - ) - sys.exit(1) - else: # script mode - if cmd_info["command"] == "start": - print(" 'start' do nothing in script mode") - elif cmd_info["command"] == "stop": - print(" 'stop' do nothing in script mode") - elif cmd_info["command"] in [ - "verilator", - "vcs", - "sardine", - "agent", - "workload", - "doc", - "marshal", - "firesim", - "compiler", - "funcsim", - "uvm", - "palladium", - ]: - # 1. Start service in background ================================ - # If port is specified, use the specified port; otherwise, automatically assign port - if args.port: - available_port = args.port - else: - available_port = find_available_port(start_port=5100, end_port=5500) - print(f"Starting server on port {available_port}...") - proc = subprocess.Popen( - ["npx", "motia", "dev", "--port", str(available_port)], cwd=workflow_dir - ) - - # Wait for service to start - max_retries = 30 - for i in range(max_retries): - try: - # Disable proxy, connect directly to localhost - # response = requests.get(f"http://localhost:{available_port}", timeout=1) - response = requests.get( - f"http://localhost:{available_port}", - timeout=1, - proxies={"http": None, "https": None, "all": None}, - ) - if response.status_code == 200: - print(f"Server is ready on port {available_port}") - break - except requests.exceptions.RequestException: - pass - time.sleep(3) - else: - print("Server failed to start within 30 seconds") - subprocess.run( - f"kill -TERM $(lsof -t -i :{available_port})", - shell=True, - check=False, - text=True, - ) - proc.terminate() - proc.wait() - sys.exit(1) - - # 2. Execute API call ================================ - api_path = f"/{cmd_info['command']}/{cmd_info['operation']}" - json_data = json.dumps(cmd_info["args"]) - print(f"Executing {cmd_info['command']} {cmd_info['operation']}...") - # Disable proxy, connect directly to localhost - result = subprocess.run( - [ - "curl", - "-sS", - "--noproxy", - "localhost", - "-X", - "POST", - f"http://localhost:{available_port}{api_path}", - "-H", - "Content-Type: application/json", - "-d", - json_data, - ], - cwd=workflow_dir, - capture_output=True, - text=True, - ) - - # 3. Shutdown service ================================ - # Give observability plugin time to finish async operations (e.g., Redis writes) - time.sleep(1) - proc.terminate() - proc.wait() - print( - f"\nTask completed. Command running on http://localhost:{available_port} is finished" - ) - - # Check the success field returned by API - try: - response = json.loads(result.stdout) - if not response.get("success", False): - print("Error: Task failed") - sys.exit(1) - except Exception: - print("Error: Invalid API response") - sys.exit(1) - - else: - print(f"Unknown command: {cmd_info['command']}") - print( - "Available commands: start, stop, verilator, vcs, sardine, agent, \ - workload, doc, marshal, firesim, compiler, funcsim, uvm" - ) - sys.exit(1) diff --git a/workflow/mcp-server/README.md b/workflow/mcp-server/README.md deleted file mode 100644 index 4629d8d1..00000000 --- a/workflow/mcp-server/README.md +++ /dev/null @@ -1,35 +0,0 @@ -# Buckyball MCP Server - -将 bbdev 工具封装为 MCP 服务，可以在 Claude/Cursor 中直接使用。 - -## 安装 - -```bash -pip install mcp -``` - -## 配置 - -Cursor - -在 MCP 配置中添加： - -```json -{ - "mcpServers": { - "bbdev": { - "command": "bash", - "args": ["-c", "cd /path/to/your/buckyball && source env.sh && python /path/to/your/buckyball/workflow/mcp-server/server.py"] - } - } -} -``` - -## 使用 - -配置后重启客户端，就可以自然语言调用 bbdev 所有功能了。 - -示例： -- "用 verilator 运行 gelu_test" -- "清理构建目录" -- "运行 sardine 测试" diff --git a/workflow/mcp-server/server.py b/workflow/mcp-server/server.py deleted file mode 100644 index 8041a3de..00000000 --- a/workflow/mcp-server/server.py +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env python3 -"""Buckyball Development Tools MCP Server""" - -import asyncio -import sys -from pathlib import Path - -# Add parent directory to path -workflow_dir = Path(__file__).parent.parent -sys.path.insert(0, str(workflow_dir)) - -from mcp.server import Server -from mcp.server.stdio import stdio_server -from mcp.types import Tool, TextContent - -from tools import get_all_tools, handle_tool_call - -# Create server -server = Server("bbdev-mcp") - - -@server.list_tools() -async def handle_list_tools() -> list[Tool]: - """List all available tools.""" - return get_all_tools() - - -@server.call_tool() -async def handle_call_tool(name: str, arguments: dict) -> list[TextContent]: - """Execute tool calls.""" - try: - result = await handle_tool_call(name, arguments) - return [TextContent(type="text", text=result)] - except Exception as e: - return [TextContent(type="text", text=f"Error: {str(e)}")] - - -async def main(): - """Main entry point.""" - async with stdio_server() as (read_stream, write_stream): - await server.run( - read_stream, write_stream, server.create_initialization_options() - ) - - -if __name__ == "__main__": - asyncio.run(main()) diff --git a/workflow/mcp-server/tools.py b/workflow/mcp-server/tools.py deleted file mode 100644 index a19da3f5..00000000 --- a/workflow/mcp-server/tools.py +++ /dev/null @@ -1,480 +0,0 @@ -""" -Tool definitions and handlers for Buckyball MCP server. -""" - -import asyncio -import json -import subprocess -import sys -from pathlib import Path -from typing import Any - -from mcp.types import Tool - -# Path to bbdev executable -BBDEV_PATH = Path(__file__).parent.parent / "bbdev" - - -async def execute_bbdev_command(command: list[str]) -> str: - """ - Execute a bbdev command and return the output. - - Args: - command: List of command arguments - - Returns: - Command output as string - """ - try: - # Run command in script mode (no --server flag) - process = await asyncio.create_subprocess_exec( - str(BBDEV_PATH), - *command, - stdout=asyncio.subprocess.PIPE, - stderr=asyncio.subprocess.PIPE, - cwd=BBDEV_PATH.parent, - ) - - stdout, stderr = await process.communicate() - - output = stdout.decode() if stdout else "" - error = stderr.decode() if stderr else "" - - if process.returncode != 0: - return f"Command failed with exit code {process.returncode}\n\nStdout:\n{output}\n\nStderr:\n{error}" - - return output if output else "Command completed successfully" - - except Exception as e: - return f"Error executing command: {str(e)}" - - -def get_all_tools() -> list[Tool]: - """Return all available tools.""" - return [ - # Verilator tools - Tool( - name="verilator_clean", - description="Clean verilator build directory", - inputSchema={ - "type": "object", - "properties": {}, - "required": [], - }, - ), - Tool( - name="verilator_verilog", - description="Generate verilog files from chisel", - inputSchema={ - "type": "object", - "properties": {}, - "required": [], - }, - ), - Tool( - name="verilator_build", - description="Build verilator simulation executable", - inputSchema={ - "type": "object", - "properties": { - "job": { - "type": "integer", - "description": "Number of parallel jobs for compilation (default: 16)", - "default": 16, - }, - }, - "required": [], - }, - ), - Tool( - name="verilator_sim", - description="Run verilator simulation with a binary", - inputSchema={ - "type": "object", - "properties": { - "binary": { - "type": "string", - "description": "Path or name of the binary to simulate", - }, - "batch": { - "type": "boolean", - "description": "Run in batch mode (no interactive output)", - "default": False, - }, - }, - "required": ["binary"], - }, - ), - Tool( - name="verilator_run", - description="Integrated build+sim+run for verilator (builds and runs simulation)", - inputSchema={ - "type": "object", - "properties": { - "binary": { - "type": "string", - "description": "Path or name of the binary to simulate", - }, - "batch": { - "type": "boolean", - "description": "Run in batch mode (no interactive output)", - "default": False, - }, - "job": { - "type": "integer", - "description": "Number of parallel jobs for compilation (default: 16)", - "default": 16, - }, - }, - "required": ["binary"], - }, - ), - # VCS tools - Tool( - name="vcs_clean", - description="Clean VCS build directory", - inputSchema={ - "type": "object", - "properties": {}, - "required": [], - }, - ), - Tool( - name="vcs_verilog", - description="Generate verilog files for VCS", - inputSchema={ - "type": "object", - "properties": {}, - "required": [], - }, - ), - Tool( - name="vcs_build", - description="Build VCS simulation executable", - inputSchema={ - "type": "object", - "properties": { - "job": { - "type": "integer", - "description": "Number of parallel jobs for compilation", - "default": 16, - }, - }, - "required": [], - }, - ), - Tool( - name="vcs_sim", - description="Run VCS simulation with a binary", - inputSchema={ - "type": "object", - "properties": { - "binary": { - "type": "string", - "description": "Path or name of the binary to simulate", - }, - "batch": { - "type": "boolean", - "description": "Run in batch mode", - "default": False, - }, - }, - "required": ["binary"], - }, - ), - Tool( - name="vcs_run", - description="Integrated build+sim+run for VCS", - inputSchema={ - "type": "object", - "properties": { - "binary": { - "type": "string", - "description": "Path or name of the binary to simulate", - }, - "batch": { - "type": "boolean", - "description": "Run in batch mode", - "default": False, - }, - "job": { - "type": "integer", - "description": "Number of parallel jobs", - "default": 16, - }, - }, - "required": ["binary"], - }, - ), - # Sardine tools - Tool( - name="sardine_run", - description="Run sardine test framework with a workload", - inputSchema={ - "type": "object", - "properties": { - "workload": { - "type": "string", - "description": "Path or name of the workload to run", - }, - }, - "required": ["workload"], - }, - ), - # Agent tools - Tool( - name="agent_chat", - description="Chat with the Buckyball development agent", - inputSchema={ - "type": "object", - "properties": { - "message": { - "type": "string", - "description": "Message to send to the agent", - }, - "model": { - "type": "string", - "description": "Model to use for the agent", - "default": "gpt-4", - }, - }, - "required": ["message"], - }, - ), - # Workload tools - Tool( - name="workload_build", - description="Build a workload for testing", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments for workload build", - "default": "", - }, - }, - "required": [], - }, - ), - # Documentation tools - Tool( - name="doc_deploy", - description="Deploy documentation", - inputSchema={ - "type": "object", - "properties": {}, - "required": [], - }, - ), - # Marshal tools - Tool( - name="marshal_build", - description="Build marshal", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments for marshal build", - "default": "", - }, - }, - "required": [], - }, - ), - Tool( - name="marshal_launch", - description="Launch marshal", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments for marshal launch", - "default": "", - }, - }, - "required": [], - }, - ), - # FireSim tools - Tool( - name="firesim_buildbitstream", - description="Build FireSim bitstream", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - Tool( - name="firesim_infrasetup", - description="Setup FireSim infrastructure", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - Tool( - name="firesim_runworkload", - description="Run workload on FireSim", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - # Compiler tools - Tool( - name="compiler_build", - description="Build compiler", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - # Funcsim tools - Tool( - name="funcsim_build", - description="Build functional simulation", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - Tool( - name="funcsim_sim", - description="Run functional simulation", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - # UVM tools - Tool( - name="uvm_builddut", - description="Build UVM DUT", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - Tool( - name="uvm_build", - description="Build UVM testbench", - inputSchema={ - "type": "object", - "properties": { - "args": { - "type": "string", - "description": "Additional arguments", - "default": "", - }, - }, - "required": [], - }, - ), - ] - - -async def handle_tool_call(name: str, arguments: dict) -> str: - """ - Handle a tool call by routing to the appropriate bbdev command. - - Args: - name: Tool name - arguments: Tool arguments - - Returns: - Tool execution result - """ - # Parse tool name to extract command and operation - parts = name.split("_", 1) - if len(parts) != 2: - return f"Invalid tool name format: {name}" - - command, operation = parts - - # Build bbdev command - cmd = [command, f"--{operation}"] - - # Build argument string based on the operation - if operation in ["build", "sim", "run"]: - arg_parts = [] - - # Handle common arguments - if "job" in arguments: - arg_parts.append(f"--jobs {arguments['job']}") - - if "binary" in arguments: - arg_parts.append(f"--binary {arguments['binary']}") - - if "batch" in arguments and arguments["batch"]: - arg_parts.append("--batch") - - if "workload" in arguments: - arg_parts.append(f"--workload {arguments['workload']}") - - if "message" in arguments: - arg_parts.append(f"--message '{arguments['message']}'") - - if "model" in arguments: - arg_parts.append(f"--model {arguments['model']}") - - if "args" in arguments and arguments["args"]: - arg_parts.append(arguments["args"]) - - # Join all arguments into a single string and pass as one argument - if arg_parts: - cmd.append(" ".join(arg_parts)) - - # Execute command - return await execute_bbdev_command(cmd) diff --git a/workflow/motia.config.ts b/workflow/motia.config.ts deleted file mode 100644 index c250ef7f..00000000 --- a/workflow/motia.config.ts +++ /dev/null @@ -1,9 +0,0 @@ -import { config } from '@motiadev/core' -const statesPlugin = require('@motiadev/plugin-states/plugin') -const endpointPlugin = require('@motiadev/plugin-endpoint/plugin') -const logsPlugin = require('@motiadev/plugin-logs/plugin') -const observabilityPlugin = require('@motiadev/plugin-observability/plugin') - -export default config({ - plugins: [observabilityPlugin, statesPlugin, endpointPlugin, logsPlugin], -}) diff --git a/workflow/package-lock.json b/workflow/package-lock.json deleted file mode 100644 index 6e6666bc..00000000 --- a/workflow/package-lock.json +++ /dev/null @@ -1,9627 +0,0 @@ -{ - "name": "workflow", - "lockfileVersion": 3, - "requires": true, - "packages": { - "": { - "name": "workflow", - "hasInstallScript": true, - "dependencies": { - "@motiadev/core": "^0.13.0", - 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}, - "keywords": [ - "motia" - ], - "dependencies": { - "@motiadev/core": "^0.13.0", - "@motiadev/plugin-endpoint": "^0.13.0", - "@motiadev/plugin-logs": "^0.13.0", - "@motiadev/plugin-observability": "^0.13.0", - "@motiadev/plugin-states": "^0.13.0", - "motia": "^0.13.0", - "zod": "^4.1.12" - }, - "devDependencies": { - "@types/react": "^19.1.1", - "ts-node": "^10.9.2", - "typescript": "^5.7.3" - } -} diff --git a/workflow/prompts/doc/common/standards.md b/workflow/prompts/doc/common/standards.md deleted file mode 100644 index c36c3698..00000000 --- a/workflow/prompts/doc/common/standards.md +++ /dev/null @@ -1,28 +0,0 @@ -# 通用文档标准 - -## 语言和格式要求 -1. 所有描述性内容必须使用中文 -2. 技术术语、API名称、代码标识符等保持英文原文 -3. 严禁使用任何emoji、装饰性符号或花哨的Unicode字符 -4. 使用专业、客观的技术写作语调，避免口语化表达 -5. 严格使用标准Markdown语法 - -## 内容准确性要求 -1. 所有技术信息必须基于实际代码内容，不得编造或夸大 -2. 代码片段必须来自实际文件，不超过15行 -3. 功能描述必须准确反映代码实现，避免"高性能"、"先进"等无根据的形容词 -4. 接口和参数描述必须与实际代码一致 -5. 依赖关系必须基于实际的import和调用关系 -6. 请先读代码后写文档 - -## 文档结构要求 -1. 根据目录类型使用对应的文档结构 -2. 每个章节必须包含实质性内容，避免空泛描述 -3. 重点说明实际功能、使用方法和关键实现 -4. 避免添加"特点"、"优势"等营销性质的内容 - -## 代码分析要求 -1. 仔细分析目录中的实际文件内容 -2. 提取真实的模块关系、接口定义、配置参数 -3. 基于实际代码结构组织文档内容 -4. 引用的代码片段必须准确无误 diff --git a/workflow/prompts/doc/customext-doc.md b/workflow/prompts/doc/customext-doc.md deleted file mode 100644 index 35616dd8..00000000 --- a/workflow/prompts/doc/customext-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# 自定义扩展测试代码目录文档生成prompt - -你是一位硬件扩展和自定义指令专家文档生成助手。你的任务是为仓库中的bb-tests/customext目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其自定义硬件扩展、指令集扩展、加速器集成以及相关的测试验证方法。 - -请严格按照以下六个部分进行书写： - -一、扩展概述 (Extension Overview) -总结自定义扩展的主要功能和目的，包括扩展的类型和功能、目标应用场景和性能优化目标、与基础架构的集成方式和接口、扩展的技术实现方法。 - -二、架构设计 (Architecture Design) -分析扩展的架构设计和实现方式，包括硬件架构和模块组织、指令集定义和编码格式、数据路径和控制逻辑设计、与主处理器的接口和通信协议。 - -三、功能模块 (Functional Modules) -详细说明各个功能模块，包括指令定义、硬件实现、软件接口、集成测试等。对于每个模块，说明其功能描述、关键接口和参数定义、实现细节，并提供相关的代码示例（控制在15行以内）。 - -四、测试验证 (Testing and Verification) -说明测试验证的方法和流程，包括功能正确性测试的设计和执行、性能基准测试和评估方法、兼容性测试和回归测试、调试工具和验证环境。 - -五、使用指南 (Usage Guide) -提供使用和集成的指导，包括编译构建和依赖配置、运行环境的设置和要求、示例程序和使用案例、常见问题和故障排除。 - -六、开发扩展 (Development Extension) -指导如何开发新的扩展，包括扩展开发的流程和规范、代码结构和组织方式、测试用例的编写方法、文档和维护的方法。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/rtl-doc.md b/workflow/prompts/doc/rtl-doc.md deleted file mode 100644 index 4563463c..00000000 --- a/workflow/prompts/doc/rtl-doc.md +++ /dev/null @@ -1,38 +0,0 @@ -# RTL 代码目录文档生成prompt - -你是一位代码文档生成专家。你的任务是为仓库中的rtl目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其硬件逻辑设计、模块功能、接口定义以及RTL级别的实现细节等硬件相关方面。 - -请严格按照以下四个部分进行书写： -一、Overview -总结其主要目的，包括目录整体的功能、设计的硬件架构目标。目录在 @arch/src/main/scala 目录下的上下层所处位置，扮演的角色 - -二、代码结构 -分析目录结构，并列出所有文件和子目录。然后介绍每个文件之间的关系，包括模块间的层次结构、调用依赖、接口连接和数据流向。 - -三、模块详细说明 -对于每个文件或关键模块： -总结其主要目的和功能。 -解释关键组件（如端口定义、内部逻辑、状态机、组合/时序逻辑），并在相关处使用代码片段。 -描述输入、输出和边缘情况。 -注明任何依赖项、外部模块或使用的硬件描述语言特定特性（如Verilog构造）。 - -四、附加信息 -提供任何你关注到的注意事项 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 禁止自行添加超出我限定范围的内容 - -最后，整个输出必须严格按照提供的参考模板结构化。 -参考模板：@arch/src/main/scala/framework/builtin/memdomain/mem/README.md ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/sardine-doc.md b/workflow/prompts/doc/sardine-doc.md deleted file mode 100644 index 1171465a..00000000 --- a/workflow/prompts/doc/sardine-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# Sardine测试框架代码目录文档生成prompt - -你是一位测试框架和自动化测试专家文档生成助手。你的任务是为仓库中的bb-tests/sardine目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其测试框架架构、自动化测试流程、测试用例管理以及相关的测试工具和方法。 - -请严格按照以下六个部分进行书写： - -一、框架概述 (Framework Overview) -总结Sardine测试框架的主要功能和目的，包括测试框架的设计理念和架构、支持的测试类型和测试场景、与其他测试工具和CI/CD系统的集成、框架的核心功能。 - -二、架构设计 (Architecture Design) -分析测试框架的架构设计，包括测试框架的整体架构和组件关系、测试执行引擎和调度机制、测试数据管理和结果收集、插件系统和扩展机制。 - -三、核心组件 (Core Components) -详细说明框架的核心组件，包括测试执行器、结果分析器、配置管理、报告生成等。对于每个组件，说明其功能描述、关键接口和API、实现细节，并提供相关的代码示例（控制在15行以内）。 - -四、测试用例管理 (Test Case Management) -说明测试用例的组织和管理，包括测试用例的分类和组织结构、测试数据的准备和管理方法、测试用例的编写规范、测试用例的维护和版本控制。 - -五、使用指南 (Usage Guide) -提供框架使用的详细指导，包括环境配置和依赖安装、测试执行的命令和参数、配置文件的编写和定制、测试结果的查看和分析。 - -六、扩展开发 (Extension Development) -指导如何扩展和定制框架，包括添加新测试类型的方法、自定义测试插件的开发、集成外部工具和服务、框架的性能优化和调优。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/script-doc.md b/workflow/prompts/doc/script-doc.md deleted file mode 100644 index 1575093d..00000000 --- a/workflow/prompts/doc/script-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# 脚本工具代码目录文档生成prompt - -你是一位脚本开发和自动化工具专家文档生成助手。你的任务是为仓库中的scripts目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其脚本功能、自动化流程、工具使用方法以及相关的开发和部署工具。 - -请严格按照以下六个部分进行书写： - -一、脚本概述 (Script Overview) -总结脚本工具的主要功能和目的，包括脚本的主要功能分类、自动化流程的设计目标和应用场景、与项目开发流程的集成关系、脚本工具的核心功能。 - -二、脚本分类 (Script Categories) -按功能对脚本进行分类说明，包括构建脚本、部署脚本、测试脚本、工具脚本、配置脚本等不同类型的脚本及其用途。 - -三、脚本详细说明 (Script Details) -对每个主要脚本进行详细说明，包括脚本的具体功能和解决的问题、输入参数和配置选项、执行流程和逻辑、输出结果和依赖要求，并提供关键代码片段（控制在15行以内）。 - -四、使用指南 (Usage Guide) -提供脚本使用的详细指导，包括环境准备和依赖安装、脚本执行的基本方法和参数、配置文件的编写和定制、批量执行和自动化集成。 - -五、开发和维护 (Development and Maintenance) -说明脚本的开发和维护方法，包括脚本开发的规范、代码结构和组织方式、测试和验证方法、版本控制和更新流程。 - -六、集成和扩展 (Integration and Extension) -指导如何集成和扩展脚本，包括与CI/CD系统的集成方法、添加新功能和脚本的步骤、自定义配置和参数化、性能优化和错误处理。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/sim-doc.md b/workflow/prompts/doc/sim-doc.md deleted file mode 100644 index 68fd1020..00000000 --- a/workflow/prompts/doc/sim-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# 仿真器代码目录文档生成prompt - -你是一位计算机架构仿真和系统建模专家文档生成助手。你的任务是为仓库中的sims目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其仿真器架构、仿真模型、性能建模以及相关的仿真工具和方法。 - -请严格按照以下六个部分进行书写： - -一、仿真器概述 (Simulator Overview) -总结仿真器的主要功能和目的，包括仿真器的类型和仿真精度级别、目标架构和支持的指令集、仿真器的性能和适用场景、与其他仿真工具和开发环境的关系。 - -二、架构设计 (Architecture Design) -分析仿真器的架构设计，包括仿真器的整体架构和模块组织、处理器模型和内存子系统建模、I/O设备和外设的仿真实现、仿真引擎和调度机制。 - -三、核心组件 (Core Components) -详细说明仿真器的核心组件，包括处理器模型、内存系统、I/O系统、调试接口等。对于每个组件，说明其功能描述和建模精度、关键接口和配置参数、实现细节，并提供相关的代码示例（控制在15行以内）。 - -四、使用指南 (Usage Guide) -提供仿真器使用的详细指导，包括编译构建和依赖配置、仿真执行的命令和参数、配置文件和仿真选项、程序加载和执行方法。 - -五、性能分析 (Performance Analysis) -说明性能分析和调优方法，包括性能统计和指标收集、仿真速度和精度的权衡、性能瓶颈分析和优化、与真实硬件的对比验证。 - -六、扩展开发 (Extension Development) -指导如何扩展和定制仿真器，包括添加新指令和功能的方法、自定义设备和外设的集成、仿真模型的修改和优化、调试工具和分析插件的开发。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/uvbb-doc.md b/workflow/prompts/doc/uvbb-doc.md deleted file mode 100644 index d1a88db0..00000000 --- a/workflow/prompts/doc/uvbb-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# UVBB测试代码目录文档生成prompt - -你是一位硬件验证和UVM测试专家文档生成助手。你的任务是为仓库中的bb-tests/uvbb目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其UVM验证环境、测试平台架构、验证组件以及相关的硬件验证方法。 - -请严格按照以下六个部分进行书写： - -一、验证环境概述 (Verification Environment Overview) -总结UVBB验证环境的主要功能和目的，包括UVM验证环境的设计目标和验证策略、被测设计(DUT)的特征和验证需求、验证环境的覆盖率目标和质量标准、与其他验证工具和流程的集成。 - -二、验证架构 (Verification Architecture) -分析UVM验证环境的架构设计，包括UVM testbench的整体架构和组件层次、Agent、Driver、Monitor、Scoreboard等组件的组织、验证环境的配置和参数化机制、测试序列和场景的管理架构。 - -三、验证组件 (Verification Components) -详细说明各个验证组件，包括UVM Agent、Driver、Monitor、Scoreboard、Sequence等。对于每个组件，说明其功能描述、关键接口和配置参数、实现细节，并提供相关的代码示例（控制在15行以内）。 - -四、测试场景 (Test Scenarios) -说明测试场景的设计和实现，包括功能测试场景的分类和覆盖、边界条件和异常情况的测试、性能和压力测试的设计、随机化测试和约束定义。 - -五、运行和调试 (Execution and Debug) -提供运行和调试的指导，包括仿真环境的配置和启动、测试执行的命令和参数、波形分析和调试方法、覆盖率收集和分析工具。 - -六、验证流程 (Verification Flow) -描述完整的验证流程，包括验证计划的制定和执行、回归测试和持续集成、覆盖率驱动的验证方法、验证结果的分析和报告。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/workflow-doc.md b/workflow/prompts/doc/workflow-doc.md deleted file mode 100644 index f06d5199..00000000 --- a/workflow/prompts/doc/workflow-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# 工作流代码目录文档生成prompt - -你是一位开发工作流和自动化流程专家文档生成助手。你的任务是为仓库中的workflow目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其工作流设计、自动化流程、开发工具以及相关的流程管理和协作方法。 - -请严格按照以下六个部分进行书写： - -一、工作流概述 (Workflow Overview) -总结工作流系统的主要功能和目的，包括工作流的设计理念和架构目标、支持的开发流程和自动化场景、与开发工具链和CI/CD系统的集成、工作流系统的核心功能。 - -二、架构设计 (Architecture Design) -分析工作流系统的架构设计，包括工作流引擎和执行框架、任务调度和依赖管理机制、配置管理和参数化系统、插件系统和扩展架构。 - -三、核心组件 (Core Components) -详细说明工作流的核心组件，包括流程定义、任务执行、状态管理、结果处理等。对于每个组件，说明其功能描述、关键接口和配置选项、实现细节，并提供相关的代码示例（控制在15行以内）。 - -四、工作流配置 (Workflow Configuration) -说明工作流的配置和定制方法，包括配置文件的结构和语法、参数定义和环境变量管理、条件执行和分支控制、错误处理和重试机制。 - -五、使用指南 (Usage Guide) -提供工作流使用的详细指导，包括环境搭建和依赖安装、工作流的启动和执行方法、监控和调试工具的使用、常见问题和故障排除。 - -六、开发和扩展 (Development and Extension) -指导如何开发和扩展工作流，包括自定义任务和插件的开发、工作流模板的创建和复用、与外部系统的集成方法、性能优化和最佳实践。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/doc/workloads-doc.md b/workflow/prompts/doc/workloads-doc.md deleted file mode 100644 index 8a90c65f..00000000 --- a/workflow/prompts/doc/workloads-doc.md +++ /dev/null @@ -1,41 +0,0 @@ -# 工作负载测试代码目录文档生成prompt - -你是一位测试工程和性能评估专家文档生成助手。你的任务是为仓库中的bb-tests/workloads目录下的代码创建一份全面的README文档。你这次的目标是目录 @[`目录相对路径`] ，你需要详细描述其测试工作负载、性能基准、测试用例以及相关的测试框架和评估方法。 - -请严格按照以下六个部分进行书写： - -一、工作负载概述 (Workload Overview) -总结工作负载的主要功能和目的，包括测试工作负载的类型、目标测试场景和应用领域、性能评估的关键指标、与系统其他测试组件的关系。 - -二、测试用例结构 (Test Case Structure) -分析测试用例的组织和结构，包括测试用例的分类和层次结构、输入数据集和参数配置、预期输出和验证标准、测试用例之间的依赖关系。 - -三、工作负载详细说明 (Workload Details) -对每个主要工作负载进行详细说明，包括功能描述、算法实现、性能特征、配置参数，并提供关键代码片段和实现细节（控制在15行以内）。 - -四、构建和运行 (Build and Execution) -提供构建和运行的详细指导，包括编译依赖和构建系统配置、编译命令和构建选项、运行方法和命令行参数、输出结果的解读和分析。 - -五、性能评估 (Performance Evaluation) -说明性能评估的方法和工具，包括性能指标的定义和测量方法、基准测试的执行流程、结果分析和性能调优建议、与其他实现或平台的对比方法。 - -六、扩展和定制 (Extension and Customization) -指导如何扩展和定制工作负载，包括添加新测试用例的方法、修改现有工作负载的步骤、集成新的性能指标、适配不同硬件平台的方法。 - -文档规范： -1. 确保文档清晰、简洁，并使用Markdown格式以提高可读性，包括标题、项目符号、代码块，以及必要时的表格或流程图。 -2. 禁止在文档中使用任何花哨的Emoji或其他装饰性符号。 -3. 所有技术信息必须基于实际代码内容，不得编造或夸大功能。 -4. 代码片段必须来自实际文件，并提供准确的中文解释。 -5. 禁止自行添加超出我限定范围的内容。 - ---- - -## 使用方法 -1. 替换上述prompt中的占位符为实际信息 -2. 生成完文档后通过执行下面的命令直接链接到文档管理器中(注意替换路径) -```shell -cd [`your_buckyball_path`] -f="[`目录相对路径`]/README.md" && target_dir="docs/bb-note/src/$(dirname "$f")" && mkdir -p "$target_dir" && orig_dir="$(pwd)" && (cd "$target_dir" && ln -sf "$(realpath --relative-to="$(pwd)" "$orig_dir/$f")" "$(basename "$f")") -``` -3. 最后把文件路径添加到 `docs/bb-note/src/SUMMARY.md` 即可 diff --git a/workflow/prompts/new-ball.md b/workflow/prompts/new-ball.md deleted file mode 100644 index 873dbcee..00000000 --- a/workflow/prompts/new-ball.md +++ /dev/null @@ -1,17 +0,0 @@ -# 使用这个promts生成并集成一个新ball - -你是一位AI定制化加速单元实现专家，你的任务是在该仓库实现并集成新的硬件加速单元。 - -使用Deepwiki获取`DangoSys/buckyball`, blink协议相关内容 -使用Deepwiki获取`DangoSys/buckyball`, 如何集成一个自定义的ball进去 - -查询完成后执行以下任务，对于仓库你有任何不懂的可以直接使用ask_question问Deepwiki -1. 请依据 [arch/src/main/scala/prototype/nagisa/layernorm] 目录下的spec.md，实现一个 [LAYERNORM] ball并集成进系统 -2. 实现对应的Ctest测试用例 -3. 使用bbdev verilator进行测试 -4. 测试通过后将该测试加入 sardine 列表 -5. 将对应设计的唯一 README.md, 使用相对路径软链接加入 bb-note - -规范： -1. 请尽量避免生成总结文档 -2. 除了集成必要以外，你不应该修改ball以外的代码 diff --git a/workflow/prompts/new-spec.md b/workflow/prompts/new-spec.md deleted file mode 100644 index 5d86bc2d..00000000 --- a/workflow/prompts/new-spec.md +++ /dev/null @@ -1,911 +0,0 @@ -# 使用这个promts生成一个新ball的spec - -你是一位AI定制化加速单元的Spec书写专家，你的任务是为新的硬件加速单元的设计书写spec。 - -请你参考下面的Spec的格式（实现方案不用参考） -``` -# GELU加速单元设计规范 - -## 1. 概述 (Overview) - -GELU (Gaussian Error Linear Unit) 加速单元是Buckyball框架中的专用计算加速器，用于高效执行GELU激活函数运算。GELU是现代深度学习模型（如Transformer、BERT、GPT等）中广泛使用的非线性激活函数。 - -### 1.1 基本参数 - -- **数据格式**: 输入为INT8，输出为INT32 -- **向量化处理**: 每次处理16个INT8元素（veclane=16） -- **流水线架构**: 多级流水线设计（ID, Load, Execute, Store） -- **计算方法**: 采用GELU近似算法（tanh公式） -- **存储接口**: 支持Scratchpad和Accumulator读写 - -### 1.2 数学定义 - -GELU激活函数的精确定义： - -``` -GELU(x) = x · Φ(x) -``` - -其中Φ(x)是标准正态分布的累积分布函数。 - -硬件实现采用tanh近似公式： - -``` -GELU(x) ≈ 0.5 · x · (1 + tanh(√(2/π) · (x + 0.044715 · x³))) -``` - -简化常数： -- √(2/π) ≈ 0.7978845608 -- 0.044715 - -## 2. 系统架构 (Block Diagram) - -### 2.1 顶层架构 - -``` -┌─────────────────────────────────────────────────────────────────┐ -│ GELU Accelerator │ -├─────────────────────────────────────────────────────────────────┤ -│ │ -│ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ │ -│ │ │ │ │ │ │ │ -│ │ Control │───▶│ Load Unit │───▶│ Execute │ │ -│ │ Unit (ID) │ │ │ │ Unit (EX) │ │ -│ │ │ │ │ │ │ │ -│ └──────┬───────┘ └──────┬───────┘ └──────┬───────┘ │ -│ │ │ │ │ -│ │ │ │ │ -│ │ ┌────▼────┐ ┌────▼────┐ │ -│ │ │ SRAM │ │ Store │ │ -│ │ │ Read │ │ Unit │ │ -│ │ │ Arbiter │ │ │ │ -│ │ └─────────┘ └────┬────┘ │ -│ │ │ │ -│ ┌──────▼────────────────────────────────┐ │ │ -│ │ Command Interface │ │ │ -│ │ (Ball Bus / RoCC Interface) │ │ │ -│ └───────────────────────────────────────┘ │ │ -│ │ │ -│ ┌──────────────────────────────────────┐ │ │ -│ │ Status Monitor │ │ │ -│ │ (ready/valid/idle/init/running) │ │ │ -│ └──────────────────────────────────────┘ │ │ -│ │ │ -└─────────────────────────────────────────────────┼───────────────┘ - │ - ┌─────▼─────┐ - │ Memory │ - │ System │ - └───────────┘ -``` - -### 2.2 流水线结构 - -``` -┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ -│ ID │───▶│ Load │───▶│ EX │───▶│ Store │ -│ Stage │ │ Stage │ │ Stage │ │ Stage │ -└────────┘ └────────┘ └────────┘ └────────┘ - │ │ │ │ - │ │ │ │ - Decode Load Data Compute GELU Write Back - Command from SRAM Approximation to ACC/SRAM -``` - -### 2.3 计算单元架构 - -``` -┌─────────────────────────────────────────────────────────┐ -│ GELU Compute Pipeline (EX Stage) │ -├─────────────────────────────────────────────────────────┤ -│ │ -│ Input x │ -│ │ │ -│ ├──────────┬──────────┬──────────┐ │ -│ │ │ │ │ │ -│ │ ┌──▼──┐ ┌──▼──┐ ┌──▼──┐ │ -│ │ │ x² │───▶│ x³ │───▶│ MUL │ (x³·0.044715)│ -│ │ └─────┘ └─────┘ └──┬──┘ │ -│ │ │ │ -│ │ ┌──────────────────────┘ │ -│ │ │ │ -│ │ ┌──▼──┐ │ -│ │ │ ADD │ (x + 0.044715·x³) │ -│ │ └──┬──┘ │ -│ │ │ │ -│ │ ┌──▼──┐ │ -│ │ │ MUL │ (0.7978845608 · ...) │ -│ │ └──┬──┘ │ -│ │ │ │ -│ │ ┌──▼──┐ │ -│ │ │TANH │ (lookup table / polynomial approx) │ -│ │ └──┬──┘ │ -│ │ │ │ -│ │ ┌──▼──┐ │ -│ │ │ADD+1│ (1 + tanh(...)) │ -│ │ └──┬──┘ │ -│ │ │ │ -│ └────┬─────┘ │ -│ │ │ -│ ┌──▼──┐ │ -│ │ MUL │ x · (...) │ -│ └──┬──┘ │ -│ │ │ -│ ┌──▼──┐ │ -│ │ MUL │ 0.5 · (...) │ -│ └──┬──┘ │ -│ │ │ -│ Output GELU(x) │ -└─────────────────────────────────────────────────────────┘ -``` - - -## 3. 接口描述 (Interface Description) - -GELU单元对外提供以下接口： -- **命令接口** (Command Interface): 接收GELU指令并返回完成响应 -- **Scratchpad接口** (SRAM Interface): 访问INT8数据的存储器 -- **Accumulator接口** (ACC Interface): 访问INT32数据的存储器 -- **状态监控接口** (Status Interface): 输出当前运行状态信息 -- **时钟和复位接口**: 提供时钟和复位信号 - -### 3.1 指令语义 (Instruction Semantics) - -一条GELU指令的完整语义如下： - -**指令含义**：对存储在Scratchpad或Accumulator中的向量执行GELU运算 - -**数据格式**： -- **Scratchpad模式** (`is_acc=0`)：INT8输入 → GELU → INT8输出 -- **Accumulator模式** (`is_acc=1`)：INT32输入 → GELU → INT32输出 -- **注意**：Scratchpad存储INT8，Accumulator存储INT32 - -**处理单位**： -- 每个向量 = 16个元素（veclane = 16） -- 每个SRAM地址存储1个INT8向量（16×8位 = 128位 = 16字节） -- 每个ACC地址存储1个INT32向量（16×32位 = 512位 = 64字节） - -**指令参数说明**： - -| 参数 | 含义 | 示例 | -|-----|------|------| -| `iter` | 要处理的向量个数 | iter=64 表示处理64个向量 | -| `op1_bank` | 输入数据所在的Bank号 | 0-3 | -| `op1_bank_addr` | 输入起始地址 | 0x100 | -| `wr_bank` | 输出数据写入的Bank号 | 0-3 | -| `wr_bank_addr` | 输出起始地址 | 0x200 | -| `is_acc` | 数据类型选择 | 0=SRAM(INT8)模式, 1=ACC(INT32)模式 | - -**模式1：is_acc=0（SRAM模式，INT8）** - -输入范围： -``` -起始地址：SRAM[op1_bank][op1_bank_addr] -结束地址：SRAM[op1_bank][op1_bank_addr + iter - 1] -每地址：16个INT8元素（128位） -总元素数：iter × 16 个INT8元素 -``` - -输出范围： -``` -起始地址：SRAM[wr_bank][wr_bank_addr] -结束地址：SRAM[wr_bank][wr_bank_addr + iter - 1] -每地址：16个INT8元素（128位） -总元素数：iter × 16 个INT8元素 -``` - -**模式2：is_acc=1（ACC模式，INT32）** - -输入范围： -``` -起始地址：ACC[op1_bank][op1_bank_addr] -结束地址：ACC[op1_bank][op1_bank_addr + iter - 1] -每地址：16个INT32元素（512位） -总元素数：iter × 16 个INT32元素 -``` - -输出范围： -``` -起始地址：ACC[wr_bank][wr_bank_addr] -结束地址：ACC[wr_bank][wr_bank_addr + iter - 1] -每地址：16个INT32元素（512位） -总元素数：iter × 16 个INT32元素 -``` - -**示例1**：SRAM模式，处理INT8数据 -``` -iter = 64 -op1_bank = 0, op1_bank_addr = 0x000 -wr_bank = 1, wr_bank_addr = 0x000 -is_acc = 0 - -输入：SRAM[0][0x000~0x03F] 的64个向量（1024个INT8元素） -输出：SRAM[1][0x000~0x03F] 的64个向量（1024个INT8元素） -``` - -**示例2**：ACC模式，处理INT32数据 -``` -iter = 64 -op1_bank = 0, op1_bank_addr = 0x000 -wr_bank = 1, wr_bank_addr = 0x000 -is_acc = 1 - -输入：ACC[0][0x000~0x03F] 的64个向量（1024个INT32元素） -输出：ACC[1][0x000~0x03F] 的64个向量（1024个INT32元素） -``` - -**示例3**：单个向量处理 -``` -iter = 1 -op1_bank = 0, op1_bank_addr = 0x100 -wr_bank = 0, wr_bank_addr = 0x200 -is_acc = 0 - -输入：SRAM[0][0x100] 的16个INT8元素 -输出：SRAM[0][0x200] 的16个INT8元素 -``` - -### 3.2 命令接口 (Command Interface) - -GELU单元通过Ball Domain标准接口与系统交互： - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `cmdReq.valid` | Input | 1 | 命令请求有效信号 | -| `cmdReq.ready` | Output | 1 | 命令请求就绪信号 | -| `cmdReq.bits.rob_id` | Input | 10 | ROB (Reorder Buffer) 标识符 | -| `cmdReq.bits.iter` | Input | 10 | 向量迭代次数 (支持1-1024) | -| `cmdReq.bits.op1_bank` | Input | 2 | 操作数Bank选择 | -| `cmdReq.bits.op1_bank_addr` | Input | 12 | 操作数Bank内地址 | -| `cmdReq.bits.wr_bank` | Input | 2 | 写回Bank选择 | -| `cmdReq.bits.wr_bank_addr` | Input | 12 | 写回Bank内地址 | -| `cmdReq.bits.is_acc` | Input | 1 | 目标存储类型 (0=SRAM, 1=ACC) | - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `cmdResp.valid` | Output | 1 | 完成响应有效信号 | -| `cmdResp.ready` | Input | 1 | 完成响应就绪信号 | -| `cmdResp.bits.rob_id` | Output | 10 | 完成指令的ROB ID | -| `cmdResp.bits.commit` | Output | 1 | 提交标志 | - -### 3.2 Scratchpad存储接口 (SRAM Interface) - -支持多Bank并行访问的SRAM接口，存储INT8数据。Bank数量由配置参数`sp_banks`决定（典型值4）。 - -**读接口** (每Bank): - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `sramRead[i].req.valid` | Output | 1 | 读请求有效信号 | -| `sramRead[i].req.ready` | Input | 1 | 读请求就绪信号 | -| `sramRead[i].req.bits.addr` | Output | log2(entries) | 读地址 | -| `sramRead[i].resp.valid` | Input | 1 | 读响应有效信号 | -| `sramRead[i].resp.bits.data` | Input | 128 | 读数据（16个INT8 = 128位）| - -**写接口** (每Bank): - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `sramWrite[i].valid` | Output | 1 | 写请求有效信号 | -| `sramWrite[i].ready` | Input | 1 | 写请求就绪信号 | -| `sramWrite[i].bits.addr` | Output | log2(entries) | 写地址 | -| `sramWrite[i].bits.data` | Output | 128 | 写数据（16个INT8 = 128位）| -| `sramWrite[i].bits.mask` | Output | 16 | 写掩码（按INT8元素）| - -### 3.3 Accumulator存储接口 (ACC Interface) - -Accumulator存储INT32数据。Bank数量由配置参数`acc_banks`决定（典型值2）。 - -**读接口** (每Bank): - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `accRead[i].req.valid` | Output | 1 | 读请求有效信号 | -| `accRead[i].req.ready` | Input | 1 | 读请求就绪信号 | -| `accRead[i].req.bits.addr` | Output | log2(acc_entries) | 读地址 | -| `accRead[i].resp.valid` | Input | 1 | 读响应有效信号 | -| `accRead[i].resp.bits.data` | Input | 512 | 读数据（16个INT32 = 512位）| - -**写接口** (每Bank): - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `accWrite[i].valid` | Output | 1 | 写请求有效信号 | -| `accWrite[i].ready` | Input | 1 | 写请求就绪信号 | -| `accWrite[i].bits.addr` | Output | log2(acc_entries) | 写地址 | -| `accWrite[i].bits.data` | Output | 512 | 写数据（16个INT32 = 512位）| -| `accWrite[i].bits.mask` | Output | 16 | 写掩码（按INT32元素）| - -### 3.4 状态监控接口 (Status Interface) - -GELU单元提供状态监控接口，用于外部观察当前运行状态： - -| 信号名称 | 方向 | 位宽 | 描述 | -|---------|------|------|------| -| `status.ready` | Output | 1 | 设备准备好接受新输入 | -| `status.valid` | Output | 1 | 设备有有效输出 | -| `status.idle` | Output | 1 | 空闲状态（无输入无输出）| -| `status.init` | Output | 1 | 初始化状态（有输入但无输出）| -| `status.running` | Output | 1 | 运行状态（已开始产生输出）| -| `status.complete` | Output | 1 | 完成信号（完全完成当前批次）| -| `status.iter` | Output | 32 | 已完成的批次迭代计数 | - -**状态转换关系**： - -``` -idle (ready=1, valid=0, idle=1) - ↓ [cmdReq.fire] -init (ready=0, valid=0, init=1) - ↓ [开始产生输出] -running (ready=0, valid=1, running=1) - ↓ [所有数据处理完成] -complete (complete=1) - ↓ [cmdResp.fire] -idle (iter += 1) -``` - -**典型实现**： - -```scala -// Status tracking registers -val iterCnt = RegInit(0.U(32.W)) -val hasInput = RegInit(false.B) -val hasOutput = RegInit(false.B) - -when(io.cmdReq.fire) { - hasInput := true.B -} -when(io.cmdResp.fire) { - hasOutput := false.B - hasInput := false.B - iterCnt := iterCnt + 1.U -} -when(io.cmdResp.valid && !hasOutput) { - hasOutput := true.B -} - -// Status signal assignments -io.status.ready := io.cmdReq.ready -io.status.valid := io.cmdResp.valid -io.status.idle := !hasInput && !hasOutput -io.status.init := hasInput && !hasOutput -io.status.running := hasOutput -io.status.complete := io.cmdResp.fire -io.status.iter := iterCnt -``` - -### 3.5 时钟和复位接口 - -| 信号名称 | 方向 | 描述 | -|---------|------|------| -| `clock` | Input | 全局时钟信号 | -| `reset` | Input | 全局同步复位信号 (高有效) | - - -## 4. 寄存器映射 (Register Map) - -### 4.1 内部控制寄存器 - -GELU单元不直接暴露APB寄存器接口，而是通过Ball Domain命令接口进行控制。内部状态寄存器如下： - -| 寄存器名称 | 位宽 | 复位值 | 描述 | -|-----------|------|--------|------| -| `state` | 3 | `idle` | 状态机状态: idle/load/exec/store/complete | -| `rob_id_reg` | 10 | 0 | 当前处理指令的ROB ID | -| `iter_reg` | 10 | 0 | 迭代次数寄存器 | -| `iter_cnt` | 10 | 0 | 迭代计数器 | -| `op1_bank_reg` | 2 | 0 | 操作数Bank寄存器 | -| `op1_addr_reg` | 12 | 0 | 操作数地址寄存器 | -| `wr_bank_reg` | 2 | 0 | 写回Bank寄存器 | -| `wr_addr_reg` | 12 | 0 | 写回地址寄存器 | -| `is_acc_reg` | 1 | 0 | 写回目标类型寄存器 | -| `load_cnt` | 4 | 0 | 加载计数器 (跟踪SRAM读延迟) | -| `exec_cnt` | 5 | 0 | 执行计数器 (跟踪流水线进度) | -| `iter_cnt` | 32 | 0 | 批次迭代计数器 (用于status.iter) | -| `has_input` | 1 | 0 | 输入状态标志 (用于status跟踪) | -| `has_output` | 1 | 0 | 输出状态标志 (用于status跟踪) | - -### 4.2 状态机编码 - -| 状态名称 | 编码 | 描述 | -|---------|------|------| -| `idle` | 3'b000 | 空闲状态，等待命令 | -| `load` | 3'b001 | 加载数据状态 | -| `exec` | 3'b010 | 执行计算状态 | -| `store` | 3'b011 | 写回结果状态 | -| `complete` | 3'b100 | 完成响应状态 | - - -## 5. 功能描述 (Functional Description) - -### 5.1 操作流程 - -#### 5.1.1 指令接收 (Idle → Load) - -1. **空闲等待**: 状态机处于`idle`状态，监听`cmdReq.valid`信号 -2. **指令解码**: 当`cmdReq.valid && cmdReq.ready`时，捕获指令参数： - ```scala - rob_id_reg := cmdReq.bits.rob_id - iter_reg := cmdReq.bits.iter - op1_bank_reg := cmdReq.bits.op1_bank - op1_addr_reg := cmdReq.bits.op1_bank_addr - wr_bank_reg := cmdReq.bits.wr_bank - wr_addr_reg := cmdReq.bits.wr_bank_addr - is_acc_reg := cmdReq.bits.is_acc - ``` -3. **状态转移**: 转移到`load`状态 - -#### 5.1.2 数据加载 (Load) - -1. **发起读请求**: 向SRAM发起读请求 - ```scala - sramRead(op1_bank_reg).req.valid := true.B - sramRead(op1_bank_reg).req.bits.addr := op1_addr_reg + iter_cnt - ``` -2. **数据接收**: 等待`sramRead.resp.valid`，将数据存入缓冲寄存器 -3. **迭代控制**: 每次加载完成后，`iter_cnt`递增 -4. **状态转移**: 当所有数据加载完成时，转移到`exec`状态 - -#### 5.1.3 GELU计算 (Execute) - -执行流水线化的GELU近似计算，每个向量元素并行处理： - -**步骤1**: 计算x³ -```scala -val x2 = x * x -val x3 = x2 * x -``` - -**步骤2**: 计算内层多项式 -```scala -val poly = x + (x3 * 0.044715.F(32.BP)) -``` - -**步骤3**: 缩放 -```scala -val scaled = poly * 0.7978845608.F(32.BP) -``` - -**步骤4**: Tanh近似 -```scala -val tanh_out = tanhApprox(scaled) -``` - -**步骤5**: 最终组合 -```scala -val gelu_out = 0.5.F(32.BP) * x * (1.F(32.BP) + tanh_out) -``` - -#### 5.1.4 结果写回 (Store) - -1. **目标选择**: 根据`is_acc_reg`决定写入SRAM或ACC -2. **写请求**: - ```scala - when(is_acc_reg) { - accWrite(wr_bank_reg).valid := true.B - accWrite(wr_bank_reg).bits.addr := wr_addr_reg + iter_cnt - accWrite(wr_bank_reg).bits.data := gelu_result - }.otherwise { - sramWrite(wr_bank_reg).valid := true.B - sramWrite(wr_bank_reg).bits.addr := wr_addr_reg + iter_cnt - sramWrite(wr_bank_reg).bits.data := gelu_result - } - ``` -3. **迭代控制**: 所有结果写回完成后，转移到`complete`状态 - -#### 5.1.5 完成响应 (Complete) - -1. **发送完成信号**: - ```scala - cmdResp.valid := true.B - cmdResp.bits.rob_id := rob_id_reg - cmdResp.bits.commit := true.B - ``` -2. **状态复位**: 返回`idle`状态，准备接收下一条指令 - -### 5.2 Tanh近似算法 - -由于硬件实现完整的tanh函数代价高昂，采用分段线性近似或查找表方法： - -#### 方案1: 查找表 (LUT) - -- **输入范围**: [-4, 4]，分为256个区间 -- **表项**: 每个区间存储斜率和截距 -- **插值**: 线性插值计算精确值 -- **误差**: < 0.01 - -#### 方案2: 分段多项式 - -将输入域划分为多个区间，每个区间用二阶多项式近似： - -``` -tanh(x) ≈ a₂x² + a₁x + a₀ (for x ∈ [x_min, x_max]) -``` - -- **区间数**: 8-16个区间 -- **系数存储**: 每区间3个系数 (a₀, a₁, a₂) -- **误差**: < 0.001 - -### 5.3 数据格式支持 - -#### 5.3.1 浮点数格式 (FP32) - -- **符号位**: 1位 -- **指数位**: 8位 (偏移127) -- **尾数位**: 23位 -- **范围**: ±1.4E-45 至 ±3.4E+38 -- **精度**: 约7位十进制 - -#### 5.3.2 半精度浮点 (FP16) - -- **符号位**: 1位 -- **指数位**: 5位 (偏移15) -- **尾数位**: 10位 -- **优势**: 节省50%存储和带宽 - -#### 5.3.3 定点数格式 (INT8/INT16) - -对于量化模型，支持定点数GELU计算： - -- **量化参数**: scale, zero_point -- **计算流程**: - 1. 反量化: `x_fp = (x_int - zero_point) * scale` - 2. GELU计算: `y_fp = GELU(x_fp)` - 3. 量化: `y_int = round(y_fp / scale) + zero_point` - -### 5.4 向量化处理 - -GELU单元支持向量级并行计算，典型配置为16通道： - -``` -Input Vector: [x₀, x₁, x₂, ..., x₁₅] - │ │ │ │ - ┌────┼───┼───┼───────┼────┐ - │ GELU Compute Array (16x) │ - └────┼───┼───┼───────┼────┘ - │ │ │ │ -Output Vector: [y₀, y₁, y₂, ..., y₁₅] -``` - -每个通道独立计算，共享控制逻辑但使用独立的数据路径。 - -### 5.5 流水线控制 - -4级流水线允许不同阶段重叠执行： - -| 周期 | Stage 0 | Stage 1 | Stage 2 | Stage 3 | -|-----|---------|---------|---------|---------| -| T0 | Decode | - | - | - | -| T1 | Decode | Load | - | - | -| T2 | Decode | Load | Exec | - | -| T3 | Decode | Load | Exec | Store | -| T4 | Idle | Load | Exec | Store | - -**吞吐率**: 在连续向量处理时，可达1次GELU/周期（每次处理16个元素） - - -## 6. 时序特性 (Timing Characteristics) - -### 6.1 延迟分析 - -| 操作阶段 | 周期数 | 说明 | -|---------|-------|------| -| 指令解码 (ID) | 1 | 命令参数捕获 | -| 数据加载 (Load) | 3-4 | SRAM读延迟 | -| GELU计算 (Exec) | 8-10 | 多级乘法和tanh近似 | -| 结果写回 (Store) | 2-3 | SRAM/ACC写延迟 | -| 完成响应 (Complete) | 1 | ROB通知 | -| **总延迟** | **15-19** | 典型值16周期 | - -### 6.2 关键路径 - -最长组合逻辑路径出现在Execute阶段的乘法器链： - -``` -x → MUL(x²) → MUL(x³) → MUL(poly) → TANH → MUL(final) -``` - -**优化策略**: -1. 插入流水线寄存器，将8-10周期的计算分解为多个子阶段 -2. 使用Booth编码乘法器减少关键路径 -3. Tanh LUT采用双端口SRAM提高访问速度 - - -## 7. 配置参数 (Configuration Parameters) - -### 7.1 编译时参数 - -通过`CustomBuckyballConfig`配置： - -| 参数名称 | 类型 | 默认值 | 描述 | -|---------|------|--------|------| -| `veclane` | Int | 16 | 向量通道数 | -| `sp_banks` | Int | 4 | Scratchpad Bank数量 | -| `acc_banks` | Int | 2 | Accumulator Bank数量 | -| `spad_bank_entries` | Int | 1024 | 每个SRAM Bank条目数 | -| `acc_bank_entries` | Int | 512 | 每个ACC Bank条目数 | -| `inputType` | DataType | FP32 | 输入数据类型 | -| `outputType` | DataType | FP32 | 输出数据类型 | -| `gelu_pipeline_depth` | Int | 10 | GELU流水线深度 | -| `tanh_lut_size` | Int | 256 | Tanh查找表大小 | - -### 7.2 运行时参数 - -通过Ball Domain指令传递： - -| 参数 | 位宽 | 范围 | 描述 | -|-----|------|------|------| -| `iter` | 10 | 1-1024 | 向量迭代次数 | -| `op1_bank` | 2 | 0-3 | 输入数据Bank | -| `op1_bank_addr` | 12 | 0-4095 | 输入起始地址 | -| `wr_bank` | 2 | 0-3 | 输出数据Bank | -| `wr_bank_addr` | 12 | 0-4095 | 输出起始地址 | -| `is_acc` | 1 | 0-1 | 输出目标 (0=SRAM, 1=ACC) | - - -## 9. 验证方案 (Verification Plan) - -### 9.1 功能验证 - -#### 9.1.1 单元测试 - -- **基本功能**: 单个元素GELU计算正确性 -- **边界条件**: 零值、最大值、最小值、NaN、Inf -- **向量处理**: 16元素并行计算一致性 -- **迭代处理**: 多次迭代的地址和数据正确性 - -#### 9.1.2 精度验证 - -与软件参考模型（PyTorch/NumPy）对比： - -```python -import torch -import numpy as np - -# Reference GELU -def gelu_ref(x): - return torch.nn.functional.gelu(x) - -# Test vectors -test_inputs = torch.randn(1000, 16) -golden_outputs = gelu_ref(test_inputs) - -# Compare with hardware outputs -max_error = torch.max(torch.abs(hw_outputs - golden_outputs)) -mean_error = torch.mean(torch.abs(hw_outputs - golden_outputs)) - -assert max_error < 1e-3, f"Max error {max_error} exceeds threshold" -``` - -### 9.3 集成验证 - -- **完整系统**: 在ToyBuckyball环境中集成测试 -- **编译器支持**: 验证MLIR lowering生成正确的GELU指令 -- **端到端**: 运行完整的Transformer模型，验证功能和性能 - - -## 10. 软件接口 (Software Interface) - -### 10.1 MLIR Dialect扩展 - -在Buckyball Dialect中添加GELU操作： - -```mlir -// MLIR IR -%output = buckyball.gelu %input : tensor<1024xf32> - -// Lowering to hardware intrinsic -func.func @gelu_layer(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) { - %c0 = arith.constant 0 : index - %c1024 = arith.constant 1024 : index - - // Issue GELU instruction to hardware - buckyball.gelu.hw %arg0, %arg1, %c0, %c1024 - {op1_bank = 0, wr_bank = 1, is_acc = 0} - - return -} -``` - -### 10.2 C/C++ Intrinsics - -提供底层硬件访问接口： - -```c -// C intrinsic -void gelu_hw( - float* input, // Input vector address - float* output, // Output vector address - int iter, // Number of vectors (each 16 elements) - int op1_bank, // Input bank - int op1_addr, // Input address offset - int wr_bank, // Output bank - int wr_addr, // Output address offset - bool is_acc // Write to accumulator -) { - // Encode instruction - uint64_t inst = encode_gelu_inst( - iter, op1_bank, op1_addr, wr_bank, wr_addr, is_acc - ); - - // Issue RoCC instruction - ROCC_INSTRUCTION(GELU_OPCODE, inst); - - // Wait for completion (optional) - wait_gelu_complete(); -} -``` - -### 10.3 编译器优化 - -#### Fusion优化 - -将连续的GELU操作与其他算子融合： - -``` -// Before -%1 = matmul(%A, %B) -%2 = add(%1, %bias) -%3 = gelu(%2) - -// After (fused) -%3 = matmul_add_gelu(%A, %B, %bias) -``` - -#### Tiling优化 - -大张量分块处理，优化内存访问： - -``` -// Original -%out = gelu(%in : tensor<10240xf32>) - -// Tiled (64 iterations of 16 elements) -for i in 0..64: - %tile_in = extract(%in, i*16, 16) - %tile_out = gelu(%tile_in) - insert(%out, %tile_out, i*16) -``` - - -## 11. 使用示例 (Usage Examples) - -### 11.1 基本用法 - -```scala -// Instantiate GELU unit -val geluUnit = Module(new GeluUnit) - -// Connect to Ball Domain -geluUnit.io.cmdReq <> ballDomain.io.geluReq -ballDomain.io.geluResp <> geluUnit.io.cmdResp - -// Connect to memory system -for (i <- 0 until sp_banks) { - scratchpad.io.read(i) <> geluUnit.io.sramRead(i) - scratchpad.io.write(i) <> geluUnit.io.sramWrite(i) -} - -for (i <- 0 until acc_banks) { - accumulator.io.read(i) <> geluUnit.io.accRead(i) - accumulator.io.write(i) <> geluUnit.io.accWrite(i) -} - -// Status monitoring (optional) -// Can be connected to performance counters or debug interface -val geluStatus = geluUnit.io.status -``` - -### 11.2 单次向量GELU - -```c -// Process single vector (16 elements) -float input[16] = {-2.0, -1.5, ..., 2.0}; -float output[16]; - -// Load input to SRAM bank 0, address 0x100 -load_to_sram(0, 0x100, input, 16); - -// Issue GELU instruction -gelu_hw( - input, output, - 1, // iter = 1 (single vector) - 0, // op1_bank = 0 - 0x100, // op1_addr - 1, // wr_bank = 1 - 0x200, // wr_addr - false // is_acc = false (write to SRAM) -); - -// Read result from SRAM bank 1, address 0x200 -read_from_sram(1, 0x200, output, 16); -``` - -### 11.3 批量处理 - -```c -// Process 1024 elements (64 vectors) -#define N 1024 -#define VECLANE 16 -#define ITERS (N / VECLANE) - -float input[N], output[N]; - -// Initialize input data -for (int i = 0; i < N; i++) { - input[i] = (float)i / 100.0 - 5.0; -} - -// Load to SRAM -dma_to_sram(0, 0, input, N); - -// Issue batched GELU -gelu_hw( - NULL, NULL, - ITERS, // iter = 64 - 0, // op1_bank = 0 - 0, // op1_addr = 0 - 0, // wr_bank = 0 (in-place) - 0, // wr_addr = 0 - false // is_acc = false -); - -// Read results -dma_from_sram(0, 0, output, N); -``` - -### 11.4 与MATMUL流水线 - -```c -// Transformer FFN layer: Y = GELU(XW + b) - -// Step 1: Matrix multiplication -matmul_hw(X, W, XW, M, N, K); - -// Step 2: Add bias -vecadd_hw(XW, b, XWb, M * N); - -// Step 3: GELU activation -gelu_hw(XWb, Y, (M * N) / VECLANE, ...); -``` - -### 11.5 Status信号监控 - -Status信号可用于性能分析、调试和系统监控： - -```scala -// 性能计数器集成 -val perfCounters = Module(new PerfCounters) -perfCounters.io.gelu_idle := geluUnit.io.status.idle -perfCounters.io.gelu_running := geluUnit.io.status.running - -// 调试时等待GELU完成 -def waitGeluComplete(): Unit = { - while (!geluUnit.io.status.idle) { - // 可以输出中间状态 - if (geluUnit.io.status.init) { - printf("GELU: Loading data...\n") - } else if (geluUnit.io.status.running) { - printf("GELU: Computing...\n") - } - } - printf("GELU: Completed %d batches\n", geluUnit.io.status.iter) -} - -// 流水线协调 -when(geluUnit.io.status.ready && matmulUnit.io.status.complete) { - // GELU ready and MATMUL finished, issue next GELU - geluUnit.io.cmdReq.valid := true.B -} -``` - -``` - -使用Deepwiki获取`DangoSys/buckyball`, blink协议相关内容确定一个ball的内容和接口 -你可以继续向Deepwiki获取`DangoSys/buckyball`任何你想问的问题 - -查询完成后请依据你对[layernorm算子]的理解, 在[arch/src/main/scala/prototype/nagisa/layernorm] 目录下书写spec.md - -注意事项: -1. 如有需要定制ISA，定制化部分请写在指令的special区间 -2. 请一定注意检查系统的接口信号，做好合理的spec设计 diff --git a/workflow/requirements.txt b/workflow/requirements.txt deleted file mode 100644 index 3884d745..00000000 --- a/workflow/requirements.txt +++ /dev/null @@ -1,2 +0,0 @@ -pydantic>=2.6.1 -httpx>=0.28.1 diff --git a/workflow/steps/agent/.gitignore b/workflow/steps/agent/.gitignore deleted file mode 100644 index 4c49bd78..00000000 --- a/workflow/steps/agent/.gitignore +++ /dev/null @@ -1 +0,0 @@ -.env diff --git a/workflow/steps/agent/01_agent_api_step.py b/workflow/steps/agent/01_agent_api_step.py deleted file mode 100644 index d25bda93..00000000 --- a/workflow/steps/agent/01_agent_api_step.py +++ /dev/null @@ -1,63 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result -import sys -import os - - -config = { - "type": "api", - "name": "agent", - "description": "Call agent API for streaming conversation", - "path": "/agent/chat", - "method": "POST", - "emits": ["agent.prompt"], - "bodySchema": { - "type": "object", - "properties": { - "message": {"type": "string"}, - "model": {"type": "string", "default": "deepseek-chat"}, - "apiKey": {"type": "string"}, - "baseUrl": {"type": "string"}, - }, - "required": ["message"], - }, - "responseSchema": { - "200": { - "type": "object", - "properties": {"traceId": {"type": "string"}, "status": {"type": "string"}}, - } - }, - "flows": ["agent"], -} - - -async def handler(req, context): - context.logger.info("agent API - Request received", {"body": req.get("body")}) - body = req.get("body") - message = body.get("message") - model = body.get("model", "deepseek-chat") - api_key = body.get("apiKey") - base_url = body.get("baseUrl") - - # Send event to processing step - await context.emit( - { - "topic": "agent.prompt", - "data": { - "message": message, - "model": model, - "traceId": context.trace_id, - "apiKey": api_key, - "baseUrl": base_url, - }, - } - ) - - # ================================================================================== - # Wait for execution result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/agent/01_agent_event_step.py b/workflow/steps/agent/01_agent_event_step.py deleted file mode 100644 index 492f3f49..00000000 --- a/workflow/steps/agent/01_agent_event_step.py +++ /dev/null @@ -1,154 +0,0 @@ -import httpx -import json -import os -from dotenv import load_dotenv -import sys - -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -load_dotenv() - -config = { - "type": "event", - "name": "agent", - "description": "Handle agent streaming response", - "subscribes": ["agent.prompt"], - "emits": ["agent.response"], - "input": { - "type": "object", - "properties": { - "message": {"type": "string"}, - "model": {"type": "string"}, - "traceId": {"type": "string"}, - "apiKey": {"type": "string"}, - "baseUrl": {"type": "string"}, - }, - }, - "flows": ["agent"], -} - - -async def handler(input_data, context): - context.logger.info("agent - Starting processing", {"input": input_data}) - - message = input_data.get("message") - model = input_data.get("model", "deepseek-chat") - trace_id = input_data.get("traceId") - - # API configuration: prefer parameters passed in, otherwise use environment variables - api_key = input_data.get("apiKey") or os.getenv("API_KEY") - base_url = input_data.get("baseUrl") or os.getenv( - "BASE_URL", "https://api.deepseek.com/v1" - ) - - if not api_key: - error_msg = "API Key not provided" - context.logger.error(error_msg) - await context.emit( - { - "topic": "agent.error", - "data": { - "error": error_msg, - "original_message": message, - "traceId": trace_id, - }, - } - ) - await check_result(context, 1, continue_run=False) - return - - headers = {"Authorization": f"Bearer {api_key}", "Content-Type": "application/json"} - - payload = { - "model": model, - "messages": [{"role": "user", "content": message}], - "stream": True, - "temperature": 0.7, - } - - try: - async with httpx.AsyncClient() as client: - async with client.stream( - "POST", - f"{base_url}/chat/completions", - headers=headers, - json=payload, - timeout=60.0, - ) as response: - - if response.status_code != 200: - context.logger.error(f"agent API error: {response.status_code}") - return - - full_response = "" - - async for line in response.aiter_lines(): - if line.startswith("data: "): - # Remove "data: " prefix - data = line[6:] - - if data == "[DONE]": - break - - try: - chunk = json.loads(data) - if "choices" in chunk and len(chunk["choices"]) > 0: - delta = chunk["choices"][0].get("delta", {}) - content = delta.get("content", "") - - if content: - full_response += content - context.logger.info(f"{content}") - - except json.JSONDecodeError: - continue - - # Send complete response - await context.emit( - { - "topic": "agent.response", - "data": { - "response": full_response, - "original_message": message, - "traceId": trace_id, - }, - } - ) - - context.logger.info( - "agent processing completed", - {"response_length": len(full_response), "traceId": trace_id}, - ) - - # Pass response content back to API via extra_fields - success_result, failure_result = await check_result( - context, 0, continue_run=False, extra_fields={"response": full_response} - ) - - except Exception as e: - context.logger.error(f"agent API call failed: {str(e)}") - await context.emit( - { - "topic": "agent.error", - "data": { - "error": str(e), - "original_message": message, - "traceId": trace_id, - }, - } - ) - - # Pass error information back to API via extra_fields - success_result, failure_result = await check_result( - context, 1, continue_run=False, extra_fields={"error": str(e)} - ) - - # ================================================================================== - # finish workflow - # ================================================================================== - return diff --git a/workflow/steps/agent/README.md b/workflow/steps/agent/README.md deleted file mode 100644 index e6fe4b89..00000000 --- a/workflow/steps/agent/README.md +++ /dev/null @@ -1,40 +0,0 @@ -# Agent Workflow - -AI assistant workflow in Buckyball framework, providing conversational interaction with AI models. - -## API Usage - -### `chat` -**Endpoint**: `POST /agent/chat` - -**Function**: Conversational interaction with AI assistant - -**Parameters**: -- **`message`** [Required] - Message content to send to AI -- **`model`** - AI model to use, default `"deepseek-chat"` - -**Examples**: -```bash -# Basic conversation -bbdev agent --chat "--message 'Hello, can you help me with Buckyball development?'" - -# Specify model -bbdev agent --chat "--message 'Explain this Scala code' --model deepseek-chat" - -# Code analysis -bbdev agent --chat "--message 'Please analyze this Chisel module and suggest optimizations'" -``` - -**Response**: -```json -{ - "traceId": "unique-trace-id", - "status": "success" -} -``` - -## Notes - -- Requires configured AI model API key -- Responses use streaming output -- Note message length limits diff --git a/workflow/steps/agent/example_prompt.md b/workflow/steps/agent/example_prompt.md deleted file mode 100644 index c834ca3b..00000000 --- a/workflow/steps/agent/example_prompt.md +++ /dev/null @@ -1,22 +0,0 @@ -# Code Generation Task - -## Objective -Create a simple Python calculator module with basic arithmetic operations. - -## Requirements -1. Create a file named `calculator.py` -2. Implement the following functions: - - `add(a, b)` - returns sum of two numbers - - `subtract(a, b)` - returns difference of two numbers - - `multiply(a, b)` - returns product of two numbers - - `divide(a, b)` - returns quotient of two numbers (handle division by zero) - -3. Each function should include: - - Type hints - - Docstrings - - Error handling where appropriate - -## Code Style -- Use 2 spaces for indentation -- Follow PEP 8 guidelines -- Keep function names concise but descriptive diff --git a/workflow/steps/agent/example_refactor_prompt.md b/workflow/steps/agent/example_refactor_prompt.md deleted file mode 100644 index 07089729..00000000 --- a/workflow/steps/agent/example_refactor_prompt.md +++ /dev/null @@ -1,37 +0,0 @@ -# 代码重构任务示例 - -## 目标 -重构现有的 calculator.py 文件，添加错误处理和日志功能 - -## 需求 - -### 1. 分析现有代码 -- 先读取 calculator.py 文件查看当前实现 -- 分析可以改进的地方 - -### 2. 添加日志功能 -- 为每个函数添加日志记录 -- 记录函数调用和参数 -- 记录计算结果 - -### 3. 增强错误处理 -- 添加输入类型检查 -- 完善除零错误处理 -- 添加有意义的错误消息 - -### 4. 代码优化 -- 保持现有的函数签名和文档字符串 -- 确保向后兼容性 -- 遵循 PEP 8 规范 - -## 代码风格 -- 使用 2 空格缩进 -- 添加详细的注释 -- 保持函数简洁 - -## 预期行为 -AI 应该： -1. 首先调用 read_file 读取现有的 calculator.py -2. 分析代码结构 -3. 调用 write_file 写入改进后的版本 -4. 解释做了哪些改进 diff --git a/workflow/steps/agent/test_code_agent.sh b/workflow/steps/agent/test_code_agent.sh deleted file mode 100755 index e53e64a1..00000000 --- a/workflow/steps/agent/test_code_agent.sh +++ /dev/null @@ -1,90 +0,0 @@ -#!/bin/bash - -# Code Agent 测试脚本 -# 演示如何使用 Function Calling 功能 - -BASE_URL="http://localhost:3001" -WORK_DIR="/home/mio/Code/buckyball/workflow/steps/agent" -MODEL="claude-sonnet-4-20250514" - -echo "==========================================" -echo "Code Agent Function Calling 测试" -echo "==========================================" -echo "" -echo "⚠️ 注意：Function Calling 模式下，AI 会多次调用工具" -echo " 每次请求可能需要 10-30 秒，请耐心等待" -echo "" - -echo "" -echo "测试 1: 单次代码生成" -echo "----------------------------" -echo "⏳ 请等待，AI 正在思考和调用工具..." -curl -s -X POST "$BASE_URL/agent/code" \ - -H "Content-Type: application/json" \ - -d "{ - \"promptPath\": \"example_prompt.md\", - \"model\": \"$MODEL\", - \"workDir\": \"$WORK_DIR\" - }" | jq - -echo "" -echo "" -echo "测试 2: 代码重构（需要先读取现有文件）" -echo "----------------------------" -echo "⏳ AI 会先读取文件，然后生成代码..." -curl -s -X POST "$BASE_URL/agent/code" \ - -H "Content-Type: application/json" \ - -d "{ - \"promptPath\": \"example_refactor_prompt.md\", - \"model\": \"$MODEL\", - \"workDir\": \"$WORK_DIR\" - }" | jq - -echo "" -echo "" -echo "测试 3: 多轮对话 - 第一轮" -echo "----------------------------" -echo "⏳ 创建新会话..." -SESSION_ID="test-session-$(date +%s)" -curl -s -X POST "$BASE_URL/agent/code" \ - -H "Content-Type: application/json" \ - -d "{ - \"promptPath\": \"example_prompt.md\", - \"workDir\": \"$WORK_DIR\", - \"model\": \"$MODEL\", - \"sessionId\": \"$SESSION_ID\" - }" | jq - -echo "" -echo "等待 2 秒..." -sleep 2 - -echo "" -echo "测试 3: 多轮对话 - 第二轮（使用同一个 session）" -echo "----------------------------" -echo "⏳ 继续之前的会话..." -# 创建一个临时 prompt -cat > /tmp/continue_prompt.md << EOF -# 继续任务 - -基于刚才创建的代码，请添加一个测试文件 test_calculator.py，包含基本的单元测试。 -EOF - -curl -s -X POST "$BASE_URL/agent/code" \ - -H "Content-Type: application/json" \ - -d "{ - \"promptPath\": \"/tmp/continue_prompt.md\", - \"workDir\": \"$WORK_DIR\", - \"model\": \"$MODEL\", - \"sessionId\": \"$SESSION_ID\" - }" | jq - -echo "" -echo "==========================================" -echo "测试完成！" -echo "==========================================" -echo "" -echo "查看生成的文件：" -echo " ls -la $WORK_DIR/*.py" -echo "" -echo "检查日志了解 AI 的工具调用过程" diff --git a/workflow/steps/compiler/01_build_api_step.py b/workflow/steps/compiler/01_build_api_step.py deleted file mode 100644 index e2420520..00000000 --- a/workflow/steps/compiler/01_build_api_step.py +++ /dev/null @@ -1,26 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Build Compiler", - "description": "build bitstream", - "path": "/compiler/build", - "method": "POST", - "emits": ["compiler.build"], - "flows": ["compiler"], -} - - -async def handler(req, context): - body = req.get("body") or {} - await context.emit({"topic": "compiler.build", "data": body}) - - # ================================================================================== - # Wait for build result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/compiler/01_build_event_step.py b/workflow/steps/compiler/01_build_event_step.py deleted file mode 100644 index 6cbd2dde..00000000 --- a/workflow/steps/compiler/01_build_event_step.py +++ /dev/null @@ -1,56 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "Build Compiler", - "description": "build bitstream", - "subscribes": ["compiler.build"], - "emits": [], - "flows": ["compiler"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - script_dir = f"{bbdir}/workflow/steps/compiler/scripts" - yaml_dir = f"{script_dir}/yaml" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"source {bbdir}/env.sh && mkdir -p {bbdir}/compiler/build" - result = stream_run_logger( - cmd=command, - logger=context.logger, - stdout_prefix="compiler build", - stderr_prefix="compiler build", - ) - command = f"cd {bbdir}/compiler/build && ninja -j{os.cpu_count()}" - result = stream_run_logger( - cmd=command, - logger=context.logger, - stdout_prefix="compiler build", - stderr_prefix="compiler build", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # ================================================================================== - return diff --git a/workflow/steps/compiler/README.md b/workflow/steps/compiler/README.md deleted file mode 100644 index 993560bc..00000000 --- a/workflow/steps/compiler/README.md +++ /dev/null @@ -1,33 +0,0 @@ -# Compiler Workflow - -Compiler build workflow in the Buckyball framework for building the Buckyball compiler toolchain. - -## API Usage - -### `build` -**Endpoint**: `POST /compiler/build` - -**Function**: Build Buckyball compiler - -**Parameters**: No specific parameters - -**Example**: -```bash -bbdev compiler --build -``` - -**Response**: -```json -{ - "status": 200, - "body": { - "success": true, - "processing": false, - "return_code": 0 - } -} -``` - -## Notes - -- Ensure the system has necessary build tools and dependencies diff --git a/workflow/steps/doc-agent/.env b/workflow/steps/doc-agent/.env deleted file mode 100644 index 596589c5..00000000 --- a/workflow/steps/doc-agent/.env +++ /dev/null @@ -1,2 +0,0 @@ -API_KEY=replace_with_your_key -BASE_URL=https://api.deepseek.com/v1 diff --git a/workflow/steps/doc-agent/00_doc_agent_api_step.py b/workflow/steps/doc-agent/00_doc_agent_api_step.py deleted file mode 100644 index 308a699d..00000000 --- a/workflow/steps/doc-agent/00_doc_agent_api_step.py +++ /dev/null @@ -1,112 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result -import sys -import os - - -config = { - "type": "api", - "name": "doc_agent", - "description": "Generate code directory documentation", - "path": "/doc/generate", - "method": "POST", - "emits": ["doc.generate"], - "bodySchema": { - "type": "object", - "properties": { - "target_path": {"type": "string"}, - "mode": {"type": "string", "enum": ["create", "update"]}, - }, - "required": ["target_path", "mode"], - }, - "responseSchema": { - "200": { - "type": "object", - "properties": { - "traceId": {"type": "string"}, - "status": {"type": "string"}, - "message": {"type": "string"}, - }, - }, - "400": { - "type": "object", - "properties": {"error": {"type": "string"}, "details": {"type": "string"}}, - }, - }, - "flows": ["doc_agent"], -} - - -async def handler(req, context): - context.logger.info("doc-agent API - Request received", {"body": req.get("body")}) - - # Parameter validation - body = req.get("body", {}) - target_path = body.get("target_path") - mode = body.get("mode") - - # Validate required parameters - if not target_path: - context.logger.error("doc-agent API - Missing target_path parameter") - return { - "status": 400, - "body": { - "error": "Missing required parameter", - "details": "target_path is required", - }, - } - - if not mode: - context.logger.error("doc-agent API - Missing mode parameter") - return { - "status": 400, - "body": { - "error": "Missing required parameter", - "details": "mode is required", - }, - } - - # Validate mode parameter value - if mode not in ["create", "update"]: - context.logger.error("doc-agent API - Invalid mode parameter", {"mode": mode}) - return { - "status": 400, - "body": { - "error": "Invalid parameter value", - "details": "mode must be either 'create' or 'update'", - }, - } - - # Validate target_path exists - if not os.path.exists(target_path): - context.logger.error( - "doc-agent API - Target path does not exist", {"target_path": target_path} - ) - return { - "status": 400, - "body": { - "error": "Invalid target path", - "details": f"Path '{target_path}' does not exist", - }, - } - - # Send event to processing step - await context.emit( - { - "topic": "doc.generate", - "data": { - "target_path": target_path, - "mode": mode, - "traceId": context.trace_id, - }, - } - ) - - # ================================================================================== - # Wait for execution result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/doc-agent/01_doc_agent_event_step.py b/workflow/steps/doc-agent/01_doc_agent_event_step.py deleted file mode 100644 index b24c39bf..00000000 --- a/workflow/steps/doc-agent/01_doc_agent_event_step.py +++ /dev/null @@ -1,195 +0,0 @@ -import httpx -import json -import os -import sys -from pathlib import Path -from dotenv import load_dotenv - -# Import local utility modules -current_dir = Path(__file__).parent -sys.path.insert(0, str(current_dir)) -from doc_utils import detect_doc_type, load_prompt_template, prepare_update_mode_prompt - -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.event_common import check_result - -load_dotenv() - -config = { - "type": "event", - "name": "doc_agent", - "description": "Handle documentation generation requests", - "subscribes": ["doc.generate"], - "emits": ["doc.response", "doc.integrate"], - "input": { - "type": "object", - "properties": { - "target_path": {"type": "string"}, - "mode": {"type": "string"}, - "traceId": {"type": "string"}, - }, - }, - "flows": ["doc_agent"], -} - - -async def handler(input_data, context): - context.logger.info("doc-agent - Start processing", {"input": input_data}) - - target_path = input_data.get("target_path") - mode = input_data.get("mode") - trace_id = input_data.get("traceId") - - try: - # 1. Detect document type and prepare prompt - doc_type = detect_doc_type(target_path) - context.logger.info( - "doc-agent - Document type detected", {"doc_type": doc_type} - ) - - prompt_template = load_prompt_template(doc_type, target_path) - prompt_template = prepare_update_mode_prompt(prompt_template, target_path, mode) - - # 2. Call LLM API to generate documentation - full_response = await generate_documentation(prompt_template, context) - - # 3. Save documentation - output_path = os.path.join(target_path, "README.md") - with open(output_path, "w", encoding="utf-8") as f: - f.write(full_response) - context.logger.info( - "doc-agent - Documentation saved", {"output_path": output_path} - ) - - # 4. Send integration event - await context.emit( - { - "topic": "doc.integrate", - "data": { - "target_path": target_path, - "output_path": output_path, - "doc_type": doc_type, - "traceId": trace_id, - }, - } - ) - - # 5. Send completion response - await send_success_response( - context, target_path, mode, doc_type, output_path, full_response, trace_id - ) - - except Exception as e: - await send_error_response(context, str(e), target_path, mode, trace_id) - - -async def generate_documentation(prompt_template, context): - """Call LLM API to generate documentation""" - api_key = os.getenv("API_KEY") - base_url = os.getenv("BASE_URL", "https://api.deepseek.com/v1") - - headers = {"Authorization": f"Bearer {api_key}", "Content-Type": "application/json"} - payload = { - "model": "deepseek-chat", - "messages": [{"role": "user", "content": prompt_template}], - "stream": True, - "temperature": 0.3, - } - - async with httpx.AsyncClient() as client: - async with client.stream( - "POST", - f"{base_url}/chat/completions", - headers=headers, - json=payload, - timeout=120.0, - ) as response: - - if response.status_code != 200: - error_text = await response.atext() - raise Exception( - f"API call failed: {response.status_code}, {error_text}" - ) - - full_response = "" - async for line in response.aiter_lines(): - if line.startswith("data: ") and line[6:] != "[DONE]": - try: - chunk = json.loads(line[6:]) - content = ( - chunk.get("choices", [{}])[0] - .get("delta", {}) - .get("content", "") - ) - if content: - full_response += content - context.logger.info(f"{content}") - except json.JSONDecodeError: - continue - - return full_response - - -async def send_success_response( - context, target_path, mode, doc_type, output_path, full_response, trace_id -): - """Send success response""" - await context.emit( - { - "topic": "doc.response", - "data": { - "response": full_response, - "target_path": target_path, - "mode": mode, - "doc_type": doc_type, - "output_path": output_path, - "traceId": trace_id, - }, - } - ) - - success_result, failure_result = await check_result( - context, - 0, - continue_run=False, - extra_fields={ - "message": f"Documentation generation successful: {output_path}", - "data": { - "target_path": target_path, - "mode": mode, - "doc_type": doc_type, - "output_path": output_path, - "response_length": len(full_response), - }, - }, - ) - - -async def send_error_response(context, error_msg, target_path, mode, trace_id): - """Send error response""" - full_error_msg = f"doc-agent processing failed: {error_msg}" - context.logger.error(full_error_msg) - - await context.emit( - { - "topic": "doc.error", - "data": { - "error": full_error_msg, - "target_path": target_path, - "mode": mode, - "traceId": trace_id, - }, - } - ) - - success_result, failure_result = await check_result( - context, - 1, - continue_run=False, - extra_fields={ - "error": full_error_msg, - }, - ) diff --git a/workflow/steps/doc-agent/README.md b/workflow/steps/doc-agent/README.md deleted file mode 100644 index f9c15216..00000000 --- a/workflow/steps/doc-agent/README.md +++ /dev/null @@ -1,46 +0,0 @@ -# Doc-Agent Workflow - -Documentation generation workflow in the Buckyball framework, providing automated code documentation generation functionality. - -## API Usage Guide - -### `generate` -**Endpoint**: `POST /doc/generate` - -**Function**: Generate documentation for specified directory - -**Parameters**: -- **`target_path`** [Required] - Target directory path -- **`mode`** [Required] - Generation mode, options: `"create"`, `"update"` - -**Example**: -```bash -# Create new documentation for specified directory -bbdev doc --generate "--target_path arch/src/main/scala/framework --mode create" - -# Update existing documentation -bbdev doc --generate "--target_path arch/src/main/scala/framework --mode update" -``` - -**Response**: -```json -{ - "traceId": "unique-trace-id", - "status": "success", - "message": "Documentation generated successfully" -} -``` - -## Supported Document Types - -- RTL hardware documentation -- Test documentation -- Script documentation -- Simulator documentation -- Workflow documentation - -## Important Notes - -- Requires AI model API key configuration -- Generated documentation is automatically integrated into the mdBook system -- Supports symbolic link management and automatic SUMMARY.md updates diff --git a/workflow/steps/doc-agent/doc_agent_README.md b/workflow/steps/doc-agent/doc_agent_README.md deleted file mode 100644 index 252187dd..00000000 --- a/workflow/steps/doc-agent/doc_agent_README.md +++ /dev/null @@ -1,401 +0,0 @@ -# Doc-Agent User Documentation - -## Overview - -Doc-Agent is an automated documentation generation system built on the Motia framework, capable of automatically generating high-quality Chinese technical documentation for different types of directories in the codebase. The system supports various document types, including RTL hardware documentation, test documentation, script documentation, simulator documentation, and workflow documentation. - -## System Architecture - -Doc-Agent adopts an event-driven microservice architecture: - -``` -API Interface → Event Processing → Document Generation → Integration Management → mdBook Integration -``` - -- **API Step**: Receives HTTP requests and triggers document generation events -- **Event Step**: Handles document generation logic and calls LLM API -- **Integration Step**: Manages symbolic links and SUMMARY.md updates -- **Template System**: Provides dedicated templates for various document types - -## API Interface Description - -### Endpoint Information - -- **URL**: `POST /doc/generate` -- **Content-Type**: `application/json` -- **Description**: Generate documentation for specified directory - -### Request Parameters - -| Parameter | Type | Required | Description | -|--------|------|------|------| -| `target_path` | string | Yes | Relative path to target code directory | -| `mode` | string | Yes | Generation mode: `create` or `update` | - -#### Mode Description - -- **create**: Create new documentation from scratch, suitable for directories without existing documentation -- **update**: Update existing documentation, retain accurate content, correct outdated information - -### Response Format - -#### Success Response (200) -```json -{ - "status": "success", - "message": "Documentation generation task started", - "data": { - "target_path": "arch/src/main/scala/framework", - "mode": "create", - "doc_type": "rtl", - "trace_id": "doc-gen-20241201-001" - } -} -``` - -#### Error Response (400/500) -```json -{ - "status": "error", - "message": "Error description", - "error_code": "INVALID_PATH", - "details": { - "target_path": "Provided path does not exist or is inaccessible" - } -} -``` - -## Usage Examples - -### Basic Usage - -#### 1. Generate RTL Hardware Documentation -```bash -curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d '{ - "target_path": "arch/src/main/scala/framework/builtin", - "mode": "create" - }' -``` - -#### 2. Update Test Documentation -```bash -curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d '{ - "target_path": "bb-tests/workloads/src", - "mode": "update" - }' -``` - -#### 3. Generate Script Documentation -```bash -curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d '{ - "target_path": "scripts/docker", - "mode": "create" - }' -``` - -### Batch Processing Examples - -#### Process Entire Test Directory -```bash -# Process all bb-tests subdirectories -for dir in workloads customext sardine uvbb; do - curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d "{\"target_path\": \"bb-tests/$dir\", \"mode\": \"create\"}" - sleep 2 # Avoid concurrent overload -done -``` - -#### Batch Update Existing Documentation -```bash -# Update documentation for all major directories -targets=("arch/src/main/scala" "bb-tests/workloads" "scripts" "sims/func-sim" "workflow/steps") - -for target in "${targets[@]}"; do - echo "Updating documentation: $target" - curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d "{\"target_path\": \"$target\", \"mode\": \"update\"}" - echo "Waiting for processing to complete..." - sleep 5 -done -``` - -## Supported Document Types - -The system automatically identifies document types based on directory paths: - -| Path Pattern | Doc Type | Template File | Description | -|----------|----------|----------|------| -| `arch/src/main/scala/**` | RTL | rtl-doc.md | RTL hardware module documentation | -| `bb-tests/workloads/**` | Workloads | workloads-doc.md | Workload test documentation | -| `bb-tests/customext/**` | CustomExt | customext-doc.md | Custom extension test documentation | -| `bb-tests/sardine/**` | Sardine | sardine-doc.md | Sardine test framework documentation | -| `bb-tests/uvbb/**` | UVBB | uvbb-doc.md | UVBB test documentation | -| `scripts/**` | Script | script-doc.md | Script and tool documentation | -| `sims/**` | Simulator | sim-doc.md | Simulator documentation | -| `workflow/**` | Workflow | workflow-doc.md | Workflow and automation documentation | - -## Documentation Standards - -All generated documentation follows unified standards: - -### Language Specifications -- **Main Language**: Chinese -- **Technical Terms**: Keep original English -- **Code Comments**: Provide Chinese explanations -- **Professional Tone**: Avoid using emojis and informal expressions - -### Format Specifications -- **Markdown Format**: Standard Markdown syntax -- **Code Blocks**: Use syntax highlighting -- **Links**: Use relative paths -- **Diagrams**: Support Mermaid diagrams - -### Structure Specifications -Different document types have different structure requirements, but all include: -- Overview section -- Code structure analysis -- Detailed explanation -- Usage examples (if applicable) - -## Integration Features - -### Automatic Integration to mdBook - -Generated documentation is automatically integrated into the project's mdBook documentation system: - -1. **Symbolic Link Creation**: Create corresponding directory structure under `docs/bb-note/src/` -2. **SUMMARY.md Update**: Automatically add new documentation to the table of contents -3. **Structure Validation**: Ensure code directories and documentation directories correspond one-to-one - -### Directory Mapping Example - -``` -Code Directory → Documentation Directory -arch/src/main/scala/ → docs/bb-note/src/arch/src/main/scala/ -bb-tests/workloads/ → docs/bb-note/src/bb-tests/workloads/ -scripts/docker/ → docs/bb-note/src/scripts/docker/ -``` - -## Common Issues and Troubleshooting - -### Q1: Documentation generation fails with "path does not exist" error - -**Cause**: The provided `target_path` does not exist or is inaccessible - -**Solution**: -```bash -# Check if path exists -ls -la arch/src/main/scala/framework - -# Ensure using relative path, do not start with / -# Correct: "arch/src/main/scala/framework" -# Wrong: "/arch/src/main/scala/framework" -``` - -### Q2: Generated documentation is of poor quality or inaccurate content - -**Causes**: -- Few code files in directory or insufficient comments -- Wrong generation mode selected -- LLM API response anomaly - -**Solutions**: -```bash -# 1. Check directory contents -find arch/src/main/scala/framework -name "*.scala" | head -10 - -# 2. Try update mode instead of create mode -curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d '{ - "target_path": "arch/src/main/scala/framework", - "mode": "update" - }' - -# 3. Check system logs -tail -f logs/doc-agent.log -``` - -### Q3: SUMMARY.md update fails - -**Causes**: -- SUMMARY.md file permission issues -- File format does not meet expectations -- Concurrent update conflicts - -**Solutions**: -```bash -# Check file permissions -ls -la docs/bb-note/src/SUMMARY.md - -# Backup and reset SUMMARY.md -cp docs/bb-note/src/SUMMARY.md docs/bb-note/src/SUMMARY.md.backup - -# Check file format -head -20 docs/bb-note/src/SUMMARY.md -``` - -### Q4: Symbolic link creation fails - -**Causes**: -- Insufficient permissions for target directory -- Insufficient disk space -- File system does not support symbolic links - -**Solutions**: -```bash -# Check disk space -df -h docs/ - -# Check permissions -ls -la docs/bb-note/src/ - -# Manually test symbolic link creation -ln -s ../../../arch/src/main/scala/framework docs/bb-note/src/arch/src/main/scala/framework -``` - -### Q5: API request timeout - -**Causes**: -- Slow LLM API response -- Too many files in directory, long analysis time -- Network connection issues - -**Solutions**: -```bash -# Increase request timeout -curl -X POST http://localhost:8080/doc/generate \ - --max-time 300 \ - -H "Content-Type: application/json" \ - -d '{ - "target_path": "arch/src/main/scala/framework", - "mode": "create" - }' - -# Process large directories in batches -# Do not process arch/src/main/scala directly, but process its subdirectories -``` - -## Performance Optimization Recommendations - -### 1. Batch Processing Optimization -```bash -# Use parallel processing (use cautiously, avoid API limits) -parallel -j 2 curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d '{\"target_path\": \"{}\", \"mode\": \"create\"}' \ - ::: arch/src/main/scala/framework arch/src/main/scala/builtin -``` - -### 2. Incremental Update Strategy -```bash -# Only update recently modified directories -find arch/src/main/scala -type d -mtime -7 | while read dir; do - if [[ -f "$dir/README.md" ]]; then - curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d "{\"target_path\": \"$dir\", \"mode\": \"update\"}" - fi -done -``` - -### 3. Monitoring and Logging -```bash -# Monitor API response time -time curl -X POST http://localhost:8080/doc/generate \ - -H "Content-Type: application/json" \ - -d '{ - "target_path": "arch/src/main/scala/framework", - "mode": "create" - }' - -# View detailed logs -tail -f logs/doc-agent.log | grep -E "(ERROR|WARN|Generation complete)" -``` - -## Configuration Guide - -### Environment Variables - -| Variable Name | Description | Default Value | -|--------|------|--------| -| `DOC_AGENT_PORT` | API service port | 8080 | -| `LLM_API_KEY` | LLM API key | Required to set | -| `LLM_API_URL` | LLM API endpoint | Required to set | -| `DOC_OUTPUT_BASE` | Documentation output base path | `docs/bb-note/src` | -| `TEMPLATE_BASE_PATH` | Template file base path | `workflow/prompts/doc` | - -### Configuration File Example - -Create `.env` file: -```bash -# LLM API configuration -LLM_API_KEY=your_api_key_here -LLM_API_URL=https://api.openai.com/v1/chat/completions - -# Documentation system configuration -DOC_OUTPUT_BASE=docs/bb-note/src -TEMPLATE_BASE_PATH=workflow/prompts/doc - -# Performance configuration -MAX_CONCURRENT_REQUESTS=3 -REQUEST_TIMEOUT=300 -``` - -## Development and Debugging - -### Local Development Environment Setup - -```bash -# 1. Install dependencies -cd workflow -npm install - -# 2. Start Motia service -npm run dev - -# 3. Test API connection -curl http://localhost:8080/health -``` - -### Debug Mode - -```bash -# Enable verbose logging -export DEBUG=doc-agent:* -npm run dev - -# Test individual components -node -e " -const { loadTemplate } = require('./steps/doc-agent/template_loader'); -console.log(loadTemplate('rtl', 'arch/src/main/scala/test')); -" -``` - -## Version Information - -- **Current Version**: 1.0.0 -- **Motia Framework Version**: Compatible with v2.x -- **Supported Node.js Version**: >= 16.0.0 -- **Last Updated**: December 2024 - -## Support and Feedback - -If you encounter issues or need feature improvements, please: - -1. Check the troubleshooting section of this document -2. Review system log files -3. Create an Issue in the project repository -4. Contact the development team - ---- - -*This document is continuously maintained with system updates, please check regularly for the latest version.* diff --git a/workflow/steps/doc-agent/doc_integration_event_step.py b/workflow/steps/doc-agent/doc_integration_event_step.py deleted file mode 100644 index 65ccdc7e..00000000 --- a/workflow/steps/doc-agent/doc_integration_event_step.py +++ /dev/null @@ -1,122 +0,0 @@ -""" -Document integration event processing step -Responsible for handling symbolic link creation and SUMMARY.md updates for documentation -""" - -import sys -import os -from pathlib import Path - -# Add current directory to path for importing local modules -current_dir = Path(__file__).parent -sys.path.insert(0, str(current_dir)) - -from link_manager import LinkManager -from summary_manager import SummaryManager - -config = { - "type": "event", - "name": "doc_integration", - "description": "Handle documentation integration tasks", - "subscribes": ["doc.integrate"], - "emits": ["doc.integration.complete"], - "input": { - "type": "object", - "properties": { - "target_path": {"type": "string"}, - "output_path": {"type": "string"}, - "doc_type": {"type": "string"}, - "traceId": {"type": "string"}, - }, - }, - "flows": ["doc_agent"], -} - - -async def handler(input_data, context): - context.logger.info("doc-integration - Start processing", {"input": input_data}) - - target_path = input_data.get("target_path") - output_path = input_data.get("output_path") - doc_type = input_data.get("doc_type") - trace_id = input_data.get("traceId") - - try: - # 1. Initialize managers - link_manager = LinkManager() - summary_manager = SummaryManager() - - # 2. Create symbolic links - docs_path = None - try: - docs_path = link_manager.create_docs_structure(target_path) - link_manager.create_symbolic_link(output_path, docs_path) - context.logger.info( - "doc-integration - Symbolic link created", - {"source": output_path, "target": docs_path}, - ) - except Exception as e: - context.logger.warning( - "doc-integration - Symbolic link creation failed", - {"error": str(e), "source": output_path}, - ) - - # 3. Update SUMMARY.md - if docs_path: - try: - summary_path = "docs/bb-note/src/SUMMARY.md" - new_entry = summary_manager.generate_entry( - target_path, docs_path, doc_type - ) - success, message = summary_manager.update_summary( - summary_path, new_entry - ) - - if success: - context.logger.info( - "doc-integration - SUMMARY.md updated", - {"entry": new_entry["line"], "message": message}, - ) - else: - context.logger.info( - "doc-integration - SUMMARY.md update skipped", - {"message": message}, - ) - except Exception as e: - context.logger.warning( - "doc-integration - SUMMARY.md update failed", {"error": str(e)} - ) - - # 4. Send completion event - await context.emit( - { - "topic": "doc.integration.complete", - "data": { - "target_path": target_path, - "output_path": output_path, - "docs_path": docs_path, - "doc_type": doc_type, - "traceId": trace_id, - }, - } - ) - - context.logger.info( - "doc-integration processing complete", - {"target_path": target_path, "docs_path": docs_path, "traceId": trace_id}, - ) - - except Exception as e: - error_msg = f"doc-integration processing failed: {str(e)}" - context.logger.error(error_msg) - - await context.emit( - { - "topic": "doc.integration.error", - "data": { - "error": error_msg, - "target_path": target_path, - "traceId": trace_id, - }, - } - ) diff --git a/workflow/steps/doc-agent/doc_utils.py b/workflow/steps/doc-agent/doc_utils.py deleted file mode 100644 index e579db43..00000000 --- a/workflow/steps/doc-agent/doc_utils.py +++ /dev/null @@ -1,78 +0,0 @@ -""" -Documentation generation utility functions -""" - -import os -from pathlib import Path - - -def detect_doc_type(target_path): - """Automatically detect document type based on directory path""" - path_str = str(Path(target_path).resolve()).replace("\\", "/") - - if "arch/src/main/scala" in path_str: - return "rtl" - elif "bb-tests" in path_str: - if "/workloads/" in path_str or path_str.endswith("/workloads"): - return "workloads" - elif "/customext/" in path_str or path_str.endswith("/customext"): - return "customext" - elif "/sardine/" in path_str or path_str.endswith("/sardine"): - return "sardine" - elif "/uvbb/" in path_str or path_str.endswith("/uvbb"): - return "uvbb" - return "workloads" - elif "/scripts/" in path_str or path_str.endswith("/scripts"): - return "script" - elif "/sims/" in path_str or path_str.endswith("/sims"): - return "sim" - elif "/workflow/" in path_str or path_str.endswith("/workflow"): - return "workflow" - - return "script" - - -def load_prompt_template(doc_type, target_path): - """Load and process prompt template""" - template_path = f"workflow/prompts/doc/{doc_type}-doc.md" - - if not os.path.exists(template_path): - raise FileNotFoundError(f"Template file not found: {template_path}") - - with open(template_path, "r", encoding="utf-8") as f: - template = f.read() - - template = template.replace("[`目录相对路径`]", target_path) - template = template.replace("@[`目录相对路径`]", f"@{target_path}") - - return template - - -def prepare_update_mode_prompt(template, target_path, mode): - """Prepare prompt for update mode""" - if mode != "update": - return template - - existing_doc_path = os.path.join(target_path, "README.md") - if not os.path.exists(existing_doc_path): - return template - - with open(existing_doc_path, "r", encoding="utf-8") as f: - existing_content = f.read() - - update_instruction = f""" - -## Special Instructions for Update Mode - -You are updating existing documentation. Please note: -1. Carefully analyze existing documentation content, retain accurate and valuable information -2. Identify and update outdated, inaccurate or incomplete sections -3. Maintain overall document structure and style consistency -4. If existing content is accurate and complete, retain it - -Existing documentation content: -```markdown -{existing_content} -``` -""" - return template + update_instruction diff --git a/workflow/steps/doc-agent/link_manager.py b/workflow/steps/doc-agent/link_manager.py deleted file mode 100644 index c76a9440..00000000 --- a/workflow/steps/doc-agent/link_manager.py +++ /dev/null @@ -1,103 +0,0 @@ -""" -Symbolic link manager -Responsible for creating and validating symbolic links in the documentation directory structure -""" - -import os -import shutil -from pathlib import Path - - -class LinkManager: - """Symbolic link manager""" - - def __init__(self): - self.project_root = Path.cwd() - self.docs_base = self.project_root / "docs" / "bb-note" / "src" - - def create_docs_structure(self, target_path): - """Create corresponding documentation directory structure""" - docs_path = self._convert_to_docs_path(target_path) - docs_dir = Path(docs_path).parent - docs_dir.mkdir(parents=True, exist_ok=True) - return docs_path - - def _convert_to_docs_path(self, target_path): - """Convert code directory path to corresponding documentation directory path""" - target_path = Path(target_path).resolve() - - try: - relative_path = target_path.relative_to(self.project_root) - except ValueError: - relative_path = ( - Path(*target_path.parts[-3:]) - if len(target_path.parts) >= 3 - else target_path - ) - - docs_path = self.docs_base / relative_path / "README.md" - return str(docs_path) - - def create_symbolic_link(self, source_path, target_path): - """Create symbolic link""" - source = Path(source_path) - target = Path(target_path) - - if not source.exists(): - raise FileNotFoundError(f"Source file does not exist: {source_path}") - - target.parent.mkdir(parents=True, exist_ok=True) - - if target.exists() or target.is_symlink(): - target.unlink() - - try: - relative_source = os.path.relpath(source, target.parent) - target.symlink_to(relative_source) - return True - except Exception as e: - try: - shutil.copy2(source, target) - return True - except Exception as copy_error: - raise Exception( - f"Both creating symbolic link and copying file failed: {str(e)}, {str(copy_error)}" - ) - - def validate_links(self, docs_base_path=None): - """Validate symbolic links""" - if docs_base_path is None: - docs_base_path = self.docs_base - else: - docs_base_path = Path(docs_base_path) - - invalid_links = [] - valid_links = [] - - for link_path in docs_base_path.rglob("*"): - if link_path.is_symlink(): - try: - if link_path.exists(): - valid_links.append(str(link_path)) - else: - invalid_links.append( - { - "link": str(link_path), - "target": str(link_path.readlink()), - "error": "Target file does not exist", - } - ) - except Exception as e: - invalid_links.append( - { - "link": str(link_path), - "target": "Cannot read", - "error": str(e), - } - ) - - return { - "valid_links": valid_links, - "invalid_links": invalid_links, - "total_links": len(valid_links) + len(invalid_links), - } diff --git a/workflow/steps/doc-agent/summary_manager.py b/workflow/steps/doc-agent/summary_manager.py deleted file mode 100644 index eb495ccd..00000000 --- a/workflow/steps/doc-agent/summary_manager.py +++ /dev/null @@ -1,111 +0,0 @@ -""" -SUMMARY.md manager -Responsible for parsing and updating mdBook's SUMMARY.md file -""" - -import os -import re -from pathlib import Path - - -class SummaryManager: - """SUMMARY.md manager""" - - def __init__(self): - self.project_root = Path.cwd() - self.docs_base = self.project_root / "docs" / "bb-note" / "src" - - def parse_summary(self, summary_path): - """Parse SUMMARY.md file and return structured data""" - if not os.path.exists(summary_path): - return {"sections": [], "entries": [], "original_content": ""} - - with open(summary_path, "r", encoding="utf-8") as f: - content = f.read() - - lines = content.split("\n") - entries = [] - - for line in lines: - line = line.rstrip() - if line.strip().startswith("-"): - match = re.match(r"\s*-\s*\[([^\]]+)\]\(([^)]+)\)", line) - if match: - title, path = match.groups() - entries.append({"title": title, "path": path, "line": line}) - - return {"entries": entries, "original_content": content} - - def generate_entry(self, target_path, docs_path, doc_type): - """Generate SUMMARY.md entry for new documentation""" - docs_file = Path(docs_path) - - try: - relative_path = docs_file.relative_to(self.docs_base) - except ValueError: - relative_path = docs_file - - title = ( - Path(target_path).parts[-1] - if Path(target_path).parts - else "Unknown Document" - ) - indent_level = self._determine_indent_level(target_path, doc_type) - indent = "\t" * indent_level - - entry = f"{indent}- [{title}](./{relative_path})" - - return { - "title": title, - "path": f"./{relative_path}", - "line": entry, - "target_path": target_path, - "doc_type": doc_type, - } - - def _determine_indent_level(self, target_path, doc_type): - """Determine indent level based on directory path and document type""" - path_parts = Path(target_path).parts - base_level = 1 - - if doc_type == "rtl" and "scala" in path_parts: - scala_index = path_parts.index("scala") - base_level += len(path_parts) - scala_index - 1 - - return max(0, base_level) - - def update_summary(self, summary_path, new_entry): - """Update SUMMARY.md file, add new entry""" - summary_data = self.parse_summary(summary_path) - - # Check for duplicates - existing_paths = [entry["path"] for entry in summary_data["entries"]] - if new_entry["path"] in existing_paths: - return False, "Entry already exists" - - # Insert new entry - lines = summary_data["original_content"].split("\n") - new_lines = self._insert_entry(lines, new_entry) - - # Write back to file - new_content = "\n".join(new_lines) - with open(summary_path, "w", encoding="utf-8") as f: - f.write(new_content) - - return True, "SUMMARY.md updated" - - def _insert_entry(self, lines, new_entry): - """Insert new entry at appropriate position""" - new_lines = [] - inserted = False - - for line in lines: - new_lines.append(line) - if "contributors" in line.lower() and not inserted: - new_lines.insert(-1, new_entry["line"]) - inserted = True - - if not inserted: - new_lines.append(new_entry["line"]) - - return new_lines diff --git a/workflow/steps/firesim/.gitignore b/workflow/steps/firesim/.gitignore deleted file mode 100644 index 1e82fc7d..00000000 --- a/workflow/steps/firesim/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.yaml diff --git a/workflow/steps/firesim/01_buildbitstream_api_step.py b/workflow/steps/firesim/01_buildbitstream_api_step.py deleted file mode 100644 index 2c5fb9e9..00000000 --- a/workflow/steps/firesim/01_buildbitstream_api_step.py +++ /dev/null @@ -1,26 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Firesim Buildbitstream", - "description": "build bitstream", - "path": "/firesim/buildbitstream", - "method": "POST", - "emits": ["firesim.buildbitstream"], - "flows": ["firesim"], -} - - -async def handler(req, context): - body = req.get("body") or {} - await context.emit({"topic": "firesim.buildbitstream", "data": body}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/firesim/01_buildbitstream_event_step.py b/workflow/steps/firesim/01_buildbitstream_event_step.py deleted file mode 100644 index 380be083..00000000 --- a/workflow/steps/firesim/01_buildbitstream_event_step.py +++ /dev/null @@ -1,54 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "Firesim Buildbitstream", - "description": "build bitstream", - "subscribes": ["firesim.buildbitstream"], - "emits": [], - "flows": ["firesim"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - script_dir = f"{bbdir}/workflow/steps/firesim/scripts" - yaml_dir = f"{script_dir}/yaml" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"source {bbdir}/env.sh && firesim buildbitstream " - command += f" -a {yaml_dir}/config_hwdb.yaml" - command += f" -b {yaml_dir}/config_build.yaml" - command += f" -r {yaml_dir}/config_build_recipes.yaml" - command += f" -c {yaml_dir}/config_runtime.yaml" - result = stream_run_logger( - cmd=command, - logger=context.logger, - stdout_prefix="firesim buildbitstream", - stderr_prefix="firesim buildbitstream", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # ================================================================================== - - return diff --git a/workflow/steps/firesim/02_infrasetup_api_step.py b/workflow/steps/firesim/02_infrasetup_api_step.py deleted file mode 100644 index 32d3eba9..00000000 --- a/workflow/steps/firesim/02_infrasetup_api_step.py +++ /dev/null @@ -1,27 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Firesim Infrasetup", - "description": "infrasetup", - "path": "/firesim/infrasetup", - "method": "POST", - "emits": ["firesim.infrasetup"], - "flows": ["firesim"], -} - - -async def handler(req, context): - body = req.get("body") or {} - data = {"jobs": body.get("jobs", 16)} - await context.emit({"topic": "firesim.infrasetup", "data": data}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/firesim/02_infrasetup_event_step.py b/workflow/steps/firesim/02_infrasetup_event_step.py deleted file mode 100644 index ab0fc01e..00000000 --- a/workflow/steps/firesim/02_infrasetup_event_step.py +++ /dev/null @@ -1,56 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "Firesim Infrasetup", - "description": "infrasetup", - "subscribes": ["firesim.infrasetup"], - "emits": [], - "flows": ["firesim"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - script_dir = f"{bbdir}/workflow/steps/firesim/scripts" - yaml_dir = f"{script_dir}/yaml" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"source {bbdir}/env.sh && firesim infrasetup " - command += f" -a {yaml_dir}/config_hwdb.yaml" - command += f" -b {yaml_dir}/config_build.yaml" - command += f" -r {yaml_dir}/config_build_recipes.yaml" - command += f" -c {yaml_dir}/config_runtime.yaml" - result = stream_run_logger( - cmd=command, - logger=context.logger, - stdout_prefix="firesim infrasetup", - stderr_prefix="firesim infrasetup", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # Routing to verilog or finish workflow - # For run workflow, continue to verilog; for standalone clean, complete - # ================================================================================== - - return diff --git a/workflow/steps/firesim/03_runworkload_api_step.py b/workflow/steps/firesim/03_runworkload_api_step.py deleted file mode 100644 index be070512..00000000 --- a/workflow/steps/firesim/03_runworkload_api_step.py +++ /dev/null @@ -1,27 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Firesim Runworkload", - "description": "run workload", - "path": "/firesim/runworkload", - "method": "POST", - "emits": ["firesim.runworkload"], - "flows": ["firesim"], -} - - -async def handler(req, context): - body = req.get("body") or {} - data = {"jobs": body.get("jobs", 16)} - await context.emit({"topic": "firesim.runworkload", "data": data}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/firesim/03_runworkload_event_step.py b/workflow/steps/firesim/03_runworkload_event_step.py deleted file mode 100644 index 534e5c0a..00000000 --- a/workflow/steps/firesim/03_runworkload_event_step.py +++ /dev/null @@ -1,56 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "Firesim Runworkload", - "description": "run workload", - "subscribes": ["firesim.runworkload"], - "emits": [], - "flows": ["firesim"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - script_dir = f"{bbdir}/workflow/steps/firesim/scripts" - yaml_dir = f"{script_dir}/yaml" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"source {bbdir}/env.sh && firesim runworkload " - command += f" -a {yaml_dir}/config_hwdb.yaml" - command += f" -b {yaml_dir}/config_build.yaml" - command += f" -r {yaml_dir}/config_build_recipes.yaml" - command += f" -c {yaml_dir}/config_runtime.yaml" - result = stream_run_logger( - cmd=command, - logger=context.logger, - stdout_prefix="firesim runworkload", - stderr_prefix="firesim runworkload", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # Routing to verilog or finish workflow - # For run workflow, continue to verilog; for standalone clean, complete - # ================================================================================== - - return diff --git a/workflow/steps/firesim/README.md b/workflow/steps/firesim/README.md deleted file mode 100644 index e3cc4737..00000000 --- a/workflow/steps/firesim/README.md +++ /dev/null @@ -1,59 +0,0 @@ -# FireSim Workflow - -FireSim FPGA simulation workflow in Buckyball framework, providing FPGA-based hardware simulation environment. - -## API Usage - -### `buildbitstream` -**Endpoint**: `POST /firesim/buildbitstream` - -**Function**: Build FPGA bitstream file - -**Parameters**: No specific parameters - -**Example**: -```bash -bbdev firesim --buildbitstream -``` - -### `infrasetup` -**Endpoint**: `POST /firesim/infrasetup` - -**Function**: Setup FireSim infrastructure - -**Parameters**: No specific parameters - -**Example**: -```bash -bbdev firesim --infrasetup -``` - -### `runworkload` -**Endpoint**: `POST /firesim/runworkload` - -**Function**: Run workload on FireSim - -**Parameters**: No specific parameters - -**Example**: -```bash -bbdev firesim --runworkload -``` - -## Typical Workflow - -```bash -# 1. Build bitstream -bbdev firesim --buildbitstream - -# 2. Setup infrastructure -bbdev firesim --infrasetup - -# 3. Run workload -bbdev firesim --runworkload -``` - -## Notes - -- Bitstream build takes several hours -- infrasetup requires cloud computing resource configuration diff --git a/workflow/steps/firesim/scripts/makefrag/firesim/build.mk b/workflow/steps/firesim/scripts/makefrag/firesim/build.mk deleted file mode 100644 index 40450d4b..00000000 --- a/workflow/steps/firesim/scripts/makefrag/firesim/build.mk +++ /dev/null @@ -1,56 +0,0 @@ -# See LICENSE for license details. - -CHIPYARD_STAGING_DIR := $(chipyard_dir)/sims/firesim-staging - -# target scala directories to copy into midas. used by TARGET_COPY_TO_MIDAS_SCALA_DIRS -TARGET_COPY_TO_MIDAS_SCALA_DIRS := \ - $(addprefix $(chipyard_dir)/generators/firechip/,bridgeinterfaces goldengateimplementations) - -# this rule always is run, but may not update the timestamp of the targets (depending on what the Chipyard make does). -# if that is the case (Chipyard make doesn't update it's outputs), then downstream rules *should* be skipped. -# all other chipyard collateral is located in chipyard's generated sources area. -$(FIRRTL_FILE) $(ANNO_FILE) &: SHELL := /usr/bin/env bash # needed for running source in recipe -$(FIRRTL_FILE) $(ANNO_FILE) &: firesim_target_symlink_hook - @mkdir -p $(@D) - @mkdir -p $(TARGET_SBT_DIR)/target/generated-src/$(long_name) - source $(TARGET_SBT_DIR)/../env.sh - cd $(TARGET_SBT_DIR) && \ - pwd && \ - ${SBT} ";project $(TARGET_SBT_PROJECT); runMain chipyard.Generator \ - --target-dir $(TARGET_SBT_DIR)/target/generated-src/$(long_name) \ - --name $(long_name) \ - --top-module $(DESIGN_PACKAGE).$(DESIGN) \ - --legacy-configs $(TARGET_CONFIG_PACKAGE):$(TARGET_CONFIG) \ - --emit-legacy-sfc" - # Link to the generated files - ln -sf $(TARGET_SBT_DIR)/target/generated-src/$(long_name)/$(long_name).sfc.fir $(FIRRTL_FILE) - ln -sf $(TARGET_SBT_DIR)/target/generated-src/$(long_name)/$(long_name).anno.json $(ANNO_FILE) - # .d needed to run metasim CI tests - ln -sf $(TARGET_SBT_DIR)/target/generated-src/$(long_name)/$(long_name).d $(GENERATED_DIR)/$(long_name).d - -####################################### -# Setup Extra Verilator Compile Flags # -####################################### - -## default flags added for cva6 -CVA6_VERILATOR_FLAGS = \ - --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ - -Wno-fatal \ - -Wno-PINCONNECTEMPTY \ - -Wno-ASSIGNDLY \ - -Wno-DECLFILENAME \ - -Wno-UNUSED \ - -Wno-UNOPTFLAT \ - -Wno-BLKANDNBLK \ - -Wno-style \ - -Wall - -# normal flags used for midas builds (that are incompatible with cva6) -DEFAULT_MIDAS_VERILATOR_FLAGS = \ - --assert - -# AJG: this must be evaluated after verilog generation to work (hence the =) -EXTRA_VERILATOR_FLAGS = \ - $(shell if ! grep -iq "module.*cva6" $(simulator_verilog); then echo "$(DEFAULT_MIDAS_VERILATOR_FLAGS)"; else echo "$(CVA6_VERILATOR_FLAGS)"; fi) diff --git a/workflow/steps/firesim/scripts/makefrag/firesim/config.mk b/workflow/steps/firesim/scripts/makefrag/firesim/config.mk deleted file mode 100644 index 55571068..00000000 --- a/workflow/steps/firesim/scripts/makefrag/firesim/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# Custom configuration for Buckyball FireSim builds -# This file overrides the default TARGET_CONFIG_PACKAGE to use our custom configs - -# Only used in this projects makefrags -makefile_path := $(abspath $(lastword $(MAKEFILE_LIST))) -makefile_dir := $(patsubst %/,%,$(dir $(makefile_path))) -chipyard_dir := $(abspath $(makefile_dir)/../../../../../../arch/thirdparty/chipyard) - -# These point at the main class of the target's Chisel generator -DESIGN_PACKAGE ?= firechip.chip -DESIGN ?= FireSim - -# Override to use our custom config package -TARGET_CONFIG_PACKAGE ?= sims.firesim -TARGET_CONFIG ?= FireSimBuckyballToyConfig - -# These guide chisel elaboration of simulation components by MIDAS, -# including models and widgets. -PLATFORM_CONFIG_PACKAGE ?= firesim.firesim -PLATFORM_CONFIG ?= BaseF1Config - -# Override project for the target. -TARGET_SBT_PROJECT := buckyball - -# Point to our project directory -TARGET_SBT_DIR := $(abspath $(makefile_dir)/../../../../../../arch) -TARGET_SOURCE_DIRS := $(abspath $(makefile_dir)/../../../../../../arch/src/main/scala) - -# SBT launcher -SBT ?= java -jar $(chipyard_dir)/scripts/sbt-launch.jar $(SBT_OPTS) diff --git a/workflow/steps/firesim/scripts/makefrag/firesim/driver.mk b/workflow/steps/firesim/scripts/makefrag/firesim/driver.mk deleted file mode 100644 index 4042d838..00000000 --- a/workflow/steps/firesim/scripts/makefrag/firesim/driver.mk +++ /dev/null @@ -1,70 +0,0 @@ -# See LICENSE for license details. - -# DOC include start: Bridge Build System Changes -########################## -# Driver Sources & Flags # -########################## - -ifeq (,$(wildcard $(RISCV)/lib/libriscv.so)) -$(warning libriscv not found) -LRISCV= -else -LRISCV=-lriscv -endif - -firechip_lib_dir = $(chipyard_dir)/generators/firechip/chip/src/main/cc -firechip_bridgestubs_lib_dir = $(chipyard_dir)/generators/firechip/bridgestubs/src/main/cc -testchipip_csrc_dir = $(chipyard_dir)/generators/testchipip/src/main/resources/testchipip/csrc - -# DRIVER_H only used to update recipe pre-reqs (ok to track more files) - -# fesvr and related srcs -DRIVER_H += \ - $(shell find $(testchipip_csrc_dir) -name "*.h") \ - $(shell find $(firechip_bridgestubs_lib_dir)/fesvr -name "*.h") -DRIVER_CC += \ - $(testchipip_csrc_dir)/cospike_impl.cc \ - $(testchipip_csrc_dir)/testchip_tsi.cc \ - $(testchipip_csrc_dir)/testchip_dtm.cc \ - $(testchipip_csrc_dir)/testchip_htif.cc \ - $(firechip_bridgestubs_lib_dir)/fesvr/firesim_tsi.cc \ - $(firechip_bridgestubs_lib_dir)/fesvr/firesim_dtm.cc \ - $(RISCV)/lib/libfesvr.a -# Disable missing override warning for testchipip. -TARGET_CXX_FLAGS += \ - -isystem $(testchipip_csrc_dir) \ - -isystem $(RISCV)/include \ - -Wno-inconsistent-missing-override -TARGET_LD_FLAGS += \ - -L$(RISCV)/lib \ - -Wl,-rpath,$(RISCV)/lib \ - $(LRISCV) - -# top-level sources -DRIVER_CC += $(addprefix $(firechip_lib_dir)/firesim/, $(addsuffix .cc, firesim_top)) -TARGET_CXX_FLAGS += -I$(firechip_bridgestubs_lib_dir)/bridge/test - -# bridge sources -DRIVER_H += $(shell find $(firechip_bridgestubs_lib_dir) -name "*.h") -DRIVER_CC += \ - $(wildcard \ - $(addprefix \ - $(firechip_bridgestubs_lib_dir)/, \ - $(addsuffix .cc,bridges/* bridges/tracerv/* bridges/cospike/*) \ - ) \ - ) -TARGET_CXX_FLAGS += \ - -I$(firechip_bridgestubs_lib_dir) \ - -I$(firechip_bridgestubs_lib_dir)/bridge \ - -I$(firechip_bridgestubs_lib_dir)/bridge/tracerv \ - -I$(firechip_bridgestubs_lib_dir)/bridge/cospike -TARGET_LD_FLAGS += \ - -l:libdwarf.so -l:libelf.so \ - -lz \ - -# other -TARGET_CXX_FLAGS += \ - -I$(GENERATED_DIR) \ - -g - -# DOC include end: Bridge Build System Changes diff --git a/workflow/steps/firesim/scripts/makefrag/firesim/metasim.mk b/workflow/steps/firesim/scripts/makefrag/firesim/metasim.mk deleted file mode 100644 index 1e7c50a3..00000000 --- a/workflow/steps/firesim/scripts/makefrag/firesim/metasim.mk +++ /dev/null @@ -1,140 +0,0 @@ -# See LICENSE for license details. - -################################################################ -# SW RTL Simulation Args -- for MIDAS- & FPGA-level Simulation # -################################################################ -TIMEOUT_CYCLES = 100000000 - -NET_SLOT ?= 0 -NET_LINK_LATENCY ?= 6405 -NET_BW ?= 100 -NET_SHMEMPORTNAME ?= $(shell printf '%0100d' $(NET_SLOT)) -NET_LOOPBACK ?= +nic-loopback0 -NET_MACADDR ?= $(shell printf '00:00:00:00:00:%02x' $$(($(NET_SLOT)+2))) -nic_args = +shmemportname0=$(NET_SHMEMPORTNAME) +macaddr0=$(NET_MACADDR) \ - +niclog0=niclog$(NET_SLOT) +linklatency0=$(NET_LINK_LATENCY) \ - +netbw0=$(NET_BW) +netburst0=8 $(NET_LOOPBACK) -tracer_args = +tracefile=TRACEFILE -blkdev_args = +blkdev-in-mem0=128 +blkdev-log0=blkdev-log$(NET_SLOT) -autocounter_args = +autocounter-readrate=1000 +autocounter-filename-base=AUTOCOUNTERFILE -# Neglecting this +arg will make the simulator use the same step size as on the -# FPGA. This will make ML simulation more closely match results seen on the -# FPGA at the expense of dramatically increased target runtime -serial_args = +fesvr-step-size=128 -#serial_args = - -COMMON_SIM_ARGS := $(COMMON_SIM_ARGS) $(serial_args) $(nic_args) $(tracer_args) $(blkdev_args) $(autocounter_args) - -# Arguments used only at a particular simulation abstraction -MIDAS_LEVEL_SIM_ARGS ?= +max-cycles=$(TIMEOUT_CYCLES) -FPGA_LEVEL_SIM_ARGS ?= - -################################ -# Verilator/VCS/XSIM execution # -################################ - -verilator = $(GENERATED_DIR)/V$(DESIGN) -verilator_debug = $(GENERATED_DIR)/V$(DESIGN)-debug -verilator_args = -vcs = $(GENERATED_DIR)/$(DESIGN) -vcs_debug = $(GENERATED_DIR)/$(DESIGN)-debug -vcs_args = +vcs+initreg+0 +vcs+initmem+0 -xsim = $(GENERATED_DIR)/$(DESIGN)-$(PLATFORM) -xcelium = $(GENERATED_DIR)/X$(DESIGN) -sim_binary_basename := $(basename $(notdir $(SIM_BINARY))) - -run-verilator: $(verilator) - cd $(dir $<) && \ - $(verilator) +permissive $(verilator_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) -which_disasm := $(shell which spike-dasm 2> /dev/null) -ifneq ($(which_disasm),) - disasm := 3>&1 1>&2 2>&3 | $(which_disasm) $(DISASM_EXTENSION) > -endif - -# Some of the generated suites use specific plus args, that are prefixed with -# the binary name. These are captured with $($*_ARGS) -$(OUTPUT_DIR)/%.run: $(OUTPUT_DIR)/% $(EMUL) - cd $(dir $($(EMUL))) && \ - ./$(notdir $($(EMUL))) $< $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \ - 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] - -$(OUTPUT_DIR)/%.out: $(OUTPUT_DIR)/% $(EMUL) - cd $(dir $($(EMUL))) && \ - ./$(notdir $($(EMUL))) $< $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \ - $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] - -$(OUTPUT_DIR)/%.vpd: $(OUTPUT_DIR)/% $(EMUL)-debug - cd $(dir $($(EMUL)_debug)) && \ - ./$(notdir $($(EMUL)_debug)) $< +vcdplusfile=$@ $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \ - $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] - -$(OUTPUT_DIR)/%.fsdb: $(OUTPUT_DIR)/% $(EMUL)-debug - cd $(dir $($(EMUL)_debug)) && \ - ./$(notdir $($(EMUL)_debug)) $< +fsdbfile=$@ $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \ - $(disasm) $(patsubst %.fsdb,%.out,$@) && [ $$PIPESTATUS -eq 0 ] - -.PRECIOUS: $(OUTPUT_DIR)/%.fsdb $(OUTPUT_DIR)/%.vpd $(OUTPUT_DIR)/%.out $(OUTPUT_DIR)/%.run - -# TraceGen rules - -$(OUTPUT_DIR)/tracegen.out: $($(EMUL)) - mkdir -p $(OUTPUT_DIR) && \ - cd $(dir $($(EMUL))) && \ - ./$(notdir $($(EMUL))) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \ - 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] - -$(OUTPUT_DIR)/tracegen.result: $(OUTPUT_DIR)/tracegen.out $(AXE) - $(chipyard_dir)/scripts/check-tracegen.sh $< > $@ - -fsim-tracegen: $(OUTPUT_DIR)/tracegen.result - -.PHONY: fsim-tracegen diff --git a/workflow/steps/firesim/scripts/yaml/config_build.yaml b/workflow/steps/firesim/scripts/yaml/config_build.yaml deleted file mode 100644 index e6ee2d5c..00000000 --- a/workflow/steps/firesim/scripts/yaml/config_build.yaml +++ /dev/null @@ -1,44 +0,0 @@ -# Build-time build design / AGFI configuration for the FireSim Simulation Manager -# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params. - -# ------------------------------------------------------------ -# Attention! This is the example on the Local U280 Machine -# Remember to modify this file use in the same way of firesim -# ------------------------------------------------------------ - -# this refers to build farms defined in config_build_farm.yaml -build_farm: - base_recipe: build-farm-recipes/externally_provisioned.yaml - recipe_arg_overrides: - # REQUIRED: (replace this) default location of build directory on build host. - default_build_dir: /home/mio/Code/buckyball/arch/thirdparty/chipyard/sims/firesim/deploy/FIRESIM_BUILD_DIR - # REQUIRED: List of IP addresses (or "localhost"). Each can have an OPTIONAL - # argument, called "override_build_dir", specifying to override the default - # build directory. - # - # Ex: - # build_farm_hosts: - # # use localhost and don't override the default build dir - # - localhost - # # use other IP address (don't override default build dir) - # - "111.111.1.111" - # # use other IP address (override default build dir for this build host) - # - "222.222.2.222": - # override_build_dir: /scratch/specific-build-host-build-dir - build_farm_hosts: - - localhost - -builds_to_run: - # this section references builds defined in config_build_recipes.yaml - # if you add a build here, it will be built when you run buildbitstream - # - alveo_u280_firesim_GemminiBuckyballConfig_no_nic - - alveo_u280_firesim_BuckyballToyConfig_no_nic - -agfis_to_share: - # - midasexamples_gcd - -share_with_accounts: - # To share with a specific user: - somebodysname: 123456789012 - # To share publicly: - # public: public diff --git a/workflow/steps/firesim/scripts/yaml/config_build_recipes.yaml b/workflow/steps/firesim/scripts/yaml/config_build_recipes.yaml deleted file mode 100644 index 01d8afb4..00000000 --- a/workflow/steps/firesim/scripts/yaml/config_build_recipes.yaml +++ /dev/null @@ -1,64 +0,0 @@ -# Build-time build recipe configuration for the FireSim Simulation Manager -# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params. - -# this file contains sections that describe hardware designs that /can/ be built. -# edit config_build.yaml to actually "turn on" a config to be built when you run -# buildbitstream - -# ------------------------------------------------------------ -# Attention! This is the example on the Local U280 Machine -# Remember to modify this file use in the same way of firesim -# ------------------------------------------------------------ - -########### -# Schema: -########### -# : -# PLATFORM: -# TARGET_PROJECT: -# TARGET_PROJECT_MAKEFRAG: -# DESIGN: -# TARGET_CONFIG: -# PLATFORM_CONFIG: -# deploy_quintuplet: -# platform_config_args: -# fpga_frequency: -# build_strategy: -# post_build_hook: -# metasim_customruntimeconfig: -# bit_builder_recipe: -# # OPTIONAL: overrides for bit builder recipe -# # Arg structure should be identical to the args given -# # in the base_recipe. -# #bit_builder_arg_overrides: -# # : - -alveo_u280_firesim_GemminiBuckyballConfig_no_nic: - PLATFORM: xilinx_alveo_u280 - TARGET_PROJECT: firesim - TARGET_PROJECT_MAKEFRAG: ../makefrag/firesim - DESIGN: FireSim - TARGET_CONFIG: sims.firesim.FireSimGemminiBuckyballConfig - PLATFORM_CONFIG: BaseXilinxAlveoU280Config - deploy_quintuplet: null - platform_config_args: - fpga_frequency: 30 - build_strategy: TIMING - post_build_hook: null - metasim_customruntimeconfig: null - bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u280.yaml - -alveo_u280_firesim_BuckyballToyConfig_no_nic: - PLATFORM: xilinx_alveo_u280 - TARGET_PROJECT: firesim - TARGET_PROJECT_MAKEFRAG: ../makefrag/firesim - DESIGN: FireSim - TARGET_CONFIG: sims.firesim.FireSimBuckyballToyConfig - PLATFORM_CONFIG: BaseXilinxAlveoU280Config - deploy_quintuplet: null - platform_config_args: - fpga_frequency: 30 - build_strategy: TIMING - post_build_hook: null - metasim_customruntimeconfig: null - bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u280.yaml diff --git a/workflow/steps/firesim/scripts/yaml/config_hwdb.yaml b/workflow/steps/firesim/scripts/yaml/config_hwdb.yaml deleted file mode 100644 index 98b8155e..00000000 --- a/workflow/steps/firesim/scripts/yaml/config_hwdb.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# Hardware config database for FireSim Simulation Manager -# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params. - -# ------------------------------------------------------------ -# Attention! This is the example on the Local U280 Machine -# Remember to modify this file use in the same way of firesim -# ------------------------------------------------------------ - -# Hardware configs represent a combination of: -# - an agfi/bitstream_tar with the bitstream for an fpga -# - (optional) a deployquintuplet override -# - (optional) a deploy_makefrag_override -# - (optional) a custom_runtime_config - -# The HWDBs (and their AGFI's/bitstream_tar's) provided below are public and available to all users. - -# DOCREF START: Example HWDB Entry -midasexamples_gcd: - bitstream_tar: https://raw.githubusercontent.com/invalid/address.tar.gz - deploy_quintuplet_override: null - deploy_makefrag_override: null - custom_runtime_config: null -# DOCREF END: Example HWDB Entry - -# alveo_u280_firesim_GemminiBuckyballConfig_no_nic: -# bitstream_tar: file:///home/mio/Code/buckyball/arch/thirdparty/chipyard/sims/firesim/deploy/results-build/2025-09-24--17-27-06-alveo_u280_firesim_GemminiBuckyballConfig_no_nic/cl_xilinx_alveo_u280-firesim-FireSim-sims.firesim.FireSimGemminiBuckyballConfig-BaseXilinxAlveoU280Config/firesim.tar.gz -# deploy_quintuplet_override: null -# custom_runtime_config: null - -alveo_u280_firesim_GemminiBuckyballConfig_no_nic: - bitstream_tar: file:///home/mio/Code/buckyball/arch/thirdparty/chipyard/sims/firesim/deploy/results-build/2025-11-19--17-01-23-alveo_u280_firesim_GemminiBuckyballConfig_no_nic/cl_xilinx_alveo_u280-firesim-FireSim-sims.firesim.FireSimGemminiBuckyballConfig-BaseXilinxAlveoU280Config/firesim.tar.gz - deploy_quintuplet_override: null - custom_runtime_config: null - -# alveo_u280_firesim_BuckyballToyConfig_no_nic: -# bitstream_tar: file:///home/mio/Code/buckyball/arch/thirdparty/chipyard/sims/firesim/deploy/results-build/2025-09-29--19-18-46-alveo_u280_firesim_BuckyballToyConfig_no_nic/cl_xilinx_alveo_u280-firesim-FireSim-sims.firesim.FireSimBuckyballToyConfig-BaseXilinxAlveoU280Config/firesim.tar.gz -# deploy_quintuplet_override: null -# custom_runtime_config: null - -alveo_u280_firesim_BuckyballToyConfig_no_nic: - bitstream_tar: file:///home/mio/Code/buckyball/arch/thirdparty/chipyard/sims/firesim/deploy/results-build/2025-11-23--04-11-23-alveo_u280_firesim_BuckyballToyConfig_no_nic/cl_xilinx_alveo_u280-firesim-FireSim-sims.firesim.FireSimBuckyballToyConfig-BaseXilinxAlveoU280Config/firesim.tar.gz - deploy_quintuplet_override: null - custom_runtime_config: null diff --git a/workflow/steps/firesim/scripts/yaml/config_runtime.yaml b/workflow/steps/firesim/scripts/yaml/config_runtime.yaml deleted file mode 100644 index 490db5f9..00000000 --- a/workflow/steps/firesim/scripts/yaml/config_runtime.yaml +++ /dev/null @@ -1,110 +0,0 @@ -# Run-time configuration for the FireSim Simulation Manager -# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params. - -# ------------------------------------------------------------ -# Attention! This is the example on the Local U280 Machine -# Remember to modify this file use in the same way of firesim -# ------------------------------------------------------------ - -run_farm: - base_recipe: run-farm-recipes/externally_provisioned.yaml - recipe_arg_overrides: - # REQUIRED: default platform used for run farm hosts. this is a class specifying - # how to run simulations on a run farm host. - default_platform: XilinxAlveoU280InstanceDeployManager - - # REQUIRED: default directory where simulations are run out of on the run farm hosts - default_simulation_dir: /home/mio/Code/buckyball/arch/thirdparty/chipyard/sims/firesim/deploy/FIRESIM_RUNS_DIR - - # REQUIRED: default fpga db file that enumerates what fpgas are available on the machine (used by XilinxU* Deploy Managers) - default_fpga_db: /opt/firesim-db.json - - # REQUIRED: List of unique hostnames/IP addresses, each with their - # corresponding specification that describes the properties of the host. - # - # Ex: - # run_farm_hosts_to_use: - # # use localhost which is described by "four_fpgas_spec" below. - # - localhost: four_fpgas_spec - # # supply IP address, which points to a machine that is described - # # by "four_fpgas_spec" below. - # - "111.111.1.111": four_fpgas_spec - run_farm_hosts_to_use: - - localhost: one_fpgas_spec - -metasimulation: - metasimulation_enabled: false - # vcs or verilator. use vcs-debug or verilator-debug for waveform generation - metasimulation_host_simulator: verilator - # plusargs passed to the simulator for all metasimulations - metasimulation_only_plusargs: "+fesvr-step-size=128 +max-cycles=100000000" - # plusargs passed to the simulator ONLY FOR vcs metasimulations - metasimulation_only_vcs_plusargs: "+vcs+initreg+0 +vcs+initmem+0" - -# DOCREF START: target_config area -target_config: - topology: no_net_config - no_net_num_nodes: 1 - link_latency: 6405 - switching_latency: 10 - net_bandwidth: 200 - profile_interval: -1 - - # This references a section from config_hwdb.yaml for fpga-accelerated simulation - # or from config_build_recipes.yaml for metasimulation - # In homogeneous configurations, use this to set the hardware config deployed - # for all simulators - default_hw_config: alveo_u280_firesim_BuckyballToyConfig_no_nic - - # Advanced: Specify any extra plusargs you would like to provide when - # booting the simulator (in both FPGA-sim and metasim modes). This is - # a string, with the contents formatted as if you were passing the plusargs - # at command line, e.g. "+a=1 +b=2" - plusarg_passthrough: "" -# DOCREF END: target_config area - -tracing: - enable: no - - # Trace output formats. Only enabled if "enable" is set to "yes" above - # 0 = human readable; 1 = binary (compressed raw data); 2 = flamegraph (stack - # unwinding -> Flame Graph) - output_format: 0 - - # Trigger selector. - # 0 = no trigger; 1 = cycle count trigger; 2 = program counter trigger; 3 = - # instruction trigger - selector: 1 - start: 0 - end: -1 - -autocounter: - read_rate: 0 - -workload: - workload_name: interactive.json # br-base.json - terminate_on_completion: no - suffix_tag: null - -host_debug: - # When enabled (=yes), Zeros-out FPGA-attached DRAM before simulations - # begin (takes 2-5 minutes). - # In general, this is not required to produce deterministic simulations on - # target machines running linux. Enable if you observe simulation non-determinism. - zero_out_dram: no - # If disable_synth_asserts: no, simulation will print assertion message and - # terminate simulation if synthesized assertion fires. - # If disable_synth_asserts: yes, simulation ignores assertion firing and - # continues simulation. - disable_synth_asserts: no - -# DOCREF START: Synthesized Prints -synth_print: - # Start and end cycles for outputting synthesized prints. - # They are given in terms of the base clock and will be converted - # for each clock domain. - start: 0 - end: -1 - # When enabled (=yes), prefix print output with the target cycle at which the print was triggered - cycle_prefix: yes -# DOCREF END: Synthesized Prints diff --git a/workflow/steps/marshal/.gitignore b/workflow/steps/marshal/.gitignore deleted file mode 100644 index 0521c5fb..00000000 --- a/workflow/steps/marshal/.gitignore +++ /dev/null @@ -1 +0,0 @@ -!*.json diff --git a/workflow/steps/marshal/01_build_api_step.py b/workflow/steps/marshal/01_build_api_step.py deleted file mode 100644 index 4c0936cf..00000000 --- a/workflow/steps/marshal/01_build_api_step.py +++ /dev/null @@ -1,25 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Marshal Build", - "description": "build marshal", - "path": "/marshal/build", - "method": "POST", - "emits": ["marshal.build"], - "flows": ["marshal"], -} - - -async def handler(req, context): - body = req.get("body") or {} - await context.emit({"topic": "marshal.build", "data": body}) - # ================================================================================== - # Wait for result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/marshal/01_build_event_step.py b/workflow/steps/marshal/01_build_event_step.py deleted file mode 100644 index db79e396..00000000 --- a/workflow/steps/marshal/01_build_event_step.py +++ /dev/null @@ -1,70 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "Marshal Build", - "description": "build marshal", - "subscribes": ["marshal.build"], - "emits": [], - "flows": ["marshal"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - script_dir = f"{bbdir}/workflow/steps/marshal/scripts" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"source {bbdir}/env.sh && ./marshal -v build interactive.json && ./marshal -v install interactive.json" - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=script_dir, - stdout_prefix="marshal build", - stderr_prefix="marshal build", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # Routing to completion or error handling - # ================================================================================== - if result.returncode == 0: - await context.emit( - { - "topic": "marshal.complete", - "data": {**data, "task": "marshal", "result": success_result}, - } - ) - else: - await context.emit( - { - "topic": "marshal.error", - "data": { - **data, - "task": "marshal", - "result": failure_result, - "returncode": result.returncode, - }, - } - ) - - return diff --git a/workflow/steps/marshal/02_launch_api_step.py b/workflow/steps/marshal/02_launch_api_step.py deleted file mode 100644 index 422f47dd..00000000 --- a/workflow/steps/marshal/02_launch_api_step.py +++ /dev/null @@ -1,26 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Marshal Launch", - "description": "launch marshal", - "path": "/marshal/launch", - "method": "POST", - "emits": ["marshal.launch"], - "flows": ["marshal"], -} - - -async def handler(req, context): - body = req.get("body") or {} - await context.emit({"topic": "marshal.launch", "data": body}) - - # ================================================================================== - # Wait for result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/marshal/02_launch_event_step.py b/workflow/steps/marshal/02_launch_event_step.py deleted file mode 100644 index 69604449..00000000 --- a/workflow/steps/marshal/02_launch_event_step.py +++ /dev/null @@ -1,50 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "Marshal Launch", - "description": "launch marshal", - "subscribes": ["marshal.launch"], - "emits": [], - "flows": ["marshal"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - script_dir = f"{bbdir}/workflow/steps/marshal/scripts" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"source {bbdir}/env.sh && ./marshal -v launch interactive.json" - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=script_dir, - stdout_prefix="marshal launch", - stderr_prefix="marshal launch", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # Finish workflow - # ================================================================================== - return diff --git a/workflow/steps/marshal/README.md b/workflow/steps/marshal/README.md deleted file mode 100644 index f8d25a32..00000000 --- a/workflow/steps/marshal/README.md +++ /dev/null @@ -1,53 +0,0 @@ -# Marshal Workflow - -Marshal workflow in the Buckyball framework, used to build and launch the Marshal component. - -## API Usage Guide - -### `build` -**Endpoint**: `POST /marshal/build` - -**Function**: Build Marshal component - -**Parameters**: No specific parameters - -**Example**: -```bash -bbdev marshal --build -``` - -### `launch` -**Endpoint**: `POST /marshal/launch` - -**Function**: Launch Marshal service - -**Parameters**: No specific parameters - -**Example**: -```bash -bbdev marshal --launch -``` - -## Typical Workflow - -```bash -# 1. Build Marshal -bbdev marshal --build - -# 2. Launch Marshal service -bbdev marshal --launch -``` - -## Response Format - -All API calls return a unified format: -```json -{ - "status": 200, - "body": { - "success": true, - "processing": false, - "return_code": 0 - } -} -``` diff --git a/workflow/steps/marshal/scripts/interactive.json b/workflow/steps/marshal/scripts/interactive.json deleted file mode 100644 index 8bb19496..00000000 --- a/workflow/steps/marshal/scripts/interactive.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "name" : "interactive", - "workdir" : ".", - "base" : "br-base.json", - "overlay" : "../output/overlay", - "host-init" : "./interactive/host-init.sh", - "rootfs-size" : "16GiB", - "spike-args" : "--extension=gemmini" -} diff --git a/workflow/steps/marshal/scripts/interactive/host-init.sh b/workflow/steps/marshal/scripts/interactive/host-init.sh deleted file mode 100755 index 45fa3b22..00000000 --- a/workflow/steps/marshal/scripts/interactive/host-init.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/bash - -# This script will run on the host from the workload directory -# (e.g. workloads/example-fed) every time the workload is built. -# It is recommended to call into something like a makefile because -# this script may be called multiple times. - -BBDIR=$(git rev-parse --show-toplevel) - -cd $BBDIR && source env.sh - -echo "Building marshal workload" -bbdev workload --build - -mkdir -p $BBDIR/workflow/steps/marshal/output -rm -rf $BBDIR/workflow/steps/marshal/output/overlay -mkdir -p $BBDIR/workflow/steps/marshal/output/overlay/root - -# Copy workload binaries to /root directory -cp -r $BBDIR/bb-tests/output/workloads/src/* $BBDIR/workflow/steps/marshal/output/overlay/root/ diff --git a/workflow/steps/marshal/scripts/marshal b/workflow/steps/marshal/scripts/marshal deleted file mode 120000 index 6b68a668..00000000 --- a/workflow/steps/marshal/scripts/marshal +++ /dev/null @@ -1 +0,0 @@ -../../../../arch/thirdparty/chipyard/software/firemarshal/marshal \ No newline at end of file diff --git a/workflow/steps/marshal/scripts/marshal-config.yaml b/workflow/steps/marshal/scripts/marshal-config.yaml deleted file mode 100644 index 97b3664e..00000000 --- a/workflow/steps/marshal/scripts/marshal-config.yaml +++ /dev/null @@ -1,2 +0,0 @@ -firesim-dir: '../../../../arch/thirdparty/chipyard/sims/firesim' -# board-dir: '../../../../arch/thirdparty/chipyard/software/firemarshal/boards/prototype' diff --git a/workflow/steps/palladium/01_verilog_api_step.py b/workflow/steps/palladium/01_verilog_api_step.py deleted file mode 100644 index 975339f6..00000000 --- a/workflow/steps/palladium/01_verilog_api_step.py +++ /dev/null @@ -1,46 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - - -from utils.path import get_buckyball_path - - -config = { - "type": "api", - "name": "palladium Verilog", - "description": "generate verilog code", - "path": "/palladium/verilog", - "method": "POST", - "emits": ["palladium.verilog"], - "flows": ["palladium"], -} - - -async def handler(req, context): - bbdir = get_buckyball_path() - body = req.get("body") or {} - - # Get config name, must be provided - config_name = body.get("config") - if not config_name or config_name == "None": - return { - "status": "error", - "message": "Configuration name is required. Please specify --config_name parameter.", - "example": './bbdev palladium --verilog "--config_name sims.palladium.BuckyballToyP2EConfig"', - } - - data = { - "config": config_name, - "balltype": body.get("balltype"), - "output_dir": body.get("output_dir", f"{bbdir}/arch/build/"), - } - await context.emit({"topic": "palladium.verilog", "data": data}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/palladium/01_verilog_event_step.py b/workflow/steps/palladium/01_verilog_event_step.py deleted file mode 100644 index 125b3d2a..00000000 --- a/workflow/steps/palladium/01_verilog_event_step.py +++ /dev/null @@ -1,184 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make verilog", - "description": "generate verilog code", - "subscribes": ["palladium.verilog"], - "emits": ["palladium.build"], - "flows": ["palladium"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - # Use arch/build as the base directory for chipyard.Generator - base_build_dir = f"{data.get('output_dir', f'{bbdir}/arch/build')}/palladium" - # Output directory for final Verilog files - verilog_output_dir = f"{base_build_dir}/verilog" - arch_dir = f"{bbdir}/arch" - - # Get config name, must be provided - config_name = data.get("config") - if not config_name or config_name == "None": - context.logger.error("Configuration name is required but not provided") - success_result, failure_result = await check_result( - context, - 1, - continue_run=False, - extra_fields={ - "task": "validation", - "error": "Configuration name is required. Please specify --config_name parameter.", - "example": './bbdev palladium --verilog "--config_name sims.palladium.BuckyballToyP2EConfig"', - }, - ) - return failure_result - - context.logger.info(f"Using configuration: {config_name}") - - # ================================================================================== - # Step 1: Generate FIRRTL using chipyard.Generator - # ================================================================================== - context.logger.info("Step 1: Generating FIRRTL with chipyard.Generator...") - os.system(f"mkdir -p {verilog_output_dir}") - firrtl_command = ( - f"cd {arch_dir} && " - f"sbt -J-Xmx256G -J-Xss64M -J-XX:+UseG1GC -J-XX:MaxGCPauseMillis=1000 " - f'"runMain chipyard.Generator ' - f"-td {base_build_dir} " - f"-T palladium.fpga.VCU118FPGATestHarness " - f'-C {config_name}"' - ) - - result = stream_run_logger( - cmd=firrtl_command, - logger=context.logger, - cwd=arch_dir, - stdout_prefix="palladium firrtl", - stderr_prefix="palladium firrtl", - ) - - if result.returncode != 0: - context.logger.error(f"FIRRTL generation failed with code {result.returncode}") - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=False, - extra_fields={"task": "firrtl", "step": "generate"}, - ) - return failure_result - - # ================================================================================== - # Step 2: Convert FIRRTL to SystemVerilog using firtool - # ================================================================================== - context.logger.info("Step 2: Converting FIRRTL to SystemVerilog with firtool...") - - # Extract the simple class name from the full config name - # e.g., "sims.palladium.BuckyballToyP2EConfig" -> "BuckyballToyP2EConfig" - config_class_name = config_name.split(".")[-1] - - # Find the generated FIRRTL file (in base_build_dir, not verilog_output_dir) - fir_file = f"{base_build_dir}/palladium.fpga.{config_class_name}.fir" - if not os.path.exists(fir_file): - context.logger.error(f"FIRRTL file not found: {fir_file}") - context.logger.info(f"Looking for files in {base_build_dir}...") - # List files to help debug - if os.path.exists(base_build_dir): - files = os.listdir(base_build_dir) - context.logger.info(f"Files in build dir: {files}") - success_result, failure_result = await check_result( - context, - 1, - continue_run=False, - extra_fields={"task": "firrtl", "step": "file_check"}, - ) - return failure_result - - verilog_command = ( - f"firtool {fir_file} " - f"-o {verilog_output_dir} " - f"--split-verilog " - f"--disable-all-randomization " - f"--strip-debug-info " - f"--ignore-read-enable-mem " - f"--lowering-options=disallowLocalVariables " - f"--disable-annotation-unknown" - ) - - result = stream_run_logger( - cmd=verilog_command, - logger=context.logger, - cwd=arch_dir, - stdout_prefix="palladium verilog", - stderr_prefix="palladium verilog", - ) - - if result.returncode != 0: - context.logger.error(f"Verilog generation failed with code {result.returncode}") - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=False, - extra_fields={"task": "verilog", "step": "firtool"}, - ) - return failure_result - - # ================================================================================== - # Step 3: Verify and clean up - # ================================================================================== - # context.logger.info("Step 3: Verifying generated files...") - - # # Check if top-level Verilog was generated - # top_sv_dir = f"{verilog_output_dir}/VCU118FPGATestHarness.sv" - # top_sv_file = f"{top_sv_dir}/VCU118FPGATestHarness.sv" - - # if os.path.exists(top_sv_file): - # # Count generated files - # sv_files = [f for f in os.listdir(top_sv_dir) if f.endswith('.sv')] - # context.logger.info(f"Successfully generated {len(sv_files)} SystemVerilog files") - # context.logger.info(f"Top-level module: {top_sv_file}") - # else: - # context.logger.error(f"Top-level Verilog file not found: {top_sv_file}") - - # # Remove unwanted file - # topname_file = f"{arch_dir}/TestHarness.sv" - # if os.path.exists(topname_file): - # os.remove(topname_file) - # context.logger.info(f"Removed unwanted file: {topname_file}") - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=data.get("from_run_workflow", False), - extra_fields={ - "task": "verilog", - "output_dir": verilog_output_dir, - "top_module": "VCU118FPGATestHarness", - }, - ) - - # ================================================================================== - # Continue routing - # Routing to verilog or finish workflow - # For run workflow, continue to verilog; for standalone clean, complete - # ================================================================================== - if data.get("from_run_workflow"): - await context.emit( - {"topic": "palladium.build", "data": {**data, "task": "run"}} - ) - - return diff --git a/workflow/steps/sardine/01_run_api_step.py b/workflow/steps/sardine/01_run_api_step.py deleted file mode 100644 index ac1e6a9f..00000000 --- a/workflow/steps/sardine/01_run_api_step.py +++ /dev/null @@ -1,42 +0,0 @@ -import subprocess -import sys -import os -import asyncio -from utils.event_common import wait_for_result - -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path - -config = { - "type": "api", - "name": "running sardine", - "description": "running sardine", - "path": "/sardine/run", - "method": "POST", - "emits": ["sardine.run"], - "flows": ["sardine"], -} - - -async def handler(req, context): - bbdir = get_buckyball_path() - - body = req.get("body") or {} - - data = {"workload": body.get("workload", "")} - - sardine_dir = f"{bbdir}/bb-tests/sardine" - - await context.emit({"topic": "sardine.run", "data": data}) - - # ================================================================================== - # Wait for execution result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/sardine/01_run_event_step.py b/workflow/steps/sardine/01_run_event_step.py deleted file mode 100644 index 500de852..00000000 --- a/workflow/steps/sardine/01_run_event_step.py +++ /dev/null @@ -1,56 +0,0 @@ -from contextlib import redirect_stdout -import os -from re import T -import subprocess -import sys -import time - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "running sardine", - "description": "running sardine", - "subscribes": ["sardine.run"], - "emits": [], - "flows": ["sardine"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - - sardine_dir = f"{bbdir}/bb-tests/sardine" - - command = f"source {bbdir}/env.sh && python run_tests.py --allure -m \"({data.get('workload', '')})\"" - context.logger.info( - "Executing sardine command", {"command": command, "cwd": sardine_dir} - ) - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=sardine_dir, - executable="bash", - stdout_prefix="sardine run", - stderr_prefix="sardine run", - ) - - # ================================================================================== - # Return execution result - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # finish workflow - # ================================================================================== - return diff --git a/workflow/steps/sardine/README.md b/workflow/steps/sardine/README.md deleted file mode 100644 index 90a82f2a..00000000 --- a/workflow/steps/sardine/README.md +++ /dev/null @@ -1,34 +0,0 @@ -# Sardine Workflow - -Sardine workflow in the Buckyball framework for running Sardine-related tasks. - -## API Usage - -### `run` -**Endpoint**: `POST /sardine/run` - -**Function**: Run Sardine tasks - -**Parameters**: -- **`workload`** - Specify the workload to run - -**Example**: -```bash -# Run specified workload -bbdev sardine --run "--workload /path/to/workload" - -# Run default workload -bbdev sardine --run -``` - -**Response**: -```json -{ - "status": 200, - "body": { - "success": true, - "processing": false, - "return_code": 0 - } -} -``` diff --git a/workflow/steps/tools/README.md b/workflow/steps/tools/README.md deleted file mode 100644 index 9dd3d0ba..00000000 --- a/workflow/steps/tools/README.md +++ /dev/null @@ -1,435 +0,0 @@ -# Function Calling Tool Management System - -A modular and extensible Function Calling tool management framework for AI Agent interaction with external systems. - -## 📁 Directory Structure - -``` -tools/ -├── __init__.py # Module exports -├── base.py # Tool base class and context -├── registry.py # Tool registry and manager -├── file_tools.py # File operation tools -├── presets.py # Predefined tool sets -└── README.md # This document -``` - -## 🚀 Quick Start - -### 1. Using Predefined Tool Manager - -```python -from steps.tools import create_code_agent_manager - -# Create tool manager (file_tools already registered) -manager = create_code_agent_manager() - -# Get tool definitions (send to LLM) -tools_schema = manager.get_tools_schema() - -# Call LLM -response = llm.chat( - messages=messages, - tools=tools_schema # Pass in tool definitions -) - -# Execute tool calls returned by LLM -if response.tool_calls: - for tool_call in response.tool_calls: - result = manager.execute_tool( - tool_name=tool_call.function.name, - arguments=tool_call.function.arguments, - work_dir="/path/to/project", - logger=logger - ) -``` - -### 2. Custom Tools - -```python -from steps.tools import Tool, ToolManager -import json - -class RunCommandTool(Tool): - """Command execution tool""" - - def get_name(self) -> str: - return "run_command" - - def get_description(self) -> str: - return "Execute a shell command" - - def get_parameters(self) -> dict: - return { - "type": "object", - "properties": { - "command": {"type": "string", "description": "Command to execute"} - }, - "required": ["command"] - } - - def execute(self, arguments: dict, context) -> str: - import subprocess - cmd = arguments.get("command") - - try: - result = subprocess.run( - cmd, - shell=True, - capture_output=True, - text=True, - timeout=30 - ) - - return json.dumps({ - "stdout": result.stdout, - "stderr": result.stderr, - "returncode": result.returncode - }) - except Exception as e: - return json.dumps({"error": str(e)}) - -# Register custom tool -manager = ToolManager() -manager.register_tool(RunCommandTool()) -``` - -## 📚 Core Concepts - -### Tool (Base Class) - -All tools inherit from the `Tool` base class: - -```python -class MyTool(Tool): - def get_name(self) -> str: - """Tool name (unique identifier)""" - return "my_tool" - - def get_description(self) -> str: - """Tool description (tells AI what this tool does)""" - return "My custom tool" - - def get_parameters(self) -> dict: - """Parameter definition (JSON Schema format)""" - return { - "type": "object", - "properties": { - "param1": {"type": "string", "description": "Parameter 1"}, - "param2": {"type": "integer", "description": "Parameter 2"} - }, - "required": ["param1"] - } - - def execute(self, arguments: dict, context) -> str: - """ - Execute tool logic - - Args: - arguments: Parameters passed by AI - context: ToolContext object (contains work_dir, logger, etc.) - - Returns: - Execution result (string, can be JSON) - """ - # Implement tool logic - return json.dumps({"result": "success"}) -``` - -### ToolContext (Execution Context) - -Execution environment provided to tools: - -```python -context = ToolContext( - work_dir="/path/to/project", # Working directory - logger=logger, # Logger - extra_key="extra_value" # Custom extension fields -) - -# Use in tool -class MyTool(Tool): - def execute(self, arguments, context): - context.log_info("Starting execution") - work_dir = context.work_dir - custom = context.extra.get("extra_key") - # ... -``` - -### ToolRegistry (Tool Registry) - -Manage tool registration and lookup: - -```python -from steps.tools import ToolRegistry, ReadFileTool, WriteFileTool - -registry = ToolRegistry() -registry.register(ReadFileTool()) -registry.register(WriteFileTool()) - -# Get tool -tool = registry.get("read_file") - -# List all tools -tools = registry.list_tools() # ['read_file', 'write_file'] - -# Convert to OpenAI format -schema = registry.to_openai_format() -``` - -### ToolManager (Tool Manager) - -High-level wrapper providing more convenient interface: - -```python -from steps.tools import ToolManager - -manager = ToolManager() -manager.register_tools([ReadFileTool(), WriteFileTool()]) - -# Get tool definitions -schema = manager.get_tools_schema() - -# Execute tool -result = manager.execute_tool( - tool_name="read_file", - arguments={"path": "main.py"}, - work_dir="/project" -) - -# View execution log -log = manager.get_execution_log() -``` - -## 🛠️ Built-in Tools - -### File Operation Tools - -#### read_file -Read file content - -```json -{ - "name": "read_file", - "parameters": { - "path": "relative/path/to/file.txt" - } -} -``` - -#### write_file -Write file content (automatically creates directories) - -```json -{ - "name": "write_file", - "parameters": { - "path": "output/file.txt", - "content": "file content here" - } -} -``` - -#### list_files -List files in directory - -```json -{ - "name": "list_files", - "parameters": { - "path": "src" // Optional, defaults to current directory - } -} -``` - -## 🎨 Predefined Tool Sets - -```python -from steps.tools import get_preset, list_presets - -# View available tool sets -presets = list_presets() # ['file_tools', 'code_agent'] - -# Get tool set -tools = get_preset("file_tools") # Returns [ReadFileTool, WriteFileTool, ...] - -# Create manager -from steps.tools import create_code_agent_manager -manager = create_code_agent_manager() -``` - -## 📝 Complete Examples - -### Agent Integration Example - -```python -from steps.tools import create_code_agent_manager -import httpx -import json - -async def run_agent(prompt: str, work_dir: str): - # 1. Create tool manager - manager = create_code_agent_manager() - tools_schema = manager.get_tools_schema() - - # 2. Initialize conversation - messages = [ - {"role": "system", "content": "You are a code assistant"}, - {"role": "user", "content": prompt} - ] - - # 3. AI loop - max_iterations = 10 - for i in range(max_iterations): - # Call LLM - response = await call_llm(messages, tools_schema) - assistant_msg = response["choices"][0]["message"] - messages.append(assistant_msg) - - # Check for tool calls - if not assistant_msg.get("tool_calls"): - print(f"Done! Final response: {assistant_msg['content']}") - break - - # Execute all tool calls - for tool_call in assistant_msg["tool_calls"]: - result = manager.execute_tool( - tool_name=tool_call["function"]["name"], - arguments=tool_call["function"]["arguments"], - work_dir=work_dir - ) - - # Add tool result to conversation - messages.append({ - "role": "tool", - "tool_call_id": tool_call["id"], - "content": result - }) -``` - -## 🔒 Security Features - -### Path Security - -All file operation tools include path traversal checks: - -```python -# ✅ Allowed -read_file("src/main.py") - -# ❌ Denied (path traversal) -read_file("../../../etc/passwd") -``` - -### Error Handling - -Tool execution automatically catches exceptions: - -```python -# Internal exceptions are caught and returned as error messages -result = manager.execute_tool("read_file", {"path": "nonexist.txt"}) -# Returns: {"error": "File not found: nonexist.txt"} -``` - -## 🧪 Testing - -Create test file: - -```python -# test_tools.py -from steps.tools import create_code_agent_manager -import tempfile -import os - -def test_file_tools(): - manager = create_code_agent_manager() - - with tempfile.TemporaryDirectory() as tmpdir: - # Test write_file - result = manager.execute_tool( - "write_file", - {"path": "test.txt", "content": "hello"}, - work_dir=tmpdir - ) - assert "success" in result - - # Test read_file - result = manager.execute_tool( - "read_file", - {"path": "test.txt"}, - work_dir=tmpdir - ) - assert result == "hello" - - print("✅ Test passed") - -if __name__ == "__main__": - test_file_tools() -``` - -## 📦 Extending Tools - -### Adding New Tool Categories - -Create new file `network_tools.py`: - -```python -from .base import Tool -import json -import httpx - -class HttpGetTool(Tool): - def get_name(self) -> str: - return "http_get" - - def get_description(self) -> str: - return "Make HTTP GET request" - - def get_parameters(self) -> dict: - return { - "type": "object", - "properties": { - "url": {"type": "string"} - }, - "required": ["url"] - } - - def execute(self, arguments, context): - url = arguments["url"] - response = httpx.get(url) - return json.dumps({ - "status": response.status_code, - "body": response.text[:1000] - }) -``` - -Then add to `presets.py`: - -```python -def create_network_tools(): - from .network_tools import HttpGetTool - return [HttpGetTool()] -``` - -## 🎯 Best Practices - -1. **Tool Naming**: Use clear verb+noun format (`read_file`, `list_users`) -2. **Parameter Descriptions**: Describe each parameter in detail to help AI use them correctly -3. **Error Handling**: Return JSON format error messages with `error` field -4. **Logging**: Use `context.log_info/log_error` to record key operations -5. **Security Checks**: Validate input parameters, prevent path traversal and other security issues -6. **Result Format**: Return JSON strings or plain text, maintain consistency - -## 🤝 Contributing - -Steps to add new tools: - -1. Inherit from `Tool` base class -2. Implement 4 abstract methods -3. Add to appropriate tool set in `presets.py` -4. Export in `__init__.py` -5. Update README documentation - -## 📄 License - -Same as main project diff --git a/workflow/steps/tools/__init__.py b/workflow/steps/tools/__init__.py deleted file mode 100644 index 6de3040c..00000000 --- a/workflow/steps/tools/__init__.py +++ /dev/null @@ -1,84 +0,0 @@ -""" -Function Calling Tool Management Module - -This module provides a complete Function Calling tool management system, including: -- Tool base class definitions -- Tool registration and management -- Predefined tool sets -- Tool execution context - -Usage example: - -```python -from tools import create_code_agent_manager - -# Create tool manager -manager = create_code_agent_manager() - -# Get tool definitions (to send to LLM) -tools_schema = manager.get_tools_schema() - -# Execute tool call -result = manager.execute_tool( - tool_name="read_file", - arguments={"path": "main.py"}, - work_dir="/path/to/project", - logger=logger -) -``` -""" - -from .base import Tool, ToolContext -from .registry import ToolRegistry, ToolManager -from .file_tools import ( - ReadFileTool, - WriteFileTool, - ListFilesTool, - MakeDirTool, - DeleteFileTool, - GetPathTool, - GrepFilesTool, -) -from .workflow_tools import WorkflowAPITool -from .deepwiki_tools import DeepwikiAskTool, DeepwikiReadWikiTool -from .agent_tools import CallAgentTool -from .presets import ( - create_file_tools, - create_code_agent_tools, - create_default_manager, - create_code_agent_manager, - get_preset, - list_presets, -) - -__all__ = [ - # Base classes - "Tool", - "ToolContext", - # Registration and management - "ToolRegistry", - "ToolManager", - # File operation tools - "ReadFileTool", - "WriteFileTool", - "ListFilesTool", - "MakeDirTool", - "DeleteFileTool", - "GetPathTool", - "GrepFilesTool", - # Agent coordination - "CallAgentTool", - # API tools - "WorkflowAPITool", - "DeepwikiAskTool", - "DeepwikiReadWikiTool", - # Predefined tool sets - "create_file_tools", - "create_code_agent_tools", - "create_default_manager", - "create_code_agent_manager", - "get_preset", - "list_presets", -] - -__version__ = "1.0.0" diff --git a/workflow/steps/tools/agent_tools.py b/workflow/steps/tools/agent_tools.py deleted file mode 100644 index 623377aa..00000000 --- a/workflow/steps/tools/agent_tools.py +++ /dev/null @@ -1,129 +0,0 @@ -"""Agent coordination tools""" - -import httpx -import uuid -from typing import Dict, Any -from .base import Tool - - -class CallAgentTool(Tool): - """Tool for calling other agents""" - - def get_name(self) -> str: - return "call_agent" - - def get_description(self) -> str: - return """Call another agent (spec_agent, code_agent, review_agent, verify_agent) with a task. - Use this to delegate work to specialized agents. - Returns the agent's response and generated files.""" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "agent_role": { - "type": "string", - "enum": ["spec", "code", "review", "verify"], - "description": "Which agent to call (spec/code/review/verify)", - }, - "task_description": { - "type": "string", - "description": "Task description or instructions for the agent", - }, - "context_files": { - "type": "array", - "items": {"type": "string"}, - "description": "Optional: List of file paths the agent should read for context", - }, - "model": { - "type": "string", - "description": "Optional: LLM model to use (will inherit from parent if not specified)", - }, - }, - "required": ["agent_role", "task_description"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - agent_role = arguments.get("agent_role") - task_description = arguments.get("task_description") - context_files = arguments.get("context_files", []) - # Prefer model from parameters, otherwise inherit from context - model = arguments.get("model") or context.extra.get("model") - - # Generate temporary task file - import os - import tempfile - - # Create temporary task file - task_content = task_description - - # Add context file references if specified - if context_files: - task_content += "\n\n## Context Files\n" - for filepath in context_files: - task_content += f"- {filepath}\n" - - # Write to temporary file - temp_dir = os.path.join(context.work_dir, ".agent_tasks") - os.makedirs(temp_dir, exist_ok=True) - - task_id = str(uuid.uuid4())[:8] - task_file = os.path.join(temp_dir, f"task_{agent_role}_{task_id}.md") - - with open(task_file, "w", encoding="utf-8") as f: - f.write(task_content) - - context.log_info(f"Created task file: {task_file}") - context.log_info(f"Calling {agent_role}_agent with task") - - try: - # Get workflow API address (from environment or use defaults) - import os - - workflow_host = os.getenv("WORKFLOW_HOST", "localhost") - workflow_port = os.getenv("WORKFLOW_PORT", "3001") - base_url = f"http://{workflow_host}:{workflow_port}" - url = f"{base_url}/agent" - - context.log_info(f"Calling workflow API at: {url}") - - payload = { - "agentRole": agent_role, - "promptPath": task_file, - "workDir": context.work_dir, - } - - # Add model to payload if specified - if model: - payload["model"] = model - context.log_info(f"Using model: {model}") - - response = httpx.post(url, json=payload, timeout=600.0) - - if response.status_code == 200: - result = response.json() - - # Clean up temporary file - try: - os.remove(task_file) - except Exception: - pass - - return str( - { - "status": "success", - "agent": agent_role, - "result": result, - "files": result.get("files", []), - } - ) - else: - return str( - { - "error": f"Agent call failed with status {response.status_code}", - "response": response.text[:500], - } - ) - - except Exception as e: - return str({"error": f"Failed to call agent: {str(e)}"}) diff --git a/workflow/steps/tools/base.py b/workflow/steps/tools/base.py deleted file mode 100644 index 7b91d9ed..00000000 --- a/workflow/steps/tools/base.py +++ /dev/null @@ -1,114 +0,0 @@ -"""Function Calling tool base classes""" - -from abc import ABC, abstractmethod -from typing import Dict, Any, Optional -import json - - -class Tool(ABC): - """Tool base class""" - - def __init__(self): - self.name = self.get_name() - self.description = self.get_description() - self.parameters = self.get_parameters() - - @abstractmethod - def get_name(self) -> str: - """Return tool name""" - pass - - @abstractmethod - def get_description(self) -> str: - """Return tool description""" - pass - - @abstractmethod - def get_parameters(self) -> Dict[str, Any]: - """Return tool parameter definition (JSON Schema)""" - pass - - @abstractmethod - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - """ - Execute tool - - Args: - arguments: Tool parameters - context: Execution context (contains logger, work_dir, etc.) - - Returns: - Execution result (string format) - """ - pass - - def to_openai_format(self) -> Dict[str, Any]: - """Convert to OpenAI Function Calling format""" - return { - "type": "function", - "function": { - "name": self.name, - "description": self.description, - "parameters": self.parameters, - }, - } - - def safe_execute(self, arguments: Any, context: Any) -> str: - """ - Safely execute tool (with error handling) - - Args: - arguments: Tool parameters (can be string or dict) - context: Execution context - - Returns: - Execution result or error message - """ - try: - # Parse arguments - if isinstance(arguments, str): - args = json.loads(arguments) - else: - args = arguments - - # Execute tool - result = self.execute(args, context) - return result - - except json.JSONDecodeError as e: - error = f"Invalid JSON arguments: {str(e)}" - if hasattr(context, "logger"): - context.logger.error(f"Tool {self.name} - {error}") - return json.dumps({"error": error}) - - except Exception as e: - error = f"Tool execution failed: {str(e)}" - if hasattr(context, "logger"): - context.logger.error(f"Tool {self.name} - {error}") - return json.dumps({"error": error}) - - def __repr__(self) -> str: - return f"Tool({self.name})" - - -class ToolContext: - """Tool execution context""" - - def __init__(self, work_dir: str, logger: Any = None, **kwargs): - self.work_dir = work_dir - self.logger = logger - self.extra = kwargs - - def log_info(self, message: str): - """Log info message""" - if self.logger: - self.logger.info(message) - else: - print(f"[INFO] {message}") - - def log_error(self, message: str): - """Log error message""" - if self.logger: - self.logger.error(message) - else: - print(f"[ERROR] {message}") diff --git a/workflow/steps/tools/deepwiki_tools.py b/workflow/steps/tools/deepwiki_tools.py deleted file mode 100644 index 214cdbda..00000000 --- a/workflow/steps/tools/deepwiki_tools.py +++ /dev/null @@ -1,327 +0,0 @@ -"""Deepwiki tool wrapper - via MCP Streamable HTTP""" - -import httpx -import json -import uuid -from httpx_sse import connect_sse -from typing import Dict, Any -from .base import Tool - - -class DeepwikiAskTool(Tool): - """Deepwiki Q&A tool - via MCP""" - - def get_name(self) -> str: - return "deepwiki_ask" - - def get_description(self) -> str: - return """Ask questions about a GitHub repository using Deepwiki. - Use this to understand code, architecture, and implementation details.""" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "repo": { - "type": "string", - "description": ( - "GitHub repository in format 'owner/repo' " - "(e.g., 'DangoSys/buckyball', 'ucb-bar/gemmini')" - ), - }, - "question": { - "type": "string", - "description": "Question to ask about the repository", - }, - }, - "required": ["repo", "question"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - repo = arguments.get("repo") - question = arguments.get("question") - - try: - context.log_info( - f"Asking Deepwiki via MCP HTTP: {question[:100]}... (repo: {repo})" - ) - - # MCP tool call request (JSON-RPC 2.0) - request_payload = { - "jsonrpc": "2.0", - "id": 1, - "method": "tools/call", - "params": { - "name": "ask_question", - "arguments": {"repoName": repo, "question": question}, - }, - } - - # Use Streamable HTTP endpoint - mcp_url = "https://mcp.deepwiki.com/mcp" - - context.log_info(f"MCP URL: {mcp_url}") - - with httpx.Client(timeout=120.0) as client: - # Step 1: Initialize session (without sessionId) - init_payload = { - "jsonrpc": "2.0", - "id": 0, - "method": "initialize", - "params": { - "protocolVersion": "2024-11-05", - "capabilities": {}, - "clientInfo": { - "name": "buckyball-workflow", - "version": "1.0.0", - }, - }, - } - - context.log_info("Initializing MCP session (without sessionId)...") - - session_id = None - # Use POST request directly, get sessionId from response headers - init_resp = client.post( - mcp_url, - json=init_payload, - headers={ - "Content-Type": "application/json", - "Accept": "application/json, text/event-stream", - }, - ) - - # Get sessionId from response headers - session_id = init_resp.headers.get("mcp-session-id") - if not session_id: - context.log_error(f"Init response status: {init_resp.status_code}") - context.log_error( - f"Init response headers: {dict(init_resp.headers)}" - ) - return "Error: No session ID in init response headers" - - context.log_info(f"Session initialized, ID: {session_id}") - - # Step 2: Call tool (with sessionId) - use SSE streaming - context.log_info( - f"Calling tool: {json.dumps(request_payload, ensure_ascii=False)[:300]}" - ) - - # Use stream instead of connect_sse - with client.stream( - "POST", - mcp_url, - json=request_payload, - headers={ - "Content-Type": "application/json", - "Accept": "application/json, text/event-stream", - "Mcp-Session-Id": session_id, - }, - ) as tool_resp: - context.log_info(f"Tool response status: {tool_resp.status_code}") - - # Manually parse SSE stream - for line in tool_resp.iter_lines(): - if line.startswith("data: "): - # Remove "data: " prefix - data_str = line[6:] - - # Skip heartbeat - if data_str.strip() == "ping": - continue - - try: - result = json.loads(data_str) - context.log_info( - f"Tool response: {json.dumps(result, ensure_ascii=False)[:500]}" - ) - - # Handle JSON-RPC 2.0 response - if "error" in result: - error = result["error"] - error_msg = f"MCP Error: {error.get('message', 'Unknown error')}" - context.log_error(error_msg) - return error_msg - - if "result" in result: - content = result["result"].get("content", []) - if content and len(content) > 0: - answer = content[0].get("text", "") - context.log_info( - f"Deepwiki answer length: {len(answer)} chars" - ) - context.log_info( - f"Deepwiki answer preview: {answer[:200]}..." - ) - - # Limit return length - if len(answer) > 3000: - answer = answer[:3000] + "\n... (truncated)" - return answer - except json.JSONDecodeError as e: - context.log_error( - f"Failed to parse SSE data: {e}, line: {line[:100]}" - ) - continue - - return "No valid response from Deepwiki" - - except Exception as e: - error_msg = f"Error calling Deepwiki MCP: {str(e)}" - context.log_error(error_msg) - return error_msg - - -class DeepwikiReadWikiTool(Tool): - """Read Deepwiki wiki content - via MCP""" - - def get_name(self) -> str: - return "deepwiki_read_wiki" - - def get_description(self) -> str: - return """Read wiki documentation for a GitHub repository from Deepwiki. - Use this to get structured documentation about the repository.""" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "repo": { - "type": "string", - "description": "GitHub repository in format 'owner/repo'", - } - }, - "required": ["repo"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - repo = arguments.get("repo") - - try: - context.log_info(f"Reading Deepwiki wiki via MCP HTTP for: {repo}") - - # MCP tool call request - request_payload = { - "jsonrpc": "2.0", - "id": 2, - "method": "tools/call", - "params": { - "name": "read_wiki_contents", - "arguments": {"repoName": repo}, - }, - } - - # Use Streamable HTTP endpoint - mcp_url = "https://mcp.deepwiki.com/mcp" - - context.log_info(f"MCP URL: {mcp_url}") - - with httpx.Client(timeout=120.0) as client: - # Step 1: Initialize session (without sessionId) - init_payload = { - "jsonrpc": "2.0", - "id": 0, - "method": "initialize", - "params": { - "protocolVersion": "2024-11-05", - "capabilities": {}, - "clientInfo": { - "name": "buckyball-workflow", - "version": "1.0.0", - }, - }, - } - - context.log_info("Initializing MCP session (without sessionId)...") - - session_id = None - # Use POST request directly, get sessionId from response headers - init_resp = client.post( - mcp_url, - json=init_payload, - headers={ - "Content-Type": "application/json", - "Accept": "application/json, text/event-stream", - }, - ) - - # Get sessionId from response headers - session_id = init_resp.headers.get("mcp-session-id") - if not session_id: - context.log_error(f"Init response status: {init_resp.status_code}") - context.log_error( - f"Init response headers: {dict(init_resp.headers)}" - ) - return "Error: No session ID in init response headers" - - context.log_info(f"Session initialized, ID: {session_id}") - - # Step 2: Call tool (with sessionId) - use SSE streaming - context.log_info( - f"Calling tool: {json.dumps(request_payload, ensure_ascii=False)}" - ) - - # Use stream instead of connect_sse - with client.stream( - "POST", - mcp_url, - json=request_payload, - headers={ - "Content-Type": "application/json", - "Accept": "application/json, text/event-stream", - "Mcp-Session-Id": session_id, - }, - ) as tool_resp: - context.log_info(f"Tool response status: {tool_resp.status_code}") - - # Manually parse SSE stream - for line in tool_resp.iter_lines(): - if line.startswith("data: "): - # Remove "data: " prefix - data_str = line[6:] - - # Skip heartbeat - if data_str.strip() == "ping": - continue - - try: - result = json.loads(data_str) - context.log_info( - f"Tool response: {json.dumps(result, ensure_ascii=False)[:500]}" - ) - - # Handle JSON-RPC 2.0 response - if "error" in result: - error = result["error"] - error_msg = f"MCP Error: {error.get('message', 'Unknown error')}" - context.log_error(error_msg) - return error_msg - - if "result" in result: - content = result["result"].get("content", []) - if content and len(content) > 0: - wiki_text = content[0].get("text", "") - context.log_info( - f"Deepwiki wiki length: {len(wiki_text)} chars" - ) - context.log_info( - f"Deepwiki wiki preview: {wiki_text[:200]}..." - ) - - if len(wiki_text) > 5000: - wiki_text = ( - wiki_text[:5000] + "\n... (truncated)" - ) - return wiki_text - except json.JSONDecodeError as e: - context.log_error( - f"Failed to parse SSE data: {e}, line: {line[:100]}" - ) - continue - - return "No valid wiki content from Deepwiki" - - except Exception as e: - error_msg = f"Error reading Deepwiki wiki via MCP: {str(e)}" - context.log_error(error_msg) - return error_msg diff --git a/workflow/steps/tools/file_tools.py b/workflow/steps/tools/file_tools.py deleted file mode 100644 index cec4ca8c..00000000 --- a/workflow/steps/tools/file_tools.py +++ /dev/null @@ -1,359 +0,0 @@ -"""File operation related tools""" - -import os -import json -import shutil -from typing import Dict, Any -from .base import Tool - - -class MakeDirTool(Tool): - """Create directory tool""" - - def get_name(self) -> str: - return "make_dir" - - def get_description(self) -> str: - return "Create a new directory (supports creating parent directories)" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "path": {"type": "string", "description": "Directory path to create"} - }, - "required": ["path"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - path = arguments.get("path") - - if not os.path.isabs(path): - path = os.path.join(context.work_dir, path) - - try: - if os.path.exists(path): - return json.dumps({"status": "exists", "path": path}) - - os.makedirs(path, exist_ok=True) - context.log_info(f"Created directory: {path}") - return json.dumps({"status": "success", "path": path}) - - except Exception as e: - return json.dumps({"error": f"Failed to create directory: {str(e)}"}) - - -class GetPathTool(Tool): - """Get path information tool""" - - def get_name(self) -> str: - return "get_path_info" - - def get_description(self) -> str: - return "Get absolute path and check if path exists" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "path": { - "type": "string", - "description": "Path to check (optional, defaults to work_dir)", - } - }, - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - path = arguments.get("path", ".") - - if not os.path.isabs(path): - path = os.path.join(context.work_dir, path) - - abs_path = os.path.abspath(path) - exists = os.path.exists(abs_path) - - info = { - "absolute_path": abs_path, - "exists": exists, - "work_dir": context.work_dir, - } - - if exists: - info["is_file"] = os.path.isfile(abs_path) - info["is_dir"] = os.path.isdir(abs_path) - - return json.dumps(info, indent=2) - - -class GrepFilesTool(Tool): - """Search file content tool""" - - def get_name(self) -> str: - return "grep_files" - - def get_description(self) -> str: - return "Search for text pattern in files" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "pattern": {"type": "string", "description": "Text pattern to search"}, - "path": {"type": "string", "description": "Directory or file path"}, - "file_ext": { - "type": "string", - "description": "File extension filter (e.g., '.scala')", - }, - }, - "required": ["pattern", "path"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - pattern = arguments.get("pattern") - path = arguments.get("path") - file_ext = arguments.get("file_ext") - - if not os.path.isabs(path): - path = os.path.join(context.work_dir, path) - - try: - results = [] - files_to_search = [] - - if os.path.isfile(path): - files_to_search = [path] - else: - for root, _, files in os.walk(path): - for file in files: - if file_ext and not file.endswith(file_ext): - continue - files_to_search.append(os.path.join(root, file)) - - # Limit file count - for filepath in files_to_search[:100]: - try: - with open(filepath, "r", encoding="utf-8", errors="ignore") as f: - for line_num, line in enumerate(f, 1): - if pattern in line: - results.append( - { - "file": filepath, - "line": line_num, - "content": line.strip()[:150], - } - ) - # Limit result count - if len(results) >= 50: - break - except Exception: - continue - - if len(results) >= 50: - break - - return json.dumps({"matches": len(results), "results": results}, indent=2) - - except Exception as e: - return json.dumps({"error": f"Search failed: {str(e)}"}) - - -class DeleteFileTool(Tool): - """Delete file tool""" - - def get_name(self) -> str: - return "delete_file" - - def get_description(self) -> str: - return "Delete a file (use with caution)" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "path": {"type": "string", "description": "Path to file to delete"} - }, - "required": ["path"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - path = arguments.get("path") - - if not os.path.isabs(path): - path = os.path.join(context.work_dir, path) - - try: - if not os.path.exists(path): - return json.dumps({"status": "not_found", "path": path}) - - if os.path.isfile(path): - os.remove(path) - context.log_info(f"Deleted file: {path}") - return json.dumps({"status": "success", "path": path}) - else: - return json.dumps({"error": "Path is a directory, not a file"}) - - except Exception as e: - return json.dumps({"error": f"Failed to delete: {str(e)}"}) - - -class ReadFileTool(Tool): - """Read file content""" - - def get_name(self) -> str: - return "read_file" - - def get_description(self) -> str: - return "Read the content of a file" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "path": { - "type": "string", - "description": "File path relative to work directory", - } - }, - "required": ["path"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - file_path = arguments.get("path") - - if not file_path: - return json.dumps({"error": "Missing required parameter: path"}) - - full_path = os.path.join(context.work_dir, file_path) - - # Security check: prevent path traversal - abs_full = os.path.abspath(full_path) - abs_work = os.path.abspath(context.work_dir) - if not abs_full.startswith(abs_work): - return json.dumps({"error": "Access denied: path outside work directory"}) - - if not os.path.exists(full_path): - return json.dumps({"error": f"File not found: {file_path}"}) - - if not os.path.isfile(full_path): - return json.dumps({"error": f"Not a file: {file_path}"}) - - try: - with open(full_path, "r", encoding="utf-8") as f: - content = f.read() - - context.log_info(f"Tool: read_file({file_path}) - {len(content)} chars") - return content - - except UnicodeDecodeError: - return json.dumps( - {"error": "Cannot read file: not a text file or encoding issue"} - ) - - -class WriteFileTool(Tool): - """Write file content""" - - def get_name(self) -> str: - return "write_file" - - def get_description(self) -> str: - return "Write content to a file (creates directories if needed)" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "path": { - "type": "string", - "description": "File path relative to work directory", - }, - "content": { - "type": "string", - "description": "Content to write to the file", - }, - }, - "required": ["path", "content"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - file_path = arguments.get("path") - content = arguments.get("content") - - if not file_path: - return json.dumps({"error": "Missing required parameter: path"}) - - if content is None: - return json.dumps({"error": "Missing required parameter: content"}) - - full_path = os.path.join(context.work_dir, file_path) - - # Security check: prevent path traversal - abs_full = os.path.abspath(full_path) - abs_work = os.path.abspath(context.work_dir) - if not abs_full.startswith(abs_work): - return json.dumps({"error": "Access denied: path outside work directory"}) - - try: - # Create directory - dir_path = os.path.dirname(full_path) - if dir_path: - os.makedirs(dir_path, exist_ok=True) - - # Write file - with open(full_path, "w", encoding="utf-8") as f: - f.write(content) - - context.log_info(f"Tool: write_file({file_path}) - {len(content)} chars") - - return json.dumps( - {"success": True, "path": file_path, "size": len(content)} - ) - - except Exception as e: - return json.dumps({"error": f"Failed to write file: {str(e)}"}) - - -class ListFilesTool(Tool): - """List files in directory""" - - def get_name(self) -> str: - return "list_files" - - def get_description(self) -> str: - return "List files in a directory" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "path": { - "type": "string", - "description": "Directory path relative to work directory (default: .)", - } - }, - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - dir_path = arguments.get("path", ".") - full_path = os.path.join(context.work_dir, dir_path) - - # Security check - abs_full = os.path.abspath(full_path) - abs_work = os.path.abspath(context.work_dir) - if not abs_full.startswith(abs_work): - return json.dumps({"error": "Access denied: path outside work directory"}) - - if not os.path.exists(full_path): - return json.dumps({"error": f"Directory not found: {dir_path}"}) - - if not os.path.isdir(full_path): - return json.dumps({"error": f"Not a directory: {dir_path}"}) - - try: - files = os.listdir(full_path) - context.log_info(f"Tool: list_files({dir_path}) - {len(files)} items") - - return json.dumps({"path": dir_path, "files": files, "count": len(files)}) - - except Exception as e: - return json.dumps({"error": f"Failed to list directory: {str(e)}"}) diff --git a/workflow/steps/tools/presets.py b/workflow/steps/tools/presets.py deleted file mode 100644 index 8db2aff0..00000000 --- a/workflow/steps/tools/presets.py +++ /dev/null @@ -1,106 +0,0 @@ -"""Predefined tool sets""" - -from typing import List -from .base import Tool -from .file_tools import ( - ReadFileTool, - WriteFileTool, - ListFilesTool, - MakeDirTool, - DeleteFileTool, - GetPathTool, - GrepFilesTool, -) -from .workflow_tools import WorkflowAPITool -from .deepwiki_tools import DeepwikiAskTool, DeepwikiReadWikiTool -from .agent_tools import CallAgentTool -from .registry import ToolManager - - -def create_file_tools() -> List[Tool]: - """Create file operation tool set""" - return [ - ReadFileTool(), - WriteFileTool(), - ListFilesTool(), - MakeDirTool(), - DeleteFileTool(), - GetPathTool(), - GrepFilesTool(), - ] - - -def create_code_agent_tools() -> List[Tool]: - """Create Code Agent tool set (includes all required tools)""" - return [ - # File operations - ReadFileTool(), - WriteFileTool(), - ListFilesTool(), - MakeDirTool(), - DeleteFileTool(), - GetPathTool(), - GrepFilesTool(), - # Agent coordination - CallAgentTool(), - # Workflow API - WorkflowAPITool(), - # Deepwiki - DeepwikiAskTool(), - DeepwikiReadWikiTool(), - ] - - -def create_default_manager() -> ToolManager: - """Create default tool manager""" - manager = ToolManager() - manager.register_tools(create_file_tools()) - return manager - - -def create_code_agent_manager() -> ToolManager: - """Create Code Agent dedicated tool manager""" - manager = ToolManager() - manager.register_tools(create_code_agent_tools()) - return manager - - -# Predefined tool set configurations -PRESET_CONFIGS = { - "file_tools": { - "name": "File Operations", - "description": "Basic file system operations", - "tools": create_file_tools, - }, - "code_agent": { - "name": "Code Agent", - "description": "Tools for code generation and manipulation", - "tools": create_code_agent_tools, - }, -} - - -def get_preset(name: str) -> List[Tool]: - """ - Get predefined tool set - - Args: - name: Tool set name ("file_tools", "code_agent") - - Returns: - Tool list - - Raises: - ValueError: If tool set does not exist - """ - config = PRESET_CONFIGS.get(name) - if not config: - available = ", ".join(PRESET_CONFIGS.keys()) - raise ValueError(f"Unknown preset: {name}. Available: {available}") - - return config["tools"]() - - -def list_presets() -> List[str]: - """List all available predefined tool sets""" - return list(PRESET_CONFIGS.keys()) diff --git a/workflow/steps/tools/registry.py b/workflow/steps/tools/registry.py deleted file mode 100644 index 13922466..00000000 --- a/workflow/steps/tools/registry.py +++ /dev/null @@ -1,131 +0,0 @@ -"""Function Calling tool registry""" - -from typing import Dict, List, Any, Optional -from .base import Tool, ToolContext - - -class ToolRegistry: - """Tool registration and management""" - - def __init__(self): - self._tools: Dict[str, Tool] = {} - - def register(self, tool: Tool): - """Register a tool""" - self._tools[tool.name] = tool - - def register_all(self, tools: List[Tool]): - """Batch register tools""" - for tool in tools: - self.register(tool) - - def get(self, name: str) -> Optional[Tool]: - """Get tool""" - return self._tools.get(name) - - def list_tools(self) -> List[str]: - """List all tool names""" - return list(self._tools.keys()) - - def to_openai_format(self) -> List[Dict[str, Any]]: - """Convert to OpenAI Function Calling format""" - return [tool.to_openai_format() for tool in self._tools.values()] - - def execute(self, tool_name: str, arguments: Any, context: ToolContext) -> str: - """ - Execute tool - - Args: - tool_name: Tool name - arguments: Tool parameters - context: Execution context - - Returns: - Execution result - """ - tool = self.get(tool_name) - - if not tool: - return f'{{"error": "Unknown tool: {tool_name}"}}' - - return tool.safe_execute(arguments, context) - - def __len__(self) -> int: - return len(self._tools) - - def __repr__(self) -> str: - return f"ToolRegistry({len(self)} tools: {', '.join(self.list_tools())})" - - -class ToolManager: - """Tool manager (high-level wrapper)""" - - def __init__(self, registry: Optional[ToolRegistry] = None): - self.registry = registry or ToolRegistry() - self._execution_log: List[Dict[str, Any]] = [] - - def register_tool(self, tool: Tool): - """Register tool""" - self.registry.register(tool) - - def register_tools(self, tools: List[Tool]): - """Batch register tools""" - self.registry.register_all(tools) - - def get_tools_schema(self) -> List[Dict[str, Any]]: - """Get tool definitions (OpenAI format)""" - return self.registry.to_openai_format() - - def execute_tool( - self, - tool_name: str, - arguments: Any, - work_dir: str, - logger: Any = None, - **kwargs, - ) -> str: - """ - Execute tool call - - Args: - tool_name: Tool name - arguments: Tool parameters - work_dir: Working directory - logger: Logger - **kwargs: Other context parameters - - Returns: - Execution result - """ - # Create context - context = ToolContext(work_dir=work_dir, logger=logger, **kwargs) - - # Execute tool - result = self.registry.execute(tool_name, arguments, context) - - # Log execution - self._execution_log.append( - { - "tool": tool_name, - "arguments": arguments, - # Truncate long results - "result": result[:200] if len(result) > 200 else result, - } - ) - - return result - - def get_execution_log(self) -> List[Dict[str, Any]]: - """Get execution log""" - return self._execution_log - - def clear_log(self): - """Clear execution log""" - self._execution_log.clear() - - def get_tool_names(self) -> List[str]: - """Get all tool names""" - return self.registry.list_tools() - - def __repr__(self) -> str: - return f"ToolManager({len(self.registry)} tools registered)" diff --git a/workflow/steps/tools/workflow_tools.py b/workflow/steps/tools/workflow_tools.py deleted file mode 100644 index ab17e891..00000000 --- a/workflow/steps/tools/workflow_tools.py +++ /dev/null @@ -1,71 +0,0 @@ -"""Workflow internal API call tools""" - -import httpx -import asyncio -from typing import Dict, Any -from .base import Tool - - -class WorkflowAPITool(Tool): - """Generic tool for calling Workflow internal APIs""" - - def get_name(self) -> str: - return "call_workflow_api" - - def get_description(self) -> str: - return """Call internal workflow API endpoints. - Available endpoints: - - /verilator/verilog: Generate Verilog - - /verilator/build: Build verilator (params: jobs) - - /verilator/sim: Run simulation (params: binary, batch) - - /workload/build: Build workload (params: args) - - /sardine/run: Run sardine tests (params: workload)""" - - def get_parameters(self) -> Dict[str, Any]: - return { - "type": "object", - "properties": { - "endpoint": { - "type": "string", - "description": "API endpoint path (e.g., '/verilator/build')", - }, - "params": { - "type": "object", - "description": "Request parameters as JSON object", - "additionalProperties": True, - }, - }, - "required": ["endpoint"], - } - - def execute(self, arguments: Dict[str, Any], context: Any) -> str: - endpoint = arguments.get("endpoint") - params = arguments.get("params", {}) - - # Get workflow API address - import os - - workflow_host = os.getenv("WORKFLOW_HOST", "localhost") - workflow_port = os.getenv("WORKFLOW_PORT", "3001") - base_url = f"http://{workflow_host}:{workflow_port}" - url = f"{base_url}{endpoint}" - - try: - context.log_info(f"Calling workflow API: {url}") - context.log_info(f"Parameters: {params}") - - # Synchronous call (using httpx sync client) - response = httpx.post(url, json=params, timeout=300.0) - - if response.status_code == 200: - return str(response.json()) - else: - return str( - { - "error": f"API call failed with status {response.status_code}", - "response": response.text[:500], - } - ) - - except Exception as e: - return str({"error": f"Workflow API call failed: {str(e)}"}) diff --git a/workflow/steps/uvm/01_builddut_api_step.py b/workflow/steps/uvm/01_builddut_api_step.py deleted file mode 100644 index 596f78bd..00000000 --- a/workflow/steps/uvm/01_builddut_api_step.py +++ /dev/null @@ -1,27 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "UVM Build DUT", - "description": "build dut", - "path": "/uvm/builddut", - "method": "POST", - "emits": ["uvm.builddut"], - "flows": ["uvm"], -} - - -async def handler(req, context): - body = req.get("body") or {} - data = {"jobs": body.get("jobs", 16)} - await context.emit({"topic": "uvm.builddut", "data": data}) - - # ================================================================================== - # Wait for build result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/uvm/01_builddut_event_step.py b/workflow/steps/uvm/01_builddut_event_step.py deleted file mode 100644 index 59678fd4..00000000 --- a/workflow/steps/uvm/01_builddut_event_step.py +++ /dev/null @@ -1,61 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "UVM Build DUT", - "description": "build dut", - "subscribes": ["uvm.builddut"], - "emits": [], - "flows": ["uvm"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - build_dir = f"{bbdir}/bb-tests/uvbb/dut/build" - dut_dir = f"{bbdir}/bb-tests/uvbb/dut" - arch_dir = f"{bbdir}/arch" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"cd {arch_dir} && mill -i __.uvbb.runMain uvbb.Elaborate " - command += "--disable-annotation-unknown -strip-debug-info -O=debug " - command += f"--split-verilog -o={build_dir}" - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=bbdir, - stdout_prefix="uvm build dut", - stderr_prefix="uvm build dut", - ) - - # Remove unwanted file - topname_file = f"{arch_dir}/BallTop.sv" - if os.path.exists(topname_file): - os.remove(topname_file) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # Continue routing - # Routing to verilog or finish workflow - # For run workflow, continue to verilog; for standalone clean, complete - # ================================================================================== - - return diff --git a/workflow/steps/uvm/03_build_api_step.py b/workflow/steps/uvm/03_build_api_step.py deleted file mode 100644 index e5fb39f7..00000000 --- a/workflow/steps/uvm/03_build_api_step.py +++ /dev/null @@ -1,27 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "UVM Build", - "description": "build uvm executable", - "path": "/uvm/build", - "method": "POST", - "emits": ["uvm.build"], - "flows": ["uvm"], -} - - -async def handler(req, context): - body = req.get("body") or {} - data = {"jobs": body.get("jobs", 16)} - await context.emit({"topic": "uvm.build", "data": data}) - - # ================================================================================== - # Wait for build result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/uvm/03_build_event_step.py b/workflow/steps/uvm/03_build_event_step.py deleted file mode 100644 index 51311692..00000000 --- a/workflow/steps/uvm/03_build_event_step.py +++ /dev/null @@ -1,109 +0,0 @@ -import os -import subprocess -import glob -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make build", - "description": "build verilator executable", - "subscribes": ["uvm.build"], - "emits": [], - "flows": ["uvm"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - arch_dir = f"{bbdir}/arch" - dut_dir = f"{bbdir}/bb-tests/uvbb/dut" - build_dir = f"{bbdir}/bb-tests/uvbb/dut/build" - waveform_dir = f"{arch_dir}/waveform" - log_dir = f"{arch_dir}/log" - - # ================================================================================== - # Execute operation - # ================================================================================== - # Find sources - vsrcs = glob.glob(f"{build_dir}/**/*.v", recursive=True) + glob.glob( - f"{build_dir}/**/*.sv", recursive=True - ) - csrcs = ( - glob.glob(f"{dut_dir}/src/main/csrc/**/*.c", recursive=True) - + glob.glob(f"{dut_dir}/src/main/csrc/**/*.cc", recursive=True) - + glob.glob(f"{dut_dir}/src/main/csrc/**/*.cpp", recursive=True) - + glob.glob(f"{build_dir}/**/*.c", recursive=True) - + glob.glob(f"{build_dir}/**/*.cc", recursive=True) - + glob.glob(f"{build_dir}/**/*.cpp", recursive=True) - ) - - # Setup paths - inc_paths = [ - os.environ.get("RISCV", "") + "/include" if os.environ.get("RISCV") else "", - f"{arch_dir}/thirdparty/chipyard/tools/DRAMSim2", - build_dir, - f"{dut_dir}/src/main/csrc/include", - ] - inc_flags = " ".join([f"-I{p}" for p in inc_paths if p]) - - topname = "BallTop" - - cflags = f"{inc_flags} -DTOP_NAME='\"V{topname}\"' -std=c++17 " - ldflags = ( - f"-lreadline -ldramsim -lfesvr " - f"-L{arch_dir}/thirdparty/chipyard/tools/DRAMSim2 " - f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build " - f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build/lib" - ) - - obj_dir = f"{build_dir}/obj_dir" - subprocess.run(f"rm -rf {obj_dir}", shell=True) - os.makedirs(obj_dir, exist_ok=True) - - sources = " ".join(vsrcs + csrcs) - jobs = data.get("jobs", "") - - verilator_cmd = ( - f"verilator -MMD --build -cc --trace -O3 --x-assign fast --x-initial fast --noassert -Wno-fatal " - f"--timing -j {jobs} +incdir+{build_dir} --top {topname} {sources} " - f"-CFLAGS '{cflags}' -LDFLAGS '{ldflags}' --Mdir {obj_dir} --exe" - ) - - result = stream_run_logger( - cmd=verilator_cmd, - logger=context.logger, - cwd=bbdir, - stdout_prefix="uvm build", - stderr_prefix="uvm build", - ) - result = stream_run_logger( - cmd=f"make -C {obj_dir} -f V{topname}.mk {obj_dir}/V{topname}", - logger=context.logger, - cwd=bbdir, - stdout_prefix="verilator build", - stderr_prefix="verilator build", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, result.returncode, continue_run=data.get("from_run_workflow", False) - ) - - # ================================================================================== - # Continue routing - # Routing to verilog or finish workflow - # For run workflow, continue to verilog; for standalone clean, complete - # ================================================================================== - - return diff --git a/workflow/steps/uvm/README.md b/workflow/steps/uvm/README.md deleted file mode 100644 index 79ec5c50..00000000 --- a/workflow/steps/uvm/README.md +++ /dev/null @@ -1,61 +0,0 @@ -# UVM Workflow - -UVM (Universal Verification Methodology) workflow in the Buckyball framework for building and running UVM verification environments. - -## API Usage - -### `builddut` -**Endpoint**: `POST /uvm/builddut` - -**Function**: Build DUT (Design Under Test) - -**Parameters**: -- **`jobs`** - Number of parallel build tasks, default 16 - -**Example**: -```bash -# Build DUT with default parallelism -bbdev uvm --builddut - -# Specify number of parallel tasks -bbdev uvm --builddut "--jobs 8" -``` - -### `build` -**Endpoint**: `POST /uvm/build` - -**Function**: Build UVM executable - -**Parameters**: -- **`jobs`** - Number of parallel build tasks, default 16 - -**Example**: -```bash -# Build UVM with default parallelism -bbdev uvm --build - -# Specify number of parallel tasks -bbdev uvm --build "--jobs 8" -``` - -## Typical Workflow - -```bash -# 1. Build DUT -bbdev uvm --builddut - -# 2. Build UVM environment -bbdev uvm --build -``` - -**Response Format**: -```json -{ - "status": 200, - "body": { - "success": true, - "processing": false, - "return_code": 0 - } -} -``` diff --git a/workflow/steps/verilator/01_clean_api_step.py b/workflow/steps/verilator/01_clean_api_step.py deleted file mode 100644 index b447792c..00000000 --- a/workflow/steps/verilator/01_clean_api_step.py +++ /dev/null @@ -1,26 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Verilator Clean", - "description": "clean build directory", - "path": "/verilator/clean", - "method": "POST", - "emits": ["verilator.clean"], - "flows": ["verilator"], -} - - -async def handler(req, context): - body = req.get("body") or {} - await context.emit({"topic": "verilator.clean", "data": {**body, "task": "clean"}}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/verilator/01_clean_event_step.py b/workflow/steps/verilator/01_clean_event_step.py deleted file mode 100644 index 626eba3e..00000000 --- a/workflow/steps/verilator/01_clean_event_step.py +++ /dev/null @@ -1,57 +0,0 @@ -import subprocess -import os -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make clean", - "description": "clean build directory", - "subscribes": ["verilator.run", "verilator.clean"], - "emits": ["verilator.verilog"], - "flows": ["verilator"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - build_dir = f"{bbdir}/arch/build" - # ================================================================================== - # Execute operation - # ================================================================================== - command = f"rm -rf {build_dir}" - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=bbdir, - stdout_prefix="verilator clean", - stderr_prefix="verilator clean", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=data.get("from_run_workflow", False), - extra_fields={"task": "clean"}, - ) - - # ================================================================================== - # Continue routing - # ================================================================================== - if data.get("from_run_workflow"): - await context.emit( - {"topic": "verilator.verilog", "data": {**data, "task": "run"}} - ) - - return diff --git a/workflow/steps/verilator/02_verilog_api_step.py b/workflow/steps/verilator/02_verilog_api_step.py deleted file mode 100644 index 5f900423..00000000 --- a/workflow/steps/verilator/02_verilog_api_step.py +++ /dev/null @@ -1,46 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - - -from utils.path import get_buckyball_path - - -config = { - "type": "api", - "name": "Verilator Verilog", - "description": "generate verilog code", - "path": "/verilator/verilog", - "method": "POST", - "emits": ["verilator.verilog"], - "flows": ["verilator"], -} - - -async def handler(req, context): - bbdir = get_buckyball_path() - body = req.get("body") or {} - - # Get config name, must be provided - config_name = body.get("config") - if not config_name or config_name == "None": - return { - "status": "error", - "message": "Configuration name is required. Please specify --config parameter.", - "example": 'bbdev verilator --verilog "--config sims.verilator.BuckyballToyVerilatorConfig"', - } - - data = { - "config": config_name, - "balltype": body.get("balltype"), - "output_dir": body.get("output_dir", f"{bbdir}/arch/build/"), - } - await context.emit({"topic": "verilator.verilog", "data": data}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/verilator/02_verilog_event_step.py b/workflow/steps/verilator/02_verilog_event_step.py deleted file mode 100644 index fd84c8ec..00000000 --- a/workflow/steps/verilator/02_verilog_event_step.py +++ /dev/null @@ -1,93 +0,0 @@ -import os -import subprocess -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make verilog", - "description": "generate verilog code", - "subscribes": ["verilator.verilog"], - "emits": ["verilator.build"], - "flows": ["verilator"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - build_dir = data.get("output_dir", f"{bbdir}/arch/build/") - arch_dir = f"{bbdir}/arch" - - # Get config name, must be provided - config_name = data.get("config") - if not config_name or config_name == "None": - context.logger.error("Configuration name is required but not provided") - success_result, failure_result = await check_result( - context, - 1, - continue_run=False, - extra_fields={ - "task": "validation", - "error": "Configuration name is required. Please specify --config parameter.", - "example": 'bbdev verilator --verilog "--config sims.verilator.BuckyballToyVerilatorConfig"', - }, - ) - return failure_result - - context.logger.info(f"Using configuration: {config_name}") - - # ================================================================================== - # Execute operation - # ================================================================================== - if data.get("balltype"): - command = ( - f"mill -i __.test.runMain sims.verify.BallTopMain {data.get('balltype')} " - ) - else: - command = f"mill -i __.test.runMain sims.verilator.Elaborate {config_name} " - - command += "--disable-annotation-unknown -strip-debug-info -O=debug " - command += f"--split-verilog -o={build_dir}" - - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=arch_dir, - stdout_prefix="verilator verilog", - stderr_prefix="verilator verilog", - ) - - # Remove unwanted file - topname_file = f"{arch_dir}/TestHarness.sv" - if os.path.exists(topname_file): - os.remove(topname_file) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=data.get("from_run_workflow", False), - extra_fields={"task": "verilog"}, - ) - - # ================================================================================== - # Continue routing - # Routing to verilog or finish workflow - # For run workflow, continue to verilog; for standalone clean, complete - # ================================================================================== - if data.get("from_run_workflow"): - await context.emit( - {"topic": "verilator.build", "data": {**data, "task": "run"}} - ) - - return diff --git a/workflow/steps/verilator/03_build_api_step.py b/workflow/steps/verilator/03_build_api_step.py deleted file mode 100644 index 2c77f19e..00000000 --- a/workflow/steps/verilator/03_build_api_step.py +++ /dev/null @@ -1,30 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Verilator Build", - "description": "build verilator executable", - "path": "/verilator/build", - "method": "POST", - "emits": ["verilator.build"], - "flows": ["verilator"], -} - - -async def handler(req, context): - body = req.get("body") or {} - data = { - "jobs": body.get("jobs", 16), - "cosim": body.get("cosim", False), - } - await context.emit({"topic": "verilator.build", "data": data}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/verilator/03_build_event_step.py b/workflow/steps/verilator/03_build_event_step.py deleted file mode 100644 index 1d5100e5..00000000 --- a/workflow/steps/verilator/03_build_event_step.py +++ /dev/null @@ -1,137 +0,0 @@ -import os -import subprocess -import glob -import sys - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make build", - "description": "build verilator executable", - "subscribes": ["verilator.build"], - "emits": ["verilator.sim", "verilator.cosim"], - "flows": ["verilator"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - arch_dir = f"{bbdir}/arch" - build_dir = f"{arch_dir}/build" - waveform_dir = f"{arch_dir}/waveform" - log_dir = f"{arch_dir}/log" - cosim = data.get("cosim", False) - - # ================================================================================== - # Execute operation - # ================================================================================== - # Find sources - vsrcs = glob.glob(f"{build_dir}/**/*.v", recursive=True) + glob.glob( - f"{build_dir}/**/*.sv", recursive=True - ) - csrcs = ( - glob.glob(f"{arch_dir}/src/csrc/**/*.c", recursive=True) - + glob.glob(f"{arch_dir}/src/csrc/**/*.cc", recursive=True) - + glob.glob(f"{arch_dir}/src/csrc/**/*.cpp", recursive=True) - + glob.glob(f"{build_dir}/**/*.c", recursive=True) - + glob.glob(f"{build_dir}/**/*.cc", recursive=True) - + glob.glob(f"{build_dir}/**/*.cpp", recursive=True) - ) - - # Setup paths: fesvr from bebop/host/spike/riscv-isa-sim (install/include, install/lib) - bebop_isa_sim = f"{bbdir}/bebop/host/spike/riscv-isa-sim" - inc_paths = [ - os.environ.get("RISCV", "") + "/include" if os.environ.get("RISCV") else "", - f"{arch_dir}/thirdparty/chipyard/tools/DRAMSim2", - f"{bebop_isa_sim}/install/include", - build_dir, - f"{arch_dir}/src/csrc/include", - ] - inc_flags = " ".join([f"-I{p}" for p in inc_paths if p]) - - if cosim: - topname = "ToyBuckyball" - else: - topname = "TestHarness" - - cflags = f"{inc_flags} -DTOP_NAME='\"V{topname}\"' -std=c++17 " - if cosim: - cflags += " -DCOSIM" - ldflags = ( - f"-lreadline -ldramsim -lfesvr -lstdc++ " - f"-L{arch_dir}/thirdparty/chipyard/tools/DRAMSim2 " - f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build " - f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build/lib" - f"-L{bebop_isa_sim}/install/lib" - ) - - obj_dir = f"{build_dir}/obj_dir" - subprocess.run(f"rm -rf {obj_dir}", shell=True) - os.makedirs(obj_dir, exist_ok=True) - - sources = " ".join(vsrcs + csrcs) - jobs = data.get("jobs", "") - - verilator_cmd = ( - f"verilator -MMD --build -cc --trace -O3 --x-assign fast --x-initial fast --noassert -Wno-fatal " - f"--trace-fst --trace-threads 1 --output-split 10000 --output-split-cfuncs 100 " - f"--unroll-count 256 " - f"-Wno-PINCONNECTEMPTY " - f"-Wno-ASSIGNDLY " - f"-Wno-DECLFILENAME " - f"-Wno-UNUSED " - f"-Wno-UNOPTFLAT " - f"-Wno-BLKANDNBLK " - f"-Wno-style " - f"-Wall " - f"--timing -j {jobs} +incdir+{build_dir} --top {topname} {sources} " - f"-CFLAGS '{cflags}' -LDFLAGS '{ldflags}' --Mdir {obj_dir} --exe" - ) - - result = stream_run_logger( - cmd=verilator_cmd, - logger=context.logger, - cwd=bbdir, - stdout_prefix="verilator build", - stderr_prefix="verilator build", - ) - result = stream_run_logger( - cmd=f"make -C {obj_dir} -f V{topname}.mk V{topname}", - logger=context.logger, - cwd=bbdir, - stdout_prefix="verilator build", - stderr_prefix="verilator build", - ) - - # ================================================================================== - # Return result to API - # ================================================================================== - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=data.get("from_run_workflow", False), - extra_fields={"task": "build"}, - ) - - # ================================================================================== - # Continue routing - # ================================================================================== - if data.get("from_run_workflow"): - if cosim: - await context.emit( - {"topic": "verilator.cosim", "data": {**data, "task": "run"}} - ) - else: - await context.emit( - {"topic": "verilator.sim", "data": {**data, "task": "run"}} - ) - - return diff --git a/workflow/steps/verilator/04_cosim_api_step.py b/workflow/steps/verilator/04_cosim_api_step.py deleted file mode 100644 index cf0c2820..00000000 --- a/workflow/steps/verilator/04_cosim_api_step.py +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Verilator Cosim", - "description": "run verilator cosimulation", - "path": "/verilator/cosim", - "method": "POST", - "emits": ["verilator.cosim"], - "flows": ["verilator"], -} - - -async def handler(req, context): - body = req.get("body") or {} - binary = body.get("binary", "") - batch = body.get("batch", False) - if not binary: - return { - "status": 400, - "body": { - "success": False, - "failure": True, - "returncode": 400, - "message": "binary parameter is required", - }, - } - - await context.emit({"topic": "verilator.cosim", "data": {**body, "task": "cosim"}}) - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/verilator/04_cosim_event_step.py b/workflow/steps/verilator/04_cosim_event_step.py deleted file mode 100644 index 66d26776..00000000 --- a/workflow/steps/verilator/04_cosim_event_step.py +++ /dev/null @@ -1,124 +0,0 @@ -import os -import subprocess -import sys -from datetime import datetime - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.search_workload import search_workload -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make cosim", - "description": "run cosimulation", - "subscribes": ["verilator.cosim"], - "emits": [], - "flows": ["verilator"], -} - - -async def handler(data, context): - # ================================================================================== - # Get simulation parameters - # ================================================================================== - bbdir = get_buckyball_path() - arch_dir = f"{bbdir}/arch" - build_dir = f"{arch_dir}/build" - - # Generate timestamp - timestamp = datetime.now().strftime("%Y-%m-%d-%H-%M") - - binary_name = data.get("binary", "") - success_result, failure_result = await check_result( - context, returncode=(binary_name == None), continue_run=True - ) - - binary_path = search_workload(f"{bbdir}/bb-tests/output/workloads/src", binary_name) - success_result, failure_result = await check_result( - context, returncode=(binary_path == None), continue_run=True - ) - if failure_result: - context.logger.error("binary not found", failure_result) - return - - # Create log and waveform directory - log_dir = f"{arch_dir}/log/{timestamp}-{binary_name}" - waveform_dir = f"{arch_dir}/waveform/{timestamp}-{binary_name}" - topname = "ToyBuckyball" - - os.makedirs(log_dir, exist_ok=True) - os.makedirs(waveform_dir, exist_ok=True) - - bin_path = f"{build_dir}/obj_dir/V{topname}" - batch = data.get("batch", False) - - # Create log and waveform file - log_path = f"{log_dir}/bdb.log" - fst_path = f"{waveform_dir}/waveform.fst" - # Remove old waveform file - subprocess.run(f"rm -f {waveform_dir}/waveform.vcd", shell=True, check=True) - - # ================================================================================== - # Execute simulation script with streaming output - # ================================================================================== - # batch_param = "True" if batch else "False" - # sim_cmd = f"./scripts/sim.sh {bin_path} {binary_path} {log_dir}/stdout.log \ - # {log_dir}/disasm.log {batch_param} {vcd_path} {log_path}" - sim_cmd = ( - f"{bin_path} +permissive +loadmem={binary_path} +loadmem_addr=800000000 " - f"{'+batch ' if batch else ''} " - f"+fst={fst_path} +log={log_path} +permissive-off " - f"{binary_path} > >(tee {log_dir}/stdout.log) 2> >(spike-dasm > {log_dir}/disasm.log)" - ) - script_dir = os.path.dirname(__file__) - - result = stream_run_logger( - cmd=sim_cmd, - logger=context.logger, - cwd=script_dir, - stdout_prefix="verilator sim", - stderr_prefix="verilator sim", - executable="bash", - ) - success_result, failure_result = await check_result( - context, returncode=result.returncode, continue_run=True - ) - if failure_result: - context.logger.error("sim failed", failure_result) - return - - if os.path.exists(f"{waveform_dir}/waveform.fst.heir"): - subprocess.run( - f"gtkwave -f {waveform_dir}/waveform.fst -H {waveform_dir}/waveform.fst.heir", - shell=True, - check=True, - ) - - # ================================================================================== - # Return simulation result - # ================================================================================== - # This is the end point of the run workflow, status will no longer be set to processing - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=False, - extra_fields={ - "task": "sim", - "binary": binary_path, - "log_dir": log_dir, - "waveform_dir": waveform_dir, - "timestamp": timestamp, - }, - ) - - # ================================================================================== - # Finish workflow - # ================================================================================== - - return diff --git a/workflow/steps/verilator/04_sim_api_step.py b/workflow/steps/verilator/04_sim_api_step.py deleted file mode 100644 index dbfd4d00..00000000 --- a/workflow/steps/verilator/04_sim_api_step.py +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Verilator Sim", - "description": "run verilator simulation", - "path": "/verilator/sim", - "method": "POST", - "emits": ["verilator.sim"], - "flows": ["verilator"], -} - - -async def handler(req, context): - body = req.get("body") or {} - binary = body.get("binary", "") - batch = body.get("batch", False) - if not binary: - return { - "status": 400, - "body": { - "success": False, - "failure": True, - "returncode": 400, - "message": "binary parameter is required", - }, - } - - await context.emit({"topic": "verilator.sim", "data": {**body, "task": "sim"}}) - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/verilator/04_sim_event_step.py b/workflow/steps/verilator/04_sim_event_step.py deleted file mode 100644 index 521236ad..00000000 --- a/workflow/steps/verilator/04_sim_event_step.py +++ /dev/null @@ -1,124 +0,0 @@ -import os -import subprocess -import sys -from datetime import datetime - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.search_workload import search_workload -from utils.event_common import check_result - -config = { - "type": "event", - "name": "make sim", - "description": "run simulation", - "subscribes": ["verilator.sim"], - "emits": [], - "flows": ["verilator"], -} - - -async def handler(data, context): - # ================================================================================== - # Get simulation parameters - # ================================================================================== - bbdir = get_buckyball_path() - arch_dir = f"{bbdir}/arch" - build_dir = f"{arch_dir}/build" - - # Generate timestamp - timestamp = datetime.now().strftime("%Y-%m-%d-%H-%M") - - binary_name = data.get("binary", "") - success_result, failure_result = await check_result( - context, returncode=(binary_name == None), continue_run=True - ) - - binary_path = search_workload(f"{bbdir}/bb-tests/output/workloads/src", binary_name) - success_result, failure_result = await check_result( - context, returncode=(binary_path == None), continue_run=True - ) - if failure_result: - context.logger.error("binary not found", failure_result) - return - - # Create log and waveform directory - log_dir = f"{arch_dir}/log/{timestamp}-{binary_name}" - waveform_dir = f"{arch_dir}/waveform/{timestamp}-{binary_name}" - topname = "TestHarness" - - os.makedirs(log_dir, exist_ok=True) - os.makedirs(waveform_dir, exist_ok=True) - - bin_path = f"{build_dir}/obj_dir/V{topname}" - batch = data.get("batch", False) - - # Create log and waveform file - log_path = f"{log_dir}/bdb.log" - fst_path = f"{waveform_dir}/waveform.fst" - # Remove old waveform file - subprocess.run(f"rm -f {waveform_dir}/waveform.vcd", shell=True, check=True) - - # ================================================================================== - # Execute simulation script with streaming output - # ================================================================================== - # batch_param = "True" if batch else "False" - # sim_cmd = f"./scripts/sim.sh {bin_path} {binary_path} {log_dir}/stdout.log \ - # {log_dir}/disasm.log {batch_param} {vcd_path} {log_path}" - sim_cmd = ( - f"{bin_path} +permissive +loadmem={binary_path} +loadmem_addr=800000000 " - f"{'+batch ' if batch else ''} " - f"+fst={fst_path} +log={log_path} +permissive-off " - f"{binary_path} > >(tee {log_dir}/stdout.log) 2> >(spike-dasm > {log_dir}/disasm.log)" - ) - script_dir = os.path.dirname(__file__) - - result = stream_run_logger( - cmd=sim_cmd, - logger=context.logger, - cwd=script_dir, - stdout_prefix="verilator sim", - stderr_prefix="verilator sim", - executable="bash", - ) - success_result, failure_result = await check_result( - context, returncode=result.returncode, continue_run=True - ) - if failure_result: - context.logger.error("sim failed", failure_result) - return - - if os.path.exists(f"{waveform_dir}/waveform.fst.heir"): - subprocess.run( - f"gtkwave -f {waveform_dir}/waveform.fst -H {waveform_dir}/waveform.fst.heir", - shell=True, - check=True, - ) - - # ================================================================================== - # Return simulation result - # ================================================================================== - # This is the end point of the run workflow, status will no longer be set to processing - success_result, failure_result = await check_result( - context, - result.returncode, - continue_run=False, - extra_fields={ - "task": "sim", - "binary": binary_path, - "log_dir": log_dir, - "waveform_dir": waveform_dir, - "timestamp": timestamp, - }, - ) - - # ================================================================================== - # Finish workflow - # ================================================================================== - - return diff --git a/workflow/steps/verilator/05_run_api_step.py b/workflow/steps/verilator/05_run_api_step.py deleted file mode 100644 index b29f3508..00000000 --- a/workflow/steps/verilator/05_run_api_step.py +++ /dev/null @@ -1,53 +0,0 @@ -import asyncio -from utils.event_common import wait_for_result - -config = { - "type": "api", - "name": "Verilator Complete Workflow", - "description": "trigger complete verilator workflow", - "path": "/verilator/run", - "method": "POST", - "emits": ["verilator.run"], - "flows": ["verilator"], -} - - -async def handler(req, context): - body = req.get("body") or {} - - config = { - "binary": body.get("binary", ""), - "config": body.get("config", "sims.verilator.BuckyballToyVerilatorConfig"), - "jobs": body.get("jobs", "16"), - "batch": body.get("batch", False), - "cosim": body.get("cosim", False), - "from_run_workflow": True, - } - - await context.emit({"topic": "verilator.run", "data": config}) - - # ================================================================================== - # Wait for simulation result - # - # Expected return result format: - # { - # "status": 200/400/500, - # "body": { - # "success": true/false, - # "failure": true/false, - # "processing": true/false, - # "return_code": 0, - # other fields - # } - # } - # - # Since the Motia framework wraps data in the data field, it needs to be unpacked - # if isinstance(result, dict) and 'data' in result: - # return result['data'] - # return result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/verilator/README.md b/workflow/steps/verilator/README.md deleted file mode 100644 index 25635f69..00000000 --- a/workflow/steps/verilator/README.md +++ /dev/null @@ -1,197 +0,0 @@ -# Verilator Simulation Workflow - -Hardware simulation workflow based on Verilator in the Buckyball framework, providing a complete automation flow from RTL generation to simulation execution. Verilator is a high-performance Verilog simulator that supports fast functional verification and performance analysis. - -## II. Original API Usage Guide - -#### `run` -**Endpoint**: `POST /verilator/run` - -**Function**: Execute complete workflow. Clean build directory, generate Verilog, compile Verilator into simulation file, and run simulation directly - -**Parameters**: - -- **`jobs`** - Number of parallel compilation tasks - - Default value: `16` -- **`binary`** [Required] - Test binary file path - - Default value: `""` - -**Example**: -```bash -# bbdev wrapper -bbdev verilator --run "jobs 256 --binary ${buckyball}/bb-tests/workloads/build/src/CTest/ctest_mvin_mvout_alternate_test_singlecore-baremetal --batch" - -# Raw command -curl -X POST http://localhost:5000/verilator/run -H "Content-Type: application/json" -d '{"jobs": 8, "binary": "/home/user/test.elf"}' -``` - - -#### `clean` - -**Endpoint**: `POST /verilator/clean` - -**Function**: Clean build folder - -**Parameters**: None - -**Example**: -```bash -curl -X POST http://localhost:5000/verilator/clean -``` - -#### `verilog` - -**Endpoint**: `POST /verilator/verilog` - -**Function**: Only generate Verilog code, without compilation and simulation - -**Parameters**: None - -**Example**: -```bash -curl -X POST http://localhost:5000/verilator/verilog -d '{"jobs": 8}' -``` - -#### `build` - -**Endpoint**: `POST /verilator/build` - -**Function**: Compile verilog source files and cpp source files into executable simulation file - -**Parameters**: - -- **`jobs`** - Number of parallel compilation tasks - - Default value: `16` - -**Example**: -```bash -curl -X POST http://localhost:5000/verilator/build -d '{"jobs": 16}' -``` - -#### `sim` - -**Endpoint**: `POST /verilator/sim` - -**Function**: Run existing simulation executable - -**Parameters**: - -- **`binary`** [Required] - Custom test binary file path - -**Example**: -```bash -curl -X POST http://localhost:5000/verilator/sim \ - -H "Content-Type: application/json" \ - -d '{"binary": "/home/user/test_program.elf"}' -``` - - - - -## II. Developer Documentation - -### Directory Structure - -``` -steps/verilator/ -├── 00_start_node_noop_step.py # Workflow entry node definition -├── 00_start_node_noop_step.tsx # Frontend UI component -├── 01_run_api_step.py # Complete workflow API entry -├── 01_clean_api_step.py # Clean API endpoint -├── 01_verilog_api_step.py # Verilog generation API endpoint -├── 01_build_api_step.py # Build API endpoint -├── 01_sim_api_step.py # Simulation API endpoint -├── 02_clean_event_step.py # Clean build directory -├── 03_verilog_event_step.py # Verilog code generation -├── 04_build_event_step.py # Verilator compilation -├── 05_sim_event_step.py # Simulation execution -├── 99_complete_event_step.py # Completion handling -├── 99_error_event_step.py # Error handling -└── README.md # This document -``` - -### Workflow Steps Detailed - -#### 1. Entry Node (`00_start_node_noop_step.py`) -- **Type**: `noop` node -- **Function**: Provide UI interface entry point -- **Frontend**: "Start Build Verilator" button - -#### 2. API Endpoints -- **Complete Workflow API** (`01_run_api_step.py`): `/verilator` → `verilator.run` -- **Clean API** (`01_clean_api_step.py`): `/verilator/clean` → `verilator.clean` -- **Verilog Generation API** (`01_verilog_api_step.py`): `/verilator/verilog` → `verilator.verilog` -- **Build API** (`01_build_api_step.py`): `/verilator/build` → `verilator.build` -- **Simulation API** (`01_sim_api_step.py`): `/verilator/sim` → `verilator.sim` - -#### 3. Clean Step (`02_clean_event_step.py`) -- **Type**: `event` step -- **Subscribes**: `verilator.run`, `verilator.clean` -- **Emits**: `verilator.verilog`, `verilator.complete` -- **Function**: Delete build directory, serves workflow or standalone operation - -#### 4. Verilog Generation (`03_verilog_event_step.py`) -- **Type**: `event` step -- **Subscribes**: `verilator.verilog` -- **Emits**: `verilator.build`, `verilator.complete` -- **Function**: Use mill to generate Verilog code to build directory - -#### 5. Verilator Compilation (`04_build_event_step.py`) -- **Type**: `event` step -- **Subscribes**: `verilator.build` -- **Emits**: `verilator.sim`, `verilator.complete` -- **Function**: Compile Verilog and C++ source files into executable simulation file - -#### 6. Simulation Execution (`05_sim_event_step.py`) -- **Type**: `event` step -- **Subscribes**: `verilator.sim` -- **Emits**: `verilator.complete` -- **Function**: Run simulation, supports custom binary parameter - -#### 7. Completion Handling (`99_complete_event_step.py`) -- **Type**: `event` step -- **Subscribes**: `verilator.complete` -- **Function**: Print success message, mark workflow as complete - -#### 8. Error Handling (`99_error_event_step.py`) -- **Type**: `event` step -- **Subscribes**: `verilator.error` -- **Function**: Print error message, handle workflow exceptions - -### Workflow Diagram - -```mermaid -graph TD; - API[POST /verilator
    Complete Workflow] --> RUN[verilator.run] - - CLEAN_DIRECT[verilator.clean
    Single-step Clean] --> CLEAN_STEP[02_clean_event_step] - VERILOG_DIRECT[verilator.verilog
    Single-step Generate] --> VERILOG_STEP[03_verilog_event_step] - BUILD_DIRECT[verilator.build
    Single-step Build] --> BUILD_STEP[04_build_event_step] - SIM_DIRECT[verilator.sim
    Single-step Simulation] --> SIM_STEP[05_sim_event_step] - - RUN --> CLEAN_STEP - CLEAN_STEP --> |Workflow Mode| VERILOG_STEP - CLEAN_STEP --> |Single-step Mode| COMPLETE[verilator.complete] - - VERILOG_STEP --> |Workflow Mode| BUILD_STEP - VERILOG_STEP --> |Single-step Mode| COMPLETE - - BUILD_STEP --> |Workflow Mode| SIM_STEP - BUILD_STEP --> |Single-step Mode| COMPLETE - - SIM_STEP --> COMPLETE - - COMPLETE --> COMPLETE_STEP[99_complete_event_step] - - CLEAN_STEP -.-> |Error| ERROR[verilator.error] - VERILOG_STEP -.-> |Error| ERROR - BUILD_STEP -.-> |Error| ERROR - SIM_STEP -.-> |Error| ERROR - - ERROR --> ERROR_STEP[99_error_event_step] - - classDef apiNode fill:#e1f5fe - classDef eventNode fill:#f3e5f5 - classDef stepNode fill:#e8f5e8 - classDef endNode fill:#fff3e0 -``` diff --git a/workflow/steps/workload/01_buidl_api_step.py b/workflow/steps/workload/01_buidl_api_step.py deleted file mode 100644 index daade0a0..00000000 --- a/workflow/steps/workload/01_buidl_api_step.py +++ /dev/null @@ -1,38 +0,0 @@ -import subprocess -import sys -import os -import asyncio -from utils.event_common import wait_for_result - -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - -from utils.path import get_buckyball_path - -config = { - "type": "api", - "name": "build workload", - "description": "build workload", - "path": "/workload/build", - "method": "POST", - "emits": ["workload.build"], - "flows": ["workload"], -} - - -async def handler(req, context): - bbdir = get_buckyball_path() - body = req.get("body") or {} - data = {"workload": body.get("workload", "")} - workload_dir = f"{bbdir}/bb-tests/workload" - await context.emit({"topic": "workload.build", "data": data}) - - # ================================================================================== - # Wait for simulation result - # ================================================================================== - while True: - result = await wait_for_result(context) - if result is not None: - return result - await asyncio.sleep(1) diff --git a/workflow/steps/workload/01_build_event_step.py b/workflow/steps/workload/01_build_event_step.py deleted file mode 100644 index 068013f1..00000000 --- a/workflow/steps/workload/01_build_event_step.py +++ /dev/null @@ -1,61 +0,0 @@ -from contextlib import redirect_stdout -import os -from re import T -import subprocess -import sys -import time - -# Add the utils directory to the Python path -utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) -if utils_path not in sys.path: - sys.path.insert(0, utils_path) - - -from utils.path import get_buckyball_path -from utils.stream_run import stream_run_logger -from utils.event_common import check_result - -config = { - "type": "event", - "name": "build workload", - "description": "build workload", - "subscribes": ["workload.build"], - "emits": [], - "flows": ["workload"], -} - - -async def handler(data, context): - bbdir = get_buckyball_path() - workload_dir = f"{bbdir}/bb-tests" - build_dir = f"{workload_dir}/build" - - # os.mkdir(f"{workload_dir}/build", exist_ok=True) - subprocess.run(f"rm -rf {build_dir} && mkdir -p {build_dir}", shell=True) - - # command = f"source {bbdir}/env.sh && cd {workload_dir}/build && cmake .. && make build-all" - command = f"source {bbdir}/env.sh && cd {build_dir} && cmake -G Ninja .. && ninja -j{os.cpu_count()}" - context.logger.info( - "Executing workload command", {"command": command, "cwd": build_dir} - ) - result = stream_run_logger( - cmd=command, - logger=context.logger, - cwd=workload_dir, - executable="bash", - stdout_prefix="workload build", - stderr_prefix="workload build", - ) - - # ================================================================================== - # Return simulation result - # ================================================================================== - # This is the end of run workflow, status no longer set to processing - success_result, failure_result = await check_result( - context, result.returncode, continue_run=False - ) - - # ================================================================================== - # finish workflow - # ================================================================================== - return diff --git a/workflow/steps/workload/README.md b/workflow/steps/workload/README.md deleted file mode 100644 index a6bb3941..00000000 --- a/workflow/steps/workload/README.md +++ /dev/null @@ -1,39 +0,0 @@ -# Workload Workflow - -Workload build workflow in Buckyball framework, used to build test workloads and benchmark programs. - -## API Usage - -### `build` -**Endpoint**: `POST /workload/build` - -**Function**: Build workload - -**Parameters**: -- **`workload`** - Specify workload name to build - -**Examples**: -```bash -# Build specific workload -bbdev workload --build "--workload test_program" - -# Build all workloads -bbdev workload --build -``` - -**Response**: -```json -{ - "status": 200, - "body": { - "success": true, - "processing": false, - "return_code": 0 - } -} -``` - -## Notes - -- Workload source code located in `bb-tests/workload` directory -- Build results typically output to `bb-tests/workloads/build` directory diff --git a/workflow/utils/__init__.py b/workflow/utils/__init__.py deleted file mode 100644 index 6db5263f..00000000 --- a/workflow/utils/__init__.py +++ /dev/null @@ -1,10 +0,0 @@ -from .stream_run import stream_run -from .path import get_buckyball_path -from .port import find_available_port -from .search_workload import ( - search_workload, - search_workload_all, - search_workload_pattern, -) - -__all__ = ["stream_run", "get_buckyball_path", "find_available_port", "search_workload"] diff --git a/workflow/utils/event_common.py b/workflow/utils/event_common.py deleted file mode 100644 index 71796922..00000000 --- a/workflow/utils/event_common.py +++ /dev/null @@ -1,111 +0,0 @@ -""" -Common utility functions for all event steps. -""" - - -async def check_result(context, returncode, continue_run=False, extra_fields=None): - """ - Check returncode, create appropriate result objects and set state. - - Args: - context: The event context object - returncode: The return code (int) - continue_run: If True, set processing state instead of success/failure - extra_fields: Optional dictionary of extra fields to include in result body - - Returns: - tuple: (success_result, failure_result) - one will be None based on returncode and continue_run - """ - extra_fields = extra_fields or {} - - if continue_run: - await context.state.set(context.trace_id, "processing", True) - return None, None - elif returncode != 0: - failure_result = { - "status": 500, - "body": { - "success": False, - "failure": True, - "processing": False, - "returncode": returncode, - **extra_fields, - }, - } - await context.state.set(context.trace_id, "failure", failure_result) - return None, failure_result - else: - success_result = { - "status": 200, - "body": { - "success": True, - "failure": False, - "processing": False, - "returncode": returncode, - **extra_fields, - }, - } - await context.state.set(context.trace_id, "success", success_result) - return success_result, None - - -# ================================================================================== -# API waits for event return result -# -# Expected return result format: -# { -# "status": 200/400/500, -# "body": { -# "success": true/false, -# "failure": true/false, -# "processing": true/false, -# "return_code": 0, -# other fields -# } -# } -# -# Since the Motia framework wraps data in the data field, it needs to be unpacked -# if isinstance(result, dict) and 'data' in result: -# return result['data'] -# return result -# ================================================================================== - - -async def wait_for_result(context): - """ - Check for task completion state (success or failure). - Returns result if found, None if still processing. - - Args: - context: The event context object - - Returns: - dict or None: The result data if task completed, None if still processing - """ - # Check for success result - success_result = await context.state.get(context.trace_id, "success") - if success_result and success_result.get("data"): - # Filter out invalid null state - if success_result == {"data": None} or ( - isinstance(success_result, dict) - and success_result.get("data") is None - and len(success_result) == 1 - ): - await context.state.delete(context.trace_id, "success") - return None - context.logger.info("task completed") - - if isinstance(success_result, dict) and "data" in success_result: - return success_result["data"] - return success_result - - # Check for error status - failure_result = await context.state.get(context.trace_id, "failure") - if failure_result and failure_result.get("data"): - context.logger.error("task failed", failure_result) - - if isinstance(failure_result, dict) and "data" in failure_result: - return failure_result["data"] - return failure_result - - return None diff --git a/workflow/utils/path.py b/workflow/utils/path.py deleted file mode 100644 index 69320c09..00000000 --- a/workflow/utils/path.py +++ /dev/null @@ -1,6 +0,0 @@ -import os - - -def get_buckyball_path(): - current_dir = os.path.dirname(__file__) - return os.path.dirname(os.path.dirname(current_dir)) diff --git a/workflow/utils/port.py b/workflow/utils/port.py deleted file mode 100644 index 82e6bfed..00000000 --- a/workflow/utils/port.py +++ /dev/null @@ -1,16 +0,0 @@ -import socket - - -def find_available_port(start_port: int = 5000, end_port: int = 5500) -> int: - """Find an available port in the specified range""" - for port in range(start_port, end_port + 1): - try: - with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as sock: - sock.bind(("localhost", port)) - return port - except OSError: - # Port is already in use, try next one - continue - - # If no port is available in the range, raise an exception - raise RuntimeError(f"No available port found in range {start_port}-{end_port}") diff --git a/workflow/utils/search_workload.py b/workflow/utils/search_workload.py deleted file mode 100644 index 0d4121f7..00000000 --- a/workflow/utils/search_workload.py +++ /dev/null @@ -1,72 +0,0 @@ -import os -from typing import Optional, List - - -def search_workload(search_dir: str, filename: str) -> Optional[str]: - """ - Recursively search for a specified filename in the directory and its subdirectories - - Args: - search_dir: Root directory to search - filename: Filename to search for - - Returns: - Absolute path of the found file, or None if not found - """ - if not os.path.exists(search_dir): - return None - - for root, dirs, files in os.walk(search_dir): - if filename in files: - return os.path.abspath(os.path.join(root, filename)) - - return None - - -def search_workload_all(search_dir: str, filename: str) -> List[str]: - """ - Recursively search for a specified filename in the directory and its subdirectories, returning all matches - - Args: - search_dir: Root directory to search - filename: Filename to search for - - Returns: - List of absolute paths of all found files - """ - results = [] - - if not os.path.exists(search_dir): - return results - - for root, dirs, files in os.walk(search_dir): - if filename in files: - results.append(os.path.abspath(os.path.join(root, filename))) - - return results - - -def search_workload_pattern(search_dir: str, pattern: str) -> List[str]: - """ - Recursively search for files matching a specified pattern in the directory and its subdirectories - - Args: - search_dir: Root directory to search - pattern: Filename pattern (supports wildcards * and ?) - - Returns: - List of absolute paths of all matching files - """ - import fnmatch - - results = [] - - if not os.path.exists(search_dir): - return results - - for root, dirs, files in os.walk(search_dir): - for file in files: - if fnmatch.fnmatch(file, pattern): - results.append(os.path.abspath(os.path.join(root, file))) - - return results diff --git a/workflow/utils/stream_run.py b/workflow/utils/stream_run.py deleted file mode 100644 index 6bd6dcb1..00000000 --- a/workflow/utils/stream_run.py +++ /dev/null @@ -1,172 +0,0 @@ -import subprocess -import threading -from typing import Optional, List, Callable - - -class StreamResult: - """Result object mimicking subprocess.CompletedProcess""" - - def __init__(self, returncode: int, stdout: str, stderr: str): - self.returncode = returncode - self.stdout = stdout - self.stderr = stderr - - -def stream_run( - cmd: str, - cwd: Optional[str] = None, - shell: bool = True, - executable: Optional[str] = None, - timeout: Optional[float] = None, - on_stdout: Optional[Callable[[str], None]] = None, - on_stderr: Optional[Callable[[str], None]] = None, - stdout_prefix: str = "STDOUT", - stderr_prefix: str = "STDERR", -) -> StreamResult: - """ - Execute command and stream output in real-time - - Args: - cmd: Command to execute - cwd: Working directory - shell: Whether to execute using shell - timeout: Timeout in seconds - on_stdout: Callback function for stdout lines - on_stderr: Callback function for stderr lines - stdout_prefix: Prefix for stdout output - stderr_prefix: Prefix for stderr output - - Returns: - StreamResult: Result object containing returncode, stdout, stderr - - Example: - def log_stdout(line): - logger.info(f'[STDOUT] {line}') - - def log_stderr(line): - logger.info(f'[STDERR] {line}') - - result = stream_run( - "make build", - cwd="/path/to/project", - on_stdout=log_stdout, - on_stderr=log_stderr - ) - """ - - def read_stream( - stream, output_list: List[str], callback: Optional[Callable], prefix: str - ): - """Thread function to read stream output""" - try: - for line in iter(stream.readline, ""): - if line: - line = line.rstrip() - output_list.append(line) - if callback: - callback(line) - finally: - stream.close() - - # Start process - process = subprocess.Popen( - cmd, - cwd=cwd, - shell=shell, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - text=True, - bufsize=1, - executable=executable, - ) - - stdout_lines = [] - stderr_lines = [] - - # Create threads to read stdout and stderr - stdout_thread = threading.Thread( - target=read_stream, - args=(process.stdout, stdout_lines, on_stdout, stdout_prefix), - ) - stderr_thread = threading.Thread( - target=read_stream, - args=(process.stderr, stderr_lines, on_stderr, stderr_prefix), - ) - - stdout_thread.start() - stderr_thread.start() - - try: - # Wait for process to finish (with timeout) - process.wait(timeout=timeout) - except subprocess.TimeoutExpired: - # Kill process on timeout - process.kill() - process.wait() - - # Wait for threads to finish - stdout_thread.join() - stderr_thread.join() - - return StreamResult( - returncode=process.returncode, - stdout="\n".join(stdout_lines), - stderr="\n".join(stderr_lines), - ) - - -def stream_run_logger( - cmd: str, - logger, - cwd: Optional[str] = None, - shell: bool = True, - executable: Optional[str] = None, - timeout: Optional[float] = None, - stdout_prefix: str = "STDOUT", - stderr_prefix: str = "STDERR", - verbose: bool = False, -) -> StreamResult: - """ - Convenience function for streaming output using logger - - Args: - cmd: Command to execute - logger: Logger instance - cwd: Working directory - shell: Whether to execute using shell - timeout: Timeout in seconds - stdout_prefix: Prefix for stdout output - stderr_prefix: Prefix for stderr output - verbose: Whether to use verbose output mode (verbose mode uses logger with timestamp, non-verbose prints directly) - - Returns: - StreamResult: Result object containing returncode, stdout, stderr - """ - - def log_stdout(line): - if verbose: - # Verbose mode: use logger.info, includes timestamp and task ID - logger.info(f"[{stdout_prefix}] {line}") - else: - # Non-verbose mode: print directly, use green for STDOUT - print(f"\033[32m[{stdout_prefix}]\033[0m {line}") - - def log_stderr(line): - if verbose: - # Verbose mode: use logger.info, includes timestamp and task ID - logger.info(f"[{stderr_prefix}] {line}") - else: - # Non-verbose mode: print directly, use red for STDERR - print(f"\033[31m[{stderr_prefix}]\033[0m {line}") - - return stream_run( - cmd=cmd, - cwd=cwd, - shell=shell, - executable=executable, - timeout=timeout, - on_stdout=log_stdout, - on_stderr=log_stderr, - stdout_prefix=stdout_prefix, - stderr_prefix=stderr_prefix, - ) diff --git a/workflow/vscode b/workflow/vscode deleted file mode 160000 index 0393e997..00000000 --- a/workflow/vscode +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 0393e997a706e320faeeae7296273667c30373db From 80b04f02cc42ab7194bdd81372acd1694a66adfa Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 09:57:36 +0800 Subject: [PATCH 099/238] [scripts] fix: add sbt to build environment and fix bug in rtl build --- arch/build.sc | 21 +++++++++++++-------- flake.nix | 1 + scripts/nix/build-all.sh | 7 ++++++- scripts/nix/build-env-scala.nix | 9 +++++++++ 4 files changed, 29 insertions(+), 9 deletions(-) diff --git a/arch/build.sc b/arch/build.sc index 574a3fae..8de92d6a 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -772,15 +772,20 @@ object firrtl2 extends SbtModule { override def millSourcePath = os.pwd / "thirdparty" / "chipyard" / "tools" / "firrtl2" override def scalaVersion = "2.13.12" - // Override sources to include generated ANTLR sources and BuildInfo + // Override sources to include generated ANTLR sources and BuildInfo (from sbt antlr4Generate/compile) override def sources = T.sources { - val baseSources = super.sources() - // Include pre-generated sources from target directory - val generatedDir = millSourcePath / "src" / "target" / "scala-2.13" / "src_managed" / "main" - if (os.exists(generatedDir)) { - baseSources ++ Seq(PathRef(generatedDir)) - } else { - baseSources + val baseSources = super.sources() + // Chipyard freshProject sets firrtl2 base to tools/firrtl2/src, so sbt puts target under src/ (normally is under here) + val underSrc = millSourcePath / "src" / "target" / "scala-2.13" / "src_managed" / "main" + // If sbt was run from tools/firrtl2 directly, target is under tools/firrtl2/ + val underRoot = millSourcePath / "target" / "scala-2.13" / "src_managed" / "main" + val generatedDir = if (os.exists(underSrc)) Some(underSrc) else if (os.exists(underRoot)) Some(underRoot) else None + generatedDir match { + case Some(dir) => baseSources ++ Seq(PathRef(dir)) + case None => + throw new Exception( + "firrtl2.antlr not found. Run: cd arch/thirdparty/chipyard && sbt compile" + ) } } diff --git a/flake.nix b/flake.nix index 82007866..b69a1230 100644 --- a/flake.nix +++ b/flake.nix @@ -50,6 +50,7 @@ # Scala tools scala.mill + scala.sbt scala.scalafmt scala.coursier diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 9b7dcba6..9de46e34 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -74,7 +74,8 @@ function begin_step begin_step "0-1" "submodules init" git submodule update --init -cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init generators/* tools/* +# fpga/fpga-shells is needed by palladium +cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init fpga/fpga-shells generators/* tools/* sims/firesim begin_step "0-2" "Nix environment setup" cd ${BBDIR} @@ -132,6 +133,10 @@ fi if run_step "3"; then begin_step "3" "arch pre-compile sources" + # Generate firrtl2 ANTLR and compile firrtl2 in chipyard first (avoids antlr missing when arch compiles chipyard) + cd ${BBDIR}/arch/thirdparty/chipyard + sbt -J-Xms512m -J-Xmx4g -J-XX:+UseG1GC "firrtl2/compile" + cd ${BBDIR}/arch bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' fi diff --git a/scripts/nix/build-env-scala.nix b/scripts/nix/build-env-scala.nix index 3a806a32..3eb6af55 100644 --- a/scripts/nix/build-env-scala.nix +++ b/scripts/nix/build-env-scala.nix @@ -28,6 +28,15 @@ in # Build tool for Scala, Java and more inherit mill; + # sbt 1.8.2 + sbt = (pkgs.sbt.override { jre = pkgs.jdk17; }).overrideAttrs (old: { + version = "1.8.2"; + src = pkgs.fetchurl { + url = "https://github.com/sbt/sbt/releases/download/v1.8.2/sbt-1.8.2.tgz"; + sha256 = "11j6vyxpiqbaxg5pzm6awmrdf6fkz3pw14zszrnxdnvll16k8r8z"; + }; + }); + # Scala formatter scalafmt = pkgs.scalafmt; From 03d1769b6e4b647ec2f0917193f43f7391f9de61 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 10:42:52 +0800 Subject: [PATCH 100/238] [ci] fix: fix PR head checkout --- .github/workflows/pr.yml | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 0f634ccc..8863401d 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -10,9 +10,6 @@ jobs: name: PR Test runs-on: cpu-server steps: - - uses: actions/checkout@v4 - - uses: DeterminateSystems/determinate-nix-action@v3 - - name: Print information run: | echo "🎉 The job was automatically triggered by a ${{ github.event_name }} event." @@ -20,28 +17,33 @@ jobs: echo "🔎 Branch: ${{ github.head_ref }} -> ${{ github.base_ref }}" echo "🔎 Repository: ${{ github.repository }}" - - name: Pull from the repository + - uses: actions/checkout@v4 + + - name: Reset to clean state shell: zsh {0} + working-directory: ${{ github.workspace }} run: | - git fetch origin +refs/pull/${{ github.event.pull_request.number }}/head:refs/remotes/origin/pr/${{ github.event.pull_request.number }} git clean -fd git reset --hard ${{ github.sha }} - name: Build Workloads shell: zsh {0} + working-directory: ${{ github.workspace }} run: | - bbdev workload --build + nix develop -c bbdev workload --build - name: Build Verilator shell: zsh {0} + working-directory: ${{ github.workspace }} run: | - bbdev verilator --clean - bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' - bbdev verilator --build '--jobs 16' + nix develop -c bbdev verilator --clean + nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' + nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test shell: zsh {0} + working-directory: ${{ github.workspace }} run: | - bbdev sardine --run '--workload ctest' + nix develop -c bbdev sardine --run '--workload ctest' - run: echo "🍏 PR Test is ${{ job.status }}." From 130ef8b23aab8b35ef821075004c3bd2da84158b Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 10:48:22 +0800 Subject: [PATCH 101/238] [nix] feat: add UV dependency to build environment --- flake.nix | 1 + scripts/nix/build-env-bbdev.nix | 3 +++ 2 files changed, 4 insertions(+) diff --git a/flake.nix b/flake.nix index b69a1230..1b50cef5 100644 --- a/flake.nix +++ b/flake.nix @@ -38,6 +38,7 @@ # bbdev dependencies bbdev.nodejs bbdev.pnpm + bbdev.uv bbdev.gcc bbdev.gnumake bbdev.pkg-config diff --git a/scripts/nix/build-env-bbdev.nix b/scripts/nix/build-env-bbdev.nix index ee47f422..72ab683e 100644 --- a/scripts/nix/build-env-bbdev.nix +++ b/scripts/nix/build-env-bbdev.nix @@ -5,6 +5,9 @@ nodejs = pkgs.nodejs_22; pnpm = pkgs.nodePackages.pnpm; + # UV (motia install uses it for Python deps; avoid auto-install via broken pip) + uv = pkgs.uv; + # Build tools (for compiling native modules) gcc = pkgs.gcc; gnumake = pkgs.gnumake; From 64d98376327f4abdc435a9beca7d3bdb136ebf3d Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 11:27:47 +0800 Subject: [PATCH 102/238] [ci] feat: add DeterminateSystems Nix action to GitHub workflow --- .github/workflows/build.yml | 28 ++++++++++++++-------------- .github/workflows/pr.yml | 20 ++++++++++++++------ 2 files changed, 28 insertions(+), 20 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 5ad32e7b..8210769d 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,16 +1,16 @@ -name: Build +# name: Build -on: - pull_request: - push: - branches: [main] +# on: +# pull_request: +# push: +# branches: [main] -jobs: - build: - name: Build - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - uses: DeterminateSystems/determinate-nix-action@v3 - - name: Build Buckyball - run: ./scripts/nix/build-all.sh +# jobs: +# build: +# name: Build +# runs-on: ubuntu-latest +# steps: +# - uses: actions/checkout@v4 +# - uses: DeterminateSystems/determinate-nix-action@v3 +# - name: Build Buckyball +# run: ./scripts/nix/build-all.sh diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 8863401d..7d2a6d71 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -17,33 +17,41 @@ jobs: echo "🔎 Branch: ${{ github.head_ref }} -> ${{ github.base_ref }}" echo "🔎 Repository: ${{ github.repository }}" - - uses: actions/checkout@v4 + # - uses: actions/checkout@v4 + # - uses: DeterminateSystems/determinate-nix-action@v3 - name: Reset to clean state shell: zsh {0} - working-directory: ${{ github.workspace }} run: | + cd ~/Code/buckyball + git fetch origin git clean -fd - git reset --hard ${{ github.sha }} + git checkout ${{ github.head_ref }} + + - name: Nix build + shell: zsh {0} + run: | + cd ~/Code/buckyball + nix build - name: Build Workloads shell: zsh {0} - working-directory: ${{ github.workspace }} run: | + cd ~/Code/buckyball nix develop -c bbdev workload --build - name: Build Verilator shell: zsh {0} - working-directory: ${{ github.workspace }} run: | + cd ~/Code/buckyball nix develop -c bbdev verilator --clean nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test shell: zsh {0} - working-directory: ${{ github.workspace }} run: | + cd ~/Code/buckyball nix develop -c bbdev sardine --run '--workload ctest' - run: echo "🍏 PR Test is ${{ job.status }}." From 703d6514e3926acc8ea3c07add1b6c523cd14dca Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 13:53:26 +0800 Subject: [PATCH 103/238] [scripts] feat: update build-all.sh to include bebop installation step --- .github/workflows/build.yml | 16 ---------------- bb-tests/sardine/tests/test_ctest.py | 2 +- bebop | 2 +- flake.nix | 1 + scripts/nix/build-all.sh | 12 +++++++++--- scripts/nix/build-env-tools.nix | 25 +++++++++++++++++++++++++ 6 files changed, 37 insertions(+), 21 deletions(-) delete mode 100644 .github/workflows/build.yml diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml deleted file mode 100644 index 8210769d..00000000 --- a/.github/workflows/build.yml +++ /dev/null @@ -1,16 +0,0 @@ -# name: Build - -# on: -# pull_request: -# push: -# branches: [main] - -# jobs: -# build: -# name: Build -# runs-on: ubuntu-latest -# steps: -# - uses: actions/checkout@v4 -# - uses: DeterminateSystems/determinate-nix-action@v3 -# - name: Build Buckyball -# run: ./scripts/nix/build-all.sh diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 87571193..ca725f9d 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -95,7 +95,7 @@ def test_ctest_workload_debug( time.sleep(test_index * 20) start_time = time.time() - command = f'source {sardine_dir}/../../env.sh && bbdev verilator --sim "--binary {workload_path} --batch"' + command = f'nix develop -c bbdev verilator --sim "--binary {workload_path} --batch"' logging.info(f"Running command: {command}") # 使用 command_run 执行命令，带提前退出检测 diff --git a/bebop b/bebop index 6ed2be07..71a0017d 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 6ed2be07e6b5a3a88cd8592fb0c4517d86370002 +Subproject commit 71a0017dac242a802d4e353979cc7f2cb3eaa42e diff --git a/flake.nix b/flake.nix index 1b50cef5..20393d81 100644 --- a/flake.nix +++ b/flake.nix @@ -21,6 +21,7 @@ name = "buckyball-environment"; paths = with pkgs; [ tools.verilator + tools.dramsim2 # RISC-V toolchain riscv.riscv-embedded-gcc diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 9de46e34..f88ac42b 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -141,12 +141,18 @@ if run_step "3"; then fi if run_step "4"; then - begin_step "4" "bb-tests pre-compile sources" - bbdev workload --build + begin_step "4" "bebop install" + cd ${BBDIR}/bebop + ./scripts/install.sh fi if run_step "5"; then - begin_step "5" "pre-commit hooks installation" + begin_step "5" "bb-tests pre-compile sources" + bbdev workload --build +fi + +if run_step "6"; then + begin_step "6" "pre-commit hooks installation" pre-commit install fi diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index 285171ed..d45f4771 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -1,5 +1,28 @@ { pkgs }: +let + # DRAMSim2 from firesim (rev matches chipyard pin); -fPIC for PIE linking under Nix + dramsim2 = pkgs.stdenv.mkDerivation { + pname = "dramsim2"; + version = "2023-05-10"; + src = pkgs.fetchFromGitHub { + owner = "firesim"; + repo = "DRAMSim2"; + rev = "44322e2f935d7dac83b7adf8dd270b41a54c6acb"; + hash = "sha256-Vfb+MeWdUESc7gt6GhL6jBO1Uuvx8s1BdfhCikTyTh8="; + }; + buildPhase = '' + make CXXFLAGS="-DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -fPIC" libdramsim.a + ''; + installPhase = '' + runHook preInstall + mkdir -p $out/lib $out/include + cp libdramsim.a $out/lib/ + cp *.h $out/include/ + runHook postInstall + ''; + }; +in { # Pin to Verilator 5.022 2024-02-24 (nixpkgs-unstable ships 5.044) verilator = pkgs.verilator.overrideAttrs (old: { @@ -11,4 +34,6 @@ sourceRoot = "verilator-5.022"; doCheck = false; }); + + dramsim2 = dramsim2; } From 306977bf5aafa48cfe0b931679f5a9176f2da0c0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 16:19:41 +0800 Subject: [PATCH 104/238] [nix] feat: add pre-commit package to flake.nix fix: add proxy support --- .pre-commit-config.yaml | 11 ++- arch/src/csrc/include/utils/debug.h | 3 +- .../workloads/lib/bbhw/isa/27_matmul_ws.c | 2 +- bb-tests/workloads/lib/bbhw/isa/33_im2col.c | 2 +- bb-tests/workloads/lib/bbhw/isa/38_relu.c | 1 - .../workloads/lib/bbhw/isa/39_bbus_config.c | 8 +-- bb-tests/workloads/lib/bbhw/isa/40_nnlut.c | 6 +- bb-tests/workloads/lib/bbhw/isa/41_snn.c | 6 +- .../workloads/lib/bbhw/isa/42_abft_systolic.c | 4 +- bb-tests/workloads/lib/bbhw/isa/43_conv.c | 6 +- bb-tests/workloads/lib/bbhw/isa/44_cim.c | 9 +-- bb-tests/workloads/lib/bbhw/isa/45_transfer.c | 6 +- bb-tests/workloads/src/CTest/toy/relu_test.c | 72 ++++++++----------- .../workloads/src/CTest/toy/transpose_test.c | 68 +++++++++--------- .../models/LeNet/pytorch-lenet-train.py | 2 +- flake.nix | 2 + scripts/nix/build-all.sh | 2 + scripts/nix/build-env-python.nix | 5 +- scripts/nix/build-env-scala.nix | 2 +- scripts/pre-commit-hook.sh | 10 +++ 20 files changed, 119 insertions(+), 108 deletions(-) create mode 100755 scripts/pre-commit-hook.sh diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 46a33fc6..a37efc89 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -6,6 +6,7 @@ repos: hooks: - id: clang-format name: clang-format C++ code + language: system files: \.(cpp|hpp|cc|cxx|h|c|hxx)$ args: [--style=llvm] @@ -13,7 +14,7 @@ repos: rev: 24.10.0 hooks: - id: black - language_version: python3.10 + language: system # a comprehensive tool for checking the style and quality of Python code. # It combines three popular Python tools: @@ -24,6 +25,7 @@ repos: rev: 6.1.0 hooks: - id: flake8 + language: system args: - --max-line-length=120 # Adjust as per your style guide - --ignore=F821,F403,F405,F401,W503,E203,E402,E401,W605,E712,E711,F841 @@ -40,17 +42,22 @@ repos: rev: v5.0.0 hooks: - id: end-of-file-fixer + language: system - id: trailing-whitespace + language: system - id: check-merge-conflict + language: system - id: check-yaml + language: system - id: check-added-large-files + language: system # Scala formatting with scalafmt - repo: local hooks: - id: scalafmt name: Format Scala code with scalafmt - entry: bash -c 'cd arch && source ../env.sh && scalafmt --config .scalafmt.conf src/main/scala' + entry: bash -c 'cd arch && scalafmt --config .scalafmt.conf src/main/scala' language: system files: ^arch/src/main/scala/.*\.scala$ pass_filenames: false diff --git a/arch/src/csrc/include/utils/debug.h b/arch/src/csrc/include/utils/debug.h index cae3b151..8e97511f 100644 --- a/arch/src/csrc/include/utils/debug.h +++ b/arch/src/csrc/include/utils/debug.h @@ -88,7 +88,8 @@ // do { \ // if (!(cond)) { \ // printf(ASNI_FMT(format, ASNI_FG_RED) "\n", ## __VA_ARGS__), \ -// fflush(stdout), fprintf(stderr, ASNI_FMT(format, ASNI_FG_RED) "\n", ## __VA_ARGS__); \ +// fflush(stdout), fprintf(stderr, ASNI_FMT(format, ASNI_FG_RED) "\n", ## +// __VA_ARGS__); \ // extern FILE* log_fp; fflush(log_fp); \ // extern void assert_fail_msg(); \ // assert_fail_msg(); \ diff --git a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c index 15d6a238..f4322a20 100644 --- a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c +++ b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c @@ -8,7 +8,7 @@ #define bb_matmul_ws(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(ws_flag, 24, 24)), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(ws_flag, 24, 24)), \ BB_MATMUL_WS_FUNC7) #endif // _MATMUL_WS_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c index 8f5e795f..d8d98cf4 100644 --- a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c +++ b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c @@ -9,7 +9,7 @@ startcol) \ BUCKYBALL_INSTRUCTION_R_R( \ (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | FIELD(incol, 8, 12) | \ + (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | FIELD(incol, 8, 12) | \ FIELD(inrow, 13, 17) | FIELD(startcol, 23, 27) | \ FIELD(startrow, 28, 32)), \ BB_IM2COL_FUNC7) diff --git a/bb-tests/workloads/lib/bbhw/isa/38_relu.c b/bb-tests/workloads/lib/bbhw/isa/38_relu.c index af013bc6..c43fe509 100644 --- a/bb-tests/workloads/lib/bbhw/isa/38_relu.c +++ b/bb-tests/workloads/lib/bbhw/isa/38_relu.c @@ -11,4 +11,3 @@ BB_RELU_FUNC7) #endif // _BB_RELU_H_ - diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c index 16ca979c..c6f8f297 100644 --- a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c +++ b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c @@ -6,9 +6,9 @@ #define BB_BBUS_CONFIG_FUNC7 39 #define bb_bbus_config(src_bid, dst_bid, enable) \ - BUCKYBALL_INSTRUCTION_R_R(0, \ - (FIELD(src_bid,0, 5) | FIELD(dst_bid, 6, 11) | \ - FIELD(enable, 12, 12)), \ - BB_BBUS_CONFIG_FUNC7) + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(src_bid, 0, 5) | FIELD(dst_bid, 6, 11) | FIELD(enable, 12, 12)), \ + BB_BBUS_CONFIG_FUNC7) #endif // _BB_BBUS_CONFIG_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c index 354d4222..46f66599 100644 --- a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c +++ b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c @@ -5,9 +5,9 @@ #define BB_NNLUT_FUNC7 40 -#define bb_nnlut(op1_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), \ +#define bb_nnlut(op1_bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), \ BB_NNLUT_FUNC7) #endif // _BB_NNLUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_snn.c b/bb-tests/workloads/lib/bbhw/isa/41_snn.c index 2e832e20..5a04e86e 100644 --- a/bb-tests/workloads/lib/bbhw/isa/41_snn.c +++ b/bb-tests/workloads/lib/bbhw/isa/41_snn.c @@ -4,9 +4,9 @@ #include "isa.h" #define BB_SNN_FUNC7 41 -#define bb_snn(op1_bank_id, wr_bank_id, iter, threshold, leak_factor) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ +#define bb_snn(op1_bank_id, wr_bank_id, iter, threshold, leak_factor) \ + BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ + (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ FIELD(threshold, 24, 31) | \ FIELD(leak_factor, 32, 39)), \ BB_SNN_FUNC7) diff --git a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c index 564298bf..4692d0e6 100644 --- a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c +++ b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c @@ -4,9 +4,9 @@ #include "isa.h" #define BB_ABFT_SYSTOLIC_FUNC7 42 -#define bb_abft_systolic(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ +#define bb_abft_systolic(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_ABFT_SYSTOLIC_FUNC7) #endif // _BB_ABFT_SYSTOLIC_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_conv.c b/bb-tests/workloads/lib/bbhw/isa/43_conv.c index f3e37e86..444f0b18 100644 --- a/bb-tests/workloads/lib/bbhw/isa/43_conv.c +++ b/bb-tests/workloads/lib/bbhw/isa/43_conv.c @@ -5,11 +5,11 @@ #define BB_CONV_FUNC7 43 -#define bb_conv(ifmap_bank_id, weight_bank_id, ofmap_bank_id, iter, in_height, \ +#define bb_conv(ifmap_bank_id, weight_bank_id, ofmap_bank_id, iter, in_height, \ in_width, kernel_h, kernel_w) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(ifmap_bank_id, 0, 7) | FIELD(weight_bank_id, 8, 15)), \ - (FIELD(ofmap_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ + (FIELD(ifmap_bank_id, 0, 7) | FIELD(weight_bank_id, 8, 15)), \ + (FIELD(ofmap_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ FIELD(in_height, 24, 39) | FIELD(in_width, 40, 55) | \ FIELD(kernel_h, 56, 63)), \ BB_CONV_FUNC7) diff --git a/bb-tests/workloads/lib/bbhw/isa/44_cim.c b/bb-tests/workloads/lib/bbhw/isa/44_cim.c index 6f2d5468..e5ced73a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/44_cim.c +++ b/bb-tests/workloads/lib/bbhw/isa/44_cim.c @@ -4,11 +4,12 @@ #include "isa.h" #define BB_CIM_FUNC7 44 -#define bb_cim(op1_bank_id, op2_bank_id, result_bank_id, iter, rows, cols, op_type) \ +#define bb_cim(op1_bank_id, op2_bank_id, result_bank_id, iter, rows, cols, \ + op_type) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(result_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(rows, 24, 39) | \ - FIELD(cols, 40, 55) | FIELD(op_type, 56, 59)), \ + (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ + (FIELD(result_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ + FIELD(rows, 24, 39) | FIELD(cols, 40, 55) | FIELD(op_type, 56, 59)), \ BB_CIM_FUNC7) #endif // _BB_CIM_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c index a81252bf..ddaf7482 100644 --- a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c +++ b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c @@ -5,10 +5,10 @@ #define BB_TRANSFER_FUNC7 45 -#define bb_transfer(op1_bank_id, wr_bank_id, iter) \ +#define bb_transfer(op1_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(op1_bank_id, 0, 7), \ - (FIELD(wr_bank_id, 0, 7) | FIELD((iter > 1023 ? 1023 : iter), 8, 23)), \ + FIELD(op1_bank_id, 0, 7), \ + (FIELD(wr_bank_id, 0, 7) | FIELD((iter > 1023 ? 1023 : iter), 8, 23)), \ BB_TRANSFER_FUNC7) #endif // _BB_TRANSFER_H_ diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index 56aa97ed..db72b4c1 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -5,7 +5,7 @@ #include #include -#define DIM 16 // 强制 16x16 +#define DIM 16 // 强制 16x16 // ======================= // 固定输入矩阵（4行周期） @@ -13,65 +13,58 @@ static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))) = { // ---- Cycle 1 ---- // Row1 - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, // Row2 - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -17, -16, -15, -14, -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, // Row3 - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -27, -26, -25, -24, -23, -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, // Row4 - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + -37, -36, -35, -34, -33, -32, -31, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 2 ---- - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, -17, -16, -15, -14, + -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, + -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, + -31, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 3 ---- - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, -17, -16, -15, -14, + -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, + -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, + -31, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 4 ---- - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38 -}; + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, -17, -16, -15, -14, + -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, + -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, + -31, 30, 31, 32, 33, 34, 35, 36, 37, 38}; // ======================= // 直接写死 ReLU 结果 // ======================= static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { // ---- Cycle 1 ---- - 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, - 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, - 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, - 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 0, 0, 0, 0, 0, 0, 0, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 2 ---- - 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, - 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, - 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, - 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 0, 0, 0, 0, 0, 0, 0, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 3 ---- - 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, - 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, - 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, - 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 0, 0, 0, 0, 0, 0, 0, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 4 ---- - 0,0,0,0,0,0,0,0,1,2,3,4,5,6,7,8, - 0,0,0,0,0,0,0,10,11,12,13,14,15,16,17,18, - 0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28, - 0,0,0,0,0,0,0,30,31,32,33,34,35,36,37,38 -}; + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 0, 0, 0, 0, 0, 0, 0, 30, 31, 32, 33, 34, 35, 36, 37, 38}; static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); - // ======================= // HW ReLU Flow（保持不变） // ======================= @@ -91,7 +84,6 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { bb_mvout((uintptr_t)b, wr_bank_id, size, 1); } - // ======================= // 测试函数（去掉 CPU 计算） // ======================= @@ -109,11 +101,7 @@ int run_test(const char *test_name, elem_t *a, int size) { } } - -int test_relu(int seed) { - return run_test("ReLU", input_matrix, DIM); -} - +int test_relu(int seed) { return run_test("ReLU", input_matrix, DIM); } int main() { #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index 3c013913..377bc336 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -9,66 +9,64 @@ static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))) = { // ---- Cycle 1 ---- // Row1 - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, // Row2 - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, + -17, -16, -15, -14, -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, // Row3 - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, + -27, -26, -25, -24, -23, -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, // Row4 - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + -37, -36, -35, -34, -33, -32, -31, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 2 ---- - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, -17, -16, -15, -14, + -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, + -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, + -31, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 3 ---- - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38, + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, -17, -16, -15, -14, + -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, + -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, + -31, 30, 31, 32, 33, 34, 35, 36, 37, 38, // ---- Cycle 4 ---- - -7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8, - -17,-16,-15,-14,-13,-12,-11,10,11,12,13,14,15,16,17,18, - -27,-26,-25,-24,-23,-22,-21,20,21,22,23,24,25,26,27,28, - -37,-36,-35,-34,-33,-32,-31,30,31,32,33,34,35,36,37,38 -}; + -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, -17, -16, -15, -14, + -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, + -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, + -31, 30, 31, 32, 33, 34, 35, 36, 37, 38}; static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { // Row 1 of A^T (col 1 of A) - -7,-17,-27,-37, -7,-17,-27,-37, -7,-17,-27,-37, -7,-17,-27,-37, + -7, -17, -27, -37, -7, -17, -27, -37, -7, -17, -27, -37, -7, -17, -27, -37, // Row 2 - -6,-16,-26,-36, -6,-16,-26,-36, -6,-16,-26,-36, -6,-16,-26,-36, + -6, -16, -26, -36, -6, -16, -26, -36, -6, -16, -26, -36, -6, -16, -26, -36, // Row 3 - -5,-15,-25,-35, -5,-15,-25,-35, -5,-15,-25,-35, -5,-15,-25,-35, + -5, -15, -25, -35, -5, -15, -25, -35, -5, -15, -25, -35, -5, -15, -25, -35, // Row 4 - -4,-14,-24,-34, -4,-14,-24,-34, -4,-14,-24,-34, -4,-14,-24,-34, + -4, -14, -24, -34, -4, -14, -24, -34, -4, -14, -24, -34, -4, -14, -24, -34, // Row 5 - -3,-13,-23,-33, -3,-13,-23,-33, -3,-13,-23,-33, -3,-13,-23,-33, + -3, -13, -23, -33, -3, -13, -23, -33, -3, -13, -23, -33, -3, -13, -23, -33, // Row 6 - -2,-12,-22,-32, -2,-12,-22,-32, -2,-12,-22,-32, -2,-12,-22,-32, + -2, -12, -22, -32, -2, -12, -22, -32, -2, -12, -22, -32, -2, -12, -22, -32, // Row 7 - -1,-11,-21,-31, -1,-11,-21,-31, -1,-11,-21,-31, -1,-11,-21,-31, + -1, -11, -21, -31, -1, -11, -21, -31, -1, -11, -21, -31, -1, -11, -21, -31, // Row 8 - 0, 10, 20, 30, 0, 10, 20, 30, 0, 10, 20, 30, 0, 10, 20, 30, + 0, 10, 20, 30, 0, 10, 20, 30, 0, 10, 20, 30, 0, 10, 20, 30, // Row 9 - 1, 11, 21, 31, 1, 11, 21, 31, 1, 11, 21, 31, 1, 11, 21, 31, + 1, 11, 21, 31, 1, 11, 21, 31, 1, 11, 21, 31, 1, 11, 21, 31, // Row 10 - 2, 12, 22, 32, 2, 12, 22, 32, 2, 12, 22, 32, 2, 12, 22, 32, + 2, 12, 22, 32, 2, 12, 22, 32, 2, 12, 22, 32, 2, 12, 22, 32, // Row 11 - 3, 13, 23, 33, 3, 13, 23, 33, 3, 13, 23, 33, 3, 13, 23, 33, + 3, 13, 23, 33, 3, 13, 23, 33, 3, 13, 23, 33, 3, 13, 23, 33, // Row 12 - 4, 14, 24, 34, 4, 14, 24, 34, 4, 14, 24, 34, 4, 14, 24, 34, + 4, 14, 24, 34, 4, 14, 24, 34, 4, 14, 24, 34, 4, 14, 24, 34, // Row 13 - 5, 15, 25, 35, 5, 15, 25, 35, 5, 15, 25, 35, 5, 15, 25, 35, + 5, 15, 25, 35, 5, 15, 25, 35, 5, 15, 25, 35, 5, 15, 25, 35, // Row 14 - 6, 16, 26, 36, 6, 16, 26, 36, 6, 16, 26, 36, 6, 16, 26, 36, + 6, 16, 26, 36, 6, 16, 26, 36, 6, 16, 26, 36, 6, 16, 26, 36, // Row 15 - 7, 17, 27, 37, 7, 17, 27, 37, 7, 17, 27, 37, 7, 17, 27, 37, + 7, 17, 27, 37, 7, 17, 27, 37, 7, 17, 27, 37, 7, 17, 27, 37, // Row 16 - 8, 18, 28, 38, 8, 18, 28, 38, 8, 18, 28, 38, 8, 18, 28, 38 -}; + 8, 18, 28, 38, 8, 18, 28, 38, 8, 18, 28, 38, 8, 18, 28, 38}; static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { @@ -84,7 +82,7 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { bb_fence(); bb_transpose(op1_bank_id, op2_bank_id, size, 0); bb_fence(); - bb_mvout((uintptr_t)b,op2_bank_id, size, 1); + bb_mvout((uintptr_t)b, op2_bank_id, size, 1); } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { diff --git a/bb-tests/workloads/src/ModelTest/models/LeNet/pytorch-lenet-train.py b/bb-tests/workloads/src/ModelTest/models/LeNet/pytorch-lenet-train.py index 4ee9e3ed..b474a69b 100644 --- a/bb-tests/workloads/src/ModelTest/models/LeNet/pytorch-lenet-train.py +++ b/bb-tests/workloads/src/ModelTest/models/LeNet/pytorch-lenet-train.py @@ -52,7 +52,7 @@ loss.backward() optimizer.step() running_loss += loss.item() - print(f"Epoch {epoch+1}/{epochs} - Loss: {running_loss/len(train_loader)}") + print(f"Epoch {epoch + 1}/{epochs} - Loss: {running_loss / len(train_loader)}") # Save the complete model torch.save(model, "lenet-model.pth") diff --git a/flake.nix b/flake.nix index 20393d81..4fb36fcd 100644 --- a/flake.nix +++ b/flake.nix @@ -29,6 +29,8 @@ # python environment python.python3Packages + pkgs."pre-commit" + pkgs.clang-tools # clang-format for pre-commit (language: system) # Bebop dependencies (rust toolchain) bebop.rustc diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index f88ac42b..d796ba07 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -154,6 +154,8 @@ fi if run_step "6"; then begin_step "6" "pre-commit hooks installation" pre-commit install + # Replace with wrapper so git commit gets nix env (result/bin in PATH) + cp "${BBDIR}/scripts/pre-commit-hook.sh" "${BBDIR}/.git/hooks/pre-commit" fi begin_step "END" "Setup completed successfully!" diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix index 0c7feec6..d113b47e 100644 --- a/scripts/nix/build-env-python.nix +++ b/scripts/nix/build-env-python.nix @@ -13,8 +13,11 @@ redis httpx-sse requests + pysocks - # pre-commit hooks + # pre-commit hooks (language: system use) + black + flake8 pre-commit-hooks # compiler diff --git a/scripts/nix/build-env-scala.nix b/scripts/nix/build-env-scala.nix index 3eb6af55..d7f7cd43 100644 --- a/scripts/nix/build-env-scala.nix +++ b/scripts/nix/build-env-scala.nix @@ -28,7 +28,7 @@ in # Build tool for Scala, Java and more inherit mill; - # sbt 1.8.2 + # sbt 1.8.2 sbt = (pkgs.sbt.override { jre = pkgs.jdk17; }).overrideAttrs (old: { version = "1.8.2"; src = pkgs.fetchurl { diff --git a/scripts/pre-commit-hook.sh b/scripts/pre-commit-hook.sh new file mode 100755 index 00000000..4591db8c --- /dev/null +++ b/scripts/pre-commit-hook.sh @@ -0,0 +1,10 @@ +#!/usr/bin/env bash +# Wrapper to run pre-commit with Nix env (result/bin in PATH). +# Git hooks run without nix develop, so we must load the env manually. + +HERE="$(cd "$(dirname "$0")" && pwd)" +REPO_ROOT="${HERE}/../.." +export PATH="${REPO_ROOT}/result/bin:${PATH}" + +exec pre-commit hook-impl --config="${REPO_ROOT}/.pre-commit-config.yaml" \ + --hook-type=pre-commit --hook-dir "$HERE" -- "$@" From af9f85f30e058d40f3a62a6ab43605e419ce3b70 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Feb 2026 16:27:27 +0800 Subject: [PATCH 105/238] [scripts] fix: replace bbdev env with nix --- scripts/nix/build-all.sh | 12 ++++++------ scripts/nix/build-env-python.nix | 1 + 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index d796ba07..43c4f224 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -92,14 +92,14 @@ fi if run_step "1"; then begin_step "1" "bbdev install" + # Create python_modules venv FIRST (uses Nix Python with pydantic/requests) + # Motia postinstall would run pip install -> SOCKS proxy fails. Use Nix instead. + echo "Setting up bbdev Python environment (from Nix)..." + python3 -m venv --without-pip --system-site-packages "${BBDIR}/bbdev/api/python_modules" + echo "Installing bbdev node dependencies..." cd ${BBDIR}/bbdev/api - pnpm install --frozen-lockfile 2>/dev/null || pnpm install - - # Setup python_modules for Motia - # Python deps are managed by Nix (overlay.nix), just need the venv structure - echo "Setting up bbdev Python environment..." - python3 -m venv --without-pip --system-site-packages "${BBDIR}/bbdev/api/python_modules" + pnpm install --ignore-scripts --frozen-lockfile 2>/dev/null || pnpm install --ignore-scripts fi if run_step "2"; then diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix index d113b47e..cebbaf52 100644 --- a/scripts/nix/build-env-python.nix +++ b/scripts/nix/build-env-python.nix @@ -7,6 +7,7 @@ # Python packages python3Packages = pkgs.python3.withPackages (ps: with ps; [ # bbdev + pydantic python-dotenv httpx mcp From 2e2e7d9a16b8d52c53e885dcc01cc836349a5586 Mon Sep 17 00:00:00 2001 From: Shiroha Date: Sun, 15 Feb 2026 15:30:18 +0800 Subject: [PATCH 106/238] [doc] update README.md --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 0dea00bd..e383591d 100644 --- a/README.md +++ b/README.md @@ -21,8 +21,8 @@ The buckyball framework provides a complete hardware design, simulation verifica ## Quick Start -### Installation in nix -We use Nix Flake as our mainly build system. If you have not installed nix, install it following the [guide](https://nix.dev/manual/nix/2.28/installation/installing-binary.html), and enable flake following the [wiki](https://nixos.wiki/wiki/Flakes#Enable_flakes). Or you can try the [installer](https://github.com/DeterminateSystems/nix-installer) provided by Determinate Systems, which enables flake by default. +### Installation in Nix +We use Nix Flake as our main build system. If you have not installed nix, install it following the [guide](https://nix.dev/manual/nix/2.28/installation/installing-binary.html), and enable flake following the [wiki](https://nixos.wiki/wiki/Flakes#Enable_flakes). Or you can try the [installer](https://github.com/DeterminateSystems/nix-installer) provided by Determinate Systems, which enables flake by default. **1. Clone Repository** From b8046e2adab649e3ce891228d5aca67bf2ad2b5d Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 15 Feb 2026 21:38:01 +0800 Subject: [PATCH 107/238] [scripts] fix: update condition for Nix installation check; [bbdev] fix: multithread kill bug --- bbdev | 2 +- scripts/nix/build-all.sh | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bbdev b/bbdev index a97a1977..c909e64b 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit a97a1977dcd125e3a4b89f0b2cb3a09a022cda0c +Subproject commit c909e64b41586314fa137ab8c0ee3a53f184da4a diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 43c4f224..a09cfc32 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -81,7 +81,7 @@ begin_step "0-2" "Nix environment setup" cd ${BBDIR} nix build -if [ "${INSTALL_IN_NIX}" = "0" ]; then +if [ "${INSTALL_IN_NIX}" != "1" ]; then SKIP_ARGS="" for skip in "${SKIP_LIST[@]}"; do SKIP_ARGS="${SKIP_ARGS} -s ${skip}" @@ -99,7 +99,7 @@ if run_step "1"; then echo "Installing bbdev node dependencies..." cd ${BBDIR}/bbdev/api - pnpm install --ignore-scripts --frozen-lockfile 2>/dev/null || pnpm install --ignore-scripts + pnpm install --ignore-scripts --frozen-lockfile 2>/dev/null fi if run_step "2"; then From 38be7dfa58dbc227a23eedb2a125065a00ee859c Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 26 Feb 2026 02:02:28 +0800 Subject: [PATCH 108/238] [bbdev] fix: bump to fix ci bug [bb-tests] fix: configure virtual banks for memory operations --- bb-tests/sardine/pytest.ini | 6 +- bb-tests/sardine/run_tests.py | 168 +++++------------- bb-tests/sardine/tests/test_ctest.py | 2 +- .../workloads/src/CTest/toy/mvin_mvout_test.c | 9 +- .../workloads/src/CTest/toy/transfer_test.c | 3 + .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 4 + .../CTest/toy/vecunit_matmul_16xn_random1.c | 10 +- .../CTest/toy/vecunit_matmul_16xn_random2.c | 4 + .../CTest/toy/vecunit_matmul_16xn_random3.c | 4 + .../toy/vecunit_matmul_16xn_zero_random.c | 4 + .../CTest/toy/vecunit_matmul_col_row_vector.c | 4 + .../toy/vecunit_matmul_identity_random.c | 4 + .../src/CTest/toy/vecunit_matmul_random1.c | 4 + .../src/CTest/toy/vecunit_matmul_random2.c | 4 + .../src/CTest/toy/vecunit_matmul_random3.c | 4 + .../CTest/toy/vecunit_matmul_zero_random.c | 4 + .../toy/vecunit_simple_nn_forward_pass_test.c | 4 + bbdev | 2 +- flake.nix | 1 + scripts/nix/build-env-bbdev.nix | 2 + scripts/nix/build-env-python.nix | 1 + 21 files changed, 116 insertions(+), 132 deletions(-) diff --git a/bb-tests/sardine/pytest.ini b/bb-tests/sardine/pytest.ini index 389d4deb..13e49a22 100644 --- a/bb-tests/sardine/pytest.ini +++ b/bb-tests/sardine/pytest.ini @@ -20,10 +20,10 @@ addopts = --log-file-level=DEBUG --log-cli-level=INFO --capture=no - # Allure 配置（当使用 --allure 时） -# --alluredir=reports/allure-results -# --clean-alluredir + --alluredir=reports/allure-results + --clean-alluredir + # 测试标记定义 markers = diff --git a/bb-tests/sardine/run_tests.py b/bb-tests/sardine/run_tests.py index 88096914..d008d69d 100644 --- a/bb-tests/sardine/run_tests.py +++ b/bb-tests/sardine/run_tests.py @@ -29,39 +29,7 @@ def get_git_commit(): return "unknown" -def check_allure_installed(): - """Check if Allure command line tool is installed.""" - try: - result = subprocess.run(["allure", "--version"], capture_output=True, text=True) - return result.returncode == 0 - except FileNotFoundError: - return False - - -def install_allure(): - """Install Allure command line tool.""" - print("Installing Allure command line tool...") - try: - # Try installing using npm - result = subprocess.run( - ["npm", "install", "-g", "allure-commandline"], - capture_output=True, - text=True, - ) - if result.returncode == 0: - print("Allure installed successfully via npm") - return True - except FileNotFoundError: - pass - - print("Please install Allure manually:") - print(" npm install -g allure-commandline") - print(" or") - print(" https://docs.qameta.io/allure/#_installing_a_commandline") - return False - - -def run_pytest(args=None, use_allure=False): +def run_pytest(args=None): """Run pytest with given arguments.""" args = args or [] @@ -78,19 +46,11 @@ def run_pytest(args=None, use_allure=False): # Build pytest command cmd = ["python3", "-m", "pytest", "-s", "-v", "-n", "auto"] - # 检查 Allure 是否已安装 - if use_allure: - if not check_allure_installed(): - if not install_allure(): - print("Falling back to default HTML report") - use_allure = False - - # Allure 配置 - if use_allure: - allure_results_dir = reports_dir / "allure-results" - allure_results_dir.mkdir(exist_ok=True) - cmd.extend(["--alluredir", str(allure_results_dir), "--clean-alluredir"]) - print(f"Allure results will be saved to: {allure_results_dir}") + # Allure 配置 + allure_results_dir = reports_dir / "allure-results" + allure_results_dir.mkdir(exist_ok=True) + cmd.extend(["--alluredir", str(allure_results_dir), "--clean-alluredir"]) + print(f"Allure results will be saved to: {allure_results_dir}") cmd.extend(args) @@ -98,84 +58,55 @@ def run_pytest(args=None, use_allure=False): print(f"Working directory: {script_dir}") print(f"Git commit: {git_commit}") - # Run pytest - try: - result = subprocess.run(cmd, cwd=script_dir) - - # Process reports whether tests succeed or fail - if use_allure: - # Generate Allure report - allure_results_dir = reports_dir / "allure-results" - allure_report_dir = reports_dir / f"{git_commit}" - current_report_dir = reports_dir / "allure" - - print("Generating Allure report...") + result = subprocess.run(cmd, cwd=script_dir) + # Process reports whether tests succeed or fail + # Generate Allure report + allure_results_dir = reports_dir / "allure-results" + allure_report_dir = reports_dir / f"{git_commit}" + current_report_dir = reports_dir / "allure" + print("Generating Allure report...") + # Generate versioned report + allure_cmd = [ + "allure", + "generate", + str(allure_results_dir), + "-o", + str(allure_report_dir), + "--clean", + ] + allure_result = subprocess.run(allure_cmd, cwd=script_dir) + if allure_result.returncode == 0: + # Generate current run report (saved in allure directory) + current_cmd = [ + "allure", + "generate", + str(allure_results_dir), + "-o", + str(current_report_dir), + "--clean", + ] + current_result = subprocess.run(current_cmd, cwd=script_dir) + print("Generated Allure reports:") + print(f" - {allure_results_dir} (raw results)") + print(f" - {allure_report_dir} (versioned HTML report)") + if current_result.returncode == 0: + print(f" - {current_report_dir} (current HTML report)") + return result.returncode - # Generate versioned report - allure_cmd = [ - "allure", - "generate", - str(allure_results_dir), - "-o", - str(allure_report_dir), - "--clean", - ] - allure_result = subprocess.run(allure_cmd, cwd=script_dir) - if allure_result.returncode == 0: - # Generate current run report (saved in allure directory) - current_cmd = [ - "allure", - "generate", - str(allure_results_dir), - "-o", - str(current_report_dir), - "--clean", - ] - - current_result = subprocess.run(current_cmd, cwd=script_dir) - - print("Generated Allure reports:") - print(f" - {allure_results_dir} (raw results)") - print(f" - {allure_report_dir} (versioned HTML report)") - if current_result.returncode == 0: - print(f" - {current_report_dir} (current HTML report)") - else: - print("Failed to generate Allure report") - - return result.returncode - except KeyboardInterrupt: - print("\nTest execution interrupted by user") - return 1 - except Exception as e: - print(f"Error running tests: {e}") - return 1 - - -def main(): - """Main entry point.""" +if __name__ == "__main__": if len(sys.argv) > 1: if sys.argv[1] in ["-h", "--help"]: print("Sardine Test Runner with Allure Support") print() print("Usage:") print(" python run_tests.py [pytest arguments]") - print(" python run_tests.py --allure [pytest arguments]") print(" python run_tests.py --open-report") print() print("Examples:") print( " python run_tests.py # Run all tests with default HTML report" ) - print( - " python run_tests.py --allure # Run all tests with Allure report" - ) - print( - " python run_tests.py --allure -m smoke # Run smoke tests with Allure report" - ) - print( - " python run_tests.py --allure -m verilator # Run verilator tests with Allure report" - ) print( " python run_tests.py --open-report # Open latest Allure report in browser" ) @@ -202,15 +133,8 @@ def main(): print(" - Historical trends") print(" - Detailed failure analysis") print(" - Test categorization") - return 0 - - elif sys.argv[1] == "--allure": - # Pass all arguments after --allure to pytest - return run_pytest(sys.argv[2:], use_allure=True) - - # Pass all arguments to pytest (default uses HTML report) - return run_pytest(sys.argv[1:]) - - -if __name__ == "__main__": - sys.exit(main()) + sys.exit(0) + print("Test started") + result = run_pytest(sys.argv[1:]) + print(f"Test result: {result}") + sys.exit(result) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index ca725f9d..b9613579 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -95,7 +95,7 @@ def test_ctest_workload_debug( time.sleep(test_index * 20) start_time = time.time() - command = f'nix develop -c bbdev verilator --sim "--binary {workload_path} --batch"' + command = f'bbdev verilator --sim "--binary {workload_path} --batch"' logging.info(f"Running command: {command}") # 使用 command_run 执行命令，带提前退出检测 diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index 0f905da5..fc41a2a4 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -5,19 +5,22 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) +#define DIM (BANK_WIDTH / sizeof(elem_t)) // Test matrices static elem_t input_matrix[DIM * DIM] __attribute__((aligned(16))); static elem_t output_matrix[DIM * DIM] __attribute__((aligned(16))); int mvin_mvout_simple_test() { + uint32_t bank_id = 0; + bb_vbank_config(bank_id, 0, 1); + for (int i = 0; i < 4; i++) { init_u8_random_matrix(input_matrix, DIM, DIM, 111); - bb_mvin((uintptr_t)input_matrix, 0, DIM, 1); + bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); clear_u8_matrix(output_matrix, DIM, DIM); bb_fence(); - bb_mvout((uintptr_t)output_matrix, 0, DIM, 1); + bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); bb_fence(); if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { printf("Test mvin/mvout simple %d FAILED\n", i); diff --git a/bb-tests/workloads/src/CTest/toy/transfer_test.c b/bb-tests/workloads/src/CTest/toy/transfer_test.c index 7f27bdb6..5be0d6d8 100644 --- a/bb-tests/workloads/src/CTest/toy/transfer_test.c +++ b/bb-tests/workloads/src/CTest/toy/transfer_test.c @@ -21,6 +21,9 @@ void hw_transfer(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(wr_bank_id, 0, 1); + // Move input into scratchpad bank0, starting at offset 0, iterate size times // row-wise bb_mvin((uintptr_t)a, op1_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index dfb8fb7e..c1d338b5 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index f7fb0100..45631c54 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -17,10 +17,16 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, transpose_u8_matrix(a, a_transposed, DIM, 64); uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 380bb0b8..6fcad2a1 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index ef890762..b1cac57d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 3e9d0e0d..b7f87485 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index 8b9389d0..52373da3 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -24,6 +24,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 92f178ba..24332ae7 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index e64cf487..25932c73 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 55621053..1ee09174 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 27dd68c9..97c729c6 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index 960e554c..a0f92186 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -23,6 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index 03ffb4e5..a70fcfb2 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -66,6 +66,10 @@ void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, acc_bank_id, size << 2, 1); diff --git a/bbdev b/bbdev index c909e64b..61bcffdb 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit c909e64b41586314fa137ab8c0ee3a53f184da4a +Subproject commit 61bcffdb1b40c31f8458112adfee9435c4c0b35d diff --git a/flake.nix b/flake.nix index 4fb36fcd..c47543dd 100644 --- a/flake.nix +++ b/flake.nix @@ -42,6 +42,7 @@ bbdev.nodejs bbdev.pnpm bbdev.uv + bbdev.allure bbdev.gcc bbdev.gnumake bbdev.pkg-config diff --git a/scripts/nix/build-env-bbdev.nix b/scripts/nix/build-env-bbdev.nix index 72ab683e..f38471e8 100644 --- a/scripts/nix/build-env-bbdev.nix +++ b/scripts/nix/build-env-bbdev.nix @@ -7,6 +7,8 @@ # UV (motia install uses it for Python deps; avoid auto-install via broken pip) uv = pkgs.uv; + # Allure CLI for sardine Allure reports + allure = pkgs.allure; # Build tools (for compiling native modules) gcc = pkgs.gcc; diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix index cebbaf52..41386472 100644 --- a/scripts/nix/build-env-python.nix +++ b/scripts/nix/build-env-python.nix @@ -15,6 +15,7 @@ httpx-sse requests pysocks + allure-pytest # pre-commit hooks (language: system use) black From 6322afa1a3243ec1e9fbef55146428d345bea761 Mon Sep 17 00:00:00 2001 From: sjm Date: Thu, 26 Feb 2026 23:23:34 +0800 Subject: [PATCH 109/238] [arch] Simplify MemMidend --- .../prototype/vector/VecLoadUnit.scala | 106 +++---- .../memdomain/midend/MemMidend.scala | 261 +++++------------- .../src/CTest/toy/vecunit_matmul_ones.c | 6 +- 3 files changed, 124 insertions(+), 249 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 8fa0c28e..41f78193 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -45,8 +45,8 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) - val mode = RegInit(0.U(1.W)) + val op1_iter_counter = RegInit(0.U(10.W)) + val op2_iter_counter = RegInit(0.U(10.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) val ld_ex_valid_reg = RegInit(false.B) @@ -54,6 +54,9 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_iter_reg = RegInit(0.U(10.W)) + val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) + val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) + for (i <- 0 until inBW) { io.bankReadReq(i).valid := false.B io.bankReadReq(i).bits.addr := 0.U @@ -63,82 +66,65 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.op2_bank_o := op2_bank io.ctrl_ld_i.ready := state === idle + bankRespQueue0.io.enq <> io.bankReadResp(0) + bankRespQueue1.io.enq <> io.bankReadResp(1) + // ----------------------------------------------------------------------------- // Set registers when Ctrl instruction arrives // ----------------------------------------------------------------------------- - when(io.ctrl_ld_i.fire) { - op1_bank := io.ctrl_ld_i.bits.op1_bank - op2_bank := io.ctrl_ld_i.bits.op2_bank - op1_addr := io.ctrl_ld_i.bits.op1_bank_addr - op2_addr := io.ctrl_ld_i.bits.op2_bank_addr - iter := io.ctrl_ld_i.bits.iter - iter_counter := 0.U - state := busy - mode := io.ctrl_ld_i.bits.mode + op1_bank := io.ctrl_ld_i.bits.op1_bank + op2_bank := io.ctrl_ld_i.bits.op2_bank + op1_addr := io.ctrl_ld_i.bits.op1_bank_addr + op2_addr := io.ctrl_ld_i.bits.op2_bank_addr + iter := io.ctrl_ld_i.bits.iter + op1_iter_counter := 0.U + op2_iter_counter := 0.U + state := busy assert(io.ctrl_ld_i.bits.iter > 0.U, "iter should be greater than 0") } - io.bankReadResp.foreach { resp => - resp.ready := state === busy - } - when(mode === 0.U) { + // ----------------------------------------------------------------------------- // Send SRAM read request // ----------------------------------------------------------------------------- - when(state === busy && io.ld_ex_o.ready) { - io.bankReadReq(0).valid := iter_counter < iter - io.bankReadReq(0).bits.addr := op1_addr + iter_counter - io.bankReadReq(1).valid := iter_counter < iter - io.bankReadReq(1).bits.addr := op2_addr + iter_counter - iter_counter := Mux(io.bankReadReq(0).ready && io.bankReadReq(1).ready, iter_counter + 1.U, iter_counter) - } + when(state === busy && io.ld_ex_o.ready) { + io.bankReadReq(0).valid := op1_iter_counter < iter + io.bankReadReq(0).bits.addr := op1_addr + op1_iter_counter + io.bankReadReq(1).valid := op1_iter_counter < iter + io.bankReadReq(1).bits.addr := op2_addr + op1_iter_counter + op1_iter_counter := Mux(io.bankReadReq(0).ready, op1_iter_counter + 1.U, op1_iter_counter) + op2_iter_counter := Mux(io.bankReadReq(1).ready, op2_iter_counter + 1.U, op2_iter_counter) + } // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- - when(io.bankReadResp(0).valid && io.bankReadResp(1).valid) { - io.ld_ex_o.valid := true.B - io.ld_ex_o.bits.op1 := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - io.ld_ex_o.bits.op2 := io.bankReadResp(1).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - ld_ex_iter_reg := ld_ex_iter_reg + 1.U - io.ld_ex_o.bits.iter := ld_ex_iter_reg - }.otherwise { - io.ld_ex_o.valid := false.B - io.ld_ex_o.bits.iter := 0.U - io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - } - -// ----------------------------------------------------------------------------- -// Reset iter_counter and return to idle state -// ----------------------------------------------------------------------------- + val deq_ready = bankRespQueue0.io.deq.valid && bankRespQueue1.io.deq.valid + bankRespQueue0.io.deq.ready := deq_ready + bankRespQueue1.io.deq.ready := deq_ready - when(state === busy && ld_ex_iter_reg === iter && (!ld_ex_valid_reg || io.ld_ex_o.ready)) { - state := idle - iter_counter := 0.U - ld_ex_iter_reg := 0.U - } + when(deq_ready) { + io.ld_ex_o.valid := true.B + io.ld_ex_o.bits.op1 := bankRespQueue0.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.ld_ex_o.bits.op2 := bankRespQueue1.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + ld_ex_iter_reg := ld_ex_iter_reg + 1.U + io.ld_ex_o.bits.iter := ld_ex_iter_reg }.otherwise { io.ld_ex_o.valid := false.B + io.ld_ex_o.bits.iter := 0.U io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) - io.ld_ex_o.bits.iter := 0.U - when(state === busy && io.bankReadResp(0).valid) { - iter_counter := iter_counter + 1.U - ld_ex_op1_reg := io.bankReadResp(0).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - io.bankReadReq(1).valid := true.B - io.bankReadReq(1).bits.addr := op2_addr + iter_counter - } - when(state === busy && io.bankReadResp(1).valid && RegNext(io.bankReadResp(0).valid)) { - io.ld_ex_o.valid := true.B - io.ld_ex_o.bits.op1 := ld_ex_op1_reg - io.ld_ex_o.bits.op2 := io.bankReadResp(1).bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - io.ld_ex_o.bits.iter := iter_counter - 1.U - } - when(state === busy && iter_counter === iter) { - state := idle - iter_counter := 0.U - } + } + +// ----------------------------------------------------------------------------- +// Reset op1_iter_counter and return to idle state +// ----------------------------------------------------------------------------- + + when(state === busy && ld_ex_iter_reg === iter) { + state := idle + op1_iter_counter := 0.U + op2_iter_counter := 0.U + ld_ex_iter_reg := 0.U } } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index cc2b2d2b..dc371afe 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -2,20 +2,27 @@ package framework.memdomain.midend import chisel3._ import chisel3.util._ +import org.chipsalliance.cde.config.Parameters import framework.top.GlobalConfig import framework.balldomain.blink.{BankRead, BankWrite} -import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.memdomain.backend.MemRequestIO +/** + * MemMidend: Midend module for memory scheduling + * Connects MemFrontend to MemManager + * + * Basic direct connection: routes requests from frontend to backend channels + */ @instantiable class MemMidend(val b: GlobalConfig) extends Module { val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum - val numChannels = b.memDomain.bankChannel - 1 // Reserve one for frontend @public val io = IO(new Bundle { + // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { val bankRead = new BankRead(b) val bankWrite = new BankWrite(b) @@ -26,228 +33,106 @@ class MemMidend(val b: GlobalConfig) extends Module { val bankWrite = Vec(totalBallWrite, new BankWrite(b)) } + // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) }) // ----------------------------------------------------------------------------- - // Mapping table + // Mapping table for tracking balldomain requests // ----------------------------------------------------------------------------- class MappingTableEntry extends Bundle { val valid = Bool() val isRead = Bool() - val id = UInt(log2Ceil(math.max(1, math.max(totalBallRead, totalBallWrite))).W) + val id = UInt(log2Ceil(math.max(totalBallRead, totalBallWrite)).W) } - val mappingTable = RegInit(VecInit(Seq.fill(numChannels)(0.U.asTypeOf(new MappingTableEntry)))) + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel - 1)(0.U.asTypeOf(new MappingTableEntry)))) - // ----------------------------------------------------------------------------- - // Core logic: allocate + same-cycle bypass routing - // ----------------------------------------------------------------------------- - private val chSelW = math.max(1, log2Ceil(numChannels)) - - // Free mask at cycle start - val freeMask0 = VecInit(mappingTable.map(!_.valid)).asUInt - - // Detect existing mappings (logical port -> physical channel) - val readMapped = Wire(Vec(totalBallRead, Bool())) - val readMappedCh = Wire(Vec(totalBallRead, UInt(chSelW.W))) - for (rid <- 0 until totalBallRead) { - val hits = VecInit((0 until numChannels).map { ch => - mappingTable(ch).valid && mappingTable(ch).isRead && (mappingTable(ch).id === rid.U) - }) - readMapped(rid) := hits.asUInt.orR - if (numChannels == 1) readMappedCh(rid) := 0.U else readMappedCh(rid) := OHToUInt(hits) + def addEntry(idx: UInt, isRead: Bool, id: UInt): Unit = { + mappingTable(idx).valid := true.B + mappingTable(idx).isRead := isRead + mappingTable(idx).id := id } - val writeMapped = Wire(Vec(totalBallWrite, Bool())) - val writeMappedCh = Wire(Vec(totalBallWrite, UInt(chSelW.W))) - for (wid <- 0 until totalBallWrite) { - val hits = VecInit((0 until numChannels).map { ch => - mappingTable(ch).valid && !mappingTable(ch).isRead && (mappingTable(ch).id === wid.U) - }) - writeMapped(wid) := hits.asUInt.orR - if (numChannels == 1) writeMappedCh(wid) := 0.U else writeMappedCh(wid) := OHToUInt(hits) + def allocateChannel(): UInt = { + val freeChannels = mappingTable.map(entry => !entry.valid) + PriorityEncoder(freeChannels) } - // Allocate unmapped requests onto free channels (combinational chaining, deterministic priority) - val readAlloc = Wire(Vec(totalBallRead, Bool())) - val readAllocCh = Wire(Vec(totalBallRead, UInt(chSelW.W))) - for (i <- 0 until totalBallRead) { readAlloc(i) := false.B; readAllocCh(i) := 0.U } - - val writeAlloc = Wire(Vec(totalBallWrite, Bool())) - val writeAllocCh = Wire(Vec(totalBallWrite, UInt(chSelW.W))) - for (i <- 0 until totalBallWrite) { writeAlloc(i) := false.B; writeAllocCh(i) := 0.U } + def isAllocated(isRead: Bool, id: UInt): Bool = + mappingTable.map(entry => entry.valid && entry.isRead === isRead && entry.id === id).reduce(_ || _) - var freeMask = freeMask0 + for (i <- 0 until totalBallRead) { + //Default values + io.balldomain.bankRead(i).io.req.ready := false.B + io.balldomain.bankRead(i).io.resp.valid := false.B; + io.balldomain.bankRead(i).io.resp.bits := DontCare - for (rid <- 0 until totalBallRead) { - val canAlloc = io.balldomain.bankRead(rid).io.req.valid && !readMapped(rid) && freeMask.orR - val chosenCh = if (numChannels == 1) 0.U(chSelW.W) else PriorityEncoder(freeMask) - readAlloc(rid) := canAlloc - readAllocCh(rid) := chosenCh - freeMask = Mux(canAlloc, freeMask & ~(1.U(numChannels.W) << chosenCh), freeMask) - } - - for (wid <- 0 until totalBallWrite) { - val canAlloc = io.balldomain.bankWrite(wid).io.req.valid && !writeMapped(wid) && freeMask.orR - val chosenCh = if (numChannels == 1) 0.U(chSelW.W) else PriorityEncoder(freeMask) - writeAlloc(wid) := canAlloc - writeAllocCh(wid) := chosenCh - freeMask = Mux(canAlloc, freeMask & ~(1.U(numChannels.W) << chosenCh), freeMask) - } - - // ----------------------------------------------------------------------------- - // Backend Connection (static LHS, no dynamic LHS assigns) - // ----------------------------------------------------------------------------- - for (ch <- 0 until numChannels) { - io.mem_req(ch).read.req.valid := false.B - io.mem_req(ch).read.req.bits := DontCare - io.mem_req(ch).read.resp.ready := true.B - io.mem_req(ch).write.req.valid := false.B - io.mem_req(ch).write.req.bits := DontCare - io.mem_req(ch).write.resp.ready := true.B - io.mem_req(ch).bank_id := 0.U - io.mem_req(ch).acc_group_id := 0.U - } - - // Default resp to ports (each port gets muxed resp from its selected channel) - for (rid <- 0 until totalBallRead) { - io.balldomain.bankRead(rid).io.resp.valid := false.B - io.balldomain.bankRead(rid).io.resp.bits := DontCare - } - for (wid <- 0 until totalBallWrite) { - io.balldomain.bankWrite(wid).io.resp.valid := false.B - io.balldomain.bankWrite(wid).io.resp.bits := DontCare - } - - // Per-port selection: mapped channel wins; otherwise same-cycle allocated channel - val readActive = Wire(Vec(totalBallRead, Bool())) - val readSelCh = Wire(Vec(totalBallRead, UInt(chSelW.W))) - for (rid <- 0 until totalBallRead) { - readActive(rid) := readMapped(rid) || readAlloc(rid) - readSelCh(rid) := Mux(readMapped(rid), readMappedCh(rid), readAllocCh(rid)) - - val mappedReady = io.mem_req(readMappedCh(rid)).read.req.ready - val allocReady = io.mem_req(readAllocCh(rid)).read.req.ready - io.balldomain.bankRead(rid).io.req.ready := Mux( - readMapped(rid), - mappedReady, - Mux(readAlloc(rid), allocReady, false.B) - ) - - io.balldomain.bankRead(rid).io.resp.valid := readActive(rid) && io.mem_req(readSelCh(rid)).read.resp.valid - io.balldomain.bankRead(rid).io.resp.bits := io.mem_req(readSelCh(rid)).read.resp.bits - } - - val writeActive = Wire(Vec(totalBallWrite, Bool())) - val writeSelCh = Wire(Vec(totalBallWrite, UInt(chSelW.W))) - for (wid <- 0 until totalBallWrite) { - writeActive(wid) := writeMapped(wid) || writeAlloc(wid) - writeSelCh(wid) := Mux(writeMapped(wid), writeMappedCh(wid), writeAllocCh(wid)) - - val mappedReady = io.mem_req(writeMappedCh(wid)).write.req.ready - val allocReady = io.mem_req(writeAllocCh(wid)).write.req.ready - io.balldomain.bankWrite(wid).io.req.ready := Mux( - writeMapped(wid), - mappedReady, - Mux(writeAlloc(wid), allocReady, false.B) - ) - - io.balldomain.bankWrite(wid).io.resp.valid := writeActive(wid) && io.mem_req(writeSelCh(wid)).write.resp.valid - io.balldomain.bankWrite(wid).io.resp.bits := io.mem_req(writeSelCh(wid)).write.resp.bits - } - - // Per-channel serving: mapped first; if unmapped, allow same-cycle allocated request to bypass - val chServeReadMapped = Wire(Vec(numChannels, Bool())) - val chServeWriteMapped = Wire(Vec(numChannels, Bool())) - for (ch <- 0 until numChannels) { - chServeReadMapped(ch) := mappingTable(ch).valid && mappingTable(ch).isRead - chServeWriteMapped(ch) := mappingTable(ch).valid && !mappingTable(ch).isRead - } - - val chServeReadAlloc = Wire(Vec(numChannels, Bool())) - val chServeWriteAlloc = Wire(Vec(numChannels, Bool())) - val chAllocReadId = Wire(Vec(numChannels, UInt(log2Ceil(math.max(1, totalBallRead)).W))) - val chAllocWriteId = Wire(Vec(numChannels, UInt(log2Ceil(math.max(1, totalBallWrite)).W))) - for (ch <- 0 until numChannels) { - chServeReadAlloc(ch) := false.B - chServeWriteAlloc(ch) := false.B - chAllocReadId(ch) := 0.U - chAllocWriteId(ch) := 0.U - } - - for (rid <- 0 until totalBallRead) { - when(readAlloc(rid)) { - chServeReadAlloc(readAllocCh(rid)) := true.B - chAllocReadId(readAllocCh(rid)) := rid.U + when(io.balldomain.bankRead(i).io.req.valid && !isAllocated(true.B, i.U)) { + addEntry(allocateChannel(), true.B, i.U) } } - for (wid <- 0 until totalBallWrite) { - when(writeAlloc(wid)) { - chServeWriteAlloc(writeAllocCh(wid)) := true.B - chAllocWriteId(writeAllocCh(wid)) := wid.U - } - } - - for (ch <- 0 until numChannels) { - val serveMapped = mappingTable(ch).valid - val serveRead = chServeReadMapped(ch) || (!serveMapped && chServeReadAlloc(ch)) - val serveWrite = chServeWriteMapped(ch) || (!serveMapped && chServeWriteAlloc(ch)) - when(serveRead) { - val ridSel = Mux(chServeReadMapped(ch), mappingTable(ch).id, chAllocReadId(ch)) + for (i <- 0 until totalBallWrite) { + //Default values + io.balldomain.bankWrite(i).io.req.ready := false.B + io.balldomain.bankWrite(i).io.resp.valid := false.B; + io.balldomain.bankWrite(i).io.resp.bits := DontCare + //disable for now - io.mem_req(ch).read.req.valid := io.balldomain.bankRead(ridSel).io.req.valid - io.mem_req(ch).read.req.bits := io.balldomain.bankRead(ridSel).io.req.bits - io.mem_req(ch).read.resp.ready := io.balldomain.bankRead(ridSel).io.resp.ready - io.mem_req(ch).bank_id := io.balldomain.bankRead(ridSel).bank_id - io.mem_req(ch).acc_group_id := io.balldomain.bankRead(ridSel).acc_group_id - }.elsewhen(serveWrite) { - val widSel = Mux(chServeWriteMapped(ch), mappingTable(ch).id, chAllocWriteId(ch)) - - io.mem_req(ch).write.req.valid := io.balldomain.bankWrite(widSel).io.req.valid - io.mem_req(ch).write.req.bits := io.balldomain.bankWrite(widSel).io.req.bits - io.mem_req(ch).write.resp.ready := io.balldomain.bankWrite(widSel).io.resp.ready - io.mem_req(ch).bank_id := io.balldomain.bankWrite(widSel).bank_id - io.mem_req(ch).acc_group_id := io.balldomain.bankWrite(widSel).acc_group_id - } + when(io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U)) { + addEntry(allocateChannel(), false.B, i.U) + } } - // Commit mappingTable only when request actually fires into backend - for (rid <- 0 until totalBallRead) { - when(readAlloc(rid) && io.balldomain.bankRead(rid).io.req.fire) { - val ch = readAllocCh(rid) - mappingTable(ch).valid := true.B - mappingTable(ch).isRead := true.B - mappingTable(ch).id := rid.U - } - } - for (wid <- 0 until totalBallWrite) { - when(writeAlloc(wid) && io.balldomain.bankWrite(wid).io.req.fire) { - val ch = writeAllocCh(wid) - mappingTable(ch).valid := true.B - mappingTable(ch).isRead := false.B - mappingTable(ch).id := wid.U + //Connect balldomain to backend + for (i <- 0 until b.top.memBallChannelNum) { + //Default values + io.mem_req(i).read.req.valid := false.B + io.mem_req(i).read.req.bits := DontCare + io.mem_req(i).read.resp.ready := false.B + io.mem_req(i).write.req.valid := false.B + io.mem_req(i).write.req.bits := DontCare + io.mem_req(i).write.resp.ready := false.B + io.mem_req(i).bank_id := 0.U + io.mem_req(i).acc_group_id := 0.U + + val isRead = mappingTable(i).isRead + val ballRead = io.balldomain.bankRead(mappingTable(i).id).io + val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io + val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id + val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id + val acc_group_id = io.balldomain.bankWrite(mappingTable(i).id).acc_group_id + + when(mappingTable(i).valid) { + when(isRead) { + io.mem_req(i).read <> ballRead + io.mem_req(i).bank_id := rbank_id + io.mem_req(i).acc_group_id := acc_group_id + }.otherwise { + io.mem_req(i).write <> ballWrite + io.mem_req(i).bank_id := wbank_id + io.mem_req(i).acc_group_id := acc_group_id + } } } - // Connect frontend to the last channel - val frontendCh = b.top.memBallChannelNum - io.mem_req(frontendCh).write <> io.frontend.bankWrite.io - io.mem_req(frontendCh).read <> io.frontend.bankRead.io - io.mem_req(frontendCh).bank_id := Mux( + //Connect frontend to backend + io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io + io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io + io.mem_req(b.top.memBallChannelNum).bank_id := Mux( io.frontend.bankRead.io.req.valid, io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id ) - io.mem_req(frontendCh).acc_group_id := Mux( + io.mem_req(b.top.memBallChannelNum).acc_group_id := Mux( io.frontend.bankRead.io.req.valid, io.frontend.bankRead.acc_group_id, io.frontend.bankWrite.acc_group_id ) // Mapping table release - for (i <- 0 until numChannels) { + for (i <- 0 until b.top.memBallChannelNum - 1) { val releaseCounter = RegInit(0.U(5.W)) when(mappingTable(i).valid && !(io.mem_req(i).read.resp.valid || diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 6f83cc88..3ad9c169 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -38,8 +38,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - cpu_matmul(a, b, expected_matrix, size, size, size); + // cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); + /* if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; @@ -47,6 +48,7 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { printf("Test %s FAILED\n", test_name); return 0; } + */ } int test_ones() { @@ -61,6 +63,7 @@ int main() { #endif int passed = test_ones(); // printf("RS2:%x", (FIELD(0, 0, 4) | FIELD(16, 5, 14) | FIELD(1, 14, 33))); + /* if (passed) { printf("vecunit_matmul_ones test PASSED\n"); return 0; @@ -68,6 +71,7 @@ int main() { printf("vecunit_matmul_ones test FAILED\n"); return 1; } + */ #ifdef MULTICORE exit(0); #endif From 5c90ead90ad2e11394cb3a000076171249e4bd6d Mon Sep 17 00:00:00 2001 From: sjm Date: Fri, 27 Feb 2026 15:00:33 +0800 Subject: [PATCH 110/238] [arch] Remove channel_id in MemBackend mapping table --- .../scala/framework/memdomain/backend/MemBackend.scala | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 3a7c359a..f109d0f5 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -35,7 +35,6 @@ class MemBackend(val b: GlobalConfig) extends Module { val vbank_id = UInt(5.W) val is_acc = Bool() val acc_group_id = UInt(3.W) - val channel_id = UInt(log2Ceil(b.memDomain.bankChannel).W) } val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) @@ -54,7 +53,6 @@ class MemBackend(val b: GlobalConfig) extends Module { entry.vbank_id := vbank_id entry.is_acc := is_acc entry.acc_group_id := acc_group_id - entry.channel_id := 0.U } def deleteEntry(vbank_id: UInt): Unit = { @@ -63,7 +61,6 @@ class MemBackend(val b: GlobalConfig) extends Module { entry.vbank_id := 0.U entry.is_acc := false.B entry.acc_group_id := 0.U - entry.channel_id := 0.U } def getFreePbankId(): UInt = { @@ -132,14 +129,9 @@ class MemBackend(val b: GlobalConfig) extends Module { (!mappingTable(j).is_acc || (mappingTable(j).is_acc && (mappingTable(j).acc_group_id === io.mem_req(i).acc_group_id))) - // Hold connection for one extra cycle to cover SramBank's 1-cycle resp pulse. - // Gate the hold with the latched channel_id to avoid a different channel stealing the resp. - val hold_one = RegNext(hit_bank && req_valid, init = false.B) && (mappingTable(j).channel_id === i.U) + val hold_one = RegNext(hit_bank && req_valid, init = false.B) when((hit_bank && req_valid) || hold_one) { - when(hit_bank && req_valid) { - mappingTable(j).channel_id := i.U - } banks(j).io.sramRead <> accPipes(i).io.sramRead banks(j).io.sramWrite <> accPipes(i).io.sramWrite } From 1df991f97d76fa3efd88a86a46fc4c9f868be3ef Mon Sep 17 00:00:00 2001 From: sjm Date: Fri, 27 Feb 2026 18:29:23 +0800 Subject: [PATCH 111/238] [arch]Rewrite memset inst --- .../scala/examples/toy/ToyBuckyBall.scala | 6 ++-- .../framework/balldomain/blink/bank.scala | 2 +- .../balldomain/prototype/im2col/Im2col.scala | 4 +-- .../balldomain/prototype/relu/Relu.scala | 4 +-- .../prototype/transpose/Transpose.scala | 4 +-- .../balldomain/prototype/vector/VecUnit.scala | 6 ++-- .../memdomain/backend/MemBackend.scala | 30 +++++++++---------- .../memdomain/backend/accpipe/AccPipe.scala | 16 +++++----- .../outside_channel/MemConfiger.scala | 28 +++++++++-------- .../frontend/outside_channel/MemLoader.scala | 2 +- .../frontend/outside_channel/MemStorer.scala | 2 +- .../memdomain/midend/MemMidend.scala | 14 ++++----- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 14 ++++----- .../workloads/src/CTest/toy/mvin_mvout_test.c | 2 +- bb-tests/workloads/src/CTest/toy/relu_test.c | 4 +-- .../workloads/src/CTest/toy/transfer_test.c | 6 ++-- .../workloads/src/CTest/toy/transpose_test.c | 4 +-- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 7 ++--- .../CTest/toy/vecunit_matmul_16xn_random1.c | 7 ++--- .../CTest/toy/vecunit_matmul_16xn_random2.c | 7 ++--- .../CTest/toy/vecunit_matmul_16xn_random3.c | 7 ++--- .../toy/vecunit_matmul_16xn_zero_random.c | 7 ++--- .../CTest/toy/vecunit_matmul_col_row_vector.c | 7 ++--- .../toy/vecunit_matmul_identity_random.c | 7 ++--- .../src/CTest/toy/vecunit_matmul_ones.c | 16 +++++----- .../src/CTest/toy/vecunit_matmul_random1.c | 7 ++--- .../src/CTest/toy/vecunit_matmul_random2.c | 7 ++--- .../src/CTest/toy/vecunit_matmul_random3.c | 7 ++--- .../CTest/toy/vecunit_matmul_zero_random.c | 7 ++--- .../toy/vecunit_simple_nn_forward_pass_test.c | 7 ++--- 30 files changed, 116 insertions(+), 132 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index 3713f9d9..a85aa944 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -104,7 +104,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) - val acc_group_id = chiselTypeOf(ballDomain.bankRead(i).acc_group_id) + val group_id = chiselTypeOf(ballDomain.bankRead(i).group_id) val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) })) @@ -112,7 +112,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id - bankReadReqWithIds.bits.acc_group_id := ballDomain.bankRead(i).acc_group_id + bankReadReqWithIds.bits.group_id := ballDomain.bankRead(i).group_id bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready @@ -123,7 +123,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id - memDomain.io.ballDomain.bankRead(i).acc_group_id := bankReadReqQ.bits.acc_group_id + memDomain.io.ballDomain.bankRead(i).group_id := bankReadReqQ.bits.group_id bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready ballDomain.bankRead(i).io.resp <> memDomain.io.ballDomain.bankRead(i).io.resp diff --git a/arch/src/main/scala/framework/balldomain/blink/bank.scala b/arch/src/main/scala/framework/balldomain/blink/bank.scala index ff89c2f8..692261d3 100644 --- a/arch/src/main/scala/framework/balldomain/blink/bank.scala +++ b/arch/src/main/scala/framework/balldomain/blink/bank.scala @@ -23,7 +23,7 @@ trait HasBallId { trait HasAccGroupId { val b: GlobalConfig - val acc_group_id = Input(UInt(3.W)) + val group_id = Input(UInt(3.W)) } class BankRead(val b: GlobalConfig) extends Bundle with HasBankId with HasRobId with HasBallId with HasAccGroupId { diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index 67c262fc..564eb06e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -80,7 +80,7 @@ class Im2col(val b: GlobalConfig) extends Module { io.bankRead(i).bank_id := rbank_reg io.bankRead(i).rob_id := rob_id_reg io.bankRead(i).ball_id := 0.U - io.bankRead(i).acc_group_id := 0.U + io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B @@ -92,7 +92,7 @@ class Im2col(val b: GlobalConfig) extends Module { io.bankWrite(i).bank_id := wbank_reg io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).ball_id := 0.U - io.bankWrite(i).acc_group_id := 0.U + io.bankWrite(i).group_id := 0.U } // cmd interface default assignment io.cmdReq.ready := true.B diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 3addce84..e2c92496 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -87,11 +87,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { for (i <- 0 until inBW) { io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).acc_group_id := 0.U + io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).acc_group_id := 0.U + io.bankWrite(i).group_id := 0.U } io.cmdReq.ready := state === idle diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index 23265be0..c4871e15 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -89,7 +89,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.resp.ready := false.B io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).acc_group_id := 0.U + io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B @@ -99,7 +99,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.wmode := false.B io.bankWrite(i).io.resp.ready := false.B io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).acc_group_id := 0.U + io.bankWrite(i).group_id := 0.U } io.cmdReq.ready := (state === idle) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index 74923a14..cf1d7b86 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -72,10 +72,10 @@ class VecUnit(val b: GlobalConfig) extends Module { VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).io.resp if (i == 0) { io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o - io.bankRead(i).acc_group_id := 0.U + io.bankRead(i).group_id := 0.U } else if (i == 1) { io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o - io.bankRead(i).acc_group_id := 0.U + io.bankRead(i).group_id := 0.U } } @@ -95,7 +95,7 @@ class VecUnit(val b: GlobalConfig) extends Module { io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o io.bankWrite(i).io.req.bits.wmode := true.B - io.bankWrite(i).acc_group_id := i.U + io.bankWrite(i).group_id := i.U } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index f109d0f5..d863cfcf 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -12,7 +12,7 @@ class MemRequestIO(b: GlobalConfig) extends Bundle { val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend val read = Flipped(new SramReadIO(b)) // midend sends read req into backend val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val acc_group_id = Output(UInt(3.W)) + val group_id = Output(UInt(3.W)) } @instantiable @@ -33,34 +33,34 @@ class MemBackend(val b: GlobalConfig) extends Module { class MappingTableEntry extends Bundle { val valid = Bool() val vbank_id = UInt(5.W) - val is_acc = Bool() - val acc_group_id = UInt(3.W) + val is_multi = Bool() + val group_id = UInt(3.W) } val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) def isAcc(vbank_id: UInt): Bool = - mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && entry.is_acc).reduce(_ || _) + mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && entry.is_multi).reduce(_ || _) def addEntry( vbank_id: UInt, pbank_id: UInt, - is_acc: Bool, - acc_group_id: UInt + is_multi: Bool, + group_id: UInt ): Unit = { val entry = mappingTable(pbank_id) entry.valid := true.B entry.vbank_id := vbank_id - entry.is_acc := is_acc - entry.acc_group_id := acc_group_id + entry.is_multi := is_multi + entry.group_id := group_id } def deleteEntry(vbank_id: UInt): Unit = { val entry = mappingTable(vbank_id) entry.valid := false.B entry.vbank_id := 0.U - entry.is_acc := false.B - entry.acc_group_id := 0.U + entry.is_multi := false.B + entry.group_id := 0.U } def getFreePbankId(): UInt = { @@ -76,7 +76,7 @@ class MemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id - accPipes(i).io.mem_req.acc_group_id := io.mem_req(i).acc_group_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id // Bank-side defaults (only driven when a bank is actually connected) accPipes(i).io.sramRead.req.ready := false.B @@ -87,7 +87,7 @@ class MemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.sramWrite.resp.valid := false.B accPipes(i).io.sramWrite.resp.bits := DontCare - accPipes(i).io.is_acc := isAcc(io.mem_req(i).bank_id) + accPipes(i).io.is_multi := isAcc(io.mem_req(i).bank_id) } io.config.ready := true.B @@ -111,7 +111,7 @@ class MemBackend(val b: GlobalConfig) extends Module { when(io.config.valid) { when(io.config.bits.alloc) { val pbank_id = getFreePbankId() - addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_acc, io.config.bits.acc_group_id) + addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) }.otherwise { deleteEntry(io.config.bits.vbank_id) } @@ -126,8 +126,8 @@ class MemBackend(val b: GlobalConfig) extends Module { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid val hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && - (!mappingTable(j).is_acc || - (mappingTable(j).is_acc && (mappingTable(j).acc_group_id === io.mem_req(i).acc_group_id))) + (!mappingTable(j).is_multi || + (mappingTable(j).is_multi && (mappingTable(j).group_id === io.mem_req(i).group_id))) val hold_one = RegNext(hit_bank && req_valid, init = false.B) diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 16d6be70..b63ba7cc 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -31,10 +31,10 @@ class AccPipe(val b: GlobalConfig) extends Module { val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in val mem_req = Flipped(new MemRequestIO(b)) - val is_acc = Input(Bool()) + val is_multi = Input(Bool()) val busy = Output(Bool()) - val acc_group_id = Output(UInt(3.W)) + val group_id = Output(UInt(3.W)) val bank_id = Output(UInt(b.memDomain.bankNum.W)) }) @@ -45,17 +45,17 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramWrite <> io.mem_req.write //Read Acc - when(io.is_acc) { + when(io.is_multi) { io.sramRead.req.bits.addr := io.mem_req.read.req.bits.addr(log2Ceil(b.memDomain.bankEntries) - 1, 2) } - //Acc_group_id output - val acc_group_id_reg = RegInit(0.U(3.W)) + //group_id output + val group_id_reg = RegInit(0.U(3.W)) when(io.mem_req.read.req.valid || io.mem_req.write.req.valid) { - io.acc_group_id := io.mem_req.acc_group_id - acc_group_id_reg := io.mem_req.acc_group_id + io.group_id := io.mem_req.group_id + group_id_reg := io.mem_req.group_id }.otherwise { - io.acc_group_id := acc_group_id_reg + io.group_id := group_id_reg } //Bank_id output diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 4fc9e819..79b53ccb 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -8,9 +8,9 @@ import chisel3.experimental.hierarchy.{instantiable, public} class MemConfigerIO(val b: GlobalConfig) extends Bundle { val vbank_id = Output(UInt(8.W)) - val is_acc = Output(Bool()) + val is_multi = Output(Bool()) val alloc = Output(Bool()) - val acc_group_id = Output(UInt(3.W)) + val group_id = Output(UInt(3.W)) } @instantiable @@ -28,31 +28,33 @@ class MemConfiger(val b: GlobalConfig) extends Module { val idle :: config :: Nil = Enum(2) val state = RegInit(idle) - val is_acc_reg = RegInit(false.B) val alloc_reg = RegInit(false.B) + val row_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val counter = RegInit(0.U(4.W)) - io.config.bits.is_acc := false.B + io.config.bits.is_multi := false.B io.config.bits.alloc := false.B io.config.bits.vbank_id := 0.U(8.W) - io.config.bits.acc_group_id := 0.U(3.W) + io.config.bits.group_id := 0.U(3.W) io.config.valid := false.B io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) when(state === idle) { when(io.cmdReq.valid) { - when(io.cmdReq.bits.cmd.special(0)) { //is acc + when(io.cmdReq.bits.cmd.special(4, 0) > 1.U) { //is multi bank state := config - is_acc_reg := io.cmdReq.bits.cmd.special(0) - alloc_reg := io.cmdReq.bits.cmd.special(1) + row_reg := io.cmdReq.bits.cmd.special(4, 0) + col_reg := io.cmdReq.bits.cmd.special(9, 5) + alloc_reg := io.cmdReq.bits.cmd.special(10) vbank_id_reg := io.cmdReq.bits.cmd.bank_id rob_id_reg := io.cmdReq.bits.rob_id - }.otherwise { //not acc - io.config.bits.alloc := io.cmdReq.bits.cmd.special(1) + }.otherwise { //not multi bank + io.config.bits.alloc := io.cmdReq.bits.cmd.special(10) io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id io.config.valid := true.B @@ -62,11 +64,11 @@ class MemConfiger(val b: GlobalConfig) extends Module { } }.otherwise { - when(counter < 4.U) { - io.config.bits.is_acc := is_acc_reg + when(counter < row_reg) { + io.config.bits.is_multi := true.B io.config.bits.alloc := alloc_reg io.config.bits.vbank_id := vbank_id_reg - io.config.bits.acc_group_id := counter + io.config.bits.group_id := counter io.config.valid := true.B counter := counter + 1.U }.otherwise { diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index b909d384..71686b70 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -70,7 +70,7 @@ class MemLoader(val b: GlobalConfig) extends Module { io.bankWrite.rob_id := rob_id_reg io.bankWrite.bank_id := wr_bank_reg io.bankWrite.ball_id := 0.U - io.bankWrite.acc_group_id := 0.U + io.bankWrite.group_id := 0.U // cmdResp (Decoupled): hold valid until accepted io.cmdResp.valid := (state === s_done) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index ee205c3e..25532b17 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -89,7 +89,7 @@ class MemStorer(val b: GlobalConfig) extends Module { io.bankRead.rob_id := rob_id_reg io.bankRead.bank_id := target_bank io.bankRead.ball_id := 0.U - io.bankRead.acc_group_id := sram_row(1, 0) + io.bankRead.group_id := sram_row(1, 0) io.bankRead.io.req.valid := (state === s_issue_sram_req) io.bankRead.io.req.bits.addr := sram_row diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index dc371afe..e551465c 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -95,24 +95,24 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).write.req.bits := DontCare io.mem_req(i).write.resp.ready := false.B io.mem_req(i).bank_id := 0.U - io.mem_req(i).acc_group_id := 0.U + io.mem_req(i).group_id := 0.U val isRead = mappingTable(i).isRead val ballRead = io.balldomain.bankRead(mappingTable(i).id).io val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id - val acc_group_id = io.balldomain.bankWrite(mappingTable(i).id).acc_group_id + val group_id = io.balldomain.bankWrite(mappingTable(i).id).group_id when(mappingTable(i).valid) { when(isRead) { io.mem_req(i).read <> ballRead io.mem_req(i).bank_id := rbank_id - io.mem_req(i).acc_group_id := acc_group_id + io.mem_req(i).group_id := group_id }.otherwise { io.mem_req(i).write <> ballWrite io.mem_req(i).bank_id := wbank_id - io.mem_req(i).acc_group_id := acc_group_id + io.mem_req(i).group_id := group_id } } } @@ -125,10 +125,10 @@ class MemMidend(val b: GlobalConfig) extends Module { io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id ) - io.mem_req(b.top.memBallChannelNum).acc_group_id := Mux( + io.mem_req(b.top.memBallChannelNum).group_id := Mux( io.frontend.bankRead.io.req.valid, - io.frontend.bankRead.acc_group_id, - io.frontend.bankWrite.acc_group_id + io.frontend.bankRead.group_id, + io.frontend.bankWrite.group_id ) // Mapping table release diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index 483bd555..ecdaaee7 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -5,18 +5,14 @@ #define BB_MSET_FUNC7 23 -#define bb_mset(relase_en, bank_id, alloc_en, row, col) \ +#define bb_mset(bank_id, alloc, row, col) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(relase_en, 0, 0) | FIELD(bank_id, 1, 13)), \ - (FIELD(alloc_en, 0, 0) | FIELD(row, 1, 5) | FIELD(col, 6, 13)), \ + 0, \ + (FIELD(bank_id, 0, 4) | FIELD(row, 5, 9) | FIELD(col, 10, 14) | FIELD(alloc, 15, 15)) , \ BB_MSET_FUNC7) -#define bb_mem_release(bank_id) bb_mset(1, bank_id, 0, 0, 0); +#define bb_mem_release(bank_id) bb_mset(bank_id, 0, 0, 0); -#define bb_mem_alloc(bank_id, row, col) bb_mset(0, bank_id, 1, row, col) +#define bb_mem_alloc(bank_id, row, col) bb_mset(bank_id, 1, row, col) -#define bb_vbank_config(bank_id, is_acc, alloc) \ - BUCKYBALL_INSTRUCTION_R_R( \ - 0, FIELD(bank_id, 0, 4) | FIELD(is_acc, 5, 5) | FIELD(alloc, 6, 6), \ - BB_MSET_FUNC7) #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index fc41a2a4..2694693d 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -13,7 +13,7 @@ static elem_t output_matrix[DIM * DIM] __attribute__((aligned(16))); int mvin_mvout_simple_test() { uint32_t bank_id = 0; - bb_vbank_config(bank_id, 0, 1); + bb_mem_alloc(bank_id, 1, 1); for (int i = 0; i < 4; i++) { init_u8_random_matrix(input_matrix, DIM, DIM, 111); diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index db72b4c1..b22f4153 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -72,8 +72,8 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(wr_bank_id, 0, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/transfer_test.c b/bb-tests/workloads/src/CTest/toy/transfer_test.c index 5be0d6d8..63baefb3 100644 --- a/bb-tests/workloads/src/CTest/toy/transfer_test.c +++ b/bb-tests/workloads/src/CTest/toy/transfer_test.c @@ -21,9 +21,9 @@ void hw_transfer(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(wr_bank_id, 0, 1); - + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); + // Move input into scratchpad bank0, starting at offset 0, iterate size times // row-wise bb_mvin((uintptr_t)a, op1_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index 377bc336..193cf092 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -75,8 +75,8 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index c1d338b5..3dc3339f 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 45631c54..38bb4776 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -18,11 +18,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 6fcad2a1..160e44e4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index b1cac57d..41a4d82f 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index b7f87485..53e1927c 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -22,10 +22,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); - - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index 52373da3..a1d6a57b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -22,11 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 24332ae7..aeb0a94e 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -22,10 +22,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); - - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 3ad9c169..b1b1f34c 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -23,9 +23,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id // bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); @@ -38,9 +38,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - // cpu_matmul(a, b, expected_matrix, size, size, size); + cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - /* if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; @@ -48,7 +47,6 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { printf("Test %s FAILED\n", test_name); return 0; } - */ } int test_ones() { @@ -62,8 +60,8 @@ int main() { multicore(MULTICORE); #endif int passed = test_ones(); - // printf("RS2:%x", (FIELD(0, 0, 4) | FIELD(16, 5, 14) | FIELD(1, 14, 33))); - /* + + if (passed) { printf("vecunit_matmul_ones test PASSED\n"); return 0; @@ -71,7 +69,7 @@ int main() { printf("vecunit_matmul_ones test FAILED\n"); return 1; } - */ + #ifdef MULTICORE exit(0); #endif diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index 25932c73..33f86220 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 1ee09174..3cb931f9 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 97c729c6..88fbe3b4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index a0f92186..1d5a745d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -21,11 +21,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index a70fcfb2..03249a7a 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -64,11 +64,10 @@ void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); From dc0247b7b4ba64bc260ec4b516d416c19ee20254 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sat, 28 Feb 2026 20:53:48 +0800 Subject: [PATCH 112/238] [arch]fix:fix the bugs of im2col in decoding --- .../toy/balldomain/DomainDecoder.scala | 2 +- .../balldomain/prototype/im2col/Im2col.scala | 36 ++++++++++--------- bb-tests/workloads/lib/bbhw/isa/33_im2col.c | 12 +++---- .../workloads/src/CTest/toy/im2col_test.c | 24 +++++++++---- 4 files changed, 44 insertions(+), 30 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 10fd0b0b..ffd57717 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -76,7 +76,7 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { // Transpose only reads op1 and writes wr_bank; it does NOT consume op2. // Enabling op2 here can stall/abort when op2_bank defaults to op1_bank. TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), - IM2COL -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs2(7, 0), rs1(15, 8), rs2(15, 8), 3.U, rs2(63, 16)), + IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(15, 8), DITER, 3.U, rs2(63, 16)), CONCAT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) ) diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index 564eb06e..72963b3e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -95,7 +95,7 @@ class Im2col(val b: GlobalConfig) extends Module { io.bankWrite(i).group_id := 0.U } // cmd interface default assignment - io.cmdReq.ready := true.B + io.cmdReq.ready := state === idle io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := rob_id_reg @@ -136,14 +136,15 @@ class Im2col(val b: GlobalConfig) extends Module { // Read part of data, fill ConvertBuffer is(read) { // Send read request - when(reqcounter < krow_reg) { - reqcounter := reqcounter + 1.U - io.bankRead(rbank_reg).io.req.valid := true.B - io.bankRead(rbank_reg).io.req.bits.addr := raddr_reg + reqcounter + startrow_reg + io.bankRead(0).io.req.valid := reqcounter < krow_reg + io.bankRead(0).io.req.bits.addr := raddr_reg + reqcounter + startrow_reg + + when(io.bankRead(0).io.req.fire) { + reqcounter := reqcounter + 1.U } // Process read response and store in ConvertBuffer - when(io.bankRead(rbank_reg).io.resp.fire) { - ConvertBuffer(respcounter) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + when(io.bankRead(0).io.resp.fire) { + ConvertBuffer(respcounter) := io.bankRead(0).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) respcounter := respcounter + 1.U } // Determine whether to transition state @@ -154,11 +155,10 @@ class Im2col(val b: GlobalConfig) extends Module { is(read_and_convert) { // Move pointer when(colptr <= colmax && rowptr <= rowmax) { - colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) - io.bankWrite(wbank_reg).io.req.valid := true.B - io.bankWrite(wbank_reg).io.req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt - io.bankWrite(wbank_reg).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) - io.bankWrite(wbank_reg).io.req.bits.data := { + io.bankWrite(0).io.req.valid := true.B + io.bankWrite(0).io.req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) + io.bankWrite(0).io.req.bits.data := { val window = Wire(Vec(InputNum, UInt(inputWidth.W))) // Initialize all to 0 first @@ -184,15 +184,19 @@ class Im2col(val b: GlobalConfig) extends Module { // For example, for klen_reg=3, combine (00)(01)(02)(10)(11)(12)(20)(21)(22) Cat((0 until InputNum).map(i => window(i)).reverse) } + + when(io.bankWrite(0).io.req.fire) { + colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) + } } // Send read request early when(colptr === colmax - 1.U) { - io.bankRead(rbank_reg).io.req.valid := true.B - io.bankRead(rbank_reg).io.req.bits.addr := raddr_reg + krow_reg + rowptr + io.bankRead(0).io.req.valid := true.B + io.bankRead(0).io.req.bits.addr := raddr_reg + krow_reg + rowptr } // Process read response and store in ConvertBuffer - when(io.bankRead(rbank_reg).io.resp.fire) { - ConvertBuffer(rowcnt % krow_reg) := io.bankRead(rbank_reg).io.resp.bits.data.asTypeOf(Vec( + when(io.bankRead(0).io.resp.fire) { + ConvertBuffer(rowcnt % krow_reg) := io.bankRead(0).io.resp.bits.data.asTypeOf(Vec( InputNum, UInt(inputWidth.W) )) diff --git a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c index d8d98cf4..d885d5b4 100644 --- a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c +++ b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c @@ -7,11 +7,11 @@ #define bb_im2col(op1_bank_id, wr_bank_id, krow, kcol, inrow, incol, startrow, \ startcol) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | FIELD(incol, 8, 12) | \ - FIELD(inrow, 13, 17) | FIELD(startcol, 23, 27) | \ - FIELD(startrow, 28, 32)), \ - BB_IM2COL_FUNC7) + BUCKYBALL_INSTRUCTION_R_R( \ + (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ + (FIELD(kcol, 16, 19) | FIELD(krow, 20, 23) | FIELD(incol, 24, 28) | \ + FIELD(inrow, 29, 38) | FIELD(startcol, 39, 43) | \ + FIELD(startrow, 44, 53)), \ + BB_IM2COL_FUNC7) #endif // _BB_IM2COL_H_ diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 7b8be15f..630ec6a8 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -9,13 +9,17 @@ static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); -void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { +void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) +{ // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_vbank_config(op1_bank_id, 0, 1); + bb_vbank_config(op2_bank_id, 0, 1); + bb_vbank_config(acc_bank_id, 1, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); uint64_t krow = 4; @@ -33,24 +37,30 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ hw_im2col(test_name, a, b, size); return 1; } -int test_im2col() { +int test_im2col() +{ init_sequence_matrix(input_matrix_a, DIM, 32); return run_test("Im2col", input_matrix_a, output_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_im2col(); - if (passed) { + if (passed) + { printf("Im2col test PASSED\n"); - } else { + } + else + { printf("Im2col test FAILED\n"); } #ifdef MULTICORE From 3f36236e8e3b596310576902b1fa317505e7d0ba Mon Sep 17 00:00:00 2001 From: sjm Date: Sat, 28 Feb 2026 23:27:25 +0800 Subject: [PATCH 113/238] [arch] Fix some bugs, successfully running most workloads using VecBall --- .../prototype/vector/VecLoadUnit.scala | 35 +++++++++++++++++-- .../outside_channel/dma/StreamReader.scala | 2 +- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 13 ++++--- .../CTest/toy/vecunit_matmul_16xn_random1.c | 7 ++-- .../CTest/toy/vecunit_matmul_16xn_random2.c | 3 +- .../CTest/toy/vecunit_matmul_16xn_random3.c | 6 ++-- .../toy/vecunit_matmul_16xn_zero_random.c | 5 ++- .../CTest/toy/vecunit_matmul_col_row_vector.c | 2 +- .../toy/vecunit_matmul_identity_random.c | 2 +- .../src/CTest/toy/vecunit_matmul_random1.c | 24 +++++++------ .../src/CTest/toy/vecunit_matmul_random2.c | 3 +- .../src/CTest/toy/vecunit_matmul_random3.c | 23 ++++++------ .../CTest/toy/vecunit_matmul_row_col_vector.c | 1 - .../CTest/toy/vecunit_matmul_zero_random.c | 1 - .../toy/vecunit_simple_nn_forward_pass_test.c | 22 ++++++------ 15 files changed, 89 insertions(+), 60 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 41f78193..10962b7c 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -49,10 +49,13 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val op2_iter_counter = RegInit(0.U(10.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) - val ld_ex_valid_reg = RegInit(false.B) val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_iter_reg = RegInit(0.U(10.W)) + val wait1_reg = RegInit(false.B) + val wait2_reg = RegInit(false.B) + val wait1_cnt = RegInit(0.U(7.W)) + val wait2_cnt = RegInit(0.U(7.W)) val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) @@ -87,15 +90,41 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Send SRAM read request // ----------------------------------------------------------------------------- - when(state === busy && io.ld_ex_o.ready) { + //wait1_reg := Mux(io.run , 0.U, wait1_reg) + + //wait2_reg := Mux(io.run , 0.U, wait2_reg) + + when(state === busy && io.ld_ex_o.ready && !wait1_reg) { io.bankReadReq(0).valid := op1_iter_counter < iter io.bankReadReq(0).bits.addr := op1_addr + op1_iter_counter + op1_iter_counter := Mux(io.bankReadReq(0).ready, op1_iter_counter + 1.U, op1_iter_counter) + wait1_reg := Mux((op1_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) + } + + when(state === busy && io.ld_ex_o.ready && !wait2_reg) { io.bankReadReq(1).valid := op1_iter_counter < iter io.bankReadReq(1).bits.addr := op2_addr + op1_iter_counter - op1_iter_counter := Mux(io.bankReadReq(0).ready, op1_iter_counter + 1.U, op1_iter_counter) op2_iter_counter := Mux(io.bankReadReq(1).ready, op2_iter_counter + 1.U, op2_iter_counter) + wait2_reg := Mux((op2_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) } + when(wait1_reg){ + wait1_cnt := wait1_cnt + 1.U + when(wait1_cnt === 32.U){ + wait1_reg := false.B + wait1_cnt := 0.U + } + } + + when(wait2_reg){ + wait2_cnt := wait2_cnt + 1.U + when(wait2_cnt === 32.U){ + wait2_reg := false.B + wait2_cnt := 0.U + } + } + + // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index 621d0782..3cbf60bc 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -75,7 +75,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl.a.valid := io.tlb.resp.valid && - !inflight + !inflight && state =/= s_idle io.tl.a.bits := get io.tl.a.bits.address := io.tlb.resp.bits.paddr diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index 3dc3339f..dc1891ee 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -4,10 +4,10 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 -static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(16))); -static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(16))); +static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(64))); +static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -36,9 +36,8 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); - cpu_matmul(a, b, expected_matrix, DIM, DIM, size); hw_matmul(test_name, a, b, output_matrix, size); + cpu_matmul(a, b, expected_matrix, DIM, DIM, size); if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test %s PASSED\n", test_name); return 1; @@ -49,8 +48,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } int test_ones_16x32() { - init_ones_matrix(input_matrix_a, DIM, 32); - init_ones_matrix(input_matrix_b, 32, DIM); + init_sequence_matrix(input_matrix_a, DIM, 32); + init_sequence_matrix(input_matrix_b, 32, DIM); return run_test("All-ones matrices", input_matrix_a, input_matrix_b, 32); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 38bb4776..738b5c49 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -4,10 +4,10 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 -static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(16))); -static elem_t input_matrix_b[64 * DIM] __attribute__((aligned(16))); +static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(64))); +static elem_t input_matrix_b[64 * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -34,7 +34,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 160e44e4..ae4df30a 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(16))); static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(16))); @@ -36,7 +36,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index 41a4d82f..92472449 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -4,10 +4,10 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 -static elem_t input_matrix_a[DIM * 48] __attribute__((aligned(16))); -static elem_t input_matrix_b[48 * DIM] __attribute__((aligned(16))); +static elem_t input_matrix_a[DIM * 48] __attribute__((aligned(64))); +static elem_t input_matrix_b[48 * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 53e1927c..55d32be0 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -6,8 +6,8 @@ #define DIM (BANK_WIDTH / sizeof(elem_t)) -static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(16))); -static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(16))); +static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(64))); +static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); @@ -36,7 +36,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index a1d6a57b..989721b2 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 #include static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index aeb0a94e..fab897b4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index 33f86220..d585fdc5 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); @@ -15,19 +15,21 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id + // bb_mem_alloc(acc_bank_id, 1, 4); bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 4, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); @@ -36,7 +38,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { @@ -48,24 +49,27 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } } -int test_random1() { +int test_ones() { init_u8_random_matrix(input_matrix_a, DIM, DIM, 456); init_u8_random_matrix(input_matrix_b, DIM, DIM, 789); - return run_test("Random matrices 1", input_matrix_a, input_matrix_b, DIM); + return run_test("Random matrices", input_matrix_a, input_matrix_b, DIM); } int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - int passed = test_random1(); + int passed = test_ones(); + + if (passed) { - printf("vecunit_matmul_random1 test PASSED\n"); + printf("vecunit_matmul_random test PASSED\n"); return 0; } else { - printf("vecunit_matmul_random1 test FAILED\n"); + printf("vecunit_matmul_random test FAILED\n"); return 1; } + #ifdef MULTICORE exit(0); #endif diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 3cb931f9..6c8e7439 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); @@ -36,7 +36,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 88fbe3b4..7c332d1f 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); @@ -15,7 +15,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; @@ -26,8 +26,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 4, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_mvin((uintptr_t)a_transposed, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); bb_fence(); @@ -36,7 +37,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { @@ -48,24 +48,27 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } } -int test_random3() { +int test_random() { init_u8_random_matrix(input_matrix_a, DIM, DIM, 333); init_u8_random_matrix(input_matrix_b, DIM, DIM, 444); - return run_test("Random matrices 3", input_matrix_a, input_matrix_b, DIM); + return run_test("Random matrices", input_matrix_a, input_matrix_b, DIM); } int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - int passed = test_random3(); + int passed = test_random(); + + if (passed) { - printf("vecunit_matmul_random3 test PASSED\n"); + printf("vecunit_matmul_random test PASSED\n"); return 0; } else { - printf("vecunit_matmul_random3 test FAILED\n"); + printf("vecunit_matmul_random test FAILED\n"); return 1; } + #ifdef MULTICORE exit(0); #endif diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index bf522d6f..e720a568 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -34,7 +34,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index 1d5a745d..f8a13e18 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -37,7 +37,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index 03249a7a..0e2faf9b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 // Define neural network parameters #define INPUT_SIZE DIM @@ -114,16 +114,7 @@ int test_neural_network() { weights2[i] = rand() % 128; } - // Clear output buffers - clear_u32_matrix(hidden_output, DIM, DIM); - clear_u32_matrix(expected_output, DIM, DIM); - - // Generate expected results on CPU - printf("Running CPU Neural Network Forward Pass...\n"); - cpu_nn_forward(input_data, weights1, weights2, hidden_output, expected_output, - DIM); - - // Clear hidden_output again for hardware computation + // Clear hidden_output for hardware computation clear_u32_matrix(hidden_output, DIM, DIM); clear_u32_matrix(final_output, DIM, DIM); @@ -132,6 +123,15 @@ int test_neural_network() { hw_nn_forward(input_data, weights1, weights2, hidden_output, final_output, DIM); + // Clear output buffers + clear_u32_matrix(hidden_output, DIM, DIM); + clear_u32_matrix(expected_output, DIM, DIM); + + // Generate expected results on CPU + printf("Running CPU Neural Network Forward Pass...\n"); + cpu_nn_forward(input_data, weights1, weights2, hidden_output, expected_output, + DIM); + // Compare hardware output with expected output printf("Comparing hardware output with expected output...\n"); if (compare_u32_matrices(final_output, expected_output, DIM, DIM)) { From 53e2c934d811a22a4c34bc6dc2e35d718c16cfbb Mon Sep 17 00:00:00 2001 From: sjm Date: Sat, 28 Feb 2026 23:30:25 +0800 Subject: [PATCH 114/238] [arch] Fix some bugs in workloads --- .../workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c | 2 +- .../workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c | 2 +- bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 55d32be0..58bc8e26 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * 32] __attribute__((aligned(64))); static elem_t input_matrix_b[32 * DIM] __attribute__((aligned(64))); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index e720a568..9cbf1caf 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index f8a13e18..d30a70da 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -4,7 +4,7 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); From fd464d60adbd17922ed353278630e2e5fea34024 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 1 Mar 2026 04:29:38 +0800 Subject: [PATCH 115/238] [bb-tests] fix: replace virtual bank configuration with memory allocation in im2col test --- .../workloads/src/CTest/toy/im2col_test.c | 25 ++++++------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 630ec6a8..b6642815 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -9,16 +9,13 @@ static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(64))); static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); -void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) -{ +void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - int acc_bank_id = 2; // virtual bank id - bb_vbank_config(op1_bank_id, 0, 1); - bb_vbank_config(op2_bank_id, 0, 1); - bb_vbank_config(acc_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_fence(); @@ -37,30 +34,24 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { hw_im2col(test_name, a, b, size); return 1; } -int test_im2col() -{ +int test_im2col() { init_sequence_matrix(input_matrix_a, DIM, 32); return run_test("Im2col", input_matrix_a, output_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_im2col(); - if (passed) - { + if (passed) { printf("Im2col test PASSED\n"); - } - else - { + } else { printf("Im2col test FAILED\n"); } #ifdef MULTICORE From a21dfef2ea8ac7f5b5342ecca3a7861da45c2bd8 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 1 Mar 2026 08:51:25 +0800 Subject: [PATCH 116/238] [bb-tests] fix: fix bugs in mvin_mvout and relu tests --- bb-tests/sardine/tests/test_ctest.py | 4 ---- bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c | 8 ++++---- bb-tests/workloads/src/CTest/toy/relu_test.c | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index b9613579..a6f933cc 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -74,10 +74,6 @@ "ctest_relu_test_singlecore-baremetal", "ctest_relu_test_singlecore-baremetal", ), - ( - "ctest_transfer_test_singlecore-baremetal", - "ctest_transfer_test_singlecore-baremetal", - ), ] diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index 2694693d..62d55d4a 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -5,17 +5,17 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 // Test matrices -static elem_t input_matrix[DIM * DIM] __attribute__((aligned(16))); -static elem_t output_matrix[DIM * DIM] __attribute__((aligned(16))); +static elem_t input_matrix[DIM * DIM] __attribute__((aligned(128))); +static elem_t output_matrix[DIM * DIM] __attribute__((aligned(128))); int mvin_mvout_simple_test() { uint32_t bank_id = 0; bb_mem_alloc(bank_id, 1, 1); - for (int i = 0; i < 4; i++) { + for (int i = 0; i < 1; i++) { init_u8_random_matrix(input_matrix, DIM, DIM, 111); bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); clear_u8_matrix(output_matrix, DIM, DIM); diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index b22f4153..2331a10b 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -110,7 +110,7 @@ int main() { int passed = test_relu(5); if (passed) { - printf("ReLU test PASSED!!!\n"); + printf("ReLU test PASSED\n"); } else { printf("ReLU test FAILED\n"); } From c9d0df308b66206308ae57a49c3eba6410057710 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sun, 1 Mar 2026 12:11:46 +0800 Subject: [PATCH 117/238] [bb-tests]add:add transpose on ctest --- bb-tests/sardine/tests/test_ctest.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index a6f933cc..03c39e64 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -74,6 +74,10 @@ "ctest_relu_test_singlecore-baremetal", "ctest_relu_test_singlecore-baremetal", ), + ( + "ctest_transpose_test_singlecore-baremetal", + "ctest_transpose_test_singlecore-baremetal", + ), ] From 918fbcbb64da8ced617bbf04c8f1502dd16d85d6 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sun, 1 Mar 2026 12:19:46 +0800 Subject: [PATCH 118/238] [bb-tests]fix:fix bugs of ctests set --- .../workloads/src/CTest/toy/aligned_matmul.c | 31 ++++--- .../src/CTest/toy/bbfp_matmul_random1.c | 28 ++++-- .../src/CTest/toy/bbfp_matmul_random2.c | 28 ++++-- .../src/CTest/toy/bbfp_matmul_random3.c | 28 ++++-- bb-tests/workloads/src/CTest/toy/bbfpmatmul.c | 27 ++++-- bb-tests/workloads/src/CTest/toy/bbfptest.c | 29 ++++--- .../src/CTest/toy/mvin_mvout_acc_test.c | 27 ++++-- .../workloads/src/CTest/toy/tiled_matmul.c | 87 ++++++++++++------- .../src/CTest/toy/transpose_matmul.c | 31 ++++--- .../toy/vecunit_matmul_16xn_zero_random.c | 28 ++++-- .../toy/vecunit_matmul_identity_random.c | 27 ++++-- .../CTest/toy/vecunit_matmul_row_col_vector.c | 28 ++++-- 12 files changed, 268 insertions(+), 131 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index 2cfa465d..f732d2a4 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -18,18 +18,20 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 uint32_t col_stride = (size + DIM - 1) / DIM; - for (int i = 0; i < col_stride; i++) { + for (int i = 0; i < col_stride; i++) + { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, op2_bank_id, DIM << 2, 1); bb_fence(); @@ -42,20 +44,25 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *aligned_a, elem_t *a, elem_t *b, - int size) { + int size) +{ clear_u32_matrix(output_matrix, DIM, DIM); hw_matmul(test_name, aligned_a, b, output_matrix, size); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); - if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_aligned_matmul() { +int test_aligned_matmul() +{ init_col_aligned_random_matrix(aligned_input_matrix_a, input_matrix_a, DIM, DIM, MATMUL_COL, 111); init_u8_random_matrix(input_matrix_b, MATMUL_COL, DIM, 222); @@ -63,15 +70,19 @@ int test_aligned_matmul() { input_matrix_b, MATMUL_COL); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_aligned_matmul(); - if (passed) { + if (passed) + { printf("Aligned Matmul test PASSED\n"); return 0; - } else { + } + else + { printf("Aligned Matmul test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c index ae3f4fb2..dad61ee0 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c @@ -12,11 +12,12 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); @@ -26,33 +27,42 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(b, a, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_random1() { +int test_random1() +{ init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 456); init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 789); return run_test("Random matrices 1", input_matrix_a, input_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_random1(); - if (passed) { + if (passed) + { printf("bbfp_matmul_random1 test PASSED\n"); - } else { + } + else + { printf("bbfp_matmul_random1 test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c index 2eb65070..b992053c 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c @@ -12,11 +12,12 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); @@ -26,33 +27,42 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(b, a, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_random1() { +int test_random1() +{ init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 111); init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 222); return run_test("Random matrices 2", input_matrix_a, input_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_random1(); - if (passed) { + if (passed) + { printf("bbfp_matmul_random2 test PASSED\n"); - } else { + } + else + { printf("bbfp_matmul_random2 test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c index ec1430ef..95ffb3b9 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c @@ -12,11 +12,12 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); @@ -26,33 +27,42 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(b, a, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_random1() { +int test_random1() +{ init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 333); init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 444); return run_test("Random matrices 3", input_matrix_a, input_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_random1(); - if (passed) { + if (passed) + { printf("bbfp_matmul_random3 test PASSED\n"); - } else { + } + else + { printf("bbfp_matmul_random3 test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c index 7837e8c3..3ac907ab 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c +++ b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c @@ -8,16 +8,21 @@ #define DIM (BANK_WIDTH / sizeof(elem_t)) -void init_matrix(elem_t *matrix, int rows, int cols, int seed) { +void init_matrix(elem_t *matrix, int rows, int cols, int seed) +{ srand(seed); - for (int i = 0; i < rows * cols; i++) { + for (int i = 0; i < rows * cols; i++) + { matrix[i] = rand() % 4; // Initialize with random values in the range [0, 127] } } -void flip_matrix(elem_t *matrix, int rows, int cols) { - for (int i = 0; i < rows / 2; i++) { - for (int j = 0; j < cols; j++) { +void flip_matrix(elem_t *matrix, int rows, int cols) +{ + for (int i = 0; i < rows / 2; i++) + { + for (int j = 0; j < cols; j++) + { elem_t temp = matrix[i * cols + j]; matrix[i * cols + j] = matrix[(rows - 1 - i) * cols + j]; matrix[(rows - 1 - i) * cols + j] = temp; @@ -31,7 +36,8 @@ static elem_t weight_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_output_matrix[DIM * DIM] __attribute__((aligned(64))); -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); // Only allow specified hart to continue #endif @@ -50,7 +56,7 @@ int main() { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)weight_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)input_matrix, op2_bank_id, DIM, 1); @@ -60,9 +66,12 @@ int main() { // Move back from scratchpad to output bb_mvout((uintptr_t)output_matrix, op2_bank_id, DIM << 2, 1); bb_fence(); - if (compare_u32_matrices(output_matrix, expected_output_matrix, DIM, DIM)) { + if (compare_u32_matrices(output_matrix, expected_output_matrix, DIM, DIM)) + { printf("Test passed!\n"); - } else { + } + else + { printf("Test failed!\n"); } // print_matrix("Output", output_matrix, DIM, DIM); diff --git a/bb-tests/workloads/src/CTest/toy/bbfptest.c b/bb-tests/workloads/src/CTest/toy/bbfptest.c index a3ac1731..d27a6e46 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfptest.c +++ b/bb-tests/workloads/src/CTest/toy/bbfptest.c @@ -15,10 +15,13 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); // Utility function void print_result_matrix(const char *name, result_t *matrix, int rows, - int cols) { + int cols) +{ printf("Matrix %s:\n", name); - for (int i = 0; i < rows; i++) { - for (int j = 0; j < cols; j++) { + for (int i = 0; i < rows; i++) + { + for (int j = 0; j < cols; j++) + { printf("%4d ", (int32_t)matrix[i * cols + j]); } printf("\n"); @@ -26,22 +29,28 @@ void print_result_matrix(const char *name, result_t *matrix, int rows, printf("\n"); } -void init_matrixv2(elem_t *matrix, int rows, int cols, int seed, int value) { - for (int i = 0; i < rows * cols; i++) { +void init_matrixv2(elem_t *matrix, int rows, int cols, int seed, int value) +{ + for (int i = 0; i < rows * cols; i++) + { matrix[i] = value; } } -int compare_matrices(result_t *a, result_t *b, int rows, int cols) { - for (int i = 0; i < rows * cols; i++) { - if (a[i] != b[i]) { +int compare_matrices(result_t *a, result_t *b, int rows, int cols) +{ + for (int i = 0; i < rows * cols; i++) + { + if (a[i] != b[i]) + { return 0; // Matrices are different } } return 1; // Matrices are the same } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); // Only allow specified hart to continue #endif @@ -58,7 +67,7 @@ int main() { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)input_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)weight_matrix, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index c981757f..155f8f1e 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -14,38 +14,47 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); static elem_t a_transposed[DIM * 1024] __attribute__((aligned(64))); -int acc_mvin_mvout_pressure_test() { - for (int i = 0; i < 4; i++) { +int acc_mvin_mvout_pressure_test() +{ + for (int i = 0; i < 4; i++) + { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); uint32_t acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM << 2, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM << 2, 1); bb_fence(); - if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { + if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) + { printf("Test ACC mvin/mvout pressure %d FAILED\n", i); return 0; - } else { + } + else + { printf("Test ACC mvin/mvout pressure %d PASSED\n", i); } } return 1; } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = acc_mvin_mvout_pressure_test(); - if (passed) { + if (passed) + { printf("ACC mvin/mvout pressure test PASSED\n"); - } else { + } + else + { printf("ACC mvin/mvout pressure test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c index 6f323859..34e24390 100644 --- a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c @@ -17,14 +17,15 @@ static result_t expected_c[DIM_I * DIM_K] __attribute__((aligned(64))); static result_t c_zero[DIM * DIM] __attribute__((aligned(64))); void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c) { + elem_t *a, elem_t *b, result_t *c) +{ // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -34,21 +35,26 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, start_compute = read_cycle(); bb_bbus_config(3, 0, en); // mvin matrix a - for (int i = 0; i < i_stride; i++) { - for (int j = 0; j < j_stride; j++) { + for (int i = 0; i < i_stride; i++) + { + for (int j = 0; j < j_stride; j++) + { bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, j_stride); } } // mvin matrix b - for (int k = 0; k < k_stride; k++) { + for (int k = 0; k < k_stride; k++) + { bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); } bb_fence(); // perform matmul - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { + for (int i = 0; i < i_stride; i++) + { + for (int k = 0; k < k_stride; k++) + { bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 1); bb_transpose((uintptr_t)op1_bank_id + dim_j * k_stride + dim_j * i, @@ -57,8 +63,10 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, } bb_fence(); // mvout matrix c - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { + for (int i = 0; i < i_stride; i++) + { + for (int k = 0; k < k_stride; k++) + { bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); bb_fence(); @@ -70,14 +78,15 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, } void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c) { + elem_t *a, elem_t *b, result_t *c) +{ // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -86,29 +95,35 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, start_compute = read_cycle(); // mvin matrix a - for (int i = 0; i < i_stride; i++) { - for (int j = 0; j < j_stride; j++) { + for (int i = 0; i < i_stride; i++) + { + for (int j = 0; j < j_stride; j++) + { bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, j_stride); } } // mvin matrix b - for (int k = 0; k < k_stride; k++) { + for (int k = 0; k < k_stride; k++) + { bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); } bb_fence(); // transpose matrix a - for (int i = 0; i < i_stride; i++) { + for (int i = 0; i < i_stride; i++) + { bb_transpose((uintptr_t)op2_bank_id + dim_j * k_stride + dim_j * i, op1_bank_id + dim_j * i, dim_j, 0); } bb_fence(); // perform matmul - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { + for (int i = 0; i < i_stride; i++) + { + for (int k = 0; k < k_stride; k++) + { bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 0); bb_fence(); @@ -116,8 +131,10 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, } bb_fence(); // mvout matrix c - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { + for (int i = 0; i < i_stride; i++) + { + for (int k = 0; k < k_stride; k++) + { bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); bb_fence(); @@ -128,13 +145,17 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, printf("Cycles for matmul: %d\n", end_compute - start_compute); } -int run_test(const char *test_name) { +int run_test(const char *test_name) +{ tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); cpu_matmul(input_a, input_b, expected_c, DIM_I, DIM_K, DIM_J); - if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { + if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) + { printf("Test Connect Mode %s PASSED\n", test_name); - } else { + } + else + { printf("Test Connect Mode %s FAILED\n", test_name); return 0; } @@ -142,20 +163,24 @@ int run_test(const char *test_name) { clear_u32_matrix(output_c, DIM_I, DIM_K); // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); // TODO: ACC overwrite write can skip this step bb_mvin((uintptr_t)output_c, acc_bank_id, DIM_I * DIM_K * 4 / DIM, 1); tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); - if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { + if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) + { printf("Test Normal Mode %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test Normal Mode %s FAILED\n", test_name); return 0; } } -int test_tiled_matmul() { +int test_tiled_matmul() +{ /** init_u8_random_matrix(input_a, DIM_I, DIM_J, 111); init_u8_random_matrix(input_b, DIM_J, DIM_K, 222); @@ -165,17 +190,21 @@ int test_tiled_matmul() { return run_test("Tiled Matmul"); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif // printf("%p ,%p", input_a, input_b); // printf("Testing Tiled Matmul\n"); int passed = test_tiled_matmul(); - if (passed) { + if (passed) + { printf("Tiled Matmul test PASSED\n"); return 0; - } else { + } + else + { printf("Tiled Matmul test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index 700c89b1..b610ba2a 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -18,16 +18,18 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); uint32_t col_stride = (size + DIM - 1) / DIM; - for (int i = 0; i < col_stride; i++) { + for (int i = 0; i < col_stride; i++) + { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, col_stride); } @@ -42,20 +44,25 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *aligned_a, elem_t *a, elem_t *b, - int size) { + int size) +{ clear_u32_matrix(output_matrix, DIM, DIM); hw_matmul(test_name, aligned_a, b, output_matrix, size); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); - if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_transpose_matmul() { +int test_transpose_matmul() +{ init_col_aligned_random_matrix(aligned_input_matrix_a, input_matrix_a, DIM, DIM, MATMUL_COL, 111); init_u8_random_matrix(input_matrix_b, MATMUL_COL, DIM, 222); @@ -63,15 +70,19 @@ int test_transpose_matmul() { input_matrix_b, MATMUL_COL); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_transpose_matmul(); - if (passed) { + if (passed) + { printf("Transpose Matmul test PASSED\n"); return 0; - } else { + } + else + { printf("Transpose Matmul test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 58bc8e26..16685b1d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -12,7 +12,8 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 32); // spad0: operand A, offset 0 @@ -21,7 +22,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 4, 1); @@ -35,33 +36,42 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ cpu_matmul(a, b, expected_matrix, DIM, DIM, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_zero_random() { +int test_zero_random() +{ clear_u8_matrix(input_matrix_a, DIM, 32); init_u8_random_matrix(input_matrix_b, 32, DIM, 444); return run_test("Zero × Random", input_matrix_a, input_matrix_b, 32); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_zero_random(); - if (passed) { + if (passed) + { printf("vecunit_matmul_16xn_zero_random test PASSED\n"); return 0; - } else { + } + else + { printf("vecunit_matmul_16xn_zero_random test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index fab897b4..0134b3c3 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -12,7 +12,8 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 @@ -21,7 +22,6 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 4, 1); @@ -36,34 +36,43 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_identity_random() { +int test_identity_random() +{ init_identity_matrix(input_matrix_a, DIM); init_random_matrix(input_matrix_b, DIM, DIM, 123); return run_test("Identity × Random", input_matrix_a, input_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_identity_random(); - if (passed) { + if (passed) + { printf("vecunit_matmul_identity_random test PASSED\n"); return 0; - } else { + } + else + { printf("vecunit_matmul_identity_random test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index 9cbf1caf..b2414e36 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -12,7 +12,8 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { + int size) +{ static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 @@ -21,7 +22,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 4, 1); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); @@ -33,34 +34,43 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) + { printf("Test %s PASSED\n", test_name); return 1; - } else { + } + else + { printf("Test %s FAILED\n", test_name); return 0; } } -int test_row_col_vector() { +int test_row_col_vector() +{ init_row_vector(input_matrix_a, DIM, 2); init_col_vector(input_matrix_b, DIM, 3); return run_test("Row vector × Column vector", input_matrix_a, input_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_row_col_vector(); - if (passed) { + if (passed) + { printf("vecunit_matmul_row_col_vector test PASSED\n"); return 0; - } else { + } + else + { printf("vecunit_matmul_row_col_vector test FAILED\n"); return 1; } From 77941e95dbb1bcd16e1594949d88710e98ffd487 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 1 Mar 2026 18:11:51 +0800 Subject: [PATCH 119/238] [bb-tests] fix:fix bugs of ctests set --- .../workloads/src/CTest/toy/aligned_matmul.c | 31 +++---- .../src/CTest/toy/bbfp_matmul_random1.c | 28 ++---- .../src/CTest/toy/bbfp_matmul_random2.c | 28 ++---- .../src/CTest/toy/bbfp_matmul_random3.c | 28 ++---- bb-tests/workloads/src/CTest/toy/bbfpmatmul.c | 27 ++---- bb-tests/workloads/src/CTest/toy/bbfptest.c | 29 +++---- .../src/CTest/toy/mvin_mvout_acc_test.c | 27 ++---- .../workloads/src/CTest/toy/tiled_matmul.c | 87 +++++++------------ .../src/CTest/toy/transpose_matmul.c | 31 +++---- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 2 +- .../CTest/toy/vecunit_matmul_16xn_random1.c | 2 +- .../CTest/toy/vecunit_matmul_16xn_random2.c | 2 +- .../CTest/toy/vecunit_matmul_16xn_random3.c | 2 +- .../toy/vecunit_matmul_16xn_zero_random.c | 28 ++---- .../CTest/toy/vecunit_matmul_col_row_vector.c | 2 +- .../toy/vecunit_matmul_identity_random.c | 28 ++---- .../src/CTest/toy/vecunit_matmul_ones.c | 5 +- .../src/CTest/toy/vecunit_matmul_random1.c | 5 +- .../src/CTest/toy/vecunit_matmul_random2.c | 2 +- .../src/CTest/toy/vecunit_matmul_random3.c | 5 +- .../CTest/toy/vecunit_matmul_row_col_vector.c | 28 ++---- .../CTest/toy/vecunit_matmul_zero_random.c | 2 +- .../toy/vecunit_simple_nn_forward_pass_test.c | 4 +- 23 files changed, 146 insertions(+), 287 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index f732d2a4..2cfa465d 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -18,20 +18,18 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 uint32_t col_stride = (size + DIM - 1) / DIM; - for (int i = 0; i < col_stride; i++) - { + for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, op2_bank_id, DIM << 2, 1); bb_fence(); @@ -44,25 +42,20 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *aligned_a, elem_t *a, elem_t *b, - int size) -{ + int size) { clear_u32_matrix(output_matrix, DIM, DIM); hw_matmul(test_name, aligned_a, b, output_matrix, size); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); - if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_aligned_matmul() -{ +int test_aligned_matmul() { init_col_aligned_random_matrix(aligned_input_matrix_a, input_matrix_a, DIM, DIM, MATMUL_COL, 111); init_u8_random_matrix(input_matrix_b, MATMUL_COL, DIM, 222); @@ -70,19 +63,15 @@ int test_aligned_matmul() input_matrix_b, MATMUL_COL); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_aligned_matmul(); - if (passed) - { + if (passed) { printf("Aligned Matmul test PASSED\n"); return 0; - } - else - { + } else { printf("Aligned Matmul test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c index dad61ee0..ae3f4fb2 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c @@ -12,12 +12,11 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); @@ -27,42 +26,33 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(b, a, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_random1() -{ +int test_random1() { init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 456); init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 789); return run_test("Random matrices 1", input_matrix_a, input_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_random1(); - if (passed) - { + if (passed) { printf("bbfp_matmul_random1 test PASSED\n"); - } - else - { + } else { printf("bbfp_matmul_random1 test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c index b992053c..2eb65070 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c @@ -12,12 +12,11 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); @@ -27,42 +26,33 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(b, a, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_random1() -{ +int test_random1() { init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 111); init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 222); return run_test("Random matrices 2", input_matrix_a, input_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_random1(); - if (passed) - { + if (passed) { printf("bbfp_matmul_random2 test PASSED\n"); - } - else - { + } else { printf("bbfp_matmul_random2 test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c index 95ffb3b9..ec1430ef 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c @@ -12,12 +12,11 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_fence(); @@ -27,42 +26,33 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(b, a, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_random1() -{ +int test_random1() { init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 333); init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 444); return run_test("Random matrices 3", input_matrix_a, input_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_random1(); - if (passed) - { + if (passed) { printf("bbfp_matmul_random3 test PASSED\n"); - } - else - { + } else { printf("bbfp_matmul_random3 test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c index 3ac907ab..7837e8c3 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c +++ b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c @@ -8,21 +8,16 @@ #define DIM (BANK_WIDTH / sizeof(elem_t)) -void init_matrix(elem_t *matrix, int rows, int cols, int seed) -{ +void init_matrix(elem_t *matrix, int rows, int cols, int seed) { srand(seed); - for (int i = 0; i < rows * cols; i++) - { + for (int i = 0; i < rows * cols; i++) { matrix[i] = rand() % 4; // Initialize with random values in the range [0, 127] } } -void flip_matrix(elem_t *matrix, int rows, int cols) -{ - for (int i = 0; i < rows / 2; i++) - { - for (int j = 0; j < cols; j++) - { +void flip_matrix(elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows / 2; i++) { + for (int j = 0; j < cols; j++) { elem_t temp = matrix[i * cols + j]; matrix[i * cols + j] = matrix[(rows - 1 - i) * cols + j]; matrix[(rows - 1 - i) * cols + j] = temp; @@ -36,8 +31,7 @@ static elem_t weight_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_output_matrix[DIM * DIM] __attribute__((aligned(64))); -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); // Only allow specified hart to continue #endif @@ -56,7 +50,7 @@ int main() uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)weight_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)input_matrix, op2_bank_id, DIM, 1); @@ -66,12 +60,9 @@ int main() // Move back from scratchpad to output bb_mvout((uintptr_t)output_matrix, op2_bank_id, DIM << 2, 1); bb_fence(); - if (compare_u32_matrices(output_matrix, expected_output_matrix, DIM, DIM)) - { + if (compare_u32_matrices(output_matrix, expected_output_matrix, DIM, DIM)) { printf("Test passed!\n"); - } - else - { + } else { printf("Test failed!\n"); } // print_matrix("Output", output_matrix, DIM, DIM); diff --git a/bb-tests/workloads/src/CTest/toy/bbfptest.c b/bb-tests/workloads/src/CTest/toy/bbfptest.c index d27a6e46..a3ac1731 100644 --- a/bb-tests/workloads/src/CTest/toy/bbfptest.c +++ b/bb-tests/workloads/src/CTest/toy/bbfptest.c @@ -15,13 +15,10 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); // Utility function void print_result_matrix(const char *name, result_t *matrix, int rows, - int cols) -{ + int cols) { printf("Matrix %s:\n", name); - for (int i = 0; i < rows; i++) - { - for (int j = 0; j < cols; j++) - { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { printf("%4d ", (int32_t)matrix[i * cols + j]); } printf("\n"); @@ -29,28 +26,22 @@ void print_result_matrix(const char *name, result_t *matrix, int rows, printf("\n"); } -void init_matrixv2(elem_t *matrix, int rows, int cols, int seed, int value) -{ - for (int i = 0; i < rows * cols; i++) - { +void init_matrixv2(elem_t *matrix, int rows, int cols, int seed, int value) { + for (int i = 0; i < rows * cols; i++) { matrix[i] = value; } } -int compare_matrices(result_t *a, result_t *b, int rows, int cols) -{ - for (int i = 0; i < rows * cols; i++) - { - if (a[i] != b[i]) - { +int compare_matrices(result_t *a, result_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { return 0; // Matrices are different } } return 1; // Matrices are the same } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); // Only allow specified hart to continue #endif @@ -67,7 +58,7 @@ int main() uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)input_matrix, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)weight_matrix, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index 155f8f1e..c981757f 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -14,47 +14,38 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); static elem_t a_transposed[DIM * 1024] __attribute__((aligned(64))); -int acc_mvin_mvout_pressure_test() -{ - for (int i = 0; i < 4; i++) - { +int acc_mvin_mvout_pressure_test() { + for (int i = 0; i < 4; i++) { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); uint32_t acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM << 2, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM << 2, 1); bb_fence(); - if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) - { + if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test ACC mvin/mvout pressure %d FAILED\n", i); return 0; - } - else - { + } else { printf("Test ACC mvin/mvout pressure %d PASSED\n", i); } } return 1; } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = acc_mvin_mvout_pressure_test(); - if (passed) - { + if (passed) { printf("ACC mvin/mvout pressure test PASSED\n"); - } - else - { + } else { printf("ACC mvin/mvout pressure test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c index 34e24390..6f323859 100644 --- a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c @@ -17,15 +17,14 @@ static result_t expected_c[DIM_I * DIM_K] __attribute__((aligned(64))); static result_t c_zero[DIM * DIM] __attribute__((aligned(64))); void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c) -{ + elem_t *a, elem_t *b, result_t *c) { // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -35,26 +34,21 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, start_compute = read_cycle(); bb_bbus_config(3, 0, en); // mvin matrix a - for (int i = 0; i < i_stride; i++) - { - for (int j = 0; j < j_stride; j++) - { + for (int i = 0; i < i_stride; i++) { + for (int j = 0; j < j_stride; j++) { bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, j_stride); } } // mvin matrix b - for (int k = 0; k < k_stride; k++) - { + for (int k = 0; k < k_stride; k++) { bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); } bb_fence(); // perform matmul - for (int i = 0; i < i_stride; i++) - { - for (int k = 0; k < k_stride; k++) - { + for (int i = 0; i < i_stride; i++) { + for (int k = 0; k < k_stride; k++) { bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 1); bb_transpose((uintptr_t)op1_bank_id + dim_j * k_stride + dim_j * i, @@ -63,10 +57,8 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, } bb_fence(); // mvout matrix c - for (int i = 0; i < i_stride; i++) - { - for (int k = 0; k < k_stride; k++) - { + for (int i = 0; i < i_stride; i++) { + for (int k = 0; k < k_stride; k++) { bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); bb_fence(); @@ -78,15 +70,14 @@ void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, } void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c) -{ + elem_t *a, elem_t *b, result_t *c) { // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t i_stride = dim_i / DIM; uint32_t j_stride = dim_j / DIM; uint32_t k_stride = dim_k / DIM; @@ -95,35 +86,29 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, start_compute = read_cycle(); // mvin matrix a - for (int i = 0; i < i_stride; i++) - { - for (int j = 0; j < j_stride; j++) - { + for (int i = 0; i < i_stride; i++) { + for (int j = 0; j < j_stride; j++) { bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, j_stride); } } // mvin matrix b - for (int k = 0; k < k_stride; k++) - { + for (int k = 0; k < k_stride; k++) { bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); } bb_fence(); // transpose matrix a - for (int i = 0; i < i_stride; i++) - { + for (int i = 0; i < i_stride; i++) { bb_transpose((uintptr_t)op2_bank_id + dim_j * k_stride + dim_j * i, op1_bank_id + dim_j * i, dim_j, 0); } bb_fence(); // perform matmul - for (int i = 0; i < i_stride; i++) - { - for (int k = 0; k < k_stride; k++) - { + for (int i = 0; i < i_stride; i++) { + for (int k = 0; k < k_stride; k++) { bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 0); bb_fence(); @@ -131,10 +116,8 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, } bb_fence(); // mvout matrix c - for (int i = 0; i < i_stride; i++) - { - for (int k = 0; k < k_stride; k++) - { + for (int i = 0; i < i_stride; i++) { + for (int k = 0; k < k_stride; k++) { bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); bb_fence(); @@ -145,17 +128,13 @@ void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, printf("Cycles for matmul: %d\n", end_compute - start_compute); } -int run_test(const char *test_name) -{ +int run_test(const char *test_name) { tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); cpu_matmul(input_a, input_b, expected_c, DIM_I, DIM_K, DIM_J); - if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) - { + if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { printf("Test Connect Mode %s PASSED\n", test_name); - } - else - { + } else { printf("Test Connect Mode %s FAILED\n", test_name); return 0; } @@ -163,24 +142,20 @@ int run_test(const char *test_name) clear_u32_matrix(output_c, DIM_I, DIM_K); // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); // TODO: ACC overwrite write can skip this step bb_mvin((uintptr_t)output_c, acc_bank_id, DIM_I * DIM_K * 4 / DIM, 1); tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); - if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) - { + if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { printf("Test Normal Mode %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test Normal Mode %s FAILED\n", test_name); return 0; } } -int test_tiled_matmul() -{ +int test_tiled_matmul() { /** init_u8_random_matrix(input_a, DIM_I, DIM_J, 111); init_u8_random_matrix(input_b, DIM_J, DIM_K, 222); @@ -190,21 +165,17 @@ int test_tiled_matmul() return run_test("Tiled Matmul"); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif // printf("%p ,%p", input_a, input_b); // printf("Testing Tiled Matmul\n"); int passed = test_tiled_matmul(); - if (passed) - { + if (passed) { printf("Tiled Matmul test PASSED\n"); return 0; - } - else - { + } else { printf("Tiled Matmul test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index b610ba2a..700c89b1 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -18,18 +18,16 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t col_stride = (size + DIM - 1) / DIM; - for (int i = 0; i < col_stride; i++) - { + for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, col_stride); } @@ -44,25 +42,20 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, } int run_test(const char *test_name, elem_t *aligned_a, elem_t *a, elem_t *b, - int size) -{ + int size) { clear_u32_matrix(output_matrix, DIM, DIM); hw_matmul(test_name, aligned_a, b, output_matrix, size); cpu_matmul(a, b, expected_matrix, DIM, DIM, size); - if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_transpose_matmul() -{ +int test_transpose_matmul() { init_col_aligned_random_matrix(aligned_input_matrix_a, input_matrix_a, DIM, DIM, MATMUL_COL, 111); init_u8_random_matrix(input_matrix_b, MATMUL_COL, DIM, 222); @@ -70,19 +63,15 @@ int test_transpose_matmul() input_matrix_b, MATMUL_COL); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_transpose_matmul(); - if (passed) - { + if (passed) { printf("Transpose Matmul test PASSED\n"); return 0; - } - else - { + } else { printf("Transpose Matmul test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index dc1891ee..fed156b2 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 738b5c49..6d712b47 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -21,7 +21,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index ae4df30a..ef774128 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index 92472449..b9b26ec4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 16685b1d..12d917c3 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -12,8 +12,7 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); transpose_u8_matrix(a, a_transposed, DIM, 32); // spad0: operand A, offset 0 @@ -25,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); @@ -36,42 +35,33 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { cpu_matmul(a, b, expected_matrix, DIM, DIM, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_zero_random() -{ +int test_zero_random() { clear_u8_matrix(input_matrix_a, DIM, 32); init_u8_random_matrix(input_matrix_b, 32, DIM, 444); return run_test("Zero × Random", input_matrix_a, input_matrix_b, 32); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_zero_random(); - if (passed) - { + if (passed) { printf("vecunit_matmul_16xn_zero_random test PASSED\n"); return 0; - } - else - { + } else { printf("vecunit_matmul_16xn_zero_random test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index 989721b2..a947da22 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -25,7 +25,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 0134b3c3..a86dd4dd 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -12,8 +12,7 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 @@ -24,7 +23,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); @@ -36,43 +35,34 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { clear_u32_matrix(output_matrix, DIM, DIM); cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_identity_random() -{ +int test_identity_random() { init_identity_matrix(input_matrix_a, DIM); init_random_matrix(input_matrix_b, DIM, DIM, 123); return run_test("Identity × Random", input_matrix_a, input_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_identity_random(); - if (passed) - { + if (passed) { printf("vecunit_matmul_identity_random test PASSED\n"); return 0; - } - else - { + } else { printf("vecunit_matmul_identity_random test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index b1b1f34c..d9475951 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -25,7 +25,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); @@ -61,7 +61,6 @@ int main() { #endif int passed = test_ones(); - if (passed) { printf("vecunit_matmul_ones test PASSED\n"); return 0; @@ -69,7 +68,7 @@ int main() { printf("vecunit_matmul_ones test FAILED\n"); return 1; } - + #ifdef MULTICORE exit(0); #endif diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index d585fdc5..3fa69673 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -25,7 +25,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); @@ -61,7 +61,6 @@ int main() { #endif int passed = test_ones(); - if (passed) { printf("vecunit_matmul_random test PASSED\n"); return 0; @@ -69,7 +68,7 @@ int main() { printf("vecunit_matmul_random test FAILED\n"); return 1; } - + #ifdef MULTICORE exit(0); #endif diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 6c8e7439..070eb551 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 7c332d1f..9a2fa1ea 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); @@ -60,7 +60,6 @@ int main() { #endif int passed = test_random(); - if (passed) { printf("vecunit_matmul_random test PASSED\n"); return 0; @@ -68,7 +67,7 @@ int main() { printf("vecunit_matmul_random test FAILED\n"); return 1; } - + #ifdef MULTICORE exit(0); #endif diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index b2414e36..9cbf1caf 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -12,8 +12,7 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) -{ + int size) { static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); transpose_u8_matrix(a, a_transposed, size, size); // spad0: operand A, offset 0 @@ -22,7 +21,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); @@ -34,43 +33,34 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) - { + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); return 1; - } - else - { + } else { printf("Test %s FAILED\n", test_name); return 0; } } -int test_row_col_vector() -{ +int test_row_col_vector() { init_row_vector(input_matrix_a, DIM, 2); init_col_vector(input_matrix_b, DIM, 3); return run_test("Row vector × Column vector", input_matrix_a, input_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_row_col_vector(); - if (passed) - { + if (passed) { printf("vecunit_matmul_row_col_vector test PASSED\n"); return 0; - } - else - { + } else { printf("vecunit_matmul_row_col_vector test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index d30a70da..794712b1 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -24,7 +24,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index 0e2faf9b..c05ca6c4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -67,7 +67,7 @@ void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 4, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); @@ -131,7 +131,7 @@ int test_neural_network() { printf("Running CPU Neural Network Forward Pass...\n"); cpu_nn_forward(input_data, weights1, weights2, hidden_output, expected_output, DIM); - + // Compare hardware output with expected output printf("Comparing hardware output with expected output...\n"); if (compare_u32_matrices(final_output, expected_output, DIM, DIM)) { From df4a5494400388e518ebdbd6a93b996ae981d56b Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 1 Mar 2026 18:51:14 +0800 Subject: [PATCH 120/238] [docs] doc: update README --- README.md | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index e383591d..5d500ba3 100644 --- a/README.md +++ b/README.md @@ -51,13 +51,13 @@ bbdev verilator --run '--jobs 16 --binary ctest_vecunit_matmul_ones_singlecore-b ``` -### Buckyball as a library + ## Tutorial @@ -67,9 +67,6 @@ You can start to learn ball and blink from [here](https://github.com/DangoSys/bu You can learn more from [DeepWiki](https://deepwiki.com/DangoSys/buckyball) and [Zread](https://zread.ai/DangoSys/buckyball) -## Community - -Join our discussion on [Slack](https://dangosys-buckyball.slack.com/) ## Contributors Thank you for considering contributing to buckyball! From 644d72fbebc8fbf9d566bda6559631f25470d07b Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Sun, 1 Mar 2026 20:39:01 +0800 Subject: [PATCH 121/238] [arch]fix: fix bugs of im2col ball and pass the test (#24) --- .../balldomain/prototype/im2col/FIFO.scala | 36 ++ .../balldomain/prototype/im2col/Im2col.scala | 400 +++++++++++------- bb-tests/sardine/tests/test_ctest.py | 4 + .../workloads/src/CTest/toy/im2col_test.c | 118 +++++- 4 files changed, 381 insertions(+), 177 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala new file mode 100644 index 00000000..b1bb2707 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala @@ -0,0 +1,36 @@ +package framework.balldomain.prototype.im2col + +import chisel3._ +import chisel3.util._ + +class RowSlotFIFO(maxRows: Int) extends Module { + val io = IO(new Bundle { + val kRows = Input(UInt(log2Ceil(maxRows + 1).W)) + val init = Input(Bool()) + val advance = Input(Bool()) + val head = Output(UInt(log2Ceil(maxRows).W)) + val slotToOverwrite = Output(UInt(log2Ceil(maxRows).W)) + }) + + private val headReg = RegInit(0.U(log2Ceil(maxRows).W)) + + io.head := headReg + io.slotToOverwrite := headReg + + when(io.init) { + headReg := 0.U + }.elsewhen(io.advance && (io.kRows > 0.U)) { + when(headReg + 1.U === io.kRows) { + headReg := 0.U + }.otherwise { + headReg := headReg + 1.U + } + } +} + +object RowSlotFIFO { + def logicalToPhysical(head: UInt, logicalRow: UInt, kRows: UInt): UInt = { + val sum = head + logicalRow + Mux(sum >= kRows, sum - kRows, sum) + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index 72963b3e..b6e51d03 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -2,10 +2,8 @@ package framework.balldomain.prototype.im2col import chisel3._ import chisel3.util._ -import chisel3.stage._ import chisel3.experimental.hierarchy.{instantiable, public} -import framework.balldomain.prototype.vector._ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.top.GlobalConfig @@ -13,19 +11,24 @@ import framework.balldomain.prototype.im2col.configs.Im2colBallParam @instantiable class Im2col(val b: GlobalConfig) extends Module { - val ballConfig = Im2colBallParam() - val InputNum = ballConfig.InputNum - val inputWidth = ballConfig.inputWidth - val bankWidth = b.memDomain.bankWidth + private val maxK = Im2colBallParam().InputNum + private val elemWidth = Im2colBallParam().inputWidth + private val bankWidth = b.memDomain.bankWidth + private val lanesPerBeat = 16 + private val laneWidth = bankWidth / lanesPerBeat + private val maxInCol = 32 + private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat + private val maxKernelElems = maxK * maxK - // Get bandwidth from config - val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "Im2colBall") + require(laneWidth == elemWidth, s"[Im2col] laneWidth($laneWidth) must equal elemWidth($elemWidth)") + + private val mapping = b.ballDomain.ballIdMappings + .find(_.ballName == "Im2colBall") .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW + private val inBW = mapping.inBW + private val outBW = mapping.outBW - @public - val io = IO(new Bundle { + @public val io = IO(new Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) val cmdResp = Decoupled(new BallRsComplete(b)) val bankRead = Vec(inBW, Flipped(new BankRead(b))) @@ -33,190 +36,271 @@ class Im2col(val b: GlobalConfig) extends Module { val status = new BallStatus }) - // State definitions - val idle :: read :: read_and_convert :: complete :: Nil = Enum(4) - // Current state register - val state = RegInit(idle) - // Conversion buffer - val ConvertBuffer = RegInit(VecInit(Seq.fill(4)(VecInit(Seq.fill(InputNum)(0.U(inputWidth.W)))))) - // Row pointer marking top-left corner of convolution window - val rowptr = RegInit(0.U(10.W)) - // Column pointer marking top-left corner of convolution window - val colptr = RegInit(0.U(5.W)) - // Request counter in read state - val reqcounter = RegInit(0.U(5.W)) - // Response counter in read state - val respcounter = RegInit(0.U(5.W)) - // Store current instruction's RoB ID - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - // Store kernel row count - val krow_reg = RegInit(0.U(log2Up(InputNum).W)) - // Store kernel column count - val kcol_reg = RegInit(0.U(log2Up(InputNum).W)) - // Store input matrix row count - val inrow_reg = RegInit(0.U(10.W)) - // Store input matrix column count - val incol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) - // Store starting column number - val startcol_reg = RegInit(0.U((log2Up(InputNum) + 1).W)) - // Store starting row number - val startrow_reg = RegInit(0.U(10.W)) - // Store write starting address - val waddr_reg = RegInit(0.U(10.W)) - // Store write bank - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - // Store read starting address - val raddr_reg = RegInit(0.U(10.W)) - // Store read bank - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - // Batch iteration counter - val iterCnt = RegInit(0.U(32.W)) - - // SRAM default assignment + require(inBW >= 1, "[Im2col] inBW must be >= 1") + require(outBW >= 1, "[Im2col] outBW must be >= 1") + + val idle :: preload_rows :: generate_window :: write_window :: load_next_row :: complete :: Nil = Enum(6) + val state = RegInit(idle) + + private val robIdReg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + private val rBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + private val wBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + + private val rBaseBeatReg = RegInit(0.U(32.W)) + private val wBaseBeatReg = RegInit(0.U(32.W)) + + private val kRowReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val kColReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val inRowReg = RegInit(0.U(16.W)) + private val inColReg = RegInit(0.U(16.W)) + private val startRowReg = RegInit(0.U(16.W)) + private val startColReg = RegInit(0.U(16.W)) + + private val rowPtrReg = RegInit(0.U(16.W)) + private val colPtrReg = RegInit(0.U(16.W)) + + private val lineBuffer = RegInit(VecInit(Seq.fill(maxK)(VecInit(Seq.fill(maxInColWords)(0.U(bankWidth.W)))))) + private val elemBuffer = RegInit(VecInit(Seq.fill(maxKernelElems)(0.U(elemWidth.W)))) + + private val rowFifo = Module(new RowSlotFIFO(maxK)) + rowFifo.io.kRows := kRowReg + rowFifo.io.init := false.B + rowFifo.io.advance := false.B + + private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) + private val ldOutstandingReg = RegInit(false.B) + + private val genElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) + private val wrElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) + private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) + private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) + + private def ceilDiv(a: UInt, d: Int): UInt = (a + (d - 1).U) / d.U + private val inColWords = ceilDiv(inColReg, lanesPerBeat) + private val totalKernelEls = kRowReg * kColReg + + private val rowMax = inRowReg - kRowReg + private val colMax = inColReg - kColReg + private val rowEnd = rowPtrReg === (startRowReg + rowMax) + private val colEnd = colPtrReg === (startColReg + colMax) + private val isLastWindow = rowEnd && colEnd + + private def laneFromBeat(beat: UInt, lane: UInt): UInt = { + val lanes = beat.asTypeOf(Vec(lanesPerBeat, UInt(elemWidth.W))) + lanes(lane) + } + + io.cmdReq.ready := (state === idle) + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := robIdReg + + io.status.idle := (state === idle) + io.status.running := (state =/= idle) && (state =/= complete) + for (i <- 0 until inBW) { io.bankRead(i).io.req.valid := false.B io.bankRead(i).io.req.bits.addr := 0.U - io.bankRead(i).io.resp.ready := (state === read) || (state === read_and_convert) - io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).bank_id := rBankReg + io.bankRead(i).rob_id := robIdReg io.bankRead(i).ball_id := 0.U - io.bankRead(i).group_id := 0.U + io.bankRead(i).group_id := 0.U } + for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B io.bankWrite(i).io.req.bits.addr := 0.U io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) io.bankWrite(i).io.req.bits.wmode := false.B - io.bankWrite(i).io.resp.ready := true.B - io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).io.resp.ready := false.B + io.bankWrite(i).bank_id := wBankReg + io.bankWrite(i).rob_id := robIdReg io.bankWrite(i).ball_id := 0.U - io.bankWrite(i).group_id := 0.U + io.bankWrite(i).group_id := 0.U } - // cmd interface default assignment - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg - val rowcnt = rowptr - startrow_reg - val colcnt = colptr - startcol_reg - val rowmax = inrow_reg - krow_reg - val colmax = incol_reg - kcol_reg + io.bankWrite(0).io.resp.ready := true.B switch(state) { - // Idle state, waiting for instruction is(idle) { - // Instruction arrives, initialize registers when(io.cmdReq.fire) { - state := read - rowptr := io.cmdReq.bits.cmd.special(37, 28) - colptr := io.cmdReq.bits.cmd.special(27, 23) - reqcounter := 0.U - respcounter := 0.U - // Kernel column count - kcol_reg := io.cmdReq.bits.cmd.special(3, 0) - // Kernel row count - krow_reg := io.cmdReq.bits.cmd.special(7, 4) - // Input matrix column count - incol_reg := io.cmdReq.bits.cmd.special(12, 8) - // Input matrix row count - inrow_reg := io.cmdReq.bits.cmd.special(22, 13) - // Starting column number - startcol_reg := io.cmdReq.bits.cmd.special(27, 23) - // Starting row number - startrow_reg := io.cmdReq.bits.cmd.special(37, 28) - rob_id_reg := io.cmdReq.bits.rob_id - waddr_reg := 0.U - wbank_reg := io.cmdReq.bits.cmd.op2_bank - raddr_reg := 0.U - rbank_reg := io.cmdReq.bits.cmd.op1_bank + robIdReg := io.cmdReq.bits.rob_id + rBankReg := io.cmdReq.bits.cmd.op1_bank + wBankReg := io.cmdReq.bits.cmd.wr_bank + + kColReg := io.cmdReq.bits.cmd.special(3, 0) + kRowReg := io.cmdReq.bits.cmd.special(7, 4) + inColReg := io.cmdReq.bits.cmd.special(12, 8) + inRowReg := io.cmdReq.bits.cmd.special(22, 13) + startColReg := io.cmdReq.bits.cmd.special(27, 23) + startRowReg := io.cmdReq.bits.cmd.special(37, 28) + + rowPtrReg := io.cmdReq.bits.cmd.special(37, 28) + colPtrReg := io.cmdReq.bits.cmd.special(27, 23) + + rBaseBeatReg := 0.U + wBaseBeatReg := 0.U + + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U + ldOutstandingReg := false.B + genElemIdxReg := 0.U + wrElemIdxReg := 0.U + packCntReg := 0.U + + rowFifo.io.init := true.B + + val cmdKCol = io.cmdReq.bits.cmd.special(3, 0) + val cmdKRow = io.cmdReq.bits.cmd.special(7, 4) + val cmdInCol = io.cmdReq.bits.cmd.special(12, 8) + val cmdInRow = io.cmdReq.bits.cmd.special(22, 13) + val invalidShape = (cmdKCol === 0.U) || (cmdKRow === 0.U) || (cmdInCol === 0.U) || (cmdInRow === 0.U) || + (cmdInCol < cmdKCol) || (cmdInRow < cmdKRow) + + when(invalidShape) { + state := complete + }.otherwise { + state := preload_rows + } } } - // Read part of data, fill ConvertBuffer - is(read) { - // Send read request - io.bankRead(0).io.req.valid := reqcounter < krow_reg - io.bankRead(0).io.req.bits.addr := raddr_reg + reqcounter + startrow_reg + + is(preload_rows) { + val doneRows = ldRowIdxReg === kRowReg + val canIssue = !doneRows && !ldOutstandingReg && (ldBeatIdxReg < inColWords) + val rowElem = rowPtrReg + ldRowIdxReg + val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg + + io.bankRead(0).io.req.valid := canIssue + io.bankRead(0).io.req.bits.addr := reqAddr + io.bankRead(0).io.resp.ready := ldOutstandingReg when(io.bankRead(0).io.req.fire) { - reqcounter := reqcounter + 1.U + ldOutstandingReg := true.B } - // Process read response and store in ConvertBuffer + when(io.bankRead(0).io.resp.fire) { - ConvertBuffer(respcounter) := io.bankRead(0).io.resp.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - respcounter := respcounter + 1.U + lineBuffer(ldRowIdxReg)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt + ldOutstandingReg := false.B + + when(ldBeatIdxReg + 1.U === inColWords) { + ldBeatIdxReg := 0.U + ldRowIdxReg := ldRowIdxReg + 1.U + }.otherwise { + ldBeatIdxReg := ldBeatIdxReg + 1.U + } } - // Determine whether to transition state - state := Mux(respcounter === krow_reg, read_and_convert, read) + when(doneRows && !ldOutstandingReg) { + genElemIdxReg := 0.U + state := generate_window + } } - // Convert data and read remaining data, write back to spad - is(read_and_convert) { - // Move pointer - when(colptr <= colmax && rowptr <= rowmax) { - io.bankWrite(0).io.req.valid := true.B - io.bankWrite(0).io.req.bits.addr := waddr_reg + rowcnt * (colmax + 1.U - startcol_reg) + colcnt - io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(~0.U(1.W))) - io.bankWrite(0).io.req.bits.data := { - - val window = Wire(Vec(InputNum, UInt(inputWidth.W))) - // Initialize all to 0 first - for (i <- 0 until InputNum) { - window(i) := 0.U - } - // Fill window data - for { - i <- 0 until 4 - j <- 0 until 4 - } { - when(i.U < krow_reg && j.U < kcol_reg) { - val bufferRow = (rowcnt + i.U) % krow_reg - val bufferCol = (colptr + j.U) % incol_reg - window((i.U * kcol_reg) + j.U) := ConvertBuffer(bufferRow)(bufferCol) - }.otherwise { - window((i.U * kcol_reg) + j.U) := 0.U - } - } + is(generate_window) { + val startLane = colPtrReg % lanesPerBeat.U + val safeKCol = Mux(kColReg === 0.U, 1.U, kColReg) - // Rearrange data - // For example, for klen_reg=3, combine (00)(01)(02)(10)(11)(12)(20)(21)(22) - Cat((0 until InputNum).map(i => window(i)).reverse) - } + val t = genElemIdxReg + val kRowIdx = t / safeKCol + val kColIdx = t % safeKCol + + val physicalSlot = RowSlotFIFO.logicalToPhysical(rowFifo.io.head, kRowIdx, kRowReg) + val laneSum = startLane + kColIdx + val beatIdx = laneSum / lanesPerBeat.U + val laneIdx = laneSum % lanesPerBeat.U + val beatWord = lineBuffer(physicalSlot)(beatIdx) + + elemBuffer(t) := laneFromBeat(beatWord, laneIdx) + + when(genElemIdxReg === (totalKernelEls - 1.U)) { + wrElemIdxReg := 0.U + state := write_window + }.otherwise { + genElemIdxReg := genElemIdxReg + 1.U + } + } + + is(write_window) { + val windowDone = wrElemIdxReg === totalKernelEls + val packFull = packCntReg === lanesPerBeat.U + + io.bankWrite(0).io.req.valid := packFull + io.bankWrite(0).io.req.bits.addr := wBaseBeatReg + io.bankWrite(0).io.req.bits.data := Cat(packReg.reverse) + io.bankWrite(0).io.req.bits.wmode := true.B + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + + when(!windowDone && !packFull) { + packReg(packCntReg) := elemBuffer(wrElemIdxReg) + packCntReg := packCntReg + 1.U + wrElemIdxReg := wrElemIdxReg + 1.U + } - when(io.bankWrite(0).io.req.fire) { - colptr := Mux(colptr === colmax, startcol_reg, colptr + 1.U) + when(io.bankWrite(0).io.req.fire) { + wBaseBeatReg := wBaseBeatReg + 1.U + packCntReg := 0.U + } + + when(windowDone) { + when(packFull && !io.bankWrite(0).io.req.fire) { + state := write_window + }.otherwise { + when(isLastWindow) { + state := complete + }.elsewhen(colEnd) { + colPtrReg := startColReg + rowPtrReg := rowPtrReg + 1.U + + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U + ldOutstandingReg := false.B + state := load_next_row + }.otherwise { + colPtrReg := colPtrReg + 1.U + genElemIdxReg := 0.U + state := generate_window + } } } - // Send read request early - when(colptr === colmax - 1.U) { - io.bankRead(0).io.req.valid := true.B - io.bankRead(0).io.req.bits.addr := raddr_reg + krow_reg + rowptr + } + + is(load_next_row) { + val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) + val rowElem = rowPtrReg + kRowReg - 1.U + val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg + val targetSlot = rowFifo.io.slotToOverwrite + + io.bankRead(0).io.req.valid := canIssue + io.bankRead(0).io.req.bits.addr := reqAddr + io.bankRead(0).io.resp.ready := ldOutstandingReg + + when(io.bankRead(0).io.req.fire) { + ldOutstandingReg := true.B } - // Process read response and store in ConvertBuffer + when(io.bankRead(0).io.resp.fire) { - ConvertBuffer(rowcnt % krow_reg) := io.bankRead(0).io.resp.bits.data.asTypeOf(Vec( - InputNum, - UInt(inputWidth.W) - )) - rowptr := rowptr + 1.U + lineBuffer(targetSlot)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt + ldOutstandingReg := false.B + + when(ldBeatIdxReg + 1.U === inColWords) { + ldBeatIdxReg := 0.U + rowFifo.io.advance := true.B + genElemIdxReg := 0.U + state := generate_window + }.otherwise { + ldBeatIdxReg := ldBeatIdxReg + 1.U + } } - // Determine whether to transition state - state := Mux(rowptr === rowmax && colptr === colmax, complete, read_and_convert) } - // Complete state, send completion signal + is(complete) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := rob_id_reg - state := idle + io.cmdResp.valid := true.B when(io.cmdResp.fire) { - iterCnt := iterCnt + 1.U + state := idle } } } - - // Status signals - io.status.idle := (state === idle) - io.status.running := (state === read_and_convert) } diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 03c39e64..e8190b49 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -78,6 +78,10 @@ "ctest_transpose_test_singlecore-baremetal", "ctest_transpose_test_singlecore-baremetal", ), + ( + "ctest_im2col_test_singlecore-baremetal", + "ctest_im2col_test_singlecore-baremetal", + ), ] diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index b6642815..98388918 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -4,12 +4,68 @@ #include #include -#define DIM (BANK_WIDTH / sizeof(elem_t)) +#define DIM 16 +#define KROW 4 +#define KCOL 1 +#define INROW 16 +#define INCOL 16 +#define STARTROW 0 +#define STARTCOL 0 -static elem_t input_matrix_a[DIM * 64] __attribute__((aligned(64))); -static elem_t output_matrix_b[DIM * 1024] __attribute__((aligned(64))); +#define EXPECTED_ROWS 1024 +#define EXPECTED_COLS 4 +#define LANES_PER_BEAT 16 + +static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t output_matrix_b[EXPECTED_ROWS * EXPECTED_COLS] __attribute__((aligned(64))); +static elem_t expected_matrix[EXPECTED_ROWS * EXPECTED_COLS] __attribute__((aligned(64))); + +static int conv_num(void) +{ + return (INROW - KROW + 1 - STARTROW) * (INCOL - KCOL + 1 - STARTCOL); +} + +static int kernel_elems(void) +{ + return KROW * KCOL; +} + +static void build_expected_im2col_matrix(elem_t *input, elem_t *expected, + int inrow, int incol, + int krow, int kcol, + int startrow, int startcol) +{ + clear_i8_matrix(expected, EXPECTED_ROWS, EXPECTED_COLS); + + int row_end = inrow - krow; + int col_end = incol - kcol; + int kernel = krow * kcol; + int window_idx = 0; + + for (int r = startrow; r <= row_end; r++) + { + for (int c = startcol; c <= col_end; c++) + { + int elem_idx = 0; + for (int kr = 0; kr < krow; kr++) + { + for (int kc = 0; kc < kcol; kc++) + { + expected[window_idx * kernel + elem_idx] = + input[(r + kr) * incol + (c + kc)]; + elem_idx++; + } + } + window_idx++; + } + } +} + +void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) +{ + (void)test_name; + (void)size; -void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { // spad0: operand A, offset 0 uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 @@ -17,41 +73,65 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, 32, 1); bb_fence(); - uint64_t krow = 4; - uint64_t kcol = 1; - uint64_t inrow = 16; - uint64_t incol = 16; - uint64_t startrow = 1; - uint64_t startcol = 1; + uint64_t krow = KROW; + uint64_t kcol = KCOL; + uint64_t inrow = INROW; + uint64_t incol = INCOL; + uint64_t startrow = STARTROW; + uint64_t startcol = STARTCOL; // bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, // startcol); bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, startcol); bb_fence(); - bb_mvout((uintptr_t)b, op2_bank_id, size, 1); + bb_mvout((uintptr_t)b, op2_bank_id, conv_num() / kernel_elems(), 1); bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) +{ + int conv = conv_num(); + int elems = kernel_elems(); + + clear_i8_matrix(b, EXPECTED_ROWS, EXPECTED_COLS); + build_expected_im2col_matrix(a, expected_matrix, INROW, INCOL, KROW, KCOL, + STARTROW, STARTCOL); + hw_im2col(test_name, a, b, size); - return 1; + + + if (compare_i8_matrices(b, expected_matrix, conv, elems)) + { + printf("%s compare test PASSED\n", test_name); + return 1; + } + else + { + printf("%s compare test FAILED\n", test_name); + return 0; + } } -int test_im2col() { - init_sequence_matrix(input_matrix_a, DIM, 32); +int test_im2col() +{ + init_sequence_matrix(input_matrix_a, DIM, DIM); return run_test("Im2col", input_matrix_a, output_matrix_b, DIM); } -int main() { +int main() +{ #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_im2col(); - if (passed) { + if (passed) + { printf("Im2col test PASSED\n"); - } else { + } + else + { printf("Im2col test FAILED\n"); } #ifdef MULTICORE From 83f8dfb39e78ac204b2e7ca558912c5c7ded314d Mon Sep 17 00:00:00 2001 From: SJM946 Date: Mon, 2 Mar 2026 18:58:25 +0800 Subject: [PATCH 122/238] [arch]fix: Fix memConfiger bugs --- .../scala/examples/toy/ToyBuckyBall.scala | 24 ++-- .../balldomain/prototype/im2col/FIFO.scala | 13 +- .../balldomain/prototype/im2col/Im2col.scala | 123 +++++++++--------- .../balldomain/prototype/relu/Relu.scala | 4 +- .../prototype/transpose/Transpose.scala | 4 +- .../prototype/vector/VecLoadUnit.scala | 17 ++- .../balldomain/prototype/vector/VecUnit.scala | 6 +- .../memdomain/backend/accpipe/AccPipe.scala | 8 +- .../outside_channel/MemConfiger.scala | 40 +++--- .../frontend/outside_channel/MemLoader.scala | 6 +- .../frontend/outside_channel/MemStorer.scala | 6 +- 11 files changed, 127 insertions(+), 124 deletions(-) diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index a85aa944..0519540d 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -101,20 +101,20 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) // IDs are queued alongside the req bits to keep them aligned through backpressure. for (i <- 0 until totalBallRead) { val bankReadReqWithIds = Wire(Decoupled(new Bundle { - val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) - val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) - val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) + val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) + val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) + val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) val group_id = chiselTypeOf(ballDomain.bankRead(i).group_id) - val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) + val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) })) - bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid - bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id - bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id - bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id - bankReadReqWithIds.bits.group_id := ballDomain.bankRead(i).group_id - bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits - ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready + bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid + bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id + bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id + bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id + bankReadReqWithIds.bits.group_id := ballDomain.bankRead(i).group_id + bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits + ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready val bankReadReqQ = Queue(bankReadReqWithIds, 8) @@ -123,7 +123,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id - memDomain.io.ballDomain.bankRead(i).group_id := bankReadReqQ.bits.group_id + memDomain.io.ballDomain.bankRead(i).group_id := bankReadReqQ.bits.group_id bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready ballDomain.bankRead(i).io.resp <> memDomain.io.ballDomain.bankRead(i).io.resp diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala index b1bb2707..97971d52 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala @@ -4,17 +4,18 @@ import chisel3._ import chisel3.util._ class RowSlotFIFO(maxRows: Int) extends Module { + val io = IO(new Bundle { - val kRows = Input(UInt(log2Ceil(maxRows + 1).W)) - val init = Input(Bool()) - val advance = Input(Bool()) - val head = Output(UInt(log2Ceil(maxRows).W)) + val kRows = Input(UInt(log2Ceil(maxRows + 1).W)) + val init = Input(Bool()) + val advance = Input(Bool()) + val head = Output(UInt(log2Ceil(maxRows).W)) val slotToOverwrite = Output(UInt(log2Ceil(maxRows).W)) }) private val headReg = RegInit(0.U(log2Ceil(maxRows).W)) - io.head := headReg + io.head := headReg io.slotToOverwrite := headReg when(io.init) { @@ -29,8 +30,10 @@ class RowSlotFIFO(maxRows: Int) extends Module { } object RowSlotFIFO { + def logicalToPhysical(head: UInt, logicalRow: UInt, kRows: UInt): UInt = { val sum = head + logicalRow Mux(sum >= kRows, sum - kRows, sum) } + } diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index b6e51d03..fd6a7c30 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -11,13 +11,13 @@ import framework.balldomain.prototype.im2col.configs.Im2colBallParam @instantiable class Im2col(val b: GlobalConfig) extends Module { - private val maxK = Im2colBallParam().InputNum - private val elemWidth = Im2colBallParam().inputWidth - private val bankWidth = b.memDomain.bankWidth - private val lanesPerBeat = 16 - private val laneWidth = bankWidth / lanesPerBeat - private val maxInCol = 32 - private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat + private val maxK = Im2colBallParam().InputNum + private val elemWidth = Im2colBallParam().inputWidth + private val bankWidth = b.memDomain.bankWidth + private val lanesPerBeat = 16 + private val laneWidth = bankWidth / lanesPerBeat + private val maxInCol = 32 + private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat private val maxKernelElems = maxK * maxK require(laneWidth == elemWidth, s"[Im2col] laneWidth($laneWidth) must equal elemWidth($elemWidth)") @@ -25,8 +25,9 @@ class Im2col(val b: GlobalConfig) extends Module { private val mapping = b.ballDomain.ballIdMappings .find(_.ballName == "Im2colBall") .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) - private val inBW = mapping.inBW - private val outBW = mapping.outBW + + private val inBW = mapping.inBW + private val outBW = mapping.outBW @public val io = IO(new Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) @@ -40,7 +41,7 @@ class Im2col(val b: GlobalConfig) extends Module { require(outBW >= 1, "[Im2col] outBW must be >= 1") val idle :: preload_rows :: generate_window :: write_window :: load_next_row :: complete :: Nil = Enum(6) - val state = RegInit(idle) + val state = RegInit(idle) private val robIdReg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) private val rBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) @@ -67,23 +68,23 @@ class Im2col(val b: GlobalConfig) extends Module { rowFifo.io.init := false.B rowFifo.io.advance := false.B - private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) - private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) + private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) private val ldOutstandingReg = RegInit(false.B) private val genElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) - private val wrElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) - private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) - private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) + private val wrElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) + private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) + private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) private def ceilDiv(a: UInt, d: Int): UInt = (a + (d - 1).U) / d.U - private val inColWords = ceilDiv(inColReg, lanesPerBeat) + private val inColWords = ceilDiv(inColReg, lanesPerBeat) private val totalKernelEls = kRowReg * kColReg - private val rowMax = inRowReg - kRowReg - private val colMax = inColReg - kColReg - private val rowEnd = rowPtrReg === (startRowReg + rowMax) - private val colEnd = colPtrReg === (startColReg + colMax) + private val rowMax = inRowReg - kRowReg + private val colMax = inColReg - kColReg + private val rowEnd = rowPtrReg === (startRowReg + rowMax) + private val colEnd = colPtrReg === (startColReg + colMax) private val isLastWindow = rowEnd && colEnd private def laneFromBeat(beat: UInt, lane: UInt): UInt = { @@ -130,10 +131,10 @@ class Im2col(val b: GlobalConfig) extends Module { rBankReg := io.cmdReq.bits.cmd.op1_bank wBankReg := io.cmdReq.bits.cmd.wr_bank - kColReg := io.cmdReq.bits.cmd.special(3, 0) - kRowReg := io.cmdReq.bits.cmd.special(7, 4) - inColReg := io.cmdReq.bits.cmd.special(12, 8) - inRowReg := io.cmdReq.bits.cmd.special(22, 13) + kColReg := io.cmdReq.bits.cmd.special(3, 0) + kRowReg := io.cmdReq.bits.cmd.special(7, 4) + inColReg := io.cmdReq.bits.cmd.special(12, 8) + inRowReg := io.cmdReq.bits.cmd.special(22, 13) startColReg := io.cmdReq.bits.cmd.special(27, 23) startRowReg := io.cmdReq.bits.cmd.special(37, 28) @@ -143,19 +144,19 @@ class Im2col(val b: GlobalConfig) extends Module { rBaseBeatReg := 0.U wBaseBeatReg := 0.U - ldRowIdxReg := 0.U - ldBeatIdxReg := 0.U + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U ldOutstandingReg := false.B - genElemIdxReg := 0.U - wrElemIdxReg := 0.U - packCntReg := 0.U + genElemIdxReg := 0.U + wrElemIdxReg := 0.U + packCntReg := 0.U rowFifo.io.init := true.B - val cmdKCol = io.cmdReq.bits.cmd.special(3, 0) - val cmdKRow = io.cmdReq.bits.cmd.special(7, 4) - val cmdInCol = io.cmdReq.bits.cmd.special(12, 8) - val cmdInRow = io.cmdReq.bits.cmd.special(22, 13) + val cmdKCol = io.cmdReq.bits.cmd.special(3, 0) + val cmdKRow = io.cmdReq.bits.cmd.special(7, 4) + val cmdInCol = io.cmdReq.bits.cmd.special(12, 8) + val cmdInRow = io.cmdReq.bits.cmd.special(22, 13) val invalidShape = (cmdKCol === 0.U) || (cmdKRow === 0.U) || (cmdInCol === 0.U) || (cmdInRow === 0.U) || (cmdInCol < cmdKCol) || (cmdInRow < cmdKRow) @@ -170,8 +171,8 @@ class Im2col(val b: GlobalConfig) extends Module { is(preload_rows) { val doneRows = ldRowIdxReg === kRowReg val canIssue = !doneRows && !ldOutstandingReg && (ldBeatIdxReg < inColWords) - val rowElem = rowPtrReg + ldRowIdxReg - val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg + val rowElem = rowPtrReg + ldRowIdxReg + val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg io.bankRead(0).io.req.valid := canIssue io.bankRead(0).io.req.bits.addr := reqAddr @@ -183,11 +184,11 @@ class Im2col(val b: GlobalConfig) extends Module { when(io.bankRead(0).io.resp.fire) { lineBuffer(ldRowIdxReg)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt - ldOutstandingReg := false.B + ldOutstandingReg := false.B when(ldBeatIdxReg + 1.U === inColWords) { ldBeatIdxReg := 0.U - ldRowIdxReg := ldRowIdxReg + 1.U + ldRowIdxReg := ldRowIdxReg + 1.U }.otherwise { ldBeatIdxReg := ldBeatIdxReg + 1.U } @@ -195,29 +196,29 @@ class Im2col(val b: GlobalConfig) extends Module { when(doneRows && !ldOutstandingReg) { genElemIdxReg := 0.U - state := generate_window + state := generate_window } } is(generate_window) { val startLane = colPtrReg % lanesPerBeat.U - val safeKCol = Mux(kColReg === 0.U, 1.U, kColReg) + val safeKCol = Mux(kColReg === 0.U, 1.U, kColReg) - val t = genElemIdxReg + val t = genElemIdxReg val kRowIdx = t / safeKCol val kColIdx = t % safeKCol val physicalSlot = RowSlotFIFO.logicalToPhysical(rowFifo.io.head, kRowIdx, kRowReg) - val laneSum = startLane + kColIdx - val beatIdx = laneSum / lanesPerBeat.U - val laneIdx = laneSum % lanesPerBeat.U - val beatWord = lineBuffer(physicalSlot)(beatIdx) + val laneSum = startLane + kColIdx + val beatIdx = laneSum / lanesPerBeat.U + val laneIdx = laneSum % lanesPerBeat.U + val beatWord = lineBuffer(physicalSlot)(beatIdx) elemBuffer(t) := laneFromBeat(beatWord, laneIdx) when(genElemIdxReg === (totalKernelEls - 1.U)) { wrElemIdxReg := 0.U - state := write_window + state := write_window }.otherwise { genElemIdxReg := genElemIdxReg + 1.U } @@ -225,7 +226,7 @@ class Im2col(val b: GlobalConfig) extends Module { is(write_window) { val windowDone = wrElemIdxReg === totalKernelEls - val packFull = packCntReg === lanesPerBeat.U + val packFull = packCntReg === lanesPerBeat.U io.bankWrite(0).io.req.valid := packFull io.bankWrite(0).io.req.bits.addr := wBaseBeatReg @@ -235,13 +236,13 @@ class Im2col(val b: GlobalConfig) extends Module { when(!windowDone && !packFull) { packReg(packCntReg) := elemBuffer(wrElemIdxReg) - packCntReg := packCntReg + 1.U - wrElemIdxReg := wrElemIdxReg + 1.U + packCntReg := packCntReg + 1.U + wrElemIdxReg := wrElemIdxReg + 1.U } when(io.bankWrite(0).io.req.fire) { wBaseBeatReg := wBaseBeatReg + 1.U - packCntReg := 0.U + packCntReg := 0.U } when(windowDone) { @@ -254,23 +255,23 @@ class Im2col(val b: GlobalConfig) extends Module { colPtrReg := startColReg rowPtrReg := rowPtrReg + 1.U - ldRowIdxReg := 0.U - ldBeatIdxReg := 0.U + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U ldOutstandingReg := false.B - state := load_next_row + state := load_next_row }.otherwise { - colPtrReg := colPtrReg + 1.U + colPtrReg := colPtrReg + 1.U genElemIdxReg := 0.U - state := generate_window + state := generate_window } } } } is(load_next_row) { - val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) - val rowElem = rowPtrReg + kRowReg - 1.U - val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg + val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) + val rowElem = rowPtrReg + kRowReg - 1.U + val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg val targetSlot = rowFifo.io.slotToOverwrite io.bankRead(0).io.req.valid := canIssue @@ -283,13 +284,13 @@ class Im2col(val b: GlobalConfig) extends Module { when(io.bankRead(0).io.resp.fire) { lineBuffer(targetSlot)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt - ldOutstandingReg := false.B + ldOutstandingReg := false.B when(ldBeatIdxReg + 1.U === inColWords) { - ldBeatIdxReg := 0.U + ldBeatIdxReg := 0.U rowFifo.io.advance := true.B - genElemIdxReg := 0.U - state := generate_window + genElemIdxReg := 0.U + state := generate_window }.otherwise { ldBeatIdxReg := ldBeatIdxReg + 1.U } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index e2c92496..a6f1f5bc 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -86,11 +86,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } for (i <- 0 until inBW) { - io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).bank_id := rbank_reg io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { - io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).bank_id := wbank_reg io.bankWrite(i).group_id := 0.U } diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index c4871e15..c95565c2 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -89,7 +89,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.resp.ready := false.B io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).group_id := 0.U + io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B @@ -99,7 +99,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.wmode := false.B io.bankWrite(i).io.resp.ready := false.B io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).group_id := 0.U + io.bankWrite(i).group_id := 0.U } io.cmdReq.ready := (state === idle) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 10962b7c..72779075 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -52,10 +52,10 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_iter_reg = RegInit(0.U(10.W)) - val wait1_reg = RegInit(false.B) - val wait2_reg = RegInit(false.B) - val wait1_cnt = RegInit(0.U(7.W)) - val wait2_cnt = RegInit(0.U(7.W)) + val wait1_reg = RegInit(false.B) + val wait2_reg = RegInit(false.B) + val wait1_cnt = RegInit(0.U(7.W)) + val wait2_cnt = RegInit(0.U(7.W)) val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) @@ -108,23 +108,22 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { wait2_reg := Mux((op2_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) } - when(wait1_reg){ + when(wait1_reg) { wait1_cnt := wait1_cnt + 1.U - when(wait1_cnt === 32.U){ + when(wait1_cnt === 32.U) { wait1_reg := false.B wait1_cnt := 0.U } } - when(wait2_reg){ + when(wait2_reg) { wait2_cnt := wait2_cnt + 1.U - when(wait2_cnt === 32.U){ + when(wait2_cnt === 32.U) { wait2_reg := false.B wait2_cnt := 0.U } } - // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index cf1d7b86..bf622aac 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -71,10 +71,10 @@ class VecUnit(val b: GlobalConfig) extends Module { io.bankRead(i).io.req <> VecLoadUnit.io.bankReadReq(i) VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).io.resp if (i == 0) { - io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o + io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o io.bankRead(i).group_id := 0.U } else if (i == 1) { - io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o + io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o io.bankRead(i).group_id := 0.U } } @@ -95,7 +95,7 @@ class VecUnit(val b: GlobalConfig) extends Module { io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o io.bankWrite(i).io.req.bits.wmode := true.B - io.bankWrite(i).group_id := i.U + io.bankWrite(i).group_id := i.U } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index b63ba7cc..4d23f043 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -30,12 +30,12 @@ class AccPipe(val b: GlobalConfig) extends Module { val sramRead = Flipped(new SramReadIO(b)) // AccPipe -> bank: req out, resp in val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in - val mem_req = Flipped(new MemRequestIO(b)) - val is_multi = Input(Bool()) + val mem_req = Flipped(new MemRequestIO(b)) + val is_multi = Input(Bool()) - val busy = Output(Bool()) + val busy = Output(Bool()) val group_id = Output(UInt(3.W)) - val bank_id = Output(UInt(b.memDomain.bankNum.W)) + val bank_id = Output(UInt(b.memDomain.bankNum.W)) }) val read :: write :: Nil = Enum(2) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 79b53ccb..a0813512 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -7,9 +7,9 @@ import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} class MemConfigerIO(val b: GlobalConfig) extends Bundle { - val vbank_id = Output(UInt(8.W)) - val is_multi = Output(Bool()) - val alloc = Output(Bool()) + val vbank_id = Output(UInt(8.W)) + val is_multi = Output(Bool()) + val alloc = Output(Bool()) val group_id = Output(UInt(3.W)) } @@ -30,26 +30,26 @@ class MemConfiger(val b: GlobalConfig) extends Module { val state = RegInit(idle) val alloc_reg = RegInit(false.B) val row_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val counter = RegInit(0.U(4.W)) - io.config.bits.is_multi := false.B - io.config.bits.alloc := false.B - io.config.bits.vbank_id := 0.U(8.W) + io.config.bits.is_multi := false.B + io.config.bits.alloc := false.B + io.config.bits.vbank_id := 0.U(8.W) io.config.bits.group_id := 0.U(3.W) - io.config.valid := false.B - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + io.config.valid := false.B + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) when(state === idle) { when(io.cmdReq.valid) { - when(io.cmdReq.bits.cmd.special(4, 0) > 1.U) { //is multi bank + when(io.cmdReq.bits.cmd.special(9, 5) > 1.U) { //is multi bank state := config - row_reg := io.cmdReq.bits.cmd.special(4, 0) - col_reg := io.cmdReq.bits.cmd.special(9, 5) - alloc_reg := io.cmdReq.bits.cmd.special(10) + row_reg := io.cmdReq.bits.cmd.special(4, 0) + col_reg := io.cmdReq.bits.cmd.special(9, 5) + alloc_reg := io.cmdReq.bits.cmd.special(10) vbank_id_reg := io.cmdReq.bits.cmd.bank_id rob_id_reg := io.cmdReq.bits.rob_id @@ -64,13 +64,13 @@ class MemConfiger(val b: GlobalConfig) extends Module { } }.otherwise { - when(counter < row_reg) { - io.config.bits.is_multi := true.B - io.config.bits.alloc := alloc_reg - io.config.bits.vbank_id := vbank_id_reg + when(counter < col_reg) { + io.config.bits.is_multi := true.B + io.config.bits.alloc := alloc_reg + io.config.bits.vbank_id := vbank_id_reg io.config.bits.group_id := counter - io.config.valid := true.B - counter := counter + 1.U + io.config.valid := true.B + counter := counter + 1.U }.otherwise { state := idle counter := 0.U diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 71686b70..647c87d0 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -67,9 +67,9 @@ class MemLoader(val b: GlobalConfig) extends Module { // IMPORTANT: always ready for write response (avoid deadlock) io.bankWrite.io.resp.ready := true.B - io.bankWrite.rob_id := rob_id_reg - io.bankWrite.bank_id := wr_bank_reg - io.bankWrite.ball_id := 0.U + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := wr_bank_reg + io.bankWrite.ball_id := 0.U io.bankWrite.group_id := 0.U // cmdResp (Decoupled): hold valid until accepted diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 25532b17..d854fb49 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -86,9 +86,9 @@ class MemStorer(val b: GlobalConfig) extends Module { // ----------------------------- // SRAM read request // ----------------------------- - io.bankRead.rob_id := rob_id_reg - io.bankRead.bank_id := target_bank - io.bankRead.ball_id := 0.U + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U io.bankRead.group_id := sram_row(1, 0) io.bankRead.io.req.valid := (state === s_issue_sram_req) From 96a8b9c19c63f3c1cbd166f1018944e0ab6933eb Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 2 Mar 2026 20:29:18 +0800 Subject: [PATCH 123/238] [arch] feat: add scoreboard for ILP [bb-tests] del: remove ISAs no longer maintained and relative tests [memdomain] refactor: rewrite design --- arch/src/csrc/include/monitor/trace.h | 27 ++ arch/src/csrc/src/monitor/trace/itrace.cc | 40 +++ arch/src/csrc/src/monitor/trace/mtrace.cc | 41 +++ .../scala/examples/toy/ToyBuckyBall.scala | 24 +- .../scala/examples/toy/balldomain/DISA.scala | 9 - .../toy/balldomain/DomainDecoder.scala | 15 +- .../balldomain/prototype/im2col/FIFO.scala | 13 +- .../balldomain/prototype/im2col/Im2col.scala | 119 ++++---- .../balldomain/prototype/relu/Relu.scala | 4 +- .../prototype/transpose/Transpose.scala | 4 +- .../prototype/vector/VecCtrlUnit.scala | 8 + .../prototype/vector/VecLoadUnit.scala | 43 ++- .../prototype/vector/VecStoreUnit.scala | 163 ++++++---- .../balldomain/prototype/vector/VecUnit.scala | 24 +- .../frontend/configs/FrontendParam.scala | 3 +- .../framework/frontend/configs/default.json | 3 +- .../frontend/decoder/GobalDecoder.scala | 58 +++- .../frontend/globalrs/GlobalROB.scala | 185 ++++++++--- .../globalrs/GlobalReservationStation.scala | 43 ++- .../frontend/scoreboard/BankScoreboard.scala | 109 +++++++ .../framework/frontend/scoreboard/README.md | 286 ++++++++++++++++++ .../frontend/scoreboard/README_EN.md | 283 +++++++++++++++++ .../scala/framework/memdomain/MemDomain.scala | 4 + .../memdomain/backend/MemBackend.scala | 101 +++++++ .../memdomain/backend/accpipe/AccPipe.scala | 8 +- .../memdomain/frontend/MemFrontend.scala | 12 + .../cmd_channel/decoder/DomainDecoder.scala | 32 +- .../outside_channel/MemConfiger.scala | 47 +-- .../frontend/outside_channel/MemLoader.scala | 65 ++-- .../frontend/outside_channel/MemStorer.scala | 106 +++++-- .../memdomain/midend/MemMidend.scala | 47 ++- .../framework/memdomain/midend/bmt/bmt.scala | 1 - bb-tests/workloads/lib/bbhw/isa/23_mset.c | 6 +- bb-tests/workloads/lib/bbhw/isa/24_mvin.c | 5 +- bb-tests/workloads/lib/bbhw/isa/25_mvout.c | 5 +- bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c | 13 - .../workloads/lib/bbhw/isa/27_matmul_ws.c | 14 - .../workloads/lib/bbhw/isa/32_mul_warp16.c | 7 +- bb-tests/workloads/lib/bbhw/isa/33_im2col.c | 12 +- .../workloads/lib/bbhw/isa/34_transpose.c | 4 +- bb-tests/workloads/lib/bbhw/isa/38_relu.c | 6 +- .../workloads/lib/bbhw/isa/39_bbus_config.c | 14 - bb-tests/workloads/lib/bbhw/isa/40_nnlut.c | 13 - bb-tests/workloads/lib/bbhw/isa/41_snn.c | 14 - .../workloads/lib/bbhw/isa/42_abft_systolic.c | 12 - bb-tests/workloads/lib/bbhw/isa/43_conv.c | 17 -- bb-tests/workloads/lib/bbhw/isa/44_cim.c | 15 - bb-tests/workloads/lib/bbhw/isa/45_transfer.c | 14 - bb-tests/workloads/lib/bbhw/isa/7_flush.c | 10 - bb-tests/workloads/lib/bbhw/isa/isa.h | 21 +- .../workloads/src/CTest/toy/CMakeLists.txt | 16 - .../src/CTest/toy/abft_systolic_test.c | 110 ------- .../workloads/src/CTest/toy/aligned_matmul.c | 7 +- .../src/CTest/toy/bbfp_matmul_random1.c | 61 ---- .../src/CTest/toy/bbfp_matmul_random2.c | 61 ---- .../src/CTest/toy/bbfp_matmul_random3.c | 61 ---- bb-tests/workloads/src/CTest/toy/bbfpmatmul.c | 73 ----- bb-tests/workloads/src/CTest/toy/bbfptest.c | 80 ----- bb-tests/workloads/src/CTest/toy/conv_test.c | 145 --------- .../workloads/src/CTest/toy/im2col_test.c | 61 ++-- .../src/CTest/toy/mvin_mvout_acc_test.c | 5 +- .../workloads/src/CTest/toy/mvin_mvout_test.c | 2 - bb-tests/workloads/src/CTest/toy/relu_test.c | 3 +- .../workloads/src/CTest/toy/tiled_matmul.c | 185 ----------- .../workloads/src/CTest/toy/transfer_test.c | 70 ----- .../src/CTest/toy/transpose_matmul.c | 5 +- .../workloads/src/CTest/toy/transpose_test.c | 4 +- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 21 +- .../CTest/toy/vecunit_matmul_16xn_random1.c | 17 +- .../CTest/toy/vecunit_matmul_16xn_random2.c | 21 +- .../CTest/toy/vecunit_matmul_16xn_random3.c | 21 +- .../toy/vecunit_matmul_16xn_zero_random.c | 21 +- .../CTest/toy/vecunit_matmul_col_row_vector.c | 20 +- .../toy/vecunit_matmul_identity_random.c | 21 +- .../src/CTest/toy/vecunit_matmul_ones.c | 2 - .../src/CTest/toy/vecunit_matmul_random1.c | 83 +++-- .../src/CTest/toy/vecunit_matmul_random2.c | 23 +- .../src/CTest/toy/vecunit_matmul_random3.c | 20 +- .../CTest/toy/vecunit_matmul_row_col_vector.c | 23 +- .../CTest/toy/vecunit_matmul_zero_random.c | 20 +- .../toy/vecunit_simple_nn_forward_pass_test.c | 28 +- 81 files changed, 1862 insertions(+), 1557 deletions(-) create mode 100644 arch/src/csrc/include/monitor/trace.h create mode 100644 arch/src/csrc/src/monitor/trace/itrace.cc create mode 100644 arch/src/csrc/src/monitor/trace/mtrace.cc create mode 100644 arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala create mode 100644 arch/src/main/scala/framework/frontend/scoreboard/README.md create mode 100644 arch/src/main/scala/framework/frontend/scoreboard/README_EN.md delete mode 100644 arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala delete mode 100644 bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/40_nnlut.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/41_snn.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/43_conv.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/44_cim.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/45_transfer.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/7_flush.c delete mode 100644 bb-tests/workloads/src/CTest/toy/abft_systolic_test.c delete mode 100644 bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c delete mode 100644 bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c delete mode 100644 bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c delete mode 100644 bb-tests/workloads/src/CTest/toy/bbfpmatmul.c delete mode 100644 bb-tests/workloads/src/CTest/toy/bbfptest.c delete mode 100644 bb-tests/workloads/src/CTest/toy/conv_test.c delete mode 100644 bb-tests/workloads/src/CTest/toy/tiled_matmul.c delete mode 100644 bb-tests/workloads/src/CTest/toy/transfer_test.c diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h new file mode 100644 index 00000000..6b0e22cc --- /dev/null +++ b/arch/src/csrc/include/monitor/trace.h @@ -0,0 +1,27 @@ +#ifndef MONITOR_TRACE_H_ +#define MONITOR_TRACE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// DPI-C function for instruction trace (itrace) +// Called from GlobalROB when instructions are issued or completed +void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete + unsigned int rob_id, unsigned int domain_id, unsigned int funct, + unsigned long long rs1, unsigned long long rs2); + +// DPI-C function for memory trace (mtrace) +// Called from MemBackend when read/write requests are made +void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read + unsigned int channel, unsigned int vbank_id, + unsigned int group_id, unsigned int addr, + unsigned long long data_lo, unsigned long long data_hi); + +#ifdef __cplusplus +} +#endif + +#endif // MONITOR_TRACE_H_ diff --git a/arch/src/csrc/src/monitor/trace/itrace.cc b/arch/src/csrc/src/monitor/trace/itrace.cc new file mode 100644 index 00000000..f17d576a --- /dev/null +++ b/arch/src/csrc/src/monitor/trace/itrace.cc @@ -0,0 +1,40 @@ +#include "monitor/trace.h" +#include "utils/debug.h" +#include +#include + +// Global log file pointer (shared with monitor.cc) +extern const char *log_path; +static FILE *itrace_fp = NULL; + +// Initialize itrace logging +static void init_itrace() { + if (itrace_fp == NULL && log_path != NULL) { + itrace_fp = fopen(log_path, "a"); + if (itrace_fp == NULL) { + panic("Failed to open itrace log file: %s", log_path); + } + } +} + +// DPI-C function for instruction trace (itrace) +// Called when an instruction is issued or completed in GlobalROB +extern "C" void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete + unsigned int rob_id, unsigned int domain_id, + unsigned int funct, unsigned long long rs1, + unsigned long long rs2) { + init_itrace(); + + if (itrace_fp) { + if (is_issue) { + fprintf(itrace_fp, + "[ITRACE] ISSUE rob_id=%u domain=%u funct=0x%02x rs1=0x%016llx " + "rs2=0x%016llx\n", + rob_id, domain_id, funct, rs1, rs2); + } else { + fprintf(itrace_fp, "[ITRACE] COMPLETE rob_id=%u domain=%u funct=0x%02x\n", + rob_id, domain_id, funct); + } + fflush(itrace_fp); + } +} diff --git a/arch/src/csrc/src/monitor/trace/mtrace.cc b/arch/src/csrc/src/monitor/trace/mtrace.cc new file mode 100644 index 00000000..951a8d66 --- /dev/null +++ b/arch/src/csrc/src/monitor/trace/mtrace.cc @@ -0,0 +1,41 @@ +#include "monitor/trace.h" +#include "utils/debug.h" +#include +#include + +// Global log file pointer (shared with monitor.cc) +extern const char *log_path; +static FILE *mtrace_fp = NULL; + +// Initialize mtrace logging +static void init_mtrace() { + if (mtrace_fp == NULL && log_path != NULL) { + mtrace_fp = fopen(log_path, "a"); + if (mtrace_fp == NULL) { + panic("Failed to open mtrace log file: %s", log_path); + } + } +} + +// DPI-C function for memory trace (mtrace) +// Called when MemBackend performs read/write operations +extern "C" void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read + unsigned int channel, unsigned int vbank_id, + unsigned int group_id, unsigned int addr, + unsigned long long data_lo, + unsigned long long data_hi) { + init_mtrace(); + + if (mtrace_fp) { + if (is_write) { + fprintf(mtrace_fp, + "[MTRACE] WRITE ch=%u vbank=%u group=%u addr=0x%08x " + "data=0x%016llx%016llx\n", + channel, vbank_id, group_id, addr, data_hi, data_lo); + } else { + fprintf(mtrace_fp, "[MTRACE] READ ch=%u vbank=%u group=%u addr=0x%08x\n", + channel, vbank_id, group_id, addr); + } + fflush(mtrace_fp); + } +} diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala index a85aa944..0519540d 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/examples/toy/ToyBuckyBall.scala @@ -101,20 +101,20 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) // IDs are queued alongside the req bits to keep them aligned through backpressure. for (i <- 0 until totalBallRead) { val bankReadReqWithIds = Wire(Decoupled(new Bundle { - val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) - val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) - val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) + val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) + val rob_id = chiselTypeOf(ballDomain.bankRead(i).rob_id) + val ball_id = chiselTypeOf(ballDomain.bankRead(i).ball_id) val group_id = chiselTypeOf(ballDomain.bankRead(i).group_id) - val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) + val req = chiselTypeOf(ballDomain.bankRead(i).io.req.bits) })) - bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid - bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id - bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id - bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id - bankReadReqWithIds.bits.group_id := ballDomain.bankRead(i).group_id - bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits - ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready + bankReadReqWithIds.valid := ballDomain.bankRead(i).io.req.valid + bankReadReqWithIds.bits.bank_id := ballDomain.bankRead(i).bank_id + bankReadReqWithIds.bits.rob_id := ballDomain.bankRead(i).rob_id + bankReadReqWithIds.bits.ball_id := ballDomain.bankRead(i).ball_id + bankReadReqWithIds.bits.group_id := ballDomain.bankRead(i).group_id + bankReadReqWithIds.bits.req := ballDomain.bankRead(i).io.req.bits + ballDomain.bankRead(i).io.req.ready := bankReadReqWithIds.ready val bankReadReqQ = Queue(bankReadReqWithIds, 8) @@ -123,7 +123,7 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) memDomain.io.ballDomain.bankRead(i).bank_id := bankReadReqQ.bits.bank_id memDomain.io.ballDomain.bankRead(i).rob_id := bankReadReqQ.bits.rob_id memDomain.io.ballDomain.bankRead(i).ball_id := bankReadReqQ.bits.ball_id - memDomain.io.ballDomain.bankRead(i).group_id := bankReadReqQ.bits.group_id + memDomain.io.ballDomain.bankRead(i).group_id := bankReadReqQ.bits.group_id bankReadReqQ.ready := memDomain.io.ballDomain.bankRead(i).io.req.ready ballDomain.bankRead(i).io.resp <> memDomain.io.ballDomain.bankRead(i).io.resp diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 01bff42c..1866c92d 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -4,17 +4,8 @@ import chisel3._ import chisel3.util._ object DISA { - val BB_BBFP_MUL = BitPat("b0011010") // 26 - val MATMUL_WS = BitPat("b0011011") // 27 val MATMUL_WARP16 = BitPat("b0100000") // 32 val IM2COL = BitPat("b0100001") // 33 val TRANSPOSE = BitPat("b0100010") // 34 val RELU = BitPat("b0100110") // 38 - val CONCAT = BitPat("b0100111") // 39 - val NNLUT = BitPat("b0101000") // 40 - val SNN = BitPat("b0101001") // 41 - val ABFT_SYSTOLIC = BitPat("b0101010") // 42 - val CONV = BitPat("b0101011") // 43 - val CIM = BitPat("b0101100") // 44 - val TRANSFER = BitPat("b0101101") // 45 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index ffd57717..1a5f6989 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -71,14 +71,13 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { func7, ball_default_decode, Array( - MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs2(7, 0), rs2(15, 8), 0.U, rs2(63, 16)), - RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 1.U, rs2(63, 16)), - // Transpose only reads op1 and writes wr_bank; it does NOT consume op2. - // Enabling op2 here can stall/abort when op2_bank defaults to op1_bank. - TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(15, 8), rs2(15, 8), 2.U, rs2(63, 16)), - IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(15, 8), DITER, 3.U, rs2(63, 16)), - CONCAT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 5.U, rs2(63, 16)), - TRANSFER -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs2(7, 0), rs2(15, 8), 6.U, rs2(63, 16)) + // New unified encoding: wr_bank is always at rs1[23:16] + // iter/special shifted in rs2 since wr_bank no longer occupies rs2[7:0] + // op1 op2 wr op1s op2s op1_bank op2_bank wr_bank iter bid special + MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 0.U, rs2(63, 10)), + RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 1.U, rs2(63, 10)), + TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 2.U, rs2(63, 10)), + IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)) ) ) diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala index b1bb2707..97971d52 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/FIFO.scala @@ -4,17 +4,18 @@ import chisel3._ import chisel3.util._ class RowSlotFIFO(maxRows: Int) extends Module { + val io = IO(new Bundle { - val kRows = Input(UInt(log2Ceil(maxRows + 1).W)) - val init = Input(Bool()) - val advance = Input(Bool()) - val head = Output(UInt(log2Ceil(maxRows).W)) + val kRows = Input(UInt(log2Ceil(maxRows + 1).W)) + val init = Input(Bool()) + val advance = Input(Bool()) + val head = Output(UInt(log2Ceil(maxRows).W)) val slotToOverwrite = Output(UInt(log2Ceil(maxRows).W)) }) private val headReg = RegInit(0.U(log2Ceil(maxRows).W)) - io.head := headReg + io.head := headReg io.slotToOverwrite := headReg when(io.init) { @@ -29,8 +30,10 @@ class RowSlotFIFO(maxRows: Int) extends Module { } object RowSlotFIFO { + def logicalToPhysical(head: UInt, logicalRow: UInt, kRows: UInt): UInt = { val sum = head + logicalRow Mux(sum >= kRows, sum - kRows, sum) } + } diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index b6e51d03..0d1644c8 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -11,13 +11,13 @@ import framework.balldomain.prototype.im2col.configs.Im2colBallParam @instantiable class Im2col(val b: GlobalConfig) extends Module { - private val maxK = Im2colBallParam().InputNum - private val elemWidth = Im2colBallParam().inputWidth - private val bankWidth = b.memDomain.bankWidth - private val lanesPerBeat = 16 - private val laneWidth = bankWidth / lanesPerBeat - private val maxInCol = 32 - private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat + private val maxK = Im2colBallParam().InputNum + private val elemWidth = Im2colBallParam().inputWidth + private val bankWidth = b.memDomain.bankWidth + private val lanesPerBeat = 16 + private val laneWidth = bankWidth / lanesPerBeat + private val maxInCol = 32 + private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat private val maxKernelElems = maxK * maxK require(laneWidth == elemWidth, s"[Im2col] laneWidth($laneWidth) must equal elemWidth($elemWidth)") @@ -25,6 +25,7 @@ class Im2col(val b: GlobalConfig) extends Module { private val mapping = b.ballDomain.ballIdMappings .find(_.ballName == "Im2colBall") .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) + private val inBW = mapping.inBW private val outBW = mapping.outBW @@ -40,7 +41,7 @@ class Im2col(val b: GlobalConfig) extends Module { require(outBW >= 1, "[Im2col] outBW must be >= 1") val idle :: preload_rows :: generate_window :: write_window :: load_next_row :: complete :: Nil = Enum(6) - val state = RegInit(idle) + val state = RegInit(idle) private val robIdReg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) private val rBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) @@ -67,23 +68,23 @@ class Im2col(val b: GlobalConfig) extends Module { rowFifo.io.init := false.B rowFifo.io.advance := false.B - private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) - private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) + private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) private val ldOutstandingReg = RegInit(false.B) private val genElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) - private val wrElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) - private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) - private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) + private val wrElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) + private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) + private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) private def ceilDiv(a: UInt, d: Int): UInt = (a + (d - 1).U) / d.U - private val inColWords = ceilDiv(inColReg, lanesPerBeat) + private val inColWords = ceilDiv(inColReg, lanesPerBeat) private val totalKernelEls = kRowReg * kColReg - private val rowMax = inRowReg - kRowReg - private val colMax = inColReg - kColReg - private val rowEnd = rowPtrReg === (startRowReg + rowMax) - private val colEnd = colPtrReg === (startColReg + colMax) + private val rowMax = inRowReg - kRowReg + private val colMax = inColReg - kColReg + private val rowEnd = rowPtrReg === (startRowReg + rowMax) + private val colEnd = colPtrReg === (startColReg + colMax) private val isLastWindow = rowEnd && colEnd private def laneFromBeat(beat: UInt, lane: UInt): UInt = { @@ -130,10 +131,10 @@ class Im2col(val b: GlobalConfig) extends Module { rBankReg := io.cmdReq.bits.cmd.op1_bank wBankReg := io.cmdReq.bits.cmd.wr_bank - kColReg := io.cmdReq.bits.cmd.special(3, 0) - kRowReg := io.cmdReq.bits.cmd.special(7, 4) - inColReg := io.cmdReq.bits.cmd.special(12, 8) - inRowReg := io.cmdReq.bits.cmd.special(22, 13) + kColReg := io.cmdReq.bits.cmd.special(3, 0) + kRowReg := io.cmdReq.bits.cmd.special(7, 4) + inColReg := io.cmdReq.bits.cmd.special(12, 8) + inRowReg := io.cmdReq.bits.cmd.special(22, 13) startColReg := io.cmdReq.bits.cmd.special(27, 23) startRowReg := io.cmdReq.bits.cmd.special(37, 28) @@ -143,19 +144,19 @@ class Im2col(val b: GlobalConfig) extends Module { rBaseBeatReg := 0.U wBaseBeatReg := 0.U - ldRowIdxReg := 0.U - ldBeatIdxReg := 0.U + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U ldOutstandingReg := false.B - genElemIdxReg := 0.U - wrElemIdxReg := 0.U - packCntReg := 0.U + genElemIdxReg := 0.U + wrElemIdxReg := 0.U + packCntReg := 0.U rowFifo.io.init := true.B - val cmdKCol = io.cmdReq.bits.cmd.special(3, 0) - val cmdKRow = io.cmdReq.bits.cmd.special(7, 4) - val cmdInCol = io.cmdReq.bits.cmd.special(12, 8) - val cmdInRow = io.cmdReq.bits.cmd.special(22, 13) + val cmdKCol = io.cmdReq.bits.cmd.special(3, 0) + val cmdKRow = io.cmdReq.bits.cmd.special(7, 4) + val cmdInCol = io.cmdReq.bits.cmd.special(12, 8) + val cmdInRow = io.cmdReq.bits.cmd.special(22, 13) val invalidShape = (cmdKCol === 0.U) || (cmdKRow === 0.U) || (cmdInCol === 0.U) || (cmdInRow === 0.U) || (cmdInCol < cmdKCol) || (cmdInRow < cmdKRow) @@ -170,8 +171,8 @@ class Im2col(val b: GlobalConfig) extends Module { is(preload_rows) { val doneRows = ldRowIdxReg === kRowReg val canIssue = !doneRows && !ldOutstandingReg && (ldBeatIdxReg < inColWords) - val rowElem = rowPtrReg + ldRowIdxReg - val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg + val rowElem = rowPtrReg + ldRowIdxReg + val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg io.bankRead(0).io.req.valid := canIssue io.bankRead(0).io.req.bits.addr := reqAddr @@ -183,11 +184,11 @@ class Im2col(val b: GlobalConfig) extends Module { when(io.bankRead(0).io.resp.fire) { lineBuffer(ldRowIdxReg)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt - ldOutstandingReg := false.B + ldOutstandingReg := false.B when(ldBeatIdxReg + 1.U === inColWords) { ldBeatIdxReg := 0.U - ldRowIdxReg := ldRowIdxReg + 1.U + ldRowIdxReg := ldRowIdxReg + 1.U }.otherwise { ldBeatIdxReg := ldBeatIdxReg + 1.U } @@ -195,29 +196,29 @@ class Im2col(val b: GlobalConfig) extends Module { when(doneRows && !ldOutstandingReg) { genElemIdxReg := 0.U - state := generate_window + state := generate_window } } is(generate_window) { val startLane = colPtrReg % lanesPerBeat.U - val safeKCol = Mux(kColReg === 0.U, 1.U, kColReg) + val safeKCol = Mux(kColReg === 0.U, 1.U, kColReg) - val t = genElemIdxReg + val t = genElemIdxReg val kRowIdx = t / safeKCol val kColIdx = t % safeKCol val physicalSlot = RowSlotFIFO.logicalToPhysical(rowFifo.io.head, kRowIdx, kRowReg) - val laneSum = startLane + kColIdx - val beatIdx = laneSum / lanesPerBeat.U - val laneIdx = laneSum % lanesPerBeat.U - val beatWord = lineBuffer(physicalSlot)(beatIdx) + val laneSum = startLane + kColIdx + val beatIdx = laneSum / lanesPerBeat.U + val laneIdx = laneSum % lanesPerBeat.U + val beatWord = lineBuffer(physicalSlot)(beatIdx) elemBuffer(t) := laneFromBeat(beatWord, laneIdx) when(genElemIdxReg === (totalKernelEls - 1.U)) { wrElemIdxReg := 0.U - state := write_window + state := write_window }.otherwise { genElemIdxReg := genElemIdxReg + 1.U } @@ -225,7 +226,7 @@ class Im2col(val b: GlobalConfig) extends Module { is(write_window) { val windowDone = wrElemIdxReg === totalKernelEls - val packFull = packCntReg === lanesPerBeat.U + val packFull = packCntReg === lanesPerBeat.U io.bankWrite(0).io.req.valid := packFull io.bankWrite(0).io.req.bits.addr := wBaseBeatReg @@ -235,13 +236,13 @@ class Im2col(val b: GlobalConfig) extends Module { when(!windowDone && !packFull) { packReg(packCntReg) := elemBuffer(wrElemIdxReg) - packCntReg := packCntReg + 1.U - wrElemIdxReg := wrElemIdxReg + 1.U + packCntReg := packCntReg + 1.U + wrElemIdxReg := wrElemIdxReg + 1.U } when(io.bankWrite(0).io.req.fire) { wBaseBeatReg := wBaseBeatReg + 1.U - packCntReg := 0.U + packCntReg := 0.U } when(windowDone) { @@ -254,23 +255,23 @@ class Im2col(val b: GlobalConfig) extends Module { colPtrReg := startColReg rowPtrReg := rowPtrReg + 1.U - ldRowIdxReg := 0.U - ldBeatIdxReg := 0.U + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U ldOutstandingReg := false.B - state := load_next_row + state := load_next_row }.otherwise { - colPtrReg := colPtrReg + 1.U + colPtrReg := colPtrReg + 1.U genElemIdxReg := 0.U - state := generate_window + state := generate_window } } } } is(load_next_row) { - val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) - val rowElem = rowPtrReg + kRowReg - 1.U - val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg + val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) + val rowElem = rowPtrReg + kRowReg - 1.U + val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg val targetSlot = rowFifo.io.slotToOverwrite io.bankRead(0).io.req.valid := canIssue @@ -283,13 +284,13 @@ class Im2col(val b: GlobalConfig) extends Module { when(io.bankRead(0).io.resp.fire) { lineBuffer(targetSlot)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt - ldOutstandingReg := false.B + ldOutstandingReg := false.B when(ldBeatIdxReg + 1.U === inColWords) { - ldBeatIdxReg := 0.U + ldBeatIdxReg := 0.U rowFifo.io.advance := true.B - genElemIdxReg := 0.U - state := generate_window + genElemIdxReg := 0.U + state := generate_window }.otherwise { ldBeatIdxReg := ldBeatIdxReg + 1.U } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index e2c92496..a6f1f5bc 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -86,11 +86,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { } for (i <- 0 until inBW) { - io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).bank_id := rbank_reg io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { - io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).bank_id := wbank_reg io.bankWrite(i).group_id := 0.U } diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index c4871e15..c95565c2 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -89,7 +89,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.resp.ready := false.B io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).group_id := 0.U + io.bankRead(i).group_id := 0.U } for (i <- 0 until outBW) { io.bankWrite(i).io.req.valid := false.B @@ -99,7 +99,7 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).io.req.bits.wmode := false.B io.bankWrite(i).io.resp.ready := false.B io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).group_id := 0.U + io.bankWrite(i).group_id := 0.U } io.cmdReq.ready := (state === idle) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala index d92e4bec..8d611130 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala @@ -53,6 +53,14 @@ class VecCtrlUnit(val b: GlobalConfig) extends Module { is_acc := false.B // Deprecated: use wmode instead mode := io.cmdReq.bits.cmd.special(0) + printf( + "[VecCtrl] Received cmd: op1_bank=%d op2_bank=%d wr_bank=%d iter=%d\n", + io.cmdReq.bits.cmd.op1_bank, + io.cmdReq.bits.cmd.op2_bank, + io.cmdReq.bits.cmd.wr_bank, + io.cmdReq.bits.cmd.iter + ) + state := busy } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 10962b7c..0321ad50 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -52,10 +52,10 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_iter_reg = RegInit(0.U(10.W)) - val wait1_reg = RegInit(false.B) - val wait2_reg = RegInit(false.B) - val wait1_cnt = RegInit(0.U(7.W)) - val wait2_cnt = RegInit(0.U(7.W)) + val wait1_reg = RegInit(false.B) + val wait2_reg = RegInit(false.B) + val wait1_cnt = RegInit(0.U(7.W)) + val wait2_cnt = RegInit(0.U(7.W)) val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) @@ -99,32 +99,37 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.bankReadReq(0).bits.addr := op1_addr + op1_iter_counter op1_iter_counter := Mux(io.bankReadReq(0).ready, op1_iter_counter + 1.U, op1_iter_counter) wait1_reg := Mux((op1_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) + when(io.bankReadReq(0).fire) { + printf("[VecLD] op1 bank=%d addr=%d iter_cnt=%d\n", op1_bank, op1_addr + op1_iter_counter, op1_iter_counter) + } } when(state === busy && io.ld_ex_o.ready && !wait2_reg) { - io.bankReadReq(1).valid := op1_iter_counter < iter - io.bankReadReq(1).bits.addr := op2_addr + op1_iter_counter + io.bankReadReq(1).valid := op2_iter_counter < iter + io.bankReadReq(1).bits.addr := op2_addr + op2_iter_counter op2_iter_counter := Mux(io.bankReadReq(1).ready, op2_iter_counter + 1.U, op2_iter_counter) wait2_reg := Mux((op2_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) + when(io.bankReadReq(1).fire) { + printf("[VecLD] op2 bank=%d addr=%d iter_cnt=%d\n", op2_bank, op2_addr + op2_iter_counter, op2_iter_counter) + } } - when(wait1_reg){ + when(wait1_reg) { wait1_cnt := wait1_cnt + 1.U - when(wait1_cnt === 32.U){ + when(wait1_cnt === 32.U) { wait1_reg := false.B wait1_cnt := 0.U } } - when(wait2_reg){ + when(wait2_reg) { wait2_cnt := wait2_cnt + 1.U - when(wait2_cnt === 32.U){ + when(wait2_cnt === 32.U) { wait2_reg := false.B wait2_cnt := 0.U } } - // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- @@ -138,6 +143,22 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.ld_ex_o.bits.op2 := bankRespQueue1.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) ld_ex_iter_reg := ld_ex_iter_reg + 1.U io.ld_ex_o.bits.iter := ld_ex_iter_reg + + // Debug: print first 8 elements of op1 and op2 + when(ld_ex_iter_reg < 8.U) { + printf( + "[VecLD_DATA] iter=%d op1[0-3]=%d,%d,%d,%d op2[0-3]=%d,%d,%d,%d\n", + ld_ex_iter_reg, + io.ld_ex_o.bits.op1(0), + io.ld_ex_o.bits.op1(1), + io.ld_ex_o.bits.op1(2), + io.ld_ex_o.bits.op1(3), + io.ld_ex_o.bits.op2(0), + io.ld_ex_o.bits.op2(1), + io.ld_ex_o.bits.op2(2), + io.ld_ex_o.bits.op2(3) + ) + } }.otherwise { io.ld_ex_o.valid := false.B io.ld_ex_o.bits.iter := 0.U diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index d70947cf..924ffb8f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -22,13 +22,6 @@ class ex_st_req(b: GlobalConfig) extends Bundle { val iter = UInt(10.W) } -class BankWriteEntry(b: GlobalConfig) extends Bundle { - val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) - val data = UInt(b.memDomain.bankWidth.W) - val mask = Vec(b.memDomain.bankMaskLen, Bool()) - val wmode = Bool() -} - @instantiable class VecStoreUnit(val b: GlobalConfig) extends Module { val config = VectorBallParam() @@ -49,14 +42,20 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { val cmdResp_o = Valid(new Bundle { val commit = Bool() }) }) - val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) - val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) + val idle :: busy :: write :: wait_last :: Nil = Enum(4) + val state = RegInit(idle) + + // Register to hold data from EX unit + val data_valid = RegInit(false.B) + val data_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val data_vec = Reg(Vec(InputNum, UInt(accWidth.W))) - val writeQueues = VecInit(Seq.fill(outBW)(Module(new Queue(new BankWriteEntry(b), 16)).io)) + // Track which channels have fired + val channel_fired = RegInit(VecInit(Seq.fill(outBW)(false.B))) // ----------------------------------------------------------------------------- // Set registers when Ctrl instruction arrives @@ -68,59 +67,124 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) iter_counter := 0.U + data_valid := false.B state := busy + + printf( + "[VecST_CTRL] Received ctrl: wr_bank=%d wr_bank_addr=%d iter=%d\n", + io.ctrl_st_i.bits.wr_bank, + io.ctrl_st_i.bits.wr_bank_addr, + io.ctrl_st_i.bits.iter + ) } // ----------------------------------------------------------------------------- -// Accept computation results from EX unit and push to write queues +// Accept computation results from EX unit // ----------------------------------------------------------------------------- - io.ex_st_i.ready := state === busy && writeQueues.forall(_.enq.ready) - - for (i <- 0 until outBW) { - writeQueues(i).enq.valid := false.B - writeQueues(i).enq.bits := DontCare - } + io.ex_st_i.ready := (state === busy || state === write) && !data_valid when(io.ex_st_i.fire) { - for (i <- 0 until outBW) { - val elementsPerChannel = InputNum / outBW - val startIdx = i * elementsPerChannel - val endIdx = startIdx + elementsPerChannel - 1 - - val entry = Wire(new BankWriteEntry(b)) - entry.addr := wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) - entry.data := Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) - entry.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - entry.wmode := true.B + // Debug: print first 8 results with all 16 elements + when(iter_counter < 8.U) { + printf( + "[VecST] iter=%d rst[0-15]=%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d addr=%d\n", + iter_counter, + io.ex_st_i.bits.rst(0), + io.ex_st_i.bits.rst(1), + io.ex_st_i.bits.rst(2), + io.ex_st_i.bits.rst(3), + io.ex_st_i.bits.rst(4), + io.ex_st_i.bits.rst(5), + io.ex_st_i.bits.rst(6), + io.ex_st_i.bits.rst(7), + io.ex_st_i.bits.rst(8), + io.ex_st_i.bits.rst(9), + io.ex_st_i.bits.rst(10), + io.ex_st_i.bits.rst(11), + io.ex_st_i.bits.rst(12), + io.ex_st_i.bits.rst(13), + io.ex_st_i.bits.rst(14), + io.ex_st_i.bits.rst(15), + wr_bank_addr + iter_counter + ) + } - writeQueues(i).enq.valid := true.B - writeQueues(i).enq.bits := entry + // Latch data + data_valid := true.B + data_addr := wr_bank_addr + iter_counter + data_vec := io.ex_st_i.bits.rst + state := write + // Reset channel_fired when receiving new data + for (i <- 0 until outBW) { + channel_fired(i) := false.B } - iter_counter := iter_counter + 1.U } // ----------------------------------------------------------------------------- -// Drain write queues to bankWrite interface +// Write data to banks // ----------------------------------------------------------------------------- + // Default values for bankWrite io.bankWrite.foreach { acc => acc.req.valid := false.B acc.req.bits.addr := 0.U - acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) + acc.req.bits.data := 0.U acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) acc.req.bits.wmode := false.B - acc.resp.ready := false.B + acc.resp.ready := true.B } - for (i <- 0 until outBW) { - writeQueues(i).deq.ready := false.B + when(state === write && data_valid) { + val all_fired = channel_fired.reduce(_ && _) + + printf("[VecST_WRITE] state=write data_valid=%d all_fired=%d iter_counter=%d\n", data_valid, all_fired, iter_counter) - when(writeQueues(i).deq.valid) { - io.bankWrite(i).req.valid := true.B - io.bankWrite(i).req.bits.addr := writeQueues(i).deq.bits.addr - io.bankWrite(i).req.bits.data := writeQueues(i).deq.bits.data - io.bankWrite(i).req.bits.mask := writeQueues(i).deq.bits.mask - io.bankWrite(i).req.bits.wmode := writeQueues(i).deq.bits.wmode - writeQueues(i).deq.ready := io.bankWrite(i).req.ready + for (i <- 0 until outBW) { + val elementsPerChannel = InputNum / outBW + val startIdx = i * elementsPerChannel + val endIdx = startIdx + elementsPerChannel - 1 + + // Debug: print each channel's status (always print, not just when !fired) + printf( + "[VecST_WRITE] ch[%d]: fired=%d valid=%d ready=%d\n", + i.U, + channel_fired(i), + io.bankWrite(i).req.valid, + io.bankWrite(i).req.ready + ) + + // Only send request if this channel hasn't fired yet + when(!channel_fired(i)) { + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := data_addr + io.bankWrite(i).req.bits.data := Cat(data_vec.slice(startIdx, endIdx + 1).reverse) + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + io.bankWrite(i).req.bits.wmode := true.B // Accumulator mode + + // Mark as fired when handshake completes + when(io.bankWrite(i).req.ready) { + channel_fired(i) := true.B + } + } + } + + when(all_fired) { + printf("[VecST_WRITE] All channels fired, advancing to next iter\n") + data_valid := false.B + iter_counter := iter_counter + 1.U + + // Reset channel_fired for next iter + for (i <- 0 until outBW) { + channel_fired(i) := false.B + } + + // Check if this is the last iter + when(iter_counter + 1.U >= iter) { + printf("[VecST_WRITE] Last iter, going to wait_last\n") + state := wait_last + }.otherwise { + printf("[VecST_WRITE] Going back to busy\n") + state := busy + } } } @@ -128,12 +192,9 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { io.wr_bank_o := wr_bank // ----------------------------------------------------------------------------- -// Reset iter counter, commit cmdResp, return to idle state +// Wait one cycle for last write to complete, then return to idle // ----------------------------------------------------------------------------- - val allQueuesEmpty = writeQueues.forall(q => !q.deq.valid) - val allDataEnqueued = state === busy && iter_counter >= iter - - when(allDataEnqueued && allQueuesEmpty) { + when(state === wait_last) { state := idle io.cmdResp_o.valid := true.B io.cmdResp_o.bits.commit := true.B diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala index cf1d7b86..4c67005c 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecUnit.scala @@ -71,10 +71,10 @@ class VecUnit(val b: GlobalConfig) extends Module { io.bankRead(i).io.req <> VecLoadUnit.io.bankReadReq(i) VecLoadUnit.io.bankReadResp(i) <> io.bankRead(i).io.resp if (i == 0) { - io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o + io.bankRead(i).bank_id := VecLoadUnit.io.op1_bank_o io.bankRead(i).group_id := 0.U } else if (i == 1) { - io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o + io.bankRead(i).bank_id := VecLoadUnit.io.op2_bank_o io.bankRead(i).group_id := 0.U } } @@ -91,11 +91,29 @@ class VecUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- VecStoreUnit.io.ctrl_st_i <> VecCtrlUnit.io.ctrl_st_o VecStoreUnit.io.ex_st_i <> VecEX.io.ex_st_o + + // Debug: print wr_bank_o + when(VecStoreUnit.io.ctrl_st_i.fire) { + printf("[VecUnit] VecStoreUnit wr_bank_o=%d\n", VecStoreUnit.io.wr_bank_o) + } + for (i <- 0 until outBW) { io.bankWrite(i).io <> VecStoreUnit.io.bankWrite(i) io.bankWrite(i).bank_id := VecStoreUnit.io.wr_bank_o io.bankWrite(i).io.req.bits.wmode := true.B - io.bankWrite(i).group_id := i.U + io.bankWrite(i).group_id := i.U + + // Debug: print all channels + when(io.bankWrite(i).io.req.valid) { + printf( + "[VecUnit] bankWrite[%d]: bank_id=%d group_id=%d valid=%d ready=%d\n", + i.U, + io.bankWrite(i).bank_id, + io.bankWrite(i).group_id, + io.bankWrite(i).io.req.valid, + io.bankWrite(i).io.req.ready + ) + } } VecCtrlUnit.io.cmdResp_i <> VecStoreUnit.io.cmdResp_o diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index 38d08b24..4a8d8bf8 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -7,7 +7,8 @@ import upickle.default._ */ case class FrontendParam( rob_entries: Int, - rs_out_of_order_response: Boolean) + rs_out_of_order_response: Boolean, + bank_id_len: Int) object FrontendParam { implicit val rw: ReadWriter[FrontendParam] = macroRW diff --git a/arch/src/main/scala/framework/frontend/configs/default.json b/arch/src/main/scala/framework/frontend/configs/default.json index f85dc375..3fda4d09 100644 --- a/arch/src/main/scala/framework/frontend/configs/default.json +++ b/arch/src/main/scala/framework/frontend/configs/default.json @@ -1,4 +1,5 @@ { "rob_entries": 16, - "rs_out_of_order_response": true + "rs_out_of_order_response": true, + "bank_id_len": 8 } diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index 72b6170a..12e7abd4 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.tile._ import framework.frontend.decoder.GISA._ import framework.memdomain.frontend.cmd_channel.decoder.DISA._ import framework.gpdomain.sequencer.decoder.DISA._ +import framework.frontend.scoreboard.BankAccessInfo import framework.core.rocket.RoCCCommandBB @@ -18,14 +19,18 @@ class BuckyballRawCmd(val b: GlobalConfig) extends Bundle { val cmd = new RoCCCommandBB(b.core.xLen) } -class PostGDCmd(b: GlobalConfig) extends Bundle { - val domain_id = UInt(4.W) - val cmd = new RoCCCommandBB(b.core.xLen) +class PostGDCmd(val b: GlobalConfig) extends Bundle { + val domain_id = UInt(4.W) + val cmd = new RoCCCommandBB(b.core.xLen) + val bankAccess = new BankAccessInfo(log2Up(b.memDomain.bankNum)) + val isFence = Bool() } @instantiable class GlobalDecoder(val b: GlobalConfig) extends Module { + val bankIdLen = b.frontend.bank_id_len + @public val io = IO(new Bundle { @@ -41,6 +46,7 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { val func7 = io.id_i.bits.cmd.funct val opcode = io.id_i.bits.cmd.opcode + val rs1 = io.id_i.bits.cmd.rs1Data // Instruction type determination: distinguish Ball, Mem, Fence, GP (RVV) instructions val is_mem_inst = (func7 === MVIN_BITPAT) || @@ -67,8 +73,48 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { ) ) + // ------------------------------------------------------------------------- + // Bank access info extraction — read valid flags from rs1[24:26] + // + // Unified rs1 layout (defined in isa.h): + // rs1[7:0] = bank_0 (rd_bank_0 or wr_bank for MVIN/MSET) + // rs1[15:8] = bank_1 (rd_bank_1, dual-operand only) + // rs1[23:16] = bank_2 (wr_bank for Ball instructions) + // rs1[24] = rd_bank_0_valid flag (BB_RD0) + // rs1[25] = rd_bank_1_valid flag (BB_RD1) + // rs1[26] = wr_bank_valid flag (BB_WR) + // rs1[63:27] = instruction-specific (mem_addr for MVIN/MVOUT, etc.) + // ------------------------------------------------------------------------- + val bankAccess = Wire(new BankAccessInfo(bankIdLen)) + + bankAccess.rd_bank_0_valid := rs1(24) + bankAccess.rd_bank_0_id := rs1(bankIdLen - 1, 0) + bankAccess.rd_bank_1_valid := rs1(25) + bankAccess.rd_bank_1_id := rs1(bankIdLen + 7, 8) + bankAccess.wr_bank_valid := rs1(26) + // For Mem instructions (MVIN/MSET), wr_bank is bank_0 (rs1[7:0]) + // For Ball instructions, wr_bank is bank_2 (rs1[23:16]) + bankAccess.wr_bank_id := Mux(is_mem_inst, rs1(bankIdLen - 1, 0), rs1(bankIdLen + 15, 16)) + // Output control - io.id_o.valid := io.id_i.valid - io.id_o.bits.domain_id := domain_id - io.id_o.bits.cmd := io.id_i.bits.cmd + io.id_o.valid := io.id_i.valid + io.id_o.bits.domain_id := domain_id + io.id_o.bits.cmd := io.id_i.bits.cmd + io.id_o.bits.bankAccess := bankAccess + io.id_o.bits.isFence := is_frontend_inst + + // Debug: print bank access info for NPU instructions + when(io.id_o.fire && !is_frontend_inst && !is_gp_inst) { + printf( + "[GD] func7=%d rs1=0x%x rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + func7, + rs1, + bankAccess.rd_bank_0_valid, + bankAccess.rd_bank_0_id, + bankAccess.rd_bank_1_valid, + bankAccess.rd_bank_1_id, + bankAccess.wr_bank_valid, + bankAccess.wr_bank_id + ) + } } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 35d49732..07cbad84 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -6,10 +6,54 @@ import chisel3.experimental._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig import framework.frontend.decoder.PostGDCmd +import framework.frontend.scoreboard.BankScoreboard + +// DPI-C BlackBox for instruction trace +class ITraceDPI extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { + val is_issue = Input(UInt(8.W)) + val rob_id = Input(UInt(32.W)) + val domain_id = Input(UInt(32.W)) + val funct = Input(UInt(32.W)) + val rs1 = Input(UInt(64.W)) + val rs2 = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline("ITraceDPI.v", + """ + |import "DPI-C" function void dpi_itrace( + | input byte unsigned is_issue, + | input int unsigned rob_id, + | input int unsigned domain_id, + | input int unsigned funct, + | input longint unsigned rs1, + | input longint unsigned rs2 + |); + | + |module ITraceDPI( + | input [7:0] is_issue, + | input [31:0] rob_id, + | input [31:0] domain_id, + | input [31:0] funct, + | input [63:0] rs1, + | input [63:0] rs2, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2); + | end + | end + |endmodule + """.stripMargin) +} @instantiable class GlobalROB(val b: GlobalConfig) extends Module { + val bankIdLen = b.frontend.bank_id_len + @public val io = IO(new Bundle { // Allocation interface @@ -34,6 +78,19 @@ class GlobalROB(val b: GlobalConfig) extends Module { val entry_complete = Output(Vec(b.frontend.rob_entries, Bool())) }) + // Bank Scoreboard — instruction-agnostic hazard detection + val scoreboard: Instance[BankScoreboard] = Instantiate(new BankScoreboard(b.memDomain.bankNum, b.frontend.rob_entries)) + + // Instruction trace DPI-C module + val itrace = Module(new ITraceDPI) + itrace.io.is_issue := 0.U + itrace.io.rob_id := 0.U + itrace.io.domain_id := 0.U + itrace.io.funct := 0.U + itrace.io.rs1 := 0.U + itrace.io.rs2 := 0.U + itrace.io.enable := false.B + // Circular ROB structure val robEntries = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(0.U.asTypeOf(new GlobalRobEntry(b))))) @@ -57,9 +114,13 @@ class GlobalROB(val b: GlobalConfig) extends Module { val isEmpty = headPtr === tailPtr && !robValid(headPtr) val isFull = headPtr === tailPtr && robValid(headPtr) -// ----------------------------------------------------------------------------- + // Helper: circular pointer arithmetic + def wrapPtr(v: UInt): UInt = Mux(v >= b.frontend.rob_entries.U, v - b.frontend.rob_entries.U, v) + +// ============================================================================= // Inbound - instruction allocation -// ----------------------------------------------------------------------------- +// Fence instructions are filtered out by GlobalReservationStation and never enter ROB. +// ============================================================================= io.alloc.ready := !isFull when(io.alloc.fire) { @@ -72,12 +133,23 @@ class GlobalROB(val b: GlobalConfig) extends Module { // Update tail pointer and rob_id counter (circular) tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) + + printf("[ROB ALLOC] rob_id=%d domain=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + robIdCounter, io.alloc.bits.domain_id, io.alloc.bits.cmd.funct, + io.alloc.bits.bankAccess.rd_bank_0_valid, io.alloc.bits.bankAccess.rd_bank_0_id, + io.alloc.bits.bankAccess.rd_bank_1_valid, io.alloc.bits.bankAccess.rd_bank_1_id, + io.alloc.bits.bankAccess.wr_bank_valid, io.alloc.bits.bankAccess.wr_bank_id) } -// ----------------------------------------------------------------------------- +// ============================================================================= // Completion signal processing -// ----------------------------------------------------------------------------- +// ============================================================================= io.complete.ready := true.B + + // Default: scoreboard complete not active + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + when(io.complete.fire) { val completeId = io.complete.bits robComplete(completeId) := true.B @@ -85,12 +157,30 @@ class GlobalROB(val b: GlobalConfig) extends Module { when(robIssued(completeId)) { issuedCount := issuedCount - 1.U } + // Update scoreboard: release bank resources + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(completeId).cmd.bankAccess + + // Instruction trace: complete + itrace.io.is_issue := 0.U + itrace.io.rob_id := completeId + itrace.io.domain_id := robEntries(completeId).cmd.domain_id + itrace.io.funct := robEntries(completeId).cmd.cmd.funct + itrace.io.rs1 := robEntries(completeId).cmd.cmd.rs1 + itrace.io.rs2 := robEntries(completeId).cmd.cmd.rs2 + itrace.io.enable := true.B + + printf("[ROB COMPLETE] rob_id=%d domain=%d func7=%d\n", + completeId, robEntries(completeId).cmd.domain_id, robEntries(completeId).cmd.cmd.funct) } -// ----------------------------------------------------------------------------- -// Outbound - issue instructions in order (starting from head) -// ----------------------------------------------------------------------------- - // Find first valid and unissued instruction starting from head +// ============================================================================= +// Outbound - issue instructions with hazard detection +// +// Scan from head to find the first issuable instruction that: +// 1. is valid && !issued && !complete +// 2. has no bank hazard (checked via scoreboard) +// ============================================================================= val canIssue = Wire(Bool()) val issuePtr = Wire(UInt(log2Up(b.frontend.rob_entries).W)) @@ -98,40 +188,73 @@ class GlobalROB(val b: GlobalConfig) extends Module { canIssue := false.B issuePtr := headPtr - // Scan from head to find first issuable instruction val scanValid = Wire(Vec(b.frontend.rob_entries, Bool())) for (i <- 0 until b.frontend.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) + val ptr = wrapPtr(headPtr + i.U) scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) } - // Find first issuable position + // Find first candidate val firstValid = PriorityEncoder(scanValid.asUInt) val hasValid = scanValid.asUInt.orR - val actualIssuePtr = Mux( - headPtr + firstValid >= b.frontend.rob_entries.U, - headPtr + firstValid - b.frontend.rob_entries.U, - headPtr + firstValid - ) + val actualIssuePtr = wrapPtr(headPtr + firstValid) + + // Scoreboard hazard query for the selected candidate + scoreboard.query := robEntries(actualIssuePtr).cmd.bankAccess + val noHazard = !scoreboard.hasHazard + + // Debug: print when a candidate is blocked by hazard + when(hasValid && scoreboard.hasHazard) { + printf("[ROB HAZARD] ptr=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + actualIssuePtr, robEntries(actualIssuePtr).cmd.cmd.funct, + robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_valid, + robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_id, + robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_valid, + robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_id, + robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_valid, + robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_id) + } - // Can only issue if issue limit is not reached + // Can only issue if issue limit is not reached and no bank hazard val canIssueMore = issuedCount < maxIssueLimit - canIssue := hasValid && canIssueMore + canIssue := hasValid && canIssueMore && noHazard issuePtr := actualIssuePtr io.issue.valid := canIssue io.issue.bits := robEntries(issuePtr) + // Default: scoreboard issue not active + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + when(io.issue.fire) { robIssued(issuePtr) := true.B issuedCount := issuedCount + 1.U + // Update scoreboard: claim bank resources + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(issuePtr).cmd.bankAccess + + // Instruction trace: issue + itrace.io.is_issue := 1.U + itrace.io.rob_id := robEntries(issuePtr).rob_id + itrace.io.domain_id := robEntries(issuePtr).cmd.domain_id + itrace.io.funct := robEntries(issuePtr).cmd.cmd.funct + itrace.io.rs1 := robEntries(issuePtr).cmd.cmd.rs1 + itrace.io.rs2 := robEntries(issuePtr).cmd.cmd.rs2 + itrace.io.enable := true.B + + printf("[ROB ISSUE] rob_id=%d domain=%d func7=%d ptr=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + robEntries(issuePtr).rob_id, robEntries(issuePtr).cmd.domain_id, robEntries(issuePtr).cmd.cmd.funct, + issuePtr, + robEntries(issuePtr).cmd.bankAccess.rd_bank_0_valid, robEntries(issuePtr).cmd.bankAccess.rd_bank_0_id, + robEntries(issuePtr).cmd.bankAccess.rd_bank_1_valid, robEntries(issuePtr).cmd.bankAccess.rd_bank_1_id, + robEntries(issuePtr).cmd.bankAccess.wr_bank_valid, robEntries(issuePtr).cmd.bankAccess.wr_bank_id) } -// ----------------------------------------------------------------------------- +// ============================================================================= // Instruction commit - commit all completed instructions out-of-order -// ----------------------------------------------------------------------------- - // Commit all completed instructions +// ============================================================================= for (i <- 0 until b.frontend.rob_entries) { when(robValid(i.U) && robComplete(i.U)) { robValid(i.U) := false.B @@ -141,31 +264,21 @@ class GlobalROB(val b: GlobalConfig) extends Module { } // Update head pointer: skip all completed (about to be cleared) positions - // Find first "valid and incomplete" instruction position starting from head val nextHeadCandidates = Wire(Vec(b.frontend.rob_entries, Bool())) for (i <- 0 until b.frontend.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) - // Entry is valid and incomplete (will not be committed) + val ptr = wrapPtr(headPtr + i.U) nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) } val hasUncommitted = nextHeadCandidates.asUInt.orR val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) + val nextHeadPtr = wrapPtr(headPtr + nextHeadOffset) - val nextHeadPtr = Mux( - headPtr + nextHeadOffset >= b.frontend.rob_entries.U, - headPtr + nextHeadOffset - b.frontend.rob_entries.U, - headPtr + nextHeadOffset - ) - - // Update head pointer: - // - If there are uncompleted instructions, move head to first uncompleted position - // - If there are no uncompleted instructions (all complete), move head to tail (ROB is empty) headPtr := Mux(hasUncommitted, nextHeadPtr, tailPtr) -// ----------------------------------------------------------------------------- -// Status signals - exposed to reservation station -// ----------------------------------------------------------------------------- +// ============================================================================= +// Status signals +// ============================================================================= io.empty := isEmpty io.full := isFull io.head_ptr := headPtr diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index ec47b5d7..91e0d4c4 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -7,10 +7,11 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.top.GlobalConfig import framework.frontend.decoder.{DomainId, PostGDCmd} import framework.frontend.decoder.GISA._ +import framework.frontend.scoreboard.{BankAccessInfo, BankScoreboard} import framework.core.rocket.RoCCResponseBB -// Global ROB entry - only contains basic information, does not include specific instruction decoding -class GlobalRobEntry(b: GlobalConfig) extends Bundle { +// Global ROB entry - contains instruction + bank access info +class GlobalRobEntry(val b: GlobalConfig) extends Bundle { val cmd = new PostGDCmd(b) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } @@ -23,8 +24,6 @@ class GlobalRsComplete(b: GlobalConfig) extends Bundle { val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } -// No additional interface Bundle needed, defined directly in IO - // Global reservation station - between GlobalDecoder and each Domain @instantiable class GlobalReservationStation(val b: GlobalConfig) extends Module { @@ -57,33 +56,33 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) // ----------------------------------------------------------------------------- -// Fence handling - fence instructions require ROB to be empty before execution +// Fence handling — fence does NOT enter ROB. +// When a fence arrives, hold busy (stop CPU) until ROB drains completely. // ----------------------------------------------------------------------------- - val fenceActive = RegInit(false.B) - // Cannot use fire, would form a loop - val func7 = io.global_decode_cmd_i.bits.cmd.funct - val isFenceCmd = io.global_decode_cmd_i.valid && (func7 === FENCE_BITPAT) - val robEmpty = rob.io.empty + val isFenceCmd = io.global_decode_cmd_i.valid && io.global_decode_cmd_i.bits.isFence - // Fence state machine: only activate when fence instruction is accepted (fire) - when(io.global_decode_cmd_i.fire && isFenceCmd && !fenceActive) { + // Fence active state: set when fence arrives, cleared when ROB is empty + val fenceActive = RegInit(false.B) + when(isFenceCmd && !fenceActive) { fenceActive := true.B } - when(fenceActive && robEmpty) { + when(fenceActive && rob.io.empty) { fenceActive := false.B } // ----------------------------------------------------------------------------- -// Inbound - instruction allocation (Fence instructions do not enter ROB) +// Inbound - instruction allocation (only non-fence instructions enter ROB) // ----------------------------------------------------------------------------- - // Filter out fence instructions (they don't need ROB tracking) - rob.io.alloc.valid := io.global_decode_cmd_i.valid && !isFenceCmd + rob.io.alloc.valid := io.global_decode_cmd_i.valid && !io.global_decode_cmd_i.bits.isFence && !fenceActive rob.io.alloc.bits := io.global_decode_cmd_i.bits - // Backpressure logic: - // - Normal instructions: wait for ROB ready - // - Fence instructions: wait for ROB empty (to ensure ordering) - io.global_decode_cmd_i.ready := Mux(isFenceCmd, robEmpty, rob.io.alloc.ready) + // Backpressure: during fence, accept the fence cmd immediately but block further cmds + // until ROB drains. For normal cmds, wait for ROB ready. + io.global_decode_cmd_i.ready := Mux( + io.global_decode_cmd_i.bits.isFence, + !fenceActive, // Accept fence if not already processing one + rob.io.alloc.ready && !fenceActive // Normal cmd: ROB ready and no fence active + ) // ----------------------------------------------------------------------------- // Outbound - instruction issue (dispatch to corresponding domain based on domain_id) @@ -143,11 +142,9 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Response generation // ----------------------------------------------------------------------------- - // Buckyball does not generate RoCC responses for normal instructions - // Only performance counter or special commands would generate responses - // This matches Gemmini's behavior where io.resp is only connected to counters io.rs_rocc_o.resp.valid := false.B io.rs_rocc_o.resp.bits.rd := 0.U io.rs_rocc_o.resp.bits.data := 0.U + // busy when ROB is not empty OR fence is active (waiting for drain) io.rs_rocc_o.busy := !rob.io.empty || fenceActive } diff --git a/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala b/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala new file mode 100644 index 00000000..7da04924 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala @@ -0,0 +1,109 @@ +package framework.frontend.scoreboard + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + +/** + * Bank access information extracted from instruction encoding. + * This is instruction-agnostic — the scoreboard only sees read/write bank sets. + */ +class BankAccessInfo(val bankIdLen: Int) extends Bundle { + val rd_bank_0_valid = Bool() + val rd_bank_0_id = UInt(bankIdLen.W) + val rd_bank_1_valid = Bool() + val rd_bank_1_id = UInt(bankIdLen.W) + val wr_bank_valid = Bool() + val wr_bank_id = UInt(bankIdLen.W) +} + +object BankAccessInfo { + + /** Create a zero-valued (no access) BankAccessInfo */ + def none(bankIdLen: Int): BankAccessInfo = { + val w = Wire(new BankAccessInfo(bankIdLen)) + w.rd_bank_0_valid := false.B + w.rd_bank_0_id := 0.U + w.rd_bank_1_valid := false.B + w.rd_bank_1_id := 0.U + w.wr_bank_valid := false.B + w.wr_bank_id := 0.U + w + } + +} + +/** + * Bank Scoreboard — tracks in-flight read/write operations per bank. + * + * Hazard rules: + * - Read bank X → requires bankWrBusy(X) == false (RAW) + * - Write bank X → requires bankRdCount(X) == 0 (WAR) + * AND bankWrBusy(X) == false (WAW) + * + * bankRdCount: multi-bit counter (multiple concurrent readers allowed, RR is OK) + * bankWrBusy: 1-bit flag (WAW rule guarantees at most 1 writer in-flight) + */ +@instantiable +class BankScoreboard(val bankNum: Int, val robEntries: Int) extends Module { + + val bankIdLen = log2Up(bankNum) + val cntWidth = log2Ceil(robEntries + 1) + + // Issue: increment counters for the accessed banks + @public + val issue = IO(Flipped(Valid(new BankAccessInfo(bankIdLen)))) + // Complete: decrement counters for the accessed banks + @public + val complete = IO(Flipped(Valid(new BankAccessInfo(bankIdLen)))) + // Hazard query: check if the given access would conflict + @public + val query = IO(Input(new BankAccessInfo(bankIdLen))) + @public + val hasHazard = IO(Output(Bool())) + + // Read counter: multi-bit, allows concurrent readers + val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) + // Write flag: 1-bit, WAW ensures at most 1 writer in-flight per bank + val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) + + // --- Hazard detection --- + val q = query + val rd0_hazard = q.rd_bank_0_valid && bankWrBusy(q.rd_bank_0_id) + val rd1_hazard = q.rd_bank_1_valid && bankWrBusy(q.rd_bank_1_id) + + val wr_hazard = q.wr_bank_valid && ( + bankRdCount(q.wr_bank_id) =/= 0.U || + bankWrBusy(q.wr_bank_id) + ) + + hasHazard := rd0_hazard || rd1_hazard || wr_hazard + + // --- Issue: increment counters --- + when(issue.valid) { + val info = issue.bits + when(info.rd_bank_0_valid) { + bankRdCount(info.rd_bank_0_id) := bankRdCount(info.rd_bank_0_id) + 1.U + } + when(info.rd_bank_1_valid) { + bankRdCount(info.rd_bank_1_id) := bankRdCount(info.rd_bank_1_id) + 1.U + } + when(info.wr_bank_valid) { + bankWrBusy(info.wr_bank_id) := true.B + } + } + + // --- Complete: decrement counters --- + when(complete.valid) { + val info = complete.bits + when(info.rd_bank_0_valid) { + bankRdCount(info.rd_bank_0_id) := bankRdCount(info.rd_bank_0_id) - 1.U + } + when(info.rd_bank_1_valid) { + bankRdCount(info.rd_bank_1_id) := bankRdCount(info.rd_bank_1_id) - 1.U + } + when(info.wr_bank_valid) { + bankWrBusy(info.wr_bank_id) := false.B + } + } +} diff --git a/arch/src/main/scala/framework/frontend/scoreboard/README.md b/arch/src/main/scala/framework/frontend/scoreboard/README.md new file mode 100644 index 00000000..0f057bf8 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/scoreboard/README.md @@ -0,0 +1,286 @@ +# Buckyball 指令级并行方案：Bank Scoreboard + +## 一、背景与问题 + +### 1.1 现状 + +Buckyball NPU 的 Global ROB 支持乱序发射和乱序完成，但软件中每两条指令之间都插入了 `bb_fence()`。fence 要求 ROB **完全排空**后才接受新指令，等价于 ILP=1——指令级并行**形同虚设**。 + +典型模式： +``` +MVIN(bank0) → fence → RELU(bank0→bank1) → fence → MVOUT(bank1) +``` + +fence 解决的本质问题是 **bank 级 RAW/WAR/WAW 数据依赖**，但它使用了最粗粒度的全局屏障——即使操作不同 bank 的指令之间完全无依赖，fence 也会强制它们串行执行。 + +### 1.2 目标 + +- 在 `framework/frontend/scoreboard/` 中实现一个**指令无感的 Bank Scoreboard** +- Scoreboard 只关心每条指令的**读 bank 集合**和**写 bank 集合**，不关心具体指令类型 +- 保留 fence 指令语义，但 fence 不再要求排空整个 ROB；fence 作为 ROB 中的**屏障点**，ROB 扫描发射时只扫描 fence 之前的指令 +- 统一所有指令的 bank 信息编码到 rs1 的特定位 +- 实现乱序跳跃发射：不同 bank 的指令可以越过有冲突的指令先发射 + +--- + +## 二、统一 rs1 Bank 编码 + +### 2.1 设计原则 + +所有指令的 bank 操作数统一编码到 rs1： + +``` +rs1[7:0] = bank_0 （第一操作数 bank / MVIN 写 bank / MVOUT 读 bank） +rs1[15:8] = bank_1 （第二操作数 bank，仅双操作数指令使用） +rs1[23:16] = bank_2 （写结果 bank） +``` + +### 2.2 各指令新编码 + +#### Mem Domain 指令 + +| 指令 | rs1 | rs2 | 变更说明 | +|------|-----|-----|---------| +| **MVIN** (24) | `[7:0]=wr_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | bank 从 rs2 移到 rs1[7:0]；mem_addr 移到 rs1 高位 | +| **MVOUT** (25) | `[7:0]=rd_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | 同上 | +| **MSET** (23) | `[7:0]=bank_id` | `[4:0]=row, [9:5]=col, [10]=alloc, ...` | bank 从 rs2 移到 rs1[7:0] | + +#### Ball Domain 指令 + +| 指令 | 当前编码 | 新编码变更 | +|------|---------|-----------| +| **MATMUL_WARP16** (32) | op1=rs1[7:0], op2=rs1[15:8], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]**；rs2 重排（iter 从 bit0 开始） | +| **RELU** (38) | op1=rs1[7:0], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]** | +| **TRANSPOSE** (34) | op1=rs1[7:0], wr=**rs1[15:8]** | wr 移到 **rs1[23:16]** | +| **IM2COL** (33) | op1=rs1[7:0], wr=**rs1[15:8]** | wr 移到 **rs1[23:16]** | +| **CONCAT** (39) | op1=rs1[7:0], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]** | +| **TRANSFER** (45) | op1=rs1[7:0], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]** | + +> BBFP_MUL(26), MATMUL_WS(27), ABFT_SYSTOLIC(42), CONV(43), CIM(44) 等双操作数指令同 MATMUL_WARP16 模式处理。 + +### 2.3 统一提取好处 + +GlobalDecoder 只需： +``` +rd_bank_0 = rs1[7:0] +rd_bank_1 = rs1[15:8] +wr_bank = rs1[23:16] （Ball 指令） + 或 rs1[7:0] （MVIN/MSET，写 bank 就是 bank_0） +``` + +加上一个简单的 valid 查找表（按 func7 索引），即可产出完全指令无感的 `BankAccessInfo`。 + +--- + +## 三、Bank Scoreboard 设计 + +### 3.1 位置 + +`framework/frontend/scoreboard/BankScoreboard.scala` + +### 3.2 核心接口 + +```scala +class BankAccessInfo(bankIdLen: Int) extends Bundle { + val rd_bank_0_valid = Bool() + val rd_bank_0_id = UInt(bankIdLen.W) + val rd_bank_1_valid = Bool() + val rd_bank_1_id = UInt(bankIdLen.W) + val wr_bank_valid = Bool() + val wr_bank_id = UInt(bankIdLen.W) +} +``` + +Scoreboard **只接收 `BankAccessInfo`**，不关心具体指令类型、domain、func7。 + +### 3.3 内部数据结构 + +```scala +// 读计数器：多 bit，允许多条指令同时读同一 bank（RR 无冲突） +val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) +// cntWidth = log2Ceil(rob_entries + 1) + +// 写标志：1-bit，WAW 规则保证同一 bank 最多 1 个写者 in-flight +val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) +``` + +**为什么 wrCount 用 1-bit 就够？** +因为冲突检测规则中，写 bank X 要求 `bankWrBusy[X]==false`（WAW 阻塞），所以同一 bank 不可能有两条写指令同时 in-flight。 + +**为什么 rdCount 需要多 bit？** +多条指令同时读同一 bank 是允许的（RR 无冲突），因此需要计数器追踪有多少个并发读者，以便写操作判断 WAR 冲突。 + +### 3.4 冲突检测规则 + +``` +新指令读 bank X → 要求 bankWrBusy[X] == false （否则 RAW 冲突：正在被写） +新指令写 bank X → 要求 bankRdCount[X] == 0 （否则 WAR 冲突：正在被读） + 且 bankWrBusy[X] == false （否则 WAW 冲突：正在被写） +``` + +即： +```scala +def hasHazard(info: BankAccessInfo): Bool = { + val rd0 = info.rd_bank_0_valid && bankWrBusy(info.rd_bank_0_id) + val rd1 = info.rd_bank_1_valid && bankWrBusy(info.rd_bank_1_id) + val wr = info.wr_bank_valid && ( + bankRdCount(info.wr_bank_id) =/= 0.U || + bankWrBusy(info.wr_bank_id) + ) + rd0 || rd1 || wr +} +``` + +### 3.5 计数器/标志更新 + +**发射时**（issue.fire）： +```scala +when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) += 1.U } +when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) += 1.U } +when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := true.B } +``` + +**完成时**（complete.fire）： +```scala +when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) -= 1.U } +when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) -= 1.U } +when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := false.B } +``` + +完成时需要从 ROB entry 中取回 `BankAccessInfo`，因此 **GlobalRobEntry 必须保存 `BankAccessInfo`**。 + +### 3.6 MSET 精确追踪 + +MSET 标记为 `wr_bank_valid=true, wr_bank_id=rs1[7:0]`。它只与同一 bank 的其他指令串行，不阻塞其他 bank。 + +### 3.7 GP Domain (RVV) 指令 + +GP 指令不访问 scratchpad bank，其 `BankAccessInfo` 全部 valid=false，不会被 scoreboard 阻塞，也不阻塞其他指令。 + +--- + +## 四、Fence 指令新语义 + +### 4.1 设计 + +Fence **进入 ROB**（当前实现中 fence 不进 ROB），但不发射到任何 domain。 + +ROB 中 fence 的作用：**发射屏障**。ROB 从 head 扫描待发射指令时，遇到 fence 就停止扫描——fence 之后的指令不会被考虑发射。 + +### 4.2 Fence 生命周期 + +1. Fence 进入 ROB，分配 entry，标记为特殊的 fence 类型 +2. ROB 扫描发射时，以 fence 为边界，只扫描 fence 之前的指令 +3. 当 fence 成为 head 且 fence 之前的所有指令都已完成时，fence 自动标记为 complete 并被 commit +4. Head 前进到 fence 之后，后续指令可以开始发射 + +### 4.3 与 Scoreboard 的关系 + +fence 之前的指令仍然受 scoreboard 管理——不同 bank 的指令可以乱序发射。fence 只是限制了扫描窗口的边界，确保 fence 之后的指令不会越过 fence 提前发射。 + +### 4.4 实际效果 + +- **无 fence 时**：ROB 中所有指令根据 bank 依赖自由发射，最大并行度 +- **有 fence 时**：fence 前后的指令严格有序，fence 内部的指令仍可乱序 +- 软件可以选择性使用 fence 来强制特定的执行顺序（调试、特殊语义等） + +--- + +## 五、ROB 发射逻辑修改 + +### 5.1 当前逻辑 + +```scala +// 从 head 扫描，找第一个 valid && !issued && !complete 的指令 +scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) +``` + +### 5.2 新逻辑 + +```scala +// 增加两个条件：(1) 无 bank 冲突 (2) 不在 fence 之后 +// fenceBarrier(i) = true 表示该位置在某个未完成的 fence 之后 +scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + && !hasHazard(robEntries(ptr).bankAccess) + && !isBehindFence(i) +``` + +**isBehindFence 计算**： +从 head 开始扫描，一旦遇到一个 valid 且未 complete 的 fence entry，其后所有位置的 `isBehindFence` 标记为 true。 + +```scala +val fenceBarrier = Wire(Vec(rob_entries, Bool())) +var seenFence = false.B +for (i <- 0 until rob_entries) { + val ptr = (headPtr + i.U) % rob_entries.U + val isFence = robValid(ptr) && isFenceEntry(ptr) && !robComplete(ptr) + seenFence = seenFence || isFence + fenceBarrier(i) := seenFence // fence 本身和之后的所有项都被屏蔽 +} +``` + +### 5.3 Fence Entry 的自动完成 + +当 fence 成为 head（即 fence 之前的所有指令都已 commit）时，fence 自动标记为 issued + complete： + +```scala +when (robValid(headPtr) && isFenceEntry(headPtr)) { + robIssued(headPtr) := true.B + robComplete(headPtr) := true.B +} +``` + +--- + +## 六、需要修改的文件 + +### 硬件（Scala） + +| 文件 | 改动内容 | +|------|---------| +| **新建** `framework/frontend/scoreboard/BankScoreboard.scala` | BankAccessInfo 定义、BankScoreboard 模块 | +| `framework/frontend/decoder/GobalDecoder.scala` | PostGDCmd 增加 BankAccessInfo 字段；增加 bank 提取逻辑和 valid 查表 | +| `framework/frontend/globalrs/GlobalROB.scala` | GlobalRobEntry 增加 BankAccessInfo 和 isFence 标志；集成 BankScoreboard；修改发射逻辑（hazard + fence barrier）；fence 自动完成逻辑 | +| `framework/frontend/globalrs/GlobalReservationStation.scala` | 删除旧的 fence 处理逻辑（fenceActive 等）；fence 改为进入 ROB 而非阻塞等待排空 | +| `framework/frontend/Frontend.scala` | 可能需要传递 bankNum 参数（已在 GlobalConfig 中） | +| `framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala` | bank_id 从 rs1[bankIdLen-1:0] 提取；mem_addr 从 rs1 高位提取；iter/stride 从 rs2 新位置提取 | +| `examples/toy/balldomain/DomainDecoder.scala` | wr_bank 统一从 rs1[23:16] 提取；更新 decode table | + +### 软件（C 指令宏） + +| 文件 | 改动内容 | +|------|---------| +| `bb-tests/.../isa/24_mvin.c` | bank_id 移到 rs1[7:0]，mem_addr 移到 rs1 高位 | +| `bb-tests/.../isa/25_mvout.c` | 同 MVIN | +| `bb-tests/.../isa/23_mset.c`（或含 mset 的文件） | bank_id 移到 rs1[7:0] | +| `bb-tests/.../isa/32_mul_warp16.c` | wr_bank 从 rs2[7:0] 移到 rs1[23:16] | +| `bb-tests/.../isa/38_relu.c` | wr_bank 从 rs2[7:0] 移到 rs1[23:16] | +| `bb-tests/.../isa/34_transpose.c` | wr_bank 从 rs1[15:8] 移到 rs1[23:16] | +| `bb-tests/.../isa/33_im2col.c` | wr_bank 从 rs1[15:8] 移到 rs1[23:16] | +| `bb-tests/.../isa/45_transfer.c` | wr_bank 从 rs2[7:0] 移到 rs1[23:16] | +| 其他 Ball 指令宏文件 | 类似处理 | +| 所有测试 .c 文件 | **删除 `bb_fence()` 调用** | + +--- + +## 七、实施步骤 + +1. 定义 `BankAccessInfo` Bundle，新建 `BankScoreboard` 模块 +2. 修改软件侧指令宏（MVIN/MVOUT/MSET/Ball 指令），统一 bank 编码到 rs1 +3. 修改 `MemDomainDecoder`，适配新的 rs1/rs2 字段位置 +4. 修改 `BallDomainDecoder`，wr_bank 统一从 rs1[23:16] 提取 +5. 修改 `GlobalDecoder`，增加 `BankAccessInfo` 提取逻辑 +6. 修改 `GlobalROB`，集成 BankScoreboard，实现 hazard 检测 + fence barrier 扫描逻辑 +7. 修改 `GlobalReservationStation`，删除旧 fence 逻辑，fence 改为进入 ROB +8. 删除测试中的 `bb_fence()` 调用 +9. 编译验证 + 运行测试 + +--- + +## 八、验证方案 + +1. Chisel 编译通过，无类型/语法错误 +2. 运行全部 CTest（relu_test, transpose_test, mvin_mvout_test, transfer_test, tiled_matmul 等） +3. 所有测试在无 fence 的情况下结果正确 +4. 可选：波形验证，确认不同 bank 的指令确实并行发射 +5. 可选：加回 fence 的测试，确认 fence barrier 语义正确 diff --git a/arch/src/main/scala/framework/frontend/scoreboard/README_EN.md b/arch/src/main/scala/framework/frontend/scoreboard/README_EN.md new file mode 100644 index 00000000..45e54a58 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/scoreboard/README_EN.md @@ -0,0 +1,283 @@ +# Buckyball ILP Proposal: Bank Scoreboard for Dependency Tracking + +## 1. Background & Problem + +### 1.1 Current State + +Buckyball's Global ROB supports out-of-order issue and out-of-order completion. However, software inserts `bb_fence()` between every pair of instructions. A fence requires the ROB to **drain completely** before accepting the next instruction, effectively reducing ILP to 1 — making the out-of-order machinery **dead code**. + +Typical pattern: +``` +MVIN(bank0) → fence → RELU(bank0→bank1) → fence → MVOUT(bank1) +``` + +The fundamental problem fences solve is **bank-level RAW/WAR/WAW data hazards**. But fences use the coarsest possible granularity — a global barrier. Even instructions operating on completely independent banks are forced to serialize. + +### 1.2 Goals + +- Implement an **instruction-agnostic Bank Scoreboard** in `framework/frontend/scoreboard/` +- The scoreboard only cares about each instruction's **read bank set** and **write bank set**, not the instruction type +- Retain fence instruction semantics, but redefine fence as a **barrier point within the ROB** — the ROB scan for issue candidates stops at the fence boundary +- Unify all instructions' bank information encoding into designated bits of rs1 +- Enable out-of-order skip-issue: instructions on different banks can leapfrog hazard-blocked instructions + +--- + +## 2. Unified rs1 Bank Encoding + +### 2.1 Design Principle + +All instructions encode bank operands in rs1: + +``` +rs1[7:0] = bank_0 (1st operand bank / MVIN write bank / MVOUT read bank) +rs1[15:8] = bank_1 (2nd operand bank, dual-operand instructions only) +rs1[23:16] = bank_2 (write/result bank) +``` + +### 2.2 Per-Instruction New Encoding + +#### Mem Domain Instructions + +| Instruction | rs1 | rs2 | Change Summary | +|-------------|-----|-----|----------------| +| **MVIN** (24) | `[7:0]=wr_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | bank moved from rs2 to rs1[7:0]; mem_addr shifted to upper rs1 | +| **MVOUT** (25) | `[7:0]=rd_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | Same as MVIN | +| **MSET** (23) | `[7:0]=bank_id` | `[4:0]=row, [9:5]=col, [10]=alloc, ...` | bank moved from rs2 to rs1[7:0] | + +#### Ball Domain Instructions + +| Instruction | Current Encoding | New Change | +|-------------|-----------------|------------| +| **MATMUL_WARP16** (32) | op1=rs1[7:0], op2=rs1[15:8], wr=**rs2[7:0]** | wr moves to **rs1[23:16]**; rs2 repacked (iter starts at bit 0) | +| **RELU** (38) | op1=rs1[7:0], wr=**rs2[7:0]** | wr moves to **rs1[23:16]** | +| **TRANSPOSE** (34) | op1=rs1[7:0], wr=**rs1[15:8]** | wr moves to **rs1[23:16]** | +| **IM2COL** (33) | op1=rs1[7:0], wr=**rs1[15:8]** | wr moves to **rs1[23:16]** | +| **CONCAT** (39) | op1=rs1[7:0], wr=**rs2[7:0]** | wr moves to **rs1[23:16]** | +| **TRANSFER** (45) | op1=rs1[7:0], wr=**rs2[7:0]** | wr moves to **rs1[23:16]** | + +> BBFP_MUL(26), MATMUL_WS(27), ABFT_SYSTOLIC(42), CONV(43), CIM(44) and other dual-operand instructions follow the MATMUL_WARP16 pattern. + +### 2.3 Unified Extraction + +After unification, the GlobalDecoder only needs: +``` +rd_bank_0 = rs1[7:0] // always +rd_bank_1 = rs1[15:8] // always (valid flag controls usage) +wr_bank = rs1[23:16] // for Ball instructions + or rs1[7:0] // for MVIN/MSET (write bank == bank_0) +``` + +Plus a simple valid lookup table indexed by func7, producing a fully instruction-agnostic `BankAccessInfo`. + +--- + +## 3. Bank Scoreboard Design + +### 3.1 Location + +`framework/frontend/scoreboard/BankScoreboard.scala` + +### 3.2 Core Interface + +```scala +class BankAccessInfo(bankIdLen: Int) extends Bundle { + val rd_bank_0_valid = Bool() + val rd_bank_0_id = UInt(bankIdLen.W) + val rd_bank_1_valid = Bool() + val rd_bank_1_id = UInt(bankIdLen.W) + val wr_bank_valid = Bool() + val wr_bank_id = UInt(bankIdLen.W) +} +``` + +The scoreboard **only receives `BankAccessInfo`** — it has no knowledge of instruction types, domains, or func7 codes. + +### 3.3 Internal Data Structure + +```scala +// Read counter: multi-bit, allows multiple instructions to read the same bank concurrently (RR is not a conflict) +val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) +// cntWidth = log2Ceil(rob_entries + 1) + +// Write flag: 1-bit, WAW rule guarantees at most 1 writer in-flight per bank +val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) +``` + +**Why is 1-bit sufficient for wrCount?** +The hazard detection rule requires `bankWrBusy[X]==false` before issuing a write to bank X (WAW blocking). Therefore, it is impossible for two write instructions targeting the same bank to be in-flight simultaneously. + +**Why does rdCount need multiple bits?** +Multiple instructions reading the same bank concurrently is allowed (RR is not a conflict). A counter is needed to track how many concurrent readers exist, so write operations can detect WAR hazards. + +### 3.4 Hazard Detection Rules + +``` +New instruction reads bank X → requires bankWrBusy[X] == false (RAW hazard: bank is being written) +New instruction writes bank X → requires bankRdCount[X] == 0 (WAR hazard: bank is being read) + AND bankWrBusy[X] == false (WAW hazard: bank is being written) +``` + +```scala +def hasHazard(info: BankAccessInfo): Bool = { + val rd0 = info.rd_bank_0_valid && bankWrBusy(info.rd_bank_0_id) + val rd1 = info.rd_bank_1_valid && bankWrBusy(info.rd_bank_1_id) + val wr = info.wr_bank_valid && ( + bankRdCount(info.wr_bank_id) =/= 0.U || + bankWrBusy(info.wr_bank_id) + ) + rd0 || rd1 || wr +} +``` + +### 3.5 Counter/Flag Updates + +**On issue** (issue.fire): +```scala +when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) += 1.U } +when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) += 1.U } +when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := true.B } +``` + +**On complete** (complete.fire): +```scala +when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) -= 1.U } +when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) -= 1.U } +when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := false.B } +``` + +Completion requires retrieving `BankAccessInfo` from the ROB entry, so **GlobalRobEntry must store `BankAccessInfo`**. + +### 3.6 MSET Precise Tracking + +MSET is marked as `wr_bank_valid=true, wr_bank_id=rs1[7:0]`. It serializes only with instructions accessing the same bank, without blocking other banks. + +### 3.7 GP Domain (RVV) Instructions + +GP instructions don't access scratchpad banks. Their `BankAccessInfo` has all valid flags set to false — they are never blocked by the scoreboard and don't block others. + +--- + +## 4. Fence Instruction — New Semantics + +### 4.1 Design + +Fence **enters the ROB** (currently it does not). But it is not dispatched to any execution domain. + +Fence acts as an **issue barrier** within the ROB. When the ROB scans from head to find issuable instructions, it **stops scanning at the first unresolved fence** — all instructions after the fence are invisible to the issue logic. + +### 4.2 Fence Lifecycle + +1. Fence enters ROB, receives an entry, marked with a fence flag +2. ROB issue scan uses fence as boundary — only instructions before fence are candidates +3. When fence reaches head (all prior instructions committed), fence auto-completes +4. Head advances past fence, subsequent instructions become visible for issue + +### 4.3 Relationship with Scoreboard + +Instructions before the fence are still managed by the scoreboard — different-bank instructions can issue out of order. The fence only limits the scan window boundary, ensuring post-fence instructions cannot leapfrog the fence. + +### 4.4 Practical Effect + +- **Without fence**: All instructions in ROB are candidates based on bank dependencies — maximum parallelism +- **With fence**: Instructions before and after fence are strictly ordered; instructions within each group can still reorder freely +- Software can selectively use fence for forced ordering (debugging, special semantics, etc.) + +--- + +## 5. ROB Issue Logic Modification + +### 5.1 Current Logic + +```scala +// Scan from head, find first valid && !issued && !complete instruction +scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) +``` + +### 5.2 New Logic + +```scala +// Add two conditions: (1) no bank hazard (2) not behind a fence +scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + && !hasHazard(robEntries(ptr).bankAccess) + && !isBehindFence(i) +``` + +**isBehindFence computation:** +Scan from head; once a valid, uncompleted fence entry is encountered, all subsequent positions are marked `isBehindFence = true`. + +```scala +val fenceBarrier = Wire(Vec(rob_entries, Bool())) +var seenFence = false.B +for (i <- 0 until rob_entries) { + val ptr = (headPtr + i.U) % rob_entries.U + val isFence = robValid(ptr) && isFenceEntry(ptr) && !robComplete(ptr) + seenFence = seenFence || isFence + fenceBarrier(i) := seenFence // fence itself and everything after are masked +} +``` + +### 5.3 Fence Auto-Completion + +When fence becomes head (all prior instructions committed), it auto-marks as issued + complete: + +```scala +when (robValid(headPtr) && isFenceEntry(headPtr)) { + robIssued(headPtr) := true.B + robComplete(headPtr) := true.B +} +``` + +--- + +## 6. Files to Modify + +### Hardware (Scala) + +| File | Change | +|------|--------| +| **NEW** `framework/frontend/scoreboard/BankScoreboard.scala` | BankAccessInfo definition, BankScoreboard module | +| `framework/frontend/decoder/GobalDecoder.scala` | Add BankAccessInfo to PostGDCmd; add bank extraction logic with valid lookup table | +| `framework/frontend/globalrs/GlobalROB.scala` | Add BankAccessInfo + isFence to GlobalRobEntry; integrate BankScoreboard; modify issue logic (hazard + fence barrier); fence auto-completion | +| `framework/frontend/globalrs/GlobalReservationStation.scala` | Remove old fence logic (fenceActive etc.); fence now enters ROB instead of stalling until drain | +| `framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala` | Extract bank_id from rs1[bankIdLen-1:0]; mem_addr from rs1 upper bits; iter/stride from new rs2 positions | +| `examples/toy/balldomain/DomainDecoder.scala` | wr_bank from rs1[23:16]; update decode table | + +### Software (C instruction macros) + +| File | Change | +|------|--------| +| `bb-tests/.../isa/24_mvin.c` | bank_id to rs1[7:0], mem_addr to rs1 upper bits | +| `bb-tests/.../isa/25_mvout.c` | Same as MVIN | +| `bb-tests/.../isa/23_mset.c` (or equivalent) | bank_id to rs1[7:0] | +| `bb-tests/.../isa/32_mul_warp16.c` | wr_bank from rs2[7:0] to rs1[23:16] | +| `bb-tests/.../isa/38_relu.c` | wr_bank from rs2[7:0] to rs1[23:16] | +| `bb-tests/.../isa/34_transpose.c` | wr_bank from rs1[15:8] to rs1[23:16] | +| `bb-tests/.../isa/33_im2col.c` | wr_bank from rs1[15:8] to rs1[23:16] | +| `bb-tests/.../isa/45_transfer.c` | wr_bank from rs2[7:0] to rs1[23:16] | +| Other Ball instruction macro files | Similar treatment | +| All test .c files | **Remove `bb_fence()` calls** | + +--- + +## 7. Implementation Steps + +1. Define `BankAccessInfo` Bundle; create `BankScoreboard` module in `framework/frontend/scoreboard/` +2. Modify software instruction macros (MVIN/MVOUT/MSET/Ball instructions) — unify bank encoding to rs1 +3. Modify `MemDomainDecoder` to adapt to new rs1/rs2 field positions +4. Modify `BallDomainDecoder` — wr_bank from rs1[23:16] +5. Modify `GlobalDecoder` — add `BankAccessInfo` extraction logic +6. Modify `GlobalROB` — integrate BankScoreboard, implement hazard detection + fence barrier scan +7. Modify `GlobalReservationStation` — remove old fence logic, fence enters ROB +8. Remove `bb_fence()` calls from tests +9. Compile + run tests + +--- + +## 8. Verification + +1. Chisel compilation passes with no type/syntax errors +2. Run all CTests (relu_test, transpose_test, mvin_mvout_test, transfer_test, tiled_matmul, etc.) +3. All tests produce correct results without fence +4. Optional: waveform inspection confirming different-bank instructions issue in parallel +5. Optional: test with fence re-inserted, confirming fence barrier semantics work correctly diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index b5cff894..cb8c784e 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -59,6 +59,10 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val midend: Instance[MemMidend] = Instantiate(new MemMidend(b)) val backend: Instance[MemBackend] = Instantiate(new MemBackend(b)) + // Connect query interface from frontend to backend + backend.io.query_vbank_id := frontend.io.query_vbank_id + frontend.io.query_group_count := backend.io.query_group_count + // ------------------------------------------------- // Connection with outside (all in frontend) // ------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index d863cfcf..704ce639 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -8,6 +8,50 @@ import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} import framework.memdomain.backend.accpipe.AccPipe +// DPI-C BlackBox for memory trace +class MTraceDPI extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { + val is_write = Input(UInt(8.W)) + val channel = Input(UInt(32.W)) + val vbank_id = Input(UInt(32.W)) + val group_id = Input(UInt(32.W)) + val addr = Input(UInt(32.W)) + val data_lo = Input(UInt(64.W)) + val data_hi = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline("MTraceDPI.v", + """ + |import "DPI-C" function void dpi_mtrace( + | input byte unsigned is_write, + | input int unsigned channel, + | input int unsigned vbank_id, + | input int unsigned group_id, + | input int unsigned addr, + | input longint unsigned data_lo, + | input longint unsigned data_hi + |); + | + |module MTraceDPI( + | input [7:0] is_write, + | input [31:0] channel, + | input [31:0] vbank_id, + | input [31:0] group_id, + | input [31:0] addr, + | input [63:0] data_lo, + | input [63:0] data_hi, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); + | end + | end + |endmodule + """.stripMargin) +} + class MemRequestIO(b: GlobalConfig) extends Bundle { val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend val read = Flipped(new SramReadIO(b)) // midend sends read req into backend @@ -22,11 +66,26 @@ class MemBackend(val b: GlobalConfig) extends Module { val io = IO(new Bundle { val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) val config = Flipped(Decoupled(new MemConfigerIO(b))) + + // Query interface for frontend to get group count + val query_vbank_id = Input(UInt(8.W)) + val query_group_count = Output(UInt(4.W)) }) val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + // Memory trace DPI-C module + val mtrace = Module(new MTraceDPI) + mtrace.io.is_write := 0.U + mtrace.io.channel := 0.U + mtrace.io.vbank_id := 0.U + mtrace.io.group_id := 0.U + mtrace.io.addr := 0.U + mtrace.io.data_lo := 0.U + mtrace.io.data_hi := 0.U + mtrace.io.enable := false.B + // ----------------------------------------------------------------------------- // Mapping table // ----------------------------------------------------------------------------- @@ -117,11 +176,46 @@ class MemBackend(val b: GlobalConfig) extends Module { } } + // ----------------------------------------------------------------------------- + // Query interface: return group count for a given vbank_id + // ----------------------------------------------------------------------------- + val groupCounts = mappingTable.map { entry => + val matches = entry.valid && (entry.vbank_id === io.query_vbank_id) + val count = Mux(entry.is_multi, entry.group_id + 1.U, 1.U) + Mux(matches, count, 0.U) + } + io.query_group_count := groupCounts.reduce((a, b) => Mux(a > b, a, b)) + // ----------------------------------------------------------------------------- // Connect AccPipe and Banks // ----------------------------------------------------------------------------- for (i <- 0 until b.memDomain.bankChannel) { val hasReq = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + + // Memory trace: read request + when(io.mem_req(i).read.req.fire) { + mtrace.io.is_write := 0.U + mtrace.io.channel := i.U + mtrace.io.vbank_id := io.mem_req(i).bank_id + mtrace.io.group_id := io.mem_req(i).group_id + mtrace.io.addr := io.mem_req(i).read.req.bits.addr + mtrace.io.data_lo := 0.U + mtrace.io.data_hi := 0.U + mtrace.io.enable := true.B + } + + // Memory trace: write request + when(io.mem_req(i).write.req.fire) { + mtrace.io.is_write := 1.U + mtrace.io.channel := i.U + mtrace.io.vbank_id := io.mem_req(i).bank_id + mtrace.io.group_id := io.mem_req(i).group_id + mtrace.io.addr := io.mem_req(i).write.req.bits.addr + mtrace.io.data_lo := io.mem_req(i).write.req.bits.data(63, 0) + mtrace.io.data_hi := io.mem_req(i).write.req.bits.data(127, 64) + mtrace.io.enable := true.B + } + for (j <- 0 until b.memDomain.bankNum) { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid @@ -131,6 +225,13 @@ class MemBackend(val b: GlobalConfig) extends Module { val hold_one = RegNext(hit_bank && req_valid, init = false.B) + // Debug: print when write request comes in + when(io.mem_req(i).write.req.valid && i.U < 4.U) { + printf("[Backend] ch=%d write req: vbank_id=%d group_id=%d\n", i.U, io.mem_req(i).bank_id, io.mem_req(i).group_id) + printf("[Backend] pbank[%d]: valid=%d vbank=%d is_multi=%d group=%d hit=%d\n", + j.U, mappingTable(j).valid, mappingTable(j).vbank_id, mappingTable(j).is_multi, mappingTable(j).group_id, hit_bank) + } + when((hit_bank && req_valid) || hold_one) { banks(j).io.sramRead <> accPipes(i).io.sramRead banks(j).io.sramWrite <> accPipes(i).io.sramWrite diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index b63ba7cc..4d23f043 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -30,12 +30,12 @@ class AccPipe(val b: GlobalConfig) extends Module { val sramRead = Flipped(new SramReadIO(b)) // AccPipe -> bank: req out, resp in val sramWrite = Flipped(new SramWriteIO(b)) // AccPipe -> bank: req out, resp in - val mem_req = Flipped(new MemRequestIO(b)) - val is_multi = Input(Bool()) + val mem_req = Flipped(new MemRequestIO(b)) + val is_multi = Input(Bool()) - val busy = Output(Bool()) + val busy = Output(Bool()) val group_id = Output(UInt(3.W)) - val bank_id = Output(UInt(b.memDomain.bankNum.W)) + val bank_id = Output(UInt(b.memDomain.bankNum.W)) }) val read :: write :: Nil = Enum(2) diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 5f21d833..82c2cd82 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -48,6 +48,10 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val config = Decoupled(new MemConfigerIO(b)) + // Query interface to backend for group count + val query_vbank_id = Output(UInt(8.W)) + val query_group_count = Input(UInt(4.W)) + // Busy signal val busy = Output(Bool()) }) @@ -73,8 +77,16 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { memDecoder.io.cmd_i.valid := io.global_issue_i.valid memDecoder.io.cmd_i.bits := io.global_issue_i.bits.cmd io.global_issue_i.ready := memDecoder.io.cmd_i.ready + + // Config signal goes to backend io.config <> configer.io.config + // Connect query interfaces + // Use memLoader's query by default, memStorer will override when active + io.query_vbank_id := Mux(memStorer.io.cmdReq.valid, memStorer.io.query_vbank_id, memLoader.io.query_vbank_id) + memLoader.io.query_group_count := io.query_group_count + memStorer.io.query_group_count := io.query_group_count + // ----------------------------------------------------------------------------- // MemDecoder -> MemReservationStation // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index b36053f2..338cdc8e 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -51,7 +51,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val bankAddrLen = log2Up(b.memDomain.bankEntries) val memAddrLen = b.memDomain.memAddrLen - val bankIdLen = log2Up(b.memDomain.bankNum) + val bankIdLen = b.frontend.bank_id_len // Only process Mem instructions io.cmd_i.ready := io.mem_decode_cmd_o.ready @@ -61,6 +61,12 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val rs2 = io.cmd_i.bits.cmd.rs2Data // Load/Store instruction decoding + // New unified encoding: + // rs1[7:0] = bank_id + // rs1[26:24] = bank access valid flags (used by scoreboard, ignored here) + // rs1[63:27] = mem_addr (for MVIN/MVOUT) + // rs2[9:0] = iter + // rs2[63:10] = special import LSDecodeFields._ val ls_default_decode = List(N, N, DADDR, DADDR, DITER, DSPECIAL, N) @@ -71,28 +77,28 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { MSET_BITPAT -> List( N, N, - rs1(memAddrLen - 1, 0), - rs2(bankIdLen - 1, 0), - rs2(9 + bankIdLen, bankIdLen), - rs2(39 + bankIdLen, bankIdLen), + 0.U(memAddrLen.W), // mem_addr: not used for MSET + rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] + rs2(9, 0), // iter from rs2[9:0] + rs2(39, 0), // special from rs2[39:0] Y ), // mset MVIN_BITPAT -> List( Y, N, - rs1(memAddrLen - 1, 0), - rs2(bankIdLen - 1, 0), - rs2(9 + bankIdLen, bankIdLen), - rs2(63, 10 + bankIdLen), + rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits + rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] + rs2(9, 0), // iter from rs2[9:0] + rs2(63, 10), // special from rs2[63:10] Y ), // mvin MVOUT_BITPAT -> List( N, Y, - rs1(memAddrLen - 1, 0), - rs2(bankIdLen - 1, 0), - rs2(9 + bankIdLen, bankIdLen), - rs2(63, 10 + bankIdLen), + rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits + rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] + rs2(9, 0), // iter from rs2[9:0] + rs2(63, 10), // special from rs2[63:10] Y ) // mvout ) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 79b53ccb..08e34d92 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -7,9 +7,9 @@ import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} class MemConfigerIO(val b: GlobalConfig) extends Bundle { - val vbank_id = Output(UInt(8.W)) - val is_multi = Output(Bool()) - val alloc = Output(Bool()) + val vbank_id = Output(UInt(8.W)) + val is_multi = Output(Bool()) + val alloc = Output(Bool()) val group_id = Output(UInt(3.W)) } @@ -29,27 +29,25 @@ class MemConfiger(val b: GlobalConfig) extends Module { val idle :: config :: Nil = Enum(2) val state = RegInit(idle) val alloc_reg = RegInit(false.B) - val row_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val counter = RegInit(0.U(4.W)) - io.config.bits.is_multi := false.B - io.config.bits.alloc := false.B - io.config.bits.vbank_id := 0.U(8.W) + io.config.bits.is_multi := false.B + io.config.bits.alloc := false.B + io.config.bits.vbank_id := 0.U(8.W) io.config.bits.group_id := 0.U(3.W) - io.config.valid := false.B - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + io.config.valid := false.B + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) when(state === idle) { when(io.cmdReq.valid) { - when(io.cmdReq.bits.cmd.special(4, 0) > 1.U) { //is multi bank + when(io.cmdReq.bits.cmd.special(9, 5) > 1.U) { //is multi bank (col > 1) state := config - row_reg := io.cmdReq.bits.cmd.special(4, 0) - col_reg := io.cmdReq.bits.cmd.special(9, 5) - alloc_reg := io.cmdReq.bits.cmd.special(10) + col_reg := io.cmdReq.bits.cmd.special(9, 5) + alloc_reg := io.cmdReq.bits.cmd.special(10) vbank_id_reg := io.cmdReq.bits.cmd.bank_id rob_id_reg := io.cmdReq.bits.rob_id @@ -64,14 +62,17 @@ class MemConfiger(val b: GlobalConfig) extends Module { } }.otherwise { - when(counter < row_reg) { - io.config.bits.is_multi := true.B - io.config.bits.alloc := alloc_reg - io.config.bits.vbank_id := vbank_id_reg - io.config.bits.group_id := counter - io.config.valid := true.B - counter := counter + 1.U - }.otherwise { + io.config.bits.is_multi := true.B + io.config.bits.alloc := alloc_reg + io.config.bits.vbank_id := vbank_id_reg + io.config.bits.group_id := counter + io.config.valid := (counter < col_reg) + + when(io.config.fire && counter < col_reg) { + counter := counter + 1.U + } + + when(counter >= col_reg) { state := idle counter := 0.U io.cmdResp.valid := true.B diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 71686b70..ff8c241f 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -23,10 +23,14 @@ class MemLoader(val b: GlobalConfig) extends Module { val dmaResp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) val bankWrite = Flipped(new BankWrite(b)) + + // Query interface to get group count + val query_vbank_id = Output(UInt(8.W)) + val query_group_count = Input(UInt(4.W)) }) - val s_idle :: s_dma_req :: s_dma_wait :: s_done :: Nil = Enum(4) - val state = RegInit(s_idle) + val s_idle :: s_dma_req :: s_dma_wait :: s_wait_last_write :: s_done :: Nil = Enum(5) + val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) @@ -35,6 +39,10 @@ class MemLoader(val b: GlobalConfig) extends Module { val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) val stride_reg = Reg(UInt(11.W)) + // Group counter for multi-bank writes + val group_counter = RegInit(0.U(4.W)) + val group_count_reg = RegInit(0.U(4.W)) + // ----------------------------- // pending latch for 1-beat DMA -> bankWrite // ----------------------------- @@ -59,7 +67,7 @@ class MemLoader(val b: GlobalConfig) extends Module { // bank write request driven from pending io.bankWrite.io.req.valid := pending - io.bankWrite.io.req.bits.addr := latRow + io.bankWrite.io.req.bits.addr := latRow / group_count_reg io.bankWrite.io.req.bits.data := latData io.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) io.bankWrite.io.req.bits.wmode := false.B @@ -67,10 +75,10 @@ class MemLoader(val b: GlobalConfig) extends Module { // IMPORTANT: always ready for write response (avoid deadlock) io.bankWrite.io.resp.ready := true.B - io.bankWrite.rob_id := rob_id_reg - io.bankWrite.bank_id := wr_bank_reg - io.bankWrite.ball_id := 0.U - io.bankWrite.group_id := 0.U + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := wr_bank_reg + io.bankWrite.ball_id := 0.U + io.bankWrite.group_id := group_counter // cmdResp (Decoupled): hold valid until accepted io.cmdResp.valid := (state === s_done) @@ -81,18 +89,27 @@ class MemLoader(val b: GlobalConfig) extends Module { // Receive load instruction // ----------------------------- when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { - state := s_dma_req - rob_id_reg := io.cmdReq.bits.rob_id - mem_addr_reg := io.cmdReq.bits.cmd.mem_addr - iter_reg := io.cmdReq.bits.cmd.iter - wr_bank_reg := io.cmdReq.bits.cmd.bank_id + state := s_dma_req + rob_id_reg := io.cmdReq.bits.rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + wr_bank_reg := io.cmdReq.bits.cmd.bank_id // BBReadRequest.stride is 10 bits wide - stride_reg := io.cmdReq.bits.cmd.special(10, 0) - resp_count := 0.U - pending := false.B - latLast := false.B + stride_reg := io.cmdReq.bits.cmd.special(10, 0) + resp_count := 0.U + pending := false.B + latLast := false.B + group_counter := 0.U + group_count_reg := io.query_group_count + + // Query group count and multiply iter + iter_reg := io.cmdReq.bits.cmd.iter * io.query_group_count } + // Drive query interface + // When idle and cmdReq is valid, query the incoming bank_id + // Otherwise use the registered bank_id + io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, wr_bank_reg) + // DMA req accepted when(io.dmaReq.fire) { state := s_dma_wait @@ -112,12 +129,24 @@ class MemLoader(val b: GlobalConfig) extends Module { pending := false.B resp_count := resp_count + 1.U + // Update group_counter + when(group_counter + 1.U < group_count_reg) { + group_counter := group_counter + 1.U + }.otherwise { + group_counter := 0.U + } + when(latLast) { - // command complete only when last beat has been accepted by bank write - state := s_done + // Last beat request sent, now wait for write response + state := s_wait_last_write } } + // Wait for the last write response before completing + when(state === s_wait_last_write && io.bankWrite.io.resp.fire) { + state := s_done + } + when(state === s_done && io.cmdResp.fire) { state := s_idle } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 25532b17..e0a1d485 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -27,6 +27,10 @@ class MemStorer(val b: GlobalConfig) extends Module { val dmaResp = Flipped(Decoupled(new BBWriteResponse)) val bankRead = Flipped(new BankRead(b)) + + // Query interface to get group count + val query_vbank_id = Output(UInt(8.W)) + val query_group_count = Input(UInt(4.W)) }) // ----------------------------- @@ -35,14 +39,16 @@ class MemStorer(val b: GlobalConfig) extends Module { val s_idle :: s_issue_sram_req :: s_wait_sram_resp :: s_have_sram_beat :: s_push_dma :: s_done :: Nil = Enum(6) val state = RegInit(s_idle) - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val mem_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) - val iter_reg = RegInit(0.U(10.W)) - val stride_reg = RegInit(0.U(10.W)) - val rd_bank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val mem_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) + val iter_reg = RegInit(0.U(10.W)) + val stride_reg = RegInit(0.U(10.W)) + val rd_bank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val group_count_reg = RegInit(1.U(4.W)) // Store group count for current operation - // which SRAM "row" we are reading (0..iter-1) - val sram_row = RegInit(0.U(10.W)) + // Address and group counters + val addr_counter = RegInit(0.U(10.W)) // Row address counter + val group_counter = RegInit(0.U(4.W)) // Group counter within a row // ----------------------------- // Pending buffer for SRAM resp @@ -70,10 +76,16 @@ class MemStorer(val b: GlobalConfig) extends Module { when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { rob_id_reg := io.cmdReq.bits.rob_id mem_addr_reg := io.cmdReq.bits.cmd.mem_addr - iter_reg := io.cmdReq.bits.cmd.iter rd_bank_reg := io.cmdReq.bits.cmd.bank_id stride_reg := io.cmdReq.bits.cmd.special(10, 0) - sram_row := 0.U + + // Query and save group count + group_count_reg := io.query_group_count + iter_reg := io.cmdReq.bits.cmd.iter + + // Initialize counters + addr_counter := 0.U + group_counter := 0.U pending := false.B data_buffer := 0.U @@ -83,16 +95,21 @@ class MemStorer(val b: GlobalConfig) extends Module { state := s_issue_sram_req } + // Drive query interface + // When idle and cmdReq is valid, query the incoming bank_id + // Otherwise use the registered bank_id + io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, rd_bank_reg) + // ----------------------------- // SRAM read request // ----------------------------- - io.bankRead.rob_id := rob_id_reg - io.bankRead.bank_id := target_bank - io.bankRead.ball_id := 0.U - io.bankRead.group_id := sram_row(1, 0) + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U + io.bankRead.group_id := group_counter io.bankRead.io.req.valid := (state === s_issue_sram_req) - io.bankRead.io.req.bits.addr := sram_row + io.bankRead.io.req.bits.addr := addr_counter // SRAMBank read resp is a 1-cycle pulse, so we must ALWAYS be ready to take it, // but only if we don't already hold a pending beat. @@ -101,6 +118,15 @@ class MemStorer(val b: GlobalConfig) extends Module { when(state === s_issue_sram_req) { // Once request handshakes, wait for resp when(io.bankRead.io.req.fire) { + // Debug: print all reads + printf( + "[MemStorer] Issue: addr=%d group_id=%d bank_id=%d iter=%d group_count=%d\n", + addr_counter, + group_counter, + target_bank, + iter_reg, + group_count_reg + ) state := s_wait_sram_resp } } @@ -110,20 +136,24 @@ class MemStorer(val b: GlobalConfig) extends Module { // ----------------------------- val bank_resp_fire = io.bankRead.io.resp.fire when(bank_resp_fire) { - pending := true.B - pendData := io.bankRead.io.resp.bits.data - pendIsLast := (sram_row + 1.U >= iter_reg) && (iter_reg =/= 0.U) // last row beat + pending := true.B + pendData := io.bankRead.io.resp.bits.data + // Last beat: last row and last group + val is_last_row = addr_counter >= iter_reg - 1.U + val is_last_group = group_counter >= group_count_reg - 1.U + pendIsLast := is_last_row && is_last_group && (iter_reg =/= 0.U) state := s_have_sram_beat } // ----------------------------- - // Address calculation (same as your pattern, but use sram_row) - // NOTE: you used a 2D style addressing with stride; keep same formula. + // Address calculation + // For multi-bank: each row has group_count groups, each group is line_bytes + // So: offset = addr * (group_count * line_bytes) + group * line_bytes // ----------------------------- val current_mem_addr = mem_addr_reg + - sram_row(1, 0) * line_bytes.U + - ((sram_row >> 2) << 2) * stride_reg * line_bytes.U + addr_counter * group_count_reg * line_bytes.U + + group_counter * line_bytes.U val addr_offset = current_mem_addr(log2Ceil(align_bytes) - 1, 0) @@ -234,15 +264,41 @@ class MemStorer(val b: GlobalConfig) extends Module { // Mark current beat consumed pending := false.B - // advance row + // Check if this was the last beat before advancing counters + val is_last_row = addr_counter >= iter_reg - 1.U + val is_last_group = group_counter >= group_count_reg - 1.U + val all_done = is_last_row && is_last_group && (iter_reg =/= 0.U) + + // Debug + printf( + "[MemStorer] DMA fire: addr=%d group=%d is_last_row=%d is_last_group=%d all_done=%d\n", + addr_counter, + group_counter, + is_last_row, + is_last_group, + all_done + ) + + // Advance counters when(iter_reg =/= 0.U) { - sram_row := sram_row + 1.U + when(group_counter + 1.U < group_count_reg) { + // Move to next group in same row + group_counter := group_counter + 1.U + printf("[MemStorer] Next group: new_group=%d\n", group_counter + 1.U) + }.otherwise { + // Move to next row, reset group counter + group_counter := 0.U + addr_counter := addr_counter + 1.U + printf("[MemStorer] Next row: new_addr=%d\n", addr_counter + 1.U) + } } - // finish condition - when(pendIsLast || iter_reg === 0.U) { + // Decide next state based on completion check done BEFORE counter update + when(pendIsLast || iter_reg === 0.U || all_done) { + printf("[MemStorer] Going to DONE\n") state := s_done }.otherwise { + printf("[MemStorer] Going to issue next req\n") state := s_issue_sram_req } } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index e551465c..e17aed95 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -54,9 +54,11 @@ class MemMidend(val b: GlobalConfig) extends Module { mappingTable(idx).id := id } - def allocateChannel(): UInt = { + def allocateChannel(): (Bool, UInt) = { val freeChannels = mappingTable.map(entry => !entry.valid) - PriorityEncoder(freeChannels) + val hasFreeChan = freeChannels.reduce(_ || _) + val chanId = PriorityEncoder(freeChannels) + (hasFreeChan, chanId) } def isAllocated(isRead: Bool, id: UInt): Bool = @@ -69,20 +71,49 @@ class MemMidend(val b: GlobalConfig) extends Module { io.balldomain.bankRead(i).io.resp.bits := DontCare when(io.balldomain.bankRead(i).io.req.valid && !isAllocated(true.B, i.U)) { - addEntry(allocateChannel(), true.B, i.U) + val (hasFree, chanId) = allocateChannel() + when(hasFree) { + addEntry(chanId, true.B, i.U) + } } } + // For ball writes, only allocate one request per cycle to avoid conflicts + // Find the first unallocated request and allocate it + val pendingWrites = VecInit((0 until totalBallWrite).map(i => + io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U))) + val hasPendingWrite = pendingWrites.asUInt.orR + val nextWriteToAllocate = PriorityEncoder(pendingWrites) + + // Debug: print allocation decisions + when(hasPendingWrite) { + printf("[MemMidend] hasPending=1 nextToAlloc=%d pending=[", nextWriteToAllocate) + for (i <- 0 until totalBallWrite) { + printf("%d", pendingWrites(i)) + } + printf("] mappingTable=[") + for (i <- 0 until b.top.memBallChannelNum - 1) { + printf("ch%d:v=%d,r=%d,id=%d ", i.U, mappingTable(i).valid, mappingTable(i).isRead, mappingTable(i).id) + } + printf("]\n") + } + for (i <- 0 until totalBallWrite) { //Default values io.balldomain.bankWrite(i).io.req.ready := false.B io.balldomain.bankWrite(i).io.resp.valid := false.B; io.balldomain.bankWrite(i).io.resp.bits := DontCare - //disable for now - when(io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U)) { - addEntry(allocateChannel(), false.B, i.U) + // Only allocate if this is the selected request + when(hasPendingWrite && nextWriteToAllocate === i.U) { + val (hasFree, chanId) = allocateChannel() + when(hasFree) { + addEntry(chanId, false.B, i.U) + printf("[MemMidend] Allocated ballWrite[%d] to ch=%d\n", i.U, chanId) + }.otherwise { + printf("[MemMidend] No free channel for ballWrite[%d]\n", i.U) } + } } //Connect balldomain to backend @@ -95,14 +126,14 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).write.req.bits := DontCare io.mem_req(i).write.resp.ready := false.B io.mem_req(i).bank_id := 0.U - io.mem_req(i).group_id := 0.U + io.mem_req(i).group_id := 0.U val isRead = mappingTable(i).isRead val ballRead = io.balldomain.bankRead(mappingTable(i).id).io val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id - val group_id = io.balldomain.bankWrite(mappingTable(i).id).group_id + val group_id = io.balldomain.bankWrite(mappingTable(i).id).group_id when(mappingTable(i).valid) { when(isRead) { diff --git a/arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala b/arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala deleted file mode 100644 index 6f26e081..00000000 --- a/arch/src/main/scala/framework/memdomain/midend/bmt/bmt.scala +++ /dev/null @@ -1 +0,0 @@ -package framework.memdomain.midend.bmt diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index ecdaaee7..9a0fcdc5 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -5,10 +5,10 @@ #define BB_MSET_FUNC7 23 -#define bb_mset(bank_id, alloc, row, col) \ +#define bb_mset(bank_id, alloc, row, col) \ BUCKYBALL_INSTRUCTION_R_R( \ - 0, \ - (FIELD(bank_id, 0, 4) | FIELD(row, 5, 9) | FIELD(col, 10, 14) | FIELD(alloc, 15, 15)) , \ + (BB_BANK0(bank_id) | BB_WR), \ + (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10)), \ BB_MSET_FUNC7) #define bb_mem_release(bank_id) bb_mset(bank_id, 0, 0, 0); diff --git a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c index 5bcba189..1d1ea825 100644 --- a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c @@ -7,8 +7,7 @@ #define bb_mvin(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(mem_addr, 0, 31), \ - (FIELD(bank_id, 0, 4) | FIELD(depth, 5, 14) | FIELD(stride, 15, 33)), \ - BB_MVIN_FUNC7) + (BB_BANK0(bank_id) | BB_WR | FIELD(mem_addr, 27, 58)), \ + (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_MVIN_FUNC7) #endif // _BB_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c index 5ee847dc..26d50c6c 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c @@ -7,8 +7,7 @@ #define bb_mvout(mem_addr, bank_id, depth, stride) \ BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(mem_addr, 0, 31), \ - (FIELD(bank_id, 0, 4) | FIELD(depth, 5, 14) | FIELD(stride, 15, 33)), \ - BB_MVOUT_FUNC7) + (BB_BANK0(bank_id) | BB_RD0 | FIELD(mem_addr, 27, 58)), \ + (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_MVOUT_FUNC7) #endif // _BB_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c b/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c deleted file mode 100644 index 763e1fa7..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/26_bbfp_mul.c +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BBFP_MUL_H_ -#define _BBFP_MUL_H_ - -#include "isa.h" - -#define BB_BBFP_MUL_FUNC7 26 - -#define bb_bbfp_mul(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_BBFP_MUL_FUNC7) - -#endif // _BBFP_MUL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c b/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c deleted file mode 100644 index f4322a20..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/27_matmul_ws.c +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _MATMUL_WS_H_ -#define _MATMUL_WS_H_ - -#include "isa.h" - -#define BB_MATMUL_WS_FUNC7 27 - -#define bb_matmul_ws(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | FIELD(ws_flag, 24, 24)), \ - BB_MATMUL_WS_FUNC7) - -#endif // _MATMUL_WS_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c index 91feb36a..761fa236 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c @@ -6,8 +6,9 @@ #define BB_MUL_WARP16_FUNC7 32 #define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_MUL_WARP16_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ + (FIELD(iter, 0, 9) | FIELD(mode, 10, 63)), \ + BB_MUL_WARP16_FUNC7) #endif // _BB_MUL_WARP16_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c index d885d5b4..a0eaafcb 100644 --- a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c +++ b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c @@ -7,11 +7,11 @@ #define bb_im2col(op1_bank_id, wr_bank_id, krow, kcol, inrow, incol, startrow, \ startcol) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(kcol, 16, 19) | FIELD(krow, 20, 23) | FIELD(incol, 24, 28) | \ - FIELD(inrow, 29, 38) | FIELD(startcol, 39, 43) | \ - FIELD(startrow, 44, 53)), \ - BB_IM2COL_FUNC7) + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ + (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | FIELD(incol, 8, 12) | \ + FIELD(inrow, 13, 22) | FIELD(startcol, 23, 27) | \ + FIELD(startrow, 28, 37)), \ + BB_IM2COL_FUNC7) #endif // _BB_IM2COL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c index 2eb82912..2b999746 100644 --- a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c +++ b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c @@ -7,7 +7,7 @@ #define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(wr_bank_id, 8, 15)), \ - (FIELD(iter, 8, 15) | FIELD(mode, 16, 16)), BB_TRANSPOSE_FUNC7) + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ + (FIELD(iter, 0, 9) | FIELD(mode, 10, 63)), BB_TRANSPOSE_FUNC7) #endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/38_relu.c b/bb-tests/workloads/lib/bbhw/isa/38_relu.c index c43fe509..edb84a0a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/38_relu.c +++ b/bb-tests/workloads/lib/bbhw/isa/38_relu.c @@ -6,8 +6,8 @@ #define BB_RELU_FUNC7 38 #define bb_relu(bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(bank_id, 0, 7), \ - FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23), \ - BB_RELU_FUNC7) + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ + (FIELD(iter, 0, 9)), BB_RELU_FUNC7) #endif // _BB_RELU_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c b/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c deleted file mode 100644 index c6f8f297..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/39_bbus_config.c +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _BB_BBUS_CONFIG_H_ -#define _BB_BBUS_CONFIG_H_ - -#include "isa.h" - -#define BB_BBUS_CONFIG_FUNC7 39 - -#define bb_bbus_config(src_bid, dst_bid, enable) \ - BUCKYBALL_INSTRUCTION_R_R( \ - 0, \ - (FIELD(src_bid, 0, 5) | FIELD(dst_bid, 6, 11) | FIELD(enable, 12, 12)), \ - BB_BBUS_CONFIG_FUNC7) - -#endif // _BB_BBUS_CONFIG_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c b/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c deleted file mode 100644 index 46f66599..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/40_nnlut.c +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BB_NNLUT_H_ -#define _BB_NNLUT_H_ - -#include "isa.h" - -#define BB_NNLUT_FUNC7 40 - -#define bb_nnlut(op1_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), \ - BB_NNLUT_FUNC7) - -#endif // _BB_NNLUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_snn.c b/bb-tests/workloads/lib/bbhw/isa/41_snn.c deleted file mode 100644 index 5a04e86e..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/41_snn.c +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _BB_SNN_H_ -#define _BB_SNN_H_ - -#include "isa.h" - -#define BB_SNN_FUNC7 41 -#define bb_snn(op1_bank_id, wr_bank_id, iter, threshold, leak_factor) \ - BUCKYBALL_INSTRUCTION_R_R(FIELD(op1_bank_id, 0, 7), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ - FIELD(threshold, 24, 31) | \ - FIELD(leak_factor, 32, 39)), \ - BB_SNN_FUNC7) - -#endif // _BB_SNN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c b/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c deleted file mode 100644 index 4692d0e6..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/42_abft_systolic.c +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BB_ABFT_SYSTOLIC_H_ -#define _BB_ABFT_SYSTOLIC_H_ - -#include "isa.h" - -#define BB_ABFT_SYSTOLIC_FUNC7 42 -#define bb_abft_systolic(op1_bank_id, op2_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(wr_bank_id, 0, 7) | FIELD(iter, 8, 23)), BB_ABFT_SYSTOLIC_FUNC7) - -#endif // _BB_ABFT_SYSTOLIC_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_conv.c b/bb-tests/workloads/lib/bbhw/isa/43_conv.c deleted file mode 100644 index 444f0b18..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/43_conv.c +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _BB_CONV_H_ -#define _BB_CONV_H_ - -#include "isa.h" - -#define BB_CONV_FUNC7 43 - -#define bb_conv(ifmap_bank_id, weight_bank_id, ofmap_bank_id, iter, in_height, \ - in_width, kernel_h, kernel_w) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(ifmap_bank_id, 0, 7) | FIELD(weight_bank_id, 8, 15)), \ - (FIELD(ofmap_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ - FIELD(in_height, 24, 39) | FIELD(in_width, 40, 55) | \ - FIELD(kernel_h, 56, 63)), \ - BB_CONV_FUNC7) - -#endif // _BB_CONV_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/44_cim.c b/bb-tests/workloads/lib/bbhw/isa/44_cim.c deleted file mode 100644 index e5ced73a..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/44_cim.c +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _BB_CIM_H_ -#define _BB_CIM_H_ - -#include "isa.h" - -#define BB_CIM_FUNC7 44 -#define bb_cim(op1_bank_id, op2_bank_id, result_bank_id, iter, rows, cols, \ - op_type) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (FIELD(op1_bank_id, 0, 7) | FIELD(op2_bank_id, 8, 15)), \ - (FIELD(result_bank_id, 0, 7) | FIELD(iter, 8, 23) | \ - FIELD(rows, 24, 39) | FIELD(cols, 40, 55) | FIELD(op_type, 56, 59)), \ - BB_CIM_FUNC7) - -#endif // _BB_CIM_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c b/bb-tests/workloads/lib/bbhw/isa/45_transfer.c deleted file mode 100644 index ddaf7482..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/45_transfer.c +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _BB_TRANSFER_H_ -#define _BB_TRANSFER_H_ - -#include "isa.h" - -#define BB_TRANSFER_FUNC7 45 - -#define bb_transfer(op1_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - FIELD(op1_bank_id, 0, 7), \ - (FIELD(wr_bank_id, 0, 7) | FIELD((iter > 1023 ? 1023 : iter), 8, 23)), \ - BB_TRANSFER_FUNC7) - -#endif // _BB_TRANSFER_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/7_flush.c b/bb-tests/workloads/lib/bbhw/isa/7_flush.c deleted file mode 100644 index 3be03848..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/7_flush.c +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _BB_FLUSH_H_ -#define _BB_FLUSH_H_ - -#include "isa.h" - -#define BB_FLUSH_FUNC7 7 - -#define bb_flush() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FLUSH_FUNC7) - -#endif // _BB_FLUSH_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index ae7eddfa..14902e55 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -21,6 +21,17 @@ typedef int32_t result_t; #define FIELD(val, start_bit, end_bit) \ (((val) & ((1UL << ((end_bit) - (start_bit) + 1)) - 1)) << (start_bit)) +// Unified rs1 bank encoding flags (bits 24-26) +// bit 24 = rd_bank_0_valid, bit 25 = rd_bank_1_valid, bit 26 = wr_bank_valid +#define BB_RD0 (1UL << 24) +#define BB_RD1 (1UL << 25) +#define BB_WR (1UL << 26) + +// rs1 bank field helpers +#define BB_BANK0(id) FIELD(id, 0, 7) +#define BB_BANK1(id) FIELD(id, 8, 15) +#define BB_BANK2(id) FIELD(id, 16, 23) + // Generic RISC-V custom instruction macro #define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c2, x0, %0, %1" \ @@ -32,20 +43,10 @@ typedef int32_t result_t; #include "23_mset.c" #include "24_mvin.c" #include "25_mvout.c" -#include "26_bbfp_mul.c" -#include "27_matmul_ws.c" #include "31_fence.c" #include "32_mul_warp16.c" #include "33_im2col.c" #include "34_transpose.c" #include "38_relu.c" -#include "39_bbus_config.c" -#include "40_nnlut.c" -#include "41_snn.c" -#include "42_abft_systolic.c" -#include "43_conv.c" -#include "44_cim.c" -#include "45_transfer.c" -#include "7_flush.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 91e898c2..662c5362 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -111,17 +111,9 @@ add_cross_platform_test_target(ctest_vecunit_matmul_16xn_random3 vecunit_matmul_ add_cross_platform_test_target(ctest_vecunit_matmul_16xn_zero_random vecunit_matmul_16xn_zero_random.c) add_cross_platform_test_target(ctest_vecunit_simple_nn_forward_pass_test vecunit_simple_nn_forward_pass_test.c) add_cross_platform_test_target(ctest_im2col_test im2col_test.c) -add_cross_platform_test_target(ctest_bbfp_matmul_test bbfpmatmul.c) -add_cross_platform_test_target(ctest_bbfp_matmul_random1 bbfp_matmul_random1.c) -add_cross_platform_test_target(ctest_bbfp_matmul_random2 bbfp_matmul_random2.c) -add_cross_platform_test_target(ctest_bbfp_matmul_random3 bbfp_matmul_random3.c) add_cross_platform_test_target(ctest_transpose_test transpose_test.c) add_cross_platform_test_target(ctest_transpose_matmul transpose_matmul.c) -add_cross_platform_test_target(ctest_tiled_matmul tiled_matmul.c) add_cross_platform_test_target(ctest_relu_test relu_test.c) -add_cross_platform_test_target(ctest_abft_systolic_test abft_systolic_test.c) -add_cross_platform_test_target(ctest_conv_test conv_test.c) -add_cross_platform_test_target(ctest_transfer_test transfer_test.c) add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) # Create master build target @@ -143,17 +135,9 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_vecunit_matmul_16xn_zero_random ctest_vecunit_simple_nn_forward_pass_test ctest_im2col_test - ctest_bbfp_matmul_test - ctest_bbfp_matmul_random1 - ctest_bbfp_matmul_random2 - ctest_bbfp_matmul_random3 ctest_transpose_test ctest_transpose_matmul - ctest_tiled_matmul ctest_relu_test - ctest_abft_systolic_test - ctest_conv_test - ctest_transfer_test ctest_vsetvli COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c b/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c deleted file mode 100644 index 1815c449..00000000 --- a/bb-tests/workloads/src/CTest/toy/abft_systolic_test.c +++ /dev/null @@ -1,110 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static elem_t output_matrix_c[DIM * DIM] __attribute__((aligned(64))); - -// CPU reference computation for matrix multiplication with ABFT -int abft_systolic_cpu_reference(elem_t *a, elem_t *b, elem_t *c, int size) { - // Compute C = A * B - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - int32_t sum = 0; - for (int k = 0; k < size; k++) { - sum += (int32_t)a[i * size + k] * (int32_t)b[k * size + j]; - } - // Clamp to int8_t range - if (sum > 127) { - c[i * size + j] = 127; - } else if (sum < -128) { - c[i * size + j] = -128; - } else { - c[i * size + j] = (elem_t)sum; - } - } - } - return 1; -} - -void hw_abft_systolic(const char *test_name, elem_t *a, elem_t *b, elem_t *c, - int size) { - // Matrix A in spad bank 0, Matrix B in spad bank 1, result in spad bank 2 - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - uint32_t wr_bank_id = 2; - - // Move input matrices into scratchpad - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_fence(); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - - // Call ABFT systolic array instruction - bb_abft_systolic(op1_bank_id, op2_bank_id, wr_bank_id, size); - bb_fence(); - - // Result will be moved back in run_test for verification -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, elem_t *c, int size) { - // CPU reference computation - abft_systolic_cpu_reference(a, b, c, size); - - // Hardware computation - hw_abft_systolic(test_name, a, b, c, size); - - // Move result back from scratchpad for verification - uint32_t wr_bank_id = 2; - bb_mvout((uintptr_t)output_matrix_c, wr_bank_id, size, 1); - bb_fence(); - - // Verify results - int passed = 1; - for (int i = 0; i < size; i++) { - for (int j = 0; j < size; j++) { - int idx = i * size + j; - if (output_matrix_c[idx] != c[idx]) { - printf("Mismatch at [%d][%d]: expected %d, got %d\n", i, j, c[idx], - output_matrix_c[idx]); - passed = 0; - } - } - } - - return passed; -} - -int test_abft_systolic(int seed) { - // Initialize input matrices with random values - init_i8_random_matrix(input_matrix_a, DIM, DIM, seed); - init_i8_random_matrix(input_matrix_b, DIM, DIM, seed + 1); - - // Run hardware test with verification - return run_test("ABFT-Systolic", input_matrix_a, input_matrix_b, - output_matrix_c, DIM); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - - int passed = test_abft_systolic(5); - if (passed) { - printf("ABFT-Systolic test PASSED!!!!\n"); - } else { - printf("ABFT-Systolic test FAILED\n"); - } - return (!passed); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index 2cfa465d..e37b702f 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -31,13 +31,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_mvin((uintptr_t)c, op2_bank_id, DIM << 2, 1); - bb_fence(); + bb_mvin((uintptr_t)c, op2_bank_id, DIM, 1); bb_transpose(op2_bank_id, op1_bank_id, size, 0); - bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, op2_bank_id, DIM << 2, 1); + bb_mvout((uintptr_t)c, op2_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c deleted file mode 100644 index ae3f4fb2..00000000 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random1.c +++ /dev/null @@ -1,61 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); - -void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, size); - bb_fence(); - bb_mvout((uintptr_t)c, op2_bank_id, size << 2, 1); - bb_fence(); -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); - cpu_matmul(b, a, expected_matrix, size, size, size); - hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { - printf("Test %s PASSED\n", test_name); - return 1; - } else { - printf("Test %s FAILED\n", test_name); - return 0; - } -} - -int test_random1() { - init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 456); - init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 789); - return run_test("Random matrices 1", input_matrix_a, input_matrix_b, DIM); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = test_random1(); - if (passed) { - printf("bbfp_matmul_random1 test PASSED\n"); - } else { - printf("bbfp_matmul_random1 test FAILED\n"); - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c deleted file mode 100644 index 2eb65070..00000000 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random2.c +++ /dev/null @@ -1,61 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); - -void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, size); - bb_fence(); - bb_mvout((uintptr_t)c, op2_bank_id, size << 2, 1); - bb_fence(); -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); - cpu_matmul(b, a, expected_matrix, size, size, size); - hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { - printf("Test %s PASSED\n", test_name); - return 1; - } else { - printf("Test %s FAILED\n", test_name); - return 0; - } -} - -int test_random1() { - init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 111); - init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 222); - return run_test("Random matrices 2", input_matrix_a, input_matrix_b, DIM); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = test_random1(); - if (passed) { - printf("bbfp_matmul_random2 test PASSED\n"); - } else { - printf("bbfp_matmul_random2 test FAILED\n"); - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c deleted file mode 100644 index ec1430ef..00000000 --- a/bb-tests/workloads/src/CTest/toy/bbfp_matmul_random3.c +++ /dev/null @@ -1,61 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); - -void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, size); - bb_fence(); - bb_mvout((uintptr_t)c, op2_bank_id, size << 2, 1); - bb_fence(); -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_u32_matrix(output_matrix, DIM, DIM); - cpu_matmul(b, a, expected_matrix, size, size, size); - hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { - printf("Test %s PASSED\n", test_name); - return 1; - } else { - printf("Test %s FAILED\n", test_name); - return 0; - } -} - -int test_random1() { - init_bbfp_random_matrix(input_matrix_a, DIM, DIM, 333); - init_bbfp_random_matrix(input_matrix_b, DIM, DIM, 444); - return run_test("Random matrices 3", input_matrix_a, input_matrix_b, DIM); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = test_random1(); - if (passed) { - printf("bbfp_matmul_random3 test PASSED\n"); - } else { - printf("bbfp_matmul_random3 test FAILED\n"); - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c b/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c deleted file mode 100644 index 7837e8c3..00000000 --- a/bb-tests/workloads/src/CTest/toy/bbfpmatmul.c +++ /dev/null @@ -1,73 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -void init_matrix(elem_t *matrix, int rows, int cols, int seed) { - srand(seed); - for (int i = 0; i < rows * cols; i++) { - matrix[i] = - rand() % 4; // Initialize with random values in the range [0, 127] - } -} -void flip_matrix(elem_t *matrix, int rows, int cols) { - for (int i = 0; i < rows / 2; i++) { - for (int j = 0; j < cols; j++) { - elem_t temp = matrix[i * cols + j]; - matrix[i * cols + j] = matrix[(rows - 1 - i) * cols + j]; - matrix[(rows - 1 - i) * cols + j] = temp; - } - } -} -// Test matrices -static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))); -static elem_t transposed_matrix[DIM * DIM] __attribute__((aligned(64))); -static elem_t weight_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_output_matrix[DIM * DIM] __attribute__((aligned(64))); - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); // Only allow specified hart to continue -#endif - - // Initialize weight matrix - init_matrix(weight_matrix, DIM, DIM, 42); - init_matrix(input_matrix, DIM, DIM, 51); - - // Clear output matrix - memset(output_matrix, 0, sizeof(output_matrix)); - cpu_matmul(input_matrix, weight_matrix, expected_output_matrix, DIM, DIM, - DIM); - // print_matrix("Input", input_matrix, DIM, DIM); - - // Move input to scratchpad - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - - bb_mvin((uintptr_t)weight_matrix, op1_bank_id, DIM, 1); - bb_mvin((uintptr_t)input_matrix, op2_bank_id, DIM, 1); - bb_fence(); - bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, DIM); - bb_fence(); - // Move back from scratchpad to output - bb_mvout((uintptr_t)output_matrix, op2_bank_id, DIM << 2, 1); - bb_fence(); - if (compare_u32_matrices(output_matrix, expected_output_matrix, DIM, DIM)) { - printf("Test passed!\n"); - } else { - printf("Test failed!\n"); - } - // print_matrix("Output", output_matrix, DIM, DIM); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/bbfptest.c b/bb-tests/workloads/src/CTest/toy/bbfptest.c deleted file mode 100644 index a3ac1731..00000000 --- a/bb-tests/workloads/src/CTest/toy/bbfptest.c +++ /dev/null @@ -1,80 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -// Test matrices -static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))); -static elem_t weight_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); - -// Utility function -void print_result_matrix(const char *name, result_t *matrix, int rows, - int cols) { - printf("Matrix %s:\n", name); - for (int i = 0; i < rows; i++) { - for (int j = 0; j < cols; j++) { - printf("%4d ", (int32_t)matrix[i * cols + j]); - } - printf("\n"); - } - printf("\n"); -} - -void init_matrixv2(elem_t *matrix, int rows, int cols, int seed, int value) { - for (int i = 0; i < rows * cols; i++) { - matrix[i] = value; - } -} - -int compare_matrices(result_t *a, result_t *b, int rows, int cols) { - for (int i = 0; i < rows * cols; i++) { - if (a[i] != b[i]) { - return 0; // Matrices are different - } - } - return 1; // Matrices are the same -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); // Only allow specified hart to continue -#endif - - // Initialize input matrix - init_matrixv2(input_matrix, 16, 16, 42, 3); - init_matrixv2(weight_matrix, 16, 16, 42, 2); - // Clear output matrix - memset(output_matrix, 0, sizeof(output_matrix)); - - // print_matrix("Input", input_matrix, DIM, DIM); - - // Move input to scratchpad - uint32_t op1_bank_id = 0; - uint32_t op2_bank_id = 1; - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - - bb_mvin((uintptr_t)input_matrix, op1_bank_id, DIM, 1); - bb_mvin((uintptr_t)weight_matrix, op2_bank_id, DIM, 1); - printf("Perform Matmul\n"); - bb_bbfp_mul(op1_bank_id, op2_bank_id, acc_bank_id, DIM); - - printf("change"); - bb_matmul_ws(acc_bank_id, op2_bank_id, acc_bank_id, 16); - init_matrixv2(input_matrix, 16, 16, 42, 4); - bb_matmul_ws(acc_bank_id, op2_bank_id, acc_bank_id, 16); - printf("Matmul Done\n"); - bb_mvout(((uintptr_t)output_matrix), op2_bank_id, DIM << 2, 1); - - print_result_matrix("Output", output_matrix, DIM, DIM); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/conv_test.c b/bb-tests/workloads/src/CTest/toy/conv_test.c deleted file mode 100644 index 49beed30..00000000 --- a/bb-tests/workloads/src/CTest/toy/conv_test.c +++ /dev/null @@ -1,145 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -#define IFMAP_SIZE 64 -#define WEIGHT_SIZE 16 -#define OFMAP_SIZE 16 - -static elem_t input_feature_map[IFMAP_SIZE] __attribute__((aligned(64))); -static elem_t weights[WEIGHT_SIZE] __attribute__((aligned(64))); -static elem_t output_feature_map[OFMAP_SIZE] __attribute__((aligned(64))); - -// CPU reference computation for simple convolution -int conv_cpu_reference(elem_t *ifmap, elem_t *weight, elem_t *ofmap, int in_h, - int in_w, int kernel_h, int kernel_w) { - // Simplified 2D convolution: assume stride=1, pad=0 - int out_h = in_h - kernel_h + 1; - int out_w = in_w - kernel_w + 1; - - for (int oh = 0; oh < out_h; oh++) { - for (int ow = 0; ow < out_w; ow++) { - int32_t sum = 0; - for (int kh = 0; kh < kernel_h; kh++) { - for (int kw = 0; kw < kernel_w; kw++) { - int ih = oh + kh; - int iw = ow + kw; - int ifmap_idx = ih * in_w + iw; - int weight_idx = kh * kernel_w + kw; - sum += (int32_t)ifmap[ifmap_idx] * (int32_t)weight[weight_idx]; - } - } - // Clamp to int8_t range - if (sum > 127) { - ofmap[oh * out_w + ow] = 127; - } else if (sum < -128) { - ofmap[oh * out_w + ow] = -128; - } else { - ofmap[oh * out_w + ow] = (elem_t)sum; - } - } - } - return 1; -} - -void hw_conv(const char *test_name, elem_t *ifmap, elem_t *weight, - elem_t *ofmap, int in_h, int in_w, int kernel_h, int kernel_w, - uint32_t ofmap_bank_id) { - // Input feature map in spad bank 0, weights in spad bank 1, output in spad - // bank 2 - uint32_t ifmap_bank_id = 0; - uint32_t weight_bank_id = 1; - // Move input feature map into scratchpad - bb_mvin((uintptr_t)ifmap, ifmap_bank_id, IFMAP_SIZE, 1); - bb_fence(); - - // Move weights into scratchpad - bb_mvin((uintptr_t)weight, weight_bank_id, WEIGHT_SIZE, 1); - bb_fence(); - - // Call CONV instruction - // iter is the number of iterations (simplified: use 1 for now) - uint32_t iter = 1; - bb_conv(ifmap_bank_id, weight_bank_id, ofmap_bank_id, iter, in_h, in_w, - kernel_h, kernel_w); - bb_fence(); - - // Result will be moved back in run_test for verification -} - -int run_test(const char *test_name, elem_t *ifmap, elem_t *weight, - elem_t *ofmap, int in_h, int in_w, int kernel_h, int kernel_w) { - // CPU reference computation - conv_cpu_reference(ifmap, weight, ofmap, in_h, in_w, kernel_h, kernel_w); - - // Output feature map in spad bank 2 - uint32_t ofmap_bank_id = 2; - - // Hardware computation - hw_conv(test_name, ifmap, weight, ofmap, in_h, in_w, kernel_h, kernel_w, - ofmap_bank_id); - - // Move result back from scratchpad for verification - bb_mvout((uintptr_t)output_feature_map, ofmap_bank_id, OFMAP_SIZE, 1); - bb_fence(); - - // Verify results - int out_h = in_h - kernel_h + 1; - int out_w = in_w - kernel_w + 1; - int passed = 1; - for (int i = 0; i < out_h; i++) { - for (int j = 0; j < out_w; j++) { - int idx = i * out_w + j; - if (output_feature_map[idx] != ofmap[idx]) { - printf("Mismatch at [%d][%d]: expected %d, got %d\n", i, j, ofmap[idx], - output_feature_map[idx]); - passed = 0; - } - } - } - - return passed; -} - -int test_conv(int seed) { - // Initialize input feature map with random values (8x8 image) - int in_h = 8; - int in_w = 8; - for (int i = 0; i < IFMAP_SIZE; i++) { - input_feature_map[i] = (elem_t)(rand() % 256 - 128); - } - - // Initialize weights with random values (3x3 kernel) - int kernel_h = 3; - int kernel_w = 3; - for (int i = 0; i < WEIGHT_SIZE; i++) { - weights[i] = (elem_t)(rand() % 256 - 128); - } - - // Run hardware test with verification - return run_test("CONV", input_feature_map, weights, output_feature_map, in_h, - in_w, kernel_h, kernel_w); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - - int passed = test_conv(5); - if (passed) { - printf("CONV test PASSED!!!!\n"); - } else { - printf("CONV test FAILED\n"); - } - return (!passed); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 98388918..848608bf 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -17,24 +17,20 @@ #define LANES_PER_BEAT 16 static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t output_matrix_b[EXPECTED_ROWS * EXPECTED_COLS] __attribute__((aligned(64))); -static elem_t expected_matrix[EXPECTED_ROWS * EXPECTED_COLS] __attribute__((aligned(64))); +static elem_t output_matrix_b[EXPECTED_ROWS * EXPECTED_COLS] + __attribute__((aligned(64))); +static elem_t expected_matrix[EXPECTED_ROWS * EXPECTED_COLS] + __attribute__((aligned(64))); -static int conv_num(void) -{ +static int conv_num(void) { return (INROW - KROW + 1 - STARTROW) * (INCOL - KCOL + 1 - STARTCOL); } -static int kernel_elems(void) -{ - return KROW * KCOL; -} +static int kernel_elems(void) { return KROW * KCOL; } static void build_expected_im2col_matrix(elem_t *input, elem_t *expected, - int inrow, int incol, - int krow, int kcol, - int startrow, int startcol) -{ + int inrow, int incol, int krow, + int kcol, int startrow, int startcol) { clear_i8_matrix(expected, EXPECTED_ROWS, EXPECTED_COLS); int row_end = inrow - krow; @@ -42,15 +38,11 @@ static void build_expected_im2col_matrix(elem_t *input, elem_t *expected, int kernel = krow * kcol; int window_idx = 0; - for (int r = startrow; r <= row_end; r++) - { - for (int c = startcol; c <= col_end; c++) - { + for (int r = startrow; r <= row_end; r++) { + for (int c = startcol; c <= col_end; c++) { int elem_idx = 0; - for (int kr = 0; kr < krow; kr++) - { - for (int kc = 0; kc < kcol; kc++) - { + for (int kr = 0; kr < krow; kr++) { + for (int kc = 0; kc < kcol; kc++) { expected[window_idx * kernel + elem_idx] = input[(r + kr) * incol + (c + kc)]; elem_idx++; @@ -61,8 +53,7 @@ static void build_expected_im2col_matrix(elem_t *input, elem_t *expected, } } -void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) -{ +void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { (void)test_name; (void)size; @@ -74,7 +65,6 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, 32, 1); - bb_fence(); uint64_t krow = KROW; uint64_t kcol = KCOL; uint64_t inrow = INROW; @@ -85,13 +75,11 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) // startcol); bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, startcol); - bb_fence(); bb_mvout((uintptr_t)b, op2_bank_id, conv_num() / kernel_elems(), 1); bb_fence(); } -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) -{ +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { int conv = conv_num(); int elems = kernel_elems(); @@ -101,37 +89,28 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) hw_im2col(test_name, a, b, size); - - if (compare_i8_matrices(b, expected_matrix, conv, elems)) - { + if (compare_i8_matrices(b, expected_matrix, conv, elems)) { printf("%s compare test PASSED\n", test_name); return 1; - } - else - { + } else { printf("%s compare test FAILED\n", test_name); return 0; } } -int test_im2col() -{ +int test_im2col() { init_sequence_matrix(input_matrix_a, DIM, DIM); return run_test("Im2col", input_matrix_a, output_matrix_b, DIM); } -int main() -{ +int main() { #ifdef MULTICORE multicore(MULTICORE); #endif int passed = test_im2col(); - if (passed) - { + if (passed) { printf("Im2col test PASSED\n"); - } - else - { + } else { printf("Im2col test FAILED\n"); } #ifdef MULTICORE diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index c981757f..38196e37 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -20,14 +20,13 @@ int acc_mvin_mvout_pressure_test() { uint32_t acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); - bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM << 2, 1); + bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); acc_bank_id = 2; // virtual bank id bb_mem_alloc(acc_bank_id, 1, 4); - bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM << 2, 1); - bb_fence(); + bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test ACC mvin/mvout pressure %d FAILED\n", i); return 0; diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index 62d55d4a..b6325d7c 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -19,9 +19,7 @@ int mvin_mvout_simple_test() { init_u8_random_matrix(input_matrix, DIM, DIM, 111); bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); clear_u8_matrix(output_matrix, DIM, DIM); - bb_fence(); bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); - bb_fence(); if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { printf("Test mvin/mvout simple %d FAILED\n", i); return 0; diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index 2331a10b..88490015 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -76,12 +76,11 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { bb_mem_alloc(wr_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_fence(); bb_relu(op1_bank_id, wr_bank_id, size); - bb_fence(); bb_mvout((uintptr_t)b, wr_bank_id, size, 1); + bb_fence(); } // ======================= diff --git a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/tiled_matmul.c deleted file mode 100644 index 6f323859..00000000 --- a/bb-tests/workloads/src/CTest/toy/tiled_matmul.c +++ /dev/null @@ -1,185 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -#define DIM_I 32 -#define DIM_J 32 -#define DIM_K 32 - -static elem_t input_a[DIM_I * DIM_J] __attribute__((aligned(16))); -static elem_t input_b[DIM_J * DIM_K] __attribute__((aligned(16))); -static result_t output_c[DIM_I * DIM_K] __attribute__((aligned(64))); -static result_t expected_c[DIM_I * DIM_K] __attribute__((aligned(64))); -static result_t c_zero[DIM * DIM] __attribute__((aligned(64))); - -void tiled_matmul_connect_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c) { - // spad0: operand A, offset 0 - uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 - uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - uint32_t i_stride = dim_i / DIM; - uint32_t j_stride = dim_j / DIM; - uint32_t k_stride = dim_k / DIM; - uint64_t en = 1; - - unsigned long long start_compute, end_compute; - start_compute = read_cycle(); - bb_bbus_config(3, 0, en); - // mvin matrix a - for (int i = 0; i < i_stride; i++) { - for (int j = 0; j < j_stride; j++) { - bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, - op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, - j_stride); - } - } - // mvin matrix b - for (int k = 0; k < k_stride; k++) { - bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); - } - bb_fence(); - // perform matmul - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { - bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, - acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 1); - bb_transpose((uintptr_t)op1_bank_id + dim_j * k_stride + dim_j * i, - op1_bank_id + dim_j * i, dim_j, 1); - } - } - bb_fence(); - // mvout matrix c - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { - bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, - acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); - bb_fence(); - } - } - bb_bbus_config(3, 0, 0); - end_compute = read_cycle(); - printf("Cycles for matmul: %d\n", end_compute - start_compute); -} - -void tiled_matmul_normal_mode(uint32_t dim_i, uint32_t dim_j, uint32_t dim_k, - elem_t *a, elem_t *b, result_t *c) { - // spad0: operand A, offset 0 - uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 - uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - uint32_t i_stride = dim_i / DIM; - uint32_t j_stride = dim_j / DIM; - uint32_t k_stride = dim_k / DIM; - - unsigned long long start_compute, end_compute; - start_compute = read_cycle(); - - // mvin matrix a - for (int i = 0; i < i_stride; i++) { - for (int j = 0; j < j_stride; j++) { - bb_mvin((uintptr_t)a + i * dim_j * DIM + j * DIM, - op1_bank_id + dim_j * k_stride + dim_j * i + j * DIM, DIM, - j_stride); - } - } - // mvin matrix b - for (int k = 0; k < k_stride; k++) { - bb_mvin((uintptr_t)b + k * DIM, op2_bank_id + dim_j * k, dim_j, k_stride); - } - bb_fence(); - - // transpose matrix a - for (int i = 0; i < i_stride; i++) { - bb_transpose((uintptr_t)op2_bank_id + dim_j * k_stride + dim_j * i, - op1_bank_id + dim_j * i, dim_j, 0); - } - bb_fence(); - - // perform matmul - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { - bb_mul_warp16(op1_bank_id + dim_j * i, op2_bank_id + dim_j * k, - acc_bank_id + i * dim_k / 2 + k * DIM / 2, dim_j, 0); - bb_fence(); - } - } - bb_fence(); - // mvout matrix c - for (int i = 0; i < i_stride; i++) { - for (int k = 0; k < k_stride; k++) { - bb_mvout((uintptr_t)c + i * dim_k * DIM * 4 + k * DIM * 4, - acc_bank_id + i * dim_k / 2 + k * DIM / 2, DIM << 2, k_stride); - bb_fence(); - } - } - - end_compute = read_cycle(); - printf("Cycles for matmul: %d\n", end_compute - start_compute); -} - -int run_test(const char *test_name) { - - tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); - cpu_matmul(input_a, input_b, expected_c, DIM_I, DIM_K, DIM_J); - if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { - printf("Test Connect Mode %s PASSED\n", test_name); - } else { - printf("Test Connect Mode %s FAILED\n", test_name); - return 0; - } - - clear_u32_matrix(output_c, DIM_I, DIM_K); - // acc0: write to accumulator, offset 0 - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); - // TODO: ACC overwrite write can skip this step - bb_mvin((uintptr_t)output_c, acc_bank_id, DIM_I * DIM_K * 4 / DIM, 1); - tiled_matmul_normal_mode(DIM_I, DIM_J, DIM_K, input_a, input_b, output_c); - if (compare_u32_matrices(output_c, expected_c, DIM_I, DIM_K)) { - printf("Test Normal Mode %s PASSED\n", test_name); - return 1; - } else { - printf("Test Normal Mode %s FAILED\n", test_name); - return 0; - } -} - -int test_tiled_matmul() { - /** - init_u8_random_matrix(input_a, DIM_I, DIM_J, 111); - init_u8_random_matrix(input_b, DIM_J, DIM_K, 222); - */ - init_sequence_matrix(input_a, DIM_I, DIM_J); - init_sequence_matrix(input_b, DIM_I, DIM_J); - return run_test("Tiled Matmul"); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - // printf("%p ,%p", input_a, input_b); - // printf("Testing Tiled Matmul\n"); - int passed = test_tiled_matmul(); - if (passed) { - printf("Tiled Matmul test PASSED\n"); - return 0; - } else { - printf("Tiled Matmul test FAILED\n"); - return 1; - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/transfer_test.c b/bb-tests/workloads/src/CTest/toy/transfer_test.c deleted file mode 100644 index 63baefb3..00000000 --- a/bb-tests/workloads/src/CTest/toy/transfer_test.c +++ /dev/null @@ -1,70 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t)) - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t output_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); -// static elem_t probe_matrix[DIM * DIM] __attribute__((aligned(64))); -// Used to verify content in SPAD after MVIN - -// bb_transfer(op1_addr, wr_addr, iter) wrapper in bbhw implementation -// (func7=TRANSFER_FUNC7). - -void hw_transfer(const char *test_name, elem_t *a, elem_t *b, int size) { - // Source operand in spad bank 0, write target in spad bank 1 - uint32_t op1_bank_id = 0; - uint32_t wr_bank_id = 1; - - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(wr_bank_id, 1, 1); - - // Move input into scratchpad bank0, starting at offset 0, iterate size times - // row-wise - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_fence(); - // Call Transfer instruction - bb_transfer(op1_bank_id, wr_bank_id, size); - bb_fence(); - bb_mvout((uintptr_t)b, wr_bank_id, size, 1); -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - clear_i8_matrix(output_matrix_b, size, size); - cpu_transfer(a, expected_matrix, size, size); - hw_transfer(test_name, a, output_matrix_b, size); - if (!compare_i8_matrices(expected_matrix, output_matrix_b, size, size)) { - printf("%s: Output matrix does not match expected result!\n", test_name); - return 0; - } - printf("%s: Output matrix match expected result!\n", test_name); - return 1; -} - -int test_transfer(int seed) { - init_i8_random_matrix(input_matrix_a, DIM, DIM, seed); - return run_test("Transfer", input_matrix_a, output_matrix_b, DIM); - // TransferBall test code, need to comment out the code block above -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = test_transfer(5); - if (passed) { - printf("Transfer test PASSED!\n"); - } else { - printf("Transfer test FAILED!\n"); - } - return (!passed); - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index 700c89b1..18f7bb42 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -32,12 +32,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, col_stride); } bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); bb_transpose(op2_bank_id + size, op1_bank_id, size, 0); - bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index 193cf092..597244ce 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -34,6 +34,7 @@ static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))) = { -13, -12, -11, 10, 11, 12, 13, 14, 15, 16, 17, 18, -27, -26, -25, -24, -23, -22, -21, 20, 21, 22, 23, 24, 25, 26, 27, 28, -37, -36, -35, -34, -33, -32, -31, 30, 31, 32, 33, 34, 35, 36, 37, 38}; + static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { // Row 1 of A^T (col 1 of A) -7, -17, -27, -37, -7, -17, -27, -37, -7, -17, -27, -37, -7, -17, -27, -37, @@ -79,10 +80,9 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_fence(); bb_transpose(op1_bank_id, op2_bank_id, size, 0); - bb_fence(); bb_mvout((uintptr_t)b, op2_bank_id, size, 1); + bb_fence(); } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index fed156b2..9ba00564 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -13,25 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); - transpose_u8_matrix(a, a_transposed, DIM, 32); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 6d712b47..70842579 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -13,23 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[64 * DIM] __attribute__((aligned(16))); - transpose_u8_matrix(a, a_transposed, DIM, 64); + // spad0: original A uint32_t op1_bank_id = 0; + // spad1: operand B uint32_t op2_bank_id = 1; + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index ef774128..874959c4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -13,25 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); - transpose_u8_matrix(a, a_transposed, DIM, 32); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index b9b26ec4..79f23613 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -13,25 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[48 * DIM] __attribute__((aligned(16))); - transpose_u8_matrix(a, a_transposed, DIM, 48); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 12d917c3..bf53b6ce 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -13,25 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[32 * DIM] __attribute__((aligned(16))); - transpose_u8_matrix(a, a_transposed, DIM, 32); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, DIM << 2, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index a947da22..5bbc1204 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -14,26 +14,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index a86dd4dd..c2d63900 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -13,25 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; + bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index d9475951..75b0b131 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -30,9 +30,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); - bb_fence(); bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index 3fa69673..9230e985 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -6,39 +6,84 @@ #define DIM 16 -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); +// Simple test matrices: A = identity-like, B = simple pattern +static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))) = { + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}; + +static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))) = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, + 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, 16}; + static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); +static result_t zero_matrix[DIM * DIM] __attribute__((aligned(64))) = {0}; + +// Expected result: A * B where A is diagonal-like +static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, + 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, + 26, 28, 30, 32, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, + 32, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 2, 4, + 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 1, 2, 3, 4, 5, + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, 16}; void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A + // spad3: transposed A + // spad1: operand B + // acc0: write to accumulator uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 - int acc_bank_id = 2; // virtual bank id - // bb_mem_alloc(acc_bank_id, 1, 4); + uint32_t acc_bank_id = 2; + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, DIM, 1); - bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + // Initialize accumulator bank with zeros before matrix multiplication + bb_mvin((uintptr_t)zero_matrix, acc_bank_id, DIM, 1); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - cpu_matmul(a, b, expected_matrix, size, size, size); hw_matmul(test_name, a, b, output_matrix, size); if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { printf("Test %s PASSED\n", test_name); @@ -50,8 +95,8 @@ int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { } int test_ones() { - init_u8_random_matrix(input_matrix_a, DIM, DIM, 456); - init_u8_random_matrix(input_matrix_b, DIM, DIM, 789); + // init_u8_random_matrix(input_matrix_a, DIM, DIM, 456); + // init_u8_random_matrix(input_matrix_b, DIM, DIM, 789); return run_test("Random matrices", input_matrix_a, input_matrix_b, DIM); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 070eb551..d08a62d8 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -13,25 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 9a2fa1ea..c2bf167c 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -13,26 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index 9cbf1caf..88a53ec5 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -13,23 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index 794712b1..56f19874 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -13,26 +13,26 @@ static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int size) { - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_fence(); - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c index c05ca6c4..bd56d951 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c @@ -53,33 +53,27 @@ void cpu_nn_forward(elem_t *input, elem_t *w1, elem_t *w2, result_t *hidden, // Execute hardware matrix multiplication void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { - // Transpose left matrix - static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); - transpose_u8_matrix(a, a_transposed, size, size); - - // Move matrices to scratchpad - // spad0: operand A, offset 0 + // spad0: original A uint32_t op1_bank_id = 0; - // spad1: operand B, offset 0 + // spad1: operand B uint32_t op2_bank_id = 1; - // acc0: write to accumulator, offset 0 + // acc0: write to accumulator int acc_bank_id = 2; // virtual bank id + // spad3: transposed A + uint32_t a_transposed_bank_id = 3; bb_mem_alloc(op1_bank_id, 1, 1); bb_mem_alloc(op2_bank_id, 1, 1); bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); - bb_mvin((uintptr_t)a_transposed, op1_bank_id, size, 1); + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_mvin((uintptr_t)c, acc_bank_id, size << 2, 1); - bb_fence(); - - // Execute matrix multiplication - bb_mul_warp16(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_fence(); + bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); + bb_mvin((uintptr_t)c, acc_bank_id, size, 1); - // Move result back - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size, 1); bb_fence(); } From a044611d19534e6984820e6d360e50a582ee8828 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 2 Mar 2026 23:21:23 +0800 Subject: [PATCH 124/238] [arch] fix: fix memdomain backend bugs --- .../balldomain/prototype/im2col/Im2col.scala | 4 +- .../framework/frontend/scoreboard/README.md | 286 ------------------ .../frontend/scoreboard/README_EN.md | 283 ----------------- .../decoder/attribute/shiftUop.scala | 15 +- .../memdomain/backend/MemBackend.scala | 67 ++-- .../memdomain/backend/accpipe/AccPipe.scala | 7 +- .../memdomain/midend/MemMidend.scala | 17 +- .../scala/sims/firesim/TargetConfigs.scala | 18 +- 8 files changed, 66 insertions(+), 631 deletions(-) delete mode 100644 arch/src/main/scala/framework/frontend/scoreboard/README.md delete mode 100644 arch/src/main/scala/framework/frontend/scoreboard/README_EN.md diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index fd6a7c30..0d1644c8 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -26,8 +26,8 @@ class Im2col(val b: GlobalConfig) extends Module { .find(_.ballName == "Im2colBall") .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) - private val inBW = mapping.inBW - private val outBW = mapping.outBW + private val inBW = mapping.inBW + private val outBW = mapping.outBW @public val io = IO(new Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) diff --git a/arch/src/main/scala/framework/frontend/scoreboard/README.md b/arch/src/main/scala/framework/frontend/scoreboard/README.md deleted file mode 100644 index 0f057bf8..00000000 --- a/arch/src/main/scala/framework/frontend/scoreboard/README.md +++ /dev/null @@ -1,286 +0,0 @@ -# Buckyball 指令级并行方案：Bank Scoreboard - -## 一、背景与问题 - -### 1.1 现状 - -Buckyball NPU 的 Global ROB 支持乱序发射和乱序完成，但软件中每两条指令之间都插入了 `bb_fence()`。fence 要求 ROB **完全排空**后才接受新指令，等价于 ILP=1——指令级并行**形同虚设**。 - -典型模式： -``` -MVIN(bank0) → fence → RELU(bank0→bank1) → fence → MVOUT(bank1) -``` - -fence 解决的本质问题是 **bank 级 RAW/WAR/WAW 数据依赖**，但它使用了最粗粒度的全局屏障——即使操作不同 bank 的指令之间完全无依赖，fence 也会强制它们串行执行。 - -### 1.2 目标 - -- 在 `framework/frontend/scoreboard/` 中实现一个**指令无感的 Bank Scoreboard** -- Scoreboard 只关心每条指令的**读 bank 集合**和**写 bank 集合**，不关心具体指令类型 -- 保留 fence 指令语义，但 fence 不再要求排空整个 ROB；fence 作为 ROB 中的**屏障点**，ROB 扫描发射时只扫描 fence 之前的指令 -- 统一所有指令的 bank 信息编码到 rs1 的特定位 -- 实现乱序跳跃发射：不同 bank 的指令可以越过有冲突的指令先发射 - ---- - -## 二、统一 rs1 Bank 编码 - -### 2.1 设计原则 - -所有指令的 bank 操作数统一编码到 rs1： - -``` -rs1[7:0] = bank_0 （第一操作数 bank / MVIN 写 bank / MVOUT 读 bank） -rs1[15:8] = bank_1 （第二操作数 bank，仅双操作数指令使用） -rs1[23:16] = bank_2 （写结果 bank） -``` - -### 2.2 各指令新编码 - -#### Mem Domain 指令 - -| 指令 | rs1 | rs2 | 变更说明 | -|------|-----|-----|---------| -| **MVIN** (24) | `[7:0]=wr_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | bank 从 rs2 移到 rs1[7:0]；mem_addr 移到 rs1 高位 | -| **MVOUT** (25) | `[7:0]=rd_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | 同上 | -| **MSET** (23) | `[7:0]=bank_id` | `[4:0]=row, [9:5]=col, [10]=alloc, ...` | bank 从 rs2 移到 rs1[7:0] | - -#### Ball Domain 指令 - -| 指令 | 当前编码 | 新编码变更 | -|------|---------|-----------| -| **MATMUL_WARP16** (32) | op1=rs1[7:0], op2=rs1[15:8], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]**；rs2 重排（iter 从 bit0 开始） | -| **RELU** (38) | op1=rs1[7:0], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]** | -| **TRANSPOSE** (34) | op1=rs1[7:0], wr=**rs1[15:8]** | wr 移到 **rs1[23:16]** | -| **IM2COL** (33) | op1=rs1[7:0], wr=**rs1[15:8]** | wr 移到 **rs1[23:16]** | -| **CONCAT** (39) | op1=rs1[7:0], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]** | -| **TRANSFER** (45) | op1=rs1[7:0], wr=**rs2[7:0]** | wr 移到 **rs1[23:16]** | - -> BBFP_MUL(26), MATMUL_WS(27), ABFT_SYSTOLIC(42), CONV(43), CIM(44) 等双操作数指令同 MATMUL_WARP16 模式处理。 - -### 2.3 统一提取好处 - -GlobalDecoder 只需： -``` -rd_bank_0 = rs1[7:0] -rd_bank_1 = rs1[15:8] -wr_bank = rs1[23:16] （Ball 指令） - 或 rs1[7:0] （MVIN/MSET，写 bank 就是 bank_0） -``` - -加上一个简单的 valid 查找表（按 func7 索引），即可产出完全指令无感的 `BankAccessInfo`。 - ---- - -## 三、Bank Scoreboard 设计 - -### 3.1 位置 - -`framework/frontend/scoreboard/BankScoreboard.scala` - -### 3.2 核心接口 - -```scala -class BankAccessInfo(bankIdLen: Int) extends Bundle { - val rd_bank_0_valid = Bool() - val rd_bank_0_id = UInt(bankIdLen.W) - val rd_bank_1_valid = Bool() - val rd_bank_1_id = UInt(bankIdLen.W) - val wr_bank_valid = Bool() - val wr_bank_id = UInt(bankIdLen.W) -} -``` - -Scoreboard **只接收 `BankAccessInfo`**，不关心具体指令类型、domain、func7。 - -### 3.3 内部数据结构 - -```scala -// 读计数器：多 bit，允许多条指令同时读同一 bank（RR 无冲突） -val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) -// cntWidth = log2Ceil(rob_entries + 1) - -// 写标志：1-bit，WAW 规则保证同一 bank 最多 1 个写者 in-flight -val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) -``` - -**为什么 wrCount 用 1-bit 就够？** -因为冲突检测规则中，写 bank X 要求 `bankWrBusy[X]==false`（WAW 阻塞），所以同一 bank 不可能有两条写指令同时 in-flight。 - -**为什么 rdCount 需要多 bit？** -多条指令同时读同一 bank 是允许的（RR 无冲突），因此需要计数器追踪有多少个并发读者，以便写操作判断 WAR 冲突。 - -### 3.4 冲突检测规则 - -``` -新指令读 bank X → 要求 bankWrBusy[X] == false （否则 RAW 冲突：正在被写） -新指令写 bank X → 要求 bankRdCount[X] == 0 （否则 WAR 冲突：正在被读） - 且 bankWrBusy[X] == false （否则 WAW 冲突：正在被写） -``` - -即： -```scala -def hasHazard(info: BankAccessInfo): Bool = { - val rd0 = info.rd_bank_0_valid && bankWrBusy(info.rd_bank_0_id) - val rd1 = info.rd_bank_1_valid && bankWrBusy(info.rd_bank_1_id) - val wr = info.wr_bank_valid && ( - bankRdCount(info.wr_bank_id) =/= 0.U || - bankWrBusy(info.wr_bank_id) - ) - rd0 || rd1 || wr -} -``` - -### 3.5 计数器/标志更新 - -**发射时**（issue.fire）： -```scala -when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) += 1.U } -when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) += 1.U } -when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := true.B } -``` - -**完成时**（complete.fire）： -```scala -when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) -= 1.U } -when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) -= 1.U } -when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := false.B } -``` - -完成时需要从 ROB entry 中取回 `BankAccessInfo`，因此 **GlobalRobEntry 必须保存 `BankAccessInfo`**。 - -### 3.6 MSET 精确追踪 - -MSET 标记为 `wr_bank_valid=true, wr_bank_id=rs1[7:0]`。它只与同一 bank 的其他指令串行，不阻塞其他 bank。 - -### 3.7 GP Domain (RVV) 指令 - -GP 指令不访问 scratchpad bank，其 `BankAccessInfo` 全部 valid=false，不会被 scoreboard 阻塞，也不阻塞其他指令。 - ---- - -## 四、Fence 指令新语义 - -### 4.1 设计 - -Fence **进入 ROB**（当前实现中 fence 不进 ROB），但不发射到任何 domain。 - -ROB 中 fence 的作用：**发射屏障**。ROB 从 head 扫描待发射指令时，遇到 fence 就停止扫描——fence 之后的指令不会被考虑发射。 - -### 4.2 Fence 生命周期 - -1. Fence 进入 ROB，分配 entry，标记为特殊的 fence 类型 -2. ROB 扫描发射时，以 fence 为边界，只扫描 fence 之前的指令 -3. 当 fence 成为 head 且 fence 之前的所有指令都已完成时，fence 自动标记为 complete 并被 commit -4. Head 前进到 fence 之后，后续指令可以开始发射 - -### 4.3 与 Scoreboard 的关系 - -fence 之前的指令仍然受 scoreboard 管理——不同 bank 的指令可以乱序发射。fence 只是限制了扫描窗口的边界，确保 fence 之后的指令不会越过 fence 提前发射。 - -### 4.4 实际效果 - -- **无 fence 时**：ROB 中所有指令根据 bank 依赖自由发射，最大并行度 -- **有 fence 时**：fence 前后的指令严格有序，fence 内部的指令仍可乱序 -- 软件可以选择性使用 fence 来强制特定的执行顺序（调试、特殊语义等） - ---- - -## 五、ROB 发射逻辑修改 - -### 5.1 当前逻辑 - -```scala -// 从 head 扫描，找第一个 valid && !issued && !complete 的指令 -scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) -``` - -### 5.2 新逻辑 - -```scala -// 增加两个条件：(1) 无 bank 冲突 (2) 不在 fence 之后 -// fenceBarrier(i) = true 表示该位置在某个未完成的 fence 之后 -scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) - && !hasHazard(robEntries(ptr).bankAccess) - && !isBehindFence(i) -``` - -**isBehindFence 计算**： -从 head 开始扫描，一旦遇到一个 valid 且未 complete 的 fence entry，其后所有位置的 `isBehindFence` 标记为 true。 - -```scala -val fenceBarrier = Wire(Vec(rob_entries, Bool())) -var seenFence = false.B -for (i <- 0 until rob_entries) { - val ptr = (headPtr + i.U) % rob_entries.U - val isFence = robValid(ptr) && isFenceEntry(ptr) && !robComplete(ptr) - seenFence = seenFence || isFence - fenceBarrier(i) := seenFence // fence 本身和之后的所有项都被屏蔽 -} -``` - -### 5.3 Fence Entry 的自动完成 - -当 fence 成为 head（即 fence 之前的所有指令都已 commit）时，fence 自动标记为 issued + complete： - -```scala -when (robValid(headPtr) && isFenceEntry(headPtr)) { - robIssued(headPtr) := true.B - robComplete(headPtr) := true.B -} -``` - ---- - -## 六、需要修改的文件 - -### 硬件（Scala） - -| 文件 | 改动内容 | -|------|---------| -| **新建** `framework/frontend/scoreboard/BankScoreboard.scala` | BankAccessInfo 定义、BankScoreboard 模块 | -| `framework/frontend/decoder/GobalDecoder.scala` | PostGDCmd 增加 BankAccessInfo 字段；增加 bank 提取逻辑和 valid 查表 | -| `framework/frontend/globalrs/GlobalROB.scala` | GlobalRobEntry 增加 BankAccessInfo 和 isFence 标志；集成 BankScoreboard；修改发射逻辑（hazard + fence barrier）；fence 自动完成逻辑 | -| `framework/frontend/globalrs/GlobalReservationStation.scala` | 删除旧的 fence 处理逻辑（fenceActive 等）；fence 改为进入 ROB 而非阻塞等待排空 | -| `framework/frontend/Frontend.scala` | 可能需要传递 bankNum 参数（已在 GlobalConfig 中） | -| `framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala` | bank_id 从 rs1[bankIdLen-1:0] 提取；mem_addr 从 rs1 高位提取；iter/stride 从 rs2 新位置提取 | -| `examples/toy/balldomain/DomainDecoder.scala` | wr_bank 统一从 rs1[23:16] 提取；更新 decode table | - -### 软件（C 指令宏） - -| 文件 | 改动内容 | -|------|---------| -| `bb-tests/.../isa/24_mvin.c` | bank_id 移到 rs1[7:0]，mem_addr 移到 rs1 高位 | -| `bb-tests/.../isa/25_mvout.c` | 同 MVIN | -| `bb-tests/.../isa/23_mset.c`（或含 mset 的文件） | bank_id 移到 rs1[7:0] | -| `bb-tests/.../isa/32_mul_warp16.c` | wr_bank 从 rs2[7:0] 移到 rs1[23:16] | -| `bb-tests/.../isa/38_relu.c` | wr_bank 从 rs2[7:0] 移到 rs1[23:16] | -| `bb-tests/.../isa/34_transpose.c` | wr_bank 从 rs1[15:8] 移到 rs1[23:16] | -| `bb-tests/.../isa/33_im2col.c` | wr_bank 从 rs1[15:8] 移到 rs1[23:16] | -| `bb-tests/.../isa/45_transfer.c` | wr_bank 从 rs2[7:0] 移到 rs1[23:16] | -| 其他 Ball 指令宏文件 | 类似处理 | -| 所有测试 .c 文件 | **删除 `bb_fence()` 调用** | - ---- - -## 七、实施步骤 - -1. 定义 `BankAccessInfo` Bundle，新建 `BankScoreboard` 模块 -2. 修改软件侧指令宏（MVIN/MVOUT/MSET/Ball 指令），统一 bank 编码到 rs1 -3. 修改 `MemDomainDecoder`，适配新的 rs1/rs2 字段位置 -4. 修改 `BallDomainDecoder`，wr_bank 统一从 rs1[23:16] 提取 -5. 修改 `GlobalDecoder`，增加 `BankAccessInfo` 提取逻辑 -6. 修改 `GlobalROB`，集成 BankScoreboard，实现 hazard 检测 + fence barrier 扫描逻辑 -7. 修改 `GlobalReservationStation`，删除旧 fence 逻辑，fence 改为进入 ROB -8. 删除测试中的 `bb_fence()` 调用 -9. 编译验证 + 运行测试 - ---- - -## 八、验证方案 - -1. Chisel 编译通过，无类型/语法错误 -2. 运行全部 CTest（relu_test, transpose_test, mvin_mvout_test, transfer_test, tiled_matmul 等） -3. 所有测试在无 fence 的情况下结果正确 -4. 可选：波形验证，确认不同 bank 的指令确实并行发射 -5. 可选：加回 fence 的测试，确认 fence barrier 语义正确 diff --git a/arch/src/main/scala/framework/frontend/scoreboard/README_EN.md b/arch/src/main/scala/framework/frontend/scoreboard/README_EN.md deleted file mode 100644 index 45e54a58..00000000 --- a/arch/src/main/scala/framework/frontend/scoreboard/README_EN.md +++ /dev/null @@ -1,283 +0,0 @@ -# Buckyball ILP Proposal: Bank Scoreboard for Dependency Tracking - -## 1. Background & Problem - -### 1.1 Current State - -Buckyball's Global ROB supports out-of-order issue and out-of-order completion. However, software inserts `bb_fence()` between every pair of instructions. A fence requires the ROB to **drain completely** before accepting the next instruction, effectively reducing ILP to 1 — making the out-of-order machinery **dead code**. - -Typical pattern: -``` -MVIN(bank0) → fence → RELU(bank0→bank1) → fence → MVOUT(bank1) -``` - -The fundamental problem fences solve is **bank-level RAW/WAR/WAW data hazards**. But fences use the coarsest possible granularity — a global barrier. Even instructions operating on completely independent banks are forced to serialize. - -### 1.2 Goals - -- Implement an **instruction-agnostic Bank Scoreboard** in `framework/frontend/scoreboard/` -- The scoreboard only cares about each instruction's **read bank set** and **write bank set**, not the instruction type -- Retain fence instruction semantics, but redefine fence as a **barrier point within the ROB** — the ROB scan for issue candidates stops at the fence boundary -- Unify all instructions' bank information encoding into designated bits of rs1 -- Enable out-of-order skip-issue: instructions on different banks can leapfrog hazard-blocked instructions - ---- - -## 2. Unified rs1 Bank Encoding - -### 2.1 Design Principle - -All instructions encode bank operands in rs1: - -``` -rs1[7:0] = bank_0 (1st operand bank / MVIN write bank / MVOUT read bank) -rs1[15:8] = bank_1 (2nd operand bank, dual-operand instructions only) -rs1[23:16] = bank_2 (write/result bank) -``` - -### 2.2 Per-Instruction New Encoding - -#### Mem Domain Instructions - -| Instruction | rs1 | rs2 | Change Summary | -|-------------|-----|-----|----------------| -| **MVIN** (24) | `[7:0]=wr_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | bank moved from rs2 to rs1[7:0]; mem_addr shifted to upper rs1 | -| **MVOUT** (25) | `[7:0]=rd_bank`, `[63:8]=mem_addr` | `[9:0]=depth, [28:10]=stride, [63:29]=special` | Same as MVIN | -| **MSET** (23) | `[7:0]=bank_id` | `[4:0]=row, [9:5]=col, [10]=alloc, ...` | bank moved from rs2 to rs1[7:0] | - -#### Ball Domain Instructions - -| Instruction | Current Encoding | New Change | -|-------------|-----------------|------------| -| **MATMUL_WARP16** (32) | op1=rs1[7:0], op2=rs1[15:8], wr=**rs2[7:0]** | wr moves to **rs1[23:16]**; rs2 repacked (iter starts at bit 0) | -| **RELU** (38) | op1=rs1[7:0], wr=**rs2[7:0]** | wr moves to **rs1[23:16]** | -| **TRANSPOSE** (34) | op1=rs1[7:0], wr=**rs1[15:8]** | wr moves to **rs1[23:16]** | -| **IM2COL** (33) | op1=rs1[7:0], wr=**rs1[15:8]** | wr moves to **rs1[23:16]** | -| **CONCAT** (39) | op1=rs1[7:0], wr=**rs2[7:0]** | wr moves to **rs1[23:16]** | -| **TRANSFER** (45) | op1=rs1[7:0], wr=**rs2[7:0]** | wr moves to **rs1[23:16]** | - -> BBFP_MUL(26), MATMUL_WS(27), ABFT_SYSTOLIC(42), CONV(43), CIM(44) and other dual-operand instructions follow the MATMUL_WARP16 pattern. - -### 2.3 Unified Extraction - -After unification, the GlobalDecoder only needs: -``` -rd_bank_0 = rs1[7:0] // always -rd_bank_1 = rs1[15:8] // always (valid flag controls usage) -wr_bank = rs1[23:16] // for Ball instructions - or rs1[7:0] // for MVIN/MSET (write bank == bank_0) -``` - -Plus a simple valid lookup table indexed by func7, producing a fully instruction-agnostic `BankAccessInfo`. - ---- - -## 3. Bank Scoreboard Design - -### 3.1 Location - -`framework/frontend/scoreboard/BankScoreboard.scala` - -### 3.2 Core Interface - -```scala -class BankAccessInfo(bankIdLen: Int) extends Bundle { - val rd_bank_0_valid = Bool() - val rd_bank_0_id = UInt(bankIdLen.W) - val rd_bank_1_valid = Bool() - val rd_bank_1_id = UInt(bankIdLen.W) - val wr_bank_valid = Bool() - val wr_bank_id = UInt(bankIdLen.W) -} -``` - -The scoreboard **only receives `BankAccessInfo`** — it has no knowledge of instruction types, domains, or func7 codes. - -### 3.3 Internal Data Structure - -```scala -// Read counter: multi-bit, allows multiple instructions to read the same bank concurrently (RR is not a conflict) -val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) -// cntWidth = log2Ceil(rob_entries + 1) - -// Write flag: 1-bit, WAW rule guarantees at most 1 writer in-flight per bank -val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) -``` - -**Why is 1-bit sufficient for wrCount?** -The hazard detection rule requires `bankWrBusy[X]==false` before issuing a write to bank X (WAW blocking). Therefore, it is impossible for two write instructions targeting the same bank to be in-flight simultaneously. - -**Why does rdCount need multiple bits?** -Multiple instructions reading the same bank concurrently is allowed (RR is not a conflict). A counter is needed to track how many concurrent readers exist, so write operations can detect WAR hazards. - -### 3.4 Hazard Detection Rules - -``` -New instruction reads bank X → requires bankWrBusy[X] == false (RAW hazard: bank is being written) -New instruction writes bank X → requires bankRdCount[X] == 0 (WAR hazard: bank is being read) - AND bankWrBusy[X] == false (WAW hazard: bank is being written) -``` - -```scala -def hasHazard(info: BankAccessInfo): Bool = { - val rd0 = info.rd_bank_0_valid && bankWrBusy(info.rd_bank_0_id) - val rd1 = info.rd_bank_1_valid && bankWrBusy(info.rd_bank_1_id) - val wr = info.wr_bank_valid && ( - bankRdCount(info.wr_bank_id) =/= 0.U || - bankWrBusy(info.wr_bank_id) - ) - rd0 || rd1 || wr -} -``` - -### 3.5 Counter/Flag Updates - -**On issue** (issue.fire): -```scala -when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) += 1.U } -when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) += 1.U } -when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := true.B } -``` - -**On complete** (complete.fire): -```scala -when(info.rd_bank_0_valid) { bankRdCount(info.rd_bank_0_id) -= 1.U } -when(info.rd_bank_1_valid) { bankRdCount(info.rd_bank_1_id) -= 1.U } -when(info.wr_bank_valid) { bankWrBusy(info.wr_bank_id) := false.B } -``` - -Completion requires retrieving `BankAccessInfo` from the ROB entry, so **GlobalRobEntry must store `BankAccessInfo`**. - -### 3.6 MSET Precise Tracking - -MSET is marked as `wr_bank_valid=true, wr_bank_id=rs1[7:0]`. It serializes only with instructions accessing the same bank, without blocking other banks. - -### 3.7 GP Domain (RVV) Instructions - -GP instructions don't access scratchpad banks. Their `BankAccessInfo` has all valid flags set to false — they are never blocked by the scoreboard and don't block others. - ---- - -## 4. Fence Instruction — New Semantics - -### 4.1 Design - -Fence **enters the ROB** (currently it does not). But it is not dispatched to any execution domain. - -Fence acts as an **issue barrier** within the ROB. When the ROB scans from head to find issuable instructions, it **stops scanning at the first unresolved fence** — all instructions after the fence are invisible to the issue logic. - -### 4.2 Fence Lifecycle - -1. Fence enters ROB, receives an entry, marked with a fence flag -2. ROB issue scan uses fence as boundary — only instructions before fence are candidates -3. When fence reaches head (all prior instructions committed), fence auto-completes -4. Head advances past fence, subsequent instructions become visible for issue - -### 4.3 Relationship with Scoreboard - -Instructions before the fence are still managed by the scoreboard — different-bank instructions can issue out of order. The fence only limits the scan window boundary, ensuring post-fence instructions cannot leapfrog the fence. - -### 4.4 Practical Effect - -- **Without fence**: All instructions in ROB are candidates based on bank dependencies — maximum parallelism -- **With fence**: Instructions before and after fence are strictly ordered; instructions within each group can still reorder freely -- Software can selectively use fence for forced ordering (debugging, special semantics, etc.) - ---- - -## 5. ROB Issue Logic Modification - -### 5.1 Current Logic - -```scala -// Scan from head, find first valid && !issued && !complete instruction -scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) -``` - -### 5.2 New Logic - -```scala -// Add two conditions: (1) no bank hazard (2) not behind a fence -scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) - && !hasHazard(robEntries(ptr).bankAccess) - && !isBehindFence(i) -``` - -**isBehindFence computation:** -Scan from head; once a valid, uncompleted fence entry is encountered, all subsequent positions are marked `isBehindFence = true`. - -```scala -val fenceBarrier = Wire(Vec(rob_entries, Bool())) -var seenFence = false.B -for (i <- 0 until rob_entries) { - val ptr = (headPtr + i.U) % rob_entries.U - val isFence = robValid(ptr) && isFenceEntry(ptr) && !robComplete(ptr) - seenFence = seenFence || isFence - fenceBarrier(i) := seenFence // fence itself and everything after are masked -} -``` - -### 5.3 Fence Auto-Completion - -When fence becomes head (all prior instructions committed), it auto-marks as issued + complete: - -```scala -when (robValid(headPtr) && isFenceEntry(headPtr)) { - robIssued(headPtr) := true.B - robComplete(headPtr) := true.B -} -``` - ---- - -## 6. Files to Modify - -### Hardware (Scala) - -| File | Change | -|------|--------| -| **NEW** `framework/frontend/scoreboard/BankScoreboard.scala` | BankAccessInfo definition, BankScoreboard module | -| `framework/frontend/decoder/GobalDecoder.scala` | Add BankAccessInfo to PostGDCmd; add bank extraction logic with valid lookup table | -| `framework/frontend/globalrs/GlobalROB.scala` | Add BankAccessInfo + isFence to GlobalRobEntry; integrate BankScoreboard; modify issue logic (hazard + fence barrier); fence auto-completion | -| `framework/frontend/globalrs/GlobalReservationStation.scala` | Remove old fence logic (fenceActive etc.); fence now enters ROB instead of stalling until drain | -| `framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala` | Extract bank_id from rs1[bankIdLen-1:0]; mem_addr from rs1 upper bits; iter/stride from new rs2 positions | -| `examples/toy/balldomain/DomainDecoder.scala` | wr_bank from rs1[23:16]; update decode table | - -### Software (C instruction macros) - -| File | Change | -|------|--------| -| `bb-tests/.../isa/24_mvin.c` | bank_id to rs1[7:0], mem_addr to rs1 upper bits | -| `bb-tests/.../isa/25_mvout.c` | Same as MVIN | -| `bb-tests/.../isa/23_mset.c` (or equivalent) | bank_id to rs1[7:0] | -| `bb-tests/.../isa/32_mul_warp16.c` | wr_bank from rs2[7:0] to rs1[23:16] | -| `bb-tests/.../isa/38_relu.c` | wr_bank from rs2[7:0] to rs1[23:16] | -| `bb-tests/.../isa/34_transpose.c` | wr_bank from rs1[15:8] to rs1[23:16] | -| `bb-tests/.../isa/33_im2col.c` | wr_bank from rs1[15:8] to rs1[23:16] | -| `bb-tests/.../isa/45_transfer.c` | wr_bank from rs2[7:0] to rs1[23:16] | -| Other Ball instruction macro files | Similar treatment | -| All test .c files | **Remove `bb_fence()` calls** | - ---- - -## 7. Implementation Steps - -1. Define `BankAccessInfo` Bundle; create `BankScoreboard` module in `framework/frontend/scoreboard/` -2. Modify software instruction macros (MVIN/MVOUT/MSET/Ball instructions) — unify bank encoding to rs1 -3. Modify `MemDomainDecoder` to adapt to new rs1/rs2 field positions -4. Modify `BallDomainDecoder` — wr_bank from rs1[23:16] -5. Modify `GlobalDecoder` — add `BankAccessInfo` extraction logic -6. Modify `GlobalROB` — integrate BankScoreboard, implement hazard detection + fence barrier scan -7. Modify `GlobalReservationStation` — remove old fence logic, fence enters ROB -8. Remove `bb_fence()` calls from tests -9. Compile + run tests - ---- - -## 8. Verification - -1. Chisel compilation passes with no type/syntax errors -2. Run all CTests (relu_test, transpose_test, mvin_mvout_test, transfer_test, tiled_matmul, etc.) -3. All tests produce correct results without fence -4. Optional: waveform inspection confirming different-bank instructions issue in parallel -5. Optional: test with fence re-inserted, confirming fence barrier semantics work correctly diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala index efc384bf..449be19d 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala @@ -6,11 +6,11 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern trait ShiftUopType extends Uop -object shiftUop0 extends ShiftUopType -object shiftUop1 extends ShiftUopType -object shiftUop2 extends ShiftUopType -object shiftUop4 extends ShiftUopType -object shiftUop6 extends ShiftUopType +object shiftUop0 extends ShiftUopType +object shiftUop1 extends ShiftUopType +object shiftUop2 extends ShiftUopType +object shiftUop4 extends ShiftUopType +object shiftUop6 extends ShiftUopType object ShiftUop { @@ -21,9 +21,8 @@ object ShiftUop { t2 _ -> shiftUop2, t4 _ -> shiftUop4, t6 _ -> shiftUop6 - ).collectFirst { - case (fn, tpe) if fn(t1DecodePattern) => tpe - }.getOrElse(UopDC) + ).collectFirst { case (fn, tpe) if fn(t1DecodePattern) => tpe } + .getOrElse(UopDC) } def t0(t1DecodePattern: T1DecodePattern): Boolean = { diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 704ce639..ebff5927 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -75,16 +75,18 @@ class MemBackend(val b: GlobalConfig) extends Module { val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) - // Memory trace DPI-C module - val mtrace = Module(new MTraceDPI) - mtrace.io.is_write := 0.U - mtrace.io.channel := 0.U - mtrace.io.vbank_id := 0.U - mtrace.io.group_id := 0.U - mtrace.io.addr := 0.U - mtrace.io.data_lo := 0.U - mtrace.io.data_hi := 0.U - mtrace.io.enable := false.B + // Per-channel memory trace DPI-C modules to avoid losing simultaneous events + val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) + for (mt <- mtraces) { + mt.io.is_write := 0.U + mt.io.channel := 0.U + mt.io.vbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B + } // ----------------------------------------------------------------------------- // Mapping table @@ -115,11 +117,14 @@ class MemBackend(val b: GlobalConfig) extends Module { } def deleteEntry(vbank_id: UInt): Unit = { - val entry = mappingTable(vbank_id) - entry.valid := false.B - entry.vbank_id := 0.U - entry.is_multi := false.B - entry.group_id := 0.U + for (i <- 0 until b.memDomain.bankNum) { + when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id) { + mappingTable(i).valid := false.B + mappingTable(i).vbank_id := 0.U + mappingTable(i).is_multi := false.B + mappingTable(i).group_id := 0.U + } + } } def getFreePbankId(): UInt = { @@ -194,26 +199,26 @@ class MemBackend(val b: GlobalConfig) extends Module { // Memory trace: read request when(io.mem_req(i).read.req.fire) { - mtrace.io.is_write := 0.U - mtrace.io.channel := i.U - mtrace.io.vbank_id := io.mem_req(i).bank_id - mtrace.io.group_id := io.mem_req(i).group_id - mtrace.io.addr := io.mem_req(i).read.req.bits.addr - mtrace.io.data_lo := 0.U - mtrace.io.data_hi := 0.U - mtrace.io.enable := true.B + mtraces(i).io.is_write := 0.U + mtraces(i).io.channel := i.U + mtraces(i).io.vbank_id := io.mem_req(i).bank_id + mtraces(i).io.group_id := io.mem_req(i).group_id + mtraces(i).io.addr := io.mem_req(i).read.req.bits.addr + mtraces(i).io.data_lo := 0.U + mtraces(i).io.data_hi := 0.U + mtraces(i).io.enable := true.B } // Memory trace: write request when(io.mem_req(i).write.req.fire) { - mtrace.io.is_write := 1.U - mtrace.io.channel := i.U - mtrace.io.vbank_id := io.mem_req(i).bank_id - mtrace.io.group_id := io.mem_req(i).group_id - mtrace.io.addr := io.mem_req(i).write.req.bits.addr - mtrace.io.data_lo := io.mem_req(i).write.req.bits.data(63, 0) - mtrace.io.data_hi := io.mem_req(i).write.req.bits.data(127, 64) - mtrace.io.enable := true.B + mtraces(i).io.is_write := 1.U + mtraces(i).io.channel := i.U + mtraces(i).io.vbank_id := io.mem_req(i).bank_id + mtraces(i).io.group_id := io.mem_req(i).group_id + mtraces(i).io.addr := io.mem_req(i).write.req.bits.addr + mtraces(i).io.data_lo := io.mem_req(i).write.req.bits.data(63, 0) + mtraces(i).io.data_hi := io.mem_req(i).write.req.bits.data(127, 64) + mtraces(i).io.enable := true.B } for (j <- 0 until b.memDomain.bankNum) { diff --git a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala index 4d23f043..9422637c 100644 --- a/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala +++ b/arch/src/main/scala/framework/memdomain/backend/accpipe/AccPipe.scala @@ -44,10 +44,9 @@ class AccPipe(val b: GlobalConfig) extends Module { io.sramRead <> io.mem_req.read io.sramWrite <> io.mem_req.write - //Read Acc - when(io.is_multi) { - io.sramRead.req.bits.addr := io.mem_req.read.req.bits.addr(log2Ceil(b.memDomain.bankEntries) - 1, 2) - } + // Each group has its own physical bank, so no address shifting is needed. + // The previous is_multi shift (addr >> 2) was incorrect: it caused mvout reads + // to access wrong physical addresses while matmul writes used unshifted addresses. //group_id output val group_id_reg = RegInit(0.U(3.W)) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index e17aed95..b7820d7a 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -128,22 +128,23 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).bank_id := 0.U io.mem_req(i).group_id := 0.U - val isRead = mappingTable(i).isRead - val ballRead = io.balldomain.bankRead(mappingTable(i).id).io - val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io - val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id - val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id - val group_id = io.balldomain.bankWrite(mappingTable(i).id).group_id + val isRead = mappingTable(i).isRead + val ballRead = io.balldomain.bankRead(mappingTable(i).id).io + val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io + val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id + val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id + val rgroup_id = io.balldomain.bankRead(mappingTable(i).id).group_id + val wgroup_id = io.balldomain.bankWrite(mappingTable(i).id).group_id when(mappingTable(i).valid) { when(isRead) { io.mem_req(i).read <> ballRead io.mem_req(i).bank_id := rbank_id - io.mem_req(i).group_id := group_id + io.mem_req(i).group_id := rgroup_id }.otherwise { io.mem_req(i).write <> ballWrite io.mem_req(i).bank_id := wbank_id - io.mem_req(i).group_id := group_id + io.mem_req(i).group_id := wgroup_id } } } diff --git a/arch/src/main/scala/sims/firesim/TargetConfigs.scala b/arch/src/main/scala/sims/firesim/TargetConfigs.scala index e22a6825..7cc7bb8e 100644 --- a/arch/src/main/scala/sims/firesim/TargetConfigs.scala +++ b/arch/src/main/scala/sims/firesim/TargetConfigs.scala @@ -3,7 +3,7 @@ package sims.firesim import chisel3._ import java.io.File -import org.chipsalliance.cde.config.{Config} +import org.chipsalliance.cde.config.Config import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ @@ -11,20 +11,20 @@ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => { + case BootROMLocated(x) => val chipyardBootROM = new File(s"./thirdparty/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img") - val firesimBootROM = new File( + val firesimBootROM = new File( s"./thirdparty/chipyard/target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img" ) - val bootROMPath = if (chipyardBootROM.exists()) { - chipyardBootROM.getAbsolutePath() - } else { - firesimBootROM.getAbsolutePath() - } + val bootROMPath = + if (chipyardBootROM.exists()) { + chipyardBootROM.getAbsolutePath() + } else { + firesimBootROM.getAbsolutePath() + } up(BootROMLocated(x)).map(_.copy(contentFileName = bootROMPath)) - } }) class FireSimGemminiBuckyballConfig From a58c76e25ad33a6fa62851a4d0c5d170695a73b9 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Mar 2026 00:19:48 +0800 Subject: [PATCH 125/238] [arch] chore: update subproject commits and scalafmt version; remove debug print statements in MemStorer and VecLoadUnit --- arch/.scalafmt.conf | 2 +- .../prototype/vector/VecCtrlUnit.scala | 8 -- .../prototype/vector/VecLoadUnit.scala | 24 +--- .../framework/core/rocket/LazyRoCCBB.scala | 46 +++---- .../framework/core/rocket/RocketCoreBB.scala | 95 ++++++++------- .../frontend/globalrs/GlobalROB.scala | 112 +++++++++++------- .../gpdomain/sequencer/Sequencer.scala | 2 +- .../decoder/attribute/shiftUop.scala | 10 +- .../memdomain/backend/MemBackend.scala | 97 ++++++++------- .../frontend/outside_channel/MemStorer.scala | 23 ---- .../memdomain/midend/MemMidend.scala | 46 +++---- .../scala/sims/firesim/TargetConfigs.scala | 2 +- .../main/scala/sims/verify/TargetConfig.scala | 35 +++--- scripts/nix/build-env-scala.nix | 10 +- 14 files changed, 239 insertions(+), 273 deletions(-) diff --git a/arch/.scalafmt.conf b/arch/.scalafmt.conf index 68e263b3..91d1b07c 100644 --- a/arch/.scalafmt.conf +++ b/arch/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 2.6.4 +version = 2.7.5 # Only format src/main/scala directory project.includeFilters = [ diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala index 8d611130..d92e4bec 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala @@ -53,14 +53,6 @@ class VecCtrlUnit(val b: GlobalConfig) extends Module { is_acc := false.B // Deprecated: use wmode instead mode := io.cmdReq.bits.cmd.special(0) - printf( - "[VecCtrl] Received cmd: op1_bank=%d op2_bank=%d wr_bank=%d iter=%d\n", - io.cmdReq.bits.cmd.op1_bank, - io.cmdReq.bits.cmd.op2_bank, - io.cmdReq.bits.cmd.wr_bank, - io.cmdReq.bits.cmd.iter - ) - state := busy } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 0321ad50..c0f082c5 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -99,9 +99,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.bankReadReq(0).bits.addr := op1_addr + op1_iter_counter op1_iter_counter := Mux(io.bankReadReq(0).ready, op1_iter_counter + 1.U, op1_iter_counter) wait1_reg := Mux((op1_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) - when(io.bankReadReq(0).fire) { - printf("[VecLD] op1 bank=%d addr=%d iter_cnt=%d\n", op1_bank, op1_addr + op1_iter_counter, op1_iter_counter) - } + when(io.bankReadReq(0).fire) {} } when(state === busy && io.ld_ex_o.ready && !wait2_reg) { @@ -109,9 +107,7 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.bankReadReq(1).bits.addr := op2_addr + op2_iter_counter op2_iter_counter := Mux(io.bankReadReq(1).ready, op2_iter_counter + 1.U, op2_iter_counter) wait2_reg := Mux((op2_iter_counter + 1.U) % 16.U === 0.U, 1.U, 0.U) - when(io.bankReadReq(1).fire) { - printf("[VecLD] op2 bank=%d addr=%d iter_cnt=%d\n", op2_bank, op2_addr + op2_iter_counter, op2_iter_counter) - } + when(io.bankReadReq(1).fire) {} } when(wait1_reg) { @@ -143,22 +139,6 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { io.ld_ex_o.bits.op2 := bankRespQueue1.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) ld_ex_iter_reg := ld_ex_iter_reg + 1.U io.ld_ex_o.bits.iter := ld_ex_iter_reg - - // Debug: print first 8 elements of op1 and op2 - when(ld_ex_iter_reg < 8.U) { - printf( - "[VecLD_DATA] iter=%d op1[0-3]=%d,%d,%d,%d op2[0-3]=%d,%d,%d,%d\n", - ld_ex_iter_reg, - io.ld_ex_o.bits.op1(0), - io.ld_ex_o.bits.op1(1), - io.ld_ex_o.bits.op1(2), - io.ld_ex_o.bits.op1(3), - io.ld_ex_o.bits.op2(0), - io.ld_ex_o.bits.op2(1), - io.ld_ex_o.bits.op2(2), - io.ld_ex_o.bits.op2(3) - ) - } }.otherwise { io.ld_ex_o.valid := false.B io.ld_ex_o.bits.iter := 0.U diff --git a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala index 0f2628c7..92207e29 100644 --- a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala +++ b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala @@ -111,24 +111,25 @@ trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => trait HasLazyRoCCModuleBB extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImpBB => - val (respArb, cmdRouter) = if (outer.roccs.nonEmpty) { - val respArb = Module(new RRArbiter(new RoCCResponseBB(coreParams.xLen), outer.roccs.size)) - // Get usingRVVRoCC from tile parameters - val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC - val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) - outer.roccs.zipWithIndex.foreach { - case (rocc, i) => - rocc.module.io.ptw ++=: ptwPorts - rocc.module.io.cmd <> cmdRouter.io.out(i) - val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) - dcIF.io.requestor <> rocc.module.io.mem - dcachePorts += dcIF.io.cache - respArb.io.in(i) <> Queue(rocc.module.io.resp) + val (respArb, cmdRouter) = + if (outer.roccs.nonEmpty) { + val respArb = Module(new RRArbiter(new RoCCResponseBB(coreParams.xLen), outer.roccs.size)) + // Get usingRVVRoCC from tile parameters + val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC + val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) + outer.roccs.zipWithIndex.foreach { + case (rocc, i) => + rocc.module.io.ptw ++=: ptwPorts + rocc.module.io.cmd <> cmdRouter.io.out(i) + val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) + dcIF.io.requestor <> rocc.module.io.mem + dcachePorts += dcIF.io.cache + respArb.io.in(i) <> Queue(rocc.module.io.resp) + } + (Some(respArb), Some(cmdRouter)) + } else { + (None, None) } - (Some(respArb), Some(cmdRouter)) - } else { - (None, None) - } val roccCSRIOs = outer.roccs.map(_.module.io.csrs) } @@ -152,11 +153,12 @@ class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implic case ((out, matches), i) => // In RVVRoCC mode: route unmatched opcodes to first RoCC (index 0) // Otherwise: only route if opcode matches - val shouldRoute = if (usingRVVRoCC && i == 0) { - matches || !anyMatch // First RoCC gets matched opcodes OR unmatched opcodes - } else { - matches // Other RoCCs only get their matched opcodes - } + val shouldRoute = + if (usingRVVRoCC && i == 0) { + matches || !anyMatch // First RoCC gets matched opcodes OR unmatched opcodes + } else { + matches // Other RoCCs only get their matched opcodes + } out.valid := cmd.valid && shouldRoute out.bits := cmd.bits diff --git a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala index 12e5fa5f..c92b681a 100644 --- a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala @@ -469,29 +469,30 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) ) else Nil)) - val (ex_new_vl, ex_new_vconfig) = if (usingVector) { - val ex_new_vtype = VType.fromUInt(MuxCase( - ex_rs(1), - Seq( - ex_reg_inst(31, 30).andR -> ex_reg_inst(29, 20), - !ex_reg_inst(31) -> ex_reg_inst(30, 20) + val (ex_new_vl, ex_new_vconfig) = + if (usingVector) { + val ex_new_vtype = VType.fromUInt(MuxCase( + ex_rs(1), + Seq( + ex_reg_inst(31, 30).andR -> ex_reg_inst(29, 20), + !ex_reg_inst(31) -> ex_reg_inst(30, 20) + ) + )) + val ex_avl = Mux( + ex_ctrl.rxs1, + Mux( + ex_reg_inst(19, 15) === 0.U, + Mux(ex_reg_inst(11, 7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), + ex_rs(0) + ), + ex_reg_inst(19, 15) ) - )) - val ex_avl = Mux( - ex_ctrl.rxs1, - Mux( - ex_reg_inst(19, 15) === 0.U, - Mux(ex_reg_inst(11, 7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), - ex_rs(0) - ), - ex_reg_inst(19, 15) - ) - val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) - val ex_new_vconfig = Wire(new VConfig) - ex_new_vconfig.vtype := ex_new_vtype - ex_new_vconfig.vl := ex_new_vl - (Some(ex_new_vl), Some(ex_new_vconfig)) - } else { (None, None) } + val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) + val ex_new_vconfig = Wire(new VConfig) + ex_new_vconfig.vtype := ex_new_vtype + ex_new_vconfig.vl := ex_new_vl + (Some(ex_new_vl), Some(ex_new_vconfig)) + } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw @@ -991,7 +992,7 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && - !csr.io.trace(0).exception + !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) @@ -1067,15 +1068,16 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) - val id_stall_fpu = if (usingFPU) { - val fp_sboard = new Scoreboard(32) - fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) - val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) - fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) - fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) + val id_stall_fpu = + if (usingFPU) { + val fp_sboard = new Scoreboard(32) + fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) + val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) + fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) + fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) - checkHazards(fp_hazard_targets, fp_sboard.read _) - } else false.B + checkHazards(fp_hazard_targets, fp_sboard.read _) + } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant @@ -1253,12 +1255,12 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid) clock_en_reg := - ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight - io.ptw.customCSRs.disableCoreClockGate || // chicken bit - !div.io.req.ready || // mul/div in flight - usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight - io.dmem.replay_next || // long-latency load replaying - (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending + ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight + io.ptw.customCSRs.disableCoreClockGate || // chicken bit + !div.io.req.ready || // mul/div in flight + usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight + io.dmem.replay_next || // long-latency load replaying + (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en) } @@ -1381,15 +1383,16 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_ || _) - def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea - else { - // efficient means to compress 64-bit VA into vaddrBits+1 bits - // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) - val b = vaddrBitsExtended - 1 - val a = (a0 >> b).asSInt - val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b - 1)) - Cat(msb, ea(b - 1, 0)) - } + def encodeVirtualAddress(a0: UInt, ea: UInt) = + if (vaddrBitsExtended == vaddrBits) ea + else { + // efficient means to compress 64-bit VA into vaddrBits+1 bits + // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) + val b = vaddrBitsExtended - 1 + val a = (a0 >> b).asSInt + val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b - 1)) + Cat(msb, ea(b - 1, 0)) + } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 07cbad84..36a73aa2 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -10,6 +10,7 @@ import framework.frontend.scoreboard.BankScoreboard // DPI-C BlackBox for instruction trace class ITraceDPI extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { val is_issue = Input(UInt(8.W)) val rob_id = Input(UInt(32.W)) @@ -20,33 +21,35 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { val enable = Input(Bool()) }) - setInline("ITraceDPI.v", + setInline( + "ITraceDPI.v", """ - |import "DPI-C" function void dpi_itrace( - | input byte unsigned is_issue, - | input int unsigned rob_id, - | input int unsigned domain_id, - | input int unsigned funct, - | input longint unsigned rs1, - | input longint unsigned rs2 - |); - | - |module ITraceDPI( - | input [7:0] is_issue, - | input [31:0] rob_id, - | input [31:0] domain_id, - | input [31:0] funct, - | input [63:0] rs1, - | input [63:0] rs2, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2); - | end - | end - |endmodule - """.stripMargin) + |import "DPI-C" function void dpi_itrace( + | input byte unsigned is_issue, + | input int unsigned rob_id, + | input int unsigned domain_id, + | input int unsigned funct, + | input longint unsigned rs1, + | input longint unsigned rs2 + |); + | + |module ITraceDPI( + | input [7:0] is_issue, + | input [31:0] rob_id, + | input [31:0] domain_id, + | input [31:0] funct, + | input [63:0] rs1, + | input [63:0] rs2, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2); + | end + | end + |endmodule + """.stripMargin + ) } @instantiable @@ -134,11 +137,18 @@ class GlobalROB(val b: GlobalConfig) extends Module { tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) - printf("[ROB ALLOC] rob_id=%d domain=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - robIdCounter, io.alloc.bits.domain_id, io.alloc.bits.cmd.funct, - io.alloc.bits.bankAccess.rd_bank_0_valid, io.alloc.bits.bankAccess.rd_bank_0_id, - io.alloc.bits.bankAccess.rd_bank_1_valid, io.alloc.bits.bankAccess.rd_bank_1_id, - io.alloc.bits.bankAccess.wr_bank_valid, io.alloc.bits.bankAccess.wr_bank_id) + printf( + "[ROB ALLOC] rob_id=%d domain=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + robIdCounter, + io.alloc.bits.domain_id, + io.alloc.bits.cmd.funct, + io.alloc.bits.bankAccess.rd_bank_0_valid, + io.alloc.bits.bankAccess.rd_bank_0_id, + io.alloc.bits.bankAccess.rd_bank_1_valid, + io.alloc.bits.bankAccess.rd_bank_1_id, + io.alloc.bits.bankAccess.wr_bank_valid, + io.alloc.bits.bankAccess.wr_bank_id + ) } // ============================================================================= @@ -152,7 +162,7 @@ class GlobalROB(val b: GlobalConfig) extends Module { when(io.complete.fire) { val completeId = io.complete.bits - robComplete(completeId) := true.B + robComplete(completeId) := true.B // When complete, decrement issued count when(robIssued(completeId)) { issuedCount := issuedCount - 1.U @@ -170,8 +180,12 @@ class GlobalROB(val b: GlobalConfig) extends Module { itrace.io.rs2 := robEntries(completeId).cmd.cmd.rs2 itrace.io.enable := true.B - printf("[ROB COMPLETE] rob_id=%d domain=%d func7=%d\n", - completeId, robEntries(completeId).cmd.domain_id, robEntries(completeId).cmd.cmd.funct) + printf( + "[ROB COMPLETE] rob_id=%d domain=%d func7=%d\n", + completeId, + robEntries(completeId).cmd.domain_id, + robEntries(completeId).cmd.cmd.funct + ) } // ============================================================================= @@ -206,14 +220,17 @@ class GlobalROB(val b: GlobalConfig) extends Module { // Debug: print when a candidate is blocked by hazard when(hasValid && scoreboard.hasHazard) { - printf("[ROB HAZARD] ptr=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - actualIssuePtr, robEntries(actualIssuePtr).cmd.cmd.funct, + printf( + "[ROB HAZARD] ptr=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + actualIssuePtr, + robEntries(actualIssuePtr).cmd.cmd.funct, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_valid, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_id, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_valid, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_id, robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_valid, - robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_id) + robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_id + ) } // Can only issue if issue limit is not reached and no bank hazard @@ -229,8 +246,8 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) when(io.issue.fire) { - robIssued(issuePtr) := true.B - issuedCount := issuedCount + 1.U + robIssued(issuePtr) := true.B + issuedCount := issuedCount + 1.U // Update scoreboard: claim bank resources scoreboard.issue.valid := true.B scoreboard.issue.bits := robEntries(issuePtr).cmd.bankAccess @@ -244,12 +261,19 @@ class GlobalROB(val b: GlobalConfig) extends Module { itrace.io.rs2 := robEntries(issuePtr).cmd.cmd.rs2 itrace.io.enable := true.B - printf("[ROB ISSUE] rob_id=%d domain=%d func7=%d ptr=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - robEntries(issuePtr).rob_id, robEntries(issuePtr).cmd.domain_id, robEntries(issuePtr).cmd.cmd.funct, + printf( + "[ROB ISSUE] rob_id=%d domain=%d func7=%d ptr=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", + robEntries(issuePtr).rob_id, + robEntries(issuePtr).cmd.domain_id, + robEntries(issuePtr).cmd.cmd.funct, issuePtr, - robEntries(issuePtr).cmd.bankAccess.rd_bank_0_valid, robEntries(issuePtr).cmd.bankAccess.rd_bank_0_id, - robEntries(issuePtr).cmd.bankAccess.rd_bank_1_valid, robEntries(issuePtr).cmd.bankAccess.rd_bank_1_id, - robEntries(issuePtr).cmd.bankAccess.wr_bank_valid, robEntries(issuePtr).cmd.bankAccess.wr_bank_id) + robEntries(issuePtr).cmd.bankAccess.rd_bank_0_valid, + robEntries(issuePtr).cmd.bankAccess.rd_bank_0_id, + robEntries(issuePtr).cmd.bankAccess.rd_bank_1_valid, + robEntries(issuePtr).cmd.bankAccess.rd_bank_1_id, + robEntries(issuePtr).cmd.bankAccess.wr_bank_valid, + robEntries(issuePtr).cmd.bankAccess.wr_bank_id + ) } // ============================================================================= diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala b/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala index 81ba1266..c7560fb1 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala @@ -96,7 +96,7 @@ class Sequencer(val b: GlobalConfig) extends Module { requestReg.bits.decodeResult := decoded requestReg.bits.instructionIndex := instructionCounter requestReg.bits.vdIsV0 := (io.global_issue_i.bits.cmd.cmd.raw_inst(11, 7) === 0.U) && - (io.global_issue_i.bits.cmd.cmd.raw_inst(6) || !io.global_issue_i.bits.cmd.cmd.raw_inst(5)) + (io.global_issue_i.bits.cmd.cmd.raw_inst(6) || !io.global_issue_i.bits.cmd.cmd.raw_inst(5)) requestReg.bits.writeByte := 0.U // TODO: calculate based on vl and sew instructionCounter := nextInstructionCounter diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala index 449be19d..22f7246f 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/attribute/shiftUop.scala @@ -6,11 +6,11 @@ package framework.gpdomain.sequencer.decoder.attribute import framework.gpdomain.sequencer.decoder.T1DecodePattern trait ShiftUopType extends Uop -object shiftUop0 extends ShiftUopType -object shiftUop1 extends ShiftUopType -object shiftUop2 extends ShiftUopType -object shiftUop4 extends ShiftUopType -object shiftUop6 extends ShiftUopType +object shiftUop0 extends ShiftUopType +object shiftUop1 extends ShiftUopType +object shiftUop2 extends ShiftUopType +object shiftUop4 extends ShiftUopType +object shiftUop6 extends ShiftUopType object ShiftUop { diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index ebff5927..b6f0ae18 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -10,6 +10,7 @@ import framework.memdomain.backend.accpipe.AccPipe // DPI-C BlackBox for memory trace class MTraceDPI extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { val is_write = Input(UInt(8.W)) val channel = Input(UInt(32.W)) @@ -21,41 +22,43 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { val enable = Input(Bool()) }) - setInline("MTraceDPI.v", + setInline( + "MTraceDPI.v", """ - |import "DPI-C" function void dpi_mtrace( - | input byte unsigned is_write, - | input int unsigned channel, - | input int unsigned vbank_id, - | input int unsigned group_id, - | input int unsigned addr, - | input longint unsigned data_lo, - | input longint unsigned data_hi - |); - | - |module MTraceDPI( - | input [7:0] is_write, - | input [31:0] channel, - | input [31:0] vbank_id, - | input [31:0] group_id, - | input [31:0] addr, - | input [63:0] data_lo, - | input [63:0] data_hi, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); - | end - | end - |endmodule - """.stripMargin) + |import "DPI-C" function void dpi_mtrace( + | input byte unsigned is_write, + | input int unsigned channel, + | input int unsigned vbank_id, + | input int unsigned group_id, + | input int unsigned addr, + | input longint unsigned data_lo, + | input longint unsigned data_hi + |); + | + |module MTraceDPI( + | input [7:0] is_write, + | input [31:0] channel, + | input [31:0] vbank_id, + | input [31:0] group_id, + | input [31:0] addr, + | input [63:0] data_lo, + | input [63:0] data_hi, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); + | end + | end + |endmodule + """.stripMargin + ) } class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) val group_id = Output(UInt(3.W)) } @@ -68,7 +71,7 @@ class MemBackend(val b: GlobalConfig) extends Module { val config = Flipped(Decoupled(new MemConfigerIO(b))) // Query interface for frontend to get group count - val query_vbank_id = Input(UInt(8.W)) + val query_vbank_id = Input(UInt(8.W)) val query_group_count = Output(UInt(4.W)) }) @@ -92,9 +95,9 @@ class MemBackend(val b: GlobalConfig) extends Module { // Mapping table // ----------------------------------------------------------------------------- class MappingTableEntry extends Bundle { - val valid = Bool() - val vbank_id = UInt(5.W) - val is_multi = Bool() + val valid = Bool() + val vbank_id = UInt(5.W) + val is_multi = Bool() val group_id = UInt(3.W) } @@ -104,15 +107,15 @@ class MemBackend(val b: GlobalConfig) extends Module { mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && entry.is_multi).reduce(_ || _) def addEntry( - vbank_id: UInt, - pbank_id: UInt, - is_multi: Bool, + vbank_id: UInt, + pbank_id: UInt, + is_multi: Bool, group_id: UInt ): Unit = { val entry = mappingTable(pbank_id) - entry.valid := true.B - entry.vbank_id := vbank_id - entry.is_multi := is_multi + entry.valid := true.B + entry.vbank_id := vbank_id + entry.is_multi := is_multi entry.group_id := group_id } @@ -139,7 +142,7 @@ class MemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read - accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id // Bank-side defaults (only driven when a bank is actually connected) @@ -186,9 +189,10 @@ class MemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- val groupCounts = mappingTable.map { entry => val matches = entry.valid && (entry.vbank_id === io.query_vbank_id) - val count = Mux(entry.is_multi, entry.group_id + 1.U, 1.U) + val count = Mux(entry.is_multi, entry.group_id + 1.U, 1.U) Mux(matches, count, 0.U) } + io.query_group_count := groupCounts.reduce((a, b) => Mux(a > b, a, b)) // ----------------------------------------------------------------------------- @@ -230,13 +234,6 @@ class MemBackend(val b: GlobalConfig) extends Module { val hold_one = RegNext(hit_bank && req_valid, init = false.B) - // Debug: print when write request comes in - when(io.mem_req(i).write.req.valid && i.U < 4.U) { - printf("[Backend] ch=%d write req: vbank_id=%d group_id=%d\n", i.U, io.mem_req(i).bank_id, io.mem_req(i).group_id) - printf("[Backend] pbank[%d]: valid=%d vbank=%d is_multi=%d group=%d hit=%d\n", - j.U, mappingTable(j).valid, mappingTable(j).vbank_id, mappingTable(j).is_multi, mappingTable(j).group_id, hit_bank) - } - when((hit_bank && req_valid) || hold_one) { banks(j).io.sramRead <> accPipes(i).io.sramRead banks(j).io.sramWrite <> accPipes(i).io.sramWrite diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index e0a1d485..be4b60ca 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -118,15 +118,6 @@ class MemStorer(val b: GlobalConfig) extends Module { when(state === s_issue_sram_req) { // Once request handshakes, wait for resp when(io.bankRead.io.req.fire) { - // Debug: print all reads - printf( - "[MemStorer] Issue: addr=%d group_id=%d bank_id=%d iter=%d group_count=%d\n", - addr_counter, - group_counter, - target_bank, - iter_reg, - group_count_reg - ) state := s_wait_sram_resp } } @@ -269,36 +260,22 @@ class MemStorer(val b: GlobalConfig) extends Module { val is_last_group = group_counter >= group_count_reg - 1.U val all_done = is_last_row && is_last_group && (iter_reg =/= 0.U) - // Debug - printf( - "[MemStorer] DMA fire: addr=%d group=%d is_last_row=%d is_last_group=%d all_done=%d\n", - addr_counter, - group_counter, - is_last_row, - is_last_group, - all_done - ) - // Advance counters when(iter_reg =/= 0.U) { when(group_counter + 1.U < group_count_reg) { // Move to next group in same row group_counter := group_counter + 1.U - printf("[MemStorer] Next group: new_group=%d\n", group_counter + 1.U) }.otherwise { // Move to next row, reset group counter group_counter := 0.U addr_counter := addr_counter + 1.U - printf("[MemStorer] Next row: new_addr=%d\n", addr_counter + 1.U) } } // Decide next state based on completion check done BEFORE counter update when(pendIsLast || iter_reg === 0.U || all_done) { - printf("[MemStorer] Going to DONE\n") state := s_done }.otherwise { - printf("[MemStorer] Going to issue next req\n") state := s_issue_sram_req } } diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index b7820d7a..e3fbbf8e 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -56,8 +56,8 @@ class MemMidend(val b: GlobalConfig) extends Module { def allocateChannel(): (Bool, UInt) = { val freeChannels = mappingTable.map(entry => !entry.valid) - val hasFreeChan = freeChannels.reduce(_ || _) - val chanId = PriorityEncoder(freeChannels) + val hasFreeChan = freeChannels.reduce(_ || _) + val chanId = PriorityEncoder(freeChannels) (hasFreeChan, chanId) } @@ -80,24 +80,11 @@ class MemMidend(val b: GlobalConfig) extends Module { // For ball writes, only allocate one request per cycle to avoid conflicts // Find the first unallocated request and allocate it - val pendingWrites = VecInit((0 until totalBallWrite).map(i => - io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U))) - val hasPendingWrite = pendingWrites.asUInt.orR + val pendingWrites = + VecInit((0 until totalBallWrite).map(i => io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U))) + val hasPendingWrite = pendingWrites.asUInt.orR val nextWriteToAllocate = PriorityEncoder(pendingWrites) - // Debug: print allocation decisions - when(hasPendingWrite) { - printf("[MemMidend] hasPending=1 nextToAlloc=%d pending=[", nextWriteToAllocate) - for (i <- 0 until totalBallWrite) { - printf("%d", pendingWrites(i)) - } - printf("] mappingTable=[") - for (i <- 0 until b.top.memBallChannelNum - 1) { - printf("ch%d:v=%d,r=%d,id=%d ", i.U, mappingTable(i).valid, mappingTable(i).isRead, mappingTable(i).id) - } - printf("]\n") - } - for (i <- 0 until totalBallWrite) { //Default values io.balldomain.bankWrite(i).io.req.ready := false.B @@ -109,9 +96,6 @@ class MemMidend(val b: GlobalConfig) extends Module { val (hasFree, chanId) = allocateChannel() when(hasFree) { addEntry(chanId, false.B, i.U) - printf("[MemMidend] Allocated ballWrite[%d] to ch=%d\n", i.U, chanId) - }.otherwise { - printf("[MemMidend] No free channel for ballWrite[%d]\n", i.U) } } } @@ -128,22 +112,22 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).bank_id := 0.U io.mem_req(i).group_id := 0.U - val isRead = mappingTable(i).isRead - val ballRead = io.balldomain.bankRead(mappingTable(i).id).io - val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io - val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id - val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id - val rgroup_id = io.balldomain.bankRead(mappingTable(i).id).group_id - val wgroup_id = io.balldomain.bankWrite(mappingTable(i).id).group_id + val isRead = mappingTable(i).isRead + val ballRead = io.balldomain.bankRead(mappingTable(i).id).io + val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io + val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id + val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id + val rgroup_id = io.balldomain.bankRead(mappingTable(i).id).group_id + val wgroup_id = io.balldomain.bankWrite(mappingTable(i).id).group_id when(mappingTable(i).valid) { when(isRead) { io.mem_req(i).read <> ballRead - io.mem_req(i).bank_id := rbank_id + io.mem_req(i).bank_id := rbank_id io.mem_req(i).group_id := rgroup_id }.otherwise { io.mem_req(i).write <> ballWrite - io.mem_req(i).bank_id := wbank_id + io.mem_req(i).bank_id := wbank_id io.mem_req(i).group_id := wgroup_id } } @@ -152,7 +136,7 @@ class MemMidend(val b: GlobalConfig) extends Module { //Connect frontend to backend io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io - io.mem_req(b.top.memBallChannelNum).bank_id := Mux( + io.mem_req(b.top.memBallChannelNum).bank_id := Mux( io.frontend.bankRead.io.req.valid, io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id diff --git a/arch/src/main/scala/sims/firesim/TargetConfigs.scala b/arch/src/main/scala/sims/firesim/TargetConfigs.scala index 7cc7bb8e..6ceeb7c3 100644 --- a/arch/src/main/scala/sims/firesim/TargetConfigs.scala +++ b/arch/src/main/scala/sims/firesim/TargetConfigs.scala @@ -14,7 +14,7 @@ class WithBootROM case BootROMLocated(x) => val chipyardBootROM = new File(s"./thirdparty/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img") - val firesimBootROM = new File( + val firesimBootROM = new File( s"./thirdparty/chipyard/target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img" ) diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index 44f87b09..c5087ac5 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -52,24 +52,25 @@ class TargetBall(ballType: BallType, b: GlobalConfig) extends Module with HasBli object BallTopMain extends App { // Select Ball type from command line arguments - val ballType = if (args.isEmpty) { - println("Usage: BallTopMain [firtool-opts...]") - println("Available ball types: vecball, matrixball, transposeball, im2colball, reluball, nnlutball") - println("Using default: vecball") - VecBallType - } else { - args(0).toLowerCase match { - case "vecball" => VecBallType - case "matrixball" => MatrixBallType - case "transposeball" => TransposeBallType - case "im2colball" => Im2colBallType - case "reluball" => ReluBallType - case "nnlutball" => NNLutBallType - case other => - println(s"Unknown ball type: $other, using vecball") - VecBallType + val ballType = + if (args.isEmpty) { + println("Usage: BallTopMain [firtool-opts...]") + println("Available ball types: vecball, matrixball, transposeball, im2colball, reluball, nnlutball") + println("Using default: vecball") + VecBallType + } else { + args(0).toLowerCase match { + case "vecball" => VecBallType + case "matrixball" => MatrixBallType + case "transposeball" => TransposeBallType + case "im2colball" => Im2colBallType + case "reluball" => ReluBallType + case "nnlutball" => NNLutBallType + case other => + println(s"Unknown ball type: $other, using vecball") + VecBallType + } } - } val b: GlobalConfig = GlobalConfig() diff --git a/scripts/nix/build-env-scala.nix b/scripts/nix/build-env-scala.nix index d7f7cd43..62fedc03 100644 --- a/scripts/nix/build-env-scala.nix +++ b/scripts/nix/build-env-scala.nix @@ -37,8 +37,14 @@ in }; }); - # Scala formatter - scalafmt = pkgs.scalafmt; + # Scala formatter - use coursier to get 2.7.5 + scalafmt = pkgs.writeShellApplication { + name = "scalafmt"; + runtimeInputs = [ pkgs.coursier ]; + text = '' + exec coursier launch org.scalameta:scalafmt-cli_2.13:2.7.5 -- "$@" + ''; + }; # Coursier - Scala dependency manager and launcher coursier = pkgs.coursier; From d44ebc21f0a0b3bfaa370b3270f34e82202afcb0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Mar 2026 00:27:10 +0800 Subject: [PATCH 126/238] [arch] chore: remove debug print statements from VecStoreUnit [ci] chore: streamline workflow scripts --- .github/workflows/pr.yml | 3 ++ .github/workflows/test.yml | 42 ++++++++--------- .../prototype/vector/VecStoreUnit.scala | 46 ------------------- 3 files changed, 23 insertions(+), 68 deletions(-) diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 7d2a6d71..43cdc095 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -24,6 +24,7 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball + setproxy git fetch origin git clean -fd git checkout ${{ github.head_ref }} @@ -32,12 +33,14 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball + setproxy nix build - name: Build Workloads shell: zsh {0} run: | cd ~/Code/buckyball + setproxy nix develop -c bbdev workload --build - name: Build Verilator diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 54932f56..d0e1a6a3 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -15,44 +15,42 @@ jobs: echo "🎉 The job was automatically triggered by a ${{ github.event_name }} event." echo "🔎 The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}." - - name: Pull from the repository + - name: Reset to clean state shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec - git fetch origin main + cd ~/Code/buckyball + setproxy git clean -fd git reset --hard ${{ github.sha }} + git checkout ${{ github.head_ref }} + + - name: Nix build + shell: zsh {0} + run: | + cd ~/Code/buckyball + setproxy + nix build - name: Build Workloads shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec - rm -rf workflow/.motia || true - bbdev workload --build + cd ~/Code/buckyball + setproxy + nix develop -c bbdev workload --build - name: Build Verilator shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec - rm -rf workflow/.motia || true - bbdev verilator --clean - rm -rf workflow/.motia || true - bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' - rm -rf workflow/.motia || true - bbdev verilator --build '--jobs 16' + cd ~/Code/buckyball + nix develop -c bbdev verilator --clean + nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' + nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test shell: zsh {0} run: | - source ~/.zshrc - buckyball_exec - rm -rf workflow/.motia || true - bbdev sardine --run '--workload ctest' - - - run: echo "🍏 CI Test is ${{ job.status }}." + cd ~/Code/buckyball + nix develop -c bbdev sardine --run '--workload ctest' # if check failed, revert the branch # - name: Revert Bad Commit diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 924ffb8f..5470bb46 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -69,13 +69,6 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { iter_counter := 0.U data_valid := false.B state := busy - - printf( - "[VecST_CTRL] Received ctrl: wr_bank=%d wr_bank_addr=%d iter=%d\n", - io.ctrl_st_i.bits.wr_bank, - io.ctrl_st_i.bits.wr_bank_addr, - io.ctrl_st_i.bits.iter - ) } // ----------------------------------------------------------------------------- @@ -84,31 +77,6 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { io.ex_st_i.ready := (state === busy || state === write) && !data_valid when(io.ex_st_i.fire) { - // Debug: print first 8 results with all 16 elements - when(iter_counter < 8.U) { - printf( - "[VecST] iter=%d rst[0-15]=%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d addr=%d\n", - iter_counter, - io.ex_st_i.bits.rst(0), - io.ex_st_i.bits.rst(1), - io.ex_st_i.bits.rst(2), - io.ex_st_i.bits.rst(3), - io.ex_st_i.bits.rst(4), - io.ex_st_i.bits.rst(5), - io.ex_st_i.bits.rst(6), - io.ex_st_i.bits.rst(7), - io.ex_st_i.bits.rst(8), - io.ex_st_i.bits.rst(9), - io.ex_st_i.bits.rst(10), - io.ex_st_i.bits.rst(11), - io.ex_st_i.bits.rst(12), - io.ex_st_i.bits.rst(13), - io.ex_st_i.bits.rst(14), - io.ex_st_i.bits.rst(15), - wr_bank_addr + iter_counter - ) - } - // Latch data data_valid := true.B data_addr := wr_bank_addr + iter_counter @@ -136,22 +104,11 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { when(state === write && data_valid) { val all_fired = channel_fired.reduce(_ && _) - printf("[VecST_WRITE] state=write data_valid=%d all_fired=%d iter_counter=%d\n", data_valid, all_fired, iter_counter) - for (i <- 0 until outBW) { val elementsPerChannel = InputNum / outBW val startIdx = i * elementsPerChannel val endIdx = startIdx + elementsPerChannel - 1 - // Debug: print each channel's status (always print, not just when !fired) - printf( - "[VecST_WRITE] ch[%d]: fired=%d valid=%d ready=%d\n", - i.U, - channel_fired(i), - io.bankWrite(i).req.valid, - io.bankWrite(i).req.ready - ) - // Only send request if this channel hasn't fired yet when(!channel_fired(i)) { io.bankWrite(i).req.valid := true.B @@ -168,7 +125,6 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { } when(all_fired) { - printf("[VecST_WRITE] All channels fired, advancing to next iter\n") data_valid := false.B iter_counter := iter_counter + 1.U @@ -179,10 +135,8 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { // Check if this is the last iter when(iter_counter + 1.U >= iter) { - printf("[VecST_WRITE] Last iter, going to wait_last\n") state := wait_last }.otherwise { - printf("[VecST_WRITE] Going back to busy\n") state := busy } } From 7f86483c68bef70c88aca82d269fbb82206ecd36 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Mar 2026 03:44:08 +0800 Subject: [PATCH 127/238] [arch] fix: correct address calculation in Transpose and VecLoadUnit to support 16xn --- .../prototype/transpose/Transpose.scala | 16 +++-- .../prototype/vector/VecStoreUnit.scala | 4 +- .../frontend/decoder/GobalDecoder.scala | 15 ----- .../frontend/globalrs/GlobalROB.scala | 53 ++------------- .../workloads/src/CTest/toy/CMakeLists.txt | 2 + .../src/CTest/toy/transpose_16xn_test.c | 67 +++++++++++++++++++ 6 files changed, 87 insertions(+), 70 deletions(-) create mode 100644 bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index c95565c2..2c6dd971 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -149,14 +149,18 @@ class Transpose(val b: GlobalConfig) extends Module { is(compute) { // --------------------------- // 1) READ REQ generation - // Only issue a read when: - // - still need reads (readReqCnt < iter_reg) - // - there is space in buffers (not both blocks full) - // - downstream ready handshake ok (via fire) + // For 16xN transpose: input matrix has N/16 addresses per row (stride). + // We read one 16x16 column-group per round using strided addresses: + // addr = row * stride + round + // where row = readReqCnt % InputNum, round = readReqCnt / InputNum // --------------------------- + val stride = iter_reg >> log2Ceil(InputNum) + val readRow = readReqCnt(log2Ceil(InputNum) - 1, 0) + val readRound = readReqCnt >> log2Ceil(InputNum) + val wantRead = (readReqCnt < iter_reg) && hasFreeBlock io.bankRead(0).io.req.valid := wantRead - io.bankRead(0).io.req.bits.addr := raddr_reg + readReqCnt + io.bankRead(0).io.req.bits.addr := raddr_reg + readRow * stride + readRound when(io.bankRead(0).io.req.fire) { readReqCnt := readReqCnt + 1.U @@ -223,7 +227,7 @@ class Transpose(val b: GlobalConfig) extends Module { val hasMoreWrite = (drainColIdx < InputNum.U) && (writeReqCnt < iter_reg) io.bankWrite(0).io.req.valid := hasMoreWrite - io.bankWrite(0).io.req.bits.addr := waddr_reg + writeReqCnt + io.bankWrite(0).io.req.bits.addr := waddr_reg + drainColIdx io.bankWrite(0).io.req.bits.data := packed io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index 5470bb46..ccc2c675 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -79,7 +79,9 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { when(io.ex_st_i.fire) { // Latch data data_valid := true.B - data_addr := wr_bank_addr + iter_counter + // Cycle through addresses 0-15: for 16xN matmul, MeshWarp outputs N results + // that need to be accumulated into 16 addresses via AccPipe's wmode + data_addr := wr_bank_addr + (iter_counter & 15.U) data_vec := io.ex_st_i.bits.rst state := write // Reset channel_fired when receiving new data diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index 12e7abd4..b4fe4d44 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -102,19 +102,4 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { io.id_o.bits.cmd := io.id_i.bits.cmd io.id_o.bits.bankAccess := bankAccess io.id_o.bits.isFence := is_frontend_inst - - // Debug: print bank access info for NPU instructions - when(io.id_o.fire && !is_frontend_inst && !is_gp_inst) { - printf( - "[GD] func7=%d rs1=0x%x rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - func7, - rs1, - bankAccess.rd_bank_0_valid, - bankAccess.rd_bank_0_id, - bankAccess.rd_bank_1_valid, - bankAccess.rd_bank_1_id, - bankAccess.wr_bank_valid, - bankAccess.wr_bank_id - ) - } } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 36a73aa2..65096cf0 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -136,19 +136,6 @@ class GlobalROB(val b: GlobalConfig) extends Module { // Update tail pointer and rob_id counter (circular) tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) - - printf( - "[ROB ALLOC] rob_id=%d domain=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - robIdCounter, - io.alloc.bits.domain_id, - io.alloc.bits.cmd.funct, - io.alloc.bits.bankAccess.rd_bank_0_valid, - io.alloc.bits.bankAccess.rd_bank_0_id, - io.alloc.bits.bankAccess.rd_bank_1_valid, - io.alloc.bits.bankAccess.rd_bank_1_id, - io.alloc.bits.bankAccess.wr_bank_valid, - io.alloc.bits.bankAccess.wr_bank_id - ) } // ============================================================================= @@ -179,13 +166,6 @@ class GlobalROB(val b: GlobalConfig) extends Module { itrace.io.rs1 := robEntries(completeId).cmd.cmd.rs1 itrace.io.rs2 := robEntries(completeId).cmd.cmd.rs2 itrace.io.enable := true.B - - printf( - "[ROB COMPLETE] rob_id=%d domain=%d func7=%d\n", - completeId, - robEntries(completeId).cmd.domain_id, - robEntries(completeId).cmd.cmd.funct - ) } // ============================================================================= @@ -218,20 +198,11 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.query := robEntries(actualIssuePtr).cmd.bankAccess val noHazard = !scoreboard.hasHazard - // Debug: print when a candidate is blocked by hazard - when(hasValid && scoreboard.hasHazard) { - printf( - "[ROB HAZARD] ptr=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - actualIssuePtr, - robEntries(actualIssuePtr).cmd.cmd.funct, - robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_valid, - robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_id, - robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_valid, - robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_id, - robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_valid, - robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_id - ) - } + /* when(hasValid && scoreboard.hasHazard) { printf( "[ROB HAZARD] ptr=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d + * wr=%d\n", actualIssuePtr, robEntries(actualIssuePtr).cmd.cmd.funct, + * robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_valid, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_id, + * robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_valid, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_id, + * robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_valid, robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_id ) } */ // Can only issue if issue limit is not reached and no bank hazard val canIssueMore = issuedCount < maxIssueLimit @@ -260,20 +231,6 @@ class GlobalROB(val b: GlobalConfig) extends Module { itrace.io.rs1 := robEntries(issuePtr).cmd.cmd.rs1 itrace.io.rs2 := robEntries(issuePtr).cmd.cmd.rs2 itrace.io.enable := true.B - - printf( - "[ROB ISSUE] rob_id=%d domain=%d func7=%d ptr=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d wr=%d\n", - robEntries(issuePtr).rob_id, - robEntries(issuePtr).cmd.domain_id, - robEntries(issuePtr).cmd.cmd.funct, - issuePtr, - robEntries(issuePtr).cmd.bankAccess.rd_bank_0_valid, - robEntries(issuePtr).cmd.bankAccess.rd_bank_0_id, - robEntries(issuePtr).cmd.bankAccess.rd_bank_1_valid, - robEntries(issuePtr).cmd.bankAccess.rd_bank_1_id, - robEntries(issuePtr).cmd.bankAccess.wr_bank_valid, - robEntries(issuePtr).cmd.bankAccess.wr_bank_id - ) } // ============================================================================= diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 662c5362..a774a1fd 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -112,6 +112,7 @@ add_cross_platform_test_target(ctest_vecunit_matmul_16xn_zero_random vecunit_mat add_cross_platform_test_target(ctest_vecunit_simple_nn_forward_pass_test vecunit_simple_nn_forward_pass_test.c) add_cross_platform_test_target(ctest_im2col_test im2col_test.c) add_cross_platform_test_target(ctest_transpose_test transpose_test.c) +add_cross_platform_test_target(ctest_transpose_16xn_test transpose_16xn_test.c) add_cross_platform_test_target(ctest_transpose_matmul transpose_matmul.c) add_cross_platform_test_target(ctest_relu_test relu_test.c) add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) @@ -136,6 +137,7 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_vecunit_simple_nn_forward_pass_test ctest_im2col_test ctest_transpose_test + ctest_transpose_16xn_test ctest_transpose_matmul ctest_relu_test ctest_vsetvli diff --git a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c new file mode 100644 index 00000000..a6e56ef1 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c @@ -0,0 +1,67 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t input_matrix[DIM * 64] __attribute__((aligned(64))); +static elem_t output_matrix[64 * DIM] __attribute__((aligned(64))); +static elem_t expected_matrix[64 * DIM] __attribute__((aligned(64))); + +void hw_transpose(elem_t *a, elem_t *b, int size) { + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); + bb_transpose(op1_bank_id, op2_bank_id, size, 0); + bb_mvout((uintptr_t)b, op2_bank_id, size, 1); + bb_fence(); +} + +int run_test(const char *test_name, int cols) { + int size = cols; // iter = number of rows in scratchpad = cols for 16xN + + // Initialize input: A[i][j] = i + j + init_sequence_matrix(input_matrix, DIM, cols); + + // Compute expected transpose on CPU + transpose_u8_matrix(input_matrix, expected_matrix, DIM, cols); + + // Run hardware transpose + hw_transpose(input_matrix, output_matrix, size); + + // Compare results + if (compare_u8_matrices(output_matrix, expected_matrix, cols, DIM)) { + printf("Test %s PASSED\n", test_name); + return 1; + } else { + printf("Test %s FAILED\n", test_name); + return 0; + } +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + int all_passed = 1; + + all_passed &= run_test("transpose_16x16", 16); + all_passed &= run_test("transpose_16x32", 32); + + if (all_passed) { + printf("All transpose_16xn tests PASSED\n"); + return 0; + } else { + printf("Some transpose_16xn tests FAILED\n"); + return 1; + } +#ifdef MULTICORE + exit(0); +#endif +} From 5d8c6100cecf03021528150c77f3e680d602b401 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Mar 2026 04:49:46 +0800 Subject: [PATCH 128/238] [arch] feat: Halving the registers files of Transpose --- .../prototype/transpose/Transpose.scala | 234 +++++++----------- bb-tests/sardine/tests/test_ctest.py | 8 +- 2 files changed, 87 insertions(+), 155 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index 2c6dd971..404d10d6 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -50,36 +50,33 @@ class Transpose(val b: GlobalConfig) extends Module { } // ------------------------------- - // State + // State: idle -> fill -> drain -> (fill or idle) + // For 16xN with stride = N/16: + // fill(16) -> drain(16) -> fill(16) -> drain(16) -> ... -> idle + // Total: 32 * stride cycles // ------------------------------- - val idle :: compute :: Nil = Enum(2) - val state = RegInit(idle) + val idle :: fill :: drain :: Nil = Enum(3) + val state = RegInit(idle) // ------------------------------- - // Ping-pong row buffers: - // 2 blocks, each stores InputNum rows, each row has InputNum elems + // Single 16x16 register array // ------------------------------- - val regArray = Reg(Vec(2 * InputNum, Vec(InputNum, UInt(inputWidth.W)))) + val regArray = Reg(Vec(InputNum, Vec(InputNum, UInt(inputWidth.W)))) - // which block are we filling / draining - val fillSel = RegInit(0.U(1.W)) // 0 or 1 - val drainSel = RegInit(0.U(1.W)) // 0 or 1 - val blockFull = RegInit(VecInit(Seq.fill(2)(false.B))) - val fillRowIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // 0..InputNum - val drainColIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // 0..InputNum - val draining = RegInit(false.B) - - // total progress counters (STRICTLY via fire) - val readReqCnt = RegInit(0.U(32.W)) - val readRespCnt = RegInit(0.U(32.W)) - val writeReqCnt = RegInit(0.U(32.W)) - - // command fields - val raddr_reg = RegInit(0.U(32.W)) - val waddr_reg = RegInit(0.U(32.W)) + // Command fields val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val iter_reg = RegInit(0.U(32.W)) + val stride = RegInit(1.U(32.W)) // iter / InputNum = addresses per row + + // Counters + val fillIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // row being filled (0..15) + val drainIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // column being drained (0..16) + val round = RegInit(0.U(32.W)) // which column-group (0..stride-1) + + // Read request tracking + val readReqCnt = RegInit(0.U(32.W)) + val readRespCnt = RegInit(0.U(32.W)) // ------------------------------- // Default IO assignments @@ -106,174 +103,109 @@ class Transpose(val b: GlobalConfig) extends Module { io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := rob_id_reg - // Always consume responses to avoid downstream backpressure deadlocks - io.bankRead(0).io.resp.ready := (state === compute) - io.bankWrite(0).io.resp.ready := (state === compute) + io.bankRead(0).io.resp.ready := (state =/= idle) + io.bankWrite(0).io.resp.ready := (state =/= idle) // ------------------------------- // Helpers // ------------------------------- - def blockBase(sel: UInt): UInt = Mux(sel === 0.U, 0.U, InputNum.U) - - // "space available" means at least one block is not full - val hasFreeBlock = !(blockFull(0) && blockFull(1)) + // Read address: strided to gather one column-group + // For round r, row i: addr = i * stride + r + def readAddr(row: UInt, r: UInt): UInt = row * stride + r + + // Pack one column of regArray into a data word + def packColumn(col: UInt): UInt = { + Cat((0 until InputNum).reverse.map { r => + regArray(r.U)(col) + }) + } // ------------------------------- // Main FSM // ------------------------------- switch(state) { is(idle) { - // reset runtime flags (not mandatory, but keeps things clean) when(io.cmdReq.fire) { - state := compute - - raddr_reg := 0.U - waddr_reg := 0.U - rbank_reg := io.cmdReq.bits.cmd.op1_bank - wbank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter - + val iterVal = io.cmdReq.bits.cmd.iter + val strideVal = iterVal >> log2Ceil(InputNum) + + rbank_reg := io.cmdReq.bits.cmd.op1_bank + wbank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := iterVal + stride := Mux(strideVal === 0.U, 1.U, strideVal) + round := 0.U + fillIdx := 0.U + drainIdx := 0.U readReqCnt := 0.U readRespCnt := 0.U - writeReqCnt := 0.U - - fillSel := 0.U - drainSel := 0.U - blockFull := VecInit(Seq.fill(2)(false.B)) - fillRowIdx := 0.U - draining := false.B - drainColIdx := 0.U + state := fill } } - is(compute) { - // --------------------------- - // 1) READ REQ generation - // For 16xN transpose: input matrix has N/16 addresses per row (stride). - // We read one 16x16 column-group per round using strided addresses: - // addr = row * stride + round - // where row = readReqCnt % InputNum, round = readReqCnt / InputNum - // --------------------------- - val stride = iter_reg >> log2Ceil(InputNum) - val readRow = readReqCnt(log2Ceil(InputNum) - 1, 0) - val readRound = readReqCnt >> log2Ceil(InputNum) - - val wantRead = (readReqCnt < iter_reg) && hasFreeBlock - io.bankRead(0).io.req.valid := wantRead - io.bankRead(0).io.req.bits.addr := raddr_reg + readRow * stride + readRound - + // ------------------------------------------------------- + // FILL: read 16 rows into regArray for current round + // ------------------------------------------------------- + is(fill) { + // Send read requests + io.bankRead(0).io.req.valid := (fillIdx < InputNum.U) + io.bankRead(0).io.req.bits.addr := readAddr(fillIdx, round) when(io.bankRead(0).io.req.fire) { readReqCnt := readReqCnt + 1.U + fillIdx := fillIdx + 1.U } - // --------------------------- - // 2) READ RESP handling (fill ping-pong block) - // Only advance fillRowIdx/blockFull on resp.fire - // --------------------------- + // Handle responses: fill regArray row by row when(io.bankRead(0).io.resp.fire) { val dataWord = io.bankRead(0).io.resp.bits.data - val base = blockBase(fillSel) - val rowIdx = base + fillRowIdx - + val respRow = readRespCnt(log2Ceil(InputNum) - 1, 0) for (col <- 0 until InputNum) { val hi = (col + 1) * inputWidth - 1 val lo = col * inputWidth - regArray(rowIdx)(col) := dataWord(hi, lo) + regArray(respRow)(col) := dataWord(hi, lo) } - readRespCnt := readRespCnt + 1.U - when(fillRowIdx === (InputNum - 1).U) { - // this block becomes full - blockFull(fillSel) := true.B - fillRowIdx := 0.U - - // switch to the other block if it is not full - when(!blockFull(~fillSel)) { - fillSel := ~fillSel - } - }.otherwise { - fillRowIdx := fillRowIdx + 1.U + // All 16 responses received → buffer full, go to drain + when(readRespCnt(log2Ceil(InputNum) - 1, 0) === (InputNum - 1).U) { + drainIdx := 0.U + state := drain } } + } - // --------------------------- - // 3) Start draining (writing) when not already draining - // --------------------------- - when(!draining) { - when(blockFull(drainSel) && (writeReqCnt < iter_reg)) { - draining := true.B - drainColIdx := 0.U - }.elsewhen(blockFull(~drainSel) && (writeReqCnt < iter_reg)) { - // if current drainSel block not full but the other is, swap - drainSel := ~drainSel - draining := true.B - drainColIdx := 0.U - } - } - - // --------------------------- - // 4) WRITE REQ generation (transpose) - // Only advance drainColIdx / writeReqCnt on req.fire - // --------------------------- - when(draining) { - val base = blockBase(drainSel) - - // compose one output row = one column of input block - val col = drainColIdx - val packed = Cat((0 until InputNum).reverse.map { r => - regArray(base + r.U)(col) - }) - - val hasMoreWrite = (drainColIdx < InputNum.U) && (writeReqCnt < iter_reg) - io.bankWrite(0).io.req.valid := hasMoreWrite - io.bankWrite(0).io.req.bits.addr := waddr_reg + drainColIdx - io.bankWrite(0).io.req.bits.data := packed + // ------------------------------------------------------- + // DRAIN: write out 16 transposed columns, then fill next + // round or signal completion + // ------------------------------------------------------- + is(drain) { + when(drainIdx < InputNum.U) { + io.bankWrite(0).io.req.valid := true.B + io.bankWrite(0).io.req.bits.addr := round * InputNum.U + drainIdx + io.bankWrite(0).io.req.bits.data := packColumn(drainIdx) io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) when(io.bankWrite(0).io.req.fire) { - writeReqCnt := writeReqCnt + 1.U - - when(drainColIdx === (InputNum - 1).U) { - // finished draining this block - draining := false.B - blockFull(drainSel) := false.B - drainSel := ~drainSel - - // move write base address by InputNum for next block’s outputs - waddr_reg := waddr_reg + InputNum.U - // move read base address too, purely optional; we already use readReqCnt for addr - // raddr_reg := raddr_reg + InputNum.U - }.otherwise { - drainColIdx := drainColIdx + 1.U + drainIdx := drainIdx + 1.U + } + }.otherwise { + // All 16 columns written + when(round === stride - 1.U) { + // Last round → signal completion + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + when(io.cmdResp.fire) { + state := idle } + }.otherwise { + // More rounds → advance round and fill next + round := round + 1.U + fillIdx := 0.U + state := fill } } - - // --------------------------- - // 5) Completion condition (NO early complete) - // Must ensure: - // - all read req issued - // - all read resp received - // - all write req issued - // - no blocks full, not draining - // --------------------------- - val done = - (readReqCnt === iter_reg) && - (readRespCnt === iter_reg) && - (writeReqCnt === iter_reg) && - !blockFull(0) && !blockFull(1) && - !draining - - io.cmdResp.valid := done - io.cmdResp.bits.rob_id := rob_id_reg - - when(done && io.cmdResp.fire) { - state := idle - } } } io.status.idle := (state === idle) - io.status.running := (state === compute) + io.status.running := (state =/= idle) } diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index e8190b49..d5020243 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -66,10 +66,6 @@ "ctest_vecunit_matmul_zero_random_singlecore-baremetal", "ctest_vecunit_matmul_zero_random_singlecore-baremetal", ), - ( - "ctest_vecunit_simple_nn_forward_pass_test_singlecore-baremetal", - "ctest_vecunit_simple_nn_forward_pass_test_singlecore-baremetal", - ), ( "ctest_relu_test_singlecore-baremetal", "ctest_relu_test_singlecore-baremetal", @@ -78,6 +74,10 @@ "ctest_transpose_test_singlecore-baremetal", "ctest_transpose_test_singlecore-baremetal", ), + ( + "ctest_transpose_16xn_test_singlecore-baremetal", + "ctest_transpose_16xn_test_singlecore-baremetal", + ), ( "ctest_im2col_test_singlecore-baremetal", "ctest_im2col_test_singlecore-baremetal", From e313caca6b9ae249d3a7c561cebaec1e5da95461 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 3 Mar 2026 06:29:16 +0800 Subject: [PATCH 129/238] [arch] fix: update VecLoadUnit and VecStoreUnit --- .github/workflows/pr.yml | 1 + .../prototype/vector/VecLoadUnit.scala | 18 +-- .../prototype/vector/VecStoreUnit.scala | 119 ++++++++---------- 3 files changed, 63 insertions(+), 75 deletions(-) diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 43cdc095..368d3394 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -28,6 +28,7 @@ jobs: git fetch origin git clean -fd git checkout ${{ github.head_ref }} + git pull - name: Nix build shell: zsh {0} diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index c0f082c5..439ccc80 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -129,23 +129,27 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // SRAM returns data and passes to EX unit // ----------------------------------------------------------------------------- - val deq_ready = bankRespQueue0.io.deq.valid && bankRespQueue1.io.deq.valid - bankRespQueue0.io.deq.ready := deq_ready - bankRespQueue1.io.deq.ready := deq_ready + val both_valid = bankRespQueue0.io.deq.valid && bankRespQueue1.io.deq.valid - when(deq_ready) { - io.ld_ex_o.valid := true.B + io.ld_ex_o.valid := both_valid + when(both_valid) { io.ld_ex_o.bits.op1 := bankRespQueue0.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) io.ld_ex_o.bits.op2 := bankRespQueue1.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) - ld_ex_iter_reg := ld_ex_iter_reg + 1.U io.ld_ex_o.bits.iter := ld_ex_iter_reg }.otherwise { - io.ld_ex_o.valid := false.B io.ld_ex_o.bits.iter := 0.U io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) } + // Only dequeue and advance iter counter on successful handshake + bankRespQueue0.io.deq.ready := io.ld_ex_o.fire + bankRespQueue1.io.deq.ready := io.ld_ex_o.fire + + when(io.ld_ex_o.fire) { + ld_ex_iter_reg := ld_ex_iter_reg + 1.U + } + // ----------------------------------------------------------------------------- // Reset op1_iter_counter and return to idle state // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index ccc2c675..d70947cf 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -22,6 +22,13 @@ class ex_st_req(b: GlobalConfig) extends Bundle { val iter = UInt(10.W) } +class BankWriteEntry(b: GlobalConfig) extends Bundle { + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val data = UInt(b.memDomain.bankWidth.W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val wmode = Bool() +} + @instantiable class VecStoreUnit(val b: GlobalConfig) extends Module { val config = VectorBallParam() @@ -42,20 +49,14 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { val cmdResp_o = Valid(new Bundle { val commit = Bool() }) }) - val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) - val idle :: busy :: write :: wait_last :: Nil = Enum(4) - val state = RegInit(idle) - - // Register to hold data from EX unit - val data_valid = RegInit(false.B) - val data_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val data_vec = Reg(Vec(InputNum, UInt(accWidth.W))) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) - // Track which channels have fired - val channel_fired = RegInit(VecInit(Seq.fill(outBW)(false.B))) + val writeQueues = VecInit(Seq.fill(outBW)(Module(new Queue(new BankWriteEntry(b), 16)).io)) // ----------------------------------------------------------------------------- // Set registers when Ctrl instruction arrives @@ -67,80 +68,59 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) iter_counter := 0.U - data_valid := false.B state := busy } // ----------------------------------------------------------------------------- -// Accept computation results from EX unit +// Accept computation results from EX unit and push to write queues // ----------------------------------------------------------------------------- - io.ex_st_i.ready := (state === busy || state === write) && !data_valid + io.ex_st_i.ready := state === busy && writeQueues.forall(_.enq.ready) + + for (i <- 0 until outBW) { + writeQueues(i).enq.valid := false.B + writeQueues(i).enq.bits := DontCare + } when(io.ex_st_i.fire) { - // Latch data - data_valid := true.B - // Cycle through addresses 0-15: for 16xN matmul, MeshWarp outputs N results - // that need to be accumulated into 16 addresses via AccPipe's wmode - data_addr := wr_bank_addr + (iter_counter & 15.U) - data_vec := io.ex_st_i.bits.rst - state := write - // Reset channel_fired when receiving new data for (i <- 0 until outBW) { - channel_fired(i) := false.B + val elementsPerChannel = InputNum / outBW + val startIdx = i * elementsPerChannel + val endIdx = startIdx + elementsPerChannel - 1 + + val entry = Wire(new BankWriteEntry(b)) + entry.addr := wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + entry.data := Cat(io.ex_st_i.bits.rst.slice(startIdx, endIdx + 1).reverse) + entry.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + entry.wmode := true.B + + writeQueues(i).enq.valid := true.B + writeQueues(i).enq.bits := entry } + iter_counter := iter_counter + 1.U } // ----------------------------------------------------------------------------- -// Write data to banks +// Drain write queues to bankWrite interface // ----------------------------------------------------------------------------- - // Default values for bankWrite io.bankWrite.foreach { acc => acc.req.valid := false.B acc.req.bits.addr := 0.U - acc.req.bits.data := 0.U + acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) acc.req.bits.wmode := false.B - acc.resp.ready := true.B + acc.resp.ready := false.B } - when(state === write && data_valid) { - val all_fired = channel_fired.reduce(_ && _) + for (i <- 0 until outBW) { + writeQueues(i).deq.ready := false.B - for (i <- 0 until outBW) { - val elementsPerChannel = InputNum / outBW - val startIdx = i * elementsPerChannel - val endIdx = startIdx + elementsPerChannel - 1 - - // Only send request if this channel hasn't fired yet - when(!channel_fired(i)) { - io.bankWrite(i).req.valid := true.B - io.bankWrite(i).req.bits.addr := data_addr - io.bankWrite(i).req.bits.data := Cat(data_vec.slice(startIdx, endIdx + 1).reverse) - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - io.bankWrite(i).req.bits.wmode := true.B // Accumulator mode - - // Mark as fired when handshake completes - when(io.bankWrite(i).req.ready) { - channel_fired(i) := true.B - } - } - } - - when(all_fired) { - data_valid := false.B - iter_counter := iter_counter + 1.U - - // Reset channel_fired for next iter - for (i <- 0 until outBW) { - channel_fired(i) := false.B - } - - // Check if this is the last iter - when(iter_counter + 1.U >= iter) { - state := wait_last - }.otherwise { - state := busy - } + when(writeQueues(i).deq.valid) { + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := writeQueues(i).deq.bits.addr + io.bankWrite(i).req.bits.data := writeQueues(i).deq.bits.data + io.bankWrite(i).req.bits.mask := writeQueues(i).deq.bits.mask + io.bankWrite(i).req.bits.wmode := writeQueues(i).deq.bits.wmode + writeQueues(i).deq.ready := io.bankWrite(i).req.ready } } @@ -148,9 +128,12 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { io.wr_bank_o := wr_bank // ----------------------------------------------------------------------------- -// Wait one cycle for last write to complete, then return to idle +// Reset iter counter, commit cmdResp, return to idle state // ----------------------------------------------------------------------------- - when(state === wait_last) { + val allQueuesEmpty = writeQueues.forall(q => !q.deq.valid) + val allDataEnqueued = state === busy && iter_counter >= iter + + when(allDataEnqueued && allQueuesEmpty) { state := idle io.cmdResp_o.valid := true.B io.cmdResp_o.bits.commit := true.B From b419d279a7d88fc1538ea97377251d36eafd54ba Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 4 Mar 2026 08:42:57 +0800 Subject: [PATCH 130/238] [docs] feat: add new documentation submodule and remove outdated files --- .github/workflows/doc.yml | 62 - .gitmodules | 3 + README.md | 2 +- docs | 1 + docs/.gitignore | 2 - docs/bb-note/book.toml | 20 - docs/bb-note/mermaid-init.js | 39 - docs/bb-note/mermaid.min.js | 2609 ----------------- docs/bb-note/src/README.md | 1 - docs/bb-note/src/SUMMARY.md | 43 - docs/bb-note/src/arch/arch.md | 68 - .../bb-note/src/arch/src/main/scala/README.md | 1 - .../src/arch/src/main/scala/Util/README.md | 1 - .../arch/src/main/scala/examples/README.md | 1 - .../src/main/scala/examples/toy/README.md | 1 - .../scala/examples/toy/balldomain/README.md | 1 - .../examples/toy/balldomain/bbus/README.md | 1 - .../examples/toy/balldomain/rs/README.md | 1 - .../arch/src/main/scala/framework/README.md | 1 - .../main/scala/framework/builtin/README.md | 1 - .../main/scala/framework/builtin/builtin.md | 1 - .../scala/framework/builtin/util/README.md | 1 - .../src/main/scala/framework/framework.md | 1 - .../arch/src/main/scala/prototype/README.md | 1 - .../src/main/scala/prototype/format/README.md | 1 - .../src/main/scala/prototype/im2col/README.md | 1 - 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-on: - # Runs on pushes targeting the default branch - push: - branches: ["main"] - - # Allows you to run this workflow manually from the Actions tab - workflow_dispatch: - -# Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages -permissions: - contents: read - pages: write - id-token: write - -# Allow only one concurrent deployment, skipping runs queued between the run in-progress and latest queued. -# However, do NOT cancel in-progress runs as we want to allow these production deployments to complete. -concurrency: - group: "pages" - cancel-in-progress: false - -jobs: - # Build job - build: - runs-on: ubuntu-latest - env: - MDBOOK_VERSION: 0.4.52 - steps: - - uses: actions/checkout@v4 - - name: Install mdBook - run: | - curl --proto '=https' --tlsv1.2 https://sh.rustup.rs -sSf -y | sh - rustup update - cargo install --version ${MDBOOK_VERSION} mdbook - cargo install mdbook-linkcheck - cargo install mdbook-pandoc - - name: Setup Pages - id: pages - uses: actions/configure-pages@v4 - - name: Build with mdBook - run: cd docs/bb-note && mdbook build - - name: Upload artifact - uses: actions/upload-pages-artifact@v3 - with: - path: ./docs/bb-note/book - - # Deployment job - deploy: - environment: - name: github-pages - url: ${{ steps.deployment.outputs.page_url }} - runs-on: ubuntu-latest - needs: build - steps: - - name: Deploy to GitHub Pages - id: deployment - uses: actions/deploy-pages@v4 diff --git a/.gitmodules b/.gitmodules index d93de6ca..a7a22d3d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -19,3 +19,6 @@ [submodule "thirdparty/palladium"] path = thirdparty/palladium url = https://github.com/SEU-ACAL/awesome-palladium.git +[submodule "docs"] + path = docs + url = https://github.com/DangoSys/documents.git diff --git a/README.md b/README.md index 5d500ba3..ec2e7879 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@

    - +

    @@ -61,7 +61,7 @@ bbdev verilator --run '--jobs 16 --binary ctest_vecunit_matmul_ones_singlecore-b ## Tutorial -You can start to learn ball and blink from [here](https://github.com/DangoSys/buckyball/blob/main/docs/bb-note/src/tutorial/tutorial.md) +You can start to learn ball and blink from [here](https://github.com/DangoSys/documents/blob/main/content/en/Tutorial/Building%20Your%20Own%20Hardware%20Designs.md) ## Additional Resources From 9f274c53bf6fd8168caf9af92e90fe9664ac2d6c Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Thu, 5 Mar 2026 15:03:53 +0800 Subject: [PATCH 133/238] [arch]add:build shared mem framework --- .../memdomain/backend/shared/SharedMem.scala | 95 +++++++++++++++++++ .../memdomain/configs/MemDomainParam.scala | 3 + .../framework/memdomain/configs/default.json | 5 +- 3 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala new file mode 100644 index 00000000..988257f8 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -0,0 +1,95 @@ +package framework.memdomain.backend.shared + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.memdomain.backend.banks.{SramReadResp, SramWriteResp} + +class SharedMemReadReq(val b: GlobalConfig) extends Bundle { + val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val group_id = UInt(3.W) + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) +} + +class SharedMemWriteReq(val b: GlobalConfig) extends Bundle { + val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val group_id = UInt(3.W) + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val data = UInt(b.memDomain.bankWidth.W) + val wmode = Bool() +} + +class SharedMemReadIO(val b: GlobalConfig) extends Bundle { + val req = Flipped(Decoupled(new SharedMemReadReq(b))) + val resp = Decoupled(new SramReadResp(b)) +} + +class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { + val req = Flipped(Decoupled(new SharedMemWriteReq(b))) + val resp = Decoupled(new SramWriteResp(b)) +} + +@instantiable +class SharedMem(val b: GlobalConfig) extends Module { + private val maxGroup = 8 + private val mask_len = b.memDomain.bankMaskLen + private val mask_elem = UInt((b.memDomain.bankWidth / mask_len).W) + private val minSharedLines = b.memDomain.bankNum * maxGroup * b.memDomain.bankEntries + + require( + b.memDomain.sharedEntries >= minSharedLines, + s"sharedEntries=${b.memDomain.sharedEntries} is too small, minimum=$minSharedLines" + ) + + @public + val io = IO(new Bundle { + val read = new SharedMemReadIO(b) + val write = new SharedMemWriteIO(b) + }) + + val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(mask_len, mask_elem)) + + // Shared memory address mapping: + // shared_addr = ((vbank_id * MAX_GROUP + group_id) * bankEntries) + local_addr + private def toSharedAddr(vbank_id: UInt, group_id: UInt, local_addr: UInt): UInt = { + val vbankPart = vbank_id * (maxGroup * b.memDomain.bankEntries).U + val groupPart = group_id * b.memDomain.bankEntries.U + vbankPart + groupPart + local_addr + } + + io.read.req.ready := !io.write.req.valid + io.write.req.ready := !io.read.req.valid + + val readReqFire = io.read.req.fire + val readAddr = toSharedAddr(io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) + + when(readReqFire) { + assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.read.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") + assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + } + + val readData = mem.read(readAddr, readReqFire) + + io.read.resp.valid := RegNext(readReqFire, init = false.B) + io.read.resp.bits.data := readData.asUInt + + val writeReqFire = io.write.req.fire + val writeAddr = toSharedAddr(io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) + + when(writeReqFire) { + assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.write.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") + assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + mem.write( + writeAddr, + io.write.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), + io.write.req.bits.mask + ) + } + + io.write.resp.valid := RegNext(writeReqFire, init = false.B) + io.write.resp.bits.ok := RegNext(writeReqFire, init = false.B) +} \ No newline at end of file diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala index c2872f7a..1a35e748 100644 --- a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -10,6 +10,9 @@ case class MemDomainParam( bankWidth: Int, bankEntries: Int, bankMaskLen: Int, + sharedEnable: Boolean, + sharedEntries: Int, + sharedDefaultGroupCount: Int, tlb_size: Int, dma_n_xacts: Int, dma_maxbytes: Int, diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index de38e5ec..d0cf78f8 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -3,6 +3,9 @@ "bankWidth": 128, "bankEntries": 128, "bankMaskLen": 16, + "sharedEnable": true, + "sharedEntries": 32768, + "sharedDefaultGroupCount": 1, "tlb_size": 4, "dma_n_xacts": 8, "dma_maxbytes": 64, @@ -13,4 +16,4 @@ "balldomainChannel": 6, "tmaReadChannel": 4, "tmaWriteChannel": 4 -} +} \ No newline at end of file From e006ad2eb9e00aaefdfc41ea2d4ebfc9209b4f1a Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Thu, 5 Mar 2026 17:42:29 +0800 Subject: [PATCH 134/238] [arch]refactor:rebuild the framework of backend --- .../memdomain/backend/MemBackend.scala | 231 +---------------- .../memdomain/backend/MemBackendTypes.scala | 13 + .../privatepath/PrivateMemBackend.scala | 234 ++++++++++++++++++ .../backend/shared/SharedMemBackend.scala | 212 ++++++++++++++++ 4 files changed, 469 insertions(+), 221 deletions(-) create mode 100644 arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala create mode 100644 arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index b6f0ae18..0a30909c 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -1,66 +1,11 @@ package framework.memdomain.backend import chisel3._ -import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.util._ import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig -import framework.memdomain.backend.banks.{SramBank, SramReadIO, SramWriteIO} -import framework.memdomain.backend.accpipe.AccPipe - -// DPI-C BlackBox for memory trace -class MTraceDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val is_write = Input(UInt(8.W)) - val channel = Input(UInt(32.W)) - val vbank_id = Input(UInt(32.W)) - val group_id = Input(UInt(32.W)) - val addr = Input(UInt(32.W)) - val data_lo = Input(UInt(64.W)) - val data_hi = Input(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "MTraceDPI.v", - """ - |import "DPI-C" function void dpi_mtrace( - | input byte unsigned is_write, - | input int unsigned channel, - | input int unsigned vbank_id, - | input int unsigned group_id, - | input int unsigned addr, - | input longint unsigned data_lo, - | input longint unsigned data_hi - |); - | - |module MTraceDPI( - | input [7:0] is_write, - | input [31:0] channel, - | input [31:0] vbank_id, - | input [31:0] group_id, - | input [31:0] addr, - | input [63:0] data_lo, - | input [63:0] data_hi, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); - | end - | end - |endmodule - """.stripMargin - ) -} - -class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val group_id = Output(UInt(3.W)) -} +import framework.memdomain.backend.privatepath.PrivateMemBackend @instantiable class MemBackend(val b: GlobalConfig) extends Module { @@ -75,170 +20,14 @@ class MemBackend(val b: GlobalConfig) extends Module { val query_group_count = Output(UInt(4.W)) }) - val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) - - // Per-channel memory trace DPI-C modules to avoid losing simultaneous events - val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) - for (mt <- mtraces) { - mt.io.is_write := 0.U - mt.io.channel := 0.U - mt.io.vbank_id := 0.U - mt.io.group_id := 0.U - mt.io.addr := 0.U - mt.io.data_lo := 0.U - mt.io.data_hi := 0.U - mt.io.enable := false.B - } - - // ----------------------------------------------------------------------------- - // Mapping table - // ----------------------------------------------------------------------------- - class MappingTableEntry extends Bundle { - val valid = Bool() - val vbank_id = UInt(5.W) - val is_multi = Bool() - val group_id = UInt(3.W) - } - - val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) - - def isAcc(vbank_id: UInt): Bool = - mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && entry.is_multi).reduce(_ || _) - - def addEntry( - vbank_id: UInt, - pbank_id: UInt, - is_multi: Bool, - group_id: UInt - ): Unit = { - val entry = mappingTable(pbank_id) - entry.valid := true.B - entry.vbank_id := vbank_id - entry.is_multi := is_multi - entry.group_id := group_id - } - - def deleteEntry(vbank_id: UInt): Unit = { - for (i <- 0 until b.memDomain.bankNum) { - when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id) { - mappingTable(i).valid := false.B - mappingTable(i).vbank_id := 0.U - mappingTable(i).is_multi := false.B - mappingTable(i).group_id := 0.U - } - } - } - - def getFreePbankId(): UInt = { - val freePbankId = mappingTable.indexWhere(_.valid === false.B) - freePbankId - } - - // ----------------------------------------------------------------------------- - // Default Value - // ----------------------------------------------------------------------------- - - for (i <- 0 until b.memDomain.bankChannel) { - accPipes(i).io.mem_req.write <> io.mem_req(i).write - accPipes(i).io.mem_req.read <> io.mem_req(i).read - accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id - accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id - - // Bank-side defaults (only driven when a bank is actually connected) - accPipes(i).io.sramRead.req.ready := false.B - accPipes(i).io.sramRead.resp.valid := false.B - accPipes(i).io.sramRead.resp.bits := DontCare - - accPipes(i).io.sramWrite.req.ready := false.B - accPipes(i).io.sramWrite.resp.valid := false.B - accPipes(i).io.sramWrite.resp.bits := DontCare - - accPipes(i).io.is_multi := isAcc(io.mem_req(i).bank_id) - } - - io.config.ready := true.B - - banks.zipWithIndex.foreach { - case (bank, i) => - bank.io.sramRead.req.valid := false.B - bank.io.sramRead.req.bits := DontCare - bank.io.sramRead.resp.ready := true.B - - bank.io.sramWrite.req.valid := false.B - bank.io.sramWrite.req.bits := DontCare - bank.io.sramWrite.resp.ready := true.B - - } - - // ----------------------------------------------------------------------------- - // Bank Alloc/Release - // ----------------------------------------------------------------------------- - - when(io.config.valid) { - when(io.config.bits.alloc) { - val pbank_id = getFreePbankId() - addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) - }.otherwise { - deleteEntry(io.config.bits.vbank_id) - } - } - - // ----------------------------------------------------------------------------- - // Query interface: return group count for a given vbank_id - // ----------------------------------------------------------------------------- - val groupCounts = mappingTable.map { entry => - val matches = entry.valid && (entry.vbank_id === io.query_vbank_id) - val count = Mux(entry.is_multi, entry.group_id + 1.U, 1.U) - Mux(matches, count, 0.U) - } - - io.query_group_count := groupCounts.reduce((a, b) => Mux(a > b, a, b)) - - // ----------------------------------------------------------------------------- - // Connect AccPipe and Banks - // ----------------------------------------------------------------------------- - for (i <- 0 until b.memDomain.bankChannel) { - val hasReq = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid - - // Memory trace: read request - when(io.mem_req(i).read.req.fire) { - mtraces(i).io.is_write := 0.U - mtraces(i).io.channel := i.U - mtraces(i).io.vbank_id := io.mem_req(i).bank_id - mtraces(i).io.group_id := io.mem_req(i).group_id - mtraces(i).io.addr := io.mem_req(i).read.req.bits.addr - mtraces(i).io.data_lo := 0.U - mtraces(i).io.data_hi := 0.U - mtraces(i).io.enable := true.B - } - - // Memory trace: write request - when(io.mem_req(i).write.req.fire) { - mtraces(i).io.is_write := 1.U - mtraces(i).io.channel := i.U - mtraces(i).io.vbank_id := io.mem_req(i).bank_id - mtraces(i).io.group_id := io.mem_req(i).group_id - mtraces(i).io.addr := io.mem_req(i).write.req.bits.addr - mtraces(i).io.data_lo := io.mem_req(i).write.req.bits.data(63, 0) - mtraces(i).io.data_hi := io.mem_req(i).write.req.bits.data(127, 64) - mtraces(i).io.enable := true.B - } - - for (j <- 0 until b.memDomain.bankNum) { - - val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid - val hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && - (!mappingTable(j).is_multi || - (mappingTable(j).is_multi && (mappingTable(j).group_id === io.mem_req(i).group_id))) - - val hold_one = RegNext(hit_bank && req_valid, init = false.B) + // Keep the private backend datapath unchanged and isolate it in a dedicated module. + val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) - when((hit_bank && req_valid) || hold_one) { - banks(j).io.sramRead <> accPipes(i).io.sramRead - banks(j).io.sramWrite <> accPipes(i).io.sramWrite - } - } - } + privateBackend.io.mem_req <> io.mem_req + privateBackend.io.config <> io.config + privateBackend.io.query_vbank_id := io.query_vbank_id + io.query_group_count := privateBackend.io.query_group_count + // Shared backend is intentionally not connected at top-level in this refactor + // to avoid private-path regressions. It can be integrated in a later step. } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala new file mode 100644 index 00000000..a8213954 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala @@ -0,0 +1,13 @@ +package framework.memdomain.backend + +import chisel3._ +import chisel3.util._ +import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} +import framework.top.GlobalConfig + +class MemRequestIO(b: GlobalConfig) extends Bundle { + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val group_id = Output(UInt(3.W)) +} diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala new file mode 100644 index 00000000..d92d4a82 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -0,0 +1,234 @@ +package framework.memdomain.backend.privatepath + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.memdomain.frontend.outside_channel.MemConfigerIO +import framework.memdomain.backend.MemRequestIO +import framework.memdomain.backend.accpipe.AccPipe +import framework.memdomain.backend.banks.SramBank +import framework.top.GlobalConfig + +// DPI-C BlackBox for memory trace +class MTraceDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val is_write = Input(UInt(8.W)) + val channel = Input(UInt(32.W)) + val vbank_id = Input(UInt(32.W)) + val group_id = Input(UInt(32.W)) + val addr = Input(UInt(32.W)) + val data_lo = Input(UInt(64.W)) + val data_hi = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "MTraceDPI.v", + """ + |import "DPI-C" function void dpi_mtrace( + | input byte unsigned is_write, + | input int unsigned channel, + | input int unsigned vbank_id, + | input int unsigned group_id, + | input int unsigned addr, + | input longint unsigned data_lo, + | input longint unsigned data_hi + |); + | + |module MTraceDPI( + | input [7:0] is_write, + | input [31:0] channel, + | input [31:0] vbank_id, + | input [31:0] group_id, + | input [31:0] addr, + | input [63:0] data_lo, + | input [63:0] data_hi, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); + | end + | end + |endmodule + """.stripMargin + ) +} + +@instantiable +class PrivateMemBackend(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val config = Flipped(Decoupled(new MemConfigerIO(b))) + + // Query interface for frontend to get group count + val query_vbank_id = Input(UInt(8.W)) + val query_group_count = Output(UInt(4.W)) + }) + + val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + + // Per-channel memory trace DPI-C modules to avoid losing simultaneous events + val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) + for (mt <- mtraces) { + mt.io.is_write := 0.U + mt.io.channel := 0.U + mt.io.vbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B + } + + // ----------------------------------------------------------------------------- + // Mapping table + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + val valid = Bool() + val vbank_id = UInt(5.W) + val is_multi = Bool() + val group_id = UInt(3.W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) + + def isAcc(vbank_id: UInt): Bool = + mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && entry.is_multi).reduce(_ || _) + + def addEntry( + vbank_id: UInt, + pbank_id: UInt, + is_multi: Bool, + group_id: UInt + ): Unit = { + val entry = mappingTable(pbank_id) + entry.valid := true.B + entry.vbank_id := vbank_id + entry.is_multi := is_multi + entry.group_id := group_id + } + + def deleteEntry(vbank_id: UInt): Unit = { + for (i <- 0 until b.memDomain.bankNum) { + when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id) { + mappingTable(i).valid := false.B + mappingTable(i).vbank_id := 0.U + mappingTable(i).is_multi := false.B + mappingTable(i).group_id := 0.U + } + } + } + + def getFreePbankId(): UInt = { + val freePbankId = mappingTable.indexWhere(_.valid === false.B) + freePbankId + } + + // ----------------------------------------------------------------------------- + // Default Value + // ----------------------------------------------------------------------------- + + for (i <- 0 until b.memDomain.bankChannel) { + accPipes(i).io.mem_req.write <> io.mem_req(i).write + accPipes(i).io.mem_req.read <> io.mem_req(i).read + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + + // Bank-side defaults (only driven when a bank is actually connected) + accPipes(i).io.sramRead.req.ready := false.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare + + accPipes(i).io.sramWrite.req.ready := false.B + accPipes(i).io.sramWrite.resp.valid := false.B + accPipes(i).io.sramWrite.resp.bits := DontCare + + accPipes(i).io.is_multi := isAcc(io.mem_req(i).bank_id) + } + + io.config.ready := true.B + + banks.zipWithIndex.foreach { + case (bank, _) => + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := DontCare + bank.io.sramRead.resp.ready := true.B + + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := DontCare + bank.io.sramWrite.resp.ready := true.B + } + + // ----------------------------------------------------------------------------- + // Bank Alloc/Release + // ----------------------------------------------------------------------------- + + when(io.config.valid) { + when(io.config.bits.alloc) { + val pbank_id = getFreePbankId() + addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) + }.otherwise { + deleteEntry(io.config.bits.vbank_id) + } + } + + // ----------------------------------------------------------------------------- + // Query interface: return group count for a given vbank_id + // ----------------------------------------------------------------------------- + val groupCounts = mappingTable.map { entry => + val matches = entry.valid && (entry.vbank_id === io.query_vbank_id) + val count = Mux(entry.is_multi, entry.group_id + 1.U, 1.U) + Mux(matches, count, 0.U) + } + + io.query_group_count := groupCounts.reduce((a, b) => Mux(a > b, a, b)) + + // ----------------------------------------------------------------------------- + // Connect AccPipe and Banks + // ----------------------------------------------------------------------------- + for (i <- 0 until b.memDomain.bankChannel) { + val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + + // Memory trace: read request + when(io.mem_req(i).read.req.fire) { + mtraces(i).io.is_write := 0.U + mtraces(i).io.channel := i.U + mtraces(i).io.vbank_id := io.mem_req(i).bank_id + mtraces(i).io.group_id := io.mem_req(i).group_id + mtraces(i).io.addr := io.mem_req(i).read.req.bits.addr + mtraces(i).io.data_lo := 0.U + mtraces(i).io.data_hi := 0.U + mtraces(i).io.enable := true.B + } + + // Memory trace: write request + when(io.mem_req(i).write.req.fire) { + mtraces(i).io.is_write := 1.U + mtraces(i).io.channel := i.U + mtraces(i).io.vbank_id := io.mem_req(i).bank_id + mtraces(i).io.group_id := io.mem_req(i).group_id + mtraces(i).io.addr := io.mem_req(i).write.req.bits.addr + mtraces(i).io.data_lo := io.mem_req(i).write.req.bits.data(63, 0) + mtraces(i).io.data_hi := io.mem_req(i).write.req.bits.data(127, 64) + mtraces(i).io.enable := true.B + } + + for (j <- 0 until b.memDomain.bankNum) { + val hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + (!mappingTable(j).is_multi || + (mappingTable(j).is_multi && (mappingTable(j).group_id === io.mem_req(i).group_id))) + + val hold_one = RegNext(hit_bank && req_valid, init = false.B) + + when((hit_bank && req_valid) || hold_one) { + banks(j).io.sramRead <> accPipes(i).io.sramRead + banks(j).io.sramWrite <> accPipes(i).io.sramWrite + } + } + } +} diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala new file mode 100644 index 00000000..ca1c195f --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -0,0 +1,212 @@ +package framework.memdomain.backend.shared + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.memdomain.backend.MemRequestIO +import framework.memdomain.backend.accpipe.AccPipe +import framework.memdomain.frontend.outside_channel.MemConfigerIO +import framework.top.GlobalConfig + +class SharedArbReq(b: GlobalConfig) extends Bundle { + val src_channel = UInt(log2Up(b.memDomain.bankChannel).W) + val is_write = Bool() + val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val group_id = UInt(3.W) + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val data = UInt(b.memDomain.bankWidth.W) + val wmode = Bool() +} + +@instantiable +class SharedMemBackend(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val config = Flipped(Decoupled(new MemConfigerIO(b))) + + // Query interface for frontend to get group count + val query_vbank_id = Input(UInt(8.W)) + val query_group_count = Output(UInt(4.W)) + }) + + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) + + // Keep per-vbank logical group count so shared path can expose the same + // query semantics expected by loader/storer loops. + val sharedGroupCountTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U(4.W)))) + + io.config.ready := true.B + + when(io.config.valid) { + val cfgVbankIdx = io.config.bits.vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) + when(io.config.bits.alloc) { + val nextCount = Mux(io.config.bits.is_multi, io.config.bits.group_id + 1.U, 1.U) + when(nextCount > sharedGroupCountTable(cfgVbankIdx)) { + sharedGroupCountTable(cfgVbankIdx) := nextCount + } + }.otherwise { + sharedGroupCountTable(cfgVbankIdx) := 0.U + } + } + + val queryVbankIdx = io.query_vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) + val sharedGroupCount = sharedGroupCountTable(queryVbankIdx) + io.query_group_count := Mux( + b.memDomain.sharedEnable.B, + Mux(sharedGroupCount =/= 0.U, sharedGroupCount, b.memDomain.sharedDefaultGroupCount.U(4.W)), + 0.U + ) + + for (i <- 0 until b.memDomain.bankChannel) { + accPipes(i).io.mem_req.write <> io.mem_req(i).write + accPipes(i).io.mem_req.read <> io.mem_req(i).read + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + + accPipes(i).io.sramRead.req.ready := false.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare + + accPipes(i).io.sramWrite.req.ready := false.B + accPipes(i).io.sramWrite.resp.valid := false.B + accPipes(i).io.sramWrite.resp.bits := DontCare + + // In shared backend, all vbank/group combinations are treated as multi-capable. + accPipes(i).io.is_multi := true.B + } + + sharedMem.io.read.req.valid := false.B + sharedMem.io.read.req.bits := DontCare + sharedMem.io.read.resp.ready := false.B + sharedMem.io.write.req.valid := false.B + sharedMem.io.write.req.bits := DontCare + sharedMem.io.write.resp.ready := false.B + + // --------------------------------------------------------------------------- + // Shared request routing arbiter + // --------------------------------------------------------------------------- + val sharedReqArb = Module(new RRArbiter(new SharedArbReq(b), b.memDomain.bankChannel)) + + for (i <- 0 until b.memDomain.bankChannel) { + val routeShared = b.memDomain.sharedEnable.B + val useRead = accPipes(i).io.sramRead.req.valid + val useWrite = !useRead && accPipes(i).io.sramWrite.req.valid + + sharedReqArb.io.in(i).valid := routeShared && (useRead || useWrite) + sharedReqArb.io.in(i).bits.src_channel := i.U + sharedReqArb.io.in(i).bits.is_write := useWrite + sharedReqArb.io.in(i).bits.vbank_id := io.mem_req(i).bank_id + sharedReqArb.io.in(i).bits.group_id := io.mem_req(i).group_id + sharedReqArb.io.in(i).bits.addr := Mux( + useRead, + accPipes(i).io.sramRead.req.bits.addr, + accPipes(i).io.sramWrite.req.bits.addr + ) + sharedReqArb.io.in(i).bits.mask := Mux(useRead, VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)), accPipes(i).io.sramWrite.req.bits.mask) + sharedReqArb.io.in(i).bits.data := Mux(useRead, 0.U, accPipes(i).io.sramWrite.req.bits.data) + sharedReqArb.io.in(i).bits.wmode := Mux(useRead, false.B, accPipes(i).io.sramWrite.req.bits.wmode) + + when(routeShared && useRead) { + accPipes(i).io.sramRead.req.ready := sharedReqArb.io.in(i).ready + } + when(routeShared && useWrite) { + accPipes(i).io.sramWrite.req.ready := sharedReqArb.io.in(i).ready + } + } + + // Keep one in-flight request per response type so source-channel mapping is exact. + val readReqPending = RegInit(false.B) + val writeReqPending = RegInit(false.B) + val readReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + val writeReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + + val readRespBufValid = RegInit(false.B) + val readRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + val readRespBufData = Reg(UInt(b.memDomain.bankWidth.W)) + + val writeRespBufValid = RegInit(false.B) + val writeRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + val writeRespBufOk = Reg(Bool()) + + val arbIsWrite = sharedReqArb.io.out.bits.is_write + val canIssueRead = !readReqPending && !readRespBufValid + val canIssueWrite = !writeReqPending && !writeRespBufValid + + sharedMem.io.read.req.valid := sharedReqArb.io.out.valid && !arbIsWrite && canIssueRead + sharedMem.io.read.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id + sharedMem.io.read.req.bits.group_id := sharedReqArb.io.out.bits.group_id + sharedMem.io.read.req.bits.addr := sharedReqArb.io.out.bits.addr + + sharedMem.io.write.req.valid := sharedReqArb.io.out.valid && arbIsWrite && canIssueWrite + sharedMem.io.write.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id + sharedMem.io.write.req.bits.group_id := sharedReqArb.io.out.bits.group_id + sharedMem.io.write.req.bits.addr := sharedReqArb.io.out.bits.addr + sharedMem.io.write.req.bits.mask := sharedReqArb.io.out.bits.mask + sharedMem.io.write.req.bits.data := sharedReqArb.io.out.bits.data + sharedMem.io.write.req.bits.wmode := sharedReqArb.io.out.bits.wmode + + sharedReqArb.io.out.ready := Mux( + arbIsWrite, + canIssueWrite && sharedMem.io.write.req.ready, + canIssueRead && sharedMem.io.read.req.ready + ) + + when(sharedMem.io.read.req.fire) { + assert(!readReqPending, "SharedMemBackend: read request issued while previous read pending") + readReqPending := true.B + readReqSrcCh := sharedReqArb.io.out.bits.src_channel + } + + when(sharedMem.io.write.req.fire) { + assert(!writeReqPending, "SharedMemBackend: write request issued while previous write pending") + writeReqPending := true.B + writeReqSrcCh := sharedReqArb.io.out.bits.src_channel + } + + // Always absorb SharedMem pulses into local response buffers. + sharedMem.io.read.resp.ready := !readRespBufValid + sharedMem.io.write.resp.ready := !writeRespBufValid + + when(sharedMem.io.read.resp.fire) { + assert(readReqPending, "SharedMemBackend: read response arrived without pending request") + readRespBufValid := true.B + readRespBufSrcCh := readReqSrcCh + readRespBufData := sharedMem.io.read.resp.bits.data + readReqPending := false.B + } + + when(sharedMem.io.write.resp.fire) { + assert(writeReqPending, "SharedMemBackend: write response arrived without pending request") + writeRespBufValid := true.B + writeRespBufSrcCh := writeReqSrcCh + writeRespBufOk := sharedMem.io.write.resp.bits.ok + writeReqPending := false.B + } + + // --------------------------------------------------------------------------- + // Response demux back to requesting channel + // --------------------------------------------------------------------------- + for (i <- 0 until b.memDomain.bankChannel) { + when(readRespBufValid && (readRespBufSrcCh === i.U)) { + accPipes(i).io.sramRead.resp.valid := true.B + accPipes(i).io.sramRead.resp.bits.data := readRespBufData + + when(accPipes(i).io.sramRead.resp.fire) { + readRespBufValid := false.B + } + } + + when(writeRespBufValid && (writeRespBufSrcCh === i.U)) { + accPipes(i).io.sramWrite.resp.valid := true.B + accPipes(i).io.sramWrite.resp.bits.ok := writeRespBufOk + + when(accPipes(i).io.sramWrite.resp.fire) { + writeRespBufValid := false.B + } + } + } +} From a5f5e99b8bb407ab6438956eaf020c02534b4b2d Mon Sep 17 00:00:00 2001 From: SJM946 Date: Fri, 6 Mar 2026 00:44:36 +0800 Subject: [PATCH 135/238] [arch] add: Add SystolicArrayBall and BFP test --- .../scala/examples/toy/balldomain/DISA.scala | 1 + .../toy/balldomain/DomainDecoder.scala | 3 +- .../toy/balldomain/bbus/busRegister.scala | 2 + .../framework/balldomain/configs/default.json | 5 +- .../systolicarray/SystolicArrayBall.scala | 37 ++++ .../systolicarray/SystolicArrayCtrl.scala | 95 +++++++++ .../systolicarray/SystolicArrayEX.scala | 196 ++++++++++++++++++ .../systolicarray/SystolicArrayLoad.scala | 115 ++++++++++ .../systolicarray/SystolicArrayStore.scala | 135 ++++++++++++ .../systolicarray/SystolicArrayUnit.scala | 107 ++++++++++ .../configs/SystolicBallParam.scala | 26 +++ .../systolicarray/configs/default.json | 8 + bb-tests/workloads/lib/bbhw/isa/39_bfp.c | 14 ++ bb-tests/workloads/lib/bbhw/isa/isa.h | 1 + .../workloads/src/CTest/toy/CMakeLists.txt | 2 + bb-tests/workloads/src/CTest/toy/bfp_test.c | 78 +++++++ 16 files changed, 822 insertions(+), 3 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/default.json create mode 100644 bb-tests/workloads/lib/bbhw/isa/39_bfp.c create mode 100644 bb-tests/workloads/src/CTest/toy/bfp_test.c diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 1866c92d..be1f91d3 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -8,4 +8,5 @@ object DISA { val IM2COL = BitPat("b0100001") // 33 val TRANSPOSE = BitPat("b0100010") // 34 val RELU = BitPat("b0100110") // 38 + val SYSTOLIC = BitPat("b0100111") // 39 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 1a5f6989..26182f08 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -77,7 +77,8 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 0.U, rs2(63, 10)), RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 1.U, rs2(63, 10)), TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 2.U, rs2(63, 10)), - IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)) + IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)), + SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 4.U, rs2(63, 10)) ) ) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 8fc8664d..08037030 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -10,6 +10,7 @@ import framework.balldomain.prototype.vector.VecBall import framework.balldomain.prototype.relu.ReluBall import framework.balldomain.prototype.transpose.TransposeBall import framework.balldomain.prototype.im2col.Im2colBall +import framework.balldomain.prototype.systolicarray.SystolicArrayBall /** * BBusModule - Ball bus module that directly extends BBus @@ -24,6 +25,7 @@ class BBusModule(b: GlobalConfig) case "ReluBall" => () => new ReluBall(b) case "TransposeBall" => () => new TransposeBall(b) case "Im2colBall" => () => new Im2colBall(b) + case "SystolicArrayBall" => () => new SystolicArrayBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index d3288286..da75d29f 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,9 +1,10 @@ { - "ballNum": 4, + "ballNum": 5, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, {"ballId": 2, "ballName": "TransposeBall", "inBW": 1, "outBW": 1}, - {"ballId": 3, "ballName": "Im2colBall", "inBW": 1, "outBW": 1} + {"ballId": 3, "ballName": "Im2colBall", "inBW": 1, "outBW": 1}, + {"ballId": 4, "ballName": "SystolicArrayBall", "inBW": 2, "outBW": 4} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala new file mode 100644 index 00000000..d78a634a --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala @@ -0,0 +1,37 @@ +package framework.balldomain.prototype.systolicarray + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.top.GlobalConfig + +@instantiable +class SystolicArrayBall(val b: GlobalConfig) extends Module with HasBlink with HasBallStatus { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") + .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + def status: BallStatus = io.status + + val systolicArrayUnit: Instance[SystolicArrayUnit] = Instantiate(new SystolicArrayUnit(b)) + + systolicArrayUnit.io.cmdReq <> io.cmdReq + systolicArrayUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + systolicArrayUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + systolicArrayUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + io.status <> systolicArrayUnit.io.status +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala new file mode 100644 index 00000000..87ba8d8f --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala @@ -0,0 +1,95 @@ +package framework.balldomain.prototype.systolicarray + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.top.GlobalConfig + +@instantiable +class SystolicArrayCtrl(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp_o = Decoupled(new BallRsComplete(b)) + + val ctrl_ld_o = Decoupled(new ctrl_ld_req(b)) + val ctrl_st_o = Decoupled(new ctrl_st_req(b)) + val ctrl_ex_o = Decoupled(new ctrl_ex_req(b)) + + val cmdResp_i = Flipped(Valid(new Bundle { val commit = Bool() })) + }) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val iter = RegInit(0.U(10.W)) + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_bank_addr = RegInit(0.U(12.W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank_addr = RegInit(0.U(12.W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(12.W)) + val has_send = RegInit(false.B) + + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) + + io.cmdReq.ready := state === idle + + when(io.cmdReq.fire) { + iter := io.cmdReq.bits.cmd.iter + rob_id_reg := io.cmdReq.bits.rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op1_bank_addr := 0.U + op2_bank := io.cmdReq.bits.cmd.op2_bank + op2_bank_addr := 0.U + wr_bank := io.cmdReq.bits.cmd.wr_bank + wr_bank_addr := 0.U + state := busy + } + + when(state === busy && !has_send) { + io.ctrl_ld_o.valid := true.B + io.ctrl_ld_o.bits.op1_bank := op1_bank + io.ctrl_ld_o.bits.op1_bank_addr := op1_bank_addr + io.ctrl_ld_o.bits.op2_bank := op2_bank + io.ctrl_ld_o.bits.op2_bank_addr := op2_bank_addr + io.ctrl_ld_o.bits.iter := iter + + io.ctrl_ex_o.valid := true.B + io.ctrl_ex_o.bits.iter := iter + + io.ctrl_st_o.valid := true.B + io.ctrl_st_o.bits.wr_bank := wr_bank + io.ctrl_st_o.bits.wr_bank_addr := wr_bank_addr + io.ctrl_st_o.bits.iter := iter + + has_send := true.B + }.otherwise { + io.ctrl_ld_o.valid := false.B + io.ctrl_ld_o.bits.op1_bank := 0.U + io.ctrl_ld_o.bits.op1_bank_addr := 0.U + io.ctrl_ld_o.bits.op2_bank := 0.U + io.ctrl_ld_o.bits.op2_bank_addr := 0.U + io.ctrl_ld_o.bits.iter := 0.U + + io.ctrl_ex_o.valid := false.B + io.ctrl_ex_o.bits.iter := 0.U + + io.ctrl_st_o.valid := false.B + io.ctrl_st_o.bits.wr_bank := 0.U + io.ctrl_st_o.bits.wr_bank_addr := 0.U + io.ctrl_st_o.bits.iter := 0.U + } + + when(io.cmdResp_i.valid) { + io.cmdResp_o.valid := true.B + io.cmdResp_o.bits.rob_id := rob_id_reg + state := idle + has_send := false.B + }.otherwise { + io.cmdResp_o.valid := false.B + io.cmdResp_o.bits.rob_id := 0.U + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala new file mode 100644 index 00000000..1f112276 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala @@ -0,0 +1,196 @@ +package framework.balldomain.prototype.systolicarray + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.prototype.systolicarray.configs.SystolicBallParam + +class ctrl_ex_req(b: GlobalConfig) extends Bundle { + val iter = UInt(10.W) +} + +class ld_ex_req(b: GlobalConfig) extends Bundle { + val config = SystolicBallParam() + val op1 = Vec(config.lane, UInt(config.inputWidth.W)) + val op2 = Vec(config.lane, UInt(config.inputWidth.W)) + val iter = UInt(10.W) +} + +class ex_st_req(b: GlobalConfig) extends Bundle { + val config = SystolicBallParam() + val result = Vec(config.lane, UInt(config.outputWidth.W)) +} + +class PE(val inputWidth: Int, val outputWidth: Int) extends Module { + val io = IO(new Bundle { + val in_a = Flipped(Decoupled(UInt(inputWidth.W))) + val in_b = Flipped(Decoupled(UInt(inputWidth.W))) + val out_a = Decoupled(UInt(inputWidth.W)) + val out_b = Decoupled(UInt(inputWidth.W)) + val out_c = Output(UInt((outputWidth).W)) + val clear = Input(Bool()) + }) + + io.out_a.valid := RegNext(io.in_a.valid) + io.out_a.bits := RegNext(io.in_a.bits) + io.in_a.ready := io.out_a.ready + + io.out_b.valid := RegNext(io.in_b.valid) + io.out_b.bits := RegNext(io.in_b.bits) + io.in_b.ready := io.out_b.ready + + val acc_reg = RegInit(0.U((outputWidth).W)) + + when(io.clear) { + acc_reg := 0.U + }.elsewhen(io.in_a.fire && io.in_b.fire) { + acc_reg := io.in_a.bits * io.in_b.bits + acc_reg + } + + io.out_c := acc_reg + +} + +@instantiable +class SystolicArrayEX(val b: GlobalConfig) extends Module { + val config = SystolicBallParam() + val inputWidth = config.inputWidth + val outputWidth = config.outputWidth + val arraySize = config.lane + + @public + val io = IO(new Bundle { + val ctrl_ex_i = Flipped(Decoupled(new ctrl_ex_req(b))) + val ld_ex_i = Flipped(Decoupled(new ld_ex_req(b))) + + val ex_st_o = Decoupled(new ex_st_req(b)) + }) + + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) + + val iter_counter = RegInit(0.U(10.W)) + val store_counter = RegInit(0.U(6.W)) + val in_counter = RegInit(0.U(10.W)) + + // Use Reg with Vec type for proper register behavior + val in_a_buffer = Reg(Vec(arraySize, Vec(arraySize, UInt(inputWidth.W)))) + val in_b_buffer = Reg(Vec(arraySize, Vec(arraySize, UInt(inputWidth.W)))) + val pes = VecInit(Seq.fill(arraySize)(VecInit(Seq.fill(arraySize)(Module(new PE(inputWidth, outputWidth)).io)))) + + // default values + io.ctrl_ex_i.ready := io.ex_st_o.ready + io.ld_ex_i.ready := io.ex_st_o.ready + + io.ex_st_o.valid := false.B + io.ex_st_o.bits.result := VecInit(Seq.fill(arraySize)(0.U(inputWidth.W))) + + for (row <- 0 until arraySize) { + for (col <- 0 until arraySize) { + pes(row)(col).clear := false.B + } + } + + // input data to buffer + when(io.ld_ex_i.fire) { + in_counter := in_counter + 1.U + when(in_counter < arraySize.U) { + for (i <- 0 until arraySize) { + in_a_buffer(in_counter)(i) := io.ld_ex_i.bits.op1(i) + in_b_buffer(in_counter)(i) := io.ld_ex_i.bits.op2(i) + } + } + } + + // PEs connection + when(in_counter === arraySize.U) { + iter_counter := iter_counter + 1.U + + for (row <- 0 until arraySize) { + for (col <- 0 until arraySize) { + + if(row == 0 && col == 0) { + when(iter_counter < arraySize.U){ + pes(row)(col).in_a.valid := true.B + pes(row)(col).in_a.bits := in_a_buffer(0)(iter_counter) + pes(row)(col).in_b.valid := true.B + pes(row)(col).in_b.bits := in_b_buffer(iter_counter)(0) + }.otherwise{ + pes(row)(col).in_a.valid := false.B + pes(row)(col).in_a.bits := 0.U + pes(row)(col).in_b.valid := false.B + pes(row)(col).in_b.bits := 0.U + } + + } else if(row == 0 && col > 0) { + when((iter_counter >= col.U) && (iter_counter < arraySize.U + col.U)){ + pes(row)(col).in_b.valid := true.B + pes(row)(col).in_b.bits := in_b_buffer(iter_counter - col.U)(col) + pes(row)(col).in_a <> pes(row)(col - 1).out_a + }.otherwise{ + pes(row)(col).in_b.valid := false.B + pes(row)(col).in_b.bits := 0.U + pes(row)(col).in_a <> pes(row)(col - 1).out_a + } + + } else if(col == 0 && row > 0) { + when((iter_counter >= row.U) && (iter_counter < arraySize.U + row.U)){ + pes(row)(col).in_a.valid := true.B + pes(row)(col).in_a.bits := in_a_buffer(row)(iter_counter - row.U) + pes(row)(col).in_b <> pes(row - 1)(col).out_b + }.otherwise{ + pes(row)(col).in_a.valid := false.B + pes(row)(col).in_a.bits := 0.U + pes(row)(col).in_b <> pes(row - 1)(col).out_b + } + + } else if(row > 0 && col > 0) { + pes(row)(col).in_a <> pes(row)(col - 1).out_a + pes(row)(col).in_b <> pes(row - 1)(col).out_b + } + + if(row == arraySize - 1 || col == arraySize - 1) { + pes(row)(col).out_a.ready := io.ex_st_o.ready + pes(row)(col).out_b.ready := io.ex_st_o.ready + } + } + } + + }.otherwise{ + for (row <- 0 until arraySize) { + for (col <- 0 until arraySize) { + pes(row)(col).in_a.valid := false.B + pes(row)(col).in_a.bits := 0.U + pes(row)(col).in_b.valid := false.B + pes(row)(col).in_b.bits := 0.U + pes(row)(col).out_a.ready := io.ex_st_o.ready + pes(row)(col).out_b.ready := io.ex_st_o.ready + } + } + } + + // output data from PEs + when(iter_counter >= 40.U) { + when(store_counter < arraySize.U) { + io.ex_st_o.valid := true.B + io.ex_st_o.bits.result := VecInit(pes(store_counter).map(_.out_c)) + store_counter := store_counter + 1.U + }.otherwise { + // back to idle + iter_counter := 0.U + store_counter := 0.U + in_counter := 0.U + + // clear PEs + for (row <- 0 until arraySize) { + for(col <- 0 until arraySize) { + pes(row)(col).clear := true.B + } + } + + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala new file mode 100644 index 00000000..0f7e2343 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala @@ -0,0 +1,115 @@ +package framework.balldomain.prototype.systolicarray + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp} +import framework.top.GlobalConfig +import framework.balldomain.prototype.systolicarray.configs.SystolicBallParam + +@instantiable +class SystolicArrayLoad(val b: GlobalConfig) extends Module { + val config = SystolicBallParam() + val InputNum = 16 + val bankWidth = b.memDomain.bankWidth + val inputWidth = config.inputWidth + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") + .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) + val inBW = ballMapping.inBW + + @public + val io = IO(new Bundle { + val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) + val ctrl_ld_i = Flipped(Decoupled(new ctrl_ld_req(b))) + val ld_ex_o = Decoupled(new ld_ex_req(b)) + val op1_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val op2_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + }) + + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val op1_iter_counter = RegInit(0.U(10.W)) + val op2_iter_counter = RegInit(0.U(10.W)) + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) + val ld_ex_iter_reg = RegInit(0.U(10.W)) + + + val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) + val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) + + for (i <- 0 until inBW) { + io.bankReadReq(i).valid := false.B + io.bankReadReq(i).bits.addr := 0.U + } + + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank + io.ctrl_ld_i.ready := state === idle + + bankRespQueue0.io.enq <> io.bankReadResp(0) + bankRespQueue1.io.enq <> io.bankReadResp(1) + + when(io.ctrl_ld_i.fire) { + op1_bank := io.ctrl_ld_i.bits.op1_bank + op2_bank := io.ctrl_ld_i.bits.op2_bank + op1_addr := io.ctrl_ld_i.bits.op1_bank_addr + op2_addr := io.ctrl_ld_i.bits.op2_bank_addr + iter := io.ctrl_ld_i.bits.iter + op1_iter_counter := 0.U + op2_iter_counter := 0.U + state := busy + } + + when(state === busy && io.ld_ex_o.ready) { + io.bankReadReq(0).valid := op1_iter_counter < iter + io.bankReadReq(0).bits.addr := op1_addr + op1_iter_counter + op1_iter_counter := Mux(io.bankReadReq(0).ready, op1_iter_counter + 1.U, op1_iter_counter) + } + + when(state === busy && io.ld_ex_o.ready) { + io.bankReadReq(1).valid := op2_iter_counter < iter + io.bankReadReq(1).bits.addr := op2_addr + op2_iter_counter + op2_iter_counter := Mux(io.bankReadReq(1).ready, op2_iter_counter + 1.U, op2_iter_counter) + } + +// ----------------------------------------------------------------------------- +// SRAM returns data and passes to EX unit +// ----------------------------------------------------------------------------- + val both_valid = bankRespQueue0.io.deq.valid && bankRespQueue1.io.deq.valid + + io.ld_ex_o.valid := both_valid + when(both_valid) { + io.ld_ex_o.bits.op1 := bankRespQueue0.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.ld_ex_o.bits.op2 := bankRespQueue1.io.deq.bits.data.asTypeOf(Vec(InputNum, UInt(inputWidth.W))) + io.ld_ex_o.bits.iter := ld_ex_iter_reg + }.otherwise { + io.ld_ex_o.bits.iter := 0.U + io.ld_ex_o.bits.op1 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + io.ld_ex_o.bits.op2 := VecInit(Seq.fill(InputNum)(0.U(inputWidth.W))) + } + + // Only dequeue and advance iter counter on successful handshake + bankRespQueue0.io.deq.ready := io.ld_ex_o.fire + bankRespQueue1.io.deq.ready := io.ld_ex_o.fire + + when(io.ld_ex_o.fire) { + ld_ex_iter_reg := ld_ex_iter_reg + 1.U + } + +// ----------------------------------------------------------------------------- +// Reset op1_iter_counter and return to idle state +// ----------------------------------------------------------------------------- + + when(state === busy && ld_ex_iter_reg === iter) { + state := idle + op1_iter_counter := 0.U + op2_iter_counter := 0.U + ld_ex_iter_reg := 0.U + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala new file mode 100644 index 00000000..c13f2dbd --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala @@ -0,0 +1,135 @@ +package framework.balldomain.prototype.systolicarray + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.memdomain.backend.banks.SramWriteIO +import framework.top.GlobalConfig + +class ctrl_st_req(b: GlobalConfig) extends Bundle { + val wr_bank = UInt(log2Up(b.memDomain.bankNum).W) + val wr_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) + val iter = UInt(10.W) +} + + +class BankWriteEntry(b: GlobalConfig) extends Bundle { + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val data = UInt(b.memDomain.bankWidth.W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val wmode = Bool() +} + +@instantiable +class SystolicArrayStore(val b: GlobalConfig) extends Module { + val accWidth = 32 + val InputNum = 16 + + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") + .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val ctrl_st_i = Flipped(Decoupled(new ctrl_st_req(b))) + val ex_st_i = Flipped(Decoupled(new ex_st_req(b))) + val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) + val wr_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val cmdResp_o = Valid(new Bundle { val commit = Bool() }) + }) + + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) + val iter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) + val idle :: busy :: Nil = Enum(2) + val state = RegInit(idle) + + val writeQueues = VecInit(Seq.fill(outBW)(Module(new Queue(new BankWriteEntry(b), 16)).io)) + +// ----------------------------------------------------------------------------- +// Set registers when Ctrl instruction arrives +// ----------------------------------------------------------------------------- + io.ctrl_st_i.ready := state === idle + + when(io.ctrl_st_i.fire) { + wr_bank := io.ctrl_st_i.bits.wr_bank + wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr + iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) + iter_counter := 0.U + state := busy + } + +// ----------------------------------------------------------------------------- +// Accept computation results from EX unit and push to write queues +// ----------------------------------------------------------------------------- + io.ex_st_i.ready := state === busy && writeQueues.forall(_.enq.ready) + + for (i <- 0 until outBW) { + writeQueues(i).enq.valid := false.B + writeQueues(i).enq.bits := DontCare + } + + when(io.ex_st_i.fire) { + for (i <- 0 until outBW) { + val elementsPerChannel = InputNum / outBW + val startIdx = i * elementsPerChannel + val endIdx = startIdx + elementsPerChannel - 1 + + val entry = Wire(new BankWriteEntry(b)) + entry.addr := wr_bank_addr + iter_counter(log2Ceil(InputNum) - 1, 0) + entry.data := Cat(io.ex_st_i.bits.result.slice(startIdx, endIdx + 1).reverse) + entry.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + entry.wmode := true.B + + writeQueues(i).enq.valid := true.B + writeQueues(i).enq.bits := entry + } + iter_counter := iter_counter + 1.U + } + +// ----------------------------------------------------------------------------- +// Drain write queues to bankWrite interface +// ----------------------------------------------------------------------------- + io.bankWrite.foreach { acc => + acc.req.valid := false.B + acc.req.bits.addr := 0.U + acc.req.bits.data := Cat(Seq.fill(accWidth / 8)(0.U(8.W))) + acc.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + acc.req.bits.wmode := false.B + acc.resp.ready := false.B + } + + for (i <- 0 until outBW) { + writeQueues(i).deq.ready := false.B + + when(writeQueues(i).deq.valid) { + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := writeQueues(i).deq.bits.addr + io.bankWrite(i).req.bits.data := writeQueues(i).deq.bits.data + io.bankWrite(i).req.bits.mask := writeQueues(i).deq.bits.mask + io.bankWrite(i).req.bits.wmode := writeQueues(i).deq.bits.wmode + writeQueues(i).deq.ready := io.bankWrite(i).req.ready + } + } + + // Output wr_bank for bank_id setting + io.wr_bank_o := wr_bank + +// ----------------------------------------------------------------------------- +// Reset iter counter, commit cmdResp, return to idle state +// ----------------------------------------------------------------------------- + val allQueuesEmpty = writeQueues.forall(q => !q.deq.valid) + val allDataEnqueued = state === busy && iter_counter >= iter + + when(allDataEnqueued && allQueuesEmpty) { + state := idle + io.cmdResp_o.valid := true.B + io.cmdResp_o.bits.commit := true.B + }.otherwise { + io.cmdResp_o.valid := false.B + io.cmdResp_o.bits.commit := false.B + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala new file mode 100644 index 00000000..cc168e8d --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala @@ -0,0 +1,107 @@ +package framework.balldomain.prototype.systolicarray + +import chisel3._ +import chisel3.util._ +import chisel3.stage._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.top.GlobalConfig +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp, SramWriteIO} + +class ctrl_ld_req(b: GlobalConfig) extends Bundle { + val op1_bank = UInt(log2Up(b.memDomain.bankNum).W) + val op1_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) + val op2_bank = UInt(log2Up(b.memDomain.bankNum).W) + val op2_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) + val iter = UInt(10.W) +} + + + +@instantiable +class SystolicArrayUnit(val b: GlobalConfig) extends Module { + val InputNum = 16 + val inputWidth = 8 + val accWidth = 32 + + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") + .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + } + + val ctrl: Instance[SystolicArrayCtrl] = Instantiate(new SystolicArrayCtrl(b)) + val load: Instance[SystolicArrayLoad] = Instantiate(new SystolicArrayLoad(b)) + val ex: Instance[SystolicArrayEX] = Instantiate(new SystolicArrayEX(b)) + val store: Instance[SystolicArrayStore] = Instantiate(new SystolicArrayStore(b)) + + ctrl.io.cmdReq <> io.cmdReq + io.cmdResp <> ctrl.io.cmdResp_o + + ctrl.io.ctrl_ld_o <> load.io.ctrl_ld_i + ctrl.io.ctrl_ex_o <> ex.io.ctrl_ex_i + ctrl.io.ctrl_st_o <> store.io.ctrl_st_i + + for (i <- 0 until inBW) { + io.bankRead(i).io.req <> load.io.bankReadReq(i) + load.io.bankReadResp(i) <> io.bankRead(i).io.resp + if (i == 0) { + io.bankRead(i).bank_id := load.io.op1_bank_o + io.bankRead(i).group_id := 0.U + } else if (i == 1) { + io.bankRead(i).bank_id := load.io.op2_bank_o + io.bankRead(i).group_id := 0.U + } + } + + load.io.ld_ex_o <> ex.io.ld_ex_i + ex.io.ex_st_o <> store.io.ex_st_i + ctrl.io.cmdResp_i <> store.io.cmdResp_o + + for (i <- 0 until outBW) { + io.bankWrite(i).io <> store.io.bankWrite(i) + io.bankWrite(i).bank_id := store.io.wr_bank_o + io.bankWrite(i).io.req.bits.wmode := true.B + io.bankWrite(i).group_id := i.U + } + + val hasInput = RegInit(false.B) + val hasOutput = RegInit(false.B) + + when(io.cmdReq.fire) { + hasInput := true.B + } + when(io.cmdResp.fire) { + hasOutput := false.B + hasInput := false.B + } + when(io.cmdResp.valid && !hasOutput) { + hasOutput := true.B + } + + io.status.idle := !hasInput && !hasOutput + io.status.running := hasOutput +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala new file mode 100644 index 00000000..f3d7259f --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala @@ -0,0 +1,26 @@ +package framework.balldomain.prototype.systolicarray.configs + +import upickle.default._ + +/** + * SystolicBall 参数 + */ +case class SystolicBallParam( + InputNum: Int, + inputWidth: Int, + lane: Int, + outputWidth: Int, + numMulThreads: Int, + numCasThreads: Int) + +object SystolicBallParam { + implicit val rw: ReadWriter[SystolicBallParam] = macroRW + + def apply(): SystolicBallParam = { + val jsonStr = scala.io.Source.fromFile( + "src/main/scala/framework/balldomain/prototype/systolicarray/configs/default.json" + ).mkString + read[SystolicBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/default.json new file mode 100644 index 00000000..d5ad5924 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/default.json @@ -0,0 +1,8 @@ +{ + "InputNum": 16, + "inputWidth": 8, + "lane": 16, + "outputWidth": 32, + "numMulThreads": 16, + "numCasThreads": 16 +} diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bfp.c b/bb-tests/workloads/lib/bbhw/isa/39_bfp.c new file mode 100644 index 00000000..924d0005 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/39_bfp.c @@ -0,0 +1,14 @@ +#ifndef _BB_BFP_H_ +#define _BB_BFP_H_ + +#include "isa.h" + +#define BB_BFP_FUNC7 39 + +#define bb_BFP(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ + (FIELD(iter, 0, 9) | FIELD(mode, 10, 63)), \ + BB_BFP_FUNC7) + +#endif // _BB_BFP_H_ \ No newline at end of file diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 14902e55..9df60671 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -48,5 +48,6 @@ typedef int32_t result_t; #include "33_im2col.c" #include "34_transpose.c" #include "38_relu.c" +#include "39_bfp.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index a774a1fd..766b2249 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -116,6 +116,7 @@ add_cross_platform_test_target(ctest_transpose_16xn_test transpose_16xn_test.c) add_cross_platform_test_target(ctest_transpose_matmul transpose_matmul.c) add_cross_platform_test_target(ctest_relu_test relu_test.c) add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) +add_cross_platform_test_target(ctest_bfp_test bfp_test.c) # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS @@ -141,5 +142,6 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_transpose_matmul ctest_relu_test ctest_vsetvli + ctest_bfp_test COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/bfp_test.c b/bb-tests/workloads/src/CTest/toy/bfp_test.c new file mode 100644 index 00000000..a25c9e20 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/bfp_test.c @@ -0,0 +1,78 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); +static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); +static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); + +void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, + int size) { + // static elem_t a_transposed[DIM * DIM] __attribute__((aligned(64))); + // transpose_u8_matrix(a, a_transposed, size, size); + // spad0: operand A, offset 0 + uint32_t op1_bank_id = 0; + // spad1: operand B, offset 0 + uint32_t op2_bank_id = 1; + // acc0: write to accumulator, offset 0 + int acc_bank_id = 2; // virtual bank id + // bb_mem_alloc(acc_bank_id, 1, 4); + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + + bb_BFP(op1_bank_id, op2_bank_id, acc_bank_id, size, 0); + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_fence(); +} + +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { + cpu_matmul(a, b, expected_matrix, size, size, size); + hw_matmul(test_name, a, b, output_matrix, size); + + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + printf("Test %s PASSED\n", test_name); + return 1; + } else { + printf("Test %s FAILED\n", test_name); + return 0; + } + return 1; +} + +int test_ones() { + /* + init_sequence_matrix(input_matrix_a, DIM, DIM); + init_sequence_matrix(input_matrix_b, DIM, DIM); + */ + init_u8_random_matrix(input_matrix_a, DIM, DIM, 111); + init_u8_random_matrix(input_matrix_b, DIM, DIM, 222); + return run_test("BFP Matmul", input_matrix_a, input_matrix_b, DIM); +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + int passed = test_ones(); + if (passed) { + printf("BFP Matmul test PASSED\n"); + return 0; + } else { + printf("BFP Matmul test FAILED\n"); + return 1; + } + +#ifdef MULTICORE + exit(0); +#endif +} From 9b34e400a5d81e9acaf673fd1efd7697ba4b80b8 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 6 Mar 2026 03:44:15 +0800 Subject: [PATCH 136/238] [nix] update: bump Verilator version to 5.036 and add ccache and lld for build acceleration; remove verilated_vpi.cpp file --- arch/src/csrc/src/utils/verilated_vpi.cpp | 3087 --------------------- bbdev | 2 +- flake.nix | 5 + scripts/nix/build-env-tools.nix | 14 +- 4 files changed, 15 insertions(+), 3093 deletions(-) delete mode 100644 arch/src/csrc/src/utils/verilated_vpi.cpp diff --git a/arch/src/csrc/src/utils/verilated_vpi.cpp b/arch/src/csrc/src/utils/verilated_vpi.cpp deleted file mode 100644 index e0437522..00000000 --- a/arch/src/csrc/src/utils/verilated_vpi.cpp +++ /dev/null @@ -1,3087 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// -// Code available from: https://verilator.org -// -// Copyright 2009-2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//========================================================================= -/// -/// \file -/// \brief Verilated VPI implementation code -/// -/// This file must be compiled and linked against all Verilated objects -/// that use the VPI. -/// -/// Use "verilator --vpi" to add this to the Makefile for the linker. -/// -/// For documentation on the exported functions (named vpi_*) that are -/// implemented here, refer to the IEEE DPI chapter. -/// -//========================================================================= - -#define VERILATOR_VERILATED_VPI_CPP_ - -#include "verilated_vpi.h" - -#include "verilated.h" -#include "verilated_imp.h" - -#include -#include -#include -#include -#include -#include -#include - -//====================================================================== -// Internal constants - -#define VL_DEBUG_IF_PLI VL_DEBUG_IF -constexpr unsigned VL_VPI_LINE_SIZE_ = 8192; - -//====================================================================== -// Internal macros - -#define VL_VPI_INTERNAL_ \ - VerilatedVpiImp::error_info()->setMessage(vpiInternal)->setMessage -#define VL_VPI_SYSTEM_ \ - VerilatedVpiImp::error_info()->setMessage(vpiSystem)->setMessage -#define VL_VPI_ERROR_ \ - VerilatedVpiImp::error_info()->setMessage(vpiError)->setMessage -#define VL_VPI_WARNING_ \ - VerilatedVpiImp::error_info()->setMessage(vpiWarning)->setMessage -#define VL_VPI_NOTICE_ \ - VerilatedVpiImp::error_info()->setMessage(vpiNotice)->setMessage -#define VL_VPI_ERROR_RESET_ VerilatedVpiImp::error_info()->resetError - -// Not supported yet -#define VL_VPI_UNIMP_() \ - (VL_VPI_ERROR_(__FILE__, __LINE__, \ - Verilated::catName("Unsupported VPI function: ", __func__))) - -//====================================================================== -// Implementation - -// Base VPI handled object -class VerilatedVpio VL_NOT_FINAL { - // CONSTANTS - // Magic value stored in front of object to detect double free etc - // Must be odd, as aligned pointer can never be odd - static constexpr uint32_t activeMagic() VL_PURE { return 0xfeed100f; } - - // MEM MANGLEMENT - // Internal note: Globals may multi-construct, see verilated.cpp top. - static thread_local uint8_t *t_freeHeadp; - -public: - // CONSTRUCTORS - VerilatedVpio() = default; - virtual ~VerilatedVpio() = default; - static void *operator new(size_t size) VL_MT_SAFE { - // We new and delete tons of vpi structures, so keep them around - // To simplify our free list, we use a size large enough for all derived - // types We reserve word zero for the next pointer, as that's safer in case - // a dangling reference to the original remains around. - static constexpr size_t CHUNK_SIZE = 96; - if (VL_UNCOVERABLE(size > CHUNK_SIZE)) - VL_FATAL_MT(__FILE__, __LINE__, "", "increase CHUNK_SIZE"); - if (VL_LIKELY(t_freeHeadp)) { - uint8_t *const newp = t_freeHeadp; - t_freeHeadp = *(reinterpret_cast(newp)); - *(reinterpret_cast(newp)) = activeMagic(); - return newp + 8; - } - // +8: 8 bytes for next - uint8_t *newp = reinterpret_cast(::operator new(CHUNK_SIZE + 8)); - *(reinterpret_cast(newp)) = activeMagic(); - return newp + 8; - } - static void operator delete(void *obj, size_t /*size*/) VL_MT_SAFE { - uint8_t *const oldp = (static_cast(obj)) - 8; - if (VL_UNLIKELY(*(reinterpret_cast(oldp)) != activeMagic())) { - VL_FATAL_MT(__FILE__, __LINE__, "", - "vpi_release_handle() called on same object twice, or on " - "non-Verilator " - "VPI object"); - } -#ifdef VL_VPI_IMMEDIATE_FREE // Define to aid in finding leaky handles - ::operator delete(oldp); -#else - *(reinterpret_cast(oldp)) = t_freeHeadp; - t_freeHeadp = oldp; -#endif - } - // MEMBERS - static VerilatedVpio *castp(vpiHandle h) { - return dynamic_cast(reinterpret_cast(h)); - } - vpiHandle castVpiHandle() { return reinterpret_cast(this); } - // ACCESSORS - virtual const char *name() const { return ""; } - virtual const char *fullname() const { return ""; } - virtual const char *defname() const { return ""; } - virtual uint32_t type() const { return 0; } - virtual uint32_t constType() const { return vpiUndefined; } - virtual uint32_t size() const { return 0; } - virtual const VerilatedRange *rangep() const { return nullptr; } - virtual vpiHandle dovpi_scan() { return nullptr; } - virtual PLI_INT32 dovpi_remove_cb() { return 0; } -}; - -class VerilatedVpioReasonCb final : public VerilatedVpio { - // A handle to a timed or non-timed callback created with vpi_register_cb - // User can call vpi_remove_cb or vpi_release_handle on it - const uint64_t m_id; // Unique id/sequence number to find schedule's event - const QData m_time; // Scheduled time, or 0 = not timed - const PLI_INT32 m_reason; // VPI callback reason code - -public: - // cppcheck-suppress uninitVar // m_value - VerilatedVpioReasonCb(uint64_t id, QData time, PLI_INT32 reason) - : m_id{id}, m_time{time}, m_reason{reason} {} - ~VerilatedVpioReasonCb() override = default; - static VerilatedVpioReasonCb *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiCallback; } - PLI_INT32 dovpi_remove_cb() override; -}; - -class VerilatedVpioConst final : public VerilatedVpio { - const int32_t m_num; - -public: - explicit VerilatedVpioConst(int32_t num) : m_num{num} {} - ~VerilatedVpioConst() override = default; - static VerilatedVpioConst *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiConstant; } - uint32_t constType() const override { return vpiDecConst; } - int32_t num() const { return m_num; } -}; - -class VerilatedVpioVarBase VL_NOT_FINAL : public VerilatedVpio { -protected: - const VerilatedVar *m_varp = nullptr; - const VerilatedScope *m_scopep = nullptr; - std::string m_fullname; - const VerilatedRange &get_range() const { - // Determine number of dimensions and return outermost - return (m_varp->dims() > 1) ? m_varp->unpacked() : m_varp->packed(); - } - -public: - VerilatedVpioVarBase(const VerilatedVar *varp, const VerilatedScope *scopep) - : m_varp{varp}, m_scopep{scopep}, - m_fullname{std::string{m_scopep->name()} + '.' + m_varp->name()} {} - explicit VerilatedVpioVarBase(const VerilatedVpioVarBase *varp) { - if (varp) { - m_varp = varp->m_varp; - m_scopep = varp->m_scopep; - m_fullname = varp->m_fullname; - } - } - static VerilatedVpioVarBase *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - const VerilatedVar *varp() const { return m_varp; } - const VerilatedScope *scopep() const { return m_scopep; } - uint32_t size() const override { return get_range().elements(); } - const VerilatedRange *rangep() const override { return &get_range(); } - const char *name() const override { return m_varp->name(); } - const char *fullname() const override { return m_fullname.c_str(); } -}; - -class VerilatedVpioParam final : public VerilatedVpioVarBase { -public: - VerilatedVpioParam(const VerilatedVar *varp, const VerilatedScope *scopep) - : VerilatedVpioVarBase{varp, scopep} {} - ~VerilatedVpioParam() override = default; - - static VerilatedVpioParam *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiParameter; } - uint32_t constType() const override { - switch (m_varp->vltype()) { - case VLVT_UINT8: - case VLVT_UINT16: - case VLVT_UINT32: - case VLVT_UINT64: - case VLVT_WDATA: - return vpiDecConst; - case VLVT_STRING: - return vpiStringConst; - case VLVT_REAL: - return vpiRealConst; - default: - return vpiUndefined; - } - } - void *varDatap() const { return m_varp->datap(); } -}; - -class VerilatedVpioRange final : public VerilatedVpio { - const VerilatedRange *const m_rangep; - -public: - explicit VerilatedVpioRange(const VerilatedRange *rangep) - : m_rangep{rangep} {} - ~VerilatedVpioRange() override = default; - static VerilatedVpioRange *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiRange; } - uint32_t size() const override { return m_rangep->elements(); } - const VerilatedRange *rangep() const override { return m_rangep; } -}; - -class VerilatedVpioRangeIter final : public VerilatedVpio { - // Only supports 1 dimension - const VerilatedRange *const m_rangep; - bool m_done = false; - -public: - explicit VerilatedVpioRangeIter(const VerilatedRange *rangep) - : m_rangep{rangep} {} - ~VerilatedVpioRangeIter() override = default; - static VerilatedVpioRangeIter *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiIterator; } - vpiHandle dovpi_scan() override { - if (VL_UNLIKELY(m_done)) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; - } - m_done = true; - return ((new VerilatedVpioRange{m_rangep})->castVpiHandle()); - } -}; - -class VerilatedVpioScope VL_NOT_FINAL : public VerilatedVpio { -protected: - const VerilatedScope *const m_scopep; - bool m_toplevel = false; - -public: - explicit VerilatedVpioScope(const VerilatedScope *scopep) : m_scopep{scopep} { - std::string scopename = m_scopep->name(); - std::string::size_type pos = std::string::npos; - // Look for '.' not inside escaped identifier - size_t i = 0; - while (i < scopename.length()) { - if (scopename[i] == '\\') { - while (i < scopename.length() && scopename[i] != ' ') - ++i; - ++i; // Proc ' ', it should always be there. Then grab '.' on next cycle - } else { - while (i < scopename.length() && scopename[i] != '.') - ++i; - if (i < scopename.length()) - pos = i++; - } - } - if (VL_UNLIKELY(pos == std::string::npos)) - m_toplevel = true; - } - ~VerilatedVpioScope() override = default; - static VerilatedVpioScope *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiScope; } - const VerilatedScope *scopep() const { return m_scopep; } - const char *name() const override { return m_scopep->name(); } - const char *fullname() const override { return m_scopep->name(); } - bool toplevel() const { return m_toplevel; } -}; - -class VerilatedVpioVar VL_NOT_FINAL : public VerilatedVpioVarBase { - uint8_t *m_prevDatap = nullptr; // Previous value of data, for cbValueChange - union { - uint8_t u8[4]; - uint32_t u32; - } m_mask; // memoized variable mask - uint32_t m_entSize = 0; // memoized variable size -protected: - void *m_varDatap = nullptr; // varp()->datap() adjusted for array entries - int32_t m_index = 0; - -public: - VerilatedVpioVar(const VerilatedVar *varp, const VerilatedScope *scopep) - : VerilatedVpioVarBase{varp, scopep} { - m_mask.u32 = VL_MASK_I(varp->packed().elements()); - m_entSize = varp->entSize(); - m_varDatap = varp->datap(); - } - explicit VerilatedVpioVar(const VerilatedVpioVar *varp) - : VerilatedVpioVarBase{varp} { - if (varp) { - m_mask.u32 = varp->m_mask.u32; - m_entSize = varp->m_entSize; - m_varDatap = varp->m_varDatap; - m_index = varp->m_index; - // Not copying m_prevDatap, must be nullptr - } else { - m_mask.u32 = 0; - } - } - ~VerilatedVpioVar() override { - if (m_prevDatap) - VL_DO_CLEAR(delete[] m_prevDatap, m_prevDatap = nullptr); - } - static VerilatedVpioVar *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t mask() const { return m_mask.u32; } - uint8_t mask_byte(int idx) const { return m_mask.u8[idx & 3]; } - uint32_t entSize() const { return m_entSize; } - uint32_t index() const { return m_index; } - uint32_t type() const override { - uint32_t type = vpiReg; - switch (varp()->vltype()) { - case VLVT_REAL: - type = vpiRealVar; - break; - case VLVT_STRING: - type = vpiStringVar; - break; - default: - break; - } - return (varp()->dims() > 1) ? vpiMemory : type; // but might be wire, logic - } - void *prevDatap() const { return m_prevDatap; } - void *varDatap() const { return m_varDatap; } - void createPrevDatap() { - if (VL_UNLIKELY(!m_prevDatap)) { - m_prevDatap = new uint8_t[entSize()]; - std::memcpy(prevDatap(), varp()->datap(), entSize()); - } - } -}; - -class VerilatedVpioMemoryWord final : public VerilatedVpioVar { -public: - VerilatedVpioMemoryWord(const VerilatedVar *varp, - const VerilatedScope *scopep, int32_t index, - int offset) - : VerilatedVpioVar{varp, scopep} { - m_index = index; - m_varDatap = (static_cast(varp->datap())) + entSize() * offset; - } - ~VerilatedVpioMemoryWord() override = default; - static VerilatedVpioMemoryWord *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiMemoryWord; } - uint32_t size() const override { return varp()->packed().elements(); } - const VerilatedRange *rangep() const override { return &(varp()->packed()); } - const char *fullname() const override { - static thread_local std::string t_out; - constexpr size_t LEN_MAX_INDEX = 25; - char num[LEN_MAX_INDEX]; - VL_SNPRINTF(num, LEN_MAX_INDEX, "%d", m_index); - t_out = std::string{scopep()->name()} + "." + name() + "[" + num + "]"; - return t_out.c_str(); - } -}; - -class VerilatedVpioVarIter final : public VerilatedVpio { - const VerilatedScope *const m_scopep; - VerilatedVarNameMap::const_iterator m_it; - bool m_started = false; - const VerilatedScope *m_topscopep = nullptr; - bool m_onlyParams; - -public: - explicit VerilatedVpioVarIter(const VerilatedVpioScope *vop, - bool onlyParams = false) - : m_scopep{vop->scopep()}, m_onlyParams{onlyParams} { - if (VL_UNLIKELY(vop->toplevel())) - // This is a toplevel, so get TOP scope to search for ports during - // vpi_scan. - m_topscopep = Verilated::threadContextp()->scopeFind("TOP"); - } - ~VerilatedVpioVarIter() override = default; - static VerilatedVpioVarIter *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiIterator; } - vpiHandle dovpi_scan() override { - if (VL_UNLIKELY(!m_scopep->varsp())) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; // End of list - only one deep - } - while (true) { - const VerilatedVarNameMap *const varsp = m_scopep->varsp(); - if (VL_UNLIKELY(!m_started)) { - m_it = varsp->begin(); - m_started = true; - } else if (VL_UNLIKELY(m_it == varsp->end())) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; - } else { - ++m_it; - } - if (VL_UNLIKELY(m_it == varsp->end())) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; - } - if (m_onlyParams && !m_it->second.isParam()) - continue; - if (VL_UNLIKELY(m_topscopep)) { - if (const VerilatedVar *topvarp = - m_topscopep->varFind(m_it->second.name())) { - if (topvarp->isParam()) { - return ((new VerilatedVpioParam{topvarp, m_topscopep}) - ->castVpiHandle()); - } else { - return ( - (new VerilatedVpioVar{topvarp, m_topscopep})->castVpiHandle()); - } - } - } - if (m_it->second.isParam()) { - return ((new VerilatedVpioParam{&(m_it->second), m_scopep}) - ->castVpiHandle()); - } else { - return ( - (new VerilatedVpioVar{&(m_it->second), m_scopep})->castVpiHandle()); - } - } - } -}; - -class VerilatedVpioMemoryWordIter final : public VerilatedVpio { - const vpiHandle m_handle; - const VerilatedVar *const m_varp; - int32_t m_iteration; - const int32_t m_direction; - bool m_done = false; - -public: - VerilatedVpioMemoryWordIter(const vpiHandle handle, const VerilatedVar *varp) - : m_handle{handle}, m_varp{varp}, m_iteration{varp->unpacked().right()}, - m_direction{ - VL_LIKELY(varp->unpacked().left() > varp->unpacked().right()) - ? 1 - : -1} {} - ~VerilatedVpioMemoryWordIter() override = default; - static VerilatedVpioMemoryWordIter *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiIterator; } - void iterationInc() { - if (!(m_done = (m_iteration == m_varp->unpacked().left()))) - m_iteration += m_direction; - } - vpiHandle dovpi_scan() override { - if (VL_UNLIKELY(m_done)) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; - } - const vpiHandle result = vpi_handle_by_index(m_handle, m_iteration); - iterationInc(); - return result; - } -}; - -class VerilatedVpioModule final : public VerilatedVpioScope { - const char *m_name; - const char *m_fullname; - -public: - explicit VerilatedVpioModule(const VerilatedScope *modulep) - : VerilatedVpioScope{modulep} { - m_fullname = m_scopep->name(); - if (std::strncmp(m_fullname, "TOP.", 4) == 0) - m_fullname += 4; - m_name = m_scopep->identifier(); - } - static VerilatedVpioModule *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiModule; } - const char *name() const override { return m_name; } - const char *fullname() const override { return m_fullname; } -}; - -class VerilatedVpioModuleIter final : public VerilatedVpio { - const std::vector *m_vec; - std::vector::const_iterator m_it; - -public: - explicit VerilatedVpioModuleIter( - const std::vector &vec) - : m_vec{&vec} { - m_it = m_vec->begin(); - } - ~VerilatedVpioModuleIter() override = default; - static VerilatedVpioModuleIter *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiIterator; } - vpiHandle dovpi_scan() override { - while (true) { - if (m_it == m_vec->end()) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; - } - const VerilatedScope::Type itype = (*m_it)->type(); - const VerilatedScope *const modp = *m_it++; - if (itype == VerilatedScope::SCOPE_MODULE) { - return (new VerilatedVpioModule{modp})->castVpiHandle(); - } - } - } -}; - -class VerilatedVpioPackage final : public VerilatedVpioScope { - std::string m_name; - std::string m_fullname; - -public: - explicit VerilatedVpioPackage(const VerilatedScope *modulep) - : VerilatedVpioScope{modulep} { - const char *sfullname = m_scopep->name(); - if (std::strncmp(sfullname, "TOP.", 4) == 0) - sfullname += 4; - m_fullname = std::string{sfullname} + "::"; - if (m_fullname == "\\$unit ::") - m_fullname = "$unit::"; - m_name = std::string(m_scopep->identifier()); - if (m_name == "\\$unit ") - m_name = "$unit"; - } - static VerilatedVpioPackage *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiPackage; } - const char *name() const override { return m_name.c_str(); } - const char *fullname() const override { return m_fullname.c_str(); } -}; - -class VerilatedVpioInstanceIter final : public VerilatedVpio { - const std::vector *m_vec; - std::vector::const_iterator m_it; - -public: - explicit VerilatedVpioInstanceIter( - const std::vector &vec) - : m_vec{&vec} { - m_it = m_vec->begin(); - } - ~VerilatedVpioInstanceIter() override = default; - static VerilatedVpioInstanceIter *castp(vpiHandle h) { - return dynamic_cast( - reinterpret_cast(h)); - } - uint32_t type() const override { return vpiIterator; } - vpiHandle dovpi_scan() override { - while (true) { - if (m_it == m_vec->end()) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; - } - const VerilatedScope::Type itype = (*m_it)->type(); - const VerilatedScope *const modp = *m_it++; - if (itype == VerilatedScope::SCOPE_MODULE) { - return (new VerilatedVpioModule{modp})->castVpiHandle(); - } - if (itype == VerilatedScope::SCOPE_PACKAGE) { - return (new VerilatedVpioPackage{modp})->castVpiHandle(); - } - } - } -}; - -//====================================================================== - -using VerilatedPliCb = PLI_INT32 (*)(struct t_cb_data *); - -class VerilatedVpiCbHolder final { - // Holds information needed to call a callback - uint64_t - m_id; // Unique id/sequence number to find schedule's event, 0 = invalid - s_cb_data m_cbData; - s_vpi_value m_value; - VerilatedVpioVar - m_varo; // If a cbValueChange callback, the object we will return - -public: - // cppcheck-suppress uninitVar // m_value - VerilatedVpiCbHolder(uint64_t id, const s_cb_data *cbDatap, - const VerilatedVpioVar *varop) - : m_id{id}, m_cbData{*cbDatap}, m_varo{varop} { - m_value.format = cbDatap->value ? cbDatap->value->format : vpiSuppressVal; - m_cbData.value = &m_value; - if (varop) { - m_cbData.obj = m_varo.castVpiHandle(); - m_varo.createPrevDatap(); - } else { - m_cbData.obj = nullptr; - } - } - ~VerilatedVpiCbHolder() = default; - VerilatedPliCb cb_rtnp() const { return m_cbData.cb_rtn; } - s_cb_data *cb_datap() { return &m_cbData; } - uint64_t id() const { return m_id; } - bool invalid() const { return !m_id; } - void invalidate() { m_id = 0; } -}; - -struct VerilatedVpiTimedCbsCmp final { - // Ordering sets keyed by time, then callback unique id - bool operator()(const std::pair &a, - const std::pair &b) const { - if (a.first < b.first) - return true; - if (a.first > b.first) - return false; - return a.second < b.second; - } -}; - -class VerilatedVpiError; - -class VerilatedVpiImp final { - enum { CB_ENUM_MAX_VALUE = cbAtEndOfSimTime + 1 }; // Maximum callback reason - using VpioCbList = std::list; - using VpioFutureCbs = - std::map, VerilatedVpiCbHolder>; - - // All only medium-speed, so use singleton function - // Callbacks that are past or at current timestamp - std::array m_cbCurrentLists; - VpioFutureCbs m_futureCbs; // Time based callbacks for future timestamps - VpioFutureCbs m_nextCbs; // cbNextSimTime callbacks - VerilatedVpiError *m_errorInfop = nullptr; // Container for vpi error info - VerilatedAssertOneThread m_assertOne; // Assert only called from single thread - uint64_t m_nextCallbackId = 1; // Id to identify callback - - static VerilatedVpiImp &s() { // Singleton - static VerilatedVpiImp s_s; - return s_s; - } - -public: - static void assertOneCheck() { s().m_assertOne.check(); } - static uint64_t nextCallbackId() { return ++s().m_nextCallbackId; } - - static void cbCurrentAdd(uint64_t id, const s_cb_data *cb_data_p) { - // The passed cb_data_p was property of the user, so need to recreate - if (VL_UNCOVERABLE(cb_data_p->reason >= CB_ENUM_MAX_VALUE)) { - VL_FATAL_MT(__FILE__, __LINE__, "", "vpi bb reason too large"); - } - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" PRId64 - " obj=%p\n", - cb_data_p->reason, id, cb_data_p->obj);); - VerilatedVpioVar *varop = nullptr; - if (cb_data_p->reason == cbValueChange) - varop = VerilatedVpioVar::castp(cb_data_p->obj); - s().m_cbCurrentLists[cb_data_p->reason].emplace_back(id, cb_data_p, varop); - } - static void cbFutureAdd(uint64_t id, const s_cb_data *cb_data_p, QData time) { - // The passed cb_data_p was property of the user, so need to recreate - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" PRId64 - " time=%" PRIu64 " obj=%p\n", - cb_data_p->reason, id, time, cb_data_p->obj);); - s().m_futureCbs.emplace(std::piecewise_construct, - std::forward_as_tuple(time, id), - std::forward_as_tuple(id, cb_data_p, nullptr)); - } - static void cbNextAdd(uint64_t id, const s_cb_data *cb_data_p, QData time) { - // The passed cb_data_p was property of the user, so need to recreate - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d(NEXT) id=%" PRId64 - " time=%" PRIu64 " obj=%p\n", - cb_data_p->reason, id, time, cb_data_p->obj);); - s().m_nextCbs.emplace(std::piecewise_construct, - std::forward_as_tuple(time, id), - std::forward_as_tuple(id, cb_data_p, nullptr)); - } - static void cbReasonRemove(uint64_t id, uint32_t reason, QData time) { - // Id might no longer exist, if already removed due to call after event, or - // teardown We do not remove it now as we may be iterating the list, instead - // set to nullptr and will cleanup later Remove from cbCurrent queue - for (auto &ir : s().m_cbCurrentLists[reason]) { - if (ir.id() == id) { - ir.invalidate(); - return; // Once found, it won't also be in m_futureCbs - } - } - { // Remove from cbFuture queue - const auto it = s().m_futureCbs.find(std::make_pair(time, id)); - if (it != s().m_futureCbs.end()) { - it->second.invalidate(); - return; - } - } - { // Remove from cbNext - const auto it = s().m_nextCbs.find(std::make_pair(time, id)); - if (it != s().m_nextCbs.end()) { - it->second.invalidate(); - return; - } - } - } - static void moveFutureCbs() VL_MT_UNSAFE_ONE { - // For any events past current time, move from cbFuture queue to cbCurrent - // queue - if (s().m_futureCbs.empty() && s().m_nextCbs.empty()) - return; - // VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: moveFutureCbs\n"); dumpCbs(); ); - const QData time = VL_TIME_Q(); - for (auto it = s().m_futureCbs.begin(); // - VL_UNLIKELY(it != s().m_futureCbs.end() && it->first.first <= time);) { - VerilatedVpiCbHolder &hor = it->second; - const auto last_it = it; - ++it; - if (VL_UNLIKELY(!hor.invalid())) { - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: moveFutureCbs id=%" PRId64 "\n", hor.id());); - s().m_cbCurrentLists[hor.cb_datap()->reason].emplace_back(hor); - } - s().m_futureCbs.erase(last_it); - } - for (auto it = s().m_nextCbs.begin(); // - VL_UNLIKELY(it != s().m_nextCbs.end() && it->first.first < time);) { - VerilatedVpiCbHolder &hor = it->second; - const auto last_it = it; - ++it; - if (VL_UNLIKELY(!hor.invalid())) { - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: moveFutureCbs id=%" PRId64 "\n", hor.id());); - s().m_cbCurrentLists[hor.cb_datap()->reason].emplace_back(hor); - } - s().m_nextCbs.erase(last_it); - } - } - static QData cbNextDeadline() { - const auto it = s().m_futureCbs.cbegin(); - if (VL_LIKELY(it != s().m_futureCbs.cend())) - return it->first.first; - return ~0ULL; // maxquad - } - static bool callCbs(const uint32_t reason) VL_MT_UNSAFE_ONE { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: callCbs reason=%u\n", reason);); - assertOneCheck(); - moveFutureCbs(); - if (s().m_cbCurrentLists[reason].empty()) - return false; - // Iterate on old list, making new list empty, to prevent looping over newly - // added elements - VpioCbList cbObjList; - std::swap(s().m_cbCurrentLists[reason], cbObjList); - bool called = false; - for (VerilatedVpiCbHolder &ihor : cbObjList) { - // cbReasonRemove sets to nullptr, so we know on removal the old end() - // will still exist - if (VL_LIKELY(!ihor.invalid())) { // Not deleted earlier - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: reason_callback reason=%d id=%" PRId64 "\n", - reason, ihor.id());); - ihor.invalidate(); // Timed callbacks are one-shot - (ihor.cb_rtnp())(ihor.cb_datap()); - called = true; - } - } - return called; - } - static bool callValueCbs() VL_MT_UNSAFE_ONE { - assertOneCheck(); - VpioCbList &cbObjList = s().m_cbCurrentLists[cbValueChange]; - bool called = false; - std::unordered_set - update; // set of objects to update after callbacks - if (cbObjList.empty()) - return called; - const auto last = - std::prev(cbObjList.end()); // prevent looping over newly added elements - for (auto it = cbObjList.begin(); true;) { - // cbReasonRemove sets to nullptr, so we know on removal the old end() - // will still exist - const bool was_last = it == last; - if (VL_UNLIKELY(it->invalid())) { // Deleted earlier, cleanup - it = cbObjList.erase(it); - if (was_last) - break; - continue; - } - VerilatedVpiCbHolder &ho = *it++; - VerilatedVpioVar *const varop = - reinterpret_cast(ho.cb_datap()->obj); - void *const newDatap = varop->varDatap(); - void *const prevDatap = - varop->prevDatap(); // Was malloced when we added the callback - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_test %s v[0]=%d/%d %p %p\n", - varop->fullname(), - *(static_cast(newDatap)), - *(static_cast(prevDatap)), newDatap, - prevDatap);); - if (std::memcmp(prevDatap, newDatap, varop->entSize()) != 0) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_callback %" PRId64 - " %s v[0]=%d\n", - ho.id(), varop->fullname(), - *(static_cast(newDatap)));); - update.insert(varop); - vpi_get_value(ho.cb_datap()->obj, ho.cb_datap()->value); - (ho.cb_rtnp())(ho.cb_datap()); - called = true; - } - if (was_last) - break; - } - for (const auto &ip : update) { - std::memcpy(ip->prevDatap(), ip->varDatap(), ip->entSize()); - } - return called; - } - static void dumpCbs() VL_MT_UNSAFE_ONE; - static VerilatedVpiError * - error_info() VL_MT_UNSAFE_ONE; // getter for vpi error info -}; - -//====================================================================== -// Statics -// Internal note: Globals may multi-construct, see verilated.cpp top. - -thread_local uint8_t *VerilatedVpio::t_freeHeadp = nullptr; - -//====================================================================== -// VerilatedVpiError -// Internal container for vpi error info - -class VerilatedVpiError final { - t_vpi_error_info m_errorInfo; - bool m_flag = false; - char m_buff[VL_VPI_LINE_SIZE_]; - void setError(PLI_BYTE8 *message, PLI_BYTE8 *code, PLI_BYTE8 *file, - PLI_INT32 line) { - m_errorInfo.message = message; - m_errorInfo.file = file; - m_errorInfo.line = line; - m_errorInfo.code = code; - do_callbacks(); - } - void do_callbacks() { - if (getError()->level >= vpiError && - Verilated::threadContextp()->fatalOnVpiError()) { - // Stop on vpi error/unsupported - vpi_unsupported(); - } - // We need to run above code first because in the case that the - // callback executes further vpi functions we will loose the error - // as it will be overwritten. - VerilatedVpiImp::callCbs(cbPLIError); - } - -public: - VerilatedVpiError() { - m_buff[0] = '\0'; - m_errorInfo.product = const_cast(Verilated::productName()); - } - ~VerilatedVpiError() = default; - static void selfTest() VL_MT_UNSAFE_ONE; - VerilatedVpiError *setMessage(PLI_INT32 level) { - m_flag = true; - m_errorInfo.level = level; - return this; - } - void setMessage(const std::string &file, PLI_INT32 line, const char *message, - ...) { - // message cannot be a const string& as va_start cannot use a reference - static thread_local std::string t_filehold; - va_list args; - va_start(args, message); - VL_VSNPRINTF(m_buff, sizeof(m_buff), message, args); - va_end(args); - m_errorInfo.state = vpiPLI; - t_filehold = file; - setError(static_cast(m_buff), nullptr, - const_cast(t_filehold.c_str()), line); - } - p_vpi_error_info getError() { - if (m_flag) - return &m_errorInfo; - return nullptr; - } - void resetError() { m_flag = false; } - static void vpi_unsupported() { - // Not supported yet - const p_vpi_error_info error_info_p = - VerilatedVpiImp::error_info()->getError(); - if (error_info_p) { - VL_FATAL_MT(error_info_p->file, error_info_p->line, "", - error_info_p->message); - return; - } - VL_FATAL_MT(__FILE__, __LINE__, "", - "vpi_unsupported called without error info set"); - } - static const char *strFromVpiVal(PLI_INT32 vpiVal) VL_PURE; - static const char *strFromVpiObjType(PLI_INT32 vpiVal) VL_PURE; - static const char *strFromVpiMethod(PLI_INT32 vpiVal) VL_PURE; - static const char *strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_PURE; - static const char *strFromVpiProp(PLI_INT32 vpiVal) VL_PURE; - static const char *strFromVpiConstType(PLI_INT32 vpiVal) VL_PURE; -}; - -//====================================================================== -// VerilatedVpi implementation - -bool VerilatedVpi::callCbs(uint32_t reason) VL_MT_UNSAFE_ONE { - return VerilatedVpiImp::callCbs(reason); -} - -// Historical, before we had multiple kinds of timed callbacks -void VerilatedVpi::callTimedCbs() VL_MT_UNSAFE_ONE { - VerilatedVpiImp::callCbs(cbAfterDelay); -} - -bool VerilatedVpi::callValueCbs() VL_MT_UNSAFE_ONE { - return VerilatedVpiImp::callValueCbs(); -} - -QData VerilatedVpi::cbNextDeadline() VL_MT_UNSAFE_ONE { - return VerilatedVpiImp::cbNextDeadline(); -} - -void VerilatedVpi::dumpCbs() VL_MT_UNSAFE_ONE { VerilatedVpiImp::dumpCbs(); } - -PLI_INT32 VerilatedVpioReasonCb::dovpi_remove_cb() { - VerilatedVpiImp::cbReasonRemove(m_id, m_reason, m_time); - delete this; // IEEE 37.2.2 a vpi_remove_cb does a vpi_release_handle - return 1; -} - -//====================================================================== -// VerilatedVpiImp implementation - -void VerilatedVpiImp::dumpCbs() VL_MT_UNSAFE_ONE { - assertOneCheck(); - VL_DBG_MSGF("- vpi: dumpCbs\n"); - for (uint32_t reason = 0; reason < CB_ENUM_MAX_VALUE; ++reason) { - VpioCbList &cbObjList = s().m_cbCurrentLists[reason]; - for (auto &ho : cbObjList) { - if (VL_UNLIKELY(!ho.invalid())) { - VL_DBG_MSGF("- vpi: reason=%d=%s id=%" PRId64 "\n", reason, - VerilatedVpiError::strFromVpiCallbackReason(reason), - ho.id()); - } - } - } - for (auto &ifuture : s().m_nextCbs) { - const QData time = ifuture.first.first; - VerilatedVpiCbHolder &ho = ifuture.second; - if (VL_UNLIKELY(!ho.invalid())) { - VL_DBG_MSGF( - "- vpi: time=%" PRId64 "(NEXT) reason=%d=%s id=%" PRId64 "\n", - time, ho.cb_datap()->reason, - VerilatedVpiError::strFromVpiCallbackReason(ho.cb_datap()->reason), - ho.id()); - } - } - for (auto &ifuture : s().m_futureCbs) { - const QData time = ifuture.first.first; - VerilatedVpiCbHolder &ho = ifuture.second; - if (VL_UNLIKELY(!ho.invalid())) { - VL_DBG_MSGF( - "- vpi: time=%" PRId64 " reason=%d=%s id=%" PRId64 "\n", time, - ho.cb_datap()->reason, - VerilatedVpiError::strFromVpiCallbackReason(ho.cb_datap()->reason), - ho.id()); - } - } -} - -VerilatedVpiError *VerilatedVpiImp::error_info() VL_MT_UNSAFE_ONE { - VerilatedVpiImp::assertOneCheck(); - if (VL_UNLIKELY(!s().m_errorInfop)) - s().m_errorInfop = new VerilatedVpiError; - return s().m_errorInfop; -} - -//====================================================================== -// VerilatedVpiError Methods - -const char *VerilatedVpiError::strFromVpiVal(PLI_INT32 vpiVal) VL_PURE { - // clang-format off - static const char* const names[] = { - "*undefined*", - "vpiBinStrVal", - "vpiOctStrVal", - "vpiDecStrVal", - "vpiHexStrVal", - "vpiScalarVal", - "vpiIntVal", - "vpiRealVal", - "vpiStringVal", - "vpiVectorVal", - "vpiStrengthVal", - "vpiTimeVal", - "vpiObjTypeVal", - "vpiSuppressVal", - "vpiShortIntVal", - "vpiLongIntVal", - "vpiShortRealVal", - "vpiRawTwoStateVal", - "vpiRawFourStateVal", - }; - // clang-format on - if (VL_UNCOVERABLE(vpiVal < 0)) - return names[0]; - return names[(vpiVal <= vpiRawFourStateVal) ? vpiVal : 0]; -} -const char *VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_PURE { - // clang-format off - static const char* const names[] = { - "*undefined*", - "vpiAlways", - "vpiAssignStmt", - "vpiAssignment", - "vpiBegin", - "vpiCase", - "vpiCaseItem", - "vpiConstant", - "vpiContAssign", - "vpiDeassign", - "vpiDefParam", - "vpiDelayControl", - "vpiDisable", - "vpiEventControl", - "vpiEventStmt", - "vpiFor", - "vpiForce", - "vpiForever", - "vpiFork", - "vpiFuncCall", - "vpiFunction", - "vpiGate", - "vpiIf", - "vpiIfElse", - "vpiInitial", - "vpiIntegerVar", - "vpiInterModPath", - "vpiIterator", - "vpiIODecl", - "vpiMemory", - "vpiMemoryWord", - "vpiModPath", - "vpiModule", - "vpiNamedBegin", - "vpiNamedEvent", - "vpiNamedFork", - "vpiNet", - "vpiNetBit", - "vpiNullStmt", - "vpiOperation", - "vpiParamAssign", - "vpiParameter", - "vpiPartSelect", - "vpiPathTerm", - "vpiPort", - "vpiPortBit", - "vpiPrimTerm", - "vpiRealVar", - "vpiReg", - "vpiRegBit", - "vpiRelease", - "vpiRepeat", - "vpiRepeatControl", - "vpiSchedEvent", - "vpiSpecParam", - "vpiSwitch", - "vpiSysFuncCall", - "vpiSysTaskCall", - "vpiTableEntry", - "vpiTask", - "vpiTaskCall", - "vpiTchk", - "vpiTchkTerm", - "vpiTimeVar", - "vpiTimeQueue", - "vpiUdp", - "vpiUdpDefn", - "vpiUserSystf", - "vpiVarSelect", - "vpiWait", - "vpiWhile", - "vpiCondition", - "vpiDelay", - "vpiElseStmt", - "vpiForIncStmt", - "vpiForInitStmt", - "vpiHighConn", - "vpiLhs", - "vpiIndex", - "vpiLeftRange", - "vpiLowConn", - "vpiParent", - "vpiRhs", - "vpiRightRange", - "vpiScope", - "vpiSysTfCall", - "vpiTchkDataTerm", - "vpiTchkNotifier", - "vpiTchkRefTerm", - "vpiArgument", - "vpiBit", - "vpiDriver", - "vpiInternalScope", - "vpiLoad", - "vpiModDataPathIn", - "vpiModPathIn", - "vpiModPathOut", - "vpiOperand", - "vpiPortInst", - "vpiProcess", - "vpiVariables", - "vpiUse", - "vpiExpr", - "vpiPrimitive", - "vpiStmt", - "vpiAttribute", - "vpiBitSelect", - "vpiCallback", - "vpiDelayTerm", - "vpiDelayDevice", - "vpiFrame", - "vpiGateArray", - "vpiModuleArray", - "vpiPrimitiveArray", - "vpiNetArray", - "vpiRange", - "vpiRegArray", - "vpiSwitchArray", - "vpiUdpArray", - "vpiActiveTimeFormat", - "vpiInTerm", - "vpiInstanceArray", - "vpiLocalDriver", - "vpiLocalLoad", - "vpiOutTerm", - "vpiPorts", - "vpiSimNet", - "vpiTaskFunc", - "vpiContAssignBit", - "vpiNamedEventArray", - "vpiIndexedPartSelect", - "vpiBaseExpr", - "vpiWidthExpr", - "vpiGenScopeArray", - "vpiGenScope", - "vpiGenVar", - "vpiAutomatics" - }; - static const char* const sv_names1[] = { - "vpiPackage", - "vpiInterface", - "vpiProgram", - "vpiInterfaceArray", - "vpiProgramArray", - "vpiTypespec", - "vpiModport", - "vpiInterfaceTfDecl", - "vpiRefObj", - "vpiTypeParameter", - "vpiLongIntVar", - "vpiShortIntVar", - "vpiIntVar", - "vpiShortRealVar", - "vpiByteVar", - "vpiClassVar", - "vpiStringVar", - "vpiEnumVar", - "vpiStructVar", - "vpiUnionVar", - "vpiBitVar", - "vpiClassObj", - "vpiChandleVar", - "vpiPackedArrayVar", - "*undefined*", // 624 is not defined for object types - "vpiLongIntTypespec", - "vpiShortRealTypespec", - "vpiByteTypespec", - "vpiShortIntTypespec", - "vpiIntTypespec", - "vpiClassTypespec", - "vpiStringTypespec", - "vpiChandleTypespec", - "vpiEnumTypespec", - "vpiEnumConst", - "vpiIntegerTypespec", - "vpiTimeTypespec", - "vpiRealTypespec", - "vpiStructTypespec", - "vpiUnionTypespec", - "vpiBitTypespec", - "vpiLogicTypespec", - "vpiArrayTypespec", - "vpiVoidTypespec", - "vpiTypespecMember", - "vpiDistItem", - "vpiAliasStmt", - "vpiThread", - "vpiMethodFuncCall", - "vpiMethodTaskCall", - "vpiClockingBlock", - "vpiClockingIODecl", - "vpiClassDefn", - "vpiConstraint", - "vpiConstraintOrdering", - "vpiPropertyDecl", - "vpiPropertySpec", - "vpiPropertyExpr", - "vpiMulticlockSequenceExpr", - "vpiClockedSeq", - "vpiPropertyInst", - "vpiSequenceDecl", - "vpiCaseProperty", - "*undefined*", // 663 is not defined for object types - "vpiSequenceInst", - "vpiImmediateAssert", - "vpiReturn", - "vpiAnyPattern", - "vpiTaggedPattern", - "vpiStructPattern", - "vpiDoWhile", - "vpiOrderedWait", - "vpiWaitFork", - "vpiDisableFork", - "vpiExpectStmt", - "vpiForeachStmt", - "vpiFinal", - "vpiExtends", - "vpiDistribution", - "vpiSeqFormalDecl", - "vpiEnumNet", - "vpiIntegerNet", - "vpiTimeNet", - "vpiStructNet", - "vpiBreak", - "vpiContinue", - "vpiAssert", - "vpiAssume", - "vpiCover", - "vpiDisableCondition", - "vpiClockingEvent", - "vpiReturnStmt", - "vpiPackedArrayTypespec", - "vpiPackedArrayNet", - "vpiImmediateAssume", - "vpiImmediateCover", - "vpiSequenceTypespec", - "vpiPropertyTypespec", - "vpiEventTypespec", - "vpiPropFormalDecl", - }; - // clang-format on - if (VL_UNCOVERABLE(vpiVal < 0)) - return names[0]; - else if (vpiVal <= vpiAutomatics) - return names[vpiVal]; - else if (vpiVal >= vpiPackage && vpiVal <= vpiPropFormalDecl) - return sv_names1[(vpiVal - vpiPackage)]; - else - return names[0]; -} -const char *VerilatedVpiError::strFromVpiMethod(PLI_INT32 vpiVal) VL_PURE { - // clang-format off - static const char* const names[] = { - "vpiCondition", - "vpiDelay", - "vpiElseStmt", - "vpiForIncStmt", - "vpiForInitStmt", - "vpiHighConn", - "vpiLhs", - "vpiIndex", - "vpiLeftRange", - "vpiLowConn", - "vpiParent", - "vpiRhs", - "vpiRightRange", - "vpiScope", - "vpiSysTfCall", - "vpiTchkDataTerm", - "vpiTchkNotifier", - "vpiTchkRefTerm", - "vpiArgument", - "vpiBit", - "vpiDriver", - "vpiInternalScope", - "vpiLoad", - "vpiModDataPathIn", - "vpiModPathIn", - "vpiModPathOut", - "vpiOperand", - "vpiPortInst", - "vpiProcess", - "vpiVariables", - "vpiUse", - "vpiExpr", - "vpiPrimitive", - "vpiStmt" - }; - // clang-format on - if (vpiVal > vpiStmt || vpiVal < vpiCondition) - return "*undefined*"; - return names[vpiVal - vpiCondition]; -} - -const char * -VerilatedVpiError::strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_PURE { - // clang-format off - static const char* const names[] = { - "*undefined*", - "cbValueChange", - "cbStmt", - "cbForce", - "cbRelease", - "cbAtStartOfSimTime", - "cbReadWriteSynch", - "cbReadOnlySynch", - "cbNextSimTime", - "cbAfterDelay", - "cbEndOfCompile", - "cbStartOfSimulation", - "cbEndOfSimulation", - "cbError", - "cbTchkViolation", - "cbStartOfSave", - "cbEndOfSave", - "cbStartOfRestart", - "cbEndOfRestart", - "cbStartOfReset", - "cbEndOfReset", - "cbEnterInteractive", - "cbExitInteractive", - "cbInteractiveScopeChange", - "cbUnresolvedSystf", - "cbAssign", - "cbDeassign", - "cbDisable", - "cbPLIError", - "cbSignal", - "cbNBASynch", - "cbAtEndOfSimTime" - }; - // clang-format on - if (VL_UNCOVERABLE(vpiVal < 0)) - return names[0]; - return names[(vpiVal <= cbAtEndOfSimTime) ? vpiVal : 0]; -} - -const char *VerilatedVpiError::strFromVpiProp(PLI_INT32 vpiVal) VL_PURE { - // clang-format off - static const char* const names[] = { - "*undefined or other*", - "vpiType", - "vpiName", - "vpiFullName", - "vpiSize", - "vpiFile", - "vpiLineNo", - "vpiTopModule", - "vpiCellInstance", - "vpiDefName", - "vpiProtected", - "vpiTimeUnit", - "vpiTimePrecision", - "vpiDefNetType", - "vpiUnconnDrive", - "vpiDefFile", - "vpiDefLineNo", - "vpiScalar", - "vpiVector", - "vpiExplicitName", - "vpiDirection", - "vpiConnByName", - "vpiNetType", - "vpiExplicitScalared", - "vpiExplicitVectored", - "vpiExpanded", - "vpiImplicitDecl", - "vpiChargeStrength", - "vpiArray", - "vpiPortIndex", - "vpiTermIndex", - "vpiStrength0", - "vpiStrength1", - "vpiPrimType", - "vpiPolarity", - "vpiDataPolarity", - "vpiEdge", - "vpiPathType", - "vpiTchkType", - "vpiOpType", - "vpiConstType", - "vpiBlocking", - "vpiCaseType", - "vpiFuncType", - "vpiNetDeclAssign", - "vpiUserDefn", - "vpiScheduled", - "*undefined*", - "*undefined*", - "vpiActive", - "vpiAutomatic", - "vpiCell", - "vpiConfig", - "vpiConstantSelect", - "vpiDecompile", - "vpiDefAttribute", - "vpiDelayType", - "vpiIteratorType", - "vpiLibrary", - "*undefined*", - "vpiOffset", - "vpiResolvedNetType", - "vpiSaveRestartID", - "vpiSaveRestartLocation", - "vpiValid", - "vpiSigned", - "vpiStop", - "vpiFinish", - "vpiReset", - "vpiSetInteractiveScope", - "vpiLocalParam", - "vpiModPathHasIfNone", - "vpiIndexedPartSelectType", - "vpiIsMemory", - "vpiIsProtected" - }; - // clang-format on - if (vpiVal == vpiUndefined) - return "vpiUndefined"; - return names[(vpiVal <= vpiIsProtected) ? vpiVal : 0]; -} -const char * -VerilatedVpiError::strFromVpiConstType(PLI_INT32 constType) VL_PURE { - // clang-format off - static const char* const names[] = { - "*undefined*", - "vpiDecConst", - "vpiRealConst", - "vpiBinaryConst", - "vpiOctConst", - "vpiHexConst", - "vpiStringConst", - "vpiIntConst", - "vpiTimeConst", - }; - // clang-format on - if (VL_UNCOVERABLE(constType < 0)) - return names[0]; - return names[(constType <= vpiTimeConst) ? constType : 0]; -} - -#define SELF_CHECK_RESULT_CSTR(got, exp) \ - if (0 != std::strcmp((got), (exp))) { \ - const std::string msg = \ - "%Error: GOT = '"s + (got) + "'" + " EXP = '" + (exp) + "'"; \ - VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); \ - } - -#define SELF_CHECK_ENUM_STR(fn, enumn) \ - do { \ - const char *const strVal = VerilatedVpiError::fn(enumn); \ - SELF_CHECK_RESULT_CSTR(strVal, #enumn); \ - } while (0) - -void VerilatedVpi::selfTest() VL_MT_UNSAFE_ONE { - VerilatedVpiError::selfTest(); -} -void VerilatedVpiError::selfTest() VL_MT_UNSAFE_ONE { - VerilatedVpiImp::assertOneCheck(); - - SELF_CHECK_ENUM_STR(strFromVpiVal, vpiBinStrVal); - SELF_CHECK_ENUM_STR(strFromVpiVal, vpiRawFourStateVal); - - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAlways); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAssignStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAssignment); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBegin); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCase); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCaseItem); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiConstant); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiContAssign); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDeassign); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDefParam); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelayControl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDisable); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEventControl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEventStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFor); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForce); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForever); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFork); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFuncCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFunction); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGate); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIf); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIfElse); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInitial); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIntegerVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInterModPath); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIterator); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIODecl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMemory); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMemoryWord); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModPath); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModule); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedBegin); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedEvent); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedFork); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNetBit); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNullStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOperation); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiParamAssign); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiParameter); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPartSelect); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPathTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPort); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPortBit); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPrimTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRealVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiReg); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRegBit); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRelease); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRepeat); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRepeatControl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSchedEvent); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSpecParam); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSwitch); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSysFuncCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSysTaskCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTableEntry); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTask); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTaskCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchk); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTimeVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTimeQueue); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdp); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdpDefn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUserSystf); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiVarSelect); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWait); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWhile); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCondition); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelay); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiElseStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForIncStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForInitStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiHighConn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLhs); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIndex); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLeftRange); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLowConn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiParent); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRhs); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRightRange); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiScope); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSysTfCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkDataTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkNotifier); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkRefTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiArgument); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBit); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDriver); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInternalScope); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLoad); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModDataPathIn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModPathIn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModPathOut); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOperand); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPortInst); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiProcess); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiVariables); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUse); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiExpr); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPrimitive); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAttribute); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBitSelect); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCallback); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelayTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelayDevice); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFrame); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGateArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModuleArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPrimitiveArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNetArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRange); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRegArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSwitchArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdpArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiActiveTimeFormat); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInstanceArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLocalDriver); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLocalLoad); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOutTerm); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPorts); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSimNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTaskFunc); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiContAssignBit); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedEventArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIndexedPartSelect); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBaseExpr); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWidthExpr); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenScopeArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenScope); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAutomatics); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPackage); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInterface); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiProgram); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInterfaceArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiProgramArray); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModport); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInterfaceTfDecl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRefObj); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTypeParameter); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLongIntVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiShortIntVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIntVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiShortRealVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiByteVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClassVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStringVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEnumVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStructVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUnionVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBitVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClassObj); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiChandleVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPackedArrayVar); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLongIntTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiShortRealTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiByteTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiShortIntTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIntTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClassTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStringTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiChandleTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEnumTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEnumConst); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIntegerTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTimeTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRealTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStructTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUnionTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBitTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLogicTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiArrayTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiVoidTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTypespecMember); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDistItem); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAliasStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiThread); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMethodFuncCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMethodTaskCall); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClockingBlock); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClockingIODecl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClassDefn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiConstraint); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiConstraintOrdering); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPropertyDecl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPropertySpec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPropertyExpr); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMulticlockSequenceExpr); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClockedSeq); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPropertyInst); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSequenceDecl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCaseProperty); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSequenceInst); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiImmediateAssert); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiReturn); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAnyPattern); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTaggedPattern); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStructPattern); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDoWhile); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOrderedWait); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWaitFork); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDisableFork); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiExpectStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForeachStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFinal); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiExtends); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDistribution); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSeqFormalDecl); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEnumNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIntegerNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTimeNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStructNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBreak); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiContinue); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAssert); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAssume); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCover); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDisableCondition); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiClockingEvent); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiReturnStmt); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPackedArrayTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPackedArrayNet); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiImmediateAssume); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiImmediateCover); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSequenceTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPropertyTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEventTypespec); - SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPropFormalDecl); - - SELF_CHECK_ENUM_STR(strFromVpiMethod, vpiCondition); - SELF_CHECK_ENUM_STR(strFromVpiMethod, vpiStmt); - - SELF_CHECK_ENUM_STR(strFromVpiCallbackReason, cbValueChange); - SELF_CHECK_ENUM_STR(strFromVpiCallbackReason, cbAtEndOfSimTime); - - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiType); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiProtected); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiDirection); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiTermIndex); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiConstType); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiAutomatic); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiOffset); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiStop); - SELF_CHECK_ENUM_STR(strFromVpiProp, vpiIsProtected); - - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiDecConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiRealConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiBinaryConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiOctConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiHexConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiStringConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiIntConst); - SELF_CHECK_ENUM_STR(strFromVpiConstType, vpiTimeConst); -} - -#undef SELF_CHECK_ENUM_STR -#undef SELF_CHECK_RESULT_CSTR - -//====================================================================== -// callback related - -vpiHandle vpi_register_cb(p_cb_data cb_data_p) { - // Returns handle so user can remove the callback, user must - // vpi_release_handle it Don't confuse with the callback-activated t_cb_data - // object handle which is the object causing the callback rather than the - // callback itself - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - // cppcheck-suppress nullPointer - if (VL_UNLIKELY(!cb_data_p)) { - VL_VPI_WARNING_(__FILE__, __LINE__, "%s : callback data pointer is null", - __func__); - return nullptr; - } - const PLI_INT32 reason = cb_data_p->reason; - switch (reason) { - case cbAfterDelay: // FALLTHRU // One-shot; time relative - case cbAtEndOfSimTime: // FALLTHRU // One-shot; time absolute; supported via - // vlt_main.cpp - case cbAtStartOfSimTime: // FALLTHRU // One-shot; time absolute; supported via - // vlt_main.cpp - case cbReadOnlySynch: // FALLTHRU // One-shot; time relative; supported via - // vlt_main.cpp - case cbReadWriteSynch: { // One-shot; time relative; supported via - // vlt_main.cpp - const bool abs = reason == cbAtStartOfSimTime || reason == cbAtEndOfSimTime; - const QData time = VL_TIME_Q(); - QData abstime = 0; - if (cb_data_p->time) { - if (abs) { - abstime = VL_SET_QII(cb_data_p->time->high, cb_data_p->time->low); - } else { - abstime = - time + VL_SET_QII(cb_data_p->time->high, cb_data_p->time->low); - } - } - const uint64_t id = VerilatedVpiImp::nextCallbackId(); - VerilatedVpioReasonCb *const vop = - new VerilatedVpioReasonCb{id, abstime, reason}; - if (abstime <= time) { - VerilatedVpiImp::cbCurrentAdd(id, cb_data_p); - } else { - VerilatedVpiImp::cbFutureAdd(id, cb_data_p, abstime); - } - return vop->castVpiHandle(); - } - case cbNextSimTime: { // One-shot; time always next; supported via - // vlt_main.cpp - const QData time = VL_TIME_Q(); - const uint64_t id = VerilatedVpiImp::nextCallbackId(); - VerilatedVpioReasonCb *const vop = new VerilatedVpioReasonCb{id, 0, reason}; - VerilatedVpiImp::cbNextAdd(id, cb_data_p, time); - return vop->castVpiHandle(); - } - case cbEndOfSimulation: // FALLTHRU // One-shot; time ignored; supported via - // vlt_main.cpp - case cbEnterInteractive: // FALLTHRU // NOP, but need to return handle, so - // make object - case cbExitInteractive: // FALLTHRU // NOP, but need to return handle, so make - // object - case cbInteractiveScopeChange: // FALLTHRU // NOP, but need to return handle, - // so make object - case cbPLIError: // FALLTHRU // NOP, but need to return handle, so make object - case cbStartOfSimulation: // FALLTHRU // One-shot; time ignored; supported via - // vlt_main.cpp - case cbValueChange: { // Multi-shot; supported via vlt_main.cpp - const uint64_t id = VerilatedVpiImp::nextCallbackId(); - VerilatedVpioReasonCb *const vop = new VerilatedVpioReasonCb{id, 0, reason}; - VerilatedVpiImp::cbCurrentAdd(id, cb_data_p); - return vop->castVpiHandle(); - } - default: - VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported callback type %s", - __func__, - VerilatedVpiError::strFromVpiCallbackReason(reason)); - return nullptr; - } -} - -PLI_INT32 vpi_remove_cb(vpiHandle cb_obj) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_remove_cb %p\n", cb_obj);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - VerilatedVpio *const vop = VerilatedVpio::castp(cb_obj); - if (VL_UNLIKELY(!vop)) - return 0; - return vop->dovpi_remove_cb(); -} - -void vpi_get_cb_info(vpiHandle /*object*/, p_cb_data /*cb_data_p*/) { - VL_VPI_UNIMP_(); -} -vpiHandle vpi_register_systf(p_vpi_systf_data /*systf_data_p*/) { - VL_VPI_UNIMP_(); - return nullptr; -} -void vpi_get_systf_info(vpiHandle /*object*/, - p_vpi_systf_data /*systf_data_p*/) { - VL_VPI_UNIMP_(); -} - -// for obtaining handles - -vpiHandle vpi_handle_by_name(PLI_BYTE8 *namep, vpiHandle scope) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - if (VL_UNLIKELY(!namep)) - return nullptr; - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: vpi_handle_by_name %s %p\n", namep, scope);); - const VerilatedVar *varp = nullptr; - const VerilatedScope *scopep; - const VerilatedVpioScope *const voScopep = VerilatedVpioScope::castp(scope); - std::string scopeAndName = namep; - if (voScopep) { - const bool scopeIsPackage = VerilatedVpioPackage::castp(scope) != nullptr; - scopeAndName = - std::string{voScopep->fullname()} + (scopeIsPackage ? "" : ".") + namep; - namep = const_cast(scopeAndName.c_str()); - } - { - // This doesn't yet follow the hierarchy in the proper way - bool isPackage = false; - scopep = Verilated::threadContextp()->scopeFind(namep); - if (scopep) { // Whole thing found as a scope - if (scopep->type() == VerilatedScope::SCOPE_MODULE) { - return (new VerilatedVpioModule{scopep})->castVpiHandle(); - } else if (scopep->type() == VerilatedScope::SCOPE_PACKAGE) { - return (new VerilatedVpioPackage{scopep})->castVpiHandle(); - } else { - return (new VerilatedVpioScope{scopep})->castVpiHandle(); - } - } - std::string basename = scopeAndName; - std::string scopename; - std::string::size_type prevpos = std::string::npos; - std::string::size_type pos = std::string::npos; - // Split hierarchical names at last '.' not inside escaped identifier - size_t i = 0; - while (i < scopeAndName.length()) { - if (scopeAndName[i] == '\\') { - while (i < scopeAndName.length() && scopeAndName[i] != ' ') - ++i; - ++i; // Proc ' ', it should always be there. Then grab '.' on next cycle - } else { - while (i < scopeAndName.length() && - (scopeAndName[i] != '.' && - (i + 1 >= scopeAndName.length() || scopeAndName[i] != ':' || - scopeAndName[i + 1] != ':'))) - ++i; - if (i < scopeAndName.length()) { - prevpos = pos; - pos = i++; - if (scopeAndName[i - 1] == ':') - isPackage = true; - } - } - } - // Do the split - if (VL_LIKELY(pos != std::string::npos)) { - basename.erase(0, pos + (isPackage ? 2 : 1)); - scopename = scopeAndName.substr(0, pos); - if (scopename == "$unit") - scopename = "\\$unit "; - } - if (prevpos == std::string::npos) { - // scopename is a toplevel (no '.' separator), so search in our TOP ports - // first. - scopep = Verilated::threadContextp()->scopeFind("TOP"); - if (scopep) - varp = scopep->varFind(basename.c_str()); - } - if (!varp) { - scopep = Verilated::threadContextp()->scopeFind(scopename.c_str()); - if (!scopep) - return nullptr; - varp = scopep->varFind(basename.c_str()); - } - } - if (!varp) - return nullptr; - - if (varp->isParam()) { - return (new VerilatedVpioParam{varp, scopep})->castVpiHandle(); - } else { - return (new VerilatedVpioVar{varp, scopep})->castVpiHandle(); - } -} - -vpiHandle vpi_handle_by_index(vpiHandle object, PLI_INT32 indx) { - // Used to get array entries - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: vpi_handle_by_index %p %d\n", object, indx);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - // Memory words are not indexable - const VerilatedVpioMemoryWord *const vop = - VerilatedVpioMemoryWord::castp(object); - if (VL_UNLIKELY(vop)) - return nullptr; - const VerilatedVpioVar *const varop = VerilatedVpioVar::castp(object); - if (VL_LIKELY(varop)) { - if (varop->varp()->dims() < 2) - return nullptr; - if (VL_LIKELY(varop->varp()->unpacked().left() >= - varop->varp()->unpacked().right())) { - if (VL_UNLIKELY(indx > varop->varp()->unpacked().left() || - indx < varop->varp()->unpacked().right())) - return nullptr; - return (new VerilatedVpioMemoryWord{ - varop->varp(), varop->scopep(), indx, - indx - varop->varp()->unpacked().right()}) - ->castVpiHandle(); - } - if (VL_UNLIKELY(indx < varop->varp()->unpacked().left() || - indx > varop->varp()->unpacked().right())) - return nullptr; - return (new VerilatedVpioMemoryWord{varop->varp(), varop->scopep(), indx, - indx - - varop->varp()->unpacked().left()}) - ->castVpiHandle(); - } - VL_VPI_INTERNAL_(__FILE__, __LINE__, "%s : can't resolve handle", __func__); - return nullptr; -} - -// for traversing relationships - -vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle %d %p\n", type, object);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - switch (type) { - case vpiLeftRange: { - if (const VerilatedVpioVarBase *const vop = - VerilatedVpioVarBase::castp(object)) { - if (VL_UNLIKELY(!vop->rangep())) - return nullptr; - return (new VerilatedVpioConst{vop->rangep()->left()})->castVpiHandle(); - } else if (const VerilatedVpioRange *const vop = - VerilatedVpioRange::castp(object)) { - if (VL_UNLIKELY(!vop->rangep())) - return nullptr; - return (new VerilatedVpioConst{vop->rangep()->left()})->castVpiHandle(); - } - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned", - __func__, object, VerilatedVpiError::strFromVpiMethod(type)); - return nullptr; - } - case vpiRightRange: { - if (const VerilatedVpioVarBase *const vop = - VerilatedVpioVarBase::castp(object)) { - if (VL_UNLIKELY(!vop->rangep())) - return nullptr; - return (new VerilatedVpioConst{vop->rangep()->right()})->castVpiHandle(); - } else if (const VerilatedVpioRange *const vop = - VerilatedVpioRange::castp(object)) { - if (VL_UNLIKELY(!vop->rangep())) - return nullptr; - return (new VerilatedVpioConst{vop->rangep()->right()})->castVpiHandle(); - } - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned", - __func__, object, VerilatedVpiError::strFromVpiMethod(type)); - return nullptr; - } - case vpiIndex: { - const VerilatedVpioVar *const vop = VerilatedVpioVar::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - const int32_t val = vop->index(); - return (new VerilatedVpioConst{val})->castVpiHandle(); - } - case vpiScope: { - const VerilatedVpioVarBase *const vop = VerilatedVpioVarBase::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - return (new VerilatedVpioScope{vop->scopep()})->castVpiHandle(); - } - case vpiParent: { - const VerilatedVpioMemoryWord *const vop = - VerilatedVpioMemoryWord::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - return (new VerilatedVpioVar{vop->varp(), vop->scopep()})->castVpiHandle(); - } - default: - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Unsupported type %s, nothing will be returned", - __func__, VerilatedVpiError::strFromVpiMethod(type)); - return nullptr; - } -} - -vpiHandle vpi_handle_multi(PLI_INT32 /*type*/, vpiHandle /*refHandle1*/, - vpiHandle /*refHandle2*/, ...) { - VL_VPI_UNIMP_(); - return nullptr; -} - -vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_iterate %d %p\n", type, object);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - switch (type) { - case vpiMemoryWord: { - const VerilatedVpioVar *const vop = VerilatedVpioVar::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - if (vop->varp()->dims() < 2) - return nullptr; - if (vop->varp()->dims() > 2) { - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: %s, object %s has unsupported number of indices (%d)", __func__, - VerilatedVpiError::strFromVpiMethod(type), vop->fullname(), - vop->varp()->dims()); - } - return (new VerilatedVpioMemoryWordIter{object, vop->varp()}) - ->castVpiHandle(); - } - case vpiRange: { - const VerilatedVpioVar *const vop = VerilatedVpioVar::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - if (vop->varp()->dims() < 2) - return nullptr; - // Unsupported is multidim list - if (vop->varp()->dims() > 2) { - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: %s, object %s has unsupported number of indices (%d)", __func__, - VerilatedVpiError::strFromVpiMethod(type), vop->fullname(), - vop->varp()->dims()); - } - return ((new VerilatedVpioRangeIter{vop->rangep()})->castVpiHandle()); - } - case vpiReg: { - const VerilatedVpioScope *const vop = VerilatedVpioScope::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - return ((new VerilatedVpioVarIter{vop})->castVpiHandle()); - } - case vpiParameter: { - const VerilatedVpioScope *const vop = VerilatedVpioScope::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - return ((new VerilatedVpioVarIter{vop, true})->castVpiHandle()); - } - case vpiModule: { - const VerilatedVpioModule *const vop = VerilatedVpioModule::castp(object); - const VerilatedHierarchyMap *const map = VerilatedImp::hierarchyMap(); - const VerilatedScope *const modp = vop ? vop->scopep() : nullptr; - const auto it = - vlstd::as_const(map)->find(const_cast(modp)); - if (it == map->end()) - return nullptr; - return ((new VerilatedVpioModuleIter{it->second})->castVpiHandle()); - } - case vpiInstance: { - if (object) - return nullptr; - const VerilatedHierarchyMap *const map = VerilatedImp::hierarchyMap(); - const auto it = vlstd::as_const(map)->find(nullptr); - if (it == map->end()) - return nullptr; - return ((new VerilatedVpioInstanceIter{it->second})->castVpiHandle()); - } - default: - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Unsupported type %s, nothing will be returned", - __func__, VerilatedVpiError::strFromVpiObjType(type)); - return nullptr; - } -} -vpiHandle vpi_scan(vpiHandle object) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_scan %p\n", object);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - VerilatedVpio *const vop = VerilatedVpio::castp(object); - if (VL_UNLIKELY(!vop)) - return nullptr; - return vop->dovpi_scan(); -} - -// for processing properties - -PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) { - // Leave this in the header file - in many cases the compiler can constant - // propagate "object" - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get %d %p\n", property, object);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - switch (property) { - case vpiTimePrecision: { - return Verilated::threadContextp()->timeprecision(); - } - case vpiTimeUnit: { - const VerilatedVpioScope *const vop = VerilatedVpioScope::castp(object); - if (!vop) - return Verilated::threadContextp() - ->timeunit(); // Null asks for global, not unlikely - return vop->scopep()->timeunit(); - } - case vpiType: { - const VerilatedVpio *const vop = VerilatedVpio::castp(object); - if (VL_UNLIKELY(!vop)) - return vpiUndefined; - return vop->type(); - } - case vpiConstType: { - const VerilatedVpio *const vop = VerilatedVpio::castp(object); - if (VL_UNLIKELY(!vop)) - return vpiUndefined; - return vop->constType(); - } - case vpiDirection: { - // By forethought, the directions already are vpi enumerated - const VerilatedVpioVarBase *const vop = VerilatedVpioVarBase::castp(object); - if (VL_UNLIKELY(!vop)) - return vpiUndefined; - return vop->varp()->vldir(); - } - case vpiScalar: // FALLTHRU - case vpiVector: { - const VerilatedVpioVarBase *const vop = VerilatedVpioVarBase::castp(object); - if (VL_UNLIKELY(!vop)) - return vpiUndefined; - return (property == vpiVector) ^ (vop->varp()->dims() == 0); - } - case vpiSize: { - const VerilatedVpioVarBase *const vop = VerilatedVpioVarBase::castp(object); - if (VL_UNLIKELY(!vop)) - return vpiUndefined; - return vop->size(); - } - default: - VL_VPI_ERROR_(__FILE__, __LINE__, - "%s: Unsupported property %s, nothing will be returned", - __func__, VerilatedVpiError::strFromVpiProp(property)); - return vpiUndefined; - } -} - -PLI_INT64 vpi_get64(PLI_INT32 /*property*/, vpiHandle /*object*/) { - VL_VPI_UNIMP_(); - return vpiUndefined; -} - -PLI_BYTE8 *vpi_get_str(PLI_INT32 property, vpiHandle object) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get_str %d %p\n", property, object);); - VerilatedVpiImp::assertOneCheck(); - const VerilatedVpio *const vop = VerilatedVpio::castp(object); - VL_VPI_ERROR_RESET_(); - if (VL_UNLIKELY(!vop)) - return nullptr; - switch (property) { - case vpiName: { - return const_cast(vop->name()); - } - case vpiFullName: { - return const_cast(vop->fullname()); - } - case vpiDefName: { - return const_cast(vop->defname()); - } - case vpiType: { - return const_cast( - VerilatedVpiError::strFromVpiObjType(vop->type())); - } - case vpiConstType: { - const PLI_INT32 constType = vpi_get(vpiConstType, object); - VL_VPI_ERROR_RESET_(); - return const_cast( - VerilatedVpiError::strFromVpiConstType(constType)); - } - default: - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Unsupported type %s, nothing will be returned", - __func__, VerilatedVpiError::strFromVpiProp(property)); - return nullptr; - } -} - -// delay processing - -void vpi_get_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { - VL_VPI_UNIMP_(); -} -void vpi_put_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { - VL_VPI_UNIMP_(); -} - -// value processing -bool vl_check_format(const VerilatedVar *varp, const p_vpi_value valuep, - const char *fullname, bool isGetValue) { - bool status = true; - if ((valuep->format == vpiVectorVal) || (valuep->format == vpiBinStrVal) || - (valuep->format == vpiOctStrVal) || (valuep->format == vpiHexStrVal)) { - switch (varp->vltype()) { - case VLVT_UINT8: - case VLVT_UINT16: - case VLVT_UINT32: - case VLVT_UINT64: - case VLVT_WDATA: - return status; - default: - status = false; - } - } else if (valuep->format == vpiDecStrVal) { - switch (varp->vltype()) { - case VLVT_UINT8: - case VLVT_UINT16: - case VLVT_UINT32: - case VLVT_UINT64: - return status; - default: - status = false; - } - } else if (valuep->format == vpiStringVal) { - switch (varp->vltype()) { - case VLVT_UINT8: - case VLVT_UINT16: - case VLVT_UINT32: - case VLVT_UINT64: - case VLVT_WDATA: - return status; - case VLVT_STRING: - // string parameter values can't be changed - if (isGetValue || !varp->isParam()) { - return status; - } else { - status = false; - break; - } - default: - status = false; - } - } else if (valuep->format == vpiIntVal) { - switch (varp->vltype()) { - case VLVT_UINT8: - case VLVT_UINT16: - case VLVT_UINT32: - return status; - default: - status = false; - } - } else if (valuep->format == vpiRealVal) { - switch (varp->vltype()) { - case VLVT_REAL: - return status; - default: - status = false; - } - } else if (valuep->format == vpiSuppressVal) { - return status; - } else { - status = false; - } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", - __func__, VerilatedVpiError::strFromVpiVal(valuep->format), - fullname); - return status; -} - -void vl_get_value(const VerilatedVar *varp, void *varDatap, p_vpi_value valuep, - const char *fullname) { - if (!vl_check_format(varp, valuep, fullname, true)) - return; - // Maximum required size is for binary string, one byte per bit plus null - // termination - static thread_local char - t_outStr[VL_VALUE_STRING_MAX_WORDS * VL_EDATASIZE + 1]; - // cppcheck-suppress variableScope - static const thread_local int t_outStrSz = sizeof(t_outStr) - 1; - // string data type is dynamic and may vary in size during simulation - static thread_local std::string t_outDynamicStr; - // We used to presume vpiValue.format = vpiIntVal or if single bit - // vpiScalarVal This may cause backward compatibility issues with older code. - if (valuep->format == vpiVectorVal) { - // Vector pointer must come from our memory pool - // It only needs to persist until the next vpi_get_value - static thread_local t_vpi_vecval t_out[VL_VALUE_STRING_MAX_WORDS * 2]; - valuep->value.vector = t_out; - if (varp->vltype() == VLVT_UINT8) { - t_out[0].aval = *(reinterpret_cast(varDatap)); - t_out[0].bval = 0; - return; - } else if (varp->vltype() == VLVT_UINT16) { - t_out[0].aval = *(reinterpret_cast(varDatap)); - t_out[0].bval = 0; - return; - } else if (varp->vltype() == VLVT_UINT32) { - t_out[0].aval = *(reinterpret_cast(varDatap)); - t_out[0].bval = 0; - return; - } else if (varp->vltype() == VLVT_UINT64) { - const QData data = *(reinterpret_cast(varDatap)); - t_out[1].aval = static_cast(data >> 32ULL); - t_out[1].bval = 0; - t_out[0].aval = static_cast(data); - t_out[0].bval = 0; - return; - } else if (varp->vltype() == VLVT_WDATA) { - const int words = VL_WORDS_I(varp->packed().elements()); - if (VL_UNCOVERABLE(words >= VL_VALUE_STRING_MAX_WORDS)) { - VL_FATAL_MT(__FILE__, __LINE__, "", - "vpi_get_value with more than VL_VALUE_STRING_MAX_WORDS; " - "increase and " - "recompile"); - } - const WDataInP datap = (reinterpret_cast(varDatap)); - for (int i = 0; i < words; ++i) { - t_out[i].aval = datap[i]; - t_out[i].bval = 0; - } - return; - } - } else if (valuep->format == vpiBinStrVal) { - valuep->value.str = t_outStr; - int bits = varp->packed().elements(); - const CData *datap = (reinterpret_cast(varDatap)); - int i; - if (bits > t_outStrSz) { - // limit maximum size of output to size of buffer to prevent overrun. - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Truncating string value of %s for %s" - " as buffer size (%d, VL_VALUE_STRING_MAX_WORDS=%d) is " - "less than required (%d)", - __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), - fullname, t_outStrSz, VL_VALUE_STRING_MAX_WORDS, bits); - bits = t_outStrSz; - } - for (i = 0; i < bits; ++i) { - const char val = (datap[i >> 3] >> (i & 7)) & 1; - t_outStr[bits - i - 1] = val ? '1' : '0'; - } - t_outStr[i] = '\0'; - return; - } else if (valuep->format == vpiOctStrVal) { - valuep->value.str = t_outStr; - int chars = (varp->packed().elements() + 2) / 3; - const int bytes = VL_BYTES_I(varp->packed().elements()); - const CData *datap = (reinterpret_cast(varDatap)); - int i; - if (chars > t_outStrSz) { - // limit maximum size of output to size of buffer to prevent overrun. - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Truncating string value of %s for %s" - " as buffer size (%d, VL_VALUE_STRING_MAX_WORDS=%d) is " - "less than required (%d)", - __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), - fullname, t_outStrSz, VL_VALUE_STRING_MAX_WORDS, chars); - chars = t_outStrSz; - } - for (i = 0; i < chars; ++i) { - const div_t idx = div(i * 3, 8); - int val = datap[idx.quot]; - if ((idx.quot + 1) < bytes) { - // if the next byte is valid or that in - // for when the required 3 bits straddle adjacent bytes - val |= datap[idx.quot + 1] << 8; - } - // align so least significant 3 bits represent octal char - val >>= idx.rem; - if (i == (chars - 1)) { - // most significant char, mask off nonexistent bits when vector - // size is not a multiple of 3 - const unsigned int rem = varp->packed().elements() % 3; - if (rem) { - // generate bit mask & zero nonexistent bits - val &= (1 << rem) - 1; - } - } - t_outStr[chars - i - 1] = '0' + (val & 7); - } - t_outStr[i] = '\0'; - return; - } else if (valuep->format == vpiDecStrVal) { - valuep->value.str = t_outStr; - // outStrSz does not include nullptr termination so add one - if (varp->vltype() == VLVT_UINT8) { - VL_SNPRINTF( - t_outStr, t_outStrSz + 1, "%hhu", - static_cast(*(reinterpret_cast(varDatap)))); - return; - } else if (varp->vltype() == VLVT_UINT16) { - VL_SNPRINTF( - t_outStr, t_outStrSz + 1, "%hu", - static_cast(*(reinterpret_cast(varDatap)))); - return; - } else if (varp->vltype() == VLVT_UINT32) { - VL_SNPRINTF( - t_outStr, t_outStrSz + 1, "%u", - static_cast(*(reinterpret_cast(varDatap)))); - return; - } else if (varp->vltype() == VLVT_UINT64) { - VL_SNPRINTF(t_outStr, t_outStrSz + 1, "%llu", - static_cast( - *(reinterpret_cast(varDatap)))); - return; - } - } else if (valuep->format == vpiHexStrVal) { - valuep->value.str = t_outStr; - int chars = (varp->packed().elements() + 3) >> 2; - const CData *datap = (reinterpret_cast(varDatap)); - int i; - if (chars > t_outStrSz) { - // limit maximum size of output to size of buffer to prevent overrun. - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Truncating string value of %s for %s" - " as buffer size (%d, VL_VALUE_STRING_MAX_WORDS=%d) is " - "less than required (%d)", - __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), - fullname, t_outStrSz, VL_VALUE_STRING_MAX_WORDS, chars); - chars = t_outStrSz; - } - for (i = 0; i < chars; ++i) { - char val = (datap[i >> 1] >> ((i & 1) << 2)) & 15; - if (i == (chars - 1)) { - // most significant char, mask off nonexistent bits when vector - // size is not a multiple of 4 - const unsigned int rem = varp->packed().elements() & 3; - if (rem) { - // generate bit mask & zero nonexistent bits - val &= (1 << rem) - 1; - } - } - t_outStr[chars - i - 1] = "0123456789abcdef"[static_cast(val)]; - } - t_outStr[i] = '\0'; - return; - } else if (valuep->format == vpiStringVal) { - if (varp->vltype() == VLVT_STRING) { - if (varp->isParam()) { - valuep->value.str = reinterpret_cast(varDatap); - return; - } else { - t_outDynamicStr = *(reinterpret_cast(varDatap)); - valuep->value.str = const_cast(t_outDynamicStr.c_str()); - return; - } - } else { - valuep->value.str = t_outStr; - int bytes = VL_BYTES_I(varp->packed().elements()); - const CData *datap = (reinterpret_cast(varDatap)); - int i; - if (bytes > t_outStrSz) { - // limit maximum size of output to size of buffer to prevent overrun. - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: Truncating string value of %s for %s" - " as buffer size (%d, VL_VALUE_STRING_MAX_WORDS=%d) is less than " - "required (%d)", - __func__, VerilatedVpiError::strFromVpiVal(valuep->format), - fullname, t_outStrSz, VL_VALUE_STRING_MAX_WORDS, bytes); - bytes = t_outStrSz; - } - for (i = 0; i < bytes; ++i) { - const char val = datap[bytes - i - 1]; - // other simulators replace [leading?] zero chars with spaces, replicate - // here. - t_outStr[i] = val ? val : ' '; - } - t_outStr[i] = '\0'; - return; - } - } else if (valuep->format == vpiIntVal) { - if (varp->vltype() == VLVT_UINT8) { - valuep->value.integer = *(reinterpret_cast(varDatap)); - return; - } else if (varp->vltype() == VLVT_UINT16) { - valuep->value.integer = *(reinterpret_cast(varDatap)); - return; - } else if (varp->vltype() == VLVT_UINT32) { - valuep->value.integer = *(reinterpret_cast(varDatap)); - return; - } - } else if (valuep->format == vpiRealVal) { - valuep->value.real = *(reinterpret_cast(varDatap)); - return; - } else if (valuep->format == vpiSuppressVal) { - return; - } - VL_VPI_ERROR_(__FILE__, __LINE__, - "%s: Unsupported format (%s) as requested for %s", __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), fullname); -} - -void vpi_get_value(vpiHandle object, p_vpi_value valuep) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get_value %p\n", object);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - if (VL_UNLIKELY(!valuep)) - return; - - if (const VerilatedVpioVar *const vop = VerilatedVpioVar::castp(object)) { - vl_get_value(vop->varp(), vop->varDatap(), valuep, vop->fullname()); - return; - } else if (const VerilatedVpioParam *const vop = - VerilatedVpioParam::castp(object)) { - vl_get_value(vop->varp(), vop->varDatap(), valuep, vop->fullname()); - return; - } else if (const VerilatedVpioConst *const vop = - VerilatedVpioConst::castp(object)) { - if (valuep->format == vpiIntVal) { - valuep->value.integer = vop->num(); - return; - } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", - __func__, VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); - return; - } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", __func__, - object); -} - -vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, - p_vpi_time /*time_p*/, PLI_INT32 /*flags*/) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_put_value %p %p\n", object, valuep);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - if (VL_UNLIKELY(!valuep)) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "Ignoring vpi_put_value with nullptr value pointer"); - return nullptr; - } - if (const VerilatedVpioVar *const vop = VerilatedVpioVar::castp(object)) { - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: vpi_put_value name=%s fmt=%d vali=%d\n", - vop->fullname(), valuep->format, valuep->value.integer); - VL_DBG_MSGF("- vpi: varp=%p putatp=%p\n", vop->varp()->datap(), - vop->varDatap());); - - if (VL_UNLIKELY(!vop->varp()->isPublicRW())) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "Ignoring vpi_put_value to signal marked read-only," - " use public_flat_rw instead: %s", - vop->fullname()); - return nullptr; - } - if (!vl_check_format(vop->varp(), valuep, vop->fullname(), false)) - return nullptr; - if (valuep->format == vpiVectorVal) { - if (VL_UNLIKELY(!valuep->value.vector)) - return nullptr; - if (vop->varp()->vltype() == VLVT_UINT8) { - *(reinterpret_cast(vop->varDatap())) = - valuep->value.vector[0].aval & vop->mask(); - return object; - } else if (vop->varp()->vltype() == VLVT_UINT16) { - *(reinterpret_cast(vop->varDatap())) = - valuep->value.vector[0].aval & vop->mask(); - return object; - } else if (vop->varp()->vltype() == VLVT_UINT32) { - *(reinterpret_cast(vop->varDatap())) = - valuep->value.vector[0].aval & vop->mask(); - return object; - } else if (vop->varp()->vltype() == VLVT_UINT64) { - *(reinterpret_cast(vop->varDatap())) = - VL_SET_QII(valuep->value.vector[1].aval & vop->mask(), - valuep->value.vector[0].aval); - return object; - } else if (vop->varp()->vltype() == VLVT_WDATA) { - const int words = VL_WORDS_I(vop->varp()->packed().elements()); - WDataOutP datap = (reinterpret_cast(vop->varDatap())); - for (int i = 0; i < words; ++i) { - datap[i] = valuep->value.vector[i].aval; - if (i == (words - 1)) - datap[i] &= vop->mask(); - } - return object; - } - } else if (valuep->format == vpiBinStrVal) { - const int bits = vop->varp()->packed().elements(); - const int len = std::strlen(valuep->value.str); - CData *const datap = (reinterpret_cast(vop->varDatap())); - for (int i = 0; i < bits; ++i) { - const char set = - (i < len) ? (valuep->value.str[len - i - 1] == '1') : 0; - // zero bits 7:1 of byte when assigning to bit 0, else - // or in 1 if bit set - if (i & 7) { - datap[i >> 3] |= set << (i & 7); - } else { - datap[i >> 3] = set; - } - } - return object; - } else if (valuep->format == vpiOctStrVal) { - const int chars = (vop->varp()->packed().elements() + 2) / 3; - const int bytes = VL_BYTES_I(vop->varp()->packed().elements()); - const int len = std::strlen(valuep->value.str); - CData *const datap = (reinterpret_cast(vop->varDatap())); - div_t idx; - datap[0] = 0; // reset zero'th byte - for (int i = 0; i < chars; ++i) { - union { - char byte[2]; - uint16_t half; - } val; - idx = div(i * 3, 8); - if (i < len) { - // ignore illegal chars - const char digit = valuep->value.str[len - i - 1]; - if (digit >= '0' && digit <= '7') { - val.half = digit - '0'; - } else { - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: Non octal character '%c' in '%s' as value %s for %s", - __func__, digit, valuep->value.str, - VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); - val.half = 0; - } - } else { - val.half = 0; - } - // align octal character to position within vector, note that - // the three bits may straddle a byte boundary so two byte wide - // assignments are made to adjacent bytes - but not if the least - // significant byte of the aligned value is the most significant - // byte of the destination. - val.half <<= idx.rem; - datap[idx.quot] |= val.byte[0]; // or in value - if ((idx.quot + 1) < bytes) { - datap[idx.quot + 1] = val.byte[1]; // this also resets - // all bits to 0 prior to or'ing above - } - } - // mask off non-existent bits in the most significant byte - if (idx.quot == (bytes - 1)) { - datap[idx.quot] &= vop->mask_byte(idx.quot); - } else if (idx.quot + 1 == (bytes - 1)) { - datap[idx.quot + 1] &= vop->mask_byte(idx.quot + 1); - } - // zero off remaining top bytes - for (int i = idx.quot + 2; i < bytes; ++i) - datap[i] = 0; - return object; - } else if (valuep->format == vpiDecStrVal) { - char remainder[16]; - unsigned long long val; - const int success = - std::sscanf(valuep->value.str, "%30llu%15s", &val, remainder); - if (success < 1) { - VL_VPI_ERROR_(__FILE__, __LINE__, - "%s: Parsing failed for '%s' as value %s for %s", - __func__, valuep->value.str, - VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); - return nullptr; - } - if (success > 1) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Trailing garbage '%s' in '%s' as value %s for %s", - __func__, remainder, valuep->value.str, - VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); - } - if (vop->varp()->vltype() == VLVT_UINT8) { - *(reinterpret_cast(vop->varDatap())) = val & vop->mask(); - return object; - } else if (vop->varp()->vltype() == VLVT_UINT16) { - *(reinterpret_cast(vop->varDatap())) = val & vop->mask(); - return object; - } else if (vop->varp()->vltype() == VLVT_UINT32) { - *(reinterpret_cast(vop->varDatap())) = val & vop->mask(); - return object; - } else if (vop->varp()->vltype() == VLVT_UINT64) { - *(reinterpret_cast(vop->varDatap())) = val; - (reinterpret_cast(vop->varDatap()))[1] &= vop->mask(); - return object; - } - } else if (valuep->format == vpiHexStrVal) { - const int chars = (vop->varp()->packed().elements() + 3) >> 2; - CData *const datap = (reinterpret_cast(vop->varDatap())); - const char *val = valuep->value.str; - // skip hex ident if one is detected at the start of the string - if (val[0] == '0' && (val[1] == 'x' || val[1] == 'X')) - val += 2; - const int len = std::strlen(val); - for (int i = 0; i < chars; ++i) { - char hex; - // compute hex digit value - if (i < len) { - const char digit = val[len - i - 1]; - if (digit >= '0' && digit <= '9') { - hex = digit - '0'; - } else if (digit >= 'a' && digit <= 'f') { - hex = digit - 'a' + 10; - } else if (digit >= 'A' && digit <= 'F') { - hex = digit - 'A' + 10; - } else { - VL_VPI_WARNING_( - __FILE__, __LINE__, - "%s: Non hex character '%c' in '%s' as value %s for %s", - __func__, digit, valuep->value.str, - VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); - hex = 0; - } - } else { - hex = 0; - } - // assign hex digit value to destination - if (i & 1) { - datap[i >> 1] |= hex << 4; - } else { - datap[i >> 1] = hex; // this also resets all - // bits to 0 prior to or'ing above of the msb - } - } - // apply bit mask to most significant byte - datap[(chars - 1) >> 1] &= vop->mask_byte((chars - 1) >> 1); - return object; - } else if (valuep->format == vpiStringVal) { - if (vop->varp()->vltype() == VLVT_STRING) { - *(reinterpret_cast(vop->varDatap())) = valuep->value.str; - return object; - } else { - const int bytes = VL_BYTES_I(vop->varp()->packed().elements()); - const int len = std::strlen(valuep->value.str); - CData *const datap = (reinterpret_cast(vop->varDatap())); - for (int i = 0; i < bytes; ++i) { - // prepend with 0 values before placing string the least significant - // bytes - datap[i] = (i < len) ? valuep->value.str[len - i - 1] : 0; - } - } - return object; - } else if (valuep->format == vpiIntVal) { - if (vop->varp()->vltype() == VLVT_UINT8) { - *(reinterpret_cast(vop->varDatap())) = - vop->mask() & valuep->value.integer; - return object; - } else if (vop->varp()->vltype() == VLVT_UINT16) { - *(reinterpret_cast(vop->varDatap())) = - vop->mask() & valuep->value.integer; - return object; - } else if (vop->varp()->vltype() == VLVT_UINT32) { - *(reinterpret_cast(vop->varDatap())) = - vop->mask() & valuep->value.integer; - return object; - } - } else if (valuep->format == vpiRealVal) { - if (vop->varp()->vltype() == VLVT_REAL) { - *(reinterpret_cast(vop->varDatap())) = valuep->value.real; - return object; - } - } - VL_VPI_ERROR_(__FILE__, __LINE__, - "%s: Unsupported format (%s) as requested for %s", __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); - return nullptr; - } else if (const VerilatedVpioParam *const vop = - VerilatedVpioParam::castp(object)) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Ignoring vpi_put_value to vpiParameter: %s", __func__, - vop->fullname()); - return nullptr; - } else if (const VerilatedVpioConst *const vop = - VerilatedVpioConst::castp(object)) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Ignoring vpi_put_value to vpiConstant: %s", __func__, - vop->fullname()); - return nullptr; - } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", __func__, - object); - return nullptr; -} - -void vpi_get_value_array(vpiHandle /*object*/, - p_vpi_arrayvalue /*arrayvalue_p*/, - PLI_INT32 * /*index_p*/, PLI_UINT32 /*num*/) { - VL_VPI_UNIMP_(); -} -void vpi_put_value_array(vpiHandle /*object*/, - p_vpi_arrayvalue /*arrayvalue_p*/, - PLI_INT32 * /*index_p*/, PLI_UINT32 /*num*/) { - VL_VPI_UNIMP_(); -} - -// time processing - -void vpi_get_time(vpiHandle object, p_vpi_time time_p) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - // cppcheck-suppress nullPointer - if (VL_UNLIKELY(!time_p)) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "Ignoring vpi_get_time with nullptr value pointer"); - return; - } - if (time_p->type == vpiSimTime) { - const QData qtime = VL_TIME_Q(); - VlWide<2> itime; - VL_SET_WQ(itime, qtime); - time_p->low = itime[0]; - time_p->high = itime[1]; - return; - } else if (time_p->type == vpiScaledRealTime) { - double dtime = VL_TIME_D(); - if (const VerilatedVpioScope *const vop = - VerilatedVpioScope::castp(object)) { - const int scalePow10 = Verilated::threadContextp()->timeprecision() - - vop->scopep()->timeunit(); - const double scale = vl_time_multiplier(scalePow10); // e.g. 0.0001 - dtime *= scale; - } - time_p->real = dtime; - return; - } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported type (%d)", __func__, - time_p->type); -} - -// I/O routines - -PLI_UINT32 vpi_mcd_open(PLI_BYTE8 *filenamep) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - return VL_FOPEN_NN(filenamep, "wb"); -} - -PLI_UINT32 vpi_mcd_close(PLI_UINT32 mcd) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - VL_FCLOSE_I(mcd); - return 0; -} - -PLI_BYTE8 *vpi_mcd_name(PLI_UINT32 /*mcd*/) { - VL_VPI_UNIMP_(); - return nullptr; -} - -PLI_INT32 vpi_mcd_printf(PLI_UINT32 mcd, PLI_BYTE8 *formatp, ...) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - va_list ap; - va_start(ap, formatp); - const int chars = vpi_mcd_vprintf(mcd, formatp, ap); - va_end(ap); - return chars; -} - -PLI_INT32 vpi_printf(PLI_BYTE8 *formatp, ...) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - va_list ap; - va_start(ap, formatp); - const int chars = vpi_vprintf(formatp, ap); - va_end(ap); - return chars; -} - -PLI_INT32 vpi_vprintf(PLI_BYTE8 *formatp, va_list ap) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - return VL_VPRINTF(formatp, ap); -} - -PLI_INT32 vpi_mcd_vprintf(PLI_UINT32 mcd, PLI_BYTE8 *format, va_list ap) { - VerilatedVpiImp::assertOneCheck(); - FILE *const fp = VL_CVT_I_FP(mcd); - VL_VPI_ERROR_RESET_(); - // cppcheck-suppress nullPointer - if (VL_UNLIKELY(!fp)) - return 0; - const int chars = vfprintf(fp, format, ap); - return chars; -} - -PLI_INT32 vpi_flush(void) { - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - Verilated::runFlushCallbacks(); - return 0; // Gcc coverage bug // LCOV_EXCL_LINE -} - -PLI_INT32 vpi_mcd_flush(PLI_UINT32 mcd) { - VerilatedVpiImp::assertOneCheck(); - FILE *const fp = VL_CVT_I_FP(mcd); - VL_VPI_ERROR_RESET_(); - if (VL_UNLIKELY(!fp)) - return 1; - std::fflush(fp); - return 0; -} - -// utility routines - -PLI_INT32 vpi_compare_objects(vpiHandle /*object1*/, vpiHandle /*object2*/) { - VL_VPI_UNIMP_(); - return 0; -} -PLI_INT32 vpi_chk_error(p_vpi_error_info error_info_p) { - // executing vpi_chk_error does not reset error - // error_info_p can be nullptr, so only return level in that case - VerilatedVpiImp::assertOneCheck(); - p_vpi_error_info const _error_info_p = - VerilatedVpiImp::error_info()->getError(); - if (error_info_p && _error_info_p) - *error_info_p = *_error_info_p; - if (!_error_info_p) - return 0; // no error occurred - return _error_info_p->level; // return error severity level -} - -#ifndef VL_NO_LEGACY -PLI_INT32 vpi_free_object(vpiHandle object) { - // vpi_free_object is IEEE deprecated, use vpi_release_handle - return vpi_release_handle(object); -} -#endif - -PLI_INT32 vpi_release_handle(vpiHandle object) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_release_handle %p\n", object);); - VerilatedVpiImp::assertOneCheck(); - VerilatedVpio *const vop = VerilatedVpio::castp(object); - VL_VPI_ERROR_RESET_(); - if (VL_UNLIKELY(!vop)) - return 0; - VL_DO_DANGLING(delete vop, vop); - return 1; -} - -PLI_INT32 vpi_get_vlog_info(p_vpi_vlog_info vlog_info_p) { - // This is VL_MT_SAFE, but not marked as can't indicate it in the standardized - // header file - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - const auto argc_argv = Verilated::threadContextp()->impp()->argc_argv(); - vlog_info_p->argc = argc_argv.first; - vlog_info_p->argv = argc_argv.second; - vlog_info_p->product = const_cast(Verilated::productName()); - vlog_info_p->version = const_cast(Verilated::productVersion()); - return 1; -} - -// routines added with 1364-2001 - -PLI_INT32 vpi_get_data(PLI_INT32 /*id*/, PLI_BYTE8 * /*dataLoc*/, - PLI_INT32 /*numOfBytes*/) { - VL_VPI_UNIMP_(); - return 0; -} -PLI_INT32 vpi_put_data(PLI_INT32 /*id*/, PLI_BYTE8 * /*dataLoc*/, - PLI_INT32 /*numOfBytes*/) { - VL_VPI_UNIMP_(); - return 0; -} -void *vpi_get_userdata(vpiHandle /*obj*/) { - VL_VPI_UNIMP_(); - return nullptr; -} -PLI_INT32 vpi_put_userdata(vpiHandle /*obj*/, void * /*userdata*/) { - VL_VPI_UNIMP_(); - return 0; -} - -PLI_INT32 vpi_control(PLI_INT32 operation, ...) { - VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_control %d\n", operation);); - VerilatedVpiImp::assertOneCheck(); - VL_VPI_ERROR_RESET_(); - switch (operation) { - case vpiFinish: { - VL_FINISH_MT("", 0, "*VPI*"); - return 1; - } - case vpiStop: { - VL_STOP_MT("", 0, "*VPI*"); - return 1; // LCOV_EXCL_LINE - } - default: { - VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, ignoring", - __func__, VerilatedVpiError::strFromVpiProp(operation)); - return 0; - } - } -} - -vpiHandle vpi_handle_by_multi_index(vpiHandle /*obj*/, PLI_INT32 /*num_index*/, - PLI_INT32 * /*index_array*/) { - VL_VPI_UNIMP_(); - return nullptr; -} diff --git a/bbdev b/bbdev index 61bcffdb..ad41c840 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 61bcffdb1b40c31f8458112adfee9435c4c0b35d +Subproject commit ad41c840a73dc77c2fa0e73a15cc4876854a9718 diff --git a/flake.nix b/flake.nix index c47543dd..de11d400 100644 --- a/flake.nix +++ b/flake.nix @@ -22,6 +22,8 @@ paths = with pkgs; [ tools.verilator tools.dramsim2 + tools.ccache + tools.lld # RISC-V toolchain riscv.riscv-embedded-gcc @@ -80,6 +82,9 @@ source "$PWD/sourceme.sh" + # Verilator build acceleration: ccache via OBJCACHE + export OBJCACHE=ccache + echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" echo "RISC-V Embedded GCC: $(riscv64-unknown-elf-gcc --version 2>&1 | head -1)" diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index d45f4771..59e934a5 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -24,16 +24,20 @@ let }; in { - # Pin to Verilator 5.022 2024-02-24 (nixpkgs-unstable ships 5.044) + # Pin to Verilator 5.036 2025-01-01 (nixpkgs-unstable ships 5.044) verilator = pkgs.verilator.overrideAttrs (old: { - version = "5.022"; + version = "5.036"; src = pkgs.fetchurl { - url = "https://github.com/verilator/verilator/archive/refs/tags/v5.022.tar.gz"; - hash = "sha256-PC9TOPS2zn4vR6FCQBrN0Yy/TF2gYJJhjW0DbAr+8S0="; + url = "https://github.com/verilator/verilator/archive/refs/tags/v5.036.tar.gz"; + hash = "sha256-QZmWSILVbPahnOgMail+vjsMNeqBEGzU9yI0JZQzfEc="; }; - sourceRoot = "verilator-5.022"; + sourceRoot = "verilator-5.036"; doCheck = false; }); dramsim2 = dramsim2; + + # Build acceleration tools + ccache = pkgs.ccache; + lld = pkgs.lld; } From 9f533ecfb83ee726a717a4fedf77def4bc0608c1 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 6 Mar 2026 15:15:26 +0800 Subject: [PATCH 137/238] [nix] update: downgrade Verilator version to 5.022 --- bbdev | 2 +- scripts/nix/build-env-tools.nix | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/bbdev b/bbdev index ad41c840..abc5efe5 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit ad41c840a73dc77c2fa0e73a15cc4876854a9718 +Subproject commit abc5efe581364b34bfed079bec249df5d2671ec6 diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index 59e934a5..465c43ce 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -24,14 +24,14 @@ let }; in { - # Pin to Verilator 5.036 2025-01-01 (nixpkgs-unstable ships 5.044) + # Pin to Verilator 5.022 2024-02-24 (nixpkgs-unstable ships 5.044) verilator = pkgs.verilator.overrideAttrs (old: { - version = "5.036"; + version = "5.022"; src = pkgs.fetchurl { - url = "https://github.com/verilator/verilator/archive/refs/tags/v5.036.tar.gz"; - hash = "sha256-QZmWSILVbPahnOgMail+vjsMNeqBEGzU9yI0JZQzfEc="; + url = "https://github.com/verilator/verilator/archive/refs/tags/v5.022.tar.gz"; + hash = "sha256-PC9TOPS2zn4vR6FCQBrN0Yy/TF2gYJJhjW0DbAr+8S0="; }; - sourceRoot = "verilator-5.036"; + sourceRoot = "verilator-5.022"; doCheck = false; }); From fd5f21d8b158df2f5e49457e8ec0a8e9400a20e4 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 6 Mar 2026 15:52:27 +0800 Subject: [PATCH 138/238] [ci] update: add ALL_PROXY environment variable to CI and PR workflows --- .github/workflows/pr.yml | 5 ++--- .github/workflows/test.yml | 8 ++++---- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 368d3394..34cef5cc 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -9,6 +9,8 @@ jobs: PR-Test: name: PR Test runs-on: cpu-server + env: + ALL_PROXY: socks5h://127.0.0.1:7890 steps: - name: Print information run: | @@ -24,7 +26,6 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball - setproxy git fetch origin git clean -fd git checkout ${{ github.head_ref }} @@ -34,14 +35,12 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball - setproxy nix build - name: Build Workloads shell: zsh {0} run: | cd ~/Code/buckyball - setproxy nix develop -c bbdev workload --build - name: Build Verilator diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index d0e1a6a3..5c265b04 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -9,6 +9,8 @@ jobs: CI-Test: name: CI Test runs-on: cpu-server + env: + ALL_PROXY: socks5h://127.0.0.1:7890 steps: - name: Print information run: | @@ -19,23 +21,21 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball - setproxy + git fetch origin git clean -fd - git reset --hard ${{ github.sha }} git checkout ${{ github.head_ref }} + git pull - name: Nix build shell: zsh {0} run: | cd ~/Code/buckyball - setproxy nix build - name: Build Workloads shell: zsh {0} run: | cd ~/Code/buckyball - setproxy nix develop -c bbdev workload --build - name: Build Verilator From d6cdf687b970effd1f32ccce315a6d46331e1aa7 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 6 Mar 2026 19:42:23 +0800 Subject: [PATCH 139/238] [arch] add: Introduce BBTile architecture with decoupled Buckyball accelerator --- arch/img/buckyball.png | Bin 143089 -> 0 bytes arch/img/dma1.png | Bin 383334 -> 0 bytes arch/img/dma2.png | Bin 245362 -> 0 bytes .../scala/examples/toy/CustomConfigs.scala | 100 ++--- .../toy/balldomain/bbus/busRegister.scala | 10 +- .../systolicarray/SystolicArrayBall.scala | 4 +- .../systolicarray/SystolicArrayEX.scala | 95 ++-- .../systolicarray/SystolicArrayLoad.scala | 9 +- .../systolicarray/SystolicArrayStore.scala | 3 +- .../systolicarray/SystolicArrayUnit.scala | 6 +- .../scala/framework/core/bbtile/BBTile.scala | 413 ++++++++++++++++++ .../framework/core/bbtile/BBTileAttach.scala | 10 + .../framework/core/bbtile/BBTileParams.scala | 46 ++ .../core/bbtile/BuckyballAccelerator.scala} | 148 +++---- .../scala/framework/core/bbtile/Configs.scala | 74 ++++ .../framework/core/bbtile/RoCCTypes.scala | 48 ++ .../{rocket => bbtile}/RocketCoreBB.scala | 19 +- .../core/bbtile/id/RVVRoCCDecode.scala | 31 ++ .../scala/framework/core/rocket/Configs.scala | 275 ------------ .../framework/core/rocket/LazyRoCCBB.scala | 176 -------- .../core/rocket/RocketSubsystem.scala | 65 --- .../framework/core/rocket/RocketTileBB.scala | 326 -------------- .../core/rocket/id/RVVRoCCDecode.scala | 76 ---- .../scala/framework/frontend/Frontend.scala | 2 +- .../frontend/decoder/GobalDecoder.scala | 2 +- .../globalrs/GlobalReservationStation.scala | 2 +- .../gpdomain/sequencer/decoder/DISA.scala | 2 +- .../sequencer/decoder/DomainDecoder.scala | 2 +- .../memdomain/backend/MemBackend.scala | 2 +- .../memdomain/backend/shared/SharedMem.scala | 146 +++---- .../backend/shared/SharedMemBackend.scala | 40 +- .../memdomain/configs/MemDomainParam.scala | 30 +- 32 files changed, 917 insertions(+), 1245 deletions(-) delete mode 100644 arch/img/buckyball.png delete mode 100644 arch/img/dma1.png delete mode 100644 arch/img/dma2.png create mode 100644 arch/src/main/scala/framework/core/bbtile/BBTile.scala create mode 100644 arch/src/main/scala/framework/core/bbtile/BBTileAttach.scala create mode 100644 arch/src/main/scala/framework/core/bbtile/BBTileParams.scala rename arch/src/main/scala/{examples/toy/ToyBuckyBall.scala => framework/core/bbtile/BuckyballAccelerator.scala} (55%) create mode 100644 arch/src/main/scala/framework/core/bbtile/Configs.scala create mode 100644 arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala rename arch/src/main/scala/framework/core/{rocket => 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z0fhq<{2iaHybj00G?P9RR#N+_%z$a>=XdX4F1Mvz=$e1o?up^0qD~p0^atU`+WMJTM!_6ToLYu=hIV73`Cs{L2c5MEFrEAXYh9`I0}6NKc3hy=QT$Dg zApI1m*XfwE^4Y%$;AiB;f`N9b0Im>8i2)|Q>Gn;US^k@V!!k3gX%_fLKDR+|E0*3ekrp5A1g9Ul=&iQ7)u#J(X2~lEgg!oR+#D8cZnza#479x4zoykoJH+VXn6F_|vXz^NVy85{wWk<;d6{N4eZ* zTpG~|T7a9WkG_5SXf@{kexh=WyMmdfU=J~n=L&I}|IaF|oVeZun|0}yz+`njxgN@xNAmrei} diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 36bff667..ac388a20 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -1,37 +1,9 @@ package examples.toy -import org.chipsalliance.cde.config.{Config, Field, Parameters} -import chisel3._ -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.tile._ -import examples.toy.ToyBuckyball -import framework.top.GlobalConfig -import framework.core.rocket.BuildRoCCBB +import org.chipsalliance.cde.config.Config +import framework.core.bbtile.WithNBBTiles -object BuckyballToyConfig { - val defaultConfig = GlobalConfig() -} - -class BuckyballCustomConfig( - buckyballConfig: GlobalConfig = GlobalConfig()) - extends Config((site, here, up) => { - case BuildRoCCBB => up(BuildRoCCBB) ++ Seq { - (p: Parameters) => - implicit val q = p - val buckyball = LazyModule(new ToyBuckyball(buckyballConfig)(q)) - buckyball - } - }) - -class BuckyballToyConfig - extends Config( - new BuckyballCustomConfig ++ - new framework.core.rocket.WithNBuckyballCores(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) - -import freechips.rocketchip.subsystem.{InCluster, InSubsystem, MBUS, SBUS} +import freechips.rocketchip.subsystem.{InCluster, InSubsystem} import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import constellation.channel._ import constellation.routing._ @@ -40,18 +12,29 @@ import constellation.topology._ import constellation.noc._ import scala.collection.immutable.ListMap -// Increase BootROM size for large core counts (device tree becomes very large) -// Note: For AddressSet(base, size-1), we need (base & (size-1)) == 0 -// This means base must be aligned to size (size must be power of 2) -// For 256 cores (8 clusters × 32 cores), 512KB should be sufficient +/** Single BBTile: 1 Rocket core + 1 Buckyball accelerator */ +class BuckyballToyConfig + extends Config( + new WithNBBTiles(1) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) + +/** Single Rocket core only (no Buckyball) */ +class RocketOnlyConfig + extends Config( + new WithNBBTiles(1, withBuckyball = false) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) + +// Increase BootROM size for large core counts class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) extends Config((site, here, up) => { - case BootROMLocated(InSubsystem) => { + case BootROMLocated(InSubsystem) => up(BootROMLocated(InSubsystem)).map(_.copy(address = address, size = size)) - } }) -// 4-core test configuration to understand NoC mapping class BuckyballToy4Config extends Config( new WithLargeBootROM(0x80000, 0x80000) ++ @@ -59,12 +42,11 @@ class BuckyballToy4Config constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "serial_tl" -> 0, - "Core 0 " -> 1, // Space after number for precise matching + "Core 0 " -> 1, "Core 1 " -> 2, "Core 2 " -> 3, "Core 3 " -> 4, "debug" -> 5, - // buckyball-stream ports appear together, map them to same node "buckyball-stream-reader[0],buckyball-stream-writer[0]" -> 6, "buckyball-stream-reader[1],buckyball-stream-writer[1]" -> 7, "buckyball-stream-reader[2],buckyball-stream-writer[2]" -> 8, @@ -79,19 +61,17 @@ class BuckyballToy4Config ) ), NoCParams( - topology = TerminalRouter(Mesh2D(4, 4)), // 4x4 mesh = 16 nodes (enough for 10 inputs + 5 outputs) + topology = TerminalRouter(Mesh2D(4, 4)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) ) )) ++ - new BuckyballCustomConfig ++ - new framework.core.rocket.WithNBuckyballCores(4) ++ + new WithNBBTiles(4) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) -// 64-core test configuration with 2 L2 banks class BuckyballToy64Config extends Config( new WithLargeBootROM(0x80000, 0x80000) ++ @@ -100,27 +80,24 @@ class BuckyballToy64Config inNodeMapping = ListMap( "serial_tl" -> 0, "debug" -> 1 - ) ++ (0 until 64).map(i => s"Core $i " -> (2 + i)).toMap // Note the space after number! + ) ++ (0 until 64).map(i => s"Core $i " -> (2 + i)).toMap ++ (0 until 64).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (66 + i)).toMap, outNodeMapping = ListMap( "pbus" -> 130 ) ++ (0 until 2).map(i => s"system[$i]" -> (131 + i)).toMap ), NoCParams( - // 12x12 mesh = 144 nodes (enough for 130 inputs + 3 outputs) topology = TerminalRouter(Mesh2D(12, 12)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) ) )) ++ - new BuckyballCustomConfig ++ - new framework.core.rocket.WithNBuckyballCores(64) ++ + new WithNBBTiles(64) ++ new freechips.rocketchip.subsystem.WithNBanks(2) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) -// 256-core test configuration with 32 L2 banks class BuckyballToy256Config extends Config( new WithLargeBootROM(0x80000, 0x80000) ++ @@ -129,21 +106,19 @@ class BuckyballToy256Config inNodeMapping = ListMap( "serial_tl" -> 0, "debug" -> 1 - ) ++ (0 until 256).map(i => s"Core $i " -> (2 + i)).toMap // Note the space after number! + ) ++ (0 until 256).map(i => s"Core $i " -> (2 + i)).toMap ++ (0 until 256).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (258 + i)).toMap, outNodeMapping = ListMap( "pbus" -> 514 ) ++ (0 until 32).map(i => s"system[$i]" -> (515 + i)).toMap ), NoCParams( - // 24x24 mesh = 576 nodes (enough for 514 inputs + 33 outputs) topology = TerminalRouter(Mesh2D(24, 24)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) ) )) ++ - new BuckyballCustomConfig ++ - new framework.core.rocket.WithNBuckyballCores(256) ++ + new WithNBBTiles(256) ++ new freechips.rocketchip.subsystem.WithNBanks(32) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig @@ -151,16 +126,15 @@ class BuckyballToy256Config class BuckyballToy256CBConfig extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ // 512KB BootROM at 0x80000 (for 1024 cores) - new BuckyballCustomConfig ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(7)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(6)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(5)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(4)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(3)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(2)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(1)) ++ - new framework.core.rocket.WithNBuckyballCores(32, location = InCluster(0)) ++ + new WithLargeBootROM(0x80000, 0x80000) ++ + new WithNBBTiles(32, location = InCluster(7)) ++ + new WithNBBTiles(32, location = InCluster(6)) ++ + new WithNBBTiles(32, location = InCluster(5)) ++ + new WithNBBTiles(32, location = InCluster(4)) ++ + new WithNBBTiles(32, location = InCluster(3)) ++ + new WithNBBTiles(32, location = InCluster(2)) ++ + new WithNBBTiles(32, location = InCluster(1)) ++ + new WithNBBTiles(32, location = InCluster(0)) ++ new freechips.rocketchip.subsystem.WithCluster(7) ++ new freechips.rocketchip.subsystem.WithCluster(6) ++ new freechips.rocketchip.subsystem.WithCluster(5) ++ diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 08037030..c8e8e415 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -21,12 +21,12 @@ class BBusModule(b: GlobalConfig) b, b.ballDomain.ballIdMappings.map { mapping => val ballGenerator: () => HasBlink with Module = mapping.ballName match { - case "VecBall" => () => new VecBall(b) - case "ReluBall" => () => new ReluBall(b) - case "TransposeBall" => () => new TransposeBall(b) - case "Im2colBall" => () => new Im2colBall(b) + case "VecBall" => () => new VecBall(b) + case "ReluBall" => () => new ReluBall(b) + case "TransposeBall" => () => new TransposeBall(b) + case "Im2colBall" => () => new Im2colBall(b) case "SystolicArrayBall" => () => new SystolicArrayBall(b) - case name => throw new IllegalArgumentException(s"Unknown ball name: $name") + case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator } diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala index d78a634a..e2e1830f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala @@ -11,8 +11,8 @@ class SystolicArrayBall(val b: GlobalConfig) extends Module with HasBlink with H val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) - val inBW = ballCommonConfig.inBW - val outBW = ballCommonConfig.outBW + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW @public val io = IO(new BlinkIO(b, inBW, outBW)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala index 1f112276..f32faf6b 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala @@ -24,13 +24,14 @@ class ex_st_req(b: GlobalConfig) extends Bundle { } class PE(val inputWidth: Int, val outputWidth: Int) extends Module { + val io = IO(new Bundle { - val in_a = Flipped(Decoupled(UInt(inputWidth.W))) - val in_b = Flipped(Decoupled(UInt(inputWidth.W))) - val out_a = Decoupled(UInt(inputWidth.W)) - val out_b = Decoupled(UInt(inputWidth.W)) - val out_c = Output(UInt((outputWidth).W)) - val clear = Input(Bool()) + val in_a = Flipped(Decoupled(UInt(inputWidth.W))) + val in_b = Flipped(Decoupled(UInt(inputWidth.W))) + val out_a = Decoupled(UInt(inputWidth.W)) + val out_b = Decoupled(UInt(inputWidth.W)) + val out_c = Output(UInt(outputWidth.W)) + val clear = Input(Bool()) }) io.out_a.valid := RegNext(io.in_a.valid) @@ -40,8 +41,8 @@ class PE(val inputWidth: Int, val outputWidth: Int) extends Module { io.out_b.valid := RegNext(io.in_b.valid) io.out_b.bits := RegNext(io.in_b.bits) io.in_b.ready := io.out_b.ready - - val acc_reg = RegInit(0.U((outputWidth).W)) + + val acc_reg = RegInit(0.U(outputWidth.W)) when(io.clear) { acc_reg := 0.U @@ -55,10 +56,10 @@ class PE(val inputWidth: Int, val outputWidth: Int) extends Module { @instantiable class SystolicArrayEX(val b: GlobalConfig) extends Module { - val config = SystolicBallParam() - val inputWidth = config.inputWidth + val config = SystolicBallParam() + val inputWidth = config.inputWidth val outputWidth = config.outputWidth - val arraySize = config.lane + val arraySize = config.lane @public val io = IO(new Bundle { @@ -69,22 +70,22 @@ class SystolicArrayEX(val b: GlobalConfig) extends Module { }) val idle :: busy :: Nil = Enum(2) - val state = RegInit(idle) + val state = RegInit(idle) - val iter_counter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(10.W)) val store_counter = RegInit(0.U(6.W)) - val in_counter = RegInit(0.U(10.W)) + val in_counter = RegInit(0.U(10.W)) // Use Reg with Vec type for proper register behavior val in_a_buffer = Reg(Vec(arraySize, Vec(arraySize, UInt(inputWidth.W)))) val in_b_buffer = Reg(Vec(arraySize, Vec(arraySize, UInt(inputWidth.W)))) - val pes = VecInit(Seq.fill(arraySize)(VecInit(Seq.fill(arraySize)(Module(new PE(inputWidth, outputWidth)).io)))) + val pes = VecInit(Seq.fill(arraySize)(VecInit(Seq.fill(arraySize)(Module(new PE(inputWidth, outputWidth)).io)))) // default values io.ctrl_ex_i.ready := io.ex_st_o.ready - io.ld_ex_i.ready := io.ex_st_o.ready + io.ld_ex_i.ready := io.ex_st_o.ready - io.ex_st_o.valid := false.B + io.ex_st_o.valid := false.B io.ex_st_o.bits.result := VecInit(Seq.fill(arraySize)(0.U(inputWidth.W))) for (row <- 0 until arraySize) { @@ -111,60 +112,60 @@ class SystolicArrayEX(val b: GlobalConfig) extends Module { for (row <- 0 until arraySize) { for (col <- 0 until arraySize) { - if(row == 0 && col == 0) { - when(iter_counter < arraySize.U){ + if (row == 0 && col == 0) { + when(iter_counter < arraySize.U) { pes(row)(col).in_a.valid := true.B - pes(row)(col).in_a.bits := in_a_buffer(0)(iter_counter) + pes(row)(col).in_a.bits := in_a_buffer(0)(iter_counter) pes(row)(col).in_b.valid := true.B - pes(row)(col).in_b.bits := in_b_buffer(iter_counter)(0) - }.otherwise{ + pes(row)(col).in_b.bits := in_b_buffer(iter_counter)(0) + }.otherwise { pes(row)(col).in_a.valid := false.B - pes(row)(col).in_a.bits := 0.U + pes(row)(col).in_a.bits := 0.U pes(row)(col).in_b.valid := false.B - pes(row)(col).in_b.bits := 0.U + pes(row)(col).in_b.bits := 0.U } - } else if(row == 0 && col > 0) { - when((iter_counter >= col.U) && (iter_counter < arraySize.U + col.U)){ + } else if (row == 0 && col > 0) { + when((iter_counter >= col.U) && (iter_counter < arraySize.U + col.U)) { pes(row)(col).in_b.valid := true.B - pes(row)(col).in_b.bits := in_b_buffer(iter_counter - col.U)(col) + pes(row)(col).in_b.bits := in_b_buffer(iter_counter - col.U)(col) pes(row)(col).in_a <> pes(row)(col - 1).out_a - }.otherwise{ + }.otherwise { pes(row)(col).in_b.valid := false.B - pes(row)(col).in_b.bits := 0.U + pes(row)(col).in_b.bits := 0.U pes(row)(col).in_a <> pes(row)(col - 1).out_a } - } else if(col == 0 && row > 0) { - when((iter_counter >= row.U) && (iter_counter < arraySize.U + row.U)){ + } else if (col == 0 && row > 0) { + when((iter_counter >= row.U) && (iter_counter < arraySize.U + row.U)) { pes(row)(col).in_a.valid := true.B - pes(row)(col).in_a.bits := in_a_buffer(row)(iter_counter - row.U) + pes(row)(col).in_a.bits := in_a_buffer(row)(iter_counter - row.U) pes(row)(col).in_b <> pes(row - 1)(col).out_b - }.otherwise{ + }.otherwise { pes(row)(col).in_a.valid := false.B - pes(row)(col).in_a.bits := 0.U + pes(row)(col).in_a.bits := 0.U pes(row)(col).in_b <> pes(row - 1)(col).out_b } - } else if(row > 0 && col > 0) { + } else if (row > 0 && col > 0) { pes(row)(col).in_a <> pes(row)(col - 1).out_a pes(row)(col).in_b <> pes(row - 1)(col).out_b } - if(row == arraySize - 1 || col == arraySize - 1) { + if (row == arraySize - 1 || col == arraySize - 1) { pes(row)(col).out_a.ready := io.ex_st_o.ready pes(row)(col).out_b.ready := io.ex_st_o.ready } } } - }.otherwise{ + }.otherwise { for (row <- 0 until arraySize) { for (col <- 0 until arraySize) { - pes(row)(col).in_a.valid := false.B - pes(row)(col).in_a.bits := 0.U - pes(row)(col).in_b.valid := false.B - pes(row)(col).in_b.bits := 0.U + pes(row)(col).in_a.valid := false.B + pes(row)(col).in_a.bits := 0.U + pes(row)(col).in_b.valid := false.B + pes(row)(col).in_b.bits := 0.U pes(row)(col).out_a.ready := io.ex_st_o.ready pes(row)(col).out_b.ready := io.ex_st_o.ready } @@ -174,19 +175,19 @@ class SystolicArrayEX(val b: GlobalConfig) extends Module { // output data from PEs when(iter_counter >= 40.U) { when(store_counter < arraySize.U) { - io.ex_st_o.valid := true.B + io.ex_st_o.valid := true.B io.ex_st_o.bits.result := VecInit(pes(store_counter).map(_.out_c)) - store_counter := store_counter + 1.U + store_counter := store_counter + 1.U }.otherwise { // back to idle - iter_counter := 0.U + iter_counter := 0.U store_counter := 0.U - in_counter := 0.U + in_counter := 0.U // clear PEs for (row <- 0 until arraySize) { - for(col <- 0 until arraySize) { - pes(row)(col).clear := true.B + for (col <- 0 until arraySize) { + pes(row)(col).clear := true.B } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala index 0f7e2343..e2d4d9bb 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala @@ -10,13 +10,13 @@ import framework.balldomain.prototype.systolicarray.configs.SystolicBallParam @instantiable class SystolicArrayLoad(val b: GlobalConfig) extends Module { - val config = SystolicBallParam() - val InputNum = 16 - val bankWidth = b.memDomain.bankWidth + val config = SystolicBallParam() + val InputNum = 16 + val bankWidth = b.memDomain.bankWidth val inputWidth = config.inputWidth val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) - val inBW = ballMapping.inBW + val inBW = ballMapping.inBW @public val io = IO(new Bundle { @@ -39,7 +39,6 @@ class SystolicArrayLoad(val b: GlobalConfig) extends Module { val state = RegInit(idle) val ld_ex_iter_reg = RegInit(0.U(10.W)) - val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala index c13f2dbd..56f01431 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala @@ -13,7 +13,6 @@ class ctrl_st_req(b: GlobalConfig) extends Bundle { val iter = UInt(10.W) } - class BankWriteEntry(b: GlobalConfig) extends Bundle { val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) val data = UInt(b.memDomain.bankWidth.W) @@ -28,7 +27,7 @@ class SystolicArrayStore(val b: GlobalConfig) extends Module { val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) - val outBW = ballMapping.outBW + val outBW = ballMapping.outBW @public val io = IO(new Bundle { diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala index cc168e8d..548c0b80 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala @@ -17,8 +17,6 @@ class ctrl_ld_req(b: GlobalConfig) extends Bundle { val iter = UInt(10.W) } - - @instantiable class SystolicArrayUnit(val b: GlobalConfig) extends Module { val InputNum = 16 @@ -27,8 +25,8 @@ class SystolicArrayUnit(val b: GlobalConfig) extends Module { val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "SystolicArrayBall") .getOrElse(throw new IllegalArgumentException("SystolicArrayBall not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW @public val io = IO(new Bundle { diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala new file mode 100644 index 00000000..2d0bb664 --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -0,0 +1,413 @@ +package framework.core.bbtile + +import chisel3._ +import chisel3.experimental.hierarchy.{Instance, Instantiate} + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile._ +import freechips.rocketchip.devices.tilelink.{BasicBusBlocker, BasicBusBlockerParams} +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, DisableMonitors} +import freechips.rocketchip.resources.{ + Description, + Resource, + ResourceAddress, + ResourceAnchors, + ResourceBinding, + ResourceBindings, + SimpleDevice +} +import freechips.rocketchip.interrupts.IntIdentityNode +import freechips.rocketchip.tilelink.{ + TLBuffer, + TLClientNode, + TLClientParameters, + TLIdentityNode, + TLMasterPortParameters, + TLWidthWidget, + TLXbar +} +import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike +import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters, RationalCrossing} +import freechips.rocketchip.util.{Annotated, InOrderArbiter} +import freechips.rocketchip.util.BooleanToAugmentedBoolean + +import framework.top.GlobalConfig +import framework.core.bbtile.id.RVVRoCCDecode + +/** + * BBTile — a composable tile containing Rocket core(s) + optional Buckyball accelerator(s). + * + * Design principles: + * - Extends BaseTile for CanAttachTile compatibility (diplomacy shell) + * - Mixes in HasHellaCache + HasICacheFrontend for Rocket core infrastructure (unavoidable) + * - Buckyball accelerator is composed as an independent module, NOT via LazyRoCCBB inheritance + * - RoCC cmd/resp are wired directly inside the tile + * - Accelerator TileLink DMA nodes are declared in the diplomacy shell + */ +class BBTile private ( + val bbParams: BBTileParams, + crossing: ClockCrossingType, + lookup: LookupByHartIdImpl, + q: Parameters) + extends BaseTile(bbParams, crossing, lookup, q) + with SinksExternalInterrupts + with SourcesExternalNotifications + with HasHellaCache + with HasICacheFrontend { + + def this( + params: BBTileParams, + crossing: HierarchicalElementCrossingParamsLike, + lookup: LookupByHartIdImpl + )( + implicit p: Parameters + ) = + this(params, crossing.crossingType, lookup, BBTile.injectBuildRoCC(p, params.withBuckyball)) + + // RoCC CSRs — Buckyball doesn't use custom CSRs, so this is always empty + val roccCSRs: Seq[Seq[CustomCSR]] = Nil + + // --------------------------------------------------------------------------- + // Diplomacy nodes — tile boundary + // --------------------------------------------------------------------------- + val intOutwardNode = bbParams.beuAddr.map(_ => IntIdentityNode()) + val slaveNode = TLIdentityNode() + val masterNode = visibilityNode + + // Scratchpad (DTIM) + val dtim_adapter = bbParams.dcache.flatMap { d => + d.scratch.map { s => + LazyModule(new ScratchpadSlavePort( + AddressSet.misaligned(s, d.dataScratchpadBytes), + lazyCoreParamsView.coreDataBytes, + bbParams.core.useAtomics && !bbParams.core.useAtomicsOnlyForIO + )) + } + } + + dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) + + // Bus error unit + val bus_error_unit = bbParams.beuAddr.map { a => + val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen / 8)) + intOutwardNode.get := beu.intNode + connectTLSlave(beu.node, xBytes) + beu + } + + // Master port blocker + val tile_master_blocker = + bbParams.blockerCtrlAddr + .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) + .map(bp => LazyModule(new BasicBusBlocker(bp))) + + tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) + + // --------------------------------------------------------------------------- + // Buckyball accelerator TileLink nodes (diplomacy layer) + // --------------------------------------------------------------------------- + val bbConfig = bbParams.buckyballConfig + + val bb_reader_node = + if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + name = "bb-dma-reader", + sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) + )))))) + else None + + val bb_writer_node = + if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + name = "bb-dma-writer", + sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) + )))))) + else None + + val bb_xbar_node = + if (bbParams.withBuckyball) { + val xbar = TLXbar() + xbar := TLBuffer() := bb_reader_node.get + xbar := TLBuffer() := bb_writer_node.get + Some(xbar) + } else None + + // Connect Buckyball DMA to tile master port (through width widget) + bb_xbar_node.foreach { xbar => + tlOtherMastersNode :=* TLWidthWidget(bbConfig.memDomain.dma_buswidth / 8) := TLBuffer() := xbar + } + + // --------------------------------------------------------------------------- + // TileLink topology + // --------------------------------------------------------------------------- + tlOtherMastersNode := tile_master_blocker.map(_.node := tlMasterXbar.node).getOrElse(tlMasterXbar.node) + masterNode :=* tlOtherMastersNode + DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) + + // DCache port count: core + PTW(via usingVM) + DTIM + vector + nDCachePorts += 1 + (dtim_adapter.isDefined).toInt + + bbParams.core.vector.map(_.useDCache.toInt).getOrElse(0) + + bbParams.withBuckyball.toInt // RoCC mem port (tied off but counted by dcacheArbPorts) + + // --------------------------------------------------------------------------- + // Device tree properties + // --------------------------------------------------------------------------- + val dtimProperty = dtim_adapter.map(d => Map("sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) + val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) + val beuProperty = bus_error_unit.map(d => Map("sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) + + val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { + override def parent = Some(ResourceAnchors.cpus) + + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description( + name, + mapping ++ cpuProperties ++ nextLevelCacheProperty + ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty + ) + } + + } + + // Vector unit (optional) + val vector_unit = bbParams.core.vector.map(v => LazyModule(v.build(p))) + vector_unit.foreach(vu => tlMasterXbar.node :=* vu.atlNode) + vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) + + ResourceBinding { + Resource(cpuDevice, "reg").bind(ResourceAddress(bbParams.tileId)) + } + + // Buckyball needs one PTW port for its TLB + if (bbParams.withBuckyball) { + nPTWPorts += 1 + } + + override lazy val module = new BBTileModuleImp(this) + + override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = + (bbParams.boundaryBuffers, crossing) match { + case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer() + case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => + TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) + case _ => TLBuffer(BufferParams.none) + } + + override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = + (bbParams.boundaryBuffers, crossing) match { + case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer() + case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => + TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) + case _ => TLBuffer(BufferParams.none) + } + +} + +// ============================================================================= +// Module implementation (Chisel layer) +// ============================================================================= +class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasICacheFrontendModule { + + Annotated.params(this, outer.bbParams) + + // --- FPU (optional) --- + val fpuOpt = outer.bbParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) + + // --- Rocket core (using our fork that accepts BBTile) --- + val core = Module(new RocketBB(outer)(outer.p)) + + // Vector unit connections + outer.vector_unit.foreach { v => + core.io.vector.get <> v.module.io.core + v.module.io.tlb <> outer.dcache.module.io.tlb_port + } + + core.io.reset_vector := DontCare + + // Report conditions + outer.reportHalt(List(outer.dcache.module.io.errors)) + outer.reportCease(outer.bbParams.core.clockGate.option( + !outer.dcache.module.io.cpu.clock_enabled && + !outer.frontend.module.io.cpu.clock_enabled && + !ptw.io.dpath.clock_enabled && + core.io.cease + )) + outer.reportWFI(Some(core.io.wfi)) + + // Interrupts + outer.decodeCoreInterrupts(core.io.interrupts) + outer.bus_error_unit.foreach { beu => + core.io.interrupts.buserror.get := beu.module.io.interrupt + beu.module.io.errors.dcache := outer.dcache.module.io.errors + beu.module.io.errors.icache := outer.frontend.module.io.errors + } + core.io.interrupts.nmi.foreach(nmi => nmi := outer.nmiSinkNode.get.bundle) + + // Trace and misc + outer.traceSourceNode.bundle <> core.io.trace + core.io.traceStall := outer.traceAuxSinkNode.bundle.stall + outer.bpwatchSourceNode.bundle <> core.io.bpwatch + core.io.hartid := outer.hartIdSinkNode.bundle + + // Core pipeline connections + outer.frontend.module.io.cpu <> core.io.imem + dcachePorts += core.io.dmem + + // FPU + fpuOpt.foreach { fpu => + core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) + fpu.io.cp_req.valid := false.B + fpu.io.cp_req.bits := DontCare + fpu.io.cp_resp.ready := false.B + } + if (fpuOpt.isEmpty) { + core.io.fpu := DontCare + } + + // Vector unit DCache port + outer.vector_unit.foreach { v => + if (outer.bbParams.core.vector.get.useDCache) { + dcachePorts += v.module.io.dmem + } else { + v.module.io.dmem := DontCare + } + } + + core.io.ptw <> ptw.io.dpath + + // DTIM adapter + outer.dtim_adapter.foreach(lm => dcachePorts += lm.module.io.dmem) + + // --------------------------------------------------------------------------- + // Buckyball accelerator (composed, not inherited via LazyRoCCBB) + // --------------------------------------------------------------------------- + if (outer.bbParams.withBuckyball) { + val (tl_reader, edge_reader) = outer.bb_reader_node.get.out(0) + val (tl_writer, _) = outer.bb_writer_node.get.out(0) + + val buckyball = Module(new BuckyballAccelerator(outer.bbConfig)(edge_reader)) + + // RoCC cmd/resp: direct wiring (both use RoCCCommandBB/RoCCResponseBB) + buckyball.io.cmd <> core.io.rocc.cmd + core.io.rocc.resp <> buckyball.io.resp + core.io.rocc.busy := buckyball.io.busy + core.io.rocc.interrupt := buckyball.io.interrupt + + // DMA TileLink + tl_reader <> buckyball.io.tl_reader + tl_writer <> buckyball.io.tl_writer + + // PTW: Buckyball's BBTLBPTWIO <-> tile's TLBPTWIO (field-by-field adaptation) + val bbPtw = Wire(new TLBPTWIO) + ptwPorts += bbPtw + bbPtw.req.valid := buckyball.io.ptw(0).req.valid + bbPtw.req.bits.valid := buckyball.io.ptw(0).req.bits.valid + bbPtw.req.bits.bits.addr := buckyball.io.ptw(0).req.bits.bits.addr + bbPtw.req.bits.bits.need_gpa := buckyball.io.ptw(0).req.bits.bits.need_gpa + bbPtw.req.bits.bits.vstage1 := buckyball.io.ptw(0).req.bits.bits.vstage1 + bbPtw.req.bits.bits.stage2 := buckyball.io.ptw(0).req.bits.bits.stage2 + buckyball.io.ptw(0).req.ready := bbPtw.req.ready + + buckyball.io.ptw(0).resp.valid := bbPtw.resp.valid + buckyball.io.ptw(0).resp.bits.ae_ptw := bbPtw.resp.bits.ae_ptw + buckyball.io.ptw(0).resp.bits.ae_final := bbPtw.resp.bits.ae_final + buckyball.io.ptw(0).resp.bits.pf := bbPtw.resp.bits.pf + buckyball.io.ptw(0).resp.bits.gf := bbPtw.resp.bits.gf + buckyball.io.ptw(0).resp.bits.hr := bbPtw.resp.bits.hr + buckyball.io.ptw(0).resp.bits.hw := bbPtw.resp.bits.hw + buckyball.io.ptw(0).resp.bits.hx := bbPtw.resp.bits.hx + buckyball.io.ptw(0).resp.bits.pte.ppn := bbPtw.resp.bits.pte.ppn + buckyball.io.ptw(0).resp.bits.pte.reserved_for_future := bbPtw.resp.bits.pte.reserved_for_future + buckyball.io.ptw(0).resp.bits.pte.reserved_for_software := bbPtw.resp.bits.pte.reserved_for_software + buckyball.io.ptw(0).resp.bits.pte.d := bbPtw.resp.bits.pte.d + buckyball.io.ptw(0).resp.bits.pte.a := bbPtw.resp.bits.pte.a + buckyball.io.ptw(0).resp.bits.pte.g := bbPtw.resp.bits.pte.g + buckyball.io.ptw(0).resp.bits.pte.u := bbPtw.resp.bits.pte.u + buckyball.io.ptw(0).resp.bits.pte.x := bbPtw.resp.bits.pte.x + buckyball.io.ptw(0).resp.bits.pte.w := bbPtw.resp.bits.pte.w + buckyball.io.ptw(0).resp.bits.pte.r := bbPtw.resp.bits.pte.r + buckyball.io.ptw(0).resp.bits.pte.v := bbPtw.resp.bits.pte.v + buckyball.io.ptw(0).resp.bits.level := bbPtw.resp.bits.level + buckyball.io.ptw(0).resp.bits.fragmented_superpage := bbPtw.resp.bits.fragmented_superpage + buckyball.io.ptw(0).resp.bits.homogeneous := bbPtw.resp.bits.homogeneous + buckyball.io.ptw(0).resp.bits.gpa.valid := bbPtw.resp.bits.gpa.valid + buckyball.io.ptw(0).resp.bits.gpa.bits := bbPtw.resp.bits.gpa.bits + buckyball.io.ptw(0).resp.bits.gpa_is_pte := bbPtw.resp.bits.gpa_is_pte + + buckyball.io.ptw(0).ptbr.mode := bbPtw.ptbr.mode + buckyball.io.ptw(0).ptbr.asid := bbPtw.ptbr.asid + buckyball.io.ptw(0).ptbr.ppn := bbPtw.ptbr.ppn + buckyball.io.ptw(0).hgatp.mode := bbPtw.hgatp.mode + buckyball.io.ptw(0).hgatp.asid := bbPtw.hgatp.asid + buckyball.io.ptw(0).hgatp.ppn := bbPtw.hgatp.ppn + buckyball.io.ptw(0).vsatp.mode := bbPtw.vsatp.mode + buckyball.io.ptw(0).vsatp.asid := bbPtw.vsatp.asid + buckyball.io.ptw(0).vsatp.ppn := bbPtw.vsatp.ppn + buckyball.io.ptw(0).status := bbPtw.status + buckyball.io.ptw(0).hstatus := bbPtw.hstatus + buckyball.io.ptw(0).gstatus := bbPtw.gstatus + buckyball.io.ptw(0).pmp.zipWithIndex.foreach { case (pmpPort, i) => + pmpPort.cfg.l := bbPtw.pmp(i).cfg.l + pmpPort.cfg.res := bbPtw.pmp(i).cfg.res + pmpPort.cfg.a := bbPtw.pmp(i).cfg.a + pmpPort.cfg.x := bbPtw.pmp(i).cfg.x + pmpPort.cfg.w := bbPtw.pmp(i).cfg.w + pmpPort.cfg.r := bbPtw.pmp(i).cfg.r + pmpPort.addr := bbPtw.pmp(i).addr + pmpPort.mask := bbPtw.pmp(i).mask + } + buckyball.io.ptw(0).customCSRs := DontCare + bbPtw.customCSRs := DontCare + + // TLB exception + buckyball.io.tlbExp(0).flush_skip := false.B + buckyball.io.tlbExp(0).flush_retry := false.B + + // RoCC mem: Buckyball doesn't use the HellaCacheIO mem port, but the + // DCache arbiter still expects a port for it (dcacheArbPorts counts BuildRoCC.size). + // Route through SimpleHellaCacheIF with tied-off requestor side. + val roccMemIF = Module(new SimpleHellaCacheIF()) + roccMemIF.io.requestor.req.valid := false.B + roccMemIF.io.requestor.req.bits := DontCare + roccMemIF.io.requestor.s1_kill := false.B + roccMemIF.io.requestor.s1_data := DontCare + roccMemIF.io.requestor.s2_kill := false.B + roccMemIF.io.requestor.keep_clock_enabled := false.B + dcachePorts += roccMemIF.io.cache + core.io.rocc.mem := DontCare + } else { + // No accelerator — tie off RoCC + core.io.rocc.cmd.ready := false.B + core.io.rocc.resp.valid := false.B + core.io.rocc.resp.bits := DontCare + core.io.rocc.busy := DontCare + core.io.rocc.interrupt := DontCare + core.io.rocc.mem := DontCare + } + + // --- Finalize DCache arbiter and PTW connections (after all ports added) --- + val h = dcachePorts.size + val c = core.dcacheArbPorts + val o = outer.nDCachePorts + require(h == c, s"port list size was $h, core expected $c") + require(h == o, s"port list size was $h, outer counted $o") + + dcacheArb.io.requestor <> dcachePorts.toSeq + ptw.io.requestor <> ptwPorts.toSeq +} + +object BBTile { + + /** + * Inject a dummy BuildRoCC entry so that usingRoCC=true throughout all + * HasRocketCoreParameters mixins (CSR, decode, etc.), without actually + * using the LazyRoCC mechanism. + */ + def injectBuildRoCC(p: Parameters, withBuckyball: Boolean): Parameters = + if (withBuckyball) + p.alterPartial { case BuildRoCC => Seq((_: Parameters) => null.asInstanceOf[LazyRoCC]) } + else p + +} diff --git a/arch/src/main/scala/framework/core/bbtile/BBTileAttach.scala b/arch/src/main/scala/framework/core/bbtile/BBTileAttach.scala new file mode 100644 index 00000000..cd3ead9a --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/BBTileAttach.scala @@ -0,0 +1,10 @@ +package framework.core.bbtile + +import freechips.rocketchip.subsystem.{CanAttachTile, RocketCrossingParams} +import freechips.rocketchip.tile.RocketTile + +/** Attach parameters for BBTile — used in chipyard Config system via TilesLocated. */ +case class BBTileAttachParams( + tileParams: BBTileParams, + crossingParams: RocketCrossingParams) + extends CanAttachTile { type TileType = BBTile } diff --git a/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala b/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala new file mode 100644 index 00000000..6b4c628f --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala @@ -0,0 +1,46 @@ +package framework.core.bbtile + +import freechips.rocketchip.rocket.{BTBParams, DCacheParams, ICacheParams, RocketCoreParams} +import freechips.rocketchip.tile.{InstantiableTileParams, RocketTileBoundaryBufferParams} +import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike +import freechips.rocketchip.prci.ClockSinkParameters +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile.LookupByHartIdImpl +import framework.top.GlobalConfig + +/** + * Parameters for a BBTile. + * + * A BBTile contains N Rocket cores, each optionally paired with a Buckyball accelerator. + * Internal modules use @instantiable + config style; diplomacy is only used for TileLink ports. + */ +case class BBTileParams( + nCores: Int = 1, + withBuckyball: Boolean = true, + core: RocketCoreParams = RocketCoreParams(), + icache: Option[ICacheParams] = Some(ICacheParams()), + dcache: Option[DCacheParams] = Some(DCacheParams()), + btb: Option[BTBParams] = Some(BTBParams()), + buckyballConfig: GlobalConfig = GlobalConfig(), + tileId: Int = 0, + beuAddr: Option[BigInt] = None, + blockerCtrlAddr: Option[BigInt] = None, + clockSinkParams: ClockSinkParameters = ClockSinkParameters(), + boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None) + extends InstantiableTileParams[BBTile] { + require(icache.isDefined) + require(dcache.isDefined) + require(nCores >= 1) + + val baseName = "bbtile" + val uniqueName = s"${baseName}_$tileId" + + def instantiate( + crossing: HierarchicalElementCrossingParamsLike, + lookup: LookupByHartIdImpl + )( + implicit p: Parameters + ): BBTile = + new BBTile(this, crossing, lookup) + +} diff --git a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala similarity index 55% rename from arch/src/main/scala/examples/toy/ToyBuckyBall.scala rename to arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index 0519540d..a4be212f 100644 --- a/arch/src/main/scala/examples/toy/ToyBuckyBall.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -1,104 +1,74 @@ -package examples.toy - -import java.nio.charset.StandardCharsets -import java.nio.file.{Files, Paths} +package framework.core.bbtile import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config._ - -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.tile.{HasCoreParameters, OpcodeSet, TileKey} -import framework.core.rocket.{LazyRoCCBB, LazyRoCCModuleImpBB} -import freechips.rocketchip.tilelink._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.hierarchy.{Instance, Instantiate} +import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.top.GlobalConfig -import examples.toy.balldomain.BallDomain import framework.frontend.Frontend import framework.gpdomain.GpDomain import framework.memdomain.MemDomain -import framework.top.channels.{Channel, ChannelCluster, ChannelIO} - -class ToyBuckyball(val b: GlobalConfig)(implicit p: Parameters) - extends LazyRoCCBB(opcodes = OpcodeSet.custom3, nPTWPorts = 1) { - - val reader_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "bb-dma-reader", - sourceId = freechips.rocketchip.diplomacy.IdRange(0, b.memDomain.dma_n_xacts) - ))))) - - val writer_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "bb-dma-writer", - sourceId = freechips.rocketchip.diplomacy.IdRange(0, b.memDomain.dma_n_xacts) - ))))) - - val xbar_node = TLXbar() - - // Connect reader and writer to xbar - xbar_node := TLBuffer() := reader_node - xbar_node := TLBuffer() := writer_node - - override lazy val module = new ToyBuckyballModule(this) - - // tlNode connects to mbus (bypassing L2 cache) - override val tlNode = TLWidthWidget(b.memDomain.dma_buswidth / 8) := TLBuffer() := xbar_node - - // atlNode is not used (set to identity for compatibility) - override val atlNode = TLIdentityNode() -} - -class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) with HasCoreParameters { - import outer.b._ - val b: GlobalConfig = outer.b - val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum - val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum - // Get TileLink edges from reader and writer nodes - val (tl_reader, edge_reader) = outer.reader_node.out(0) - val (tl_writer, edge_writer) = outer.writer_node.out(0) +import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBPTWIO} +import examples.toy.balldomain.BallDomain +/** + * Standalone Buckyball accelerator module. + * + * Decoupled from the LazyRoCCBB inheritance chain. + * Uses @instantiable + GlobalConfig pattern. + * TileLink bundles are passed in from the tile's diplomacy shell. + * + * @param b GlobalConfig for the accelerator + * @param edge TLEdgeOut from the DMA TileLink nodes (for TLBundle sizing) + */ +@instantiable +class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + + @public + val io = IO(new Bundle { + // RoCC command/response (connected to Rocket core inside tile) + val cmd = Flipped(Decoupled(new RoCCCommandBB(b.core.xLen))) + val resp = Decoupled(new RoCCResponseBB(b.core.xLen)) + val busy = Output(Bool()) + val interrupt = Output(Bool()) + + // PTW interface (shared with Rocket core's PTW) + val ptw = Vec(1, new BBTLBPTWIO(b)) + // TLB exception interface + val tlbExp = Vec(1, new BBTLBExceptionIO) + + // TileLink DMA bundles (from tile's diplomacy nodes) + val tl_reader = new TLBundle(edge.bundle) + val tl_writer = new TLBundle(edge.bundle) + }) + + // --- Instantiate domains --- val frontend: Instance[Frontend] = Instantiate(new Frontend(b)) val ballDomain: Instance[BallDomain] = Instantiate(new BallDomain(b)) - val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge_reader)) + val memDomain: Instance[MemDomain] = Instantiate(new MemDomain(b)(edge)) val gpDomain: Instance[GpDomain] = Instantiate(new GpDomain(b)) + // --- Frontend <- cmd --- frontend.io.cmd.valid := io.cmd.valid frontend.io.cmd.bits.cmd := io.cmd.bits io.cmd.ready := frontend.io.cmd.ready - // Frontend -> BallDomain + // --- Frontend -> BallDomain --- ballDomain.global_issue_i <> frontend.io.ball_issue_o frontend.io.ball_complete_i <> ballDomain.global_complete_o - // Frontend -> MemDomain + // --- Frontend -> MemDomain --- memDomain.io.global_issue_i <> frontend.io.mem_issue_o frontend.io.mem_complete_i <> memDomain.io.global_complete_o - // PTW connected to MemDomain's TLB (shared TLB has only 1 PTW port) - // Connect all fields except customCSRs which is not supported in our BBTLBPTWIO - io.ptw(0).req <> memDomain.io.ptw(0).req - memDomain.io.ptw(0).resp <> io.ptw(0).resp - memDomain.io.ptw(0).ptbr <> io.ptw(0).ptbr - memDomain.io.ptw(0).hgatp <> io.ptw(0).hgatp - memDomain.io.ptw(0).vsatp <> io.ptw(0).vsatp - memDomain.io.ptw(0).status <> io.ptw(0).status - memDomain.io.ptw(0).hstatus <> io.ptw(0).hstatus - memDomain.io.ptw(0).gstatus <> io.ptw(0).gstatus - memDomain.io.ptw(0).pmp <> io.ptw(0).pmp - // customCSRs is tied off - we don't use custom CSRs in our implementation - memDomain.io.ptw(0).customCSRs := DontCare - - // TLB exception handling - shared TLB has only 1 exception interface - // Set flush input signals - memDomain.io.tlbExp(0).flush_skip := false.B - memDomain.io.tlbExp(0).flush_retry := false.B - - // Frontend -> GpDomain + // --- Frontend -> GpDomain --- gpDomain.io.global_issue_i <> frontend.io.gp_issue_o frontend.io.gp_complete_i <> gpDomain.io.global_complete_o - // Break potential combinational loops on bankRead by registering the req channel. - // IDs are queued alongside the req bits to keep them aligned through backpressure. + // --- BallDomain <-> MemDomain (bankRead with pipeline register to break comb loops) --- for (i <- 0 until totalBallRead) { val bankReadReqWithIds = Wire(Decoupled(new Bundle { val bank_id = chiselTypeOf(ballDomain.bankRead(i).bank_id) @@ -131,16 +101,34 @@ class ToyBuckyballModule(outer: ToyBuckyball) extends LazyRoCCModuleImpBB(outer) ballDomain.bankWrite <> memDomain.io.ballDomain.bankWrite - // Connect TileLink DMA ports from MemDomain to LazyModule nodes - tl_reader <> memDomain.io.tl_reader - tl_writer <> memDomain.io.tl_writer + // --- PTW --- + io.ptw(0).req <> memDomain.io.ptw(0).req + memDomain.io.ptw(0).resp <> io.ptw(0).resp + memDomain.io.ptw(0).ptbr <> io.ptw(0).ptbr + memDomain.io.ptw(0).hgatp <> io.ptw(0).hgatp + memDomain.io.ptw(0).vsatp <> io.ptw(0).vsatp + memDomain.io.ptw(0).status <> io.ptw(0).status + memDomain.io.ptw(0).hstatus <> io.ptw(0).hstatus + memDomain.io.ptw(0).gstatus <> io.ptw(0).gstatus + memDomain.io.ptw(0).pmp <> io.ptw(0).pmp + memDomain.io.ptw(0).customCSRs := DontCare + // --- TLB exception --- + memDomain.io.tlbExp(0).flush_skip := false.B + memDomain.io.tlbExp(0).flush_retry := false.B + io.tlbExp(0) <> memDomain.io.tlbExp(0) + + // --- TileLink DMA --- + io.tl_reader <> memDomain.io.tl_reader + io.tl_writer <> memDomain.io.tl_writer + + // --- Response & status --- io.resp <> frontend.io.resp io.busy := frontend.io.busy io.interrupt := memDomain.io.tlbExp(0).interrupt + // --- Busy watchdog --- val busy_counter = RegInit(0.U(32.W)) busy_counter := Mux(frontend.io.busy, busy_counter + 1.U, 0.U) - assert(busy_counter < 10000.U, "ToyBuckyball: busy for too long!") - + assert(busy_counter < 10000.U, "BuckyballAccelerator: busy for too long!") } diff --git a/arch/src/main/scala/framework/core/bbtile/Configs.scala b/arch/src/main/scala/framework/core/bbtile/Configs.scala new file mode 100644 index 00000000..43f7b911 --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/Configs.scala @@ -0,0 +1,74 @@ +package framework.core.bbtile + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.rocket.{BTBParams, DCacheParams, ICacheParams, MulDivParams, RocketCoreParams} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tile.{FPUParams, RocketTileBoundaryBufferParams} +import framework.top.GlobalConfig + +/** + * Config fragment to add N BBTiles. + * + * Each BBTile contains one Rocket core + optional Buckyball accelerator. + */ +object WithNBBTiles { + + private def defaultCrossing(location: HierarchicalLocation): RocketCrossingParams = + RocketCrossingParams( + master = HierarchicalElementMasterPortParams.locationDefault(location), + slave = HierarchicalElementSlavePortParams.locationDefault(location), + mmioBaseAddressPrefixWhere = location match { + case InSubsystem => CBUS + case InCluster(clusterId) => CCBUS(clusterId) + } + ) + +} + +class WithNBBTiles( + n: Int, + location: HierarchicalLocation = InSubsystem, + withBuckyball: Boolean = true, + buckyballConfig: GlobalConfig = GlobalConfig(), + crossing: Option[RocketCrossingParams] = None) + extends Config((site, here, up) => { + case TilesLocated(`location`) => + val prev = up(TilesLocated(`location`), site) + val idOffset = up(NumTiles) + val actualCrossing = crossing.getOrElse(WithNBBTiles.defaultCrossing(location)) + val tileParams = BBTileParams( + withBuckyball = withBuckyball, + buckyballConfig = buckyballConfig, + core = RocketCoreParams( + mulDiv = Some(MulDivParams( + mulUnroll = 8, + mulEarlyOut = true, + divEarlyOut = true + )), + useZba = true, + useZbb = true, + useZbs = true, + fpu = Some(FPUParams(minFLen = 16)) + ), + dcache = Some(DCacheParams( + nSets = 64, + nWays = 8, + rowBits = site(SystemBusKey).beatBits, + nMSHRs = 0, + blockBytes = site(CacheBlockBytes) + )), + icache = Some(ICacheParams( + nSets = 64, + nWays = 8, + rowBits = site(SystemBusKey).beatBits, + blockBytes = site(CacheBlockBytes) + )) + ) + List.tabulate(n)(i => + BBTileAttachParams( + tileParams.copy(tileId = i + idOffset), + actualCrossing + ) + ) ++ prev + case NumTiles => up(NumTiles) + n + }) diff --git a/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala b/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala new file mode 100644 index 00000000..e17559d0 --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala @@ -0,0 +1,48 @@ +package framework.core.bbtile + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile.{CoreBundle, CustomCSRIO} +import freechips.rocketchip.rocket.HellaCacheIO + +/** RoCC command bundle */ +class RoCCCommandBB(xLen: Int = 64) extends Bundle { + val raw_inst = UInt(32.W) + val funct = UInt(7.W) + val rs2 = Bits(5.W) + val rs1 = Bits(5.W) + val xd = Bool() + val xs1 = Bool() + val xs2 = Bool() + val rd = Bits(5.W) + val opcode = UInt(7.W) + val rs1Data = UInt(xLen.W) + val rs2Data = UInt(xLen.W) +} + +/** RoCC response bundle */ +class RoCCResponseBB(xLen: Int = 64) extends Bundle { + val rd = Bits(5.W) + val data = Bits(xLen.W) +} + +/** RoCC interface between a core and an accelerator. */ +class RoCCIO(xLen: Int = 64) extends Bundle { + val cmd = Flipped(Decoupled(new RoCCCommandBB(xLen))) + val resp = Decoupled(new RoCCResponseBB(xLen)) + val busy = Output(Bool()) + val interrupt = Output(Bool()) + val exception = Input(Bool()) +} + +/** RoCC core IO — used inside Rocket core. */ +class RoCCCoreIOBB(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { + val cmd = Flipped(Decoupled(new RoCCCommandBB)) + val resp = Decoupled(new RoCCResponseBB) + val mem = new HellaCacheIO + val busy = Output(Bool()) + val interrupt = Output(Bool()) + val exception = Input(Bool()) + val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) +} diff --git a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala similarity index 99% rename from arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala rename to arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala index c92b681a..6ce50bee 100644 --- a/arch/src/main/scala/framework/core/rocket/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala @@ -1,7 +1,7 @@ // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. -package framework.core.rocket +package framework.core.bbtile import chisel3._ import chisel3.util._ @@ -13,8 +13,7 @@ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer import freechips.rocketchip.rocket._ -import framework.core.rocket.RoCCCoreIOBB -import framework.core.rocket.id.RVVRoCCDecode +import framework.core.bbtile.id.RVVRoCCDecode trait HasRocketCoreIOBB extends HasRocketCoreParameters { implicit val p: Parameters @@ -23,7 +22,7 @@ trait HasRocketCoreIOBB extends HasRocketCoreParameters { val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) - val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParamsBB].beuAddr.isDefined)) + val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[BBTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) @@ -39,11 +38,17 @@ trait HasRocketCoreIOBB extends HasRocketCoreParameters { } -class RocketBB(tile: RocketTileBB)(implicit p: Parameters) +class RocketBB(tile: BBTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIOBB { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size + + // Override usingRoCC: BBTile doesn't use BuildRoCC/LazyRoCC, but when + // withBuckyball is enabled the core must still treat custom instructions as + // RoCC commands. + override val usingRoCC = tile.bbParams.withBuckyball + import ALU._ val clock_en_reg = RegInit(true.B) @@ -158,7 +163,7 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen - val usingRVVRoCC = tile.rocketParams.usingRVVRoCC + val usingRVVRoCC = tile.bbParams.withBuckyball // Ensure usingVector and usingRVVRoCC are mutually exclusive require( @@ -297,7 +302,7 @@ class RocketBB(tile: RocketTileBB)(implicit p: Parameters) perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, - tile.rocketParams.beuAddr.isDefined + tile.bbParams.beuAddr.isDefined )) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) diff --git a/arch/src/main/scala/framework/core/bbtile/id/RVVRoCCDecode.scala b/arch/src/main/scala/framework/core/bbtile/id/RVVRoCCDecode.scala new file mode 100644 index 00000000..c5c6e430 --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/id/RVVRoCCDecode.scala @@ -0,0 +1,31 @@ +package framework.core.bbtile.id + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.rocket._ +import freechips.rocketchip.rocket.Instructions._ +import freechips.rocketchip.rocket.ALU._ +import freechips.rocketchip.rocket.constants.ScalarOpConstants +import freechips.rocketchip.rocket.constants.MemoryOpConstants +import freechips.rocketchip.util._ + +/** RVV -> RoCC decode table. Marks RVV instructions as RoCC so they route to Buckyball. */ +class RVVRoCCDecode(implicit val p: Parameters) extends DecodeConstants with ScalarOpConstants with MemoryOpConstants { + + private val rvvRoCCBase: List[BitPat] = + List(Y, N, Y, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR.N, N, N, N, N) + + val table: Array[(BitPat, List[BitPat])] = Array( + BitPat("b?????????????????????????????????1010111") -> rvvRoCCBase, + BitPat("b?????????????????000?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????101?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????110?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????111?????0000111") -> rvvRoCCBase, + BitPat("b?????????????????000?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????101?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????110?????0100111") -> rvvRoCCBase, + BitPat("b?????????????????111?????0100111") -> rvvRoCCBase + ) + +} diff --git a/arch/src/main/scala/framework/core/rocket/Configs.scala b/arch/src/main/scala/framework/core/rocket/Configs.scala deleted file mode 100644 index e938d71c..00000000 --- a/arch/src/main/scala/framework/core/rocket/Configs.scala +++ /dev/null @@ -1,275 +0,0 @@ -package framework.core.rocket - -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import org.chipsalliance.diplomacy.lazymodule._ - -import freechips.rocketchip.rocket._ -import freechips.rocketchip.prci.{AsynchronousCrossing, ClockCrossingType, RationalCrossing, SynchronousCrossing} -import freechips.rocketchip.subsystem.{ - CBUS, - CCBUS, - CacheBlockBytes, - CloneTileAttachParams, - ClustersLocated, - HierarchicalElementMasterPortParams, - HierarchicalElementSlavePortParams, - HierarchicalLocation, - InCluster, - InSubsystem, - NumTiles, - RocketCrossingParams, - RocketTileAttachParams, - SystemBusKey, - TileAttachConfig, - TilesLocated -} -import freechips.rocketchip.tile.{FPUParams, RocketTileBoundaryBufferParams, RocketTileParams} -import scala.reflect.ClassTag - -import framework.core.rocket.{RocketCrossingParamsBB, RocketTileParamsBB} - -class WithNBuckyballCores( - n: Int, - location: HierarchicalLocation, - crossing: RocketCrossingParams) - extends Config((site, here, up) => { - case TilesLocated(`location`) => { - val prev = up(TilesLocated(`location`), site) - val idOffset = up(NumTiles) - val big = RocketTileParamsBB( - usingRVVRoCC = true, - core = RocketCoreParams( - mulDiv = Some(MulDivParams( - mulUnroll = 8, - mulEarlyOut = true, - divEarlyOut = true - )), - useZba = true, - useZbb = true, - useZbs = true, - fpu = Some(FPUParams(minFLen = 16)) - ), - dcache = Some(DCacheParams( - nSets = 64, - nWays = 8, - rowBits = site(SystemBusKey).beatBits, - nMSHRs = 0, - blockBytes = site(CacheBlockBytes) - )), - icache = Some(ICacheParams( - nSets = 64, - nWays = 8, - rowBits = site(SystemBusKey).beatBits, - blockBytes = site(CacheBlockBytes) - )) - ) - List.tabulate(n)(i => - RocketTileAttachParamsBB( - big.copy(tileId = i + idOffset), - crossing - ) - ) ++ prev - } - case NumTiles => up(NumTiles) + n - }) { - def this(n: Int, location: HierarchicalLocation = InSubsystem) = this( - n, - location, - RocketCrossingParams( - master = HierarchicalElementMasterPortParams.locationDefault(location), - slave = HierarchicalElementSlavePortParams.locationDefault(location), - mmioBaseAddressPrefixWhere = location match { - case InSubsystem => CBUS - case InCluster(clusterId) => CCBUS(clusterId) - } - ) - ) -} - -class RocketTileAttachConfig(f: RocketTileAttachParams => RocketTileAttachParams) - extends TileAttachConfig[RocketTileAttachParams](f) - -class RocketTileConfig(f: RocketTileParams => RocketTileParams) - extends RocketTileAttachConfig(tp => - tp.copy( - tileParams = f(tp.tileParams) - ) - ) - -class RocketCrossingConfig(f: RocketCrossingParams => RocketCrossingParams) - extends RocketTileAttachConfig(tp => - tp.copy( - crossingParams = f(tp.crossingParams) - ) - ) - -class RocketCoreConfig(f: RocketCoreParams => RocketCoreParams) - extends RocketTileConfig(tp => - tp.copy( - core = f(tp.core) - ) - ) - -class RocketICacheConfig(f: ICacheParams => ICacheParams) - extends RocketTileConfig(tp => - tp.copy( - icache = tp.icache.map(ic => f(ic)) - ) - ) - -class RocketDCacheConfig(f: DCacheParams => DCacheParams) - extends RocketTileConfig(tp => - tp.copy( - dcache = tp.dcache.map(dc => f(dc)) - ) - ) - -class WithL1ICacheSets(sets: Int) extends RocketICacheConfig(_.copy(nSets = sets)) -class WithL1ICacheWays(ways: Int) extends RocketICacheConfig(_.copy(nWays = ways)) -class WithL1ICacheECC(dataECC: String, tagECC: String) - extends RocketICacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC))) -class WithL1ICacheRowBits(n: Int) extends RocketICacheConfig(_.copy(rowBits = n)) -class WithL1ICacheTLBSets(sets: Int) extends RocketICacheConfig(_.copy(nTLBSets = sets)) -class WithL1ICacheTLBWays(ways: Int) extends RocketICacheConfig(_.copy(nTLBWays = ways)) -class WithL1ICacheTLBBasePageSectors(sectors: Int) extends RocketICacheConfig(_.copy(nTLBBasePageSectors = sectors)) -class WithL1ICacheTLBSuperpages(superpages: Int) extends RocketICacheConfig(_.copy(nTLBSuperpages = superpages)) -class WithL1ICacheBlockBytes(bytes: Int = 64) extends RocketICacheConfig(_.copy(blockBytes = bytes)) - -class WithL1DCacheSets(sets: Int) extends RocketDCacheConfig(_.copy(nSets = sets)) -class WithL1DCacheWays(ways: Int) extends RocketDCacheConfig(_.copy(nWays = ways)) -class WithL1DCacheECC(dataECC: String, tagECC: String) - extends RocketDCacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC))) -class WithL1DCacheRowBits(n: Int) extends RocketDCacheConfig(_.copy(rowBits = n)) -class WithL1DCacheTLBSets(sets: Int) extends RocketDCacheConfig(_.copy(nTLBSets = sets)) -class WithL1DCacheTLBWays(ways: Int) extends RocketDCacheConfig(_.copy(nTLBWays = ways)) -class WithL1DCacheTLBBasePageSectors(sectors: Int) extends RocketDCacheConfig(_.copy(nTLBBasePageSectors = sectors)) -class WithL1DCacheTLBSuperpages(superpages: Int) extends RocketDCacheConfig(_.copy(nTLBSuperpages = superpages)) -class WithL1DCacheBlockBytes(bytes: Int = 64) extends RocketDCacheConfig(_.copy(blockBytes = bytes)) -class WithL1DCacheNonblocking(nMSHRs: Int) extends RocketDCacheConfig(_.copy(nMSHRs = nMSHRs)) -class WithL1DCacheClockGating extends RocketDCacheConfig(_.copy(clockGate = true)) -class WithL1DCacheDTIMAddress(address: BigInt) extends RocketDCacheConfig(_.copy(scratch = Some(address))) - -class WithScratchpadsOnly - extends RocketTileConfig(tp => - tp.copy( - core = tp.core.copy(useVM = false), - dcache = tp.dcache.map(_.copy( - nSets = 256, // 16Kb scratchpad - nWays = 1, - scratch = Some(0x80000000L) - )) - ) - ) - -class WithCacheRowBits(n: Int) - extends RocketTileConfig(tp => - tp.copy( - dcache = tp.dcache.map(_.copy(rowBits = n)), - icache = tp.icache.map(_.copy(rowBits = n)) - ) - ) - -class WithBEU(addr: BigInt) extends RocketTileConfig(_.copy(beuAddr = Some(addr))) -class WithBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) - extends RocketTileConfig(_.copy(boundaryBuffers = buffers)) - -class WithRV32 - extends RocketCoreConfig(c => - c.copy( - xLen = 32, - pgLevels = 2, // sv32 - fpu = c.fpu.map(_.copy(fLen = 32)), - mulDiv = Some(MulDivParams(mulUnroll = 8)) - ) - ) - -class WithoutVM extends RocketCoreConfig(_.copy(useVM = false)) -class WithCFlushEnabled extends RocketCoreConfig(_.copy(haveCFlush = true)) -class WithNBreakpoints(hwbp: Int) extends RocketCoreConfig(_.copy(nBreakpoints = hwbp)) -class WithHypervisor(hext: Boolean = true) extends RocketCoreConfig(_.copy(useHypervisor = hext)) -class WithCease(enable: Boolean = true) extends RocketCoreConfig(_.copy(haveCease = enable)) -class WithCoreClockGatingEnabled extends RocketCoreConfig(_.copy(clockGate = true)) -class WithPgLevels(n: Int) extends RocketCoreConfig(_.copy(pgLevels = n)) -class WithZba extends RocketCoreConfig(_.copy(useZba = true)) -class WithZbb extends RocketCoreConfig(_.copy(useZbb = true)) -class WithZbs extends RocketCoreConfig(_.copy(useZbs = true)) -class WithB extends RocketCoreConfig(_.copy(useZba = true, useZbb = true, useZbs = true)) -class WithSV48 extends WithPgLevels(4) -class WithSV39 extends WithPgLevels(3) - -// Simulation-only configs -class WithNoSimulationTimeout extends RocketCoreConfig(_.copy(haveSimTimeout = false)) -class WithDebugROB(enable: Boolean = true, size: Int = 0) - extends RocketCoreConfig(_.copy(debugROB = Option.when(enable)(DebugROBParams(size)))) - -// FPU configs -class WithoutFPU extends RocketCoreConfig(_.copy(fpu = None)) -class WithFP16 extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(minFLen = 16)))) -class WithFPUWithoutDivSqrt extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(divSqrt = false)))) - -// mul-div configs -class WithFastMulDiv - extends RocketCoreConfig(c => - c.copy(mulDiv = - Some( - MulDivParams(mulUnroll = 8, mulEarlyOut = c.xLen > 32, divEarlyOut = true) - ) - ) - ) - -class WithCustomFastMulDiv( - mUnroll: Int = 8, - mEarlyOut: Boolean = true, - dUnroll: Int = 1, - dEarlyOut: Boolean = true, - dEarlyOutGranularity: Int = 1) - extends RocketCoreConfig(_.copy(mulDiv = - Some( - MulDivParams( - mulUnroll = mUnroll, - mulEarlyOut = mEarlyOut, - divUnroll = dUnroll, - divEarlyOut = dEarlyOut, - divEarlyOutGranularity = dEarlyOutGranularity - ) - ) - )) - -class WithoutMulDiv extends RocketCoreConfig(_.copy(mulDiv = None)) - -// Branch-prediction configs -class WithDefaultBtb extends RocketTileConfig(t => t.copy(btb = Some(BTBParams()))) -class WithNoBtb extends RocketTileConfig(_.copy(btb = None)) - -// Tile CDC configs -class WithCDC(crossingType: ClockCrossingType = SynchronousCrossing()) - extends RocketCrossingConfig(_.copy(crossingType = crossingType)) -class WithSeperateClockReset extends RocketCrossingConfig(_.copy(forceSeparateClockReset = true)) -class WithSynchronousCDCs extends WithCDC(SynchronousCrossing()) -class WithAsynchronousCDCs(depth: Int, sync: Int) extends WithCDC(AsynchronousCrossing(depth, sync)) -class WithRationalCDCs extends WithCDC(RationalCrossing()) - -class WithCloneRocketTiles( - n: Int = 1, - cloneTileId: Int = 0, - location: HierarchicalLocation = InSubsystem, - cloneLocation: HierarchicalLocation = InSubsystem) - extends Config((site, here, up) => { - case TilesLocated(`location`) => { - val prev = up(TilesLocated(location), site) - val idOffset = up(NumTiles) - val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId) - .get.asInstanceOf[RocketTileAttachParams] - (0 until n).map { i => - CloneTileAttachParams( - cloneTileId, - tileAttachParams.copy( - tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset) - ) - ) - } ++ prev - } - case NumTiles => up(NumTiles) + n - }) diff --git a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala b/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala deleted file mode 100644 index 92207e29..00000000 --- a/arch/src/main/scala/framework/core/rocket/LazyRoCCBB.scala +++ /dev/null @@ -1,176 +0,0 @@ -// See LICENSE.Berkeley for license details. -// See LICENSE.SiFive for license details. - -package framework.core.rocket - -import chisel3._ -import chisel3.util._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ - -import org.chipsalliance.cde.config._ -import org.chipsalliance.diplomacy.lazymodule._ - -import freechips.rocketchip.rocket.{ - CanHavePTW, - CanHavePTWModule, - HellaCacheIO, - MStatus, - M_SZ, - M_XRD, - PRV, - PTE, - SimpleHellaCacheIF, - TLBPTWIO -} -import freechips.rocketchip.tilelink.{TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters, TLNode} -import freechips.rocketchip.util.{BooleanToAugmentedBoolean, InOrderArbiter} - -case object BuildRoCCBB extends Field[Seq[Parameters => LazyRoCCBB]](Nil) - -// Custom simplified RoCC types without implicit Parameters -class RoCCCommandBB(xLen: Int = 64) extends Bundle { - val raw_inst = UInt(32.W) - val funct = UInt(7.W) - val rs2 = Bits(5.W) - val rs1 = Bits(5.W) - val xd = Bool() - val xs1 = Bool() - val xs2 = Bool() - val rd = Bits(5.W) - val opcode = UInt(7.W) - val rs1Data = UInt(xLen.W) - val rs2Data = UInt(xLen.W) - // val status = new MStatus // Reserved - removed as unused -} - -class RoCCResponseBB(xLen: Int = 64) extends Bundle { - val rd = Bits(5.W) - val data = Bits(xLen.W) -} - -class RoCCCoreIOBB(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { - val cmd = Flipped(Decoupled(new RoCCCommandBB)) - val resp = Decoupled(new RoCCResponseBB) - val mem = new HellaCacheIO - val busy = Output(Bool()) - val interrupt = Output(Bool()) - val exception = Input(Bool()) - val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) -} - -class RoCCIOBB(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIOBB(nRoCCCSRs)(p) { - val ptw = Vec(nPTWPorts, new TLBPTWIO) - val fpu_req = Decoupled(new FPInput) - val fpu_resp = Flipped(Decoupled(new FPResult)) -} - -/** Base classes for Diplomatic TL2 RoCC units * */ -abstract class LazyRoCCBB( - val opcodes: OpcodeSet, - val nPTWPorts: Int = 0, - val usesFPU: Boolean = false, - val roccCSRs: Seq[CustomCSR] = Nil -)( - implicit p: Parameters) - extends LazyModule { - val module: LazyRoCCModuleImpBB - require(roccCSRs.map(_.id).toSet.size == roccCSRs.size) - val atlNode: TLNode = TLIdentityNode() - val tlNode: TLNode = TLIdentityNode() - val stlNode: TLNode = TLIdentityNode() -} - -class LazyRoCCModuleImpBB(outer: LazyRoCCBB) extends LazyModuleImp(outer) { - val io = IO(new RoCCIOBB(outer.nPTWPorts, outer.roccCSRs.size)) - io := DontCare -} - -/** Mixins for including RoCC * */ - -trait HasLazyRoCCBB extends CanHavePTW { this: BaseTile => - override def usingRoCC: Boolean = !p(BuildRoCCBB).isEmpty - - override def dcacheArbPorts: Int = - 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCCBB).size + - (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt - - val roccs = p(BuildRoCCBB).map(_(p)) - val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs - require( - roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, - "LazyRoCC instantiations require overlapping CSRs" - ) - roccs.map(_.atlNode).foreach(atl => tlMasterXbar.node :=* atl) - roccs.map(_.tlNode).foreach(tl => tlOtherMastersNode :=* tl) - roccs.map(_.stlNode).foreach(stl => stl :*= tlSlaveXbar.node) - - nPTWPorts += roccs.map(_.nPTWPorts).sum - nDCachePorts += roccs.size -} - -trait HasLazyRoCCModuleBB extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImpBB => - - val (respArb, cmdRouter) = - if (outer.roccs.nonEmpty) { - val respArb = Module(new RRArbiter(new RoCCResponseBB(coreParams.xLen), outer.roccs.size)) - // Get usingRVVRoCC from tile parameters - val usingRVVRoCC = outer.rocketParams.asInstanceOf[RocketTileParamsBB].usingRVVRoCC - val cmdRouter = Module(new RoccCommandRouterBB(outer.roccs.map(_.opcodes), usingRVVRoCC)(outer.p)) - outer.roccs.zipWithIndex.foreach { - case (rocc, i) => - rocc.module.io.ptw ++=: ptwPorts - rocc.module.io.cmd <> cmdRouter.io.out(i) - val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) - dcIF.io.requestor <> rocc.module.io.mem - dcachePorts += dcIF.io.cache - respArb.io.in(i) <> Queue(rocc.module.io.resp) - } - (Some(respArb), Some(cmdRouter)) - } else { - (None, None) - } - - val roccCSRIOs = outer.roccs.map(_.module.io.csrs) -} - -class RoccCommandRouterBB(opcodes: Seq[OpcodeSet], usingRVVRoCC: Boolean)(implicit p: Parameters) - extends CoreModule()(p) { - - val io = IO(new Bundle { - val in = Flipped(Decoupled(new RoCCCommandBB)) - val out = Vec(opcodes.size, Decoupled(new RoCCCommandBB)) - val busy = Output(Bool()) - }) - - val cmd = Queue(io.in) - - // Check which opcodes match - val opcodeMatches = opcodes.map(opcode => opcode.matches(cmd.bits.opcode)) - val anyMatch = opcodeMatches.reduce(_ || _) - - val cmdReadys = io.out.zip(opcodeMatches).zipWithIndex.map { - case ((out, matches), i) => - // In RVVRoCC mode: route unmatched opcodes to first RoCC (index 0) - // Otherwise: only route if opcode matches - val shouldRoute = - if (usingRVVRoCC && i == 0) { - matches || !anyMatch // First RoCC gets matched opcodes OR unmatched opcodes - } else { - matches // Other RoCCs only get their matched opcodes - } - - out.valid := cmd.valid && shouldRoute - out.bits := cmd.bits - out.ready && shouldRoute - } - - cmd.ready := cmdReadys.reduce(_ || _) - io.busy := cmd.valid - - // In RVVRoCC mode, allow unmatched opcodes to go to first RoCC - // Otherwise, assert that only one RoCC matches - if (!usingRVVRoCC) { - assert(PopCount(cmdReadys) <= 1.U, "Custom opcode matched for more than one accelerator") - } -} diff --git a/arch/src/main/scala/framework/core/rocket/RocketSubsystem.scala b/arch/src/main/scala/framework/core/rocket/RocketSubsystem.scala deleted file mode 100644 index 94865181..00000000 --- a/arch/src/main/scala/framework/core/rocket/RocketSubsystem.scala +++ /dev/null @@ -1,65 +0,0 @@ -// See LICENSE.SiFive for license details. - -package framework.core.rocket - -import org.chipsalliance.cde.config._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug.HasPeripheryDebug -import freechips.rocketchip.devices.tilelink.{CanHavePeripheryCLINT, CanHavePeripheryPLIC} -import freechips.rocketchip.prci.{ClockCrossingType, NoResetCrossing, ResetCrossingType, SynchronousCrossing} -import freechips.rocketchip.tile.{RocketTile, RocketTileParams} -import freechips.rocketchip.util.HasCoreMonitorBundles - -import framework.core.rocket._ - -// currently, this RocketCrossingParamsBB is not used, we use the default RocketCrossingParams -case class RocketCrossingParamsBB( - crossingType: ClockCrossingType = SynchronousCrossing(), - master: HierarchicalElementPortParamsLike = HierarchicalElementMasterPortParams(), - slave: HierarchicalElementSlavePortParams = HierarchicalElementSlavePortParams(), - mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS, - resetCrossingType: ResetCrossingType = NoResetCrossing(), - forceSeparateClockReset: Boolean = false) - extends HierarchicalElementCrossingParamsLike - -case class RocketTileAttachParams( - tileParams: RocketTileParams, - crossingParams: RocketCrossingParams) - extends CanAttachTile { type TileType = RocketTile } - -case class RocketTileAttachParamsBB( - tileParams: RocketTileParamsBB, - crossingParams: RocketCrossingParams) - extends CanAttachTile { type TileType = RocketTileBB } - -trait HasRocketTiles { - this: BaseSubsystem with InstantiatesHierarchicalElements => - val rocketTiles = totalTiles.values.collect { case r: RocketTile => r } - - def coreMonitorBundles = (rocketTiles map { t => - t.module.core.rocketImpl.coreMonitorBundle - }).toList - -} - -class RocketSubsystem(implicit p: Parameters) - extends BaseSubsystem - with InstantiatesHierarchicalElements - with HasTileNotificationSinks - with HasTileInputConstants - with CanHavePeripheryCLINT - with CanHavePeripheryPLIC - with HasPeripheryDebug - with HasHierarchicalElementsRootContext - with HasHierarchicalElements - with HasCoreMonitorBundles - with HasRocketTiles { - override lazy val module = new RocketSubsystemModuleImp(this) -} - -class RocketSubsystemModuleImp[+L <: RocketSubsystem](_outer: L) - extends BaseSubsystemModuleImp(_outer) - with HasHierarchicalElementsRootContextModuleImp { - override lazy val outer = _outer -} diff --git a/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala b/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala deleted file mode 100644 index 4a1614b6..00000000 --- a/arch/src/main/scala/framework/core/rocket/RocketTileBB.scala +++ /dev/null @@ -1,326 +0,0 @@ -// See LICENSE.SiFive for license details. -// See LICENSE.Berkeley for license details. - -package framework.core.rocket - -import chisel3._ - -import org.chipsalliance.cde.config._ -import org.chipsalliance.diplomacy.lazymodule._ -import freechips.rocketchip.rocket._ -import freechips.rocketchip.tile._ - -import freechips.rocketchip.devices.tilelink.{BasicBusBlocker, BasicBusBlockerParams} -import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, DisableMonitors} -import freechips.rocketchip.resources.{ - Description, - Resource, - ResourceAddress, - ResourceAnchors, - ResourceBinding, - ResourceBindings, - SimpleDevice -} -import freechips.rocketchip.interrupts.IntIdentityNode -import freechips.rocketchip.tilelink.{TLBuffer, TLIdentityNode} -import freechips.rocketchip.rocket.{ - BTBParams, - DCacheParams, - HasHellaCache, - HasICacheFrontend, - HasICacheFrontendModule, - ICacheParams, - Rocket, - RocketCoreParams, - ScratchpadSlavePort -} -import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike -import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters, RationalCrossing} -import freechips.rocketchip.util.{Annotated, InOrderArbiter} - -import freechips.rocketchip.util.BooleanToAugmentedBoolean - -case class RocketTileBoundaryBufferParams(force: Boolean = false) - -case class RocketTileParamsBB( - core: RocketCoreParams = RocketCoreParams(), - icache: Option[ICacheParams] = Some(ICacheParams()), - dcache: Option[DCacheParams] = Some(DCacheParams()), - btb: Option[BTBParams] = Some(BTBParams()), - dataScratchpadBytes: Int = 0, - tileId: Int = 0, - beuAddr: Option[BigInt] = None, - blockerCtrlAddr: Option[BigInt] = None, - clockSinkParams: ClockSinkParameters = ClockSinkParameters(), - boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None, - usingRVVRoCC: Boolean = false) - extends InstantiableTileParams[RocketTileBB] { - require(icache.isDefined) - require(dcache.isDefined) - val baseName = "rockettile" - val uniqueName = s"${baseName}_$tileId" - - def instantiate( - crossing: HierarchicalElementCrossingParamsLike, - lookup: LookupByHartIdImpl - )( - implicit p: Parameters - ): RocketTileBB = - new RocketTileBB(this, crossing, lookup) - -} - -class RocketTileBB private ( - val rocketParams: RocketTileParamsBB, - crossing: ClockCrossingType, - lookup: LookupByHartIdImpl, - q: Parameters) - extends BaseTile(rocketParams, crossing, lookup, q) - with SinksExternalInterrupts - with SourcesExternalNotifications - with HasLazyRoCCBB - with HasHellaCache - with HasICacheFrontend { - // Private constructor ensures altered LazyModule.p is used implicitly - def this( - params: RocketTileParamsBB, - crossing: HierarchicalElementCrossingParamsLike, - lookup: LookupByHartIdImpl - )( - implicit p: Parameters - ) = - this(params, crossing.crossingType, lookup, p) - - val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } - val slaveNode = TLIdentityNode() - val masterNode = visibilityNode - - val dtim_adapter = rocketParams.dcache.flatMap { d => - d.scratch.map { s => - LazyModule(new ScratchpadSlavePort( - AddressSet.misaligned(s, d.dataScratchpadBytes), - lazyCoreParamsView.coreDataBytes, - rocketParams.core.useAtomics && !rocketParams.core.useAtomicsOnlyForIO - )) - } - } - - dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) - - val bus_error_unit = rocketParams.beuAddr map { a => - val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen / 8)) - intOutwardNode.get := beu.intNode - connectTLSlave(beu.node, xBytes) - beu - } - - val tile_master_blocker = - rocketParams.blockerCtrlAddr - .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) - .map(bp => LazyModule(new BasicBusBlocker(bp))) - - tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) - - // TODO: this doesn't block other masters, e.g. RoCCs - tlOtherMastersNode := tile_master_blocker.map(_.node := tlMasterXbar.node) getOrElse { tlMasterXbar.node } - masterNode :=* tlOtherMastersNode - DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) - - nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map( - _.useDCache.toInt - ).getOrElse(0) - - val dtimProperty = dtim_adapter.map(d => - Map( - "sifive,dtim" -> d.device.asProperty - ) - ).getOrElse(Nil) - - val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) - - val beuProperty = bus_error_unit.map(d => - Map( - "sifive,buserror" -> d.device.asProperty - ) - ).getOrElse(Nil) - - val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { - override def parent = Some(ResourceAnchors.cpus) - - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - Description( - name, - mapping ++ cpuProperties ++ nextLevelCacheProperty - ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty - ) - } - - } - - val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) - vector_unit.foreach(vu => tlMasterXbar.node :=* vu.atlNode) - vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) - - ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(rocketParams.tileId)) - } - - override lazy val module = new RocketTileModuleImpBB(this) - - override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = - (rocketParams.boundaryBuffers, crossing) match { - case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer() - case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => - TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) - case _ => TLBuffer(BufferParams.none) - } - - override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = - (rocketParams.boundaryBuffers, crossing) match { - case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer() - case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => - TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) - case _ => TLBuffer(BufferParams.none) - } - -} - -class RocketTileModuleImpBB(outer: RocketTileBB) - extends BaseTileModuleImp(outer) - with HasFpuOptBB - with HasLazyRoCCModuleBB - with HasICacheFrontendModule { - Annotated.params(this, outer.rocketParams) - - val modifiedP = outer.p.alterMap(Map( - BuildRoCC -> (outer.p(BuildRoCC) ++ outer.p(BuildRoCCBB).map(f => - (p: Parameters) => f(p).asInstanceOf[freechips.rocketchip.tile.LazyRoCC] - )) - )) - - val core = Module(new RocketBB(outer)(modifiedP)) - outer.vector_unit.foreach { v => - core.io.vector.get <> v.module.io.core - v.module.io.tlb <> outer.dcache.module.io.tlb_port - } - - // reset vector is connected in the Frontend to s2_pc - core.io.reset_vector := DontCare - - // Report unrecoverable error conditions; for now the only cause is cache ECC errors - outer.reportHalt(List(outer.dcache.module.io.errors)) - - // Report when the tile has ceased to retire instructions; for now the only cause is clock gating - outer.reportCease(outer.rocketParams.core.clockGate.option( - !outer.dcache.module.io.cpu.clock_enabled && - !outer.frontend.module.io.cpu.clock_enabled && - !ptw.io.dpath.clock_enabled && - core.io.cease - )) - - outer.reportWFI(Some(core.io.wfi)) - - outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector - - outer.bus_error_unit.foreach { beu => - core.io.interrupts.buserror.get := beu.module.io.interrupt - beu.module.io.errors.dcache := outer.dcache.module.io.errors - beu.module.io.errors.icache := outer.frontend.module.io.errors - } - - core.io.interrupts.nmi.foreach(nmi => nmi := outer.nmiSinkNode.get.bundle) - - // Pass through various external constants and reports that were bundle-bridged into the tile - outer.traceSourceNode.bundle <> core.io.trace - core.io.traceStall := outer.traceAuxSinkNode.bundle.stall - outer.bpwatchSourceNode.bundle <> core.io.bpwatch - core.io.hartid := outer.hartIdSinkNode.bundle - require( - core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, - s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)" - ) - - // Connect the core pipeline to other intra-tile modules - outer.frontend.module.io.cpu <> core.io.imem - dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? - fpuOpt foreach { fpu => - core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) - } - if (fpuOpt.isEmpty) { - core.io.fpu := DontCare - } - outer.vector_unit foreach { v => - if (outer.rocketParams.core.vector.get.useDCache) { - dcachePorts += v.module.io.dmem - } else { - v.module.io.dmem := DontCare - } - } - core.io.ptw <> ptw.io.dpath - - // Connect the coprocessor interfaces - if (outer.roccs.size > 0) { - cmdRouter.get.io.in <> core.io.rocc.cmd - outer.roccs.foreach { lm => - lm.module.io.exception := core.io.rocc.exception - lm.module.io.fpu_req.ready := DontCare - lm.module.io.fpu_resp.valid := DontCare - lm.module.io.fpu_resp.bits.data := DontCare - lm.module.io.fpu_resp.bits.exc := DontCare - } - core.io.rocc.resp <> respArb.get.io.out - core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _)) - core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _) - (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach(t => t._2 <> t._1) - } else { - // tie off - core.io.rocc.cmd.ready := false.B - core.io.rocc.resp.valid := false.B - core.io.rocc.resp.bits := DontCare - core.io.rocc.busy := DontCare - core.io.rocc.interrupt := DontCare - } - // Dont care mem since not all RoCC need accessing memory - core.io.rocc.mem := DontCare - - // Rocket has higher priority to DTIM than other TileLink clients - outer.dtim_adapter.foreach(lm => dcachePorts += lm.module.io.dmem) - - // TODO eliminate this redundancy - val h = dcachePorts.size - val c = core.dcacheArbPorts - val o = outer.nDCachePorts - require(h == c, s"port list size was $h, core expected $c") - require(h == o, s"port list size was $h, outer counted $o") - // TODO figure out how to move the below into their respective mix-ins - dcacheArb.io.requestor <> dcachePorts.toSeq - ptw.io.requestor <> ptwPorts.toSeq -} - -trait HasFpuOptBB { this: RocketTileModuleImpBB => - val fpuOpt = outer.rocketParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) - fpuOpt.foreach { fpu => - val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) - val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt - if (nFPUPorts > 0) { - val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) - fpu.io.cp_req <> fpArb.io.out_req - fpArb.io.out_resp <> fpu.io.cp_resp - - val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io) - for (i <- 0 until nRoCCFPUPorts) { - fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req - fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) - } - outer.vector_unit.foreach { vu => - fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req - vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) - } - } else { - fpu.io.cp_req.valid := false.B - fpu.io.cp_req.bits := DontCare - fpu.io.cp_resp.ready := false.B - } - } -} diff --git a/arch/src/main/scala/framework/core/rocket/id/RVVRoCCDecode.scala b/arch/src/main/scala/framework/core/rocket/id/RVVRoCCDecode.scala deleted file mode 100644 index fe8dda6a..00000000 --- a/arch/src/main/scala/framework/core/rocket/id/RVVRoCCDecode.scala +++ /dev/null @@ -1,76 +0,0 @@ -// See LICENSE.Berkeley for license details. -// See LICENSE.SiFive for license details. - -package framework.core.rocket.id - -import chisel3._ -import chisel3.util._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.rocket._ -import freechips.rocketchip.rocket.Instructions._ -import freechips.rocketchip.rocket.ALU._ -import freechips.rocketchip.rocket.constants.ScalarOpConstants -import freechips.rocketchip.rocket.constants.MemoryOpConstants -import freechips.rocketchip.util._ - -/** - * RVVRoCCDecode - Decoder for RVV (RISC-V Vector) instructions marked as RoCC - * - * This decoder takes standard RVV instructions and marks them as RoCC instructions, - * allowing them to be handled by a RoCC accelerator instead of the built-in vector unit. - * - * Usage: Enable by setting usingRVVRoCC parameter to true in RocketTileParamsBB - * Note: usingVector and usingRVVRoCC cannot both be true simultaneously - * - * This decoder uses opcode-based matching patterns instead of listing all 447 RVV instructions - * individually to avoid JVM method size limits and memory issues during decode minimization. - * - * RVV instruction opcodes: - * - 1010111 (0x57): V-type arithmetic/logic instructions, vector config - * - 0000111 (0x07): Vector load instructions (funct3 != 010) - * - 0100111 (0x27): Vector store instructions (funct3 != 010) - * - * Note: This decoder uses wildcard patterns that may match invalid encodings. - * The RoCC accelerator should validate instructions and handle illegal opcodes appropriately. - */ -class RVVRoCCDecode(implicit val p: Parameters) extends DecodeConstants with ScalarOpConstants with MemoryOpConstants { - import freechips.rocketchip.rocket.Instructions._ - - // Common decode signals for RVV instructions (rocc field set to Y) - // Most RVV instructions don't read scalar registers by default (overridden by specific patterns) - private val rvvRoCCBase: List[BitPat] = - List(Y, N, Y, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR.N, N, N, N, N) - - // Vector configuration instructions need wxd=Y and may read rs1 - private val vcfgSigs: List[BitPat] = - List(Y, N, Y, N, N, N, N, Y, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, Y, CSR.N, N, N, N, N) - private val vcfgImmSigs: List[BitPat] = - List(Y, N, Y, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, Y, CSR.N, N, N, N, N) - - val table: Array[(BitPat, List[BitPat])] = Array( - // All V-type instructions (opcode = 1010111) - // This includes VSETVL, VSETVLI, VSETIVLI and all arithmetic/logic vector instructions - // Note: VSET* instructions should ideally have wxd=Y and rxs1=Y, but we use uniform - // decode signals here to avoid pattern overlap issues. The RoCC accelerator should - // handle the detailed decoding of vset instructions. - BitPat("b?????????????????????????????????1010111") -> rvvRoCCBase, - // Vector load instructions (opcode = 0000111, funct3 = 000/101/110/111) - // funct3=101: VLE16, VLE256, etc. - // funct3=110: VLE32, VLE512, etc. - // funct3=111: VLE64, VLE1024, etc. - BitPat("b?????????????????000?????0000111") -> rvvRoCCBase, - BitPat("b?????????????????101?????0000111") -> rvvRoCCBase, - BitPat("b?????????????????110?????0000111") -> rvvRoCCBase, - BitPat("b?????????????????111?????0000111") -> rvvRoCCBase, - // Vector store instructions (opcode = 0100111, but NOT funct3=010 which is FP store) - // funct3=000: VSE8, VSE128, VS*R, etc. - // funct3=101: VSE16, VSE256, etc. - // funct3=110: VSE32, VSE512, etc. - // funct3=111: VSE64, VSE1024, etc. - BitPat("b?????????????????000?????0100111") -> rvvRoCCBase, - BitPat("b?????????????????101?????0100111") -> rvvRoCCBase, - BitPat("b?????????????????110?????0100111") -> rvvRoCCBase, - BitPat("b?????????????????111?????0100111") -> rvvRoCCBase - ) - -} diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala index 3b64fac3..d3dc86d7 100644 --- a/arch/src/main/scala/framework/frontend/Frontend.scala +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -6,7 +6,7 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.frontend.decoder.{GlobalDecoder, PostGDCmd} import framework.frontend.globalrs.{GlobalReservationStation, GlobalRsComplete, GlobalRsIssue} import framework.top.GlobalConfig -import framework.core.rocket.{RoCCCommandBB, RoCCResponseBB} +import framework.core.bbtile.{RoCCCommandBB, RoCCResponseBB} /** * Frontend Module diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index b4fe4d44..5d09bfaf 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -13,7 +13,7 @@ import framework.memdomain.frontend.cmd_channel.decoder.DISA._ import framework.gpdomain.sequencer.decoder.DISA._ import framework.frontend.scoreboard.BankAccessInfo -import framework.core.rocket.RoCCCommandBB +import framework.core.bbtile.RoCCCommandBB class BuckyballRawCmd(val b: GlobalConfig) extends Bundle { val cmd = new RoCCCommandBB(b.core.xLen) diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 91e0d4c4..535fa234 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -8,7 +8,7 @@ import framework.top.GlobalConfig import framework.frontend.decoder.{DomainId, PostGDCmd} import framework.frontend.decoder.GISA._ import framework.frontend.scoreboard.{BankAccessInfo, BankScoreboard} -import framework.core.rocket.RoCCResponseBB +import framework.core.bbtile.RoCCResponseBB // Global ROB entry - contains instruction + bank access info class GlobalRobEntry(val b: GlobalConfig) extends Bundle { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala index 928c06da..87995075 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DISA.scala @@ -2,7 +2,7 @@ package framework.gpdomain.sequencer.decoder import chisel3._ import chisel3.util._ -import framework.core.rocket.RoCCCommandBB +import framework.core.bbtile.RoCCCommandBB import framework.top.GlobalConfig object DISA { diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala index 91cfa20d..bf4b7dba 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/decoder/DomainDecoder.scala @@ -3,7 +3,7 @@ package framework.gpdomain.sequencer.decoder import chisel3._ import chisel3.util._ import framework.top.GlobalConfig -import framework.core.rocket.RoCCCommandBB +import framework.core.bbtile.RoCCCommandBB import framework.gpdomain.sequencer.decoder.{Decoder, DecoderParam} import chisel3.experimental.hierarchy.{instantiable, public} diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 0a30909c..99dd22fc 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -26,7 +26,7 @@ class MemBackend(val b: GlobalConfig) extends Module { privateBackend.io.mem_req <> io.mem_req privateBackend.io.config <> io.config privateBackend.io.query_vbank_id := io.query_vbank_id - io.query_group_count := privateBackend.io.query_group_count + io.query_group_count := privateBackend.io.query_group_count // Shared backend is intentionally not connected at top-level in this refactor // to avoid private-path regressions. It can be integrated in a later step. diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index 988257f8..f5ef03fb 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -7,89 +7,89 @@ import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadResp, SramWriteResp} class SharedMemReadReq(val b: GlobalConfig) extends Bundle { - val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) - val group_id = UInt(3.W) - val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val group_id = UInt(3.W) + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) } class SharedMemWriteReq(val b: GlobalConfig) extends Bundle { - val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) - val group_id = UInt(3.W) - val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) - val mask = Vec(b.memDomain.bankMaskLen, Bool()) - val data = UInt(b.memDomain.bankWidth.W) - val wmode = Bool() + val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val group_id = UInt(3.W) + val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) + val mask = Vec(b.memDomain.bankMaskLen, Bool()) + val data = UInt(b.memDomain.bankWidth.W) + val wmode = Bool() } class SharedMemReadIO(val b: GlobalConfig) extends Bundle { - val req = Flipped(Decoupled(new SharedMemReadReq(b))) - val resp = Decoupled(new SramReadResp(b)) + val req = Flipped(Decoupled(new SharedMemReadReq(b))) + val resp = Decoupled(new SramReadResp(b)) } class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { - val req = Flipped(Decoupled(new SharedMemWriteReq(b))) - val resp = Decoupled(new SramWriteResp(b)) + val req = Flipped(Decoupled(new SharedMemWriteReq(b))) + val resp = Decoupled(new SramWriteResp(b)) } @instantiable class SharedMem(val b: GlobalConfig) extends Module { - private val maxGroup = 8 - private val mask_len = b.memDomain.bankMaskLen - private val mask_elem = UInt((b.memDomain.bankWidth / mask_len).W) - private val minSharedLines = b.memDomain.bankNum * maxGroup * b.memDomain.bankEntries - - require( - b.memDomain.sharedEntries >= minSharedLines, - s"sharedEntries=${b.memDomain.sharedEntries} is too small, minimum=$minSharedLines" - ) - - @public - val io = IO(new Bundle { - val read = new SharedMemReadIO(b) - val write = new SharedMemWriteIO(b) - }) - - val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(mask_len, mask_elem)) - - // Shared memory address mapping: - // shared_addr = ((vbank_id * MAX_GROUP + group_id) * bankEntries) + local_addr - private def toSharedAddr(vbank_id: UInt, group_id: UInt, local_addr: UInt): UInt = { - val vbankPart = vbank_id * (maxGroup * b.memDomain.bankEntries).U - val groupPart = group_id * b.memDomain.bankEntries.U - vbankPart + groupPart + local_addr - } - - io.read.req.ready := !io.write.req.valid - io.write.req.ready := !io.read.req.valid - - val readReqFire = io.read.req.fire - val readAddr = toSharedAddr(io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) - - when(readReqFire) { - assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") - assert(io.read.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") - assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") - } - - val readData = mem.read(readAddr, readReqFire) - - io.read.resp.valid := RegNext(readReqFire, init = false.B) - io.read.resp.bits.data := readData.asUInt - - val writeReqFire = io.write.req.fire - val writeAddr = toSharedAddr(io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) - - when(writeReqFire) { - assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") - assert(io.write.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") - assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") - mem.write( - writeAddr, - io.write.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), - io.write.req.bits.mask - ) - } - - io.write.resp.valid := RegNext(writeReqFire, init = false.B) - io.write.resp.bits.ok := RegNext(writeReqFire, init = false.B) -} \ No newline at end of file + private val maxGroup = 8 + private val mask_len = b.memDomain.bankMaskLen + private val mask_elem = UInt((b.memDomain.bankWidth / mask_len).W) + private val minSharedLines = b.memDomain.bankNum * maxGroup * b.memDomain.bankEntries + + require( + b.memDomain.sharedEntries >= minSharedLines, + s"sharedEntries=${b.memDomain.sharedEntries} is too small, minimum=$minSharedLines" + ) + + @public + val io = IO(new Bundle { + val read = new SharedMemReadIO(b) + val write = new SharedMemWriteIO(b) + }) + + val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(mask_len, mask_elem)) + + // Shared memory address mapping: + // shared_addr = ((vbank_id * MAX_GROUP + group_id) * bankEntries) + local_addr + private def toSharedAddr(vbank_id: UInt, group_id: UInt, local_addr: UInt): UInt = { + val vbankPart = vbank_id * (maxGroup * b.memDomain.bankEntries).U + val groupPart = group_id * b.memDomain.bankEntries.U + vbankPart + groupPart + local_addr + } + + io.read.req.ready := !io.write.req.valid + io.write.req.ready := !io.read.req.valid + + val readReqFire = io.read.req.fire + val readAddr = toSharedAddr(io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) + + when(readReqFire) { + assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.read.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") + assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + } + + val readData = mem.read(readAddr, readReqFire) + + io.read.resp.valid := RegNext(readReqFire, init = false.B) + io.read.resp.bits.data := readData.asUInt + + val writeReqFire = io.write.req.fire + val writeAddr = toSharedAddr(io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) + + when(writeReqFire) { + assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.write.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") + assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + mem.write( + writeAddr, + io.write.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), + io.write.req.bits.mask + ) + } + + io.write.resp.valid := RegNext(writeReqFire, init = false.B) + io.write.resp.bits.ok := RegNext(writeReqFire, init = false.B) +} diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index ca1c195f..8d10d775 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -32,8 +32,8 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val query_group_count = Output(UInt(4.W)) }) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) - val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) // Keep per-vbank logical group count so shared path can expose the same // query semantics expected by loader/storer loops. @@ -101,14 +101,18 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { sharedReqArb.io.in(i).bits.is_write := useWrite sharedReqArb.io.in(i).bits.vbank_id := io.mem_req(i).bank_id sharedReqArb.io.in(i).bits.group_id := io.mem_req(i).group_id - sharedReqArb.io.in(i).bits.addr := Mux( + sharedReqArb.io.in(i).bits.addr := Mux( useRead, accPipes(i).io.sramRead.req.bits.addr, accPipes(i).io.sramWrite.req.bits.addr ) - sharedReqArb.io.in(i).bits.mask := Mux(useRead, VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)), accPipes(i).io.sramWrite.req.bits.mask) - sharedReqArb.io.in(i).bits.data := Mux(useRead, 0.U, accPipes(i).io.sramWrite.req.bits.data) - sharedReqArb.io.in(i).bits.wmode := Mux(useRead, false.B, accPipes(i).io.sramWrite.req.bits.wmode) + sharedReqArb.io.in(i).bits.mask := Mux( + useRead, + VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)), + accPipes(i).io.sramWrite.req.bits.mask + ) + sharedReqArb.io.in(i).bits.data := Mux(useRead, 0.U, accPipes(i).io.sramWrite.req.bits.data) + sharedReqArb.io.in(i).bits.wmode := Mux(useRead, false.B, accPipes(i).io.sramWrite.req.bits.wmode) when(routeShared && useRead) { accPipes(i).io.sramRead.req.ready := sharedReqArb.io.in(i).ready @@ -119,27 +123,27 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { } // Keep one in-flight request per response type so source-channel mapping is exact. - val readReqPending = RegInit(false.B) - val writeReqPending = RegInit(false.B) - val readReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - val writeReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + val readReqPending = RegInit(false.B) + val writeReqPending = RegInit(false.B) + val readReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + val writeReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - val readRespBufValid = RegInit(false.B) - val readRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - val readRespBufData = Reg(UInt(b.memDomain.bankWidth.W)) + val readRespBufValid = RegInit(false.B) + val readRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) + val readRespBufData = Reg(UInt(b.memDomain.bankWidth.W)) val writeRespBufValid = RegInit(false.B) val writeRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) val writeRespBufOk = Reg(Bool()) - val arbIsWrite = sharedReqArb.io.out.bits.is_write + val arbIsWrite = sharedReqArb.io.out.bits.is_write val canIssueRead = !readReqPending && !readRespBufValid val canIssueWrite = !writeReqPending && !writeRespBufValid - sharedMem.io.read.req.valid := sharedReqArb.io.out.valid && !arbIsWrite && canIssueRead - sharedMem.io.read.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id - sharedMem.io.read.req.bits.group_id := sharedReqArb.io.out.bits.group_id - sharedMem.io.read.req.bits.addr := sharedReqArb.io.out.bits.addr + sharedMem.io.read.req.valid := sharedReqArb.io.out.valid && !arbIsWrite && canIssueRead + sharedMem.io.read.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id + sharedMem.io.read.req.bits.group_id := sharedReqArb.io.out.bits.group_id + sharedMem.io.read.req.bits.addr := sharedReqArb.io.out.bits.addr sharedMem.io.write.req.valid := sharedReqArb.io.out.valid && arbIsWrite && canIssueWrite sharedMem.io.write.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala index 1a35e748..6a13e2ee 100644 --- a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -6,22 +6,22 @@ import upickle.default._ * MemDomain参数 */ case class MemDomainParam( - bankNum: Int, - bankWidth: Int, - bankEntries: Int, - bankMaskLen: Int, - sharedEnable: Boolean, - sharedEntries: Int, + bankNum: Int, + bankWidth: Int, + bankEntries: Int, + bankMaskLen: Int, + sharedEnable: Boolean, + sharedEntries: Int, sharedDefaultGroupCount: Int, - tlb_size: Int, - dma_n_xacts: Int, - dma_maxbytes: Int, - bankChannel: Int, - max_in_flight_mem_reqs: Int, - dma_buswidth: Int, - memAddrLen: Int, - tmaReadChannel: Int, - tmaWriteChannel: Int) + tlb_size: Int, + dma_n_xacts: Int, + dma_maxbytes: Int, + bankChannel: Int, + max_in_flight_mem_reqs: Int, + dma_buswidth: Int, + memAddrLen: Int, + tmaReadChannel: Int, + tmaWriteChannel: Int) object MemDomainParam { implicit val rw: ReadWriter[MemDomainParam] = macroRW From a8babf85b08e417b00c102e61ad29f237d88db38 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Fri, 6 Mar 2026 20:48:01 +0800 Subject: [PATCH 140/238] [arch]add:add shared_mvin/out inst but not finished --- .../framework/memdomain/backend/MTrace.scala | 51 +++++++++++ .../privatepath/PrivateMemBackend.scala | 89 +++++-------------- .../memdomain/backend/shared/SharedMem.scala | 50 +++++------ .../backend/shared/SharedMemBackend.scala | 80 +++++++++++------ .../framework/memdomain/configs/default.json | 2 +- .../frontend/cmd_channel/decoder/DISA.scala | 3 + .../cmd_channel/decoder/DomainDecoder.scala | 35 +++++++- .../workloads/lib/bbhw/isa/21_shared_mvin.c | 13 +++ .../workloads/lib/bbhw/isa/22_shared_mvout.c | 13 +++ bb-tests/workloads/lib/bbhw/isa/isa.h | 2 + 10 files changed, 216 insertions(+), 122 deletions(-) create mode 100644 arch/src/main/scala/framework/memdomain/backend/MTrace.scala create mode 100644 bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c diff --git a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala new file mode 100644 index 00000000..ee528125 --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala @@ -0,0 +1,51 @@ +package framework.memdomain.backend + +import chisel3._ +import chisel3.util._ + +// DPI-C BlackBox for memory trace +class MTraceDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val is_write = Input(UInt(8.W)) + val channel = Input(UInt(32.W)) + val vbank_id = Input(UInt(32.W)) + val group_id = Input(UInt(32.W)) + val addr = Input(UInt(32.W)) + val data_lo = Input(UInt(64.W)) + val data_hi = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "MTraceDPI.v", + """ + |import "DPI-C" function void dpi_mtrace( + | input byte unsigned is_write, + | input int unsigned channel, + | input int unsigned vbank_id, + | input int unsigned group_id, + | input int unsigned addr, + | input longint unsigned data_lo, + | input longint unsigned data_hi + |); + | + |module MTraceDPI( + | input [7:0] is_write, + | input [31:0] channel, + | input [31:0] vbank_id, + | input [31:0] group_id, + | input [31:0] addr, + | input [63:0] data_lo, + | input [63:0] data_hi, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); + | end + | end + |endmodule + """.stripMargin + ) +} diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index d92d4a82..7704acb5 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -4,58 +4,11 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.memdomain.frontend.outside_channel.MemConfigerIO -import framework.memdomain.backend.MemRequestIO +import framework.memdomain.backend.{MemRequestIO, MTraceDPI} import framework.memdomain.backend.accpipe.AccPipe import framework.memdomain.backend.banks.SramBank import framework.top.GlobalConfig -// DPI-C BlackBox for memory trace -class MTraceDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val is_write = Input(UInt(8.W)) - val channel = Input(UInt(32.W)) - val vbank_id = Input(UInt(32.W)) - val group_id = Input(UInt(32.W)) - val addr = Input(UInt(32.W)) - val data_lo = Input(UInt(64.W)) - val data_hi = Input(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "MTraceDPI.v", - """ - |import "DPI-C" function void dpi_mtrace( - | input byte unsigned is_write, - | input int unsigned channel, - | input int unsigned vbank_id, - | input int unsigned group_id, - | input int unsigned addr, - | input longint unsigned data_lo, - | input longint unsigned data_hi - |); - | - |module MTraceDPI( - | input [7:0] is_write, - | input [31:0] channel, - | input [31:0] vbank_id, - | input [31:0] group_id, - | input [31:0] addr, - | input [63:0] data_lo, - | input [63:0] data_hi, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); - | end - | end - |endmodule - """.stripMargin - ) -} - @instantiable class PrivateMemBackend(val b: GlobalConfig) extends Module { @@ -169,10 +122,10 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- when(io.config.valid) { - when(io.config.bits.alloc) { + when(io.config.bits.alloc === 1.U) { val pbank_id = getFreePbankId() addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) - }.otherwise { + }.elsewhen(io.config.bits.alloc === 0.U) { deleteEntry(io.config.bits.vbank_id) } } @@ -191,31 +144,35 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Connect AccPipe and Banks // ----------------------------------------------------------------------------- + private def emitTrace(ch: Int, isWrite: UInt, addr: UInt, dataLo: UInt, dataHi: UInt, en: Bool): Unit = { + mtraces(ch).io.is_write := isWrite + mtraces(ch).io.channel := ch.U + mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.group_id := io.mem_req(ch).group_id + mtraces(ch).io.addr := addr + mtraces(ch).io.data_lo := dataLo + mtraces(ch).io.data_hi := dataHi + mtraces(ch).io.enable := en + } + for (i <- 0 until b.memDomain.bankChannel) { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid // Memory trace: read request when(io.mem_req(i).read.req.fire) { - mtraces(i).io.is_write := 0.U - mtraces(i).io.channel := i.U - mtraces(i).io.vbank_id := io.mem_req(i).bank_id - mtraces(i).io.group_id := io.mem_req(i).group_id - mtraces(i).io.addr := io.mem_req(i).read.req.bits.addr - mtraces(i).io.data_lo := 0.U - mtraces(i).io.data_hi := 0.U - mtraces(i).io.enable := true.B + emitTrace(i, 0.U, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) } // Memory trace: write request when(io.mem_req(i).write.req.fire) { - mtraces(i).io.is_write := 1.U - mtraces(i).io.channel := i.U - mtraces(i).io.vbank_id := io.mem_req(i).bank_id - mtraces(i).io.group_id := io.mem_req(i).group_id - mtraces(i).io.addr := io.mem_req(i).write.req.bits.addr - mtraces(i).io.data_lo := io.mem_req(i).write.req.bits.data(63, 0) - mtraces(i).io.data_hi := io.mem_req(i).write.req.bits.data(127, 64) - mtraces(i).io.enable := true.B + emitTrace( + i, + 1.U, + io.mem_req(i).write.req.bits.addr, + io.mem_req(i).write.req.bits.data(63, 0), + io.mem_req(i).write.req.bits.data(127, 64), + true.B + ) } for (j <- 0 until b.memDomain.bankNum) { diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index f5ef03fb..bbda8629 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -33,10 +33,9 @@ class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { @instantiable class SharedMem(val b: GlobalConfig) extends Module { - private val maxGroup = 8 - private val mask_len = b.memDomain.bankMaskLen - private val mask_elem = UInt((b.memDomain.bankWidth / mask_len).W) - private val minSharedLines = b.memDomain.bankNum * maxGroup * b.memDomain.bankEntries + private val maskLen = b.memDomain.bankMaskLen + private val maskElem = UInt((b.memDomain.bankWidth / maskLen).W) + private val minSharedLines = b.memDomain.bankNum * b.memDomain.bankEntries require( b.memDomain.sharedEntries >= minSharedLines, @@ -49,15 +48,14 @@ class SharedMem(val b: GlobalConfig) extends Module { val write = new SharedMemWriteIO(b) }) - val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(mask_len, mask_elem)) + val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(maskLen, maskElem)) - // Shared memory address mapping: - // shared_addr = ((vbank_id * MAX_GROUP + group_id) * bankEntries) + local_addr - private def toSharedAddr(vbank_id: UInt, group_id: UInt, local_addr: UInt): UInt = { - val vbankPart = vbank_id * (maxGroup * b.memDomain.bankEntries).U - val groupPart = group_id * b.memDomain.bankEntries.U - vbankPart + groupPart + local_addr - } + // Shared memory address mapping (group_id intentionally ignored): + // shared_addr = (vbank_id * bankEntries) + local_addr + private def toSharedAddr(vbank_id: UInt, _group_id: UInt, local_addr: UInt): UInt = { + val vbankPart = vbank_id * b.memDomain.bankEntries.U + vbankPart + local_addr + } io.read.req.ready := !io.write.req.valid io.write.req.ready := !io.read.req.valid @@ -65,11 +63,10 @@ class SharedMem(val b: GlobalConfig) extends Module { val readReqFire = io.read.req.fire val readAddr = toSharedAddr(io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) - when(readReqFire) { - assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") - assert(io.read.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") - assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") - } + when(readReqFire) { + assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + } val readData = mem.read(readAddr, readReqFire) @@ -79,16 +76,15 @@ class SharedMem(val b: GlobalConfig) extends Module { val writeReqFire = io.write.req.fire val writeAddr = toSharedAddr(io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) - when(writeReqFire) { - assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") - assert(io.write.req.bits.group_id < maxGroup.U, "SharedMem: group_id out of range") - assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") - mem.write( - writeAddr, - io.write.req.bits.data.asTypeOf(Vec(mask_len, mask_elem)), - io.write.req.bits.mask - ) - } + when(writeReqFire) { + assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + mem.write( + writeAddr, + io.write.req.bits.data.asTypeOf(Vec(maskLen, maskElem)), + io.write.req.bits.mask + ) + } io.write.resp.valid := RegNext(writeReqFire, init = false.B) io.write.resp.bits.ok := RegNext(writeReqFire, init = false.B) diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index 8d10d775..561adbdd 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -3,7 +3,7 @@ package framework.memdomain.backend.shared import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.memdomain.backend.MemRequestIO +import framework.memdomain.backend.{MemRequestIO, MTraceDPI} import framework.memdomain.backend.accpipe.AccPipe import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig @@ -32,33 +32,38 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val query_group_count = Output(UInt(4.W)) }) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) - val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) - - // Keep per-vbank logical group count so shared path can expose the same - // query semantics expected by loader/storer loops. - val sharedGroupCountTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U(4.W)))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) + val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) + val sharedAllocTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) + + for (mt <- mtraces) { + mt.io.is_write := 0.U + mt.io.channel := 0.U + mt.io.vbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B + } io.config.ready := true.B - when(io.config.valid) { val cfgVbankIdx = io.config.bits.vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) - when(io.config.bits.alloc) { - val nextCount = Mux(io.config.bits.is_multi, io.config.bits.group_id + 1.U, 1.U) - when(nextCount > sharedGroupCountTable(cfgVbankIdx)) { - sharedGroupCountTable(cfgVbankIdx) := nextCount - } - }.otherwise { - sharedGroupCountTable(cfgVbankIdx) := 0.U + when(io.config.bits.alloc === 2.U) { + sharedAllocTable(cfgVbankIdx) := true.B + }.elsewhen(io.config.bits.alloc === 0.U) { + sharedAllocTable(cfgVbankIdx) := false.B } } - val queryVbankIdx = io.query_vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) - val sharedGroupCount = sharedGroupCountTable(queryVbankIdx) + // Shared memory treats each vbank as single-group storage. + val queryVbankIdx = io.query_vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) io.query_group_count := Mux( - b.memDomain.sharedEnable.B, - Mux(sharedGroupCount =/= 0.U, sharedGroupCount, b.memDomain.sharedDefaultGroupCount.U(4.W)), - 0.U + b.memDomain.sharedEnable.B && sharedAllocTable(queryVbankIdx), + 1.U(4.W), + 0.U(4.W) ) for (i <- 0 until b.memDomain.bankChannel) { @@ -75,8 +80,8 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.sramWrite.resp.valid := false.B accPipes(i).io.sramWrite.resp.bits := DontCare - // In shared backend, all vbank/group combinations are treated as multi-capable. - accPipes(i).io.is_multi := true.B + // Group dimension is intentionally disabled in shared backend. + accPipes(i).io.is_multi := false.B } sharedMem.io.read.req.valid := false.B @@ -89,19 +94,44 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- // Shared request routing arbiter // --------------------------------------------------------------------------- + private def emitTrace(ch: Int, isWrite: UInt, addr: UInt, dataLo: UInt, dataHi: UInt, en: Bool): Unit = { + mtraces(ch).io.is_write := isWrite + mtraces(ch).io.channel := ch.U + mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.group_id := io.mem_req(ch).group_id + mtraces(ch).io.addr := addr + mtraces(ch).io.data_lo := dataLo + mtraces(ch).io.data_hi := dataHi + mtraces(ch).io.enable := en + } + val sharedReqArb = Module(new RRArbiter(new SharedArbReq(b), b.memDomain.bankChannel)) for (i <- 0 until b.memDomain.bankChannel) { - val routeShared = b.memDomain.sharedEnable.B + val routeShared = b.memDomain.sharedEnable.B && sharedAllocTable(io.mem_req(i).bank_id) val useRead = accPipes(i).io.sramRead.req.valid val useWrite = !useRead && accPipes(i).io.sramWrite.req.valid + when(io.mem_req(i).read.req.fire) { + emitTrace(i, 0.U, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) + } + when(io.mem_req(i).write.req.fire) { + emitTrace( + i, + 1.U, + io.mem_req(i).write.req.bits.addr, + io.mem_req(i).write.req.bits.data(63, 0), + io.mem_req(i).write.req.bits.data(127, 64), + true.B + ) + } + sharedReqArb.io.in(i).valid := routeShared && (useRead || useWrite) sharedReqArb.io.in(i).bits.src_channel := i.U sharedReqArb.io.in(i).bits.is_write := useWrite sharedReqArb.io.in(i).bits.vbank_id := io.mem_req(i).bank_id - sharedReqArb.io.in(i).bits.group_id := io.mem_req(i).group_id - sharedReqArb.io.in(i).bits.addr := Mux( + sharedReqArb.io.in(i).bits.group_id := 0.U + sharedReqArb.io.in(i).bits.addr := Mux( useRead, accPipes(i).io.sramRead.req.bits.addr, accPipes(i).io.sramWrite.req.bits.addr diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index d0cf78f8..524d4e95 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -4,7 +4,7 @@ "bankEntries": 128, "bankMaskLen": 16, "sharedEnable": true, - "sharedEntries": 32768, + "sharedEntries": 4096, "sharedDefaultGroupCount": 1, "tlb_size": 4, "dma_n_xacts": 8, diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index 4da6fc37..1cb4b53a 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -4,6 +4,9 @@ import chisel3._ import chisel3.util._ object DISA { + + val SHARED_MVIN_BITPAT = BitPat("b0010101") // 21 + val SHARED_MVOUT_BITPAT = BitPat("b0010110") // 22 val MSET_BITPAT = BitPat("b0010111") // 23 val MVIN_BITPAT = BitPat("b0011000") // 24 val MVOUT_BITPAT = BitPat("b0011001") // 25 diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index 338cdc8e..cec1d19b 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -10,6 +10,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} // Detailed decode output for Mem domain class MemDecodeCmd(b: GlobalConfig) extends Bundle { + val is_shared = Bool() // Whether this is a shared memory access (for synchronization) val is_load = Bool() val is_store = Bool() val is_config = Bool() @@ -27,7 +28,7 @@ class MemDecodeCmd(b: GlobalConfig) extends Bundle { // LS decode fields object LSDecodeFields extends Enumeration { type Field = Value - val LD_EN, ST_EN, MEMADDR, BANK_ID, ITER, SPECIAL, VALID = Value + val SHARED_EN, LD_EN, ST_EN, MEMADDR, BANK_ID, ITER, SPECIAL, VALID = Value } // Default constants for Mem decoder @@ -68,13 +69,14 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // rs2[9:0] = iter // rs2[63:10] = special import LSDecodeFields._ - val ls_default_decode = List(N, N, DADDR, DADDR, DITER, DSPECIAL, N) + val ls_default_decode = List(N, N, N, DADDR, DADDR, DITER, DSPECIAL, N) val ls_decode_list = ListLookup( func7, ls_default_decode, Array( MSET_BITPAT -> List( + N, N, N, 0.U(memAddrLen.W), // mem_addr: not used for MSET @@ -84,6 +86,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { Y ), // mset MVIN_BITPAT -> List( + N, Y, N, rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits @@ -93,6 +96,27 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { Y ), // mvin MVOUT_BITPAT -> List( + N, + N, + Y, + rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits + rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] + rs2(9, 0), // iter from rs2[9:0] + rs2(63, 10), // special from rs2[63:10] + Y + ), // mvout + SHARED_MVIN_BITPAT -> List( + Y, + Y, + N, + rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits + rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] + rs2(9, 0), // iter from rs2[9:0] + rs2(63, 10), // special from rs2[63:10] + Y + ), // shared mvin + SHARED_MVOUT_BITPAT -> List( + Y, N, Y, rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits @@ -100,7 +124,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs2(9, 0), // iter from rs2[9:0] rs2(63, 10), // special from rs2[63:10] Y - ) // mvout + ) // shared mvout ) ) @@ -115,6 +139,11 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- io.mem_decode_cmd_o.valid := io.cmd_i.valid && (io.cmd_i.bits.domain_id === DomainId.MEM) + io.mem_decode_cmd_o.bits.is_shared := Mux( + io.mem_decode_cmd_o.valid, + ls_decode_list(LSDecodeFields.SHARED_EN.id).asBool, + false.B + ) io.mem_decode_cmd_o.bits.is_load := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.LD_EN.id).asBool, diff --git a/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c b/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c new file mode 100644 index 00000000..ba417b4c --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c @@ -0,0 +1,13 @@ +#ifndef _BB_SHARED_MVIN_H_ +#define _BB_SHARED_MVIN_H_ + +#include "isa.h" + +#define BB_SHARED_MVIN_FUNC7 21 + +#define bb_shared_mvin(mem_addr, bank_id, depth, stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_WR | FIELD(mem_addr, 27, 58)), \ + (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_SHARED_MVIN_FUNC7) + +#endif // _BB_SHARED_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c b/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c new file mode 100644 index 00000000..b755aa7b --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c @@ -0,0 +1,13 @@ +#ifndef _BB_SHARED_MVOUT_H_ +#define _BB_SHARED_MVOUT_H_ + +#include "isa.h" + +#define BB_SHARED_MVOUT_FUNC7 22 + +#define bb_shared_mvout(mem_addr, bank_id, depth, stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_RD0 | FIELD(mem_addr, 27, 58)), \ + (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_SHARED_MVOUT_FUNC7) + +#endif // _BB_SHARED_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 9df60671..1834856d 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -40,6 +40,8 @@ typedef int32_t result_t; : "memory") // Include all instruction definitions +#include "21_shared_mvin.c" +#include "22_shared_mvout.c" #include "23_mset.c" #include "24_mvin.c" #include "25_mvout.c" From 53679fbc57b8095bc93608e90e6f7a4cf85ab469 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Fri, 6 Mar 2026 21:38:39 +0800 Subject: [PATCH 141/238] [arch]add:build is_shared flag to backend --- arch/src/main/scala/framework/memdomain/MemDomain.scala | 2 ++ .../framework/memdomain/backend/MemBackendTypes.scala | 1 + .../memdomain/backend/privatepath/PrivateMemBackend.scala | 1 + .../memdomain/backend/shared/SharedMemBackend.scala | 1 + .../scala/framework/memdomain/frontend/MemFrontend.scala | 4 ++++ .../memdomain/frontend/outside_channel/MemLoader.scala | 6 ++++++ .../memdomain/frontend/outside_channel/MemStorer.scala | 6 ++++++ .../main/scala/framework/memdomain/midend/MemMidend.scala | 8 ++++++++ 8 files changed, 29 insertions(+) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index cb8c784e..b4d64367 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -86,6 +86,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { midend.io.balldomain.bankWrite <> io.ballDomain.bankWrite midend.io.frontend.bankRead <> frontend.io.interdma.bankRead midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite + midend.io.frontend.read_is_shared := frontend.io.interdma.read_is_shared + midend.io.frontend.write_is_shared := frontend.io.interdma.write_is_shared midend.io.mem_req <> backend.io.mem_req backend.io.config <> frontend.io.config diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala index a8213954..362ae993 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala @@ -10,4 +10,5 @@ class MemRequestIO(b: GlobalConfig) extends Bundle { val read = Flipped(new SramReadIO(b)) // midend sends read req into backend val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) val group_id = Output(UInt(3.W)) + val is_shared = Output(Bool()) } diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index 7704acb5..4d53f9e6 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -91,6 +91,7 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.mem_req.read <> io.mem_req(i).read accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared // Bank-side defaults (only driven when a bank is actually connected) accPipes(i).io.sramRead.req.ready := false.B diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index 561adbdd..f6acb568 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -71,6 +71,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.mem_req.read <> io.mem_req(i).read accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared accPipes(i).io.sramRead.req.ready := false.B accPipes(i).io.sramRead.resp.valid := false.B diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 82c2cd82..1ceae233 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -33,6 +33,8 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val interdma = new Bundle { val bankRead = Flipped(new BankRead(b)) val bankWrite = Flipped(new BankWrite(b)) + val read_is_shared = Output(Bool()) + val write_is_shared = Output(Bool()) } // TLB interfaces for internal DMA modules (Reader/Writer) @@ -160,6 +162,8 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Connect MemLoader and MemStorer to MemController's DMA interface memLoader.io.bankWrite <> io.interdma.bankWrite memStorer.io.bankRead <> io.interdma.bankRead + io.interdma.read_is_shared := memStorer.io.is_shared + io.interdma.write_is_shared := memLoader.io.is_shared // Completion signal connected to global RS io.global_complete_o <> memRs.io.complete_o diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index ff8c241f..7a95e902 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -27,6 +27,9 @@ class MemLoader(val b: GlobalConfig) extends Module { // Query interface to get group count val query_vbank_id = Output(UInt(8.W)) val query_group_count = Input(UInt(4.W)) + + // Propagate decoded shared/private access intent. + val is_shared = Output(Bool()) }) val s_idle :: s_dma_req :: s_dma_wait :: s_wait_last_write :: s_done :: Nil = Enum(5) @@ -38,6 +41,7 @@ class MemLoader(val b: GlobalConfig) extends Module { val resp_count = RegInit(0.U(log2Up(16).W)) val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) val stride_reg = Reg(UInt(11.W)) + val is_shared_reg = RegInit(false.B) // Group counter for multi-bank writes val group_counter = RegInit(0.U(4.W)) @@ -79,6 +83,7 @@ class MemLoader(val b: GlobalConfig) extends Module { io.bankWrite.bank_id := wr_bank_reg io.bankWrite.ball_id := 0.U io.bankWrite.group_id := group_counter + io.is_shared := is_shared_reg // cmdResp (Decoupled): hold valid until accepted io.cmdResp.valid := (state === s_done) @@ -100,6 +105,7 @@ class MemLoader(val b: GlobalConfig) extends Module { latLast := false.B group_counter := 0.U group_count_reg := io.query_group_count + is_shared_reg := io.cmdReq.bits.cmd.is_shared // Query group count and multiply iter iter_reg := io.cmdReq.bits.cmd.iter * io.query_group_count diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index be4b60ca..68fa5403 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -31,6 +31,9 @@ class MemStorer(val b: GlobalConfig) extends Module { // Query interface to get group count val query_vbank_id = Output(UInt(8.W)) val query_group_count = Input(UInt(4.W)) + + // Propagate decoded shared/private access intent. + val is_shared = Output(Bool()) }) // ----------------------------- @@ -45,6 +48,7 @@ class MemStorer(val b: GlobalConfig) extends Module { val stride_reg = RegInit(0.U(10.W)) val rd_bank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val group_count_reg = RegInit(1.U(4.W)) // Store group count for current operation + val is_shared_reg = RegInit(false.B) // Address and group counters val addr_counter = RegInit(0.U(10.W)) // Row address counter @@ -82,6 +86,7 @@ class MemStorer(val b: GlobalConfig) extends Module { // Query and save group count group_count_reg := io.query_group_count iter_reg := io.cmdReq.bits.cmd.iter + is_shared_reg := io.cmdReq.bits.cmd.is_shared // Initialize counters addr_counter := 0.U @@ -107,6 +112,7 @@ class MemStorer(val b: GlobalConfig) extends Module { io.bankRead.bank_id := target_bank io.bankRead.ball_id := 0.U io.bankRead.group_id := group_counter + io.is_shared := is_shared_reg io.bankRead.io.req.valid := (state === s_issue_sram_req) io.bankRead.io.req.bits.addr := addr_counter diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index e3fbbf8e..5ceb4eb0 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -26,6 +26,8 @@ class MemMidend(val b: GlobalConfig) extends Module { val frontend = new Bundle { val bankRead = new BankRead(b) val bankWrite = new BankWrite(b) + val read_is_shared = Input(Bool()) + val write_is_shared = Input(Bool()) } val balldomain = new Bundle { @@ -111,6 +113,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).write.resp.ready := false.B io.mem_req(i).bank_id := 0.U io.mem_req(i).group_id := 0.U + io.mem_req(i).is_shared := false.B val isRead = mappingTable(i).isRead val ballRead = io.balldomain.bankRead(mappingTable(i).id).io @@ -146,6 +149,11 @@ class MemMidend(val b: GlobalConfig) extends Module { io.frontend.bankRead.group_id, io.frontend.bankWrite.group_id ) + io.mem_req(b.top.memBallChannelNum).is_shared := Mux( + io.frontend.bankRead.io.req.valid, + io.frontend.read_is_shared, + io.frontend.write_is_shared + ) // Mapping table release for (i <- 0 until b.top.memBallChannelNum - 1) { From c30822e03ddc16adf58b3cab69b5fa018d288df8 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 7 Mar 2026 04:11:51 +0800 Subject: [PATCH 142/238] [nix] update: add Yosys and OpenSTA tools [bb-tests] feat: coverage support in tests --- .gitignore | 2 +- arch/src/csrc/include/bdb.h | 3 ++ arch/src/csrc/src/main.cc | 5 +++ bb-tests/sardine/run_tests.py | 10 +++++- bb-tests/sardine/tests/test_ctest.py | 4 ++- bbdev | 2 +- flake.nix | 4 +++ scripts/nix/build-env-tools.nix | 49 ++++++++++++++++++++++++++++ 8 files changed, 75 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 7da0902b..627cf4f3 100644 --- a/.gitignore +++ b/.gitignore @@ -16,7 +16,7 @@ index.html *.vcd *.fst *.log - +*.dot .clangd diff --git a/arch/src/csrc/include/bdb.h b/arch/src/csrc/include/bdb.h index b553189e..c3e39a15 100644 --- a/arch/src/csrc/include/bdb.h +++ b/arch/src/csrc/include/bdb.h @@ -16,6 +16,9 @@ #endif #include "verilated_fst_c.h" +#if VM_COVERAGE +#include "verilated_cov.h" +#endif // ================ BDB Config =================== // VCD file path diff --git a/arch/src/csrc/src/main.cc b/arch/src/csrc/src/main.cc index 218e7b69..0e33048c 100644 --- a/arch/src/csrc/src/main.cc +++ b/arch/src/csrc/src/main.cc @@ -76,6 +76,11 @@ void sim_exit() { } #endif +#if VM_COVERAGE + Verilated::mkdir("coverage"); + contextp->coveragep()->write(); +#endif + exit(0); } diff --git a/bb-tests/sardine/run_tests.py b/bb-tests/sardine/run_tests.py index d008d69d..eb98cc10 100644 --- a/bb-tests/sardine/run_tests.py +++ b/bb-tests/sardine/run_tests.py @@ -135,6 +135,14 @@ def run_pytest(args=None): print(" - Test categorization") sys.exit(0) print("Test started") - result = run_pytest(sys.argv[1:]) + # Filter out --coverage flag (handled by bbdev, not pytest) + # Set env var so test cases know to pass --coverage to verilator sim + pytest_args = [] + for a in sys.argv[1:]: + if a == "--coverage": + os.environ["SARDINE_COVERAGE"] = "1" + else: + pytest_args.append(a) + result = run_pytest(pytest_args) print(f"Test result: {result}") sys.exit(result) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index d5020243..aa018fa2 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -1,6 +1,7 @@ import pytest import logging import time +import os from pathlib import Path import subprocess @@ -99,7 +100,8 @@ def test_ctest_workload_debug( time.sleep(test_index * 20) start_time = time.time() - command = f'bbdev verilator --sim "--binary {workload_path} --batch"' + coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" + command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' logging.info(f"Running command: {command}") # 使用 command_run 执行命令，带提前退出检测 diff --git a/bbdev b/bbdev index abc5efe5..46f0727f 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit abc5efe581364b34bfed079bec249df5d2671ec6 +Subproject commit 46f0727f2c89c44f8b8b8713a6c39a44ec8552fb diff --git a/flake.nix b/flake.nix index de11d400..f0f2b930 100644 --- a/flake.nix +++ b/flake.nix @@ -24,6 +24,8 @@ tools.dramsim2 tools.ccache tools.lld + tools.yosys + tools.opensta # RISC-V toolchain riscv.riscv-embedded-gcc @@ -97,6 +99,8 @@ echo "npm: $(npm --version 2>&1 | head -1)" echo "bbdev: $(which bbdev)" echo "RISCV: $RISCV" + echo "Yosys: $(yosys --version 2>&1 | head -1)" + echo "OpenSTA: $(sta -version 2>&1 | head -1)" echo "===========================================================================" ''; }; diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index 465c43ce..a2edb792 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -22,6 +22,49 @@ let runHook postInstall ''; }; + + # CUDD BDD library (required by OpenSTA) + cudd = pkgs.stdenv.mkDerivation { + pname = "cudd"; + version = "3.0.0"; + src = pkgs.fetchFromGitHub { + owner = "The-OpenROAD-Project"; + repo = "cudd"; + rev = "3.0.0"; + hash = "sha256-ybsFPcggPsb6lfZbWbwxNTuZSOC7lLNY/iZSTvyFmdU="; + }; + nativeBuildInputs = [ pkgs.autoreconfHook ]; + configureFlags = [ "--prefix=$(out)" "CFLAGS=-fPIC" "CXXFLAGS=-fPIC" ]; + installPhase = '' + runHook preInstall + make install + runHook postInstall + ''; + }; + + # OpenSTA - gate-level static timing analysis + opensta = pkgs.stdenv.mkDerivation { + pname = "opensta"; + version = "unstable-2025"; + src = pkgs.fetchFromGitHub { + owner = "The-OpenROAD-Project"; + repo = "OpenSTA"; + rev = "5e9e9db7061fddf1b0b9c47c49c920c56da140e3"; + hash = "sha256-SfxNh5PFWWTdTH0ZiiATV1F0qOBTh50+xM9roJMHtLg=="; + }; + nativeBuildInputs = with pkgs; [ cmake flex bison swig ]; + buildInputs = with pkgs; [ tcl eigen zlib ]; + cmakeFlags = [ + "-DCUDD_DIR=${cudd}" + "-DUSE_TCL_READLINE=OFF" + ]; + installPhase = '' + runHook preInstall + mkdir -p $out/bin + find . -name sta -type f -executable -exec cp {} $out/bin/ \; + runHook postInstall + ''; + }; in { # Pin to Verilator 5.022 2024-02-24 (nixpkgs-unstable ships 5.044) @@ -40,4 +83,10 @@ in # Build acceleration tools ccache = pkgs.ccache; lld = pkgs.lld; + + # Synthesis tools + yosys = pkgs.yosys; + + # Static timing analysis + opensta = opensta; } From b0be7f83e7a206b23770e79dce006885a8173be7 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 7 Mar 2026 04:51:42 +0800 Subject: [PATCH 143/238] [arch] feat: enhance coverage support with signal handling and cleanup --- arch/src/csrc/src/main.cc | 27 ++++++++++++++++++++++----- bbdev | 2 +- flake.nix | 1 + scripts/nix/build-env-tools.nix | 3 +++ 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/arch/src/csrc/src/main.cc b/arch/src/csrc/src/main.cc index 0e33048c..88213b21 100644 --- a/arch/src/csrc/src/main.cc +++ b/arch/src/csrc/src/main.cc @@ -6,6 +6,9 @@ #include "monitor/cosim.h" #endif +#include +#include + vluint64_t sim_time = 0; VerilatedContext *contextp = NULL; VerilatedFstC *tfp = NULL; @@ -19,6 +22,19 @@ static VTestHarness *top; int bb_step = 1; +#if VM_COVERAGE +static void coverage_atexit() { + if (contextp) { + contextp->coveragep()->write(); + } +} + +static void coverage_signal_handler(int sig) { + coverage_atexit(); + _exit(128 + sig); +} +#endif + void step_and_dump_wave() { top->eval(); contextp->timeInc(1); @@ -53,6 +69,12 @@ void sim_init(int argc, char **argv) { top->clock = 0; step_and_dump_wave(); +#if VM_COVERAGE + atexit(coverage_atexit); + signal(SIGTERM, coverage_signal_handler); + signal(SIGINT, coverage_signal_handler); +#endif + #ifdef COSIM // Initialize COSIM socket server cosim_server = new CosimServer(top); @@ -76,11 +98,6 @@ void sim_exit() { } #endif -#if VM_COVERAGE - Verilated::mkdir("coverage"); - contextp->coveragep()->write(); -#endif - exit(0); } diff --git a/bbdev b/bbdev index 46f0727f..bf405ec0 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 46f0727f2c89c44f8b8b8713a6c39a44ec8552fb +Subproject commit bf405ec0a9a6f4f13ae5ef2e417aa98d78af4adb diff --git a/flake.nix b/flake.nix index f0f2b930..cca6eaab 100644 --- a/flake.nix +++ b/flake.nix @@ -26,6 +26,7 @@ tools.lld tools.yosys tools.opensta + tools.lcov # RISC-V toolchain riscv.riscv-embedded-gcc diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index a2edb792..f54d01fe 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -89,4 +89,7 @@ in # Static timing analysis opensta = opensta; + + # Coverage report (genhtml) + lcov = pkgs.lcov; } From 8ad61a9b5001c43c529e4d56fd8ee8872012ea0b Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 7 Mar 2026 12:58:25 +0800 Subject: [PATCH 144/238] [bbdev] update: bump bbdev to the latest version --- bbdev | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bbdev b/bbdev index bf405ec0..47fe2ab1 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit bf405ec0a9a6f4f13ae5ef2e417aa98d78af4adb +Subproject commit 47fe2ab1c8b11b4b958ecc9227c78edb6c63142c From 51a955a4113772501b61861db8f0ea530abe38d0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 7 Mar 2026 17:26:17 +0800 Subject: [PATCH 145/238] [arch] feat: implement Quant and Dequant Balls with associated tests and configurations [bbAgent] feat: add a base workflow for buckyball --- .claude/.gitignore | 2 + .claude/commands/ball.md | 73 +++ .claude/commands/check.md | 11 + .claude/commands/optimize.md | 78 +++ .claude/commands/verify.md | 48 ++ .claude/settings.json | 9 + .gitignore | 2 +- CLAUDE.md | 94 +++ .../scala/examples/toy/balldomain/DISA.scala | 2 + .../toy/balldomain/DomainDecoder.scala | 4 +- .../toy/balldomain/bbus/busRegister.scala | 4 + .../framework/balldomain/configs/default.json | 6 +- .../prototype/dequant/Dequant.scala | 234 ++++++++ .../prototype/dequant/DequantBall.scala | 36 ++ .../dequant/configs/DequantBallParam.scala | 17 + .../prototype/dequant/configs/default.json | 3 + .../balldomain/prototype/quant/Quant.scala | 306 ++++++++++ .../prototype/quant/QuantBall.scala | 36 ++ .../quant/configs/QuantBallParam.scala | 18 + .../prototype/quant/configs/default.json | 3 + .../memdomain/backend/MemBackendTypes.scala | 8 +- .../privatepath/PrivateMemBackend.scala | 15 +- .../memdomain/backend/shared/SharedMem.scala | 46 +- .../backend/shared/SharedMemBackend.scala | 23 +- .../memdomain/frontend/MemFrontend.scala | 4 +- .../frontend/cmd_channel/decoder/DISA.scala | 8 +- .../cmd_channel/decoder/DomainDecoder.scala | 12 +- .../frontend/outside_channel/MemLoader.scala | 12 +- .../memdomain/midend/MemMidend.scala | 8 +- bb-tests/sardine/tests/test_ctest.py | 8 + bb-tests/workloads/lib/bbhw/isa/40_quant.c | 18 + bb-tests/workloads/lib/bbhw/isa/41_dequant.c | 18 + bb-tests/workloads/lib/bbhw/isa/isa.h | 2 + .../workloads/src/CTest/toy/CMakeLists.txt | 6 +- .../workloads/src/CTest/toy/dequant_test.c | 87 +++ bb-tests/workloads/src/CTest/toy/quant_test.c | 147 +++++ .../toy/vecunit_simple_nn_forward_pass_test.c | 156 ----- scripts/claude/README.md | 97 +++ scripts/claude/mcp_server.py | 566 ++++++++++++++++++ 39 files changed, 2004 insertions(+), 223 deletions(-) create mode 100644 .claude/.gitignore create mode 100644 .claude/commands/ball.md create mode 100644 .claude/commands/check.md create mode 100644 .claude/commands/optimize.md create mode 100644 .claude/commands/verify.md create mode 100644 .claude/settings.json create mode 100644 CLAUDE.md create mode 100644 arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/dequant/configs/DequantBallParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/dequant/configs/default.json create mode 100644 arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/quant/configs/QuantBallParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/quant/configs/default.json create mode 100644 bb-tests/workloads/lib/bbhw/isa/40_quant.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/41_dequant.c create mode 100644 bb-tests/workloads/src/CTest/toy/dequant_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/quant_test.c delete mode 100644 bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c create mode 100644 scripts/claude/README.md create mode 100644 scripts/claude/mcp_server.py diff --git a/.claude/.gitignore b/.claude/.gitignore new file mode 100644 index 00000000..8c9bdd3a --- /dev/null +++ b/.claude/.gitignore @@ -0,0 +1,2 @@ +agents/ +settings.local.json diff --git a/.claude/commands/ball.md b/.claude/commands/ball.md new file mode 100644 index 00000000..72b6aeb3 --- /dev/null +++ b/.claude/commands/ball.md @@ -0,0 +1,73 @@ +创建一个名为 $ARGUMENTS 的新 Buckyball Ball 算子，完成从实现到验证的全流程。 + +**重要：编译、仿真等操作必须通过 MCP 工具（validate、bbdev_workload_build、bbdev_verilator_run 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 阶段 1 — 需求收集 + +1. 读取当前注册状态，确定新 Ball 的 ballId 和 funct7： + - `arch/src/main/scala/framework/balldomain/configs/default.json` + - `arch/src/main/scala/examples/toy/balldomain/DISA.scala` +2. 向用户确认以下信息： + - Ball 的计算语义（做什么运算） + - inBW / outBW（读/写 bank 端口数量） + - 是否需要第二个操作数（op2） + - iter（迭代次数）的含义 + +## 阶段 2 — 实现 Ball + +1. 读取参考代码，理解 Blink 协议和现有 Ball 的写法： + - 简单参考：`arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala` 和 `Relu.scala` + - 复杂参考：`arch/src/main/scala/framework/balldomain/prototype/systolicarray/` + - Blink 协议：`arch/src/main/scala/framework/balldomain/blink/blink.scala`、`bank.scala`、`status.scala` + - SRAM 接口：`arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala` +2. 在 `arch/src/main/scala/framework/balldomain/prototype//` 下创建： + - `Ball.scala` — wrapper，extends Module with HasBlink，从 ballIdMappings 取 inBW/outBW，实例化 core，连接 BlinkIO + - `.scala` — core 计算逻辑，包含 FSM 和数据通路 + - `configs/BallParam.scala` — 算子参数 case class + - `configs/default.json` — 算子专属配置 + +关键约束： +- SRAM 读延迟 = 1 cycle（req.fire 后下一周期 resp.valid） +- cmdReq.fire 时 latch 命令字段到寄存器 +- FSM 基本模式：idle → 读数据 → 计算 → 写数据 → complete → idle +- status.idle 和 status.running 必须映射 FSM 状态 + +## 阶段 3 — 注册 + +按顺序更新以下四个文件： +1. `arch/src/main/scala/framework/balldomain/configs/default.json` — 追加 ballIdMappings 条目，更新 ballNum +2. `arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala` — 添加 import 和 match case +3. `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — 添加 `val XXX = BitPat("bxxxxxxx")` +4. `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — 添加 ListLookup 解码行，BID = ballId.U + +## 阶段 4 — ISA C 宏 + +1. 在 `bb-tests/workloads/lib/bbhw/isa/` 下创建 `_.c` + - 定义 `BB__FUNC7` 宏（funct7 十进制值） + - 定义 `bb_(...)` 宏（编码 rs1/rs2 + 调用 BUCKYBALL_INSTRUCTION_R_R） + - 参考：`bb-tests/workloads/lib/bbhw/isa/38_relu.c` +2. 在 `bb-tests/workloads/lib/bbhw/isa/isa.h` 中 `#include` 新文件 + +## 阶段 5 — CTest + +1. 在 `bb-tests/workloads/src/CTest/toy/` 下创建 `_test.c` + - 包含固定输入矩阵和预期输出矩阵 + - 遵循 bb_mem_alloc → bb_mvin → bb_ → bb_mvout → bb_fence 流程 + - compare 判定 PASS/FAIL + - 参考：`bb-tests/workloads/src/CTest/toy/relu_test.c` +2. 在 `bb-tests/workloads/src/CTest/toy/CMakeLists.txt` 中用 `add_cross_platform_test_target` 注册 +3. 在 `bb-tests/sardine/tests/test_ctest.py` 的 `ctest_workloads` 列表中追加对应条目 + +## 阶段 6 — 校验 + 编译 + 仿真 + +1. 调用 MCP 工具 `validate` 做静态校验，确认 6 项不变量全部通过 +2. 调用 MCP 工具 `bbdev_workload_build` 编译 CTest +3. 调用 MCP 工具 `bbdev_verilator_run` 跑仿真，指定新 Ball 的 CTest binary +4. 解析仿真结果： + - PASSED → 完成 + - FAILED → 进入调试： + a. 找到日志目录（MCP 返回的 `log_dir`，或 `ls -t arch/log/ | head -5`） + b. 读取 `stdout.log`（程序输出）、`disasm.log`（反汇编）、**`bdb.log`（Ball 硬件调试日志，最重要）** + c. 在 bdb.log 中搜索 Ball 名称，检查 SRAM 读写地址/数据、bank_id 分配、iter 次数 + d. 结合 Chisel 源码定位问题并修复 + e. 重新通过 MCP 工具编译和仿真验证 diff --git a/.claude/commands/check.md b/.claude/commands/check.md new file mode 100644 index 00000000..62bc9ed3 --- /dev/null +++ b/.claude/commands/check.md @@ -0,0 +1,11 @@ +对 Buckyball Ball 注册状态做静态校验。 + +调用 MCP 工具 `validate`，检查以下 6 项注册不变量： +1. ballNum == ballIdMappings 数组长度 +2. ballId 严格递增 +3. ballId 无重复 +4. DISA.scala funct7 无重复 +5. busRegister.scala case 名称与 default.json ballName 一致 +6. DomainDecoder.scala BID 与 default.json ballId 一致 + +每项报告 pass/fail 状态。如果有失败项，分析原因并给出修复建议。 diff --git a/.claude/commands/optimize.md b/.claude/commands/optimize.md new file mode 100644 index 00000000..46d61c50 --- /dev/null +++ b/.claude/commands/optimize.md @@ -0,0 +1,78 @@ +分析并优化名为 $ARGUMENTS 的 Ball 的延迟和面积。 + +**重要：综合、仿真等操作必须通过 MCP 工具（bbdev_yosys_synth、bbdev_verilator_run、bbdev_workload_build 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 阶段 1 — 基线测量 + +1. 调用 MCP 工具 `bbdev_yosys_synth` 跑 Yosys 综合 + OpenSTA 时序分析 +2. 读取面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解） +3. 读取时序报告：`bbdev/api/steps/yosys/log/timing_report.txt`（关键路径） +4. 检查该 Ball 的 CTest 中是否有 `read_rdcycle()` 计时代码 + - 如果有：调用 `bbdev_verilator_run` 跑仿真获取基线 cycle 数 + - 如果没有：自动在 CTest 中加入 read_rdcycle() 前后对比代码，调用 `bbdev_workload_build` 重新编译，再调用 `bbdev_verilator_run` 获取基线 cycle 数 + +## 阶段 2 — 面积分析 + +从 hierarchy_report.txt 提取目标 Ball 及其子模块的面积数据： +- 总面积（Chip area） +- Sequential 占比（寄存器面积） +- Combinational 占比（组合逻辑面积） +- 子模块面积排名 + +识别面积大户： +- Sequential 占比高 → 寄存器多，考虑是否可用 SRAM 替代 +- Combinational 占比高 → 逻辑复杂，考虑是否可以简化或共享 + +对比同类 Ball 面积（如 ReluBall vs TransposeBall），找出效率差距。 + +## 阶段 3 — 时序/延迟分析 + +1. 从 timing_report.txt 看关键路径是否经过该 Ball，以及路径延迟 +2. 从仿真结果看操作延迟（cycle 数） +3. 读取 Ball 的 Chisel core 源码，分析 FSM： + - 绘制 FSM 状态转移图 + - 计算每个状态的 cycle 数（最佳/最坏情况） + - 识别瓶颈状态（哪个状态耗时最多） + - 分析 SRAM 读写模式（串行 vs 流水 vs 多端口并行） + +## 阶段 4 — 优化方案 + +提出可量化的优化方案，每个方案包含： +- 优化手段描述 +- 预期面积变化（参考 hierarchy_report 数据量化） +- 预期延迟变化（cycle 数） +- 预期频率影响 +- trade-off 说明 + +常见优化模式： + +**降延迟**： +- 读写流水化：让写操作和下一轮读操作重叠，面积略增，延迟显著降 +- 多 bank 端口并行读：利用 inBW > 1 同时读多行，面积不变，延迟与端口数成比例降 +- 去中间等待状态：合并不必要的 FSM 状态，面积略降 +- 边读边算：计算嵌入读响应周期，利用 SRAM 1-cycle 延迟的下降沿做计算 + +**降面积**： +- regArray 改 SRAM：大块寄存器阵列换成 SRAM 端口访问，面积显著降，可能增延迟 +- 共享计算单元：多操作时分复用同一计算单元，面积降，延迟可能增 +- 减少 counter 位宽：根据实际范围缩减位宽，面积微降 + +**提频率**： +- 拆分组合逻辑长路径：在关键路径中间插入寄存器，面积略增，可能增 1 cycle 延迟 + +列出方案后让用户选择。 + +## 阶段 5 — 实施 + +根据用户选择的方案修改 Chisel 代码。 + +## 阶段 6 — 优化后测量 + +1. 再次调用 `bbdev_yosys_synth`，对比 hierarchy_report +2. 再次调用 `bbdev_verilator_run`，对比 cycle 数 +3. 调用 `validate` 确认注册一致性未被破坏 +4. 输出优化前后对比报告： + - 面积差值和百分比变化 + - Cycle 数差值和百分比变化 + - 关键路径延迟变化 + - 频率变化 diff --git a/.claude/commands/verify.md b/.claude/commands/verify.md new file mode 100644 index 00000000..6c8b9a38 --- /dev/null +++ b/.claude/commands/verify.md @@ -0,0 +1,48 @@ +验证名为 $ARGUMENTS 的 Ball 的功能正确性。 + +**重要：编译、仿真、测试等操作必须通过 MCP 工具（bbdev_workload_build、bbdev_verilator_run、bbdev_sardine_run 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 阶段 1 — 完整性检查 + +检查以下各项是否存在，缺什么补什么： +1. Ball 是否在 `arch/src/main/scala/framework/balldomain/configs/default.json` 中注册 +2. ISA 宏是否存在：`bb-tests/workloads/lib/bbhw/isa/` 下对应的 .c 文件 +3. CTest 是否存在：`bb-tests/workloads/src/CTest/toy/` 下对应的 _test.c 文件 +4. sardine 列表是否包含：`bb-tests/sardine/tests/test_ctest.py` 的 ctest_workloads 列表 + +## 阶段 2 — 编译 + 仿真 + +1. 调用 MCP 工具 `bbdev_workload_build` 编译所有 CTest +2. 调用 MCP 工具 `bbdev_verilator_run` 仿真该 Ball 的 CTest + - binary 名称格式：`ctest__test_singlecore-baremetal` + - 设置 batch=true +3. 如果编译或仿真失败，分析错误并修复 + +## 阶段 3 — 覆盖率分析 + +1. 调用 MCP 工具 `bbdev_sardine_run`，设置 coverage=true +2. 读取覆盖率报告：`bb-tests/sardine/reports/coverage/html/` 和 `bb-tests/sardine/reports/coverage/annotated/` +3. 分析该 Ball 的 RTL 行覆盖情况 +4. 如果覆盖率不足，建议或自动补充测试用例，补充后重新编译和仿真验证 + +## 阶段 4 — 失败分析（如有） + +如果仿真结果为 FAILED： + +1. **找到日志目录**：MCP 工具返回的 JSON 中包含 `log_dir` 字段，如 `arch/log/2026-03-07-12-00-ctest_xxx/` + - 如果 MCP 返回中没有 `log_dir`，用 `ls -t arch/log/ | head -5` 找最近的日志目录 + +2. **读取关键日志**： + - `arch/log//stdout.log` — 程序标准输出，包含 PASSED/FAILED 和 printf 输出 + - `arch/log//disasm.log` — 反汇编指令流，可以看到实际执行了哪些指令 + - `arch/log//bdb.log` — **Buckyball 调试日志**，包含 Ball 内部状态变化、SRAM 读写请求/响应、FSM 状态转移等硬件级信息。这是定位 Ball 逻辑错误最重要的日志 + +3. **分析 bdb.log 的方法**： + - 搜索目标 Ball 的名称，找到相关的命令发射和完成事件 + - 检查 SRAM 读写地址和数据是否正确 + - 检查 bank_id 分配是否和 CTest 中 bb_mem_alloc 一致 + - 检查迭代次数（iter）是否正确 + +4. 结合日志分析 Ball 的 Chisel 源码，定位时序或逻辑问题 +5. 提出修复方案并实施 +6. 重新编译和仿真验证修复结果（通过 MCP 工具） diff --git a/.claude/settings.json b/.claude/settings.json new file mode 100644 index 00000000..aff6200b --- /dev/null +++ b/.claude/settings.json @@ -0,0 +1,9 @@ +{ + "mcpServers": { + "buckyball-dev": { + "type": "stdio", + "command": "python3", + "args": ["scripts/claude/mcp_server.py"] + } + } +} diff --git a/.gitignore b/.gitignore index 627cf4f3..7fa4e75e 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,6 @@ .vscode/ .metals/ -.claude/ +# .claude/ .motia/ .cursor/ .bsp/ diff --git a/CLAUDE.md b/CLAUDE.md new file mode 100644 index 00000000..b6bbd4f8 --- /dev/null +++ b/CLAUDE.md @@ -0,0 +1,94 @@ +# Buckyball + +基于 RISC-V 的 DSA（Domain Specific Architecture）框架。Chisel 6.5.0，Nix Flake 构建。 + +## 项目结构 + +- `arch/src/main/scala/framework/` — 框架核心 + - `balldomain/prototype/` — Ball 算子实现（每个 Ball 一个子目录） + - `balldomain/blink/` — Blink 协议定义（BlinkIO、BankRead/Write、BallStatus） + - `balldomain/configs/` — BallDomainParam + default.json（ballIdMappings） + - `balldomain/bbus/` — BBus 总线 + - `balldomain/rs/` — BallRsIssue / BallRsComplete（命令/完成接口） + - `memdomain/backend/banks/` — SramReadIO / SramWriteIO + - `core/bbtile/` — BBTile 集成（Rocket core + Buckyball） + - `top/` — GlobalConfig（顶层参数汇聚） +- `arch/src/main/scala/examples/toy/balldomain/` — toy 配置 + - `DISA.scala` — 指令 opcode（funct7 BitPat） + - `DomainDecoder.scala` — 指令解码表（ListLookup） + - `bbus/busRegister.scala` — Ball 生成器注册（match case） +- `arch/src/main/scala/sims/` — 仿真配置 + - `verilator/` — Verilator 配置 + - `verify/` — 单 Ball elaboration（BallTopMain） +- `bb-tests/` — 测试 + - `workloads/lib/bbhw/isa/` — ISA C 宏（每条指令一个 .c 文件） + - `workloads/src/CTest/toy/` — C 测试用例 + - `sardine/` — pytest 测试框架 +- `bbdev/` — 开发工具链（Motia 工作流后端） + +## Blink 协议 + +Ball 通过 Blink 协议接入 BBus。每个 Ball 实现 `HasBlink` trait。 + +``` +BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int): + cmdReq: Flipped(Decoupled(BallRsIssue)) // 命令输入（含 BallDecodeCmd + rob_id） + cmdResp: Decoupled(BallRsComplete) // 完成输出（含 rob_id） + bankRead: Vec(inBW, Flipped(BankRead)) // SRAM 读端口 + bankWrite: Vec(outBW, Flipped(BankWrite)) // SRAM 写端口 + status: BallStatus { idle, running } // 状态信号 + +BankRead/BankWrite 元数据字段（均为 Input）: + bank_id, rob_id, ball_id, group_id + +SramReadIO: req.valid/ready + req.bits.addr → resp.valid + resp.bits.data +SramWriteIO: req.valid/ready + req.bits(addr, data, mask, wmode) → resp.valid + resp.bits.ok +``` + +关键时序：SRAM 读延迟 = 1 cycle（req.fire 后下一周期 resp.valid 拉高）。 + +## 注册不变量 + +添加或修改 Ball 注册时，以下 6 项必须同时满足： + +1. `default.json` 的 `ballNum` == `ballIdMappings` 数组长度 +2. `ballId` 严格递增（0, 1, 2, ...），不跳号 +3. `ballId` 无重复 +4. `DISA.scala` 中 funct7 无重复 +5. `busRegister.scala` 中的 case 名称集合 == `default.json` 中的 ballName 集合 +6. `DomainDecoder.scala` 中的 BID 值集合 == `default.json` 中的 ballId 集合 + +用 `/check` 命令可以自动检查所有不变量。 + +## MCP 工具 + +项目配置了 `buckyball-dev` MCP Server，提供以下工具。 + +**重要：编译、仿真、综合、测试等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** +bbdev CLI 是给人类程序员用的，MCP 工具是给 agent 用的——MCP 工具内部会自动管理 bbdev server 生命周期并通过 HTTP API 调用。 + +### 校验 +- `validate` — 检查 6 项注册不变量 + +### bbdev API 封装（自动管理 server 生命周期） +- `bbdev_workload_build` — 编译 CTest +- `bbdev_verilator_run` — 全流程 clean→verilog→build→sim +- `bbdev_verilator_verilog` — 生成 Verilog（支持 balltype 参数单独 elaborate 某个 Ball） +- `bbdev_verilator_build` — 编译 Verilator +- `bbdev_verilator_sim` — 跑仿真 +- `bbdev_sardine_run` — 批量测试（支持 coverage） +- `bbdev_yosys_synth` — Yosys 综合 + OpenSTA 时序分析 + +### 分析报告路径 +- 面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解）、`area_report.txt`（顶层） +- 时序报告：`bbdev/api/steps/yosys/log/timing_report.txt` +- 覆盖率报告：`bb-tests/sardine/reports/coverage/html/` +- 仿真日志：`arch/log//stdout.log`、`disasm.log` + +## 约定 + +- 改 Ball 实现时不要碰注册文件，改注册文件时不要碰实现文件 +- Chisel 版本 6.5.0，不要使用 6.6+ 新 API +- CTest 用 `add_cross_platform_test_target` 注册到 CMakeLists.txt +- **禁止直接调用 `bbdev` CLI 或 `nix develop -c bbdev ...`**，必须通过 MCP 工具调用 +- Ball wrapper 类名必须和 `default.json` 中 `ballName` 一致 diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index be1f91d3..cabccf18 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -9,4 +9,6 @@ object DISA { val TRANSPOSE = BitPat("b0100010") // 34 val RELU = BitPat("b0100110") // 38 val SYSTOLIC = BitPat("b0100111") // 39 + val QUANT = BitPat("b0101000") // 40 + val DEQUANT = BitPat("b0101001") // 41 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 26182f08..213e8399 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -78,7 +78,9 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 1.U, rs2(63, 10)), TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 2.U, rs2(63, 10)), IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)), - SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 4.U, rs2(63, 10)) + SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 4.U, rs2(63, 10)), + QUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 5.U, rs2(63, 10)), + DEQUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 6.U, rs2(63, 10)) ) ) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index c8e8e415..775cc8bf 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -11,6 +11,8 @@ import framework.balldomain.prototype.relu.ReluBall import framework.balldomain.prototype.transpose.TransposeBall import framework.balldomain.prototype.im2col.Im2colBall import framework.balldomain.prototype.systolicarray.SystolicArrayBall +import framework.balldomain.prototype.quant.QuantBall +import framework.balldomain.prototype.dequant.DequantBall /** * BBusModule - Ball bus module that directly extends BBus @@ -26,6 +28,8 @@ class BBusModule(b: GlobalConfig) case "TransposeBall" => () => new TransposeBall(b) case "Im2colBall" => () => new Im2colBall(b) case "SystolicArrayBall" => () => new SystolicArrayBall(b) + case "QuantBall" => () => new QuantBall(b) + case "DequantBall" => () => new DequantBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index da75d29f..51f963b7 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,10 +1,12 @@ { - "ballNum": 5, + "ballNum": 7, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, {"ballId": 2, "ballName": "TransposeBall", "inBW": 1, "outBW": 1}, {"ballId": 3, "ballName": "Im2colBall", "inBW": 1, "outBW": 1}, - {"ballId": 4, "ballName": "SystolicArrayBall", "inBW": 2, "outBW": 4} + {"ballId": 4, "ballName": "SystolicArrayBall", "inBW": 2, "outBW": 4}, + {"ballId": 5, "ballName": "QuantBall", "inBW": 1, "outBW": 1}, + {"ballId": 6, "ballName": "DequantBall", "inBW": 1, "outBW": 1} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala b/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala new file mode 100644 index 00000000..a150db7c --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala @@ -0,0 +1,234 @@ +package framework.balldomain.prototype.dequant + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.top.GlobalConfig + +/** + * Dequant - Dequantization core logic. + * INT32 -> FP32: fp32_val = int32_val * scale + * Each 128-bit SRAM word = 4 x INT32. Output: 4 x FP32 = 128 bits. 1:1 read/write. + * Scale from cmd.special(31,0) as FP32 bit pattern. + * + * FSM follows ReluBall pattern: + * idle -> sRead -> sWrite -> complete -> idle + */ +@instantiable +class Dequant(val b: GlobalConfig) extends Module { + val elemsPerWord = 4 + val bankWidth = b.memDomain.bankWidth + val InputNum = 16 + + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "DequantBall") + .getOrElse(throw new IllegalArgumentException("DequantBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + } + + val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) + val state = RegInit(idle) + + val regArray = RegInit(VecInit(Seq.fill(InputNum)(0.U(bankWidth.W)))) + + val readCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + + val raddr_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val waddr_reg = RegInit(0.U(10.W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(10.W)) + val scale_reg = RegInit(0.U(32.W)) + + // Default outputs + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).group_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).group_id := 0.U + } + + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + // INT32 to FP32 + def int32ToFp32(intVal: UInt): UInt = { + val signed = intVal.asSInt + val is_zero = signed === 0.S + val sign = intVal(31) + val absVal = Wire(UInt(32.W)) + absVal := Mux(sign.asBool, (~intVal + 1.U), intVal) + + val leadingOne = Wire(UInt(5.W)) + leadingOne := (30.U - PriorityEncoder(Reverse(absVal(30, 0)))) + + val exponent = Wire(UInt(8.W)) + exponent := leadingOne +& 127.U + + val mantissa = Wire(UInt(23.W)) + when(leadingOne >= 23.U) { + mantissa := (absVal >> (leadingOne - 23.U))(22, 0) + }.otherwise { + mantissa := (absVal << (23.U - leadingOne))(22, 0) + } + + val result = Wire(UInt(32.W)) + when(is_zero) { + result := 0.U + }.otherwise { + result := Cat(sign, exponent, mantissa) + } + result + } + + // FP32 multiply + def fp32Multiply(a: UInt, bv: UInt): UInt = { + val a_sign = a(31) + val b_sign = bv(31) + val a_exp = a(30, 23) + val b_exp = bv(30, 23) + val a_mant = Cat(1.U(1.W), a(22, 0)) + val b_mant = Cat(1.U(1.W), bv(22, 0)) + val result_sign = a_sign ^ b_sign + val a_is_zero = a_exp === 0.U && a(22, 0) === 0.U + val b_is_zero = b_exp === 0.U && bv(22, 0) === 0.U + val mant_product = (a_mant * b_mant)(47, 0) + val mant_shifted = Wire(UInt(24.W)) + val exp_adjust = Wire(UInt(1.W)) + when(mant_product(47)) { + mant_shifted := mant_product(47, 24) + exp_adjust := 1.U + }.otherwise { + mant_shifted := mant_product(46, 23) + exp_adjust := 0.U + } + val result_exp_wide = a_exp +& b_exp +& exp_adjust - 127.U + val result_exp = result_exp_wide(7, 0) + val result = Wire(UInt(32.W)) + when(a_is_zero || b_is_zero) { + result := 0.U + }.elsewhen(result_exp_wide(9, 8) =/= 0.U && result_exp_wide(9)) { + result := 0.U + }.elsewhen(result_exp_wide(8) && !result_exp_wide(9)) { + result := Cat(result_sign, 255.U(8.W), 0.U(23.W)) + }.otherwise { + result := Cat(result_sign, result_exp, mant_shifted(22, 0)) + } + result + } + + // FSM + switch(state) { + is(idle) { + when(io.cmdReq.fire) { + state := sRead + readCounter := 0.U + respCounter := 0.U + writeCounter := 0.U + raddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + waddr_reg := 0.U + wbank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter + scale_reg := io.cmdReq.bits.cmd.special(31, 0) + } + } + + is(sRead) { + io.bankRead(0).io.resp.ready := true.B + + io.bankRead(0).io.req.valid := readCounter < iter_reg + io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter + + when(io.bankRead(0).io.req.fire) { + readCounter := readCounter + 1.U + } + + val dataWord = io.bankRead(0).io.resp.bits.data + + when(io.bankRead(0).io.resp.fire) { + val results = Wire(Vec(elemsPerWord, UInt(32.W))) + for (i <- 0 until elemsPerWord) { + val int_elem = dataWord((i + 1) * 32 - 1, i * 32) + val fp_elem = int32ToFp32(int_elem) + results(i) := fp32Multiply(fp_elem, scale_reg) + } + regArray(respCounter) := Cat(results.reverse) + respCounter := respCounter + 1.U + + when(respCounter === (iter_reg - 1.U)) { + state := sWrite + } + } + } + + is(sWrite) { + val hasMore = writeCounter < iter_reg + + io.bankWrite(0).io.req.valid := hasMore + io.bankWrite(0).io.req.bits.addr := waddr_reg + writeCounter + io.bankWrite(0).io.req.bits.data := regArray(writeCounter) + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) + io.bankWrite(0).io.resp.ready := true.B + + when(io.bankWrite(0).io.req.fire) { + when(writeCounter === (iter_reg - 1.U)) { + state := complete + }.otherwise { + writeCounter := writeCounter + 1.U + } + } + } + + is(complete) { + io.bankWrite(0).io.resp.ready := true.B + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + when(io.cmdResp.fire) { + state := idle + } + } + } + + io.status.idle := state === idle + io.status.running := (state === sRead) || (state === sWrite) +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala b/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala new file mode 100644 index 00000000..857a65a6 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala @@ -0,0 +1,36 @@ +package framework.balldomain.prototype.dequant + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.top.GlobalConfig + +@instantiable +class DequantBall(val b: GlobalConfig) extends Module with HasBlink { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "DequantBall") + .getOrElse(throw new IllegalArgumentException("DequantBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + + val dequantUnit: Instance[Dequant] = Instantiate(new Dequant(b)) + + dequantUnit.io.cmdReq <> io.cmdReq + dequantUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + dequantUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + dequantUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + io.status <> dequantUnit.io.status +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/configs/DequantBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/dequant/configs/DequantBallParam.scala new file mode 100644 index 00000000..96223f15 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/configs/DequantBallParam.scala @@ -0,0 +1,17 @@ +package framework.balldomain.prototype.dequant.configs + +import upickle.default._ + +case class DequantBallParam( + placeholder: Boolean) + +object DequantBallParam { + implicit val rw: ReadWriter[DequantBallParam] = macroRW + + def apply(): DequantBallParam = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/framework/balldomain/prototype/dequant/configs/default.json").mkString + read[DequantBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/dequant/configs/default.json new file mode 100644 index 00000000..97ac37b6 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/configs/default.json @@ -0,0 +1,3 @@ +{ + "placeholder": true +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala b/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala new file mode 100644 index 00000000..f510a193 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala @@ -0,0 +1,306 @@ +package framework.balldomain.prototype.quant + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.top.GlobalConfig +import framework.balldomain.prototype.quant.configs.QuantBallParam + +/** + * Quant - Quantization core logic. + * + * INT32 mode: FP32 -> INT32 + * Each 128-bit SRAM word = 4 x FP32. + * Output: 4 x INT32 = 128 bits. 1:1 read/write. + * + * INT8 mode: FP32 -> INT8 + * Read 4 words (16 FP32), pack into 1 output word (16 x INT8 = 128 bits). 4:1 read/write. + * + * Scale factor from cmd.special(31,0) as FP32 bit pattern. + * + * FSM follows ReluBall pattern: + * idle -> sRead (pipelined read all words, process on resp) -> sWrite (write all results) -> complete -> idle + */ +@instantiable +class Quant(val b: GlobalConfig) extends Module { + val ballConfig = QuantBallParam() + val isInt8 = ballConfig.targetType == "INT8" + val elemsPerWord = 4 + val bankWidth = b.memDomain.bankWidth + // For INT32: InputNum = iter (max 16), for INT8: InputNum = iter (output words, max 16) + val InputNum = 16 // max elements per dimension, matching ReluBall + + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "QuantBall") + .getOrElse(throw new IllegalArgumentException("QuantBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + } + + // FSM + val idle :: sRead :: sWrite :: complete :: Nil = Enum(4) + val state = RegInit(idle) + + // Result storage: up to InputNum output words, each 128 bits + val regArray = RegInit(VecInit(Seq.fill(InputNum)(0.U(bankWidth.W)))) + + val readCounter = RegInit(0.U(log2Ceil(InputNum * 4 + 1).W)) // request counter + val respCounter = RegInit(0.U(log2Ceil(InputNum * 4 + 1).W)) // response counter + val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) + + val raddr_reg = RegInit(0.U(10.W)) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val waddr_reg = RegInit(0.U(10.W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(10.W)) + val scale_reg = RegInit(0.U(32.W)) + + // For INT8: accumulate 4 responses into one output word + val int8AccumIdx = RegInit(0.U(2.W)) // 0..3 within current output word + val int8OutIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // output word index + + // Total read requests needed + val totalReads = Wire(UInt(10.W)) + if (isInt8) { + totalReads := iter_reg << 2 + } else { + totalReads := iter_reg + } + + val writeDataReg = Reg(UInt(bankWidth.W)) + val writeMaskReg = Reg(Vec(b.memDomain.bankMaskLen, UInt(1.W))) + + // Default outputs + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).group_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).group_id := 0.U + } + + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + // ---- FP32 multiply ---- + def fp32Multiply(a: UInt, bv: UInt): UInt = { + val a_sign = a(31) + val b_sign = bv(31) + val a_exp = a(30, 23) + val b_exp = bv(30, 23) + val a_mant = Cat(1.U(1.W), a(22, 0)) + val b_mant = Cat(1.U(1.W), bv(22, 0)) + val result_sign = a_sign ^ b_sign + val a_is_zero = a_exp === 0.U && a(22, 0) === 0.U + val b_is_zero = b_exp === 0.U && bv(22, 0) === 0.U + val mant_product = (a_mant * b_mant)(47, 0) + val mant_shifted = Wire(UInt(24.W)) + val exp_adjust = Wire(UInt(1.W)) + when(mant_product(47)) { + mant_shifted := mant_product(47, 24) + exp_adjust := 1.U + }.otherwise { + mant_shifted := mant_product(46, 23) + exp_adjust := 0.U + } + val result_exp_wide = a_exp +& b_exp +& exp_adjust - 127.U + val result_exp = result_exp_wide(7, 0) + val result = Wire(UInt(32.W)) + when(a_is_zero || b_is_zero) { + result := 0.U + }.elsewhen(result_exp_wide(9, 8) =/= 0.U && result_exp_wide(9)) { + result := 0.U + }.elsewhen(result_exp_wide(8) && !result_exp_wide(9)) { + result := Cat(result_sign, 255.U(8.W), 0.U(23.W)) + }.otherwise { + result := Cat(result_sign, result_exp, mant_shifted(22, 0)) + } + result + } + + def fp32ToInt32(fp: UInt): UInt = { + val sign = fp(31) + val exponent = fp(30, 23) + val mantissa = Cat(1.U(1.W), fp(22, 0)) + val is_zero = exponent === 0.U && fp(22, 0) === 0.U + val exp_val = exponent.asSInt - 127.S + val result = Wire(SInt(32.W)) + when(is_zero) { + result := 0.S + }.elsewhen(exp_val >= 31.S) { + result := Mux(sign.asBool, -2147483648L.S(32.W), 2147483647.S(32.W)) + }.elsewhen(exp_val < 0.S) { + when(exp_val === -1.S) { + result := Mux(sign.asBool, -1.S(32.W), 1.S(32.W)) + }.otherwise { + result := 0.S + } + }.otherwise { + val shift_amount = exp_val.asUInt(4, 0) + val magnitude = Wire(UInt(32.W)) + when(shift_amount >= 23.U) { + magnitude := mantissa << (shift_amount - 23.U) + }.otherwise { + magnitude := mantissa >> (23.U - shift_amount) + } + result := Mux(sign.asBool, -(magnitude.asSInt), magnitude.asSInt) + } + result.asUInt + } + + def fp32ToInt8(fp: UInt): UInt = { + val int32val = fp32ToInt32(fp).asSInt + val clamped = Wire(SInt(8.W)) + when(int32val > 127.S) { + clamped := 127.S(8.W) + }.elsewhen(int32val < -128.S) { + clamped := -128.S(8.W) + }.otherwise { + clamped := int32val(7, 0).asSInt + } + clamped.asUInt + } + + // ---- FSM ---- + switch(state) { + is(idle) { + when(io.cmdReq.fire) { + state := sRead + readCounter := 0.U + respCounter := 0.U + writeCounter := 0.U + raddr_reg := 0.U + rbank_reg := io.cmdReq.bits.cmd.op1_bank + waddr_reg := 0.U + wbank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter + scale_reg := io.cmdReq.bits.cmd.special(31, 0) + if (isInt8) { + int8AccumIdx := 0.U + int8OutIdx := 0.U + } + } + } + + is(sRead) { + io.bankRead(0).io.resp.ready := true.B + + // Send read requests (pipelined) + io.bankRead(0).io.req.valid := readCounter < totalReads + io.bankRead(0).io.req.bits.addr := raddr_reg + readCounter + + when(io.bankRead(0).io.req.fire) { + readCounter := readCounter + 1.U + } + + // Process responses (1 cycle latency after req) + val dataWord = io.bankRead(0).io.resp.bits.data + + when(io.bankRead(0).io.resp.fire) { + if (isInt8) { + // Quantize 4 FP32 -> 4 INT8, store in current output word + val packedBytes = Wire(Vec(4, UInt(8.W))) + for (i <- 0 until elemsPerWord) { + val fp_elem = dataWord((i + 1) * 32 - 1, i * 32) + val scaled = fp32Multiply(fp_elem, scale_reg) + packedBytes(i) := fp32ToInt8(scaled) + } + // Write 4 bytes into the correct position of regArray(int8OutIdx) + // Position: int8AccumIdx * 32 bits + val shift = int8AccumIdx * 32.U + val mask = ~(Fill(32, 1.U(1.W)) << shift) + val newBits = Cat(packedBytes(3), packedBytes(2), packedBytes(1), packedBytes(0)) + regArray(int8OutIdx) := (regArray(int8OutIdx) & mask) | (newBits.asUInt << shift) + + when(int8AccumIdx === 3.U) { + int8AccumIdx := 0.U + int8OutIdx := int8OutIdx + 1.U + }.otherwise { + int8AccumIdx := int8AccumIdx + 1.U + } + } else { + // INT32 mode: quantize 4 FP32 -> 4 INT32, pack into 128-bit word + val results = Wire(Vec(elemsPerWord, UInt(32.W))) + for (i <- 0 until elemsPerWord) { + val fp_elem = dataWord((i + 1) * 32 - 1, i * 32) + val scaled = fp32Multiply(fp_elem, scale_reg) + results(i) := fp32ToInt32(scaled) + } + regArray(respCounter) := Cat(results.reverse) + } + respCounter := respCounter + 1.U + + // Check if all responses received + val totalResps = if (isInt8) iter_reg << 2 else iter_reg + when(respCounter === (totalResps - 1.U)) { + state := sWrite + } + } + } + + is(sWrite) { + val hasMore = writeCounter < iter_reg + + io.bankWrite(0).io.req.valid := hasMore + io.bankWrite(0).io.req.bits.addr := waddr_reg + writeCounter + io.bankWrite(0).io.req.bits.data := regArray(writeCounter) + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) + io.bankWrite(0).io.resp.ready := true.B + + when(io.bankWrite(0).io.req.fire) { + when(writeCounter === (iter_reg - 1.U)) { + state := complete + }.otherwise { + writeCounter := writeCounter + 1.U + } + } + } + + is(complete) { + io.bankWrite(0).io.resp.ready := true.B + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + when(io.cmdResp.fire) { + state := idle + } + } + } + + io.status.idle := state === idle + io.status.running := (state === sRead) || (state === sWrite) +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala b/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala new file mode 100644 index 00000000..99a21c48 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala @@ -0,0 +1,36 @@ +package framework.balldomain.prototype.quant + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.top.GlobalConfig + +@instantiable +class QuantBall(val b: GlobalConfig) extends Module with HasBlink { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "QuantBall") + .getOrElse(throw new IllegalArgumentException("QuantBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + + val quantUnit: Instance[Quant] = Instantiate(new Quant(b)) + + quantUnit.io.cmdReq <> io.cmdReq + quantUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + quantUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + quantUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + io.status <> quantUnit.io.status +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/configs/QuantBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/quant/configs/QuantBallParam.scala new file mode 100644 index 00000000..20dac444 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/configs/QuantBallParam.scala @@ -0,0 +1,18 @@ +package framework.balldomain.prototype.quant.configs + +import upickle.default._ + +case class QuantBallParam( + targetType: String // "INT32" or "INT8" +) + +object QuantBallParam { + implicit val rw: ReadWriter[QuantBallParam] = macroRW + + def apply(): QuantBallParam = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/framework/balldomain/prototype/quant/configs/default.json").mkString + read[QuantBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/quant/configs/default.json new file mode 100644 index 00000000..46314b30 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/configs/default.json @@ -0,0 +1,3 @@ +{ + "targetType": "INT32" +} diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala index 362ae993..55482eeb 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala @@ -6,9 +6,9 @@ import framework.memdomain.backend.banks.{SramReadIO, SramWriteIO} import framework.top.GlobalConfig class MemRequestIO(b: GlobalConfig) extends Bundle { - val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend - val read = Flipped(new SramReadIO(b)) // midend sends read req into backend - val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val group_id = Output(UInt(3.W)) + val write = Flipped(new SramWriteIO(b)) // midend sends write req into backend + val read = Flipped(new SramReadIO(b)) // midend sends read req into backend + val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val group_id = Output(UInt(3.W)) val is_shared = Output(Bool()) } diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index 4d53f9e6..8cc9c70f 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.memdomain.frontend.outside_channel.MemConfigerIO -import framework.memdomain.backend.{MemRequestIO, MTraceDPI} +import framework.memdomain.backend.{MTraceDPI, MemRequestIO} import framework.memdomain.backend.accpipe.AccPipe import framework.memdomain.backend.banks.SramBank import framework.top.GlobalConfig @@ -89,8 +89,8 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read - accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id - accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared // Bank-side defaults (only driven when a bank is actually connected) @@ -145,7 +145,14 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Connect AccPipe and Banks // ----------------------------------------------------------------------------- - private def emitTrace(ch: Int, isWrite: UInt, addr: UInt, dataLo: UInt, dataHi: UInt, en: Bool): Unit = { + private def emitTrace( + ch: Int, + isWrite: UInt, + addr: UInt, + dataLo: UInt, + dataHi: UInt, + en: Bool + ): Unit = { mtraces(ch).io.is_write := isWrite mtraces(ch).io.channel := ch.U mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index bbda8629..0d03a9f0 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -33,9 +33,9 @@ class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { @instantiable class SharedMem(val b: GlobalConfig) extends Module { - private val maskLen = b.memDomain.bankMaskLen - private val maskElem = UInt((b.memDomain.bankWidth / maskLen).W) - private val minSharedLines = b.memDomain.bankNum * b.memDomain.bankEntries + private val maskLen = b.memDomain.bankMaskLen + private val maskElem = UInt((b.memDomain.bankWidth / maskLen).W) + private val minSharedLines = b.memDomain.bankNum * b.memDomain.bankEntries require( b.memDomain.sharedEntries >= minSharedLines, @@ -48,14 +48,14 @@ class SharedMem(val b: GlobalConfig) extends Module { val write = new SharedMemWriteIO(b) }) - val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(maskLen, maskElem)) + val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(maskLen, maskElem)) - // Shared memory address mapping (group_id intentionally ignored): - // shared_addr = (vbank_id * bankEntries) + local_addr - private def toSharedAddr(vbank_id: UInt, _group_id: UInt, local_addr: UInt): UInt = { - val vbankPart = vbank_id * b.memDomain.bankEntries.U - vbankPart + local_addr - } + // Shared memory address mapping (group_id intentionally ignored): + // shared_addr = (vbank_id * bankEntries) + local_addr + private def toSharedAddr(vbank_id: UInt, _group_id: UInt, local_addr: UInt): UInt = { + val vbankPart = vbank_id * b.memDomain.bankEntries.U + vbankPart + local_addr + } io.read.req.ready := !io.write.req.valid io.write.req.ready := !io.read.req.valid @@ -63,10 +63,10 @@ class SharedMem(val b: GlobalConfig) extends Module { val readReqFire = io.read.req.fire val readAddr = toSharedAddr(io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) - when(readReqFire) { - assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") - assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") - } + when(readReqFire) { + assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + } val readData = mem.read(readAddr, readReqFire) @@ -76,15 +76,15 @@ class SharedMem(val b: GlobalConfig) extends Module { val writeReqFire = io.write.req.fire val writeAddr = toSharedAddr(io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) - when(writeReqFire) { - assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") - assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") - mem.write( - writeAddr, - io.write.req.bits.data.asTypeOf(Vec(maskLen, maskElem)), - io.write.req.bits.mask - ) - } + when(writeReqFire) { + assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") + mem.write( + writeAddr, + io.write.req.bits.data.asTypeOf(Vec(maskLen, maskElem)), + io.write.req.bits.mask + ) + } io.write.resp.valid := RegNext(writeReqFire, init = false.B) io.write.resp.bits.ok := RegNext(writeReqFire, init = false.B) diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index f6acb568..0b038e18 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -3,7 +3,7 @@ package framework.memdomain.backend.shared import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.memdomain.backend.{MemRequestIO, MTraceDPI} +import framework.memdomain.backend.{MTraceDPI, MemRequestIO} import framework.memdomain.backend.accpipe.AccPipe import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig @@ -32,9 +32,9 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val query_group_count = Output(UInt(4.W)) }) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) - val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) - val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) + val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) val sharedAllocTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) for (mt <- mtraces) { @@ -69,8 +69,8 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read - accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id - accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared accPipes(i).io.sramRead.req.ready := false.B @@ -95,7 +95,14 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- // Shared request routing arbiter // --------------------------------------------------------------------------- - private def emitTrace(ch: Int, isWrite: UInt, addr: UInt, dataLo: UInt, dataHi: UInt, en: Bool): Unit = { + private def emitTrace( + ch: Int, + isWrite: UInt, + addr: UInt, + dataLo: UInt, + dataHi: UInt, + en: Bool + ): Unit = { mtraces(ch).io.is_write := isWrite mtraces(ch).io.channel := ch.U mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id @@ -132,7 +139,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { sharedReqArb.io.in(i).bits.is_write := useWrite sharedReqArb.io.in(i).bits.vbank_id := io.mem_req(i).bank_id sharedReqArb.io.in(i).bits.group_id := 0.U - sharedReqArb.io.in(i).bits.addr := Mux( + sharedReqArb.io.in(i).bits.addr := Mux( useRead, accPipes(i).io.sramRead.req.bits.addr, accPipes(i).io.sramWrite.req.bits.addr diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 1ceae233..1205da5a 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -31,8 +31,8 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Bank read/write interface - used by load/store val interdma = new Bundle { - val bankRead = Flipped(new BankRead(b)) - val bankWrite = Flipped(new BankWrite(b)) + val bankRead = Flipped(new BankRead(b)) + val bankWrite = Flipped(new BankWrite(b)) val read_is_shared = Output(Bool()) val write_is_shared = Output(Bool()) } diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index 1cb4b53a..30637c78 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -6,8 +6,8 @@ import chisel3.util._ object DISA { val SHARED_MVIN_BITPAT = BitPat("b0010101") // 21 - val SHARED_MVOUT_BITPAT = BitPat("b0010110") // 22 - val MSET_BITPAT = BitPat("b0010111") // 23 - val MVIN_BITPAT = BitPat("b0011000") // 24 - val MVOUT_BITPAT = BitPat("b0011001") // 25 + val SHARED_MVOUT_BITPAT = BitPat("b0010110") // 22 + val MSET_BITPAT = BitPat("b0010111") // 23 + val MVIN_BITPAT = BitPat("b0011000") // 24 + val MVOUT_BITPAT = BitPat("b0011001") // 25 } diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index cec1d19b..db7df0c9 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -10,7 +10,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} // Detailed decode output for Mem domain class MemDecodeCmd(b: GlobalConfig) extends Bundle { - val is_shared = Bool() // Whether this is a shared memory access (for synchronization) + val is_shared = Bool() // Whether this is a shared memory access (for synchronization) val is_load = Bool() val is_store = Bool() val is_config = Bool() @@ -75,7 +75,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { func7, ls_default_decode, Array( - MSET_BITPAT -> List( + MSET_BITPAT -> List( N, N, N, @@ -85,7 +85,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs2(39, 0), // special from rs2[39:0] Y ), // mset - MVIN_BITPAT -> List( + MVIN_BITPAT -> List( N, Y, N, @@ -95,7 +95,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs2(63, 10), // special from rs2[63:10] Y ), // mvin - MVOUT_BITPAT -> List( + MVOUT_BITPAT -> List( N, N, Y, @@ -105,7 +105,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs2(63, 10), // special from rs2[63:10] Y ), // mvout - SHARED_MVIN_BITPAT -> List( + SHARED_MVIN_BITPAT -> List( Y, Y, N, @@ -139,7 +139,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- io.mem_decode_cmd_o.valid := io.cmd_i.valid && (io.cmd_i.bits.domain_id === DomainId.MEM) - io.mem_decode_cmd_o.bits.is_shared := Mux( + io.mem_decode_cmd_o.bits.is_shared := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.SHARED_EN.id).asBool, false.B diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 7a95e902..a6986f49 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -35,12 +35,12 @@ class MemLoader(val b: GlobalConfig) extends Module { val s_idle :: s_dma_req :: s_dma_wait :: s_wait_last_write :: s_done :: Nil = Enum(5) val state = RegInit(s_idle) - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) - val iter_reg = Reg(UInt(10.W)) - val resp_count = RegInit(0.U(log2Up(16).W)) - val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - val stride_reg = Reg(UInt(11.W)) + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) + val iter_reg = Reg(UInt(10.W)) + val resp_count = RegInit(0.U(log2Up(16).W)) + val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) + val stride_reg = Reg(UInt(11.W)) val is_shared_reg = RegInit(false.B) // Group counter for multi-bank writes diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 5ceb4eb0..fded4747 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -24,8 +24,8 @@ class MemMidend(val b: GlobalConfig) extends Module { // Input from frontend (Ball Domain read/write requests) - receiver perspective val frontend = new Bundle { - val bankRead = new BankRead(b) - val bankWrite = new BankWrite(b) + val bankRead = new BankRead(b) + val bankWrite = new BankWrite(b) val read_is_shared = Input(Bool()) val write_is_shared = Input(Bool()) } @@ -139,12 +139,12 @@ class MemMidend(val b: GlobalConfig) extends Module { //Connect frontend to backend io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io - io.mem_req(b.top.memBallChannelNum).bank_id := Mux( + io.mem_req(b.top.memBallChannelNum).bank_id := Mux( io.frontend.bankRead.io.req.valid, io.frontend.bankRead.bank_id, io.frontend.bankWrite.bank_id ) - io.mem_req(b.top.memBallChannelNum).group_id := Mux( + io.mem_req(b.top.memBallChannelNum).group_id := Mux( io.frontend.bankRead.io.req.valid, io.frontend.bankRead.group_id, io.frontend.bankWrite.group_id diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index aa018fa2..7b8df251 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -83,6 +83,14 @@ "ctest_im2col_test_singlecore-baremetal", "ctest_im2col_test_singlecore-baremetal", ), + ( + "ctest_quant_test_singlecore-baremetal", + "ctest_quant_test_singlecore-baremetal", + ), + ( + "ctest_dequant_test_singlecore-baremetal", + "ctest_dequant_test_singlecore-baremetal", + ), ] diff --git a/bb-tests/workloads/lib/bbhw/isa/40_quant.c b/bb-tests/workloads/lib/bbhw/isa/40_quant.c new file mode 100644 index 00000000..95e59e35 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/40_quant.c @@ -0,0 +1,18 @@ +#ifndef _BB_QUANT_H_ +#define _BB_QUANT_H_ + +#include "isa.h" + +#define BB_QUANT_FUNC7 40 + +// bb_quant(bank_id, wr_bank_id, iter, scale_fp32) +// scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern +// Encoding: rs1 = BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR +// rs2 = FIELD(iter, 0, 9) | FIELD(scale_fp32, 10, 41) +#define bb_quant(bank_id, wr_bank_id, iter, scale_fp32) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ + (FIELD(iter, 0, 9) | FIELD((uint64_t)(scale_fp32), 10, 41)), \ + BB_QUANT_FUNC7) + +#endif // _BB_QUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_dequant.c b/bb-tests/workloads/lib/bbhw/isa/41_dequant.c new file mode 100644 index 00000000..4f4d907a --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/41_dequant.c @@ -0,0 +1,18 @@ +#ifndef _BB_DEQUANT_H_ +#define _BB_DEQUANT_H_ + +#include "isa.h" + +#define BB_DEQUANT_FUNC7 41 + +// bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) +// scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern +// Encoding: rs1 = BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR +// rs2 = FIELD(iter, 0, 9) | FIELD(scale_fp32, 10, 41) +#define bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ + (FIELD(iter, 0, 9) | FIELD((uint64_t)(scale_fp32), 10, 41)), \ + BB_DEQUANT_FUNC7) + +#endif // _BB_DEQUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 1834856d..a51fdbb7 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -51,5 +51,7 @@ typedef int32_t result_t; #include "34_transpose.c" #include "38_relu.c" #include "39_bfp.c" +#include "40_quant.c" +#include "41_dequant.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 766b2249..aa6a5853 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -109,7 +109,6 @@ add_cross_platform_test_target(ctest_vecunit_matmul_16xn_random1 vecunit_matmul_ add_cross_platform_test_target(ctest_vecunit_matmul_16xn_random2 vecunit_matmul_16xn_random2.c) add_cross_platform_test_target(ctest_vecunit_matmul_16xn_random3 vecunit_matmul_16xn_random3.c) add_cross_platform_test_target(ctest_vecunit_matmul_16xn_zero_random vecunit_matmul_16xn_zero_random.c) -add_cross_platform_test_target(ctest_vecunit_simple_nn_forward_pass_test vecunit_simple_nn_forward_pass_test.c) add_cross_platform_test_target(ctest_im2col_test im2col_test.c) add_cross_platform_test_target(ctest_transpose_test transpose_test.c) add_cross_platform_test_target(ctest_transpose_16xn_test transpose_16xn_test.c) @@ -117,6 +116,8 @@ add_cross_platform_test_target(ctest_transpose_matmul transpose_matmul.c) add_cross_platform_test_target(ctest_relu_test relu_test.c) add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) add_cross_platform_test_target(ctest_bfp_test bfp_test.c) +add_cross_platform_test_target(ctest_quant_test quant_test.c) +add_cross_platform_test_target(ctest_dequant_test dequant_test.c) # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS @@ -135,7 +136,6 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_vecunit_matmul_16xn_random2 ctest_vecunit_matmul_16xn_random3 ctest_vecunit_matmul_16xn_zero_random - ctest_vecunit_simple_nn_forward_pass_test ctest_im2col_test ctest_transpose_test ctest_transpose_16xn_test @@ -143,5 +143,7 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_relu_test ctest_vsetvli ctest_bfp_test + ctest_quant_test + ctest_dequant_test COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/dequant_test.c b/bb-tests/workloads/src/CTest/toy/dequant_test.c new file mode 100644 index 00000000..8d8ff0bc --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/dequant_test.c @@ -0,0 +1,87 @@ +#include "buckyball.h" +#include +#include +#include +#include +#include + +#define DIM 16 + +// INT32 input data (4 elements per SRAM word, 16 words) +static int32_t int32_input[DIM * 4] __attribute__((aligned(64))) = { + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 7, 100, -100, 8, 16, -8, + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 7, 100, -100, 8, 16, -8, + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 7, 100, -100, 8, 16, -8, + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 7, 100, -100, 8, 16, -8, +}; + +// Expected FP32 output as bit patterns: int32_val * 1.0 = float(int32_val) +// 1.0=0x3F800000, 2.0=0x40000000, 3.0=0x40400000, -1.0=0xBF800000 +// -2.0=0xC0000000, 0.0=0x00000000, 4.0=0x40800000, 5.0=0x40A00000 +// 10.0=0x41200000, -10.0=0xC1200000, 7.0=0x40E00000, 100.0=0x42C80000 +// -100.0=0xC2C80000, 8.0=0x41000000, 16.0=0x41800000, -8.0=0xC1000000 +static uint32_t expected_fp32[DIM * 4] __attribute__((aligned(64))) = { + 0x3F800000, 0x40000000, 0x40400000, 0xBF800000, 0xC0000000, 0x00000000, + 0x40800000, 0x40A00000, 0x41200000, 0xC1200000, 0x40E00000, 0x42C80000, + 0xC2C80000, 0x41000000, 0x41800000, 0xC1000000, 0x3F800000, 0x40000000, + 0x40400000, 0xBF800000, 0xC0000000, 0x00000000, 0x40800000, 0x40A00000, + 0x41200000, 0xC1200000, 0x40E00000, 0x42C80000, 0xC2C80000, 0x41000000, + 0x41800000, 0xC1000000, 0x3F800000, 0x40000000, 0x40400000, 0xBF800000, + 0xC0000000, 0x00000000, 0x40800000, 0x40A00000, 0x41200000, 0xC1200000, + 0x40E00000, 0x42C80000, 0xC2C80000, 0x41000000, 0x41800000, 0xC1000000, + 0x3F800000, 0x40000000, 0x40400000, 0xBF800000, 0xC0000000, 0x00000000, + 0x40800000, 0x40A00000, 0x41200000, 0xC1200000, 0x40E00000, 0x42C80000, + 0xC2C80000, 0x41000000, 0x41800000, 0xC1000000, +}; + +static uint32_t output_fp32[DIM * 4] __attribute__((aligned(64))); + +// FP32 bit pattern for scale = 1.0 +#define SCALE_1_0 0x3F800000U + +void hw_dequant(int32_t *input, uint32_t *output, int num_words) { + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); + + bb_mvin((uintptr_t)input, op1_bank_id, num_words, 1); + + bb_dequant(op1_bank_id, wr_bank_id, num_words, SCALE_1_0); + + bb_mvout((uintptr_t)output, wr_bank_id, num_words, 1); + bb_fence(); +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + for (int i = 0; i < DIM * 4; i++) { + output_fp32[i] = 0; + } + + hw_dequant(int32_input, output_fp32, DIM); + + int passed = 1; + for (int i = 0; i < DIM * 4; i++) { + if (output_fp32[i] != expected_fp32[i]) { + printf("MISMATCH at [%d]: got 0x%08X, expected 0x%08X\n", i, + output_fp32[i], expected_fp32[i]); + passed = 0; + } + } + + if (passed) { + printf("Dequant test PASSED\n"); + } else { + printf("Dequant test FAILED\n"); + } + return (!passed); + +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/toy/quant_test.c b/bb-tests/workloads/src/CTest/toy/quant_test.c new file mode 100644 index 00000000..14d8a87f --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/quant_test.c @@ -0,0 +1,147 @@ +#include "buckyball.h" +#include +#include +#include +#include +#include + +#define DIM 16 + +// FP32 bit patterns for input data (4 elements per SRAM word, 16 words = 64 +// FP32 values) Using scale = 1.0 so INT32 result = round(fp32_val * 1.0) = +// round(fp32_val) Values: 1.0, 2.0, 3.0, -1.0, -2.0, 0.0, 4.0, 5.0, 10.0, +// -10.0, 0.5, 100.0, -100.0, 7.0, 8.0, -8.0 Repeated 4 times to fill 16 words +// (64 elements) + +static uint32_t fp32_input[DIM * 4] __attribute__((aligned(64))) = { + // Word 0-3 (row 0): 1.0, 2.0, 3.0, -1.0 | -2.0, 0.0, 4.0, 5.0 | 10.0, + // -10.0, 0.5, 100.0 | -100.0, 7.0, 8.0, -8.0 + 0x3F800000, + 0x40000000, + 0x40400000, + 0xBF800000, + 0xC0000000, + 0x00000000, + 0x40800000, + 0x40A00000, + 0x41200000, + 0xC1200000, + 0x3F000000, + 0x42C80000, + 0xC2C80000, + 0x40E00000, + 0x41000000, + 0xC1000000, + // Word 4-7 (row 1): same pattern + 0x3F800000, + 0x40000000, + 0x40400000, + 0xBF800000, + 0xC0000000, + 0x00000000, + 0x40800000, + 0x40A00000, + 0x41200000, + 0xC1200000, + 0x3F000000, + 0x42C80000, + 0xC2C80000, + 0x40E00000, + 0x41000000, + 0xC1000000, + // Word 8-11 (row 2): same pattern + 0x3F800000, + 0x40000000, + 0x40400000, + 0xBF800000, + 0xC0000000, + 0x00000000, + 0x40800000, + 0x40A00000, + 0x41200000, + 0xC1200000, + 0x3F000000, + 0x42C80000, + 0xC2C80000, + 0x40E00000, + 0x41000000, + 0xC1000000, + // Word 12-15 (row 3): same pattern + 0x3F800000, + 0x40000000, + 0x40400000, + 0xBF800000, + 0xC0000000, + 0x00000000, + 0x40800000, + 0x40A00000, + 0x41200000, + 0xC1200000, + 0x3F000000, + 0x42C80000, + 0xC2C80000, + 0x40E00000, + 0x41000000, + 0xC1000000, +}; + +// Expected INT32 output: round(fp32 * 1.0) +// 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 1, 100, -100, 7, 8, -8 (0.5 rounds to 1) +static int32_t expected_int32[DIM * 4] __attribute__((aligned(64))) = { + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 1, 100, -100, 7, 8, -8, + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 1, 100, -100, 7, 8, -8, + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 1, 100, -100, 7, 8, -8, + 1, 2, 3, -1, -2, 0, 4, 5, 10, -10, 1, 100, -100, 7, 8, -8, +}; + +static int32_t output_int32[DIM * 4] __attribute__((aligned(64))); + +// FP32 bit pattern for scale = 1.0 +#define SCALE_1_0 0x3F800000U + +void hw_quant(uint32_t *input, int32_t *output, int num_words) { + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); + + bb_mvin((uintptr_t)input, op1_bank_id, num_words, 1); + + bb_quant(op1_bank_id, wr_bank_id, num_words, SCALE_1_0); + + bb_mvout((uintptr_t)output, wr_bank_id, num_words, 1); + bb_fence(); +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + for (int i = 0; i < DIM * 4; i++) { + output_int32[i] = 0; + } + + hw_quant(fp32_input, output_int32, DIM); + + int passed = 1; + for (int i = 0; i < DIM * 4; i++) { + if (output_int32[i] != expected_int32[i]) { + printf("MISMATCH at [%d]: got %d, expected %d\n", i, output_int32[i], + expected_int32[i]); + passed = 0; + } + } + + if (passed) { + printf("Quant test PASSED\n"); + } else { + printf("Quant test FAILED\n"); + } + return (!passed); + +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c b/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c deleted file mode 100644 index bd56d951..00000000 --- a/bb-tests/workloads/src/CTest/toy/vecunit_simple_nn_forward_pass_test.c +++ /dev/null @@ -1,156 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM 16 - -// Define neural network parameters -#define INPUT_SIZE DIM -#define HIDDEN_SIZE DIM -#define OUTPUT_SIZE DIM - -// Test matrices and data buffers -static elem_t input_data[DIM * DIM] __attribute__((aligned(64))); -static elem_t weights1[HIDDEN_SIZE * INPUT_SIZE] __attribute__((aligned(64))); -static elem_t weights2[OUTPUT_SIZE * HIDDEN_SIZE] __attribute__((aligned(64))); -static result_t hidden_output[DIM * DIM] __attribute__((aligned(64))); -static result_t final_output[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_output[DIM * DIM] __attribute__((aligned(64))); - -// ReLU activation function (executed on CPU) -void relu(result_t *matrix, int rows, int cols) { - for (int i = 0; i < rows * cols; i++) { - if (matrix[i] < 0) { - matrix[i] = 0; - } - } -} - -// Quantization function (quantize int32 results to elem_t type) -void quantize_matrix(result_t *src, elem_t *dst, int size) { - for (int i = 0; i < size * size; i++) { - dst[i] = (src[i] > 127) ? 127 : (src[i] < -128) ? -128 : (elem_t)src[i]; - } -} - -// Neural network forward propagation on CPU -void cpu_nn_forward(elem_t *input, elem_t *w1, elem_t *w2, result_t *hidden, - result_t *output, int size) { - // Input layer -> hidden layer - cpu_matmul(input, w1, hidden, size, size, size); - // Apply ReLU activation - relu(hidden, size, size); - - // Quantize hidden layer output as input for next layer - static elem_t hidden_quantized[DIM * DIM]; - quantize_matrix(hidden, hidden_quantized, size); - - // Hidden layer -> output layer - cpu_matmul(hidden_quantized, w2, output, size, size, size); -} - -// Execute hardware matrix multiplication -void hw_matmul(elem_t *a, elem_t *b, result_t *c, int size) { - // spad0: original A - uint32_t op1_bank_id = 0; - // spad1: operand B - uint32_t op2_bank_id = 1; - // acc0: write to accumulator - int acc_bank_id = 2; // virtual bank id - // spad3: transposed A - uint32_t a_transposed_bank_id = 3; - - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); - - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_mvin((uintptr_t)b, op2_bank_id, size, 1); - bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - bb_mvin((uintptr_t)c, acc_bank_id, size, 1); - - bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_mvout((uintptr_t)c, acc_bank_id, size, 1); - bb_fence(); -} - -void hw_nn_forward(elem_t *input, elem_t *w1, elem_t *w2, result_t *hidden, - result_t *output, int size) { - // Input layer -> hidden layer - hw_matmul(input, w1, hidden, size); - // Apply ReLU on CPU - relu(hidden, size, size); - - // Quantize hidden layer output as input for next layer - static elem_t hidden_quantized[DIM * DIM]; - quantize_matrix(hidden, hidden_quantized, size); - - // Hidden layer -> output layer - hw_matmul(hidden_quantized, w2, output, size); -} - -// Execute neural network test -int test_neural_network() { - // Initialize data - printf("Initializing random input data and weights...\n"); - init_u8_random_matrix(input_data, DIM, DIM, 123); - - // Initialize weights - srand(114); - for (int i = 0; i < HIDDEN_SIZE * INPUT_SIZE; i++) { - weights1[i] = rand() % 128; - } - srand(514); - for (int i = 0; i < OUTPUT_SIZE * HIDDEN_SIZE; i++) { - weights2[i] = rand() % 128; - } - - // Clear hidden_output for hardware computation - clear_u32_matrix(hidden_output, DIM, DIM); - clear_u32_matrix(final_output, DIM, DIM); - - // Execute neural network forward propagation on hardware - printf("Running Hardware Neural Network Forward Pass...\n"); - hw_nn_forward(input_data, weights1, weights2, hidden_output, final_output, - DIM); - - // Clear output buffers - clear_u32_matrix(hidden_output, DIM, DIM); - clear_u32_matrix(expected_output, DIM, DIM); - - // Generate expected results on CPU - printf("Running CPU Neural Network Forward Pass...\n"); - cpu_nn_forward(input_data, weights1, weights2, hidden_output, expected_output, - DIM); - - // Compare hardware output with expected output - printf("Comparing hardware output with expected output...\n"); - if (compare_u32_matrices(final_output, expected_output, DIM, DIM)) { - return 1; - } else { - return 0; - } -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - printf("Neural Network Test Starting...\n"); - int pass = test_neural_network(); - if (pass) { - printf("Neural Network test PASSED\n"); - return 0; - } else { - printf("Neural Network test FAILED\n"); - return 1; - } - -#ifdef MULTICORE - exit(0); -#endif - return 0; -} diff --git a/scripts/claude/README.md b/scripts/claude/README.md new file mode 100644 index 00000000..70c88eec --- /dev/null +++ b/scripts/claude/README.md @@ -0,0 +1,97 @@ +# Buckyball Claude Code Workflow + +Claude Code 作为交互前端，bbdev 作为执行后端。Claude 通过 MCP Server 调用 bbdev 的 HTTP API（server 模式，自动管理生命周期）。 + +## 三个 Workflow + +| # | 触发 | 功能 | +|---|------|------| +| 1 | `/ball ` | 新建 Ball：实现 → 注册 → ISA 宏 → CTest → 编译 → 仿真验证 | +| 2 | `/verify ` | 验证 Ball：完整性检查 → 补全 → 编译 → 仿真 → 覆盖率分析 | +| 3 | `/optimize ` | 优化 Ball：面积(yosys) + 时序(OpenSTA) + 延迟(仿真cycle) → 优化 → 回归验证 | + +## 架构 + +``` +用户 ──→ Claude Code (slash commands + CLAUDE.md) + │ + ├── 读写代码：Read/Edit/Write + ├── 静态校验：MCP validate + └── 编译/仿真/综合/测试：MCP bbdev_* → bbdev HTTP API + │ + └── bbdev server (Motia workflow 后端，MCP 自动管理生命周期) + ├── POST /verilator/run 全流程 clean→verilog→build→sim + ├── POST /verilator/verilog 生成 Verilog（支持 --balltype） + ├── POST /verilator/build 编译 Verilator（支持 --coverage） + ├── POST /verilator/sim 跑仿真（支持 --coverage） + ├── POST /workload/build 编译 CTest + ├── POST /sardine/run 批量测试（支持 --coverage → 覆盖率报告） + └── POST /yosys/synth Yosys 综合 + OpenSTA 时序分析 +``` + +## 文件清单 + +| 文件 | 说明 | +|------|------| +| `scripts/claude/mcp_server.py` | MCP Server：validate + bbdev API 封装 + server 生命周期管理 | +| `.claude/settings.json` | MCP 配置 | +| `CLAUDE.md` | 全局指令：项目结构、Blink 协议、注册不变量、工具使用 | +| `.claude/commands/ball.md` | `/ball ` 新建 Ball 全流程 | +| `.claude/commands/verify.md` | `/verify ` 验证 Ball | +| `.claude/commands/optimize.md` | `/optimize ` 优化 Ball | +| `.claude/commands/check.md` | `/check` 静态校验 | + +## MCP Server 工具列表 + +### 校验 +| 工具 | 功能 | +|------|------| +| `validate` | 检查 6 项注册不变量（ballId 递增/funct7 唯一/bid 对齐等） | + +### bbdev API 封装 +| 工具 | API | 说明 | +|------|-----|------| +| `bbdev_workload_build` | `/workload/build` | 编译 CTest | +| `bbdev_verilator_run` | `/verilator/run` | 全流程 clean→verilog→build→sim | +| `bbdev_verilator_verilog` | `/verilator/verilog` | 生成 Verilog | +| `bbdev_verilator_build` | `/verilator/build` | 编译 Verilator | +| `bbdev_verilator_sim` | `/verilator/sim` | 跑仿真 | +| `bbdev_sardine_run` | `/sardine/run` | 批量测试 | +| `bbdev_yosys_synth` | `/yosys/synth` | Yosys 综合 + OpenSTA | + +## bbdev Server 生命周期 + +MCP Server 自动管理 bbdev server： +- 首次调用 bbdev_* 时自动启动（`pnpm dev --port `） +- 启动前清理 BullMQ AOF 防止重放旧事件 +- 端口从 5100-5500 自动选择 +- 健康检查通过后才返回 +- 每次调用前检查存活，挂了自动重启 +- MCP Server 退出时自动清理 + +## Workflow 详细流程 + +### `/ball ` — 新建 Ball + +1. **需求收集**：读 default.json/DISA.scala 确定 ballId/funct7，问用户功能/inBW/outBW/op2 +2. **实现 Ball**：参考现有 Ball 代码，在 prototype/ 下创建 wrapper/core/config +3. **注册**：更新 default.json + busRegister + DISA + DomainDecoder +4. **ISA 宏**：创建 C 宏文件，更新 isa.h +5. **CTest**：创建测试 .c，注册 CMakeLists.txt，追加 sardine 列表 +6. **验证**：validate → bbdev_workload_build → bbdev_verilator_run → PASS/FAIL + +### `/verify ` — 验证 Ball + +1. **完整性检查**：注册/ISA 宏/CTest/sardine 条目是否完整，缺什么补什么 +2. **编译 + 仿真**：bbdev_workload_build → bbdev_verilator_run +3. **覆盖率分析**：bbdev_sardine_run(coverage=true) → 读覆盖率报告 → 建议补测试 +4. **失败分析**：读仿真 log → 分析 Chisel 代码 → 提修复方案 + +### `/optimize ` — 优化 Ball + +1. **基线测量**：bbdev_yosys_synth（面积+时序）+ bbdev_verilator_run（cycle 数） +2. **面积分析**：从 hierarchy_report 提取子模块面积，识别面积大户 +3. **时序/延迟分析**：timing_report 关键路径 + 仿真 cycle 数 + FSM 源码分析 +4. **优化方案**：量化的方案列表（手段/面积变化/延迟变化/频率影响/trade-off） +5. **实施**：修改 Chisel 代码 +6. **优化后测量**：再跑 yosys + verilator，输出前后对比报告 diff --git a/scripts/claude/mcp_server.py b/scripts/claude/mcp_server.py new file mode 100644 index 00000000..1a73815c --- /dev/null +++ b/scripts/claude/mcp_server.py @@ -0,0 +1,566 @@ +#!/usr/bin/env python3 +"""MCP Server for Buckyball Claude Code workflow. + +Provides: +- validate: static registration invariant checks +- bbdev_* tools: wrappers around bbdev HTTP API (server mode, auto-managed lifecycle) +""" + +from __future__ import annotations + +import atexit +import json +import os +import re +import shutil +import signal +import socket +import subprocess +import sys +import time +from pathlib import Path +from typing import Any, Dict, List, Optional + +# --------------------------------------------------------------------------- +# Paths +# --------------------------------------------------------------------------- +REPO_ROOT = Path(__file__).resolve().parents[2] +BBDEV_API_DIR = REPO_ROOT / "bbdev" / "api" + +REGISTRATION_FILES = { + "default_json": REPO_ROOT + / "arch/src/main/scala/framework/balldomain/configs/default.json", + "bus_register": REPO_ROOT + / "arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala", + "disa": REPO_ROOT / "arch/src/main/scala/examples/toy/balldomain/DISA.scala", + "domain_decoder": REPO_ROOT + / "arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala", +} + +# --------------------------------------------------------------------------- +# bbdev server lifecycle +# --------------------------------------------------------------------------- +_bbdev_proc: Optional[subprocess.Popen] = None +_bbdev_port: Optional[int] = None + + +def _find_available_port(start: int = 5100, end: int = 5500) -> int: + for port in range(start, end + 1): + try: + with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: + s.bind(("localhost", port)) + return port + except OSError: + continue + raise RuntimeError(f"No available port in {start}-{end}") + + +def _ensure_bbdev_server() -> int: + """Start bbdev server if not running. Returns port.""" + global _bbdev_proc, _bbdev_port + + if _bbdev_port is not None and _bbdev_proc is not None: + if _bbdev_proc.poll() is None and _health_check(_bbdev_port): + return _bbdev_port + # Server died, clean up + _stop_bbdev_server() + + # Clean AOF to prevent BullMQ replaying old events + aof_dir = BBDEV_API_DIR / ".motia" / "appendonlydir" + if aof_dir.exists(): + shutil.rmtree(aof_dir) + + port = _find_available_port() + _bbdev_proc = subprocess.Popen( + ["pnpm", "dev", "--port", str(port)], + cwd=str(BBDEV_API_DIR), + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL, + ) + _bbdev_port = port + + # Wait for server to be ready + for _ in range(90): + if _health_check(port): + return port + time.sleep(1) + + _stop_bbdev_server() + raise RuntimeError(f"bbdev server failed to start on port {port} within 90s") + + +def _health_check(port: int) -> bool: + try: + import urllib.request + + req = urllib.request.Request( + f"http://localhost:{port}", + method="GET", + ) + with urllib.request.urlopen(req, timeout=2) as resp: + return resp.status == 200 + except Exception: + return False + + +def _stop_bbdev_server(): + global _bbdev_proc, _bbdev_port + if _bbdev_proc is not None: + try: + _bbdev_proc.terminate() + _bbdev_proc.wait(timeout=5) + except Exception: + try: + _bbdev_proc.kill() + except Exception: + pass + _bbdev_proc = None + _bbdev_port = None + + +atexit.register(_stop_bbdev_server) + + +def _bbdev_call( + endpoint: str, params: Dict[str, Any], timeout: int = 600 +) -> Dict[str, Any]: + """Call bbdev HTTP API. Auto-starts server if needed.""" + port = _ensure_bbdev_server() + url = f"http://localhost:{port}{endpoint}" + + data = json.dumps(params).encode("utf-8") + import urllib.request + + req = urllib.request.Request( + url, + data=data, + headers={"Content-Type": "application/json"}, + method="POST", + ) + try: + with urllib.request.urlopen(req, timeout=timeout) as resp: + body = resp.read().decode("utf-8") + return json.loads(body) + except Exception as e: + return {"success": False, "failure": True, "error": str(e)} + + +# --------------------------------------------------------------------------- +# MCP protocol helpers +# --------------------------------------------------------------------------- +def _write_message(payload: Dict[str, Any]) -> None: + data = json.dumps(payload).encode("utf-8") + header = f"Content-Length: {len(data)}\r\n\r\n".encode("ascii") + sys.stdout.buffer.write(header) + sys.stdout.buffer.write(data) + sys.stdout.buffer.flush() + + +def _read_message() -> Optional[Dict[str, Any]]: + content_length = None + while True: + line = sys.stdin.buffer.readline() + if not line: + return None + line = line.decode("ascii", errors="ignore").strip() + if not line: + break + if line.lower().startswith("content-length:"): + content_length = int(line.split(":", 1)[1].strip()) + if content_length is None: + return None + body = sys.stdin.buffer.read(content_length) + if not body: + return None + return json.loads(body.decode("utf-8")) + + +def _response( + msg_id: Any, result: Any = None, error: Optional[Dict[str, Any]] = None +) -> Dict[str, Any]: + payload: Dict[str, Any] = {"jsonrpc": "2.0", "id": msg_id} + if error is not None: + payload["error"] = error + else: + payload["result"] = result + return payload + + +def _ok(payload: Any) -> Dict[str, Any]: + return { + "content": [ + {"type": "text", "text": json.dumps(payload, ensure_ascii=False, indent=2)} + ], + "isError": False, + } + + +def _err(message: str) -> Dict[str, Any]: + return {"content": [{"type": "text", "text": message}], "isError": True} + + +# --------------------------------------------------------------------------- +# validate tool +# --------------------------------------------------------------------------- +def _read_json(path: Path) -> Any: + with path.open("r", encoding="utf-8") as f: + return json.load(f) + + +def _extract_bitpat_values(text: str) -> List[int]: + vals = [] + for m in re.finditer(r'BitPat\("b([01]+)"\)', text): + vals.append(int(m.group(1), 2)) + return vals + + +def _extract_bus_register_names(text: str) -> List[str]: + names = [] + for m in re.finditer(r'case\s+"(\w+)"', text): + names.append(m.group(1)) + return names + + +def _extract_decoder_bids(text: str) -> List[int]: + bids = [] + for m in re.finditer(r"(\d+)\.U,\s*rs2", text): + bids.append(int(m.group(1))) + return bids + + +def handle_validate(params: Dict[str, Any]) -> Dict[str, Any]: + missing_files = [] + for name, path in REGISTRATION_FILES.items(): + if not path.exists(): + missing_files.append(str(path)) + + if missing_files: + return _err(f"Missing registration files: {', '.join(missing_files)}") + + cfg = _read_json(REGISTRATION_FILES["default_json"]) + mappings = cfg.get("ballIdMappings", []) + ids = [e.get("ballId") for e in mappings] + names_from_json = [e.get("ballName") for e in mappings] + + disa_text = REGISTRATION_FILES["disa"].read_text(encoding="utf-8") + funct7_values = _extract_bitpat_values(disa_text) + + bus_text = REGISTRATION_FILES["bus_register"].read_text(encoding="utf-8") + bus_names = _extract_bus_register_names(bus_text) + + decoder_text = REGISTRATION_FILES["domain_decoder"].read_text(encoding="utf-8") + decoder_bids = _extract_decoder_bids(decoder_text) + + checks = { + "ballNum_matches_count": { + "pass": cfg.get("ballNum") == len(mappings), + "expected": len(mappings), + "actual": cfg.get("ballNum"), + }, + "ballId_strict_increment": { + "pass": ids == list(range(len(ids))), + "ids": ids, + }, + "ballId_no_duplicates": { + "pass": len(ids) == len(set(ids)), + "duplicates": sorted(x for x in ids if ids.count(x) > 1), + }, + "funct7_no_duplicates": { + "pass": len(funct7_values) == len(set(funct7_values)), + "duplicates": sorted( + x for x in funct7_values if funct7_values.count(x) > 1 + ), + }, + "busRegister_matches_json": { + "pass": set(bus_names) == set(names_from_json), + "in_json_not_bus": sorted(set(names_from_json) - set(bus_names)), + "in_bus_not_json": sorted(set(bus_names) - set(names_from_json)), + }, + "decoder_bids_match_json": { + "pass": sorted(decoder_bids) == sorted(ids), + "decoder_bids": sorted(decoder_bids), + "json_ids": sorted(ids), + }, + } + + all_passed = all(c["pass"] for c in checks.values()) + return _ok({"passed": all_passed, "checks": checks}) + + +# --------------------------------------------------------------------------- +# bbdev tool handlers +# --------------------------------------------------------------------------- +def handle_bbdev_workload_build(params: Dict[str, Any]) -> Dict[str, Any]: + result = _bbdev_call("/workload/build", {}, timeout=120) + return _ok(result) + + +def handle_bbdev_verilator_run(params: Dict[str, Any]) -> Dict[str, Any]: + api_params = { + "binary": params.get("binary", ""), + "config": params.get("config", "sims.verilator.BuckyballToyVerilatorConfig"), + "batch": params.get("batch", True), + "coverage": params.get("coverage", False), + } + if params.get("jobs"): + api_params["jobs"] = params["jobs"] + result = _bbdev_call("/verilator/run", api_params, timeout=1200) + return _ok(result) + + +def handle_bbdev_verilator_verilog(params: Dict[str, Any]) -> Dict[str, Any]: + api_params = {} + if params.get("config"): + api_params["config"] = params["config"] + if params.get("balltype"): + api_params["balltype"] = params["balltype"] + result = _bbdev_call("/verilator/verilog", api_params, timeout=600) + return _ok(result) + + +def handle_bbdev_verilator_build(params: Dict[str, Any]) -> Dict[str, Any]: + api_params = {"jobs": params.get("jobs", 16)} + if params.get("coverage"): + api_params["coverage"] = True + result = _bbdev_call("/verilator/build", api_params, timeout=600) + return _ok(result) + + +def handle_bbdev_verilator_sim(params: Dict[str, Any]) -> Dict[str, Any]: + api_params = { + "binary": params.get("binary", ""), + "batch": params.get("batch", True), + } + if params.get("coverage"): + api_params["coverage"] = True + result = _bbdev_call("/verilator/sim", api_params, timeout=1200) + return _ok(result) + + +def handle_bbdev_sardine_run(params: Dict[str, Any]) -> Dict[str, Any]: + api_params = {"workload": params.get("workload", "ctest")} + if params.get("coverage"): + api_params["coverage"] = True + result = _bbdev_call("/sardine/run", api_params, timeout=1200) + return _ok(result) + + +def handle_bbdev_yosys_synth(params: Dict[str, Any]) -> Dict[str, Any]: + api_params = {} + if params.get("top"): + api_params["top"] = params["top"] + if params.get("config"): + api_params["config"] = params["config"] + result = _bbdev_call("/yosys/synth", api_params, timeout=600) + return _ok(result) + + +# --------------------------------------------------------------------------- +# Tool registry +# --------------------------------------------------------------------------- +TOOLS = { + "validate": { + "description": "Check 6 registration invariants: ballNum consistency, ballId strict increment, " + "ballId no duplicates, funct7 no duplicates, busRegister matches default.json, " + "decoder BIDs match default.json.", + "inputSchema": { + "type": "object", + "properties": {}, + "additionalProperties": False, + }, + "handler": handle_validate, + }, + "bbdev_workload_build": { + "description": "Compile CTest workloads (bb-tests). Calls bbdev POST /workload/build.", + "inputSchema": { + "type": "object", + "properties": {}, + "additionalProperties": False, + }, + "handler": handle_bbdev_workload_build, + }, + "bbdev_verilator_run": { + "description": "Full verilator pipeline: clean -> verilog -> build -> sim. " + "Calls bbdev POST /verilator/run.", + "inputSchema": { + "type": "object", + "properties": { + "binary": { + "type": "string", + "description": "Test binary name (e.g. ctest_relu_test_singlecore-baremetal)", + }, + "config": { + "type": "string", + "description": "Elaborate config class (default: sims.verilator.BuckyballToyVerilatorConfig)", + }, + "batch": { + "type": "boolean", + "description": "Run in batch mode (default: true)", + }, + "coverage": { + "type": "boolean", + "description": "Enable coverage collection (default: false)", + }, + "jobs": {"type": "integer", "description": "Parallel build jobs"}, + }, + "required": ["binary"], + }, + "handler": handle_bbdev_verilator_run, + }, + "bbdev_verilator_verilog": { + "description": "Generate Verilog from Chisel. Supports --balltype for single Ball elaboration. " + "Calls bbdev POST /verilator/verilog.", + "inputSchema": { + "type": "object", + "properties": { + "config": {"type": "string", "description": "Elaborate config class"}, + "balltype": { + "type": "string", + "description": "Single Ball type for standalone elaboration (e.g. reluball)", + }, + }, + }, + "handler": handle_bbdev_verilator_verilog, + }, + "bbdev_verilator_build": { + "description": "Build verilator simulation executable. Calls bbdev POST /verilator/build.", + "inputSchema": { + "type": "object", + "properties": { + "jobs": { + "type": "integer", + "description": "Parallel build jobs (default: 16)", + }, + "coverage": { + "type": "boolean", + "description": "Build with coverage support", + }, + }, + }, + "handler": handle_bbdev_verilator_build, + }, + "bbdev_verilator_sim": { + "description": "Run verilator simulation (assumes already built). Calls bbdev POST /verilator/sim.", + "inputSchema": { + "type": "object", + "properties": { + "binary": {"type": "string", "description": "Test binary name"}, + "batch": { + "type": "boolean", + "description": "Batch mode (default: true)", + }, + "coverage": {"type": "boolean", "description": "Enable coverage"}, + }, + "required": ["binary"], + }, + "handler": handle_bbdev_verilator_sim, + }, + "bbdev_sardine_run": { + "description": "Run sardine batch tests. Calls bbdev POST /sardine/run. " + "With coverage=true, generates coverage report at bb-tests/sardine/reports/coverage/.", + "inputSchema": { + "type": "object", + "properties": { + "workload": { + "type": "string", + "description": "Workload filter (default: ctest)", + }, + "coverage": { + "type": "boolean", + "description": "Enable coverage collection and report", + }, + }, + }, + "handler": handle_bbdev_sardine_run, + }, + "bbdev_yosys_synth": { + "description": "Run Yosys synthesis for area estimation + OpenSTA timing analysis. " + "Generates hierarchy_report.txt, area_report.txt, and timing_report.txt " + "in bbdev/api/steps/yosys/log/. Calls bbdev POST /yosys/synth.", + "inputSchema": { + "type": "object", + "properties": { + "top": { + "type": "string", + "description": "Top module name (default: BuckyballAccelerator)", + }, + "config": {"type": "string", "description": "Elaborate config class"}, + }, + }, + "handler": handle_bbdev_yosys_synth, + }, +} + + +# --------------------------------------------------------------------------- +# Main server loop +# --------------------------------------------------------------------------- +def serve() -> int: + while True: + msg = _read_message() + if msg is None: + return 0 + + msg_id = msg.get("id") + method = msg.get("method") + params = msg.get("params", {}) + + try: + if method == "initialize": + _write_message( + _response( + msg_id, + { + "protocolVersion": "2024-11-05", + "serverInfo": {"name": "buckyball-dev", "version": "0.1.0"}, + "capabilities": {"tools": {}}, + }, + ) + ) + continue + + if method == "notifications/initialized": + continue + + if method == "tools/list": + tools = [ + { + "name": name, + "description": spec["description"], + "inputSchema": spec["inputSchema"], + } + for name, spec in TOOLS.items() + ] + _write_message(_response(msg_id, {"tools": tools})) + continue + + if method == "tools/call": + name = params.get("name") + arguments = params.get("arguments", {}) + if name not in TOOLS: + _write_message( + _response( + msg_id, + error={"code": -32601, "message": f"Unknown tool: {name}"}, + ) + ) + continue + result = TOOLS[name]["handler"](arguments) + _write_message(_response(msg_id, result)) + continue + + _write_message( + _response( + msg_id, + error={"code": -32601, "message": f"Unknown method: {method}"}, + ) + ) + + except Exception as exc: + _write_message( + _response(msg_id, error={"code": -32000, "message": str(exc)}) + ) + + +if __name__ == "__main__": + raise SystemExit(serve()) From e33f494b16663f3ad06676d1d01f849b23e9e169 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 7 Mar 2026 17:58:54 +0800 Subject: [PATCH 146/238] [bbAgent] fix: refactor MCP server to use official SDK --- .claude/settings.json | 7 +- .cursor/mcp.json | 12 + .gitignore | 4 +- flake.nix | 36 +-- scripts/claude/mcp_server.py | 424 +++++++++-------------------------- 5 files changed, 144 insertions(+), 339 deletions(-) create mode 100644 .cursor/mcp.json diff --git a/.claude/settings.json b/.claude/settings.json index aff6200b..ad19c30f 100644 --- a/.claude/settings.json +++ b/.claude/settings.json @@ -2,8 +2,11 @@ "mcpServers": { "buckyball-dev": { "type": "stdio", - "command": "python3", - "args": ["scripts/claude/mcp_server.py"] + "command": "nix", + "args": ["develop", "-c", "python3", "-u", "scripts/claude/mcp_server.py"], + "env": { + "BUCKYBALL_QUIET": "1" + } } } } diff --git a/.cursor/mcp.json b/.cursor/mcp.json new file mode 100644 index 00000000..9e454870 --- /dev/null +++ b/.cursor/mcp.json @@ -0,0 +1,12 @@ +{ + "mcpServers": { + "buckyball-dev": { + "command": "nix", + "args": ["develop", "-c", "python3", "-u", "scripts/claude/mcp_server.py"], + "cwd": "${workspaceFolder}", + "env": { + "BUCKYBALL_QUIET": "1" + } + } + } + } diff --git a/.gitignore b/.gitignore index 7fa4e75e..a530c749 100644 --- a/.gitignore +++ b/.gitignore @@ -2,7 +2,7 @@ .metals/ # .claude/ .motia/ -.cursor/ +# .cursor/ .bsp/ out/ result @@ -21,3 +21,5 @@ index.html .clangd .kiro + +__pycache__/ diff --git a/flake.nix b/flake.nix index cca6eaab..f4b541b8 100644 --- a/flake.nix +++ b/flake.nix @@ -78,9 +78,8 @@ shellHook = '' if [ -d "$PWD/result/bin" ]; then export PATH="$PWD/result/bin:$PATH" - echo "================= Buckyball Environment Activated =========================" else - echo "Warning: result/bin not found. Run 'nix build' first." + echo "Warning: result/bin not found. Run 'nix build' first." >&2 fi source "$PWD/sourceme.sh" @@ -88,21 +87,24 @@ # Verilator build acceleration: ccache via OBJCACHE export OBJCACHE=ccache - echo "Development environment loaded:" - echo "Verilator: $(verilator --version 2>&1 | head -1)" - echo "RISC-V Embedded GCC: $(riscv64-unknown-elf-gcc --version 2>&1 | head -1)" - echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" - echo "Bebop: $(which bebop)" - echo "Spike: $(which spike)" - echo "Bebop Gem5: $(which gem5.opt)" - echo "Mill: $(mill --version 2>&1 | head -1)" - echo "Cargo: $(cargo --version 2>&1 | head -1)" - echo "npm: $(npm --version 2>&1 | head -1)" - echo "bbdev: $(which bbdev)" - echo "RISCV: $RISCV" - echo "Yosys: $(yosys --version 2>&1 | head -1)" - echo "OpenSTA: $(sta -version 2>&1 | head -1)" - echo "===========================================================================" + if [ -z "$BUCKYBALL_QUIET" ]; then + echo "================= Buckyball Environment Activated =========================" + echo "Development environment loaded:" + echo "Verilator: $(verilator --version 2>&1 | head -1)" + echo "RISC-V Embedded GCC: $(riscv64-unknown-elf-gcc --version 2>&1 | head -1)" + echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" + echo "Bebop: $(which bebop)" + echo "Spike: $(which spike)" + echo "Bebop Gem5: $(which gem5.opt)" + echo "Mill: $(mill --version 2>&1 | head -1)" + echo "Cargo: $(cargo --version 2>&1 | head -1)" + echo "npm: $(npm --version 2>&1 | head -1)" + echo "bbdev: $(which bbdev)" + echo "RISCV: $RISCV" + echo "Yosys: $(yosys --version 2>&1 | head -1)" + echo "OpenSTA: $(sta -version 2>&1 | head -1)" + echo "===========================================================================" + fi ''; }; } diff --git a/scripts/claude/mcp_server.py b/scripts/claude/mcp_server.py index 1a73815c..ad90facc 100644 --- a/scripts/claude/mcp_server.py +++ b/scripts/claude/mcp_server.py @@ -4,23 +4,25 @@ Provides: - validate: static registration invariant checks - bbdev_* tools: wrappers around bbdev HTTP API (server mode, auto-managed lifecycle) + +Uses the official `mcp` Python SDK for protocol compatibility with both +Claude Code CLI and Cursor IDE. """ from __future__ import annotations import atexit import json -import os import re import shutil -import signal import socket import subprocess -import sys import time from pathlib import Path from typing import Any, Dict, List, Optional +from mcp.server.fastmcp import FastMCP + # --------------------------------------------------------------------------- # Paths # --------------------------------------------------------------------------- @@ -146,61 +148,7 @@ def _bbdev_call( # --------------------------------------------------------------------------- -# MCP protocol helpers -# --------------------------------------------------------------------------- -def _write_message(payload: Dict[str, Any]) -> None: - data = json.dumps(payload).encode("utf-8") - header = f"Content-Length: {len(data)}\r\n\r\n".encode("ascii") - sys.stdout.buffer.write(header) - sys.stdout.buffer.write(data) - sys.stdout.buffer.flush() - - -def _read_message() -> Optional[Dict[str, Any]]: - content_length = None - while True: - line = sys.stdin.buffer.readline() - if not line: - return None - line = line.decode("ascii", errors="ignore").strip() - if not line: - break - if line.lower().startswith("content-length:"): - content_length = int(line.split(":", 1)[1].strip()) - if content_length is None: - return None - body = sys.stdin.buffer.read(content_length) - if not body: - return None - return json.loads(body.decode("utf-8")) - - -def _response( - msg_id: Any, result: Any = None, error: Optional[Dict[str, Any]] = None -) -> Dict[str, Any]: - payload: Dict[str, Any] = {"jsonrpc": "2.0", "id": msg_id} - if error is not None: - payload["error"] = error - else: - payload["result"] = result - return payload - - -def _ok(payload: Any) -> Dict[str, Any]: - return { - "content": [ - {"type": "text", "text": json.dumps(payload, ensure_ascii=False, indent=2)} - ], - "isError": False, - } - - -def _err(message: str) -> Dict[str, Any]: - return {"content": [{"type": "text", "text": message}], "isError": True} - - -# --------------------------------------------------------------------------- -# validate tool +# Helpers # --------------------------------------------------------------------------- def _read_json(path: Path) -> Any: with path.open("r", encoding="utf-8") as f: @@ -228,14 +176,26 @@ def _extract_decoder_bids(text: str) -> List[int]: return bids -def handle_validate(params: Dict[str, Any]) -> Dict[str, Any]: +def _fmt(payload: Any) -> str: + return json.dumps(payload, ensure_ascii=False, indent=2) + + +# --------------------------------------------------------------------------- +# MCP Server (using official SDK) +# --------------------------------------------------------------------------- +mcp = FastMCP("buckyball-dev") + + +@mcp.tool() +def validate() -> str: + """Check 6 registration invariants: ballNum consistency, ballId strict increment, ballId no duplicates, funct7 no duplicates, busRegister matches default.json, decoder BIDs match default.json.""" missing_files = [] for name, path in REGISTRATION_FILES.items(): if not path.exists(): missing_files.append(str(path)) if missing_files: - return _err(f"Missing registration files: {', '.join(missing_files)}") + return f"ERROR: Missing registration files: {', '.join(missing_files)}" cfg = _read_json(REGISTRATION_FILES["default_json"]) mappings = cfg.get("ballIdMappings", []) @@ -284,283 +244,109 @@ def handle_validate(params: Dict[str, Any]) -> Dict[str, Any]: } all_passed = all(c["pass"] for c in checks.values()) - return _ok({"passed": all_passed, "checks": checks}) + return _fmt({"passed": all_passed, "checks": checks}) -# --------------------------------------------------------------------------- -# bbdev tool handlers -# --------------------------------------------------------------------------- -def handle_bbdev_workload_build(params: Dict[str, Any]) -> Dict[str, Any]: +@mcp.tool() +def bbdev_workload_build() -> str: + """Compile CTest workloads (bb-tests). Calls bbdev POST /workload/build.""" result = _bbdev_call("/workload/build", {}, timeout=120) - return _ok(result) - - -def handle_bbdev_verilator_run(params: Dict[str, Any]) -> Dict[str, Any]: - api_params = { - "binary": params.get("binary", ""), - "config": params.get("config", "sims.verilator.BuckyballToyVerilatorConfig"), - "batch": params.get("batch", True), - "coverage": params.get("coverage", False), + return _fmt(result) + + +@mcp.tool() +def bbdev_verilator_run( + binary: str, + config: str = "sims.verilator.BuckyballToyVerilatorConfig", + batch: bool = True, + coverage: bool = False, + jobs: Optional[int] = None, +) -> str: + """Full verilator pipeline: clean -> verilog -> build -> sim. Calls bbdev POST /verilator/run.""" + api_params: Dict[str, Any] = { + "binary": binary, + "config": config, + "batch": batch, + "coverage": coverage, } - if params.get("jobs"): - api_params["jobs"] = params["jobs"] + if jobs is not None: + api_params["jobs"] = jobs result = _bbdev_call("/verilator/run", api_params, timeout=1200) - return _ok(result) - - -def handle_bbdev_verilator_verilog(params: Dict[str, Any]) -> Dict[str, Any]: - api_params = {} - if params.get("config"): - api_params["config"] = params["config"] - if params.get("balltype"): - api_params["balltype"] = params["balltype"] + return _fmt(result) + + +@mcp.tool() +def bbdev_verilator_verilog( + config: Optional[str] = None, + balltype: Optional[str] = None, +) -> str: + """Generate Verilog from Chisel. Supports --balltype for single Ball elaboration. Calls bbdev POST /verilator/verilog.""" + api_params: Dict[str, Any] = {} + if config: + api_params["config"] = config + if balltype: + api_params["balltype"] = balltype result = _bbdev_call("/verilator/verilog", api_params, timeout=600) - return _ok(result) + return _fmt(result) -def handle_bbdev_verilator_build(params: Dict[str, Any]) -> Dict[str, Any]: - api_params = {"jobs": params.get("jobs", 16)} - if params.get("coverage"): +@mcp.tool() +def bbdev_verilator_build( + jobs: int = 16, + coverage: bool = False, +) -> str: + """Build verilator simulation executable. Calls bbdev POST /verilator/build.""" + api_params: Dict[str, Any] = {"jobs": jobs} + if coverage: api_params["coverage"] = True result = _bbdev_call("/verilator/build", api_params, timeout=600) - return _ok(result) - - -def handle_bbdev_verilator_sim(params: Dict[str, Any]) -> Dict[str, Any]: - api_params = { - "binary": params.get("binary", ""), - "batch": params.get("batch", True), + return _fmt(result) + + +@mcp.tool() +def bbdev_verilator_sim( + binary: str, + batch: bool = True, + coverage: bool = False, +) -> str: + """Run verilator simulation (assumes already built). Calls bbdev POST /verilator/sim.""" + api_params: Dict[str, Any] = { + "binary": binary, + "batch": batch, } - if params.get("coverage"): + if coverage: api_params["coverage"] = True result = _bbdev_call("/verilator/sim", api_params, timeout=1200) - return _ok(result) + return _fmt(result) -def handle_bbdev_sardine_run(params: Dict[str, Any]) -> Dict[str, Any]: - api_params = {"workload": params.get("workload", "ctest")} - if params.get("coverage"): +@mcp.tool() +def bbdev_sardine_run( + workload: str = "ctest", + coverage: bool = False, +) -> str: + """Run sardine batch tests. Calls bbdev POST /sardine/run. With coverage=true, generates coverage report at bb-tests/sardine/reports/coverage/.""" + api_params: Dict[str, Any] = {"workload": workload} + if coverage: api_params["coverage"] = True result = _bbdev_call("/sardine/run", api_params, timeout=1200) - return _ok(result) - - -def handle_bbdev_yosys_synth(params: Dict[str, Any]) -> Dict[str, Any]: - api_params = {} - if params.get("top"): - api_params["top"] = params["top"] - if params.get("config"): - api_params["config"] = params["config"] + return _fmt(result) + + +@mcp.tool() +def bbdev_yosys_synth( + top: Optional[str] = None, + config: Optional[str] = None, +) -> str: + """Run Yosys synthesis for area estimation + OpenSTA timing analysis. Generates hierarchy_report.txt, area_report.txt, and timing_report.txt in bbdev/api/steps/yosys/log/. Calls bbdev POST /yosys/synth.""" + api_params: Dict[str, Any] = {} + if top: + api_params["top"] = top + if config: + api_params["config"] = config result = _bbdev_call("/yosys/synth", api_params, timeout=600) - return _ok(result) - - -# --------------------------------------------------------------------------- -# Tool registry -# --------------------------------------------------------------------------- -TOOLS = { - "validate": { - "description": "Check 6 registration invariants: ballNum consistency, ballId strict increment, " - "ballId no duplicates, funct7 no duplicates, busRegister matches default.json, " - "decoder BIDs match default.json.", - "inputSchema": { - "type": "object", - "properties": {}, - "additionalProperties": False, - }, - "handler": handle_validate, - }, - "bbdev_workload_build": { - "description": "Compile CTest workloads (bb-tests). Calls bbdev POST /workload/build.", - "inputSchema": { - "type": "object", - "properties": {}, - "additionalProperties": False, - }, - "handler": handle_bbdev_workload_build, - }, - "bbdev_verilator_run": { - "description": "Full verilator pipeline: clean -> verilog -> build -> sim. " - "Calls bbdev POST /verilator/run.", - "inputSchema": { - "type": "object", - "properties": { - "binary": { - "type": "string", - "description": "Test binary name (e.g. ctest_relu_test_singlecore-baremetal)", - }, - "config": { - "type": "string", - "description": "Elaborate config class (default: sims.verilator.BuckyballToyVerilatorConfig)", - }, - "batch": { - "type": "boolean", - "description": "Run in batch mode (default: true)", - }, - "coverage": { - "type": "boolean", - "description": "Enable coverage collection (default: false)", - }, - "jobs": {"type": "integer", "description": "Parallel build jobs"}, - }, - "required": ["binary"], - }, - "handler": handle_bbdev_verilator_run, - }, - "bbdev_verilator_verilog": { - "description": "Generate Verilog from Chisel. Supports --balltype for single Ball elaboration. " - "Calls bbdev POST /verilator/verilog.", - "inputSchema": { - "type": "object", - "properties": { - "config": {"type": "string", "description": "Elaborate config class"}, - "balltype": { - "type": "string", - "description": "Single Ball type for standalone elaboration (e.g. reluball)", - }, - }, - }, - "handler": handle_bbdev_verilator_verilog, - }, - "bbdev_verilator_build": { - "description": "Build verilator simulation executable. Calls bbdev POST /verilator/build.", - "inputSchema": { - "type": "object", - "properties": { - "jobs": { - "type": "integer", - "description": "Parallel build jobs (default: 16)", - }, - "coverage": { - "type": "boolean", - "description": "Build with coverage support", - }, - }, - }, - "handler": handle_bbdev_verilator_build, - }, - "bbdev_verilator_sim": { - "description": "Run verilator simulation (assumes already built). Calls bbdev POST /verilator/sim.", - "inputSchema": { - "type": "object", - "properties": { - "binary": {"type": "string", "description": "Test binary name"}, - "batch": { - "type": "boolean", - "description": "Batch mode (default: true)", - }, - "coverage": {"type": "boolean", "description": "Enable coverage"}, - }, - "required": ["binary"], - }, - "handler": handle_bbdev_verilator_sim, - }, - "bbdev_sardine_run": { - "description": "Run sardine batch tests. Calls bbdev POST /sardine/run. " - "With coverage=true, generates coverage report at bb-tests/sardine/reports/coverage/.", - "inputSchema": { - "type": "object", - "properties": { - "workload": { - "type": "string", - "description": "Workload filter (default: ctest)", - }, - "coverage": { - "type": "boolean", - "description": "Enable coverage collection and report", - }, - }, - }, - "handler": handle_bbdev_sardine_run, - }, - "bbdev_yosys_synth": { - "description": "Run Yosys synthesis for area estimation + OpenSTA timing analysis. " - "Generates hierarchy_report.txt, area_report.txt, and timing_report.txt " - "in bbdev/api/steps/yosys/log/. Calls bbdev POST /yosys/synth.", - "inputSchema": { - "type": "object", - "properties": { - "top": { - "type": "string", - "description": "Top module name (default: BuckyballAccelerator)", - }, - "config": {"type": "string", "description": "Elaborate config class"}, - }, - }, - "handler": handle_bbdev_yosys_synth, - }, -} - - -# --------------------------------------------------------------------------- -# Main server loop -# --------------------------------------------------------------------------- -def serve() -> int: - while True: - msg = _read_message() - if msg is None: - return 0 - - msg_id = msg.get("id") - method = msg.get("method") - params = msg.get("params", {}) - - try: - if method == "initialize": - _write_message( - _response( - msg_id, - { - "protocolVersion": "2024-11-05", - "serverInfo": {"name": "buckyball-dev", "version": "0.1.0"}, - "capabilities": {"tools": {}}, - }, - ) - ) - continue - - if method == "notifications/initialized": - continue - - if method == "tools/list": - tools = [ - { - "name": name, - "description": spec["description"], - "inputSchema": spec["inputSchema"], - } - for name, spec in TOOLS.items() - ] - _write_message(_response(msg_id, {"tools": tools})) - continue - - if method == "tools/call": - name = params.get("name") - arguments = params.get("arguments", {}) - if name not in TOOLS: - _write_message( - _response( - msg_id, - error={"code": -32601, "message": f"Unknown tool: {name}"}, - ) - ) - continue - result = TOOLS[name]["handler"](arguments) - _write_message(_response(msg_id, result)) - continue - - _write_message( - _response( - msg_id, - error={"code": -32601, "message": f"Unknown method: {method}"}, - ) - ) - - except Exception as exc: - _write_message( - _response(msg_id, error={"code": -32000, "message": str(exc)}) - ) + return _fmt(result) if __name__ == "__main__": - raise SystemExit(serve()) + mcp.run(transport="stdio") From d31cd19ea999aaa290997e67be7973ea83749f5c Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 7 Mar 2026 20:51:29 +0800 Subject: [PATCH 147/238] [arch] feat: implement Im2col module with LineBufferManager and StreamWriter for optimized data handling [compiler] update: bump compiler to the latest version --- .claude/commands/optimize.md | 6 + .claude/commands/verify.md | 1 + CLAUDE.md | 15 +- .../balldomain/prototype/im2col/Im2col.scala | 306 +++++++----------- .../prototype/im2col/LineBufferManager.scala | 179 ++++++++++ .../prototype/im2col/StreamWriter.scala | 123 +++++++ .../im2col/configs/Im2colBallParam.scala | 2 +- .../relu/configs/ReluBallParam.scala | 2 +- .../configs/SystolicBallParam.scala | 2 +- .../configs/TransposeBallParam.scala | 2 +- .../vector/configs/VectorBallParam.scala | 2 +- .../framework/core/configs/CoreParam.scala | 2 +- .../frontend/configs/FrontendParam.scala | 2 +- .../gpdomain/configs/GpDomainParam.scala | 2 +- .../memdomain/configs/MemDomainParam.scala | 2 +- .../main/scala/sims/verify/TargetConfig.scala | 18 +- compiler | 2 +- scripts/claude/mcp_server.py | 24 +- 18 files changed, 474 insertions(+), 218 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/LineBufferManager.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/im2col/StreamWriter.scala diff --git a/.claude/commands/optimize.md b/.claude/commands/optimize.md index 46d61c50..28735f5b 100644 --- a/.claude/commands/optimize.md +++ b/.claude/commands/optimize.md @@ -76,3 +76,9 @@ - Cycle 数差值和百分比变化 - 关键路径延迟变化 - 频率变化 + +## 故障排查 + +如果 MCP 工具返回 HTTP 500 或 returncode=1： +- 读取 `bbdev/server.log` — bbdev server 的运行日志，包含 Chisel 编译错误、mill 构建错误等详细堆栈信息 +- 该日志特别有助于诊断 elaborate 失败（如类型不匹配、缺少注册等编译期错误） diff --git a/.claude/commands/verify.md b/.claude/commands/verify.md index 6c8b9a38..a629547c 100644 --- a/.claude/commands/verify.md +++ b/.claude/commands/verify.md @@ -36,6 +36,7 @@ - `arch/log//stdout.log` — 程序标准输出，包含 PASSED/FAILED 和 printf 输出 - `arch/log//disasm.log` — 反汇编指令流，可以看到实际执行了哪些指令 - `arch/log//bdb.log` — **Buckyball 调试日志**，包含 Ball 内部状态变化、SRAM 读写请求/响应、FSM 状态转移等硬件级信息。这是定位 Ball 逻辑错误最重要的日志 + - `bbdev/server.log` — bbdev server 的运行日志，包含 Chisel 编译错误、mill 构建错误等详细堆栈信息 3. **分析 bdb.log 的方法**： - 搜索目标 Ball 的名称，找到相关的命令发射和完成事件 diff --git a/CLAUDE.md b/CLAUDE.md index b6bbd4f8..d0ee951e 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -72,12 +72,15 @@ bbdev CLI 是给人类程序员用的，MCP 工具是给 agent 用的——MCP ### bbdev API 封装（自动管理 server 生命周期） - `bbdev_workload_build` — 编译 CTest -- `bbdev_verilator_run` — 全流程 clean→verilog→build→sim -- `bbdev_verilator_verilog` — 生成 Verilog（支持 balltype 参数单独 elaborate 某个 Ball） -- `bbdev_verilator_build` — 编译 Verilator -- `bbdev_verilator_sim` — 跑仿真 -- `bbdev_sardine_run` — 批量测试（支持 coverage） -- `bbdev_yosys_synth` — Yosys 综合 + OpenSTA 时序分析 +- `bbdev_verilator_run(binary, config?, batch?, coverage?)` — 全流程 clean→verilog→build→sim +- `bbdev_verilator_verilog(config, balltype?)` — 生成 Verilog；`config` 必传，`balltype` 可选（单 Ball elaborate） +- `bbdev_verilator_build(jobs?, coverage?)` — 编译 Verilator 仿真器 +- `bbdev_verilator_sim(binary, batch?, coverage?)` — 跑仿真（需先 build） +- `bbdev_sardine_run(workload?, coverage?)` — 批量测试 +- `bbdev_yosys_synth(top?, config?)` — Yosys 综合 + OpenSTA 时序分析 + +默认 config 值：`sims.verilator.BuckyballToyVerilatorConfig` +仿真 binary 命名格式：`ctest__test_singlecore-baremetal` ### 分析报告路径 - 面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解）、`area_report.txt`（顶层） diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index 0d1644c8..593d7792 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -2,25 +2,23 @@ package framework.balldomain.prototype.im2col import chisel3._ import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.top.GlobalConfig import framework.balldomain.prototype.im2col.configs.Im2colBallParam +/** + * Im2col — FSM scheduler that coordinates LineBufferManager and StreamWriter. + * + * Optimizations applied: + * A) Eliminated elemBuffer — elements stream directly from lineBuffer to pack register + * B) Eliminated hardware divider — dual counters (kRowIdx, kColIdx) replace t/kCol, t%kCol + */ @instantiable class Im2col(val b: GlobalConfig) extends Module { - private val maxK = Im2colBallParam().InputNum - private val elemWidth = Im2colBallParam().inputWidth - private val bankWidth = b.memDomain.bankWidth - private val lanesPerBeat = 16 - private val laneWidth = bankWidth / lanesPerBeat - private val maxInCol = 32 - private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat - private val maxKernelElems = maxK * maxK - - require(laneWidth == elemWidth, s"[Im2col] laneWidth($laneWidth) must equal elemWidth($elemWidth)") + private val maxK = Im2colBallParam().InputNum private val mapping = b.ballDomain.ballIdMappings .find(_.ballName == "Im2colBall") @@ -40,13 +38,18 @@ class Im2col(val b: GlobalConfig) extends Module { require(inBW >= 1, "[Im2col] inBW must be >= 1") require(outBW >= 1, "[Im2col] outBW must be >= 1") - val idle :: preload_rows :: generate_window :: write_window :: load_next_row :: complete :: Nil = Enum(6) - val state = RegInit(idle) + // --- Sub-modules --- + val lineBuf: Instance[LineBufferManager] = Instantiate(new LineBufferManager(b)) + val writer: Instance[StreamWriter] = Instantiate(new StreamWriter(b)) - private val robIdReg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - private val rBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - private val wBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + // --- FSM --- + val idle :: preload :: stream :: flushing :: loadNext :: complete :: Nil = Enum(6) + val state = RegInit(idle) + // --- Registers --- + private val robIdReg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + private val rBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + private val wBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) private val rBaseBeatReg = RegInit(0.U(32.W)) private val wBaseBeatReg = RegInit(0.U(32.W)) @@ -56,74 +59,60 @@ class Im2col(val b: GlobalConfig) extends Module { private val inColReg = RegInit(0.U(16.W)) private val startRowReg = RegInit(0.U(16.W)) private val startColReg = RegInit(0.U(16.W)) + private val rowPtrReg = RegInit(0.U(16.W)) + private val colPtrReg = RegInit(0.U(16.W)) - private val rowPtrReg = RegInit(0.U(16.W)) - private val colPtrReg = RegInit(0.U(16.W)) - - private val lineBuffer = RegInit(VecInit(Seq.fill(maxK)(VecInit(Seq.fill(maxInColWords)(0.U(bankWidth.W)))))) - private val elemBuffer = RegInit(VecInit(Seq.fill(maxKernelElems)(0.U(elemWidth.W)))) - - private val rowFifo = Module(new RowSlotFIFO(maxK)) - rowFifo.io.kRows := kRowReg - rowFifo.io.init := false.B - rowFifo.io.advance := false.B - - private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) - private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) - private val ldOutstandingReg = RegInit(false.B) - - private val genElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) - private val wrElemIdxReg = RegInit(0.U(log2Ceil(maxKernelElems + 1).W)) - private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) - private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) - - private def ceilDiv(a: UInt, d: Int): UInt = (a + (d - 1).U) / d.U - private val inColWords = ceilDiv(inColReg, lanesPerBeat) - private val totalKernelEls = kRowReg * kColReg + // Dual counters (optimization B — replaces hardware divider) + private val kRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val kColIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val elemDoneReg = RegInit(false.B) + // --- Derived signals --- private val rowMax = inRowReg - kRowReg private val colMax = inColReg - kColReg private val rowEnd = rowPtrReg === (startRowReg + rowMax) private val colEnd = colPtrReg === (startColReg + colMax) private val isLastWindow = rowEnd && colEnd - private def laneFromBeat(beat: UInt, lane: UInt): UInt = { - val lanes = beat.asTypeOf(Vec(lanesPerBeat, UInt(elemWidth.W))) - lanes(lane) - } - + // --- Top-level IO defaults --- io.cmdReq.ready := (state === idle) io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := robIdReg + io.status.idle := (state === idle) + io.status.running := (state =/= idle) && (state =/= complete) - io.status.idle := (state === idle) - io.status.running := (state =/= idle) && (state =/= complete) - + // --- Wire up LineBufferManager --- for (i <- 0 until inBW) { - io.bankRead(i).io.req.valid := false.B - io.bankRead(i).io.req.bits.addr := 0.U - io.bankRead(i).io.resp.ready := false.B - io.bankRead(i).bank_id := rBankReg - io.bankRead(i).rob_id := robIdReg - io.bankRead(i).ball_id := 0.U - io.bankRead(i).group_id := 0.U + lineBuf.io.bankRead(i) <> io.bankRead(i) } - + lineBuf.io.startPreload := false.B + lineBuf.io.startLoadNext := false.B + lineBuf.io.kRow := kRowReg + lineBuf.io.inCol := inColReg + lineBuf.io.rowPtr := rowPtrReg + lineBuf.io.rBaseBeat := rBaseBeatReg + lineBuf.io.rBankId := rBankReg + lineBuf.io.robId := robIdReg + lineBuf.io.elemReq.kRowIdx := kRowIdxReg + lineBuf.io.elemReq.kColIdx := kColIdxReg + lineBuf.io.elemReq.colPtr := colPtrReg + + // --- Wire up StreamWriter --- for (i <- 0 until outBW) { - io.bankWrite(i).io.req.valid := false.B - io.bankWrite(i).io.req.bits.addr := 0.U - io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) - io.bankWrite(i).io.req.bits.wmode := false.B - io.bankWrite(i).io.resp.ready := false.B - io.bankWrite(i).bank_id := wBankReg - io.bankWrite(i).rob_id := robIdReg - io.bankWrite(i).ball_id := 0.U - io.bankWrite(i).group_id := 0.U + writer.io.bankWrite(i) <> io.bankWrite(i) } - - io.bankWrite(0).io.resp.ready := true.B - + writer.io.start := false.B + writer.io.init := false.B + writer.io.flush := false.B + writer.io.wBaseBeat := wBaseBeatReg + writer.io.wBankId := wBankReg + writer.io.robId := robIdReg + + // Element stream: connect lineBuffer output to writer input + writer.io.elemIn.valid := false.B + writer.io.elemIn.bits := lineBuf.io.elemData + + // --- FSM --- switch(state) { is(idle) { when(io.cmdReq.fire) { @@ -143,15 +132,9 @@ class Im2col(val b: GlobalConfig) extends Module { rBaseBeatReg := 0.U wBaseBeatReg := 0.U - - ldRowIdxReg := 0.U - ldBeatIdxReg := 0.U - ldOutstandingReg := false.B - genElemIdxReg := 0.U - wrElemIdxReg := 0.U - packCntReg := 0.U - - rowFifo.io.init := true.B + kRowIdxReg := 0.U + kColIdxReg := 0.U + elemDoneReg := false.B val cmdKCol = io.cmdReq.bits.cmd.special(3, 0) val cmdKRow = io.cmdReq.bits.cmd.special(7, 4) @@ -163,137 +146,80 @@ class Im2col(val b: GlobalConfig) extends Module { when(invalidShape) { state := complete }.otherwise { - state := preload_rows + lineBuf.io.startPreload := true.B + state := preload } } } - is(preload_rows) { - val doneRows = ldRowIdxReg === kRowReg - val canIssue = !doneRows && !ldOutstandingReg && (ldBeatIdxReg < inColWords) - val rowElem = rowPtrReg + ldRowIdxReg - val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg - - io.bankRead(0).io.req.valid := canIssue - io.bankRead(0).io.req.bits.addr := reqAddr - io.bankRead(0).io.resp.ready := ldOutstandingReg - - when(io.bankRead(0).io.req.fire) { - ldOutstandingReg := true.B + is(preload) { + when(lineBuf.io.loadDone) { + kRowIdxReg := 0.U + kColIdxReg := 0.U + elemDoneReg := false.B + writer.io.init := true.B + state := stream } + } - when(io.bankRead(0).io.resp.fire) { - lineBuffer(ldRowIdxReg)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt - ldOutstandingReg := false.B + is(stream) { + // Stream elements from lineBuffer through writer + when(!elemDoneReg && writer.io.elemIn.ready) { + writer.io.elemIn.valid := true.B - when(ldBeatIdxReg + 1.U === inColWords) { - ldBeatIdxReg := 0.U - ldRowIdxReg := ldRowIdxReg + 1.U + // Advance dual counters + val isLastElem = (kRowIdxReg === (kRowReg - 1.U)) && (kColIdxReg === (kColReg - 1.U)) + when(isLastElem) { + elemDoneReg := true.B }.otherwise { - ldBeatIdxReg := ldBeatIdxReg + 1.U + when(kColIdxReg === (kColReg - 1.U)) { + kColIdxReg := 0.U + kRowIdxReg := kRowIdxReg + 1.U + }.otherwise { + kColIdxReg := kColIdxReg + 1.U + } } } - when(doneRows && !ldOutstandingReg) { - genElemIdxReg := 0.U - state := generate_window - } - } - - is(generate_window) { - val startLane = colPtrReg % lanesPerBeat.U - val safeKCol = Mux(kColReg === 0.U, 1.U, kColReg) - - val t = genElemIdxReg - val kRowIdx = t / safeKCol - val kColIdx = t % safeKCol - - val physicalSlot = RowSlotFIFO.logicalToPhysical(rowFifo.io.head, kRowIdx, kRowReg) - val laneSum = startLane + kColIdx - val beatIdx = laneSum / lanesPerBeat.U - val laneIdx = laneSum % lanesPerBeat.U - val beatWord = lineBuffer(physicalSlot)(beatIdx) - - elemBuffer(t) := laneFromBeat(beatWord, laneIdx) - - when(genElemIdxReg === (totalKernelEls - 1.U)) { - wrElemIdxReg := 0.U - state := write_window - }.otherwise { - genElemIdxReg := genElemIdxReg + 1.U - } - } - - is(write_window) { - val windowDone = wrElemIdxReg === totalKernelEls - val packFull = packCntReg === lanesPerBeat.U - - io.bankWrite(0).io.req.valid := packFull - io.bankWrite(0).io.req.bits.addr := wBaseBeatReg - io.bankWrite(0).io.req.bits.data := Cat(packReg.reverse) - io.bankWrite(0).io.req.bits.wmode := true.B - io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - - when(!windowDone && !packFull) { - packReg(packCntReg) := elemBuffer(wrElemIdxReg) - packCntReg := packCntReg + 1.U - wrElemIdxReg := wrElemIdxReg + 1.U - } - - when(io.bankWrite(0).io.req.fire) { - wBaseBeatReg := wBaseBeatReg + 1.U - packCntReg := 0.U - } - - when(windowDone) { - when(packFull && !io.bankWrite(0).io.req.fire) { - state := write_window + // Window done — transition without flushing (pack continues across windows) + when(elemDoneReg && !writer.io.busy) { + when(isLastWindow) { + // Last window: flush remaining partial pack + writer.io.flush := true.B + state := flushing + }.elsewhen(colEnd) { + // Row boundary: need to load next row + colPtrReg := startColReg + rowPtrReg := rowPtrReg + 1.U + kRowIdxReg := 0.U + kColIdxReg := 0.U + elemDoneReg := false.B + lineBuf.io.startLoadNext := true.B + state := loadNext }.otherwise { - when(isLastWindow) { - state := complete - }.elsewhen(colEnd) { - colPtrReg := startColReg - rowPtrReg := rowPtrReg + 1.U - - ldRowIdxReg := 0.U - ldBeatIdxReg := 0.U - ldOutstandingReg := false.B - state := load_next_row - }.otherwise { - colPtrReg := colPtrReg + 1.U - genElemIdxReg := 0.U - state := generate_window - } + // Column slide: directly start next window + colPtrReg := colPtrReg + 1.U + kRowIdxReg := 0.U + kColIdxReg := 0.U + elemDoneReg := false.B + state := stream } } } - is(load_next_row) { - val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) - val rowElem = rowPtrReg + kRowReg - 1.U - val reqAddr = rBaseBeatReg + rowElem * inColWords + ldBeatIdxReg - val targetSlot = rowFifo.io.slotToOverwrite - - io.bankRead(0).io.req.valid := canIssue - io.bankRead(0).io.req.bits.addr := reqAddr - io.bankRead(0).io.resp.ready := ldOutstandingReg - - when(io.bankRead(0).io.req.fire) { - ldOutstandingReg := true.B + is(flushing) { + // Wait for writer to finish flushing (write request must fire) + when(!writer.io.busy) { + state := complete } + } - when(io.bankRead(0).io.resp.fire) { - lineBuffer(targetSlot)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt - ldOutstandingReg := false.B - - when(ldBeatIdxReg + 1.U === inColWords) { - ldBeatIdxReg := 0.U - rowFifo.io.advance := true.B - genElemIdxReg := 0.U - state := generate_window - }.otherwise { - ldBeatIdxReg := ldBeatIdxReg + 1.U - } + is(loadNext) { + when(lineBuf.io.loadDone) { + kRowIdxReg := 0.U + kColIdxReg := 0.U + elemDoneReg := false.B + state := stream } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/LineBufferManager.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/LineBufferManager.scala new file mode 100644 index 00000000..0561ad94 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/LineBufferManager.scala @@ -0,0 +1,179 @@ +package framework.balldomain.prototype.im2col + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + +import framework.balldomain.blink.BankRead +import framework.top.GlobalConfig +import framework.balldomain.prototype.im2col.configs.Im2colBallParam + +/** + * LineBufferManager — manages lineBuffer loading and element extraction. + * + * Handles preload (loading kRow rows) and load_next_row (loading 1 new row + * with FIFO rotation). Provides a combinational element read port that + * extracts a single element from the lineBuffer given (kRowIdx, kColIdx). + */ +@instantiable +class LineBufferManager(val b: GlobalConfig) extends Module { + private val maxK = Im2colBallParam().InputNum + private val elemWidth = Im2colBallParam().inputWidth + private val bankWidth = b.memDomain.bankWidth + private val lanesPerBeat = 16 + private val maxInCol = 32 + private val maxInColWords = (maxInCol + lanesPerBeat - 1) / lanesPerBeat + + private val mapping = b.ballDomain.ballIdMappings + .find(_.ballName == "Im2colBall") + .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) + + private val inBW = mapping.inBW + + @public val io = IO(new Bundle { + // SRAM read port (directly connected to Ball's bankRead) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + + // Control inputs + val startPreload = Input(Bool()) // pulse: begin preloading kRow rows + val startLoadNext = Input(Bool()) // pulse: begin loading 1 new row + + // Configuration (latched by Im2col on cmdReq.fire) + val kRow = Input(UInt(log2Ceil(maxK + 1).W)) + val inCol = Input(UInt(16.W)) + val rowPtr = Input(UInt(16.W)) + val rBaseBeat = Input(UInt(32.W)) + val rBankId = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val robId = Input(UInt(log2Up(b.frontend.rob_entries).W)) + + // Status outputs + val loadDone = Output(Bool()) // high when load operation is complete + + // Element read port (combinational) + val elemReq = new Bundle { + val kRowIdx = Input(UInt(log2Ceil(maxK + 1).W)) + val kColIdx = Input(UInt(log2Ceil(maxK + 1).W)) + val colPtr = Input(UInt(16.W)) + } + + val elemData = Output(UInt(elemWidth.W)) + }) + + private def ceilDiv(a: UInt, d: Int): UInt = (a + (d - 1).U) / d.U + private val inColWords = ceilDiv(io.inCol, lanesPerBeat) + + // Line buffer storage + private val lineBuffer = RegInit(VecInit(Seq.fill(maxK)(VecInit(Seq.fill(maxInColWords)(0.U(bankWidth.W)))))) + + // Row slot FIFO for circular buffer management + private val rowFifo = Module(new RowSlotFIFO(maxK)) + rowFifo.io.kRows := io.kRow + rowFifo.io.init := false.B + rowFifo.io.advance := false.B + + // Load state machine + val sIdle :: sPreload :: sLoadNext :: Nil = Enum(3) + val loadState = RegInit(sIdle) + + private val ldRowIdxReg = RegInit(0.U(log2Ceil(maxK + 1).W)) + private val ldBeatIdxReg = RegInit(0.U(log2Ceil(maxInColWords + 1).W)) + private val ldOutstandingReg = RegInit(false.B) + + io.loadDone := (loadState === sIdle) + + // Default bankRead signals + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).bank_id := io.rBankId + io.bankRead(i).rob_id := io.robId + io.bankRead(i).ball_id := 0.U + io.bankRead(i).group_id := 0.U + } + + // Element extraction (combinational) — no division needed + private val startLane = io.elemReq.colPtr % lanesPerBeat.U + private val physicalSlot = RowSlotFIFO.logicalToPhysical(rowFifo.io.head, io.elemReq.kRowIdx, io.kRow) + private val laneSum = startLane + io.elemReq.kColIdx + private val beatIdx = laneSum / lanesPerBeat.U + private val laneIdx = laneSum % lanesPerBeat.U + private val beatWord = lineBuffer(physicalSlot)(beatIdx) + private val lanes = beatWord.asTypeOf(Vec(lanesPerBeat, UInt(elemWidth.W))) + io.elemData := lanes(laneIdx) + + switch(loadState) { + is(sIdle) { + when(io.startPreload) { + ldRowIdxReg := 0.U + ldBeatIdxReg := 0.U + ldOutstandingReg := false.B + rowFifo.io.init := true.B + loadState := sPreload + }.elsewhen(io.startLoadNext) { + ldBeatIdxReg := 0.U + ldOutstandingReg := false.B + loadState := sLoadNext + } + } + + is(sPreload) { + val doneRows = ldRowIdxReg === io.kRow + val canIssue = !doneRows && !ldOutstandingReg && (ldBeatIdxReg < inColWords) + val rowElem = io.rowPtr + ldRowIdxReg + val reqAddr = io.rBaseBeat + rowElem * inColWords + ldBeatIdxReg + + io.bankRead(0).io.req.valid := canIssue + io.bankRead(0).io.req.bits.addr := reqAddr + io.bankRead(0).io.resp.ready := ldOutstandingReg + + when(io.bankRead(0).io.req.fire) { + ldOutstandingReg := true.B + } + + when(io.bankRead(0).io.resp.fire) { + lineBuffer(ldRowIdxReg)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt + ldOutstandingReg := false.B + + when(ldBeatIdxReg + 1.U === inColWords) { + ldBeatIdxReg := 0.U + ldRowIdxReg := ldRowIdxReg + 1.U + }.otherwise { + ldBeatIdxReg := ldBeatIdxReg + 1.U + } + } + + when(doneRows && !ldOutstandingReg) { + loadState := sIdle + } + } + + is(sLoadNext) { + val canIssue = !ldOutstandingReg && (ldBeatIdxReg < inColWords) + val rowElem = io.rowPtr + io.kRow - 1.U + val reqAddr = io.rBaseBeat + rowElem * inColWords + ldBeatIdxReg + val targetSlot = rowFifo.io.slotToOverwrite + + io.bankRead(0).io.req.valid := canIssue + io.bankRead(0).io.req.bits.addr := reqAddr + io.bankRead(0).io.resp.ready := ldOutstandingReg + + when(io.bankRead(0).io.req.fire) { + ldOutstandingReg := true.B + } + + when(io.bankRead(0).io.resp.fire) { + lineBuffer(targetSlot)(ldBeatIdxReg) := io.bankRead(0).io.resp.bits.data.asUInt + ldOutstandingReg := false.B + + when(ldBeatIdxReg + 1.U === inColWords) { + ldBeatIdxReg := 0.U + rowFifo.io.advance := true.B + loadState := sIdle + }.otherwise { + ldBeatIdxReg := ldBeatIdxReg + 1.U + } + } + } + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/StreamWriter.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/StreamWriter.scala new file mode 100644 index 00000000..6ae89606 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/StreamWriter.scala @@ -0,0 +1,123 @@ +package framework.balldomain.prototype.im2col + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + +import framework.balldomain.blink.BankWrite +import framework.top.GlobalConfig +import framework.balldomain.prototype.im2col.configs.Im2colBallParam + +/** + * StreamWriter — packs elements into beats and writes to SRAM. + * + * Accepts one element per cycle via elemIn, packs lanesPerBeat elements + * into a full beat, then issues a write request. Handles partial flush + * at window end. + */ +@instantiable +class StreamWriter(val b: GlobalConfig) extends Module { + private val maxK = Im2colBallParam().InputNum + private val elemWidth = Im2colBallParam().inputWidth + private val bankWidth = b.memDomain.bankWidth + private val lanesPerBeat = 16 + + private val mapping = b.ballDomain.ballIdMappings + .find(_.ballName == "Im2colBall") + .getOrElse(throw new IllegalArgumentException("Im2colBall not found in config")) + + private val outBW = mapping.outBW + + @public val io = IO(new Bundle { + // SRAM write port + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + + // Element input + val elemIn = Flipped(Decoupled(UInt(elemWidth.W))) + + // Control + val start = Input(Bool()) // pulse: reset pack state for new window (does NOT reset write address) + val init = Input(Bool()) // pulse: initialize write address for new operation + val flush = Input(Bool()) // pulse: flush partial pack at window end + + // Configuration + val wBaseBeat = Input(UInt(32.W)) // initial write address (used only on init) + val wBankId = Input(UInt(log2Up(b.memDomain.bankNum).W)) + val robId = Input(UInt(log2Up(b.frontend.rob_entries).W)) + + // Status + val busy = Output(Bool()) // actively writing or have pending data + val wBaseBeatOut = Output(UInt(32.W)) // updated write address + }) + + private val packCntReg = RegInit(0.U(log2Ceil(lanesPerBeat + 1).W)) + private val packReg = RegInit(VecInit(Seq.fill(lanesPerBeat)(0.U(elemWidth.W)))) + private val wrPendingReg = RegInit(false.B) + private val wAddrReg = RegInit(0.U(32.W)) + private val flushingReg = RegInit(false.B) + + io.wBaseBeatOut := wAddrReg + io.busy := wrPendingReg || flushingReg + + // Default bankWrite signals + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B + io.bankWrite(i).bank_id := io.wBankId + io.bankWrite(i).rob_id := io.robId + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).group_id := 0.U + } + + io.bankWrite(0).io.resp.ready := true.B + + // Write request when pack full or flushing + io.bankWrite(0).io.req.valid := wrPendingReg + io.bankWrite(0).io.req.bits.addr := wAddrReg + io.bankWrite(0).io.req.bits.data := Cat(packReg.reverse) + io.bankWrite(0).io.req.bits.wmode := true.B + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + + // Accept elements when not pending a write + io.elemIn.ready := !wrPendingReg && !flushingReg + + when(io.init) { + wAddrReg := io.wBaseBeat + packCntReg := 0.U + wrPendingReg := false.B + flushingReg := false.B + } + + when(io.start) { + packCntReg := 0.U + wrPendingReg := false.B + flushingReg := false.B + } + + when(io.bankWrite(0).io.req.fire) { + wAddrReg := wAddrReg + 1.U + packCntReg := 0.U + wrPendingReg := false.B + flushingReg := false.B + } + + when(io.elemIn.fire) { + packReg(packCntReg) := io.elemIn.bits + val nextCnt = packCntReg + 1.U + packCntReg := nextCnt + when(nextCnt === lanesPerBeat.U) { + wrPendingReg := true.B + } + } + + when(io.flush && !wrPendingReg) { + when(packCntReg > 0.U) { + wrPendingReg := true.B + flushingReg := true.B + } + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala index db53bae3..e468c565 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/configs/Im2colBallParam.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.im2col.configs import upickle.default._ /** - * Im2colBall参数 + * Im2colBall Parameter */ case class Im2colBallParam( InputNum: Int, diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala index 3082b8a8..e8948dc1 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/configs/ReluBallParam.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.relu.configs import upickle.default._ /** - * ReluBall参数 + * ReluBall Parameter */ case class ReluBallParam( InputNum: Int, diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala index f3d7259f..035e901e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/configs/SystolicBallParam.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.systolicarray.configs import upickle.default._ /** - * SystolicBall 参数 + * SystolicBall Parameter */ case class SystolicBallParam( InputNum: Int, diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala index 87389adc..a11a7343 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/configs/TransposeBallParam.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.transpose.configs import upickle.default._ /** - * TransposeBall参数 + * TransposeBall Parameter */ case class TransposeBallParam( InputNum: Int, diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala index 3da72064..12da7338 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/configs/VectorBallParam.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.vector.configs import upickle.default._ /** - * VectorBall参数 + * VectorBall Parameter */ case class VectorBallParam( InputNum: Int, diff --git a/arch/src/main/scala/framework/core/configs/CoreParam.scala b/arch/src/main/scala/framework/core/configs/CoreParam.scala index 4e0386c9..9686f33a 100644 --- a/arch/src/main/scala/framework/core/configs/CoreParam.scala +++ b/arch/src/main/scala/framework/core/configs/CoreParam.scala @@ -3,7 +3,7 @@ package framework.core.configs import upickle.default._ /** - * Core参数 + * Core Parameter */ case class CoreParam( coreDataBytes: Int, diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index 4a8d8bf8..0213195e 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -3,7 +3,7 @@ package framework.frontend.configs import upickle.default._ /** - * Frontend参数 - 包含前端所有配置 + * Frontend Parameter - 包含前端所有配置 */ case class FrontendParam( rob_entries: Int, diff --git a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala index 405bde98..620b0109 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala +++ b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala @@ -3,7 +3,7 @@ package framework.gpdomain.configs import upickle.default._ /** - * GpDomain参数 + * GpDomain Parameter */ case class GpDomainParam( /** Number of lanes in the GP domain */ diff --git a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala index 6a13e2ee..63c03cd4 100644 --- a/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala +++ b/arch/src/main/scala/framework/memdomain/configs/MemDomainParam.scala @@ -3,7 +3,7 @@ package framework.memdomain.configs import upickle.default._ /** - * MemDomain参数 + * MemDomain Parameter */ case class MemDomainParam( bankNum: Int, diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala index c5087ac5..5bbcfa1d 100644 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ b/arch/src/main/scala/sims/verify/TargetConfig.scala @@ -6,10 +6,8 @@ import framework.top.GlobalConfig import framework.balldomain.blink.{BlinkIO, HasBlink} import framework.balldomain.prototype.vector.VecBall import framework.balldomain.prototype.relu.ReluBall -// import framework.balldomain.prototype.matrix.MatrixBall -// import framework.balldomain.prototype.transpose.TransposeBall -// import framework.balldomain.prototype.im2col.Im2colBall -// import framework.balldomain.prototype.nnlut.NNLutBall +import framework.balldomain.prototype.im2col.Im2colBall +import framework.balldomain.prototype.transpose.TransposeBall sealed trait BallType case object VecBallType extends BallType @@ -24,9 +22,9 @@ class TargetBall(ballType: BallType, b: GlobalConfig) extends Module with HasBli val ballName = ballType match { case VecBallType => "VecBall" case ReluBallType => "ReluBall" + case Im2colBallType => "Im2colBall" + case TransposeBallType => "TransposeBall" case MatrixBallType => throw new IllegalArgumentException("MatrixBall not implemented") - case Im2colBallType => throw new IllegalArgumentException("Im2colBall not implemented") - case TransposeBallType => throw new IllegalArgumentException("TransposeBall not implemented") case NNLutBallType => throw new IllegalArgumentException("NNLutBall not implemented") case _ => throw new scala.MatchError("TargetBall does not handle this ball type") } @@ -41,9 +39,11 @@ class TargetBall(ballType: BallType, b: GlobalConfig) extends Module with HasBli def blink: BlinkIO = io val ball = ballType match { - case VecBallType => Module(new VecBall(b)) - case ReluBallType => Module(new ReluBall(b)) - case _ => throw new scala.MatchError("TargetBall does not handle this ball type") + case VecBallType => Module(new VecBall(b)) + case ReluBallType => Module(new ReluBall(b)) + case Im2colBallType => Module(new Im2colBall(b)) + case TransposeBallType => Module(new TransposeBall(b)) + case _ => throw new scala.MatchError("TargetBall does not handle this ball type") } io <> ball.blink diff --git a/compiler b/compiler index 1a3d0383..e66f53ad 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit 1a3d038338e5251ed191506674544630efc2ecf8 +Subproject commit e66f53ad6c6ff125d644f14c89627b180dd3fd83 diff --git a/scripts/claude/mcp_server.py b/scripts/claude/mcp_server.py index ad90facc..a0586014 100644 --- a/scripts/claude/mcp_server.py +++ b/scripts/claude/mcp_server.py @@ -20,6 +20,7 @@ import time from pathlib import Path from typing import Any, Dict, List, Optional +from urllib.error import HTTPError from mcp.server.fastmcp import FastMCP @@ -28,6 +29,8 @@ # --------------------------------------------------------------------------- REPO_ROOT = Path(__file__).resolve().parents[2] BBDEV_API_DIR = REPO_ROOT / "bbdev" / "api" +BBDEV_LOG_DIR = REPO_ROOT / "bbdev" / "api" / "steps" +BBDEV_SERVER_LOG = REPO_ROOT / "bbdev" / "server.log" REGISTRATION_FILES = { "default_json": REPO_ROOT @@ -46,7 +49,7 @@ _bbdev_port: Optional[int] = None -def _find_available_port(start: int = 5100, end: int = 5500) -> int: +def _find_available_port(start: int = 5200, end: int = 5500) -> int: for port in range(start, end + 1): try: with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: @@ -73,11 +76,12 @@ def _ensure_bbdev_server() -> int: shutil.rmtree(aof_dir) port = _find_available_port() + _log_file = open(BBDEV_SERVER_LOG, "a", encoding="utf-8") _bbdev_proc = subprocess.Popen( ["pnpm", "dev", "--port", str(port)], cwd=str(BBDEV_API_DIR), - stdout=subprocess.DEVNULL, - stderr=subprocess.DEVNULL, + stdout=_log_file, + stderr=_log_file, ) _bbdev_port = port @@ -143,6 +147,20 @@ def _bbdev_call( with urllib.request.urlopen(req, timeout=timeout) as resp: body = resp.read().decode("utf-8") return json.loads(body) + except urllib.error.HTTPError as e: + error_body = "" + try: + error_body = e.read().decode("utf-8") + except Exception: + pass + return { + "success": False, + "failure": True, + "error": str(e), + "status_code": e.code, + "response_body": error_body, + "server_log": str(BBDEV_SERVER_LOG), + } except Exception as e: return {"success": False, "failure": True, "error": str(e)} From 85124a8813081ce3221d7f3c163cc55439c6ab28 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 8 Mar 2026 00:03:28 +0800 Subject: [PATCH 148/238] [bb-tests] feat: add MLIR OpTest workloads and tests for Gemmini operations --- bb-tests/sardine/pytest.ini | 1 + bb-tests/sardine/tests/test_mlir.py | 121 ++++++++++++ .../lib/bbhw/isa/42_gemmini_config.c | 20 ++ .../lib/bbhw/isa/43_gemmini_preload.c | 17 ++ .../bbhw/isa/44_gemmini_compute_preloaded.c | 20 ++ .../bbhw/isa/45_gemmini_compute_accumulated.c | 20 ++ .../workloads/lib/bbhw/isa/46_gemmini_flush.c | 12 ++ bb-tests/workloads/lib/bbhw/isa/isa.h | 5 + .../workloads/src/CTest/toy/CMakeLists.txt | 2 + .../src/CTest/toy/gemmini_matmul_test.c | 75 +++++++ bb-tests/workloads/src/OpTest/CMakeLists.txt | 5 +- .../workloads/src/OpTest/tile/CMakeLists.txt | 69 +++++++ .../src/OpTest/tile/tile_conv2d.mlir | 40 ++++ .../src/OpTest/tile/tile_matmul.mlir | 93 +++++++++ .../src/OpTest/tile/tile_transpose.mlir | 56 ++++++ .../workloads/src/OpTest/toy/CMakeLists.txt | 187 ++++++------------ .../workloads/src/OpTest/toy/bb_conv2d.mlir | 43 ++++ .../workloads/src/OpTest/toy/bb_dma1.mlir | 11 +- .../workloads/src/OpTest/toy/bb_dma2.mlir | 17 +- .../workloads/src/OpTest/toy/bb_dma3.mlir | 15 +- .../workloads/src/OpTest/toy/bb_im2col.mlir | 46 +++++ .../src/OpTest/toy/bb_mul_warp16.mlir | 32 +-- .../src/OpTest/toy/bb_mvin_mvout.mlir | 22 +-- .../src/OpTest/toy/bb_quant_dequant.mlir | 51 +++++ compiler | 2 +- 25 files changed, 788 insertions(+), 194 deletions(-) create mode 100644 bb-tests/sardine/tests/test_mlir.py create mode 100644 bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c create mode 100644 bb-tests/workloads/src/OpTest/tile/CMakeLists.txt create mode 100644 bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir create mode 100644 bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir create mode 100644 bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir create mode 100644 bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir create mode 100644 bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir create mode 100644 bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir diff --git a/bb-tests/sardine/pytest.ini b/bb-tests/sardine/pytest.ini index 13e49a22..ec881495 100644 --- a/bb-tests/sardine/pytest.ini +++ b/bb-tests/sardine/pytest.ini @@ -35,6 +35,7 @@ markers = fast: Fast tests ctest: CTest tests + mlir: MLIR OpTest tests # 最小版本要求 minversion = 6.0 diff --git a/bb-tests/sardine/tests/test_mlir.py b/bb-tests/sardine/tests/test_mlir.py new file mode 100644 index 00000000..b9d273aa --- /dev/null +++ b/bb-tests/sardine/tests/test_mlir.py @@ -0,0 +1,121 @@ +import pytest +import logging +import time +import os +from pathlib import Path + + +sardine_dir = Path(__file__).parent.parent +mlir_toy_workload_dir = ( + sardine_dir / ".." / "output" / "workloads" / "src" / "OpTest" / "toy" +) +mlir_tile_workload_dir = ( + sardine_dir / ".." / "output" / "workloads" / "src" / "OpTest" / "tile" +) + + +# Define all MLIR OpTest workloads (binary name, test id) +mlir_workloads = [ + ("bb_mvin_mvout_singlecore-baremetal", "bb_mvin_mvout"), + ("bb_dma1_singlecore-baremetal", "bb_dma1"), + ("bb_dma2_singlecore-baremetal", "bb_dma2"), + ("bb_dma3_singlecore-baremetal", "bb_dma3"), + ("bb_mul_warp16_singlecore-baremetal", "bb_mul_warp16"), + ("bb_im2col_singlecore-baremetal", "bb_im2col"), + ("bb_quant_dequant_singlecore-baremetal", "bb_quant_dequant"), +] + +# Tile-level tests +mlir_tile_workloads = [ + ("tile_matmul_singlecore-baremetal", "tile_matmul"), + ("tile_transpose_singlecore-baremetal", "tile_transpose"), + ("tile_conv2d_singlecore-baremetal", "tile_conv2d"), +] + + +@pytest.mark.verilator +@pytest.mark.mlir +@pytest.mark.parametrize( + "workload_path, workload_id, test_index", + [(path, id, idx) for idx, (path, id) in enumerate(mlir_workloads)], + ids=[w[1] for w in mlir_workloads], +) +def test_mlir_optest(command_run, caplog, workload_path, workload_id, test_index): + caplog.set_level(logging.INFO) + + time.sleep(test_index * 20) + start_time = time.time() + coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" + command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' + logging.info(f"Running command: {command}") + + early_exit_pattern = ( + r"Task completed\. Command running on http://localhost:\d+ is finished" + ) + result = command_run(command, early_exit_pattern=early_exit_pattern, timeout=1200) + execution_time = time.time() - start_time + + logging.info(f"Workload: {workload_id}") + logging.info(f"Workload path: {workload_path}") + logging.info(f"Test index: {test_index}") + logging.info(f"Execution time: {execution_time:.2f} seconds") + logging.info(f"Return code: {result['returncode']}") + logging.info("Script output completed") + + min_execution_time = 5.0 + assert ( + execution_time >= min_execution_time + ), f"Script executed too quickly: {execution_time:.2f}s < {min_execution_time}s" + assert result["returncode"] in [ + 0, + 1, + ], f"Script failed with unexpected return code: {result['returncode']}" + + if "PASSED" not in result["stdout"]: + assert False, f"Script failed: {result['stdout']}" + + logging.info("test completed") + + +@pytest.mark.verilator +@pytest.mark.mlir +@pytest.mark.parametrize( + "workload_path, workload_id, test_index", + [(path, id, idx) for idx, (path, id) in enumerate(mlir_tile_workloads)], + ids=[w[1] for w in mlir_tile_workloads], +) +def test_mlir_tile_optest(command_run, caplog, workload_path, workload_id, test_index): + caplog.set_level(logging.INFO) + + time.sleep(test_index * 20) + start_time = time.time() + coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" + command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' + logging.info(f"Running command: {command}") + + early_exit_pattern = ( + r"Task completed\. Command running on http://localhost:\d+ is finished" + ) + result = command_run(command, early_exit_pattern=early_exit_pattern, timeout=1200) + execution_time = time.time() - start_time + + logging.info(f"Workload: {workload_id}") + logging.info(f"Workload path: {workload_path}") + logging.info(f"Test index: {test_index}") + logging.info(f"Execution time: {execution_time:.2f} seconds") + logging.info(f"Return code: {result['returncode']}") + logging.info("Script output completed") + + min_execution_time = 5.0 + assert ( + execution_time >= min_execution_time + ), f"Script executed too quickly: {execution_time:.2f}s < {min_execution_time}s" + assert result["returncode"] in [ + 0, + 1, + ], f"Script failed with unexpected return code: {result['returncode']}" + + if "PASSED" not in result["stdout"]: + assert False, f"Script failed: {result['stdout']}" + + logging.info("test completed") diff --git a/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c b/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c new file mode 100644 index 00000000..4b0f29a8 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c @@ -0,0 +1,20 @@ +#ifndef _BB_GEMMINI_CONFIG_H_ +#define _BB_GEMMINI_CONFIG_H_ + +#include "isa.h" + +#define BB_GEMMINI_CONFIG_FUNC7 42 + +// Configure Gemmini systolic array +// dataflow: 0=OS, 1=WS +// activation: 0=none, 1=relu +// a_transpose, b_transpose: transpose flags +// in_shift: right-shift amount for output +#define bb_gemmini_config(dataflow, activation, a_transpose, b_transpose, \ + in_shift) \ + BUCKYBALL_INSTRUCTION_R_R((FIELD(dataflow, 2, 2) | FIELD(activation, 3, 4) | \ + FIELD(a_transpose, 8, 8) | \ + FIELD(b_transpose, 9, 9)), \ + (FIELD(in_shift, 0, 31)), BB_GEMMINI_CONFIG_FUNC7) + +#endif // _BB_GEMMINI_CONFIG_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c b/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c new file mode 100644 index 00000000..468e7aa5 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c @@ -0,0 +1,17 @@ +#ifndef _BB_GEMMINI_PRELOAD_H_ +#define _BB_GEMMINI_PRELOAD_H_ + +#include "isa.h" + +#define BB_GEMMINI_PRELOAD_FUNC7 43 + +// Preload D/B matrix into systolic array +// op1_bank_id: source bank for D (OS) or B (WS) +// wr_bank_id: destination bank for C output +// iter: number of rows to preload +#define bb_gemmini_preload(op1_bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ + (FIELD(iter, 0, 9)), BB_GEMMINI_PRELOAD_FUNC7) + +#endif // _BB_GEMMINI_PRELOAD_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c b/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c new file mode 100644 index 00000000..68f5af06 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c @@ -0,0 +1,20 @@ +#ifndef _BB_GEMMINI_COMPUTE_PRELOADED_H_ +#define _BB_GEMMINI_COMPUTE_PRELOADED_H_ + +#include "isa.h" + +#define BB_GEMMINI_COMPUTE_PRELOADED_FUNC7 44 + +// Compute matmul using preloaded data: C = A * B + D(preloaded) +// op1_bank_id: bank for A matrix +// op2_bank_id: bank for B matrix (OS) or D matrix (WS) +// wr_bank_id: bank for C output +// iter: number of rows +#define bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, wr_bank_id, \ + iter) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ + (FIELD(iter, 0, 9)), \ + BB_GEMMINI_COMPUTE_PRELOADED_FUNC7) + +#endif // _BB_GEMMINI_COMPUTE_PRELOADED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c b/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c new file mode 100644 index 00000000..3de78f3d --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c @@ -0,0 +1,20 @@ +#ifndef _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ +#define _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ + +#include "isa.h" + +#define BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7 45 + +// Compute matmul reusing previously accumulated results +// op1_bank_id: bank for A matrix +// op2_bank_id: bank for B/D matrix +// wr_bank_id: bank for C output +// iter: number of rows +#define bb_gemmini_compute_accumulated(op1_bank_id, op2_bank_id, wr_bank_id, \ + iter) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ + (FIELD(iter, 0, 9)), \ + BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7) + +#endif // _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c b/bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c new file mode 100644 index 00000000..c589f0b8 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c @@ -0,0 +1,12 @@ +#ifndef _BB_GEMMINI_FLUSH_H_ +#define _BB_GEMMINI_FLUSH_H_ + +#include "isa.h" + +#define BB_GEMMINI_FLUSH_FUNC7 46 + +// Flush the systolic array state +#define bb_gemmini_flush() \ + BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_GEMMINI_FLUSH_FUNC7) + +#endif // _BB_GEMMINI_FLUSH_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index a51fdbb7..3fd7cebf 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -53,5 +53,10 @@ typedef int32_t result_t; #include "39_bfp.c" #include "40_quant.c" #include "41_dequant.c" +#include "42_gemmini_config.c" +#include "43_gemmini_preload.c" +#include "44_gemmini_compute_preloaded.c" +#include "45_gemmini_compute_accumulated.c" +#include "46_gemmini_flush.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index aa6a5853..98676a32 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -118,6 +118,7 @@ add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) add_cross_platform_test_target(ctest_bfp_test bfp_test.c) add_cross_platform_test_target(ctest_quant_test quant_test.c) add_cross_platform_test_target(ctest_dequant_test dequant_test.c) +add_cross_platform_test_target(ctest_gemmini_matmul_test gemmini_matmul_test.c) # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS @@ -145,5 +146,6 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_bfp_test ctest_quant_test ctest_dequant_test + ctest_gemmini_matmul_test COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c new file mode 100644 index 00000000..c78f0e0c --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c @@ -0,0 +1,75 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); +static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); +static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); + +void hw_gemmini_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, + int size) { + uint32_t op1_bank_id = 0; // A matrix + uint32_t op2_bank_id = 1; // B matrix + int acc_bank_id = 2; // C output (accumulator width) + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + + // Load A and B into SRAM banks + bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); + bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); + + // Configure: OS mode, no activation, no transpose, no shift + bb_gemmini_config(0, 0, 0, 0, 0); + + // Preload D=0 (zero bias), set output bank + bb_gemmini_preload(op1_bank_id, acc_bank_id, size); + + // Compute: A * B + D(preloaded) + bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, acc_bank_id, size); + + // Read results back + bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); + bb_fence(); +} + +int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { + cpu_matmul(a, b, expected_matrix, size, size, size); + hw_gemmini_matmul(test_name, a, b, output_matrix, size); + + if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { + printf("Test %s PASSED\n", test_name); + return 1; + } else { + printf("Test %s FAILED\n", test_name); + return 0; + } +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + init_u8_random_matrix(input_matrix_a, DIM, DIM, 42); + init_u8_random_matrix(input_matrix_b, DIM, DIM, 84); + + int passed = + run_test("Gemmini OS Matmul", input_matrix_a, input_matrix_b, DIM); + if (passed) { + printf("Gemmini matmul test PASSED\n"); + return 0; + } else { + printf("Gemmini matmul test FAILED\n"); + return 1; + } + +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/OpTest/CMakeLists.txt b/bb-tests/workloads/src/OpTest/CMakeLists.txt index 784d4753..6d2f6993 100644 --- a/bb-tests/workloads/src/OpTest/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/CMakeLists.txt @@ -1,10 +1,13 @@ set(OPTEST_TOY_DIR ${OPTEST_WORKLOAD_DIR}/toy) +set(OPTEST_TILE_DIR ${OPTEST_WORKLOAD_DIR}/tile) set(OPTEST_GEMMINI_DIR ${OPTEST_WORKLOAD_DIR}/gemmini) add_subdirectory(toy) +add_subdirectory(tile) add_subdirectory(gemmini) add_custom_target(OpTest-all ALL DEPENDS OpTest-gemmini -# OpTest-toy + OpTest-toy + OpTest-tile ) diff --git a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt new file mode 100644 index 00000000..180f8c2d --- /dev/null +++ b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt @@ -0,0 +1,69 @@ + +#------------------------------------------------------------------------------- +# Generate executables for different platforms +#------------------------------------------------------------------------------- + +# singlecore baremetal +function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) + set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal.o") + set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal") + + # Compile xx.mlir to xx-baremetal.o + # Tile-level tests need: linalg->tile->buckyball->llvm pipeline + add_custom_command( + OUTPUT ${OBJ_FILE} + COMMAND ${BUDDY_OPT} ${MLIR_FILE} + -convert-linalg-to-tile + -convert-tile-to-buckyball + -expand-strided-metadata + -convert-linalg-to-loops + -lower-buckyball + -finalize-memref-to-llvm + -convert-arith-to-llvm + -convert-func-to-llvm + -reconcile-unrealized-casts | + ${BUDDY_TRANSLATE} --buddy-to-llvmir | + ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 + -mattr=+buddyext,+D -float-abi=hard + -relocation-model=pic + -o ${OBJ_FILE} + DEPENDS ${MLIR_FILE} + COMMENT "Compiling ${MLIR_FILE} to singlecore baremetal object" + ) + + # Link (use htif_nano.specs crt0) + add_custom_command( + OUTPUT ${EXECUTABLE} + COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} + ${OBJ_FILE} -o ${EXECUTABLE} + DEPENDS ${OBJ_FILE} + COMMENT "Linking singlecore baremetal executable: ${EXECUTABLE}" + ) + + add_custom_target(${TARGET_NAME}_singlecore_baremetal + DEPENDS ${EXECUTABLE} + ) +endfunction() + +# Unified build function +function(add_optest_target TARGET_NAME MLIR_FILE) + add_singlecore_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) + + add_custom_target(${TARGET_NAME} + DEPENDS ${TARGET_NAME}_singlecore_baremetal + COMMENT "Building ${TARGET_NAME}" + ) +endfunction() + +#------------------------------------------------------------------------------- +# Build list +#------------------------------------------------------------------------------- +add_optest_target(tile_matmul ${OPTEST_TILE_DIR}/tile_matmul.mlir) +add_optest_target(tile_transpose ${OPTEST_TILE_DIR}/tile_transpose.mlir) +add_optest_target(tile_conv2d ${OPTEST_TILE_DIR}/tile_conv2d.mlir) + +add_custom_target(OpTest-tile ALL DEPENDS + tile_matmul + tile_transpose + tile_conv2d +) diff --git a/bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir b/bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir new file mode 100644 index 00000000..4db5b905 --- /dev/null +++ b/bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir @@ -0,0 +1,40 @@ +// Test for tile-level conv2d: linalg.conv_2d_nhwc_hwcf -> tile.tile_conv2d -> buckyball +// Pipeline: -convert-linalg-to-tile -convert-tile-to-buckyball -lower-buckyball +// Input: [1,6,6,1], Filter: [3,3,1,1], Output: [1,4,4,1] + +// Input image: 6x6 with incrementing values +memref.global "private" @input : memref<1x6x6x1xi8> = dense<[[ + [[1],[2],[3],[4],[5],[6]], + [[7],[8],[9],[10],[11],[12]], + [[13],[14],[15],[16],[17],[18]], + [[19],[20],[21],[22],[23],[24]], + [[25],[26],[27],[28],[29],[30]], + [[31],[32],[33],[34],[35],[36]] +]]> + +// Filter: 3x3 all ones (sum pooling equivalent) +memref.global "private" @filter : memref<3x3x1x1xi8> = dense<[[ + [[1]],[[1]],[[1]] +],[ + [[1]],[[1]],[[1]] +],[ + [[1]],[[1]],[[1]] +]]> + +func.func @main() -> i8 { + %0 = arith.constant 0 : i8 + + %input = memref.get_global @input : memref<1x6x6x1xi8> + %filter = memref.get_global @filter : memref<3x3x1x1xi8> + %output = memref.alloc() : memref<1x4x4x1xi32> + + // linalg.conv_2d_nhwc_hwcf -> tile.tile_conv2d -> im2col + matmul + linalg.conv_2d_nhwc_hwcf + ins(%input, %filter : memref<1x6x6x1xi8>, memref<3x3x1x1xi8>) + outs(%output : memref<1x4x4x1xi32>) + + buckyball.bb_print_memref %output : memref<1x4x4x1xi32> + + memref.dealloc %output : memref<1x4x4x1xi32> + return %0 : i8 +} diff --git a/bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir b/bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir new file mode 100644 index 00000000..19a72228 --- /dev/null +++ b/bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir @@ -0,0 +1,93 @@ +// Test for tile-level matmul: linalg.matmul -> tile.tile_matmul -> buckyball +// Pipeline: -convert-linalg-to-tile -convert-tile-to-buckyball -lower-buckyball + +// Matrix A: 32x32 identity matrix +memref.global "private" @matrix_a : memref<32x32xi8> = dense<[ + [1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0], + [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1] +]> + +// Matrix B: 32x32 with row pattern +memref.global "private" @matrix_b : memref<32x32xi8> = dense<[ + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16] +]> + +func.func @main() -> i8 { + %0 = arith.constant 0 : i8 + + %arrayA = memref.get_global @matrix_a : memref<32x32xi8> + %arrayB = memref.get_global @matrix_b : memref<32x32xi8> + %arrayC = memref.alloc() : memref<32x32xi32> + + // linalg.matmul -> tile.tile_matmul -> buckyball.bb_matmul -> intrinsics + // Identity * B = B (result should equal matrix B) + linalg.matmul + ins(%arrayA, %arrayB : memref<32x32xi8>, memref<32x32xi8>) + outs(%arrayC : memref<32x32xi32>) + + buckyball.bb_print_memref %arrayC : memref<32x32xi32> + + memref.dealloc %arrayC : memref<32x32xi32> + return %0 : i8 +} diff --git a/bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir b/bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir new file mode 100644 index 00000000..916e1d7e --- /dev/null +++ b/bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir @@ -0,0 +1,56 @@ +// Test for tile-level transpose: linalg.transpose -> tile.tile_transpose -> buckyball +// Pipeline: -convert-linalg-to-tile -convert-tile-to-buckyball -lower-buckyball + +// Matrix: 32x32 with distinct values for verification +memref.global "private" @matrix_input : memref<32x32xi8> = dense<[ + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], + [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], + [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64] +]> + +func.func @main() -> i8 { + %0 = arith.constant 0 : i8 + + %input = memref.get_global @matrix_input : memref<32x32xi8> + %output = memref.alloc() : memref<32x32xi8> + + // linalg.transpose -> tile.tile_transpose -> buckyball.bb_transpose -> intrinsics + linalg.transpose + ins(%input : memref<32x32xi8>) + outs(%output : memref<32x32xi8>) + permutation = [1, 0] + + buckyball.bb_print_memref %output : memref<32x32xi8> + + memref.dealloc %output : memref<32x32xi8> + return %0 : i8 +} diff --git a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt index cdce50b0..88827e24 100644 --- a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt @@ -1,137 +1,74 @@ - #------------------------------------------------------------------------------- # Generate executables for different platforms #------------------------------------------------------------------------------- -# single-core baremetal -# function(add_baremetal_target TARGET_NAME MLIR_FILE) -# set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-baremetal.o") -# set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-baremetal") - -# # Compile xx.mlir to xx-baremetal.o -# add_custom_command( -# OUTPUT ${OBJ_FILE} -# COMMAND ${BUDDY_OPT} ${MLIR_FILE} -# -lower-buckyball | -# ${BUDDY_TRANSLATE} --buddy-to-llvmir | -# ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 -# -mattr=+buddyext,+D -float-abi=hard -# -relocation-model=pic -# -o ${OBJ_FILE} -# DEPENDS ${MLIR_FILE} -# COMMENT "Compiling ${MLIR_FILE} to object file" -# ) - -# # Link xx-baremetal.o to xx-baremetal -# add_custom_command( - -# OUTPUT ${EXECUTABLE} -# COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -# ${OBJ_FILE} -o ${EXECUTABLE} -# DEPENDS ${OBJ_FILE} -# COMMENT "Linking baremetal executable: ${EXECUTABLE}" -# ) - -# # Create target for xx-baremetal -# add_custom_target(${TARGET_NAME}_baremetal -# DEPENDS ${EXECUTABLE} -# ) -# endfunction() - -# multi-core baremetal -# function(add_baremetal_target TARGET_NAME MLIR_FILE) -# set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-baremetal.o") -# set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-baremetal") - -# # Compile xx.mlir to xx-baremetal.o -# add_custom_command( -# OUTPUT ${OBJ_FILE} -# COMMAND ${BUDDY_OPT} ${MLIR_FILE} -# -lower-buckyball=hartId=3 | -# ${BUDDY_TRANSLATE} --buddy-to-llvmir | -# ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 -# -mattr=+buddyext,+D -float-abi=hard -# -relocation-model=pic -# -o ${OBJ_FILE} -# DEPENDS ${MLIR_FILE} -# COMMENT "Compiling ${MLIR_FILE} to object file" -# ) - -# # Link xx-baremetal.o to xx-baremetal -# add_custom_command( - -# OUTPUT ${EXECUTABLE} -# COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -# ${OBJ_FILE} -o ${EXECUTABLE} -# DEPENDS ${OBJ_FILE} -# COMMENT "Linking baremetal executable: ${EXECUTABLE}" -# ) - -# # Create target for xx-baremetal -# add_custom_target(${TARGET_NAME}_baremetal -# DEPENDS ${EXECUTABLE} -# ) -# endfunction() - -# Generate Linux executables -# function(add_linux_target TARGET_NAME MLIR_FILE) -# set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-linux.o") -# set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-linux") - -# # Compile xx.mlir to xx-linux.o -# add_custom_command( -# OUTPUT ${OBJ_FILE} -# COMMAND ${BUDDY_OPT} ${MLIR_FILE} -# -lower-buckyball | -# ${BUDDY_TRANSLATE} --buddy-to-llvmir | -# ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 -# -mattr=+buddyext,+D -float-abi=hard -# -o ${OBJ_FILE} -# DEPENDS ${MLIR_FILE} -# COMMENT "Compiling ${MLIR_FILE} to Linux object file" -# ) - -# # Link xx-linux.o to xx-linux -# add_custom_command( -# OUTPUT ${EXECUTABLE} -# COMMAND ${LINUX_CC} -O2 -static ${OBJ_FILE} -o ${EXECUTABLE} -# DEPENDS ${OBJ_FILE} -# COMMENT "Linking Linux executable: ${EXECUTABLE}" -# ) - -# # Create target for xx-linux - use target name prefix to avoid conflicts -# add_custom_target(${TARGET_NAME}_linux -# DEPENDS ${EXECUTABLE} -# ) -# endfunction() +# singlecore baremetal +function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) + set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal.o") + set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal") + + # Compile xx.mlir to xx-baremetal.o + add_custom_command( + OUTPUT ${OBJ_FILE} + COMMAND ${BUDDY_OPT} ${MLIR_FILE} + -expand-strided-metadata + -convert-linalg-to-loops + -lower-buckyball + -finalize-memref-to-llvm + -convert-arith-to-llvm + -convert-func-to-llvm + -reconcile-unrealized-casts | + ${BUDDY_TRANSLATE} --buddy-to-llvmir | + ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 + -mattr=+buddyext,+D -float-abi=hard + -relocation-model=pic + -o ${OBJ_FILE} + DEPENDS ${MLIR_FILE} + COMMENT "Compiling ${MLIR_FILE} to singlecore baremetal object" + ) + + # Link (same as CTest singlecore: no start.S, use htif_nano.specs crt0) + add_custom_command( + OUTPUT ${EXECUTABLE} + COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} + ${OBJ_FILE} -o ${EXECUTABLE} + DEPENDS ${OBJ_FILE} + COMMENT "Linking singlecore baremetal executable: ${EXECUTABLE}" + ) + + add_custom_target(${TARGET_NAME}_singlecore_baremetal + DEPENDS ${EXECUTABLE} + ) +endfunction() # Unified build function -# function(add_cross_platform_target TARGET_NAME MLIR_FILE) -# add_multicore_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) -# add_singlecore_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) -# add_linux_target(${TARGET_NAME} ${MLIR_FILE}) - -# add_custom_target(${TARGET_NAME} -# DEPENDS ${TARGET_NAME}_multicore_baremetal ${TARGET_NAME}_singlecore_baremetal ${TARGET_NAME}_linux -# COMMENT "Building ${TARGET_NAME} for both baremetal and Linux" -# ) -# endfunction() +function(add_optest_target TARGET_NAME MLIR_FILE) + add_singlecore_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) + add_custom_target(${TARGET_NAME} + DEPENDS ${TARGET_NAME}_singlecore_baremetal + COMMENT "Building ${TARGET_NAME}" + ) +endfunction() #------------------------------------------------------------------------------- # Build list #------------------------------------------------------------------------------- -# add_cross_platform_target(bb_mvin_mvout ${OPTEST_TOY_DIR}/bb_mvin_mvout.mlir) -# add_cross_platform_target(bb_dma1 ${OPTEST_TOY_DIR}/bb_dma1.mlir) -# add_cross_platform_target(bb_dma2 ${OPTEST_TOY_DIR}/bb_dma2.mlir) -# add_cross_platform_target(bb_dma3 ${OPTEST_TOY_DIR}/bb_dma3.mlir) -# add_cross_platform_target(bb_mul_warp16 ${OPTEST_TOY_DIR}/bb_mul_warp16.mlir) - -# add_custom_target(OpTest-toy ALL DEPENDS -# bb_mvin_mvout -# bb_dma1 -# bb_dma2 -# bb_dma3 -# bb_mul_warp16 -# ) +add_optest_target(bb_mvin_mvout ${OPTEST_TOY_DIR}/bb_mvin_mvout.mlir) +add_optest_target(bb_dma1 ${OPTEST_TOY_DIR}/bb_dma1.mlir) +add_optest_target(bb_dma2 ${OPTEST_TOY_DIR}/bb_dma2.mlir) +add_optest_target(bb_dma3 ${OPTEST_TOY_DIR}/bb_dma3.mlir) +add_optest_target(bb_mul_warp16 ${OPTEST_TOY_DIR}/bb_mul_warp16.mlir) +add_optest_target(bb_im2col ${OPTEST_TOY_DIR}/bb_im2col.mlir) +add_optest_target(bb_quant_dequant ${OPTEST_TOY_DIR}/bb_quant_dequant.mlir) + +add_custom_target(OpTest-toy ALL DEPENDS + bb_mvin_mvout + bb_dma1 + bb_dma2 + bb_dma3 + bb_mul_warp16 + bb_im2col + bb_quant_dequant +) diff --git a/bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir b/bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir new file mode 100644 index 00000000..82ba009d --- /dev/null +++ b/bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir @@ -0,0 +1,43 @@ +// Test for conv2d end-to-end: tile_conv2d -> im2col + matmul +// RUN: buddy-opt %s \ +// RUN: -convert-tile-to-buckyball \ +// RUN: -lower-buckyball | \ +// RUN: FileCheck %s + +// Spec: +// Purpose: verify conv2d tiling and lowering through Tile -> Buckyball -> LLVM +// Input: [1, 4, 4, 1] (N=1, H=4, W=4, C=1) +// Filter: [3, 3, 1, 1] (KH=3, KW=3, C=1, OC=1) +// Output: [1, 2, 2, 1] (N=1, OH=2, OW=2, OC=1) + +// Input: 1x4x4x1 +memref.global "private" @conv_input : memref<1x4x4x1xi8> = dense<[[ + [[1], [2], [3], [4]], + [[5], [6], [7], [8]], + [[9], [10], [11], [12]], + [[13], [14], [15], [16]] +]]> + +// Filter: 3x3x1x1 +memref.global "private" @conv_filter : memref<3x3x1x1xi8> = dense<[[ + [[1]], [[0]], [[0]], + [[0]], [[1]], [[0]], + [[0]], [[0]], [[1]] +]]> + +func.func @main() -> i8 { + %0 = arith.constant 0 : i8 + + %input = memref.get_global @conv_input : memref<1x4x4x1xi8> + %filter = memref.get_global @conv_filter : memref<3x3x1x1xi8> + %output = memref.alloc() : memref<1x2x2x1xi8> + + // Print input + // buckyball.print %input : memref<1x4x4x1xi8> + + // CHECK: tile_conv2d + tile.tile_conv2d %input %filter %output : memref<1x4x4x1xi8> memref<3x3x1x1xi8> memref<1x2x2x1xi8> + + memref.dealloc %output : memref<1x2x2x1xi8> + return %0 : i8 +} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir index c5810df4..8e1513d7 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir @@ -19,26 +19,25 @@ func.func @main() -> i8 { %0 = arith.constant 0 : i8 // 16-byte aligned scratchpad address %spadAddr16 = arith.constant 16 : i64 - // 32-byte aligned scratchpad address - %spadAddr32 = arith.constant 32 : i64 + %stride = arith.constant 16 : i64 %arrayA = memref.get_global @input_matrix_aligned : memref<4x16xi8> %arrayB = memref.alloc() {alignment = 16} : memref<4x16xi8> // Print input matrix // Print target matrix before move [CHECK1] - buckyball.print %arrayA : memref<4x16xi8> - buckyball.print %arrayB : memref<4x16xi8> + buckyball.bb_print_memref %arrayA : memref<4x16xi8> + buckyball.bb_print_memref %arrayB : memref<4x16xi8> // Use mvin to move data from 16-byte aligned address to scratchpad // CHECK: mvin // Use mvout to move data from scratchpad to 16-byte aligned target address - buckyball.bb_mvin %arrayA %spadAddr16 : memref<4x16xi8> i64 + buckyball.bb_mvin %arrayA %spadAddr16 %stride : memref<4x16xi8> i64 i64 // CHECK: mvout buckyball.bb_mvout %arrayB %spadAddr16 : memref<4x16xi8> i64 // Print output matrix after move [CHECK2] - buckyball.print %arrayB : memref<4x16xi8> + buckyball.bb_print_memref %arrayB : memref<4x16xi8> // Release allocated memory memref.dealloc %arrayB : memref<4x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir index 81e847ca..ee249823 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir @@ -21,42 +21,43 @@ func.func @main() -> i8 { %spadAddr1 = arith.constant 10 : i64 // Scratchpad address 2 %spadAddr2 = arith.constant 50 : i64 + %stride = arith.constant 16 : i64 %arrayA = memref.get_global @input_matrix_a : memref<2x16xi8> %arrayB = memref.get_global @input_matrix_b : memref<2x16xi8> %arrayTemp = memref.alloc() {alignment = 16} : memref<2x16xi8> // Print input matrices A and B - buckyball.print %arrayA : memref<2x16xi8> - buckyball.print %arrayB : memref<2x16xi8> + buckyball.bb_print_memref %arrayA : memref<2x16xi8> + buckyball.bb_print_memref %arrayB : memref<2x16xi8> // Print temporary matrix before move [CHECK1] - buckyball.print %arrayTemp : memref<2x16xi8> + buckyball.bb_print_memref %arrayTemp : memref<2x16xi8> // Fast alternating mvin/mvout operation sequence // Step 1: A -> scratchpad 1 // CHECK: mvin // Step 2: scratchpad 1 -> temp - buckyball.bb_mvin %arrayA %spadAddr1 : memref<2x16xi8> i64 + buckyball.bb_mvin %arrayA %spadAddr1 %stride : memref<2x16xi8> i64 i64 // CHECK: mvout buckyball.bb_mvout %arrayTemp %spadAddr1 : memref<2x16xi8> i64 // Step 3: B -> scratchpad 2 // CHECK: mvin // Step 4: scratchpad 2 -> A - buckyball.bb_mvin %arrayB %spadAddr2 : memref<2x16xi8> i64 + buckyball.bb_mvin %arrayB %spadAddr2 %stride : memref<2x16xi8> i64 i64 // CHECK: mvout buckyball.bb_mvout %arrayA %spadAddr2 : memref<2x16xi8> i64 // Step 5: temp -> scratchpad 1 // CHECK: mvin // Step 6: scratchpad 1 -> B - buckyball.bb_mvin %arrayTemp %spadAddr1 : memref<2x16xi8> i64 + buckyball.bb_mvin %arrayTemp %spadAddr1 %stride : memref<2x16xi8> i64 i64 // CHECK: mvout buckyball.bb_mvout %arrayB %spadAddr1 : memref<2x16xi8> i64 // Print swapped matrices [CHECK2] - buckyball.print %arrayA : memref<2x16xi8> - buckyball.print %arrayB : memref<2x16xi8> + buckyball.bb_print_memref %arrayA : memref<2x16xi8> + buckyball.bb_print_memref %arrayB : memref<2x16xi8> // Release allocated memory memref.dealloc %arrayTemp : memref<2x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir index 7a58e6c8..98da83b7 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir @@ -19,6 +19,7 @@ func.func @main() -> i8 { %c127 = arith.constant 127 : index // Scratchpad start address %spadAddr = arith.constant 0 : i64 + %stride = arith.constant 16 : i64 // ========== Row count configuration area (only modify here) ========== // Total number of rows @@ -51,19 +52,19 @@ func.func @main() -> i8 { // Print first two rows and last two rows of input matrix %arrayA_head = memref.subview %arrayA[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> %arrayA_tail = memref.subview %arrayA[1021, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1], offset: 16336>> - buckyball.print %arrayA_head : memref<2x16xi8, strided<[16, 1]>> - buckyball.print %arrayA_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> + buckyball.bb_print_memref %arrayA_head : memref<2x16xi8, strided<[16, 1]>> + buckyball.bb_print_memref %arrayA_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> // Print first two rows and last two rows of target matrix before move [CHECK1] %arrayB_head = memref.subview %arrayB[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> %arrayB_tail = memref.subview %arrayB[1021, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1], offset: 16336>> - buckyball.print %arrayB_head : memref<2x16xi8, strided<[16, 1]>> - buckyball.print %arrayB_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> + buckyball.bb_print_memref %arrayB_head : memref<2x16xi8, strided<[16, 1]>> + buckyball.bb_print_memref %arrayB_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> // Execute long read/write operations // Step 1: long read - read large amount of data from memory into scratchpad // CHECK: mvin - buckyball.bb_mvin %arrayA %spadAddr : memref<1023x16xi8> i64 + buckyball.bb_mvin %arrayA %spadAddr %stride : memref<1023x16xi8> i64 i64 // Step 2: long write - write large amount of data from scratchpad to memory // CHECK: mvout @@ -72,8 +73,8 @@ func.func @main() -> i8 { // Print first two rows and last two rows of output matrix after move [CHECK2] %arrayB_head_after = memref.subview %arrayB[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> %arrayB_tail_after = memref.subview %arrayB[1021, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1], offset: 16336>> - buckyball.print %arrayB_head_after : memref<2x16xi8, strided<[16, 1]>> - buckyball.print %arrayB_tail_after : memref<2x16xi8, strided<[16, 1], offset: 16336>> + buckyball.bb_print_memref %arrayB_head_after : memref<2x16xi8, strided<[16, 1]>> + buckyball.bb_print_memref %arrayB_tail_after : memref<2x16xi8, strided<[16, 1], offset: 16336>> // Release allocated memory memref.dealloc %arrayA : memref<1023x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir b/bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir new file mode 100644 index 00000000..940f48bb --- /dev/null +++ b/bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir @@ -0,0 +1,46 @@ +// Test for bb_im2col: extract 3x3 patches from 4x16 input +// RUN: buddy-opt %s \ +// RUN: -lower-buckyball | \ +// RUN: FileCheck %s + +// Spec: +// Purpose: verify correctness of im2col operation +// 1. Load input matrix (4x16) +// 2. Im2col with 3x3 kernel extracts patches into output matrix +// 3. Print output matrix to verify patch extraction + +// Input: 4x16 matrix +memref.global "private" @input : memref<4x16xi8> = dense<[ + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], + [17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32], + [33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48], + [49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64]]> + +func.func @main() -> i8 { + %0 = arith.constant 0 : i8 + + %arrayIn = memref.get_global @input : memref<4x16xi8> + // Output for im2col: 2 output rows, 3*3*1=9 patch cols (padded to 16) + %arrayOut = memref.alloc() : memref<2x16xi8> + + // Im2col parameters + %kRow = arith.constant 3 : i64 + %kCol = arith.constant 3 : i64 + %inRow = arith.constant 4 : i64 + %inCol = arith.constant 16 : i64 + %startRow = arith.constant 0 : i64 + %startCol = arith.constant 0 : i64 + + // Print input + buckyball.bb_print_memref %arrayIn : memref<4x16xi8> + + // CHECK: im2col + buckyball.bb_im2col %arrayIn %arrayOut %kRow %kCol %inRow %inCol %startRow %startCol + : memref<4x16xi8> memref<2x16xi8> + + // Print output + buckyball.bb_print_memref %arrayOut : memref<2x16xi8> + + memref.dealloc %arrayOut : memref<2x16xi8> + return %0 : i8 +} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir b/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir index 5e246f7a..ee72220a 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir @@ -1,5 +1,5 @@ -// Test for bb_mul_warp16: 16x16 * 16x16 = 16x16 matrix multiplication -// RUN: %run +// Test for bb_matmul: 16x16 * 16x16 = 16x16 matrix multiplication +// Uses bb_matmul Op which lowers to mvin + mul_warp16 + mvout // Matrix A: 16x16 (identity-like matrix for easier verification) memref.global "private" @matrix_a : memref<16x16xi8> = dense<[[1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], @@ -37,40 +37,18 @@ memref.global "private" @matrix_b : memref<16x16xi8> = dense<[[1, 2, 3, 4, 5, 6, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]]> -memref.global "private" @val : memref<1x1xi8> = dense<[[1]]> - func.func @main() -> i8 { %0 = arith.constant 0 : i8 - // Scratchpad addresses - %spadAddr_a = arith.constant 0: i64 // Matrix A (16x16) at spad address 0-15 - %spadAddr_b = arith.constant 4096 : i64 // Matrix B (16x16) at spad address 16-31 - %spadAddr_c = arith.constant 8192 : i64 // Result C (16x16) at spad address 32-47 - // Get global matrices %arrayA = memref.get_global @matrix_a : memref<16x16xi8> %arrayB = memref.get_global @matrix_b : memref<16x16xi8> %arrayC = memref.alloc() : memref<16x16xi8> - %val = memref.get_global @val : memref<1x1xi8> - // Initialize result matrix C to zero - // MVIN: Move matrices to scratchpad - buckyball.bb_mvin %arrayA %spadAddr_a : memref<16x16xi8> i64 - buckyball.bb_mvin %arrayB %spadAddr_b : memref<16x16xi8> i64 - buckyball.print %val : memref<1x1xi8> - // WARP16: Matrix multiplication (16x16 * 16x16) - // aSpAddr = 0 (Matrix A address) - // bSpAddr = 20 (Matrix B address) - // cSpAddr = 40 (Result C address) - // nLen = 16 (matrix dimension) - %nLen = arith.constant 16 : i64 - buckyball.bb_mul_warp16 %spadAddr_a %spadAddr_b %spadAddr_c %nLen : i64 i64 i64 i64 - // MVOUT: Move result from scratchpad to memory - buckyball.print %val : memref<1x1xi8> - buckyball.bb_mvout %arrayC %spadAddr_c : memref<16x16xi8> i64 + // bb_matmul: lowers to mvin A + mvin B + mul_warp16 + mvout C + buckyball.bb_matmul %arrayA %arrayB %arrayC : memref<16x16xi8> memref<16x16xi8> memref<16x16xi8> // Print result matrix - // Expected: Since A is identity matrix, result should be same as matrix B - buckyball.print %arrayC : memref<16x16xi8> + buckyball.bb_print_memref %arrayC : memref<16x16xi8> memref.dealloc %arrayC : memref<16x16xi8> return %0 : i8 diff --git a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir index aaec6cb9..a627a556 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir @@ -16,37 +16,21 @@ memref.global "private" @input_matrix : memref<4x16xi8> = dense<[[1, 2, 3, 4, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]]> -// // === Check if current hartid is 5, otherwise exit === func.func @main() -> i8 { -// %hartid = llvm.inline_asm "csrr $0, mhartid", "=r" : () -> i32 -// // buckyball.print_scalar %hartid : i32 - -// %target_hart = arith.constant 5 : i32 -// %is_correct_hart = arith.cmpi eq, %hartid, %target_hart : i32 -// cf.cond_br %is_correct_hart, ^continue, ^exit - -// ^exit: -// // If not hart 5, return 0 -// %error = arith.constant -1 : i8 -// return %error : i8 - -// ^continue: - buckyball.multicore - // %hartid = llvm.inline_asm "csrr $0, mhartid", "=r" : () -> i32 - // buckyball.print_scalar %hartid : i32 // === Main program === %0 = arith.constant 0 : i8 %spadAddr = arith.constant 1040 : i64 + %stride = arith.constant 16 : i64 %arrayA = memref.get_global @input_matrix : memref<4x16xi8> %arrayB = memref.alloc() : memref<4x16xi8> // Use mvin to move data from memory to scratchpad // CHECK: mvin - buckyball.bb_mvin %arrayA %spadAddr : memref<4x16xi8> i64 + buckyball.bb_mvin %arrayA %spadAddr %stride : memref<4x16xi8> i64 i64 // Use mvout to move data from scratchpad back to output memory // CHECK: mvout buckyball.bb_mvout %arrayB %spadAddr : memref<4x16xi8> i64 // Print moved output matrix - buckyball.print %arrayB : memref<4x16xi8> + buckyball.bb_print_memref %arrayB : memref<4x16xi8> // Release allocated memory memref.dealloc %arrayB : memref<4x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir b/bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir new file mode 100644 index 00000000..81d81b7c --- /dev/null +++ b/bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir @@ -0,0 +1,51 @@ +// Test for bb_quant and bb_dequant: quantize FP32 to INT8 then dequantize back +// RUN: buddy-opt %s \ +// RUN: -lower-buckyball | \ +// RUN: FileCheck %s + +// Spec: +// Purpose: verify quant -> matmul -> dequant pipeline +// 1. Quantize FP32 input to INT8 using scale factor +// 2. Perform matmul on quantized data +// 3. Dequantize result back to FP32 + +// FP32 input matrix A: 16x16 +memref.global "private" @fp_input_a : memref<16x16xf32> = dense<1.0> +// FP32 input matrix B: 16x16 +memref.global "private" @fp_input_b : memref<16x16xf32> = dense<2.0> + +func.func @main() -> i8 { + %0 = arith.constant 0 : i8 + %scale = arith.constant 0.1 : f32 + + // Load FP32 inputs + %fpA = memref.get_global @fp_input_a : memref<16x16xf32> + %fpB = memref.get_global @fp_input_b : memref<16x16xf32> + + // Allocate INT8 buffers for quantized data + %qA = memref.alloc() : memref<16x16xi8> + %qB = memref.alloc() : memref<16x16xi8> + + // Quantize A and B + // CHECK: quant + buckyball.bb_quant %fpA %qA %scale : memref<16x16xf32> memref<16x16xi8> f32 + buckyball.bb_quant %fpB %qB %scale : memref<16x16xf32> memref<16x16xi8> f32 + + // MatMul on quantized data + %qC = memref.alloc() : memref<16x16xi8> + buckyball.bb_matmul %qA %qB %qC : memref<16x16xi8> memref<16x16xi8> memref<16x16xi8> + + // Dequantize result + %fpC = memref.alloc() : memref<16x16xf32> + // CHECK: dequant + buckyball.bb_dequant %qC %fpC %scale : memref<16x16xi8> memref<16x16xf32> f32 + + // Print dequantized result + buckyball.bb_print_memref %fpC : memref<16x16xf32> + + memref.dealloc %qA : memref<16x16xi8> + memref.dealloc %qB : memref<16x16xi8> + memref.dealloc %qC : memref<16x16xi8> + memref.dealloc %fpC : memref<16x16xf32> + return %0 : i8 +} diff --git a/compiler b/compiler index e66f53ad..d2fdc68e 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit e66f53ad6c6ff125d644f14c89627b180dd3fd83 +Subproject commit d2fdc68efa7111641309c3120fdf1fd3e832ec2b From ebe4f0c85158dfa4d77c7eff11fb6b9d492e9f98 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 8 Mar 2026 02:10:36 +0800 Subject: [PATCH 149/238] [arch] fix: fix bugs in TLB [arch] feat: add GemminiBall and GemminiExCtrl modules with associated configurations and tests [bb-test] feat: add tlb test --- .../scala/examples/toy/balldomain/DISA.scala | 7 + .../toy/balldomain/DomainDecoder.scala | 44 +- .../toy/balldomain/bbus/busRegister.scala | 2 + .../framework/balldomain/configs/default.json | 5 +- .../prototype/gemmini/GemminiBall.scala | 57 +++ .../prototype/gemmini/GemminiExCtrl.scala | 476 ++++++++++++++++++ .../prototype/gemmini/LICENSE.gemmini | 24 + .../gemmini/configs/GemminiBallParam.scala | 30 ++ .../prototype/gemmini/configs/default.json | 10 + .../scala/framework/core/bbtile/BBTile.scala | 3 + .../core/bbtile/BuckyballAccelerator.scala | 4 +- .../outside_channel/dma/StreamReader.scala | 4 +- .../outside_channel/dma/StreamWriter.scala | 6 +- .../frontend/outside_channel/tlb/TLB.scala | 38 +- .../outside_channel/tlb/TLBCluster.scala | 21 +- .../outside_channel/tlb/TLBEntry.scala | 83 ++- bb-tests/sardine/tests/test_ctest.py | 4 + .../workloads/src/CTest/toy/CMakeLists.txt | 2 + bb-tests/workloads/src/CTest/toy/tlb_test.c | 217 ++++++++ .../workloads/src/OpTest/tile/CMakeLists.txt | 2 + .../workloads/src/OpTest/toy/CMakeLists.txt | 2 + .../workloads/src/OpTest/toy/bb_dma1.mlir | 12 +- .../workloads/src/OpTest/toy/bb_dma2.mlir | 35 +- .../workloads/src/OpTest/toy/bb_dma3.mlir | 13 +- .../src/OpTest/toy/bb_mvin_mvout.mlir | 22 +- compiler | 2 +- 26 files changed, 1043 insertions(+), 82 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/LICENSE.gemmini create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json create mode 100644 bb-tests/workloads/src/CTest/toy/tlb_test.c diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index cabccf18..6ebc8144 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -11,4 +11,11 @@ object DISA { val SYSTOLIC = BitPat("b0100111") // 39 val QUANT = BitPat("b0101000") // 40 val DEQUANT = BitPat("b0101001") // 41 + + // Gemmini systolic array instructions + val GEMMINI_CONFIG = BitPat("b0101010") // 42 + val GEMMINI_PRELOAD = BitPat("b0101011") // 43 + val GEMMINI_COMPUTE_PRELOADED = BitPat("b0101100") // 44 + val GEMMINI_COMPUTE_ACCUMULATED = BitPat("b0101101") // 45 + val GEMMINI_FLUSH = BitPat("b0101110") // 46 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 213e8399..244d3790 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -74,13 +74,43 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { // New unified encoding: wr_bank is always at rs1[23:16] // iter/special shifted in rs2 since wr_bank no longer occupies rs2[7:0] // op1 op2 wr op1s op2s op1_bank op2_bank wr_bank iter bid special - MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 0.U, rs2(63, 10)), - RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 1.U, rs2(63, 10)), - TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 2.U, rs2(63, 10)), - IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)), - SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 4.U, rs2(63, 10)), - QUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 5.U, rs2(63, 10)), - DEQUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 6.U, rs2(63, 10)) + MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 0.U, rs2(63, 10)), + RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 1.U, rs2(63, 10)), + TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 2.U, rs2(63, 10)), + IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)), + SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 4.U, rs2(63, 10)), + QUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 5.U, rs2(63, 10)), + DEQUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 6.U, rs2(63, 10)), + // Gemmini systolic array instructions — all share bid=7, sub-command in special[3:0] + GEMMINI_CONFIG -> List(N, N, N, N, N, DADDR, DADDR, DADDR, DITER, 7.U, Cat(0.U(36.W), 0.U(4.W))), + GEMMINI_PRELOAD -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 7.U, Cat(rs2(63, 10), 1.U(4.W))), + GEMMINI_COMPUTE_PRELOADED -> List( + Y, + Y, + Y, + Y, + Y, + rs1(7, 0), + rs1(15, 8), + rs1(23, 16), + rs2(9, 0), + 7.U, + Cat(rs2(63, 10), 2.U(4.W)) + ), + GEMMINI_COMPUTE_ACCUMULATED -> List( + Y, + Y, + Y, + Y, + Y, + rs1(7, 0), + rs1(15, 8), + rs1(23, 16), + rs2(9, 0), + 7.U, + Cat(rs2(63, 10), 3.U(4.W)) + ), + GEMMINI_FLUSH -> List(N, N, N, N, N, DADDR, DADDR, DADDR, DITER, 7.U, Cat(0.U(36.W), 4.U(4.W))) ) ) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 775cc8bf..20a7fa8e 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -13,6 +13,7 @@ import framework.balldomain.prototype.im2col.Im2colBall import framework.balldomain.prototype.systolicarray.SystolicArrayBall import framework.balldomain.prototype.quant.QuantBall import framework.balldomain.prototype.dequant.DequantBall +import framework.balldomain.prototype.gemmini.GemminiBall /** * BBusModule - Ball bus module that directly extends BBus @@ -30,6 +31,7 @@ class BBusModule(b: GlobalConfig) case "SystolicArrayBall" => () => new SystolicArrayBall(b) case "QuantBall" => () => new QuantBall(b) case "DequantBall" => () => new DequantBall(b) + case "GemminiBall" => () => new GemminiBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index 51f963b7..f0d7fafa 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,5 +1,5 @@ { - "ballNum": 7, + "ballNum": 8, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, @@ -7,6 +7,7 @@ {"ballId": 3, "ballName": "Im2colBall", "inBW": 1, "outBW": 1}, {"ballId": 4, "ballName": "SystolicArrayBall", "inBW": 2, "outBW": 4}, {"ballId": 5, "ballName": "QuantBall", "inBW": 1, "outBW": 1}, - {"ballId": 6, "ballName": "DequantBall", "inBW": 1, "outBW": 1} + {"ballId": 6, "ballName": "DequantBall", "inBW": 1, "outBW": 1}, + {"ballId": 7, "ballName": "GemminiBall", "inBW": 2, "outBW": 4} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala new file mode 100644 index 00000000..6c3ece31 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala @@ -0,0 +1,57 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.top.GlobalConfig + +@instantiable +class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBallStatus { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "GemminiBall") + .getOrElse(throw new IllegalArgumentException("GemminiBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + def status: BallStatus = io.status + + val exCtrl: Instance[GemminiExCtrl] = Instantiate(new GemminiExCtrl(b)) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + // Command interface + exCtrl.io.cmdReq <> io.cmdReq + exCtrl.io.cmdResp <> io.cmdResp + + // Bank read ports + for (i <- 0 until inBW) { + io.bankRead(i).io.req <> exCtrl.io.bankReadReq(i) + exCtrl.io.bankReadResp(i) <> io.bankRead(i).io.resp + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + io.bankRead(i).group_id := 0.U + } + io.bankRead(0).bank_id := exCtrl.io.op1_bank_o + if (inBW > 1) { + io.bankRead(1).bank_id := exCtrl.io.op2_bank_o + } + + // Bank write ports + for (i <- 0 until outBW) { + io.bankWrite(i).io <> exCtrl.io.bankWrite(i) + io.bankWrite(i).bank_id := exCtrl.io.wr_bank_o + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).group_id := i.U + } + + io.status <> exCtrl.io.status +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala new file mode 100644 index 00000000..5ca61fff --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala @@ -0,0 +1,476 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp, SramWriteIO} +import framework.top.GlobalConfig +import framework.balldomain.prototype.gemmini.configs.GemminiBallParam +import gemmini._ +import gemmini.Util._ + +/** Minimal tag for MeshWithDelays that satisfies TagQueueTag */ +class SimpleTag extends Bundle with TagQueueTag { + val rob = UInt(8.W) + override def make_this_garbage(dummy: Int = 0): Unit = + rob := 0.U +} + +/** Sub-command encoding within the special field */ +object GemminiSubCmd { + val CONFIG = 0.U(4.W) + val PRELOAD = 1.U(4.W) + val COMPUTE_PRELOADED = 2.U(4.W) + val COMPUTE_ACCUMULATED = 3.U(4.W) + val FLUSH = 4.U(4.W) +} + +/** + * GemminiExCtrl — Execute controller adapter for MeshWithDelays. + * + * Receives BallRsIssue commands (config / preload / compute / flush), + * drives gemmini.MeshWithDelays, reads data from SRAM banks, and + * writes results back to SRAM banks. + */ +@instantiable +class GemminiExCtrl(val b: GlobalConfig) extends Module { + val config = GemminiBallParam() + val DIM = config.blockSize // e.g., 16 + + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "GemminiBall") + .getOrElse(throw new IllegalArgumentException("GemminiBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + val inputType = SInt(config.inputWidth.W) + val accType = SInt(config.accWidth.W) + val outputType = SInt(config.accWidth.W) + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) + val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) + val op1_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val op2_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val wr_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val status = new BallStatus + }) + + // ========================================================================= + // Instantiate Gemmini's MeshWithDelays (the real systolic array) + // ========================================================================= + val mesh = Module(new MeshWithDelays( + inputType = inputType, + outputType = outputType, + accType = accType, + tagType = new SimpleTag, + df = Dataflow.BOTH, + tree_reduction = false, + tile_latency = config.tileLatency, + output_delay = config.outputDelay, + tileRows = config.tileRows, + tileColumns = config.tileColumns, + meshRows = config.meshRows, + meshColumns = config.meshColumns, + leftBanks = 1, + upBanks = 1, + n_simultaneous_matmuls = 5 + )) + + // ========================================================================= + // Configuration registers (updated by CONFIG sub-command) + // ========================================================================= + val cfg_dataflow = RegInit(0.U(1.W)) // 0=OS, 1=WS + val cfg_activation = RegInit(0.U(2.W)) // 0=none, 1=relu + val cfg_a_transpose = RegInit(false.B) + val cfg_b_transpose = RegInit(false.B) + val cfg_in_shift = RegInit(0.U(log2Up(config.accWidth).W)) + + // ========================================================================= + // State machine + // ========================================================================= + val sIdle :: sPreloadReq :: sPreloadRead :: sPreloadFeed :: sComputeReq :: sComputeRead :: sComputeFeed :: sFlush :: sDrain :: sStore :: sCommit :: Nil = + Enum(11) + val state = RegInit(sIdle) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + + // Saved rs1/rs2 from the command (latched at sIdle when cmdReq fires) + val saved_rs1 = Reg(UInt(64.W)) + val saved_rs2 = Reg(UInt(64.W)) + val saved_sub_cmd = Reg(UInt(4.W)) + + // Bank addressing + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank + io.wr_bank_o := wr_bank + + // Iteration counters + val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) + val req_sent = RegInit(false.B) // whether mesh.io.req has fired for this matmul + + // Sub-command from special field (live wire, only valid when cmdReq is valid) + val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) + + // Read response queues + val rdQueue0 = Module(new Queue(new SramReadResp(b), entries = DIM)) + val rdQueue1 = Module(new Queue(new SramReadResp(b), entries = DIM)) + rdQueue0.io.enq <> io.bankReadResp(0) + rdQueue1.io.enq <> io.bankReadResp(1) + + // Output buffer: collect mesh responses row by row + val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, outputType)))) + val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) + + // Per-port write completion tracking for sStore + val port_written = RegInit(VecInit(Seq.fill(outBW)(false.B))) + + // ========================================================================= + // Defaults + // ========================================================================= + io.cmdReq.ready := state === sIdle + + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + for (i <- 0 until inBW) { + io.bankReadReq(i).valid := false.B + io.bankReadReq(i).bits.addr := 0.U + } + + rdQueue0.io.deq.ready := false.B + rdQueue1.io.deq.ready := false.B + + mesh.io.a.valid := false.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := false.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := false.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + mesh.io.req.valid := false.B + mesh.io.req.bits := 0.U.asTypeOf(mesh.io.req.bits) + + io.bankWrite.foreach { bw => + bw.req.valid := false.B + bw.req.bits.addr := 0.U + bw.req.bits.data := 0.U + bw.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + bw.req.bits.wmode := true.B + bw.resp.ready := true.B + } + + // ========================================================================= + // State Machine + // ========================================================================= + switch(state) { + + // ----------------------------------------------------------------------- + // IDLE: accept new command, latch rs1/rs2/sub_cmd + // ----------------------------------------------------------------------- + is(sIdle) { + io.cmdReq.ready := true.B + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op2_bank := io.cmdReq.bits.cmd.op2_bank + wr_bank := io.cmdReq.bits.cmd.wr_bank + saved_rs1 := io.cmdReq.bits.cmd.rs1 + saved_rs2 := io.cmdReq.bits.cmd.rs2 + saved_sub_cmd := sub_cmd + total_rows := Mux(io.cmdReq.bits.cmd.iter === 0.U, DIM.U, io.cmdReq.bits.cmd.iter) + + when(sub_cmd === GemminiSubCmd.CONFIG) { + // CONFIG: decode and apply immediately from live wires (still valid this cycle) + cfg_dataflow := io.cmdReq.bits.cmd.rs1(2) + cfg_activation := io.cmdReq.bits.cmd.rs1(4, 3) + cfg_a_transpose := io.cmdReq.bits.cmd.rs1(8) + cfg_b_transpose := io.cmdReq.bits.cmd.rs1(9) + cfg_in_shift := io.cmdReq.bits.cmd.rs2(log2Up(config.accWidth) - 1, 0) + // Commit immediately + io.cmdResp.valid := true.B + // Stay in sIdle if resp fires, else we need a config state + // Since cmdReq.fire and cmdResp can both happen in same cycle: + state := sCommit + }.elsewhen(sub_cmd === GemminiSubCmd.PRELOAD) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + req_sent := false.B + state := sPreloadRead + }.elsewhen(sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + outBufRows := 0.U + req_sent := false.B + state := sComputeRead + }.elsewhen(sub_cmd === GemminiSubCmd.FLUSH) { + state := sFlush + } + } + } + + // ----------------------------------------------------------------------- + // PRELOAD_READ: read D/B matrix from SRAM bank into rdQueue + // Address starts from 0 (beginning of the bank allocation) + // ----------------------------------------------------------------------- + is(sPreloadRead) { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := read_row_cnt + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + } + + // ----------------------------------------------------------------------- + // PRELOAD_FEED: send req to mesh, then feed D/B data row by row + // For OS mode: preload bias/D into mesh via d input, a=0, b=0 + // For WS mode: preload weights via b input, a=0, d=0 + // ----------------------------------------------------------------------- + is(sPreloadFeed) { + // Step 1: fire mesh.io.req (once) + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := ~cfg_dataflow // OS: propagate=1, WS: propagate=0 for preload + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := cfg_a_transpose + mesh.io.req.bits.bd_transpose := cfg_b_transpose + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := rob_id_reg + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + // Step 2: feed data rows (only after req has fired) + when(req_sent && feed_row_cnt < total_rows) { + when(rdQueue0.io.deq.valid) { + val row_data = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + + // a = 0 always for preload + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS: preload accumulator via d input + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + }.otherwise { + // WS: preload weights via b input + mesh.io.b.valid := true.B + mesh.io.b.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + } + + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := true.B + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + // Step 3: all rows fed → commit + when(req_sent && feed_row_cnt >= total_rows) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + + // ----------------------------------------------------------------------- + // COMPUTE_READ: read A (port 0) and B/D (port 1) from SRAM banks + // Both start from address 0 + // ----------------------------------------------------------------------- + is(sComputeRead) { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := read_row_cnt + io.bankReadReq(1).valid := true.B + io.bankReadReq(1).bits.addr := read_row_cnt + + when(io.bankReadReq(0).ready && io.bankReadReq(1).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sComputeFeed + } + } + + // ----------------------------------------------------------------------- + // COMPUTE_FEED: send req to mesh, then feed A and B/D row by row + // Collect mesh responses in parallel + // ----------------------------------------------------------------------- + is(sComputeFeed) { + // Always collect mesh output when valid + when(mesh.io.resp.valid) { + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows + 1.U + } + + // Step 1: fire mesh.io.req (once) + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := cfg_dataflow // OS: propagate=0, WS: propagate=1 for compute + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := cfg_a_transpose + mesh.io.req.bits.bd_transpose := cfg_b_transpose + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := rob_id_reg + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + // Step 2: feed data rows (only after req has fired) + when(req_sent && feed_row_cnt < total_rows) { + when(rdQueue0.io.deq.valid && rdQueue1.io.deq.valid) { + val a_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val bd_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + + mesh.io.a.valid := true.B + mesh.io.a.bits := VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) + + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS: b carries multiply operand, d = 0 (accumulator already preloaded) + mesh.io.b.valid := true.B + mesh.io.b.bits := VecInit(bd_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + }.otherwise { + // WS: d carries input activations, b = 0 + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := VecInit(bd_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + } + + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := true.B + rdQueue1.io.deq.ready := true.B + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + // Step 3: all rows fed → wait for all mesh responses + when(req_sent && feed_row_cnt >= total_rows) { + state := sDrain + } + } + + // ----------------------------------------------------------------------- + // DRAIN: wait for remaining mesh responses + // ----------------------------------------------------------------------- + is(sDrain) { + when(mesh.io.resp.valid) { + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows + 1.U + } + when(outBufRows >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + } + + // ----------------------------------------------------------------------- + // STORE: write results back to SRAM bank + // Each row: DIM elements × accWidth bits = 512 bits + // bankWidth = 128 bits, outBW = 4 write ports → 4×128 = 512 bits per cycle + // Use per-port written flags to handle non-simultaneous ready signals + // ----------------------------------------------------------------------- + is(sStore) { + when(store_row_cnt < total_rows) { + val row = outBuf(store_row_cnt) + val flat_row = VecInit(row.flatten) // Vec of DIM SInt(accWidth) + val row_bits = Cat(flat_row.reverse.map(_.asUInt)) // DIM * accWidth total bits + + val bitsPerPort = b.memDomain.bankWidth + + for (i <- 0 until outBW) { + when(!port_written(i)) { + val slice = row_bits((i + 1) * bitsPerPort - 1, i * bitsPerPort) + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := store_row_cnt + io.bankWrite(i).req.bits.data := slice + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + io.bankWrite(i).req.bits.wmode := true.B + when(io.bankWrite(i).req.ready) { + port_written(i) := true.B + } + } + } + + // All ports done for this row → advance to next row + when(port_written.asUInt.andR) { + store_row_cnt := store_row_cnt + 1.U + port_written.foreach(_ := false.B) + } + }.otherwise { + state := sCommit + } + } + + // ----------------------------------------------------------------------- + // COMMIT: send completion response + // ----------------------------------------------------------------------- + is(sCommit) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + + // ----------------------------------------------------------------------- + // FLUSH: send flush to mesh, commit + // ----------------------------------------------------------------------- + is(sFlush) { + mesh.io.req.valid := true.B + mesh.io.req.bits.flush := 2.U + mesh.io.req.bits.total_rows := DIM.U + mesh.io.req.bits.tag.rob := rob_id_reg + + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + + when(mesh.io.req.ready) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + } + + // ========================================================================= + // Status + // ========================================================================= + io.status.idle := state === sIdle + io.status.running := state =/= sIdle +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LICENSE.gemmini b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LICENSE.gemmini new file mode 100644 index 00000000..17824de7 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LICENSE.gemmini @@ -0,0 +1,24 @@ +Copyright (c) 2018-2019, The Regents of the University of California +(Regents). All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala new file mode 100644 index 00000000..db5015c4 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala @@ -0,0 +1,30 @@ +package framework.balldomain.prototype.gemmini.configs + +import upickle.default._ + +case class GemminiBallParam( + meshRows: Int, + meshColumns: Int, + tileRows: Int, + tileColumns: Int, + inputWidth: Int, + accWidth: Int, + tileLatency: Int, + outputDelay: Int) { + + val totalRows: Int = meshRows * tileRows + val totalColumns: Int = meshColumns * tileColumns + val blockSize: Int = totalRows // == totalColumns (must be square) +} + +object GemminiBallParam { + implicit val rw: ReadWriter[GemminiBallParam] = macroRW + + def apply(): GemminiBallParam = { + val jsonStr = scala.io.Source.fromFile( + "src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json" + ).mkString + read[GemminiBallParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json new file mode 100644 index 00000000..4299a30f --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json @@ -0,0 +1,10 @@ +{ + "meshRows": 4, + "meshColumns": 4, + "tileRows": 4, + "tileColumns": 4, + "inputWidth": 8, + "accWidth": 32, + "tileLatency": 0, + "outputDelay": 0 +} diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index 2d0bb664..13f1d3af 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -365,6 +365,9 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC buckyball.io.tlbExp(0).flush_skip := false.B buckyball.io.tlbExp(0).flush_retry := false.B + // CPU sfence → Buckyball TLB flush + buckyball.io.sfence := ptw.io.dpath.sfence.valid + // RoCC mem: Buckyball doesn't use the HellaCacheIO mem port, but the // DCache arbiter still expects a port for it (dcacheArbPorts counts BuildRoCC.size). // Route through SimpleHellaCacheIF with tied-off requestor side. diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index a4be212f..6046e376 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -39,6 +39,8 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module val ptw = Vec(1, new BBTLBPTWIO(b)) // TLB exception interface val tlbExp = Vec(1, new BBTLBExceptionIO) + // CPU sfence signal — flushes Buckyball's TLB + val sfence = Input(Bool()) // TileLink DMA bundles (from tile's diplomacy nodes) val tl_reader = new TLBundle(edge.bundle) @@ -115,7 +117,7 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module // --- TLB exception --- memDomain.io.tlbExp(0).flush_skip := false.B - memDomain.io.tlbExp(0).flush_retry := false.B + memDomain.io.tlbExp(0).flush_retry := io.sfence io.tlbExp(0) <> memDomain.io.tlbExp(0) // --- TileLink DMA --- diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index 3cbf60bc..d4df131e 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -66,7 +66,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := read_vaddr - io.tlb.req.bits.passthrough := true.B + io.tlb.req.bits.passthrough := false.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XRD io.tlb.req.bits.prv := 3.U @@ -74,7 +74,7 @@ class StreamReader(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.bits.status := reqReg.status io.tl.a.valid := - io.tlb.resp.valid && + io.tlb.resp.valid && !io.tlb.resp.bits.miss && !inflight && state =/= s_idle io.tl.a.bits := get diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala index b6c93c97..43580148 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamWriter.scala @@ -91,7 +91,7 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.req.valid := (state === s_tlb_req) io.tlb.req.bits := DontCare io.tlb.req.bits.vaddr := reqReg.vaddr - io.tlb.req.bits.passthrough := true.B + io.tlb.req.bits.passthrough := false.B io.tlb.req.bits.size := 0.U io.tlb.req.bits.cmd := M_XWR io.tlb.req.bits.prv := 3.U @@ -103,9 +103,9 @@ class StreamWriter(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tlb.resp.ready := (state === s_tlb_req) && io.tl.a.ready // ----------------------- - // TileLink A channel (only when tlb resp is present) + // TileLink A channel (only when tlb resp is present and NOT a miss) // ----------------------- - io.tl.a.valid := (state === s_tlb_req) && io.tlb.resp.valid + io.tl.a.valid := (state === s_tlb_req) && io.tlb.resp.valid && !io.tlb.resp.bits.miss io.tl.a.bits := putMsg io.tl.a.bits.address := io.tlb.resp.bits.paddr diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala index 5f72daf5..894d79cb 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLB.scala @@ -14,6 +14,7 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { val pgIdxBits = b.core.pgIdxBits val vpnBits = vaddrBits - pgIdxBits val ppnBits = paddrBits - pgIdxBits + val pgLevels = if (b.core.xLen == 32) 2 else 4 // Match Rocket PTW convention @public val io = IO(new Bundle { @@ -25,7 +26,7 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { }) // TLB entries storage - val tlbEntries = Reg(Vec(entries, new TLBEntry(vaddrBits, pgIdxBits, paddrBits))) + val tlbEntries = Reg(Vec(entries, new TLBEntry(vaddrBits, pgIdxBits, paddrBits, pgLevels = pgLevels))) val lru = Reg(Vec(entries, UInt(log2Ceil(entries).W))) // Simple LRU counter // State machine @@ -62,8 +63,8 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { // Find LRU entry for replacement val lruIdx = PriorityEncoder(lru.map(_ === 0.U)) - // VM enable check (simplified: check if VM is enabled via status) - val vm_enabled = true.B // Simplified: assume VM is always enabled for now + // VM enable check: mode != 0 means virtual memory is on (Sv39/Sv48/etc.) + val vm_enabled = io.ptw.ptbr.mode =/= 0.U val tlbMiss = vm_enabled && !io.req.bits.passthrough && !tlbHit @@ -99,7 +100,7 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { entryData.pf := io.ptw.resp.bits.pf entryData.ae_final := io.ptw.resp.bits.ae_final - tlbEntries(refill_idx).insert(refill_vpn, entryData) + tlbEntries(refill_idx).insert(refill_vpn, io.ptw.resp.bits.level, entryData) // Update LRU lru(refill_idx) := (entries - 1).U for (i <- 0 until entries) { @@ -123,17 +124,24 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { state := s_ready } - // Response generation - val hitEntry = Mux( + // Response generation — use superpage-aware ppn from the hit entry + val hitEntryData = Mux( tlbHit, tlbEntries(hitIdx).data, WireDefault(new TLBEntryData(paddrBits, pgIdxBits), 0.U.asTypeOf(new TLBEntryData(paddrBits, pgIdxBits))) ) + // For superpage entries, TLBEntry.ppn() replaces lower PPN bits with VPN bits + val hitPPN = Mux( + tlbHit, + tlbEntries(hitIdx).ppn(vpn), + 0.U(ppnBits.W) + ) + val paddr = Mux( io.req.bits.passthrough || !vm_enabled, io.req.bits.vaddr, - Cat(hitEntry.ppn, pgIdx) + Cat(hitPPN, pgIdx) ) io.resp.valid := io.req.valid && state === s_ready @@ -141,21 +149,21 @@ class TLB(val b: GlobalConfig, val lgMaxSize: Int) extends Module { io.resp.bits.paddr := paddr(paddrBits - 1, 0) io.resp.bits.gpa := 0.U io.resp.bits.gpa_is_pte := false.B - io.resp.bits.pf.ld := hitEntry.pf - io.resp.bits.pf.st := hitEntry.pf - io.resp.bits.pf.inst := hitEntry.pf + io.resp.bits.pf.ld := hitEntryData.pf + io.resp.bits.pf.st := hitEntryData.pf + io.resp.bits.pf.inst := hitEntryData.pf io.resp.bits.gf.ld := false.B io.resp.bits.gf.st := false.B io.resp.bits.gf.inst := false.B - io.resp.bits.ae.ld := hitEntry.ae_final - io.resp.bits.ae.st := hitEntry.ae_final - io.resp.bits.ae.inst := hitEntry.ae_final + io.resp.bits.ae.ld := hitEntryData.ae_final + io.resp.bits.ae.st := hitEntryData.ae_final + io.resp.bits.ae.inst := hitEntryData.ae_final io.resp.bits.ma.ld := false.B io.resp.bits.ma.st := false.B io.resp.bits.ma.inst := false.B - io.resp.bits.cacheable := hitEntry.cacheable + io.resp.bits.cacheable := hitEntryData.cacheable io.resp.bits.must_alloc := false.B - io.resp.bits.prefetchable := hitEntry.cacheable + io.resp.bits.prefetchable := hitEntryData.cacheable io.resp.bits.size := io.req.bits.size io.resp.bits.cmd := io.req.bits.cmd } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala index e4b7ba26..3832702a 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBCluster.scala @@ -72,6 +72,14 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo assert(!io.exp(0).flush_retry || !io.exp(0).flush_skip, "TLB: flushing with both retry and skip at same time") + // Track which client won the arbiter + val arbGranted = tlbArb.io.chosen + + // TLB resp.ready: only the winning client controls backpressure + tlb_io.resp.ready := MuxLookup(arbGranted, false.B)( + io.clients.zipWithIndex.map { case (client, i) => i.U -> client.resp.ready } + ) + io.clients.zipWithIndex.foreach { case (client, i) => val last_translated_valid = RegInit(false.B) @@ -98,13 +106,10 @@ class BBTLBCluster(val b: GlobalConfig)(implicit val edge: TLEdgeOut) extends Mo when(io.exp(0).flush()) { last_translated_valid := false.B } - client.resp.bits.miss := tlb_io.resp.bits.miss - when(client.req.valid || tlb.io.resp.valid) { - client.resp <> tlb_io.resp - }.otherwise { - client.resp.valid := false.B - client.resp.bits := DontCare - tlb_io.resp.ready := false.B - } + + // Response routing: only the winning client gets the TLB response + val isMyTurn = tlbArbOut.valid && arbGranted === i.U + client.resp.valid := isMyTurn && tlb_io.resp.valid + client.resp.bits := Mux(isMyTurn, tlb_io.resp.bits, 0.U.asTypeOf(tlb_io.resp.bits)) } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala index 7dccc8d3..dcdc974e 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/tlb/TLBEntry.scala @@ -1,6 +1,7 @@ package framework.memdomain.frontend.outside_channel.tlb import chisel3._ +import chisel3.util._ /** TLB entry data containing translation and permission information */ class TLBEntryData(val paddrBits: Int, val pgIdxBits: Int) extends Bundle { @@ -19,19 +20,93 @@ class TLBEntryData(val paddrBits: Int, val pgIdxBits: Int) extends Bundle { val ae_final = Bool() } -/** TLB entry containing VPN tag and entry data */ -class TLBEntry(val vaddrBits: Int, val pgIdxBits: Int, val paddrBits: Int) extends Bundle { +/** + * TLB entry containing VPN tag and entry data. + * + * Supports superpages. The `level` field stores the PTW response level, + * which indicates at which page table walk step the PTE was found. + * For Sv39 with pgLevels=4 (matching Rocket PTW): + * level=1 → 1GB gigapage (only VPN[2] in PPN, VPN[1:0] from VA) + * level=2 → 2MB megapage (VPN[2:1] in PPN, VPN[0] from VA) + * level=3 → 4KB page (full PPN from PTE) + * + * The superpage PPN generation follows Rocket TLB's logic: + * for j in 1 until pgLevels: + * if level < j: use VPN chunk (superpage covers this level) + * else: use PPN chunk from PTE + */ +class TLBEntry( + val vaddrBits: Int, + val pgIdxBits: Int, + val paddrBits: Int, + val pgLevelBits: Int = 9, + val pgLevels: Int = 4) + extends Bundle { val vpnBits = vaddrBits - pgIdxBits + val ppnBits = paddrBits - pgIdxBits val tag_vpn = UInt(vpnBits.W) val valid = Bool() + val level = UInt(log2Ceil(pgLevels).W) val data = new TLBEntryData(paddrBits, pgIdxBits) - def hit(vpn: UInt): Bool = valid && (tag_vpn === vpn) + /** + * Superpage-aware hit: only compare VPN chunks that are above the + * superpage boundary. Follows Rocket's convention where `level < j` + * means the chunk at position j is covered by the superpage. + */ + def hit(vpn: UInt): Bool = { + // Walk from highest VPN chunk (j=1) to lowest (j=pgLevels-1), + // same ordering as Rocket TLB's ppn() method. + val matches = (1 until pgLevels).map { j => + // Rocket convention: j=1 is the highest VPN/PPN chunk below the top, + // j=pgLevels-1 is the lowest. + // supervisorVPNBits = pgLevels * pgLevelBits (may exceed actual vpnBits) + val supervisorVPNBits = pgLevels * pgLevelBits + val hi = supervisorVPNBits - j * pgLevelBits - 1 + val lo = supervisorVPNBits - (j + 1) * pgLevelBits + // Clamp to actual vpnBits + val clampedHi = math.min(hi, vpnBits - 1) + val clampedLo = math.max(lo, 0) + if (clampedHi < clampedLo) { + true.B // Chunk doesn't exist in VPN, always matches + } else { + val ignore = level < j.U + ignore || (vpn(clampedHi, clampedLo) === tag_vpn(clampedHi, clampedLo)) + } + } + valid && matches.reduce(_ && _) + } + + /** + * Generate the correct PPN for superpage translation. + * Follows Rocket TLB's ppn() method exactly. + */ + def ppn(vpn: UInt): UInt = { + val supervisorVPNBits = pgLevels * pgLevelBits + // Start with the highest PPN chunk (above all VPN levels) + var res = data.ppn >> (pgLevelBits * (pgLevels - 1)) + for (j <- 1 until pgLevels) { + val hi = supervisorVPNBits - j * pgLevelBits - 1 + val lo = supervisorVPNBits - (j + 1) * pgLevelBits + // Clamp to actual ppnBits and vpnBits + val ppnHi = math.min(hi, ppnBits - 1) + val ppnLo = math.max(lo, 0) + if (ppnHi >= ppnLo) { + val ignore = level < j.U + val vpnHi = math.min(hi, vpnBits - 1) + val vpnLo = math.max(lo, 0) + val chunk = Mux(ignore, vpn(vpnHi, vpnLo), data.ppn(ppnHi, ppnLo)) + res = Cat(res, chunk) + } + } + res + } - def insert(vpn: UInt, entryData: TLBEntryData): Unit = { + def insert(vpn: UInt, lvl: UInt, entryData: TLBEntryData): Unit = { tag_vpn := vpn valid := true.B + level := lvl data := entryData } diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 7b8df251..46c1aa6a 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -91,6 +91,10 @@ "ctest_dequant_test_singlecore-baremetal", "ctest_dequant_test_singlecore-baremetal", ), + ( + "ctest_tlb_test-baremetal", + "ctest_tlb_test-baremetal", + ), ] diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 98676a32..6a6ab687 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -119,6 +119,7 @@ add_cross_platform_test_target(ctest_bfp_test bfp_test.c) add_cross_platform_test_target(ctest_quant_test quant_test.c) add_cross_platform_test_target(ctest_dequant_test dequant_test.c) add_cross_platform_test_target(ctest_gemmini_matmul_test gemmini_matmul_test.c) +add_cross_platform_test_target(ctest_tlb_test tlb_test.c) # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS @@ -147,5 +148,6 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_quant_test ctest_dequant_test ctest_gemmini_matmul_test + ctest_tlb_test COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/tlb_test.c b/bb-tests/workloads/src/CTest/toy/tlb_test.c new file mode 100644 index 00000000..06e3926b --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/tlb_test.c @@ -0,0 +1,217 @@ +#include "buckyball.h" +#include +#include +#include +#include + +// --------------------------------------------------------------------------- +// Sv39 page table setup for bare-metal TLB test +// --------------------------------------------------------------------------- +// Sv39: 3-level page table, 4KB pages +// VA bits: [38:30] VPN[2], [29:21] VPN[1], [20:12] VPN[0], [11:0] offset +// We use 1GB megapages (level-2 only) for simplicity: one PTE covers 1GB. +// This creates an identity mapping (VA == PA) for the first 4GB. + +#define PAGESIZE 4096 +#define PTE_V 0x01 // Valid +#define PTE_R 0x02 // Read +#define PTE_W 0x04 // Write +#define PTE_X 0x08 // Execute +#define PTE_U 0x00 // Supervisor only (U=0) +#define PTE_A 0x40 // Accessed +#define PTE_D 0x80 // Dirty +#define PTE_RWXAD (PTE_R | PTE_W | PTE_X | PTE_A | PTE_D) + +#define SATP_MODE_SV39 8UL +#define SATP_MODE_BARE 0UL + +// Page table: one page, 512 entries (level-2 table for Sv39) +// Must be page-aligned (4KB) +static uint64_t page_table[512] __attribute__((aligned(PAGESIZE))); + +static void setup_identity_mapping(void) { + // Create identity mapping using 1GB megapages + // PTE format: [53:10] = PPN, [7:0] = flags + // For a 1GB megapage at level 2: PPN = physical GB index + for (int i = 0; i < 4; i++) { + // PPN for 1GB megapage: GB_index << 18 (since PPN has 28 bits for Sv39, + // and 1GB = 2^30 bytes, PPN = PA >> 12, so PPN = i << 18) + uint64_t ppn = (uint64_t)i << 18; + page_table[i] = (ppn << 10) | PTE_V | PTE_RWXAD; + } + // Remaining entries are invalid (0) + for (int i = 4; i < 512; i++) { + page_table[i] = 0; + } +} + +static void enable_sv39(void) { + uint64_t satp_val = (SATP_MODE_SV39 << 60) | ((uint64_t)page_table >> 12); + asm volatile("csrw satp, %0" ::"r"(satp_val)); + // Flush TLB after changing satp + asm volatile("sfence.vma"); +} + +static void disable_vm(void) { + uint64_t satp_val = SATP_MODE_BARE << 60; + asm volatile("csrw satp, %0" ::"r"(satp_val)); + asm volatile("sfence.vma"); +} + +// --------------------------------------------------------------------------- +// Test data +// --------------------------------------------------------------------------- +#define DIM 16 + +static elem_t input_matrix[DIM * DIM] __attribute__((aligned(128))); +static elem_t output_matrix[DIM * DIM] __attribute__((aligned(128))); + +// --------------------------------------------------------------------------- +// Test 1: DMA with VM disabled (satp.mode=Bare) +// Verifies passthrough works (vm_enabled=false → vaddr=paddr) +// --------------------------------------------------------------------------- +int test_bare_mode(void) { + printf("[TLB Test 1] DMA with VM disabled (Bare mode)...\n"); + + disable_vm(); + + uint32_t bank_id = 0; + bb_mem_alloc(bank_id, 1, 1); + + init_u8_random_matrix(input_matrix, DIM, DIM, 42); + clear_u8_matrix(output_matrix, DIM, DIM); + + bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); + bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); + bb_fence(); + + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { + printf("[TLB Test 1] FAILED: mvin/mvout mismatch in Bare mode\n"); + return 0; + } + + printf("[TLB Test 1] PASSED\n"); + return 1; +} + +// --------------------------------------------------------------------------- +// Test 2: DMA with Sv39 identity mapping +// Verifies TLB translation works (vm_enabled=true, but VA==PA) +// --------------------------------------------------------------------------- +int test_sv39_identity(void) { + printf("[TLB Test 2] DMA with Sv39 identity mapping...\n"); + + setup_identity_mapping(); + enable_sv39(); + + uint32_t bank_id = 0; + bb_mem_alloc(bank_id, 1, 1); + + init_u8_random_matrix(input_matrix, DIM, DIM, 77); + clear_u8_matrix(output_matrix, DIM, DIM); + + bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); + bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); + bb_fence(); + + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { + printf("[TLB Test 2] FAILED: mvin/mvout mismatch with Sv39\n"); + disable_vm(); + return 0; + } + + printf("[TLB Test 2] PASSED\n"); + return 1; +} + +// --------------------------------------------------------------------------- +// Test 3: sfence.vma flushes Buckyball TLB +// After Sv39 is active, issue sfence.vma, then verify DMA still works +// (TLB entries were flushed, must refill from page table) +// --------------------------------------------------------------------------- +int test_sfence_flush(void) { + printf("[TLB Test 3] sfence.vma flush + DMA refill...\n"); + + // sfence.vma: flush all TLBs (CPU + Buckyball) + asm volatile("sfence.vma"); + + uint32_t bank_id = 0; + bb_mem_alloc(bank_id, 1, 1); + + init_u8_random_matrix(input_matrix, DIM, DIM, 99); + clear_u8_matrix(output_matrix, DIM, DIM); + + bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); + bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); + bb_fence(); + + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { + printf("[TLB Test 3] FAILED: mvin/mvout mismatch after sfence\n"); + disable_vm(); + return 0; + } + + printf("[TLB Test 3] PASSED\n"); + return 1; +} + +// --------------------------------------------------------------------------- +// Test 4: Multiple sfence cycles +// Repeatedly: do DMA → sfence → do DMA, to stress TLB flush/refill +// --------------------------------------------------------------------------- +int test_repeated_sfence(void) { + printf("[TLB Test 4] Repeated sfence + DMA cycles...\n"); + + uint32_t bank_id = 0; + + for (int i = 0; i < 4; i++) { + asm volatile("sfence.vma"); + + bb_mem_alloc(bank_id, 1, 1); + init_u8_random_matrix(input_matrix, DIM, DIM, 100 + i); + clear_u8_matrix(output_matrix, DIM, DIM); + + bb_mvin((uintptr_t)input_matrix, bank_id, DIM, 1); + bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); + bb_fence(); + + if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM)) { + printf("[TLB Test 4] FAILED at iteration %d\n", i); + disable_vm(); + return 0; + } + } + + printf("[TLB Test 4] PASSED\n"); + return 1; +} + +// --------------------------------------------------------------------------- +// Main +// --------------------------------------------------------------------------- +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + int all_passed = 1; + + all_passed &= test_bare_mode(); + all_passed &= test_sv39_identity(); + all_passed &= test_sfence_flush(); + all_passed &= test_repeated_sfence(); + + // Restore Bare mode + disable_vm(); + + if (all_passed) { + printf("\n=== ALL TLB TESTS PASSED ===\n"); + } else { + printf("\n=== SOME TLB TESTS FAILED ===\n"); + } + +#ifdef MULTICORE + exit(0); +#endif + return !all_passed; +} diff --git a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt index 180f8c2d..bc3531ac 100644 --- a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt @@ -18,8 +18,10 @@ function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) -expand-strided-metadata -convert-linalg-to-loops -lower-buckyball + -convert-scf-to-cf -finalize-memref-to-llvm -convert-arith-to-llvm + -convert-cf-to-llvm -convert-func-to-llvm -reconcile-unrealized-casts | ${BUDDY_TRANSLATE} --buddy-to-llvmir | diff --git a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt index 88827e24..72d3ed5f 100644 --- a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt @@ -15,8 +15,10 @@ function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) -expand-strided-metadata -convert-linalg-to-loops -lower-buckyball + -convert-scf-to-cf -finalize-memref-to-llvm -convert-arith-to-llvm + -convert-cf-to-llvm -convert-func-to-llvm -reconcile-unrealized-casts | ${BUDDY_TRANSLATE} --buddy-to-llvmir | diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir index 8e1513d7..142f474f 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir @@ -17,9 +17,9 @@ memref.global "private" @input_matrix_aligned : memref<4x16xi8> = dense<[[0, 1, func.func @main() -> i8 { %0 = arith.constant 0 : i8 - // 16-byte aligned scratchpad address - %spadAddr16 = arith.constant 16 : i64 - %stride = arith.constant 16 : i64 + // Bank ID for data storage + %bankId = arith.constant 0 : i64 + %stride = arith.constant 1 : i64 %arrayA = memref.get_global @input_matrix_aligned : memref<4x16xi8> %arrayB = memref.alloc() {alignment = 16} : memref<4x16xi8> @@ -29,12 +29,14 @@ func.func @main() -> i8 { buckyball.bb_print_memref %arrayA : memref<4x16xi8> buckyball.bb_print_memref %arrayB : memref<4x16xi8> + // Allocate bank 0 before mvin + buckyball.bb_mset %bankId : i64 // Use mvin to move data from 16-byte aligned address to scratchpad // CHECK: mvin // Use mvout to move data from scratchpad to 16-byte aligned target address - buckyball.bb_mvin %arrayA %spadAddr16 %stride : memref<4x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId %stride : memref<4x16xi8> i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayB %spadAddr16 : memref<4x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId : memref<4x16xi8> i64 // Print output matrix after move [CHECK2] buckyball.bb_print_memref %arrayB : memref<4x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir index ee249823..6fdafbe9 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir @@ -17,11 +17,10 @@ memref.global "private" @input_matrix_b : memref<2x16xi8> = dense<[[100, 101, 10 func.func @main() -> i8 { %0 = arith.constant 0 : i8 - // Scratchpad address 1 - %spadAddr1 = arith.constant 10 : i64 - // Scratchpad address 2 - %spadAddr2 = arith.constant 50 : i64 - %stride = arith.constant 16 : i64 + // Bank IDs + %bankId0 = arith.constant 0 : i64 + %bankId1 = arith.constant 1 : i64 + %stride = arith.constant 1 : i64 %arrayA = memref.get_global @input_matrix_a : memref<2x16xi8> %arrayB = memref.get_global @input_matrix_b : memref<2x16xi8> @@ -33,27 +32,31 @@ func.func @main() -> i8 { // Print temporary matrix before move [CHECK1] buckyball.bb_print_memref %arrayTemp : memref<2x16xi8> + // Allocate banks before use + buckyball.bb_mset %bankId0 : i64 + buckyball.bb_mset %bankId1 : i64 + // Fast alternating mvin/mvout operation sequence - // Step 1: A -> scratchpad 1 + // Step 1: A -> bank 0 // CHECK: mvin // Step 2: scratchpad 1 -> temp - buckyball.bb_mvin %arrayA %spadAddr1 %stride : memref<2x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId0 %stride : memref<2x16xi8> i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayTemp %spadAddr1 : memref<2x16xi8> i64 + buckyball.bb_mvout %arrayTemp %bankId0 : memref<2x16xi8> i64 - // Step 3: B -> scratchpad 2 + // Step 3: B -> bank 1 // CHECK: mvin - // Step 4: scratchpad 2 -> A - buckyball.bb_mvin %arrayB %spadAddr2 %stride : memref<2x16xi8> i64 i64 + // Step 4: bank 1 -> A + buckyball.bb_mvin %arrayB %bankId1 %stride : memref<2x16xi8> i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayA %spadAddr2 : memref<2x16xi8> i64 + buckyball.bb_mvout %arrayA %bankId1 : memref<2x16xi8> i64 - // Step 5: temp -> scratchpad 1 + // Step 5: temp -> bank 0 // CHECK: mvin - // Step 6: scratchpad 1 -> B - buckyball.bb_mvin %arrayTemp %spadAddr1 %stride : memref<2x16xi8> i64 i64 + // Step 6: bank 0 -> B + buckyball.bb_mvin %arrayTemp %bankId0 %stride : memref<2x16xi8> i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayB %spadAddr1 : memref<2x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId0 : memref<2x16xi8> i64 // Print swapped matrices [CHECK2] buckyball.bb_print_memref %arrayA : memref<2x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir index 98da83b7..939f7591 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir @@ -17,9 +17,9 @@ func.func @main() -> i8 { %c2 = arith.constant 2 : index %c16 = arith.constant 16 : index %c127 = arith.constant 127 : index - // Scratchpad start address - %spadAddr = arith.constant 0 : i64 - %stride = arith.constant 16 : i64 + // Bank ID for storage + %bankId = arith.constant 0 : i64 + %stride = arith.constant 1 : i64 // ========== Row count configuration area (only modify here) ========== // Total number of rows @@ -61,14 +61,17 @@ func.func @main() -> i8 { buckyball.bb_print_memref %arrayB_head : memref<2x16xi8, strided<[16, 1]>> buckyball.bb_print_memref %arrayB_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> + // Allocate bank 0 before mvin + buckyball.bb_mset %bankId : i64 + // Execute long read/write operations // Step 1: long read - read large amount of data from memory into scratchpad // CHECK: mvin - buckyball.bb_mvin %arrayA %spadAddr %stride : memref<1023x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId %stride : memref<1023x16xi8> i64 i64 // Step 2: long write - write large amount of data from scratchpad to memory // CHECK: mvout - buckyball.bb_mvout %arrayB %spadAddr : memref<1023x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId : memref<1023x16xi8> i64 // Print first two rows and last two rows of output matrix after move [CHECK2] %arrayB_head_after = memref.subview %arrayB[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir index a627a556..50f2cd28 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir @@ -19,25 +19,21 @@ memref.global "private" @input_matrix : memref<4x16xi8> = dense<[[1, 2, 3, 4, 5, func.func @main() -> i8 { // === Main program === %0 = arith.constant 0 : i8 - %spadAddr = arith.constant 1040 : i64 - %stride = arith.constant 16 : i64 + %bankId = arith.constant 0 : i64 + %stride = arith.constant 1 : i64 %arrayA = memref.get_global @input_matrix : memref<4x16xi8> %arrayB = memref.alloc() : memref<4x16xi8> - // Use mvin to move data from memory to scratchpad + // Allocate bank 0 before mvin + buckyball.bb_mset %bankId : i64 + // Use mvin to move data from memory to bank 0 // CHECK: mvin - buckyball.bb_mvin %arrayA %spadAddr %stride : memref<4x16xi8> i64 i64 - // Use mvout to move data from scratchpad back to output memory + buckyball.bb_mvin %arrayA %bankId %stride : memref<4x16xi8> i64 i64 + // Use mvout to move data from bank 0 back to output memory // CHECK: mvout - buckyball.bb_mvout %arrayB %spadAddr : memref<4x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId : memref<4x16xi8> i64 // Print moved output matrix buckyball.bb_print_memref %arrayB : memref<4x16xi8> // Release allocated memory memref.dealloc %arrayB : memref<4x16xi8> - - // exit - %exit_code = arith.constant 0 : i32 - func.call @exit(%exit_code) : (i32) -> () - llvm.unreachable + return %0 : i8 } - -func.func private @exit(i32) -> () diff --git a/compiler b/compiler index d2fdc68e..71fbdf72 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit d2fdc68efa7111641309c3120fdf1fd3e832ec2b +Subproject commit 71fbdf72c3361b22064fc5596c3e7d22beda4b38 From 5470ea1fab57c8c7baf77eef3c4c3ec95cbde617 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 8 Mar 2026 02:39:57 +0800 Subject: [PATCH 150/238] [bb-tests] fix: update TLB test workload names for consistency --- bb-tests/sardine/tests/test_ctest.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 46c1aa6a..1f72bed0 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -92,8 +92,8 @@ "ctest_dequant_test_singlecore-baremetal", ), ( - "ctest_tlb_test-baremetal", - "ctest_tlb_test-baremetal", + "ctest_tlb_test_singlecore-baremetal", + "ctest_tlb_test_singlecore-baremetal", ), ] From a879d2de7021cd3a293d0b95056f0f2077906136 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sun, 8 Mar 2026 18:10:38 +0800 Subject: [PATCH 151/238] [arch]add: finish is_shared flag connection but sharedmemback have problems --- .../memdomain/backend/MemBackend.scala | 108 +++++++++++++++++- 1 file changed, 103 insertions(+), 5 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 99dd22fc..2251f454 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -6,6 +6,7 @@ import chisel3.util._ import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig import framework.memdomain.backend.privatepath.PrivateMemBackend +import framework.memdomain.backend.shared.SharedMemBackend @instantiable class MemBackend(val b: GlobalConfig) extends Module { @@ -22,12 +23,109 @@ class MemBackend(val b: GlobalConfig) extends Module { // Keep the private backend datapath unchanged and isolate it in a dedicated module. val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) + val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) - privateBackend.io.mem_req <> io.mem_req - privateBackend.io.config <> io.config + // Broadcast config so alloc/release is handled by the corresponding backend. + privateBackend.io.config.valid := io.config.valid + privateBackend.io.config.bits := io.config.bits + sharedBackend.io.config.valid := io.config.valid + sharedBackend.io.config.bits := io.config.bits + io.config.ready := privateBackend.io.config.ready && sharedBackend.io.config.ready + + // Query both backends; shared takes priority when this vbank is allocated as shared. privateBackend.io.query_vbank_id := io.query_vbank_id - io.query_group_count := privateBackend.io.query_group_count + sharedBackend.io.query_vbank_id := io.query_vbank_id + io.query_group_count := Mux( + sharedBackend.io.query_group_count =/= 0.U, + sharedBackend.io.query_group_count, + privateBackend.io.query_group_count + ) + + // Per-channel request routing: is_shared=0 -> private, is_shared=1 -> shared. + // Route selection is latched at request fire to keep response demux stable. + val readPending = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) + val writePending = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) + val readRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) + val writeRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) + + for (i <- 0 until b.memDomain.bankChannel) { + val useSharedReq = io.mem_req(i).is_shared + val useSharedReadResp = Mux(readPending(i), readRouteShared(i), useSharedReq) + val useSharedWriteResp = Mux(writePending(i), writeRouteShared(i), useSharedReq) + + when(io.mem_req(i).read.req.fire) { + readPending(i) := true.B + readRouteShared(i) := useSharedReq + } + when(io.mem_req(i).read.resp.fire) { + readPending(i) := false.B + } + + when(io.mem_req(i).write.req.fire) { + writePending(i) := true.B + writeRouteShared(i) := useSharedReq + } + when(io.mem_req(i).write.resp.fire) { + writePending(i) := false.B + } + + // Metadata is passed to both backends; only selected backend receives valid req/resp-ready. + privateBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id + privateBackend.io.mem_req(i).group_id := io.mem_req(i).group_id + privateBackend.io.mem_req(i).is_shared := io.mem_req(i).is_shared + sharedBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id + sharedBackend.io.mem_req(i).group_id := io.mem_req(i).group_id + sharedBackend.io.mem_req(i).is_shared := io.mem_req(i).is_shared + + // Read request route + privateBackend.io.mem_req(i).read.req.valid := io.mem_req(i).read.req.valid && !useSharedReq + privateBackend.io.mem_req(i).read.req.bits := io.mem_req(i).read.req.bits + sharedBackend.io.mem_req(i).read.req.valid := io.mem_req(i).read.req.valid && useSharedReq + sharedBackend.io.mem_req(i).read.req.bits := io.mem_req(i).read.req.bits + io.mem_req(i).read.req.ready := Mux( + useSharedReq, + sharedBackend.io.mem_req(i).read.req.ready, + privateBackend.io.mem_req(i).read.req.ready + ) + + // Write request route + privateBackend.io.mem_req(i).write.req.valid := io.mem_req(i).write.req.valid && !useSharedReq + privateBackend.io.mem_req(i).write.req.bits := io.mem_req(i).write.req.bits + sharedBackend.io.mem_req(i).write.req.valid := io.mem_req(i).write.req.valid && useSharedReq + sharedBackend.io.mem_req(i).write.req.bits := io.mem_req(i).write.req.bits + io.mem_req(i).write.req.ready := Mux( + useSharedReq, + sharedBackend.io.mem_req(i).write.req.ready, + privateBackend.io.mem_req(i).write.req.ready + ) + + // Response ready route (selected by latched request route when pending). + privateBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && !useSharedReadResp + sharedBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && useSharedReadResp + privateBackend.io.mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && !useSharedWriteResp + sharedBackend.io.mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && useSharedWriteResp + + // Response valid/bits mux back to midend. + io.mem_req(i).read.resp.valid := Mux( + useSharedReadResp, + sharedBackend.io.mem_req(i).read.resp.valid, + privateBackend.io.mem_req(i).read.resp.valid + ) + io.mem_req(i).read.resp.bits := Mux( + useSharedReadResp, + sharedBackend.io.mem_req(i).read.resp.bits, + privateBackend.io.mem_req(i).read.resp.bits + ) - // Shared backend is intentionally not connected at top-level in this refactor - // to avoid private-path regressions. It can be integrated in a later step. + io.mem_req(i).write.resp.valid := Mux( + useSharedWriteResp, + sharedBackend.io.mem_req(i).write.resp.valid, + privateBackend.io.mem_req(i).write.resp.valid + ) + io.mem_req(i).write.resp.bits := Mux( + useSharedWriteResp, + sharedBackend.io.mem_req(i).write.resp.bits, + privateBackend.io.mem_req(i).write.resp.bits + ) + } } From 02ded4e3aadce8270cbaba5ae262c5264782052c Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sun, 8 Mar 2026 19:43:24 +0800 Subject: [PATCH 152/238] [arch]add:send hartid signal to sharedmem --- .../scala/framework/core/bbtile/BBTile.scala | 1 + .../core/bbtile/BuckyballAccelerator.scala | 2 ++ .../scala/framework/memdomain/MemDomain.scala | 4 ++++ .../memdomain/backend/MemBackend.scala | 3 +++ .../memdomain/backend/shared/SharedMem.scala | 19 +++++++++++++------ .../backend/shared/SharedMemBackend.scala | 4 ++++ .../framework/memdomain/configs/default.json | 2 +- 7 files changed, 28 insertions(+), 7 deletions(-) diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index 13f1d3af..fdf223db 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -288,6 +288,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC val (tl_writer, _) = outer.bb_writer_node.get.out(0) val buckyball = Module(new BuckyballAccelerator(outer.bbConfig)(edge_reader)) + buckyball.io.hartid := outer.hartIdSinkNode.bundle // RoCC cmd/resp: direct wiring (both use RoCCCommandBB/RoCCResponseBB) buckyball.io.cmd <> core.io.rocc.cmd diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index 6046e376..403312af 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -34,6 +34,7 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module val resp = Decoupled(new RoCCResponseBB(b.core.xLen)) val busy = Output(Bool()) val interrupt = Output(Bool()) + val hartid = Input(UInt(b.core.xLen.W)) // PTW interface (shared with Rocket core's PTW) val ptw = Vec(1, new BBTLBPTWIO(b)) @@ -65,6 +66,7 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module // --- Frontend -> MemDomain --- memDomain.io.global_issue_i <> frontend.io.mem_issue_o frontend.io.mem_complete_i <> memDomain.io.global_complete_o + memDomain.io.hartid := io.hartid // --- Frontend -> GpDomain --- gpDomain.io.global_issue_i <> frontend.io.gp_issue_o diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index b4d64367..e32386dd 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -53,6 +53,9 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // TileLink physical connections for DMA val tl_reader = new TLBundle(edge.bundle) val tl_writer = new TLBundle(edge.bundle) + + // Core/thread id used by shared memory addressing. + val hartid = Input(UInt(b.core.xLen.W)) }) val frontend: Instance[MemFrontend] = Instantiate(new MemFrontend(b)(edge)) @@ -62,6 +65,7 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Connect query interface from frontend to backend backend.io.query_vbank_id := frontend.io.query_vbank_id frontend.io.query_group_count := backend.io.query_group_count + backend.io.hartid := io.hartid // ------------------------------------------------- // Connection with outside (all in frontend) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 2251f454..8e88f7d5 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -19,6 +19,8 @@ class MemBackend(val b: GlobalConfig) extends Module { // Query interface for frontend to get group count val query_vbank_id = Input(UInt(8.W)) val query_group_count = Output(UInt(4.W)) + + val hartid = Input(UInt(b.core.xLen.W)) }) // Keep the private backend datapath unchanged and isolate it in a dedicated module. @@ -35,6 +37,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // Query both backends; shared takes priority when this vbank is allocated as shared. privateBackend.io.query_vbank_id := io.query_vbank_id sharedBackend.io.query_vbank_id := io.query_vbank_id + sharedBackend.io.hartid := io.hartid io.query_group_count := Mux( sharedBackend.io.query_group_count =/= 0.U, sharedBackend.io.query_group_count, diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index 0d03a9f0..3cf307b4 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -7,12 +7,14 @@ import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadResp, SramWriteResp} class SharedMemReadReq(val b: GlobalConfig) extends Bundle { + val hartid = UInt(b.core.xLen.W) val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) val group_id = UInt(3.W) val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) } class SharedMemWriteReq(val b: GlobalConfig) extends Bundle { + val hartid = UInt(b.core.xLen.W) val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) val group_id = UInt(3.W) val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) @@ -35,7 +37,9 @@ class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { class SharedMem(val b: GlobalConfig) extends Module { private val maskLen = b.memDomain.bankMaskLen private val maskElem = UInt((b.memDomain.bankWidth / maskLen).W) - private val minSharedLines = b.memDomain.bankNum * b.memDomain.bankEntries + private val hartLines = b.memDomain.bankNum * b.memDomain.bankEntries + private val minSharedLines = hartLines + private val hartSlots = math.max(1, b.memDomain.sharedEntries / hartLines) require( b.memDomain.sharedEntries >= minSharedLines, @@ -51,17 +55,20 @@ class SharedMem(val b: GlobalConfig) extends Module { val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(maskLen, maskElem)) // Shared memory address mapping (group_id intentionally ignored): - // shared_addr = (vbank_id * bankEntries) + local_addr - private def toSharedAddr(vbank_id: UInt, _group_id: UInt, local_addr: UInt): UInt = { + // shared_addr = (hart_slot * bankNum * bankEntries) + (vbank_id * bankEntries) + local_addr. + // hart_slot is derived from hartid and bounded by available shared capacity. + private def toSharedAddr(hartid: UInt, vbank_id: UInt, _group_id: UInt, local_addr: UInt): UInt = { + val hartSlot = if (hartSlots == 1) 0.U else (hartid(log2Ceil(hartSlots) - 1, 0) % hartSlots.U) + val hartPart = hartSlot * hartLines.U val vbankPart = vbank_id * b.memDomain.bankEntries.U - vbankPart + local_addr + hartPart + vbankPart + local_addr } io.read.req.ready := !io.write.req.valid io.write.req.ready := !io.read.req.valid val readReqFire = io.read.req.fire - val readAddr = toSharedAddr(io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) + val readAddr = toSharedAddr(io.read.req.bits.hartid, io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) when(readReqFire) { assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") @@ -74,7 +81,7 @@ class SharedMem(val b: GlobalConfig) extends Module { io.read.resp.bits.data := readData.asUInt val writeReqFire = io.write.req.fire - val writeAddr = toSharedAddr(io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) + val writeAddr = toSharedAddr(io.write.req.bits.hartid, io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) when(writeReqFire) { assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index 0b038e18..aee34888 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -30,6 +30,8 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { // Query interface for frontend to get group count val query_vbank_id = Input(UInt(8.W)) val query_group_count = Output(UInt(4.W)) + + val hartid = Input(UInt(b.core.xLen.W)) }) val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) @@ -179,11 +181,13 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val canIssueWrite = !writeReqPending && !writeRespBufValid sharedMem.io.read.req.valid := sharedReqArb.io.out.valid && !arbIsWrite && canIssueRead + sharedMem.io.read.req.bits.hartid := io.hartid sharedMem.io.read.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id sharedMem.io.read.req.bits.group_id := sharedReqArb.io.out.bits.group_id sharedMem.io.read.req.bits.addr := sharedReqArb.io.out.bits.addr sharedMem.io.write.req.valid := sharedReqArb.io.out.valid && arbIsWrite && canIssueWrite + sharedMem.io.write.req.bits.hartid := io.hartid sharedMem.io.write.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id sharedMem.io.write.req.bits.group_id := sharedReqArb.io.out.bits.group_id sharedMem.io.write.req.bits.addr := sharedReqArb.io.out.bits.addr diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index 524d4e95..357fa453 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -4,7 +4,7 @@ "bankEntries": 128, "bankMaskLen": 16, "sharedEnable": true, - "sharedEntries": 4096, + "sharedEntries": 16384, "sharedDefaultGroupCount": 1, "tlb_size": 4, "dma_n_xacts": 8, From 7d1865df0977722aa1cff6caee3692214d6942a7 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 9 Mar 2026 01:35:01 +0800 Subject: [PATCH 153/238] [mcp] feat: add waveform-mcp submodule and configuration; update build script and ignore files --- .claude/.gitignore | 5 +++-- CLAUDE.md => .claude/CLAUDE.md | 0 .claude/settings.json | 12 ------------ .cursor/mcp.json | 12 ------------ .gitignore | 3 +-- .gitmodules | 3 +++ .mcp.json | 23 +++++++++++++++++++++++ flake.nix | 2 +- scripts/nix/build-all.sh | 15 ++++++++++++--- 9 files changed, 43 insertions(+), 32 deletions(-) rename CLAUDE.md => .claude/CLAUDE.md (100%) delete mode 100644 .claude/settings.json delete mode 100644 .cursor/mcp.json create mode 100644 .mcp.json diff --git a/.claude/.gitignore b/.claude/.gitignore index 8c9bdd3a..adda676e 100644 --- a/.claude/.gitignore +++ b/.claude/.gitignore @@ -1,2 +1,3 @@ -agents/ -settings.local.json +* +!commands/ +!CLAUDE.md diff --git a/CLAUDE.md b/.claude/CLAUDE.md similarity index 100% rename from CLAUDE.md rename to .claude/CLAUDE.md diff --git a/.claude/settings.json b/.claude/settings.json deleted file mode 100644 index ad19c30f..00000000 --- a/.claude/settings.json +++ /dev/null @@ -1,12 +0,0 @@ -{ - "mcpServers": { - "buckyball-dev": { - "type": "stdio", - "command": "nix", - "args": ["develop", "-c", "python3", "-u", "scripts/claude/mcp_server.py"], - "env": { - "BUCKYBALL_QUIET": "1" - } - } - } -} diff --git a/.cursor/mcp.json b/.cursor/mcp.json deleted file mode 100644 index 9e454870..00000000 --- a/.cursor/mcp.json +++ /dev/null @@ -1,12 +0,0 @@ -{ - "mcpServers": { - "buckyball-dev": { - "command": "nix", - "args": ["develop", "-c", "python3", "-u", "scripts/claude/mcp_server.py"], - "cwd": "${workspaceFolder}", - "env": { - "BUCKYBALL_QUIET": "1" - } - } - } - } diff --git a/.gitignore b/.gitignore index a530c749..f2b9252c 100644 --- a/.gitignore +++ b/.gitignore @@ -1,8 +1,7 @@ .vscode/ .metals/ -# .claude/ .motia/ -# .cursor/ +.cursor/ .bsp/ out/ result diff --git a/.gitmodules b/.gitmodules index a7a22d3d..f37eca4a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -22,3 +22,6 @@ [submodule "docs"] path = docs url = https://github.com/DangoSys/documents.git +[submodule "thirdparty/waveform-mcp"] + path = thirdparty/waveform-mcp + url = https://github.com/jiegec/waveform-mcp.git diff --git a/.mcp.json b/.mcp.json new file mode 100644 index 00000000..0993e650 --- /dev/null +++ b/.mcp.json @@ -0,0 +1,23 @@ +{ + "mcpServers": { + "buckyball-dev": { + "type": "stdio", + "command": "nix", + "args": [ + "develop", + "-c", + "python3", + "-u", + "scripts/claude/mcp_server.py" + ], + "env": { + "NIX_QUIET": "1" + } + }, + "waveform-mcp": { + "type": "stdio", + "command": "thirdparty/waveform-mcp/target/release/waveform-mcp", + "args": [] + } + } +} diff --git a/flake.nix b/flake.nix index f4b541b8..b2f2e6b6 100644 --- a/flake.nix +++ b/flake.nix @@ -87,7 +87,7 @@ # Verilator build acceleration: ccache via OBJCACHE export OBJCACHE=ccache - if [ -z "$BUCKYBALL_QUIET" ]; then + if [ -z "$NIX_QUIET" ]; then echo "================= Buckyball Environment Activated =========================" echo "Development environment loaded:" echo "Verilator: $(verilator --version 2>&1 | head -1)" diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index a09cfc32..eaafab92 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -14,8 +14,10 @@ usage() { echo " 1. bbdev install" echo " 2. Compiler installation" echo " 3. RTL pre-compile sources" - echo " 4. workloads pre-compile sources" - echo " 5. pre-commit hooks installation" + echo " 4. bebop install" + echo " 5. bb-tests pre-compile sources" + echo " 6. waveform-mcp build" + echo " 7. pre-commit hooks installation" echo "" echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" echo "" @@ -152,7 +154,14 @@ if run_step "5"; then fi if run_step "6"; then - begin_step "6" "pre-commit hooks installation" + begin_step "6" "waveform-mcp build" + cd ${BBDIR}/thirdparty/waveform-mcp + cargo build --release +fi + +if run_step "7"; then + begin_step "7" "pre-commit hooks installation" + cd ${BBDIR} pre-commit install # Replace with wrapper so git commit gets nix env (result/bin in PATH) cp "${BBDIR}/scripts/pre-commit-hook.sh" "${BBDIR}/.git/hooks/pre-commit" From 6ded0005c5d72dc04a673947d8af6330f8ca44d5 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 9 Mar 2026 01:52:54 +0800 Subject: [PATCH 154/238] [bbAgent] feat: initialize waveform-mcp submodule --- thirdparty/waveform-mcp | 1 + 1 file changed, 1 insertion(+) create mode 160000 thirdparty/waveform-mcp diff --git a/thirdparty/waveform-mcp b/thirdparty/waveform-mcp new file mode 160000 index 00000000..0dc6a87d --- /dev/null +++ b/thirdparty/waveform-mcp @@ -0,0 +1 @@ +Subproject commit 0dc6a87dca16a151ca2313223b75c67e4270f610 From 0c35959a2859e9046ce85624daf1ecae442f1dd1 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 9 Mar 2026 03:01:15 +0800 Subject: [PATCH 155/238] [arch] feat: refactor instruction encoding [bb-tests] feat: refactor instruction encoding --- .../toy/balldomain/DomainDecoder.scala | 88 +++++++++++-------- .../prototype/dequant/Dequant.scala | 6 +- .../prototype/gemmini/GemminiExCtrl.scala | 14 +-- .../balldomain/prototype/quant/Quant.scala | 8 +- .../balldomain/prototype/relu/Relu.scala | 6 +- .../systolicarray/SystolicArrayCtrl.scala | 2 +- .../systolicarray/SystolicArrayEX.scala | 8 +- .../systolicarray/SystolicArrayLoad.scala | 8 +- .../systolicarray/SystolicArrayStore.scala | 8 +- .../systolicarray/SystolicArrayUnit.scala | 2 +- .../prototype/vector/VecCtrlUnit.scala | 2 +- .../prototype/vector/VecEXUnit.scala | 4 +- .../prototype/vector/VecLoadUnit.scala | 10 +-- .../prototype/vector/VecStoreUnit.scala | 10 +-- .../balldomain/rs/reservationStation.scala | 6 +- .../frontend/configs/FrontendParam.scala | 3 +- .../framework/frontend/configs/default.json | 3 +- .../frontend/decoder/GobalDecoder.scala | 30 +++---- .../memdomain/backend/MemBackend.scala | 18 ++-- .../memdomain/backend/shared/SharedMem.scala | 18 +++- .../framework/memdomain/configs/default.json | 4 +- .../cmd_channel/decoder/DomainDecoder.scala | 72 +++++++-------- .../frontend/outside_channel/MemLoader.scala | 6 +- .../frontend/outside_channel/MemStorer.scala | 8 +- .../workloads/lib/bbhw/isa/21_shared_mvin.c | 8 +- .../workloads/lib/bbhw/isa/22_shared_mvout.c | 8 +- bb-tests/workloads/lib/bbhw/isa/24_mvin.c | 6 +- bb-tests/workloads/lib/bbhw/isa/25_mvout.c | 6 +- .../workloads/lib/bbhw/isa/32_mul_warp16.c | 6 +- .../workloads/lib/bbhw/isa/34_transpose.c | 6 +- bb-tests/workloads/lib/bbhw/isa/38_relu.c | 6 +- bb-tests/workloads/lib/bbhw/isa/39_bfp.c | 10 +-- bb-tests/workloads/lib/bbhw/isa/40_quant.c | 12 +-- bb-tests/workloads/lib/bbhw/isa/41_dequant.c | 12 +-- .../lib/bbhw/isa/42_gemmini_config.c | 12 ++- .../lib/bbhw/isa/43_gemmini_preload.c | 6 +- .../bbhw/isa/44_gemmini_compute_preloaded.c | 6 +- .../bbhw/isa/45_gemmini_compute_accumulated.c | 6 +- bb-tests/workloads/lib/bbhw/isa/isa.h | 23 ++--- 39 files changed, 255 insertions(+), 222 deletions(-) diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 244d3790..8a89d2ad 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -9,10 +9,10 @@ import examples.toy.balldomain.DISA._ import framework.top.GlobalConfig // Detailed decode output for Ball domain -class BallDecodeCmd(numBanks: Int) extends Bundle { +class BallDecodeCmd(numBanks: Int, iterLen: Int) extends Bundle { val bid = UInt(5.W) // Iteration count - val iter = UInt(10.W) + val iter = UInt(iterLen.W) // Ball-specific fields val op1_en = Bool() @@ -20,10 +20,10 @@ class BallDecodeCmd(numBanks: Int) extends Bundle { val wr_spad_en = Bool() val op1_from_spad = Bool() val op2_from_spad = Bool() - // Instruction-specific subfield - val special = UInt(40.W) + // Instruction-specific subfield (full rs2) + val special = UInt(64.W) - // Ball operand bank IDs (now directly from rs1/rs2) + // Ball operand bank IDs val op1_bank = UInt(log2Up(numBanks).W) val op2_bank = UInt(log2Up(numBanks).W) val wr_bank = UInt(log2Up(numBanks).W) @@ -35,7 +35,7 @@ class BallDecodeCmd(numBanks: Int) extends Bundle { // Ball decode fields object BallDecodeFields extends Enumeration { type Field = Value - val OP1_EN, OP2_EN, WR_SPAD, OP1_FROM_SPAD, OP2_FROM_SPAD, OP1_SPADDR, OP2_SPADDR, WR_SPADDR, ITER, BID, SPECIAL = + val OP1_EN, OP2_EN, WR_SPAD, OP1_FROM_SPAD, OP2_FROM_SPAD, OP1_SPADDR, OP2_SPADDR, WR_SPADDR, BID, SPECIAL = Value } @@ -43,19 +43,22 @@ object BallDecodeFields extends Enumeration { object BallDefaultConstants { val Y = true.B val N = false.B - val DADDR = 0.U(14.W) - val DITER = 0.U(10.W) + val DADDR = 0.U(15.W) val DBID = 0.U(5.W) - val DSPECIAL = 0.U(40.W) + val DSPECIAL = 0.U(64.W) } @instantiable class BallDomainDecoder(val b: GlobalConfig) extends Module { import BallDefaultConstants._ + + val bankIdLen = b.frontend.bank_id_len + val iterLen = b.frontend.iter_len + @public val cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) @public - val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum))) + val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum, iterLen))) cmd_i.ready := ball_decode_cmd_o.ready @@ -63,39 +66,52 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { val rs1 = cmd_i.bits.cmd.rs1Data val rs2 = cmd_i.bits.cmd.rs2Data + // Unified rs1 layout: + // rs1[14:0] = BANK0 (op1 bank) + // rs1[29:15] = BANK1 (op2 bank) + // rs1[44:30] = BANK2 (wr bank) + // rs1[45] = BB_RD0 + // rs1[46] = BB_RD1 + // rs1[47] = BB_WR + // rs1[63:48] = ITER + // rs2 = special (full 64-bit) + + val op1_bank_raw = rs1(bankIdLen - 1, 0) + val op2_bank_raw = rs1(bankIdLen + 14, 15) + val wr_bank_raw = rs1(bankIdLen + 29, 30) + val iter_raw = rs1(63, 48) + // Ball instruction decoding import BallDecodeFields._ - val ball_default_decode = List(N, N, N, N, N, 0.U, 0.U, 0.U, DITER, DBID, DSPECIAL) + val ball_default_decode = List(N, N, N, N, N, 0.U, 0.U, 0.U, DBID, DSPECIAL) val ball_decode_list = ListLookup( func7, ball_default_decode, Array( - // New unified encoding: wr_bank is always at rs1[23:16] - // iter/special shifted in rs2 since wr_bank no longer occupies rs2[7:0] - // op1 op2 wr op1s op2s op1_bank op2_bank wr_bank iter bid special - MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 0.U, rs2(63, 10)), - RELU -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 1.U, rs2(63, 10)), - TRANSPOSE -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 2.U, rs2(63, 10)), - IM2COL -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), DITER, 3.U, rs2(63, 0)), - SYSTOLIC -> List(Y, Y, Y, Y, Y, rs1(7, 0), rs1(15, 8), rs1(23, 16), rs2(9, 0), 4.U, rs2(63, 10)), - QUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 5.U, rs2(63, 10)), - DEQUANT -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 6.U, rs2(63, 10)), + // Unified encoding: banks from rs1[14:0]/[29:15]/[44:30], iter from rs1[63:48], special = rs2 + // op1 op2 wr op1s op2s op1_bank op2_bank wr_bank bid special // Gemmini systolic array instructions — all share bid=7, sub-command in special[3:0] - GEMMINI_CONFIG -> List(N, N, N, N, N, DADDR, DADDR, DADDR, DITER, 7.U, Cat(0.U(36.W), 0.U(4.W))), - GEMMINI_PRELOAD -> List(Y, N, Y, Y, N, rs1(7, 0), DADDR, rs1(23, 16), rs2(9, 0), 7.U, Cat(rs2(63, 10), 1.U(4.W))), + MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 0.U, rs2), + RELU -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 1.U, rs2), + TRANSPOSE -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 2.U, rs2), + IM2COL -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 3.U, rs2), + SYSTOLIC -> List(Y, Y, Y, Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 4.U, rs2), + QUANT -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 5.U, rs2), + DEQUANT -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 6.U, rs2), + GEMMINI_CONFIG -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 7.U, Cat(rs2(63, 4), 0.U(4.W))), + GEMMINI_PRELOAD -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 7.U, Cat(rs2(63, 4), 1.U(4.W))), GEMMINI_COMPUTE_PRELOADED -> List( Y, Y, Y, Y, Y, - rs1(7, 0), - rs1(15, 8), - rs1(23, 16), - rs2(9, 0), + op1_bank_raw, + op2_bank_raw, + wr_bank_raw, 7.U, - Cat(rs2(63, 10), 2.U(4.W)) + Cat(rs2(63, 4), 2.U(4.W)) ), GEMMINI_COMPUTE_ACCUMULATED -> List( Y, @@ -103,14 +119,13 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { Y, Y, Y, - rs1(7, 0), - rs1(15, 8), - rs1(23, 16), - rs2(9, 0), + op1_bank_raw, + op2_bank_raw, + wr_bank_raw, 7.U, - Cat(rs2(63, 10), 3.U(4.W)) + Cat(rs2(63, 4), 3.U(4.W)) ), - GEMMINI_FLUSH -> List(N, N, N, N, N, DADDR, DADDR, DADDR, DITER, 7.U, Cat(0.U(36.W), 4.U(4.W))) + GEMMINI_FLUSH -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 7.U, Cat(0.U(60.W), 4.U(4.W))) ) ) @@ -121,10 +136,11 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) + // iter is always from rs1[63:48] ball_decode_cmd_o.bits.iter := Mux( ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.ITER.id).asUInt, - 0.U(10.W) + iter_raw, + 0.U(iterLen.W) ) ball_decode_cmd_o.bits.special := Mux( ball_decode_cmd_o.valid, diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala b/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala index a150db7c..91f8219a 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala @@ -60,11 +60,11 @@ class Dequant(val b: GlobalConfig) extends Module { val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val raddr_reg = RegInit(0.U(10.W)) + val raddr_reg = RegInit(0.U(b.frontend.iter_len.W)) val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val waddr_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(b.frontend.iter_len.W)) val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(10.W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val scale_reg = RegInit(0.U(32.W)) // Default outputs diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala index 5ca61fff..a2c93bd8 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala @@ -192,12 +192,14 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { total_rows := Mux(io.cmdReq.bits.cmd.iter === 0.U, DIM.U, io.cmdReq.bits.cmd.iter) when(sub_cmd === GemminiSubCmd.CONFIG) { - // CONFIG: decode and apply immediately from live wires (still valid this cycle) - cfg_dataflow := io.cmdReq.bits.cmd.rs1(2) - cfg_activation := io.cmdReq.bits.cmd.rs1(4, 3) - cfg_a_transpose := io.cmdReq.bits.cmd.rs1(8) - cfg_b_transpose := io.cmdReq.bits.cmd.rs1(9) - cfg_in_shift := io.cmdReq.bits.cmd.rs2(log2Up(config.accWidth) - 1, 0) + // CONFIG: decode from special field (rs2 with sub_cmd in [3:0]) + // Config params start at bit 4: [4]=dataflow, [6:5]=activation, [7]=a_transpose, [8]=b_transpose, + // [40:9]=in_shift + cfg_dataflow := io.cmdReq.bits.cmd.special(4) + cfg_activation := io.cmdReq.bits.cmd.special(6, 5) + cfg_a_transpose := io.cmdReq.bits.cmd.special(7) + cfg_b_transpose := io.cmdReq.bits.cmd.special(8) + cfg_in_shift := io.cmdReq.bits.cmd.special(log2Up(config.accWidth) + 8, 9) // Commit immediately io.cmdResp.valid := true.B // Stay in sIdle if resp fires, else we need a config state diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala b/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala index f510a193..fc6239d8 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala @@ -72,11 +72,11 @@ class Quant(val b: GlobalConfig) extends Module { val respCounter = RegInit(0.U(log2Ceil(InputNum * 4 + 1).W)) // response counter val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val raddr_reg = RegInit(0.U(10.W)) + val raddr_reg = RegInit(0.U(b.frontend.iter_len.W)) val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val waddr_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(b.frontend.iter_len.W)) val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(10.W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val scale_reg = RegInit(0.U(32.W)) // For INT8: accumulate 4 responses into one output word @@ -84,7 +84,7 @@ class Quant(val b: GlobalConfig) extends Module { val int8OutIdx = RegInit(0.U(log2Ceil(InputNum + 1).W)) // output word index // Total read requests needed - val totalReads = Wire(UInt(10.W)) + val totalReads = Wire(UInt(b.frontend.iter_len.W)) if (isInt8) { totalReads := iter_reg << 2 } else { diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index a6f1f5bc..0abc7e2f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -60,11 +60,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { val respCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) val writeCounter = RegInit(0.U(log2Ceil(InputNum + 1).W)) - val waddr_reg = RegInit(0.U(10.W)) + val waddr_reg = RegInit(0.U(b.frontend.iter_len.W)) val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val raddr_reg = RegInit(0.U(10.W)) + val raddr_reg = RegInit(0.U(b.frontend.iter_len.W)) val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(10.W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val cycle_reg = RegInit(0.U(6.W)) val iterCnt = RegInit(0.U(32.W)) val writeDataReg = Reg(UInt(bankWidth.W)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala index 87ba8d8f..97d84024 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala @@ -23,7 +23,7 @@ class SystolicArrayCtrl(val b: GlobalConfig) extends Module { }) val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - val iter = RegInit(0.U(10.W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val op1_bank_addr = RegInit(0.U(12.W)) val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala index f32faf6b..a854051f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayEX.scala @@ -8,14 +8,14 @@ import framework.top.GlobalConfig import framework.balldomain.prototype.systolicarray.configs.SystolicBallParam class ctrl_ex_req(b: GlobalConfig) extends Bundle { - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } class ld_ex_req(b: GlobalConfig) extends Bundle { val config = SystolicBallParam() val op1 = Vec(config.lane, UInt(config.inputWidth.W)) val op2 = Vec(config.lane, UInt(config.inputWidth.W)) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } class ex_st_req(b: GlobalConfig) extends Bundle { @@ -72,9 +72,9 @@ class SystolicArrayEX(val b: GlobalConfig) extends Module { val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) - val iter_counter = RegInit(0.U(10.W)) + val iter_counter = RegInit(0.U(b.frontend.iter_len.W)) val store_counter = RegInit(0.U(6.W)) - val in_counter = RegInit(0.U(10.W)) + val in_counter = RegInit(0.U(b.frontend.iter_len.W)) // Use Reg with Vec type for proper register behavior val in_a_buffer = Reg(Vec(arraySize, Vec(arraySize, UInt(inputWidth.W)))) diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala index e2d4d9bb..d086e8c6 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayLoad.scala @@ -32,12 +32,12 @@ class SystolicArrayLoad(val b: GlobalConfig) extends Module { val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val op1_iter_counter = RegInit(0.U(10.W)) - val op2_iter_counter = RegInit(0.U(10.W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) + val op1_iter_counter = RegInit(0.U(b.frontend.iter_len.W)) + val op2_iter_counter = RegInit(0.U(b.frontend.iter_len.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) - val ld_ex_iter_reg = RegInit(0.U(10.W)) + val ld_ex_iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val bankRespQueue0 = Module(new Queue(new SramReadResp(b), entries = 8)) val bankRespQueue1 = Module(new Queue(new SramReadResp(b), entries = 8)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala index 56f01431..c930a4d3 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayStore.scala @@ -10,7 +10,7 @@ import framework.top.GlobalConfig class ctrl_st_req(b: GlobalConfig) extends Bundle { val wr_bank = UInt(log2Up(b.memDomain.bankNum).W) val wr_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } class BankWriteEntry(b: GlobalConfig) extends Bundle { @@ -40,8 +40,8 @@ class SystolicArrayStore(val b: GlobalConfig) extends Module { val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) + val iter_counter = RegInit(0.U(b.frontend.iter_len.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) @@ -55,7 +55,7 @@ class SystolicArrayStore(val b: GlobalConfig) extends Module { when(io.ctrl_st_i.fire) { wr_bank := io.ctrl_st_i.bits.wr_bank wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr - iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) + iter := (io.ctrl_st_i.bits.iter + 15.U) & (~15.U(b.frontend.iter_len.W)) iter_counter := 0.U state := busy } diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala index 548c0b80..f3ac5bfd 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayUnit.scala @@ -14,7 +14,7 @@ class ctrl_ld_req(b: GlobalConfig) extends Bundle { val op1_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) val op2_bank = UInt(log2Up(b.memDomain.bankNum).W) val op2_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } @instantiable diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala index d92e4bec..0467beaf 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala @@ -23,7 +23,7 @@ class VecCtrlUnit(val b: GlobalConfig) extends Module { }) val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - val iter = RegInit(0.U(10.W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala index cc7797ca..50f81ed3 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecEXUnit.scala @@ -9,14 +9,14 @@ import framework.balldomain.prototype.vector.warp.MeshWarp import framework.balldomain.prototype.vector.configs.VectorBallParam class ctrl_ex_req(b: GlobalConfig) extends Bundle { - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } class ld_ex_req(b: GlobalConfig) extends Bundle { val config = VectorBallParam() val op1 = Vec(config.lane, UInt(config.inputWidth.W)) val op2 = Vec(config.lane, UInt(config.inputWidth.W)) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } @instantiable diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala index 439ccc80..5ea42d23 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecLoadUnit.scala @@ -13,7 +13,7 @@ class ctrl_ld_req(b: GlobalConfig) extends Bundle { val op1_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) val op2_bank = UInt(log2Up(b.memDomain.bankNum).W) val op2_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) val mode = UInt(1.W) } @@ -44,14 +44,14 @@ class VecLoadUnit(val b: GlobalConfig) extends Module { val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val op1_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val op2_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val op1_iter_counter = RegInit(0.U(10.W)) - val op2_iter_counter = RegInit(0.U(10.W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) + val op1_iter_counter = RegInit(0.U(b.frontend.iter_len.W)) + val op2_iter_counter = RegInit(0.U(b.frontend.iter_len.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) val ld_ex_op1_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) val ld_ex_op2_reg = Reg(Vec(InputNum, UInt(inputWidth.W))) - val ld_ex_iter_reg = RegInit(0.U(10.W)) + val ld_ex_iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val wait1_reg = RegInit(false.B) val wait2_reg = RegInit(false.B) val wait1_cnt = RegInit(0.U(7.W)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala index d70947cf..9dc711dd 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecStoreUnit.scala @@ -11,7 +11,7 @@ import framework.balldomain.prototype.vector.configs.VectorBallParam class ctrl_st_req(b: GlobalConfig) extends Bundle { val wr_bank = UInt(log2Up(b.memDomain.bankNum).W) val wr_bank_addr = UInt(log2Up(b.memDomain.bankEntries).W) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } class ex_st_req(b: GlobalConfig) extends Bundle { @@ -19,7 +19,7 @@ class ex_st_req(b: GlobalConfig) extends Bundle { val InputNum = config.lane val accWidth = config.outputWidth val rst = Vec(InputNum, UInt(accWidth.W)) - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) } class BankWriteEntry(b: GlobalConfig) extends Bundle { @@ -51,8 +51,8 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val wr_bank_addr = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) - val iter = RegInit(0.U(10.W)) - val iter_counter = RegInit(0.U(10.W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) + val iter_counter = RegInit(0.U(b.frontend.iter_len.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) @@ -66,7 +66,7 @@ class VecStoreUnit(val b: GlobalConfig) extends Module { when(io.ctrl_st_i.fire) { wr_bank := io.ctrl_st_i.bits.wr_bank wr_bank_addr := io.ctrl_st_i.bits.wr_bank_addr - iter := (io.ctrl_st_i.bits.iter + 15.U(10.W)) & (~15.U(10.W)) + iter := (io.ctrl_st_i.bits.iter + 15.U) & (~15.U(b.frontend.iter_len.W)) iter_counter := 0.U state := busy } diff --git a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala index af09bd9f..0058ea8b 100644 --- a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala @@ -8,7 +8,7 @@ import examples.toy.balldomain.BallDecodeCmd // Ball domain issue interface - includes global rob_id class BallRsIssue(b: GlobalConfig) extends Bundle { - val cmd = new BallDecodeCmd(b.memDomain.bankNum) + val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) // Global ROB ID val rob_id = UInt(log2Up(b.frontend.rob_entries).W) } @@ -34,7 +34,7 @@ class BallReservationStation(val b: GlobalConfig) extends Module { @public val ball_decode_cmd_i = IO(Flipped(new DecoupledIO(new Bundle { - val cmd = new BallDecodeCmd(b.memDomain.bankNum) + val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) // Global ROB ID val rob_id = UInt(log2Up(b.frontend.rob_entries).W) }))) @@ -53,7 +53,7 @@ class BallReservationStation(val b: GlobalConfig) extends Module { // Simple FIFO queue, only for buffering val fifo = Module(new Queue( new Bundle { - val cmd = new BallDecodeCmd(b.memDomain.bankNum) + val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) val rob_id = UInt(log2Up(b.frontend.rob_entries).W) }, entries = 4 diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index 0213195e..767e5d17 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -8,7 +8,8 @@ import upickle.default._ case class FrontendParam( rob_entries: Int, rs_out_of_order_response: Boolean, - bank_id_len: Int) + bank_id_len: Int, + iter_len: Int) object FrontendParam { implicit val rw: ReadWriter[FrontendParam] = macroRW diff --git a/arch/src/main/scala/framework/frontend/configs/default.json b/arch/src/main/scala/framework/frontend/configs/default.json index 3fda4d09..6be04f87 100644 --- a/arch/src/main/scala/framework/frontend/configs/default.json +++ b/arch/src/main/scala/framework/frontend/configs/default.json @@ -1,5 +1,6 @@ { "rob_entries": 16, "rs_out_of_order_response": true, - "bank_id_len": 8 + "bank_id_len": 15, + "iter_len": 16 } diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index 5d09bfaf..06dc86c8 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -74,27 +74,27 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { ) // ------------------------------------------------------------------------- - // Bank access info extraction — read valid flags from rs1[24:26] + // Bank access info extraction — read valid flags from rs1[45:47] // // Unified rs1 layout (defined in isa.h): - // rs1[7:0] = bank_0 (rd_bank_0 or wr_bank for MVIN/MSET) - // rs1[15:8] = bank_1 (rd_bank_1, dual-operand only) - // rs1[23:16] = bank_2 (wr_bank for Ball instructions) - // rs1[24] = rd_bank_0_valid flag (BB_RD0) - // rs1[25] = rd_bank_1_valid flag (BB_RD1) - // rs1[26] = wr_bank_valid flag (BB_WR) - // rs1[63:27] = instruction-specific (mem_addr for MVIN/MVOUT, etc.) + // rs1[14:0] = bank_0 (rd_bank_0 or wr_bank for MVIN/MSET) + // rs1[29:15] = bank_1 (rd_bank_1, dual-operand only) + // rs1[44:30] = bank_2 (wr_bank for Ball instructions) + // rs1[45] = rd_bank_0_valid flag (BB_RD0) + // rs1[46] = rd_bank_1_valid flag (BB_RD1) + // rs1[47] = wr_bank_valid flag (BB_WR) + // rs1[63:48] = iter (16-bit) // ------------------------------------------------------------------------- val bankAccess = Wire(new BankAccessInfo(bankIdLen)) - bankAccess.rd_bank_0_valid := rs1(24) + bankAccess.rd_bank_0_valid := rs1(45) bankAccess.rd_bank_0_id := rs1(bankIdLen - 1, 0) - bankAccess.rd_bank_1_valid := rs1(25) - bankAccess.rd_bank_1_id := rs1(bankIdLen + 7, 8) - bankAccess.wr_bank_valid := rs1(26) - // For Mem instructions (MVIN/MSET), wr_bank is bank_0 (rs1[7:0]) - // For Ball instructions, wr_bank is bank_2 (rs1[23:16]) - bankAccess.wr_bank_id := Mux(is_mem_inst, rs1(bankIdLen - 1, 0), rs1(bankIdLen + 15, 16)) + bankAccess.rd_bank_1_valid := rs1(46) + bankAccess.rd_bank_1_id := rs1(bankIdLen + 14, 15) + bankAccess.wr_bank_valid := rs1(47) + // For Mem instructions (MVIN/MSET), wr_bank is bank_0 (rs1[14:0]) + // For Ball instructions, wr_bank is bank_2 (rs1[44:30]) + bankAccess.wr_bank_id := Mux(is_mem_inst, rs1(bankIdLen - 1, 0), rs1(bankIdLen + 29, 30)) // Output control io.id_o.valid := io.id_i.valid diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 8e88f7d5..c75eb8f2 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -25,7 +25,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // Keep the private backend datapath unchanged and isolate it in a dedicated module. val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) - val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) + val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) // Broadcast config so alloc/release is handled by the corresponding backend. privateBackend.io.config.valid := io.config.valid @@ -52,12 +52,12 @@ class MemBackend(val b: GlobalConfig) extends Module { val writeRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) for (i <- 0 until b.memDomain.bankChannel) { - val useSharedReq = io.mem_req(i).is_shared - val useSharedReadResp = Mux(readPending(i), readRouteShared(i), useSharedReq) + val useSharedReq = io.mem_req(i).is_shared + val useSharedReadResp = Mux(readPending(i), readRouteShared(i), useSharedReq) val useSharedWriteResp = Mux(writePending(i), writeRouteShared(i), useSharedReq) when(io.mem_req(i).read.req.fire) { - readPending(i) := true.B + readPending(i) := true.B readRouteShared(i) := useSharedReq } when(io.mem_req(i).read.resp.fire) { @@ -65,7 +65,7 @@ class MemBackend(val b: GlobalConfig) extends Module { } when(io.mem_req(i).write.req.fire) { - writePending(i) := true.B + writePending(i) := true.B writeRouteShared(i) := useSharedReq } when(io.mem_req(i).write.resp.fire) { @@ -103,8 +103,8 @@ class MemBackend(val b: GlobalConfig) extends Module { ) // Response ready route (selected by latched request route when pending). - privateBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && !useSharedReadResp - sharedBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && useSharedReadResp + privateBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && !useSharedReadResp + sharedBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && useSharedReadResp privateBackend.io.mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && !useSharedWriteResp sharedBackend.io.mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && useSharedWriteResp @@ -114,7 +114,7 @@ class MemBackend(val b: GlobalConfig) extends Module { sharedBackend.io.mem_req(i).read.resp.valid, privateBackend.io.mem_req(i).read.resp.valid ) - io.mem_req(i).read.resp.bits := Mux( + io.mem_req(i).read.resp.bits := Mux( useSharedReadResp, sharedBackend.io.mem_req(i).read.resp.bits, privateBackend.io.mem_req(i).read.resp.bits @@ -125,7 +125,7 @@ class MemBackend(val b: GlobalConfig) extends Module { sharedBackend.io.mem_req(i).write.resp.valid, privateBackend.io.mem_req(i).write.resp.valid ) - io.mem_req(i).write.resp.bits := Mux( + io.mem_req(i).write.resp.bits := Mux( useSharedWriteResp, sharedBackend.io.mem_req(i).write.resp.bits, privateBackend.io.mem_req(i).write.resp.bits diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index 3cf307b4..9a393786 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -57,7 +57,12 @@ class SharedMem(val b: GlobalConfig) extends Module { // Shared memory address mapping (group_id intentionally ignored): // shared_addr = (hart_slot * bankNum * bankEntries) + (vbank_id * bankEntries) + local_addr. // hart_slot is derived from hartid and bounded by available shared capacity. - private def toSharedAddr(hartid: UInt, vbank_id: UInt, _group_id: UInt, local_addr: UInt): UInt = { + private def toSharedAddr( + hartid: UInt, + vbank_id: UInt, + _group_id: UInt, + local_addr: UInt + ): UInt = { val hartSlot = if (hartSlots == 1) 0.U else (hartid(log2Ceil(hartSlots) - 1, 0) % hartSlots.U) val hartPart = hartSlot * hartLines.U val vbankPart = vbank_id * b.memDomain.bankEntries.U @@ -68,7 +73,8 @@ class SharedMem(val b: GlobalConfig) extends Module { io.write.req.ready := !io.read.req.valid val readReqFire = io.read.req.fire - val readAddr = toSharedAddr(io.read.req.bits.hartid, io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) + val readAddr = + toSharedAddr(io.read.req.bits.hartid, io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) when(readReqFire) { assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") @@ -81,7 +87,13 @@ class SharedMem(val b: GlobalConfig) extends Module { io.read.resp.bits.data := readData.asUInt val writeReqFire = io.write.req.fire - val writeAddr = toSharedAddr(io.write.req.bits.hartid, io.write.req.bits.vbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) + + val writeAddr = toSharedAddr( + io.write.req.bits.hartid, + io.write.req.bits.vbank_id, + io.write.req.bits.group_id, + io.write.req.bits.addr + ) when(writeReqFire) { assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") diff --git a/arch/src/main/scala/framework/memdomain/configs/default.json b/arch/src/main/scala/framework/memdomain/configs/default.json index 357fa453..bf7223da 100644 --- a/arch/src/main/scala/framework/memdomain/configs/default.json +++ b/arch/src/main/scala/framework/memdomain/configs/default.json @@ -12,8 +12,8 @@ "bankChannel": 7, "max_in_flight_mem_reqs": 16, "dma_buswidth": 128, - "memAddrLen": 32, + "memAddrLen": 39, "balldomainChannel": 6, "tmaReadChannel": 4, "tmaWriteChannel": 4 -} \ No newline at end of file +} diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index db7df0c9..e4ee056d 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -18,26 +18,24 @@ class MemDecodeCmd(b: GlobalConfig) extends Bundle { // Memory address val mem_addr = UInt(b.memDomain.memAddrLen.W) // Iteration count - val iter = UInt(10.W) + val iter = UInt(b.frontend.iter_len.W) // Bank information - // 3 bits, supports 8 banks (SPAD+ACC) val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val special = UInt(40.W) + val special = UInt(64.W) } -// LS decode fields +// LS decode fields (iter removed from decode table — always from rs1[63:48]) object LSDecodeFields extends Enumeration { type Field = Value - val SHARED_EN, LD_EN, ST_EN, MEMADDR, BANK_ID, ITER, SPECIAL, VALID = Value + val SHARED_EN, LD_EN, ST_EN, MEMADDR, BANK_ID, SPECIAL, VALID = Value } // Default constants for Mem decoder object MemDefaultConstants { val Y = true.B val N = false.B - val DADDR = 0.U(14.W) - val DITER = 0.U(10.W) - val DSPECIAL = 0.U(40.W) + val DADDR = 0.U(15.W) + val DSPECIAL = 0.U(64.W) } @instantiable @@ -53,6 +51,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val bankAddrLen = log2Up(b.memDomain.bankEntries) val memAddrLen = b.memDomain.memAddrLen val bankIdLen = b.frontend.bank_id_len + val iterLen = b.frontend.iter_len // Only process Mem instructions io.cmd_i.ready := io.mem_decode_cmd_o.ready @@ -61,15 +60,14 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val rs1 = io.cmd_i.bits.cmd.rs1Data val rs2 = io.cmd_i.bits.cmd.rs2Data - // Load/Store instruction decoding - // New unified encoding: - // rs1[7:0] = bank_id - // rs1[26:24] = bank access valid flags (used by scoreboard, ignored here) - // rs1[63:27] = mem_addr (for MVIN/MVOUT) - // rs2[9:0] = iter - // rs2[63:10] = special + // Unified encoding: + // rs1[14:0] = bank_id (BANK0) + // rs1[45:47] = bank access valid flags (used by scoreboard, ignored here) + // rs1[63:48] = iter + // rs2[38:0] = mem_addr (for MVIN/MVOUT, 39-bit) + // rs2[63:0] = special (full 64-bit) import LSDecodeFields._ - val ls_default_decode = List(N, N, N, DADDR, DADDR, DITER, DSPECIAL, N) + val ls_default_decode = List(N, N, N, DADDR, DADDR, DSPECIAL, N) val ls_decode_list = ListLookup( func7, @@ -79,50 +77,45 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { N, N, N, - 0.U(memAddrLen.W), // mem_addr: not used for MSET - rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] - rs2(9, 0), // iter from rs2[9:0] - rs2(39, 0), // special from rs2[39:0] + 0.U(memAddrLen.W), // mem_addr: not used for MSET + rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs2, // special = full rs2 Y ), // mset MVIN_BITPAT -> List( N, Y, N, - rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits - rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] - rs2(9, 0), // iter from rs2[9:0] - rs2(63, 10), // special from rs2[63:10] + rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs2, // special = full rs2 Y ), // mvin MVOUT_BITPAT -> List( N, N, Y, - rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits - rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] - rs2(9, 0), // iter from rs2[9:0] - rs2(63, 10), // special from rs2[63:10] + rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs2, // special = full rs2 Y ), // mvout SHARED_MVIN_BITPAT -> List( Y, Y, N, - rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits - rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] - rs2(9, 0), // iter from rs2[9:0] - rs2(63, 10), // special from rs2[63:10] + rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs2, // special = full rs2 Y ), // shared mvin SHARED_MVOUT_BITPAT -> List( Y, N, Y, - rs1(memAddrLen + 26, 27), // mem_addr from rs1 upper bits - rs1(bankIdLen - 1, 0), // bank_id from rs1[bankIdLen-1:0] - rs2(9, 0), // iter from rs2[9:0] - rs2(63, 10), // special from rs2[63:10] + rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs2, // special = full rs2 Y ) // shared mvout ) @@ -164,10 +157,11 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { ls_decode_list(LSDecodeFields.MEMADDR.id).asUInt, 0.U(b.memDomain.memAddrLen.W) ) + // iter is always from rs1[63:48] io.mem_decode_cmd_o.bits.iter := Mux( io.mem_decode_cmd_o.valid, - ls_decode_list(LSDecodeFields.ITER.id).asUInt, - 0.U(10.W) + rs1(63, 48), + 0.U(iterLen.W) ) // Address parsing @@ -176,6 +170,6 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { io.mem_decode_cmd_o.bits.special := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.SPECIAL.id).asUInt, - 0.U(40.W) + 0.U(64.W) ) } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index a6986f49..fdb38045 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -37,7 +37,7 @@ class MemLoader(val b: GlobalConfig) extends Module { val rob_id_reg = RegInit(0.U(rob_id_width.W)) val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) - val iter_reg = Reg(UInt(10.W)) + val iter_reg = Reg(UInt(b.frontend.iter_len.W)) val resp_count = RegInit(0.U(log2Up(16).W)) val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) val stride_reg = Reg(UInt(11.W)) @@ -98,8 +98,8 @@ class MemLoader(val b: GlobalConfig) extends Module { rob_id_reg := io.cmdReq.bits.rob_id mem_addr_reg := io.cmdReq.bits.cmd.mem_addr wr_bank_reg := io.cmdReq.bits.cmd.bank_id - // BBReadRequest.stride is 10 bits wide - stride_reg := io.cmdReq.bits.cmd.special(10, 0) + // stride from rs2[57:39] + stride_reg := io.cmdReq.bits.cmd.special(57, 39) resp_count := 0.U pending := false.B latLast := false.B diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 68fa5403..7fdf8665 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -44,15 +44,15 @@ class MemStorer(val b: GlobalConfig) extends Module { val rob_id_reg = RegInit(0.U(rob_id_width.W)) val mem_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) - val iter_reg = RegInit(0.U(10.W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val stride_reg = RegInit(0.U(10.W)) val rd_bank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val group_count_reg = RegInit(1.U(4.W)) // Store group count for current operation val is_shared_reg = RegInit(false.B) // Address and group counters - val addr_counter = RegInit(0.U(10.W)) // Row address counter - val group_counter = RegInit(0.U(4.W)) // Group counter within a row + val addr_counter = RegInit(0.U(b.frontend.iter_len.W)) // Row address counter + val group_counter = RegInit(0.U(4.W)) // Group counter within a row // ----------------------------- // Pending buffer for SRAM resp @@ -81,7 +81,7 @@ class MemStorer(val b: GlobalConfig) extends Module { rob_id_reg := io.cmdReq.bits.rob_id mem_addr_reg := io.cmdReq.bits.cmd.mem_addr rd_bank_reg := io.cmdReq.bits.cmd.bank_id - stride_reg := io.cmdReq.bits.cmd.special(10, 0) + stride_reg := io.cmdReq.bits.cmd.special(57, 39) // Query and save group count group_count_reg := io.query_group_count diff --git a/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c b/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c index ba417b4c..1f5e3444 100644 --- a/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c @@ -5,9 +5,9 @@ #define BB_SHARED_MVIN_FUNC7 21 -#define bb_shared_mvin(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_WR | FIELD(mem_addr, 27, 58)), \ - (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_SHARED_MVIN_FUNC7) +#define bb_shared_mvin(mem_addr, bank_id, depth, stride) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_WR | BB_ITER(depth)), \ + (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ + BB_SHARED_MVIN_FUNC7) #endif // _BB_SHARED_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c b/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c index b755aa7b..31a7b045 100644 --- a/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c @@ -5,9 +5,9 @@ #define BB_SHARED_MVOUT_FUNC7 22 -#define bb_shared_mvout(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_RD0 | FIELD(mem_addr, 27, 58)), \ - (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_SHARED_MVOUT_FUNC7) +#define bb_shared_mvout(mem_addr, bank_id, depth, stride) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_RD0 | BB_ITER(depth)), \ + (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ + BB_SHARED_MVOUT_FUNC7) #endif // _BB_SHARED_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c index 1d1ea825..79198d99 100644 --- a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/24_mvin.c @@ -6,8 +6,8 @@ #define BB_MVIN_FUNC7 24 #define bb_mvin(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_WR | FIELD(mem_addr, 27, 58)), \ - (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_MVIN_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_WR | BB_ITER(depth)), \ + (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ + BB_MVIN_FUNC7) #endif // _BB_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c index 26d50c6c..4fa645c0 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/25_mvout.c @@ -6,8 +6,8 @@ #define BB_MVOUT_FUNC7 25 #define bb_mvout(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_RD0 | FIELD(mem_addr, 27, 58)), \ - (FIELD(depth, 0, 9) | FIELD(stride, 10, 28)), BB_MVOUT_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_RD0 | BB_ITER(depth)), \ + (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ + BB_MVOUT_FUNC7) #endif // _BB_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c index 761fa236..5ebedc37 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c @@ -7,8 +7,8 @@ #define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ - (FIELD(iter, 0, 9) | FIELD(mode, 10, 63)), \ - BB_MUL_WARP16_FUNC7) + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ + BB_ITER(iter)), \ + (FIELD(mode, 0, 63)), BB_MUL_WARP16_FUNC7) #endif // _BB_MUL_WARP16_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c index 2b999746..be296040 100644 --- a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c +++ b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c @@ -6,8 +6,8 @@ #define BB_TRANSPOSE_FUNC7 34 #define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ - (FIELD(iter, 0, 9) | FIELD(mode, 10, 63)), BB_TRANSPOSE_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | \ + BB_RD0 | BB_WR | BB_ITER(iter)), \ + (FIELD(mode, 0, 63)), BB_TRANSPOSE_FUNC7) #endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/38_relu.c b/bb-tests/workloads/lib/bbhw/isa/38_relu.c index edb84a0a..a4271878 100644 --- a/bb-tests/workloads/lib/bbhw/isa/38_relu.c +++ b/bb-tests/workloads/lib/bbhw/isa/38_relu.c @@ -6,8 +6,8 @@ #define BB_RELU_FUNC7 38 #define bb_relu(bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ - (FIELD(iter, 0, 9)), BB_RELU_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ + BB_RD0 | BB_WR | BB_ITER(iter)), \ + 0, BB_RELU_FUNC7) #endif // _BB_RELU_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bfp.c b/bb-tests/workloads/lib/bbhw/isa/39_bfp.c index 924d0005..32f365e7 100644 --- a/bb-tests/workloads/lib/bbhw/isa/39_bfp.c +++ b/bb-tests/workloads/lib/bbhw/isa/39_bfp.c @@ -5,10 +5,10 @@ #define BB_BFP_FUNC7 39 -#define bb_BFP(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ +#define bb_BFP(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ - (FIELD(iter, 0, 9) | FIELD(mode, 10, 63)), \ - BB_BFP_FUNC7) + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ + BB_ITER(iter)), \ + (FIELD(mode, 0, 63)), BB_BFP_FUNC7) -#endif // _BB_BFP_H_ \ No newline at end of file +#endif // _BB_BFP_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/40_quant.c b/bb-tests/workloads/lib/bbhw/isa/40_quant.c index 95e59e35..338c62a0 100644 --- a/bb-tests/workloads/lib/bbhw/isa/40_quant.c +++ b/bb-tests/workloads/lib/bbhw/isa/40_quant.c @@ -7,12 +7,12 @@ // bb_quant(bank_id, wr_bank_id, iter, scale_fp32) // scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern -// Encoding: rs1 = BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR -// rs2 = FIELD(iter, 0, 9) | FIELD(scale_fp32, 10, 41) +// Encoding: rs1 = banks | enables | iter +// rs2 = scale_fp32 #define bb_quant(bank_id, wr_bank_id, iter, scale_fp32) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ - (FIELD(iter, 0, 9) | FIELD((uint64_t)(scale_fp32), 10, 41)), \ - BB_QUANT_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ + BB_RD0 | BB_WR | BB_ITER(iter)), \ + (FIELD((uint64_t)(scale_fp32), 0, 31)), \ + BB_QUANT_FUNC7) #endif // _BB_QUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_dequant.c b/bb-tests/workloads/lib/bbhw/isa/41_dequant.c index 4f4d907a..dd268d04 100644 --- a/bb-tests/workloads/lib/bbhw/isa/41_dequant.c +++ b/bb-tests/workloads/lib/bbhw/isa/41_dequant.c @@ -7,12 +7,12 @@ // bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) // scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern -// Encoding: rs1 = BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR -// rs2 = FIELD(iter, 0, 9) | FIELD(scale_fp32, 10, 41) +// Encoding: rs1 = banks | enables | iter +// rs2 = FIELD(scale_fp32, 0, 31) #define bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ - (FIELD(iter, 0, 9) | FIELD((uint64_t)(scale_fp32), 10, 41)), \ - BB_DEQUANT_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ + BB_RD0 | BB_WR | BB_ITER(iter)), \ + (FIELD((uint64_t)(scale_fp32), 0, 31)), \ + BB_DEQUANT_FUNC7) #endif // _BB_DEQUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c b/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c index 4b0f29a8..ae5cd61f 100644 --- a/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c +++ b/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c @@ -6,15 +6,19 @@ #define BB_GEMMINI_CONFIG_FUNC7 42 // Configure Gemmini systolic array +// All config parameters go in rs2 (special), starting from bit 4 +// (bits [3:0] reserved for sub-command tag in decoder) // dataflow: 0=OS, 1=WS // activation: 0=none, 1=relu // a_transpose, b_transpose: transpose flags // in_shift: right-shift amount for output #define bb_gemmini_config(dataflow, activation, a_transpose, b_transpose, \ in_shift) \ - BUCKYBALL_INSTRUCTION_R_R((FIELD(dataflow, 2, 2) | FIELD(activation, 3, 4) | \ - FIELD(a_transpose, 8, 8) | \ - FIELD(b_transpose, 9, 9)), \ - (FIELD(in_shift, 0, 31)), BB_GEMMINI_CONFIG_FUNC7) + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(dataflow, 4, 4) | FIELD(activation, 5, 6) | \ + FIELD(a_transpose, 7, 7) | \ + FIELD(b_transpose, 8, 8) | \ + FIELD(in_shift, 9, 40)), \ + BB_GEMMINI_CONFIG_FUNC7) #endif // _BB_GEMMINI_CONFIG_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c b/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c index 468e7aa5..0d07bfeb 100644 --- a/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c +++ b/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c @@ -10,8 +10,8 @@ // wr_bank_id: destination bank for C output // iter: number of rows to preload #define bb_gemmini_preload(op1_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ - (FIELD(iter, 0, 9)), BB_GEMMINI_PRELOAD_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | \ + BB_RD0 | BB_WR | BB_ITER(iter)), \ + 0, BB_GEMMINI_PRELOAD_FUNC7) #endif // _BB_GEMMINI_PRELOAD_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c b/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c index 68f5af06..609edf5b 100644 --- a/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c +++ b/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c @@ -13,8 +13,8 @@ #define bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, wr_bank_id, \ iter) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ - (FIELD(iter, 0, 9)), \ - BB_GEMMINI_COMPUTE_PRELOADED_FUNC7) + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ + BB_ITER(iter)), \ + 0, BB_GEMMINI_COMPUTE_PRELOADED_FUNC7) #endif // _BB_GEMMINI_COMPUTE_PRELOADED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c b/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c index 3de78f3d..d3e25a9e 100644 --- a/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c +++ b/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c @@ -13,8 +13,8 @@ #define bb_gemmini_compute_accumulated(op1_bank_id, op2_bank_id, wr_bank_id, \ iter) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR), \ - (FIELD(iter, 0, 9)), \ - BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7) + BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ + BB_ITER(iter)), \ + 0, BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7) #endif // _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 3fd7cebf..0cb2c7b7 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -21,16 +21,19 @@ typedef int32_t result_t; #define FIELD(val, start_bit, end_bit) \ (((val) & ((1UL << ((end_bit) - (start_bit) + 1)) - 1)) << (start_bit)) -// Unified rs1 bank encoding flags (bits 24-26) -// bit 24 = rd_bank_0_valid, bit 25 = rd_bank_1_valid, bit 26 = wr_bank_valid -#define BB_RD0 (1UL << 24) -#define BB_RD1 (1UL << 25) -#define BB_WR (1UL << 26) - -// rs1 bank field helpers -#define BB_BANK0(id) FIELD(id, 0, 7) -#define BB_BANK1(id) FIELD(id, 8, 15) -#define BB_BANK2(id) FIELD(id, 16, 23) +// Unified rs1 bank encoding flags (bits 45-47) +// bit 45 = rd_bank_0_valid, bit 46 = rd_bank_1_valid, bit 47 = wr_bank_valid +#define BB_RD0 (1UL << 45) +#define BB_RD1 (1UL << 46) +#define BB_WR (1UL << 47) + +// rs1 bank field helpers (15-bit each) +#define BB_BANK0(id) FIELD(id, 0, 14) +#define BB_BANK1(id) FIELD(id, 15, 29) +#define BB_BANK2(id) FIELD(id, 30, 44) + +// rs1 iter field (16-bit, bits 48-63) +#define BB_ITER(n) FIELD(n, 48, 63) // Generic RISC-V custom instruction macro #define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ From 7652a4481f6aec450261a24372214e8ef6ea2ded Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 9 Mar 2026 16:13:48 +0800 Subject: [PATCH 156/238] [bbAgent] add skills for ball creation and registration checks [arch] implement PMC tracing for Ball and Memory operations --- .claude/.gitignore | 3 +- .claude/CLAUDE.md | 16 +- .claude/commands/ball.md | 73 ----- .claude/commands/check.md | 11 - .claude/commands/optimize.md | 84 ------ .claude/commands/verify.md | 49 --- .claude/skills/ball/SKILL.md | 285 ++++++++++++++++++ .claude/skills/check/SKILL.md | 42 +++ .claude/skills/debug/SKILL.md | 116 +++++++ .claude/skills/optimize/SKILL.md | 116 +++++++ .claude/skills/verify/SKILL.md | 59 ++++ .claude/skills/waveform/SKILL.md | 139 +++++++++ README.md | 2 +- arch/src/csrc/include/monitor/trace.h | 10 + arch/src/csrc/src/monitor/trace/pmctrace.cc | 49 +++ .../balldomain/bbus/pmc/BallCyclePMC.scala | 16 +- .../balldomain/bbus/pmc/PMCTraceDPI.scala | 39 +++ .../frontend/globalrs/GlobalROB.scala | 6 - .../memdomain/utils/pmc/MemCyclePMC.scala | 26 +- .../memdomain/utils/pmc/MemPMCTraceDPI.scala | 39 +++ bb-tests/workloads/lib/bbhw/isa/isa.h | 2 +- docs | 2 +- 22 files changed, 953 insertions(+), 231 deletions(-) delete mode 100644 .claude/commands/ball.md delete mode 100644 .claude/commands/check.md delete mode 100644 .claude/commands/optimize.md delete mode 100644 .claude/commands/verify.md create mode 100644 .claude/skills/ball/SKILL.md create mode 100644 .claude/skills/check/SKILL.md create mode 100644 .claude/skills/debug/SKILL.md create mode 100644 .claude/skills/optimize/SKILL.md create mode 100644 .claude/skills/verify/SKILL.md create mode 100644 .claude/skills/waveform/SKILL.md create mode 100644 arch/src/csrc/src/monitor/trace/pmctrace.cc create mode 100644 arch/src/main/scala/framework/balldomain/bbus/pmc/PMCTraceDPI.scala create mode 100644 arch/src/main/scala/framework/memdomain/utils/pmc/MemPMCTraceDPI.scala diff --git a/.claude/.gitignore b/.claude/.gitignore index adda676e..1b6c8fc3 100644 --- a/.claude/.gitignore +++ b/.claude/.gitignore @@ -1,3 +1,4 @@ * -!commands/ +!skills/ +!skills/**/* !CLAUDE.md diff --git a/.claude/CLAUDE.md b/.claude/CLAUDE.md index d0ee951e..28ea2439 100644 --- a/.claude/CLAUDE.md +++ b/.claude/CLAUDE.md @@ -58,7 +58,7 @@ SramWriteIO: req.valid/ready + req.bits(addr, data, mask, wmode) → resp.vali 5. `busRegister.scala` 中的 case 名称集合 == `default.json` 中的 ballName 集合 6. `DomainDecoder.scala` 中的 BID 值集合 == `default.json` 中的 ballId 集合 -用 `/check` 命令可以自动检查所有不变量。 +用 `/check` skill 可以自动检查所有不变量并可选自动修复。 ## MCP 工具 @@ -87,6 +87,20 @@ bbdev CLI 是给人类程序员用的，MCP 工具是给 agent 用的——MCP - 时序报告：`bbdev/api/steps/yosys/log/timing_report.txt` - 覆盖率报告：`bb-tests/sardine/reports/coverage/html/` - 仿真日志：`arch/log//stdout.log`、`disasm.log` +- bdb 调试日志：`arch/log//bdb.log`，包含三种 DPI-C trace： + - `[ITRACE]` — 指令发射/完成 + - `[MTRACE]` — SRAM 读写 + - `[PMCTRACE]` — Ball/Mem 性能计数（elapsed cycles） + +## Skills + +项目 skill 位于 `.claude/skills/` 下： +- `/ball` — 创建新 Ball 算子（全流程：实现→注册→ISA→CTest→仿真） +- `/check` — 注册状态校验 + 自动修复 +- `/verify` — Ball 功能验证（编译→仿真→覆盖率→PMC 分析） +- `/optimize` — RTL 模块面积/延迟优化（适用于任意模块，不限 Ball） +- `/debug` — 仿真调试（日志分析→波形→故障模式库） +- `/waveform` — 波形分析（waveform-mcp 使用指南） ## 约定 diff --git a/.claude/commands/ball.md b/.claude/commands/ball.md deleted file mode 100644 index 72b6aeb3..00000000 --- a/.claude/commands/ball.md +++ /dev/null @@ -1,73 +0,0 @@ -创建一个名为 $ARGUMENTS 的新 Buckyball Ball 算子，完成从实现到验证的全流程。 - -**重要：编译、仿真等操作必须通过 MCP 工具（validate、bbdev_workload_build、bbdev_verilator_run 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** - -## 阶段 1 — 需求收集 - -1. 读取当前注册状态，确定新 Ball 的 ballId 和 funct7： - - `arch/src/main/scala/framework/balldomain/configs/default.json` - - `arch/src/main/scala/examples/toy/balldomain/DISA.scala` -2. 向用户确认以下信息： - - Ball 的计算语义（做什么运算） - - inBW / outBW（读/写 bank 端口数量） - - 是否需要第二个操作数（op2） - - iter（迭代次数）的含义 - -## 阶段 2 — 实现 Ball - -1. 读取参考代码，理解 Blink 协议和现有 Ball 的写法： - - 简单参考：`arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala` 和 `Relu.scala` - - 复杂参考：`arch/src/main/scala/framework/balldomain/prototype/systolicarray/` - - Blink 协议：`arch/src/main/scala/framework/balldomain/blink/blink.scala`、`bank.scala`、`status.scala` - - SRAM 接口：`arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala` -2. 在 `arch/src/main/scala/framework/balldomain/prototype//` 下创建： - - `Ball.scala` — wrapper，extends Module with HasBlink，从 ballIdMappings 取 inBW/outBW，实例化 core，连接 BlinkIO - - `.scala` — core 计算逻辑，包含 FSM 和数据通路 - - `configs/BallParam.scala` — 算子参数 case class - - `configs/default.json` — 算子专属配置 - -关键约束： -- SRAM 读延迟 = 1 cycle（req.fire 后下一周期 resp.valid） -- cmdReq.fire 时 latch 命令字段到寄存器 -- FSM 基本模式：idle → 读数据 → 计算 → 写数据 → complete → idle -- status.idle 和 status.running 必须映射 FSM 状态 - -## 阶段 3 — 注册 - -按顺序更新以下四个文件： -1. `arch/src/main/scala/framework/balldomain/configs/default.json` — 追加 ballIdMappings 条目，更新 ballNum -2. `arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala` — 添加 import 和 match case -3. `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — 添加 `val XXX = BitPat("bxxxxxxx")` -4. `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — 添加 ListLookup 解码行，BID = ballId.U - -## 阶段 4 — ISA C 宏 - -1. 在 `bb-tests/workloads/lib/bbhw/isa/` 下创建 `_.c` - - 定义 `BB__FUNC7` 宏（funct7 十进制值） - - 定义 `bb_(...)` 宏（编码 rs1/rs2 + 调用 BUCKYBALL_INSTRUCTION_R_R） - - 参考：`bb-tests/workloads/lib/bbhw/isa/38_relu.c` -2. 在 `bb-tests/workloads/lib/bbhw/isa/isa.h` 中 `#include` 新文件 - -## 阶段 5 — CTest - -1. 在 `bb-tests/workloads/src/CTest/toy/` 下创建 `_test.c` - - 包含固定输入矩阵和预期输出矩阵 - - 遵循 bb_mem_alloc → bb_mvin → bb_ → bb_mvout → bb_fence 流程 - - compare 判定 PASS/FAIL - - 参考：`bb-tests/workloads/src/CTest/toy/relu_test.c` -2. 在 `bb-tests/workloads/src/CTest/toy/CMakeLists.txt` 中用 `add_cross_platform_test_target` 注册 -3. 在 `bb-tests/sardine/tests/test_ctest.py` 的 `ctest_workloads` 列表中追加对应条目 - -## 阶段 6 — 校验 + 编译 + 仿真 - -1. 调用 MCP 工具 `validate` 做静态校验，确认 6 项不变量全部通过 -2. 调用 MCP 工具 `bbdev_workload_build` 编译 CTest -3. 调用 MCP 工具 `bbdev_verilator_run` 跑仿真，指定新 Ball 的 CTest binary -4. 解析仿真结果： - - PASSED → 完成 - - FAILED → 进入调试： - a. 找到日志目录（MCP 返回的 `log_dir`，或 `ls -t arch/log/ | head -5`） - b. 读取 `stdout.log`（程序输出）、`disasm.log`（反汇编）、**`bdb.log`（Ball 硬件调试日志，最重要）** - c. 在 bdb.log 中搜索 Ball 名称，检查 SRAM 读写地址/数据、bank_id 分配、iter 次数 - d. 结合 Chisel 源码定位问题并修复 - e. 重新通过 MCP 工具编译和仿真验证 diff --git a/.claude/commands/check.md b/.claude/commands/check.md deleted file mode 100644 index 62bc9ed3..00000000 --- a/.claude/commands/check.md +++ /dev/null @@ -1,11 +0,0 @@ -对 Buckyball Ball 注册状态做静态校验。 - -调用 MCP 工具 `validate`，检查以下 6 项注册不变量： -1. ballNum == ballIdMappings 数组长度 -2. ballId 严格递增 -3. ballId 无重复 -4. DISA.scala funct7 无重复 -5. busRegister.scala case 名称与 default.json ballName 一致 -6. DomainDecoder.scala BID 与 default.json ballId 一致 - -每项报告 pass/fail 状态。如果有失败项，分析原因并给出修复建议。 diff --git a/.claude/commands/optimize.md b/.claude/commands/optimize.md deleted file mode 100644 index 28735f5b..00000000 --- a/.claude/commands/optimize.md +++ /dev/null @@ -1,84 +0,0 @@ -分析并优化名为 $ARGUMENTS 的 Ball 的延迟和面积。 - -**重要：综合、仿真等操作必须通过 MCP 工具（bbdev_yosys_synth、bbdev_verilator_run、bbdev_workload_build 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** - -## 阶段 1 — 基线测量 - -1. 调用 MCP 工具 `bbdev_yosys_synth` 跑 Yosys 综合 + OpenSTA 时序分析 -2. 读取面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解） -3. 读取时序报告：`bbdev/api/steps/yosys/log/timing_report.txt`（关键路径） -4. 检查该 Ball 的 CTest 中是否有 `read_rdcycle()` 计时代码 - - 如果有：调用 `bbdev_verilator_run` 跑仿真获取基线 cycle 数 - - 如果没有：自动在 CTest 中加入 read_rdcycle() 前后对比代码，调用 `bbdev_workload_build` 重新编译，再调用 `bbdev_verilator_run` 获取基线 cycle 数 - -## 阶段 2 — 面积分析 - -从 hierarchy_report.txt 提取目标 Ball 及其子模块的面积数据： -- 总面积（Chip area） -- Sequential 占比（寄存器面积） -- Combinational 占比（组合逻辑面积） -- 子模块面积排名 - -识别面积大户： -- Sequential 占比高 → 寄存器多，考虑是否可用 SRAM 替代 -- Combinational 占比高 → 逻辑复杂，考虑是否可以简化或共享 - -对比同类 Ball 面积（如 ReluBall vs TransposeBall），找出效率差距。 - -## 阶段 3 — 时序/延迟分析 - -1. 从 timing_report.txt 看关键路径是否经过该 Ball，以及路径延迟 -2. 从仿真结果看操作延迟（cycle 数） -3. 读取 Ball 的 Chisel core 源码，分析 FSM： - - 绘制 FSM 状态转移图 - - 计算每个状态的 cycle 数（最佳/最坏情况） - - 识别瓶颈状态（哪个状态耗时最多） - - 分析 SRAM 读写模式（串行 vs 流水 vs 多端口并行） - -## 阶段 4 — 优化方案 - -提出可量化的优化方案，每个方案包含： -- 优化手段描述 -- 预期面积变化（参考 hierarchy_report 数据量化） -- 预期延迟变化（cycle 数） -- 预期频率影响 -- trade-off 说明 - -常见优化模式： - -**降延迟**： -- 读写流水化：让写操作和下一轮读操作重叠，面积略增，延迟显著降 -- 多 bank 端口并行读：利用 inBW > 1 同时读多行，面积不变，延迟与端口数成比例降 -- 去中间等待状态：合并不必要的 FSM 状态，面积略降 -- 边读边算：计算嵌入读响应周期，利用 SRAM 1-cycle 延迟的下降沿做计算 - -**降面积**： -- regArray 改 SRAM：大块寄存器阵列换成 SRAM 端口访问，面积显著降，可能增延迟 -- 共享计算单元：多操作时分复用同一计算单元，面积降，延迟可能增 -- 减少 counter 位宽：根据实际范围缩减位宽，面积微降 - -**提频率**： -- 拆分组合逻辑长路径：在关键路径中间插入寄存器，面积略增，可能增 1 cycle 延迟 - -列出方案后让用户选择。 - -## 阶段 5 — 实施 - -根据用户选择的方案修改 Chisel 代码。 - -## 阶段 6 — 优化后测量 - -1. 再次调用 `bbdev_yosys_synth`，对比 hierarchy_report -2. 再次调用 `bbdev_verilator_run`，对比 cycle 数 -3. 调用 `validate` 确认注册一致性未被破坏 -4. 输出优化前后对比报告： - - 面积差值和百分比变化 - - Cycle 数差值和百分比变化 - - 关键路径延迟变化 - - 频率变化 - -## 故障排查 - -如果 MCP 工具返回 HTTP 500 或 returncode=1： -- 读取 `bbdev/server.log` — bbdev server 的运行日志，包含 Chisel 编译错误、mill 构建错误等详细堆栈信息 -- 该日志特别有助于诊断 elaborate 失败（如类型不匹配、缺少注册等编译期错误） diff --git a/.claude/commands/verify.md b/.claude/commands/verify.md deleted file mode 100644 index a629547c..00000000 --- a/.claude/commands/verify.md +++ /dev/null @@ -1,49 +0,0 @@ -验证名为 $ARGUMENTS 的 Ball 的功能正确性。 - -**重要：编译、仿真、测试等操作必须通过 MCP 工具（bbdev_workload_build、bbdev_verilator_run、bbdev_sardine_run 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** - -## 阶段 1 — 完整性检查 - -检查以下各项是否存在，缺什么补什么： -1. Ball 是否在 `arch/src/main/scala/framework/balldomain/configs/default.json` 中注册 -2. ISA 宏是否存在：`bb-tests/workloads/lib/bbhw/isa/` 下对应的 .c 文件 -3. CTest 是否存在：`bb-tests/workloads/src/CTest/toy/` 下对应的 _test.c 文件 -4. sardine 列表是否包含：`bb-tests/sardine/tests/test_ctest.py` 的 ctest_workloads 列表 - -## 阶段 2 — 编译 + 仿真 - -1. 调用 MCP 工具 `bbdev_workload_build` 编译所有 CTest -2. 调用 MCP 工具 `bbdev_verilator_run` 仿真该 Ball 的 CTest - - binary 名称格式：`ctest__test_singlecore-baremetal` - - 设置 batch=true -3. 如果编译或仿真失败，分析错误并修复 - -## 阶段 3 — 覆盖率分析 - -1. 调用 MCP 工具 `bbdev_sardine_run`，设置 coverage=true -2. 读取覆盖率报告：`bb-tests/sardine/reports/coverage/html/` 和 `bb-tests/sardine/reports/coverage/annotated/` -3. 分析该 Ball 的 RTL 行覆盖情况 -4. 如果覆盖率不足，建议或自动补充测试用例，补充后重新编译和仿真验证 - -## 阶段 4 — 失败分析（如有） - -如果仿真结果为 FAILED： - -1. **找到日志目录**：MCP 工具返回的 JSON 中包含 `log_dir` 字段，如 `arch/log/2026-03-07-12-00-ctest_xxx/` - - 如果 MCP 返回中没有 `log_dir`，用 `ls -t arch/log/ | head -5` 找最近的日志目录 - -2. **读取关键日志**： - - `arch/log//stdout.log` — 程序标准输出，包含 PASSED/FAILED 和 printf 输出 - - `arch/log//disasm.log` — 反汇编指令流，可以看到实际执行了哪些指令 - - `arch/log//bdb.log` — **Buckyball 调试日志**，包含 Ball 内部状态变化、SRAM 读写请求/响应、FSM 状态转移等硬件级信息。这是定位 Ball 逻辑错误最重要的日志 - - `bbdev/server.log` — bbdev server 的运行日志，包含 Chisel 编译错误、mill 构建错误等详细堆栈信息 - -3. **分析 bdb.log 的方法**： - - 搜索目标 Ball 的名称，找到相关的命令发射和完成事件 - - 检查 SRAM 读写地址和数据是否正确 - - 检查 bank_id 分配是否和 CTest 中 bb_mem_alloc 一致 - - 检查迭代次数（iter）是否正确 - -4. 结合日志分析 Ball 的 Chisel 源码，定位时序或逻辑问题 -5. 提出修复方案并实施 -6. 重新编译和仿真验证修复结果（通过 MCP 工具） diff --git a/.claude/skills/ball/SKILL.md b/.claude/skills/ball/SKILL.md new file mode 100644 index 00000000..416dea2b --- /dev/null +++ b/.claude/skills/ball/SKILL.md @@ -0,0 +1,285 @@ +--- +name: ball +description: 创建一个名为 $ARGUMENTS 的新 Buckyball Ball 算子，完成从实现到验证的全流程。当用户要求创建新 Ball、新算子、新加速单元，或说"加一个 XX Ball"、"实现 XX 操作"时，使用此 skill。即使用户没有明确说"Ball"，只要意图是在 Buckyball 框架中增加一个新的计算算子，都应触发。 +--- + +**重要：编译、仿真等操作必须通过 MCP 工具（validate、bbdev_workload_build、bbdev_verilator_run 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 阶段 1 — 需求收集 + +1. 读取当前注册状态，确定新 Ball 的 ballId 和 funct7： + - `arch/src/main/scala/framework/balldomain/configs/default.json` + - `arch/src/main/scala/examples/toy/balldomain/DISA.scala` +2. 检查是否已部分存在（增量模式）： + - 搜索 `arch/src/main/scala/framework/balldomain/prototype/` 下是否有同名目录 + - 搜索 `bb-tests/workloads/lib/bbhw/isa/` 下是否有对应的 ISA 宏文件 + - 搜索 `bb-tests/workloads/src/CTest/toy/` 下是否有对应的 CTest + - 如果部分文件已存在，只补齐缺失部分 +3. 向用户确认以下信息： + - Ball 的计算语义（做什么运算） + - inBW / outBW（读/写 bank 端口数量） + - 是否需要第二个操作数（op2） + - iter（迭代次数）的含义 + +## 阶段 2 — 实现 Ball + +1. 读取参考代码，理解 Blink 协议和现有 Ball 的写法： + - 简单参考：`arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala` 和 `Relu.scala` + - 复杂参考：`arch/src/main/scala/framework/balldomain/prototype/systolicarray/` + - Blink 协议：`arch/src/main/scala/framework/balldomain/blink/blink.scala`、`bank.scala`、`status.scala` + - SRAM 接口：`arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala` +2. 在 `arch/src/main/scala/framework/balldomain/prototype//` 下创建文件，使用 `references/` 中的模板作为起点。 + +### Ball wrapper 模板（`Ball.scala`） + +```scala +package framework.balldomain.prototype. + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.top.GlobalConfig + +@instantiable +class Ball(val b: GlobalConfig) extends Module with HasBlink { + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "Ball") + .getOrElse(throw new IllegalArgumentException("Ball not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + def blink: BlinkIO = io + + val core: Instance[] = Instantiate(new (b)) + + core.io.cmdReq <> io.cmdReq + core.io.cmdResp <> io.cmdResp + for (i <- 0 until inBW) { core.io.bankRead(i) <> io.bankRead(i) } + for (i <- 0 until outBW) { core.io.bankWrite(i) <> io.bankWrite(i) } + io.status <> core.io.status +} +``` + +### Core 模板（`.scala`） + +```scala +package framework.balldomain.prototype. + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.top.GlobalConfig + +@instantiable +class (val b: GlobalConfig) extends Module { + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "Ball") + .getOrElse(throw new IllegalArgumentException("Ball not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + // Latch rob_id on cmdReq.fire + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { rob_id_reg := io.cmdReq.bits.rob_id } + + // Propagate rob_id to bank metadata + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + } + + // FSM: idle -> read -> compute -> write -> complete -> idle + val idle :: sRead :: sCompute :: sWrite :: complete :: Nil = Enum(5) + val state = RegInit(idle) + + // Default port assignments (override in FSM states) + for (i <- 0 until inBW) { + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + io.bankRead(i).bank_id := 0.U + io.bankRead(i).group_id := 0.U + } + for (i <- 0 until outBW) { + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B + io.bankWrite(i).bank_id := 0.U + io.bankWrite(i).group_id := 0.U + } + + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + // Latch command fields + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) + + switch(state) { + is(idle) { + when(io.cmdReq.fire) { + rbank_reg := io.cmdReq.bits.cmd.op1_bank + wbank_reg := io.cmdReq.bits.cmd.wr_bank + iter_reg := io.cmdReq.bits.cmd.iter + state := sRead + } + } + is(sRead) { + // TODO: implement read logic + // Key: SRAM read latency = 1 cycle (resp.valid on next cycle after req.fire) + } + is(sCompute) { + // TODO: implement compute logic + } + is(sWrite) { + // TODO: implement write logic + } + is(complete) { + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + when(io.cmdResp.fire) { state := idle } + } + } + + io.status.idle := (state === idle) + io.status.running := (state =/= idle) && (state =/= complete) +} +``` + +### Param 模板（`configs/BallParam.scala`） + +```scala +package framework.balldomain.prototype..configs + +import upickle.default._ + +case class BallParam( + // TODO: add Ball-specific parameters +) + +object BallParam { + implicit val rw: ReadWriter[BallParam] = macroRW + + def apply(): BallParam = { + val jsonStr = scala.io.Source + .fromFile("src/main/scala/framework/balldomain/prototype//configs/default.json") + .mkString + read[BallParam](jsonStr) + } +} +``` + +关键约束： +- SRAM 读延迟 = 1 cycle（req.fire 后下一周期 resp.valid） +- cmdReq.fire 时 latch 命令字段到寄存器 +- FSM 基本模式：idle → 读数据 → 计算 → 写数据 → complete → idle +- status.idle 和 status.running 必须映射 FSM 状态 + +## 阶段 3 — 注册 + +按顺序更新以下四个文件： +1. `arch/src/main/scala/framework/balldomain/configs/default.json` — 追加 ballIdMappings 条目，更新 ballNum +2. `arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala` — 添加 import 和 match case +3. `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — 添加 `val XXX = BitPat("bxxxxxxx")` +4. `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — 添加 ListLookup 解码行，BID = ballId.U + +## 阶段 4 — ISA C 宏 + +在 `bb-tests/workloads/lib/bbhw/isa/` 下创建 `_.c`： + +```c +#ifndef _BB__H_ +#define _BB__H_ + +#include "isa.h" + +#define BB__FUNC7 + +#define bb_(bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ + BB_RD0 | BB_WR | BB_ITER(iter)), \ + 0, BB__FUNC7) + +#endif // _BB__H_ +``` + +在 `bb-tests/workloads/lib/bbhw/isa/isa.h` 中 `#include` 新文件。 + +## 阶段 5 — CTest + +在 `bb-tests/workloads/src/CTest/toy/` 下创建 `_test.c`： + +```c +#include "buckyball.h" +#include +#include +#include +#include +#include + +#define DIM 16 + +// Fixed input and expected output matrices +static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))) = { /* ... */ }; +static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { /* ... */ }; +static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); + +void hw_(const char *test_name, elem_t *a, elem_t *b, int size) { + uint32_t op1_bank_id = 0; + uint32_t wr_bank_id = 1; + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); + + bb_mvin((uintptr_t)a, op1_bank_id, size, 1); + bb_(op1_bank_id, wr_bank_id, size); + bb_mvout((uintptr_t)b, wr_bank_id, size, 1); + bb_fence(); +} + +int main() { + clear_i8_matrix(output_matrix, DIM, DIM); + hw_("", input_matrix, output_matrix, DIM); + + if (compare_i8_matrices(output_matrix, expected_matrix, DIM, DIM)) { + printf(" test PASSED\n"); + return 0; + } else { + printf(" test FAILED\n"); + return 1; + } +} +``` + +在 `bb-tests/workloads/src/CTest/toy/CMakeLists.txt` 中用 `add_cross_platform_test_target` 注册。 +在 `bb-tests/sardine/tests/test_ctest.py` 的 `ctest_workloads` 列表中追加对应条目。 + +## 阶段 6 — 校验 + 编译 + 仿真 + +1. 调用 MCP 工具 `validate` 做静态校验，确认 6 项不变量全部通过 +2. 调用 MCP 工具 `bbdev_workload_build` 编译 CTest +3. 调用 MCP 工具 `bbdev_verilator_run` 跑仿真，指定新 Ball 的 CTest binary +4. 解析仿真结果： + - PASSED → 完成 + - FAILED → 使用 `/debug` skill 进入调试流程 diff --git a/.claude/skills/check/SKILL.md b/.claude/skills/check/SKILL.md new file mode 100644 index 00000000..6ffc9edd --- /dev/null +++ b/.claude/skills/check/SKILL.md @@ -0,0 +1,42 @@ +--- +name: check +description: 对 Buckyball Ball 注册状态做静态校验，并可选自动修复不一致。当用户要求检查注册状态、校验 Ball 配置、排查注册问题，或在修改注册文件后需要验证一致性时使用此 skill。 +--- + +## 校验流程 + +调用 MCP 工具 `validate`，检查以下 6 项注册不变量： +1. ballNum == ballIdMappings 数组长度 +2. ballId 严格递增（0, 1, 2, ...），不跳号 +3. ballId 无重复 +4. DISA.scala funct7 无重复 +5. busRegister.scala case 名称与 default.json ballName 一致 +6. DomainDecoder.scala BID 与 default.json ballId 一致 + +每项报告 pass/fail 状态。 + +## 注册状态概览 + +校验后生成一张汇总表，展示当前所有 Ball 的注册信息。数据源： + +- `arch/src/main/scala/framework/balldomain/configs/default.json` — ballId, ballName, inBW, outBW +- `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — funct7 值 +- `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — 解码行中的 BID + +表格格式： + +| ballId | ballName | funct7 | inBW | outBW | DISA | busReg | Decoder | +|--------|----------|--------|------|-------|------|--------|---------| +| 0 | VecBall | 32 | 2 | 4 | ok | ok | ok | +| ... | ... | ... | ... | ... | ... | ... | ... | + +## 自动修复 + +如果校验发现不一致，且属于以下可确定性修复的类型，提示用户是否自动修复： + +1. **ballNum 不匹配** — 自动将 ballNum 更新为 ballIdMappings 数组长度 +2. **ballId 不连续** — 自动重编号为 0, 1, 2, ...（同步更新 DomainDecoder.scala 中的 BID） +3. **busRegister.scala 缺少 case** — 提示缺少哪些 Ball，给出需要添加的 import 和 match case 代码 +4. **DomainDecoder.scala BID 不一致** — 自动更新 BID 值与 default.json 匹配 + +对于无法自动修复的问题（如 funct7 冲突），给出原因分析和手动修复建议。 diff --git a/.claude/skills/debug/SKILL.md b/.claude/skills/debug/SKILL.md new file mode 100644 index 00000000..62bac63d --- /dev/null +++ b/.claude/skills/debug/SKILL.md @@ -0,0 +1,116 @@ +--- +name: debug +description: 系统性调试 Buckyball 仿真失败。当仿真返回 FAILED、CTest 测试不通过、Chisel 编译报错，或用户报告 Ball 行为异常时使用此 skill。涵盖日志分析、波形分析、常见故障模式匹配。即使用户只是说"仿真失败了"或"跑不过"也应触发。 +--- + +**重要：编译、仿真等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 第一步 — 定位日志 + +1. 找到日志目录： + - MCP 工具返回的 JSON 中包含 `log_dir` 字段 + - 如果没有，用 `ls -t arch/log/ | head -5` 找最近的日志目录 +2. 确认关键日志文件存在： + - `stdout.log` — 程序标准输出（PASSED/FAILED、printf） + - `disasm.log` — 反汇编指令流 + - `bdb.log` — Buckyball 硬件调试日志（最重要） + - `bbdev/server.log` — bbdev server 日志（编译错误在这里） + +## 第二步 — 分层分析 + +按照从高层到底层的顺序分析，先排除简单问题： + +### Level 1: 编译错误（bbdev/server.log） + +如果 MCP 工具返回 HTTP 500 或 returncode=1，先看 server.log： +- Chisel 编译错误（类型不匹配、缺少注册等） +- mill 构建错误（依赖问题） +- CTest 编译错误（C 语法、链接问题） + +### Level 2: 程序输出（stdout.log） + +- 搜索 `PASSED` / `FAILED` 确认测试结果 +- 搜索 `printf` 输出，检查实际值 vs 预期值 +- 搜索 `panic` / `abort` / `trap` 看是否有异常 + +### Level 3: 指令流（disasm.log） + +- 确认 Ball 的 custom 指令确实被执行了（搜索 `custom3`） +- 检查指令顺序是否正确（mvin → ball_op → mvout → fence） +- 检查是否有 trap 或 exception + +### Level 4: 硬件跟踪（bdb.log） + +这是定位 Ball 逻辑错误最重要的日志，包含三种 trace： + +**[ITRACE] 指令 trace：** +- `ISSUE rob_id=X domain=Y funct=0xZZ` — 指令发射 +- `COMPLETE rob_id=X` — 指令完成 +- 检查：指令是否被发射？是否完成？完成顺序是否正确？ + +**[MTRACE] 内存 trace：** +- `READ ch=X vbank=Y group=Z addr=0xAA` — SRAM 读 +- `WRITE ch=X vbank=Y group=Z addr=0xAA data=0x...` — SRAM 写 +- 检查：读写地址是否正确？数据是否正确？bank_id 是否匹配？ + +**[PMCTRACE] 性能计数 trace：** +- `BALL ball_id=X rob_id=Y elapsed=Z` — Ball 操作耗时 +- `LOAD/STORE rob_id=X elapsed=Y` — 内存操作耗时 +- 检查：elapsed 是否合理？是否有异常长的操作？ + +### Level 5: 波形分析（waveform-mcp） + +如果日志分析无法定位问题，使用 waveform-mcp 做 cycle-level 分析。详见 `/waveform` skill。 + +## 第三步 — 常见故障模式 + +### 1. Ball 没有响应（cmdResp 永远不 fire） +**症状：** 仿真超时或死锁，bdb.log 中有 ISSUE 但没有 COMPLETE +**原因：** +- FSM 卡在某个状态（检查 state 转移条件） +- SRAM resp.valid 没被处理（忘了 resp.ready := true.B） +- cmdResp.valid 没有被拉高 + +### 2. 数据全零 +**症状：** CTest 报 FAILED，输出矩阵全是 0 +**原因：** +- 写操作 addr 错误（waddr 没有递增） +- 写操作 mask 全零（忘了设置 mask := 1） +- bank_id 错误（写到了错误的 bank） + +### 3. 数据不变（输出 == 输入） +**症状：** CTest 报 FAILED，输出矩阵等于输入矩阵 +**原因：** +- 计算逻辑没有生效（跳过了 compute 状态） +- 读到的数据没有被处理就直接写回了 + +### 4. 部分数据错误 +**症状：** CTest 报 FAILED，部分行正确部分行错误 +**原因：** +- iter 次数计算错误（少读/少写了几行） +- 地址偏移量计算错误（行之间的 stride） +- 边界条件处理错误 + +### 5. SRAM 时序错误 +**症状：** 数据看起来"偏移了一行" +**原因：** +- SRAM 读延迟是 1 cycle，但代码在 req.fire 的同一个 cycle 就取了 resp.bits.data +- 正确做法：req.fire 后等一个 cycle，在下一个 cycle resp.valid 时读取数据 + +### 6. bank_id 冲突 +**症状：** assertion failure 或数据错乱 +**原因：** +- op1_bank 和 wr_bank 使用了同一个 bank（读写冲突） +- 多个 Ball 同时访问同一个 bank + +### 7. rob_id 不匹配 +**症状：** 指令完成顺序混乱 +**原因：** +- cmdResp.bits.rob_id 没有返回正确的 rob_id +- rob_id 没有在 cmdReq.fire 时被 latch + +## 第四步 — 修复 + 验证 + +1. 结合日志/波形分析定位到的问题，修改 Chisel 源码 +2. 重新通过 MCP 工具编译和仿真验证修复结果 +3. 如果修复引入新问题，回到第二步重新分析 diff --git a/.claude/skills/optimize/SKILL.md b/.claude/skills/optimize/SKILL.md new file mode 100644 index 00000000..ea59425e --- /dev/null +++ b/.claude/skills/optimize/SKILL.md @@ -0,0 +1,116 @@ +--- +name: optimize +description: 分析并优化名为 $ARGUMENTS 的 RTL 模块的延迟和面积。适用于任何 RTL 模块（Ball、MemFrontend、BBus、GlobalROB 等），不限于 Ball 算子。当用户要求优化某个模块的面积、延迟、时序、性能，或说"XX 太大了"、"XX 太慢了"、"分析一下 XX 的面积"时使用此 skill。 +--- + +**重要：综合、仿真等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 阶段 1 — 基线测量 + +1. 调用 MCP 工具 `bbdev_yosys_synth` 跑 Yosys 综合 + OpenSTA 时序分析 +2. 读取面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解） +3. 读取时序报告：`bbdev/api/steps/yosys/log/timing_report.txt`（关键路径） + +### hierarchy_report.txt 解析指引 + +报告格式为 Yosys `stat -top` 输出，关键字段： +- `Chip area for module` 行后面是每个子模块的面积分解 +- `Number of cells` — 单元数量 +- `Sequential` — 寄存器面积（flip-flops） +- `Combinational` — 组合逻辑面积 +- 搜索目标模块名定位其层次结构 + +### timing_report.txt 解析指引 + +OpenSTA 输出格式： +- `Startpoint:` / `Endpoint:` — 关键路径起止点 +- `Path Delay` — 路径延迟 +- `Slack` — 时序裕量（负值表示违约） +- 搜索目标模块名看是否在关键路径上 + +### 延迟测量 + +**如果是 Ball 模块：** +1. 检查仿真 bdb.log 中的 PMC trace 数据（`[PMCTRACE] BALL ball_id=X`），提取 elapsed cycles +2. 如果 CTest 中有 `read_rdcycle()` 计时代码，也可以从 stdout.log 获取 cycle 数 +3. 如果两者都没有，可以用 waveform-mcp 精确测量： + - 用 `find_conditional_events` 找 `cmdReq.valid && cmdReq.ready` 的时刻 + - 用 `find_conditional_events` 找 `cmdResp.valid` 的时刻 + - 两者之差即为操作延迟 + +**如果是其他模块：** +1. 用 waveform-mcp 在波形上测量关键操作的 cycle 数 +2. 或在 CTest 中加入 `read_rdcycle()` 前后对比代码 + +## 阶段 2 — 面积分析 + +从 hierarchy_report.txt 提取目标模块及其子模块的面积数据： +- 总面积（Chip area） +- Sequential 占比（寄存器面积） +- Combinational 占比（组合逻辑面积） +- 子模块面积排名 + +识别面积大户： +- Sequential 占比高 → 寄存器多，考虑是否可用 SRAM 替代 +- Combinational 占比高 → 逻辑复杂，考虑是否可以简化或共享 + +对比同类模块面积，找出效率差距。 + +## 阶段 3 — 时序/延迟分析 + +1. 从 timing_report.txt 看关键路径是否经过该模块，以及路径延迟 +2. 从 PMC trace 或波形数据看操作延迟（cycle 数） +3. 如果是 Ball 或有 FSM 的模块，读取 Chisel 源码分析 FSM： + - 绘制 FSM 状态转移图 + - 计算每个状态的 cycle 数（最佳/最坏情况） + - 识别瓶颈状态（哪个状态耗时最多） + - 分析 SRAM 读写模式（串行 vs 流水 vs 多端口并行） + +## 阶段 4 — 优化方案 + +提出可量化的优化方案，每个方案包含： +- 优化手段描述 +- 预期面积变化（参考 hierarchy_report 数据量化） +- 预期延迟变化（cycle 数） +- 预期频率影响 +- trade-off 说明 + +常见优化模式： + +**降延迟**： +- 读写流水化：让写操作和下一轮读操作重叠，面积略增，延迟显著降 +- 多 bank 端口并行读：利用 inBW > 1 同时读多行，面积不变，延迟与端口数成比例降 +- 去中间等待状态：合并不必要的 FSM 状态，面积略降 +- 边读边算：计算嵌入读响应周期，利用 SRAM 1-cycle 延迟的下降沿做计算 + +**降面积**： +- regArray 改 SRAM：大块寄存器阵列换成 SRAM 端口访问，面积显著降，可能增延迟 +- 共享计算单元：多操作时分复用同一计算单元，面积降，延迟可能增 +- 减少 counter 位宽：根据实际范围缩减位宽，面积微降 + +**提频率**： +- 拆分组合逻辑长路径：在关键路径中间插入寄存器，面积略增，可能增 1 cycle 延迟 + +列出方案后让用户选择。 + +## 阶段 5 — 实施 + +根据用户选择的方案修改 Chisel 代码。 + +## 阶段 6 — 优化后测量 + +1. 再次调用 `bbdev_yosys_synth`，对比 hierarchy_report +2. 如果有 CTest，再次调用 `bbdev_verilator_run` 跑仿真，对比 PMC trace 中的 cycle 数 +3. 调用 `validate` 确认注册一致性未被破坏 +4. 输出优化前后对比报告： + +| 指标 | 优化前 | 优化后 | 变化 | +|------|--------|--------|------| +| 面积 | X | Y | -Z% | +| Cycle 数 | A | B | -C% | +| 关键路径延迟 | D | E | -F% | + +## 故障排查 + +如果 MCP 工具返回 HTTP 500 或 returncode=1： +- 读取 `bbdev/server.log` 获取详细错误信息 diff --git a/.claude/skills/verify/SKILL.md b/.claude/skills/verify/SKILL.md new file mode 100644 index 00000000..fb34ff41 --- /dev/null +++ b/.claude/skills/verify/SKILL.md @@ -0,0 +1,59 @@ +--- +name: verify +description: 验证名为 $ARGUMENTS 的 Ball 的功能正确性。当用户要求验证、测试某个 Ball，检查 Ball 是否工作正常，或说"验证 XX Ball"、"跑一下 XX 测试"时使用此 skill。也适用于用户新建完 Ball 后想确认其正确性的场景。 +--- + +**重要：编译、仿真、测试等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** + +## 阶段 1 — 完整性检查 + +使用 `/check` 的逻辑检查注册一致性，然后检查以下各项是否存在，缺什么补什么： +1. Ball 实现：`arch/src/main/scala/framework/balldomain/prototype//` 目录是否存在 +2. 注册：`arch/src/main/scala/framework/balldomain/configs/default.json` 中是否有条目 +3. ISA 宏：`bb-tests/workloads/lib/bbhw/isa/` 下对应的 .c 文件 +4. CTest：`bb-tests/workloads/src/CTest/toy/` 下对应的 _test.c 文件 +5. sardine 列表：`bb-tests/sardine/tests/test_ctest.py` 的 ctest_workloads 列表 + +## 阶段 2 — 编译 + 仿真 + +1. 调用 MCP 工具 `bbdev_workload_build` 编译所有 CTest +2. 调用 MCP 工具 `bbdev_verilator_run` 仿真该 Ball 的 CTest + - binary 名称格式：`ctest__test_singlecore-baremetal` + - 设置 batch=true +3. 如果编译或仿真失败，使用 `/debug` skill 进入调试流程 + +## 阶段 3 — 覆盖率分析 + +1. 调用 MCP 工具 `bbdev_sardine_run`，设置 coverage=true +2. 读取覆盖率报告： + - 行覆盖数据在 `bb-tests/sardine/reports/coverage/annotated/` 下 + - 找到对应 Ball 的文件：grep 搜索 Ball 类名 +3. 分析该 Ball 的 RTL 行覆盖情况： + - 查看未覆盖的行（标记为 `000000`） + - 重点关注 FSM 状态、边界条件、错误路径 +4. 如果覆盖率不足，建议或自动补充测试用例，补充后重新编译和仿真验证 + +## 阶段 4 — PMC 性能分析 + +仿真通过后，读取 bdb.log 中的 PMC trace 数据来分析性能： + +1. 找到日志目录（`ls -t arch/log/ | head -5`） +2. 在 bdb.log 中搜索 `[PMCTRACE] BALL` 条目，提取该 Ball 的 elapsed cycle 数据 +3. 汇总报告： + - 平均 elapsed cycles per task + - 最大/最小 elapsed cycles + - 总调用次数 + +## 阶段 5 — 波形分析（仿真失败时） + +如果仿真失败，除了读日志外，还可以用 waveform-mcp 做精确的时序分析。详见 `/waveform` skill。 + +关键信号检查清单： +- `cmdReq.valid && cmdReq.ready`（命令握手） +- SRAM `req.valid/ready` 和 `resp.valid`（读写时序） +- FSM state 寄存器（状态转移） +- `cmdResp.valid && cmdResp.fire`（完成握手） + +## 失败分析 + +如果仿真结果为 FAILED，使用 `/debug` skill 进行系统性调试。 diff --git a/.claude/skills/waveform/SKILL.md b/.claude/skills/waveform/SKILL.md new file mode 100644 index 00000000..82dccfd5 --- /dev/null +++ b/.claude/skills/waveform/SKILL.md @@ -0,0 +1,139 @@ +--- +name: waveform +description: 使用 waveform-mcp 工具分析 VCD/FST 波形文件，检查 Buckyball 模块的信号时序。当需要做 cycle-level 的时序分析、调试握手协议、检查 FSM 状态转移，或用户要求"看波形"、"分析信号"时使用此 skill。也适用于 `/debug` 和 `/optimize` 中需要波形分析的场景。 +--- + +## 工具概览 + +项目配置了 `waveform-mcp` MCP server，提供以下工具： +- `open_waveform(file_path)` — 打开 VCD/FST 文件 +- `list_signals(waveform_id, hierarchy_prefix?, name_pattern?, recursive?)` — 列出信号 +- `read_signal(waveform_id, signal_path, time_index|time_indices)` — 读取信号值 +- `get_signal_info(waveform_id, signal_path)` — 获取信号元数据 +- `find_signal_events(waveform_id, signal_path, start?, end?, limit?)` — 找信号变化 +- `find_conditional_events(waveform_id, condition, start?, end?, limit?)` — 条件搜索 +- `close_waveform(waveform_id)` — 关闭波形 + +## 波形文件位置 + +仿真生成的波形文件通常在： +- `arch/log//` 目录下 +- 文件格式：`.vcd` 或 `.fst` +- 用 `find arch/log -name "*.vcd" -o -name "*.fst" | head -5` 查找 + +## 信号层次结构 + +Buckyball 的信号层次大致为： +``` +TOP +├── BuckyballToy (顶层) +│ ├── bbtile (BBTile) +│ │ ├── buckyball (Buckyball 主体) +│ │ │ ├── frontend +│ │ │ │ ├── globalDecoder +│ │ │ │ └── globalROB +│ │ │ ├── ballDomain +│ │ │ │ └── bbus (BBus) +│ │ │ │ ├── cmdRouter +│ │ │ │ ├── pmc (BallCyclePMC) +│ │ │ │ ├── balls_0 (第一个 Ball，按 ballId 排序) +│ │ │ │ ├── balls_1 +│ │ │ │ └── ... +│ │ │ └── memDomain +│ │ │ ├── memFrontend +│ │ │ └── memBackend +``` + +### 定位 Ball 信号 + +要找到特定 Ball 的信号： +1. `list_signals(waveform_id, recursive=false)` — 先看顶层 +2. 逐级向下：`list_signals(waveform_id, hierarchy_prefix="TOP.BuckyballToy")` 等 +3. 或直接用 `name_pattern` 搜索：`list_signals(waveform_id, name_pattern="relu", recursive=true)` + +## 常用检查模板 + +### 1. 握手检查（Decoupled valid/ready） + +检查 cmdReq 握手是否成功： +``` +find_conditional_events(waveform_id, + condition="TOP...cmdReq_valid && TOP...cmdReq_ready") +``` + +检查 cmdResp 握手： +``` +find_conditional_events(waveform_id, + condition="TOP...cmdResp_valid && TOP...cmdResp_ready") +``` + +### 2. SRAM 读时序检查 + +验证 SRAM 1-cycle 读延迟： +``` +# 找到读请求 +find_conditional_events(waveform_id, + condition="TOP...bankRead_0_io_req_valid && TOP...bankRead_0_io_req_ready") + +# 检查下一个 cycle 是否有 resp.valid +# 取上面事件的 time_index + 1，然后 +read_signal(waveform_id, "TOP...bankRead_0_io_resp_valid", time_index=) +``` + +### 3. FSM 状态转移追踪 + +找 state 寄存器的所有变化： +``` +find_signal_events(waveform_id, signal_path="TOP...state") +``` + +然后读取每个变化点的值来重建状态转移序列。 + +### 4. Ball 操作延迟测量 + +测量从 cmdReq.fire 到 cmdResp.fire 的 cycle 数： +``` +# 找 cmdReq 握手时刻 +req_events = find_conditional_events(waveform_id, + condition="TOP...cmdReq_valid && TOP...cmdReq_ready") + +# 找 cmdResp 握手时刻 +resp_events = find_conditional_events(waveform_id, + condition="TOP...cmdResp_valid && TOP...cmdResp_ready") + +# 对应的 resp - req 即为延迟 +``` + +### 5. Bank 地址/数据检查 + +在某个时刻读取 SRAM 读写的地址和数据： +``` +read_signal(waveform_id, "TOP...bankRead_0_io_req_bits_addr", time_index=T) +read_signal(waveform_id, "TOP...bankRead_0_io_resp_bits_data", time_index=T+1) +read_signal(waveform_id, "TOP...bankWrite_0_io_req_bits_addr", time_index=T) +read_signal(waveform_id, "TOP...bankWrite_0_io_req_bits_data", time_index=T) +``` + +## 条件搜索语法 + +`find_conditional_events` 的 condition 支持： +- 信号路径：`TOP.module.signal` +- 位运算：`~`(NOT), `&`(AND), `|`(OR), `^`(XOR) +- 布尔运算：`&&`, `||`, `!` +- 比较：`==`, `!=` +- 位提取：`signal[bit]` 或 `signal[msb:lsb]` +- 前值：`$past(signal)` — 前一个 time_index 的值 +- Verilog 字面量：`4'b0001`, `8'hFF` + +常用 pattern： +- 上升沿：`!$past(TOP.signal) && TOP.signal` +- 下降沿：`$past(TOP.signal) && !TOP.signal` +- 握手：`TOP.valid && TOP.ready` +- 某位为 1：`TOP.flags & 4'b0001` + +## 使用建议 + +1. **先 list_signals 再 read** — 信号路径名可能和 Chisel 源码中的名称略有不同（Chisel 会做 name mangling），先搜索确认 +2. **用 find_conditional_events 而不是逐 cycle read** — 效率差几个数量级 +3. **限制 limit** — 波形可能很长，设置合理的 limit 避免返回过多数据 +4. **用完记得 close_waveform** — 释放内存 diff --git a/README.md b/README.md index 79b59a18..2e44a5b3 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ [![Ask DeepWiki](https://deepwiki.com/badge.svg)](https://deepwiki.com/DangoSys/buckyball) [![zread](https://img.shields.io/badge/Ask_Zread-_.svg?style=flat&color=00b0aa&labelColor=000000&logo=data%3Aimage%2Fsvg%2Bxml%3Bbase64%2CPHN2ZyB3aWR0aD0iMTYiIGhlaWdodD0iMTYiIHZpZXdCb3g9IjAgMCAxNiAxNiIgZmlsbD0ibm9uZSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIj4KPHBhdGggZD0iTTQuOTYxNTYgMS42MDAxSDIuMjQxNTZDMS44ODgxIDEuNjAwMSAxLjYwMTU2IDEuODg2NjQgMS42MDE1NiAyLjI0MDFWNC45NjAxQzEuNjAxNTYgNS4zMTM1NiAxLjg4ODEgNS42MDAxIDIuMjQxNTYgNS42MDAxSDQuOTYxNTZDNS4zMTUwMiA1LjYwMDEgNS42MDE1NiA1LjMxMzU2IDUuNjAxNTYgNC45NjAxVjIuMjQwMUM1LjYwMTU2IDEuODg2NjQgNS4zMTUwMiAxLjYwMDEgNC45NjE1NiAxLjYwMDFaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00Ljk2MTU2IDEwLjM5OTlIMi4yNDE1NkMxLjg4ODEgMTAuMzk5OSAxLjYwMTU2IDEwLjY4NjQgMS42MDE1NiAxMS4wMzk5VjEzLjc1OTlDMS42MDE1NiAxNC4xMTM0IDEuODg4MSAxNC4zOTk5IDIuMjQxNTYgMTQuMzk5OUg0Ljk2MTU2QzUuMzE1MDIgMTQuMzk5OSA1LjYwMTU2IDE0LjExMzQgNS42MDE1NiAxMy43NTk5VjExLjAzOTlDNS42MDE1NiAxMC42ODY0IDUuMzE1MDIgMTAuMzk5OSA0Ljk2MTU2IDEwLjM5OTlaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik0xMy43NTg0IDEuNjAwMUgxMS4wMzg0QzEwLjY4NSAxLjYwMDEgMTAuMzk4NCAxLjg4NjY0IDEwLjM5ODQgMi4yNDAxVjQuOTYwMUMxMC4zOTg0IDUuMzEzNTYgMTAuNjg1IDUuNjAwMSAxMS4wMzg0IDUuNjAwMUgxMy43NTg0QzE0LjExMTkgNS42MDAxIDE0LjM5ODQgNS4zMTM1NiAxNC4zOTg0IDQuOTYwMVYyLjI0MDFDMTQuMzk4NCAxLjg4NjY0IDE0LjExMTkgMS42MDAxIDEzLjc1ODQgMS42MDAxWiIgZmlsbD0iI2ZmZiIvPgo8cGF0aCBkPSJNNCAxMkwxMiA0TDQgMTJaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00IDEyTDEyIDQiIHN0cm9rZT0iI2ZmZiIgc3Ryb2tlLXdpZHRoPSIxLjUiIHN0cm9rZS1saW5lY2FwPSJyb3VuZCIvPgo8L3N2Zz4K&logoColor=ffffff)](https://zread.ai/DangoSys/buckyball) -[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://175.178.48.176/docs/en/Overview.md) +[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://175.178.48.176/docs/en/Overview/Overview.md) [![buckyball CI](https://github.com/DangoSys/buckyball/actions/workflows/test.yml/badge.svg)](https://github.com/DangoSys/buckyball/actions/workflows/test.yml) diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index 6b0e22cc..73e347a3 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -20,6 +20,16 @@ void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read unsigned int group_id, unsigned int addr, unsigned long long data_lo, unsigned long long data_hi); +// DPI-C function for Ball PMC trace (pmctrace) +// Called from BallCyclePMC when a Ball completes a task +void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, + unsigned long long elapsed); + +// DPI-C function for memory PMC trace (pmctrace) +// Called from MemCyclePMC when a load/store completes +void dpi_mem_pmctrace(unsigned char is_store, // 1 = store, 0 = load + unsigned int rob_id, unsigned long long elapsed); + #ifdef __cplusplus } #endif diff --git a/arch/src/csrc/src/monitor/trace/pmctrace.cc b/arch/src/csrc/src/monitor/trace/pmctrace.cc new file mode 100644 index 00000000..ec5784c4 --- /dev/null +++ b/arch/src/csrc/src/monitor/trace/pmctrace.cc @@ -0,0 +1,49 @@ +#include "monitor/trace.h" +#include "utils/debug.h" +#include +#include + +// Global log file pointer (shared with monitor.cc) +extern const char *log_path; +static FILE *pmctrace_fp = NULL; + +// Initialize pmctrace logging +static void init_pmctrace() { + if (pmctrace_fp == NULL && log_path != NULL) { + pmctrace_fp = fopen(log_path, "a"); + if (pmctrace_fp == NULL) { + panic("Failed to open pmctrace log file: %s", log_path); + } + } +} + +// DPI-C function for Ball PMC trace +// Called when a Ball completes a task, reports elapsed cycles +extern "C" void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, + unsigned long long elapsed) { + init_pmctrace(); + + if (pmctrace_fp) { + fprintf(pmctrace_fp, "[PMCTRACE] BALL ball_id=%u rob_id=%u elapsed=%llu\n", + ball_id, rob_id, elapsed); + fflush(pmctrace_fp); + } +} + +// DPI-C function for Memory PMC trace +// Called when a load/store completes, reports elapsed cycles +extern "C" void dpi_mem_pmctrace(unsigned char is_store, unsigned int rob_id, + unsigned long long elapsed) { + init_pmctrace(); + + if (pmctrace_fp) { + if (is_store) { + fprintf(pmctrace_fp, "[PMCTRACE] STORE rob_id=%u elapsed=%llu\n", rob_id, + elapsed); + } else { + fprintf(pmctrace_fp, "[PMCTRACE] LOAD rob_id=%u elapsed=%llu\n", rob_id, + elapsed); + } + fflush(pmctrace_fp); + } +} diff --git a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala index 2701bf7f..2ef55d4d 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala @@ -24,6 +24,15 @@ class BallCyclePMC(val b: GlobalConfig) extends Module { val startTime = Reg(Vec(b.frontend.rob_entries, UInt(64.W))) val ballTotalCycles = RegInit(VecInit(Seq.fill(numBalls)(0.U(64.W)))) + // Per-Ball DPI-C trace modules + val pmcTraces = Seq.fill(numBalls)(Module(new PMCTraceDPI)) + for (pt <- pmcTraces) { + pt.io.ball_id := 0.U + pt.io.rob_id := 0.U + pt.io.elapsed := 0.U + pt.io.enable := false.B + } + for (i <- 0 until numBalls) { when(io.cmdReq_i(i).valid) { startTime(io.cmdReq_i(i).bits.rob_id) := cycleCounter @@ -35,7 +44,12 @@ class BallCyclePMC(val b: GlobalConfig) extends Module { val robId = io.cmdResp_o(i).bits.rob_id val elapsed = cycleCounter - startTime(robId) ballTotalCycles(i) := ballTotalCycles(i) + elapsed - printf("[PMC] Ball %d completed task, elapsed: %d cycles\n", i.U, elapsed) + + // DPI-C trace output + pmcTraces(i).io.ball_id := i.U + pmcTraces(i).io.rob_id := robId + pmcTraces(i).io.elapsed := elapsed + pmcTraces(i).io.enable := true.B } } diff --git a/arch/src/main/scala/framework/balldomain/bbus/pmc/PMCTraceDPI.scala b/arch/src/main/scala/framework/balldomain/bbus/pmc/PMCTraceDPI.scala new file mode 100644 index 00000000..56514365 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/bbus/pmc/PMCTraceDPI.scala @@ -0,0 +1,39 @@ +package framework.balldomain.bbus.pmc + +import chisel3._ +import chisel3.util._ + +// DPI-C BlackBox for PMC trace +class PMCTraceDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val ball_id = Input(UInt(32.W)) + val rob_id = Input(UInt(32.W)) + val elapsed = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "PMCTraceDPI.v", + """ + |import "DPI-C" function void dpi_pmctrace( + | input int unsigned ball_id, + | input int unsigned rob_id, + | input longint unsigned elapsed + |); + | + |module PMCTraceDPI( + | input [31:0] ball_id, + | input [31:0] rob_id, + | input [63:0] elapsed, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_pmctrace(ball_id, rob_id, elapsed); + | end + | end + |endmodule + """.stripMargin + ) +} diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 65096cf0..e39aebe6 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -198,12 +198,6 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.query := robEntries(actualIssuePtr).cmd.bankAccess val noHazard = !scoreboard.hasHazard - /* when(hasValid && scoreboard.hasHazard) { printf( "[ROB HAZARD] ptr=%d func7=%d rd0v=%d rd0=%d rd1v=%d rd1=%d wrv=%d - * wr=%d\n", actualIssuePtr, robEntries(actualIssuePtr).cmd.cmd.funct, - * robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_valid, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_0_id, - * robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_valid, robEntries(actualIssuePtr).cmd.bankAccess.rd_bank_1_id, - * robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_valid, robEntries(actualIssuePtr).cmd.bankAccess.wr_bank_id ) } */ - // Can only issue if issue limit is not reached and no bank hazard val canIssueMore = issuedCount < maxIssueLimit canIssue := hasValid && canIssueMore && noHazard diff --git a/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala b/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala index 1ecc4087..cff18f5f 100644 --- a/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala +++ b/arch/src/main/scala/framework/memdomain/utils/pmc/MemCyclePMC.scala @@ -26,6 +26,20 @@ class MemCyclePMC(val b: GlobalConfig) extends Module { val ldTotalCycles = RegInit(0.U(64.W)) val stTotalCycles = RegInit(0.U(64.W)) + // DPI-C trace modules for load and store + val ldPmcTrace = Module(new MemPMCTraceDPI) + val stPmcTrace = Module(new MemPMCTraceDPI) + + ldPmcTrace.io.is_store := 0.U + ldPmcTrace.io.rob_id := 0.U + ldPmcTrace.io.elapsed := 0.U + ldPmcTrace.io.enable := false.B + + stPmcTrace.io.is_store := 1.U + stPmcTrace.io.rob_id := 0.U + stPmcTrace.io.elapsed := 0.U + stPmcTrace.io.enable := false.B + when(io.ldReq_i.valid) { startTime(io.ldReq_i.bits.rob_id) := cycleCounter } @@ -38,14 +52,22 @@ class MemCyclePMC(val b: GlobalConfig) extends Module { val robId = io.ldResp_o.bits.rob_id val elapsed = cycleCounter - startTime(robId) ldTotalCycles := ldTotalCycles + elapsed - printf("[PMC] Load completed, elapsed: %d cycles\n", elapsed) + + // DPI-C trace output + ldPmcTrace.io.rob_id := robId + ldPmcTrace.io.elapsed := elapsed + ldPmcTrace.io.enable := true.B } when(io.stResp_o.valid) { val robId = io.stResp_o.bits.rob_id val elapsed = cycleCounter - startTime(robId) stTotalCycles := stTotalCycles + elapsed - printf("[PMC] Store completed, elapsed: %d cycles\n", elapsed) + + // DPI-C trace output + stPmcTrace.io.rob_id := robId + stPmcTrace.io.elapsed := elapsed + stPmcTrace.io.enable := true.B } io.ldTotalCycles := ldTotalCycles diff --git a/arch/src/main/scala/framework/memdomain/utils/pmc/MemPMCTraceDPI.scala b/arch/src/main/scala/framework/memdomain/utils/pmc/MemPMCTraceDPI.scala new file mode 100644 index 00000000..07a24bdb --- /dev/null +++ b/arch/src/main/scala/framework/memdomain/utils/pmc/MemPMCTraceDPI.scala @@ -0,0 +1,39 @@ +package framework.memdomain.utils.pmc + +import chisel3._ +import chisel3.util._ + +// DPI-C BlackBox for memory PMC trace +class MemPMCTraceDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val is_store = Input(UInt(8.W)) + val rob_id = Input(UInt(32.W)) + val elapsed = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "MemPMCTraceDPI.v", + """ + |import "DPI-C" function void dpi_mem_pmctrace( + | input byte unsigned is_store, + | input int unsigned rob_id, + | input longint unsigned elapsed + |); + | + |module MemPMCTraceDPI( + | input [7:0] is_store, + | input [31:0] rob_id, + | input [63:0] elapsed, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_mem_pmctrace(is_store, rob_id, elapsed); + | end + | end + |endmodule + """.stripMargin + ) +} diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 0cb2c7b7..6e98cbfe 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -19,7 +19,7 @@ typedef int32_t result_t; // Field encoding macro with start and end bit #define FIELD(val, start_bit, end_bit) \ - (((val) & ((1UL << ((end_bit) - (start_bit) + 1)) - 1)) << (start_bit)) + (((val) & ((2UL << ((end_bit) - (start_bit))) - 1)) << (start_bit)) // Unified rs1 bank encoding flags (bits 45-47) // bit 45 = rd_bank_0_valid, bit 46 = rd_bank_1_valid, bit 47 = wr_bank_valid diff --git a/docs b/docs index 0b1e11a5..ae40fa84 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 0b1e11a5ef548ed8927344eff83e4012e1e96c44 +Subproject commit ae40fa845f9d8463d588f6d85bef9214074396a5 From b6bea0b63f0169b4fb94de55d8efe63f30f408a5 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 9 Mar 2026 20:41:35 +0800 Subject: [PATCH 157/238] [arch]fix:change the code framework of sharedmembackend --- .../scala/framework/memdomain/MemDomain.scala | 1 + .../memdomain/backend/MemBackend.scala | 28 +- .../memdomain/backend/MemBackendTypes.scala | 1 + .../privatepath/PrivateMemBackend.scala | 5 +- .../memdomain/backend/shared/SharedMem.scala | 45 ++- .../backend/shared/SharedMemBackend.scala | 290 ++++++++---------- .../outside_channel/MemConfiger.scala | 2 + .../memdomain/midend/MemMidend.scala | 4 + 8 files changed, 184 insertions(+), 192 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index e32386dd..8c3f8742 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -92,6 +92,7 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite midend.io.frontend.read_is_shared := frontend.io.interdma.read_is_shared midend.io.frontend.write_is_shared := frontend.io.interdma.write_is_shared + midend.io.hartid := io.hartid midend.io.mem_req <> backend.io.mem_req backend.io.config <> frontend.io.config diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index c75eb8f2..ccfbb51e 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -27,17 +27,20 @@ class MemBackend(val b: GlobalConfig) extends Module { val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) + val cfgWithHart = Wire(new MemConfigerIO(b)) + cfgWithHart := io.config.bits + cfgWithHart.hart_id := io.hartid + // Broadcast config so alloc/release is handled by the corresponding backend. privateBackend.io.config.valid := io.config.valid - privateBackend.io.config.bits := io.config.bits + privateBackend.io.config.bits := cfgWithHart sharedBackend.io.config.valid := io.config.valid - sharedBackend.io.config.bits := io.config.bits + sharedBackend.io.config.bits := cfgWithHart io.config.ready := privateBackend.io.config.ready && sharedBackend.io.config.ready // Query both backends; shared takes priority when this vbank is allocated as shared. privateBackend.io.query_vbank_id := io.query_vbank_id sharedBackend.io.query_vbank_id := io.query_vbank_id - sharedBackend.io.hartid := io.hartid io.query_group_count := Mux( sharedBackend.io.query_group_count =/= 0.U, sharedBackend.io.query_group_count, @@ -51,6 +54,23 @@ class MemBackend(val b: GlobalConfig) extends Module { val readRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) val writeRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) + // Shared backend reserves channels for 4 harts; only hart-0 channels are currently wired. + val totalSharedChannels = b.memDomain.bankChannel * 4 + for (i <- 0 until totalSharedChannels) { + sharedBackend.io.mem_req(i).bank_id := 0.U + sharedBackend.io.mem_req(i).group_id := 0.U + sharedBackend.io.mem_req(i).is_shared := false.B + sharedBackend.io.mem_req(i).hart_id := 0.U + + sharedBackend.io.mem_req(i).read.req.valid := false.B + sharedBackend.io.mem_req(i).read.req.bits := DontCare + sharedBackend.io.mem_req(i).read.resp.ready := false.B + + sharedBackend.io.mem_req(i).write.req.valid := false.B + sharedBackend.io.mem_req(i).write.req.bits := DontCare + sharedBackend.io.mem_req(i).write.resp.ready := false.B + } + for (i <- 0 until b.memDomain.bankChannel) { val useSharedReq = io.mem_req(i).is_shared val useSharedReadResp = Mux(readPending(i), readRouteShared(i), useSharedReq) @@ -76,9 +96,11 @@ class MemBackend(val b: GlobalConfig) extends Module { privateBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id privateBackend.io.mem_req(i).group_id := io.mem_req(i).group_id privateBackend.io.mem_req(i).is_shared := io.mem_req(i).is_shared + privateBackend.io.mem_req(i).hart_id := io.mem_req(i).hart_id sharedBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id sharedBackend.io.mem_req(i).group_id := io.mem_req(i).group_id sharedBackend.io.mem_req(i).is_shared := io.mem_req(i).is_shared + sharedBackend.io.mem_req(i).hart_id := io.mem_req(i).hart_id // Read request route privateBackend.io.mem_req(i).read.req.valid := io.mem_req(i).read.req.valid && !useSharedReq diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala index 55482eeb..7f6201c8 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackendTypes.scala @@ -11,4 +11,5 @@ class MemRequestIO(b: GlobalConfig) extends Bundle { val bank_id = Output(UInt(log2Up(b.memDomain.bankNum).W)) val group_id = Output(UInt(3.W)) val is_shared = Output(Bool()) + val hart_id = Output(UInt(b.core.xLen.W)) } diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index 8cc9c70f..de293be8 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -92,6 +92,7 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared + accPipes(i).io.mem_req.hart_id := io.mem_req(i).hart_id // Bank-side defaults (only driven when a bank is actually connected) accPipes(i).io.sramRead.req.ready := false.B @@ -123,10 +124,10 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- when(io.config.valid) { - when(io.config.bits.alloc === 1.U) { + when(io.config.bits.alloc) { val pbank_id = getFreePbankId() addEntry(io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) - }.elsewhen(io.config.bits.alloc === 0.U) { + }.otherwise { deleteEntry(io.config.bits.vbank_id) } } diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index 9a393786..f80d20c2 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -6,16 +6,25 @@ import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadResp, SramWriteResp} +object SharedMemLayout { + val AccPipePerHart: Int = 8 + val MaxHart: Int = 4 + val TotalAccPipe: Int = AccPipePerHart * MaxHart + + val BankPerHart: Int = 32 + val TotalBank: Int = BankPerHart * MaxHart +} + class SharedMemReadReq(val b: GlobalConfig) extends Bundle { val hartid = UInt(b.core.xLen.W) - val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val pbank_id = UInt(log2Ceil(SharedMemLayout.TotalBank).W) val group_id = UInt(3.W) val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) } class SharedMemWriteReq(val b: GlobalConfig) extends Bundle { val hartid = UInt(b.core.xLen.W) - val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) + val pbank_id = UInt(log2Ceil(SharedMemLayout.TotalBank).W) val group_id = UInt(3.W) val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) val mask = Vec(b.memDomain.bankMaskLen, Bool()) @@ -37,9 +46,8 @@ class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { class SharedMem(val b: GlobalConfig) extends Module { private val maskLen = b.memDomain.bankMaskLen private val maskElem = UInt((b.memDomain.bankWidth / maskLen).W) - private val hartLines = b.memDomain.bankNum * b.memDomain.bankEntries - private val minSharedLines = hartLines - private val hartSlots = math.max(1, b.memDomain.sharedEntries / hartLines) + private val totalBanks = SharedMemLayout.TotalBank + private val minSharedLines = totalBanks * b.memDomain.bankEntries require( b.memDomain.sharedEntries >= minSharedLines, @@ -55,29 +63,24 @@ class SharedMem(val b: GlobalConfig) extends Module { val mem = SyncReadMem(b.memDomain.sharedEntries, Vec(maskLen, maskElem)) // Shared memory address mapping (group_id intentionally ignored): - // shared_addr = (hart_slot * bankNum * bankEntries) + (vbank_id * bankEntries) + local_addr. - // hart_slot is derived from hartid and bounded by available shared capacity. + // shared_addr = pbank_id * bankEntries + local_addr. private def toSharedAddr( - hartid: UInt, - vbank_id: UInt, + pbank_id: UInt, _group_id: UInt, local_addr: UInt ): UInt = { - val hartSlot = if (hartSlots == 1) 0.U else (hartid(log2Ceil(hartSlots) - 1, 0) % hartSlots.U) - val hartPart = hartSlot * hartLines.U - val vbankPart = vbank_id * b.memDomain.bankEntries.U - hartPart + vbankPart + local_addr + val pbankPart = pbank_id * b.memDomain.bankEntries.U + pbankPart + local_addr } io.read.req.ready := !io.write.req.valid io.write.req.ready := !io.read.req.valid val readReqFire = io.read.req.fire - val readAddr = - toSharedAddr(io.read.req.bits.hartid, io.read.req.bits.vbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) + val readAddr = toSharedAddr(io.read.req.bits.pbank_id, io.read.req.bits.group_id, io.read.req.bits.addr) when(readReqFire) { - assert(io.read.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.read.req.bits.pbank_id < totalBanks.U, "SharedMem: pbank_id out of range") assert(io.read.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") } @@ -87,16 +90,10 @@ class SharedMem(val b: GlobalConfig) extends Module { io.read.resp.bits.data := readData.asUInt val writeReqFire = io.write.req.fire - - val writeAddr = toSharedAddr( - io.write.req.bits.hartid, - io.write.req.bits.vbank_id, - io.write.req.bits.group_id, - io.write.req.bits.addr - ) + val writeAddr = toSharedAddr(io.write.req.bits.pbank_id, io.write.req.bits.group_id, io.write.req.bits.addr) when(writeReqFire) { - assert(io.write.req.bits.vbank_id < b.memDomain.bankNum.U, "SharedMem: vbank_id out of range") + assert(io.write.req.bits.pbank_id < totalBanks.U, "SharedMem: pbank_id out of range") assert(io.write.req.bits.addr < b.memDomain.bankEntries.U, "SharedMem: local addr out of range") mem.write( writeAddr, diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index aee34888..3ba532f8 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -5,40 +5,44 @@ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.memdomain.backend.{MTraceDPI, MemRequestIO} import framework.memdomain.backend.accpipe.AccPipe +import framework.memdomain.backend.banks.SramBank import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig -class SharedArbReq(b: GlobalConfig) extends Bundle { - val src_channel = UInt(log2Up(b.memDomain.bankChannel).W) - val is_write = Bool() - val vbank_id = UInt(log2Up(b.memDomain.bankNum).W) - val group_id = UInt(3.W) - val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) - val mask = Vec(b.memDomain.bankMaskLen, Bool()) - val data = UInt(b.memDomain.bankWidth.W) - val wmode = Bool() -} +// class SharedArbReq(b: GlobalConfig) extends Bundle { +// val src_channel = UInt(log2Up(b.memDomain.bankChannel).W) +// val is_write = Bool() +// val hart_id = UInt(b.core.xLen.W) +// val pbank_id = UInt(log2Ceil(SharedMemLayout.TotalBank).W) +// val group_id = UInt(3.W) +// val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) +// val mask = Vec(b.memDomain.bankMaskLen, Bool()) +// val data = UInt(b.memDomain.bankWidth.W) +// val wmode = Bool() +// } @instantiable class SharedMemBackend(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val mem_req = Vec(b.memDomain.bankChannel*4, Flipped(new MemRequestIO(b))) val config = Flipped(Decoupled(new MemConfigerIO(b))) // Query interface for frontend to get group count val query_vbank_id = Input(UInt(8.W)) val query_group_count = Output(UInt(4.W)) - - val hartid = Input(UInt(b.core.xLen.W)) }) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) - val sharedMem: Instance[SharedMem] = Instantiate(new SharedMem(b)) - val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) - val sharedAllocTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) + // Shared backend is sized for 4 harts, but currently only hart-0 channels are connected. + private val activeHartCount = 1 + private val activeChannelCount = b.memDomain.bankChannel * activeHartCount + + val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum*4)(Instantiate(new SramBank(b))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel*4)(Instantiate(new AccPipe(b))) + // Per-channel memory trace DPI-C modules to avoid losing simultaneous events + val mtraces = Seq.fill(b.memDomain.bankChannel*4)(Module(new MTraceDPI)) for (mt <- mtraces) { mt.io.is_write := 0.U mt.io.channel := 0.U @@ -50,31 +54,67 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { mt.io.enable := false.B } - io.config.ready := true.B - when(io.config.valid) { - val cfgVbankIdx = io.config.bits.vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) - when(io.config.bits.alloc === 2.U) { - sharedAllocTable(cfgVbankIdx) := true.B - }.elsewhen(io.config.bits.alloc === 0.U) { - sharedAllocTable(cfgVbankIdx) := false.B + // ----------------------------------------------------------------------------- + // Mapping table + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + + val valid = Bool() + val hart_id = UInt(b.core.xLen.W) + val vbank_id = UInt(5.W) + val is_multi = Bool() + val group_id = UInt(3.W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum*4)(0.U.asTypeOf(new MappingTableEntry)))) + + def isAcc(hart_id: UInt, vbank_id: UInt): Bool = + mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && (entry.hart_id === hart_id) && entry.is_multi).reduce(_ || _) + + def addEntry( + hart_id: UInt, + vbank_id: UInt, + pbank_id: UInt, + is_multi: Bool, + group_id: UInt + ): Unit = { + val entry = mappingTable(pbank_id) + entry.valid := true.B + entry.hart_id := hart_id + entry.vbank_id := vbank_id + entry.is_multi := is_multi + entry.group_id := group_id + } + + def deleteEntry(hart_id: UInt, vbank_id: UInt): Unit = { + for (i <- 0 until b.memDomain.bankNum*4) { + when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id && mappingTable(i).hart_id === hart_id) { + mappingTable(i).valid := false.B + mappingTable(i).vbank_id := 0.U + mappingTable(i).is_multi := false.B + mappingTable(i).group_id := 0.U + } } } - // Shared memory treats each vbank as single-group storage. - val queryVbankIdx = io.query_vbank_id(log2Up(b.memDomain.bankNum) - 1, 0) - io.query_group_count := Mux( - b.memDomain.sharedEnable.B && sharedAllocTable(queryVbankIdx), - 1.U(4.W), - 0.U(4.W) - ) + def getFreePbankId(): UInt = { + val freePbankId = mappingTable.indexWhere(_.valid === false.B) + freePbankId + } + + // ----------------------------------------------------------------------------- + // Default Value + // ----------------------------------------------------------------------------- - for (i <- 0 until b.memDomain.bankChannel) { + for (i <- 0 until b.memDomain.bankChannel*4) { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared + accPipes(i).io.mem_req.hart_id := io.mem_req(i).hart_id + // Bank-side defaults (only driven when a bank is actually connected) accPipes(i).io.sramRead.req.ready := false.B accPipes(i).io.sramRead.resp.valid := false.B accPipes(i).io.sramRead.resp.bits := DontCare @@ -83,20 +123,49 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { accPipes(i).io.sramWrite.resp.valid := false.B accPipes(i).io.sramWrite.resp.bits := DontCare - // Group dimension is intentionally disabled in shared backend. - accPipes(i).io.is_multi := false.B + accPipes(i).io.is_multi := isAcc(io.mem_req(i).hart_id, io.mem_req(i).bank_id) } - sharedMem.io.read.req.valid := false.B - sharedMem.io.read.req.bits := DontCare - sharedMem.io.read.resp.ready := false.B - sharedMem.io.write.req.valid := false.B - sharedMem.io.write.req.bits := DontCare - sharedMem.io.write.resp.ready := false.B + io.config.ready := true.B + + banks.zipWithIndex.foreach { + case (bank, _) => + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := DontCare + bank.io.sramRead.resp.ready := true.B - // --------------------------------------------------------------------------- - // Shared request routing arbiter - // --------------------------------------------------------------------------- + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := DontCare + bank.io.sramWrite.resp.ready := true.B + } + + // ----------------------------------------------------------------------------- + // Bank Alloc/Release + // ----------------------------------------------------------------------------- + + when(io.config.valid) { + when(io.config.bits.alloc) { + val pbank_id = getFreePbankId() + addEntry(io.config.bits.hart_id, io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) + }.otherwise { + deleteEntry(io.config.bits.hart_id, io.config.bits.vbank_id) + } + } + + // ----------------------------------------------------------------------------- + // Query interface: return group count for a given vbank_id + // ----------------------------------------------------------------------------- + val groupCounts = mappingTable.map { entry => + val matches = entry.valid && (entry.vbank_id === io.query_vbank_id) + val count = Mux(entry.is_multi, entry.group_id + 1.U, 1.U) + Mux(matches, count, 0.U) + } + + io.query_group_count := groupCounts.reduce((a, b) => Mux(a > b, a, b)) + + // ----------------------------------------------------------------------------- + // Connect AccPipe and Banks + // ----------------------------------------------------------------------------- private def emitTrace( ch: Int, isWrite: UInt, @@ -115,16 +184,15 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { mtraces(ch).io.enable := en } - val sharedReqArb = Module(new RRArbiter(new SharedArbReq(b), b.memDomain.bankChannel)) - - for (i <- 0 until b.memDomain.bankChannel) { - val routeShared = b.memDomain.sharedEnable.B && sharedAllocTable(io.mem_req(i).bank_id) - val useRead = accPipes(i).io.sramRead.req.valid - val useWrite = !useRead && accPipes(i).io.sramWrite.req.valid + for (i <- 0 until activeChannelCount) { + val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + // Memory trace: read request when(io.mem_req(i).read.req.fire) { emitTrace(i, 0.U, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) } + + // Memory trace: write request when(io.mem_req(i).write.req.fire) { emitTrace( i, @@ -136,122 +204,18 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { ) } - sharedReqArb.io.in(i).valid := routeShared && (useRead || useWrite) - sharedReqArb.io.in(i).bits.src_channel := i.U - sharedReqArb.io.in(i).bits.is_write := useWrite - sharedReqArb.io.in(i).bits.vbank_id := io.mem_req(i).bank_id - sharedReqArb.io.in(i).bits.group_id := 0.U - sharedReqArb.io.in(i).bits.addr := Mux( - useRead, - accPipes(i).io.sramRead.req.bits.addr, - accPipes(i).io.sramWrite.req.bits.addr - ) - sharedReqArb.io.in(i).bits.mask := Mux( - useRead, - VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)), - accPipes(i).io.sramWrite.req.bits.mask - ) - sharedReqArb.io.in(i).bits.data := Mux(useRead, 0.U, accPipes(i).io.sramWrite.req.bits.data) - sharedReqArb.io.in(i).bits.wmode := Mux(useRead, false.B, accPipes(i).io.sramWrite.req.bits.wmode) - - when(routeShared && useRead) { - accPipes(i).io.sramRead.req.ready := sharedReqArb.io.in(i).ready - } - when(routeShared && useWrite) { - accPipes(i).io.sramWrite.req.ready := sharedReqArb.io.in(i).ready - } - } - - // Keep one in-flight request per response type so source-channel mapping is exact. - val readReqPending = RegInit(false.B) - val writeReqPending = RegInit(false.B) - val readReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - val writeReqSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - - val readRespBufValid = RegInit(false.B) - val readRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - val readRespBufData = Reg(UInt(b.memDomain.bankWidth.W)) - - val writeRespBufValid = RegInit(false.B) - val writeRespBufSrcCh = Reg(UInt(log2Up(b.memDomain.bankChannel).W)) - val writeRespBufOk = Reg(Bool()) - - val arbIsWrite = sharedReqArb.io.out.bits.is_write - val canIssueRead = !readReqPending && !readRespBufValid - val canIssueWrite = !writeReqPending && !writeRespBufValid - - sharedMem.io.read.req.valid := sharedReqArb.io.out.valid && !arbIsWrite && canIssueRead - sharedMem.io.read.req.bits.hartid := io.hartid - sharedMem.io.read.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id - sharedMem.io.read.req.bits.group_id := sharedReqArb.io.out.bits.group_id - sharedMem.io.read.req.bits.addr := sharedReqArb.io.out.bits.addr - - sharedMem.io.write.req.valid := sharedReqArb.io.out.valid && arbIsWrite && canIssueWrite - sharedMem.io.write.req.bits.hartid := io.hartid - sharedMem.io.write.req.bits.vbank_id := sharedReqArb.io.out.bits.vbank_id - sharedMem.io.write.req.bits.group_id := sharedReqArb.io.out.bits.group_id - sharedMem.io.write.req.bits.addr := sharedReqArb.io.out.bits.addr - sharedMem.io.write.req.bits.mask := sharedReqArb.io.out.bits.mask - sharedMem.io.write.req.bits.data := sharedReqArb.io.out.bits.data - sharedMem.io.write.req.bits.wmode := sharedReqArb.io.out.bits.wmode - - sharedReqArb.io.out.ready := Mux( - arbIsWrite, - canIssueWrite && sharedMem.io.write.req.ready, - canIssueRead && sharedMem.io.read.req.ready - ) - - when(sharedMem.io.read.req.fire) { - assert(!readReqPending, "SharedMemBackend: read request issued while previous read pending") - readReqPending := true.B - readReqSrcCh := sharedReqArb.io.out.bits.src_channel - } - - when(sharedMem.io.write.req.fire) { - assert(!writeReqPending, "SharedMemBackend: write request issued while previous write pending") - writeReqPending := true.B - writeReqSrcCh := sharedReqArb.io.out.bits.src_channel - } - - // Always absorb SharedMem pulses into local response buffers. - sharedMem.io.read.resp.ready := !readRespBufValid - sharedMem.io.write.resp.ready := !writeRespBufValid - - when(sharedMem.io.read.resp.fire) { - assert(readReqPending, "SharedMemBackend: read response arrived without pending request") - readRespBufValid := true.B - readRespBufSrcCh := readReqSrcCh - readRespBufData := sharedMem.io.read.resp.bits.data - readReqPending := false.B - } - - when(sharedMem.io.write.resp.fire) { - assert(writeReqPending, "SharedMemBackend: write response arrived without pending request") - writeRespBufValid := true.B - writeRespBufSrcCh := writeReqSrcCh - writeRespBufOk := sharedMem.io.write.resp.bits.ok - writeReqPending := false.B - } - - // --------------------------------------------------------------------------- - // Response demux back to requesting channel - // --------------------------------------------------------------------------- - for (i <- 0 until b.memDomain.bankChannel) { - when(readRespBufValid && (readRespBufSrcCh === i.U)) { - accPipes(i).io.sramRead.resp.valid := true.B - accPipes(i).io.sramRead.resp.bits.data := readRespBufData - - when(accPipes(i).io.sramRead.resp.fire) { - readRespBufValid := false.B - } - } + for (j <- 0 until b.memDomain.bankNum*4) { + val hit_bank = mappingTable(j).valid && + (mappingTable(j).hart_id === io.mem_req(i).hart_id) && + (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + (!mappingTable(j).is_multi || + (mappingTable(j).is_multi && (mappingTable(j).group_id === io.mem_req(i).group_id))) - when(writeRespBufValid && (writeRespBufSrcCh === i.U)) { - accPipes(i).io.sramWrite.resp.valid := true.B - accPipes(i).io.sramWrite.resp.bits.ok := writeRespBufOk + val hold_one = RegNext(hit_bank && req_valid, init = false.B) - when(accPipes(i).io.sramWrite.resp.fire) { - writeRespBufValid := false.B + when((hit_bank && req_valid) || hold_one) { + banks(j).io.sramRead <> accPipes(i).io.sramRead + banks(j).io.sramWrite <> accPipes(i).io.sramWrite } } } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 1eb8644e..2ed01ef7 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -11,6 +11,7 @@ class MemConfigerIO(val b: GlobalConfig) extends Bundle { val is_multi = Output(Bool()) val alloc = Output(Bool()) val group_id = Output(UInt(3.W)) + val hart_id = Output(UInt(b.core.xLen.W)) } @instantiable @@ -39,6 +40,7 @@ class MemConfiger(val b: GlobalConfig) extends Module { io.config.bits.alloc := false.B io.config.bits.vbank_id := 0.U(8.W) io.config.bits.group_id := 0.U(3.W) + io.config.bits.hart_id := 0.U(b.core.xLen.W) io.config.valid := false.B io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index fded4747..9839069a 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -30,6 +30,8 @@ class MemMidend(val b: GlobalConfig) extends Module { val write_is_shared = Input(Bool()) } + val hartid = Input(UInt(b.core.xLen.W)) + val balldomain = new Bundle { val bankRead = Vec(totalBallRead, new BankRead(b)) val bankWrite = Vec(totalBallWrite, new BankWrite(b)) @@ -114,6 +116,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).bank_id := 0.U io.mem_req(i).group_id := 0.U io.mem_req(i).is_shared := false.B + io.mem_req(i).hart_id := io.hartid val isRead = mappingTable(i).isRead val ballRead = io.balldomain.bankRead(mappingTable(i).id).io @@ -154,6 +157,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.frontend.read_is_shared, io.frontend.write_is_shared ) + io.mem_req(b.top.memBallChannelNum).hart_id := io.hartid // Mapping table release for (i <- 0 until b.top.memBallChannelNum - 1) { From 9497a18e4ef38ae81ed921481e085eb40a66ba16 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 9 Mar 2026 20:56:56 +0800 Subject: [PATCH 158/238] [trace]add:add is_ shared and hartid for debug --- arch/src/csrc/include/monitor/trace.h | 49 ++++++++++--------- arch/src/csrc/src/monitor/trace/mtrace.cc | 38 +++++++++----- .../framework/memdomain/backend/MTrace.scala | 8 ++- .../privatepath/PrivateMemBackend.scala | 4 ++ .../backend/shared/SharedMemBackend.scala | 4 ++ 5 files changed, 67 insertions(+), 36 deletions(-) diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index 73e347a3..447b33ef 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -4,31 +4,34 @@ #include #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -// DPI-C function for instruction trace (itrace) -// Called from GlobalROB when instructions are issued or completed -void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete - unsigned int rob_id, unsigned int domain_id, unsigned int funct, - unsigned long long rs1, unsigned long long rs2); - -// DPI-C function for memory trace (mtrace) -// Called from MemBackend when read/write requests are made -void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read - unsigned int channel, unsigned int vbank_id, - unsigned int group_id, unsigned int addr, - unsigned long long data_lo, unsigned long long data_hi); - -// DPI-C function for Ball PMC trace (pmctrace) -// Called from BallCyclePMC when a Ball completes a task -void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, - unsigned long long elapsed); - -// DPI-C function for memory PMC trace (pmctrace) -// Called from MemCyclePMC when a load/store completes -void dpi_mem_pmctrace(unsigned char is_store, // 1 = store, 0 = load - unsigned int rob_id, unsigned long long elapsed); + // DPI-C function for instruction trace (itrace) + // Called from GlobalROB when instructions are issued or completed + void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete + unsigned int rob_id, unsigned int domain_id, unsigned int funct, + unsigned long long rs1, unsigned long long rs2); + + // DPI-C function for memory trace (mtrace) + // Called from MemBackend when read/write requests are made + void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read + unsigned char is_shared, // 1 = shared path, 0 = private path + unsigned int channel, unsigned long long hart_id, + unsigned int vbank_id, + unsigned int group_id, unsigned int addr, + unsigned long long data_lo, unsigned long long data_hi); + + // DPI-C function for Ball PMC trace (pmctrace) + // Called from BallCyclePMC when a Ball completes a task + void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, + unsigned long long elapsed); + + // DPI-C function for memory PMC trace (pmctrace) + // Called from MemCyclePMC when a load/store completes + void dpi_mem_pmctrace(unsigned char is_store, // 1 = store, 0 = load + unsigned int rob_id, unsigned long long elapsed); #ifdef __cplusplus } diff --git a/arch/src/csrc/src/monitor/trace/mtrace.cc b/arch/src/csrc/src/monitor/trace/mtrace.cc index 951a8d66..5ce7b3c6 100644 --- a/arch/src/csrc/src/monitor/trace/mtrace.cc +++ b/arch/src/csrc/src/monitor/trace/mtrace.cc @@ -8,10 +8,13 @@ extern const char *log_path; static FILE *mtrace_fp = NULL; // Initialize mtrace logging -static void init_mtrace() { - if (mtrace_fp == NULL && log_path != NULL) { +static void init_mtrace() +{ + if (mtrace_fp == NULL && log_path != NULL) + { mtrace_fp = fopen(log_path, "a"); - if (mtrace_fp == NULL) { + if (mtrace_fp == NULL) + { panic("Failed to open mtrace log file: %s", log_path); } } @@ -20,21 +23,32 @@ static void init_mtrace() { // DPI-C function for memory trace (mtrace) // Called when MemBackend performs read/write operations extern "C" void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read - unsigned int channel, unsigned int vbank_id, + unsigned char is_shared, + unsigned int channel, unsigned long long hart_id, + unsigned int vbank_id, unsigned int group_id, unsigned int addr, unsigned long long data_lo, - unsigned long long data_hi) { + unsigned long long data_hi) +{ init_mtrace(); - if (mtrace_fp) { - if (is_write) { + if (mtrace_fp) + { + if (is_write) + { fprintf(mtrace_fp, - "[MTRACE] WRITE ch=%u vbank=%u group=%u addr=0x%08x " + "[MTRACE] WRITE ch=%u hart=%llu shared=%u vbank=%u group=%u " + "addr=0x%08x " "data=0x%016llx%016llx\n", - channel, vbank_id, group_id, addr, data_hi, data_lo); - } else { - fprintf(mtrace_fp, "[MTRACE] READ ch=%u vbank=%u group=%u addr=0x%08x\n", - channel, vbank_id, group_id, addr); + channel, hart_id, is_shared, vbank_id, group_id, addr, data_hi, + data_lo); + } + else + { + fprintf(mtrace_fp, + "[MTRACE] READ ch=%u hart=%llu shared=%u vbank=%u group=%u " + "addr=0x%08x\n", + channel, hart_id, is_shared, vbank_id, group_id, addr); } fflush(mtrace_fp); } diff --git a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala index ee528125..5bb86328 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala @@ -8,7 +8,9 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { val is_write = Input(UInt(8.W)) + val is_shared = Input(UInt(8.W)) val channel = Input(UInt(32.W)) + val hart_id = Input(UInt(64.W)) val vbank_id = Input(UInt(32.W)) val group_id = Input(UInt(32.W)) val addr = Input(UInt(32.W)) @@ -22,7 +24,9 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { """ |import "DPI-C" function void dpi_mtrace( | input byte unsigned is_write, + | input byte unsigned is_shared, | input int unsigned channel, + | input longint unsigned hart_id, | input int unsigned vbank_id, | input int unsigned group_id, | input int unsigned addr, @@ -32,7 +36,9 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { | |module MTraceDPI( | input [7:0] is_write, + | input [7:0] is_shared, | input [31:0] channel, + | input [63:0] hart_id, | input [31:0] vbank_id, | input [31:0] group_id, | input [31:0] addr, @@ -42,7 +48,7 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { |); | always @(*) begin | if (enable) begin - | dpi_mtrace(is_write, channel, vbank_id, group_id, addr, data_lo, data_hi); + | dpi_mtrace(is_write, is_shared, channel, hart_id, vbank_id, group_id, addr, data_lo, data_hi); | end | end |endmodule diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index de293be8..35d34a06 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -29,7 +29,9 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) for (mt <- mtraces) { mt.io.is_write := 0.U + mt.io.is_shared := 0.U mt.io.channel := 0.U + mt.io.hart_id := 0.U mt.io.vbank_id := 0.U mt.io.group_id := 0.U mt.io.addr := 0.U @@ -155,7 +157,9 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { en: Bool ): Unit = { mtraces(ch).io.is_write := isWrite + mtraces(ch).io.is_shared := io.mem_req(ch).is_shared.asUInt mtraces(ch).io.channel := ch.U + mtraces(ch).io.hart_id := io.mem_req(ch).hart_id mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id mtraces(ch).io.group_id := io.mem_req(ch).group_id mtraces(ch).io.addr := addr diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index 3ba532f8..c05c6edf 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -45,7 +45,9 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val mtraces = Seq.fill(b.memDomain.bankChannel*4)(Module(new MTraceDPI)) for (mt <- mtraces) { mt.io.is_write := 0.U + mt.io.is_shared := 0.U mt.io.channel := 0.U + mt.io.hart_id := 0.U mt.io.vbank_id := 0.U mt.io.group_id := 0.U mt.io.addr := 0.U @@ -175,7 +177,9 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { en: Bool ): Unit = { mtraces(ch).io.is_write := isWrite + mtraces(ch).io.is_shared := io.mem_req(ch).is_shared.asUInt mtraces(ch).io.channel := ch.U + mtraces(ch).io.hart_id := io.mem_req(ch).hart_id mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id mtraces(ch).io.group_id := io.mem_req(ch).group_id mtraces(ch).io.addr := addr From 737f1270c1b605698591c36c2fcad012b1680298 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Mon, 9 Mar 2026 21:36:18 +0800 Subject: [PATCH 159/238] [arch]fix:put two signal together on hartid --- .../src/main/scala/framework/memdomain/MemDomain.scala | 2 +- .../scala/framework/memdomain/backend/MemBackend.scala | 10 ++-------- .../framework/memdomain/frontend/MemFrontend.scala | 3 +++ .../frontend/outside_channel/MemConfiger.scala | 3 ++- 4 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 8c3f8742..003d0058 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -65,7 +65,7 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Connect query interface from frontend to backend backend.io.query_vbank_id := frontend.io.query_vbank_id frontend.io.query_group_count := backend.io.query_group_count - backend.io.hartid := io.hartid + frontend.io.hartid := io.hartid // ------------------------------------------------- // Connection with outside (all in frontend) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index ccfbb51e..9aa1e88a 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -19,23 +19,17 @@ class MemBackend(val b: GlobalConfig) extends Module { // Query interface for frontend to get group count val query_vbank_id = Input(UInt(8.W)) val query_group_count = Output(UInt(4.W)) - - val hartid = Input(UInt(b.core.xLen.W)) }) // Keep the private backend datapath unchanged and isolate it in a dedicated module. val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) - val cfgWithHart = Wire(new MemConfigerIO(b)) - cfgWithHart := io.config.bits - cfgWithHart.hart_id := io.hartid - // Broadcast config so alloc/release is handled by the corresponding backend. privateBackend.io.config.valid := io.config.valid - privateBackend.io.config.bits := cfgWithHart + privateBackend.io.config.bits := io.config.bits sharedBackend.io.config.valid := io.config.valid - sharedBackend.io.config.bits := cfgWithHart + sharedBackend.io.config.bits := io.config.bits io.config.ready := privateBackend.io.config.ready && sharedBackend.io.config.ready // Query both backends; shared takes priority when this vbank is allocated as shared. diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 1205da5a..f9c32a70 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -54,6 +54,8 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { val query_vbank_id = Output(UInt(8.W)) val query_group_count = Input(UInt(4.W)) + val hartid = Input(UInt(b.core.xLen.W)) + // Busy signal val busy = Output(Bool()) }) @@ -104,6 +106,7 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { memLoader.io.cmdReq <> memRs.io.issue_o.ld memStorer.io.cmdReq <> memRs.io.issue_o.st configer.io.cmdReq <> memRs.io.issue_o.cf + configer.io.hartid := io.hartid memRs.io.commit_i.ld <> memLoader.io.cmdResp memRs.io.commit_i.st <> memStorer.io.cmdResp memRs.io.commit_i.cf <> configer.io.cmdResp diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 2ed01ef7..2eca2ef6 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -25,6 +25,7 @@ class MemConfiger(val b: GlobalConfig) extends Module { val cmdResp = Decoupled(new MemRsComplete(b)) val config = Decoupled(new MemConfigerIO(b)) + val hartid = Input(UInt(b.core.xLen.W)) }) val idle :: config :: Nil = Enum(2) @@ -40,7 +41,7 @@ class MemConfiger(val b: GlobalConfig) extends Module { io.config.bits.alloc := false.B io.config.bits.vbank_id := 0.U(8.W) io.config.bits.group_id := 0.U(3.W) - io.config.bits.hart_id := 0.U(b.core.xLen.W) + io.config.bits.hart_id := io.hartid io.config.valid := false.B io.cmdResp.valid := false.B io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) From 9a6026644180a290848ee9b61fd77929444e2900 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 11 Mar 2026 13:10:46 +0800 Subject: [PATCH 160/238] [arch]refactor:let hardware detect is_shared automatically --- .../scala/framework/memdomain/MemDomain.scala | 1 + .../memdomain/backend/MemBackend.scala | 18 +++++----- .../memdomain/frontend/MemFrontend.scala | 2 ++ .../frontend/cmd_channel/decoder/DISA.scala | 2 -- .../cmd_channel/decoder/DomainDecoder.scala | 36 ++++--------------- .../outside_channel/MemConfiger.scala | 6 ++++ .../frontend/outside_channel/MemLoader.scala | 2 ++ .../frontend/outside_channel/MemStorer.scala | 2 ++ .../workloads/lib/bbhw/isa/21_shared_mvin.c | 13 ------- .../workloads/lib/bbhw/isa/22_shared_mvout.c | 13 ------- bb-tests/workloads/lib/bbhw/isa/isa.h | 2 -- 11 files changed, 27 insertions(+), 70 deletions(-) delete mode 100644 bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 003d0058..60772cd9 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -64,6 +64,7 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Connect query interface from frontend to backend backend.io.query_vbank_id := frontend.io.query_vbank_id + backend.io.query_is_shared := frontend.io.query_is_shared frontend.io.query_group_count := backend.io.query_group_count frontend.io.hartid := io.hartid diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 9aa1e88a..95eae4ee 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -18,6 +18,7 @@ class MemBackend(val b: GlobalConfig) extends Module { // Query interface for frontend to get group count val query_vbank_id = Input(UInt(8.W)) + val query_is_shared = Input(Bool()) val query_group_count = Output(UInt(4.W)) }) @@ -25,21 +26,18 @@ class MemBackend(val b: GlobalConfig) extends Module { val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) - // Broadcast config so alloc/release is handled by the corresponding backend. - privateBackend.io.config.valid := io.config.valid + // Route config to the selected backend only. + val cfgToShared = io.config.bits.is_shared + privateBackend.io.config.valid := io.config.valid && !cfgToShared privateBackend.io.config.bits := io.config.bits - sharedBackend.io.config.valid := io.config.valid + sharedBackend.io.config.valid := io.config.valid && cfgToShared sharedBackend.io.config.bits := io.config.bits - io.config.ready := privateBackend.io.config.ready && sharedBackend.io.config.ready + io.config.ready := Mux(cfgToShared, sharedBackend.io.config.ready, privateBackend.io.config.ready) - // Query both backends; shared takes priority when this vbank is allocated as shared. + // Query selected backend according to decoded shared/private intent. privateBackend.io.query_vbank_id := io.query_vbank_id sharedBackend.io.query_vbank_id := io.query_vbank_id - io.query_group_count := Mux( - sharedBackend.io.query_group_count =/= 0.U, - sharedBackend.io.query_group_count, - privateBackend.io.query_group_count - ) + io.query_group_count := Mux(io.query_is_shared, sharedBackend.io.query_group_count, privateBackend.io.query_group_count) // Per-channel request routing: is_shared=0 -> private, is_shared=1 -> shared. // Route selection is latched at request fire to keep response demux stable. diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index f9c32a70..6d713206 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -52,6 +52,7 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Query interface to backend for group count val query_vbank_id = Output(UInt(8.W)) + val query_is_shared = Output(Bool()) val query_group_count = Input(UInt(4.W)) val hartid = Input(UInt(b.core.xLen.W)) @@ -88,6 +89,7 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Connect query interfaces // Use memLoader's query by default, memStorer will override when active io.query_vbank_id := Mux(memStorer.io.cmdReq.valid, memStorer.io.query_vbank_id, memLoader.io.query_vbank_id) + io.query_is_shared := Mux(memStorer.io.cmdReq.valid, memStorer.io.query_is_shared, memLoader.io.query_is_shared) memLoader.io.query_group_count := io.query_group_count memStorer.io.query_group_count := io.query_group_count diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index 30637c78..886ee16c 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -5,8 +5,6 @@ import chisel3.util._ object DISA { - val SHARED_MVIN_BITPAT = BitPat("b0010101") // 21 - val SHARED_MVOUT_BITPAT = BitPat("b0010110") // 22 val MSET_BITPAT = BitPat("b0010111") // 23 val MVIN_BITPAT = BitPat("b0011000") // 24 val MVOUT_BITPAT = BitPat("b0011001") // 25 diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index e4ee056d..46f87b70 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -10,7 +10,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} // Detailed decode output for Mem domain class MemDecodeCmd(b: GlobalConfig) extends Bundle { - val is_shared = Bool() // Whether this is a shared memory access (for synchronization) + val is_shared = Bool() // Shared memory access marker derived from bank_id threshold. val is_load = Bool() val is_store = Bool() val is_config = Bool() @@ -27,7 +27,7 @@ class MemDecodeCmd(b: GlobalConfig) extends Bundle { // LS decode fields (iter removed from decode table — always from rs1[63:48]) object LSDecodeFields extends Enumeration { type Field = Value - val SHARED_EN, LD_EN, ST_EN, MEMADDR, BANK_ID, SPECIAL, VALID = Value + val LD_EN, ST_EN, MEMADDR, BANK_ID, SPECIAL, VALID = Value } // Default constants for Mem decoder @@ -67,14 +67,13 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // rs2[38:0] = mem_addr (for MVIN/MVOUT, 39-bit) // rs2[63:0] = special (full 64-bit) import LSDecodeFields._ - val ls_default_decode = List(N, N, N, DADDR, DADDR, DSPECIAL, N) + val ls_default_decode = List(N, N, DADDR, DADDR, DSPECIAL, N) val ls_decode_list = ListLookup( func7, ls_default_decode, Array( MSET_BITPAT -> List( - N, N, N, 0.U(memAddrLen.W), // mem_addr: not used for MSET @@ -83,7 +82,6 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { Y ), // mset MVIN_BITPAT -> List( - N, Y, N, rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] @@ -92,32 +90,13 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { Y ), // mvin MVOUT_BITPAT -> List( - N, - N, - Y, - rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] - rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] - rs2, // special = full rs2 - Y - ), // mvout - SHARED_MVIN_BITPAT -> List( - Y, - Y, - N, - rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] - rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] - rs2, // special = full rs2 - Y - ), // shared mvin - SHARED_MVOUT_BITPAT -> List( - Y, N, Y, rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] rs2, // special = full rs2 Y - ) // shared mvout + ) // mvout ) ) @@ -132,11 +111,8 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- io.mem_decode_cmd_o.valid := io.cmd_i.valid && (io.cmd_i.bits.domain_id === DomainId.MEM) - io.mem_decode_cmd_o.bits.is_shared := Mux( - io.mem_decode_cmd_o.valid, - ls_decode_list(LSDecodeFields.SHARED_EN.id).asBool, - false.B - ) + val raw_bank_id = rs1(bankIdLen - 1, 0) + io.mem_decode_cmd_o.bits.is_shared := io.mem_decode_cmd_o.valid && (raw_bank_id > 31.U) io.mem_decode_cmd_o.bits.is_load := Mux( io.mem_decode_cmd_o.valid, ls_decode_list(LSDecodeFields.LD_EN.id).asBool, diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 2eca2ef6..33990f4b 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -8,6 +8,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} class MemConfigerIO(val b: GlobalConfig) extends Bundle { val vbank_id = Output(UInt(8.W)) + val is_shared = Output(Bool()) val is_multi = Output(Bool()) val alloc = Output(Bool()) val group_id = Output(UInt(3.W)) @@ -31,6 +32,7 @@ class MemConfiger(val b: GlobalConfig) extends Module { val idle :: config :: Nil = Enum(2) val state = RegInit(idle) val alloc_reg = RegInit(false.B) + val is_shared_reg = RegInit(false.B) val row_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) @@ -38,6 +40,7 @@ class MemConfiger(val b: GlobalConfig) extends Module { val counter = RegInit(0.U(4.W)) io.config.bits.is_multi := false.B + io.config.bits.is_shared := false.B io.config.bits.alloc := false.B io.config.bits.vbank_id := 0.U(8.W) io.config.bits.group_id := 0.U(3.W) @@ -52,11 +55,13 @@ class MemConfiger(val b: GlobalConfig) extends Module { state := config col_reg := io.cmdReq.bits.cmd.special(9, 5) alloc_reg := io.cmdReq.bits.cmd.special(10) + is_shared_reg := io.cmdReq.bits.cmd.is_shared vbank_id_reg := io.cmdReq.bits.cmd.bank_id rob_id_reg := io.cmdReq.bits.rob_id }.otherwise { //not multi bank io.config.bits.alloc := io.cmdReq.bits.cmd.special(10) + io.config.bits.is_shared := io.cmdReq.bits.cmd.is_shared io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id io.config.valid := true.B @@ -67,6 +72,7 @@ class MemConfiger(val b: GlobalConfig) extends Module { }.otherwise { io.config.bits.is_multi := true.B + io.config.bits.is_shared := is_shared_reg io.config.bits.alloc := alloc_reg io.config.bits.vbank_id := vbank_id_reg io.config.bits.group_id := counter diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index fdb38045..c96a66d6 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -26,6 +26,7 @@ class MemLoader(val b: GlobalConfig) extends Module { // Query interface to get group count val query_vbank_id = Output(UInt(8.W)) + val query_is_shared = Output(Bool()) val query_group_count = Input(UInt(4.W)) // Propagate decoded shared/private access intent. @@ -115,6 +116,7 @@ class MemLoader(val b: GlobalConfig) extends Module { // When idle and cmdReq is valid, query the incoming bank_id // Otherwise use the registered bank_id io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, wr_bank_reg) + io.query_is_shared := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.is_shared, is_shared_reg) // DMA req accepted when(io.dmaReq.fire) { diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 7fdf8665..76761d9b 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -30,6 +30,7 @@ class MemStorer(val b: GlobalConfig) extends Module { // Query interface to get group count val query_vbank_id = Output(UInt(8.W)) + val query_is_shared = Output(Bool()) val query_group_count = Input(UInt(4.W)) // Propagate decoded shared/private access intent. @@ -104,6 +105,7 @@ class MemStorer(val b: GlobalConfig) extends Module { // When idle and cmdReq is valid, query the incoming bank_id // Otherwise use the registered bank_id io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, rd_bank_reg) + io.query_is_shared := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.is_shared, is_shared_reg) // ----------------------------- // SRAM read request diff --git a/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c b/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c deleted file mode 100644 index 1f5e3444..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/21_shared_mvin.c +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BB_SHARED_MVIN_H_ -#define _BB_SHARED_MVIN_H_ - -#include "isa.h" - -#define BB_SHARED_MVIN_FUNC7 21 - -#define bb_shared_mvin(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_WR | BB_ITER(depth)), \ - (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ - BB_SHARED_MVIN_FUNC7) - -#endif // _BB_SHARED_MVIN_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c b/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c deleted file mode 100644 index 31a7b045..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/22_shared_mvout.c +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BB_SHARED_MVOUT_H_ -#define _BB_SHARED_MVOUT_H_ - -#include "isa.h" - -#define BB_SHARED_MVOUT_FUNC7 22 - -#define bb_shared_mvout(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_RD0 | BB_ITER(depth)), \ - (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ - BB_SHARED_MVOUT_FUNC7) - -#endif // _BB_SHARED_MVOUT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 6e98cbfe..fd61d654 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -43,8 +43,6 @@ typedef int32_t result_t; : "memory") // Include all instruction definitions -#include "21_shared_mvin.c" -#include "22_shared_mvout.c" #include "23_mset.c" #include "24_mvin.c" #include "25_mvout.c" From 5bafdfc54dd30858d24707329c2f8fbe7173a9da Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 11 Mar 2026 15:29:42 +0800 Subject: [PATCH 161/238] [arch]fix:fix bugs of connection between sharedmem and balls --- .../memdomain/backend/MemBackend.scala | 40 +++++++++++++++++-- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 19 +++++++-- .../workloads/src/CTest/toy/aligned_matmul.c | 2 +- bb-tests/workloads/src/CTest/toy/bfp_test.c | 6 +-- .../workloads/src/CTest/toy/dequant_test.c | 4 +- .../src/CTest/toy/gemmini_matmul_test.c | 6 +-- .../workloads/src/CTest/toy/im2col_test.c | 4 +- .../src/CTest/toy/mvin_mvout_acc_test.c | 4 +- .../workloads/src/CTest/toy/mvin_mvout_test.c | 2 +- bb-tests/workloads/src/CTest/toy/quant_test.c | 4 +- bb-tests/workloads/src/CTest/toy/relu_test.c | 4 +- bb-tests/workloads/src/CTest/toy/tlb_test.c | 8 ++-- .../src/CTest/toy/transpose_16xn_test.c | 4 +- .../src/CTest/toy/transpose_matmul.c | 2 +- .../workloads/src/CTest/toy/transpose_test.c | 4 +- .../src/CTest/toy/vecunit_matmul_16xn_ones.c | 8 ++-- .../CTest/toy/vecunit_matmul_16xn_random1.c | 8 ++-- .../CTest/toy/vecunit_matmul_16xn_random2.c | 8 ++-- .../CTest/toy/vecunit_matmul_16xn_random3.c | 8 ++-- .../toy/vecunit_matmul_16xn_zero_random.c | 8 ++-- .../CTest/toy/vecunit_matmul_col_row_vector.c | 8 ++-- .../toy/vecunit_matmul_identity_random.c | 8 ++-- .../src/CTest/toy/vecunit_matmul_ones.c | 6 +-- .../src/CTest/toy/vecunit_matmul_random1.c | 8 ++-- .../src/CTest/toy/vecunit_matmul_random2.c | 8 ++-- .../src/CTest/toy/vecunit_matmul_random3.c | 8 ++-- .../CTest/toy/vecunit_matmul_row_col_vector.c | 8 ++-- .../CTest/toy/vecunit_matmul_zero_random.c | 8 ++-- 28 files changed, 130 insertions(+), 85 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index 95eae4ee..f1ff25e0 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -39,6 +39,28 @@ class MemBackend(val b: GlobalConfig) extends Module { sharedBackend.io.query_vbank_id := io.query_vbank_id io.query_group_count := Mux(io.query_is_shared, sharedBackend.io.query_group_count, privateBackend.io.query_group_count) + // Track whether a vbank is currently allocated in shared backend. + // Ball requests do not carry explicit shared/private info, so they are routed by this table. + private val vbankIdxWidth = log2Up(b.memDomain.bankNum) + val privateAllocByVbank = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) + val sharedAllocByVbank = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) + val cfgVbankIdx = io.config.bits.vbank_id(vbankIdxWidth - 1, 0) + when(io.config.fire) { + when(io.config.bits.alloc) { + when(io.config.bits.is_shared) { + sharedAllocByVbank(cfgVbankIdx) := true.B + }.otherwise { + privateAllocByVbank(cfgVbankIdx) := true.B + } + }.otherwise { + when(io.config.bits.is_shared) { + sharedAllocByVbank(cfgVbankIdx) := false.B + }.otherwise { + privateAllocByVbank(cfgVbankIdx) := false.B + } + } + } + // Per-channel request routing: is_shared=0 -> private, is_shared=1 -> shared. // Route selection is latched at request fire to keep response demux stable. val readPending = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) @@ -64,7 +86,19 @@ class MemBackend(val b: GlobalConfig) extends Module { } for (i <- 0 until b.memDomain.bankChannel) { - val useSharedReq = io.mem_req(i).is_shared + val isBallChannel = i < b.top.memBallChannelNum + val hasPrivateAlloc = privateAllocByVbank(io.mem_req(i).bank_id) + val hasSharedAlloc = sharedAllocByVbank(io.mem_req(i).bank_id) + val hasBallReq = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + when(isBallChannel.B && hasBallReq) { + assert( + !(hasPrivateAlloc && hasSharedAlloc), + "MemBackend ambiguous Ball route: idx=%d has both private and shared allocations\n", + io.mem_req(i).bank_id + ) + } + val ballRouteShared = hasSharedAlloc && !hasPrivateAlloc + val useSharedReq = Mux(isBallChannel.B, ballRouteShared, io.mem_req(i).is_shared) val useSharedReadResp = Mux(readPending(i), readRouteShared(i), useSharedReq) val useSharedWriteResp = Mux(writePending(i), writeRouteShared(i), useSharedReq) @@ -87,11 +121,11 @@ class MemBackend(val b: GlobalConfig) extends Module { // Metadata is passed to both backends; only selected backend receives valid req/resp-ready. privateBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id privateBackend.io.mem_req(i).group_id := io.mem_req(i).group_id - privateBackend.io.mem_req(i).is_shared := io.mem_req(i).is_shared + privateBackend.io.mem_req(i).is_shared := useSharedReq privateBackend.io.mem_req(i).hart_id := io.mem_req(i).hart_id sharedBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id sharedBackend.io.mem_req(i).group_id := io.mem_req(i).group_id - sharedBackend.io.mem_req(i).is_shared := io.mem_req(i).is_shared + sharedBackend.io.mem_req(i).is_shared := useSharedReq sharedBackend.io.mem_req(i).hart_id := io.mem_req(i).hart_id // Read request route diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index 9a0fcdc5..f8760fb8 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -5,14 +5,25 @@ #define BB_MSET_FUNC7 23 -#define bb_mset(bank_id, alloc, row, col) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_WR), \ - (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10)), \ +// Shared-bank software IDs are 1-based: shared_id=1 maps to hardware vbank_id=32. +#define BB_SHARED_BANK_OFFSET 31UL +#define BB_SHARED_BANK_ID(shared_id) ((shared_id) + BB_SHARED_BANK_OFFSET) + +#define bb_mset(bank_id, alloc, row, col) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_WR), \ + (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10)), \ BB_MSET_FUNC7) #define bb_mem_release(bank_id) bb_mset(bank_id, 0, 0, 0); #define bb_mem_alloc(bank_id, row, col) bb_mset(bank_id, 1, row, col) +#define bb_mem_alloc_private(bank_id, row, col) bb_mem_alloc(bank_id, row, col) +#define bb_mem_alloc_shared(shared_id, row, col) \ + bb_mem_alloc(BB_SHARED_BANK_ID(shared_id), row, col) + +#define bb_mem_release_private(bank_id) bb_mem_release(bank_id) +#define bb_mem_release_shared(shared_id) bb_mem_release(BB_SHARED_BANK_ID(shared_id)) + #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index e37b702f..d2c9b556 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -29,7 +29,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(acc_bank_id, 1, 4); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, op2_bank_id, DIM, 1); bb_transpose(op2_bank_id, op1_bank_id, size, 0); diff --git a/bb-tests/workloads/src/CTest/toy/bfp_test.c b/bb-tests/workloads/src/CTest/toy/bfp_test.c index a25c9e20..6a362ece 100644 --- a/bb-tests/workloads/src/CTest/toy/bfp_test.c +++ b/bb-tests/workloads/src/CTest/toy/bfp_test.c @@ -23,9 +23,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id // bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/dequant_test.c b/bb-tests/workloads/src/CTest/toy/dequant_test.c index 8d8ff0bc..32cc211f 100644 --- a/bb-tests/workloads/src/CTest/toy/dequant_test.c +++ b/bb-tests/workloads/src/CTest/toy/dequant_test.c @@ -43,8 +43,8 @@ void hw_dequant(int32_t *input, uint32_t *output, int num_words) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(wr_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(wr_bank_id, 1, 1); bb_mvin((uintptr_t)input, op1_bank_id, num_words, 1); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c index c78f0e0c..d102bd13 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c @@ -17,9 +17,9 @@ void hw_gemmini_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // B matrix int acc_bank_id = 2; // C output (accumulator width) - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); // Load A and B into SRAM banks bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 848608bf..182501ee 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -61,8 +61,8 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, 32, 1); uint64_t krow = KROW; diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index 38196e37..90742f67 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -19,13 +19,13 @@ int acc_mvin_mvout_pressure_test() { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); uint32_t acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(acc_bank_id, 1, 4); bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(acc_bank_id, 1, 4); bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test ACC mvin/mvout pressure %d FAILED\n", i); diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index b6325d7c..6d6aa8b4 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -13,7 +13,7 @@ static elem_t output_matrix[DIM * DIM] __attribute__((aligned(128))); int mvin_mvout_simple_test() { uint32_t bank_id = 0; - bb_mem_alloc(bank_id, 1, 1); + bb_mem_alloc_private(bank_id, 1, 1); for (int i = 0; i < 1; i++) { init_u8_random_matrix(input_matrix, DIM, DIM, 111); diff --git a/bb-tests/workloads/src/CTest/toy/quant_test.c b/bb-tests/workloads/src/CTest/toy/quant_test.c index 14d8a87f..8495e7b9 100644 --- a/bb-tests/workloads/src/CTest/toy/quant_test.c +++ b/bb-tests/workloads/src/CTest/toy/quant_test.c @@ -103,8 +103,8 @@ void hw_quant(uint32_t *input, int32_t *output, int num_words) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(wr_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(wr_bank_id, 1, 1); bb_mvin((uintptr_t)input, op1_bank_id, num_words, 1); diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index 88490015..b5006278 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -72,8 +72,8 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(wr_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(wr_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/tlb_test.c b/bb-tests/workloads/src/CTest/toy/tlb_test.c index 06e3926b..99be2502 100644 --- a/bb-tests/workloads/src/CTest/toy/tlb_test.c +++ b/bb-tests/workloads/src/CTest/toy/tlb_test.c @@ -76,7 +76,7 @@ int test_bare_mode(void) { disable_vm(); uint32_t bank_id = 0; - bb_mem_alloc(bank_id, 1, 1); + bb_mem_alloc_private(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 42); clear_u8_matrix(output_matrix, DIM, DIM); @@ -105,7 +105,7 @@ int test_sv39_identity(void) { enable_sv39(); uint32_t bank_id = 0; - bb_mem_alloc(bank_id, 1, 1); + bb_mem_alloc_private(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 77); clear_u8_matrix(output_matrix, DIM, DIM); @@ -136,7 +136,7 @@ int test_sfence_flush(void) { asm volatile("sfence.vma"); uint32_t bank_id = 0; - bb_mem_alloc(bank_id, 1, 1); + bb_mem_alloc_private(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 99); clear_u8_matrix(output_matrix, DIM, DIM); @@ -167,7 +167,7 @@ int test_repeated_sfence(void) { for (int i = 0; i < 4; i++) { asm volatile("sfence.vma"); - bb_mem_alloc(bank_id, 1, 1); + bb_mem_alloc_private(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 100 + i); clear_u8_matrix(output_matrix, DIM, DIM); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c index a6e56ef1..50daa329 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c @@ -14,8 +14,8 @@ void hw_transpose(elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_transpose(op1_bank_id, op2_bank_id, size, 0); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index 18f7bb42..42596493 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -25,7 +25,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(acc_bank_id, 1, 4); uint32_t col_stride = (size + DIM - 1) / DIM; for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index 597244ce..c815496c 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -76,8 +76,8 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_transpose(op1_bank_id, op2_bank_id, size, 0); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index 9ba00564..a2299d1b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 70842579..2850a533 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 874959c4..4bf8ce7e 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index 79f23613..6e7a45c1 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index bf53b6ce..8ce60586 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index 5bbc1204..8c3189b8 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -23,10 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index c2d63900..6d1a0511 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 75b0b131..1402e387 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -23,9 +23,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id // bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index 9230e985..8a53cf56 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -67,10 +67,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t acc_bank_id = 2; uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); // Initialize accumulator bank with zeros before matrix multiplication bb_mvin((uintptr_t)zero_matrix, acc_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index d08a62d8..8997f3a3 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index c2bf167c..9909e7b3 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index 88a53ec5..ee7258b0 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index 56f19874..fa51ca71 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); + bb_mem_alloc_private(op1_bank_id, 1, 1); + bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc_private(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); From 4abed3b6eb8e67ba5015bea7207253a6438b87b2 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 11 Mar 2026 16:48:48 +0800 Subject: [PATCH 162/238] [bbtest]fix:fix bugs of index of shared banks --- bb-tests/workloads/lib/bbhw/isa/23_mset.c | 10 ---------- bb-tests/workloads/src/CTest/toy/aligned_matmul.c | 2 +- bb-tests/workloads/src/CTest/toy/bfp_test.c | 6 +++--- bb-tests/workloads/src/CTest/toy/dequant_test.c | 4 ++-- bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c | 6 +++--- bb-tests/workloads/src/CTest/toy/im2col_test.c | 4 ++-- bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c | 4 ++-- bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c | 2 +- bb-tests/workloads/src/CTest/toy/quant_test.c | 4 ++-- bb-tests/workloads/src/CTest/toy/relu_test.c | 4 ++-- bb-tests/workloads/src/CTest/toy/tlb_test.c | 8 ++++---- bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c | 4 ++-- bb-tests/workloads/src/CTest/toy/transpose_matmul.c | 2 +- bb-tests/workloads/src/CTest/toy/transpose_test.c | 4 ++-- .../workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_16xn_random1.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_16xn_random2.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_16xn_random3.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_16xn_zero_random.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_col_row_vector.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_identity_random.c | 8 ++++---- bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c | 6 +++--- .../workloads/src/CTest/toy/vecunit_matmul_random1.c | 8 ++++---- .../workloads/src/CTest/toy/vecunit_matmul_random2.c | 8 ++++---- .../workloads/src/CTest/toy/vecunit_matmul_random3.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_row_col_vector.c | 8 ++++---- .../src/CTest/toy/vecunit_matmul_zero_random.c | 8 ++++---- 27 files changed, 78 insertions(+), 88 deletions(-) diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/23_mset.c index f8760fb8..31988429 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/23_mset.c @@ -5,10 +5,6 @@ #define BB_MSET_FUNC7 23 -// Shared-bank software IDs are 1-based: shared_id=1 maps to hardware vbank_id=32. -#define BB_SHARED_BANK_OFFSET 31UL -#define BB_SHARED_BANK_ID(shared_id) ((shared_id) + BB_SHARED_BANK_OFFSET) - #define bb_mset(bank_id, alloc, row, col) \ BUCKYBALL_INSTRUCTION_R_R( \ (BB_BANK0(bank_id) | BB_WR), \ @@ -19,11 +15,5 @@ #define bb_mem_alloc(bank_id, row, col) bb_mset(bank_id, 1, row, col) -#define bb_mem_alloc_private(bank_id, row, col) bb_mem_alloc(bank_id, row, col) -#define bb_mem_alloc_shared(shared_id, row, col) \ - bb_mem_alloc(BB_SHARED_BANK_ID(shared_id), row, col) - -#define bb_mem_release_private(bank_id) bb_mem_release(bank_id) -#define bb_mem_release_shared(shared_id) bb_mem_release(BB_SHARED_BANK_ID(shared_id)) #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c index d2c9b556..e37b702f 100644 --- a/bb-tests/workloads/src/CTest/toy/aligned_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/aligned_matmul.c @@ -29,7 +29,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, bb_mvin((uintptr_t)a + i * DIM, op2_bank_id, size + i * DIM, col_stride); } int acc_bank_id = 2; // virtual bank id - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); bb_mvin((uintptr_t)c, op2_bank_id, DIM, 1); bb_transpose(op2_bank_id, op1_bank_id, size, 0); diff --git a/bb-tests/workloads/src/CTest/toy/bfp_test.c b/bb-tests/workloads/src/CTest/toy/bfp_test.c index 6a362ece..a25c9e20 100644 --- a/bb-tests/workloads/src/CTest/toy/bfp_test.c +++ b/bb-tests/workloads/src/CTest/toy/bfp_test.c @@ -23,9 +23,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id // bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/dequant_test.c b/bb-tests/workloads/src/CTest/toy/dequant_test.c index 32cc211f..8d8ff0bc 100644 --- a/bb-tests/workloads/src/CTest/toy/dequant_test.c +++ b/bb-tests/workloads/src/CTest/toy/dequant_test.c @@ -43,8 +43,8 @@ void hw_dequant(int32_t *input, uint32_t *output, int num_words) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(wr_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); bb_mvin((uintptr_t)input, op1_bank_id, num_words, 1); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c index d102bd13..c78f0e0c 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c @@ -17,9 +17,9 @@ void hw_gemmini_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // B matrix int acc_bank_id = 2; // C output (accumulator width) - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); // Load A and B into SRAM banks bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 182501ee..848608bf 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -61,8 +61,8 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, 32, 1); uint64_t krow = KROW; diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c index 90742f67..38196e37 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_acc_test.c @@ -19,13 +19,13 @@ int acc_mvin_mvout_pressure_test() { init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); uint32_t acc_bank_id = 2; // virtual bank id - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)expected_matrix, acc_bank_id, DIM, 1); init_u32_random_matrix(expected_matrix, DIM, DIM, i * 10 + i); clear_u32_matrix(output_matrix, DIM, DIM); acc_bank_id = 2; // virtual bank id - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); if (!compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { printf("Test ACC mvin/mvout pressure %d FAILED\n", i); diff --git a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c index 6d6aa8b4..b6325d7c 100644 --- a/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c +++ b/bb-tests/workloads/src/CTest/toy/mvin_mvout_test.c @@ -13,7 +13,7 @@ static elem_t output_matrix[DIM * DIM] __attribute__((aligned(128))); int mvin_mvout_simple_test() { uint32_t bank_id = 0; - bb_mem_alloc_private(bank_id, 1, 1); + bb_mem_alloc(bank_id, 1, 1); for (int i = 0; i < 1; i++) { init_u8_random_matrix(input_matrix, DIM, DIM, 111); diff --git a/bb-tests/workloads/src/CTest/toy/quant_test.c b/bb-tests/workloads/src/CTest/toy/quant_test.c index 8495e7b9..14d8a87f 100644 --- a/bb-tests/workloads/src/CTest/toy/quant_test.c +++ b/bb-tests/workloads/src/CTest/toy/quant_test.c @@ -103,8 +103,8 @@ void hw_quant(uint32_t *input, int32_t *output, int num_words) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(wr_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); bb_mvin((uintptr_t)input, op1_bank_id, num_words, 1); diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index b5006278..88490015 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -72,8 +72,8 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t wr_bank_id = 1; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(wr_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(wr_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/tlb_test.c b/bb-tests/workloads/src/CTest/toy/tlb_test.c index 99be2502..06e3926b 100644 --- a/bb-tests/workloads/src/CTest/toy/tlb_test.c +++ b/bb-tests/workloads/src/CTest/toy/tlb_test.c @@ -76,7 +76,7 @@ int test_bare_mode(void) { disable_vm(); uint32_t bank_id = 0; - bb_mem_alloc_private(bank_id, 1, 1); + bb_mem_alloc(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 42); clear_u8_matrix(output_matrix, DIM, DIM); @@ -105,7 +105,7 @@ int test_sv39_identity(void) { enable_sv39(); uint32_t bank_id = 0; - bb_mem_alloc_private(bank_id, 1, 1); + bb_mem_alloc(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 77); clear_u8_matrix(output_matrix, DIM, DIM); @@ -136,7 +136,7 @@ int test_sfence_flush(void) { asm volatile("sfence.vma"); uint32_t bank_id = 0; - bb_mem_alloc_private(bank_id, 1, 1); + bb_mem_alloc(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 99); clear_u8_matrix(output_matrix, DIM, DIM); @@ -167,7 +167,7 @@ int test_repeated_sfence(void) { for (int i = 0; i < 4; i++) { asm volatile("sfence.vma"); - bb_mem_alloc_private(bank_id, 1, 1); + bb_mem_alloc(bank_id, 1, 1); init_u8_random_matrix(input_matrix, DIM, DIM, 100 + i); clear_u8_matrix(output_matrix, DIM, DIM); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c index 50daa329..a6e56ef1 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c @@ -14,8 +14,8 @@ void hw_transpose(elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_transpose(op1_bank_id, op2_bank_id, size, 0); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c index 42596493..18f7bb42 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_matmul.c @@ -25,7 +25,7 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t op2_bank_id = 1; // acc0: write to accumulator, offset 0 int acc_bank_id = 2; // virtual bank id - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(acc_bank_id, 1, 4); uint32_t col_stride = (size + DIM - 1) / DIM; for (int i = 0; i < col_stride; i++) { bb_mvin((uintptr_t)a + i * DIM, op2_bank_id + size + i * DIM, DIM, diff --git a/bb-tests/workloads/src/CTest/toy/transpose_test.c b/bb-tests/workloads/src/CTest/toy/transpose_test.c index c815496c..597244ce 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_test.c @@ -76,8 +76,8 @@ void hw_transpose(const char *test_name, elem_t *a, elem_t *b, int size) { // spad1: operand B, offset 0 uint32_t op2_bank_id = 1; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_transpose(op1_bank_id, op2_bank_id, size, 0); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c index a2299d1b..9ba00564 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_ones.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c index 2850a533..70842579 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random1.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c index 4bf8ce7e..874959c4 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random2.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c index 6e7a45c1..79f23613 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_random3.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c index 8ce60586..bf53b6ce 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_16xn_zero_random.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c index 8c3189b8..5bbc1204 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_col_row_vector.c @@ -23,10 +23,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c index 6d1a0511..c2d63900 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_identity_random.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c index 1402e387..75b0b131 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_ones.c @@ -23,9 +23,9 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, int acc_bank_id = 2; // virtual bank id // bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c index 8a53cf56..9230e985 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random1.c @@ -67,10 +67,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, uint32_t acc_bank_id = 2; uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); // Initialize accumulator bank with zeros before matrix multiplication bb_mvin((uintptr_t)zero_matrix, acc_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c index 8997f3a3..d08a62d8 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random2.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c index 9909e7b3..c2bf167c 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c index ee7258b0..88a53ec5 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_row_col_vector.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c index fa51ca71..56f19874 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_zero_random.c @@ -22,10 +22,10 @@ void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, // spad3: transposed A uint32_t a_transposed_bank_id = 3; - bb_mem_alloc_private(op1_bank_id, 1, 1); - bb_mem_alloc_private(op2_bank_id, 1, 1); - bb_mem_alloc_private(acc_bank_id, 1, 4); - bb_mem_alloc_private(a_transposed_bank_id, 1, 1); + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); bb_mvin((uintptr_t)a, op1_bank_id, size, 1); bb_mvin((uintptr_t)b, op2_bank_id, size, 1); From 9e65082d08171a7cc886adfcd4623daad99abd44 Mon Sep 17 00:00:00 2001 From: Shiroha Date: Wed, 11 Mar 2026 20:45:31 +0800 Subject: [PATCH 163/238] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2e44a5b3..09da5643 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ [![Ask DeepWiki](https://deepwiki.com/badge.svg)](https://deepwiki.com/DangoSys/buckyball) [![zread](https://img.shields.io/badge/Ask_Zread-_.svg?style=flat&color=00b0aa&labelColor=000000&logo=data%3Aimage%2Fsvg%2Bxml%3Bbase64%2CPHN2ZyB3aWR0aD0iMTYiIGhlaWdodD0iMTYiIHZpZXdCb3g9IjAgMCAxNiAxNiIgZmlsbD0ibm9uZSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIj4KPHBhdGggZD0iTTQuOTYxNTYgMS42MDAxSDIuMjQxNTZDMS44ODgxIDEuNjAwMSAxLjYwMTU2IDEuODg2NjQgMS42MDE1NiAyLjI0MDFWNC45NjAxQzEuNjAxNTYgNS4zMTM1NiAxLjg4ODEgNS42MDAxIDIuMjQxNTYgNS42MDAxSDQuOTYxNTZDNS4zMTUwMiA1LjYwMDEgNS42MDE1NiA1LjMxMzU2IDUuNjAxNTYgNC45NjAxVjIuMjQwMUM1LjYwMTU2IDEuODg2NjQgNS4zMTUwMiAxLjYwMDEgNC45NjE1NiAxLjYwMDFaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00Ljk2MTU2IDEwLjM5OTlIMi4yNDE1NkMxLjg4ODEgMTAuMzk5OSAxLjYwMTU2IDEwLjY4NjQgMS42MDE1NiAxMS4wMzk5VjEzLjc1OTlDMS42MDE1NiAxNC4xMTM0IDEuODg4MSAxNC4zOTk5IDIuMjQxNTYgMTQuMzk5OUg0Ljk2MTU2QzUuMzE1MDIgMTQuMzk5OSA1LjYwMTU2IDE0LjExMzQgNS42MDE1NiAxMy43NTk5VjExLjAzOTlDNS42MDE1NiAxMC42ODY0IDUuMzE1MDIgMTAuMzk5OSA0Ljk2MTU2IDEwLjM5OTlaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik0xMy43NTg0IDEuNjAwMUgxMS4wMzg0QzEwLjY4NSAxLjYwMDEgMTAuMzk4NCAxLjg4NjY0IDEwLjM5ODQgMi4yNDAxVjQuOTYwMUMxMC4zOTg0IDUuMzEzNTYgMTAuNjg1IDUuNjAwMSAxMS4wMzg0IDUuNjAwMUgxMy43NTg0QzE0LjExMTkgNS42MDAxIDE0LjM5ODQgNS4zMTM1NiAxNC4zOTg0IDQuOTYwMVYyLjI0MDFDMTQuMzk4NCAxLjg4NjY0IDE0LjExMTkgMS42MDAxIDEzLjc1ODQgMS42MDAxWiIgZmlsbD0iI2ZmZiIvPgo8cGF0aCBkPSJNNCAxMkwxMiA0TDQgMTJaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00IDEyTDEyIDQiIHN0cm9rZT0iI2ZmZiIgc3Ryb2tlLXdpZHRoPSIxLjUiIHN0cm9rZS1saW5lY2FwPSJyb3VuZCIvPgo8L3N2Zz4K&logoColor=ffffff)](https://zread.ai/DangoSys/buckyball) -[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://175.178.48.176/docs/en/Overview/Overview.md) +[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://www,buckyball.tech/docs/en/Overview/Overview.md) [![buckyball CI](https://github.com/DangoSys/buckyball/actions/workflows/test.yml/badge.svg)](https://github.com/DangoSys/buckyball/actions/workflows/test.yml) From a8ab1c99008f78ab3f6c022dba38c3f27d4fedb7 Mon Sep 17 00:00:00 2001 From: Shiroha Date: Wed, 11 Mar 2026 20:46:38 +0800 Subject: [PATCH 164/238] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 09da5643..be2949c4 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ [![Ask DeepWiki](https://deepwiki.com/badge.svg)](https://deepwiki.com/DangoSys/buckyball) [![zread](https://img.shields.io/badge/Ask_Zread-_.svg?style=flat&color=00b0aa&labelColor=000000&logo=data%3Aimage%2Fsvg%2Bxml%3Bbase64%2CPHN2ZyB3aWR0aD0iMTYiIGhlaWdodD0iMTYiIHZpZXdCb3g9IjAgMCAxNiAxNiIgZmlsbD0ibm9uZSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIj4KPHBhdGggZD0iTTQuOTYxNTYgMS42MDAxSDIuMjQxNTZDMS44ODgxIDEuNjAwMSAxLjYwMTU2IDEuODg2NjQgMS42MDE1NiAyLjI0MDFWNC45NjAxQzEuNjAxNTYgNS4zMTM1NiAxLjg4ODEgNS42MDAxIDIuMjQxNTYgNS42MDAxSDQuOTYxNTZDNS4zMTUwMiA1LjYwMDEgNS42MDE1NiA1LjMxMzU2IDUuNjAxNTYgNC45NjAxVjIuMjQwMUM1LjYwMTU2IDEuODg2NjQgNS4zMTUwMiAxLjYwMDEgNC45NjE1NiAxLjYwMDFaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00Ljk2MTU2IDEwLjM5OTlIMi4yNDE1NkMxLjg4ODEgMTAuMzk5OSAxLjYwMTU2IDEwLjY4NjQgMS42MDE1NiAxMS4wMzk5VjEzLjc1OTlDMS42MDE1NiAxNC4xMTM0IDEuODg4MSAxNC4zOTk5IDIuMjQxNTYgMTQuMzk5OUg0Ljk2MTU2QzUuMzE1MDIgMTQuMzk5OSA1LjYwMTU2IDE0LjExMzQgNS42MDE1NiAxMy43NTk5VjExLjAzOTlDNS42MDE1NiAxMC42ODY0IDUuMzE1MDIgMTAuMzk5OSA0Ljk2MTU2IDEwLjM5OTlaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik0xMy43NTg0IDEuNjAwMUgxMS4wMzg0QzEwLjY4NSAxLjYwMDEgMTAuMzk4NCAxLjg4NjY0IDEwLjM5ODQgMi4yNDAxVjQuOTYwMUMxMC4zOTg0IDUuMzEzNTYgMTAuNjg1IDUuNjAwMSAxMS4wMzg0IDUuNjAwMUgxMy43NTg0QzE0LjExMTkgNS42MDAxIDE0LjM5ODQgNS4zMTM1NiAxNC4zOTg0IDQuOTYwMVYyLjI0MDFDMTQuMzk4NCAxLjg4NjY0IDE0LjExMTkgMS42MDAxIDEzLjc1ODQgMS42MDAxWiIgZmlsbD0iI2ZmZiIvPgo8cGF0aCBkPSJNNCAxMkwxMiA0TDQgMTJaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00IDEyTDEyIDQiIHN0cm9rZT0iI2ZmZiIgc3Ryb2tlLXdpZHRoPSIxLjUiIHN0cm9rZS1saW5lY2FwPSJyb3VuZCIvPgo8L3N2Zz4K&logoColor=ffffff)](https://zread.ai/DangoSys/buckyball) -[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://www,buckyball.tech/docs/en/Overview/Overview.md) +[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://www.buckyball.tech/docs/en/Overview/Overview.md) [![buckyball CI](https://github.com/DangoSys/buckyball/actions/workflows/test.yml/badge.svg)](https://github.com/DangoSys/buckyball/actions/workflows/test.yml) From 49b1ac1798a223acae7088053e633b1362b8e5b2 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 12:08:51 +0800 Subject: [PATCH 165/238] [bdb] feat: add MMIO support and UART output handling [arch] feat: first version of goban [bb-tests] del: remove the fevsr and htif requirements --- .gitignore | 1 + arch/build.sc | 29 +- arch/src/csrc/include/bdb.h | 18 +- arch/src/csrc/include/ioe/mmio.h | 14 + arch/src/csrc/include/monitor/cosim.h | 160 ------ arch/src/csrc/include/monitor/halt.h | 16 + arch/src/csrc/include/monitor/trace.h | 70 ++- arch/src/csrc/src/main.cc | 60 +-- arch/src/csrc/src/monitor/cosim/cosim.cc | 491 ------------------ arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc | 279 ++++++++++ arch/src/csrc/src/monitor/ioe/mem.cc | 41 -- arch/src/csrc/src/monitor/ioe/mmio.cc | 48 ++ arch/src/csrc/src/monitor/monitor.cc | 65 +-- arch/src/csrc/src/monitor/trace/ctrace.cc | 135 +++++ arch/src/csrc/src/monitor/trace/halt.cc | 9 + .../scala/examples/goban/CustomConfigs.scala | 40 ++ .../scala/examples/toy/CustomConfigs.scala | 134 +---- .../scala/examples/toy/balldomain/DISA.scala | 4 + .../toy/balldomain/DomainDecoder.scala | 5 +- .../toy/balldomain/bbus/busRegister.scala | 2 + .../framework/balldomain/configs/default.json | 5 +- .../balldomain/prototype/trace/README.md | 132 +++++ .../balldomain/prototype/trace/Trace.scala | 365 +++++++++++++ .../prototype/trace/TraceBall.scala | 43 ++ .../balldomain/prototype/trace/TraceDPI.scala | 231 ++++++++ .../scala/framework/core/bbtile/BBTile.scala | 169 +++--- .../framework/core/bbtile/BarrierUnit.scala | 34 ++ .../core/bbtile/BuckyballAccelerator.scala | 22 + .../scala/framework/frontend/Frontend.scala | 8 + .../framework/frontend/decoder/GISA.scala | 3 +- .../frontend/decoder/GobalDecoder.scala | 5 +- .../globalrs/GlobalReservationStation.scala | 48 +- .../scala/framework/memdomain/MemDomain.scala | 38 +- .../memdomain/backend/MemBackend.scala | 88 ++-- .../memdomain/backend/shared/SharedMem.scala | 17 +- .../backend/shared/SharedMemBackend.scala | 38 +- .../framework/top/configs/TopConfig.scala | 3 +- .../scala/framework/top/configs/default.json | 3 +- .../scala/sims/palladium/TargetConfigs.scala | 26 +- .../scala/sims/pegasus/PegasusHarness.scala | 125 +++++ .../sims/pegasus/PegasusHarnessBinders.scala | 68 +++ .../scala/sims/pegasus/TargetConfigs.scala | 45 ++ .../scala/sims/verilator/BBSimHarness.scala | 146 ++++++ .../scala/sims/verilator/TargetConfig.scala | 40 ++ bb-tests/workloads/CMakeLists.txt | 1 + .../workloads/lib/bbhw/isa/48_bdb_counter.c | 33 ++ .../workloads/lib/bbhw/isa/49_bdb_backdoor.c | 26 + bb-tests/workloads/lib/bbhw/isa/50_barrier.c | 22 + bb-tests/workloads/lib/bbhw/isa/isa.h | 3 + bb-tests/workloads/src/CTest/CMakeLists.txt | 1 + .../workloads/src/CTest/goban/CMakeLists.txt | 55 ++ .../src/CTest/goban/barrier_mvin_test.c | 83 +++ .../workloads/src/CTest/goban/barrier_test.c | 66 +++ bb-tests/workloads/src/CTest/goban/goban.h | 14 + bb-tests/workloads/src/CTest/goban/start.S | 21 + .../workloads/src/CTest/toy/CMakeLists.txt | 10 +- bb-tests/workloads/src/CTest/toy/bbsim.ld | 38 ++ .../src/CTest/toy/bdb_backdoor_test.c | 52 ++ .../src/CTest/toy/bdb_counter_test.c | 65 +++ bb-tests/workloads/src/CTest/toy/buckyball.c | 23 + bb-tests/workloads/src/CTest/toy/crt0.S | 25 + .../workloads/src/CTest/toy/im2col_test.c | 2 - .../src/CTest/toy/transpose_16xn_test.c | 8 +- bbdev | 2 +- bebop | 2 +- flake.nix | 4 +- pegasus/.gitignore | 5 + pegasus/README.md | 2 + .../src/main/scala/pegasus/PegasusShell.scala | 462 ++++++++++++++++ .../chisel/src/main/scala/pegasus/SCU.scala | 207 ++++++++ .../src/main/scala/pegasus/UARTCapture.scala | 128 +++++ .../scala/pegasus/blackbox/HBM2BlackBox.scala | 115 ++++ .../scala/pegasus/blackbox/XDMABlackBox.scala | 170 ++++++ pegasus/driver/.gitignore | 2 + pegasus/driver/CMakeLists.txt | 35 ++ pegasus/driver/include/pegasus.h | 132 +++++ pegasus/driver/src/elf.cc | 185 +++++++ pegasus/driver/src/main.cc | 156 ++++++ pegasus/driver/src/scu.cc | 49 ++ pegasus/driver/src/uart.cc | 17 + pegasus/driver/src/xdma.cc | 124 +++++ pegasus/flake.lock | 61 +++ pegasus/flake.nix | 89 ++++ pegasus/vivado/au280.xdc | 79 +++ pegasus/vivado/build.tcl | 169 ++++++ pegasus/vivado/ip/axi_crossbar_ip.tcl | 37 ++ pegasus/vivado/ip/hbm2_ip.tcl | 31 ++ pegasus/vivado/ip/xdma_ip.tcl | 25 + pegasus/vivado/synth_only.tcl | 58 +++ 89 files changed, 5077 insertions(+), 1140 deletions(-) create mode 100644 arch/src/csrc/include/ioe/mmio.h delete mode 100644 arch/src/csrc/include/monitor/cosim.h create mode 100644 arch/src/csrc/include/monitor/halt.h delete mode 100644 arch/src/csrc/src/monitor/cosim/cosim.cc create mode 100644 arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc delete mode 100644 arch/src/csrc/src/monitor/ioe/mem.cc create mode 100644 arch/src/csrc/src/monitor/ioe/mmio.cc create mode 100644 arch/src/csrc/src/monitor/trace/ctrace.cc create mode 100644 arch/src/csrc/src/monitor/trace/halt.cc create mode 100644 arch/src/main/scala/examples/goban/CustomConfigs.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/trace/README.md create mode 100644 arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala create mode 100644 arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala create mode 100644 arch/src/main/scala/sims/pegasus/PegasusHarness.scala create mode 100644 arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala create mode 100644 arch/src/main/scala/sims/pegasus/TargetConfigs.scala create mode 100644 arch/src/main/scala/sims/verilator/BBSimHarness.scala create mode 100644 bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/50_barrier.c create mode 100644 bb-tests/workloads/src/CTest/goban/CMakeLists.txt create mode 100644 bb-tests/workloads/src/CTest/goban/barrier_mvin_test.c create mode 100644 bb-tests/workloads/src/CTest/goban/barrier_test.c create mode 100644 bb-tests/workloads/src/CTest/goban/goban.h create mode 100644 bb-tests/workloads/src/CTest/goban/start.S create mode 100644 bb-tests/workloads/src/CTest/toy/bbsim.ld create mode 100644 bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/bdb_counter_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/crt0.S create mode 100644 pegasus/.gitignore create mode 100644 pegasus/README.md create mode 100644 pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala create mode 100644 pegasus/chisel/src/main/scala/pegasus/SCU.scala create mode 100644 pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala create mode 100644 pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala create mode 100644 pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala create mode 100644 pegasus/driver/.gitignore create mode 100644 pegasus/driver/CMakeLists.txt create mode 100644 pegasus/driver/include/pegasus.h create mode 100644 pegasus/driver/src/elf.cc create mode 100644 pegasus/driver/src/main.cc create mode 100644 pegasus/driver/src/scu.cc create mode 100644 pegasus/driver/src/uart.cc create mode 100644 pegasus/driver/src/xdma.cc create mode 100644 pegasus/flake.lock create mode 100644 pegasus/flake.nix create mode 100644 pegasus/vivado/au280.xdc create mode 100644 pegasus/vivado/build.tcl create mode 100644 pegasus/vivado/ip/axi_crossbar_ip.tcl create mode 100644 pegasus/vivado/ip/hbm2_ip.tcl create mode 100644 pegasus/vivado/ip/xdma_ip.tcl create mode 100644 pegasus/vivado/synth_only.tcl diff --git a/.gitignore b/.gitignore index f2b9252c..1dd60dae 100644 --- a/.gitignore +++ b/.gitignore @@ -12,6 +12,7 @@ env.sh mill.* index.html +*.jou *.vcd *.fst *.log diff --git a/arch/build.sc b/arch/build.sc index 8de92d6a..9c8180f5 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -23,7 +23,8 @@ object buckyball extends SbtModule { m => override def moduleDeps = Seq( chipyard, firechip, - palladium + palladium, + pegasus ) override def ivyDeps = Agg( @@ -962,3 +963,29 @@ object palladium extends SbtModule { ) } + +// Pegasus FPGA framework Chisel sources +// Physical location: pegasus/chisel/ (outside arch/) +// Pure Chisel only — no Chipyard dependency (avoids circular dep with buckyball) +// buckyball depends on pegasus (one-way) +object pegasus extends SbtModule { + override def millSourcePath = os.pwd / os.up / "pegasus" / "chisel" + override def scalaVersion = "2.13.12" + + override def ivyDeps = Agg( + ivy"org.chipsalliance::chisel:6.5.0" + ) + + override def scalacPluginIvyDeps = Agg( + ivy"org.chipsalliance:::chisel-plugin:6.5.0" + ) + + override def scalacOptions = Seq( + "-language:reflectiveCalls", + "-deprecation", + "-feature", + "-Xcheckinit", + "-Ymacro-annotations" + ) + +} diff --git a/arch/src/csrc/include/bdb.h b/arch/src/csrc/include/bdb.h index c3e39a15..9a5e4704 100644 --- a/arch/src/csrc/include/bdb.h +++ b/arch/src/csrc/include/bdb.h @@ -3,34 +3,32 @@ // DPI-C #include "verilated_dpi.h" -// #include "Vtop__Dpi.h" #include "svdpi.h" // verilator #include "verilated.h" -// #include "verilated_vcd_c.h" - -#ifdef COSIM -#include "VToyBuckyball.h" -#else -#include "VTestHarness.h" -#endif +#include "VBBSimHarness.h" #include "verilated_fst_c.h" #if VM_COVERAGE #include "verilated_cov.h" #endif +extern VBBSimHarness *top; + // ================ BDB Config =================== -// VCD file path -extern const char *vcd_path; // Log file path extern const char *log_path; // FST file path extern const char *fst_path; +// UART stdout file path +extern const char *stdout_path; +// Raw stdout fd saved before dup2 — UART writes here for real-time display +extern int raw_stdout_fd; void init_monitor(int argc, char *argv[]); void bdb_mainloop(); void ball_exec_once(); void bdb_set_batch_mode(); +void sim_exit(); #endif // _BDB_H_ diff --git a/arch/src/csrc/include/ioe/mmio.h b/arch/src/csrc/include/ioe/mmio.h new file mode 100644 index 00000000..dfd26022 --- /dev/null +++ b/arch/src/csrc/include/ioe/mmio.h @@ -0,0 +1,14 @@ +#ifndef _MMIO_H_ +#define _MMIO_H_ + +// mmio_tick: called at posedge (before 2nd eval) to drive ready/valid signals. +// mmio_tick_post: called after 2nd eval to observe RTL's b_ready/r_ready and +// immediately clear b_pending/r_pending if handshake completed in this cycle. +// +// Address map: +// 0x6000_0000 : simulation exit — write triggers sim_exit() +// 0x6002_0000 : UART0 TX — write low byte → putchar +void mmio_tick(); +void mmio_tick_post(); + +#endif // _MMIO_H_ diff --git a/arch/src/csrc/include/monitor/cosim.h b/arch/src/csrc/include/monitor/cosim.h deleted file mode 100644 index 716c8a62..00000000 --- a/arch/src/csrc/include/monitor/cosim.h +++ /dev/null @@ -1,160 +0,0 @@ -#ifndef MONITOR_COSIM_H_ -#define MONITOR_COSIM_H_ - -#include -#include -#include -#include -#include -#include - -// Forward declaration for VToyBuckyball -class VToyBuckyball; - -// Socket protocol structures (match bebop/host/ipc/include/ipc/socket.h) -// Verilator uses different ports (7000-7002) to avoid conflict with Bebop's -// server (6000-6002) -#define SOCKET_CMD_PORT 7000 -#define SOCKET_DMA_READ_PORT 7001 -#define SOCKET_DMA_WRITE_PORT 7002 - -enum socket_msg_type_t : uint32_t { - MSG_TYPE_CMD_REQ = 0, - MSG_TYPE_CMD_RESP = 1, - MSG_TYPE_DMA_READ_REQ = 2, - MSG_TYPE_DMA_READ_RESP = 3, - MSG_TYPE_DMA_WRITE_REQ = 4, - MSG_TYPE_DMA_WRITE_RESP = 5 -}; - -struct msg_header_t { - uint32_t msg_type; - uint32_t reserved; -}; - -struct cmd_req_t { - msg_header_t header; - uint32_t funct; - uint32_t padding; - uint64_t xs1; - uint64_t xs2; -}; - -struct cmd_resp_t { - msg_header_t header; - uint64_t result; -}; - -struct dma_read_req_t { - msg_header_t header; - uint32_t size; - uint32_t padding; - uint64_t addr; -}; - -struct dma_read_resp_t { - msg_header_t header; - uint64_t data_lo; - uint64_t data_hi; -}; - -struct dma_write_req_t { - msg_header_t header; - uint32_t size; - uint32_t padding; - uint64_t addr; - uint64_t data_lo; - uint64_t data_hi; -}; - -struct dma_write_resp_t { - msg_header_t header; - uint64_t reserved; -}; - -// TileLink transaction for pending DMA requests -struct tilelink_transaction_t { - uint8_t opcode; // TileLink opcode (0/1=Put, 4=Get) - uint8_t source; // Transaction ID - uint32_t address; // Memory address - uint8_t size; // Transfer size (2^size bytes) - uint16_t mask; // Byte mask - uint64_t data_lo; // Data low 64 bits (for write) - uint64_t data_hi; // Data high 64 bits (for write) -}; - -// Cosim socket server for VToyBuckyball -class CosimServer { -public: - CosimServer(VToyBuckyball *dut); - ~CosimServer(); - - // Initialize socket servers and start listening - bool init(); - - // Shutdown all connections - void shutdown(); - - // Main update function - called each cycle to handle socket I/O and drive DUT - void update(); - - // Check if server is running - bool is_running() const { return server_running; } - -private: - VToyBuckyball *dut; - std::atomic server_running; - - // Socket file descriptors - int cmd_server_fd; - int dma_read_server_fd; - int dma_write_server_fd; - int cmd_client_fd; - int dma_read_client_fd; - int dma_write_client_fd; - - // Background threads for socket I/O - std::thread cmd_thread; - std::thread dma_read_thread; - std::thread dma_write_thread; - - // CMD queue (Bebop -> Verilator) - std::queue cmd_queue; - std::mutex cmd_mutex; - std::condition_variable cmd_cv; - - // TileLink request queue (Verilator -> Bebop) - std::queue tl_req_queue; - std::mutex tl_req_mutex; - - // TileLink response queue (Bebop -> Verilator) - std::queue tl_resp_queue; - std::mutex tl_resp_mutex; - - // Current CMD being processed - bool cmd_in_progress; - cmd_req_t current_cmd; - - // Socket thread functions - void cmd_server_thread(); - void dma_read_server_thread(); - void dma_write_server_thread(); - - // Socket helpers - int create_server_socket(int port); - int accept_client(int server_fd); - bool recv_all(int fd, void *buf, size_t len); - bool send_all(int fd, const void *buf, size_t len); - - // CMD processing - void handle_cmd_request(); - void drive_cmd_interface(); - - // TileLink/DMA processing - void sample_tilelink_request(); - void drive_tilelink_response(); - void process_dma_read_request(const tilelink_transaction_t &tx); - void process_dma_write_request(const tilelink_transaction_t &tx); -}; - -#endif // MONITOR_COSIM_H_ diff --git a/arch/src/csrc/include/monitor/halt.h b/arch/src/csrc/include/monitor/halt.h new file mode 100644 index 00000000..c336cf9f --- /dev/null +++ b/arch/src/csrc/include/monitor/halt.h @@ -0,0 +1,16 @@ +#ifndef MONITOR_HALT_H_ +#define MONITOR_HALT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +// DPI-C function called by HaltDPI.sv when ebreak is detected +// Triggers bdb sim_exit() from within the simulation loop +void dpi_sim_halt(void); + +#ifdef __cplusplus +} +#endif + +#endif // MONITOR_HALT_H_ diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index 447b33ef..bf2572e6 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -4,34 +4,52 @@ #include #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - // DPI-C function for instruction trace (itrace) - // Called from GlobalROB when instructions are issued or completed - void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete - unsigned int rob_id, unsigned int domain_id, unsigned int funct, - unsigned long long rs1, unsigned long long rs2); - - // DPI-C function for memory trace (mtrace) - // Called from MemBackend when read/write requests are made - void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read - unsigned char is_shared, // 1 = shared path, 0 = private path - unsigned int channel, unsigned long long hart_id, - unsigned int vbank_id, - unsigned int group_id, unsigned int addr, - unsigned long long data_lo, unsigned long long data_hi); - - // DPI-C function for Ball PMC trace (pmctrace) - // Called from BallCyclePMC when a Ball completes a task - void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, - unsigned long long elapsed); - - // DPI-C function for memory PMC trace (pmctrace) - // Called from MemCyclePMC when a load/store completes - void dpi_mem_pmctrace(unsigned char is_store, // 1 = store, 0 = load - unsigned int rob_id, unsigned long long elapsed); +// DPI-C function for instruction trace (itrace) +// Called from GlobalROB when instructions are issued or completed +void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete + unsigned int rob_id, unsigned int domain_id, unsigned int funct, + unsigned long long rs1, unsigned long long rs2); + +// DPI-C function for memory trace (mtrace) +// Called from MemBackend when read/write requests are made +void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read + unsigned char is_shared, + unsigned int channel, unsigned long long hart_id, + unsigned int vbank_id, + unsigned int group_id, unsigned int addr, + unsigned long long data_lo, unsigned long long data_hi); + +// DPI-C function for Ball PMC trace (pmctrace) +// Called from BallCyclePMC when a Ball completes a task +void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, + unsigned long long elapsed); + +// DPI-C function for memory PMC trace (pmctrace) +// Called from MemCyclePMC when a load/store completes +void dpi_mem_pmctrace(unsigned char is_store, // 1 = store, 0 = load + unsigned int rob_id, unsigned long long elapsed); + +// DPI-C function for cycle counter trace (ctrace) +// Called from TraceBall when counter commands are executed +void dpi_ctrace(unsigned char subcmd, // 0=START, 1=STOP, 2=READ + unsigned int ctr_id, unsigned long long tag, + unsigned long long elapsed, unsigned long long cycle); + +// DPI-C functions for bank backdoor (TraceBall) +// RTL calls these to get parameters from C++ testbench +unsigned long long dpi_backdoor_get_read_addr(void); +unsigned long long dpi_backdoor_get_write_addr(void); +void dpi_backdoor_get_write_data(unsigned long long *data_lo, + unsigned long long *data_hi); +void dpi_backdoor_put_read_data(unsigned int bank_id, unsigned int row, + unsigned long long data_lo, + unsigned long long data_hi); +void dpi_backdoor_put_write_done(unsigned int bank_id, unsigned int row, + unsigned long long data_lo, + unsigned long long data_hi); #ifdef __cplusplus } diff --git a/arch/src/csrc/src/main.cc b/arch/src/csrc/src/main.cc index 88213b21..830afd51 100644 --- a/arch/src/csrc/src/main.cc +++ b/arch/src/csrc/src/main.cc @@ -1,11 +1,8 @@ #include "bdb.h" +#include "ioe/mmio.h" #include "utils/debug.h" #include "utils/macro.h" -#ifdef COSIM -#include "monitor/cosim.h" -#endif - #include #include @@ -13,12 +10,7 @@ vluint64_t sim_time = 0; VerilatedContext *contextp = NULL; VerilatedFstC *tfp = NULL; -#ifdef COSIM -static VToyBuckyball *top; -static CosimServer *cosim_server = NULL; -#else -static VTestHarness *top; -#endif +VBBSimHarness *top; int bb_step = 1; @@ -47,11 +39,7 @@ void sim_init(int argc, char **argv) { contextp->commandArgs(argc, argv); tfp = new VerilatedFstC; -#ifdef COSIM - top = new VToyBuckyball{contextp}; -#else - top = new VTestHarness{contextp}; -#endif + top = new VBBSimHarness{contextp}; contextp->traceEverOn(true); top->trace(tfp, 0); @@ -74,15 +62,6 @@ void sim_init(int argc, char **argv) { signal(SIGTERM, coverage_signal_handler); signal(SIGINT, coverage_signal_handler); #endif - -#ifdef COSIM - // Initialize COSIM socket server - cosim_server = new CosimServer(top); - if (!cosim_server->init()) { - panic("Failed to initialize COSIM server"); - } - Log("COSIM mode: waiting for Bebop connection..."); -#endif } void sim_exit() { @@ -90,36 +69,21 @@ void sim_exit() { tfp->dump(contextp->time()); tfp->close(); printf("The wave data has been saved to the FST file: %s\n", fst_path); - -#ifdef COSIM - if (cosim_server) { - cosim_server->shutdown(); - delete cosim_server; - } -#endif - exit(0); } void ball_exec_once() { -#ifdef COSIM - // Update COSIM server (handle socket I/O and drive DUT signals) - if (cosim_server) { - cosim_server->update(); - } -#endif + // posedge: clock=1, eval (FF outputs settle), read fire pulse from RTL slave + top->clock = 1; + top->eval(); + mmio_tick(); // read io_mmio_fire; all AXI4 handshaking done in RTL + contextp->timeInc(1); + tfp->dump(contextp->time()); + sim_time++; - top->clock ^= 1; - step_and_dump_wave(); - top->clock ^= 1; + // negedge: clock=0, eval + top->clock = 0; step_and_dump_wave(); - -#ifndef COSIM - if (top->io_success == 1) { - printf("simulation success\n"); - sim_exit(); - } -#endif } //================ main =====================// diff --git a/arch/src/csrc/src/monitor/cosim/cosim.cc b/arch/src/csrc/src/monitor/cosim/cosim.cc deleted file mode 100644 index ac5b660b..00000000 --- a/arch/src/csrc/src/monitor/cosim/cosim.cc +++ /dev/null @@ -1,491 +0,0 @@ -#ifdef COSIM - -#include "monitor/cosim.h" -#include "VToyBuckyball.h" -#include "utils/debug.h" -#include -#include -#include -#include -#include -#include -#include -#include - -CosimServer::CosimServer(VToyBuckyball *dut) - : dut(dut), server_running(false), cmd_server_fd(-1), - dma_read_server_fd(-1), dma_write_server_fd(-1), cmd_client_fd(-1), - dma_read_client_fd(-1), dma_write_client_fd(-1), cmd_in_progress(false) {} - -CosimServer::~CosimServer() { shutdown(); } - -bool CosimServer::init() { - Log("Initializing COSIM socket server..."); - - // Create server sockets - cmd_server_fd = create_server_socket(SOCKET_CMD_PORT); - dma_read_server_fd = create_server_socket(SOCKET_DMA_READ_PORT); - dma_write_server_fd = create_server_socket(SOCKET_DMA_WRITE_PORT); - - if (cmd_server_fd < 0 || dma_read_server_fd < 0 || dma_write_server_fd < 0) { - panic("Failed to create server sockets"); - return false; - } - - Log("Socket servers listening on ports %d, %d, %d", SOCKET_CMD_PORT, - SOCKET_DMA_READ_PORT, SOCKET_DMA_WRITE_PORT); - - server_running = true; - - // Start background threads - cmd_thread = std::thread(&CosimServer::cmd_server_thread, this); - dma_read_thread = std::thread(&CosimServer::dma_read_server_thread, this); - dma_write_thread = std::thread(&CosimServer::dma_write_server_thread, this); - - Log("COSIM server initialized successfully"); - return true; -} - -void CosimServer::shutdown() { - if (!server_running) - return; - - Log("Shutting down COSIM server..."); - server_running = false; - - // Wake up all threads - cmd_cv.notify_all(); - - // Close client connections - if (cmd_client_fd >= 0) - close(cmd_client_fd); - if (dma_read_client_fd >= 0) - close(dma_read_client_fd); - if (dma_write_client_fd >= 0) - close(dma_write_client_fd); - - // Close server sockets - if (cmd_server_fd >= 0) - close(cmd_server_fd); - if (dma_read_server_fd >= 0) - close(dma_read_server_fd); - if (dma_write_server_fd >= 0) - close(dma_write_server_fd); - - // Join threads - if (cmd_thread.joinable()) - cmd_thread.join(); - if (dma_read_thread.joinable()) - dma_read_thread.join(); - if (dma_write_thread.joinable()) - dma_write_thread.join(); - - Log("COSIM server shutdown complete"); -} - -int CosimServer::create_server_socket(int port) { - int fd = socket(AF_INET, SOCK_STREAM, 0); - if (fd < 0) { - panic("socket() failed: %s", strerror(errno)); - return -1; - } - - // Set SO_REUSEADDR - int opt = 1; - if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt)) < 0) { - panic("setsockopt() failed: %s", strerror(errno)); - close(fd); - return -1; - } - - // Bind - struct sockaddr_in addr; - memset(&addr, 0, sizeof(addr)); - addr.sin_family = AF_INET; - addr.sin_addr.s_addr = INADDR_ANY; - addr.sin_port = htons(port); - - if (bind(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) { - panic("bind() failed on port %d: %s", port, strerror(errno)); - close(fd); - return -1; - } - - // Listen - if (listen(fd, 1) < 0) { - panic("listen() failed: %s", strerror(errno)); - close(fd); - return -1; - } - - return fd; -} - -int CosimServer::accept_client(int server_fd) { - struct sockaddr_in client_addr; - socklen_t client_len = sizeof(client_addr); - int client_fd = - accept(server_fd, (struct sockaddr *)&client_addr, &client_len); - if (client_fd < 0) { - panic("accept() failed: %s", strerror(errno)); - return -1; - } - Log("Accepted client connection from %s:%d", inet_ntoa(client_addr.sin_addr), - ntohs(client_addr.sin_port)); - - // Set TCP_NODELAY to disable Nagle's algorithm - int opt = 1; - if (setsockopt(client_fd, IPPROTO_TCP, TCP_NODELAY, &opt, sizeof(opt)) < 0) { - Log("Failed to set TCP_NODELAY: %s", strerror(errno)); - } - - return client_fd; -} - -bool CosimServer::recv_all(int fd, void *buf, size_t len) { - size_t received = 0; - while (received < len) { - ssize_t n = recv(fd, (char *)buf + received, len - received, 0); - if (n <= 0) { - if (n < 0) - panic("recv() failed: %s", strerror(errno)); - return false; - } - received += n; - } - return true; -} - -bool CosimServer::send_all(int fd, const void *buf, size_t len) { - size_t sent = 0; - while (sent < len) { - ssize_t n = send(fd, (const char *)buf + sent, len - sent, 0); - if (n <= 0) { - if (n < 0) - panic("send() failed: %s", strerror(errno)); - return false; - } - sent += n; - } - return true; -} - -// ============ CMD Server Thread ============ -void CosimServer::cmd_server_thread() { - Log("CMD server thread started"); - - // Accept client connection - cmd_client_fd = accept_client(cmd_server_fd); - if (cmd_client_fd < 0) - return; - - // Process CMD requests - while (server_running) { - cmd_req_t req; - if (!recv_all(cmd_client_fd, &req, sizeof(req))) { - Log("CMD client disconnected"); - break; - } - - if (req.header.msg_type != MSG_TYPE_CMD_REQ) { - panic("Invalid CMD message type: %u", req.header.msg_type); - continue; - } - - // Enqueue CMD request - { - std::lock_guard lock(cmd_mutex); - cmd_queue.push(req); - } - cmd_cv.notify_one(); - - // Wait for CMD completion (io_busy goes low) - // The response will be sent from the main update loop - } - - Log("CMD server thread exiting"); -} - -// ============ DMA Read Server Thread ============ -void CosimServer::dma_read_server_thread() { - Log("DMA Read server thread started"); - - // Accept client connection - dma_read_client_fd = accept_client(dma_read_server_fd); - if (dma_read_client_fd < 0) - return; - Log("DMA Read client accepted"); - - // Process DMA read responses from client - while (server_running) { - Log("DMA Read thread: waiting for response..."); - dma_read_resp_t resp; - // Use non-blocking recv to avoid deadlock - int flags = fcntl(dma_read_client_fd, F_GETFL, 0); - fcntl(dma_read_client_fd, F_SETFL, flags | O_NONBLOCK); - - ssize_t n = recv(dma_read_client_fd, &resp, sizeof(resp), 0); - - fcntl(dma_read_client_fd, F_SETFL, flags); - - if (n > 0) { - Log("DMA Read thread: received msg_type=%u, size=%ld", - resp.header.msg_type, n); - - if (resp.header.msg_type == MSG_TYPE_DMA_READ_RESP) { - // Enqueue TileLink response - tilelink_transaction_t tx; - tx.opcode = 1; // AccessAckData - tx.data_lo = resp.data_lo; - tx.data_hi = resp.data_hi; - - { - std::lock_guard lock(tl_resp_mutex); - tl_resp_queue.push(tx); - } - } else { - panic("Invalid DMA Read response type: %u", resp.header.msg_type); - } - } else if (n == 0) { - Log("DMA Read client disconnected"); - break; - } else if (errno != EAGAIN && errno != EWOULDBLOCK) { - Log("DMA Read recv error: %s", strerror(errno)); - break; - } - - // Sleep briefly to avoid busy-waiting - usleep(100); - } - - Log("DMA Read server thread exiting"); -} - -// ============ DMA Write Server Thread ============ -void CosimServer::dma_write_server_thread() { - Log("DMA Write server thread started"); - - // Accept client connection - dma_write_client_fd = accept_client(dma_write_server_fd); - if (dma_write_client_fd < 0) - return; - - // Process DMA write responses from client - while (server_running) { - dma_write_resp_t resp; - // Use non-blocking recv to avoid deadlock - int flags = fcntl(dma_write_client_fd, F_GETFL, 0); - fcntl(dma_write_client_fd, F_SETFL, flags | O_NONBLOCK); - - ssize_t n = recv(dma_write_client_fd, &resp, sizeof(resp), 0); - - fcntl(dma_write_client_fd, F_SETFL, flags); - - if (n > 0) { - Log("DMA Write thread: received msg_type=%u", resp.header.msg_type); - - if (resp.header.msg_type == MSG_TYPE_DMA_WRITE_RESP) { - // Enqueue TileLink response - tilelink_transaction_t tx; - tx.opcode = 0; // AccessAck - - { - std::lock_guard lock(tl_resp_mutex); - tl_resp_queue.push(tx); - } - } else { - panic("Invalid DMA Write response type: %u", resp.header.msg_type); - } - } else if (n == 0) { - Log("DMA Write client disconnected"); - break; - } else if (errno != EAGAIN && errno != EWOULDBLOCK) { - Log("DMA Write recv error: %s", strerror(errno)); - break; - } - - // Sleep briefly to avoid busy-waiting - usleep(100); - } - - Log("DMA Write server thread exiting"); -} - -// ============ Main Update (called each cycle) ============ -void CosimServer::update() { - // 1. Drive CMD interface (io_cmd_*) - drive_cmd_interface(); - - // 2. Sample TileLink requests (auto_widget_anon_out_a_*) - sample_tilelink_request(); - - // 3. Drive TileLink responses (auto_widget_anon_out_d_*) - drive_tilelink_response(); -} - -void CosimServer::drive_cmd_interface() { - // Check if there's a pending CMD request - if (!cmd_in_progress) { - std::lock_guard lock(cmd_mutex); - if (!cmd_queue.empty()) { - current_cmd = cmd_queue.front(); - cmd_queue.pop(); - cmd_in_progress = true; - - // Drive io_cmd signals - dut->io_cmd_valid = 1; - dut->io_cmd_bits_inst_funct = current_cmd.funct & 0x7F; - dut->io_cmd_bits_rs1 = current_cmd.xs1; - dut->io_cmd_bits_rs2 = current_cmd.xs2; - - Log("CMD Request: funct=%u, xs1=0x%lx, xs2=0x%lx", current_cmd.funct, - current_cmd.xs1, current_cmd.xs2); - } else { - // No pending CMD, clear io_cmd_valid - dut->io_cmd_valid = 0; - } - } else { - // CMD in progress, check if accelerator is ready - if (dut->io_cmd_ready == 1) { - // CMD accepted, clear valid - dut->io_cmd_valid = 0; - cmd_in_progress = false; - - // Send response immediately - cmd_resp_t resp; - resp.header.msg_type = MSG_TYPE_CMD_RESP; - resp.header.reserved = 0; - resp.result = 1; // Success - - if (cmd_client_fd >= 0) { - send_all(cmd_client_fd, &resp, sizeof(resp)); - } - - Log("CMD Response: result=0x%lx", resp.result); - } - } -} - -void CosimServer::sample_tilelink_request() { - // Check if TileLink Channel A has a valid request - static int no_request_count = 0; - - if (dut->auto_widget_anon_out_a_valid == 1) { - tilelink_transaction_t tx; - tx.opcode = dut->auto_widget_anon_out_a_bits_opcode; - tx.source = dut->auto_widget_anon_out_a_bits_source; - tx.address = dut->auto_widget_anon_out_a_bits_address; - tx.size = dut->auto_widget_anon_out_a_bits_size; - tx.mask = dut->auto_widget_anon_out_a_bits_mask; - - // Read data from 128-bit VlWide array (4 x 32-bit words) - // VlWide<4> means 4 words of 32 bits each = 128 bits total - uint32_t *data_words = dut->auto_widget_anon_out_a_bits_data; - tx.data_lo = ((uint64_t)data_words[1] << 32) | (uint64_t)data_words[0]; - tx.data_hi = ((uint64_t)data_words[3] << 32) | (uint64_t)data_words[2]; - - Log("TileLink Request: opcode=%u, addr=0x%x, size=%u, source=%u, ready=%d", - tx.opcode, tx.address, tx.size, tx.source, - dut->auto_widget_anon_out_a_ready); - - no_request_count = 0; - - // Process based on opcode - if (tx.opcode == 4) { - // Get (Read) - process_dma_read_request(tx); - } else if (tx.opcode == 0 || tx.opcode == 1) { - // PutFullData or PutPartialData (Write) - process_dma_write_request(tx); - } - - // Set ready after handling - dut->auto_widget_anon_out_a_ready = 1; - } else { - // No request - if (++no_request_count % 100 == 0) { - Log("No TileLink requests yet (valid=%d, ready=%d)", - dut->auto_widget_anon_out_a_valid, dut->auto_widget_anon_out_a_ready); - } - dut->auto_widget_anon_out_a_ready = 1; - } -} - -void CosimServer::drive_tilelink_response() { - // Check if there's a pending TileLink response - std::lock_guard lock(tl_resp_mutex); - if (!tl_resp_queue.empty() && dut->auto_widget_anon_out_d_ready == 1) { - tilelink_transaction_t tx = tl_resp_queue.front(); - tl_resp_queue.pop(); - - // Drive Channel D signals - dut->auto_widget_anon_out_d_valid = 1; - dut->auto_widget_anon_out_d_bits_opcode = tx.opcode; - dut->auto_widget_anon_out_d_bits_source = tx.source; - - if (tx.opcode == 1) { - // AccessAckData (read response) - // Write data to 128-bit VlWide array (4 x 32-bit words) - uint32_t *data_words = dut->auto_widget_anon_out_d_bits_data; - data_words[0] = (uint32_t)(tx.data_lo & 0xFFFFFFFF); - data_words[1] = (uint32_t)(tx.data_lo >> 32); - data_words[2] = (uint32_t)(tx.data_hi & 0xFFFFFFFF); - data_words[3] = (uint32_t)(tx.data_hi >> 32); - Log("TileLink Response: opcode=%u (AckData), data=0x%lx%lx", tx.opcode, - tx.data_hi, tx.data_lo); - } else { - // AccessAck (write response) - Log("TileLink Response: opcode=%u (Ack)", tx.opcode); - } - } else { - // No pending response - dut->auto_widget_anon_out_d_valid = 0; - } -} - -void CosimServer::process_dma_read_request(const tilelink_transaction_t &tx) { - // Send DMA read request to client - dma_read_req_t req; - req.header.msg_type = MSG_TYPE_DMA_READ_REQ; - req.header.reserved = 0; - req.addr = tx.address; - req.size = 1 << tx.size; // Convert 2^size to bytes - req.padding = 0; - - Log("process_dma_read_request: about to send request, fd=%d", - dma_read_client_fd); - if (dma_read_client_fd >= 0) { - Log("process_dma_read_request: sending request..."); - // Disable Nagle's algorithm to ensure immediate transmission - int opt = 1; - setsockopt(dma_read_client_fd, IPPROTO_TCP, TCP_NODELAY, &opt, sizeof(opt)); - send_all(dma_read_client_fd, &req, sizeof(req)); - Log("process_dma_read_request: request sent: addr=0x%lx, size=%u", req.addr, - req.size); - } else { - Log("process_dma_read_request: dma_read_client_fd is invalid!"); - } - - // Response will be handled in dma_read_server_thread -} - -void CosimServer::process_dma_write_request(const tilelink_transaction_t &tx) { - // Send DMA write request to client - dma_write_req_t req; - req.header.msg_type = MSG_TYPE_DMA_WRITE_REQ; - req.header.reserved = 0; - req.addr = tx.address; - req.size = 1 << tx.size; // Convert 2^size to bytes - req.padding = 0; - req.data_lo = tx.data_lo; - req.data_hi = tx.data_hi; - - if (dma_write_client_fd >= 0) { - send_all(dma_write_client_fd, &req, sizeof(req)); - Log("DMA Write Request: addr=0x%lx, size=%u, data=0x%lx%lx", req.addr, - req.size, req.data_hi, req.data_lo); - } - - // Response will be handled in dma_write_server_thread -} -#endif diff --git a/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc b/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc new file mode 100644 index 00000000..6e5e8a68 --- /dev/null +++ b/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc @@ -0,0 +1,279 @@ +// SimDRAM_bb.cc — Override memory_init from testchipip's SimDRAM.cc +// Replaces fesvr load_elf with libelf-based ELF loader. +// This file is compiled into the simulation and takes precedence over +// the version embedded in the SimDRAM Verilog blackbox resource. +// +// Globals shared with testchipip/csrc/mm_dramsim2.cc (included via linkage): +// extern bool use_dramsim; +// extern std::string loadmem_file; +// extern std::vector> backing_mem_data; + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// elf.h is available in glibc, no extra library needed for parsing +#include +#include +#include +#include + +#include "mm_dramsim2.h" + +// Global state — defined here since testchipip's SimDRAM.cc is excluded from build. +// memory_tick (not overridden) accesses these via external linkage from mm_dramsim2.cc. +bool use_dramsim = false; +std::string ini_dir = "dramsim2_ini"; +std::vector> backing_mem_data = {}; + +// ELF file path, set via +elf= plusarg +static std::string elf_file = ""; + +// --------------------------------------------------------------------------- +// load_elf_to_mem: parse ELF64 and copy PT_LOAD segments into backing data +// --------------------------------------------------------------------------- +static void load_elf_to_mem(const char *path, uint8_t *data, + uint64_t mem_base, uint64_t mem_size) { + int fd = open(path, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "[SimDRAM_bb] Cannot open ELF: %s\n", path); + abort(); + } + + struct stat st; + fstat(fd, &st); + size_t file_size = st.st_size; + + uint8_t *file_buf = (uint8_t *)mmap(NULL, file_size, PROT_READ, MAP_PRIVATE, fd, 0); + close(fd); + if (file_buf == MAP_FAILED) { + fprintf(stderr, "[SimDRAM_bb] mmap failed for ELF: %s\n", path); + abort(); + } + + Elf64_Ehdr *ehdr = (Elf64_Ehdr *)file_buf; + if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG) != 0) { + fprintf(stderr, "[SimDRAM_bb] Not a valid ELF file: %s\n", path); + abort(); + } + if (ehdr->e_ident[EI_CLASS] != ELFCLASS64) { + fprintf(stderr, "[SimDRAM_bb] Only ELF64 supported\n"); + abort(); + } + + Elf64_Phdr *phdrs = (Elf64_Phdr *)(file_buf + ehdr->e_phoff); + size_t loaded = 0; + for (int i = 0; i < ehdr->e_phnum; i++) { + Elf64_Phdr *ph = &phdrs[i]; + if (ph->p_type != PT_LOAD) continue; + if (ph->p_filesz == 0) continue; + + uint64_t vaddr = ph->p_paddr; // use physical address + if (vaddr < mem_base || vaddr + ph->p_memsz > mem_base + mem_size) { + fprintf(stderr, + "[SimDRAM_bb] Segment paddr=0x%lx size=0x%lx outside mem [0x%lx, 0x%lx)\n", + vaddr, ph->p_memsz, mem_base, mem_base + mem_size); + abort(); + } + uint64_t offset = vaddr - mem_base; + // Copy file content + memcpy(data + offset, file_buf + ph->p_offset, ph->p_filesz); + // Zero BSS (memsz > filesz) + if (ph->p_memsz > ph->p_filesz) { + memset(data + offset + ph->p_filesz, 0, ph->p_memsz - ph->p_filesz); + } + loaded += ph->p_filesz; + } + + munmap(file_buf, file_size); + printf("[SimDRAM_bb] Loaded ELF '%s': %zu bytes\n", path, loaded); +} + +// --------------------------------------------------------------------------- +// memory_init override — called from SimDRAM.v via DPI-C +// --------------------------------------------------------------------------- +extern "C" void *memory_init( + int chip_id, + long long int mem_size, + long long int word_size, + long long int line_size, + long long int id_bits, + long long int clock_hz, + long long int mem_base) +{ + mm_t *mm; + s_vpi_vlog_info info; + + std::string memory_ini = "DDR3_micron_64M_8B_x4_sg15.ini"; + std::string system_ini = "system.ini"; + std::string local_ini_dir = "dramsim2_ini"; + + if (!vpi_get_vlog_info(&info)) + abort(); + + // Parse plusargs: +elf=, +dramsim, +dramsim_ini_dir=

    + for (int i = 1; i < info.argc; i++) { + std::string arg(info.argv[i]); + if (arg.find("+elf=") == 0) + elf_file = arg.substr(strlen("+elf=")); + if (arg == "+dramsim") + use_dramsim = true; + if (arg.find("+dramsim_ini_dir=") == 0) + local_ini_dir = arg.substr(strlen("+dramsim_ini_dir=")); + } + + while (chip_id >= (int)backing_mem_data.size()) { + backing_mem_data.push_back(std::map()); + } + + if (backing_mem_data[chip_id].find(mem_base) != backing_mem_data[chip_id].end()) { + assert(backing_mem_data[chip_id][mem_base].size == (size_t)mem_size); + } else { + uint8_t *data = (uint8_t *)mmap(NULL, mem_size, + PROT_READ | PROT_WRITE, + MAP_SHARED | MAP_ANONYMOUS, -1, 0); + if (data == MAP_FAILED) { + fprintf(stderr, "[SimDRAM_bb] mmap for backing store failed\n"); + abort(); + } + memset(data, 0, mem_size); + + // Load ELF if +elf= was provided + if (!elf_file.empty()) { + load_elf_to_mem(elf_file.c_str(), data, (uint64_t)mem_base, (uint64_t)mem_size); + } + + backing_mem_data[chip_id][mem_base] = {data, (size_t)mem_size}; + } + + if (use_dramsim) { + mm = (mm_t *)(new mm_dramsim2_t( + mem_base, mem_size, word_size, line_size, + backing_mem_data[chip_id][mem_base], + memory_ini, system_ini, local_ini_dir, + 1 << id_bits, clock_hz)); + } else { + mm = (mm_t *)(new mm_magic_t( + mem_base, mem_size, word_size, line_size, + backing_mem_data[chip_id][mem_base])); + } + + return mm; +} + +// --------------------------------------------------------------------------- +// MMIO device state for UART interception +// SiFive UART TX register: base 0x10020000, offset 0 = txdata +// AXI write is split: aw channel (address) and w channel (data) may arrive +// in different cycles. We track pending aw/w separately. +// --------------------------------------------------------------------------- + +#define UART_TX_ADDR 0x10020000LL + +struct mmio_state_t { + bool aw_pending = false; + long long aw_addr = 0; + int aw_id = 0; + bool b_fire = false; // b response ready to send + int b_id_val = 0; +} mmio_state; + +static void mmio_uart_tick( + unsigned char reset, + unsigned char aw_valid, unsigned char *aw_ready, + long long int aw_addr_in, int aw_id_in, + unsigned char w_valid, unsigned char *w_ready, + long long w_data, + unsigned char *b_valid, unsigned char b_ready, int *b_id, int *b_resp) +{ + if (reset) { + mmio_state = mmio_state_t{}; + *aw_ready = 1; *w_ready = 1; *b_valid = 0; + return; + } + + // Accept aw + *aw_ready = !mmio_state.aw_pending; + if (aw_valid && *aw_ready) { + mmio_state.aw_pending = true; + mmio_state.aw_addr = aw_addr_in; + mmio_state.aw_id = aw_id_in; + } + + // Accept w when aw is pending + *w_ready = mmio_state.aw_pending && !mmio_state.b_fire; + if (w_valid && *w_ready) { + if (mmio_state.aw_addr == UART_TX_ADDR) { + char ch = (char)(w_data & 0xFF); + putchar(ch); + fflush(stdout); + } + mmio_state.aw_pending = false; + mmio_state.b_fire = true; + mmio_state.b_id_val = mmio_state.aw_id; + } + + // Send b response + *b_valid = mmio_state.b_fire; + *b_id = mmio_state.b_id_val; + *b_resp = 0; + if (mmio_state.b_fire && b_ready) + mmio_state.b_fire = false; +} + +// --------------------------------------------------------------------------- +// memory_tick — DPI-C from SimDRAM.v / SimAXIMem.v +// MMIO region (base != DRAM base) is dispatched to mmio_uart_tick. +// --------------------------------------------------------------------------- +extern "C" void memory_tick( + void *channel, + unsigned char reset, + unsigned char ar_valid, unsigned char *ar_ready, + long long int ar_addr, int ar_id, int ar_size, int ar_len, + unsigned char aw_valid, unsigned char *aw_ready, + long long int aw_addr, int aw_id, int aw_size, int aw_len, + unsigned char w_valid, unsigned char *w_ready, + int w_strb, long long w_data, unsigned char w_last, + unsigned char *r_valid, unsigned char r_ready, + int *r_id, int *r_resp, long long *r_data, unsigned char *r_last, + unsigned char *b_valid, unsigned char b_ready, + int *b_id, int *b_resp) +{ + mm_t *mm = (mm_t *)channel; + + // Route MMIO channel (mem_base < 0x80000000) to our MMIO handler. + // DRAM is always at 0x80000000+; MMIO (SiFive peripherals) is below. + if (mm->get_base() < 0x80000000ULL) { + *ar_ready = 0; *r_valid = 0; *r_last = 0; *r_id = 0; *r_resp = 0; *r_data = 0; + mmio_uart_tick(reset, + aw_valid, aw_ready, aw_addr, aw_id, + w_valid, w_ready, w_data, + b_valid, b_ready, b_id, b_resp); + return; + } + + mm->tick(reset, + ar_valid, ar_addr, ar_id, ar_size, ar_len, + aw_valid, aw_addr, aw_id, aw_size, aw_len, + w_valid, w_strb, &w_data, w_last, + r_ready, b_ready); + *ar_ready = mm->ar_ready(); + *aw_ready = mm->aw_ready(); + *w_ready = mm->w_ready(); + *r_valid = mm->r_valid(); + *r_id = mm->r_id(); + *r_resp = mm->r_resp(); + *r_data = *((long *)mm->r_data()); + *r_last = mm->r_last(); + *b_valid = mm->b_valid(); + *b_id = mm->b_id(); + *b_resp = mm->b_resp(); +} diff --git a/arch/src/csrc/src/monitor/ioe/mem.cc b/arch/src/csrc/src/monitor/ioe/mem.cc deleted file mode 100644 index e3bbce1e..00000000 --- a/arch/src/csrc/src/monitor/ioe/mem.cc +++ /dev/null @@ -1,41 +0,0 @@ -// #include "utils/mem.h" -#include "utils/debug.h" -#include -#include -#include -#include -#include -#include - -#define MEM_SIZE 100000 - -static uint8_t mem[MEM_SIZE] = {0}; - -// Load image from am-kernels (Makefile -> ./image.bin) -static long load_image(char const *img_file) { - if (img_file == NULL) { - printf("No image is given. Use the default build-in image."); - return 4096; // built-in image size - } - FILE *fp = fopen(img_file, "rb"); - Assert(fp, "Can not open '%s'", img_file); - - // fseek: set file position pointer related to fp to a specified position - // fseek(fp, 0, SEEK_END) positions file pointer to end of file, offset 0 - // bytes - fseek(fp, 0, SEEK_END); - // ftell: returns file size - static long img_size = ftell(fp); - - printf("The image is %s, size = %ld\n", img_file, img_size); - - // fseek(fp, 0, SEEK_SET) positions file pointer to beginning of file, offset - // 0 bytes - fseek(fp, 0, SEEK_SET); - // Read img_size from fp to mem - int ret = fread(mem, img_size, 1, fp); - assert(ret == 1); - - fclose(fp); - return img_size; -} diff --git a/arch/src/csrc/src/monitor/ioe/mmio.cc b/arch/src/csrc/src/monitor/ioe/mmio.cc new file mode 100644 index 00000000..fd871abc --- /dev/null +++ b/arch/src/csrc/src/monitor/ioe/mmio.cc @@ -0,0 +1,48 @@ +#include "ioe/mmio.h" +#include "bdb.h" + +#include +#include +#include + +#define SIM_EXIT_ADDR 0x60000000ULL +#define UART_TX_ADDR 0x60020000ULL + +static FILE *uart_fp = nullptr; + +static void uart_putchar(char ch) { + if (!uart_fp) { + const char *path = stdout_path ? stdout_path : "stdout.log"; + uart_fp = fopen(path, "w"); + } + if (uart_fp) { + fputc(ch, uart_fp); + fflush(uart_fp); + } + if (raw_stdout_fd >= 0) { + write(raw_stdout_fd, &ch, 1); + } +} + +// Called once per posedge after eval(). +// io_mmio_fire is a 1-cycle pulse (harness clock domain = C++ sampling clock). +void mmio_tick() { + if (!top->io_mmio_fire) return; + + uint64_t addr = top->io_mmio_fire_addr; + uint64_t data = top->io_mmio_fire_data; + + if (addr == SIM_EXIT_ADDR) { + int code = (int)(data & 0xFFFFFFFF); + if (code == 0) fprintf(stderr, "[MMIO] simulation success\n"); + else fprintf(stderr, "[MMIO] simulation exit code %d\n", code); + if (uart_fp) fclose(uart_fp); + sim_exit(); + } else if (addr == UART_TX_ADDR) { + uart_putchar((char)(data & 0xFF)); + } +} + +void mmio_tick_post() { + // No-op: handshake is now managed entirely in RTL. +} diff --git a/arch/src/csrc/src/monitor/monitor.cc b/arch/src/csrc/src/monitor/monitor.cc index 57edb3b2..185cce3c 100644 --- a/arch/src/csrc/src/monitor/monitor.cc +++ b/arch/src/csrc/src/monitor/monitor.cc @@ -1,95 +1,72 @@ #include "bdb.h" #include "utils/debug.h" #include "utils/macro.h" -#include #include #include - +#include #include #include -#include "ioe/mem.cc" #include "utils/welcome.cc" -// Define global VCD path variable -const char *vcd_path = nullptr; +// Define global path variables +const char *log_path = nullptr; +const char *fst_path = nullptr; +const char *stdout_path = nullptr; -// Define global log path variable -const char *log_path = nullptr; -const char *fst_path = nullptr; +// Raw stdout fd saved before dup2 redirect — used by UART putchar for real-time display. +int raw_stdout_fd = -1; static int parse_args(int argc, char *argv[]) { - // const struct option table[] = { - // {"batch" , no_argument , NULL, 'b'}, - // {"vcd" , required_argument, NULL, 'v'}, - // {"log" , required_argument, NULL, 'l'}, - // {"help" , no_argument , NULL, 'h'}, - // }; - // int o; - // while ( (o = getopt_long(argc, argv, "bv:l:", table, NULL)) != -1) { - // switch (o) { - // case 'b': bdb_set_batch_mode(); break; - // case 'v': vcd_path = optarg; break; - // case 'l': log_path = optarg; break; - // default: - // printf("\t-b,--batch run with batch mode\n"); - // printf("\t-v,--vcd specify VCD file path\n"); - // printf("\t-l,--log specify log file path\n"); - - // Manually parse Verilator-style parameters (+vcd=path, +log=path) for (int i = 1; i < argc; i++) { - if (strncmp(argv[i], "+vcd=", 5) == 0) { - // Skip "+vcd=" - vcd_path = argv[i] + 5; - } else if (strncmp(argv[i], "+fst=", 5) == 0) { - // Skip "+fst=" + if (strncmp(argv[i], "+fst=", 5) == 0) { fst_path = argv[i] + 5; } else if (strncmp(argv[i], "+log=", 5) == 0) { - // Skip "+log=" log_path = argv[i] + 5; + } else if (strncmp(argv[i], "+stdout=", 8) == 0) { + stdout_path = argv[i] + 8; } else if (strcmp(argv[i], "+batch") == 0) { bdb_set_batch_mode(); } else if (strcmp(argv[i], "+help") == 0) { printf("\t+batch run with batch mode\n"); - printf("\t+vcd= specify VCD file path\n"); + printf("\t+elf= specify ELF binary to load into DRAM\n"); printf("\t+log= specify log file path\n"); - printf("\t+fst= specify FST file path\n"); + printf("\t+stdout= specify UART output file path\n"); + printf("\t+fst= specify FST waveform file path\n"); printf("\n"); exit(0); } + // +elf= is parsed by SimDRAM_bb.cc via vpi_get_vlog_info (Verilator plusargs) } - // Assert(vcd_path, "VCD file path is required. Use +vcd= to specify."); Assert(log_path, "Log file path is required. Use +log= to specify."); Assert(fst_path, "FST file path is required. Use +fst= to specify."); return 0; } static void init_log(const char *log_file) { - FILE *log_fp = NULL; - log_fp = stdout; if (log_file != NULL) { + // Save original stdout fd for UART real-time display + raw_stdout_fd = dup(STDOUT_FILENO); FILE *fp = fopen(log_file, "w"); Assert(fp, "Can not open '%s'", log_file); - log_fp = fp; + // Redirect stdout to bdb.log for Log() / DPI-C printf output + fflush(stdout); + dup2(fileno(fp), STDOUT_FILENO); + fclose(fp); } Log("Log is written to %s", log_file ? log_file : "stdout"); } static void init_io() { - // Force flush all output buffers fflush(stdout); fflush(stderr); - // Restore terminal echo functionality struct termios tty; if (tcgetattr(STDIN_FILENO, &tty) == 0) { - // Enable echo tty.c_lflag |= ECHO; - // Enable line buffered mode tty.c_lflag |= ICANON; tcsetattr(STDIN_FILENO, TCSANOW, &tty); - Log("Terminal echo restored"); } } @@ -97,7 +74,5 @@ void init_monitor(int argc, char *argv[]) { parse_args(argc, argv); init_log(log_path); init_io(); - // long img_size = - // load_image("/home/mio/Code/buckyball/arch/hello-baremetal"); welcome(); } diff --git a/arch/src/csrc/src/monitor/trace/ctrace.cc b/arch/src/csrc/src/monitor/trace/ctrace.cc new file mode 100644 index 00000000..aa9d30db --- /dev/null +++ b/arch/src/csrc/src/monitor/trace/ctrace.cc @@ -0,0 +1,135 @@ +#include "monitor/trace.h" +#include "utils/debug.h" +#include +#include +#include + +// Global log file pointer (shared with monitor.cc) +extern const char *log_path; +static FILE *ctrace_fp = NULL; + +// Backdoor write state +static uint32_t bd_write_row_cursor = 0; +static uint64_t bd_write_data_lo = 0; +static uint64_t bd_write_data_hi = 0; + +// Backdoor read state +static uint32_t bd_read_row_cursor = 0; + +// Backdoor test data generator +// Generates a simple incremental pattern for each row. +// 128-bit = 16 bytes, each byte = (row * 16 + byte_offset) & 0xFF +static void generate_test_data(uint32_t row, uint64_t *data_lo, + uint64_t *data_hi) { + uint8_t data[16]; + for (int i = 0; i < 16; i++) { + data[i] = (uint8_t)((row * 16 + i) & 0xFF); + } + *data_lo = 0; + *data_hi = 0; + for (int i = 0; i < 8; i++) { + *data_lo |= ((uint64_t)data[i]) << (i * 8); + *data_hi |= ((uint64_t)data[i + 8]) << (i * 8); + } +} + +static void init_ctrace() { + if (ctrace_fp == NULL && log_path != NULL) { + ctrace_fp = fopen(log_path, "a"); + if (ctrace_fp == NULL) { + panic("Failed to open ctrace log file: %s", log_path); + } + } +} + +// ================================================================ +// Cycle counter DPI-C +// ================================================================ + +extern "C" void dpi_ctrace(unsigned char subcmd, unsigned int ctr_id, + unsigned long long tag, unsigned long long elapsed, + unsigned long long cycle) { + init_ctrace(); + + if (ctrace_fp) { + switch (subcmd) { + case 0: // CTR_START + fprintf(ctrace_fp, "[CTRACE] CTR_START ctr=%u tag=0x%llX cycle=%llu\n", + ctr_id, tag, cycle); + break; + case 1: // CTR_STOP + fprintf(ctrace_fp, + "[CTRACE] CTR_STOP ctr=%u tag=0x%llX elapsed=%llu cycle=%llu\n", + ctr_id, tag, elapsed, cycle); + break; + case 2: // CTR_READ + fprintf(ctrace_fp, + "[CTRACE] CTR_READ ctr=%u current=%llu cycle=%llu\n", ctr_id, + elapsed, cycle); + break; + } + fflush(ctrace_fp); + } +} + +// ================================================================ +// Backdoor DPI-C functions +// RTL calls these each iteration. C++ auto-increments row. +// bank_id comes from RTL (instruction encoding), not from C++. +// ================================================================ + +// RTL calls this to get the next row to read. +// Returns row in [31:0], upper bits = 0. +extern "C" unsigned long long dpi_backdoor_get_read_addr(void) { + uint32_t row = bd_read_row_cursor; + bd_read_row_cursor++; + return (uint64_t)row; +} + +// RTL calls this to get the next row to write. +// Also pre-generates test data for this row. +// Returns row in [31:0], upper bits = 0. +extern "C" unsigned long long dpi_backdoor_get_write_addr(void) { + uint32_t row = bd_write_row_cursor; + generate_test_data(row, &bd_write_data_lo, &bd_write_data_hi); + bd_write_row_cursor++; + return (uint64_t)row; +} + +// RTL calls this to get write data (128-bit as lo/hi). +// Data was pre-generated by the preceding get_write_addr call. +extern "C" void dpi_backdoor_get_write_data(unsigned long long *data_lo, + unsigned long long *data_hi) { + *data_lo = bd_write_data_lo; + *data_hi = bd_write_data_hi; +} + +// RTL calls this after reading SRAM — logs the data to bdb.log +extern "C" void dpi_backdoor_put_read_data(unsigned int bank_id, + unsigned int row, + unsigned long long data_lo, + unsigned long long data_hi) { + init_ctrace(); + if (ctrace_fp) { + fprintf(ctrace_fp, + "[BANK-TRACE] BACKDOOR_READ bank=%u row=%u " + "data=0x%016llX%016llX\n", + bank_id, row, data_hi, data_lo); + fflush(ctrace_fp); + } +} + +// RTL calls this after writing SRAM — logs the write to bdb.log +extern "C" void dpi_backdoor_put_write_done(unsigned int bank_id, + unsigned int row, + unsigned long long data_lo, + unsigned long long data_hi) { + init_ctrace(); + if (ctrace_fp) { + fprintf(ctrace_fp, + "[BANK-TRACE] BACKDOOR_WRITE bank=%u row=%u " + "data=0x%016llX%016llX\n", + bank_id, row, data_hi, data_lo); + fflush(ctrace_fp); + } +} diff --git a/arch/src/csrc/src/monitor/trace/halt.cc b/arch/src/csrc/src/monitor/trace/halt.cc new file mode 100644 index 00000000..49799d7f --- /dev/null +++ b/arch/src/csrc/src/monitor/trace/halt.cc @@ -0,0 +1,9 @@ +#include "monitor/halt.h" +#include "bdb.h" +#include + +// Called from HaltDPI.sv via DPI-C when ebreak exception is detected +void dpi_sim_halt(void) { + printf("simulation success\n"); + sim_exit(); +} diff --git a/arch/src/main/scala/examples/goban/CustomConfigs.scala b/arch/src/main/scala/examples/goban/CustomConfigs.scala new file mode 100644 index 00000000..81b635ca --- /dev/null +++ b/arch/src/main/scala/examples/goban/CustomConfigs.scala @@ -0,0 +1,40 @@ +package examples.goban + +import org.chipsalliance.cde.config.Config +import framework.core.bbtile.WithNBBTiles +import framework.top.GlobalConfig +import framework.top.configs.TopConfig + +import freechips.rocketchip.subsystem.InSubsystem + +/** + * Goban: multi-core BBTile configuration. + * + * Each BBTile contains nCores Rocket cores, each paired with a BuckyballAccelerator. + * All accelerators within the tile share a single SharedMemBackend and BarrierUnit. + * The ISA, Ball operators, and memory layout are identical to the toy configuration. + */ +object GobanConfig { + /** Number of cores inside each BBTile. */ + val nCores: Int = 4 + + /** GlobalConfig for goban: same as toy but with nCores set. */ + def apply(): GlobalConfig = { + val base = GlobalConfig() + base.copy(top = base.top.copy(nCores = nCores)) + } +} + +/** 1 BBTile × 4 cores (4 Rocket + 4 Buckyball, shared SharedMem + BarrierUnit) */ +class BuckyballGobanConfig extends Config( + new WithNBBTiles(1, buckyballConfig = GobanConfig()) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig +) + +/** 2 BBTiles × 4 cores = 8 total cores */ +class BuckyballGoban2TileConfig extends Config( + new WithNBBTiles(2, buckyballConfig = GobanConfig()) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig +) diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index ac388a20..6fad1be9 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -13,20 +13,18 @@ import constellation.noc._ import scala.collection.immutable.ListMap /** Single BBTile: 1 Rocket core + 1 Buckyball accelerator */ -class BuckyballToyConfig - extends Config( - new WithNBBTiles(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) +class BuckyballToyConfig extends Config( + new WithNBBTiles(1) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig +) /** Single Rocket core only (no Buckyball) */ -class RocketOnlyConfig - extends Config( - new WithNBBTiles(1, withBuckyball = false) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) +class RocketOnlyConfig extends Config( + new WithNBBTiles(1, withBuckyball = false) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig +) // Increase BootROM size for large core counts class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) @@ -34,115 +32,3 @@ class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) case BootROMLocated(InSubsystem) => up(BootROMLocated(InSubsystem)).map(_.copy(address = address, size = size)) }) - -class BuckyballToy4Config - extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( - constellation.protocol.DiplomaticNetworkNodeMapping( - inNodeMapping = ListMap( - "serial_tl" -> 0, - "Core 0 " -> 1, - "Core 1 " -> 2, - "Core 2 " -> 3, - "Core 3 " -> 4, - "debug" -> 5, - "buckyball-stream-reader[0],buckyball-stream-writer[0]" -> 6, - "buckyball-stream-reader[1],buckyball-stream-writer[1]" -> 7, - "buckyball-stream-reader[2],buckyball-stream-writer[2]" -> 8, - "buckyball-stream-reader[3],buckyball-stream-writer[3]" -> 9 - ), - outNodeMapping = ListMap( - "pbus" -> 10, - "system[0]" -> 11, - "system[1]" -> 12, - "system[2]" -> 13, - "system[3]" -> 14 - ) - ), - NoCParams( - topology = TerminalRouter(Mesh2D(4, 4)), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), - routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) - ) - )) ++ - new WithNBBTiles(4) ++ - new freechips.rocketchip.subsystem.WithNBanks(4) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) - -class BuckyballToy64Config - extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( - constellation.protocol.DiplomaticNetworkNodeMapping( - inNodeMapping = ListMap( - "serial_tl" -> 0, - "debug" -> 1 - ) ++ (0 until 64).map(i => s"Core $i " -> (2 + i)).toMap - ++ (0 until 64).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (66 + i)).toMap, - outNodeMapping = ListMap( - "pbus" -> 130 - ) ++ (0 until 2).map(i => s"system[$i]" -> (131 + i)).toMap - ), - NoCParams( - topology = TerminalRouter(Mesh2D(12, 12)), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), - routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) - ) - )) ++ - new WithNBBTiles(64) ++ - new freechips.rocketchip.subsystem.WithNBanks(2) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) - -class BuckyballToy256Config - extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( - constellation.protocol.DiplomaticNetworkNodeMapping( - inNodeMapping = ListMap( - "serial_tl" -> 0, - "debug" -> 1 - ) ++ (0 until 256).map(i => s"Core $i " -> (2 + i)).toMap - ++ (0 until 256).map(i => s"buckyball-stream-reader[$i],buckyball-stream-writer[$i]" -> (258 + i)).toMap, - outNodeMapping = ListMap( - "pbus" -> 514 - ) ++ (0 until 32).map(i => s"system[$i]" -> (515 + i)).toMap - ), - NoCParams( - topology = TerminalRouter(Mesh2D(24, 24)), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(8)(UserVirtualChannelParams(4))), - routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1) - ) - )) ++ - new WithNBBTiles(256) ++ - new freechips.rocketchip.subsystem.WithNBanks(32) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) - -class BuckyballToy256CBConfig - extends Config( - new WithLargeBootROM(0x80000, 0x80000) ++ - new WithNBBTiles(32, location = InCluster(7)) ++ - new WithNBBTiles(32, location = InCluster(6)) ++ - new WithNBBTiles(32, location = InCluster(5)) ++ - new WithNBBTiles(32, location = InCluster(4)) ++ - new WithNBBTiles(32, location = InCluster(3)) ++ - new WithNBBTiles(32, location = InCluster(2)) ++ - new WithNBBTiles(32, location = InCluster(1)) ++ - new WithNBBTiles(32, location = InCluster(0)) ++ - new freechips.rocketchip.subsystem.WithCluster(7) ++ - new freechips.rocketchip.subsystem.WithCluster(6) ++ - new freechips.rocketchip.subsystem.WithCluster(5) ++ - new freechips.rocketchip.subsystem.WithCluster(4) ++ - new freechips.rocketchip.subsystem.WithCluster(3) ++ - new freechips.rocketchip.subsystem.WithCluster(2) ++ - new freechips.rocketchip.subsystem.WithCluster(1) ++ - new freechips.rocketchip.subsystem.WithCluster(0) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig - ) diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 6ebc8144..7db99acc 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -18,4 +18,8 @@ object DISA { val GEMMINI_COMPUTE_PRELOADED = BitPat("b0101100") // 44 val GEMMINI_COMPUTE_ACCUMULATED = BitPat("b0101101") // 45 val GEMMINI_FLUSH = BitPat("b0101110") // 46 + + // TraceBall instructions + val BDB_COUNTER = BitPat("b0110000") // 48 + val BDB_BACKDOOR = BitPat("b0110001") // 49 } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 8a89d2ad..6f4de21e 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -125,7 +125,10 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { 7.U, Cat(rs2(63, 4), 3.U(4.W)) ), - GEMMINI_FLUSH -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 7.U, Cat(0.U(60.W), 4.U(4.W))) + GEMMINI_FLUSH -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 7.U, Cat(0.U(60.W), 4.U(4.W))), + // TraceBall instructions + BDB_COUNTER -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 8.U, rs2), + BDB_BACKDOOR -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 8.U, rs2) ) ) diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala index 20a7fa8e..2c247e2e 100644 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala @@ -14,6 +14,7 @@ import framework.balldomain.prototype.systolicarray.SystolicArrayBall import framework.balldomain.prototype.quant.QuantBall import framework.balldomain.prototype.dequant.DequantBall import framework.balldomain.prototype.gemmini.GemminiBall +import framework.balldomain.prototype.trace.TraceBall /** * BBusModule - Ball bus module that directly extends BBus @@ -32,6 +33,7 @@ class BBusModule(b: GlobalConfig) case "QuantBall" => () => new QuantBall(b) case "DequantBall" => () => new DequantBall(b) case "GemminiBall" => () => new GemminiBall(b) + case "TraceBall" => () => new TraceBall(b) case name => throw new IllegalArgumentException(s"Unknown ball name: $name") } ballGenerator diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json index f0d7fafa..e4a7df1a 100644 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/configs/default.json @@ -1,5 +1,5 @@ { - "ballNum": 8, + "ballNum": 9, "ballIdMappings": [ {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, @@ -8,6 +8,7 @@ {"ballId": 4, "ballName": "SystolicArrayBall", "inBW": 2, "outBW": 4}, {"ballId": 5, "ballName": "QuantBall", "inBW": 1, "outBW": 1}, {"ballId": 6, "ballName": "DequantBall", "inBW": 1, "outBW": 1}, - {"ballId": 7, "ballName": "GemminiBall", "inBW": 2, "outBW": 4} + {"ballId": 7, "ballName": "GemminiBall", "inBW": 2, "outBW": 4}, + {"ballId": 8, "ballName": "TraceBall", "inBW": 1, "outBW": 1} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/README.md b/arch/src/main/scala/framework/balldomain/prototype/trace/README.md new file mode 100644 index 00000000..21e085ee --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/README.md @@ -0,0 +1,132 @@ +# TraceBall — 调试追踪 Ball + +## 概述 + +TraceBall 是一个不做计算的特殊 Ball，通过 Buckyball 指令通道提供运行时调试能力。它有两个核心功能： + +1. **Cycle Counter（计数器管理）**— 通过指令 set/release 多个独立的 cycle 计数器，用于测量任意代码区间的执行周期 +2. **Bank Backdoor（SRAM 后门读写）**— 通过 DPI-C 注入数据写入 SRAM bank，或读取 SRAM bank 数据通过 DPI-C 输出 + +所有 DPI-C 接口仅存在于 TraceBall 内部，不影响其他模块。 + +--- + +## 指令编码 + +TraceBall 使用 **两个 funct7 编码**。 + +### 指令 1：`bdb_counter` (funct7 = 48, 0x30) + +Cycle counter 管理。**不访问 SRAM，不需要 bank 端口，1 cycle 完成。** + +rs1 布局： +- rs1 = 任意（不使用，不需要设 BB_RD0/BB_WR 标志） + +rs2 布局（64-bit）： +``` +rs2[3:0] = subcmd 子命令 (0=START, 1=STOP, 2=READ) +rs2[7:4] = ctr_id 计数器编号 (0-15，最多 16 个独立计数器) +rs2[63:8] = payload +``` + +子命令定义： + +| subcmd | 名称 | 行为 | payload 含义 | +|--------|------|------|-------------| +| 0 | `CTR_START` | 启动计数器 ctr_id，记录当前 cycle 为起始点 | payload = tag（用户自定义标签，会输出到 trace） | +| 1 | `CTR_STOP` | 停止计数器 ctr_id，输出 elapsed cycles 到 DPI-C trace，然后释放计数器 | payload = 忽略 | +| 2 | `CTR_READ` | 读取计数器 ctr_id 当前值（不停止），输出到 DPI-C trace | payload = 忽略 | + +DPI-C 输出格式（写入 bdb.log）： +``` +[CTRACE] CTR_START ctr=0 tag=0xDEAD cycle=10042 +[CTRACE] CTR_STOP ctr=0 tag=0xDEAD elapsed=387 cycle=10429 +[CTRACE] CTR_READ ctr=0 current=200 cycle=10242 +``` + +### 指令 2：`bdb_backdoor` (funct7 = 49, 0x31) + +SRAM 后门读写，**所有参数（bank_id, row, data）由 DPI-C 提供**。**需要 bank 端口（inBW=1, outBW=1）。** + +rs1 布局： +``` +rs1[45] = BB_RD0 读模式：从 DPI-C 获取地址，读 SRAM，输出数据到 DPI-C +rs1[47] = BB_WR 写模式：从 DPI-C 获取地址+数据，写 SRAM +rs1[63:48] = iter 操作次数（0 = 单次，>0 = 循环 iter 次） +``` + +rs2 布局： +- rs2 = 任意（不使用） + +操作模式： + +| rs1 flag | 行为 | DPI-C 交互 | +|----------|------|-----------| +| BB_RD0 | 读模式 | RTL 调用 `dpi_backdoor_get_read_addr()` 获取 (bank_id, row)，读 SRAM，调用 `dpi_backdoor_put_read_data()` 输出数据 | +| BB_WR | 写模式 | RTL 调用 `dpi_backdoor_get_write_req()` 获取 (bank_id, row, data)，写 SRAM | + +DPI-C 输出格式： +``` +[BANK-TRACE] BACKDOOR_READ bank=2 row=5 data=0x00010002000300040005000600070008 +[BANK-TRACE] BACKDOOR_WRITE bank=3 row=10 data=0xDEADBEEFDEADBEEFDEADBEEFDEADBEEF +``` + + +## 使用示例 + +### 测量算子执行周期 + +```c +// 测量一次 matmul 的 cycle +bdb_counter_start(0, 0xA001); // 计数器 0，tag=matmul +bb_mul_warp16(A, B, C, 16); +bb_fence(); +bdb_counter_stop(0); // 输出 elapsed + +// 测量嵌套区间 +bdb_counter_start(0, 0xB001); // 外层：整个 conv + bdb_counter_start(1, 0xB002); // 内层：im2col + bb_im2col(...); + bb_fence(); + bdb_counter_stop(1); + + bdb_counter_start(2, 0xB003); // 内层：matmul + bb_mul_warp16(...); + bb_fence(); + bdb_counter_stop(2); +bdb_counter_stop(0); // 外层结束 +``` + +bdb.log 输出： +``` +[CTRACE] CTR_START ctr=0 tag=0xB001 cycle=0 +[CTRACE] CTR_START ctr=1 tag=0xB002 cycle=0 +[CTRACE] CTR_STOP ctr=1 tag=0xB002 elapsed=150 cycle=150 +[CTRACE] CTR_START ctr=2 tag=0xB003 cycle=0 +[CTRACE] CTR_STOP ctr=2 tag=0xB003 elapsed=300 cycle=300 +[CTRACE] CTR_STOP ctr=0 tag=0xB001 elapsed=456 cycle=456 +``` + +### SRAM 后门注入测试数据 + +TraceBall内有一个私有bank，不会被配置看到 + +```c +// 不走 DMA，直接通过 DPI-C 注入测试数据到 bank 0 +// （C++ 先通过 DPI-C 注入数据到TraceBall内的bank） +bb_alloc(0, 1, 1) +bdb_backdoor_mvin(16); // 注入 16 行到 私有bank +bdb_backdoor_write(0, 16); // 将私有bank的数据 注入 16 行到 bank 0 + +// 跑 Transpose +bb_transpose(0, 1, 16); +// 检查部分结果 +bdb_backdoor_peek(0, 15); // 检查最后一行 + +// 读出全部结果 +bdb_backdoor_read(1, 16); // dump bank 1 的 16 行到 trace +``` + + + +注意，所有RTL修改都在traceball内部，不允许动外部bank等地方 diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala new file mode 100644 index 00000000..374d6f3d --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala @@ -0,0 +1,365 @@ +package framework.balldomain.prototype.trace + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} +import framework.memdomain.backend.banks.SramBank +import framework.top.GlobalConfig + +/** Trace — TraceBall inner processing unit. + * + * Handles two instruction types: + * - bdb_counter (funct7=48): cycle counter management (START/STOP/READ) + * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C + * + * Backdoor write: C++ generates (row, data) via DPI-C each iteration, + * RTL writes to external bank at (wbank_reg, row). + * Backdoor read: RTL reads external bank at (rbank_reg, row from DPI-C), + * sends data back to C++ via DPI-C for logging. + * + * bank_id always comes from the instruction encoding (rs1), + * row and data come from DPI-C (C++ auto-increments row each call). + */ +@instantiable +class Trace(val b: GlobalConfig) extends Module { + val ballMapping = b.ballDomain.ballIdMappings + .find(_.ballName == "TraceBall") + .getOrElse(throw new IllegalArgumentException("TraceBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + val bankWidth = b.memDomain.bankWidth + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankRead = Vec(inBW, Flipped(new BankRead(b))) + val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val status = new BallStatus + }) + + // ============================================================ + // Constants + // ============================================================ + val CTR_START = 0.U(4.W) + val CTR_STOP = 1.U(4.W) + val CTR_READ = 2.U(4.W) + + val NUM_COUNTERS = 16 + + // ============================================================ + // State machine + // ============================================================ + val idle :: sCounter :: sBdReadExt :: sBdReadExtResp :: sBdGetWriteData :: sBdWriteExt :: sBdWriteExtResp :: complete :: Nil = + Enum(8) + val state = RegInit(idle) + + // ============================================================ + // Registers + // ============================================================ + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + + // Command decode registers + val isRead_reg = RegInit(false.B) // BB_RD0 flag + val isWrite_reg = RegInit(false.B) // BB_WR flag + val iter_reg = RegInit(0.U(16.W)) + val iterCnt = RegInit(0.U(16.W)) + + // Counter-specific registers + val subcmd_reg = RegInit(0.U(4.W)) + val ctr_id_reg = RegInit(0.U(4.W)) + val payload_reg = RegInit(0.U(56.W)) + + // Cycle counters: 16 independent counters + val cycleCounter = RegInit(0.U(64.W)) + cycleCounter := cycleCounter + 1.U + + val ctrStartCycle = RegInit(VecInit(Seq.fill(NUM_COUNTERS)(0.U(64.W)))) + val ctrTag = RegInit(VecInit(Seq.fill(NUM_COUNTERS)(0.U(56.W)))) + val ctrActive = RegInit(VecInit(Seq.fill(NUM_COUNTERS)(false.B))) + + // Bank metadata registers (from instruction encoding) + val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + + // Backdoor address/data (row from DPI-C, data from DPI-C for writes) + val bd_addr_reg = RegInit(0.U(32.W)) + val bd_data_reg = RegInit(0.U(bankWidth.W)) + + // ============================================================ + // Private SramBank (staging buffer for future use) + // ============================================================ + val privBank = Module(new SramBank(b)) + + // Default: private bank idle + privBank.io.sramRead.req.valid := false.B + privBank.io.sramRead.req.bits.addr := 0.U + privBank.io.sramRead.resp.ready := false.B + privBank.io.sramWrite.req.valid := false.B + privBank.io.sramWrite.req.bits.addr := 0.U + privBank.io.sramWrite.req.bits.data := 0.U + privBank.io.sramWrite.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + privBank.io.sramWrite.req.bits.wmode := false.B + privBank.io.sramWrite.resp.ready := true.B + + // ============================================================ + // DPI-C modules + // ============================================================ + val ctraceDpi = Module(new CTraceDPI) + ctraceDpi.io.subcmd := 0.U + ctraceDpi.io.ctr_id := 0.U + ctraceDpi.io.tag := 0.U + ctraceDpi.io.elapsed := 0.U + ctraceDpi.io.cycle := cycleCounter + ctraceDpi.io.enable := false.B + + val bdGetReadAddr = Module(new BackdoorGetReadAddrDPI) + val bdGetWriteAddr = Module(new BackdoorGetWriteAddrDPI) + val bdGetWriteData = Module(new BackdoorGetWriteDataDPI) + val bdPutReadData = Module(new BackdoorPutReadDataDPI) + val bdPutWriteDone = Module(new BackdoorPutWriteDoneDPI) + + bdGetReadAddr.io.enable := false.B + bdGetWriteAddr.io.enable := false.B + bdGetWriteData.io.enable := false.B + + bdPutReadData.io.bank_id := 0.U + bdPutReadData.io.row := 0.U + bdPutReadData.io.data_lo := 0.U + bdPutReadData.io.data_hi := 0.U + bdPutReadData.io.enable := false.B + + bdPutWriteDone.io.bank_id := 0.U + bdPutWriteDone.io.row := 0.U + bdPutWriteDone.io.data_lo := 0.U + bdPutWriteDone.io.data_hi := 0.U + bdPutWriteDone.io.enable := false.B + + // ============================================================ + // External bank port defaults + // ============================================================ + for (i <- 0 until inBW) { + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).group_id := 0.U + io.bankRead(i).io.req.valid := false.B + io.bankRead(i).io.req.bits.addr := 0.U + io.bankRead(i).io.resp.ready := false.B + } + + for (i <- 0 until outBW) { + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).group_id := 0.U + io.bankWrite(i).io.req.valid := false.B + io.bankWrite(i).io.req.bits.addr := 0.U + io.bankWrite(i).io.req.bits.data := 0.U + io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) + io.bankWrite(i).io.req.bits.wmode := false.B + io.bankWrite(i).io.resp.ready := false.B + } + + // ============================================================ + // Command interface + // ============================================================ + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + + // ============================================================ + // State machine + // ============================================================ + switch(state) { + is(idle) { + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + + val cmd = io.cmdReq.bits.cmd + val rs2 = cmd.rs2 + + // Distinguish counter vs backdoor by op1_en / wr_spad_en + val isBackdoor = cmd.op1_en || cmd.wr_spad_en + + isRead_reg := cmd.op1_en // BB_RD0 + isWrite_reg := cmd.wr_spad_en // BB_WR + iter_reg := cmd.iter + iterCnt := 0.U + + // Counter fields from rs2 + subcmd_reg := rs2(3, 0) + ctr_id_reg := rs2(7, 4) + payload_reg := rs2(63, 8) + + // Bank IDs from decoded cmd + rbank_reg := cmd.op1_bank + wbank_reg := cmd.wr_bank + + when(!isBackdoor) { + state := sCounter + }.elsewhen(cmd.wr_spad_en) { + // Backdoor write: get row+data from DPI-C, write external bank + state := sBdGetWriteData + }.otherwise { + // Backdoor read: get row from DPI-C, read external bank + state := sBdReadExt + } + } + } + + // ---------------------------------------------------------- + // Counter instruction: execute and complete in 1 cycle + // ---------------------------------------------------------- + is(sCounter) { + val cid = ctr_id_reg + + ctraceDpi.io.subcmd := subcmd_reg + ctraceDpi.io.ctr_id := cid + + switch(subcmd_reg) { + is(CTR_START) { + ctrStartCycle(cid) := cycleCounter + ctrTag(cid) := payload_reg + ctrActive(cid) := true.B + + ctraceDpi.io.tag := payload_reg + ctraceDpi.io.elapsed := 0.U + ctraceDpi.io.enable := true.B + } + is(CTR_STOP) { + val elapsed = cycleCounter - ctrStartCycle(cid) + ctrActive(cid) := false.B + + ctraceDpi.io.tag := ctrTag(cid) + ctraceDpi.io.elapsed := elapsed + ctraceDpi.io.enable := true.B + } + is(CTR_READ) { + val current = cycleCounter - ctrStartCycle(cid) + + ctraceDpi.io.tag := ctrTag(cid) + ctraceDpi.io.elapsed := current + ctraceDpi.io.enable := true.B + } + } + + state := complete + } + + // ---------------------------------------------------------- + // Backdoor read: get row from DPI-C, read external bank + // ---------------------------------------------------------- + is(sBdReadExt) { + // Get row from DPI-C (C++ auto-increments) + bdGetReadAddr.io.enable := true.B + val row = bdGetReadAddr.io.result(31, 0) + + bd_addr_reg := row + + // Issue read to external bank (bank_id from instruction) + io.bankRead(0).io.req.valid := true.B + io.bankRead(0).io.req.bits.addr := row + io.bankRead(0).io.resp.ready := true.B + + when(io.bankRead(0).io.req.fire) { + state := sBdReadExtResp + } + } + + is(sBdReadExtResp) { + io.bankRead(0).io.resp.ready := true.B + + when(io.bankRead(0).io.resp.valid) { + val data = io.bankRead(0).io.resp.bits.data + + // Output data via DPI-C + bdPutReadData.io.bank_id := rbank_reg + bdPutReadData.io.row := bd_addr_reg + bdPutReadData.io.data_lo := data(63, 0) + bdPutReadData.io.data_hi := data(127, 64) + bdPutReadData.io.enable := true.B + + // Check if more iterations + iterCnt := iterCnt + 1.U + when(iterCnt >= iter_reg) { + state := complete + }.otherwise { + state := sBdReadExt + } + } + } + + // ---------------------------------------------------------- + // Backdoor write: get row+data from DPI-C, write external bank + // ---------------------------------------------------------- + is(sBdGetWriteData) { + // Get row from DPI-C (C++ auto-increments and pre-generates data) + bdGetWriteAddr.io.enable := true.B + val row = bdGetWriteAddr.io.result(31, 0) + bd_addr_reg := row + + // Get data from DPI-C + bdGetWriteData.io.enable := true.B + val fullData = Cat(bdGetWriteData.io.data_hi, bdGetWriteData.io.data_lo) + bd_data_reg := fullData + + state := sBdWriteExt + } + + is(sBdWriteExt) { + // Write to external bank (bank_id from instruction) + io.bankWrite(0).io.req.valid := true.B + io.bankWrite(0).io.req.bits.addr := bd_addr_reg + io.bankWrite(0).io.req.bits.data := bd_data_reg + io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) + io.bankWrite(0).io.req.bits.wmode := false.B + io.bankWrite(0).io.resp.ready := true.B + + when(io.bankWrite(0).io.req.fire) { + state := sBdWriteExtResp + } + } + + is(sBdWriteExtResp) { + io.bankWrite(0).io.resp.ready := true.B + + when(io.bankWrite(0).io.resp.valid) { + // Log the write via DPI-C + bdPutWriteDone.io.bank_id := wbank_reg + bdPutWriteDone.io.row := bd_addr_reg + bdPutWriteDone.io.data_lo := bd_data_reg(63, 0) + bdPutWriteDone.io.data_hi := bd_data_reg(127, 64) + bdPutWriteDone.io.enable := true.B + + // Check if more iterations + iterCnt := iterCnt + 1.U + when(iterCnt >= iter_reg) { + state := complete + }.otherwise { + state := sBdGetWriteData + } + } + } + + // ---------------------------------------------------------- + // Complete: fire cmdResp + // ---------------------------------------------------------- + is(complete) { + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + when(io.cmdResp.fire) { + state := idle + } + } + } + + // ============================================================ + // Status + // ============================================================ + io.status.idle := state === idle + io.status.running := state =/= idle && state =/= complete +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala new file mode 100644 index 00000000..fd38a514 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala @@ -0,0 +1,43 @@ +package framework.balldomain.prototype.trace + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.top.GlobalConfig + +/** TraceBall — Debug trace Ball providing cycle counters and SRAM backdoor. + * + * Uses two funct7 encodings: + * - bdb_counter (funct7=48): cycle counter management + * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C + */ +@instantiable +class TraceBall(val b: GlobalConfig) extends Module with HasBlink { + + val ballCommonConfig = b.ballDomain.ballIdMappings + .find(_.ballName == "TraceBall") + .getOrElse(throw new IllegalArgumentException("TraceBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + + val traceUnit: Instance[Trace] = Instantiate(new Trace(b)) + + traceUnit.io.cmdReq <> io.cmdReq + traceUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + traceUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + traceUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + io.status <> traceUnit.io.status +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala new file mode 100644 index 00000000..3bd7e1aa --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala @@ -0,0 +1,231 @@ +package framework.balldomain.prototype.trace + +import chisel3._ +import chisel3.util._ + +/** DPI-C BlackBox for cycle counter trace. + * Outputs [CTRACE] lines to bdb.log. + */ +class CTraceDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val subcmd = Input(UInt(8.W)) + val ctr_id = Input(UInt(32.W)) + val tag = Input(UInt(64.W)) + val elapsed = Input(UInt(64.W)) + val cycle = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "CTraceDPI.v", + """ + |import "DPI-C" function void dpi_ctrace( + | input byte unsigned subcmd, + | input int unsigned ctr_id, + | input longint unsigned tag, + | input longint unsigned elapsed, + | input longint unsigned cycle + |); + | + |module CTraceDPI( + | input [7:0] subcmd, + | input [31:0] ctr_id, + | input [63:0] tag, + | input [63:0] elapsed, + | input [63:0] cycle, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_ctrace(subcmd, ctr_id, tag, elapsed, cycle); + | end + | end + |endmodule + """.stripMargin + ) +} + +/** DPI-C BlackBox for backdoor get_read_addr. + * Returns packed [63:32]=bank_id, [31:0]=row. + */ +class BackdoorGetReadAddrDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val result = Output(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "BackdoorGetReadAddrDPI.v", + """ + |import "DPI-C" function longint unsigned dpi_backdoor_get_read_addr(); + | + |module BackdoorGetReadAddrDPI( + | output [63:0] result, + | input enable + |); + | reg [63:0] result_reg; + | assign result = result_reg; + | always @(*) begin + | result_reg = 64'd0; + | if (enable) begin + | result_reg = dpi_backdoor_get_read_addr(); + | end + | end + |endmodule + """.stripMargin + ) +} + +/** DPI-C BlackBox for backdoor get_write_addr. + * Returns packed [63:32]=bank_id, [31:0]=row. + */ +class BackdoorGetWriteAddrDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val result = Output(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "BackdoorGetWriteAddrDPI.v", + """ + |import "DPI-C" function longint unsigned dpi_backdoor_get_write_addr(); + | + |module BackdoorGetWriteAddrDPI( + | output [63:0] result, + | input enable + |); + | reg [63:0] result_reg; + | assign result = result_reg; + | always @(*) begin + | result_reg = 64'd0; + | if (enable) begin + | result_reg = dpi_backdoor_get_write_addr(); + | end + | end + |endmodule + """.stripMargin + ) +} + +/** DPI-C BlackBox for backdoor get_write_data. + * Returns 128-bit data as two 64-bit outputs. + */ +class BackdoorGetWriteDataDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val data_lo = Output(UInt(64.W)) + val data_hi = Output(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "BackdoorGetWriteDataDPI.v", + """ + |import "DPI-C" function void dpi_backdoor_get_write_data( + | output longint unsigned data_lo, + | output longint unsigned data_hi + |); + | + |module BackdoorGetWriteDataDPI( + | output [63:0] data_lo, + | output [63:0] data_hi, + | input enable + |); + | reg [63:0] data_lo_reg; + | reg [63:0] data_hi_reg; + | assign data_lo = data_lo_reg; + | assign data_hi = data_hi_reg; + | always @(*) begin + | data_lo_reg = 64'd0; + | data_hi_reg = 64'd0; + | if (enable) begin + | dpi_backdoor_get_write_data(data_lo_reg, data_hi_reg); + | end + | end + |endmodule + """.stripMargin + ) +} + +/** DPI-C BlackBox for backdoor put_read_data. + * Reports read data back to C++ for logging. + */ +class BackdoorPutReadDataDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val bank_id = Input(UInt(32.W)) + val row = Input(UInt(32.W)) + val data_lo = Input(UInt(64.W)) + val data_hi = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "BackdoorPutReadDataDPI.v", + """ + |import "DPI-C" function void dpi_backdoor_put_read_data( + | input int unsigned bank_id, + | input int unsigned row, + | input longint unsigned data_lo, + | input longint unsigned data_hi + |); + | + |module BackdoorPutReadDataDPI( + | input [31:0] bank_id, + | input [31:0] row, + | input [63:0] data_lo, + | input [63:0] data_hi, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_backdoor_put_read_data(bank_id, row, data_lo, data_hi); + | end + | end + |endmodule + """.stripMargin + ) +} + +/** DPI-C BlackBox for backdoor put_write_done. + * Reports write completion back to C++ for logging. + */ +class BackdoorPutWriteDoneDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val bank_id = Input(UInt(32.W)) + val row = Input(UInt(32.W)) + val data_lo = Input(UInt(64.W)) + val data_hi = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "BackdoorPutWriteDoneDPI.v", + """ + |import "DPI-C" function void dpi_backdoor_put_write_done( + | input int unsigned bank_id, + | input int unsigned row, + | input longint unsigned data_lo, + | input longint unsigned data_hi + |); + | + |module BackdoorPutWriteDoneDPI( + | input [31:0] bank_id, + | input [31:0] row, + | input [63:0] data_lo, + | input [63:0] data_hi, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_backdoor_put_write_done(bank_id, row, data_lo, data_hi); + | end + | end + |endmodule + """.stripMargin + ) +} diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index fdf223db..37b4dbdf 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -1,6 +1,7 @@ package framework.core.bbtile import chisel3._ +import chisel3.util._ import chisel3.experimental.hierarchy.{Instance, Instantiate} import org.chipsalliance.cde.config._ @@ -36,16 +37,20 @@ import freechips.rocketchip.util.BooleanToAugmentedBoolean import framework.top.GlobalConfig import framework.core.bbtile.id.RVVRoCCDecode +import framework.memdomain.backend.MemRequestIO +import framework.memdomain.backend.shared.SharedMemBackend +import framework.memdomain.frontend.outside_channel.MemConfigerIO /** * BBTile — a composable tile containing Rocket core(s) + optional Buckyball accelerator(s). * - * Design principles: - * - Extends BaseTile for CanAttachTile compatibility (diplomacy shell) - * - Mixes in HasHellaCache + HasICacheFrontend for Rocket core infrastructure (unavoidable) - * - Buckyball accelerator is composed as an independent module, NOT via LazyRoCCBB inheritance - * - RoCC cmd/resp are wired directly inside the tile - * - Accelerator TileLink DMA nodes are declared in the diplomacy shell + * When nCores=1 (default), behaviour is identical to the original single-core tile. + * When nCores>1, the tile contains N (RocketBB + BuckyballAccelerator) pairs that share + * a single SharedMemBackend and BarrierUnit. + * + * The trait-provided DCache/ICache/PTW serve core-0. Cores 1..N-1 are wired entirely + * inside BBTileModuleImp (no extra diplomacy DCache/ICache — they share core-0's cache + * hierarchy via the same TL xbar for now; independent caches are a future enhancement). */ class BBTile private ( val bbParams: BBTileParams, @@ -67,6 +72,8 @@ class BBTile private ( ) = this(params, crossing.crossingType, lookup, BBTile.injectBuildRoCC(p, params.withBuckyball)) + val nCores = bbParams.nCores + // RoCC CSRs — Buckyball doesn't use custom CSRs, so this is always empty val roccCSRs: Seq[Seq[CustomCSR]] = Nil @@ -107,35 +114,32 @@ class BBTile private ( tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // --------------------------------------------------------------------------- - // Buckyball accelerator TileLink nodes (diplomacy layer) + // Buckyball accelerator TileLink nodes (diplomacy layer) — N pairs of DMA // --------------------------------------------------------------------------- val bbConfig = bbParams.buckyballConfig - val bb_reader_node = + val bb_reader_nodes: Seq[Option[TLClientNode]] = (0 until nCores).map { i => if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "bb-dma-reader", + name = s"bb-dma-reader-$i", sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) - )))))) - else None + )))))) else None + } - val bb_writer_node = + val bb_writer_nodes: Seq[Option[TLClientNode]] = (0 until nCores).map { i => if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( - name = "bb-dma-writer", + name = s"bb-dma-writer-$i", sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) - )))))) - else None - - val bb_xbar_node = - if (bbParams.withBuckyball) { - val xbar = TLXbar() - xbar := TLBuffer() := bb_reader_node.get - xbar := TLBuffer() := bb_writer_node.get - Some(xbar) - } else None - - // Connect Buckyball DMA to tile master port (through width widget) - bb_xbar_node.foreach { xbar => - tlOtherMastersNode :=* TLWidthWidget(bbConfig.memDomain.dma_buswidth / 8) := TLBuffer() := xbar + )))))) else None + } + + // Gather all DMA nodes into one xbar + if (bbParams.withBuckyball) { + val bb_xbar = TLXbar() + for (i <- 0 until nCores) { + bb_xbar := TLBuffer() := bb_reader_nodes(i).get + bb_xbar := TLBuffer() := bb_writer_nodes(i).get + } + tlOtherMastersNode :=* TLWidthWidget(bbConfig.memDomain.dma_buswidth / 8) := TLBuffer() := bb_xbar } // --------------------------------------------------------------------------- @@ -145,10 +149,10 @@ class BBTile private ( masterNode :=* tlOtherMastersNode DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) - // DCache port count: core + PTW(via usingVM) + DTIM + vector + // DCache port count: core + PTW(via usingVM) + DTIM + vector + RoCC tieoff nDCachePorts += 1 + (dtim_adapter.isDefined).toInt + bbParams.core.vector.map(_.useDCache.toInt).getOrElse(0) + - bbParams.withBuckyball.toInt // RoCC mem port (tied off but counted by dcacheArbPorts) + bbParams.withBuckyball.toInt // --------------------------------------------------------------------------- // Device tree properties @@ -180,9 +184,9 @@ class BBTile private ( Resource(cpuDevice, "reg").bind(ResourceAddress(bbParams.tileId)) } - // Buckyball needs one PTW port for its TLB + // Buckyball needs one PTW port per accelerator if (bbParams.withBuckyball) { - nPTWPorts += 1 + nPTWPorts += nCores } override lazy val module = new BBTileModuleImp(this) @@ -211,6 +215,7 @@ class BBTile private ( class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasICacheFrontendModule { Annotated.params(this, outer.bbParams) + val nCores = outer.nCores // --- FPU (optional) --- val fpuOpt = outer.bbParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) @@ -281,26 +286,9 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC outer.dtim_adapter.foreach(lm => dcachePorts += lm.module.io.dmem) // --------------------------------------------------------------------------- - // Buckyball accelerator (composed, not inherited via LazyRoCCBB) + // Helper: wire a BuckyballAccelerator's PTW to tile's PTW subsystem // --------------------------------------------------------------------------- - if (outer.bbParams.withBuckyball) { - val (tl_reader, edge_reader) = outer.bb_reader_node.get.out(0) - val (tl_writer, _) = outer.bb_writer_node.get.out(0) - - val buckyball = Module(new BuckyballAccelerator(outer.bbConfig)(edge_reader)) - buckyball.io.hartid := outer.hartIdSinkNode.bundle - - // RoCC cmd/resp: direct wiring (both use RoCCCommandBB/RoCCResponseBB) - buckyball.io.cmd <> core.io.rocc.cmd - core.io.rocc.resp <> buckyball.io.resp - core.io.rocc.busy := buckyball.io.busy - core.io.rocc.interrupt := buckyball.io.interrupt - - // DMA TileLink - tl_reader <> buckyball.io.tl_reader - tl_writer <> buckyball.io.tl_writer - - // PTW: Buckyball's BBTLBPTWIO <-> tile's TLBPTWIO (field-by-field adaptation) + def wireBBPtw(buckyball: BuckyballAccelerator): Unit = { val bbPtw = Wire(new TLBPTWIO) ptwPorts += bbPtw bbPtw.req.valid := buckyball.io.ptw(0).req.valid @@ -361,17 +349,45 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC } buckyball.io.ptw(0).customCSRs := DontCare bbPtw.customCSRs := DontCare + } - // TLB exception - buckyball.io.tlbExp(0).flush_skip := false.B - buckyball.io.tlbExp(0).flush_retry := false.B + // --------------------------------------------------------------------------- + // Buckyball accelerators — N instances sharing SharedMemBackend + BarrierUnit + // --------------------------------------------------------------------------- + if (outer.bbParams.withBuckyball) { + val bankChannel = outer.bbConfig.memDomain.bankChannel - // CPU sfence → Buckyball TLB flush - buckyball.io.sfence := ptw.io.dpath.sfence.valid + // Instantiate N accelerators + val accelerators = (0 until nCores).map { i => + val (tl_reader, edge) = outer.bb_reader_nodes(i).get.out(0) + val (tl_writer, _) = outer.bb_writer_nodes(i).get.out(0) + val acc = Module(new BuckyballAccelerator(outer.bbConfig)(edge)) + acc.io.hartid := outer.hartIdSinkNode.bundle + i.U - // RoCC mem: Buckyball doesn't use the HellaCacheIO mem port, but the - // DCache arbiter still expects a port for it (dcacheArbPorts counts BuildRoCC.size). - // Route through SimpleHellaCacheIF with tied-off requestor side. + // DMA TileLink + tl_reader <> acc.io.tl_reader + tl_writer <> acc.io.tl_writer + + // PTW + wireBBPtw(acc) + + // TLB exception + acc.io.tlbExp(0).flush_skip := false.B + acc.io.tlbExp(0).flush_retry := false.B + + // CPU sfence → Buckyball TLB flush + acc.io.sfence := ptw.io.dpath.sfence.valid + + acc + } + + // Core-0 RoCC wiring (the single Rocket core drives accelerator 0) + accelerators(0).io.cmd <> core.io.rocc.cmd + core.io.rocc.resp <> accelerators(0).io.resp + core.io.rocc.busy := accelerators(0).io.busy + core.io.rocc.interrupt := accelerators(0).io.interrupt + + // RoCC mem: tied-off HellaCacheIF for the DCache arbiter port count val roccMemIF = Module(new SimpleHellaCacheIF()) roccMemIF.io.requestor.req.valid := false.B roccMemIF.io.requestor.req.bits := DontCare @@ -381,6 +397,43 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC roccMemIF.io.requestor.keep_clock_enabled := false.B dcachePorts += roccMemIF.io.cache core.io.rocc.mem := DontCare + + // SharedMemBackend (tile-level singleton) + val sharedBackend = Module(new SharedMemBackend(outer.bbConfig)) + + // Connect each accelerator's shared ports to the SharedMemBackend + for (i <- 0 until nCores) { + for (ch <- 0 until bankChannel) { + val slot = i * bankChannel + ch + sharedBackend.io.mem_req(slot) <> accelerators(i).io.shared_mem_req(ch) + } + // Shared query: connect per-core query to shared backend + // (only one query port on SharedMemBackend — for now use accelerator 0's query; + // each accelerator's MemBackend routes shared queries through its IO) + } + + // Shared config arbiter: N accelerators → 1 SharedMemBackend config port + val cfgArb = Module(new Arbiter(new MemConfigerIO(outer.bbConfig), nCores)) + for (i <- 0 until nCores) { + cfgArb.io.in(i) <> accelerators(i).io.shared_config + } + sharedBackend.io.config <> cfgArb.io.out + + // Shared query — simplified: each accelerator queries independently, + // but SharedMemBackend has one query port. Use accelerator 0's for now. + sharedBackend.io.query_vbank_id := accelerators(0).io.shared_query_vbank_id + accelerators(0).io.shared_query_group_count := sharedBackend.io.query_group_count + for (i <- 1 until nCores) { + accelerators(i).io.shared_query_group_count := sharedBackend.io.query_group_count + } + + // BarrierUnit (tile-level singleton) + val barrierUnit = Module(new BarrierUnit(nCores)) + for (i <- 0 until nCores) { + barrierUnit.io.arrive(i) := accelerators(i).io.barrier_arrive + accelerators(i).io.barrier_release := barrierUnit.io.release(i) + } + } else { // No accelerator — tie off RoCC core.io.rocc.cmd.ready := false.B diff --git a/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala b/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala new file mode 100644 index 00000000..40d8a152 --- /dev/null +++ b/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala @@ -0,0 +1,34 @@ +package framework.core.bbtile + +import chisel3._ +import chisel3.experimental.hierarchy.{instantiable, public} + +/** + * BarrierUnit — tile-level hardware barrier for multi-core synchronization. + * + * Each core's BuckyballAccelerator raises arrive(i) after its ROB drains. + * When all N cores have arrived, release(i) is asserted for one cycle, + * allowing all cores to proceed simultaneously. + * + * @param nCores number of cores in this tile + */ +@instantiable +class BarrierUnit(val nCores: Int) extends Module { + @public + val io = IO(new Bundle { + val arrive = Input(Vec(nCores, Bool())) + val release = Output(Vec(nCores, Bool())) + }) + + val arrived = RegInit(VecInit(Seq.fill(nCores)(false.B))) + val allArrived = arrived.asUInt.andR + + for (i <- 0 until nCores) { + when(io.arrive(i)) { arrived(i) := true.B } + io.release(i) := allArrived + } + + when(allArrived) { + for (i <- 0 until nCores) { arrived(i) := false.B } + } +} diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index 403312af..1189694b 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -9,6 +9,8 @@ import framework.top.GlobalConfig import framework.frontend.Frontend import framework.gpdomain.GpDomain import framework.memdomain.MemDomain +import framework.memdomain.backend.MemRequestIO +import framework.memdomain.frontend.outside_channel.{MemConfigerIO} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBPTWIO} import examples.toy.balldomain.BallDomain @@ -46,6 +48,16 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module // TileLink DMA bundles (from tile's diplomacy nodes) val tl_reader = new TLBundle(edge.bundle) val tl_writer = new TLBundle(edge.bundle) + + // Shared memory path — exposed to tile level for multi-core SharedMemBackend + val shared_mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + val shared_config = Decoupled(new MemConfigerIO(b)) + val shared_query_vbank_id = Output(UInt(8.W)) + val shared_query_group_count = Input(UInt(4.W)) + + // Barrier interface — connected to tile-level BarrierUnit + val barrier_arrive = Output(Bool()) + val barrier_release = Input(Bool()) }) // --- Instantiate domains --- @@ -126,6 +138,16 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module io.tl_reader <> memDomain.io.tl_reader io.tl_writer <> memDomain.io.tl_writer + // --- Shared memory passthrough --- + io.shared_mem_req <> memDomain.io.shared_mem_req + io.shared_config <> memDomain.io.shared_config + io.shared_query_vbank_id := memDomain.io.shared_query_vbank_id + memDomain.io.shared_query_group_count := io.shared_query_group_count + + // --- Barrier passthrough --- + io.barrier_arrive := frontend.io.barrier_arrive + frontend.io.barrier_release := io.barrier_release + // --- Response & status --- io.resp <> frontend.io.resp io.busy := frontend.io.busy diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala index d3dc86d7..bf406de2 100644 --- a/arch/src/main/scala/framework/frontend/Frontend.scala +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -35,6 +35,10 @@ class Frontend(val b: GlobalConfig) extends Module { // RoCC response val resp = Decoupled(new RoCCResponseBB(b.core.xLen)) val busy = Output(Bool()) + + // Barrier interface — passthrough to GlobalRS + val barrier_arrive = Output(Bool()) + val barrier_release = Input(Bool()) }) val gDecoder: Instance[GlobalDecoder] = Instantiate(new GlobalDecoder(b)) @@ -57,4 +61,8 @@ class Frontend(val b: GlobalConfig) extends Module { io.resp <> globalRs.io.rs_rocc_o.resp io.busy := globalRs.io.rs_rocc_o.busy + // Barrier passthrough + io.barrier_arrive := globalRs.io.barrier_arrive + globalRs.io.barrier_release := io.barrier_release + } diff --git a/arch/src/main/scala/framework/frontend/decoder/GISA.scala b/arch/src/main/scala/framework/frontend/decoder/GISA.scala index d71906d3..7a4db238 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GISA.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GISA.scala @@ -4,7 +4,8 @@ import chisel3._ import chisel3.util._ object GISA { - val FENCE_BITPAT = BitPat("b0011111") // 31 (0x1F) + val FENCE_BITPAT = BitPat("b0011111") // 31 (0x1F) + val BARRIER_BITPAT = BitPat("b0110010") // 50 (0x32) } // Domain ID constants diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index 06dc86c8..a574e9db 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -24,6 +24,7 @@ class PostGDCmd(val b: GlobalConfig) extends Bundle { val cmd = new RoCCCommandBB(b.core.xLen) val bankAccess = new BankAccessInfo(log2Up(b.memDomain.bankNum)) val isFence = Bool() + val isBarrier = Bool() } @instantiable @@ -54,13 +55,14 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { (func7 === MSET_BITPAT) val is_frontend_inst = func7 === FENCE_BITPAT + val is_barrier_inst = func7 === BARRIER_BITPAT // RVV instructions: opcode 0x57 (vector compute), 0x07 (vector load), 0x27 (vector store) val is_gp_inst = (opcode === RVV_OPCODE_V) || (opcode === RVV_OPCODE_VL) || (opcode === RVV_OPCODE_VS) - val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_gp_inst + val is_ball_inst = !is_mem_inst && !is_frontend_inst && !is_barrier_inst && !is_gp_inst // Encode domain ID val domain_id = MuxCase( @@ -102,4 +104,5 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { io.id_o.bits.cmd := io.id_i.bits.cmd io.id_o.bits.bankAccess := bankAccess io.id_o.bits.isFence := is_frontend_inst + io.id_o.bits.isBarrier := is_barrier_inst } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 535fa234..3966cf64 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -51,6 +51,9 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { val busy = Output(Bool()) } + // Barrier interface — connected to tile-level BarrierUnit via BuckyballAccelerator + val barrier_arrive = Output(Bool()) + val barrier_release = Input(Bool()) }) val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) @@ -71,17 +74,44 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { } // ----------------------------------------------------------------------------- -// Inbound - instruction allocation (only non-fence instructions enter ROB) +// Barrier handling — barrier does NOT enter ROB. +// Two phases: +// 1. barrierWaitROB: wait for own ROB to drain (implicit fence) +// 2. barrierWaitRelease: arrive at BarrierUnit, wait for all cores // ----------------------------------------------------------------------------- - rob.io.alloc.valid := io.global_decode_cmd_i.valid && !io.global_decode_cmd_i.bits.isFence && !fenceActive + val isBarrierCmd = io.global_decode_cmd_i.valid && io.global_decode_cmd_i.bits.isBarrier + + val barrierWaitROB = RegInit(false.B) + val barrierWaitRelease = RegInit(false.B) + + when(isBarrierCmd && !barrierWaitROB && !barrierWaitRelease && !fenceActive) { + barrierWaitROB := true.B + } + when(barrierWaitROB && rob.io.empty) { + barrierWaitROB := false.B + barrierWaitRelease := true.B + } + when(barrierWaitRelease && io.barrier_release) { + barrierWaitRelease := false.B + } + + io.barrier_arrive := barrierWaitRelease + +// ----------------------------------------------------------------------------- +// Inbound - instruction allocation (fence/barrier do not enter ROB) +// ----------------------------------------------------------------------------- + val isFrontendCmd = io.global_decode_cmd_i.bits.isFence || io.global_decode_cmd_i.bits.isBarrier + val anyStall = fenceActive || barrierWaitROB || barrierWaitRelease + + rob.io.alloc.valid := io.global_decode_cmd_i.valid && !isFrontendCmd && !anyStall rob.io.alloc.bits := io.global_decode_cmd_i.bits - // Backpressure: during fence, accept the fence cmd immediately but block further cmds - // until ROB drains. For normal cmds, wait for ROB ready. + // Backpressure: fence/barrier are consumed immediately (if not already active), + // normal cmds wait for ROB ready and no stall. io.global_decode_cmd_i.ready := Mux( - io.global_decode_cmd_i.bits.isFence, - !fenceActive, // Accept fence if not already processing one - rob.io.alloc.ready && !fenceActive // Normal cmd: ROB ready and no fence active + isFrontendCmd, + !anyStall, // Accept fence/barrier if no stall active + rob.io.alloc.ready && !anyStall // Normal cmd: ROB ready and no stall ) // ----------------------------------------------------------------------------- @@ -145,6 +175,6 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { io.rs_rocc_o.resp.valid := false.B io.rs_rocc_o.resp.bits.rd := 0.U io.rs_rocc_o.resp.bits.data := 0.U - // busy when ROB is not empty OR fence is active (waiting for drain) - io.rs_rocc_o.busy := !rob.io.empty || fenceActive + // busy when ROB is not empty OR fence/barrier is active + io.rs_rocc_o.busy := !rob.io.empty || fenceActive || barrierWaitROB || barrierWaitRelease } diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 60772cd9..619c964e 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -8,8 +8,9 @@ import framework.balldomain.blink.{BankRead, BankWrite} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.top.GlobalConfig - +import framework.memdomain.backend.MemRequestIO import framework.memdomain.frontend.MemFrontend +import framework.memdomain.frontend.outside_channel.{MemConfigerIO} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBPTWIO} import framework.memdomain.midend.MemMidend import framework.memdomain.backend.MemBackend @@ -24,38 +25,34 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ------------------------------------------------- // Command Channel // ------------------------------------------------- - // global RS -> MemDomain val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) - // MemDomain -> global RS val global_complete_o = Decoupled(new GlobalRsComplete(b)) val busy = Output(Bool()) // ------------------------------------------------- // Inside Channel // ------------------------------------------------- - // Bank interface for interaction with Ball Domain - // BankRead/BankWrite are used with Flipped at Ball Device side - // MemDomain receives requests from Ball Domain, so uses raw Bundle (Input for bank_id) - // Use bbusProducerChannels and bbusConsumerChannels instead of bankNum to match BallDomain output val ballDomain = new Bundle { val bankRead = Vec(totalBallRead, new BankRead(b)) val bankWrite = Vec(totalBallWrite, new BankWrite(b)) - } // ------------------------------------------------- // Outside Channel // ------------------------------------------------- - // PTW and TLB exception interfaces for external connection val ptw = Vec(1, new BBTLBPTWIO(b)) val tlbExp = Vec(1, new BBTLBExceptionIO) - - // TileLink physical connections for DMA val tl_reader = new TLBundle(edge.bundle) val tl_writer = new TLBundle(edge.bundle) - - // Core/thread id used by shared memory addressing. val hartid = Input(UInt(b.core.xLen.W)) + + // ------------------------------------------------- + // Shared memory path — exposed for tile-level sharing + // ------------------------------------------------- + val shared_mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + val shared_config = Decoupled(new MemConfigerIO(b)) + val shared_query_vbank_id = Output(UInt(8.W)) + val shared_query_group_count = Input(UInt(4.W)) }) val frontend: Instance[MemFrontend] = Instantiate(new MemFrontend(b)(edge)) @@ -68,25 +65,24 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { frontend.io.query_group_count := backend.io.query_group_count frontend.io.hartid := io.hartid + // Shared query: backend delegates shared query to external SharedMemBackend + backend.io.shared_query_group_count := io.shared_query_group_count + io.shared_query_vbank_id := backend.io.shared_query_vbank_id + // ------------------------------------------------- // Connection with outside (all in frontend) // ------------------------------------------------- - // Global RS interface frontend.io.global_issue_i <> io.global_issue_i frontend.io.global_complete_o <> io.global_complete_o io.busy := frontend.io.busy - // TLB interface - // Note: frontend.io.tlb is connected internally to DMA modules - // Only PTW and TLB exception interfaces are exposed to outside frontend.io.ptw <> io.ptw frontend.io.tlbExp <> io.tlbExp - // TileLink physical connections for DMA (Reader/Writer are inside frontend) io.tl_reader <> frontend.io.tl_reader io.tl_writer <> frontend.io.tl_writer - // Ball Domain interface connects directly to midend (Ball devices' read/write requests) + // Ball Domain interface connects directly to midend midend.io.balldomain.bankRead <> io.ballDomain.bankRead midend.io.balldomain.bankWrite <> io.ballDomain.bankWrite midend.io.frontend.bankRead <> frontend.io.interdma.bankRead @@ -97,4 +93,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { midend.io.mem_req <> backend.io.mem_req backend.io.config <> frontend.io.config + + // Shared path passthrough + io.shared_mem_req <> backend.io.shared_mem_req + io.shared_config <> backend.io.shared_config } diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index f1ff25e0..f49f9bd2 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -6,7 +6,6 @@ import chisel3.util._ import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig import framework.memdomain.backend.privatepath.PrivateMemBackend -import framework.memdomain.backend.shared.SharedMemBackend @instantiable class MemBackend(val b: GlobalConfig) extends Module { @@ -16,7 +15,16 @@ class MemBackend(val b: GlobalConfig) extends Module { val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) val config = Flipped(Decoupled(new MemConfigerIO(b))) - // Query interface for frontend to get group count + // Shared path — exposed to tile level for multi-core sharing. + // bankChannel ports: one per midend channel of this core. + val shared_mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + val shared_config = Decoupled(new MemConfigerIO(b)) + + // Query interface: shared query goes out, private query handled internally. + val shared_query_vbank_id = Output(UInt(8.W)) + val shared_query_group_count = Input(UInt(4.W)) + + // Original query interface from frontend val query_vbank_id = Input(UInt(8.W)) val query_is_shared = Input(Bool()) val query_group_count = Output(UInt(4.W)) @@ -24,20 +32,19 @@ class MemBackend(val b: GlobalConfig) extends Module { // Keep the private backend datapath unchanged and isolate it in a dedicated module. val privateBackend: Instance[PrivateMemBackend] = Instantiate(new PrivateMemBackend(b)) - val sharedBackend: Instance[SharedMemBackend] = Instantiate(new SharedMemBackend(b)) // Route config to the selected backend only. val cfgToShared = io.config.bits.is_shared privateBackend.io.config.valid := io.config.valid && !cfgToShared privateBackend.io.config.bits := io.config.bits - sharedBackend.io.config.valid := io.config.valid && cfgToShared - sharedBackend.io.config.bits := io.config.bits - io.config.ready := Mux(cfgToShared, sharedBackend.io.config.ready, privateBackend.io.config.ready) + io.shared_config.valid := io.config.valid && cfgToShared + io.shared_config.bits := io.config.bits + io.config.ready := Mux(cfgToShared, io.shared_config.ready, privateBackend.io.config.ready) - // Query selected backend according to decoded shared/private intent. + // Query routing privateBackend.io.query_vbank_id := io.query_vbank_id - sharedBackend.io.query_vbank_id := io.query_vbank_id - io.query_group_count := Mux(io.query_is_shared, sharedBackend.io.query_group_count, privateBackend.io.query_group_count) + io.shared_query_vbank_id := io.query_vbank_id + io.query_group_count := Mux(io.query_is_shared, io.shared_query_group_count, privateBackend.io.query_group_count) // Track whether a vbank is currently allocated in shared backend. // Ball requests do not carry explicit shared/private info, so they are routed by this table. @@ -61,28 +68,27 @@ class MemBackend(val b: GlobalConfig) extends Module { } } - // Per-channel request routing: is_shared=0 -> private, is_shared=1 -> shared. + // Per-channel request routing: is_shared=0 -> private, is_shared=1 -> shared IO. // Route selection is latched at request fire to keep response demux stable. val readPending = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) val writePending = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) val readRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) val writeRouteShared = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(false.B))) - // Shared backend reserves channels for 4 harts; only hart-0 channels are currently wired. - val totalSharedChannels = b.memDomain.bankChannel * 4 - for (i <- 0 until totalSharedChannels) { - sharedBackend.io.mem_req(i).bank_id := 0.U - sharedBackend.io.mem_req(i).group_id := 0.U - sharedBackend.io.mem_req(i).is_shared := false.B - sharedBackend.io.mem_req(i).hart_id := 0.U - - sharedBackend.io.mem_req(i).read.req.valid := false.B - sharedBackend.io.mem_req(i).read.req.bits := DontCare - sharedBackend.io.mem_req(i).read.resp.ready := false.B - - sharedBackend.io.mem_req(i).write.req.valid := false.B - sharedBackend.io.mem_req(i).write.req.bits := DontCare - sharedBackend.io.mem_req(i).write.resp.ready := false.B + // Shared IO defaults + for (i <- 0 until b.memDomain.bankChannel) { + io.shared_mem_req(i).bank_id := 0.U + io.shared_mem_req(i).group_id := 0.U + io.shared_mem_req(i).is_shared := false.B + io.shared_mem_req(i).hart_id := 0.U + + io.shared_mem_req(i).read.req.valid := false.B + io.shared_mem_req(i).read.req.bits := DontCare + io.shared_mem_req(i).read.resp.ready := false.B + + io.shared_mem_req(i).write.req.valid := false.B + io.shared_mem_req(i).write.req.bits := DontCare + io.shared_mem_req(i).write.resp.ready := false.B } for (i <- 0 until b.memDomain.bankChannel) { @@ -123,59 +129,59 @@ class MemBackend(val b: GlobalConfig) extends Module { privateBackend.io.mem_req(i).group_id := io.mem_req(i).group_id privateBackend.io.mem_req(i).is_shared := useSharedReq privateBackend.io.mem_req(i).hart_id := io.mem_req(i).hart_id - sharedBackend.io.mem_req(i).bank_id := io.mem_req(i).bank_id - sharedBackend.io.mem_req(i).group_id := io.mem_req(i).group_id - sharedBackend.io.mem_req(i).is_shared := useSharedReq - sharedBackend.io.mem_req(i).hart_id := io.mem_req(i).hart_id + io.shared_mem_req(i).bank_id := io.mem_req(i).bank_id + io.shared_mem_req(i).group_id := io.mem_req(i).group_id + io.shared_mem_req(i).is_shared := useSharedReq + io.shared_mem_req(i).hart_id := io.mem_req(i).hart_id // Read request route privateBackend.io.mem_req(i).read.req.valid := io.mem_req(i).read.req.valid && !useSharedReq privateBackend.io.mem_req(i).read.req.bits := io.mem_req(i).read.req.bits - sharedBackend.io.mem_req(i).read.req.valid := io.mem_req(i).read.req.valid && useSharedReq - sharedBackend.io.mem_req(i).read.req.bits := io.mem_req(i).read.req.bits + io.shared_mem_req(i).read.req.valid := io.mem_req(i).read.req.valid && useSharedReq + io.shared_mem_req(i).read.req.bits := io.mem_req(i).read.req.bits io.mem_req(i).read.req.ready := Mux( useSharedReq, - sharedBackend.io.mem_req(i).read.req.ready, + io.shared_mem_req(i).read.req.ready, privateBackend.io.mem_req(i).read.req.ready ) // Write request route privateBackend.io.mem_req(i).write.req.valid := io.mem_req(i).write.req.valid && !useSharedReq privateBackend.io.mem_req(i).write.req.bits := io.mem_req(i).write.req.bits - sharedBackend.io.mem_req(i).write.req.valid := io.mem_req(i).write.req.valid && useSharedReq - sharedBackend.io.mem_req(i).write.req.bits := io.mem_req(i).write.req.bits + io.shared_mem_req(i).write.req.valid := io.mem_req(i).write.req.valid && useSharedReq + io.shared_mem_req(i).write.req.bits := io.mem_req(i).write.req.bits io.mem_req(i).write.req.ready := Mux( useSharedReq, - sharedBackend.io.mem_req(i).write.req.ready, + io.shared_mem_req(i).write.req.ready, privateBackend.io.mem_req(i).write.req.ready ) // Response ready route (selected by latched request route when pending). privateBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && !useSharedReadResp - sharedBackend.io.mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && useSharedReadResp + io.shared_mem_req(i).read.resp.ready := io.mem_req(i).read.resp.ready && useSharedReadResp privateBackend.io.mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && !useSharedWriteResp - sharedBackend.io.mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && useSharedWriteResp + io.shared_mem_req(i).write.resp.ready := io.mem_req(i).write.resp.ready && useSharedWriteResp // Response valid/bits mux back to midend. io.mem_req(i).read.resp.valid := Mux( useSharedReadResp, - sharedBackend.io.mem_req(i).read.resp.valid, + io.shared_mem_req(i).read.resp.valid, privateBackend.io.mem_req(i).read.resp.valid ) io.mem_req(i).read.resp.bits := Mux( useSharedReadResp, - sharedBackend.io.mem_req(i).read.resp.bits, + io.shared_mem_req(i).read.resp.bits, privateBackend.io.mem_req(i).read.resp.bits ) io.mem_req(i).write.resp.valid := Mux( useSharedWriteResp, - sharedBackend.io.mem_req(i).write.resp.valid, + io.shared_mem_req(i).write.resp.valid, privateBackend.io.mem_req(i).write.resp.valid ) io.mem_req(i).write.resp.bits := Mux( useSharedWriteResp, - sharedBackend.io.mem_req(i).write.resp.bits, + io.shared_mem_req(i).write.resp.bits, privateBackend.io.mem_req(i).write.resp.bits ) } diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index f80d20c2..ca329a81 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -7,24 +7,23 @@ import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadResp, SramWriteResp} object SharedMemLayout { - val AccPipePerHart: Int = 8 - val MaxHart: Int = 4 - val TotalAccPipe: Int = AccPipePerHart * MaxHart - - val BankPerHart: Int = 32 - val TotalBank: Int = BankPerHart * MaxHart + def bankPerHart(b: GlobalConfig): Int = b.memDomain.bankNum + def maxHart(b: GlobalConfig): Int = b.top.nCores + def totalBank(b: GlobalConfig): Int = bankPerHart(b) * maxHart(b) + def channelPerHart(b: GlobalConfig): Int = b.memDomain.bankChannel + def totalChannel(b: GlobalConfig): Int = channelPerHart(b) * maxHart(b) } class SharedMemReadReq(val b: GlobalConfig) extends Bundle { val hartid = UInt(b.core.xLen.W) - val pbank_id = UInt(log2Ceil(SharedMemLayout.TotalBank).W) + val pbank_id = UInt(log2Ceil(SharedMemLayout.totalBank(b)).W) val group_id = UInt(3.W) val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) } class SharedMemWriteReq(val b: GlobalConfig) extends Bundle { val hartid = UInt(b.core.xLen.W) - val pbank_id = UInt(log2Ceil(SharedMemLayout.TotalBank).W) + val pbank_id = UInt(log2Ceil(SharedMemLayout.totalBank(b)).W) val group_id = UInt(3.W) val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) val mask = Vec(b.memDomain.bankMaskLen, Bool()) @@ -46,7 +45,7 @@ class SharedMemWriteIO(val b: GlobalConfig) extends Bundle { class SharedMem(val b: GlobalConfig) extends Module { private val maskLen = b.memDomain.bankMaskLen private val maskElem = UInt((b.memDomain.bankWidth / maskLen).W) - private val totalBanks = SharedMemLayout.TotalBank + private val totalBanks = SharedMemLayout.totalBank(b) private val minSharedLines = totalBanks * b.memDomain.bankEntries require( diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index c05c6edf..dcae7e74 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -9,24 +9,15 @@ import framework.memdomain.backend.banks.SramBank import framework.memdomain.frontend.outside_channel.MemConfigerIO import framework.top.GlobalConfig -// class SharedArbReq(b: GlobalConfig) extends Bundle { -// val src_channel = UInt(log2Up(b.memDomain.bankChannel).W) -// val is_write = Bool() -// val hart_id = UInt(b.core.xLen.W) -// val pbank_id = UInt(log2Ceil(SharedMemLayout.TotalBank).W) -// val group_id = UInt(3.W) -// val addr = UInt(log2Ceil(b.memDomain.bankEntries).W) -// val mask = Vec(b.memDomain.bankMaskLen, Bool()) -// val data = UInt(b.memDomain.bankWidth.W) -// val wmode = Bool() -// } - @instantiable class SharedMemBackend(val b: GlobalConfig) extends Module { + private val nCores = b.top.nCores + private val totalBanks = SharedMemLayout.totalBank(b) + private val totalChannel = SharedMemLayout.totalChannel(b) @public val io = IO(new Bundle { - val mem_req = Vec(b.memDomain.bankChannel*4, Flipped(new MemRequestIO(b))) + val mem_req = Vec(totalChannel, Flipped(new MemRequestIO(b))) val config = Flipped(Decoupled(new MemConfigerIO(b))) // Query interface for frontend to get group count @@ -34,15 +25,11 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val query_group_count = Output(UInt(4.W)) }) - // Shared backend is sized for 4 harts, but currently only hart-0 channels are connected. - private val activeHartCount = 1 - private val activeChannelCount = b.memDomain.bankChannel * activeHartCount - - val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum*4)(Instantiate(new SramBank(b))) - val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel*4)(Instantiate(new AccPipe(b))) + val banks: Seq[Instance[SramBank]] = Seq.fill(totalBanks)(Instantiate(new SramBank(b))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(totalChannel)(Instantiate(new AccPipe(b))) // Per-channel memory trace DPI-C modules to avoid losing simultaneous events - val mtraces = Seq.fill(b.memDomain.bankChannel*4)(Module(new MTraceDPI)) + val mtraces = Seq.fill(totalChannel)(Module(new MTraceDPI)) for (mt <- mtraces) { mt.io.is_write := 0.U mt.io.is_shared := 0.U @@ -60,7 +47,6 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { // Mapping table // ----------------------------------------------------------------------------- class MappingTableEntry extends Bundle { - val valid = Bool() val hart_id = UInt(b.core.xLen.W) val vbank_id = UInt(5.W) @@ -68,7 +54,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val group_id = UInt(3.W) } - val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum*4)(0.U.asTypeOf(new MappingTableEntry)))) + val mappingTable = RegInit(VecInit(Seq.fill(totalBanks)(0.U.asTypeOf(new MappingTableEntry)))) def isAcc(hart_id: UInt, vbank_id: UInt): Bool = mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && (entry.hart_id === hart_id) && entry.is_multi).reduce(_ || _) @@ -89,7 +75,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { } def deleteEntry(hart_id: UInt, vbank_id: UInt): Unit = { - for (i <- 0 until b.memDomain.bankNum*4) { + for (i <- 0 until totalBanks) { when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id && mappingTable(i).hart_id === hart_id) { mappingTable(i).valid := false.B mappingTable(i).vbank_id := 0.U @@ -108,7 +94,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { // Default Value // ----------------------------------------------------------------------------- - for (i <- 0 until b.memDomain.bankChannel*4) { + for (i <- 0 until totalChannel) { accPipes(i).io.mem_req.write <> io.mem_req(i).write accPipes(i).io.mem_req.read <> io.mem_req(i).read accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id @@ -188,7 +174,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { mtraces(ch).io.enable := en } - for (i <- 0 until activeChannelCount) { + for (i <- 0 until totalChannel) { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid // Memory trace: read request @@ -208,7 +194,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { ) } - for (j <- 0 until b.memDomain.bankNum*4) { + for (j <- 0 until totalBanks) { val hit_bank = mappingTable(j).valid && (mappingTable(j).hart_id === io.mem_req(i).hart_id) && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && diff --git a/arch/src/main/scala/framework/top/configs/TopConfig.scala b/arch/src/main/scala/framework/top/configs/TopConfig.scala index cbb493f4..3f448654 100644 --- a/arch/src/main/scala/framework/top/configs/TopConfig.scala +++ b/arch/src/main/scala/framework/top/configs/TopConfig.scala @@ -4,7 +4,8 @@ import upickle.default._ case class TopConfig( ballMemChannelNum: Int, - memBallChannelNum: Int) + memBallChannelNum: Int, + nCores: Int) object TopConfig { implicit val rw: ReadWriter[TopConfig] = macroRW diff --git a/arch/src/main/scala/framework/top/configs/default.json b/arch/src/main/scala/framework/top/configs/default.json index a5888670..cbb6925a 100644 --- a/arch/src/main/scala/framework/top/configs/default.json +++ b/arch/src/main/scala/framework/top/configs/default.json @@ -1,4 +1,5 @@ { "ballMemChannelNum": 6, - "memBallChannelNum": 6 + "memBallChannelNum": 6, + "nCores": 1 } diff --git a/arch/src/main/scala/sims/palladium/TargetConfigs.scala b/arch/src/main/scala/sims/palladium/TargetConfigs.scala index 450519d1..52da638a 100644 --- a/arch/src/main/scala/sims/palladium/TargetConfigs.scala +++ b/arch/src/main/scala/sims/palladium/TargetConfigs.scala @@ -3,17 +3,17 @@ package sims.palladium import org.chipsalliance.cde.config.Config import chipyard._ -class BuckyballToyP2EConfig - extends Config( - new palladium.fpga.WithFPGAFrequency(50) ++ - new palladium.fpga.WithVCU19PTweaks ++ - new examples.toy.BuckyballToy256Config // Test with 256 cores + 8 L2 banks - ) +// class BuckyballToyP2EConfig +// extends Config( +// new palladium.fpga.WithFPGAFrequency(50) ++ +// new palladium.fpga.WithVCU19PTweaks ++ +// new examples.toy.BuckyballToy256Config // Test with 256 cores + 8 L2 banks +// ) -// Cross-bar config -class BuckyballToyP2ECBConfig - extends Config( - new palladium.fpga.WithFPGAFrequency(50) ++ - new palladium.fpga.WithVCU19PTweaks ++ - new examples.toy.BuckyballToy256CBConfig - ) +// // Cross-bar config +// class BuckyballToyP2ECBConfig +// extends Config( +// new palladium.fpga.WithFPGAFrequency(50) ++ +// new palladium.fpga.WithVCU19PTweaks ++ +// new examples.toy.BuckyballToy256CBConfig +// ) diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala new file mode 100644 index 00000000..d3f751f4 --- /dev/null +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -0,0 +1,125 @@ +package sims.pegasus + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config.{Parameters} +import freechips.rocketchip.util.{ResetCatchAndSync} + +import chipyard.harness.{HasHarnessInstantiators} +import chipyard.iobinders.{AXI4MemPort} + +import pegasus._ + +// PegasusHarness: top-level Chisel Module for AU280 FPGA. +// Integrates PegasusShell (FPGA IPs) with ChipTop (SoC DUT) via Chipyard +// harness infrastructure. +// +// PCIe and HBM2 reference clock pins are the top-level IOs. +// ChipTop is instantiated inside via instantiateChipTops(). +// HarnessBinders connect ChipTop's exposed ports (AXI4MemPort, UARTPort, etc.) +// to pegasusShell's interface signals. +// +class PegasusHarness(implicit val p: Parameters) + extends Module + with HasHarnessInstantiators { + + val io = IO(new Bundle { + // PCIe physical interface + val pcie_sys_clk = Input(Clock()) + val pcie_sys_clk_gt = Input(Clock()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) + + // HBM2 reference clock (100 MHz) + val hbm_ref_clk = Input(Clock()) + }) + + // --- Instantiate PegasusShell --- + val pegasusShell = Module(new PegasusShell) + pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk + pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt + pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n + io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp + io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn + pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp + pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn + pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk + + // UART TX: default idle high until ChipTop provides real signal + pegasusShell.io.uart_tx := true.B + + // Chip mem: tie off until ChipTop provides real signals + pegasusShell.io.chip_mem_awid := 0.U + pegasusShell.io.chip_mem_awaddr := 0.U + pegasusShell.io.chip_mem_awlen := 0.U + pegasusShell.io.chip_mem_awsize := 0.U + pegasusShell.io.chip_mem_awburst := 0.U + pegasusShell.io.chip_mem_awvalid := false.B + pegasusShell.io.chip_mem_wdata := 0.U + pegasusShell.io.chip_mem_wstrb := 0.U + pegasusShell.io.chip_mem_wlast := false.B + pegasusShell.io.chip_mem_wvalid := false.B + pegasusShell.io.chip_mem_bready := false.B + pegasusShell.io.chip_mem_arid := 0.U + pegasusShell.io.chip_mem_araddr := 0.U + pegasusShell.io.chip_mem_arlen := 0.U + pegasusShell.io.chip_mem_arsize := 0.U + pegasusShell.io.chip_mem_arburst := 0.U + pegasusShell.io.chip_mem_arvalid := false.B + pegasusShell.io.chip_mem_rready := false.B + + // --- HasHarnessInstantiators required interface --- + def referenceClockFreqMHz: Double = 200.0 + def referenceClock: Clock = pegasusShell.io.dut_clk + def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset + + val success = WireInit(false.B) + + // --- Instantiate ChipTop and apply HarnessBinders --- + // HarnessBinders for UART and AXI4Mem will override the defaults above + // by calling connectChipMem() and driving pegasusShell.io.uart_tx + val lazyDuts = instantiateChipTops() + + // Called by WithPegasusAXIMem HarnessBinder to connect ChipTop ExtMem AXI4 + def connectChipMem(port: AXI4MemPort): Unit = { + val axi = port.io.bits + // Write address channel + pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(6.W)) + pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(33.W)) + pegasusShell.io.chip_mem_awlen := axi.aw.bits.len + pegasusShell.io.chip_mem_awsize := axi.aw.bits.size + pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst + pegasusShell.io.chip_mem_awvalid := axi.aw.valid + axi.aw.ready := pegasusShell.io.chip_mem_awready + // Write data channel + pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(256.W)) + pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(32.W)) + pegasusShell.io.chip_mem_wlast := axi.w.bits.last + pegasusShell.io.chip_mem_wvalid := axi.w.valid + axi.w.ready := pegasusShell.io.chip_mem_wready + // Write response channel + axi.b.bits.id := pegasusShell.io.chip_mem_bid.asTypeOf(axi.b.bits.id) + axi.b.bits.resp := pegasusShell.io.chip_mem_bresp + axi.b.valid := pegasusShell.io.chip_mem_bvalid + pegasusShell.io.chip_mem_bready := axi.b.ready + // Read address channel + pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(6.W)) + pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(33.W)) + pegasusShell.io.chip_mem_arlen := axi.ar.bits.len + pegasusShell.io.chip_mem_arsize := axi.ar.bits.size + pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst + pegasusShell.io.chip_mem_arvalid := axi.ar.valid + axi.ar.ready := pegasusShell.io.chip_mem_arready + // Read data channel + axi.r.bits.id := pegasusShell.io.chip_mem_rid.asTypeOf(axi.r.bits.id) + axi.r.bits.data := pegasusShell.io.chip_mem_rdata.asTypeOf(axi.r.bits.data) + axi.r.bits.resp := pegasusShell.io.chip_mem_rresp + axi.r.bits.last := pegasusShell.io.chip_mem_rlast + axi.r.valid := pegasusShell.io.chip_mem_rvalid + pegasusShell.io.chip_mem_rready := axi.r.ready + } +} diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala new file mode 100644 index 00000000..7bc548ba --- /dev/null +++ b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala @@ -0,0 +1,68 @@ +package sims.pegasus + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config.{Config} + +import chipyard.harness._ +import chipyard.iobinders._ + +import pegasus._ + +// HarnessBinder: connect ChipTop ExtMem AXI4 port to PegasusShell chip_mem interface +// Replaces WithBlackBoxSimMem (Verilator simulation DRAM model) +class WithPegasusAXIMem extends HarnessBinder({ + case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => { + th.connectChipMem(port) + } +}) + +// HarnessBinder: connect ChipTop UART TX to PegasusShell (goes to UARTCapture) +// Replaces WithUARTAdapter (Verilator stdout adapter) +class WithPegasusUART extends HarnessBinder({ + case (th: PegasusHarness, port: UARTPort, chipId: Int) => { + th.pegasusShell.io.uart_tx := port.io.txd + port.io.rxd := true.B // UART RX idle high (no input from host) + } +}) + +// Tie off JTAG (not used on FPGA; debug via GDB/OpenOCD over UART is possible but not in scope) +class WithPegasusTiedOffJTAG extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => { + port.io.TCK := true.B.asClock + port.io.TMS := true.B + port.io.TDI := true.B + } +}) + +// Tie off DMI (no simulation-side debug model needed on FPGA) +class WithPegasusTiedOffDMI extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => { + port.io.dmi.req.valid := false.B + port.io.dmi.req.bits := DontCare + port.io.dmi.resp.ready := true.B + port.io.dmiClock := false.B.asClock + port.io.dmiReset := true.B + } +}) + +// Aggregate config fragment: select PegasusHarness binders +// and override Verilator-only simulation models +class WithPegasusHarness extends Config( + new WithPegasusAXIMem ++ + new WithPegasusUART ++ + new WithPegasusTiedOffJTAG ++ + new WithPegasusTiedOffDMI ++ + // Standard binders that are safe to keep on FPGA + new chipyard.harness.WithTieOffInterrupts ++ + new chipyard.harness.WithTieOffL2FBusAXI ++ + new chipyard.harness.WithGPIOTiedOff ++ + new chipyard.harness.WithGPIOPinsTiedOff ++ + new chipyard.harness.WithDriveChipIdPin ++ + new chipyard.harness.WithCustomBootPinPlusArg ++ + new chipyard.harness.WithSerialTLTiedOff ++ + new chipyard.harness.WithClockFromHarness ++ + new chipyard.harness.WithResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator +) diff --git a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala new file mode 100644 index 00000000..63a14008 --- /dev/null +++ b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala @@ -0,0 +1,45 @@ +package sims.pegasus + +import chisel3._ +import _root_.circt.stage.ChiselStage +import org.chipsalliance.cde.config.Config + +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} +import freechips.rocketchip.subsystem.InSubsystem + +// import pegasus.{PegasusHarness, WithPegasusHarness} + +// BootROM for FPGA (points to the same bootrom image as the Verilator target) +class WithPegasusBootROM + extends Config((site, here, up) => { + case BootROMLocated(InSubsystem) => Some(BootROMParams( + contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" + )) + }) + +// PegasusBuckyballToyConfig: Buckyball Toy SoC on AU280 FPGA +// +// Target clock: 200 MHz. If timing closure yields a different Fmax, +// update all WithXxxBusFrequency values and re-elaborate so the DTB +// gets the correct UART baud divisor (otherwise UART output will be garbled). +class PegasusBuckyballToyConfig extends Config( + new WithPegasusHarness ++ + new WithPegasusBootROM ++ + new chipyard.config.WithSystemBusFrequency(200.0) ++ + new chipyard.config.WithMemoryBusFrequency(200.0) ++ + new chipyard.config.WithPeripheryBusFrequency(200.0) ++ + new chipyard.config.WithControlBusFrequency(200.0) ++ + new chipyard.config.WithFrontBusFrequency(200.0) ++ + new chipyard.config.WithOffchipBusFrequency(200.0) ++ + new examples.toy.BuckyballToyConfig +) + +// Elaborate entry point: generate SystemVerilog for PegasusHarness +// Usage: mill pegasus.runMain sims.pegasus.ElaboratePegasus [firtool options] +object ElaboratePegasus extends App { + ChiselStage.emitSystemVerilogFile( + new PegasusHarness()(new PegasusBuckyballToyConfig().toInstance), + firtoolOpts = args, + args = Array.empty + ) +} diff --git a/arch/src/main/scala/sims/verilator/BBSimHarness.scala b/arch/src/main/scala/sims/verilator/BBSimHarness.scala new file mode 100644 index 00000000..c8b20ec5 --- /dev/null +++ b/arch/src/main/scala/sims/verilator/BBSimHarness.scala @@ -0,0 +1,146 @@ +package sims.verilator + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config.{Config, Parameters} +import freechips.rocketchip.subsystem.WithDefaultMMIOPort + +import chipyard.harness.{HasHarnessInstantiators, HarnessBinder} +import chipyard.iobinders.{AXI4MMIOPort, UARTPort} + +// ============================================================================= +// WithBBSimMMIO: wire AXI4 MMIO port. +// +// All registers are created inside withClockAndReset(port.io.clock, ...) so +// they run in the same clock domain as the AXI4Buffer B-FIFO inside chiptop0. +// The AXI4MMIOPort uses ClockedIO, so port.io.clock is the SoC clock (1 GHz), +// not the harnessBinderClock (100 MHz) that plain RegInit would use here. +// +// AW/W/B/AR/R are handled entirely in RTL registers (no SimMMIOSlave needed). +// ============================================================================= +class WithBBSimMMIO extends HarnessBinder({ + case (th: BBSimHarness, port: AXI4MMIOPort, chipId: Int) => { + // Use the harness clock (1 GHz) for all registers so they are in the + // same domain as C++ mmio_tick() and no cross-domain issues arise. + // The AXI4Buffer inside chiptop0 runs on its own clock; the port signals + // are async from the harness perspective, but in Verilator simulation + // everything is single-threaded so there is no real metastability risk. + withClockAndReset(th.clock, th.reset) { + val addrBits = port.io.bits.aw.bits.addr.getWidth + val idBits = port.io.bits.aw.bits.id.getWidth + + val sIdle :: sGotAW :: Nil = Enum(2) + val state = RegInit(sIdle) + val latchedAddr = Reg(UInt(addrBits.W)) + val latchedId = Reg(UInt(idBits.W)) + val bPending = RegInit(false.B) + val bId = Reg(UInt(idBits.W)) + + // --- AW channel --- + port.io.bits.aw.ready := (state === sIdle) + when(state === sIdle && port.io.bits.aw.valid) { + latchedAddr := port.io.bits.aw.bits.addr + latchedId := port.io.bits.aw.bits.id + state := sGotAW + } + + // --- W channel --- + port.io.bits.w.ready := (state === sGotAW) + val wFire = (state === sGotAW) && port.io.bits.w.valid + val latchedData = RegEnable(port.io.bits.w.bits.data, wFire) + when(wFire) { + state := sIdle + bPending := true.B + bId := latchedId + } + + // --- B channel --- + when(port.io.bits.b.valid && port.io.bits.b.ready) { + bPending := false.B + } + port.io.bits.b.valid := bPending + port.io.bits.b.bits.id := bId + port.io.bits.b.bits.resp := 0.U + + // --- Expose fire for C++ mmio_tick() --- + // All registers run at harness clock (1 GHz) = C++ sampling rate. + // wFire is high for exactly 1 cycle (W accept), so no de-bounce needed. + th.io.mmio_fire := wFire + th.io.mmio_fire_addr := latchedAddr + th.io.mmio_fire_data := port.io.bits.w.bits.data + + // --- AR channel: accept immediately, return 0 next cycle --- + port.io.bits.ar.ready := true.B + val rValid = RegNext(port.io.bits.ar.valid, false.B) + val rId = RegNext(port.io.bits.ar.bits.id) + port.io.bits.r.valid := rValid + port.io.bits.r.bits.data := 0.U + port.io.bits.r.bits.resp := 0.U + port.io.bits.r.bits.last := true.B + port.io.bits.r.bits.id := rId + } + } +}) + +// ============================================================================= +// WithNoUARTAdapter: suppress UARTAdapter; tie RX high (idle line) +// ============================================================================= +class WithNoUARTAdapter extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => { + port.io.rxd := true.B + } +}) + +// ============================================================================= +// BBSimConfig +// ============================================================================= +class BBSimConfig extends Config( + new WithNoUARTAdapter ++ + new WithBBSimMMIO ++ + new WithDefaultMMIOPort ++ + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithSerialTLTiedOff ++ + new chipyard.harness.WithTieOffInterrupts ++ + new chipyard.harness.WithGPIOTiedOff ++ + new chipyard.harness.WithTieOffL2FBusAXI ++ + new chipyard.harness.WithClockFromHarness ++ + new chipyard.harness.WithResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ + new chipyard.iobinders.WithNMITiedOff +) + +class BuckyballToyBBSimConfig extends Config( + new BBSimConfig ++ + new WithCustomBootROM ++ + new examples.toy.BuckyballToyConfig +) + +// ============================================================================= +// BBSimHarness +// ============================================================================= +class BBSimHarness(implicit val p: Parameters) + extends Module + with HasHarnessInstantiators { + + val io = IO(new Bundle { + val mmio_fire = Output(Bool()) + val mmio_fire_addr = Output(UInt(32.W)) + val mmio_fire_data = Output(UInt(64.W)) + }) + + // Defaults; WithBBSimMMIO binder overrides these. + io.mmio_fire := false.B + io.mmio_fire_addr := 0.U + io.mmio_fire_data := 0.U + + def referenceClockFreqMHz: Double = 1000.0 + def referenceClock: Clock = clock + def referenceReset: Reset = reset + + val success = WireInit(false.B) + + val lazyDuts = instantiateChipTops() +} diff --git a/arch/src/main/scala/sims/verilator/TargetConfig.scala b/arch/src/main/scala/sims/verilator/TargetConfig.scala index e103c4a0..b364724e 100644 --- a/arch/src/main/scala/sims/verilator/TargetConfig.scala +++ b/arch/src/main/scala/sims/verilator/TargetConfig.scala @@ -20,6 +20,12 @@ class BuckyballToyVerilatorConfig new examples.toy.BuckyballToyConfig ) +class BuckyballGobanVerilatorConfig + extends Config( + new WithCustomBootROM ++ + new examples.goban.BuckyballGobanConfig + ) + class BuckyballGemminiVerilatorConfig extends Config( new WithCustomBootROM ++ @@ -57,3 +63,37 @@ object Elaborate extends App { args = Array.empty ) } + +// BBSimElaborate: elaborates BBSimHarness instead of TestHarness. +// Used for bdb-based simulation (no fesvr, ELF loaded via libelf). +// Usage: BBSimElaborate sims.verilator.BuckyballToyBBSimConfig [firtool-opts...] +object BBSimElaborate extends App { + if (args.isEmpty) { + println("Usage: BBSimElaborate [firtool-opts...]") + println("Example: BBSimElaborate sims.verilator.BuckyballToyBBSimConfig") + sys.exit(1) + } + + val configClassName = args(0) + println(s"Elaborating BBSimHarness with config: $configClassName") + + val config: Config = + try { + val configClass = Class.forName(configClassName) + configClass.getDeclaredConstructor().newInstance().asInstanceOf[Config] + } catch { + case e: ClassNotFoundException => + println(s"Error: Config class not found: $configClassName") + sys.exit(1) + case e: Exception => + println(s"Error loading config class: ${e.getMessage}") + e.printStackTrace() + sys.exit(1) + } + + ChiselStage.emitSystemVerilogFile( + new BBSimHarness()(config.toInstance), + firtoolOpts = args.drop(1), + args = Array.empty + ) +} diff --git a/bb-tests/workloads/CMakeLists.txt b/bb-tests/workloads/CMakeLists.txt index 8f4e3d0d..25e5d91e 100644 --- a/bb-tests/workloads/CMakeLists.txt +++ b/bb-tests/workloads/CMakeLists.txt @@ -71,6 +71,7 @@ add_dependencies(sync-bin buckyball-gemmini-build buckyball-rvv-build OpTest-all + buckyball-goban-CTest-build ) add_custom_target(build-all ALL diff --git a/bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c b/bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c new file mode 100644 index 00000000..a3694757 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c @@ -0,0 +1,33 @@ +#ifndef _BDB_COUNTER_H_ +#define _BDB_COUNTER_H_ + +#include "isa.h" + +#define BDB_COUNTER_FUNC7 48 + +// subcmd values +#define BDB_CTR_START 0 +#define BDB_CTR_STOP 1 +#define BDB_CTR_READ 2 + +// rs2 layout: [3:0]=subcmd, [7:4]=ctr_id, [63:8]=payload +#define BDB_CTR_RS2(subcmd, ctr_id, payload) \ + (((unsigned long long)(payload) << 8) | (((ctr_id)&0xF) << 4) | \ + ((subcmd)&0xF)) + +// Start counter ctr_id with user tag +#define bdb_counter_start(ctr_id, tag) \ + BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_START, ctr_id, tag), \ + BDB_COUNTER_FUNC7) + +// Stop counter ctr_id, output elapsed to trace +#define bdb_counter_stop(ctr_id) \ + BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_STOP, ctr_id, 0), \ + BDB_COUNTER_FUNC7) + +// Read counter ctr_id current value (non-destructive), output to trace +#define bdb_counter_read(ctr_id) \ + BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_READ, ctr_id, 0), \ + BDB_COUNTER_FUNC7) + +#endif // _BDB_COUNTER_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c b/bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c new file mode 100644 index 00000000..d19e867a --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c @@ -0,0 +1,26 @@ +#ifndef _BDB_BACKDOOR_H_ +#define _BDB_BACKDOOR_H_ + +#include "isa.h" + +#define BDB_BACKDOOR_FUNC7 49 + +// Backdoor write: DPI-C provides data, write to external bank +// bank_id = target bank, iter = number of rows +#define bdb_backdoor_write(bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK2(bank_id) | BB_WR | BB_ITER(iter)), 0, BDB_BACKDOOR_FUNC7) + +// Backdoor read: read from external bank, output via DPI-C +// bank_id = source bank, iter = number of rows +#define bdb_backdoor_read(bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_RD0 | BB_ITER(iter)), 0, BDB_BACKDOOR_FUNC7) + +// Backdoor peek: read single row from external bank +#define bdb_backdoor_peek(bank_id, row_count) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_RD0 | BB_ITER(row_count)), 0, \ + BDB_BACKDOOR_FUNC7) + +#endif // _BDB_BACKDOOR_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/50_barrier.c b/bb-tests/workloads/lib/bbhw/isa/50_barrier.c new file mode 100644 index 00000000..2768897c --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/50_barrier.c @@ -0,0 +1,22 @@ +#ifndef _BB_BARRIER_H_ +#define _BB_BARRIER_H_ + +#include "isa.h" + +#define BB_BARRIER_FUNC7 50 + +/** + * bb_barrier() - hardware multi-core barrier synchronization. + * + * Semantics: + * 1. Waits for this core's own instruction ROB to drain (implicit fence). + * 2. Signals arrive to the tile-level BarrierUnit. + * 3. Stalls until all nCores cores have arrived (hardware all-reduce). + * + * All cores in the same BBTile must call bb_barrier() at the same point. + * Mixing bb_barrier() with bb_fence() within the same barrier epoch is + * undefined behaviour. + */ +#define bb_barrier() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_BARRIER_FUNC7) + +#endif // _BB_BARRIER_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index fd61d654..07afc1c1 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -59,5 +59,8 @@ typedef int32_t result_t; #include "44_gemmini_compute_preloaded.c" #include "45_gemmini_compute_accumulated.c" #include "46_gemmini_flush.c" +#include "48_bdb_counter.c" +#include "49_bdb_backdoor.c" +#include "50_barrier.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/src/CTest/CMakeLists.txt b/bb-tests/workloads/src/CTest/CMakeLists.txt index 926585cb..ff477d4f 100644 --- a/bb-tests/workloads/src/CTest/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/CMakeLists.txt @@ -7,3 +7,4 @@ add_subdirectory(gemmini) add_subdirectory(toy) add_subdirectory(rvv) add_subdirectory(bebop) +add_subdirectory(goban) diff --git a/bb-tests/workloads/src/CTest/goban/CMakeLists.txt b/bb-tests/workloads/src/CTest/goban/CMakeLists.txt new file mode 100644 index 00000000..08126947 --- /dev/null +++ b/bb-tests/workloads/src/CTest/goban/CMakeLists.txt @@ -0,0 +1,55 @@ +set(ELF_CC "riscv64-unknown-elf-gcc") + +#------------------------------------------------------------------------------- +# Goban: multi-core (SPMD) baremetal workloads +# All cores run the ELF simultaneously; divergence is by mhartid. +#------------------------------------------------------------------------------- +set(CTEST_GOBAN_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/goban) + +set(GOBAN_C_FLAGS + -g -fno-common -O2 -static + -march=rv64gc -mcmodel=medany + -fno-builtin-printf + -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} + -I${WORKLOAD_LIB_DIR} + -I${CTEST_GOBAN_WORKLOAD_DIR} +) + +# Generate a multicore baremetal ELF. +# start.S (goban version) launches all harts into main(). +function(add_goban_test_target TEST_NAME SOURCE_FILE) + set(EXECUTABLE "${TEST_NAME}_multicore-baremetal") + + add_custom_command( + OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} + COMMAND ${ELF_CC} ${GOBAN_C_FLAGS} + -o ${EXECUTABLE} + ${CTEST_GOBAN_WORKLOAD_DIR}/start.S + ${CTEST_GOBAN_WORKLOAD_DIR}/${SOURCE_FILE} + DEPENDS + ${CTEST_GOBAN_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_GOBAN_WORKLOAD_DIR}/start.S + COMMENT "Building goban multicore baremetal: ${EXECUTABLE}" + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + + add_custom_target(${TEST_NAME} + DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} + COMMENT "Building ${TEST_NAME}" + ) +endfunction() + +#------------------------------------------------------------------------------- +# Build list +#------------------------------------------------------------------------------- +add_goban_test_target(ctest_goban_barrier_test barrier_test.c) +add_goban_test_target(ctest_goban_barrier_mvin_test barrier_mvin_test.c) + +# Master build target +add_custom_target(buckyball-goban-CTest-build ALL + DEPENDS + ctest_goban_barrier_test + ctest_goban_barrier_mvin_test + COMMENT "Building all Goban workloads" + VERBATIM +) diff --git a/bb-tests/workloads/src/CTest/goban/barrier_mvin_test.c b/bb-tests/workloads/src/CTest/goban/barrier_mvin_test.c new file mode 100644 index 00000000..d67fe3f7 --- /dev/null +++ b/bb-tests/workloads/src/CTest/goban/barrier_mvin_test.c @@ -0,0 +1,83 @@ +/* + * barrier_mvin_test.c — Goban multi-core parallel mvin/mvout + barrier test. + * + * SPMD: all 4 cores run this program simultaneously. + * + * Each core: + * 1. Allocates its own private bank (bank = cid). + * 2. Fills the bank with a core-specific pattern (mvin). + * 3. Reads it back (mvout) and verifies locally. + * 4. Calls bb_barrier() — waits for all cores. + * 5. Records a "done" flag in shared memory. + * 6. Core 0 prints the summary. + * + * This test exercises: + * - Per-core private-bank mvin/mvout (no sharing needed) + * - bb_barrier() synchronization across all 4 cores + * - Parallel hardware accelerator utilization + */ + +#include "goban.h" +#include +#include + +#define DIM 16 +#define NCORES 4 + +/* Per-core scratchpad buffers — compiler places these in BSS (all harts share + the same virtual address space, but each core writes its own slot). */ +static elem_t src[NCORES][DIM * DIM] __attribute__((aligned(128))); +static elem_t dst[NCORES][DIM * DIM] __attribute__((aligned(128))); +static volatile int core_ok[NCORES]; + +int main(void) { + int cid = bb_get_core_id(); + + printf("[core %d] starting mvin/mvout\n", cid); + + /* ---- Step 1: fill src with a core-specific pattern ---- */ + elem_t pat = (elem_t)(cid + 1); /* core 0 → 1, core 1 → 2, … */ + for (int i = 0; i < DIM * DIM; i++) { + src[cid][i] = pat; + } + + /* ---- Step 2: mvin → shared bank ---- */ + int bank = cid; /* each core uses its own bank, no conflict */ + bb_mem_alloc(bank, 1, 1); + bb_mvin((uintptr_t)src[cid], bank, DIM, 1); + + /* ---- Step 3: mvout → dst ---- */ + memset(dst[cid], 0, sizeof(dst[cid])); + bb_mvout((uintptr_t)dst[cid], bank, DIM, 1); + bb_mem_release(bank); + + /* ---- Step 4: verify locally ---- */ + int ok = 1; + for (int i = 0; i < DIM * DIM; i++) { + if (dst[cid][i] != pat) { + printf("[core %d] ERROR at [%d]: got %d, expected %d\n", + cid, i, (int)dst[cid][i], (int)pat); + ok = 0; + break; + } + } + core_ok[cid] = ok; + printf("[core %d] mvin/mvout %s\n", cid, ok ? "PASSED" : "FAILED"); + + /* ============ BARRIER: wait for all cores to finish ============ */ + bb_barrier(); + + /* ---- Step 5: core 0 collects results ---- */ + if (cid == 0) { + int all_ok = 1; + for (int i = 0; i < NCORES; i++) { + if (!core_ok[i]) { + all_ok = 0; + printf("[core 0] core %d reported FAILED\n", i); + } + } + printf("=== barrier_mvin_test %s ===\n", all_ok ? "PASSED" : "FAILED"); + } + + return core_ok[cid] ? 0 : 1; +} diff --git a/bb-tests/workloads/src/CTest/goban/barrier_test.c b/bb-tests/workloads/src/CTest/goban/barrier_test.c new file mode 100644 index 00000000..c10dfd60 --- /dev/null +++ b/bb-tests/workloads/src/CTest/goban/barrier_test.c @@ -0,0 +1,66 @@ +/* + * barrier_test.c — Goban multi-core barrier smoke test. + * + * All nCores harts run this program concurrently (SPMD). + * Test plan: + * 1. Each core records a "before" cycle count. + * 2. All cores execute bb_barrier() — hardware stalls until everyone arrives. + * 3. Each core records an "after" cycle count. + * 4. Core 0 prints a summary; all cores reach the final printf. + * + * Correctness criterion: if the simulation does not hang and all cores print + * their completion message, the barrier works. + */ + +#include "goban.h" +#include + +/* Shared flag written by each core after the barrier to verify ordering. */ +static volatile int arrived[4] = {0, 0, 0, 0}; + +int main(void) { + int cid = bb_get_core_id(); + + printf("[core %d] starting\n", cid); + + /* --- Phase 1: mark arrival before barrier --- */ + arrived[cid] = 1; + + /* ============ BARRIER 1 ============ */ + bb_barrier(); + + /* --- Phase 2: all cores should see every arrival flag set --- */ + int ok = 1; + for (int i = 0; i < 4; i++) { + if (!arrived[i]) { + printf("[core %d] ERROR: arrived[%d] not set after barrier!\n", cid, i); + ok = 0; + } + } + + if (ok) { + printf("[core %d] after barrier: all arrival flags set — PASSED\n", cid); + } + + /* ============ BARRIER 2 ============ */ + /* Verify barrier can be used more than once in the same program. */ + arrived[cid] = 2; + bb_barrier(); + + for (int i = 0; i < 4; i++) { + if (arrived[i] != 2) { + printf("[core %d] ERROR: arrived[%d] != 2 after barrier 2!\n", cid, i); + ok = 0; + } + } + + if (ok) { + printf("[core %d] barrier 2 PASSED\n", cid); + } + + if (cid == 0) { + printf("=== barrier_test %s ===\n", ok ? "PASSED" : "FAILED"); + } + + return ok ? 0 : 1; +} diff --git a/bb-tests/workloads/src/CTest/goban/goban.h b/bb-tests/workloads/src/CTest/goban/goban.h new file mode 100644 index 00000000..45f40bb8 --- /dev/null +++ b/bb-tests/workloads/src/CTest/goban/goban.h @@ -0,0 +1,14 @@ +#ifndef GOBAN_H +#define GOBAN_H + +#include +#include + +/* Read hart ID from CSR mhartid */ +static inline int bb_get_core_id(void) { + int hartid; + asm volatile("csrr %0, mhartid" : "=r"(hartid)); + return hartid; +} + +#endif // GOBAN_H diff --git a/bb-tests/workloads/src/CTest/goban/start.S b/bb-tests/workloads/src/CTest/goban/start.S new file mode 100644 index 00000000..63e67e71 --- /dev/null +++ b/bb-tests/workloads/src/CTest/goban/start.S @@ -0,0 +1,21 @@ +# Multi-core SPMD startup for Goban (nCores=4 by default). +# All harts jump to main(); divergence is done via mhartid inside main(). +# Stack layout: base = 0x80020000, each hart gets 4 KB downward. + +.section .text.init +.global _start + +_start: + csrr t0, mhartid # t0 = hart id + + # Stack per hart: base - hartid * 0x1000 + li sp, 0x80020000 + li t1, 0x1000 + mul t1, t0, t1 + sub sp, sp, t1 + + call main + +.align 12 +stack_space: + .space 0x8000 # 32 KB total stack space (8 harts × 4 KB) diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 6a6ab687..292ffaf5 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -4,8 +4,10 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") #------------------------------------------------------------------------------- # Set baremetal compilation flags #------------------------------------------------------------------------------- +set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} -I${CTEST_TOY_WORKLOAD_DIR}) + -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles + -Wl,-T,${BBSIM_LD} -I${CTEST_TOY_WORKLOAD_DIR}) #------------------------------------------------------------------------------- # Define common compilation step functions @@ -56,10 +58,12 @@ function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} + ${CTEST_TOY_WORKLOAD_DIR}/crt0.S ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} DEPENDS ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_TOY_WORKLOAD_DIR}/crt0.S ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} @@ -120,6 +124,8 @@ add_cross_platform_test_target(ctest_quant_test quant_test.c) add_cross_platform_test_target(ctest_dequant_test dequant_test.c) add_cross_platform_test_target(ctest_gemmini_matmul_test gemmini_matmul_test.c) add_cross_platform_test_target(ctest_tlb_test tlb_test.c) +add_cross_platform_test_target(ctest_bdb_counter_test bdb_counter_test.c) +add_cross_platform_test_target(ctest_bdb_backdoor_test bdb_backdoor_test.c) # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS @@ -149,5 +155,7 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_dequant_test ctest_gemmini_matmul_test ctest_tlb_test + ctest_bdb_counter_test + ctest_bdb_backdoor_test COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/bbsim.ld b/bb-tests/workloads/src/CTest/toy/bbsim.ld new file mode 100644 index 00000000..a88bf712 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/bbsim.ld @@ -0,0 +1,38 @@ +/* bbsim.ld — baremetal linker script for BBSimHarness (DRAM at 0x8000_0000) */ +/* Bootrom jumps directly to 0x80000000 (ELF entry), no _start needed. */ +OUTPUT_ARCH("riscv") +ENTRY(main) + +SECTIONS { + . = 0x80000000; + + .text : { + *(.text.init) /* crt0.S _start must be first */ + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } + + .rodata : { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + PROVIDE(_edata = .); + } + + .bss (NOLOAD) : { + PROVIDE(__bss_start = .); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + PROVIDE(__bss_end = .); + } + + . = ALIGN(16); + PROVIDE(end = .); + PROVIDE(_end = .); +} diff --git a/bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c b/bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c new file mode 100644 index 00000000..be04c941 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c @@ -0,0 +1,52 @@ +#include "buckyball.h" +#include +#include +#include +#include +#include + +// Test bdb_backdoor: SRAM backdoor write + read via DPI-C +// +// C++ side (ctrace.cc) generates test data: each 128-bit row is filled +// with (row*16 + byte_offset) & 0xFF pattern via generate_test_data(). +// +// Flow: +// 1. bdb_backdoor_write: C++ generates (row, data) per iteration via DPI-C, +// RTL writes to external bank 0 +// 2. bdb_backdoor_read: RTL reads bank 0, sends data back via DPI-C, +// C++ logs to bdb.log as [BANK-TRACE] +// 3. mvout + fence: verify data was actually written (no hang = pass) + +#define DIM 16 + +static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + // Build expected pattern (must match C++ generate_test_data): + // row i, byte j -> (i*16 + j) & 0xFF + + uint32_t bank_id = 0; + bb_mem_alloc(bank_id, 1, 1); + + // C++ injects DIM rows into bank 0 via DPI-C (data decided by C++) + bdb_backdoor_write(bank_id, DIM); + + // Dump bank 0 contents to bdb.log via DPI-C + bdb_backdoor_read(bank_id, DIM); + + // mvout to verify data integrity + clear_i8_matrix(output_matrix, DIM, DIM); + bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); + bb_fence(); + + printf("bdb_backdoor test PASSED\n"); + return 0; + +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/toy/bdb_counter_test.c b/bb-tests/workloads/src/CTest/toy/bdb_counter_test.c new file mode 100644 index 00000000..5acc8693 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/bdb_counter_test.c @@ -0,0 +1,65 @@ +#include "buckyball.h" +#include +#include +#include +#include +#include + +// Test bdb_counter: start/stop/read cycle counters +// Verification: if the instruction reaches TraceBall and completes without +// hanging, the test passes. The actual [CTRACE] output goes to bdb.log. + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== bdb_counter test ===\n"); + + // Test 1: basic start/stop on counter 0 + printf("Test 1: basic start/stop\n"); + bdb_counter_start(0, 0xA001); + // Do some work to burn cycles + volatile int x = 0; + for (int i = 0; i < 10; i++) x += i; + bdb_counter_stop(0); + printf("Test 1 PASSED\n"); + + // Test 2: read without stopping + printf("Test 2: start/read/stop\n"); + bdb_counter_start(1, 0xA002); + volatile int y = 0; + for (int i = 0; i < 5; i++) y += i; + bdb_counter_read(1); + bdb_counter_stop(1); + printf("Test 2 PASSED\n"); + + // Test 3: nested counters (two levels) + printf("Test 3: nested counters\n"); + bdb_counter_start(0, 0xB001); // outer + bdb_counter_start(1, 0xB002); // inner + volatile int z = 0; + for (int i = 0; i < 5; i++) z += i; + bdb_counter_stop(1); // inner done + bdb_counter_stop(0); // outer done + printf("Test 3 PASSED\n"); + + // Test 4: multiple independent counters + printf("Test 4: multiple counters\n"); + bdb_counter_start(0, 0xC000); + bdb_counter_start(1, 0xC001); + bdb_counter_start(2, 0xC002); + bdb_counter_start(3, 0xC003); + bdb_counter_stop(3); + bdb_counter_stop(2); + bdb_counter_stop(1); + bdb_counter_stop(0); + printf("Test 4 PASSED\n"); + + printf("bdb_counter test PASSED\n"); + return 0; + +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bb-tests/workloads/src/CTest/toy/buckyball.c b/bb-tests/workloads/src/CTest/toy/buckyball.c index f86b9740..91e8c57e 100644 --- a/bb-tests/workloads/src/CTest/toy/buckyball.c +++ b/bb-tests/workloads/src/CTest/toy/buckyball.c @@ -273,3 +273,26 @@ unsigned long long read_cycle(void) { asm volatile("csrr %0, cycle" : "=r"(c)); return c; } + +// MMIO address map (BBSimHarness, WithDefaultMMIOPort base=0x6000_0000): +// 0x6000_0000 : simulation exit — write triggers sim_exit() +// 0x6002_0000 : UART0 TX — write low byte → putchar in C++ +#define MMIO_SIM_EXIT ((volatile uint32_t *)0x60000000UL) +#define MMIO_UART_TX ((volatile uint32_t *)0x60020000UL) + +// _write: route stdout/stderr through MMIO UART so printf works in simulation. +// nosys.specs provides a weak _write stub; we override it here. +int _write(int fd, const char *buf, int len) { + (void)fd; + for (int i = 0; i < len; i++) { + *MMIO_UART_TX = (uint32_t)(unsigned char)buf[i]; + } + return len; +} + +// _exit: write exit code to MMIO sim-exit register; C++ mmio_tick() detects +// this and calls sim_exit(). +void __attribute__((noreturn)) _exit(int code) { + *MMIO_SIM_EXIT = (uint32_t)code; + while (1) {} // wait for C++ to process the MMIO write and call sim_exit() +} diff --git a/bb-tests/workloads/src/CTest/toy/crt0.S b/bb-tests/workloads/src/CTest/toy/crt0.S new file mode 100644 index 00000000..9e143f3a --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/crt0.S @@ -0,0 +1,25 @@ +/* crt0.S — minimal startup for BBSimHarness baremetal + * Bootrom jumps to 0x80000000 (this code). + * Sets up stack, clears BSS, then calls main. */ +.section .text.init,"ax",@progbits +.global _start +_start: + /* stack pointer: use a fixed address well above code */ + li sp, 0x80400000 + + /* clear BSS */ + la a0, __bss_start + la a1, __bss_end +bss_loop: + bgeu a0, a1, bss_done + sd zero, 0(a0) + addi a0, a0, 8 + j bss_loop +bss_done: + + call main + + /* if main returns, write 0 to sim_exit */ + li a0, 0x60000000 + sw zero, 0(a0) +1: j 1b diff --git a/bb-tests/workloads/src/CTest/toy/im2col_test.c b/bb-tests/workloads/src/CTest/toy/im2col_test.c index 848608bf..d3ebae5a 100644 --- a/bb-tests/workloads/src/CTest/toy/im2col_test.c +++ b/bb-tests/workloads/src/CTest/toy/im2col_test.c @@ -71,8 +71,6 @@ void hw_im2col(const char *test_name, elem_t *a, elem_t *b, int size) { uint64_t incol = INCOL; uint64_t startrow = STARTROW; uint64_t startcol = STARTCOL; - // bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, - // startcol); bb_im2col(op1_bank_id, op2_bank_id, krow, kcol, inrow, incol, startrow, startcol); bb_mvout((uintptr_t)b, op2_bank_id, conv_num() / kernel_elems(), 1); diff --git a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c index a6e56ef1..27301f89 100644 --- a/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c +++ b/bb-tests/workloads/src/CTest/toy/transpose_16xn_test.c @@ -51,14 +51,14 @@ int main() { #endif int all_passed = 1; - all_passed &= run_test("transpose_16x16", 16); - all_passed &= run_test("transpose_16x32", 32); + all_passed &= run_test("transpose 16x16", 16); + all_passed &= run_test("transpose 16x32", 32); if (all_passed) { - printf("All transpose_16xn tests PASSED\n"); + printf("All transpose 16xn tests PASSED\n"); return 0; } else { - printf("Some transpose_16xn tests FAILED\n"); + printf("Some transpose 16xn tests FAILED\n"); return 1; } #ifdef MULTICORE diff --git a/bbdev b/bbdev index 47fe2ab1..0d8ecd96 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 47fe2ab1c8b11b4b958ecc9227c78edb6c63142c +Subproject commit 0d8ecd9650673ef8a430642fc1524d7082efefc1 diff --git a/bebop b/bebop index 71a0017d..cabf424a 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 71a0017dac242a802d4e353979cc7f2cb3eaa42e +Subproject commit cabf424ae58ed80e287869b1a211e53d62056953 diff --git a/flake.nix b/flake.nix index b2f2e6b6..024e3115 100644 --- a/flake.nix +++ b/flake.nix @@ -108,7 +108,5 @@ ''; }; } - ) // { - inherit inputs; - }; + ); } diff --git a/pegasus/.gitignore b/pegasus/.gitignore new file mode 100644 index 00000000..499f6904 --- /dev/null +++ b/pegasus/.gitignore @@ -0,0 +1,5 @@ +generated/ +*jou +*.log +*_proj +.Xil diff --git a/pegasus/README.md b/pegasus/README.md new file mode 100644 index 00000000..85964e7b --- /dev/null +++ b/pegasus/README.md @@ -0,0 +1,2 @@ + +适配xx版本的Vivado \ No newline at end of file diff --git a/pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala b/pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala new file mode 100644 index 00000000..678ece2c --- /dev/null +++ b/pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala @@ -0,0 +1,462 @@ +package pegasus + +import chisel3._ +import chisel3.util._ +import pegasus.blackbox.{XDMABlackBox, HBM2BlackBox} + +// AXI4 Crossbar black box (Vivado axi_crossbar IP) +// 2 masters (XDMA DMA + ChipTop ExtMem), 1 slave (HBM2 PC0) +// Data width: 256-bit (narrowed from XDMA's 512-bit via width converter) +// Address width: 33-bit (HBM2 address space) +class AXICrossbarBlackBox extends BlackBox { + override def desiredName = "axi_crossbar_0" + val io = IO(new Bundle { + val aclk = Input(Clock()) + val aresetn = Input(Bool()) + + // Master port 0: XDMA DMA (width-converted to 256-bit) + val s_axi_awid_0 = Input(UInt(6.W)) + val s_axi_awaddr_0 = Input(UInt(33.W)) + val s_axi_awlen_0 = Input(UInt(8.W)) + val s_axi_awsize_0 = Input(UInt(3.W)) + val s_axi_awburst_0 = Input(UInt(2.W)) + val s_axi_awvalid_0 = Input(Bool()) + val s_axi_awready_0 = Output(Bool()) + val s_axi_wdata_0 = Input(UInt(256.W)) + val s_axi_wstrb_0 = Input(UInt(32.W)) + val s_axi_wlast_0 = Input(Bool()) + val s_axi_wvalid_0 = Input(Bool()) + val s_axi_wready_0 = Output(Bool()) + val s_axi_bid_0 = Output(UInt(6.W)) + val s_axi_bresp_0 = Output(UInt(2.W)) + val s_axi_bvalid_0 = Output(Bool()) + val s_axi_bready_0 = Input(Bool()) + val s_axi_arid_0 = Input(UInt(6.W)) + val s_axi_araddr_0 = Input(UInt(33.W)) + val s_axi_arlen_0 = Input(UInt(8.W)) + val s_axi_arsize_0 = Input(UInt(3.W)) + val s_axi_arburst_0 = Input(UInt(2.W)) + val s_axi_arvalid_0 = Input(Bool()) + val s_axi_arready_0 = Output(Bool()) + val s_axi_rid_0 = Output(UInt(6.W)) + val s_axi_rdata_0 = Output(UInt(256.W)) + val s_axi_rresp_0 = Output(UInt(2.W)) + val s_axi_rlast_0 = Output(Bool()) + val s_axi_rvalid_0 = Output(Bool()) + val s_axi_rready_0 = Input(Bool()) + + // Master port 1: ChipTop ExtMem AXI4 + val s_axi_awid_1 = Input(UInt(6.W)) + val s_axi_awaddr_1 = Input(UInt(33.W)) + val s_axi_awlen_1 = Input(UInt(8.W)) + val s_axi_awsize_1 = Input(UInt(3.W)) + val s_axi_awburst_1 = Input(UInt(2.W)) + val s_axi_awvalid_1 = Input(Bool()) + val s_axi_awready_1 = Output(Bool()) + val s_axi_wdata_1 = Input(UInt(256.W)) + val s_axi_wstrb_1 = Input(UInt(32.W)) + val s_axi_wlast_1 = Input(Bool()) + val s_axi_wvalid_1 = Input(Bool()) + val s_axi_wready_1 = Output(Bool()) + val s_axi_bid_1 = Output(UInt(6.W)) + val s_axi_bresp_1 = Output(UInt(2.W)) + val s_axi_bvalid_1 = Output(Bool()) + val s_axi_bready_1 = Input(Bool()) + val s_axi_arid_1 = Input(UInt(6.W)) + val s_axi_araddr_1 = Input(UInt(33.W)) + val s_axi_arlen_1 = Input(UInt(8.W)) + val s_axi_arsize_1 = Input(UInt(3.W)) + val s_axi_arburst_1 = Input(UInt(2.W)) + val s_axi_arvalid_1 = Input(Bool()) + val s_axi_arready_1 = Output(Bool()) + val s_axi_rid_1 = Output(UInt(6.W)) + val s_axi_rdata_1 = Output(UInt(256.W)) + val s_axi_rresp_1 = Output(UInt(2.W)) + val s_axi_rlast_1 = Output(Bool()) + val s_axi_rvalid_1 = Output(Bool()) + val s_axi_rready_1 = Input(Bool()) + + // Slave port 0: HBM2 PC0 + val m_axi_awid_0 = Output(UInt(6.W)) + val m_axi_awaddr_0 = Output(UInt(33.W)) + val m_axi_awlen_0 = Output(UInt(8.W)) + val m_axi_awsize_0 = Output(UInt(3.W)) + val m_axi_awburst_0 = Output(UInt(2.W)) + val m_axi_awvalid_0 = Output(Bool()) + val m_axi_awready_0 = Input(Bool()) + val m_axi_wdata_0 = Output(UInt(256.W)) + val m_axi_wstrb_0 = Output(UInt(32.W)) + val m_axi_wlast_0 = Output(Bool()) + val m_axi_wvalid_0 = Output(Bool()) + val m_axi_wready_0 = Input(Bool()) + val m_axi_bid_0 = Input(UInt(6.W)) + val m_axi_bresp_0 = Input(UInt(2.W)) + val m_axi_bvalid_0 = Input(Bool()) + val m_axi_bready_0 = Output(Bool()) + val m_axi_arid_0 = Output(UInt(6.W)) + val m_axi_araddr_0 = Output(UInt(33.W)) + val m_axi_arlen_0 = Output(UInt(8.W)) + val m_axi_arsize_0 = Output(UInt(3.W)) + val m_axi_arburst_0 = Output(UInt(2.W)) + val m_axi_arvalid_0 = Output(Bool()) + val m_axi_arready_0 = Input(Bool()) + val m_axi_rid_0 = Input(UInt(6.W)) + val m_axi_rdata_0 = Input(UInt(256.W)) + val m_axi_rresp_0 = Input(UInt(2.W)) + val m_axi_rlast_0 = Input(Bool()) + val m_axi_rvalid_0 = Input(Bool()) + val m_axi_rready_0 = Output(Bool()) + }) +} + +// AXI Width Converter: 512-bit → 256-bit (for XDMA DMA → Crossbar) +class AXIWidthConverterBlackBox extends BlackBox { + override def desiredName = "axi_dwidth_converter_0" + val io = IO(new Bundle { + val aclk = Input(Clock()) + val aresetn = Input(Bool()) + + // Slave side: 512-bit (from XDMA DMA) + val s_axi_awid = Input(UInt(4.W)) + val s_axi_awaddr = Input(UInt(64.W)) + val s_axi_awlen = Input(UInt(8.W)) + val s_axi_awsize = Input(UInt(3.W)) + val s_axi_awburst = Input(UInt(2.W)) + val s_axi_awvalid = Input(Bool()) + val s_axi_awready = Output(Bool()) + val s_axi_wdata = Input(UInt(512.W)) + val s_axi_wstrb = Input(UInt(64.W)) + val s_axi_wlast = Input(Bool()) + val s_axi_wvalid = Input(Bool()) + val s_axi_wready = Output(Bool()) + val s_axi_bid = Output(UInt(4.W)) + val s_axi_bresp = Output(UInt(2.W)) + val s_axi_bvalid = Output(Bool()) + val s_axi_bready = Input(Bool()) + val s_axi_arid = Input(UInt(4.W)) + val s_axi_araddr = Input(UInt(64.W)) + val s_axi_arlen = Input(UInt(8.W)) + val s_axi_arsize = Input(UInt(3.W)) + val s_axi_arburst = Input(UInt(2.W)) + val s_axi_arvalid = Input(Bool()) + val s_axi_arready = Output(Bool()) + val s_axi_rid = Output(UInt(4.W)) + val s_axi_rdata = Output(UInt(512.W)) + val s_axi_rresp = Output(UInt(2.W)) + val s_axi_rlast = Output(Bool()) + val s_axi_rvalid = Output(Bool()) + val s_axi_rready = Input(Bool()) + + // Master side: 256-bit (to crossbar) + val m_axi_awid = Output(UInt(6.W)) + val m_axi_awaddr = Output(UInt(33.W)) + val m_axi_awlen = Output(UInt(8.W)) + val m_axi_awsize = Output(UInt(3.W)) + val m_axi_awburst = Output(UInt(2.W)) + val m_axi_awvalid = Output(Bool()) + val m_axi_awready = Input(Bool()) + val m_axi_wdata = Output(UInt(256.W)) + val m_axi_wstrb = Output(UInt(32.W)) + val m_axi_wlast = Output(Bool()) + val m_axi_wvalid = Output(Bool()) + val m_axi_wready = Input(Bool()) + val m_axi_bid = Input(UInt(6.W)) + val m_axi_bresp = Input(UInt(2.W)) + val m_axi_bvalid = Input(Bool()) + val m_axi_bready = Output(Bool()) + val m_axi_arid = Output(UInt(6.W)) + val m_axi_araddr = Output(UInt(33.W)) + val m_axi_arlen = Output(UInt(8.W)) + val m_axi_arsize = Output(UInt(3.W)) + val m_axi_arburst = Output(UInt(2.W)) + val m_axi_arvalid = Output(Bool()) + val m_axi_arready = Input(Bool()) + val m_axi_rid = Input(UInt(6.W)) + val m_axi_rdata = Input(UInt(256.W)) + val m_axi_rresp = Input(UInt(2.W)) + val m_axi_rlast = Input(Bool()) + val m_axi_rvalid = Input(Bool()) + val m_axi_rready = Output(Bool()) + }) +} + +// PegasusShell: top-level Verilog module for AU280 FPGA +// +// Connects: +// XDMA IP <→> SCU (AXI-Lite BAR0) +// XDMA IP <→> AXI Crossbar master 0 (DMA) +// ChipTop <→> AXI Crossbar master 1 (ExtMem) +// Crossbar <→> HBM2 PC0 (slave) +// ChipTop UART TX → UARTCapture → XDMA AXI-Stream C2H +// SCU BUFGCE → ChipTop clock +// SCU dut_reset → ChipTop reset +// +// The ChipTop is NOT instantiated here — it is connected via the PegasusHarness +// (Chipyard's LazyModule infrastructure). PegasusShell only contains the IP +// blackboxes and glue logic. The PegasusHarness wraps PegasusShell and adds ChipTop. +// +class PegasusShell extends Module { + val io = IO(new Bundle { + // PCIe physical pins (to AU280 edge connector) + val pcie_sys_clk = Input(Clock()) + val pcie_sys_clk_gt = Input(Clock()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) + + // HBM2 reference clock (100 MHz, from MMCM or board clock) + val hbm_ref_clk = Input(Clock()) + + // Exported DUT clock and reset (to PegasusHarness for ChipTop) + val dut_clk = Output(Clock()) + val dut_reset = Output(Bool()) + + // ChipTop AXI4 memory interface (from PegasusHarness, ExtMem punchthrough) + // 256-bit data, 34-bit address (for 4GB address space) + val chip_mem_awid = Input(UInt(6.W)) + val chip_mem_awaddr = Input(UInt(33.W)) + val chip_mem_awlen = Input(UInt(8.W)) + val chip_mem_awsize = Input(UInt(3.W)) + val chip_mem_awburst = Input(UInt(2.W)) + val chip_mem_awvalid = Input(Bool()) + val chip_mem_awready = Output(Bool()) + val chip_mem_wdata = Input(UInt(256.W)) + val chip_mem_wstrb = Input(UInt(32.W)) + val chip_mem_wlast = Input(Bool()) + val chip_mem_wvalid = Input(Bool()) + val chip_mem_wready = Output(Bool()) + val chip_mem_bid = Output(UInt(6.W)) + val chip_mem_bresp = Output(UInt(2.W)) + val chip_mem_bvalid = Output(Bool()) + val chip_mem_bready = Input(Bool()) + val chip_mem_arid = Input(UInt(6.W)) + val chip_mem_araddr = Input(UInt(33.W)) + val chip_mem_arlen = Input(UInt(8.W)) + val chip_mem_arsize = Input(UInt(3.W)) + val chip_mem_arburst = Input(UInt(2.W)) + val chip_mem_arvalid = Input(Bool()) + val chip_mem_arready = Output(Bool()) + val chip_mem_rid = Output(UInt(6.W)) + val chip_mem_rdata = Output(UInt(256.W)) + val chip_mem_rresp = Output(UInt(2.W)) + val chip_mem_rlast = Output(Bool()) + val chip_mem_rvalid = Output(Bool()) + val chip_mem_rready = Input(Bool()) + + // ChipTop UART TX (serial output from DUT) + val uart_tx = Input(Bool()) + }) + + // --- Instantiate XDMA --- + val xdma = Module(new XDMABlackBox) + xdma.io.sys_clk := io.pcie_sys_clk + xdma.io.sys_clk_gt := io.pcie_sys_clk_gt + xdma.io.sys_rst_n := io.pcie_sys_rst_n + io.pcie_exp_txp := xdma.io.pci_exp_txp + io.pcie_exp_txn := xdma.io.pci_exp_txn + xdma.io.pci_exp_rxp := io.pcie_exp_rxp + xdma.io.pci_exp_rxn := io.pcie_exp_rxn + + val axiClk = xdma.io.axi_aclk + val axiResetn = xdma.io.axi_aresetn + + // --- Instantiate SCU (runs on host AXI clock) --- + // The SCU module uses the implicit clock from withClockAndReset context. + // We need it to run on axiClk. + val scu = withClockAndReset(axiClk, !axiResetn) { + Module(new SCU) + } + scu.io.host_clk := axiClk + + // Connect XDMA AXI-Lite master to SCU + scu.io.axil.awvalid := xdma.io.m_axil_awvalid + xdma.io.m_axil_awready := scu.io.axil.awready + scu.io.axil.awaddr := xdma.io.m_axil_awaddr + scu.io.axil.awprot := xdma.io.m_axil_awprot + scu.io.axil.wvalid := xdma.io.m_axil_wvalid + xdma.io.m_axil_wready := scu.io.axil.wready + scu.io.axil.wdata := xdma.io.m_axil_wdata + scu.io.axil.wstrb := xdma.io.m_axil_wstrb + xdma.io.m_axil_bvalid := scu.io.axil.bvalid + scu.io.axil.bready := xdma.io.m_axil_bready + xdma.io.m_axil_bresp := scu.io.axil.bresp + scu.io.axil.arvalid := xdma.io.m_axil_arvalid + xdma.io.m_axil_arready := scu.io.axil.arready + scu.io.axil.araddr := xdma.io.m_axil_araddr + scu.io.axil.arprot := xdma.io.m_axil_arprot + xdma.io.m_axil_rvalid := scu.io.axil.rvalid + scu.io.axil.rready := xdma.io.m_axil_rready + xdma.io.m_axil_rdata := scu.io.axil.rdata + xdma.io.m_axil_rresp := scu.io.axil.rresp + + // Export DUT clock and reset + io.dut_clk := scu.io.dut_clk + io.dut_reset := scu.io.dut_reset + + // --- Instantiate UARTCapture --- + val uartCapture = withClockAndReset(axiClk, !axiResetn) { + Module(new UARTCapture()) + } + uartCapture.io.uart_tx := io.uart_tx + + // Connect UART FIFO to XDMA AXI-Stream C2H channel 0 + // XDMA C2H channel expects 512-bit wide tdata; pad the 8-bit byte + xdma.io.s_axis_c2h_tvalid_0 := uartCapture.io.axis_tvalid + uartCapture.io.axis_tready := xdma.io.s_axis_c2h_tready_0 + xdma.io.s_axis_c2h_tdata_0 := Cat(0.U(504.W), uartCapture.io.axis_tdata) + xdma.io.s_axis_c2h_tlast_0 := uartCapture.io.axis_tlast + xdma.io.s_axis_c2h_tkeep_0 := Cat(0.U(63.W), uartCapture.io.axis_tkeep) + + // --- Instantiate AXI Width Converter (XDMA 512-bit → 256-bit) --- + val widthConv = Module(new AXIWidthConverterBlackBox) + widthConv.io.aclk := axiClk + widthConv.io.aresetn := axiResetn + + // Connect XDMA DMA AXI4 master to width converter + widthConv.io.s_axi_awid := xdma.io.m_axi_awid + widthConv.io.s_axi_awaddr := xdma.io.m_axi_awaddr + widthConv.io.s_axi_awlen := xdma.io.m_axi_awlen + widthConv.io.s_axi_awsize := xdma.io.m_axi_awsize + widthConv.io.s_axi_awburst := xdma.io.m_axi_awburst + widthConv.io.s_axi_awvalid := xdma.io.m_axi_awvalid + xdma.io.m_axi_awready := widthConv.io.s_axi_awready + widthConv.io.s_axi_wdata := xdma.io.m_axi_wdata + widthConv.io.s_axi_wstrb := xdma.io.m_axi_wstrb + widthConv.io.s_axi_wlast := xdma.io.m_axi_wlast + widthConv.io.s_axi_wvalid := xdma.io.m_axi_wvalid + xdma.io.m_axi_wready := widthConv.io.s_axi_wready + xdma.io.m_axi_bid := widthConv.io.s_axi_bid + xdma.io.m_axi_bresp := widthConv.io.s_axi_bresp + xdma.io.m_axi_bvalid := widthConv.io.s_axi_bvalid + widthConv.io.s_axi_bready := xdma.io.m_axi_bready + widthConv.io.s_axi_arid := xdma.io.m_axi_arid + widthConv.io.s_axi_araddr := xdma.io.m_axi_araddr + widthConv.io.s_axi_arlen := xdma.io.m_axi_arlen + widthConv.io.s_axi_arsize := xdma.io.m_axi_arsize + widthConv.io.s_axi_arburst := xdma.io.m_axi_arburst + widthConv.io.s_axi_arvalid := xdma.io.m_axi_arvalid + xdma.io.m_axi_arready := widthConv.io.s_axi_arready + xdma.io.m_axi_rid := widthConv.io.s_axi_rid + xdma.io.m_axi_rdata := widthConv.io.s_axi_rdata + xdma.io.m_axi_rresp := widthConv.io.s_axi_rresp + xdma.io.m_axi_rlast := widthConv.io.s_axi_rlast + xdma.io.m_axi_rvalid := widthConv.io.s_axi_rvalid + widthConv.io.s_axi_rready := xdma.io.m_axi_rready + + // --- Instantiate AXI Crossbar --- + val crossbar = Module(new AXICrossbarBlackBox) + crossbar.io.aclk := axiClk + crossbar.io.aresetn := axiResetn + + // Connect width converter output to crossbar master port 0 (XDMA DMA) + crossbar.io.s_axi_awid_0 := widthConv.io.m_axi_awid + crossbar.io.s_axi_awaddr_0 := widthConv.io.m_axi_awaddr + crossbar.io.s_axi_awlen_0 := widthConv.io.m_axi_awlen + crossbar.io.s_axi_awsize_0 := widthConv.io.m_axi_awsize + crossbar.io.s_axi_awburst_0 := widthConv.io.m_axi_awburst + crossbar.io.s_axi_awvalid_0 := widthConv.io.m_axi_awvalid + widthConv.io.m_axi_awready := crossbar.io.s_axi_awready_0 + crossbar.io.s_axi_wdata_0 := widthConv.io.m_axi_wdata + crossbar.io.s_axi_wstrb_0 := widthConv.io.m_axi_wstrb + crossbar.io.s_axi_wlast_0 := widthConv.io.m_axi_wlast + crossbar.io.s_axi_wvalid_0 := widthConv.io.m_axi_wvalid + widthConv.io.m_axi_wready := crossbar.io.s_axi_wready_0 + widthConv.io.m_axi_bid := crossbar.io.s_axi_bid_0 + widthConv.io.m_axi_bresp := crossbar.io.s_axi_bresp_0 + widthConv.io.m_axi_bvalid := crossbar.io.s_axi_bvalid_0 + crossbar.io.s_axi_bready_0 := widthConv.io.m_axi_bready + crossbar.io.s_axi_arid_0 := widthConv.io.m_axi_arid + crossbar.io.s_axi_araddr_0 := widthConv.io.m_axi_araddr + crossbar.io.s_axi_arlen_0 := widthConv.io.m_axi_arlen + crossbar.io.s_axi_arsize_0 := widthConv.io.m_axi_arsize + crossbar.io.s_axi_arburst_0 := widthConv.io.m_axi_arburst + crossbar.io.s_axi_arvalid_0 := widthConv.io.m_axi_arvalid + widthConv.io.m_axi_arready := crossbar.io.s_axi_arready_0 + widthConv.io.m_axi_rid := crossbar.io.s_axi_rid_0 + widthConv.io.m_axi_rdata := crossbar.io.s_axi_rdata_0 + widthConv.io.m_axi_rresp := crossbar.io.s_axi_rresp_0 + widthConv.io.m_axi_rlast := crossbar.io.s_axi_rlast_0 + widthConv.io.m_axi_rvalid := crossbar.io.s_axi_rvalid_0 + crossbar.io.s_axi_rready_0 := widthConv.io.m_axi_rready + + // Connect ChipTop ExtMem to crossbar master port 1 + // Address offset: SoC physical addr 0x80000000 → HBM2 addr 0x0 + // The address translation is done here: chip_mem_araddr - 0x80000000 + crossbar.io.s_axi_awid_1 := io.chip_mem_awid + crossbar.io.s_axi_awaddr_1 := io.chip_mem_awaddr - 0x80000000L.U(33.W) + crossbar.io.s_axi_awlen_1 := io.chip_mem_awlen + crossbar.io.s_axi_awsize_1 := io.chip_mem_awsize + crossbar.io.s_axi_awburst_1 := io.chip_mem_awburst + crossbar.io.s_axi_awvalid_1 := io.chip_mem_awvalid + io.chip_mem_awready := crossbar.io.s_axi_awready_1 + crossbar.io.s_axi_wdata_1 := io.chip_mem_wdata + crossbar.io.s_axi_wstrb_1 := io.chip_mem_wstrb + crossbar.io.s_axi_wlast_1 := io.chip_mem_wlast + crossbar.io.s_axi_wvalid_1 := io.chip_mem_wvalid + io.chip_mem_wready := crossbar.io.s_axi_wready_1 + io.chip_mem_bid := crossbar.io.s_axi_bid_1 + io.chip_mem_bresp := crossbar.io.s_axi_bresp_1 + io.chip_mem_bvalid := crossbar.io.s_axi_bvalid_1 + crossbar.io.s_axi_bready_1 := io.chip_mem_bready + crossbar.io.s_axi_arid_1 := io.chip_mem_arid + crossbar.io.s_axi_araddr_1 := io.chip_mem_araddr - 0x80000000L.U(33.W) + crossbar.io.s_axi_arlen_1 := io.chip_mem_arlen + crossbar.io.s_axi_arsize_1 := io.chip_mem_arsize + crossbar.io.s_axi_arburst_1 := io.chip_mem_arburst + crossbar.io.s_axi_arvalid_1 := io.chip_mem_arvalid + io.chip_mem_arready := crossbar.io.s_axi_arready_1 + io.chip_mem_rid := crossbar.io.s_axi_rid_1 + io.chip_mem_rdata := crossbar.io.s_axi_rdata_1 + io.chip_mem_rresp := crossbar.io.s_axi_rresp_1 + io.chip_mem_rlast := crossbar.io.s_axi_rlast_1 + io.chip_mem_rvalid := crossbar.io.s_axi_rvalid_1 + crossbar.io.s_axi_rready_1 := io.chip_mem_rready + + // --- Instantiate HBM2 --- + val hbm2 = Module(new HBM2BlackBox) + hbm2.io.HBM_REF_CLK_0 := io.hbm_ref_clk + hbm2.io.AXI_00_ACLK := axiClk + hbm2.io.AXI_00_ARESET_N := axiResetn + + // Connect crossbar slave port 0 to HBM2 PC0 + hbm2.io.AXI_00_AWID := crossbar.io.m_axi_awid_0 + hbm2.io.AXI_00_AWADDR := crossbar.io.m_axi_awaddr_0 + hbm2.io.AXI_00_AWLEN := crossbar.io.m_axi_awlen_0(3, 0) // HBM2 only has 4-bit len + hbm2.io.AXI_00_AWSIZE := crossbar.io.m_axi_awsize_0 + hbm2.io.AXI_00_AWBURST := crossbar.io.m_axi_awburst_0 + hbm2.io.AXI_00_AWVALID := crossbar.io.m_axi_awvalid_0 + crossbar.io.m_axi_awready_0 := hbm2.io.AXI_00_AWREADY + hbm2.io.AXI_00_WDATA := crossbar.io.m_axi_wdata_0 + hbm2.io.AXI_00_WSTRB := crossbar.io.m_axi_wstrb_0 + hbm2.io.AXI_00_WLAST := crossbar.io.m_axi_wlast_0 + hbm2.io.AXI_00_WVALID := crossbar.io.m_axi_wvalid_0 + crossbar.io.m_axi_wready_0 := hbm2.io.AXI_00_WREADY + crossbar.io.m_axi_bid_0 := hbm2.io.AXI_00_BID + crossbar.io.m_axi_bresp_0 := hbm2.io.AXI_00_BRESP + crossbar.io.m_axi_bvalid_0 := hbm2.io.AXI_00_BVALID + hbm2.io.AXI_00_BREADY := crossbar.io.m_axi_bready_0 + hbm2.io.AXI_00_ARID := crossbar.io.m_axi_arid_0 + hbm2.io.AXI_00_ARADDR := crossbar.io.m_axi_araddr_0 + hbm2.io.AXI_00_ARLEN := crossbar.io.m_axi_arlen_0(3, 0) + hbm2.io.AXI_00_ARSIZE := crossbar.io.m_axi_arsize_0 + hbm2.io.AXI_00_ARBURST := crossbar.io.m_axi_arburst_0 + hbm2.io.AXI_00_ARVALID := crossbar.io.m_axi_arvalid_0 + crossbar.io.m_axi_arready_0 := hbm2.io.AXI_00_ARREADY + crossbar.io.m_axi_rid_0 := hbm2.io.AXI_00_RID + crossbar.io.m_axi_rdata_0 := hbm2.io.AXI_00_RDATA + crossbar.io.m_axi_rresp_0 := hbm2.io.AXI_00_RRESP + crossbar.io.m_axi_rlast_0 := hbm2.io.AXI_00_RLAST + crossbar.io.m_axi_rvalid_0 := hbm2.io.AXI_00_RVALID + hbm2.io.AXI_00_RREADY := crossbar.io.m_axi_rready_0 + + // HBM2 APB configuration interface: tie off (no runtime config needed) + hbm2.io.APB_0_PWDATA := 0.U + hbm2.io.APB_0_PADDR := 0.U + hbm2.io.APB_0_PCLK := axiClk + hbm2.io.APB_0_PENABLE := false.B + hbm2.io.APB_0_PRESET_N := axiResetn + hbm2.io.APB_0_PSEL := false.B + hbm2.io.APB_0_PWRITE := false.B +} diff --git a/pegasus/chisel/src/main/scala/pegasus/SCU.scala b/pegasus/chisel/src/main/scala/pegasus/SCU.scala new file mode 100644 index 00000000..20a26db8 --- /dev/null +++ b/pegasus/chisel/src/main/scala/pegasus/SCU.scala @@ -0,0 +1,207 @@ +package pegasus + +import chisel3._ +import chisel3.util._ + +// BUFGCE Xilinx primitive for glitch-free clock gating +// Must be instantiated as a BlackBox — never use Chisel when() to gate a clock +class BUFGCE extends BlackBox { + val io = IO(new Bundle { + val I = Input(Clock()) + val CE = Input(Bool()) + val O = Output(Clock()) + }) +} + +// AXI-Lite slave interface (from XDMA AXI-Lite master, BAR0) +// Signal direction is from the perspective of the AXI-Lite slave (SCU) +class SCUAXILiteIO extends Bundle { + // Write address channel (Input from master) + val awvalid = Input(Bool()) + val awready = Output(Bool()) + val awaddr = Input(UInt(16.W)) + val awprot = Input(UInt(3.W)) + + // Write data channel + val wvalid = Input(Bool()) + val wready = Output(Bool()) + val wdata = Input(UInt(32.W)) + val wstrb = Input(UInt(4.W)) + + // Write response channel + val bvalid = Output(Bool()) + val bready = Input(Bool()) + val bresp = Output(UInt(2.W)) + + // Read address channel + val arvalid = Input(Bool()) + val arready = Output(Bool()) + val araddr = Input(UInt(16.W)) + val arprot = Input(UInt(3.W)) + + // Read data channel + val rvalid = Output(Bool()) + val rready = Input(Bool()) + val rdata = Output(UInt(32.W)) + val rresp = Output(UInt(2.W)) +} + +// Simulation Control Unit +// +// Register map (AXI-Lite, BAR0 offsets): +// 0x0000 CTRL W [0]=freeRun, [1]=stepMode enter +// 0x0004 STEP_N W [31:0] = number of cycles to execute; writing triggers single-step +// 0x0008 STATUS R [0]=idle, [1]=stepDone +// 0x000C CYCLE_LO R [31:0] = cycle counter low +// 0x0010 CYCLE_HI R [31:0] = cycle counter high +// 0x0014 RESET W [0] = DUT reset (1=assert, 0=deassert) +// +// Clock gating: SCU uses a BUFGCE primitive to gate the host clock. +// The SCU itself runs on the host (AXI) clock. DUT gets the gated clock. +// +class SCU extends Module { + val io = IO(new Bundle { + val axil = new SCUAXILiteIO // AXI-Lite slave (from XDMA BAR0 master) + val host_clk = Input(Clock()) // Host clock input (XDMA axi_aclk, 250 MHz) + val dut_clk = Output(Clock()) // Gated DUT clock output + val dut_reset = Output(Bool()) // DUT reset signal (active high) + }) + + // --- Clock gate --- + val bufgce = Module(new BUFGCE) + bufgce.io.I := io.host_clk + + // --- Control registers (run on host clock domain, i.e. the module's implicit clock) --- + val freeRunMode = RegInit(false.B) + val stepMode = RegInit(false.B) + val stepCount = RegInit(0.U(32.W)) + val cycleCounter = RegInit(0.U(64.W)) + val stepDone = RegInit(false.B) + val dutReset = RegInit(true.B) // DUT starts in reset + + // Clock enable logic + val clkEnable = Wire(Bool()) + when(stepMode) { + clkEnable := stepCount > 0.U + when(clkEnable) { + stepCount := stepCount - 1.U + cycleCounter := cycleCounter + 1.U + } + // Mark step done when last cycle fires + when(stepCount === 1.U && clkEnable) { + stepDone := true.B + } + }.otherwise { + clkEnable := freeRunMode + when(clkEnable) { + cycleCounter := cycleCounter + 1.U + } + } + + bufgce.io.CE := clkEnable + io.dut_clk := bufgce.io.O + io.dut_reset := dutReset + + // --- AXI-Lite state machine --- + // Simple two-state machine: IDLE and handle write/read + // AW and W channels are accepted together; B response sent immediately (OKAY) + // AR channel is accepted; R response sent with register data + + val sIdle :: sWriteResp :: sReadData :: Nil = Enum(3) + val state = RegInit(sIdle) + + // Captured write address and data + val wrAddr = RegInit(0.U(16.W)) + val wrData = RegInit(0.U(32.W)) + val wrStrb = RegInit(0.U(4.W)) + + // Captured read address + val rdAddr = RegInit(0.U(16.W)) + val rdData = RegInit(0.U(32.W)) + + // Default outputs + io.axil.awready := false.B + io.axil.wready := false.B + io.axil.bvalid := false.B + io.axil.bresp := 0.U // OKAY + io.axil.arready := false.B + io.axil.rvalid := false.B + io.axil.rdata := 0.U + io.axil.rresp := 0.U // OKAY + + switch(state) { + is(sIdle) { + // Accept write if both AW and W are valid + when(io.axil.awvalid && io.axil.wvalid) { + io.axil.awready := true.B + io.axil.wready := true.B + wrAddr := io.axil.awaddr + wrData := io.axil.wdata + wrStrb := io.axil.wstrb + state := sWriteResp + }.elsewhen(io.axil.arvalid) { + // Accept read + io.axil.arready := true.B + rdAddr := io.axil.araddr + state := sReadData + } + } + is(sWriteResp) { + // Apply the write and send B response + io.axil.bvalid := true.B + when(io.axil.bready) { + state := sIdle + } + // Register writes + switch(wrAddr(7, 0)) { + is(0x00.U) { // CTRL + when(wrData(0)) { + // CTRL[0] = 1: start free running, clear step mode + freeRunMode := true.B + stepMode := false.B + }.otherwise { + // CTRL[0] = 0: halt + freeRunMode := false.B + } + when(wrData(1)) { + // CTRL[1] = 1: enter step mode (halts freeRun) + stepMode := true.B + freeRunMode := false.B + } + } + is(0x04.U) { // STEP_N: write N → single-step N cycles + stepCount := wrData + stepMode := true.B + freeRunMode := false.B + stepDone := false.B + } + is(0x14.U) { // RESET + dutReset := wrData(0) + } + } + } + is(sReadData) { + // Compute read data + val rdat = Wire(UInt(32.W)) + rdat := 0.U + switch(rdAddr(7, 0)) { + is(0x08.U) { // STATUS + rdat := Cat(0.U(30.W), stepDone, (!freeRunMode && !clkEnable)) + } + is(0x0C.U) { // CYCLE_LO + rdat := cycleCounter(31, 0) + } + is(0x10.U) { // CYCLE_HI + rdat := cycleCounter(63, 32) + } + } + rdData := rdat + + io.axil.rvalid := true.B + io.axil.rdata := rdData + when(io.axil.rready) { + state := sIdle + } + } + } +} diff --git a/pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala b/pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala new file mode 100644 index 00000000..36a8ef43 --- /dev/null +++ b/pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala @@ -0,0 +1,128 @@ +package pegasus + +import chisel3._ +import chisel3.util._ + +// UARTCapture: receives UART TX from DUT, decodes bytes, buffers in FIFO, +// and outputs via AXI-Stream to the XDMA C2H channel. +// +// UART frame format: 1 start bit (0), 8 data bits (LSB first), 1 stop bit (1) +// Baud rate: 115200 baud by default +// Clock: host_clk (250 MHz from XDMA) +// +// The DUT's UART TX is already a standard async serial signal (the DUT's +// UART peripheral encodes the bytes into UART frames internally). +// This module acts as a UART receiver (RX) that samples the DUT's TX line. +// +// Parameters: +// clockFreqHz : host clock frequency in Hz (default 250 MHz) +// baudRate : UART baud rate (default 115200) +// fifoDepth : byte FIFO depth (default 4096) +// +class UARTCapture( + clockFreqHz: Int = 250_000_000, + baudRate: Int = 115200, + fifoDepth: Int = 4096 +) extends Module { + val io = IO(new Bundle { + val uart_tx = Input(Bool()) // DUT UART TX line (idle high) + + // AXI-Stream master output → XDMA C2H channel + val axis_tvalid = Output(Bool()) + val axis_tready = Input(Bool()) + val axis_tdata = Output(UInt(8.W)) + val axis_tlast = Output(Bool()) + val axis_tkeep = Output(UInt(1.W)) + }) + + // --- Baud rate configuration --- + // Number of clock cycles per UART bit + val cyclesPerBit = (clockFreqHz / baudRate).U + // Half period offset for sampling in middle of bit + val halfCyclesPerBit = (clockFreqHz / baudRate / 2).U + + // --- Input synchronizer (2-FF for metastability) --- + val rxd_sync0 = RegNext(io.uart_tx, true.B) + val rxd_sync1 = RegNext(rxd_sync0, true.B) + val rxd = rxd_sync1 + + // --- UART RX state machine --- + val sIdle :: sStart :: sData :: sStop :: Nil = Enum(4) + val state = RegInit(sIdle) + + val bitCounter = RegInit(0.U(4.W)) // counts 0..7 data bits + val clockCount = RegInit(0.U(32.W)) // counts cycles within a bit period + val shiftReg = RegInit(0.U(8.W)) // shift register for received byte + val byteValid = RegInit(false.B) // pulse: one byte received + val receivedByte = RegInit(0.U(8.W)) + + byteValid := false.B // default + + switch(state) { + is(sIdle) { + // Wait for start bit (falling edge: idle is 1, start bit is 0) + when(!rxd) { + state := sStart + clockCount := 0.U + } + } + is(sStart) { + // Wait half a bit period, then verify start bit is still low + clockCount := clockCount + 1.U + when(clockCount >= halfCyclesPerBit - 1.U) { + when(!rxd) { + // Valid start bit; begin receiving data bits + state := sData + clockCount := 0.U + bitCounter := 0.U + shiftReg := 0.U + }.otherwise { + // Spurious glitch, return to idle + state := sIdle + } + } + } + is(sData) { + // Sample each data bit at center of bit period + clockCount := clockCount + 1.U + when(clockCount >= cyclesPerBit - 1.U) { + clockCount := 0.U + // Sample bit (LSB first) + shiftReg := Cat(rxd, shiftReg(7, 1)) + bitCounter := bitCounter + 1.U + when(bitCounter === 7.U) { + state := sStop + } + } + } + is(sStop) { + // Wait for stop bit + clockCount := clockCount + 1.U + when(clockCount >= cyclesPerBit - 1.U) { + when(rxd) { + // Valid stop bit: byte received + byteValid := true.B + receivedByte := shiftReg + } + // Return to idle regardless (even on framing errors, resync) + state := sIdle + clockCount := 0.U + } + } + } + + // --- Byte FIFO --- + val fifo = Module(new Queue(UInt(8.W), fifoDepth)) + fifo.io.enq.valid := byteValid + fifo.io.enq.bits := receivedByte + + // AXI-Stream output from FIFO + io.axis_tvalid := fifo.io.deq.valid + io.axis_tdata := fifo.io.deq.bits + io.axis_tlast := false.B // No natural frame boundary for UART bytes + io.axis_tkeep := 1.U // 1 valid byte per beat + fifo.io.deq.ready := io.axis_tready + + // Drop silently if FIFO is full (overflow protection) + // The FIFO's enq.ready going low just means we lose bytes +} diff --git a/pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala b/pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala new file mode 100644 index 00000000..d0688dc6 --- /dev/null +++ b/pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala @@ -0,0 +1,115 @@ +package pegasus.blackbox + +import chisel3._ +import chisel3.util._ + +// AXI4 HBM2 slave port bundle (one pseudo-channel) +// Data width: 256-bit, addr width: 33-bit, id width: 6-bit +class HBM2AXI4Bundle extends Bundle { + // Write address channel + val awid = Input(UInt(6.W)) + val awaddr = Input(UInt(33.W)) + val awlen = Input(UInt(4.W)) // HBM2 supports burst length up to 16 + val awsize = Input(UInt(3.W)) + val awburst = Input(UInt(2.W)) + val awvalid = Input(Bool()) + val awready = Output(Bool()) + + // Write data channel + val wdata = Input(UInt(256.W)) + val wstrb = Input(UInt(32.W)) + val wlast = Input(Bool()) + val wvalid = Input(Bool()) + val wready = Output(Bool()) + + // Write response channel + val bid = Output(UInt(6.W)) + val bresp = Output(UInt(2.W)) + val bvalid = Output(Bool()) + val bready = Input(Bool()) + + // Read address channel + val arid = Input(UInt(6.W)) + val araddr = Input(UInt(33.W)) + val arlen = Input(UInt(4.W)) + val arsize = Input(UInt(3.W)) + val arburst = Input(UInt(2.W)) + val arvalid = Input(Bool()) + val arready = Output(Bool()) + + // Read data channel + val rid = Output(UInt(6.W)) + val rdata = Output(UInt(256.W)) + val rresp = Output(UInt(2.W)) + val rlast = Output(Bool()) + val rvalid = Output(Bool()) + val rready = Input(Bool()) +} + +// Xilinx HBM2 IP black box for AU280 (xcu280) +// AU280 has 2 HBM stacks, each with 8 pseudo-channels. +// MVP uses Stack 0, PC0 only. +// AXI interface: 256-bit data, 33-bit address, 6-bit ID, 250 MHz +class HBM2BlackBox extends BlackBox { + override def desiredName = "hbm_0" + val io = IO(new Bundle { + // Reference clocks for HBM2 (provided by MMCM) + val HBM_REF_CLK_0 = Input(Clock()) // 100 MHz reference for stack 0 + + // AXI interface clock (250 MHz, from XDMA axi_aclk) + val AXI_00_ACLK = Input(Clock()) + val AXI_00_ARESET_N = Input(Bool()) + + // AXI slave port for PC0 (Stack 0, Pseudo-channel 0) + val AXI_00_AWID = Input(UInt(6.W)) + val AXI_00_AWADDR = Input(UInt(33.W)) + val AXI_00_AWLEN = Input(UInt(4.W)) + val AXI_00_AWSIZE = Input(UInt(3.W)) + val AXI_00_AWBURST = Input(UInt(2.W)) + val AXI_00_AWVALID = Input(Bool()) + val AXI_00_AWREADY = Output(Bool()) + + val AXI_00_WDATA = Input(UInt(256.W)) + val AXI_00_WSTRB = Input(UInt(32.W)) + val AXI_00_WLAST = Input(Bool()) + val AXI_00_WVALID = Input(Bool()) + val AXI_00_WREADY = Output(Bool()) + + val AXI_00_BID = Output(UInt(6.W)) + val AXI_00_BRESP = Output(UInt(2.W)) + val AXI_00_BVALID = Output(Bool()) + val AXI_00_BREADY = Input(Bool()) + + val AXI_00_ARID = Input(UInt(6.W)) + val AXI_00_ARADDR = Input(UInt(33.W)) + val AXI_00_ARLEN = Input(UInt(4.W)) + val AXI_00_ARSIZE = Input(UInt(3.W)) + val AXI_00_ARBURST = Input(UInt(2.W)) + val AXI_00_ARVALID = Input(Bool()) + val AXI_00_ARREADY = Output(Bool()) + + val AXI_00_RID = Output(UInt(6.W)) + val AXI_00_RDATA = Output(UInt(256.W)) + val AXI_00_RRESP = Output(UInt(2.W)) + val AXI_00_RLAST = Output(Bool()) + val AXI_00_RVALID = Output(Bool()) + val AXI_00_RREADY = Input(Bool()) + + // APB (configuration) interface + val APB_0_PWDATA = Input(UInt(32.W)) + val APB_0_PADDR = Input(UInt(22.W)) + val APB_0_PCLK = Input(Clock()) + val APB_0_PENABLE = Input(Bool()) + val APB_0_PRESET_N = Input(Bool()) + val APB_0_PSEL = Input(Bool()) + val APB_0_PWRITE = Input(Bool()) + val APB_0_PRDATA = Output(UInt(32.W)) + val APB_0_PREADY = Output(Bool()) + val APB_0_PSLVERR = Output(Bool()) + + // HBM2 initialization status + val apb_complete_0 = Output(Bool()) + val DRAM_0_STAT_CATTRIP = Output(Bool()) + val DRAM_0_STAT_TEMP = Output(UInt(7.W)) + }) +} diff --git a/pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala b/pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala new file mode 100644 index 00000000..22adabed --- /dev/null +++ b/pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala @@ -0,0 +1,170 @@ +package pegasus.blackbox + +import chisel3._ +import chisel3.util._ + +// AXI4-Lite bundle for XDMA AXI-Lite master interface +class AXILiteBundle(addrWidth: Int = 32, dataWidth: Int = 32) extends Bundle { + val awvalid = Output(Bool()) + val awready = Input(Bool()) + val awaddr = Output(UInt(addrWidth.W)) + val awprot = Output(UInt(3.W)) + + val wvalid = Output(Bool()) + val wready = Input(Bool()) + val wdata = Output(UInt(dataWidth.W)) + val wstrb = Output(UInt((dataWidth / 8).W)) + + val bvalid = Input(Bool()) + val bready = Output(Bool()) + val bresp = Input(UInt(2.W)) + + val arvalid = Output(Bool()) + val arready = Input(Bool()) + val araddr = Output(UInt(addrWidth.W)) + val arprot = Output(UInt(3.W)) + + val rvalid = Input(Bool()) + val rready = Output(Bool()) + val rdata = Input(UInt(dataWidth.W)) + val rresp = Input(UInt(2.W)) +} + +// AXI4 bundle for XDMA DMA master interface (connects to HBM2 via crossbar) +class AXI4Bundle( + addrWidth: Int = 64, + dataWidth: Int = 512, + idWidth: Int = 4 +) extends Bundle { + val awid = Output(UInt(idWidth.W)) + val awaddr = Output(UInt(addrWidth.W)) + val awlen = Output(UInt(8.W)) + val awsize = Output(UInt(3.W)) + val awburst = Output(UInt(2.W)) + val awvalid = Output(Bool()) + val awready = Input(Bool()) + + val wdata = Output(UInt(dataWidth.W)) + val wstrb = Output(UInt((dataWidth / 8).W)) + val wlast = Output(Bool()) + val wvalid = Output(Bool()) + val wready = Input(Bool()) + + val bid = Input(UInt(idWidth.W)) + val bresp = Input(UInt(2.W)) + val bvalid = Input(Bool()) + val bready = Output(Bool()) + + val arid = Output(UInt(idWidth.W)) + val araddr = Output(UInt(addrWidth.W)) + val arlen = Output(UInt(8.W)) + val arsize = Output(UInt(3.W)) + val arburst = Output(UInt(2.W)) + val arvalid = Output(Bool()) + val arready = Input(Bool()) + + val rid = Input(UInt(idWidth.W)) + val rdata = Input(UInt(dataWidth.W)) + val rresp = Input(UInt(2.W)) + val rlast = Input(Bool()) + val rvalid = Input(Bool()) + val rready = Output(Bool()) +} + +// AXI-Stream bundle (XDMA C2H channel for UART) +class AXIStreamBundle(dataWidth: Int = 8) extends Bundle { + val tvalid = Input(Bool()) + val tready = Output(Bool()) + val tdata = Input(UInt(dataWidth.W)) + val tlast = Input(Bool()) + val tkeep = Input(UInt((dataWidth / 8).W)) +} + +// Xilinx XDMA IP black box +// PCIe x16 Gen3, 512-bit AXI, 250 MHz AXI clock +// Exposes: +// - axi_aclk / axi_aresetn : AXI clock/reset outputs (driven by IP) +// - m_axil_* : AXI-Lite master (for SCU MMIO) +// - m_axi_* : AXI4 master (DMA, 512-bit, to HBM2 via crossbar) +// - s_axis_c2h_* : AXI-Stream slave (C2H, for UART upload) +// - pcie_* : PCIe PHY pins +class XDMABlackBox extends BlackBox { + override def desiredName = "xdma_0" + val io = IO(new Bundle { + // PCIe reference clock (100 MHz differential) + val sys_clk = Input(Clock()) + val sys_clk_gt = Input(Clock()) + val sys_rst_n = Input(Bool()) + + // Clocks/reset outputs (driven by XDMA IP) + val axi_aclk = Output(Clock()) + val axi_aresetn = Output(Bool()) + + // AXI-Lite master (MMIO, BAR0) + val m_axil_awvalid = Output(Bool()) + val m_axil_awready = Input(Bool()) + val m_axil_awaddr = Output(UInt(32.W)) + val m_axil_awprot = Output(UInt(3.W)) + val m_axil_wvalid = Output(Bool()) + val m_axil_wready = Input(Bool()) + val m_axil_wdata = Output(UInt(32.W)) + val m_axil_wstrb = Output(UInt(4.W)) + val m_axil_bvalid = Input(Bool()) + val m_axil_bready = Output(Bool()) + val m_axil_bresp = Input(UInt(2.W)) + val m_axil_arvalid = Output(Bool()) + val m_axil_arready = Input(Bool()) + val m_axil_araddr = Output(UInt(32.W)) + val m_axil_arprot = Output(UInt(3.W)) + val m_axil_rvalid = Input(Bool()) + val m_axil_rready = Output(Bool()) + val m_axil_rdata = Input(UInt(32.W)) + val m_axil_rresp = Input(UInt(2.W)) + + // AXI4 master (DMA, 512-bit data bus) + val m_axi_awid = Output(UInt(4.W)) + val m_axi_awaddr = Output(UInt(64.W)) + val m_axi_awlen = Output(UInt(8.W)) + val m_axi_awsize = Output(UInt(3.W)) + val m_axi_awburst = Output(UInt(2.W)) + val m_axi_awprot = Output(UInt(3.W)) + val m_axi_awvalid = Output(Bool()) + val m_axi_awready = Input(Bool()) + val m_axi_wdata = Output(UInt(512.W)) + val m_axi_wstrb = Output(UInt(64.W)) + val m_axi_wlast = Output(Bool()) + val m_axi_wvalid = Output(Bool()) + val m_axi_wready = Input(Bool()) + val m_axi_bid = Input(UInt(4.W)) + val m_axi_bresp = Input(UInt(2.W)) + val m_axi_bvalid = Input(Bool()) + val m_axi_bready = Output(Bool()) + val m_axi_arid = Output(UInt(4.W)) + val m_axi_araddr = Output(UInt(64.W)) + val m_axi_arlen = Output(UInt(8.W)) + val m_axi_arsize = Output(UInt(3.W)) + val m_axi_arburst = Output(UInt(2.W)) + val m_axi_arprot = Output(UInt(3.W)) + val m_axi_arvalid = Output(Bool()) + val m_axi_arready = Input(Bool()) + val m_axi_rid = Input(UInt(4.W)) + val m_axi_rdata = Input(UInt(512.W)) + val m_axi_rresp = Input(UInt(2.W)) + val m_axi_rlast = Input(Bool()) + val m_axi_rvalid = Input(Bool()) + val m_axi_rready = Output(Bool()) + + // AXI-Stream slave C2H channel 0 (host-bound, e.g. UART output) + val s_axis_c2h_tvalid_0 = Input(Bool()) + val s_axis_c2h_tready_0 = Output(Bool()) + val s_axis_c2h_tdata_0 = Input(UInt(512.W)) + val s_axis_c2h_tlast_0 = Input(Bool()) + val s_axis_c2h_tkeep_0 = Input(UInt(64.W)) + + // PCIe differential pairs (x16) + val pci_exp_txp = Output(UInt(16.W)) + val pci_exp_txn = Output(UInt(16.W)) + val pci_exp_rxp = Input(UInt(16.W)) + val pci_exp_rxn = Input(UInt(16.W)) + }) +} diff --git a/pegasus/driver/.gitignore b/pegasus/driver/.gitignore new file mode 100644 index 00000000..6654b8d8 --- /dev/null +++ b/pegasus/driver/.gitignore @@ -0,0 +1,2 @@ +build/ +compile_commands.json diff --git a/pegasus/driver/CMakeLists.txt b/pegasus/driver/CMakeLists.txt new file mode 100644 index 00000000..ff794d95 --- /dev/null +++ b/pegasus/driver/CMakeLists.txt @@ -0,0 +1,35 @@ +cmake_minimum_required(VERSION 3.16) +project(pegasus-driver CXX) + +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +# Compiler flags +add_compile_options(-Wall -Wextra -O2) + +# Find libelf (required for ELF parsing) +find_library(LIBELF_LIB elf REQUIRED) +find_path(LIBELF_INCLUDE libelf.h + PATHS /usr/include /usr/local/include + REQUIRED) + +# ---- pegasus-run executable ---- +add_executable(pegasus-run + src/xdma.cc + src/scu.cc + src/uart.cc + src/elf.cc + src/main.cc +) + +target_include_directories(pegasus-run PRIVATE + include + ${LIBELF_INCLUDE} +) + +target_link_libraries(pegasus-run PRIVATE + ${LIBELF_LIB} +) + +# Install target (optional) +install(TARGETS pegasus-run DESTINATION bin) diff --git a/pegasus/driver/include/pegasus.h b/pegasus/driver/include/pegasus.h new file mode 100644 index 00000000..a95fe38f --- /dev/null +++ b/pegasus/driver/include/pegasus.h @@ -0,0 +1,132 @@ +#pragma once +#include +#include +#include +#include + +// ============================================================ +// Pegasus FPGA Simulation Framework — Public API +// ============================================================ + +// ---- SCU register offsets (BAR0 MMIO) ---- +#define SCU_CTRL_OFFSET 0x0000U // W: [0]=run, [1]=enter step mode +#define SCU_STEP_N_OFFSET 0x0004U // W: write N → execute N DUT cycles, auto-stop +#define SCU_STATUS_OFFSET 0x0008U // R: [0]=idle, [1]=step_done +#define SCU_CYCLE_LO_OFFSET 0x000CU // R: cycle counter bits [31:0] +#define SCU_CYCLE_HI_OFFSET 0x0010U // R: cycle counter bits [63:32] +#define SCU_RESET_OFFSET 0x0014U // W: [0]=assert DUT reset (1=reset, 0=run) + +// ---- HBM2 address space (as seen by XDMA DMA engine) ---- +#define HBM2_BASE 0x000000000ULL // FPGA-internal HBM2 base address +#define HBM2_SIZE 0x100000000ULL // 4 GB (single pseudo-channel) + +// ---- SoC memory map (Rocket core physical address space) ---- +#define SOC_DRAM_BASE 0x080000000ULL // SoC DRAM starts here (physical) + +// Address translation: SoC physical → HBM2 DMA address +#define SOC_TO_HBM2(paddr) ((paddr) - SOC_DRAM_BASE + HBM2_BASE) + +// ---- XDMA device file paths ---- +// UART data comes from C2H channel 1 (channel 0 used for DMA) +#define XDMA_H2C_CHAN "/dev/xdma0_h2c_0" +#define XDMA_C2H_CHAN "/dev/xdma0_c2h_0" +#define XDMA_USER_BAR "/dev/xdma0_user" +#define XDMA_UART_C2H "/dev/xdma0_c2h_1" + +// ============================================================ +// XDMA device handle +// ============================================================ +struct PegasusXDMA { + int h2c_fd; // H2C DMA file descriptor (write to FPGA) + int c2h_fd; // C2H DMA file descriptor (read from FPGA) + int uart_fd; // C2H channel 1 (UART stream) + int bar_fd; // BAR0 mmap file descriptor + void *bar0_base; // mmap'd BAR0 base pointer + uint32_t bar0_size; // BAR0 size in bytes +}; + +// ============================================================ +// ELF information extracted from ELF file +// ============================================================ +struct ELFSegment { + uint64_t paddr; // SoC physical load address + uint64_t vaddr; // Virtual address (unused) + uint64_t filesz; // Bytes to copy from file + uint64_t memsz; // Bytes in memory (filesz ≤ memsz, zero-fill rest) + uint64_t offset; // Offset in ELF file +}; + +struct ELFInfo { + std::string path; + uint64_t entry; // Entry point (SoC physical) + uint64_t tohost_paddr; // SoC physical address of tohost symbol + uint64_t fromhost_paddr; // SoC physical address of fromhost symbol + std::vector segments; // PT_LOAD segments +}; + +// ============================================================ +// XDMA device open/close +// ============================================================ + +// Open XDMA device. +// dev_prefix: e.g. "/dev/xdma0" — appended with "_h2c_0", "_c2h_0", etc. +// Returns nullptr on failure. +PegasusXDMA *xdma_open(const char *dev_prefix = "/dev/xdma0"); +void xdma_close(PegasusXDMA *xdma); + +// ============================================================ +// BAR0 MMIO (32-bit registers) +// ============================================================ +void mmio_write32(PegasusXDMA *xdma, uint64_t offset, uint32_t val); +uint32_t mmio_read32(PegasusXDMA *xdma, uint64_t offset); + +// ============================================================ +// DMA read/write (pread/pwrite on /dev/xdma0_h2c_0 and c2h_0) +// ============================================================ + +// Write buf[0..len) to FPGA HBM2 at fpga_addr. +// fpga_addr is the DMA address (e.g., 0x0 for start of HBM2). +ssize_t dma_write(PegasusXDMA *xdma, uint64_t fpga_addr, const void *buf, size_t len); + +// Read len bytes from FPGA HBM2 at fpga_addr into buf. +ssize_t dma_read(PegasusXDMA *xdma, uint64_t fpga_addr, void *buf, size_t len); + +// ============================================================ +// SCU control +// ============================================================ + +// Assert DUT reset for ~10ms, then deassert. +void scu_reset(PegasusXDMA *xdma); + +// Start free-running DUT clock (CTRL[0]=1, CTRL[1]=0). +void scu_run(PegasusXDMA *xdma); + +// Halt DUT clock (CTRL[0]=0). +void scu_halt(PegasusXDMA *xdma); + +// Execute exactly n_cycles DUT clock cycles, then stop. +// Blocks until STATUS[1] (step_done) is set. +void scu_step(PegasusXDMA *xdma, uint32_t n_cycles); + +// Read current DUT cycle counter (64-bit). +uint64_t scu_read_cycles(PegasusXDMA *xdma); + +// ============================================================ +// UART polling +// ============================================================ + +// Non-blocking read from UART FIFO (XDMA C2H channel 1). +// Writes received bytes to stdout. Call repeatedly in a loop. +void uart_poll(PegasusXDMA *xdma); + +// ============================================================ +// ELF loading +// ============================================================ + +// Parse ELF file: extract LOAD segments and tohost/fromhost symbol addresses. +// Exits on fatal error (file not found, not a valid RISC-V ELF, etc.). +ELFInfo elf_parse(const char *elf_path); + +// Load all PT_LOAD segments from the parsed ELF into HBM2 via DMA. +// Address translation: SoC physical paddr → HBM2 DMA addr via SOC_TO_HBM2(). +void elf_load(PegasusXDMA *xdma, const ELFInfo *info); diff --git a/pegasus/driver/src/elf.cc b/pegasus/driver/src/elf.cc new file mode 100644 index 00000000..6c623d61 --- /dev/null +++ b/pegasus/driver/src/elf.cc @@ -0,0 +1,185 @@ +#include "pegasus.h" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// libelf headers +#include +#include + +// Parse an ELF file and return load segment info + tohost/fromhost symbol addresses +ELFInfo elf_parse(const char *elf_path) { + ELFInfo info; + info.path = elf_path; + info.entry = 0; + info.tohost_paddr = 0; + info.fromhost_paddr = 0; + + if (elf_version(EV_CURRENT) == EV_NONE) { + fprintf(stderr, "[pegasus] libelf init failed: %s\n", elf_errmsg(-1)); + exit(1); + } + + int fd = open(elf_path, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "[pegasus] Cannot open ELF: %s: %s\n", + elf_path, strerror(errno)); + exit(1); + } + + Elf *elf = elf_begin(fd, ELF_C_READ, nullptr); + if (!elf) { + fprintf(stderr, "[pegasus] elf_begin failed: %s\n", elf_errmsg(-1)); + close(fd); + exit(1); + } + + if (elf_kind(elf) != ELF_K_ELF) { + fprintf(stderr, "[pegasus] %s is not an ELF file\n", elf_path); + elf_end(elf); + close(fd); + exit(1); + } + + GElf_Ehdr ehdr; + if (!gelf_getehdr(elf, &ehdr)) { + fprintf(stderr, "[pegasus] gelf_getehdr failed: %s\n", elf_errmsg(-1)); + elf_end(elf); + close(fd); + exit(1); + } + + if (ehdr.e_machine != EM_RISCV) { + fprintf(stderr, "[pegasus] Warning: ELF machine type is not RISC-V (got %u)\n", + ehdr.e_machine); + } + + info.entry = ehdr.e_entry; + + // --- Walk program headers to find PT_LOAD segments --- + size_t phnum = 0; + elf_getphdrnum(elf, &phnum); + + for (size_t i = 0; i < phnum; i++) { + GElf_Phdr phdr; + if (!gelf_getphdr(elf, static_cast(i), &phdr)) continue; + if (phdr.p_type != PT_LOAD) continue; + if (phdr.p_filesz == 0) continue; + + ELFSegment seg; + seg.paddr = phdr.p_paddr; + seg.vaddr = phdr.p_vaddr; + seg.filesz = phdr.p_filesz; + seg.memsz = phdr.p_memsz; + seg.offset = phdr.p_offset; + info.segments.push_back(seg); + } + + // --- Walk symbol table for tohost / fromhost --- + Elf_Scn *scn = nullptr; + while ((scn = elf_nextscn(elf, scn)) != nullptr) { + GElf_Shdr shdr; + gelf_getshdr(scn, &shdr); + if (shdr.sh_type != SHT_SYMTAB && shdr.sh_type != SHT_DYNSYM) continue; + + Elf_Data *data = elf_getdata(scn, nullptr); + size_t sym_count = (data && shdr.sh_entsize) ? + data->d_size / shdr.sh_entsize : 0; + + for (size_t j = 0; j < sym_count; j++) { + GElf_Sym sym; + gelf_getsym(data, static_cast(j), &sym); + const char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); + if (!name) continue; + if (strcmp(name, "tohost") == 0) { + info.tohost_paddr = sym.st_value; + } else if (strcmp(name, "fromhost") == 0) { + info.fromhost_paddr = sym.st_value; + } + } + } + + elf_end(elf); + close(fd); + + if (info.segments.empty()) { + fprintf(stderr, "[pegasus] Warning: No PT_LOAD segments found in %s\n", elf_path); + } + if (info.tohost_paddr == 0) { + fprintf(stderr, "[pegasus] Warning: 'tohost' symbol not found in %s\n", elf_path); + } + + return info; +} + +// Load all PT_LOAD segments into FPGA HBM2 via DMA +// Address translation: SoC physical → HBM2 DMA address (subtract SOC_DRAM_BASE) +void elf_load(PegasusXDMA *xdma, const ELFInfo *info) { + // Open ELF file for raw reads + int fd = open(info->path.c_str(), O_RDONLY); + if (fd < 0) { + fprintf(stderr, "[pegasus] Cannot open ELF for loading: %s: %s\n", + info->path.c_str(), strerror(errno)); + exit(1); + } + + for (const auto &seg : info->segments) { + // Translate SoC physical address to HBM2 DMA address + if (seg.paddr < SOC_DRAM_BASE) { + fprintf(stderr, "[pegasus] Segment at 0x%" PRIx64 " is below SOC_DRAM_BASE " + "(0x%" PRIx64 ") — skipping\n", + seg.paddr, (uint64_t)SOC_DRAM_BASE); + continue; + } + uint64_t hbm2_addr = SOC_TO_HBM2(seg.paddr); + + fprintf(stderr, "[pegasus] Loading segment: SoC 0x%08" PRIx64 + " -> HBM2 0x%09" PRIx64 " (%" PRIu64 " bytes)\n", + seg.paddr, hbm2_addr, seg.filesz); + + // Read segment from ELF file + std::vector buf(seg.filesz); + ssize_t n = pread(fd, buf.data(), seg.filesz, + static_cast(seg.offset)); + if (n != static_cast(seg.filesz)) { + fprintf(stderr, "[pegasus] Short read from ELF (got %zd, expected %" PRIu64 ")\n", + n, seg.filesz); + close(fd); + exit(1); + } + + // DMA write to HBM2 + ssize_t written = dma_write(xdma, hbm2_addr, buf.data(), seg.filesz); + if (written != static_cast(seg.filesz)) { + fprintf(stderr, "[pegasus] DMA write failed at HBM2 0x%09" PRIx64 ": " + "wrote %zd of %" PRIu64 " bytes\n", + hbm2_addr, written, seg.filesz); + close(fd); + exit(1); + } + + // Zero-fill remaining memsz (BSS region) + if (seg.memsz > seg.filesz) { + size_t bss_size = seg.memsz - seg.filesz; + std::vector zeros(bss_size, 0); + uint64_t bss_addr = hbm2_addr + seg.filesz; + ssize_t w = dma_write(xdma, bss_addr, zeros.data(), bss_size); + if (w != static_cast(bss_size)) { + fprintf(stderr, "[pegasus] BSS zero-fill failed at HBM2 0x%09" PRIx64 "\n", + bss_addr); + } + } + } + + close(fd); + fprintf(stderr, "[pegasus] ELF loaded: entry=0x%" PRIx64 ", tohost=0x%" PRIx64 "\n", + info->entry, info->tohost_paddr); +} diff --git a/pegasus/driver/src/main.cc b/pegasus/driver/src/main.cc new file mode 100644 index 00000000..912674d1 --- /dev/null +++ b/pegasus/driver/src/main.cc @@ -0,0 +1,156 @@ +#include "pegasus.h" + +#include +#include +#include +#include +#include +#include +#include + +// ============================================================ +// Usage: +// pegasus-run Bare-metal: poll tohost, exit on done +// pegasus-run --linux Linux mode: forward UART, Ctrl+C to stop +// ============================================================ + +static volatile bool g_interrupted = false; + +static void sigint_handler(int) { + g_interrupted = true; +} + +static void print_usage(const char *argv0) { + fprintf(stderr, "Usage:\n"); + fprintf(stderr, " %s bare-metal mode (poll tohost)\n", argv0); + fprintf(stderr, " %s --linux Linux mode (UART only, Ctrl+C to exit)\n", argv0); +} + +int main(int argc, char **argv) { + if (argc < 2) { + print_usage(argv[0]); + return 1; + } + + bool linux_mode = false; + const char *elf_path = nullptr; + + if (argc >= 3 && strcmp(argv[1], "--linux") == 0) { + linux_mode = true; + elf_path = argv[2]; + } else if (argc >= 2 && argv[1][0] != '-') { + elf_path = argv[1]; + } else { + print_usage(argv[0]); + return 1; + } + + fprintf(stderr, "[pegasus] Mode: %s\n", linux_mode ? "Linux" : "bare-metal"); + fprintf(stderr, "[pegasus] ELF: %s\n", elf_path); + + // 1. Parse ELF + ELFInfo elf = elf_parse(elf_path); + + // 2. Open XDMA device + PegasusXDMA *xdma = xdma_open("/dev/xdma0"); + if (!xdma) { + fprintf(stderr, "[pegasus] Failed to open XDMA device\n"); + return 1; + } + + // 3. Reset DUT + fprintf(stderr, "[pegasus] Resetting DUT...\n"); + scu_reset(xdma); + + // 4. Load ELF into HBM2 + fprintf(stderr, "[pegasus] Loading ELF into HBM2...\n"); + elf_load(xdma, &elf); + + // 5. Start DUT (free-running) + fprintf(stderr, "[pegasus] Starting DUT...\n"); + scu_run(xdma); + + // 6. Run loop + signal(SIGINT, sigint_handler); + + if (linux_mode) { + // Linux mode: forward UART output until Ctrl+C + fprintf(stderr, "[pegasus] Linux mode running. Press Ctrl+C to stop.\n"); + while (!g_interrupted) { + uart_poll(xdma); + usleep(1000); // 1ms poll interval + } + fprintf(stderr, "\n[pegasus] Interrupted by user.\n"); + + } else { + // Bare-metal mode: poll tohost + forward UART + if (elf.tohost_paddr == 0) { + fprintf(stderr, "[pegasus] Warning: tohost not found in ELF; " + "cannot detect program exit. Running indefinitely.\n"); + while (!g_interrupted) { + uart_poll(xdma); + usleep(1000); + } + } else { + uint64_t tohost_hbm2 = SOC_TO_HBM2(elf.tohost_paddr); + uint64_t tohost_val = 0; + + while (tohost_val == 0 && !g_interrupted) { + uart_poll(xdma); + + ssize_t n = dma_read(xdma, tohost_hbm2, &tohost_val, sizeof(tohost_val)); + if (n != sizeof(tohost_val)) { + fprintf(stderr, "[pegasus] Warning: DMA read tohost returned %zd\n", n); + tohost_val = 0; + } + + // tohost format: + // bit0=1 → exit event: exit_code = tohost >> 1 + // bit0=0 → syscall request (e.g. printf → write syscall) + // respond by writing 1 to fromhost + if (tohost_val != 0 && (tohost_val & 1) == 0) { + // Syscall: acknowledge by writing 1 to fromhost + if (elf.fromhost_paddr != 0) { + uint64_t resp = 1; + uint64_t fromhost_hbm2 = SOC_TO_HBM2(elf.fromhost_paddr); + dma_write(xdma, fromhost_hbm2, &resp, sizeof(resp)); + } + tohost_val = 0; // Reset and keep polling + } + + if (tohost_val == 0) { + usleep(1000); // 1ms poll interval + } + } + + if (g_interrupted) { + fprintf(stderr, "\n[pegasus] Interrupted by user.\n"); + scu_halt(xdma); + xdma_close(xdma); + return 130; + } + + // Decode exit code + int exit_code = 0; + if ((tohost_val & 1) == 1) { + exit_code = static_cast((tohost_val >> 1) & 0x7FFFFFFF); + } + + if (exit_code == 0) { + fprintf(stderr, "[pegasus] Program exited successfully (exit code 0)\n"); + } else { + fprintf(stderr, "[pegasus] Program exited with code %d\n", exit_code); + } + + scu_halt(xdma); + uint64_t cycles = scu_read_cycles(xdma); + fprintf(stderr, "[pegasus] Total DUT cycles: %lu\n", cycles); + xdma_close(xdma); + return exit_code; + } + } + + scu_halt(xdma); + xdma_close(xdma); + return 0; +} diff --git a/pegasus/driver/src/scu.cc b/pegasus/driver/src/scu.cc new file mode 100644 index 00000000..9f2db268 --- /dev/null +++ b/pegasus/driver/src/scu.cc @@ -0,0 +1,49 @@ +#include "pegasus.h" + +#include +#include +#include + +// Assert DUT reset (high), hold for 10ms, then deassert (low) +void scu_reset(PegasusXDMA *xdma) { + mmio_write32(xdma, SCU_RESET_OFFSET, 1); // assert reset + usleep(10000); // hold 10ms + mmio_write32(xdma, SCU_RESET_OFFSET, 0); // deassert reset + usleep(1000); // settle 1ms +} + +// Start free-running DUT clock: CTRL[0]=1, CTRL[1]=0 +void scu_run(PegasusXDMA *xdma) { + mmio_write32(xdma, SCU_CTRL_OFFSET, 0x1); +} + +// Halt DUT clock: CTRL[0]=0 +void scu_halt(PegasusXDMA *xdma) { + mmio_write32(xdma, SCU_CTRL_OFFSET, 0x0); +} + +// Single-step: write STEP_N (enters step mode automatically), wait for step_done +void scu_step(PegasusXDMA *xdma, uint32_t n_cycles) { + if (n_cycles == 0) return; + // Write STEP_N: SCU enters step mode, starts counting + mmio_write32(xdma, SCU_STEP_N_OFFSET, n_cycles); + // Poll STATUS[1] (step_done) until set + while (true) { + uint32_t status = mmio_read32(xdma, SCU_STATUS_OFFSET); + if (status & 0x2) break; // step_done set + usleep(100); + } +} + +// Read current 64-bit DUT cycle counter +uint64_t scu_read_cycles(PegasusXDMA *xdma) { + // Read low first, then high — if high changes between reads, + // re-read until consistent (handles 32→64 bit rollover) + uint32_t lo, hi, hi2; + do { + hi = mmio_read32(xdma, SCU_CYCLE_HI_OFFSET); + lo = mmio_read32(xdma, SCU_CYCLE_LO_OFFSET); + hi2 = mmio_read32(xdma, SCU_CYCLE_HI_OFFSET); + } while (hi != hi2); + return (static_cast(hi) << 32) | lo; +} diff --git a/pegasus/driver/src/uart.cc b/pegasus/driver/src/uart.cc new file mode 100644 index 00000000..863c5487 --- /dev/null +++ b/pegasus/driver/src/uart.cc @@ -0,0 +1,17 @@ +#include "pegasus.h" + +#include +#include + +// Non-blocking UART poll: read bytes from XDMA C2H channel 1, write to stdout +void uart_poll(PegasusXDMA *xdma) { + if (xdma->uart_fd < 0) return; + + static char buf[4096]; + while (true) { + ssize_t n = read(xdma->uart_fd, buf, sizeof(buf)); + if (n <= 0) break; // EAGAIN or no data (non-blocking fd) + fwrite(buf, 1, static_cast(n), stdout); + fflush(stdout); + } +} diff --git a/pegasus/driver/src/xdma.cc b/pegasus/driver/src/xdma.cc new file mode 100644 index 00000000..bd7a5ccb --- /dev/null +++ b/pegasus/driver/src/xdma.cc @@ -0,0 +1,124 @@ +#include "pegasus.h" + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +// Open XDMA device files and mmap BAR0 +PegasusXDMA *xdma_open(const char *dev_prefix) { + auto *xdma = new PegasusXDMA(); + xdma->bar0_size = 0x1000; // 4 KB BAR0 for SCU registers + xdma->bar0_base = nullptr; + + std::string prefix(dev_prefix); + + // Open H2C (host-to-card, i.e., write to FPGA) + std::string h2c_path = prefix + "_h2c_0"; + xdma->h2c_fd = open(h2c_path.c_str(), O_WRONLY); + if (xdma->h2c_fd < 0) { + fprintf(stderr, "[pegasus] Failed to open %s: %s\n", + h2c_path.c_str(), strerror(errno)); + delete xdma; + return nullptr; + } + + // Open C2H (card-to-host, i.e., read from FPGA) + std::string c2h_path = prefix + "_c2h_0"; + xdma->c2h_fd = open(c2h_path.c_str(), O_RDONLY); + if (xdma->c2h_fd < 0) { + fprintf(stderr, "[pegasus] Failed to open %s: %s\n", + c2h_path.c_str(), strerror(errno)); + close(xdma->h2c_fd); + delete xdma; + return nullptr; + } + + // Open UART C2H stream (channel 1) + std::string uart_path = prefix + "_c2h_1"; + xdma->uart_fd = open(uart_path.c_str(), O_RDONLY | O_NONBLOCK); + if (xdma->uart_fd < 0) { + // Non-fatal: UART stream may not be configured + fprintf(stderr, "[pegasus] Warning: Failed to open UART stream %s: %s\n", + uart_path.c_str(), strerror(errno)); + xdma->uart_fd = -1; + } + + // Open and mmap BAR0 (user BAR for MMIO) + std::string bar_path = prefix + "_user"; + xdma->bar_fd = open(bar_path.c_str(), O_RDWR | O_SYNC); + if (xdma->bar_fd < 0) { + fprintf(stderr, "[pegasus] Failed to open BAR0 %s: %s\n", + bar_path.c_str(), strerror(errno)); + close(xdma->h2c_fd); + close(xdma->c2h_fd); + if (xdma->uart_fd >= 0) close(xdma->uart_fd); + delete xdma; + return nullptr; + } + + xdma->bar0_base = mmap(nullptr, xdma->bar0_size, + PROT_READ | PROT_WRITE, MAP_SHARED, + xdma->bar_fd, 0); + if (xdma->bar0_base == MAP_FAILED) { + fprintf(stderr, "[pegasus] Failed to mmap BAR0: %s\n", strerror(errno)); + close(xdma->h2c_fd); + close(xdma->c2h_fd); + if (xdma->uart_fd >= 0) close(xdma->uart_fd); + close(xdma->bar_fd); + delete xdma; + return nullptr; + } + + return xdma; +} + +void xdma_close(PegasusXDMA *xdma) { + if (!xdma) return; + if (xdma->bar0_base && xdma->bar0_base != MAP_FAILED) { + munmap(xdma->bar0_base, xdma->bar0_size); + } + if (xdma->bar_fd >= 0) close(xdma->bar_fd); + if (xdma->h2c_fd >= 0) close(xdma->h2c_fd); + if (xdma->c2h_fd >= 0) close(xdma->c2h_fd); + if (xdma->uart_fd >= 0) close(xdma->uart_fd); + delete xdma; +} + +// BAR0 MMIO (32-bit aligned reads/writes) +void mmio_write32(PegasusXDMA *xdma, uint64_t offset, uint32_t val) { + assert(xdma && xdma->bar0_base); + assert(offset + 4 <= xdma->bar0_size); + volatile uint32_t *reg = reinterpret_cast( + static_cast(xdma->bar0_base) + offset); + *reg = val; +} + +uint32_t mmio_read32(PegasusXDMA *xdma, uint64_t offset) { + assert(xdma && xdma->bar0_base); + assert(offset + 4 <= xdma->bar0_size); + volatile uint32_t *reg = reinterpret_cast( + static_cast(xdma->bar0_base) + offset); + return *reg; +} + +// DMA write: host → FPGA HBM2 via H2C channel +ssize_t dma_write(PegasusXDMA *xdma, uint64_t fpga_addr, + const void *buf, size_t len) { + assert(xdma && xdma->h2c_fd >= 0); + return pwrite(xdma->h2c_fd, buf, len, static_cast(fpga_addr)); +} + +// DMA read: FPGA HBM2 → host via C2H channel +ssize_t dma_read(PegasusXDMA *xdma, uint64_t fpga_addr, + void *buf, size_t len) { + assert(xdma && xdma->c2h_fd >= 0); + return pread(xdma->c2h_fd, buf, len, static_cast(fpga_addr)); +} diff --git a/pegasus/flake.lock b/pegasus/flake.lock new file mode 100644 index 00000000..38483124 --- /dev/null +++ b/pegasus/flake.lock @@ -0,0 +1,61 @@ +{ + "nodes": { + "flake-utils": { + "inputs": { + "systems": "systems" + }, + "locked": { + "lastModified": 1731533236, + "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=", + "owner": "numtide", + "repo": "flake-utils", + "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b", + "type": "github" + }, + "original": { + "owner": "numtide", + "repo": "flake-utils", + "type": "github" + } + }, + "nixpkgs": { + "locked": { + "lastModified": 1772963539, + "narHash": "sha256-9jVDGZnvCckTGdYT53d/EfznygLskyLQXYwJLKMPsZs=", + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "9dcb002ca1690658be4a04645215baea8b95f31d", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixos-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "root": { + "inputs": { + "flake-utils": "flake-utils", + "nixpkgs": "nixpkgs" + } + }, + "systems": { + "locked": { + "lastModified": 1681028828, + "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", + "owner": "nix-systems", + "repo": "default", + "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "type": "github" + }, + "original": { + "owner": "nix-systems", + "repo": "default", + "type": "github" + } + } + }, + "root": "root", + "version": 7 +} diff --git a/pegasus/flake.nix b/pegasus/flake.nix new file mode 100644 index 00000000..a8ab1a46 --- /dev/null +++ b/pegasus/flake.nix @@ -0,0 +1,89 @@ +{ + description = "Pegasus FPGA simulation framework for AU280 (Buckyball project)"; + + inputs = { + nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; + flake-utils.url = "github:numtide/flake-utils"; + }; + + outputs = { self, nixpkgs, flake-utils }: + flake-utils.lib.eachDefaultSystem (system: + let + pkgs = import nixpkgs { inherit system; }; + in + { + # nix develop — C++ driver build + Vivado environment + devShells.default = pkgs.mkShell { + name = "pegasus-dev"; + packages = with pkgs; [ + cmake + gcc + gnumake + pkg-config + libelf + python3 + python3Packages.pyelftools + git + ]; + shellHook = '' + for ver in 2024.1 2023.2 2022.2; do + if [ -f /tools/Xilinx/Vivado/$ver/settings64.sh ]; then + source /tools/Xilinx/Vivado/$ver/settings64.sh + echo "Vivado $ver loaded." + break + fi + done + echo "Pegasus dev shell ready." + echo " Build driver: cmake -B driver/build driver && cmake --build driver/build" + echo " Install XDMA: nix run .#install-xdma" + ''; + }; + + # nix build .#install-xdma — produces result/bin/install-xdma + # nix run .#install-xdma — build + run directly + # + # Clones XDMA sources and compiles against the *running* kernel at + # execution time, so the .ko matches whatever kernel the server has. + packages.install-xdma = pkgs.writeShellApplication { + name = "install-xdma"; + runtimeInputs = with pkgs; [ git gnumake gcc kmod ]; + text = '' + KERNEL=$(uname -r) + KBUILD=/lib/modules/$KERNEL/build + + if [ ! -d "$KBUILD" ]; then + echo "ERROR: Kernel headers not found at $KBUILD" + echo " Run: sudo apt install linux-headers-$KERNEL" + exit 1 + fi + + TMPDIR=$(mktemp -d) + trap "rm -rf $TMPDIR" EXIT + + echo "==> Cloning XDMA driver source..." + git clone https://github.com/joonho3020/dma_ip_drivers "$TMPDIR/src" + git -C "$TMPDIR/src" checkout ubuntu-24-xdma + + echo "==> Building against kernel $KERNEL..." + make -C "$TMPDIR/src/XDMA/linux-kernel/xdma" KERNELDIR="$KBUILD" + + echo "==> Installing (requires sudo)..." + sudo make -C "$TMPDIR/src/XDMA/linux-kernel/xdma" KERNELDIR="$KBUILD" install + sudo modprobe xdma + + echo "==> Verifying..." + if ls /dev/xdma* 2>/dev/null; then + echo "XDMA installed successfully!" + else + echo "Module loaded. No /dev/xdma* yet — connect AU280 and re-run: sudo modprobe xdma" + fi + ''; + }; + + apps.install-xdma = { + type = "app"; + program = "${pkgs.lib.getExe self.packages.${system}.install-xdma}"; + }; + } + ); +} diff --git a/pegasus/vivado/au280.xdc b/pegasus/vivado/au280.xdc new file mode 100644 index 00000000..7c9224d5 --- /dev/null +++ b/pegasus/vivado/au280.xdc @@ -0,0 +1,79 @@ +# Xilinx AU280 (xcu280-fsvh2892-2L-e) Pin and Timing Constraints +# For Pegasus FPGA simulation framework + +################################################################################ +# PCIe Interface (x16, connected to AU280 PCIe edge connector) +################################################################################ + +# PCIe reference clock (100 MHz differential, from PCIe slot) +set_property PACKAGE_PIN BF41 [get_ports pcie_sys_clk_p] +set_property PACKAGE_PIN BG41 [get_ports pcie_sys_clk_n] +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_sys_clk_p] + +# PCIe reset (active low, from PCIe slot) +set_property PACKAGE_PIN BJ44 [get_ports pcie_sys_rst_n] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_sys_rst_n] +set_property PULLUP true [get_ports pcie_sys_rst_n] +set_false_path -from [get_ports pcie_sys_rst_n] + +# PCIe TX/RX differential pairs (x16) +# Note: actual pin assignments depend on AU280 board schematic / Vivado auto-assign +# These are placeholders; real assignments come from xdma IP's XDC output +# set_property PACKAGE_PIN [get_ports {pcie_exp_txp[0]}] +# ... (x16 lanes, auto-assigned by XDMA IP) + +################################################################################ +# HBM2 Reference Clock (from MMCM or direct board clock) +################################################################################ + +# HBM2 cattrip override (required for AU280 to prevent thermal shutdown) +# Must be driven by MMCM output at 100 MHz +# set_property PACKAGE_PIN [get_ports hbm_cattrip] + +################################################################################ +# Main AXI Clock (250 MHz from XDMA IP axi_aclk output) +################################################################################ + +# The axi_aclk is generated inside XDMA IP — create a generated clock constraint +create_generated_clock -name axi_aclk \ + -source [get_pins xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O] \ + -multiply_by 1 \ + [get_pins xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O] + +################################################################################ +# DUT Clock (gated by SCU BUFGCE, derived from axi_aclk) +################################################################################ + +# The DUT clock is axi_aclk gated by BUFGCE. +# Vivado will automatically detect the BUFGCE hierarchy and propagate the clock. +# Add a multicycle path constraint since BUFGCE introduces enable-based gating. +set_multicycle_path -setup 1 \ + -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */bufgce/O}]] \ + -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */bufgce/O}]] + +################################################################################ +# False paths (async reset signals) +################################################################################ + +set_false_path -from [get_ports pcie_sys_rst_n] + +################################################################################ +# I/O Timing (set_input_delay / set_output_delay not needed for PCIe — XDMA IP handles it) +################################################################################ + +################################################################################ +# Placement hints +################################################################################ + +# Place XDMA IP near PCIe lanes (right side of AU280) +# Place HBM2 controller near HBM2 stacks (left side of AU280) +# These are Pblock suggestions; actual placement by Vivado + +################################################################################ +# Bitstream settings +################################################################################ + +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CFGBVS GND [current_design] diff --git a/pegasus/vivado/build.tcl b/pegasus/vivado/build.tcl new file mode 100644 index 00000000..b373401b --- /dev/null +++ b/pegasus/vivado/build.tcl @@ -0,0 +1,169 @@ +# Pegasus Vivado Build Script +# Synthesizes and implements the Pegasus FPGA design for AU280 +# +# Usage: +# vivado -mode batch -source build.tcl +# +# Prerequisites: +# 1. Run ElaboratePegasus to generate Verilog: +# cd arch && sbt "runMain sims.pegasus.ElaboratePegasus" +# Then copy generated/*.sv to ./generated/ +# 2. Vivado 2021.1+ must be installed and in PATH + +set PART xcu280-fsvh2892-2L-e +set TOP PegasusHarness +set PROJ_NAME pegasus_proj +set PROJ_DIR ./${PROJ_NAME} +set GEN_DIR ./generated +set IP_DIR ./ip +set XDC_FILE ./au280.xdc + +################################################################################ +# Step 1: Create project +################################################################################ + +create_project ${PROJ_NAME} ${PROJ_DIR} -part ${PART} -force + +# Set project properties +set_property target_language Verilog [current_project] +set_property simulator_language Mixed [current_project] + +################################################################################ +# Step 2: Create IPs +################################################################################ + +puts "==> Creating IP cores..." +source ${IP_DIR}/xdma_ip.tcl +source ${IP_DIR}/hbm2_ip.tcl +source ${IP_DIR}/axi_crossbar_ip.tcl + +# Synthesize IPs out-of-context so their netlists are available to synth_design +puts "==> Synthesizing IP cores (OOC)..." +set top_ips [list xdma_0 hbm_0 axi_crossbar_0 axi_dwidth_converter_0] +foreach ip_name $top_ips { + set ip [get_ips $ip_name -quiet] + if {$ip ne ""} { + puts " synth_ip: ${ip_name}" + synth_ip $ip + } +} + +# After synth_ip, exclude unisim/secureip library files from top-level synthesis +foreach f [get_files -filter {FILE_TYPE == "Verilog" && NAME =~ "*/unisim*"}] { + set_property USED_IN_SYNTHESIS false $f +} +foreach f [get_files -filter {FILE_TYPE == "Verilog" && NAME =~ "*/secureip*"}] { + set_property USED_IN_SYNTHESIS false $f +} +# Also exclude unisim_comp.v which is in scripts/rt/data/ +foreach f [get_files -filter {NAME =~ "*/scripts/rt/data/*"}] { + set_property USED_IN_SYNTHESIS false $f +} + +################################################################################ +# Step 3: Add generated Verilog sources +# Exclude simulation-only files: DPI-C wrappers, clock generators, IO cell models +################################################################################ + +# Patterns for simulation-only files to exclude from synthesis +set sim_only_patterns { + BackdoorGet* BackdoorPut* + *DPI.v *DPI.sv + ClockSource* EICG_wrapper* + GenericDigital*IOCell* +} + +proc is_sim_only {fname patterns} { + set base [file tail $fname] + foreach pat $patterns { + if {[string match $pat $base]} { return 1 } + } + return 0 +} + +puts "==> Adding Verilog sources (excluding simulation-only files)..." + +set sv_files [glob -nocomplain ${GEN_DIR}/*.sv] +set v_files [glob -nocomplain ${GEN_DIR}/*.v] + +set synth_files {} +foreach f [concat $sv_files $v_files] { + if {![is_sim_only $f $sim_only_patterns]} { + lappend synth_files $f + } else { + puts " skipping sim-only: [file tail $f]" + } +} + +if {[llength $synth_files] > 0} { + add_files $synth_files +} + +set_property top ${TOP} [current_fileset] + +################################################################################ +# Step 4: Add constraints +################################################################################ + +puts "==> Adding constraints..." +add_files -fileset constrs_1 ${XDC_FILE} + +################################################################################ +# Step 5: Synthesis +################################################################################ + +# Multi-threading + runtime-optimized strategy (256-core server) +set_param general.maxThreads 32 + +puts "==> Running synthesis..." +synth_design -top ${TOP} -part ${PART} \ + -flatten_hierarchy rebuilt \ + -gated_clock_conversion auto \ + -fsm_extraction one_hot \ + -directive RuntimeOptimized + +write_checkpoint -force ${PROJ_DIR}/post_synth.dcp +report_utilization -file ${PROJ_DIR}/utilization_synth.rpt + +################################################################################ +# Step 6: Implementation +################################################################################ + +puts "==> Optimizing design..." +opt_design -directive RuntimeOptimized + +puts "==> Placing design..." +place_design -directive RuntimeOptimized + +puts "==> Routing design..." +route_design -directive RuntimeOptimized + +# Post-implementation reports +write_checkpoint -force ${PROJ_DIR}/post_route.dcp +report_timing_summary -file ${PROJ_DIR}/timing_summary.rpt -warn_on_violation +report_utilization -file ${PROJ_DIR}/utilization_impl.rpt +report_power -file ${PROJ_DIR}/power.rpt + +# Check timing +if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { + puts "WARNING: Setup timing violations detected. Check timing_summary.rpt" + puts "WARNING: You may need to reduce PegasusConfig frequency and re-elaborate." +} else { + puts "INFO: Timing closure achieved." +} + +################################################################################ +# Step 7: Generate bitstream +################################################################################ + +puts "==> Generating bitstream..." +write_bitstream -force ${PROJ_DIR}/pegasus.bit + +puts "==> Build complete: ${PROJ_DIR}/pegasus.bit" +puts "" +puts "Next steps:" +puts " 1. Check timing_summary.rpt for actual Fmax" +puts " 2. If Fmax differs from 200 MHz, update PegasusConfig frequencies and re-elaborate" +puts " 3. Program FPGA: source scripts/program_fpga.sh" +puts " 4. Install XDMA driver: nix run .#install-xdma" +puts " 5. Run workload: pegasus-run ./workload.elf" diff --git a/pegasus/vivado/ip/axi_crossbar_ip.tcl b/pegasus/vivado/ip/axi_crossbar_ip.tcl new file mode 100644 index 00000000..3e845969 --- /dev/null +++ b/pegasus/vivado/ip/axi_crossbar_ip.tcl @@ -0,0 +1,37 @@ +# AXI Crossbar IP configuration +# 2 master ports (XDMA DMA + ChipTop ExtMem), 1 slave port (HBM2 PC0) +# Data width: 256-bit, address width: 33-bit, ID width: 6-bit, 250 MHz + +create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 \ + -module_name axi_crossbar_0 + +set_property -dict [list \ + CONFIG.NUM_SI {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.STRATEGY {1} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.ADDR_WIDTH {33} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \ + CONFIG.M00_A00_ADDR_WIDTH {33} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.WUSER_WIDTH {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ +] [get_ips axi_crossbar_0] + +generate_target all [get_ips axi_crossbar_0] + +# AXI Data Width Converter: 512-bit (XDMA) → 256-bit (HBM2/Crossbar) +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 \ + -module_name axi_dwidth_converter_0 + +set_property -dict [list \ + CONFIG.ADDR_WIDTH {33} \ + CONFIG.MI_DATA_WIDTH {256} \ + CONFIG.SI_DATA_WIDTH {512} \ + CONFIG.SI_ID_WIDTH {4} \ +] [get_ips axi_dwidth_converter_0] + +generate_target all [get_ips axi_dwidth_converter_0] diff --git a/pegasus/vivado/ip/hbm2_ip.tcl b/pegasus/vivado/ip/hbm2_ip.tcl new file mode 100644 index 00000000..892a90e0 --- /dev/null +++ b/pegasus/vivado/ip/hbm2_ip.tcl @@ -0,0 +1,31 @@ +# HBM2 IP configuration for AU280 (xcu280) +# Uses Stack 0, Pseudo-channel 0 only (MVP) +# AXI4 interface: 256-bit data, 33-bit address, 250 MHz +# Compatible with Vivado 2021.1 (HBM IP v1.0) + +create_ip -name hbm -vendor xilinx.com -library ip -version 1.0 \ + -module_name hbm_0 + +set_property -dict [list \ + CONFIG.USER_HBM_STACK {1} \ + CONFIG.USER_HBM_DENSITY {8GB} \ + CONFIG.USER_SINGLE_STACK_SELECTION {LEFT} \ + CONFIG.USER_SWITCH_ENABLE_00 {TRUE} \ + CONFIG.USER_SWITCH_ENABLE_01 {FALSE} \ + CONFIG.USER_MC_ENABLE_00 {TRUE} \ + CONFIG.USER_MC_ENABLE_01 {FALSE} \ + CONFIG.USER_MC_ENABLE_02 {FALSE} \ + CONFIG.USER_MC_ENABLE_03 {FALSE} \ + CONFIG.USER_MC_ENABLE_04 {FALSE} \ + CONFIG.USER_MC_ENABLE_05 {FALSE} \ + CONFIG.USER_MC_ENABLE_06 {FALSE} \ + CONFIG.USER_MC_ENABLE_07 {FALSE} \ + CONFIG.USER_AXI_CLK_FREQ {250} \ + CONFIG.USER_CLK_SEL_00 {FALSE} \ + CONFIG.USER_SAXI_00 {true} \ + CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {TRUE} \ + CONFIG.USER_MC0_LOOKAHEAD_PCH {TRUE} \ + CONFIG.USER_MC0_MAINTAIN_COHERENCY {TRUE} \ +] [get_ips hbm_0] + +generate_target all [get_ips hbm_0] diff --git a/pegasus/vivado/ip/xdma_ip.tcl b/pegasus/vivado/ip/xdma_ip.tcl new file mode 100644 index 00000000..86d630a0 --- /dev/null +++ b/pegasus/vivado/ip/xdma_ip.tcl @@ -0,0 +1,25 @@ +# XDMA PCIe IP configuration for AU280 +# PCIe x16 Gen3, AXI4 data width 512-bit, 250 MHz AXI clock +# AXI-Lite master (BAR0) + AXI4 DMA master + AXI-Stream C2H channel +# Compatible with Vivado 2021.1 (XDMA IP v4.1) + +create_ip -name xdma -vendor xilinx.com -library ip -version 4.1 \ + -module_name xdma_0 + +set_property -dict [list \ + CONFIG.pl_link_cap_max_link_width {X16} \ + CONFIG.pl_link_cap_max_link_speed {8.0_GT/s} \ + CONFIG.axi_data_width {512_bit} \ + CONFIG.axisten_freq {250} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {32} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_rnum_chnl {1} \ + CONFIG.xdma_wnum_chnl {1} \ + CONFIG.pf0_msix_cap_table_bir {BAR_1} \ + CONFIG.pf0_msix_cap_pba_bir {BAR_1} \ + CONFIG.dsc_bypass_rd {0000} \ + CONFIG.dsc_bypass_wr {0000} \ +] [get_ips xdma_0] + +generate_target all [get_ips xdma_0] diff --git a/pegasus/vivado/synth_only.tcl b/pegasus/vivado/synth_only.tcl new file mode 100644 index 00000000..cdb8d58c --- /dev/null +++ b/pegasus/vivado/synth_only.tcl @@ -0,0 +1,58 @@ +# Pegasus Synthesis-Only Script +# Assumes IP cores already created (pegasus_proj exists with IPs synthesized) +# +# Usage (from vivado/ directory): +# vivado -mode batch -source synth_only.tcl + +set PART xcu280-fsvh2892-2L-e +set TOP PegasusHarness +set PROJ_NAME pegasus_proj +set PROJ_DIR ./${PROJ_NAME} +set GEN_DIR ./generated + +# Open existing project +open_project ${PROJ_DIR}/${PROJ_NAME}.xpr + +# Replace user RTL sources (keep IP files intact) +set old_rtl [get_files -quiet -filter {NAME =~ "*/generated/*"}] +if {[llength $old_rtl] > 0} { + remove_files $old_rtl +} + +# Patterns for simulation-only files +proc is_sim_only {fname} { + set base [file tail $fname] + foreach pat {BackdoorGet* BackdoorPut* *DPI.v *DPI.sv ClockSource* EICG_wrapper* GenericDigital*IOCell*} { + if {[string match $pat $base]} { return 1 } + } + return 0 +} + +set synth_files {} +foreach f [concat [glob -nocomplain ${GEN_DIR}/*.sv] [glob -nocomplain ${GEN_DIR}/*.v]] { + if {![is_sim_only $f]} { + lappend synth_files $f + } else { + puts " skipping sim-only: [file tail $f]" + } +} +if {[llength $synth_files] > 0} { add_files $synth_files } +set_property top ${TOP} [current_fileset] + +# Lock IP OOC runs so synth_design uses their DCPs directly +foreach run [get_runs -filter {IS_SYNTHESIS == 1 && NAME != "synth_1"}] { + set_property IS_ENABLED false $run +} + +set_param general.maxThreads 32 + +puts "==> Running synthesis..." +synth_design -top ${TOP} -part ${PART} \ + -flatten_hierarchy rebuilt \ + -gated_clock_conversion auto \ + -fsm_extraction one_hot \ + -directive RuntimeOptimized + +write_checkpoint -force ${PROJ_DIR}/post_synth.dcp +report_utilization -file ${PROJ_DIR}/utilization_synth.rpt +puts "==> Synthesis complete: ${PROJ_DIR}/post_synth.dcp" From 33446c56ca051ca3f34db8dab38eac7cef4da7d6 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 12:09:44 +0800 Subject: [PATCH 166/238] [arch] fix: update mmio_tick to debounce wFire signal and adjust clock handling in BBSimHarness --- arch/src/csrc/src/monitor/ioe/mmio.cc | 23 ++- .../scala/examples/goban/CustomConfigs.scala | 24 ++- .../scala/examples/toy/CustomConfigs.scala | 22 +- .../balldomain/prototype/trace/Trace.scala | 55 ++--- .../prototype/trace/TraceBall.scala | 14 +- .../balldomain/prototype/trace/TraceDPI.scala | 42 ++-- .../scala/framework/core/bbtile/BBTile.scala | 14 +- .../framework/core/bbtile/BarrierUnit.scala | 5 +- .../core/bbtile/BuckyballAccelerator.scala | 6 +- .../scala/framework/frontend/Frontend.scala | 4 +- .../globalrs/GlobalReservationStation.scala | 4 +- .../scala/framework/memdomain/MemDomain.scala | 14 +- .../framework/memdomain/backend/MTrace.scala | 18 +- .../memdomain/backend/MemBackend.scala | 8 +- .../privatepath/PrivateMemBackend.scala | 36 ++-- .../memdomain/backend/shared/SharedMem.scala | 8 +- .../backend/shared/SharedMemBackend.scala | 50 +++-- .../frontend/cmd_channel/decoder/DISA.scala | 6 +- .../cmd_channel/decoder/DomainDecoder.scala | 8 +- .../outside_channel/MemConfiger.scala | 52 ++--- .../frontend/outside_channel/MemLoader.scala | 2 +- .../frontend/outside_channel/MemStorer.scala | 2 +- .../memdomain/midend/MemMidend.scala | 2 +- .../scala/sims/pegasus/PegasusHarness.scala | 15 +- .../sims/pegasus/PegasusHarnessBinders.scala | 93 +++++---- .../scala/sims/pegasus/TargetConfigs.scala | 27 +-- .../scala/sims/verilator/BBSimHarness.scala | 190 +++++++++--------- 27 files changed, 393 insertions(+), 351 deletions(-) diff --git a/arch/src/csrc/src/monitor/ioe/mmio.cc b/arch/src/csrc/src/monitor/ioe/mmio.cc index fd871abc..8ecca972 100644 --- a/arch/src/csrc/src/monitor/ioe/mmio.cc +++ b/arch/src/csrc/src/monitor/ioe/mmio.cc @@ -1,12 +1,12 @@ #include "ioe/mmio.h" #include "bdb.h" -#include #include +#include #include #define SIM_EXIT_ADDR 0x60000000ULL -#define UART_TX_ADDR 0x60020000ULL +#define UART_TX_ADDR 0x60020000ULL static FILE *uart_fp = nullptr; @@ -25,18 +25,27 @@ static void uart_putchar(char ch) { } // Called once per posedge after eval(). -// io_mmio_fire is a 1-cycle pulse (harness clock domain = C++ sampling clock). +// wFire is combinational and may stay high for multiple cycles if the AXI4 +// master holds W valid. De-bounce on the rising edge (0→1 transition). void mmio_tick() { - if (!top->io_mmio_fire) return; + static uint8_t prev_fire = 0; + uint8_t cur_fire = top->io_mmio_fire ? 1 : 0; + bool rising = (!prev_fire && cur_fire); + prev_fire = cur_fire; + if (!rising) + return; uint64_t addr = top->io_mmio_fire_addr; uint64_t data = top->io_mmio_fire_data; if (addr == SIM_EXIT_ADDR) { int code = (int)(data & 0xFFFFFFFF); - if (code == 0) fprintf(stderr, "[MMIO] simulation success\n"); - else fprintf(stderr, "[MMIO] simulation exit code %d\n", code); - if (uart_fp) fclose(uart_fp); + if (code == 0) + fprintf(stderr, "[MMIO] simulation success\n"); + else + fprintf(stderr, "[MMIO] simulation exit code %d\n", code); + if (uart_fp) + fclose(uart_fp); sim_exit(); } else if (addr == UART_TX_ADDR) { uart_putchar((char)(data & 0xFF)); diff --git a/arch/src/main/scala/examples/goban/CustomConfigs.scala b/arch/src/main/scala/examples/goban/CustomConfigs.scala index 81b635ca..578e6c57 100644 --- a/arch/src/main/scala/examples/goban/CustomConfigs.scala +++ b/arch/src/main/scala/examples/goban/CustomConfigs.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.subsystem.InSubsystem * The ISA, Ball operators, and memory layout are identical to the toy configuration. */ object GobanConfig { + /** Number of cores inside each BBTile. */ val nCores: Int = 4 @@ -23,18 +24,21 @@ object GobanConfig { val base = GlobalConfig() base.copy(top = base.top.copy(nCores = nCores)) } + } /** 1 BBTile × 4 cores (4 Rocket + 4 Buckyball, shared SharedMem + BarrierUnit) */ -class BuckyballGobanConfig extends Config( - new WithNBBTiles(1, buckyballConfig = GobanConfig()) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig -) +class BuckyballGobanConfig + extends Config( + new WithNBBTiles(1, buckyballConfig = GobanConfig()) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) /** 2 BBTiles × 4 cores = 8 total cores */ -class BuckyballGoban2TileConfig extends Config( - new WithNBBTiles(2, buckyballConfig = GobanConfig()) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig -) +class BuckyballGoban2TileConfig + extends Config( + new WithNBBTiles(2, buckyballConfig = GobanConfig()) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 6fad1be9..13bcd042 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -13,18 +13,20 @@ import constellation.noc._ import scala.collection.immutable.ListMap /** Single BBTile: 1 Rocket core + 1 Buckyball accelerator */ -class BuckyballToyConfig extends Config( - new WithNBBTiles(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig -) +class BuckyballToyConfig + extends Config( + new WithNBBTiles(1) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) /** Single Rocket core only (no Buckyball) */ -class RocketOnlyConfig extends Config( - new WithNBBTiles(1, withBuckyball = false) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig -) +class RocketOnlyConfig + extends Config( + new WithNBBTiles(1, withBuckyball = false) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) // Increase BootROM size for large core counts class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala index 374d6f3d..a87ea846 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala @@ -8,25 +8,28 @@ import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} import framework.memdomain.backend.banks.SramBank import framework.top.GlobalConfig -/** Trace — TraceBall inner processing unit. - * - * Handles two instruction types: - * - bdb_counter (funct7=48): cycle counter management (START/STOP/READ) - * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C - * - * Backdoor write: C++ generates (row, data) via DPI-C each iteration, - * RTL writes to external bank at (wbank_reg, row). - * Backdoor read: RTL reads external bank at (rbank_reg, row from DPI-C), - * sends data back to C++ via DPI-C for logging. - * - * bank_id always comes from the instruction encoding (rs1), - * row and data come from DPI-C (C++ auto-increments row each call). - */ +/** + * Trace — TraceBall inner processing unit. + * + * Handles two instruction types: + * - bdb_counter (funct7=48): cycle counter management (START/STOP/READ) + * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C + * + * Backdoor write: C++ generates (row, data) via DPI-C each iteration, + * RTL writes to external bank at (wbank_reg, row). + * Backdoor read: RTL reads external bank at (rbank_reg, row from DPI-C), + * sends data back to C++ via DPI-C for logging. + * + * bank_id always comes from the instruction encoding (rs1), + * row and data come from DPI-C (C++ auto-increments row each call). + */ @instantiable class Trace(val b: GlobalConfig) extends Module { + val ballMapping = b.ballDomain.ballIdMappings .find(_.ballName == "TraceBall") .getOrElse(throw new IllegalArgumentException("TraceBall not found in config")) + val inBW = ballMapping.inBW val outBW = ballMapping.outBW @@ -55,7 +58,7 @@ class Trace(val b: GlobalConfig) extends Module { // ============================================================ val idle :: sCounter :: sBdReadExt :: sBdReadExtResp :: sBdGetWriteData :: sBdWriteExt :: sBdWriteExtResp :: complete :: Nil = Enum(8) - val state = RegInit(idle) + val state = RegInit(idle) // ============================================================ // Registers @@ -95,9 +98,9 @@ class Trace(val b: GlobalConfig) extends Module { val privBank = Module(new SramBank(b)) // Default: private bank idle - privBank.io.sramRead.req.valid := false.B - privBank.io.sramRead.req.bits.addr := 0.U - privBank.io.sramRead.resp.ready := false.B + privBank.io.sramRead.req.valid := false.B + privBank.io.sramRead.req.bits.addr := 0.U + privBank.io.sramRead.resp.ready := false.B privBank.io.sramWrite.req.valid := false.B privBank.io.sramWrite.req.bits.addr := 0.U privBank.io.sramWrite.req.bits.data := 0.U @@ -142,20 +145,20 @@ class Trace(val b: GlobalConfig) extends Module { // External bank port defaults // ============================================================ for (i <- 0 until inBW) { - io.bankRead(i).rob_id := rob_id_reg - io.bankRead(i).ball_id := 0.U - io.bankRead(i).bank_id := rbank_reg - io.bankRead(i).group_id := 0.U + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).group_id := 0.U io.bankRead(i).io.req.valid := false.B io.bankRead(i).io.req.bits.addr := 0.U io.bankRead(i).io.resp.ready := false.B } for (i <- 0 until outBW) { - io.bankWrite(i).rob_id := rob_id_reg - io.bankWrite(i).ball_id := 0.U - io.bankWrite(i).bank_id := wbank_reg - io.bankWrite(i).group_id := 0.U + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).group_id := 0.U io.bankWrite(i).io.req.valid := false.B io.bankWrite(i).io.req.bits.addr := 0.U io.bankWrite(i).io.req.bits.data := 0.U diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala index fd38a514..9c9d6cad 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala @@ -6,18 +6,20 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} import framework.top.GlobalConfig -/** TraceBall — Debug trace Ball providing cycle counters and SRAM backdoor. - * - * Uses two funct7 encodings: - * - bdb_counter (funct7=48): cycle counter management - * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C - */ +/** + * TraceBall — Debug trace Ball providing cycle counters and SRAM backdoor. + * + * Uses two funct7 encodings: + * - bdb_counter (funct7=48): cycle counter management + * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C + */ @instantiable class TraceBall(val b: GlobalConfig) extends Module with HasBlink { val ballCommonConfig = b.ballDomain.ballIdMappings .find(_.ballName == "TraceBall") .getOrElse(throw new IllegalArgumentException("TraceBall not found in config")) + val inBW = ballCommonConfig.inBW val outBW = ballCommonConfig.outBW diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala index 3bd7e1aa..79d6327e 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala @@ -3,9 +3,10 @@ package framework.balldomain.prototype.trace import chisel3._ import chisel3.util._ -/** DPI-C BlackBox for cycle counter trace. - * Outputs [CTRACE] lines to bdb.log. - */ +/** + * DPI-C BlackBox for cycle counter trace. + * Outputs [CTRACE] lines to bdb.log. + */ class CTraceDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { @@ -46,9 +47,10 @@ class CTraceDPI extends BlackBox with HasBlackBoxInline { ) } -/** DPI-C BlackBox for backdoor get_read_addr. - * Returns packed [63:32]=bank_id, [31:0]=row. - */ +/** + * DPI-C BlackBox for backdoor get_read_addr. + * Returns packed [63:32]=bank_id, [31:0]=row. + */ class BackdoorGetReadAddrDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { @@ -78,9 +80,10 @@ class BackdoorGetReadAddrDPI extends BlackBox with HasBlackBoxInline { ) } -/** DPI-C BlackBox for backdoor get_write_addr. - * Returns packed [63:32]=bank_id, [31:0]=row. - */ +/** + * DPI-C BlackBox for backdoor get_write_addr. + * Returns packed [63:32]=bank_id, [31:0]=row. + */ class BackdoorGetWriteAddrDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { @@ -110,9 +113,10 @@ class BackdoorGetWriteAddrDPI extends BlackBox with HasBlackBoxInline { ) } -/** DPI-C BlackBox for backdoor get_write_data. - * Returns 128-bit data as two 64-bit outputs. - */ +/** + * DPI-C BlackBox for backdoor get_write_data. + * Returns 128-bit data as two 64-bit outputs. + */ class BackdoorGetWriteDataDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { @@ -150,9 +154,10 @@ class BackdoorGetWriteDataDPI extends BlackBox with HasBlackBoxInline { ) } -/** DPI-C BlackBox for backdoor put_read_data. - * Reports read data back to C++ for logging. - */ +/** + * DPI-C BlackBox for backdoor put_read_data. + * Reports read data back to C++ for logging. + */ class BackdoorPutReadDataDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { @@ -190,9 +195,10 @@ class BackdoorPutReadDataDPI extends BlackBox with HasBlackBoxInline { ) } -/** DPI-C BlackBox for backdoor put_write_done. - * Reports write completion back to C++ for logging. - */ +/** + * DPI-C BlackBox for backdoor put_write_done. + * Reports write completion back to C++ for logging. + */ class BackdoorPutWriteDoneDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index 37b4dbdf..0cc82421 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -122,14 +122,16 @@ class BBTile private ( if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = s"bb-dma-reader-$i", sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) - )))))) else None + )))))) + else None } val bb_writer_nodes: Seq[Option[TLClientNode]] = (0 until nCores).map { i => if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = s"bb-dma-writer-$i", sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) - )))))) else None + )))))) + else None } // Gather all DMA nodes into one xbar @@ -361,7 +363,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC val accelerators = (0 until nCores).map { i => val (tl_reader, edge) = outer.bb_reader_nodes(i).get.out(0) val (tl_writer, _) = outer.bb_writer_nodes(i).get.out(0) - val acc = Module(new BuckyballAccelerator(outer.bbConfig)(edge)) + val acc = Module(new BuckyballAccelerator(outer.bbConfig)(edge)) acc.io.hartid := outer.hartIdSinkNode.bundle + i.U // DMA TileLink @@ -421,7 +423,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC // Shared query — simplified: each accelerator queries independently, // but SharedMemBackend has one query port. Use accelerator 0's for now. - sharedBackend.io.query_vbank_id := accelerators(0).io.shared_query_vbank_id + sharedBackend.io.query_vbank_id := accelerators(0).io.shared_query_vbank_id accelerators(0).io.shared_query_group_count := sharedBackend.io.query_group_count for (i <- 1 until nCores) { accelerators(i).io.shared_query_group_count := sharedBackend.io.query_group_count @@ -430,8 +432,8 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC // BarrierUnit (tile-level singleton) val barrierUnit = Module(new BarrierUnit(nCores)) for (i <- 0 until nCores) { - barrierUnit.io.arrive(i) := accelerators(i).io.barrier_arrive - accelerators(i).io.barrier_release := barrierUnit.io.release(i) + barrierUnit.io.arrive(i) := accelerators(i).io.barrier_arrive + accelerators(i).io.barrier_release := barrierUnit.io.release(i) } } else { diff --git a/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala b/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala index 40d8a152..63f7ea19 100644 --- a/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala +++ b/arch/src/main/scala/framework/core/bbtile/BarrierUnit.scala @@ -14,6 +14,7 @@ import chisel3.experimental.hierarchy.{instantiable, public} */ @instantiable class BarrierUnit(val nCores: Int) extends Module { + @public val io = IO(new Bundle { val arrive = Input(Vec(nCores, Bool())) @@ -24,8 +25,8 @@ class BarrierUnit(val nCores: Int) extends Module { val allArrived = arrived.asUInt.andR for (i <- 0 until nCores) { - when(io.arrive(i)) { arrived(i) := true.B } - io.release(i) := allArrived + when(io.arrive(i))(arrived(i) := true.B) + io.release(i) := allArrived } when(allArrived) { diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index 1189694b..71dcfed2 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -140,12 +140,12 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module // --- Shared memory passthrough --- io.shared_mem_req <> memDomain.io.shared_mem_req - io.shared_config <> memDomain.io.shared_config - io.shared_query_vbank_id := memDomain.io.shared_query_vbank_id + io.shared_config <> memDomain.io.shared_config + io.shared_query_vbank_id := memDomain.io.shared_query_vbank_id memDomain.io.shared_query_group_count := io.shared_query_group_count // --- Barrier passthrough --- - io.barrier_arrive := frontend.io.barrier_arrive + io.barrier_arrive := frontend.io.barrier_arrive frontend.io.barrier_release := io.barrier_release // --- Response & status --- diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala index bf406de2..43d529e7 100644 --- a/arch/src/main/scala/framework/frontend/Frontend.scala +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -62,7 +62,7 @@ class Frontend(val b: GlobalConfig) extends Module { io.busy := globalRs.io.rs_rocc_o.busy // Barrier passthrough - io.barrier_arrive := globalRs.io.barrier_arrive - globalRs.io.barrier_release := io.barrier_release + io.barrier_arrive := globalRs.io.barrier_arrive + globalRs.io.barrier_release := io.barrier_release } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 3966cf64..1a6c830c 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -110,8 +110,8 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { // normal cmds wait for ROB ready and no stall. io.global_decode_cmd_i.ready := Mux( isFrontendCmd, - !anyStall, // Accept fence/barrier if no stall active - rob.io.alloc.ready && !anyStall // Normal cmd: ROB ready and no stall + !anyStall, // Accept fence/barrier if no stall active + rob.io.alloc.ready && !anyStall // Normal cmd: ROB ready and no stall ) // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 619c964e..75c0737f 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -40,18 +40,18 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ------------------------------------------------- // Outside Channel // ------------------------------------------------- - val ptw = Vec(1, new BBTLBPTWIO(b)) - val tlbExp = Vec(1, new BBTLBExceptionIO) + val ptw = Vec(1, new BBTLBPTWIO(b)) + val tlbExp = Vec(1, new BBTLBExceptionIO) val tl_reader = new TLBundle(edge.bundle) val tl_writer = new TLBundle(edge.bundle) - val hartid = Input(UInt(b.core.xLen.W)) + val hartid = Input(UInt(b.core.xLen.W)) // ------------------------------------------------- // Shared memory path — exposed for tile-level sharing // ------------------------------------------------- - val shared_mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) - val shared_config = Decoupled(new MemConfigerIO(b)) - val shared_query_vbank_id = Output(UInt(8.W)) + val shared_mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + val shared_config = Decoupled(new MemConfigerIO(b)) + val shared_query_vbank_id = Output(UInt(8.W)) val shared_query_group_count = Input(UInt(4.W)) }) @@ -96,5 +96,5 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // Shared path passthrough io.shared_mem_req <> backend.io.shared_mem_req - io.shared_config <> backend.io.shared_config + io.shared_config <> backend.io.shared_config } diff --git a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala index 5bb86328..769d0677 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala @@ -7,16 +7,16 @@ import chisel3.util._ class MTraceDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { - val is_write = Input(UInt(8.W)) + val is_write = Input(UInt(8.W)) val is_shared = Input(UInt(8.W)) - val channel = Input(UInt(32.W)) - val hart_id = Input(UInt(64.W)) - val vbank_id = Input(UInt(32.W)) - val group_id = Input(UInt(32.W)) - val addr = Input(UInt(32.W)) - val data_lo = Input(UInt(64.W)) - val data_hi = Input(UInt(64.W)) - val enable = Input(Bool()) + val channel = Input(UInt(32.W)) + val hart_id = Input(UInt(64.W)) + val vbank_id = Input(UInt(32.W)) + val group_id = Input(UInt(32.W)) + val addr = Input(UInt(32.W)) + val data_lo = Input(UInt(64.W)) + val data_hi = Input(UInt(64.W)) + val enable = Input(Bool()) }) setInline( diff --git a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala index f49f9bd2..fc71fc6d 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MemBackend.scala @@ -48,10 +48,10 @@ class MemBackend(val b: GlobalConfig) extends Module { // Track whether a vbank is currently allocated in shared backend. // Ball requests do not carry explicit shared/private info, so they are routed by this table. - private val vbankIdxWidth = log2Up(b.memDomain.bankNum) - val privateAllocByVbank = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) - val sharedAllocByVbank = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) - val cfgVbankIdx = io.config.bits.vbank_id(vbankIdxWidth - 1, 0) + private val vbankIdxWidth = log2Up(b.memDomain.bankNum) + val privateAllocByVbank = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) + val sharedAllocByVbank = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(false.B))) + val cfgVbankIdx = io.config.bits.vbank_id(vbankIdxWidth - 1, 0) when(io.config.fire) { when(io.config.bits.alloc) { when(io.config.bits.is_shared) { diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index 35d34a06..389616a9 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -28,16 +28,16 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { // Per-channel memory trace DPI-C modules to avoid losing simultaneous events val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) for (mt <- mtraces) { - mt.io.is_write := 0.U + mt.io.is_write := 0.U mt.io.is_shared := 0.U - mt.io.channel := 0.U - mt.io.hart_id := 0.U - mt.io.vbank_id := 0.U - mt.io.group_id := 0.U - mt.io.addr := 0.U - mt.io.data_lo := 0.U - mt.io.data_hi := 0.U - mt.io.enable := false.B + mt.io.channel := 0.U + mt.io.hart_id := 0.U + mt.io.vbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B } // ----------------------------------------------------------------------------- @@ -156,16 +156,16 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { dataHi: UInt, en: Bool ): Unit = { - mtraces(ch).io.is_write := isWrite + mtraces(ch).io.is_write := isWrite mtraces(ch).io.is_shared := io.mem_req(ch).is_shared.asUInt - mtraces(ch).io.channel := ch.U - mtraces(ch).io.hart_id := io.mem_req(ch).hart_id - mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id - mtraces(ch).io.group_id := io.mem_req(ch).group_id - mtraces(ch).io.addr := addr - mtraces(ch).io.data_lo := dataLo - mtraces(ch).io.data_hi := dataHi - mtraces(ch).io.enable := en + mtraces(ch).io.channel := ch.U + mtraces(ch).io.hart_id := io.mem_req(ch).hart_id + mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.group_id := io.mem_req(ch).group_id + mtraces(ch).io.addr := addr + mtraces(ch).io.data_lo := dataLo + mtraces(ch).io.data_hi := dataHi + mtraces(ch).io.enable := en } for (i <- 0 until b.memDomain.bankChannel) { diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala index ca329a81..81caefc9 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMem.scala @@ -7,11 +7,11 @@ import framework.top.GlobalConfig import framework.memdomain.backend.banks.{SramReadResp, SramWriteResp} object SharedMemLayout { - def bankPerHart(b: GlobalConfig): Int = b.memDomain.bankNum - def maxHart(b: GlobalConfig): Int = b.top.nCores - def totalBank(b: GlobalConfig): Int = bankPerHart(b) * maxHart(b) + def bankPerHart(b: GlobalConfig): Int = b.memDomain.bankNum + def maxHart(b: GlobalConfig): Int = b.top.nCores + def totalBank(b: GlobalConfig): Int = bankPerHart(b) * maxHart(b) def channelPerHart(b: GlobalConfig): Int = b.memDomain.bankChannel - def totalChannel(b: GlobalConfig): Int = channelPerHart(b) * maxHart(b) + def totalChannel(b: GlobalConfig): Int = channelPerHart(b) * maxHart(b) } class SharedMemReadReq(val b: GlobalConfig) extends Bundle { diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index dcae7e74..c93da78e 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -31,16 +31,16 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { // Per-channel memory trace DPI-C modules to avoid losing simultaneous events val mtraces = Seq.fill(totalChannel)(Module(new MTraceDPI)) for (mt <- mtraces) { - mt.io.is_write := 0.U + mt.io.is_write := 0.U mt.io.is_shared := 0.U - mt.io.channel := 0.U - mt.io.hart_id := 0.U - mt.io.vbank_id := 0.U - mt.io.group_id := 0.U - mt.io.addr := 0.U - mt.io.data_lo := 0.U - mt.io.data_hi := 0.U - mt.io.enable := false.B + mt.io.channel := 0.U + mt.io.hart_id := 0.U + mt.io.vbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B } // ----------------------------------------------------------------------------- @@ -57,10 +57,12 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { val mappingTable = RegInit(VecInit(Seq.fill(totalBanks)(0.U.asTypeOf(new MappingTableEntry)))) def isAcc(hart_id: UInt, vbank_id: UInt): Bool = - mappingTable.map(entry => entry.valid && (entry.vbank_id === vbank_id) && (entry.hart_id === hart_id) && entry.is_multi).reduce(_ || _) + mappingTable.map(entry => + entry.valid && (entry.vbank_id === vbank_id) && (entry.hart_id === hart_id) && entry.is_multi + ).reduce(_ || _) def addEntry( - hart_id: UInt, + hart_id: UInt, vbank_id: UInt, pbank_id: UInt, is_multi: Bool, @@ -134,7 +136,13 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { when(io.config.valid) { when(io.config.bits.alloc) { val pbank_id = getFreePbankId() - addEntry(io.config.bits.hart_id, io.config.bits.vbank_id, pbank_id, io.config.bits.is_multi, io.config.bits.group_id) + addEntry( + io.config.bits.hart_id, + io.config.bits.vbank_id, + pbank_id, + io.config.bits.is_multi, + io.config.bits.group_id + ) }.otherwise { deleteEntry(io.config.bits.hart_id, io.config.bits.vbank_id) } @@ -162,16 +170,16 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { dataHi: UInt, en: Bool ): Unit = { - mtraces(ch).io.is_write := isWrite + mtraces(ch).io.is_write := isWrite mtraces(ch).io.is_shared := io.mem_req(ch).is_shared.asUInt - mtraces(ch).io.channel := ch.U - mtraces(ch).io.hart_id := io.mem_req(ch).hart_id - mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id - mtraces(ch).io.group_id := io.mem_req(ch).group_id - mtraces(ch).io.addr := addr - mtraces(ch).io.data_lo := dataLo - mtraces(ch).io.data_hi := dataHi - mtraces(ch).io.enable := en + mtraces(ch).io.channel := ch.U + mtraces(ch).io.hart_id := io.mem_req(ch).hart_id + mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.group_id := io.mem_req(ch).group_id + mtraces(ch).io.addr := addr + mtraces(ch).io.data_lo := dataLo + mtraces(ch).io.data_hi := dataHi + mtraces(ch).io.enable := en } for (i <- 0 until totalChannel) { diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index 886ee16c..bbe01ab3 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -5,7 +5,7 @@ import chisel3.util._ object DISA { - val MSET_BITPAT = BitPat("b0010111") // 23 - val MVIN_BITPAT = BitPat("b0011000") // 24 - val MVOUT_BITPAT = BitPat("b0011001") // 25 + val MSET_BITPAT = BitPat("b0010111") // 23 + val MVIN_BITPAT = BitPat("b0011000") // 24 + val MVOUT_BITPAT = BitPat("b0011001") // 25 } diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index 46f87b70..6aeeb0e1 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -73,7 +73,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { func7, ls_default_decode, Array( - MSET_BITPAT -> List( + MSET_BITPAT -> List( N, N, 0.U(memAddrLen.W), // mem_addr: not used for MSET @@ -81,7 +81,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs2, // special = full rs2 Y ), // mset - MVIN_BITPAT -> List( + MVIN_BITPAT -> List( Y, N, rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] @@ -89,14 +89,14 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { rs2, // special = full rs2 Y ), // mvin - MVOUT_BITPAT -> List( + MVOUT_BITPAT -> List( N, Y, rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] rs2, // special = full rs2 Y - ) // mvout + ) // mvout ) ) diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 33990f4b..4718a7e6 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -7,12 +7,12 @@ import framework.memdomain.frontend.cmd_channel.rs.{MemRsComplete, MemRsIssue} import chisel3.experimental.hierarchy.{instantiable, public} class MemConfigerIO(val b: GlobalConfig) extends Bundle { - val vbank_id = Output(UInt(8.W)) + val vbank_id = Output(UInt(8.W)) val is_shared = Output(Bool()) - val is_multi = Output(Bool()) - val alloc = Output(Bool()) - val group_id = Output(UInt(3.W)) - val hart_id = Output(UInt(b.core.xLen.W)) + val is_multi = Output(Bool()) + val alloc = Output(Bool()) + val group_id = Output(UInt(3.W)) + val hart_id = Output(UInt(b.core.xLen.W)) } @instantiable @@ -39,31 +39,31 @@ class MemConfiger(val b: GlobalConfig) extends Module { val rob_id_reg = RegInit(0.U(rob_id_width.W)) val counter = RegInit(0.U(4.W)) - io.config.bits.is_multi := false.B + io.config.bits.is_multi := false.B io.config.bits.is_shared := false.B - io.config.bits.alloc := false.B - io.config.bits.vbank_id := 0.U(8.W) - io.config.bits.group_id := 0.U(3.W) - io.config.bits.hart_id := io.hartid - io.config.valid := false.B - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + io.config.bits.alloc := false.B + io.config.bits.vbank_id := 0.U(8.W) + io.config.bits.group_id := 0.U(3.W) + io.config.bits.hart_id := io.hartid + io.config.valid := false.B + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) when(state === idle) { when(io.cmdReq.valid) { when(io.cmdReq.bits.cmd.special(9, 5) > 1.U) { //is multi bank (col > 1) - state := config - col_reg := io.cmdReq.bits.cmd.special(9, 5) - alloc_reg := io.cmdReq.bits.cmd.special(10) + state := config + col_reg := io.cmdReq.bits.cmd.special(9, 5) + alloc_reg := io.cmdReq.bits.cmd.special(10) is_shared_reg := io.cmdReq.bits.cmd.is_shared - vbank_id_reg := io.cmdReq.bits.cmd.bank_id - rob_id_reg := io.cmdReq.bits.rob_id + vbank_id_reg := io.cmdReq.bits.cmd.bank_id + rob_id_reg := io.cmdReq.bits.rob_id }.otherwise { //not multi bank - io.config.bits.alloc := io.cmdReq.bits.cmd.special(10) + io.config.bits.alloc := io.cmdReq.bits.cmd.special(10) io.config.bits.is_shared := io.cmdReq.bits.cmd.is_shared - io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id - io.config.valid := true.B + io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id + io.config.valid := true.B io.cmdResp.valid := true.B io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id @@ -71,12 +71,12 @@ class MemConfiger(val b: GlobalConfig) extends Module { } }.otherwise { - io.config.bits.is_multi := true.B + io.config.bits.is_multi := true.B io.config.bits.is_shared := is_shared_reg - io.config.bits.alloc := alloc_reg - io.config.bits.vbank_id := vbank_id_reg - io.config.bits.group_id := counter - io.config.valid := (counter < col_reg) + io.config.bits.alloc := alloc_reg + io.config.bits.vbank_id := vbank_id_reg + io.config.bits.group_id := counter + io.config.valid := (counter < col_reg) when(io.config.fire && counter < col_reg) { counter := counter + 1.U diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index c96a66d6..72835299 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -115,7 +115,7 @@ class MemLoader(val b: GlobalConfig) extends Module { // Drive query interface // When idle and cmdReq is valid, query the incoming bank_id // Otherwise use the registered bank_id - io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, wr_bank_reg) + io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, wr_bank_reg) io.query_is_shared := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.is_shared, is_shared_reg) // DMA req accepted diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 76761d9b..92826014 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -104,7 +104,7 @@ class MemStorer(val b: GlobalConfig) extends Module { // Drive query interface // When idle and cmdReq is valid, query the incoming bank_id // Otherwise use the registered bank_id - io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, rd_bank_reg) + io.query_vbank_id := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.bank_id, rd_bank_reg) io.query_is_shared := Mux(state === s_idle && io.cmdReq.valid, io.cmdReq.bits.cmd.is_shared, is_shared_reg) // ----------------------------- diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 9839069a..e501a3f0 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -157,7 +157,7 @@ class MemMidend(val b: GlobalConfig) extends Module { io.frontend.read_is_shared, io.frontend.write_is_shared ) - io.mem_req(b.top.memBallChannelNum).hart_id := io.hartid + io.mem_req(b.top.memBallChannelNum).hart_id := io.hartid // Mapping table release for (i <- 0 until b.top.memBallChannelNum - 1) { diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index d3f751f4..7a1ce414 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -20,9 +20,7 @@ import pegasus._ // HarnessBinders connect ChipTop's exposed ports (AXI4MemPort, UARTPort, etc.) // to pegasusShell's interface signals. // -class PegasusHarness(implicit val p: Parameters) - extends Module - with HasHarnessInstantiators { +class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { val io = IO(new Bundle { // PCIe physical interface @@ -35,7 +33,7 @@ class PegasusHarness(implicit val p: Parameters) val pcie_exp_rxn = Input(UInt(16.W)) // HBM2 reference clock (100 MHz) - val hbm_ref_clk = Input(Clock()) + val hbm_ref_clk = Input(Clock()) }) // --- Instantiate PegasusShell --- @@ -43,8 +41,8 @@ class PegasusHarness(implicit val p: Parameters) pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n - io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp - io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn + io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp + io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk @@ -74,8 +72,8 @@ class PegasusHarness(implicit val p: Parameters) // --- HasHarnessInstantiators required interface --- def referenceClockFreqMHz: Double = 200.0 - def referenceClock: Clock = pegasusShell.io.dut_clk - def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset + def referenceClock: Clock = pegasusShell.io.dut_clk + def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset val success = WireInit(false.B) @@ -122,4 +120,5 @@ class PegasusHarness(implicit val p: Parameters) axi.r.valid := pegasusShell.io.chip_mem_rvalid pegasusShell.io.chip_mem_rready := axi.r.ready } + } diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala index 7bc548ba..aa335b13 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala @@ -12,57 +12,62 @@ import pegasus._ // HarnessBinder: connect ChipTop ExtMem AXI4 port to PegasusShell chip_mem interface // Replaces WithBlackBoxSimMem (Verilator simulation DRAM model) -class WithPegasusAXIMem extends HarnessBinder({ - case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => { - th.connectChipMem(port) - } -}) +class WithPegasusAXIMem + extends HarnessBinder({ + case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => { + th.connectChipMem(port) + } + }) // HarnessBinder: connect ChipTop UART TX to PegasusShell (goes to UARTCapture) // Replaces WithUARTAdapter (Verilator stdout adapter) -class WithPegasusUART extends HarnessBinder({ - case (th: PegasusHarness, port: UARTPort, chipId: Int) => { - th.pegasusShell.io.uart_tx := port.io.txd - port.io.rxd := true.B // UART RX idle high (no input from host) - } -}) +class WithPegasusUART + extends HarnessBinder({ + case (th: PegasusHarness, port: UARTPort, chipId: Int) => { + th.pegasusShell.io.uart_tx := port.io.txd + port.io.rxd := true.B // UART RX idle high (no input from host) + } + }) // Tie off JTAG (not used on FPGA; debug via GDB/OpenOCD over UART is possible but not in scope) -class WithPegasusTiedOffJTAG extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => { - port.io.TCK := true.B.asClock - port.io.TMS := true.B - port.io.TDI := true.B - } -}) +class WithPegasusTiedOffJTAG + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => { + port.io.TCK := true.B.asClock + port.io.TMS := true.B + port.io.TDI := true.B + } + }) // Tie off DMI (no simulation-side debug model needed on FPGA) -class WithPegasusTiedOffDMI extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => { - port.io.dmi.req.valid := false.B - port.io.dmi.req.bits := DontCare - port.io.dmi.resp.ready := true.B - port.io.dmiClock := false.B.asClock - port.io.dmiReset := true.B - } -}) +class WithPegasusTiedOffDMI + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => { + port.io.dmi.req.valid := false.B + port.io.dmi.req.bits := DontCare + port.io.dmi.resp.ready := true.B + port.io.dmiClock := false.B.asClock + port.io.dmiReset := true.B + } + }) // Aggregate config fragment: select PegasusHarness binders // and override Verilator-only simulation models -class WithPegasusHarness extends Config( - new WithPegasusAXIMem ++ - new WithPegasusUART ++ - new WithPegasusTiedOffJTAG ++ - new WithPegasusTiedOffDMI ++ - // Standard binders that are safe to keep on FPGA - new chipyard.harness.WithTieOffInterrupts ++ - new chipyard.harness.WithTieOffL2FBusAXI ++ - new chipyard.harness.WithGPIOTiedOff ++ - new chipyard.harness.WithGPIOPinsTiedOff ++ - new chipyard.harness.WithDriveChipIdPin ++ - new chipyard.harness.WithCustomBootPinPlusArg ++ - new chipyard.harness.WithSerialTLTiedOff ++ - new chipyard.harness.WithClockFromHarness ++ - new chipyard.harness.WithResetFromHarness ++ - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator -) +class WithPegasusHarness + extends Config( + new WithPegasusAXIMem ++ + new WithPegasusUART ++ + new WithPegasusTiedOffJTAG ++ + new WithPegasusTiedOffDMI ++ + // Standard binders that are safe to keep on FPGA + new chipyard.harness.WithTieOffInterrupts ++ + new chipyard.harness.WithTieOffL2FBusAXI ++ + new chipyard.harness.WithGPIOTiedOff ++ + new chipyard.harness.WithGPIOPinsTiedOff ++ + new chipyard.harness.WithDriveChipIdPin ++ + new chipyard.harness.WithCustomBootPinPlusArg ++ + new chipyard.harness.WithSerialTLTiedOff ++ + new chipyard.harness.WithClockFromHarness ++ + new chipyard.harness.WithResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator + ) diff --git a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala index 63a14008..6e3f252a 100644 --- a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala +++ b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala @@ -13,8 +13,8 @@ import freechips.rocketchip.subsystem.InSubsystem class WithPegasusBootROM extends Config((site, here, up) => { case BootROMLocated(InSubsystem) => Some(BootROMParams( - contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" - )) + contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" + )) }) // PegasusBuckyballToyConfig: Buckyball Toy SoC on AU280 FPGA @@ -22,17 +22,18 @@ class WithPegasusBootROM // Target clock: 200 MHz. If timing closure yields a different Fmax, // update all WithXxxBusFrequency values and re-elaborate so the DTB // gets the correct UART baud divisor (otherwise UART output will be garbled). -class PegasusBuckyballToyConfig extends Config( - new WithPegasusHarness ++ - new WithPegasusBootROM ++ - new chipyard.config.WithSystemBusFrequency(200.0) ++ - new chipyard.config.WithMemoryBusFrequency(200.0) ++ - new chipyard.config.WithPeripheryBusFrequency(200.0) ++ - new chipyard.config.WithControlBusFrequency(200.0) ++ - new chipyard.config.WithFrontBusFrequency(200.0) ++ - new chipyard.config.WithOffchipBusFrequency(200.0) ++ - new examples.toy.BuckyballToyConfig -) +class PegasusBuckyballToyConfig + extends Config( + new WithPegasusHarness ++ + new WithPegasusBootROM ++ + new chipyard.config.WithSystemBusFrequency(200.0) ++ + new chipyard.config.WithMemoryBusFrequency(200.0) ++ + new chipyard.config.WithPeripheryBusFrequency(200.0) ++ + new chipyard.config.WithControlBusFrequency(200.0) ++ + new chipyard.config.WithFrontBusFrequency(200.0) ++ + new chipyard.config.WithOffchipBusFrequency(200.0) ++ + new examples.toy.BuckyballToyConfig + ) // Elaborate entry point: generate SystemVerilog for PegasusHarness // Usage: mill pegasus.runMain sims.pegasus.ElaboratePegasus [firtool options] diff --git a/arch/src/main/scala/sims/verilator/BBSimHarness.scala b/arch/src/main/scala/sims/verilator/BBSimHarness.scala index c8b20ec5..a9212d15 100644 --- a/arch/src/main/scala/sims/verilator/BBSimHarness.scala +++ b/arch/src/main/scala/sims/verilator/BBSimHarness.scala @@ -6,7 +6,7 @@ import chisel3.util._ import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.WithDefaultMMIOPort -import chipyard.harness.{HasHarnessInstantiators, HarnessBinder} +import chipyard.harness.{HarnessBinder, HasHarnessInstantiators} import chipyard.iobinders.{AXI4MMIOPort, UARTPort} // ============================================================================= @@ -19,111 +19,111 @@ import chipyard.iobinders.{AXI4MMIOPort, UARTPort} // // AW/W/B/AR/R are handled entirely in RTL registers (no SimMMIOSlave needed). // ============================================================================= -class WithBBSimMMIO extends HarnessBinder({ - case (th: BBSimHarness, port: AXI4MMIOPort, chipId: Int) => { - // Use the harness clock (1 GHz) for all registers so they are in the - // same domain as C++ mmio_tick() and no cross-domain issues arise. - // The AXI4Buffer inside chiptop0 runs on its own clock; the port signals - // are async from the harness perspective, but in Verilator simulation - // everything is single-threaded so there is no real metastability risk. - withClockAndReset(th.clock, th.reset) { - val addrBits = port.io.bits.aw.bits.addr.getWidth - val idBits = port.io.bits.aw.bits.id.getWidth - - val sIdle :: sGotAW :: Nil = Enum(2) - val state = RegInit(sIdle) - val latchedAddr = Reg(UInt(addrBits.W)) - val latchedId = Reg(UInt(idBits.W)) - val bPending = RegInit(false.B) - val bId = Reg(UInt(idBits.W)) - - // --- AW channel --- - port.io.bits.aw.ready := (state === sIdle) - when(state === sIdle && port.io.bits.aw.valid) { - latchedAddr := port.io.bits.aw.bits.addr - latchedId := port.io.bits.aw.bits.id - state := sGotAW +class WithBBSimMMIO + extends HarnessBinder({ + case (th: BBSimHarness, port: AXI4MMIOPort, chipId: Int) => { + // State machine and B channel run on port.io.clock. + // WithUniformBusFrequencies(1000) ensures port.io.clock = harness clock = 1 GHz, + // so wFire is a true 1-cycle pulse and C++ sees it cleanly. + withClockAndReset(port.io.clock, th.reset) { + val addrBits = port.io.bits.aw.bits.addr.getWidth + val idBits = port.io.bits.aw.bits.id.getWidth + + val sIdle :: sGotAW :: Nil = Enum(2) + val state = RegInit(sIdle) + val latchedAddr = Reg(UInt(addrBits.W)) + val latchedId = Reg(UInt(idBits.W)) + val bPending = RegInit(false.B) + val bId = Reg(UInt(idBits.W)) + + // --- AW channel --- + port.io.bits.aw.ready := (state === sIdle) + when(state === sIdle && port.io.bits.aw.valid) { + latchedAddr := port.io.bits.aw.bits.addr + latchedId := port.io.bits.aw.bits.id + state := sGotAW + } + + // --- W channel --- + port.io.bits.w.ready := (state === sGotAW) + val wFire = (state === sGotAW) && port.io.bits.w.valid + when(wFire) { + state := sIdle + bPending := true.B + bId := latchedId + } + + // --- B channel --- + when(port.io.bits.b.valid && port.io.bits.b.ready) { + bPending := false.B + } + port.io.bits.b.valid := bPending + port.io.bits.b.bits.id := bId + port.io.bits.b.bits.resp := 0.U + + // --- Expose fire for C++ mmio_tick() --- + // With WithUniformBusFrequencies(1000), port.io.clock = 1 GHz. + // wFire is combinational; C++ de-bounces on rising edge. + th.io.mmio_fire := wFire + th.io.mmio_fire_addr := latchedAddr + th.io.mmio_fire_data := port.io.bits.w.bits.data + + // --- AR channel: accept immediately, return 0 next cycle --- + port.io.bits.ar.ready := true.B + val rValid = RegNext(port.io.bits.ar.valid, false.B) + val rId = RegNext(port.io.bits.ar.bits.id) + port.io.bits.r.valid := rValid + port.io.bits.r.bits.data := 0.U + port.io.bits.r.bits.resp := 0.U + port.io.bits.r.bits.last := true.B + port.io.bits.r.bits.id := rId + } } - - // --- W channel --- - port.io.bits.w.ready := (state === sGotAW) - val wFire = (state === sGotAW) && port.io.bits.w.valid - val latchedData = RegEnable(port.io.bits.w.bits.data, wFire) - when(wFire) { - state := sIdle - bPending := true.B - bId := latchedId - } - - // --- B channel --- - when(port.io.bits.b.valid && port.io.bits.b.ready) { - bPending := false.B - } - port.io.bits.b.valid := bPending - port.io.bits.b.bits.id := bId - port.io.bits.b.bits.resp := 0.U - - // --- Expose fire for C++ mmio_tick() --- - // All registers run at harness clock (1 GHz) = C++ sampling rate. - // wFire is high for exactly 1 cycle (W accept), so no de-bounce needed. - th.io.mmio_fire := wFire - th.io.mmio_fire_addr := latchedAddr - th.io.mmio_fire_data := port.io.bits.w.bits.data - - // --- AR channel: accept immediately, return 0 next cycle --- - port.io.bits.ar.ready := true.B - val rValid = RegNext(port.io.bits.ar.valid, false.B) - val rId = RegNext(port.io.bits.ar.bits.id) - port.io.bits.r.valid := rValid - port.io.bits.r.bits.data := 0.U - port.io.bits.r.bits.resp := 0.U - port.io.bits.r.bits.last := true.B - port.io.bits.r.bits.id := rId - } - } -}) + }) // ============================================================================= // WithNoUARTAdapter: suppress UARTAdapter; tie RX high (idle line) // ============================================================================= -class WithNoUARTAdapter extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => { - port.io.rxd := true.B - } -}) +class WithNoUARTAdapter + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => { + port.io.rxd := true.B + } + }) // ============================================================================= // BBSimConfig // ============================================================================= -class BBSimConfig extends Config( - new WithNoUARTAdapter ++ - new WithBBSimMMIO ++ - new WithDefaultMMIOPort ++ - new chipyard.harness.WithBlackBoxSimMem ++ - new chipyard.harness.WithSerialTLTiedOff ++ - new chipyard.harness.WithTieOffInterrupts ++ - new chipyard.harness.WithGPIOTiedOff ++ - new chipyard.harness.WithTieOffL2FBusAXI ++ - new chipyard.harness.WithClockFromHarness ++ - new chipyard.harness.WithResetFromHarness ++ - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ - new chipyard.iobinders.WithNMITiedOff -) - -class BuckyballToyBBSimConfig extends Config( - new BBSimConfig ++ - new WithCustomBootROM ++ - new examples.toy.BuckyballToyConfig -) +class BBSimConfig + extends Config( + new WithNoUARTAdapter ++ + new WithBBSimMMIO ++ + new WithDefaultMMIOPort ++ + new chipyard.config.WithUniformBusFrequencies(1000.0) ++ // match harness 1 GHz so MMIO clock = harness clock + new chipyard.harness.WithBlackBoxSimMem ++ + new chipyard.harness.WithSerialTLTiedOff ++ + new chipyard.harness.WithTieOffInterrupts ++ + new chipyard.harness.WithGPIOTiedOff ++ + new chipyard.harness.WithTieOffL2FBusAXI ++ + new chipyard.harness.WithClockFromHarness ++ + new chipyard.harness.WithResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ + new chipyard.iobinders.WithNMITiedOff + ) + +class BuckyballToyBBSimConfig + extends Config( + new BBSimConfig ++ + new WithCustomBootROM ++ + new examples.toy.BuckyballToyConfig + ) // ============================================================================= // BBSimHarness // ============================================================================= -class BBSimHarness(implicit val p: Parameters) - extends Module - with HasHarnessInstantiators { +class BBSimHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { val io = IO(new Bundle { val mmio_fire = Output(Bool()) @@ -137,8 +137,8 @@ class BBSimHarness(implicit val p: Parameters) io.mmio_fire_data := 0.U def referenceClockFreqMHz: Double = 1000.0 - def referenceClock: Clock = clock - def referenceReset: Reset = reset + def referenceClock: Clock = clock + def referenceReset: Reset = reset val success = WireInit(false.B) From 4388b8e1f9861931ca1cb1f8ffaf8d1894089da7 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 17:21:36 +0800 Subject: [PATCH 167/238] [ci] fix: update verilator configuration in CI workflows --- .github/workflows/pr.yml | 2 +- .github/workflows/test.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 34cef5cc..d90da44d 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -48,7 +48,7 @@ jobs: run: | cd ~/Code/buckyball nix develop -c bbdev verilator --clean - nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' + nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyBBSimConfig' nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 5c265b04..4aefee42 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -43,7 +43,7 @@ jobs: run: | cd ~/Code/buckyball nix develop -c bbdev verilator --clean - nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' + nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyBBSimConfig' nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test From 624590dc3785a6cde712586afa572af69e53f821 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 17:39:38 +0800 Subject: [PATCH 168/238] [arch] fix: correct memory section handling in BBSimHarness and linker script --- bb-tests/workloads/src/CTest/toy/bbsim.ld | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bb-tests/workloads/src/CTest/toy/bbsim.ld b/bb-tests/workloads/src/CTest/toy/bbsim.ld index a88bf712..7d8e660d 100644 --- a/bb-tests/workloads/src/CTest/toy/bbsim.ld +++ b/bb-tests/workloads/src/CTest/toy/bbsim.ld @@ -15,19 +15,26 @@ SECTIONS { .rodata : { *(.rodata .rodata.*) + *(.srodata .srodata.*) *(.gnu.linkonce.r.*) } .data : { *(.data .data.*) + *(.sdata .sdata.*) *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) PROVIDE(_edata = .); } + /* All zero-init sections: crt0.S clears __bss_start .. __bss_end, + so heap (at _end) starts after ALL bss including sbss. */ .bss (NOLOAD) : { PROVIDE(__bss_start = .); *(.bss .bss.*) + *(.sbss .sbss.*) *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) *(COMMON) PROVIDE(__bss_end = .); } From ec532a11dd9b6b687530a09b95e73e3788e6d296 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 18:17:56 +0800 Subject: [PATCH 169/238] [bb-tests] refactor: sync new simulation framework --- .github/workflows/pr.yml | 1 + .github/workflows/test.yml | 1 + arch/src/csrc/include/ioe/mmio.h | 7 +- arch/src/csrc/include/utils/debug.h | 80 +- arch/src/csrc/include/utils/macro.h | 104 +- arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc | 214 +- arch/src/csrc/src/monitor/ioe/mmio.cc | 14 +- .../scala/sims/verilator/BBSimHarness.scala | 30 +- bb-tests/workloads/CMakeLists.txt | 25 +- bb-tests/workloads/src/CTest/CMakeLists.txt | 4 - .../workloads/src/CTest/bebop/CMakeLists.txt | 5 +- .../src/CTest/gemmini/CMakeLists.txt | 213 - bb-tests/workloads/src/CTest/gemmini/Makefile | 132 - .../workloads/src/CTest/gemmini/aligned.c | 73 - bb-tests/workloads/src/CTest/gemmini/conv.c | 337 -- .../workloads/src/CTest/gemmini/conv_dw.c | 247 -- .../src/CTest/gemmini/conv_dw_perf.c | 103 - .../src/CTest/gemmini/conv_first_layer.c | 337 -- .../workloads/src/CTest/gemmini/conv_perf.c | 128 - .../workloads/src/CTest/gemmini/conv_rect.c | 337 -- .../src/CTest/gemmini/conv_rect_pool.c | 431 -- .../workloads/src/CTest/gemmini/conv_stride.c | 309 -- .../src/CTest/gemmini/conv_trans_input_3120.c | 295 -- ...nv_trans_input_3120_with_kernel_dilation.c | 297 -- .../CTest/gemmini/conv_trans_output_1203.c | 290 -- .../CTest/gemmini/conv_trans_weight_0132.c | 294 -- .../CTest/gemmini/conv_trans_weight_1203.c | 291 -- .../CTest/gemmini/conv_with_input_dilation.c | 380 -- ...conv_with_input_dilation_and_neg_padding.c | 373 -- .../conv_with_input_dilation_and_rot180.c | 387 -- .../CTest/gemmini/conv_with_kernel_dilation.c | 396 -- .../src/CTest/gemmini/conv_with_pool.c | 431 -- .../src/CTest/gemmini/conv_with_rot180.c | 387 -- .../src/CTest/gemmini/gemmini_counter.c | 129 - .../src/CTest/gemmini/global_average.c | 92 - .../src/CTest/gemmini/include/accumulator.h | 24 - .../src/CTest/gemmini/include/character.h | 10 - .../src/CTest/gemmini/include/gemmini.h | 3929 ----------------- .../CTest/gemmini/include/gemmini_counter.h | 79 - .../src/CTest/gemmini/include/gemmini_nn.h | 584 --- .../CTest/gemmini/include/gemmini_params.h | 102 - .../CTest/gemmini/include/gemmini_testutils.h | 307 -- .../src/CTest/gemmini/include/translator.h | 12 - bb-tests/workloads/src/CTest/gemmini/matmul.c | 460 -- .../workloads/src/CTest/gemmini/matmul_os.c | 206 - .../workloads/src/CTest/gemmini/matmul_ws.c | 227 - .../workloads/src/CTest/gemmini/matrix_add.c | 72 - .../workloads/src/CTest/gemmini/mvin_mvout.c | 62 - .../src/CTest/gemmini/mvin_mvout_acc.c | 132 - .../src/CTest/gemmini/mvin_mvout_acc_full.c | 119 - .../gemmini/mvin_mvout_acc_full_stride.c | 177 - .../src/CTest/gemmini/mvin_mvout_acc_stride.c | 235 - .../gemmini/mvin_mvout_acc_zero_stride.c | 104 - .../CTest/gemmini/mvin_mvout_block_stride.c | 71 - .../src/CTest/gemmini/mvin_mvout_stride.c | 116 - .../src/CTest/gemmini/mvin_mvout_zeros.c | 52 - .../workloads/src/CTest/gemmini/mvin_scale.c | 126 - bb-tests/workloads/src/CTest/gemmini/padded.c | 190 - .../workloads/src/CTest/gemmini/raw_hazard.c | 132 - bb-tests/workloads/src/CTest/gemmini/resadd.c | 105 - .../src/CTest/gemmini/resadd_stride.c | 108 - .../CTest/gemmini/rocc-software/.gitignore | 3 - .../gemmini/rocc-software/CONTRIBUTING.md | 46 - .../src/CTest/gemmini/rocc-software/LICENSE | 201 - .../src/CTest/gemmini/rocc-software/README.md | 4 - .../rocc-software/src/riscv_test_rocc.h | 26 - .../CTest/gemmini/rocc-software/src/xcustom.h | 170 - .../workloads/src/CTest/gemmini/template.c | 75 - .../src/CTest/gemmini/tiled_matmul_cpu.c | 167 - .../src/CTest/gemmini/tiled_matmul_option.c | 245 - .../src/CTest/gemmini/tiled_matmul_os.c | 180 - .../src/CTest/gemmini/tiled_matmul_ws.c | 182 - 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@@ -1,14 +1,13 @@ #ifndef _MMIO_H_ #define _MMIO_H_ -// mmio_tick: called at posedge (before 2nd eval) to drive ready/valid signals. -// mmio_tick_post: called after 2nd eval to observe RTL's b_ready/r_ready and -// immediately clear b_pending/r_pending if handshake completed in this cycle. +// mmio_tick: called once per posedge after eval(). +// io_mmio_fire is a 1-cycle register pulse; addr/data are stable latched +// registers. // // Address map: // 0x6000_0000 : simulation exit — write triggers sim_exit() // 0x6002_0000 : UART0 TX — write low byte → putchar void mmio_tick(); -void mmio_tick_post(); #endif // _MMIO_H_ diff --git a/arch/src/csrc/include/utils/debug.h b/arch/src/csrc/include/utils/debug.h index 8e97511f..156c1bf1 100644 --- a/arch/src/csrc/include/utils/debug.h +++ b/arch/src/csrc/include/utils/debug.h @@ -4,99 +4,27 @@ #include "utils/macro.h" #include -// Without formatting -// #define COLOR(a, b) "\033[" #b "m" a "\033[0m" -// #define GREEN(a) COLOR(a, 32) -// #define RED(a) COLOR(a, 31) -// #define BLUE(a) COLOR(a, 34) - -// Printf parameters for convenience, default is FG -#define BLACK "\33[1;30m" -#define RED "\33[1;31m" -#define GREEN "\33[1;32m" -#define YELLOW "\33[1;33m" -#define BLUE "\33[1;34m" -#define MAGENTA "\33[1;35m" -#define CYAN "\33[1;36m" -#define WHITE "\33[1;37m" - -// Interface with original Debug -// Foreground color -#define ASNI_FG_BLACK "\33[1;30m" #define ASNI_FG_RED "\33[1;31m" #define ASNI_FG_GREEN "\33[1;32m" #define ASNI_FG_YELLOW "\33[1;33m" #define ASNI_FG_BLUE "\33[1;34m" -#define ASNI_FG_MAGENTA "\33[1;35m" -#define ASNI_FG_CYAN "\33[1;36m" -#define ASNI_FG_WHITE "\33[1;37m" -#define ASNI_BG_BLACK "\33[1;40m" #define ASNI_BG_RED "\33[1;41m" -#define ASNI_BG_GREEN "\33[1;42m" -#define ASNI_BG_YELLOW "\33[1;43m" -#define ASNI_BG_BLUE "\33[1;44m" -#define ASNI_BG_MAGENTA "\33[1;35m" -#define ASNI_BG_CYAN "\33[1;46m" -#define ASNI_BG_WHITE "\33[1;47m" -// Reset color to "\033[0m" #define ASNI_NONE "\33[0m" #define ASNI_FMT(str, fmt) fmt str ASNI_NONE -#define log_write(...) \ - IFDEF( \ - CONFIG_TARGET_NATIVE_ELF, do { \ - extern FILE *log_fp; \ - extern bool log_enable(); \ - if (log_enable()) { \ - fprintf(log_fp, __VA_ARGS__); \ - fflush(log_fp); \ - } \ - } while (0)) - -#define _Log(...) \ - do { \ - printf(__VA_ARGS__); \ - log_write(__VA_ARGS__); \ - } while (0) - #define Log(format, ...) \ - _Log(ASNI_FMT("[%s:%d %s] " format, ASNI_FG_BLUE) "\n", __FILE__, __LINE__, \ - __func__, ##__VA_ARGS__) - -// Printf usage: first parameter is color, subsequent parameters (if any) follow -// in order -#define Printf(format, color, ...) _Log(ASNI_FMT(format, color), ##__VA_ARGS__) - -// #define assert(cond) \ -// do { \ -// if (!(cond)) { \ -// printf("Assertion fail at %s:%d\n", __FILE__, __LINE__); \ -// halt(0); \ -// } \ -// } while (0) + printf(ASNI_FMT("[%s:%d %s] " format, ASNI_FG_BLUE) "\n", __FILE__, \ + __LINE__, __func__, ##__VA_ARGS__) #define Assert(cond, format, ...) \ do { \ if (!(cond)) { \ - fflush(stdout), \ - fprintf(stderr, ASNI_FMT(format, ASNI_FG_RED) "\n", ##__VA_ARGS__); \ + fflush(stdout); \ + fprintf(stderr, ASNI_FMT(format, ASNI_FG_RED) "\n", ##__VA_ARGS__); \ } \ } while (0) -// #define Assert(cond, format, ...) \ -// do { \ -// if (!(cond)) { \ -// printf(ASNI_FMT(format, ASNI_FG_RED) "\n", ## __VA_ARGS__), \ -// fflush(stdout), fprintf(stderr, ASNI_FMT(format, ASNI_FG_RED) "\n", ## -// __VA_ARGS__); \ -// extern FILE* log_fp; fflush(log_fp); \ -// extern void assert_fail_msg(); \ -// assert_fail_msg(); \ -// assert(cond); \ -// } \ -// } while (0) - #define panic(format, ...) Assert(0, format, ##__VA_ARGS__) #endif diff --git a/arch/src/csrc/include/utils/macro.h b/arch/src/csrc/include/utils/macro.h index 1551febd..e1b6eae9 100644 --- a/arch/src/csrc/include/utils/macro.h +++ b/arch/src/csrc/include/utils/macro.h @@ -1,118 +1,20 @@ #ifndef __MACRO_H__ #define __MACRO_H__ -#include - // macro stringizing #define str_temp(x) #x #define str(x) str_temp(x) -// strlen() for string constant -#define STRLEN(CONST_STR) (sizeof(CONST_STR) - 1) - -// calculate the length of an array +// array length #define ARRLEN(arr) (int)(sizeof(arr) / sizeof(arr[0])) -// macro concatenation -#define concat_temp(x, y) x##y -#define concat(x, y) concat_temp(x, y) -#define concat3(x, y, z) concat(concat(x, y), z) -#define concat4(x, y, z, w) concat3(concat(x, y), z, w) -#define concat5(x, y, z, v, w) concat4(concat(x, y), z, v, w) - -// macro testing -// See -// https://stackoverflow.com/questions/26099745/test-if-preprocessor-symbol-is-defined-inside-macro -#define CHOOSE2nd(a, b, ...) b -#define MUX_WITH_COMMA(contain_comma, a, b) CHOOSE2nd(contain_comma a, b) -#define MUX_MACRO_PROPERTY(p, macro, a, b) \ - MUX_WITH_COMMA(concat(p, macro), a, b) -// define placeholders for some property -#define __P_DEF_0 X, -#define __P_DEF_1 X, -#define __P_ONE_1 X, -#define __P_ZERO_0 X, -// define some selection functions based on the properties of BOOLEAN macro -#define MUXDEF(macro, X, Y) MUX_MACRO_PROPERTY(__P_DEF_, macro, X, Y) -// If defined, then X, otherwise Y -#define MUXNDEF(macro, X, Y) MUX_MACRO_PROPERTY(__P_DEF_, macro, Y, X) -#define MUXONE(macro, X, Y) MUX_MACRO_PROPERTY(__P_ONE_, macro, X, Y) -#define MUXZERO(macro, X, Y) MUX_MACRO_PROPERTY(__P_ZERO_, macro, X, Y) - -// test if a boolean macro is defined -#define ISDEF(macro) MUXDEF(macro, 1, 0) -// test if a boolean macro is undefined -#define ISNDEF(macro) MUXNDEF(macro, 1, 0) -// test if a boolean macro is defined to 1 -#define ISONE(macro) MUXONE(macro, 1, 0) -// test if a boolean macro is defined to 0 -#define ISZERO(macro) MUXZERO(macro, 1, 0) -// test if a macro of ANY type is defined -// NOTE1: it ONLY works inside a function, since it calls `strcmp()` -// NOTE2: macros defined to themselves (#define A A) will get wrong results -#define isdef(macro) (strcmp("" #macro, "" str(macro)) != 0) - -// simplification for conditional compilation -#define __IGNORE(...) -#define __KEEP(...) __VA_ARGS__ -// keep the code if a boolean macro is defined -#define IFDEF(macro, ...) MUXDEF(macro, __KEEP, __IGNORE)(__VA_ARGS__) -// keep the code if a boolean macro is undefined -#define IFNDEF(macro, ...) MUXNDEF(macro, __KEEP, __IGNORE)(__VA_ARGS__) -// keep the code if a boolean macro is defined to 1 -#define IFONE(macro, ...) MUXONE(macro, __KEEP, __IGNORE)(__VA_ARGS__) -// keep the code if a boolean macro is defined to 0 -#define IFZERO(macro, ...) MUXZERO(macro, __KEEP, __IGNORE)(__VA_ARGS__) - -// functional-programming-like macro (X-macro) -// apply the function `f` to each element in the container `c` -// NOTE1: `c` should be defined as a list like: -// f(a0) f(a1) f(a2) ... -// NOTE2: each element in the container can be a tuple -#define MAP(c, f) c(f) - +// bit manipulation #define BITMASK(bits) ((1ull << (bits)) - 1) -#define BITS(x, hi, lo) \ - (((x) >> (lo)) & BITMASK((hi) - (lo) + 1)) // similar to x[hi:lo] in verilog - // Extract bits hi to lo from x -#define SEXT(x, len) \ - ({ \ - struct { \ - int64_t n : len; \ - } __x = {.n = x}; \ - (int64_t)__x.n; \ - }) - -// #define ROUNDUP(a, sz) ((((uintptr_t)a) + (sz) - 1) & ~((sz) - 1)) -// #define ROUNDDOWN(a, sz) ((((uintptr_t)a)) & ~((sz) - 1)) - -// #define PG_ALIGN __attribute((aligned(4096))) +#define BITS(x, hi, lo) (((x) >> (lo)) & BITMASK((hi) - (lo) + 1)) #if !defined(likely) #define likely(cond) __builtin_expect(cond, 1) #define unlikely(cond) __builtin_expect(cond, 0) #endif -// // for AM IOE -// #define io_read(reg) \ -// ({ reg##_T __io_param; \ -// ioe_read(reg, &__io_param); \ -// __io_param; }) - -// #define io_write(reg, ...) \ -// ({ reg##_T __io_param = (reg##_T) { __VA_ARGS__ }; \ -// ioe_write(reg, &__io_param); }) - -// Custom macros -#define MUX(v, p, a, b) v == p ? a : b -// value, p possible value, then a, otherwise b -#define SWAP(a, b) \ - a ^= b; \ - b ^= a; \ - a ^= b; - -// Convert x to string -#define STRINGIFY(x) #x -#define TOSTRING(x) STRINGIFY(x) - #endif diff --git a/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc b/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc index 6e5e8a68..70959f2a 100644 --- a/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc +++ b/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc @@ -2,46 +2,39 @@ // Replaces fesvr load_elf with libelf-based ELF loader. // This file is compiled into the simulation and takes precedence over // the version embedded in the SimDRAM Verilog blackbox resource. -// -// Globals shared with testchipip/csrc/mm_dramsim2.cc (included via linkage): -// extern bool use_dramsim; -// extern std::string loadmem_file; -// extern std::vector> backing_mem_data; -#include -#include -#include #include -#include -#include #include #include -#include +#include #include +#include +#include +#include +#include #include +#include -// elf.h is available in glibc, no extra library needed for parsing #include #include -#include #include +#include #include "mm_dramsim2.h" -// Global state — defined here since testchipip's SimDRAM.cc is excluded from build. -// memory_tick (not overridden) accesses these via external linkage from mm_dramsim2.cc. +// Global state — defined here since testchipip's SimDRAM.cc is excluded from +// build. bool use_dramsim = false; std::string ini_dir = "dramsim2_ini"; std::vector> backing_mem_data = {}; -// ELF file path, set via +elf= plusarg static std::string elf_file = ""; // --------------------------------------------------------------------------- // load_elf_to_mem: parse ELF64 and copy PT_LOAD segments into backing data // --------------------------------------------------------------------------- -static void load_elf_to_mem(const char *path, uint8_t *data, - uint64_t mem_base, uint64_t mem_size) { +static void load_elf_to_mem(const char *path, uint8_t *data, uint64_t mem_base, + uint64_t mem_size) { int fd = open(path, O_RDONLY); if (fd < 0) { fprintf(stderr, "[SimDRAM_bb] Cannot open ELF: %s\n", path); @@ -52,7 +45,8 @@ static void load_elf_to_mem(const char *path, uint8_t *data, fstat(fd, &st); size_t file_size = st.st_size; - uint8_t *file_buf = (uint8_t *)mmap(NULL, file_size, PROT_READ, MAP_PRIVATE, fd, 0); + uint8_t *file_buf = + (uint8_t *)mmap(NULL, file_size, PROT_READ, MAP_PRIVATE, fd, 0); close(fd); if (file_buf == MAP_FAILED) { fprintf(stderr, "[SimDRAM_bb] mmap failed for ELF: %s\n", path); @@ -73,23 +67,23 @@ static void load_elf_to_mem(const char *path, uint8_t *data, size_t loaded = 0; for (int i = 0; i < ehdr->e_phnum; i++) { Elf64_Phdr *ph = &phdrs[i]; - if (ph->p_type != PT_LOAD) continue; - if (ph->p_filesz == 0) continue; + if (ph->p_type != PT_LOAD) + continue; + if (ph->p_filesz == 0) + continue; - uint64_t vaddr = ph->p_paddr; // use physical address + uint64_t vaddr = ph->p_paddr; if (vaddr < mem_base || vaddr + ph->p_memsz > mem_base + mem_size) { fprintf(stderr, - "[SimDRAM_bb] Segment paddr=0x%lx size=0x%lx outside mem [0x%lx, 0x%lx)\n", - vaddr, ph->p_memsz, mem_base, mem_base + mem_size); + "[SimDRAM_bb] Segment paddr=0x%lx size=0x%lx outside mem [0x%lx, " + "0x%lx)\n", + vaddr, ph->p_memsz, mem_base, mem_base + mem_size); abort(); } uint64_t offset = vaddr - mem_base; - // Copy file content memcpy(data + offset, file_buf + ph->p_offset, ph->p_filesz); - // Zero BSS (memsz > filesz) - if (ph->p_memsz > ph->p_filesz) { + if (ph->p_memsz > ph->p_filesz) memset(data + offset + ph->p_filesz, 0, ph->p_memsz - ph->p_filesz); - } loaded += ph->p_filesz; } @@ -98,17 +92,12 @@ static void load_elf_to_mem(const char *path, uint8_t *data, } // --------------------------------------------------------------------------- -// memory_init override — called from SimDRAM.v via DPI-C +// memory_init — DPI-C from SimDRAM.v, called once at simulation start // --------------------------------------------------------------------------- -extern "C" void *memory_init( - int chip_id, - long long int mem_size, - long long int word_size, - long long int line_size, - long long int id_bits, - long long int clock_hz, - long long int mem_base) -{ +extern "C" void *memory_init(int chip_id, long long int mem_size, + long long int word_size, long long int line_size, + long long int id_bits, long long int clock_hz, + long long int mem_base) { mm_t *mm; s_vpi_vlog_info info; @@ -119,7 +108,6 @@ extern "C" void *memory_init( if (!vpi_get_vlog_info(&info)) abort(); - // Parse plusargs: +elf=, +dramsim, +dramsim_ini_dir= for (int i = 1; i < info.argc; i++) { std::string arg(info.argv[i]); if (arg.find("+elf=") == 0) @@ -130,15 +118,14 @@ extern "C" void *memory_init( local_ini_dir = arg.substr(strlen("+dramsim_ini_dir=")); } - while (chip_id >= (int)backing_mem_data.size()) { + while (chip_id >= (int)backing_mem_data.size()) backing_mem_data.push_back(std::map()); - } - if (backing_mem_data[chip_id].find(mem_base) != backing_mem_data[chip_id].end()) { + if (backing_mem_data[chip_id].find(mem_base) != + backing_mem_data[chip_id].end()) { assert(backing_mem_data[chip_id][mem_base].size == (size_t)mem_size); } else { - uint8_t *data = (uint8_t *)mmap(NULL, mem_size, - PROT_READ | PROT_WRITE, + uint8_t *data = (uint8_t *)mmap(NULL, mem_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_ANONYMOUS, -1, 0); if (data == MAP_FAILED) { fprintf(stderr, "[SimDRAM_bb] mmap for backing store failed\n"); @@ -146,134 +133,51 @@ extern "C" void *memory_init( } memset(data, 0, mem_size); - // Load ELF if +elf= was provided - if (!elf_file.empty()) { - load_elf_to_mem(elf_file.c_str(), data, (uint64_t)mem_base, (uint64_t)mem_size); - } + if (!elf_file.empty()) + load_elf_to_mem(elf_file.c_str(), data, (uint64_t)mem_base, + (uint64_t)mem_size); backing_mem_data[chip_id][mem_base] = {data, (size_t)mem_size}; } if (use_dramsim) { - mm = (mm_t *)(new mm_dramsim2_t( - mem_base, mem_size, word_size, line_size, - backing_mem_data[chip_id][mem_base], - memory_ini, system_ini, local_ini_dir, - 1 << id_bits, clock_hz)); + mm = (mm_t *)(new mm_dramsim2_t(mem_base, mem_size, word_size, line_size, + backing_mem_data[chip_id][mem_base], + memory_ini, system_ini, local_ini_dir, + 1 << id_bits, clock_hz)); } else { - mm = (mm_t *)(new mm_magic_t( - mem_base, mem_size, word_size, line_size, - backing_mem_data[chip_id][mem_base])); + mm = (mm_t *)(new mm_magic_t(mem_base, mem_size, word_size, line_size, + backing_mem_data[chip_id][mem_base])); } return mm; } // --------------------------------------------------------------------------- -// MMIO device state for UART interception -// SiFive UART TX register: base 0x10020000, offset 0 = txdata -// AXI write is split: aw channel (address) and w channel (data) may arrive -// in different cycles. We track pending aw/w separately. -// --------------------------------------------------------------------------- - -#define UART_TX_ADDR 0x10020000LL - -struct mmio_state_t { - bool aw_pending = false; - long long aw_addr = 0; - int aw_id = 0; - bool b_fire = false; // b response ready to send - int b_id_val = 0; -} mmio_state; - -static void mmio_uart_tick( - unsigned char reset, - unsigned char aw_valid, unsigned char *aw_ready, - long long int aw_addr_in, int aw_id_in, - unsigned char w_valid, unsigned char *w_ready, - long long w_data, - unsigned char *b_valid, unsigned char b_ready, int *b_id, int *b_resp) -{ - if (reset) { - mmio_state = mmio_state_t{}; - *aw_ready = 1; *w_ready = 1; *b_valid = 0; - return; - } - - // Accept aw - *aw_ready = !mmio_state.aw_pending; - if (aw_valid && *aw_ready) { - mmio_state.aw_pending = true; - mmio_state.aw_addr = aw_addr_in; - mmio_state.aw_id = aw_id_in; - } - - // Accept w when aw is pending - *w_ready = mmio_state.aw_pending && !mmio_state.b_fire; - if (w_valid && *w_ready) { - if (mmio_state.aw_addr == UART_TX_ADDR) { - char ch = (char)(w_data & 0xFF); - putchar(ch); - fflush(stdout); - } - mmio_state.aw_pending = false; - mmio_state.b_fire = true; - mmio_state.b_id_val = mmio_state.aw_id; - } - - // Send b response - *b_valid = mmio_state.b_fire; - *b_id = mmio_state.b_id_val; - *b_resp = 0; - if (mmio_state.b_fire && b_ready) - mmio_state.b_fire = false; -} - -// --------------------------------------------------------------------------- -// memory_tick — DPI-C from SimDRAM.v / SimAXIMem.v -// MMIO region (base != DRAM base) is dispatched to mmio_uart_tick. +// memory_tick — DPI-C from SimDRAM.v / SimAXIMem.v, called each cycle // --------------------------------------------------------------------------- extern "C" void memory_tick( - void *channel, - unsigned char reset, - unsigned char ar_valid, unsigned char *ar_ready, - long long int ar_addr, int ar_id, int ar_size, int ar_len, - unsigned char aw_valid, unsigned char *aw_ready, + void *channel, unsigned char reset, unsigned char ar_valid, + unsigned char *ar_ready, long long int ar_addr, int ar_id, int ar_size, + int ar_len, unsigned char aw_valid, unsigned char *aw_ready, long long int aw_addr, int aw_id, int aw_size, int aw_len, - unsigned char w_valid, unsigned char *w_ready, - int w_strb, long long w_data, unsigned char w_last, - unsigned char *r_valid, unsigned char r_ready, + unsigned char w_valid, unsigned char *w_ready, int w_strb, long long w_data, + unsigned char w_last, unsigned char *r_valid, unsigned char r_ready, int *r_id, int *r_resp, long long *r_data, unsigned char *r_last, - unsigned char *b_valid, unsigned char b_ready, - int *b_id, int *b_resp) -{ + unsigned char *b_valid, unsigned char b_ready, int *b_id, int *b_resp) { mm_t *mm = (mm_t *)channel; - - // Route MMIO channel (mem_base < 0x80000000) to our MMIO handler. - // DRAM is always at 0x80000000+; MMIO (SiFive peripherals) is below. - if (mm->get_base() < 0x80000000ULL) { - *ar_ready = 0; *r_valid = 0; *r_last = 0; *r_id = 0; *r_resp = 0; *r_data = 0; - mmio_uart_tick(reset, - aw_valid, aw_ready, aw_addr, aw_id, - w_valid, w_ready, w_data, - b_valid, b_ready, b_id, b_resp); - return; - } - - mm->tick(reset, - ar_valid, ar_addr, ar_id, ar_size, ar_len, - aw_valid, aw_addr, aw_id, aw_size, aw_len, - w_valid, w_strb, &w_data, w_last, - r_ready, b_ready); + mm->tick(reset, ar_valid, ar_addr, ar_id, ar_size, ar_len, aw_valid, aw_addr, + aw_id, aw_size, aw_len, w_valid, w_strb, &w_data, w_last, r_ready, + b_ready); *ar_ready = mm->ar_ready(); *aw_ready = mm->aw_ready(); - *w_ready = mm->w_ready(); - *r_valid = mm->r_valid(); - *r_id = mm->r_id(); - *r_resp = mm->r_resp(); - *r_data = *((long *)mm->r_data()); - *r_last = mm->r_last(); - *b_valid = mm->b_valid(); - *b_id = mm->b_id(); - *b_resp = mm->b_resp(); + *w_ready = mm->w_ready(); + *r_valid = mm->r_valid(); + *r_id = mm->r_id(); + *r_resp = mm->r_resp(); + *r_data = *((long *)mm->r_data()); + *r_last = mm->r_last(); + *b_valid = mm->b_valid(); + *b_id = mm->b_id(); + *b_resp = mm->b_resp(); } diff --git a/arch/src/csrc/src/monitor/ioe/mmio.cc b/arch/src/csrc/src/monitor/ioe/mmio.cc index 8ecca972..78fdd49b 100644 --- a/arch/src/csrc/src/monitor/ioe/mmio.cc +++ b/arch/src/csrc/src/monitor/ioe/mmio.cc @@ -25,14 +25,10 @@ static void uart_putchar(char ch) { } // Called once per posedge after eval(). -// wFire is combinational and may stay high for multiple cycles if the AXI4 -// master holds W valid. De-bounce on the rising edge (0→1 transition). +// io_mmio_fire is RegNext(wFire) — a 1-cycle register pulse. addr and data +// are stable registers latched on wFire, so they are always valid when fire=1. void mmio_tick() { - static uint8_t prev_fire = 0; - uint8_t cur_fire = top->io_mmio_fire ? 1 : 0; - bool rising = (!prev_fire && cur_fire); - prev_fire = cur_fire; - if (!rising) + if (!top->io_mmio_fire) return; uint64_t addr = top->io_mmio_fire_addr; @@ -51,7 +47,3 @@ void mmio_tick() { uart_putchar((char)(data & 0xFF)); } } - -void mmio_tick_post() { - // No-op: handshake is now managed entirely in RTL. -} diff --git a/arch/src/main/scala/sims/verilator/BBSimHarness.scala b/arch/src/main/scala/sims/verilator/BBSimHarness.scala index a9212d15..1a80df9f 100644 --- a/arch/src/main/scala/sims/verilator/BBSimHarness.scala +++ b/arch/src/main/scala/sims/verilator/BBSimHarness.scala @@ -12,19 +12,18 @@ import chipyard.iobinders.{AXI4MMIOPort, UARTPort} // ============================================================================= // WithBBSimMMIO: wire AXI4 MMIO port. // -// All registers are created inside withClockAndReset(port.io.clock, ...) so -// they run in the same clock domain as the AXI4Buffer B-FIFO inside chiptop0. -// The AXI4MMIOPort uses ClockedIO, so port.io.clock is the SoC clock (1 GHz), -// not the harnessBinderClock (100 MHz) that plain RegInit would use here. -// -// AW/W/B/AR/R are handled entirely in RTL registers (no SimMMIOSlave needed). +// All registers run in port.io.clock domain (= harness clock = 1 GHz, thanks +// to WithUniformBusFrequencies(1000)). C++ samples three stable register +// outputs each posedge: +// - firePulse = RegNext(wFire) — 1-cycle pulse, no debounce needed +// - latchedAddr = Reg latched on AW — stable address +// - latchedData = RegEnable on wFire — stable write data +// bPending is set on wFire (not delayed) so the B response reaches the CPU +// one cycle before C++ processes the event. // ============================================================================= class WithBBSimMMIO extends HarnessBinder({ case (th: BBSimHarness, port: AXI4MMIOPort, chipId: Int) => { - // State machine and B channel run on port.io.clock. - // WithUniformBusFrequencies(1000) ensures port.io.clock = harness clock = 1 GHz, - // so wFire is a true 1-cycle pulse and C++ sees it cleanly. withClockAndReset(port.io.clock, th.reset) { val addrBits = port.io.bits.aw.bits.addr.getWidth val idBits = port.io.bits.aw.bits.id.getWidth @@ -46,7 +45,8 @@ class WithBBSimMMIO // --- W channel --- port.io.bits.w.ready := (state === sGotAW) - val wFire = (state === sGotAW) && port.io.bits.w.valid + val wFire = (state === sGotAW) && port.io.bits.w.valid + val latchedData = RegEnable(port.io.bits.w.bits.data, wFire) when(wFire) { state := sIdle bPending := true.B @@ -61,12 +61,12 @@ class WithBBSimMMIO port.io.bits.b.bits.id := bId port.io.bits.b.bits.resp := 0.U - // --- Expose fire for C++ mmio_tick() --- - // With WithUniformBusFrequencies(1000), port.io.clock = 1 GHz. - // wFire is combinational; C++ de-bounces on rising edge. - th.io.mmio_fire := wFire + // --- Fire pulse for C++ mmio_tick() --- + // RegNext delays 1 cycle; addr/data are stable registers at that point. + val firePulse = RegNext(wFire, false.B) + th.io.mmio_fire := firePulse th.io.mmio_fire_addr := latchedAddr - th.io.mmio_fire_data := port.io.bits.w.bits.data + th.io.mmio_fire_data := latchedData // --- AR channel: accept immediately, return 0 next cycle --- port.io.bits.ar.ready := true.B diff --git a/bb-tests/workloads/CMakeLists.txt b/bb-tests/workloads/CMakeLists.txt index 25e5d91e..175e78b5 100644 --- a/bb-tests/workloads/CMakeLists.txt +++ b/bb-tests/workloads/CMakeLists.txt @@ -2,14 +2,6 @@ cmake_minimum_required(VERSION 3.12) project(BuckyballTest C CXX) set(CMAKE_EXPORT_COMPILE_COMMANDS ON) -# get the root directory of the project -# execute_process( -# COMMAND git rev-parse --show-toplevel -# WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} -# OUTPUT_VARIABLE BBDIR -# OUTPUT_STRIP_TRAILING_WHITESPACE -# ) - set(WORKLOAD_DIR ${CMAKE_CURRENT_SOURCE_DIR}) set(WORKLOAD_SRC_DIR ${WORKLOAD_DIR}/src) set(WORKLOAD_LIB_DIR ${WORKLOAD_DIR}/lib) @@ -24,7 +16,6 @@ set(LLVM_BUILD_DIR ${BUDDY_MLIR_DIR}/llvm/build) set(ELF_CC ${RISCV_GNU_TOOLCHAIN}/bin/riscv64-unknown-elf-gcc) set(LINUX_CC ${RISCV_GNU_TOOLCHAIN}/bin/riscv64-unknown-linux-gnu-gcc) -set(HTIF_DIR ${RISCV_GNU_TOOLCHAIN}/riscv64-unknown-elf/lib) set(BUILD_BIN_DIR ${WORKLOAD_DIR}/../build/workloads) set(OUTPUT_BIN_DIR ${WORKLOAD_DIR}/../output/workloads) @@ -39,7 +30,6 @@ add_subdirectory(src) #------------------------------------------------------------------------------- # setup directory #------------------------------------------------------------------------------- -# Will be created during cmake file(MAKE_DIRECTORY ${OUTPUT_BIN_DIR}) #------------------------------------------------------------------------------- @@ -50,12 +40,6 @@ add_custom_target(create-dirs COMMENT "Creating necessary directories" ) - -# add_custom_target(build-compiler -# COMMAND ${BBDIR}/bb-tests/scripts/build-compiler.sh -# COMMENT "Building Buddy Compiler" -# ) - add_custom_target(sync-bin COMMAND rsync -av --exclude="CMakeFiles" --include="*/" --include="*-baremetal" --include="*-linux" @@ -64,15 +48,12 @@ add_custom_target(sync-bin COMMENT "Syncing binary files to output directory" ) - add_dependencies(sync-bin tutorial-build - buckyball-CTest-build - buckyball-gemmini-build - buckyball-rvv-build - OpTest-all + buckyball-CTest-build + OpTest-all buckyball-goban-CTest-build - ) +) add_custom_target(build-all ALL DEPENDS sync-bin diff --git a/bb-tests/workloads/src/CTest/CMakeLists.txt b/bb-tests/workloads/src/CTest/CMakeLists.txt index ff477d4f..38766598 100644 --- a/bb-tests/workloads/src/CTest/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/CMakeLists.txt @@ -1,10 +1,6 @@ -set(CTEST_GEMMINI_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/gemmini) set(CTEST_TOY_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/toy) -set(CTEST_RVV_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/rvv) set(CTEST_BEBOP_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/bebop) -add_subdirectory(gemmini) add_subdirectory(toy) -add_subdirectory(rvv) add_subdirectory(bebop) add_subdirectory(goban) diff --git a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt index edc9eb6b..3eff5fcf 100644 --- a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt @@ -4,9 +4,10 @@ set(LINUX_CC "riscv64-unknown-linux-gnu-g++") #------------------------------------------------------------------------------- # Set baremetal compilation flags #------------------------------------------------------------------------------- +set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} - -I${CTEST_TOY_WORKLOAD_DIR}) + -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles + -Wl,-T,${BBSIM_LD} -I${CTEST_TOY_WORKLOAD_DIR}) #------------------------------------------------------------------------------- # Define common compilation step functions diff --git a/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt b/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt deleted file mode 100644 index 654003c9..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/CMakeLists.txt +++ /dev/null @@ -1,213 +0,0 @@ -set(ELF_CC "riscv64-unknown-elf-gcc") -set(LINUX_CC "riscv64-unknown-linux-gnu-g++") - -#------------------------------------------------------------------------------- -# Set baremetal compilation flags -#------------------------------------------------------------------------------- -set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -std=gnu99 -ffast-math -fno-builtin-printf -fno-tree-loop-distribute-patterns - -DBAREMETAL=1 -DPREALLOCATE=1 -DMULTITHREAD=1 -DPRINT_TILE=0 - -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} -I${CTEST_GEMMINI_WORKLOAD_DIR}) - -# Link libraries -set(LINK_LIBS -lm -lgcc) - -#------------------------------------------------------------------------------- -# Define common compilation step functions -#------------------------------------------------------------------------------- - -#------------------------------------------------------------------------------- -# Generate executables for different platforms -#------------------------------------------------------------------------------- -set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-g++") -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc -mcmodel=medany -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -DPREALLOCATE=1 -DMULTITHREAD=1 -DPRINT_TILE=0") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gc -mcmodel=medany -std=gnu++11 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -DPREALLOCATE=1 -DMULTITHREAD=1 -DPRINT_TILE=0") - -# Generate Linux version executables -function(add_linux_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}-linux") - - add_executable(${EXECUTABLE} ${CTEST_GEMMINI_WORKLOAD_DIR}/${SOURCE_FILE}) - target_include_directories(${EXECUTABLE} PRIVATE - ${WORKLOAD_LIB_DIR} - ${CTEST_GEMMINI_WORKLOAD_DIR} - ) - target_link_libraries(${EXECUTABLE} m) -endfunction() - -# Generate multicore baremetal version executables -function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}_multicore-baremetal") - - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} ${CTEST_TOY_WORKLOAD_DIR}/start.S - -DMULTICORE=3 - ${CTEST_GEMMINI_WORKLOAD_DIR}/${SOURCE_FILE} - -I${WORKLOAD_LIB_DIR} - ${LINK_LIBS} - DEPENDS ${CTEST_GEMMINI_WORKLOAD_DIR}/${SOURCE_FILE} - ${CTEST_TOY_WORKLOAD_DIR}/start.S - COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - - add_custom_target(${TEST_NAME}_multicore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) -endfunction() - -# Generate singlecore baremetal version executables -function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}_singlecore-baremetal") - - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} - ${CTEST_GEMMINI_WORKLOAD_DIR}/${SOURCE_FILE} - -I${WORKLOAD_LIB_DIR} - ${LINK_LIBS} - DEPENDS ${CTEST_GEMMINI_WORKLOAD_DIR}/${SOURCE_FILE} - COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - - add_custom_target(${TEST_NAME}_singlecore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) -endfunction() - -# Create cross-platform test targets -function(add_cross_platform_test_target TEST_NAME SOURCE_FILE) - add_linux_test_target(${TEST_NAME} ${SOURCE_FILE}) - add_multicore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - add_singlecore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - - # Create a master target that builds all platforms simultaneously - add_custom_target(${TEST_NAME} - DEPENDS ${TEST_NAME}-linux ${TEST_NAME}_multicore_baremetal ${TEST_NAME}_singlecore_baremetal - COMMENT "Building ${TEST_NAME} for all platforms" - ) -endfunction() - -#------------------------------------------------------------------------------- -# build linux version workload -#------------------------------------------------------------------------------- -set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") -set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${LINK_FLAGS}") - -#------------------------------------------------------------------------------- -# Build list - use cross-platform function to generate all test targets -#------------------------------------------------------------------------------- -add_cross_platform_test_target(gemmini_mvin_mvout mvin_mvout.c) -add_cross_platform_test_target(gemmini_mvin_mvout_zeros mvin_mvout_zeros.c) -add_cross_platform_test_target(gemmini_mvin_mvout_stride mvin_mvout_stride.c) -add_cross_platform_test_target(gemmini_mvin_mvout_block_stride mvin_mvout_block_stride.c) -add_cross_platform_test_target(gemmini_mvin_mvout_acc mvin_mvout_acc.c) -add_cross_platform_test_target(gemmini_mvin_mvout_acc_zero_stride mvin_mvout_acc_zero_stride.c) -add_cross_platform_test_target(gemmini_mvin_mvout_acc_stride mvin_mvout_acc_stride.c) -add_cross_platform_test_target(gemmini_mvin_mvout_acc_full mvin_mvout_acc_full.c) -add_cross_platform_test_target(gemmini_mvin_mvout_acc_full_stride mvin_mvout_acc_full_stride.c) -add_cross_platform_test_target(gemmini_matmul_os matmul_os.c) -add_cross_platform_test_target(gemmini_matmul_ws matmul_ws.c) -add_cross_platform_test_target(gemmini_matmul matmul.c) -add_cross_platform_test_target(gemmini_raw_hazard raw_hazard.c) -add_cross_platform_test_target(gemmini_aligned aligned.c) -add_cross_platform_test_target(gemmini_padded padded.c) -add_cross_platform_test_target(gemmini_mvin_scale mvin_scale.c) -add_cross_platform_test_target(gemmini_conv conv.c) -add_cross_platform_test_target(gemmini_conv_stride conv_stride.c) -add_cross_platform_test_target(gemmini_conv_rect conv_rect.c) -add_cross_platform_test_target(gemmini_conv_rect_pool conv_rect_pool.c) -add_cross_platform_test_target(gemmini_conv_with_pool conv_with_pool.c) -add_cross_platform_test_target(gemmini_conv_with_rot180 conv_with_rot180.c) -add_cross_platform_test_target(gemmini_conv_with_kernel_dilation conv_with_kernel_dilation.c) -add_cross_platform_test_target(gemmini_conv_with_input_dilation conv_with_input_dilation.c) -add_cross_platform_test_target(gemmini_conv_with_input_dilation_and_rot180 conv_with_input_dilation_and_rot180.c) -add_cross_platform_test_target(gemmini_conv_with_input_dilation_and_neg_padding conv_with_input_dilation_and_neg_padding.c) -add_cross_platform_test_target(gemmini_conv_trans_output_1203 conv_trans_output_1203.c) -add_cross_platform_test_target(gemmini_conv_trans_weight_1203 conv_trans_weight_1203.c) -add_cross_platform_test_target(gemmini_conv_trans_weight_0132 conv_trans_weight_0132.c) -add_cross_platform_test_target(gemmini_conv_trans_input_3120 conv_trans_input_3120.c) -add_cross_platform_test_target(gemmini_conv_trans_input_3120_with_kernel_dilation conv_trans_input_3120_with_kernel_dilation.c) -add_cross_platform_test_target(gemmini_conv_first_layer conv_first_layer.c) -add_cross_platform_test_target(gemmini_conv_dw conv_dw.c) -add_cross_platform_test_target(gemmini_conv_perf conv_perf.c) -add_cross_platform_test_target(gemmini_conv_dw_perf conv_dw_perf.c) -add_cross_platform_test_target(gemmini_tiled_matmul_os tiled_matmul_os.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws tiled_matmul_ws.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_At tiled_matmul_ws_At.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_Bt tiled_matmul_ws_Bt.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_full_C tiled_matmul_ws_full_C.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_low_D tiled_matmul_ws_low_D.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_igelu tiled_matmul_ws_igelu.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_layernorm tiled_matmul_ws_layernorm.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_softmax tiled_matmul_ws_softmax.c) -add_cross_platform_test_target(gemmini_tiled_matmul_ws_perf tiled_matmul_ws_perf.c) -add_cross_platform_test_target(gemmini_tiled_matmul_cpu tiled_matmul_cpu.c) -add_cross_platform_test_target(gemmini_tiled_matmul_option tiled_matmul_option.c) -add_cross_platform_test_target(gemmini_transpose transpose.c) -add_cross_platform_test_target(gemmini_matrix_add matrix_add.c) -add_cross_platform_test_target(gemmini_resadd resadd.c) -add_cross_platform_test_target(gemmini_resadd_stride resadd_stride.c) -add_cross_platform_test_target(gemmini_global_average global_average.c) -add_cross_platform_test_target(gemmini_gemmini_counter gemmini_counter.c) -add_cross_platform_test_target(gemmini_template template.c) - -# Create master build target -add_custom_target(buckyball-gemmini-build ALL DEPENDS - gemmini_mvin_mvout - gemmini_mvin_mvout_zeros - gemmini_mvin_mvout_stride - gemmini_mvin_mvout_block_stride - gemmini_mvin_mvout_acc - gemmini_mvin_mvout_acc_zero_stride - gemmini_mvin_mvout_acc_stride - gemmini_mvin_mvout_acc_full - gemmini_mvin_mvout_acc_full_stride - gemmini_matmul_os - gemmini_matmul_ws - gemmini_matmul - gemmini_raw_hazard - gemmini_aligned - gemmini_padded - gemmini_mvin_scale - gemmini_conv - gemmini_conv_stride - gemmini_conv_rect - gemmini_conv_rect_pool - gemmini_conv_with_pool - gemmini_conv_with_rot180 - gemmini_conv_with_kernel_dilation - gemmini_conv_with_input_dilation - gemmini_conv_with_input_dilation_and_rot180 - gemmini_conv_with_input_dilation_and_neg_padding - gemmini_conv_trans_output_1203 - gemmini_conv_trans_weight_1203 - gemmini_conv_trans_weight_0132 - gemmini_conv_trans_input_3120 - gemmini_conv_trans_input_3120_with_kernel_dilation - gemmini_conv_first_layer - gemmini_conv_dw - gemmini_conv_perf - gemmini_conv_dw_perf - gemmini_tiled_matmul_os - gemmini_tiled_matmul_ws - gemmini_tiled_matmul_ws_At - gemmini_tiled_matmul_ws_Bt - gemmini_tiled_matmul_ws_full_C - gemmini_tiled_matmul_ws_low_D - gemmini_tiled_matmul_ws_igelu - gemmini_tiled_matmul_ws_layernorm - gemmini_tiled_matmul_ws_softmax - gemmini_tiled_matmul_ws_perf - gemmini_tiled_matmul_cpu - gemmini_tiled_matmul_option - gemmini_transpose - gemmini_matrix_add - gemmini_resadd - gemmini_resadd_stride - gemmini_global_average - gemmini_gemmini_counter - gemmini_template - COMMENT "Building all Gemmini workloads for Buckyball" - VERBATIM) diff --git a/bb-tests/workloads/src/CTest/gemmini/Makefile b/bb-tests/workloads/src/CTest/gemmini/Makefile deleted file mode 100644 index fd4d4aaf..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/Makefile +++ /dev/null @@ -1,132 +0,0 @@ -include $(abs_top_srcdir)/Makefrag - -tests = \ - mvin_mvout \ - mvin_mvout_zeros \ - mvin_mvout_stride \ - mvin_mvout_block_stride \ - mvin_mvout_acc \ - mvin_mvout_acc_zero_stride \ - mvin_mvout_acc_stride \ - mvin_mvout_acc_full \ - mvin_mvout_acc_full_stride \ - matmul_os \ - matmul_ws \ - matmul \ - raw_hazard \ - aligned \ - padded \ - mvin_scale \ - conv \ - conv_stride \ - conv_rect \ - conv_rect_pool \ - conv_with_pool \ - conv_with_rot180 \ - conv_with_kernel_dilation \ - conv_with_input_dilation \ - conv_with_input_dilation_and_rot180 \ - conv_with_input_dilation_and_neg_padding \ - conv_trans_output_1203 \ - conv_trans_weight_1203 \ - conv_trans_weight_0132 \ - conv_trans_input_3120 \ - conv_trans_input_3120_with_kernel_dilation \ - conv_first_layer \ - conv_dw \ - conv_perf \ - conv_dw_perf \ - tiled_matmul_os \ - tiled_matmul_ws \ - tiled_matmul_ws_At \ - tiled_matmul_ws_Bt \ - tiled_matmul_ws_full_C \ - tiled_matmul_ws_low_D \ - tiled_matmul_ws_igelu \ - tiled_matmul_ws_layernorm \ - tiled_matmul_ws_softmax \ - tiled_matmul_ws_perf \ - tiled_matmul_cpu \ - tiled_matmul_option \ - transpose \ - matrix_add \ - resadd \ - resadd_stride \ - global_average \ - gemmini_counter \ - template \ - -tests_baremetal = $(tests:=-baremetal) - -ifeq ($(findstring spike,$(RUNNER)),spike) -# Currently don't support conv or conv-with-pool on spike -runs_baremetal = $(addsuffix .run,$(filter-out conv-baremetal conv_with_pool-baremetal,$(tests_baremetal))) -else -# Don't run very long benchmarks for RTL sim -runs_baremetal = $(addsuffix .run,$(filter-out tiled_matmul_cpu-baremetal tiled_matmul_option-baremetal,$(tests_baremetal))) -endif - -ifdef BAREMETAL_ONLY - tests_linux = - tests_pk = -else - tests_linux = $(tests:=-linux) - tests_pk = $(tests:=-pk) -endif - -BENCH_COMMON = $(abs_top_srcdir)/riscv-tests/benchmarks/common -GEMMINI_HEADERS = $(abs_top_srcdir)/include/gemmini.h $(abs_top_srcdir)/include/gemmini_params.h $(abs_top_srcdir)/include/gemmini_testutils.h - -CFLAGS := $(CFLAGS) \ - -DPREALLOCATE=1 \ - -DMULTITHREAD=1 \ - -mcmodel=medany \ - -std=gnu99 \ - -O2 \ - -ffast-math \ - -fno-common \ - -fno-builtin-printf \ - -fno-tree-loop-distribute-patterns \ - -march=rv64gc -Wa,-march=rv64gc \ - -lm \ - -lgcc \ - -I$(abs_top_srcdir)/riscv-tests \ - -I$(abs_top_srcdir)/riscv-tests/env \ - -I$(abs_top_srcdir) \ - -I$(BENCH_COMMON) \ - -DID_STRING=$(ID_STRING) \ - -DPRINT_TILE=0 \ - -CFLAGS_PK := \ - $(CFLAGS) \ - -static \ - -DBAREMETAL=1 \ - -CFLAGS_BAREMETAL := \ - $(CFLAGS) \ - -nostdlib \ - -nostartfiles \ - -static \ - -T $(BENCH_COMMON)/test.ld \ - -DBAREMETAL=1 \ - -all: $(tests_baremetal) $(tests_linux) $(tests_pk) - -vpath %.c $(src_dir) - -%-baremetal: %.c $(GEMMINI_HEADERS) - $(CC_BAREMETAL) $(CFLAGS_BAREMETAL) $< $(LFLAGS) -o $@ \ - $(wildcard $(BENCH_COMMON)/*.c) $(wildcard $(BENCH_COMMON)/*.S) $(LIBS) - -%-linux: %.c $(GEMMINI_HEADERS) - $(CC_LINUX) $(CFLAGS) $< $(LFLAGS) -o $@ - -%-pk: %.c $(GEMMINI_HEADERS) - $(CC_LINUX) $(CFLAGS_PK) $< $(LFLAGS) -o $@ - -run-baremetal: $(runs_baremetal) - -%-baremetal.run: %-baremetal - $(RUNNER)$(abs_top_srcdir)/build/bareMetalC/$^ - -junk += $(tests_baremetal) $(tests_linux) $(tests_pk) diff --git a/bb-tests/workloads/src/CTest/gemmini/aligned.c b/bb-tests/workloads/src/CTest/gemmini/aligned.c deleted file mode 100644 index c48c6ad8..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/aligned.c +++ /dev/null @@ -1,73 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define PG_SIZE (4 * 1024) -#define OFFSET 1 - -/*struct aligned_buffer { - char garbage[0]; - elem_t data[DIM][DIM]; -} __attribute__((__packed__));*/ - -struct offset_buffer { - elem_t garbage[OFFSET]; - elem_t data[DIM][DIM]; -} __attribute__((__packed__)); - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // static struct aligned_buffer In __attribute__((aligned(PG_SIZE))); - static struct offset_buffer In __attribute__((aligned(PG_SIZE))); - static struct offset_buffer Out __attribute__((aligned(PG_SIZE))); - - for (size_t i = 0; i < OFFSET; ++i) { - In.garbage[i] = ~0; - Out.garbage[i] = 1; - } - - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { - In.data[i][j] = i * DIM + j; - Out.data[i][j] = 1; - } - - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - // printf("Mvin\n"); - gemmini_mvin(In.data, 0); - // printf("Mvout\n"); - gemmini_mvout(Out.data, 0); - - // printf("Fence\n"); - gemmini_fence(); - - if (!is_equal(In.data, Out.data)) { - printf("Matrix:\n"); - printMatrix(In.data); - printf("Matrix output:\n"); - printMatrix(Out.data); - printf("\n"); - - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv.c b/bb-tests/workloads/src/CTest/gemmini/conv.c deleted file mode 100644 index 073e8cae..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv.c +++ /dev/null @@ -1,337 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != (in_row_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - exit(1); - } - - if (out_col_dim != (in_col_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions (rows by columns): %u by %u\n", IN_ROW_DIM, - IN_COL_DIM); - printf("Output dimensions (rows by columns): %u by %u\n\n", OUT_ROW_DIM, - OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, PADDING, input, weights, - bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_dw.c b/bb-tests/workloads/src/CTest/gemmini/conv_dw.c deleted file mode 100644 index 89992329..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_dw.c +++ /dev/null @@ -1,247 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 3 -#define IN_ROW_DIM 112 -#define IN_COL_DIM 112 -#define CHANNELS 17 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define CHANNELS 5 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define CHANNELS 15 - -#endif - -#define BATCH_SIZE 3 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][CHANNELS]; - static elem_t weights[CHANNELS][KERNEL_DIM][KERNEL_DIM]; - static acc_t bias[CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - tiled_conv_dw_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, CHANNELS, OUT_ROW_DIM, - OUT_COL_DIM, STRIDE, PADDING, KERNEL_DIM, - - (elem_t *)input, (elem_t *)weights, (acc_t *)bias, - (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 1, 0, 0, - - CPU); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t output_mat[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][CHANNELS]; - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_dw_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, CHANNELS, OUT_ROW_DIM, - OUT_COL_DIM, STRIDE, PADDING, KERNEL_DIM, - - (elem_t *)input, (elem_t *)weights, (acc_t *)bias, - (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 1, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int i = 0; i < sizeof(output_mat) / sizeof(output_mat[0]); i++) { - elem_t v = *((elem_t *)output_mat + i); - if (v != 5 && v != 7 && v != 10) { - success = false; - break; - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0][0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("%d,", weights[och][wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < CHANNELS; och++) { - printf("%d,", output_mat[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_dw_perf.c b/bb-tests/workloads/src/CTest/gemmini/conv_dw_perf.c deleted file mode 100644 index 2f71be6a..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_dw_perf.c +++ /dev/null @@ -1,103 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define HEAP_SIZE (8 * 1024 * 1024) - -int str2int(char *str) { - int res = 0; - for (int i = 0; str[i] != '\0'; ++i) - res = res * 10 + str[i] - '0'; - return res; -} - -int main(int argc, char *argv[]) { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - int BATCH_SIZE = 3; - int IN_DIM = 112; - int CHANNELS = 17; - int KERNEL_DIM = 3; - int PADDING = 1; - int STRIDE = 2; - bool NO_BIAS = false; - - if (argc == 8) { - BATCH_SIZE = str2int(argv[1]); - IN_DIM = str2int(argv[2]); - CHANNELS = str2int(argv[3]); - KERNEL_DIM = str2int(argv[4]); - PADDING = str2int(argv[5]); - STRIDE = str2int(argv[6]); - NO_BIAS = str2int(argv[7]); - } else if (argc > 1) { - printf("BATCH_SIZE IN_DIM CHANNELS KERNEL_DIM PADDING STRIDE NO_BIAS\n"); - exit(1); - } - - int OUT_DIM = ((IN_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1); - - printf("BATCH_SIZE = %d\n", BATCH_SIZE); - printf("IN_DIM = %d\n", IN_DIM); - printf("CHANNELS = %d\n", CHANNELS); - printf("KERNEL_DIM = %d\n", KERNEL_DIM); - printf("PADDING = %d\n", PADDING); - printf("STRIDE = %d\n", STRIDE); - printf("NO_BIAS = %d\n", NO_BIAS); - - gemmini_flush(0); - - printf("Output dimension: %u\n\n", OUT_DIM); - - static uint8_t heap[HEAP_SIZE]; - - // static elem_t input[BATCH_SIZE][IN_DIM][IN_DIM][CHANNELS]; - // static elem_t weights[CHANNELS][KERNEL_DIM][KERNEL_DIM]; - // static acc_t bias[CHANNELS]; - // static elem_t output[BATCH_SIZE][OUT_DIM][OUT_DIM][CHANNELS]; - - elem_t *input = (elem_t *)(&heap[0]); - elem_t *weights = - (elem_t *)((elem_t *)input + BATCH_SIZE * IN_DIM * IN_DIM * CHANNELS); - acc_t *bias = - (acc_t *)((elem_t *)weights + CHANNELS * KERNEL_DIM * KERNEL_DIM); - elem_t *output = (elem_t *)((acc_t *)bias + CHANNELS); - - { - uint8_t *end = (uint8_t *)((elem_t *)output + - BATCH_SIZE * OUT_DIM * OUT_DIM * CHANNELS); - if (end >= &heap[HEAP_SIZE]) { - printf("problem size is too large to fit in memory"); - exit(1); - } - } - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - - tiled_conv_dw_auto(BATCH_SIZE, IN_DIM, IN_DIM, CHANNELS, OUT_DIM, OUT_DIM, - STRIDE, PADDING, KERNEL_DIM, - - (elem_t *)input, (elem_t *)weights, (acc_t *)bias, - (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 1, 0, 0, - - WS); - - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_first_layer.c b/bb-tests/workloads/src/CTest/gemmini/conv_first_layer.c deleted file mode 100644 index 222ff264..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_first_layer.c +++ /dev/null @@ -1,337 +0,0 @@ -// Here, we test Gemmini's optimizations for conv layers with few input -// channels, like the first layer of most CNNs. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != (in_row_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - exit(1); - } - if (out_col_dim != (in_col_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, PADDING, input, weights, - bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 13 && v != 19 && v != 28) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_perf.c b/bb-tests/workloads/src/CTest/gemmini/conv_perf.c deleted file mode 100644 index 4fe2cf4e..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_perf.c +++ /dev/null @@ -1,128 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define HEAP_SIZE (4 * 1024 * 1024) - -int str2int(char *str) { - int res = 0; - for (int i = 0; str[i] != '\0'; ++i) - res = res * 10 + str[i] - '0'; - return res; -} - -int main(int argc, char *argv[]) { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - int BATCH_SIZE = 4; - int IN_DIM = 224; - int IN_CHANNELS = 3; - int OUT_CHANNELS = 32; - int KERNEL_DIM = 3; - int PADDING = 1; - int STRIDE = 2; - bool NO_BIAS = false; - - if (argc == 9) { - BATCH_SIZE = str2int(argv[1]); - IN_DIM = str2int(argv[2]); - IN_CHANNELS = str2int(argv[3]); - OUT_CHANNELS = str2int(argv[4]); - KERNEL_DIM = str2int(argv[5]); - PADDING = str2int(argv[6]); - STRIDE = str2int(argv[7]); - NO_BIAS = str2int(argv[8]); - } else if (argc > 1) { - printf("BATCH_SIZE IN_DIM IN_CHANNELS OUT_CHANNELS KERNEL_DIM PADDING " - "STRIDE NO_BIAS\n"); - exit(1); - } - - int OUT_DIM = ((IN_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1); - - printf("BATCH_SIZE = %d\n", BATCH_SIZE); - printf("IN_DIM = %d\n", IN_DIM); - printf("IN_CHANNELS = %d\n", IN_CHANNELS); - printf("OUT_CHANNELS = %d\n", OUT_CHANNELS); - printf("KERNEL_DIM = %d\n", KERNEL_DIM); - printf("PADDING = %d\n", PADDING); - printf("STRIDE = %d\n", STRIDE); - printf("NO_BIAS = %d\n", NO_BIAS); - printf("Output dimension: %u\n\n", OUT_DIM); - - bool map_to_matmul = KERNEL_DIM == 1 && PADDING == 0 && STRIDE == 1; - int I = BATCH_SIZE * OUT_DIM * OUT_DIM; - int J = OUT_CHANNELS; - int K = KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; - - if (map_to_matmul) { - printf("I = %d\n", I); - printf("J = %d\n", J); - printf("K = %d\n", K); - } - - gemmini_flush(0); - - static uint8_t heap[HEAP_SIZE]; - - // static elem_t input[BATCH_SIZE][IN_DIM][IN_DIM][IN_CHANNELS]; - // static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - // static acc_t bias[OUT_CHANNELS]; - // static elem_t output[BATCH_SIZE][OUT_DIM][OUT_DIM][OUT_CHANNELS]; - - elem_t *input = (elem_t *)(&heap[0]); - elem_t *weights = - (elem_t *)((elem_t *)input + BATCH_SIZE * IN_DIM * IN_DIM * IN_CHANNELS); - acc_t *bias = (acc_t *)((elem_t *)weights + - OUT_CHANNELS * KERNEL_DIM * KERNEL_DIM * IN_CHANNELS); - elem_t *output = (elem_t *)((acc_t *)bias + OUT_CHANNELS); - - { - uint8_t *end = (uint8_t *)((elem_t *)output + - BATCH_SIZE * OUT_DIM * OUT_DIM * OUT_CHANNELS); - if (end >= &heap[HEAP_SIZE]) { - printf("problem size is too large to fit in memory"); - exit(1); - } - } - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - - if (map_to_matmul) { - - tiled_matmul_auto(I, J, K, input, weights, NO_BIAS ? NULL : bias, output, K, - J, J, J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - true, false, false, false, false, 0, WS); - - } else { - - tiled_conv_auto(BATCH_SIZE, IN_DIM, IN_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_DIM, OUT_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, false, - false, false, false, false, - - (elem_t *)input, (elem_t *)weights, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - } - - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_rect.c b/bb-tests/workloads/src/CTest/gemmini/conv_rect.c deleted file mode 100644 index d5e9f74b..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_rect.c +++ /dev/null @@ -1,337 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 7 -#define IN_COL_DIM 11 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 18 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != (in_row_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - exit(1); - } - - if (out_col_dim != (in_col_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions (rows by columns): %u by %u\n", IN_ROW_DIM, - IN_COL_DIM); - printf("Output dimensions (rows by columns): %u by %u\n\n", OUT_ROW_DIM, - OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, PADDING, input, weights, - bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_rect_pool.c b/bb-tests/workloads/src/CTest/gemmini/conv_rect_pool.c deleted file mode 100644 index 8e2ddab2..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_rect_pool.c +++ /dev/null @@ -1,431 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#define POOL_SIZE 3 -#define POOL_STRIDE 2 -#define POOL_PADDING 1 - -#else - -#ifdef FAST -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 -#else -#define IN_ROW_DIM 9 -#define IN_COL_DIM 11 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 12 -#endif - -#define BATCH_SIZE 1 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 - -#define POOL_SIZE 3 -#define POOL_STRIDE 2 -#define POOL_PADDING 1 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -#define POOL_OUT_ROW_DIM \ - ((OUT_ROW_DIM + 2 * POOL_PADDING - POOL_SIZE) / POOL_STRIDE + 1) -#define POOL_OUT_COL_DIM \ - ((OUT_COL_DIM + 2 * POOL_PADDING - POOL_SIZE) / POOL_STRIDE + 1) - -#define NO_POOL false - -#if NO_POOL == true && \ - !(POOL_SIZE == 1 && POOL_STRIDE == 1 && POOL_PADDING == 0) -#error NO_POOL is not set correctly -#endif - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != (in_row_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - exit(1); - } - if (out_col_dim != (in_col_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void pool(int batch_size, int channels, int in_row_dim, int in_col_dim, - int out_row_dim, int out_col_dim, int window_dim, int stride, - int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][channels], - elem_t output[batch_size][out_row_dim][out_col_dim][channels]) { - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int ch = 0; ch < channels; ch++) { - output[b][orow][ocol][ch] = elem_t_min; - - for (int wrow = 0; wrow < window_dim; wrow++) { - for (int wcol = 0; wcol < window_dim; wcol++) { - int irow = orow * stride + wrow - padding; - int icol = ocol * stride + wcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][ch]; - - if (pixel > output[b][orow][ocol][ch]) { - output[b][orow][ocol][ch] = pixel; - } - } - } - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((IN_DIM + 2*PADDING - KERNEL_DIM) % STRIDE == 0); - // assert((OUT_DIM + 2*PADDING - POOL_SIZE) % POOL_STRIDE == 0); - - printf("Output dimensions (rows by columns): %u by %u\n", OUT_ROW_DIM, - OUT_COL_DIM); - printf("Pooling output dimensions (rows by columns): %u by %u\n\n", - POOL_OUT_ROW_DIM, POOL_OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - static elem_t pool_output[BATCH_SIZE][POOL_OUT_ROW_DIM][POOL_OUT_COL_DIM] - [OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - -#ifndef FAST - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, PADDING, input, weights, - bias, output); - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("CPU pool...\n"); - uint64_t start_cpu_pool = read_cycles(); - pool(BATCH_SIZE, OUT_CHANNELS, OUT_ROW_DIM, OUT_COL_DIM, POOL_OUT_ROW_DIM, - POOL_OUT_COL_DIM, POOL_SIZE, POOL_STRIDE, POOL_PADDING, output, - pool_output); - uint64_t end_cpu_pool = read_cycles(); - printf("CPU pool took %llu cycles\n", end_cpu_pool - start_cpu_pool); - - printf("CPU conv+pool took %llu cycles\n", - end_cpu_pool - start_cpu_pool + end_cpu - start_cpu); -#endif - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - static elem_t pool_output_mat[BATCH_SIZE * POOL_OUT_ROW_DIM * - POOL_OUT_COL_DIM][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, false, false, false, false, - - // 1, - // 1, 1, 1, - // 1, 1, 1, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)pool_output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, POOL_SIZE, - NO_POOL ? 0 : POOL_STRIDE, POOL_PADDING, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(pool_output_mat) == sizeof(pool_output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * POOL_OUT_ROW_DIM * POOL_OUT_COL_DIM; - orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - if (pool_output_mat[orow][ocol] != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&pool_output[0][0][0][0], &pool_output_mat[0][0], - sizeof(pool_output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("pool_output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < POOL_OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < POOL_OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", pool_output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("pool_output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * POOL_OUT_ROW_DIM * POOL_OUT_COL_DIM; - orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", pool_output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("Output dimensions (rows by columns): %u by %u\n", OUT_ROW_DIM, - OUT_COL_DIM); - printf("Pooling output dimensions: %u by %u\n\n", POOL_OUT_ROW_DIM, - POOL_OUT_COL_DIM); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_stride.c b/bb-tests/workloads/src/CTest/gemmini/conv_stride.c deleted file mode 100644 index 074ad8c8..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_stride.c +++ /dev/null @@ -1,309 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#define IN_ROW_DIM 7 -#define IN_COL_DIM 7 -#define IN_CHANNELS 13 -#define OUT_CHANNELS 17 -#define BATCH_SIZE 1 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -#define IN_STRIDE (IN_CHANNELS + 3) -#define WEIGHT_STRIDE (OUT_CHANNELS + 4) -#define OUT_STRIDE (OUT_CHANNELS + 2) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int padding, int in_stride, int out_stride, - elem_t input[batch_size][in_row_dim][in_col_dim][in_stride], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_stride]) { - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != (in_row_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - exit(1); - } - - if (out_col_dim != (in_col_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - int out_stride, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_stride]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int row, int col, int stride) { - elem_t i = 0; - for (int r = 0; r < row; r++) { - for (int c = 0; c < col; c++) { - elem_t *ptr = buf + r * stride + c; - *ptr = (rand() % 5) - 2; - } - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; - *ptr = (rand() % 5) - 2; - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - gemmini_flush(0); - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions (rows by columns): %u by %u\n", IN_ROW_DIM, - IN_COL_DIM); - printf("Output dimensions (rows by columns): %u by %u\n\n", OUT_ROW_DIM, - OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_STRIDE]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_STRIDE]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], BATCH_SIZE * IN_ROW_DIM * IN_COL_DIM, - IN_CHANNELS, IN_STRIDE); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], OUT_CHANNELS * KERNEL_DIM * KERNEL_DIM, - IN_CHANNELS, IN_CHANNELS); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, PADDING, IN_STRIDE, - OUT_STRIDE, input, weights, bias, output); - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][WEIGHT_STRIDE] = {0}; - static elem_t output_mat[N_PATCHES][OUT_STRIDE] = {0}; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, - WEIGHT_STRIDE, weights, weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_stride_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, - OUT_CHANNELS, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, - PADDING, KERNEL_DIM, IN_STRIDE, WEIGHT_STRIDE, - OUT_STRIDE, false, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < WEIGHT_STRIDE; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_STRIDE; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_STRIDE; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],\n"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_STRIDE; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_trans_input_3120.c b/bb-tests/workloads/src/CTest/gemmini/conv_trans_input_3120.c deleted file mode 100644 index 8c82a97c..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_trans_input_3120.c +++ /dev/null @@ -1,295 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define TRANS_OUTPUT_1203 false -#define TRANS_WEIGHT_1203 false -#define TRANS_WEIGHT_0132 false -#define TRANS_INPUT_3120 true - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS][BATCH_SIZE]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, TRANS_INPUT_3120, TRANS_WEIGHT_1203, - TRANS_WEIGHT_0132, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - CPU); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, TRANS_INPUT_3120, TRANS_WEIGHT_1203, - TRANS_WEIGHT_0132, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[irow][icol][ich][batch]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_trans_input_3120_with_kernel_dilation.c b/bb-tests/workloads/src/CTest/gemmini/conv_trans_input_3120_with_kernel_dilation.c deleted file mode 100644 index 560a1560..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_trans_input_3120_with_kernel_dilation.c +++ /dev/null @@ -1,297 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define KERNEL_DILATION 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define KERNEL_DILATION 2 - -#endif - -#define NO_BIAS false - -#define TRANS_OUTPUT_1203 false -#define TRANS_WEIGHT_1203 false -#define TRANS_WEIGHT_0132 false -#define TRANS_INPUT_3120 true - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, KERNEL_DILATION, PADDING, - KERNEL_DIM, false, TRANS_OUTPUT_1203, TRANS_INPUT_3120, - TRANS_WEIGHT_1203, TRANS_WEIGHT_0132, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - CPU); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, KERNEL_DILATION, PADDING, - KERNEL_DIM, false, TRANS_OUTPUT_1203, TRANS_INPUT_3120, - TRANS_WEIGHT_1203, TRANS_WEIGHT_0132, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 6 && v != 11 && v != 16 && v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_trans_output_1203.c b/bb-tests/workloads/src/CTest/gemmini/conv_trans_output_1203.c deleted file mode 100644 index 904aa8ef..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_trans_output_1203.c +++ /dev/null @@ -1,290 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define TRANS_OUTPUT_1203 true - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - CPU); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_trans_weight_0132.c b/bb-tests/workloads/src/CTest/gemmini/conv_trans_weight_0132.c deleted file mode 100644 index 4a42fc23..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_trans_weight_0132.c +++ /dev/null @@ -1,294 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define TRANS_OUTPUT_1203 false -#define TRANS_WEIGHT_1203 false -#define TRANS_WEIGHT_0132 true - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, false, TRANS_WEIGHT_1203, - TRANS_WEIGHT_0132, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - CPU); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, false, TRANS_WEIGHT_1203, - TRANS_WEIGHT_0132, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_trans_weight_1203.c b/bb-tests/workloads/src/CTest/gemmini/conv_trans_weight_1203.c deleted file mode 100644 index 297763e9..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_trans_weight_1203.c +++ /dev/null @@ -1,291 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 17 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#endif - -#define NO_BIAS false - -#define TRANS_OUTPUT_1203 false -#define TRANS_WEIGHT_1203 true - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, false, TRANS_WEIGHT_1203, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - CPU); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, TRANS_OUTPUT_1203, false, TRANS_WEIGHT_1203, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation.c b/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation.c deleted file mode 100644 index 4b0fffcd..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation.c +++ /dev/null @@ -1,380 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 17 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 23 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 - -#endif - -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 2 - -#endif - -#define NO_BIAS false - -#define IN_ROW_DIM_DILATED \ - (IN_ROW_DIM + (INPUT_DILATION - 1) * (IN_ROW_DIM - 1)) -#define IN_COL_DIM_DILATED \ - (IN_COL_DIM + (INPUT_DILATION - 1) * (IN_COL_DIM - 1)) -#define OUT_ROW_DIM \ - ((IN_ROW_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM \ - ((IN_COL_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int input_dilation, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - - const size_t in_row_dim_dilated = - in_row_dim + (input_dilation - 1) * (in_row_dim - 1); - const size_t in_col_dim_dilated = - in_col_dim + (input_dilation - 1) * (in_col_dim - 1); - assert(in_row_dim_dilated == IN_ROW_DIM_DILATED); - assert(in_col_dim_dilated == IN_COL_DIM_DILATED); - static elem_t dilated[BATCH_SIZE][IN_ROW_DIM_DILATED][IN_COL_DIM_DILATED] - [IN_CHANNELS]; - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != - (in_row_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - printf("out_row_dim\n"); - exit(1); - } - if (out_col_dim != - (in_col_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - printf("out_col_dim\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow++) - for (int icol = 0; icol < in_col_dim_dilated; icol++) - for (int ich = 0; ich < in_channels; ich++) - dilated[b][irow][icol][ich] = 0; - - size_t idx = 0; - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow += input_dilation) - for (int icol = 0; icol < in_col_dim_dilated; icol += input_dilation) - for (int ich = 0; ich < in_channels; ich++) { - dilated[b][irow][icol][ich] = *((elem_t *)input + idx); - idx++; - } - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim_dilated || - icol < 0 || icol >= in_col_dim_dilated - ? 0 - : dilated[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, PADDING, - input, weights, bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, 1, PADDING, - KERNEL_DIM, false, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 6 && v != 11 && v != 21) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation_and_neg_padding.c b/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation_and_neg_padding.c deleted file mode 100644 index 85cd1eaf..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation_and_neg_padding.c +++ /dev/null @@ -1,373 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 17 -#define KERNEL_DIM 3 -#define PADDING -1 -#define STRIDE 1 -#define INPUT_DILATION 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING -1 -#define STRIDE 1 -#define INPUT_DILATION 2 - -#endif - -#define NO_BIAS false - -#define IN_ROW_DIM_DILATED \ - (IN_ROW_DIM + (INPUT_DILATION - 1) * (IN_ROW_DIM - 1)) -#define IN_COL_DIM_DILATED \ - (IN_COL_DIM + (INPUT_DILATION - 1) * (IN_COL_DIM - 1)) -#define OUT_ROW_DIM \ - ((IN_ROW_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM \ - ((IN_COL_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int input_dilation, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - - const size_t in_row_dim_dilated = - in_row_dim + (input_dilation - 1) * (in_row_dim - 1); - const size_t in_col_dim_dilated = - in_col_dim + (input_dilation - 1) * (in_col_dim - 1); - assert(in_row_dim_dilated == IN_ROW_DIM_DILATED); - assert(in_col_dim_dilated == IN_COL_DIM_DILATED); - static elem_t dilated[BATCH_SIZE][IN_ROW_DIM_DILATED][IN_COL_DIM_DILATED] - [IN_CHANNELS]; - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != - (in_row_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - printf("out_row_dim\n"); - exit(1); - } - if (out_col_dim != - (in_col_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - printf("out_col_dim\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow++) - for (int icol = 0; icol < in_col_dim_dilated; icol++) - for (int ich = 0; ich < in_channels; ich++) - dilated[b][irow][icol][ich] = 0; - - size_t idx = 0; - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow += input_dilation) - for (int icol = 0; icol < in_col_dim_dilated; icol += input_dilation) - for (int ich = 0; ich < in_channels; ich++) { - dilated[b][irow][icol][ich] = *((elem_t *)input + idx); - idx++; - } - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim_dilated || - icol < 0 || icol >= in_col_dim_dilated - ? 0 - : dilated[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Dilated input dimensions: %u by %u\n", IN_ROW_DIM_DILATED, - IN_COL_DIM_DILATED); - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, PADDING, - input, weights, bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, 1, PADDING, - KERNEL_DIM, false, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - // CPU); - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 6 && v != 11 && v != 21) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation_and_rot180.c b/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation_and_rot180.c deleted file mode 100644 index d226d8c2..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_with_input_dilation_and_rot180.c +++ /dev/null @@ -1,387 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 17 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 2 - -#endif - -#define NO_BIAS false - -#define WROT180 true - -#define IN_ROW_DIM_DILATED \ - (IN_ROW_DIM + (INPUT_DILATION - 1) * (IN_ROW_DIM - 1)) -#define IN_COL_DIM_DILATED \ - (IN_COL_DIM + (INPUT_DILATION - 1) * (IN_COL_DIM - 1)) -#define OUT_ROW_DIM \ - ((IN_ROW_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM \ - ((IN_COL_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int input_dilation, int padding, bool wrot180, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - - const size_t in_row_dim_dilated = - in_row_dim + (input_dilation - 1) * (in_row_dim - 1); - const size_t in_col_dim_dilated = - in_col_dim + (input_dilation - 1) * (in_col_dim - 1); - assert(in_row_dim_dilated == IN_ROW_DIM_DILATED); - assert(in_col_dim_dilated == IN_COL_DIM_DILATED); - static elem_t dilated[BATCH_SIZE][IN_ROW_DIM_DILATED][IN_COL_DIM_DILATED] - [IN_CHANNELS]; - - static elem_t weights_rot180[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM] - [IN_CHANNELS]; - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != - (in_row_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - printf("out_row_dim\n"); - exit(1); - } - if (out_col_dim != - (in_col_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - printf("out_col_dim\n"); - exit(1); - } -#endif - - // Populate dilated - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow++) - for (int icol = 0; icol < in_col_dim_dilated; icol++) - for (int ich = 0; ich < in_channels; ich++) - dilated[b][irow][icol][ich] = 0; - - size_t idx = 0; - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow += input_dilation) - for (int icol = 0; icol < in_col_dim_dilated; icol += input_dilation) - for (int ich = 0; ich < in_channels; ich++) { - dilated[b][irow][icol][ich] = *((elem_t *)input + idx); - idx++; - } - - // Populate weights_rot180 - for (int och = 0; och < out_channels; och++) - for (int krow = 0; krow < kernel_dim; krow++) - for (int kcol = 0; kcol < kernel_dim; kcol++) - for (int kch = 0; kch < in_channels; kch++) - weights_rot180[och][krow][kcol][kch] = - weights[och][kernel_dim - krow - 1][kernel_dim - kcol - 1][kch]; - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim_dilated || - icol < 0 || icol >= in_col_dim_dilated - ? 0 - : dilated[b][irow][icol][kch]; - - elem_t w = wrot180 ? weights_rot180[och][krow][kcol][kch] - : weights[och][krow][kcol][kch]; - - result += w * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, PADDING, - WROT180, input, weights, bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, 1, PADDING, - KERNEL_DIM, WROT180, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 6 && v != 11 && v != 21) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_with_kernel_dilation.c b/bb-tests/workloads/src/CTest/gemmini/conv_with_kernel_dilation.c deleted file mode 100644 index 326633fc..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_with_kernel_dilation.c +++ /dev/null @@ -1,396 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 17 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 -#define INPUT_DILATION 1 -#define KERNEL_DILATION 2 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 1 -#define KERNEL_DILATION 2 - -#endif - -#define NO_BIAS false - -#define IN_ROW_DIM_DILATED \ - (IN_ROW_DIM + (INPUT_DILATION - 1) * (IN_ROW_DIM - 1)) -#define IN_COL_DIM_DILATED \ - (IN_COL_DIM + (INPUT_DILATION - 1) * (IN_COL_DIM - 1)) -#define KERNEL_DIM_DILATED \ - (KERNEL_DIM + (KERNEL_DILATION - 1) * (KERNEL_DIM - 1)) -#define OUT_ROW_DIM \ - ((IN_ROW_DIM_DILATED + 2 * PADDING - KERNEL_DIM_DILATED) / STRIDE + 1) -#define OUT_COL_DIM \ - ((IN_COL_DIM_DILATED + 2 * PADDING - KERNEL_DIM_DILATED) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int input_dilation, int kernel_dilation, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - - const size_t in_row_dim_dilated = - in_row_dim + (input_dilation - 1) * (in_row_dim - 1); - const size_t in_col_dim_dilated = - in_col_dim + (input_dilation - 1) * (in_col_dim - 1); - assert(in_row_dim_dilated == IN_ROW_DIM_DILATED); - assert(in_col_dim_dilated == IN_COL_DIM_DILATED); - static elem_t dilated[BATCH_SIZE][IN_ROW_DIM_DILATED][IN_COL_DIM_DILATED] - [IN_CHANNELS]; - - const size_t kernel_dim_dilated = - kernel_dim + (kernel_dilation - 1) * (kernel_dim - 1); - assert(kernel_dim_dilated == KERNEL_DIM_DILATED); - static elem_t weights_dilated[OUT_CHANNELS][KERNEL_DIM_DILATED] - [KERNEL_DIM_DILATED][IN_CHANNELS]; - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != - (in_row_dim_dilated + 2 * padding - kernel_dim_dilated) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - printf("out_row_dim\n"); - exit(1); - } - if (out_col_dim != - (in_col_dim_dilated + 2 * padding - kernel_dim_dilated) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - printf("out_col_dim\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow++) - for (int icol = 0; icol < in_col_dim_dilated; icol++) - for (int ich = 0; ich < in_channels; ich++) - dilated[b][irow][icol][ich] = 0; - - size_t idx = 0; - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow += input_dilation) - for (int icol = 0; icol < in_col_dim_dilated; icol += input_dilation) - for (int ich = 0; ich < in_channels; ich++) { - dilated[b][irow][icol][ich] = *((elem_t *)input + idx); - idx++; - } - - for (int och = 0; och < out_channels; och++) - for (int krow = 0; krow < kernel_dim_dilated; krow++) - for (int kcol = 0; kcol < kernel_dim_dilated; kcol++) - for (int kch = 0; kch < in_channels; kch++) - weights_dilated[och][krow][kcol][kch] = 0; - - idx = 0; - for (int och = 0; och < out_channels; och++) - for (int krow = 0; krow < kernel_dim_dilated; krow += kernel_dilation) - for (int kcol = 0; kcol < kernel_dim_dilated; kcol += kernel_dilation) - for (int kch = 0; kch < in_channels; kch++) { - weights_dilated[och][krow][kcol][kch] = *((elem_t *)weights + idx); - idx++; - } - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim_dilated; krow++) { - for (int kcol = 0; kcol < kernel_dim_dilated; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim_dilated || - icol < 0 || icol >= in_col_dim_dilated - ? 0 - : dilated[b][irow][icol][kch]; - - result += weights_dilated[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, - KERNEL_DILATION, PADDING, input, weights, bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, - KERNEL_DILATION, PADDING, KERNEL_DIM, false, false, false, - false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_with_pool.c b/bb-tests/workloads/src/CTest/gemmini/conv_with_pool.c deleted file mode 100644 index a5eb558e..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_with_pool.c +++ /dev/null @@ -1,431 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 32 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#define POOL_SIZE 3 -#define POOL_STRIDE 2 -#define POOL_PADDING 1 - -#else - -#ifdef FAST -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 -#else -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 2 - -#define POOL_SIZE 3 -#define POOL_STRIDE 2 -#define POOL_PADDING 1 - -#endif - -#define NO_BIAS false - -#define OUT_ROW_DIM ((IN_ROW_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM ((IN_COL_DIM + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -#define POOL_OUT_ROW_DIM \ - ((OUT_ROW_DIM + 2 * POOL_PADDING - POOL_SIZE) / POOL_STRIDE + 1) -#define POOL_OUT_COL_DIM \ - ((OUT_COL_DIM + 2 * POOL_PADDING - POOL_SIZE) / POOL_STRIDE + 1) - -#define NO_POOL false - -#if NO_POOL == true && \ - !(POOL_SIZE == 1 && POOL_STRIDE == 1 && POOL_PADDING == 0) -#error NO_POOL is not set correctly -#endif - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != (in_row_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - exit(1); - } - if (out_col_dim != (in_col_dim + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - exit(1); - } -#endif - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][kch]; - - result += weights[och][krow][kcol][kch] * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void pool(int batch_size, int channels, int in_row_dim, int in_col_dim, - int out_row_dim, int out_col_dim, int window_dim, int stride, - int padding, - elem_t input[batch_size][in_row_dim][in_col_dim][channels], - elem_t output[batch_size][out_row_dim][out_col_dim][channels]) { - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int ch = 0; ch < channels; ch++) { - output[b][orow][ocol][ch] = elem_t_min; - - for (int wrow = 0; wrow < window_dim; wrow++) { - for (int wcol = 0; wcol < window_dim; wcol++) { - int irow = orow * stride + wrow - padding; - int icol = ocol * stride + wcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : input[b][irow][icol][ch]; - - if (pixel > output[b][orow][ocol][ch]) { - output[b][orow][ocol][ch] = pixel; - } - } - } - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((IN_DIM + 2*PADDING - KERNEL_DIM) % STRIDE == 0); - // assert((OUT_DIM + 2*PADDING - POOL_SIZE) % POOL_STRIDE == 0); - - printf("Output dimensions (rows by columns): %u by %u\n", OUT_ROW_DIM, - OUT_COL_DIM); - printf("Pooling output dimensions (rows by columns): %u by %u\n\n", - POOL_OUT_ROW_DIM, POOL_OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - static elem_t pool_output[BATCH_SIZE][POOL_OUT_ROW_DIM][POOL_OUT_COL_DIM] - [OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - -#ifndef FAST - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, PADDING, input, weights, - bias, output); - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - printf("CPU pool...\n"); - uint64_t start_cpu_pool = read_cycles(); - pool(BATCH_SIZE, OUT_CHANNELS, OUT_ROW_DIM, OUT_COL_DIM, POOL_OUT_ROW_DIM, - POOL_OUT_COL_DIM, POOL_SIZE, POOL_STRIDE, POOL_PADDING, output, - pool_output); - uint64_t end_cpu_pool = read_cycles(); - printf("CPU pool took %llu cycles\n", end_cpu_pool - start_cpu_pool); - - printf("CPU conv+pool took %llu cycles\n", - end_cpu_pool - start_cpu_pool + end_cpu - start_cpu); -#endif - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - static elem_t pool_output_mat[BATCH_SIZE * POOL_OUT_ROW_DIM * - POOL_OUT_COL_DIM][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, 1, 1, PADDING, KERNEL_DIM, - false, false, false, false, false, - - // 1, - // 1, 1, 1, - // 1, 1, 1, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)pool_output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, POOL_SIZE, - NO_POOL ? 0 : POOL_STRIDE, POOL_PADDING, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(pool_output_mat) == sizeof(pool_output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * POOL_OUT_ROW_DIM * POOL_OUT_COL_DIM; - orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - if (pool_output_mat[orow][ocol] != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&pool_output[0][0][0][0], &pool_output_mat[0][0], - sizeof(pool_output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("pool_output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < POOL_OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < POOL_OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", pool_output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("pool_output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * POOL_OUT_ROW_DIM * POOL_OUT_COL_DIM; - orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", pool_output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("Output dimensions (rows by columns): %u by %u\n", OUT_ROW_DIM, - OUT_COL_DIM); - printf("Pooling output dimensions: %u by %u\n\n", POOL_OUT_ROW_DIM, - POOL_OUT_COL_DIM); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/conv_with_rot180.c b/bb-tests/workloads/src/CTest/gemmini/conv_with_rot180.c deleted file mode 100644 index e511641b..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/conv_with_rot180.c +++ /dev/null @@ -1,387 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCH_SIZE 4 -#define IN_ROW_DIM 224 -#define IN_COL_DIM 224 -#define IN_CHANNELS 3 -#define OUT_CHANNELS 17 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 1 - -#else - -#ifdef FAST - -#define IN_ROW_DIM 9 -#define IN_COL_DIM 9 -#define IN_CHANNELS 5 -#define OUT_CHANNELS 7 - -#else - -#define IN_ROW_DIM 17 -#define IN_COL_DIM 17 -#define IN_CHANNELS 18 -#define OUT_CHANNELS 19 - -#endif - -#define BATCH_SIZE 2 -#define KERNEL_DIM 3 -#define PADDING 1 -#define STRIDE 1 -#define INPUT_DILATION 1 - -#endif - -#define NO_BIAS false - -#define WROT180 true - -#define IN_ROW_DIM_DILATED \ - (IN_ROW_DIM + (INPUT_DILATION - 1) * (IN_ROW_DIM - 1)) -#define IN_COL_DIM_DILATED \ - (IN_COL_DIM + (INPUT_DILATION - 1) * (IN_COL_DIM - 1)) -#define OUT_ROW_DIM \ - ((IN_ROW_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define OUT_COL_DIM \ - ((IN_COL_DIM_DILATED + 2 * PADDING - KERNEL_DIM) / STRIDE + 1) -#define PATCH_SIZE (KERNEL_DIM * KERNEL_DIM * IN_CHANNELS) -#define N_PATCHES (BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM) - -void conv(int batch_size, int in_channels, int in_row_dim, int in_col_dim, - int out_channels, int kernel_dim, int out_row_dim, int out_col_dim, - int stride, int input_dilation, int padding, bool wrot180, - elem_t input[batch_size][in_row_dim][in_col_dim][in_channels], - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - acc_t bias[out_channels], - elem_t output[batch_size][out_row_dim][out_col_dim][out_channels]) { - - const size_t in_row_dim_dilated = - in_row_dim + (input_dilation - 1) * (in_row_dim - 1); - const size_t in_col_dim_dilated = - in_col_dim + (input_dilation - 1) * (in_col_dim - 1); - assert(in_row_dim_dilated == IN_ROW_DIM_DILATED); - assert(in_col_dim_dilated == IN_COL_DIM_DILATED); - static elem_t dilated[BATCH_SIZE][IN_ROW_DIM_DILATED][IN_COL_DIM_DILATED] - [IN_CHANNELS]; - - static elem_t weights_rot180[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM] - [IN_CHANNELS]; - -#ifdef GEMMINI_ASSERTIONS - if (out_row_dim != - (in_row_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_row_dim is not correct\n"); - printf("out_row_dim\n"); - exit(1); - } - if (out_col_dim != - (in_col_dim_dilated + 2 * padding - kernel_dim) / stride + 1) { - printf("conv out_col_dim is not correct\n"); - printf("out_col_dim\n"); - exit(1); - } -#endif - - // Populate dilated - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow++) - for (int icol = 0; icol < in_col_dim_dilated; icol++) - for (int ich = 0; ich < in_channels; ich++) - dilated[b][irow][icol][ich] = 0; - - size_t idx = 0; - for (int b = 0; b < batch_size; b++) - for (int irow = 0; irow < in_row_dim_dilated; irow += input_dilation) - for (int icol = 0; icol < in_col_dim_dilated; icol += input_dilation) - for (int ich = 0; ich < in_channels; ich++) { - dilated[b][irow][icol][ich] = *((elem_t *)input + idx); - idx++; - } - - // Populate weights_rot180 - for (int och = 0; och < out_channels; och++) - for (int krow = 0; krow < kernel_dim; krow++) - for (int kcol = 0; kcol < kernel_dim; kcol++) - for (int kch = 0; kch < in_channels; kch++) - weights_rot180[och][krow][kcol][kch] = - weights[och][kernel_dim - krow - 1][kernel_dim - kcol - 1][kch]; - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - acc_t result = bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int kch = 0; kch < in_channels; kch++) { - int irow = orow * stride + krow - padding; - int icol = ocol * stride + kcol - padding; - - elem_t pixel = irow < 0 || irow >= in_row_dim_dilated || - icol < 0 || icol >= in_col_dim_dilated - ? 0 - : dilated[b][irow][icol][kch]; - - elem_t w = wrot180 ? weights_rot180[och][krow][kcol][kch] - : weights[och][krow][kcol][kch]; - - result += w * pixel; - } - } - } - - // Clip result - result = result > elem_t_max - ? elem_t_max - : (result < elem_t_min ? elem_t_min : result); - - output[b][orow][ocol][och] = result; - } - } - } - } -} - -void flatten_weights( - int out_channels, int kernel_dim, int in_channels, int patch_size, - elem_t weights[out_channels][kernel_dim][kernel_dim][in_channels], - elem_t weights_mat[patch_size][out_channels]) { - - assert(patch_size == kernel_dim * kernel_dim * in_channels); - - for (int outc = 0; outc < out_channels; outc++) { - for (int krow = 0; krow < kernel_dim; krow++) { - for (int kcol = 0; kcol < kernel_dim; kcol++) { - for (int inc = 0; inc < in_channels; inc++) { - int wmatrow = - krow * kernel_dim * in_channels + kcol * in_channels + inc; - - weights_mat[wmatrow][outc] = weights[outc][krow][kcol][inc]; - } - } - } - } -} - -bool vec_is_equal(elem_t *a, elem_t *b, int len) { - for (int i = 0; i < len; i++) - if (a[i] != b[i]) - return false; - return true; -} - -void init_random(elem_t *buf, int len) { - elem_t i = 0; - for (elem_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_random_acc(acc_t *buf, int len) { - elem_t i = 0; - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - // *ptr = (rand() % 32) - 16; -#ifdef FAST - *ptr = 1; -#else - *ptr = (rand() % 5) - 2; -#endif - } -} - -void init_zeros_acc(acc_t *buf, int len) { - for (acc_t *ptr = buf; ptr < buf + len; ptr++) { - *ptr = 0; - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // assert((in_dim + 2*padding - kernel_dim) % stride == 0); - - printf("Input dimensions: %u by %u\n", IN_ROW_DIM, IN_COL_DIM); - printf("Output dimensions: %u by %u\n\n", OUT_ROW_DIM, OUT_COL_DIM); - - static elem_t input[BATCH_SIZE][IN_ROW_DIM][IN_COL_DIM][IN_CHANNELS]; - static elem_t weights[OUT_CHANNELS][KERNEL_DIM][KERNEL_DIM][IN_CHANNELS]; - static acc_t bias[OUT_CHANNELS]; - static elem_t output[BATCH_SIZE][OUT_ROW_DIM][OUT_COL_DIM][OUT_CHANNELS]; - - printf("Randomize inputs...\n"); - init_random(&input[0][0][0][0], sizeof(input) / sizeof(elem_t)); - - printf("Randomize weights...\n"); - init_random(&weights[0][0][0][0], sizeof(weights) / sizeof(elem_t)); - - printf("Randomize bias...\n"); - if (NO_BIAS) - init_zeros_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - else - init_random_acc(&bias[0], sizeof(bias) / sizeof(acc_t)); - - printf("CPU conv...\n"); - uint64_t start_cpu = read_cycles(); -#ifndef FAST - conv(BATCH_SIZE, IN_CHANNELS, IN_ROW_DIM, IN_COL_DIM, OUT_CHANNELS, - KERNEL_DIM, OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, PADDING, - WROT180, input, weights, bias, output); -#endif - uint64_t end_cpu = read_cycles(); - printf("CPU conv took %llu cycles\n", end_cpu - start_cpu); - - static elem_t weights_mat[PATCH_SIZE][OUT_CHANNELS]; - static elem_t output_mat[N_PATCHES][OUT_CHANNELS]; - - printf("Flatten weights...\n"); - flatten_weights(OUT_CHANNELS, KERNEL_DIM, IN_CHANNELS, PATCH_SIZE, weights, - weights_mat); - - printf("Gemmini conv...\n"); - uint64_t start_gemmini = read_cycles(); - tiled_conv_auto(BATCH_SIZE, IN_ROW_DIM, IN_COL_DIM, IN_CHANNELS, OUT_CHANNELS, - OUT_ROW_DIM, OUT_COL_DIM, STRIDE, INPUT_DILATION, 1, PADDING, - KERNEL_DIM, WROT180, false, false, false, false, - - (elem_t *)input, (elem_t *)weights_mat, - NO_BIAS ? NULL : (acc_t *)bias, (elem_t *)output_mat, - - NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, 0, 0, - - WS); - uint64_t end_gemmini = read_cycles(); - printf("Gemmini conv took %llu cycles\n", end_gemmini - start_gemmini); - - assert(sizeof(output_mat) == sizeof(output)); - -#ifdef FAST - bool success = true; - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - elem_t v = output_mat[orow][ocol]; - if (v != 21 && v != 31 && v != 46) { - success = false; - break; - } - } - } -#else - bool success = vec_is_equal(&output[0][0][0][0], &output_mat[0][0], - sizeof(output) / sizeof(elem_t)); -#endif - - if (!success) { - // return 1; - - printf("bias:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", bias[och]); - } - printf("\b\n\n"); - - printf("weights:\n"); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("["); - for (int wrow = 0; wrow < KERNEL_DIM; wrow++) { - printf("["); - for (int wcol = 0; wcol < KERNEL_DIM; wcol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", weights[och][wrow][wcol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("weights_mat:\n"); - for (int wrow = 0; wrow < KERNEL_DIM * KERNEL_DIM * IN_CHANNELS; wrow++) { - printf("["); - for (int wcol = 0; wcol < OUT_CHANNELS; wcol++) { - printf("%d,", weights_mat[wrow][wcol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - printf("input:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int irow = 0; irow < IN_ROW_DIM; irow++) { - printf("["); - for (int icol = 0; icol < IN_COL_DIM; icol++) { - printf("["); - for (int ich = 0; ich < IN_CHANNELS; ich++) { - printf("%d,", input[batch][irow][icol][ich]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output:\n"); - for (int batch = 0; batch < BATCH_SIZE; batch++) { - printf("["); - for (int orow = 0; orow < OUT_ROW_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_COL_DIM; ocol++) { - printf("["); - for (int och = 0; och < OUT_CHANNELS; och++) { - printf("%d,", output[batch][orow][ocol][och]); - } - printf("\b],"); - } - printf("\b],\n"); - } - printf("\b],"); - } - printf("\b\n\n"); - - printf("output_mat:\n"); - for (int orow = 0; orow < BATCH_SIZE * OUT_ROW_DIM * OUT_COL_DIM; orow++) { - printf("["); - for (int ocol = 0; ocol < OUT_CHANNELS; ocol++) { - printf("%d,", output_mat[orow][ocol]); - } - printf("\b],\n"); - } - printf("\b\n\n"); - - return 1; - } - - return 0; -} diff --git a/bb-tests/workloads/src/CTest/gemmini/gemmini_counter.c b/bb-tests/workloads/src/CTest/gemmini/gemmini_counter.c deleted file mode 100644 index 13388e4b..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/gemmini_counter.c +++ /dev/null @@ -1,129 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define N 8 - -#if (N * DIM) > (BANK_NUM * BANK_ROWS) -#error not enough scratchpad space -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - // Set counter and reset - counter_configure(0, LOAD_ACTIVE_CYCLE); - if (counter_read(0) != 0) { - printf("Counter Reset Failed (not equal to 0)\n"); - exit(1); - } - - // Initial matrix - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - static elem_t In[N][DIM][DIM] row_align(1); - static elem_t Out[N][DIM][DIM] row_align(1); - - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) - In[n][i][j] = i * DIM + j + n; - - // Move in - for (size_t i = 0; i < N; i++) { - gemmini_mvin(In[i], i * DIM); - gemmini_mvout(Out[i], i * DIM); - } - - // Check value (should be increasing right now as Gemmini executes in the - // background) - int counter_val = counter_read(0); - - // Take a snapshot - counter_snapshot_take(); - int snapshot_val = counter_read(0); - - // Print first counter value (Syscall takes a lot of time, and we might not - // capture a snapshot when the instructions are still being executed) - printf("Read DMA cycles: %d\n", counter_val); - if (counter_val == 0) { - printf("Counter Value failed to increase\n"); - exit(1); - } - - // Wait till the operation finish - gemmini_fence(); - - // Check again - counter_val = counter_read(0); - printf("Cycle when taking snapshot: %d, Cycle read after operation finished: " - "%d\n", - snapshot_val, counter_val); - if (counter_val != snapshot_val) { - printf("Snapshot changed after taken; test failed\n"); - exit(1); - } - - // Reset snapshot, and check if cycles changed - counter_snapshot_reset(); - counter_val = counter_read(0); - printf("Cycles after snapshot is reset: %d\n", counter_val); - if (counter_val < snapshot_val + 10) { - printf("Counter values changed too little after snapshot reset; check if " - "counter continues properly\n"); - exit(1); - } - - // Global reset - counter_reset(); - counter_val = counter_read(0); - printf("Cycles after counter reset: %d\n", counter_val); - if (counter_val != 0) { - printf("Cycles did not reset after global reset inst\n"); - exit(1); - } - - // Check external counter - counter_configure(7, RESERVATION_STATION_LD_COUNT); - for (size_t i = 0; i < N; i++) { - gemmini_mvin(In[i], i * DIM); - gemmini_mvout(Out[i], i * DIM); - } - - // Fused read and take snapshot command - uint32_t custom_command = (7 & 0x7) << 4 | 0x4; - gemmini_counter_access(counter_val, custom_command); - - printf("RESERVATION_STATION # of load insts after executing %d mvin and " - "mvout insts: %d\n", - N - 1, counter_val); - if (counter_val < 2) { - printf("The load RESERVATION_STATION counter value is too small\n"); - exit(1); - } - - snapshot_val = counter_read(7); - if (counter_val != snapshot_val) { - printf("Snapshot value doesn't match the raw value read before snapshot " - "taken\n"); - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/global_average.c b/bb-tests/workloads/src/CTest/gemmini/global_average.c deleted file mode 100644 index 3994d281..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/global_average.c +++ /dev/null @@ -1,92 +0,0 @@ -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL - -#define BATCHES 4 -#define INPUT_DIM 7 -#define CHANNELS 2048 - -#else - -#define BATCHES 2 -#define INPUT_DIM 3 -#define CHANNELS 47 - -#endif - -void init_random(elem_t *buf, int len) { - for (int i = 0; i < len; i++) { - buf[i] = rand() % 10; - } -} - -bool is_same(elem_t *x, elem_t *y, int len) { - for (int i = 0; i < len; i++) - if (x[i] != y[i]) - return false; - return true; -} - -int main() { - static elem_t input[BATCHES][INPUT_DIM][INPUT_DIM][CHANNELS]; - static elem_t output[BATCHES][CHANNELS]; - static elem_t gold[BATCHES][CHANNELS]; - - init_random((elem_t *)input, BATCHES * INPUT_DIM * INPUT_DIM * CHANNELS); - - printf("CPU average pooling...\n"); - tiled_global_average_auto((elem_t *)input, (elem_t *)gold, BATCHES, CHANNELS, - INPUT_DIM, CPU); - - printf("Gemmini average pooling...\n"); - tiled_global_average_auto((elem_t *)input, (elem_t *)output, BATCHES, - CHANNELS, INPUT_DIM, WS); - - if (!is_same((elem_t *)gold, (elem_t *)output, BATCHES * CHANNELS)) { - printf("Fail\n"); - - printf("Input:\n"); - for (int b = 0; b < BATCHES; b++) { - for (int row = 0; row < INPUT_DIM; row++) { - printf("{"); - for (int col = 0; col < INPUT_DIM; col++) { - printf("{"); - for (int ch = 0; ch < CHANNELS; ch++) { - printf("%d ", input[b][row][col][ch]); - } - printf("}"); - } - printf("}"); - } - printf("\n"); - } - - printf("Output:\n"); - for (int b = 0; b < BATCHES; b++) { - for (int ch = 0; ch < CHANNELS; ch++) { - printf("%d ", output[b][ch]); - } - printf("\n"); - } - - printf("Gold:\n"); - for (int b = 0; b < BATCHES; b++) { - for (int ch = 0; ch < CHANNELS; ch++) { - printf("%d ", gold[b][ch]); - } - printf("\n"); - } - - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/include/accumulator.h b/bb-tests/workloads/src/CTest/gemmini/include/accumulator.h deleted file mode 100644 index c4d53ac8..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/accumulator.h +++ /dev/null @@ -1,24 +0,0 @@ -// See LICENSE for license details. - -#ifndef SRC_MAIN_C_ACCUMULATOR_H -#define SRC_MAIN_C_ACCUMULATOR_H - -#include "rocc-software/src/xcustom.h" - -#define k_DO_WRITE 0 -#define k_DO_READ 1 -#define k_DO_LOAD 2 -#define k_DO_ACCUM 3 - -#define XCUSTOM_ACC 0 - -#define doWrite(y, rocc_rd, data) \ - ROCC_INSTRUCTION(XCUSTOM_ACC, y, data, rocc_rd, k_DO_WRITE); -#define doRead(y, rocc_rd) \ - ROCC_INSTRUCTION(XCUSTOM_ACC, y, 0, rocc_rd, k_DO_READ); -#define doLoad(y, rocc_rd, mem_addr) \ - ROCC_INSTRUCTION(XCUSTOM_ACC, y, mem_addr, rocc_rd, k_DO_LOAD); -#define doAccum(y, rocc_rd, data) \ - ROCC_INSTRUCTION(XCUSTOM_ACC, y, data, rocc_rd, k_DO_ACCUM); - -#endif // SRC_MAIN_C_ACCUMULATOR_H diff --git a/bb-tests/workloads/src/CTest/gemmini/include/character.h b/bb-tests/workloads/src/CTest/gemmini/include/character.h deleted file mode 100644 index baeeb178..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/character.h +++ /dev/null @@ -1,10 +0,0 @@ -// See LICENSE for license details. - -#ifndef SRC_MAIN_C_CHARACTER_H -#define SRC_MAIN_C_CHARACTER_H - -#include "rocc-software/src/xcustom.h" - -#define XCUSTOM_CHAR 2 - -#endif // SRC_MAIN_C_CHARACTER_H diff --git a/bb-tests/workloads/src/CTest/gemmini/include/gemmini.h b/bb-tests/workloads/src/CTest/gemmini/include/gemmini.h deleted file mode 100644 index 261b0846..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/gemmini.h +++ /dev/null @@ -1,3929 +0,0 @@ -// See LICENSE for license details. - -#ifndef SRC_MAIN_C_GEMMINI_H -#define SRC_MAIN_C_GEMMINI_H - -#undef abs - -#include -#include -#include -#include -#include -#include - -#include "include/gemmini_params.h" - -#define GEMMINI_ASSERTIONS - -// Accelerator interface -#include "rocc-software/src/xcustom.h" - -// Counter Definition -#include "include/gemmini_counter.h" - -#define k_CONFIG 0 -#define k_MVIN2 1 -#define k_MVIN 2 -#define k_MVOUT 3 -#define k_COMPUTE_PRELOADED 4 -#define k_COMPUTE_ACCUMULATE 5 -#define k_PRELOAD 6 -#define k_FLUSH 7 - -#define k_LOOP_WS 8 -#define k_LOOP_WS_CONFIG_BOUNDS 9 -#define k_LOOP_WS_CONFIG_ADDRS_AB 10 -#define k_LOOP_WS_CONFIG_ADDRS_DC 11 -#define k_LOOP_WS_CONFIG_STRIDES_AB 12 -#define k_LOOP_WS_CONFIG_STRIDES_DC 13 - -#define k_MVIN3 14 - -#define k_COUNTER 126 - -#define k_LOOP_CONV_WS 15 -#define k_LOOP_CONV_WS_CONFIG_1 16 -#define k_LOOP_CONV_WS_CONFIG_2 17 -#define k_LOOP_CONV_WS_CONFIG_3 18 -#define k_LOOP_CONV_WS_CONFIG_4 19 -#define k_LOOP_CONV_WS_CONFIG_5 20 -#define k_LOOP_CONV_WS_CONFIG_6 21 - -#define CONFIG_EX 0 -#define CONFIG_LD 1 -#define CONFIG_ST 2 -#define CONFIG_BERT 3 - -#define GARBAGE_ADDR ((uint32_t)(-1)) -#define OUTPUT_STATIONARY 0 -#define WEIGHT_STATIONARY 1 - -#define NO_ACTIVATION 0 -#define RELU 1 -#define LAYERNORM 2 -#define IGELU 3 -#define SOFTMAX 4 - -#ifdef ELEM_T_IS_FLOAT -elem_t elem_t_bits_to_elem_t(elem_t_bits x) { - union { - elem_t_bits b; - elem_t f; - } un; - - un.b = x; - return un.f; -} - -elem_t_bits elem_t_to_elem_t_bits(elem_t x) { - union { - elem_t_bits b; - elem_t f; - } un; - - un.f = x; - return un.b; -} - -acc_t acc_t_bits_to_acc_t(acc_t_bits x) { - union { - acc_t_bits b; - acc_t f; - } un; - - un.b = x; - return un.f; -} - -acc_t_bits acc_t_to_acc_t_bits(acc_t x) { - union { - acc_t_bits b; - acc_t f; - } un; - - un.f = x; - return un.b; -} - -bool elem_t_isnan(elem_t x) { - elem_t_bits bits = elem_t_to_elem_t_bits(x); - uint64_t exp = - (bits >> (ELEM_T_SIG_BITS - 1)) & (((uint64_t)1 << ELEM_T_EXP_BITS) - 1); - uint64_t sig = bits & (((uint64_t)1 << ELEM_T_SIG_BITS) - 1); - bool is_nan_or_inf = exp == (((uint64_t)1 << ELEM_T_EXP_BITS) - 1); - bool is_not_inf = sig != 0; - return is_nan_or_inf && is_not_inf; -} - -bool acc_t_isnan(acc_t x) { - acc_t_bits bits = acc_t_to_acc_t_bits(x); - uint64_t exp = - (bits >> (ACC_T_SIG_BITS - 1)) & (((uint64_t)1 << ACC_T_EXP_BITS) - 1); - uint64_t sig = bits & (((uint64_t)1 << ACC_T_SIG_BITS) - 1); - bool is_nan_or_inf = exp == (((uint64_t)1 << ACC_T_EXP_BITS) - 1); - bool is_not_inf = sig != 0; - return is_nan_or_inf && is_not_inf; -} -#endif - -#ifdef HAS_MVIN_SCALE -static scale_t scale_t_bits_to_scale_t(scale_t_bits x) { - union { - scale_t_bits b; - scale_t f; - } un; - - un.b = x; - return un.f; -} - -static scale_t_bits scale_t_to_scale_t_bits(scale_t x) { - union { - scale_t_bits b; - scale_t f; - } un; - - un.f = x; - return un.b; -} -#else -#define scale_t_to_scale_t_bits(x) 0 -#endif - -#ifdef HAS_MVIN_ACC_SCALE -static scale_acc_t scale_acc_t_bits_to_scale_acc_t(scale_acc_t_bits x) { - union { - scale_acc_t_bits b; - scale_acc_t f; - } un; - - un.b = x; - return un.f; -} - -static scale_acc_t_bits scale_acc_t_to_scale_acc_t_bits(scale_acc_t x) { - union { - scale_acc_t_bits b; - scale_acc_t f; - } un; - - un.f = x; - return un.b; -} -#endif - -static acc_scale_t acc_scale_t_bits_to_acc_scale_t(acc_scale_t_bits x) { - union { - acc_scale_t_bits b; - acc_scale_t f; - } un; - - un.b = x; - return un.f; -} - -static acc_scale_t_bits acc_scale_t_to_acc_scale_t_bits(acc_scale_t x) { - union { - acc_scale_t_bits b; - acc_scale_t f; - } un; - - un.f = x; - return un.b; -} - -#define ROCC_INSTRUCTION_RS1_RS2(x, rs1, rs2, funct) \ - ROCC_INSTRUCTION_0_R_R(x, rs1, rs2, funct) - -// mvin and mvout -#define gemmini_extended_mvin(dram_addr, spad_addr, cols, rows) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, dram_addr, \ - ((uint64_t)(rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(cols) << ADDR_LEN) | (spad_addr), \ - k_MVIN) - -#define gemmini_extended_mvin2(dram_addr, spad_addr, cols, rows) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, dram_addr, \ - ((uint64_t)(rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(cols) << ADDR_LEN) | (spad_addr), \ - k_MVIN2) - -#define gemmini_extended_mvin3(dram_addr, spad_addr, cols, rows) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, dram_addr, \ - ((uint64_t)(rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(cols) << ADDR_LEN) | (spad_addr), \ - k_MVIN3) - -#define gemmini_block_mvin(dram_addr, spad_addr, len) \ - gemmini_extended_mvin(dram_addr, spad_addr, (len) * DIM, DIM) - -#define gemmini_mvin(dram_addr, spad_addr) \ - gemmini_extended_mvin(dram_addr, spad_addr, DIM, DIM) - -#define gemmini_extended_mvout(dram_addr, spad_addr, cols, rows) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, dram_addr, \ - ((uint64_t)(rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(cols) << ADDR_LEN) | \ - (uint64_t)(spad_addr), \ - k_MVOUT) - -#define gemmini_mvout(dram_addr, spad_addr) \ - gemmini_extended_mvout(dram_addr, spad_addr, DIM, DIM) - -// compute -#define gemmini_extended_compute_preloaded(A, BD, A_cols, A_rows, BD_cols, \ - BD_rows) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(A_rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(A_cols) << ADDR_LEN) | (uint64_t)(A), \ - ((uint64_t)(BD_rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(BD_cols) << ADDR_LEN) | (uint64_t)(BD), \ - k_COMPUTE_PRELOADED) - -#define gemmini_extended_compute_accumulated(A, BD, A_cols, A_rows, BD_cols, \ - BD_rows) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(A_rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(A_cols) << ADDR_LEN) | (uint64_t)(A), \ - ((uint64_t)(BD_rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(BD_cols) << ADDR_LEN) | (uint64_t)(BD), \ - k_COMPUTE_ACCUMULATE) - -#define gemmini_compute_preloaded(A, BD) \ - gemmini_extended_compute_preloaded(A, BD, DIM, DIM, DIM, DIM) - -#define gemmini_compute_accumulated(A, BD) \ - gemmini_extended_compute_accumulated(A, BD, DIM, DIM, DIM, DIM) - -// preload -#define gemmini_extended_preload(BD, C, BD_cols, BD_rows, C_cols, C_rows) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(BD_rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(BD_cols) << ADDR_LEN) | (uint64_t)(BD), \ - ((uint64_t)(C_rows) << (ADDR_LEN + 16)) | \ - ((uint64_t)(C_cols) << ADDR_LEN) | (uint64_t)(C), \ - k_PRELOAD) - -#define gemmini_preload(BD, C) \ - gemmini_extended_preload(BD, C, DIM, DIM, DIM, DIM) - -#define gemmini_preload_zeros(C) gemmini_preload(GARBAGE_ADDR, C) - -// config -#define gemmini_extended3_config_ex( \ - dataflow, sys_act, sys_shift, sys_acc_scale, C_stride, A_stride, \ - A_transpose, B_transpose, set_only_strides) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)acc_scale_t_to_acc_scale_t_bits((acc_scale_t)sys_acc_scale) \ - << 32) | \ - ((uint64_t)(A_stride) << 16) | (B_transpose << 9) | \ - (A_transpose << 8) | ((set_only_strides) << 7) | ((sys_act) << 3) | \ - ((dataflow) << 2) | CONFIG_EX, \ - ((uint64_t)(C_stride) << 48) | (sys_shift), k_CONFIG); - -#define gemmini_extended2_config_ex(dataflow, sys_act, sys_shift, A_stride, \ - A_transpose, B_transpose) \ - gemmini_extended3_config_ex(dataflow, sys_act, sys_shift, \ - ACC_SCALE_IDENTITY, 1, A_stride, A_transpose, \ - B_transpose, false) - -#define gemmini_extended_config_ex(dataflow, sys_act, sys_shift, A_stride, \ - A_transpose, B_transpose) \ - gemmini_extended2_config_ex(dataflow, sys_act, sys_shift, A_stride, \ - A_transpose, B_transpose) - -#define gemmini_config_ex(dataflow, sys_act, sys_shift) \ - gemmini_extended_config_ex(dataflow, sys_act, sys_shift, 1, 0, 0) - -// Note: The "pixel_repeats" parameter below is still experimental, andthere is -// a high chance that it will be removed in future releases. -#define gemmini_extended5_config_ld(stride, scale, shrunk, block_mvin_stride, \ - pixel_repeats, id) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(scale_t_to_scale_t_bits(scale)) << 32) | \ - ((uint64_t)(block_mvin_stride) << 16) | \ - ((uint64_t)(pixel_repeats) << 8) | ((id) << 3) | ((shrunk) << 2) | \ - CONFIG_LD, \ - stride, k_CONFIG) - -#define gemmini_extended4_config_ld(stride, scale, shrunk, block_mvin_stride, \ - id) \ - gemmini_extended5_config_ld(stride, scale, shrunk, block_mvin_stride, 1, id) - -#define gemmini_extended3_config_ld(stride, scale, shrunk, id) \ - gemmini_extended4_config_ld(stride, scale, shrunk, DIM, id) - -#define gemmini_extended2_config_ld(stride, scale, shrunk) \ - gemmini_extended3_config_ld(stride, scale, shrunk, 0) - -#define gemmini_extended_config_ld(stride, scale) \ - gemmini_extended2_config_ld(stride, scale, false) - -#define gemmini_config_ld(stride) \ - gemmini_extended_config_ld(stride, MVIN_SCALE_IDENTITY) - -#define gemmini_extended2_config_st(stride, acc_act, acc_scale, pool_stride, \ - pool_size, pool_out_dim, porows, pocols, \ - orows, ocols, upad, lpad) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(ocols) << 56) | ((uint64_t)(orows) << 48) | \ - ((uint64_t)(pocols) << 40) | ((uint64_t)(porows) << 32) | \ - ((uint64_t)(pool_out_dim) << 24) | ((uint64_t)(lpad) << 10) | \ - ((uint64_t)(upad) << 8) | ((uint64_t)(pool_size) << 6) | \ - ((uint64_t)(pool_stride) << 4) | ((uint64_t)(acc_act) << 2) | \ - CONFIG_ST, \ - ((uint64_t)acc_scale_t_to_acc_scale_t_bits((acc_scale_t)acc_scale) \ - << 32) | \ - ((uint32_t)stride), \ - k_CONFIG) - -#define gemmini_extended_config_st(stride, acc_act, acc_scale) \ - gemmini_extended2_config_st(stride, acc_act, acc_scale, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0) - -#define gemmini_config_st(stride) \ - gemmini_extended_config_st(stride, NO_ACTIVATION, ACC_SCALE_IDENTITY) - -#define gemmini_config_norm(q_const, q_const_type, set_stats_id_only, act_msb, \ - stat_id, igelu_qb, igelu_qc) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - (((uint64_t)((uint32_t)q_const)) << 32) | ((q_const_type & 1) << 18) | \ - ((set_stats_id_only & 1) << 17) | ((act_msb & 1) << 16) | \ - ((uint64_t)stat_id << 8) | CONFIG_BERT, \ - ((uint64_t)((uint32_t)(igelu_qc)) << 32) | \ - ((uint64_t)((uint32_t)(igelu_qb))), \ - k_CONFIG) - -// flush -#define gemmini_flush(skip) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, skip, 0, k_FLUSH) - -// fence -#define gemmini_fence() asm volatile("fence") - -// Counter access -#define gemmini_counter_access(rd, config_reg) \ - { \ - uint32_t _placeholder; \ - ROCC_INSTRUCTION(XCUSTOM_ACC, rd, config_reg, _placeholder, k_COUNTER) \ - } - -// Read counter -static uint32_t counter_read(size_t index) { - uint32_t config_reg = (index & 0x7) << 4; - uint32_t res; - gemmini_counter_access(res, config_reg); - return res; -} - -// Configure counter to take a new signal -static void counter_configure(size_t index, size_t counter_code) { - int non_incremental = counter_code > INCREMENTAL_COUNTERS; - if (non_incremental) { - counter_code -= INCREMENTAL_COUNTERS; - } - - uint32_t config_reg = (index & 0x7) << 4 | 0x8 | (counter_code & 0x3f) << 12 | - non_incremental << 31; - uint32_t placeholder; - gemmini_counter_access(placeholder, config_reg); -} - -// Take a snapshot -static void counter_snapshot_take() { - uint32_t config_reg = 0x4; - uint32_t placeholder; - gemmini_counter_access(placeholder, config_reg); -} - -// Counter snapshot reset -static void counter_snapshot_reset() { - uint32_t config_reg = 0x2; - uint32_t placeholder; - gemmini_counter_access(placeholder, config_reg); -} - -// Counter module reset -static void counter_reset() { - uint32_t config_reg = 0x1; - uint32_t placeholder; - gemmini_counter_access(placeholder, config_reg); -} - -int ceil_divide_int(int a, int b) { - int c = (a % b == 0) ? ((int)(a / b)) : (((int)(a / b)) + 1); - if (a < b) - c = 1; - return c; -} - -// weight-stationary matmul loop -#define gemmini_loop_ws(I, J, K, pad_I, pad_J, pad_K, A, B, D, C, A_stride, \ - B_stride, D_stride, C_stride, A_transpose, \ - B_transpose, full_C, low_D, ex_accumulate, act, \ - a_spad_id, b_spad_id, is_resadd) \ - {ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, \ - ((uint64_t)(pad_K) << 32) | \ - ((uint64_t)(pad_J) << 16) | (uint64_t)(pad_I), \ - ((uint64_t)(K) << 32) | ((uint64_t)(J) << 16) | \ - (uint64_t)(I), \ - k_LOOP_WS_CONFIG_BOUNDS) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, A, B, k_LOOP_WS_CONFIG_ADDRS_AB) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, D, C, \ - k_LOOP_WS_CONFIG_ADDRS_DC) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, A_stride, B_stride, \ - k_LOOP_WS_CONFIG_STRIDES_AB) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, D_stride, C_stride, \ - k_LOOP_WS_CONFIG_STRIDES_DC) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(a_spad_id) << 18) | \ - ((uint64_t)(b_spad_id) << 16) | \ - ((uint64_t)(act) << 8) | ((low_D) << 2) | \ - ((full_C) << 1) | (ex_accumulate), \ - ((is_resadd) << 2) | ((B_transpose) << 1) | \ - (A_transpose), \ - k_LOOP_WS)} - -// weight-stationary conv loop -#define gemmini_loop_conv_ws( \ - batch_size, in_row_dim, in_col_dim, in_channels, out_channels, \ - out_row_dim, out_col_dim, pool_out_row_dim, pool_out_col_dim, stride, \ - padding, kernel_dim, kernel_dilation, pool_size, pool_stride, \ - pool_padding, batches, porows, pocols, pochs, krows, kcols, kchs, lpad, \ - rpad, upad, dpad, plpad, prpad, pupad, pdpad, orows, ocols, weights, \ - output, bias, input, no_bias, no_pool, downsample, wrot180, input_dilated, \ - activation, trans_output_1203, trans_weight_1203, trans_weight_0132, \ - trans_input_3120, max_pixels_per_row, in_stride, weight_stride, \ - out_stride, dw, a_spad_id, b_spad_id) \ - {ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(out_channels) << 48) | ((uint64_t)(in_channels) << 32) | \ - ((uint64_t)(in_row_dim) << 16) | (uint64_t)(batch_size), \ - ((uint64_t)(padding) << 56) | ((uint64_t)(stride) << 48) | \ - ((uint64_t)(out_col_dim) << 32) | \ - ((uint64_t)(pool_out_row_dim) << 16) | (uint64_t)(out_row_dim), \ - k_LOOP_CONV_WS_CONFIG_1) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(kernel_dim) << 48) | \ - ((uint64_t)(pool_out_col_dim) << 32) | \ - ((uint64_t)(pool_size) << 16) | \ - ((uint64_t)(pool_stride) << 8) | (uint64_t)(pool_padding), \ - ((uint64_t)(batches) << 48) | ((uint64_t)(porows) << 32) | \ - ((uint64_t)(pocols) << 16) | (uint64_t)(pochs), \ - k_LOOP_CONV_WS_CONFIG_2) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(krows) << 48) | ((uint64_t)(kcols) << 32) | \ - ((uint64_t)(kchs) << 16) | (uint64_t)(lpad), \ - ((uint64_t)(rpad) << 48) | ((uint64_t)(upad) << 32) | \ - ((uint64_t)(dpad) << 24) | ((uint64_t)(plpad) << 16) | \ - ((uint64_t)(in_col_dim)), \ - k_LOOP_CONV_WS_CONFIG_3) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(orows) << 48) | ((uint64_t)(prpad) << 32) | \ - ((uint64_t)(pupad) << 21) | ((uint64_t)(pdpad) << 10) | \ - (uint64_t)(kernel_dilation), \ - ((uint64_t)(in_stride) << 48) | \ - ((uint64_t)(weight_stride) << 32) | \ - ((uint64_t)(out_stride) << 16) | (uint64_t)(ocols), \ - k_LOOP_CONV_WS_CONFIG_4) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, weights, output, \ - k_LOOP_CONV_WS_CONFIG_5) \ - ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, bias, input, \ - k_LOOP_CONV_WS_CONFIG_6) \ - ROCC_INSTRUCTION_RS1_RS2( \ - XCUSTOM_ACC, \ - ((uint64_t)(a_spad_id) << 18) | \ - ((uint64_t)(b_spad_id) << 16) | \ - ((uint64_t)(max_pixels_per_row) << 8) | \ - ((dw) << 6) | ((trans_input_3120) << 5) | \ - ((trans_weight_0132) << 4) | \ - ((trans_weight_1203) << 3) | \ - ((trans_output_1203) << 2) | \ - ((wrot180) << 1) | (no_bias), \ - ((activation) << 3) | ((input_dilated) << 2) | \ - ((downsample) << 1) | (no_pool), \ - k_LOOP_CONV_WS)} - -// Tiling functions -static void -sp_tiled_matmul_os(const elem_t *A, const elem_t *B, const void *D, void *C, - scale_t A_scale_factor, scale_t B_scale_factor, - scale_acc_t D_scale_factor, size_t I, size_t J, size_t K, - size_t pad_I, size_t pad_J, size_t pad_K, - size_t A_row_stride, size_t B_row_stride, - size_t D_row_stride, size_t C_row_stride, bool a_transpose, - bool b_transpose, bool full_C, bool low_D, bool no_bias, - bool repeating_bias, int act, int a_spad_id, int b_spad_id) { - - const uint32_t A_sp_addr_start = 0; - const uint32_t B_sp_addr_start = BANK_NUM * BANK_ROWS - K * J * DIM; - const uint32_t D_sp_addr_start = 1 << (ADDR_LEN - 1); - const uint32_t C_sp_addr_start = - (3 << (ADDR_LEN - 2)) | (full_C << (ADDR_LEN - 3)); - - const int A_blocks = K <= MAX_BLOCK_LEN ? K : MAX_BLOCK_LEN; - const int B_blocks = J <= MAX_BLOCK_LEN ? J : MAX_BLOCK_LEN; - const int D_blocks = J <= MAX_BLOCK_LEN_ACC ? J : MAX_BLOCK_LEN_ACC; - - // Move-in D - if (D != NULL && !no_bias) { - const size_t D_stride = repeating_bias ? 0 : D_row_stride * sizeof(acc_t); - gemmini_extended_config_ld(D_stride, D_scale_factor); - - for (size_t i = 0; i < I; i++) { - for (size_t j = 0; j < J; j += D_blocks) { - const size_t bias_row = repeating_bias ? 0 : i; - const acc_t *const D_dram_addr = - (acc_t *)D + (bias_row * D_row_stride + j) * DIM; - - const uint32_t D_sp_addr_acc = D_sp_addr_start + (i * J + j) * DIM; - - const size_t blocks = j + D_blocks <= J ? D_blocks : J - j; - - const size_t cols = blocks * DIM - (j + blocks >= J ? pad_J : 0); - const size_t rows = DIM - (i == I - 1 ? pad_I : 0); - - gemmini_extended_mvin(D_dram_addr, D_sp_addr_acc, cols, rows); - } - } - } - - // Move-in B - gemmini_extended_config_ld(B_row_stride * sizeof(elem_t), B_scale_factor); - for (size_t j = 0; j < J; j += B_blocks) { - for (size_t k = 0; k < K; k++) { - const elem_t *const B_dram_addr = B + (k * B_row_stride + j) * DIM; - const uint32_t B_sp_addr = B_sp_addr_start + (k * J + j) * DIM; - const size_t blocks = j + B_blocks <= J ? B_blocks : J - j; - const size_t cols = blocks * DIM - (j + blocks >= J ? pad_J : 0); - const size_t rows = DIM - (k == K - 1 ? pad_K : 0); - gemmini_extended_mvin(B_dram_addr, B_sp_addr, cols, rows); - } - } - - // Move-in A - gemmini_extended_config_ld(A_row_stride * sizeof(elem_t), A_scale_factor); - for (size_t i = 0; i < I; i++) { - for (size_t k = 0; k < K; k += A_blocks) { - const elem_t *const A_dram_addr = A + (i * A_row_stride + k) * DIM; - const uint32_t A_sp_addr = A_sp_addr_start + (i * K + k) * DIM; - const size_t blocks = k + A_blocks <= K ? A_blocks : K - k; - const size_t cols = blocks * DIM - (k + blocks >= K ? pad_K : 0); - const size_t rows = DIM - (i == I - 1 ? pad_I : 0); - gemmini_extended_mvin(A_dram_addr, A_sp_addr, cols, rows); - } - } - - for (size_t i = 0; i < I; i++) { - for (size_t j = 0; j < J; j++) { - const uint32_t C_sp_addr = C_sp_addr_start + (i * J + j) * DIM; - - for (size_t k = 0; k < K; k++) { - - const uint32_t A_sp_addr = A_sp_addr_start + (i * K + k) * DIM; - const uint32_t B_sp_addr = B_sp_addr_start + (k * J + j) * DIM; - - uint32_t out_sp_addr = k == K - 1 ? C_sp_addr : GARBAGE_ADDR; - - // If we're not using a bias, then we want to overwrite what's in the - // accumulator, rather than writing over it - int no_bias_new_matrix = no_bias && D != NULL && k == K - 1; - if (no_bias_new_matrix) { - out_sp_addr &= ~(1 << (ADDR_LEN - 2)); - } - - const size_t A_cols = DIM - (k == K - 1 ? pad_K : 0); - const size_t A_rows = DIM - (i == I - 1 ? pad_I : 0); - const size_t B_cols = DIM - (j == J - 1 ? pad_J : 0); - const size_t B_rows = DIM - (k == K - 1 ? pad_K : 0); - const size_t C_cols = DIM - (j == J - 1 ? pad_J : 0); - const size_t C_rows = DIM - (i == I - 1 ? pad_I : 0); - - gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr, DIM, DIM, C_cols, - C_rows); - - if (k == 0) { // First iteration - gemmini_extended_compute_preloaded(A_sp_addr, B_sp_addr, A_cols, - A_rows, B_cols, B_rows); - } else { // All other iterations - gemmini_extended_compute_accumulated(A_sp_addr, B_sp_addr, A_cols, - A_rows, B_cols, B_rows); - } - } - } - } - - // Move-out C - if (C != NULL) { - const size_t sizeof_C = full_C ? sizeof(acc_t) : sizeof(elem_t); - - for (size_t i = 0; i < I; i++) { - for (size_t j = 0; j < J; j++) { - void *const C_dram_addr = - (int8_t *)C + (i * C_row_stride + j) * DIM * sizeof_C; - const uint32_t C_sp_addr = C_sp_addr_start + (i * J + j) * DIM; - - const size_t C_cols = DIM - (j == J - 1 ? pad_J : 0); - const size_t C_rows = DIM - (i == I - 1 ? pad_I : 0); - - gemmini_extended_mvout(C_dram_addr, C_sp_addr, C_cols, C_rows); - } - } - } -} - -static void -sp_tiled_matmul_ws(const elem_t *A, const elem_t *B, const void *D, void *C, - scale_t A_scale_factor, scale_t B_scale_factor, - scale_acc_t D_scale_factor, size_t I, size_t J, size_t K, - size_t pad_I, size_t pad_J, size_t pad_K, - size_t A_row_stride, size_t B_row_stride, - size_t D_row_stride, size_t C_row_stride, bool a_transpose, - bool b_transpose, bool full_C, bool low_D, bool no_bias, - bool repeating_bias, int act, int a_spad_id, int b_spad_id) { - /* - const uint32_t A_sp_addr_start = 0; - const uint32_t B_sp_addr_start = BANK_NUM * BANK_ROWS - K * J * DIM; - const uint32_t D_sp_addr_start = 1 << (ADDR_LEN-1); - const uint32_t C_sp_addr_start = 3 << (ADDR_LEN-2) | (full_C << - (ADDR_LEN-3)); const int A_blocks = a_transpose ? (I <= MAX_BLOCK_LEN ? I : - MAX_BLOCK_LEN) : (K <= MAX_BLOCK_LEN ? K : MAX_BLOCK_LEN); const int - B_blocks = b_transpose ? (K <= MAX_BLOCK_LEN ? K : MAX_BLOCK_LEN) : (J <= - MAX_BLOCK_LEN ? J : MAX_BLOCK_LEN); const int D_blocks = low_D ? (J <= - MAX_BLOCK_LEN ? J : MAX_BLOCK_LEN) : (J <= MAX_BLOCK_LEN_ACC ? J : - MAX_BLOCK_LEN_ACC); const int C_blocks = full_C ? 1 : (J <= MAX_BLOCK_LEN ? - J : MAX_BLOCK_LEN); const size_t sizeof_D = low_D ? sizeof(elem_t) : - sizeof(acc_t); const size_t sizeof_C = full_C ? sizeof(acc_t) : - sizeof(elem_t); - // Move-in D - if (D != NULL && !no_bias) { - for (size_t i = 0; i < I; i++) { - const size_t rows = DIM - (i == I-1 ? pad_I : 0); - for (size_t j = 0; j < J; j += D_blocks) { - const size_t bias_row = repeating_bias ? 0 : i; - const void * const D_dram_addr = (int8_t *)D + (bias_row * - D_row_stride + j)*DIM*sizeof_D; const uint32_t D_sp_addr_acc = - D_sp_addr_start + (i*J + j)*DIM; size_t blocks = j + D_blocks <= J ? - D_blocks : J-j; const size_t cols = blocks * DIM - (j + blocks >= J ? pad_J - : 0); gemmini_extended_mvin3(D_dram_addr, D_sp_addr_acc, cols, rows); - } - } - } - for (size_t k = 0; k < K; k++) { - for (size_t j = 0; j < J; j++) { - for (size_t i = 0; i < I; i++) { - const uint32_t A_sp_addr = a_transpose ? (A_sp_addr_start + (k*I + - i)*DIM) : (A_sp_addr_start + (i*K + k)*DIM); const uint32_t B_sp_addr = - b_transpose ? (B_sp_addr_start + (j*K + k)*DIM) : (B_sp_addr_start + (k*J + - j)*DIM); const uint32_t C_sp_addr = C_sp_addr_start + (i*J + j)*DIM; - // Mvin A - if (a_transpose) { - if (j == 0 && i % A_blocks == 0) { - const elem_t * const A_dram_addr = A + (k*A_row_stride + i)*DIM; - const size_t blocks = i + A_blocks <= I ? A_blocks : I-i; - const size_t cols = blocks * DIM - (i + blocks >= I ? pad_I : 0); - const size_t rows = DIM - (k == K-1 ? pad_K : 0); - gemmini_extended_mvin(A_dram_addr, A_sp_addr, cols, rows); - } - } else { - if (j == 0 && k % A_blocks == 0) { - const elem_t * const A_dram_addr = A + (i*A_row_stride + k)*DIM; - const size_t blocks = k + A_blocks <= K ? A_blocks : K-k; - const size_t cols = blocks * DIM - (k + blocks >= K ? pad_K : 0); - const size_t rows = DIM - (i == I-1 ? pad_I : 0); - gemmini_extended_mvin(A_dram_addr, A_sp_addr, cols, rows); - } - } - // Mvin B - if (b_transpose) { - if (i == 0 && k % B_blocks == 0) { - const elem_t * const B_dram_addr = B + (j*B_row_stride + k)*DIM; - const size_t blocks = k + B_blocks <= K ? B_blocks : K-k; - const size_t cols = blocks * DIM - (k + blocks >= K ? pad_K : 0); - const size_t rows = DIM - (j == J-1 ? pad_J : 0); - gemmini_extended_mvin2(B_dram_addr, B_sp_addr, cols, rows); - } - } else { - if (i == 0 && j % B_blocks == 0) { - const elem_t * const B_dram_addr = B + (k*B_row_stride + j)*DIM; - const size_t blocks = j + B_blocks <= J ? B_blocks : J-j; - const size_t cols = blocks * DIM - (j + blocks >= J ? pad_J : 0); - const size_t rows = DIM - (k == K-1 ? pad_K : 0); - gemmini_extended_mvin2(B_dram_addr, B_sp_addr, cols, rows); - } - } - // Compute - { - uint32_t pre_sp_addr = i == 0 ? B_sp_addr : GARBAGE_ADDR; - uint32_t out_sp_addr = C_sp_addr; - // If we're not using a bias, then we want to overwrite what's in - the - // accumulator, rather than writing over it - int no_bias_new_matrix = no_bias && D != NULL && k == 0; - if (no_bias_new_matrix) { - out_sp_addr &= ~(1 << (ADDR_LEN-2)); - } - const size_t A_cols = DIM - (k == K - 1 ? pad_K : 0); - const size_t A_rows = DIM - (i == I - 1 ? pad_I : 0); - const size_t B_cols = DIM - (j == J - 1 ? pad_J : 0); - const size_t B_rows = DIM - (k == K - 1 ? pad_K : 0); - const size_t C_cols = DIM - (j == J - 1 ? pad_J : 0); - const size_t C_rows = DIM - (i == I - 1 ? pad_I : 0); - gemmini_extended_preload(pre_sp_addr, out_sp_addr, B_cols, B_rows, - C_cols, C_rows); if (i == 0) { // First iteration - gemmini_extended_compute_preloaded(A_sp_addr, GARBAGE_ADDR, - A_cols, A_rows, DIM, DIM); } else { // All other iterations - gemmini_extended_compute_accumulated(A_sp_addr, GARBAGE_ADDR, - A_cols, A_rows, DIM, DIM); - } - } - if (C != NULL && k == K-1) { - // Move-out C (if not normalizing) - if (((act != LAYERNORM) && (act != SOFTMAX)) && (j == J-1 || j % - C_blocks == C_blocks-1)) { const size_t rounded_j = (j / C_blocks) * - C_blocks; const uint32_t rounded_C_sp_addr = C_sp_addr_start + (i*J + - rounded_j)*DIM; void * const C_dram_addr = (int8_t*)C + (i*C_row_stride + - rounded_j)*DIM*sizeof_C; const size_t blocks = rounded_j + C_blocks <= J ? - C_blocks : J-rounded_j; const size_t cols = blocks * DIM - (rounded_j + - blocks >= J ? pad_J : 0); const size_t rows = DIM - (i == I - 1 ? pad_I : - 0); gemmini_extended_mvout(C_dram_addr, rounded_C_sp_addr, cols, rows); - } - // Move-out C (if normalizing) - if (act == LAYERNORM && j == J - 1) { - uint32_t norm_cmds[][2] = {{1,2},{3,4},{0,0}}; - const int norm_cmds_size = sizeof(norm_cmds) / - sizeof(norm_cmds[0]); const size_t rows = DIM - (i == I-1 ? pad_I : 0); for - (size_t row = 0; row < rows; row += NORM_STAT_IDS) { const size_t stat_ids = - rows - row > NORM_STAT_IDS ? NORM_STAT_IDS : rows - row; for (int cmd = 0; - cmd < norm_cmds_size; cmd++) { for (size_t stat_id = 0; stat_id < stat_ids; - stat_id++) { gemmini_config_norm(0, 0, 0, 0, stat_id, 0, 0); const size_t r - = row + stat_id; for (size_t jj = 0; jj < J; jj += C_blocks) { uint32_t - norm_C_sp_addr = C_sp_addr_start + (i*J + jj)*DIM + r; if (jj + C_blocks >= - J) { norm_C_sp_addr |= (norm_cmds[cmd][1] << 26); // Final mean/inv-std-dev - calculation } else { norm_C_sp_addr |= (norm_cmds[cmd][0] << 26); // - Accumulate sum/variance - } - void * const C_dram_addr = (int8_t*)C + - (i*C_row_stride + jj) * DIM * sizeof_C + - r * C_row_stride * sizeof_C; - const size_t blocks = jj + C_blocks <= J ? C_blocks : - J-jj; const size_t cols = blocks * DIM - (jj + blocks >= J ? pad_J : 0); - gemmini_extended_mvout(C_dram_addr, norm_C_sp_addr, cols, - 1); - } - } - } - } - } else if (act == SOFTMAX && j == J - 1) { - uint32_t norm_cmds[][2] = {{5,5},{6,7},{0,0}}; - const int norm_cmds_size = sizeof(norm_cmds) / - sizeof(norm_cmds[0]); const size_t rows = DIM - (i == I-1 ? pad_I : 0); for - (size_t row = 0; row < rows; row += NORM_STAT_IDS) { const size_t stat_ids = - rows - row > NORM_STAT_IDS ? NORM_STAT_IDS : rows - row; for (int cmd = 0; - cmd < norm_cmds_size; cmd++) { for (size_t stat_id = 0; stat_id < stat_ids; - stat_id++) { - // set stat id only - gemmini_config_norm(0, 0, 1, 0, stat_id, 0, 0); - const size_t r = row + stat_id; - for (size_t jj = 0; jj < J; jj += C_blocks) { - uint32_t norm_C_sp_addr = C_sp_addr_start + (i*J + jj)*DIM - + r; if (jj + C_blocks >= J) { norm_C_sp_addr |= (norm_cmds[cmd][1] << 26); - // Final mean/inv-std-dev calculation } else { norm_C_sp_addr |= - (norm_cmds[cmd][0] << 26); // Accumulate sum/variance - } - void * const C_dram_addr = (int8_t*)C + - (i*C_row_stride + jj) * DIM * sizeof_C + - r * C_row_stride * sizeof_C; - const size_t blocks = jj + C_blocks <= J ? C_blocks : - J-jj; const size_t cols = blocks * DIM - (jj + blocks >= J ? pad_J : 0); - gemmini_extended_mvout(C_dram_addr, norm_C_sp_addr, cols, - 1); - } - } - } - } - } - } - } - } - } - */ - - // Combined loop - gemmini_loop_ws(I, J, K, pad_I, pad_J, pad_K, A, B, no_bias ? NULL : D, C, - A_row_stride, B_row_stride, repeating_bias ? 0 : D_row_stride, - C_row_stride, a_transpose, b_transpose, full_C, low_D, - !no_bias || D == NULL, act, a_spad_id, b_spad_id, false); -} - -static void tiled_matmul_outer( - size_t dim_I, size_t dim_J, size_t dim_K, const elem_t *A, const elem_t *B, - const void *D, void *C, size_t stride_A, size_t stride_B, size_t stride_D, - size_t stride_C, scale_t A_scale_factor, scale_t B_scale_factor, - scale_acc_t D_scale_factor, size_t tile_I, size_t tile_J, size_t tile_K, - int act, acc_scale_t scale, acc_scale_t bert_scale, bool repeating_bias, - bool a_transpose, bool b_transpose, bool full_C, bool low_D, - uint8_t weightA, int dataflow) { - - const size_t dim_I_padded = (dim_I / DIM + (dim_I % DIM != 0)) * DIM; - const size_t dim_J_padded = (dim_J / DIM + (dim_J % DIM != 0)) * DIM; - const size_t dim_K_padded = (dim_K / DIM + (dim_K % DIM != 0)) * DIM; - - const size_t I0 = - dim_I_padded / (tile_I * DIM) + (dim_I_padded % (tile_I * DIM) != 0); - const size_t J0 = - dim_J_padded / (tile_J * DIM) + (dim_J_padded % (tile_J * DIM) != 0); - const size_t K0 = - dim_K_padded / (tile_K * DIM) + (dim_K_padded % (tile_K * DIM) != 0); - - // These lines here are supposed to help us deal with when the dimensions of - // the systolic array aren't divisible by the tiling factors - const size_t last_I = dim_I_padded % (tile_I * DIM) == 0 - ? tile_I - : (dim_I_padded / DIM) % tile_I; - const size_t last_J = dim_J_padded % (tile_J * DIM) == 0 - ? tile_J - : (dim_J_padded / DIM) % tile_J; - const size_t last_K = dim_K_padded % (tile_K * DIM) == 0 - ? tile_K - : (dim_K_padded / DIM) % tile_K; - - // These lines are supposed to figure out how much padding the hardware is - // supposed to add for the final tile - const size_t padding_I = dim_I_padded - dim_I; - const size_t padding_J = dim_J_padded - dim_J; - const size_t padding_K = dim_K_padded - dim_K; - - const bool no_bias = D == NULL; - - if (no_bias) { - D = (void *)1; // Dummy address which isn't NULL - } - - const size_t sizeof_D = low_D ? sizeof(elem_t) : sizeof(acc_t); - const size_t sizeof_C = full_C ? sizeof(acc_t) : sizeof(elem_t); - - gemmini_extended_config_ex(dataflow, act & 3, 0, 1, a_transpose, b_transpose); - gemmini_extended_config_st(stride_C * sizeof_C, act & 3, scale); - gemmini_extended3_config_ld(stride_A * sizeof(elem_t), A_scale_factor, false, - 0); - gemmini_extended3_config_ld(stride_B * sizeof(elem_t), B_scale_factor, false, - 1) - gemmini_extended3_config_ld(repeating_bias ? 0 : (stride_D * sizeof_D), - D_scale_factor, low_D, 2); - - if (act == IGELU) { - const acc_scale_t sqrt_2 = 1.41421356237; - const acc_scale_t S = bert_scale; - const acc_scale_t S_erf = (-0.2888 * ((S * S) / 2)); - - const acc_t qb = -1.769 / (S / sqrt_2); - const acc_t qc = 1.0 / S_erf; - - gemmini_config_norm(0, 0, 0, 0, 0, qb, qc); - } - - if (act == SOFTMAX) { - const scale_t a = 0.3585; - const scale_t b = 1.353; - const scale_t c = 0.344; - - const acc_t qln2 = (int)(0.693147 / bert_scale); - const acc_t qln2_inv = 65536 / qln2; - const acc_t qb = b / bert_scale; - const acc_t qc = c / (a * bert_scale * bert_scale); - - gemmini_config_norm(qln2, 0, 0, 1, 0, qb, qc); - gemmini_config_norm(qln2_inv, 1, 0, 1, 0, qb, qc); - } - - void (*inner)(const elem_t *, const elem_t *, const void *, void *, scale_t, - scale_t, scale_acc_t, size_t, size_t, size_t, size_t, size_t, - size_t, size_t, size_t, size_t, size_t, bool, bool, bool, bool, - bool, bool, int, int, int); - - if (dataflow == OUTPUT_STATIONARY) { - inner = &sp_tiled_matmul_os; - } else /* if (dataflow == WEIGHT_STATIONARY) */ { - inner = &sp_tiled_matmul_ws; - } - - // reuse operand if it fits scratchpad - int a_spad_id = 0; - int b_spad_id = 0; - bool b_reuse = (J0 * K0 <= 2) && (dataflow == WEIGHT_STATIONARY); - bool a_reuse = (I0 * K0 <= 2) && (dataflow == WEIGHT_STATIONARY); - - for (size_t i0 = 0; i0 < I0; i0++) - for (size_t j0 = 0; j0 < J0; j0++) - for (size_t k0 = 0; k0 < K0; k0++) { - if (a_reuse) - a_spad_id = ((i0 + k0) == 0) ? 1 : 2; - if (b_reuse) - b_spad_id = ((j0 + k0) == 0) ? 1 : 2; - - const void *pre; - if (k0 != 0) { - pre = NULL; - } else { - size_t bias_row = repeating_bias ? 0 : i0 * tile_I * DIM; - // pre = &(((acc_t*)D)[bias_row * stride_D + j0 * tile_J * DIM]); - pre = (int8_t *)D + - (bias_row * stride_D + j0 * tile_J * DIM) * sizeof_D; - } - - void *out = k0 == K0 - 1 ? (int8_t *)C + (i0 * tile_I * DIM * stride_C + - j0 * tile_J * DIM) * - sizeof_C - : NULL; - - const size_t I = i0 < I0 - 1 ? tile_I : last_I; - const size_t J = j0 < J0 - 1 ? tile_J : last_J; - const size_t K = k0 < K0 - 1 ? tile_K : last_K; - - const size_t pad_I = i0 == I0 - 1 ? padding_I : 0; - const size_t pad_J = j0 == J0 - 1 ? padding_J : 0; - const size_t pad_K = k0 == K0 - 1 ? padding_K : 0; - - const elem_t *a = - a_transpose - ? (A + k0 * tile_K * DIM * stride_A + i0 * tile_I * DIM) - : (A + i0 * tile_I * DIM * stride_A + k0 * tile_K * DIM); - - const elem_t *b = - b_transpose - ? (B + j0 * tile_J * DIM * stride_B + k0 * tile_K * DIM) - : (B + k0 * tile_K * DIM * stride_B + j0 * tile_J * DIM); - - if (a_reuse && j0 >= 1) - a = NULL; - if (b_reuse && i0 >= 1) - b = NULL; - // printf("a_reuse: %d, b_reuse: %d, a_spad_id: %d, b_spad_id: %d, a: - // %llu, b: %llu \n", a_reuse, b_reuse, a_spad_id, b_spad_id, a, b); - (*inner)(a, b, pre, out, A_scale_factor, B_scale_factor, D_scale_factor, - I, J, K, pad_I, pad_J, pad_K, stride_A, stride_B, stride_D, - stride_C, a_transpose, b_transpose, full_C, low_D, no_bias, - repeating_bias, act, a_spad_id, b_spad_id); - } - - gemmini_fence(); -} - -static acc_t int_sqrt(acc_t n) { - if (n == 0) - return 0; - - int bits = 0; - for (acc_t x = n; x > 0; x /= 2) - bits++; - - acc_t x_prev = 1 << ((bits + 1) / 2); - - while (1) { - acc_t x_next = (x_prev + n / x_prev) / 2; - if (x_next >= x_prev) - return x_prev; - x_prev = x_next; - }; -} - -static elem_t scale_and_sat(acc_t x, int act, acc_scale_t scale, - acc_scale_t bert_scale) { - // Apply I-GELU if needed - if (act == IGELU) { - const acc_scale_t sqrt_2 = 1.41421356237; - - const acc_scale_t S = bert_scale; - - const acc_scale_t S_erf = (-0.2888 * (S / sqrt_2) * (S / sqrt_2)); - const acc_t q1 = 1 / S_erf; - const acc_t qb = -1.769 / (S / sqrt_2); - const acc_t qc = 1.0 / (-0.2888 * (S / sqrt_2) * (S / sqrt_2)); - - const acc_t q = x; - - const acc_t q_sign = q < 0 ? -1 : 1; - const acc_t q_clipped = abs(q) > (-qb) ? (-qb) : abs(q); - const acc_t q_poly = (q_clipped + qb) * (q_clipped + qb) + qc; - const acc_t q_erf = q_sign * q_poly; - - x = q * (q_erf + q1); - } - - // Scale value down and round it - x = ACC_SCALE(x, scale); - // Clip result - x = x > elem_t_max ? elem_t_max : (x < elem_t_min ? elem_t_min : x); - // Apply activation function - if (act == RELU) { - x = x < 0 ? 0 : x; - } - return x; -} - -#ifdef HAS_MVIN_SCALE -#define GEMMINI_SCALE(x, scale) MVIN_SCALE((x), (scale)) -#else -#define GEMMINI_SCALE(x, scale) (x) -#endif - -#ifdef HAS_MVIN_ACC_SCALE -#define GEMMINI_ACC_SCALE(x, scale) MVIN_SCALE_ACC((x), (scale)) -#else -#define GEMMINI_ACC_SCALE(x, scale) (x) -#endif - -static void matmul_cpu(bool transA, bool transB, size_t DIM_I, size_t DIM_J, - size_t DIM_K, const elem_t *A, const elem_t *B, - const acc_t *D, elem_t *C, size_t stride_A, - size_t stride_B, size_t stride_D, size_t stride_C, - scale_t A_scale_factor, scale_t B_scale_factor, - scale_acc_t D_scale_factor, int act, acc_scale_t scale, - acc_scale_t bert_scale, bool repeating_bias) { - - const int no_bias = D == NULL; - if (act != LAYERNORM && act != SOFTMAX && !transA && !transB && - DIM_I % 4 == 0 && DIM_J % 4 == 0) { - for (size_t i = 0; i < DIM_I; i += 4) { - for (size_t j = 0; j < DIM_J; j += 4) { - - acc_t result[4][4]; // = {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, - // 0, 0, 0}}; - - for (size_t ii = 0; ii < 4; ii++) - for (size_t jj = 0; jj < 4; jj++) { - const size_t bias_row = repeating_bias ? 0 : i + ii; - result[ii][jj] = - no_bias ? 0 - : GEMMINI_ACC_SCALE(*(D + bias_row * stride_D + j + jj), - D_scale_factor); - } - - for (size_t k = 0; k < DIM_K; k++) { - result[0][0] += - GEMMINI_SCALE(*(A + i * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j), B_scale_factor); - result[0][1] += - GEMMINI_SCALE(*(A + i * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 1), B_scale_factor); - result[0][2] += - GEMMINI_SCALE(*(A + i * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 2), B_scale_factor); - result[0][3] += - GEMMINI_SCALE(*(A + i * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 3), B_scale_factor); - result[1][0] += - GEMMINI_SCALE(*(A + (i + 1) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j), B_scale_factor); - result[1][1] += - GEMMINI_SCALE(*(A + (i + 1) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 1), B_scale_factor); - result[1][2] += - GEMMINI_SCALE(*(A + (i + 1) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 2), B_scale_factor); - result[1][3] += - GEMMINI_SCALE(*(A + (i + 1) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 3), B_scale_factor); - result[2][0] += - GEMMINI_SCALE(*(A + (i + 2) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j), B_scale_factor); - result[2][1] += - GEMMINI_SCALE(*(A + (i + 2) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 1), B_scale_factor); - result[2][2] += - GEMMINI_SCALE(*(A + (i + 2) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 2), B_scale_factor); - result[2][3] += - GEMMINI_SCALE(*(A + (i + 2) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 3), B_scale_factor); - result[3][0] += - GEMMINI_SCALE(*(A + (i + 3) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j), B_scale_factor); - result[3][1] += - GEMMINI_SCALE(*(A + (i + 3) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 1), B_scale_factor); - result[3][2] += - GEMMINI_SCALE(*(A + (i + 3) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 2), B_scale_factor); - result[3][3] += - GEMMINI_SCALE(*(A + (i + 3) * stride_A + k), A_scale_factor) * - GEMMINI_SCALE(*(B + k * stride_B + j + 3), B_scale_factor); - } - - *(C + i * stride_C + j) = - scale_and_sat(result[0][0], act, scale, bert_scale); - *(C + i * stride_C + j + 1) = - scale_and_sat(result[0][1], act, scale, bert_scale); - *(C + i * stride_C + j + 2) = - scale_and_sat(result[0][2], act, scale, bert_scale); - *(C + i * stride_C + j + 3) = - scale_and_sat(result[0][3], act, scale, bert_scale); - *(C + (i + 1) * stride_C + j) = - scale_and_sat(result[1][0], act, scale, bert_scale); - *(C + (i + 1) * stride_C + j + 1) = - scale_and_sat(result[1][1], act, scale, bert_scale); - *(C + (i + 1) * stride_C + j + 2) = - scale_and_sat(result[1][2], act, scale, bert_scale); - *(C + (i + 1) * stride_C + j + 3) = - scale_and_sat(result[1][3], act, scale, bert_scale); - *(C + (i + 2) * stride_C + j) = - scale_and_sat(result[2][0], act, scale, bert_scale); - *(C + (i + 2) * stride_C + j + 1) = - scale_and_sat(result[2][1], act, scale, bert_scale); - *(C + (i + 2) * stride_C + j + 2) = - scale_and_sat(result[2][2], act, scale, bert_scale); - *(C + (i + 2) * stride_C + j + 3) = - scale_and_sat(result[2][3], act, scale, bert_scale); - *(C + (i + 3) * stride_C + j) = - scale_and_sat(result[3][0], act, scale, bert_scale); - *(C + (i + 3) * stride_C + j + 1) = - scale_and_sat(result[3][1], act, scale, bert_scale); - *(C + (i + 3) * stride_C + j + 2) = - scale_and_sat(result[3][2], act, scale, bert_scale); - *(C + (i + 3) * stride_C + j + 3) = - scale_and_sat(result[3][3], act, scale, bert_scale); - } - } - } else { - size_t A_dim_strides[2] = {!transA ? stride_A : 1, - !transA ? 1 : stride_A}; // i, j stride - size_t B_dim_strides[2] = {!transB ? 1 : stride_B, - !transB ? stride_B : 1}; // j, k stride - - // We also create a buffer that we can use for layernorms and softmaxes - static acc_t c_buffer[1024]; - const size_t c_buffer_sz = sizeof(c_buffer) / sizeof(c_buffer[0]); - if ((act == LAYERNORM || act == SOFTMAX) && DIM_J > c_buffer_sz) { - printf("Matmul is too large to normalize\n"); - exit(1); - } - - for (size_t i = 0; i < DIM_I; i++) { - for (size_t j = 0; j < DIM_J; j++) { - elem_t *c = C + (i * stride_C) + j; - - const size_t bias_row = repeating_bias ? 0 : i; - acc_t sum = no_bias ? 0 - : GEMMINI_ACC_SCALE(*(D + bias_row * stride_D + j), - D_scale_factor); - - for (size_t k = 0; k < DIM_K; k++) { - const elem_t *a = A + i * A_dim_strides[0] + k * A_dim_strides[1]; - const elem_t *b = B + j * B_dim_strides[0] + k * B_dim_strides[1]; - sum += (GEMMINI_SCALE(*a, A_scale_factor) * - GEMMINI_SCALE(*b, B_scale_factor)); - } - - if (act == LAYERNORM || act == SOFTMAX) - c_buffer[j] = sum; - else - *c = scale_and_sat(sum, act, scale, bert_scale); - } - - if (act == LAYERNORM) { - acc_t sum = 0; - for (size_t j = 0; j < DIM_J; j++) - sum += c_buffer[j]; - acc_t mean = sum / (acc_t)DIM_J; - - acc_t total_err_sq = 0; - for (size_t j = 0; j < DIM_J; j++) - total_err_sq += (c_buffer[j] - mean) * (c_buffer[j] - mean); - acc_t variance = total_err_sq / (acc_t)DIM_J; - - acc_t stddev = int_sqrt(variance); - if (variance == 0) - stddev = 1; - - for (size_t j = 0; j < DIM_J; j++) { - c_buffer[j] -= mean; - // c_buffer[j] /= stddev; - c_buffer[j] = ROUND_NEAR_EVEN( - (double)c_buffer[j] / - stddev); // TODO I don't think I-BERT uses round-near-even, so we - // shouldn't either. We just use this rounding mode here - // in order to match the hardware. - - elem_t *c = C + (i * stride_C) + j; - *c = scale_and_sat(c_buffer[j], act, scale, bert_scale); - } - } else if (act == SOFTMAX) { - const scale_t a = 0.3585; - const scale_t b = 1.353; - const scale_t c = 0.344; - - // is SCALE supposed to be input scale? - const acc_t qln2 = (acc_t)(0.693147 / bert_scale); - const acc_t qln2_inv = 65536 / qln2; - const acc_t qb = b / bert_scale; - const acc_t qc = c / (a * bert_scale * bert_scale); - - // pass 1: get max_q - acc_t max_q = -2147483648; - for (size_t j = 0; j < DIM_J; j++) { - if (c_buffer[j] > max_q) - max_q = c_buffer[j]; - } - - // pass 2: calculate iexp(q_tilde) and sum(q_tilde) - acc_t sum_exp = 0; - for (size_t j = 0; j < DIM_J; j++) { - acc_t q = c_buffer[j] - max_q; - acc_t z = (acc_t)(-q * qln2_inv) >> 16; - acc_t qp = q + z * qln2; - acc_t q_exp = (qp + qb) * (qp + qb) + qc; - c_buffer[j] = q_exp >> z; - sum_exp += c_buffer[j]; - } - - // pass 3: divide by sum - scale_t factor = - (127.f) / (float)sum_exp; // what corresponds to 1 in output? - for (size_t j = 0; j < DIM_J; j++) { - elem_t *c = C + (i * stride_C) + j; - *c = scale_and_sat(c_buffer[j], act, factor, bert_scale); - } - } - } - } -} - -#undef GEMMINI_SCALE - -// General matmul which can be run with different dataflows, or on the CPU -enum tiled_matmul_type_t { - OS, - WS, - CPU -}; // TODO rename this so it's name also applies to convs - -// This function runs a tiled matrix mulctiplication, with hardcoded tiling -// factors -static void tiled_matmul( - size_t dim_I, size_t dim_J, size_t dim_K, const elem_t *A, const elem_t *B, - const void *D, void *C, size_t stride_A, size_t stride_B, size_t stride_D, - size_t stride_C, scale_t A_scale_factor, scale_t B_scale_factor, - scale_acc_t D_scale_factor, int act, acc_scale_t scale, - acc_scale_t bert_scale, bool repeating_bias, size_t tile_I, size_t tile_J, - size_t tile_K, bool transpose_A, bool transpose_B, bool full_C, bool low_D, - uint8_t weightA, enum tiled_matmul_type_t tiled_matmul_type) { - -#ifdef GEMMINI_ASSERTIONS - // Make sure that the tiling factors make sense - if (tile_I <= 0) { - printf("tile_I is non-positive\n"); - exit(1); - } else if (tile_J <= 0) { - printf("tile_J is non-positive\n"); - exit(1); - } else if (tile_K <= 0) { - printf("tile_K is non-positive\n"); - exit(1); - } - - const size_t dim_I_padded = (dim_I / DIM + (dim_I % DIM != 0)) * DIM; - const size_t dim_J_padded = (dim_J / DIM + (dim_J % DIM != 0)) * DIM; - const size_t dim_K_padded = (dim_K / DIM + (dim_K % DIM != 0)) * DIM; - - if (tile_I * DIM > dim_I_padded) { - printf("tile_I is too large (tile_I * DIM > dim_I_padded)\n"); - exit(1); - } else if (tile_J * DIM > dim_J_padded) { - printf("tile_J is too large (tile_J * DIM > dim_J_padded)\n"); - exit(1); - } else if (tile_K * DIM > dim_K_padded) { - printf("tile_K is too large (tile_K * DIM > dim_K_padded)\n"); - exit(1); - } - - const bool double_buffered = tiled_matmul_type == WS; - - const size_t total_spad_size = - double_buffered ? BANK_NUM * BANK_ROWS / 2 : BANK_NUM * BANK_ROWS; - const size_t total_acc_size = double_buffered ? ACC_ROWS / 2 : ACC_ROWS; - - const size_t total_spad_rows = (tile_I * tile_K * DIM) + // Rows to store A - (tile_K * tile_J * DIM); // Rows to store B - - if (total_spad_rows > total_spad_size) { - printf("Not enough space in scratchpad to store A and B matrices\n"); - exit(1); - } - - const size_t total_acc_rows = tile_I * tile_J * DIM; // Rows to store C - - if (total_acc_rows > total_acc_size) { - printf("Not enough space in accumulator to store C\n"); - exit(1); - } - - if (tile_I > 65535 || tile_J > 65535 || tile_K > 65535) { - printf("I, J, and K tiling factors must be less than 65535, to fit within " - "the bounds of the LOOP_WS function"); - exit(1); - } - - char matmul_type_str[][4] = {"OS", "WS", "CPU"}; - - // Check if transpose options are correct - if (((tiled_matmul_type == OS) && (transpose_A || transpose_B)) || - (tiled_matmul_type == WS && transpose_A && transpose_B)) { - printf("Not implemented: %s matmul, a_transpose=%d, b_transpose=%d\n", - matmul_type_str[tiled_matmul_type], transpose_A, transpose_B); - exit(1); - } - - // Check if full_C options are correct - if ((tiled_matmul_type == CPU && (full_C || low_D)) || - (tiled_matmul_type == OS && low_D)) { - printf("Not implemented: %s matmul, full_C=%d, low_D=%d\n", - matmul_type_str[tiled_matmul_type], full_C, low_D); - } - - if (act == LAYERNORM || act == SOFTMAX) { - if (tiled_matmul_type == OS) { - printf("Not implemented: %s matmul, act=%d\n", - matmul_type_str[tiled_matmul_type], act); - } - if (tile_J * DIM < dim_J) { - printf("When doing layernorm or softmax, the full J dimension of the " - "matrix must fit in the accumulator\n"); - } - } -#endif - - // Run a tiled matrix multiplication on either Gemmini or the CPU - if (tiled_matmul_type == OS || tiled_matmul_type == WS) { - tiled_matmul_outer(dim_I, dim_J, dim_K, A, B, D, C, stride_A, stride_B, - stride_D, stride_C, A_scale_factor, B_scale_factor, - D_scale_factor, tile_I, tile_J, tile_K, act, scale, - bert_scale, repeating_bias, transpose_A, transpose_B, - full_C, low_D, weightA, (int)tiled_matmul_type); - } else /*if (tiled_matmul_type == CPU)*/ { - matmul_cpu(transpose_A, transpose_B, dim_I, dim_J, dim_K, A, B, - (const acc_t *)D, (elem_t *)C, stride_A, stride_B, stride_D, - stride_C, A_scale_factor, B_scale_factor, D_scale_factor, act, - scale, bert_scale, repeating_bias); - } -} - -static size_t tiled_matmul_total_spad_rows(size_t I, size_t J, size_t K) { - return (I * K + K * J) * DIM; -} - -static size_t tiled_matmul_total_acc_rows(size_t I, size_t J) { - return (I * J) * DIM; -} - -// This function runs a tiled matrix multiplication, with automatically -// calculated tiling factors -static void -tiled_matmul_auto(size_t dim_I, size_t dim_J, size_t dim_K, const elem_t *A, - const elem_t *B, const void *D, void *C, size_t stride_A, - size_t stride_B, size_t stride_D, size_t stride_C, - scale_t A_scale_factor, scale_t B_scale_factor, - scale_acc_t D_scale_factor, int act, acc_scale_t scale, - acc_scale_t bert_scale, bool repeating_bias, bool transpose_A, - bool transpose_B, bool full_C, bool low_D, uint8_t weightA, - enum tiled_matmul_type_t tiled_matmul_type) { - -#define partition_rows (BANK_NUM * BANK_ROWS / 2) -#define mats_in_partition (partition_rows / DIM) -#define mats_in_acc (ACC_ROWS / DIM) -#define max_tile_i_j ((size_t)sqrt(mats_in_acc)) -#define max_tile_k (mats_in_partition / max_tile_i_j) - - // "db_" means "double-buffered" -#define db_partition_rows ((BANK_NUM * BANK_ROWS / 2) / 2) -#define db_mats_in_partition (db_partition_rows / DIM) -#define db_mats_in_acc ((ACC_ROWS / 2) / DIM) -#define db_max_tile_i_j ((size_t)sqrt(db_mats_in_acc)) -#define db_max_tile_k (db_mats_in_partition / db_max_tile_i_j) - - const size_t dim_I_padded = (dim_I / DIM + (dim_I % DIM != 0)) * DIM; - const size_t dim_J_padded = (dim_J / DIM + (dim_J % DIM != 0)) * DIM; - const size_t dim_K_padded = (dim_K / DIM + (dim_K % DIM != 0)) * DIM; - - const bool double_buffered = tiled_matmul_type == WS; - - const size_t max_spad_rows = - double_buffered ? BANK_NUM * BANK_ROWS / 2 : BANK_NUM * BANK_ROWS; - const size_t max_acc_rows = double_buffered ? ACC_ROWS / 2 : ACC_ROWS; - - size_t tile_I, tile_J, tile_K; - - if (act == LAYERNORM || act == SOFTMAX) { - tile_I = 1; - tile_J = dim_J_padded / DIM; - tile_K = 1; - } else if (double_buffered) { - tile_I = dim_I_padded / DIM < db_max_tile_i_j ? dim_I_padded / DIM - : db_max_tile_i_j; - tile_J = dim_J_padded / DIM < db_max_tile_i_j ? dim_J_padded / DIM - : db_max_tile_i_j; - tile_K = - dim_K_padded / DIM < db_max_tile_k ? dim_K_padded / DIM : db_max_tile_k; - } else { - tile_I = - dim_I_padded / DIM < max_tile_i_j ? dim_I_padded / DIM : max_tile_i_j; - tile_J = - dim_J_padded / DIM < max_tile_i_j ? dim_J_padded / DIM : max_tile_i_j; - tile_K = dim_K_padded / DIM < max_tile_k ? dim_K_padded / DIM : max_tile_k; - } - - // Fill scratchpad as much as possible - while (true) { - bool increased = false; - - if (tiled_matmul_total_spad_rows(tile_I, tile_J + 1, tile_K) <= - max_spad_rows && - tiled_matmul_total_acc_rows(tile_I, tile_J + 1) <= max_acc_rows && - (tile_J + 1) * DIM <= dim_J_padded) { - tile_J++; - increased = true; - } - - if (tiled_matmul_total_spad_rows(tile_I + 1, tile_J, tile_K) <= - max_spad_rows && - tiled_matmul_total_acc_rows(tile_I + 1, tile_J) <= max_acc_rows && - (tile_I + 1) * DIM <= dim_I_padded) { - tile_I++; - increased = true; - } - - if (tiled_matmul_total_spad_rows(tile_I, tile_J, tile_K + 1) <= - max_spad_rows && - (tile_K + 1) * DIM <= dim_K_padded) { - tile_K++; - increased = true; - } - - if (!increased) - break; - } - -#ifdef PRINT_TILE -#if PRINT_TILE - const int spad_rows = tiled_matmul_total_spad_rows(tile_I, tile_J, tile_K); - const int acc_rows = tiled_matmul_total_acc_rows(tile_I, tile_J); - - printf("tile_I: %d\n", tile_I); - printf("tile_J: %d\n", tile_J); - printf("tile_K: %d\n\n", tile_K); - - printf("spad_rows: %d\n", spad_rows); - printf("acc_rows: %d\n\n", acc_rows); - - printf("spad_row utilization: %d%%\n", (spad_rows * 100) / max_spad_rows); - printf("acc_row utilization: %d%%\n\n", (acc_rows * 100) / max_acc_rows); - - exit(EXIT_SUCCESS); -#endif -#endif - - tiled_matmul(dim_I, dim_J, dim_K, A, B, D, C, stride_A, stride_B, stride_D, - stride_C, A_scale_factor, B_scale_factor, D_scale_factor, act, - scale, bert_scale, repeating_bias, tile_I, tile_J, tile_K, - transpose_A, transpose_B, full_C, low_D, weightA, - tiled_matmul_type); - -#undef partition_rows -#undef mats_in_partition -#undef mats_in_acc -#undef max_tile_i_j -#undef max_tile_k -} - -static void -sp_tiled_conv(int batch_size, int in_row_dim, int in_col_dim, int in_channels, - int out_channels, int out_row_dim, int out_col_dim, - int pool_out_row_dim, int pool_out_col_dim, - - int stride, int padding, int kernel_dim, int kernel_dilation, - int in_stride, int weight_stride, int out_stride, - - int pool_size, int pool_stride, int pool_padding, - - int batches, int porows, int pocols, int pochs, int krows, - int kcols, int kchs, - - int lpad, int rpad, int upad, int dpad, int plpad, int prpad, - int pupad, int pdpad, - - const elem_t *input, const elem_t *weights, elem_t *output, - const acc_t *bias, - - int act, acc_scale_t scale, - - bool wrot180, bool trans_output_1203, bool trans_input_3120, - bool trans_weight_1203, bool trans_weight_0132, - - bool no_bias, bool no_pool, bool downsample, bool input_dilated, - bool dw, int a_spad_id, int b_spad_id) { - - // When dw convs are true, we assume that kchs and ochs are 1 - if (dw) { - kchs = 1; - pochs = 1; - } - - const int orows = porows * pool_stride + pool_size - 1 - pupad - pdpad; - const int ocols = pocols * pool_stride + pool_size - 1 - plpad - prpad; - const int ochs = pochs; - - // Calculate image dimensions - // Note: "irows" and "icols" includes padding - const int dilated_krows = krows + (kernel_dilation - 1) * (krows - 1); - const int dilated_kcols = kcols + (kernel_dilation - 1) * (kcols - 1); - int irows = orows * stride + dilated_krows - 1; - int icols = ocols * stride + dilated_kcols - 1; - int irows_unpadded = irows - upad - dpad; - int icols_unpadded = icols - lpad - rpad; - const int ichs = kchs; - -#define UNDILATED(x) ((input_dilated) ? (((x) + 1) / 2) : (x)) - - if (input_dilated) { - irows_unpadded = (irows_unpadded + 1) / 2; - icols_unpadded = (icols_unpadded + 1) / 2; - - irows = irows_unpadded + UNDILATED(upad) + UNDILATED(dpad); - icols = icols_unpadded + UNDILATED(lpad) + UNDILATED(rpad); - } - -#ifdef HAS_FIRST_LAYER_OPTIMIZATIONS - const bool transposed = trans_output_1203 || trans_input_3120 || - trans_weight_1203 || trans_weight_0132; - int max_pixels_per_row = transposed || wrot180 || downsample || - input_dilated || kernel_dilation > 1 || - ichs > DIM - ? 1 - : DIM / ichs; - if (max_pixels_per_row > kcols) - max_pixels_per_row = kcols; -#else - const int max_pixels_per_row = 1; -#endif - - // Calculate spad address offsets - const int out_channels_per_bank = ochs / DIM + (ochs % DIM != 0); - const int in_channels_per_bank = kchs / DIM + (kchs % DIM != 0); - const int B_rows = trans_weight_0132 - ? in_channels_per_bank * kcols * krows * ochs - : out_channels_per_bank * kcols * krows * kchs; - - static uint32_t D_sp_addr_row = 0; - static uint32_t C_sp_addr_row = 0; - - const uint32_t A_sp_addr_start = 0; - const uint32_t B_sp_addr_start = BANK_NUM * BANK_ROWS - B_rows; - const uint32_t D_sp_addr_start = (1 << (ADDR_LEN - 1)) + D_sp_addr_row; - const uint32_t C_sp_addr_start = (3 << (ADDR_LEN - 2)) + C_sp_addr_row; - - if (bias != 0) { - D_sp_addr_row = (D_sp_addr_row + ACC_ROWS / 2) % ACC_ROWS; - } - - if (output != 0) { - C_sp_addr_row = (C_sp_addr_row + ACC_ROWS / 2) % ACC_ROWS; - } - - gemmini_loop_conv_ws( - batch_size, in_row_dim, in_col_dim, in_channels, out_channels, - out_row_dim, out_col_dim, pool_out_row_dim, pool_out_col_dim, stride, - padding, kernel_dim, kernel_dilation, pool_size, pool_stride, - pool_padding, batches, porows, pocols, pochs, krows, kcols, kchs, lpad, - rpad, upad, dpad, plpad, prpad, pupad, pdpad, orows, ocols, weights, - output, bias, input, no_bias, no_pool, downsample, wrot180, input_dilated, - act, trans_output_1203, trans_weight_1203, trans_weight_0132, - trans_input_3120, max_pixels_per_row, in_stride, weight_stride, - out_stride, dw, a_spad_id, b_spad_id); - - /* - if (!no_pool) { - printf("Pooling with rectangular convolutions is currently not - supported.\n"); exit(1); - } - - // Only rectangular convolutions will use the following C code - - // mvin bias - if (bias != NULL) { - // TODO we probably don't need quite this many nested loops for this part - - const int max_ochs_per_mvin = ochs < MAX_BLOCK_LEN_ACC * DIM ? ochs : - MAX_BLOCK_LEN_ACC * DIM; - - gemmini_extended4_config_ld(0, MVIN_SCALE_IDENTITY, false, batches * orows - * ocols, 2); - - for (int b = 0; b < batches; b++) - for (int orow = 0; orow < orows; orow++) - for (int ocol = 0; ocol < ocols; ocol += DIM) { - const int I = ocols - ocol > DIM ? DIM : ocols - ocol; - - for (int och = 0; och < ochs; och += max_ochs_per_mvin) { - const int J = ochs - och > max_ochs_per_mvin ? max_ochs_per_mvin : - ochs - och; - - const uint32_t D_sp_addr = D_sp_addr_start + (och / DIM) * batches - * orows * ocols + b * orows * ocols + orow * ocols + ocol; - - const acc_t * bias_dram_addr = no_bias ? NULL : bias + och; - - gemmini_extended_mvin3(bias_dram_addr, - D_sp_addr, - J, I); - } - } - } - - // mvin input - if (input != NULL){ - int max_chs_per_mvin = ichs < MAX_BLOCK_LEN * DIM ? ichs : - MAX_BLOCK_LEN * DIM; - if (trans_input_3120) { - max_chs_per_mvin = batches < MAX_BLOCK_LEN * DIM ? batches : - MAX_BLOCK_LEN * DIM; - } - - const int dram_stride = trans_input_3120 ? - batch_size * sizeof(elem_t) : - in_channels * sizeof(elem_t); - - const int spad_stride = trans_input_3120 ? - ichs * (irows >> downsample) * (icols >> downsample) : - batches * (irows >> downsample) * (icols >> downsample); - - gemmini_extended5_config_ld(dram_stride << downsample, - MVIN_SCALE_IDENTITY, false, spad_stride, max_pixels_per_row, 0); - - const int b_it = trans_input_3120 ? max_chs_per_mvin : 1; - const int ich_it = trans_input_3120 ? 1 : max_chs_per_mvin; - - for (int b = 0; b < batches; b += b_it) - for (int irow = -UNDILATED(upad); irow < irows_unpadded + - UNDILATED(dpad); irow += 1 + downsample) { const int irow_padded = irow + - UNDILATED(upad); - - for (int icol = -UNDILATED(lpad); icol < icols_unpadded + - UNDILATED(rpad);) { - // TODO There might be some unnecessary mvins here at the edge of - the image - - int I = icols_unpadded - icol > (DIM << downsample) ? - (DIM << downsample) : icols_unpadded - icol; - - if (icol < 0) { - I = -icol > DIM ? DIM : -icol; - } else if (icol >= icols_unpadded) { - I = icols_unpadded + UNDILATED(rpad) - icol > DIM ? DIM : - icols_unpadded + UNDILATED(rpad) - icol; - } - - const int icol_padded = icol + UNDILATED(lpad); - - for (int ich = 0; ich < ichs; ich += ich_it) { - int K = ichs - ich > max_chs_per_mvin ? - max_chs_per_mvin : ichs - ich; - if (trans_input_3120) { - K = batches - b > max_chs_per_mvin ? - max_chs_per_mvin : batches - b; - } - - #define DS(x) ((x) >> (downsample)) - - uint32_t A_sp_addr = A_sp_addr_start + (ich / DIM) * batches * - DS(irows) * DS(icols) + b * DS(irows) * DS(icols) + DS(irow_padded) * - DS(icols) + DS(icol_padded); if (trans_input_3120) { A_sp_addr = - A_sp_addr_start + (b / DIM) * ichs * DS(irows) * DS(icols) + ich * DS(irows) * - DS(icols) + DS(irow_padded) * DS(icols) + DS(icol_padded); - } - - const bool is_zeros = irow < 0 || irow >= irows_unpadded || icol < - 0 || icol >= icols_unpadded; - - const elem_t * in = input + (b*in_row_dim*in_col_dim + - irow*in_col_dim + icol) * in_stride + ich; if (is_zeros) { in = NULL; } else - if (trans_input_3120) { in = input + (ich*in_row_dim*in_col_dim + - irow*in_col_dim + icol) * batch_size + b; - } - - gemmini_extended_mvin(in, - A_sp_addr, - K, I >> downsample); - } - - icol += I; - } - } - } - - // mvin weights - if (weights != NULL) { - int max_chs_per_mvin = ochs < MAX_BLOCK_LEN * DIM ? ochs : - MAX_BLOCK_LEN * DIM; - if (trans_weight_0132) { - max_chs_per_mvin = kchs < MAX_BLOCK_LEN * DIM ? kchs : - MAX_BLOCK_LEN * DIM; - } - - size_t dram_stride = weight_stride * sizeof(elem_t); - if (dw) { - dram_stride = sizeof(elem_t); - } else if (trans_weight_1203) { - dram_stride = kernel_dim * kernel_dim * out_channels * sizeof(elem_t); - } else if (trans_weight_0132) { - dram_stride = in_channels * sizeof(elem_t); - } - - const size_t spad_block_stride = trans_weight_0132 ? - krows * kcols * ochs : krows * kcols * kchs; - - gemmini_extended4_config_ld(dram_stride, MVIN_SCALE_IDENTITY, false, - spad_block_stride, 1); - - const size_t och_it = trans_weight_0132 ? DIM : max_chs_per_mvin; - const size_t kch_it = trans_weight_0132 ? max_chs_per_mvin : DIM; - - for (int och = 0; och < ochs; och += och_it) { - for (int krow = 0; krow < krows; krow++) - for (int kcol = 0; kcol < kcols; kcol++) - for (int kch = 0; kch < kchs; kch += kch_it) { - int K = kchs - kch > DIM ? DIM : kchs - kch; - int J = ochs - och > max_chs_per_mvin ? max_chs_per_mvin : ochs - - och; if (trans_weight_0132) { K = ochs - och > DIM ? DIM : ochs - och; J = - kchs - kch > max_chs_per_mvin ? max_chs_per_mvin : kchs - kch; - } - - uint32_t B_sp_addr = B_sp_addr_start + (och / DIM) * krows * kcols - * kchs + krow * kcols * kchs + kcol * kchs + kch; if (trans_weight_0132) { - B_sp_addr = B_sp_addr_start + (kch / DIM) * krows * kcols * ochs - + krow * kcols * ochs + kcol * ochs + och; - } - - const elem_t * w = weights + (krow*kernel_dim*in_channels + - kcol*in_channels + kch) * weight_stride + och; if (dw) { w = weights + krow * - kernel_dim + kcol; } else if (trans_weight_1203) { w = weights + (kch * - kernel_dim * kernel_dim + krow * kernel_dim + kcol) * out_channels + och; } - else if (trans_weight_0132) { w = weights + (krow * kernel_dim * out_channels - + kcol * out_channels + och) * in_channels + kch; - } - - gemmini_extended_mvin2(w, B_sp_addr, J, K); - } - } - } - - // Compute - { - const int b_it = trans_input_3120 ? DIM : 1; - const int ocol_it = trans_input_3120 ? 1 : (DIM << input_dilated); - - if (trans_input_3120) { - gemmini_extended3_config_ex(0, 0, 0, 0, orows * ocols, irows * icols, 0, - 0, true); - } - - for (int och = 0; och < ochs; och += DIM) { - for (int krow = 0; krow < krows; krow++) { - for (int kcol = 0; kcol < kcols; kcol += max_pixels_per_row) { - for (int kch = 0; kch < kchs; kch += DIM) { - bool new_weights = true; - - for (int b = 0; b < batches; b += b_it) { - for (int orow = 0; orow < orows; orow++) { - // Skip some kernel rows due to input-dilation - if (input_dilated && ((krow * kernel_dilation + orow * stride - - upad) % 2 != 0)) { continue; - } - - for (int ocol = 0; ocol < ocols;) { - // Skip some cols dimensions due to input-dilation - if (input_dilated && ((kcol + ocol * stride - lpad) % 2 != - 0)) { ocol++; continue; - } - - int irow = orow * stride + krow * kernel_dilation; - int icol = ocol * stride + kcol * kernel_dilation; - - if (input_dilated) { - irow = (irow + 1) / 2; - icol = (icol + 1) / 2; - } - - const int pixels = kcols - kcol > max_pixels_per_row ? - max_pixels_per_row : kcols - kcol; - - const uint32_t C_sp_addr = C_sp_addr_start + (och / DIM) * - batches * orows * ocols + b * orows * ocols + orow * ocols + ocol; - - // Over here, construct a new matrix - // - // Let us assume that we only ever operate on - // one pixel in one row. - // Thus, krows == kcols == 1 - // - // Then, for every set of I, J, and K values - // - I = ocols - // - J = ochs - // - K = kchs - - int I = UNDILATED(ocols - ocol > (DIM << input_dilated) ? - (DIM << input_dilated) : ocols - ocol); const int J = ochs - och > DIM ? DIM : - ochs - och; const int K = pixels * (kchs - kch > DIM ? DIM : kchs - kch); - - if (trans_input_3120) { - I = batches - b > DIM ? DIM : batches - b; - } - - uint32_t A_sp_addr = A_sp_addr_start + (kch / DIM) * batches - * DS(irows) * DS(icols) + b * DS(irows) * DS(icols) + DS(irow) * DS(icols) + - DS(icol); if (trans_input_3120) { A_sp_addr = A_sp_addr_start + (b / DIM) * - kchs * DS(irows) * DS(icols) + kch * DS(irows) * DS(icols) + DS(irow) * - DS(icols) + DS(icol); - } - - const int krow_ = wrot180 ? krows - krow - 1 : krow; - const int kcol_ = wrot180 ? kcols - kcol - 1 : kcol; - - uint32_t B_sp_addr = B_sp_addr_start + (och / DIM) * krows * - kcols * kchs + krow_ * kcols * kchs + kcol_ * kchs + kch; if - (trans_weight_0132) { B_sp_addr = B_sp_addr_start + (kch / DIM) * krows * - kcols * ochs + krow_ * kcols * ochs + kcol_ * ochs + och; - } - - const uint32_t pre_sp_addr = new_weights ? - B_sp_addr : GARBAGE_ADDR; - - // perform matmul - gemmini_extended_preload(pre_sp_addr, C_sp_addr, J, K, J, - I); - - if (new_weights) { - gemmini_extended_compute_preloaded(A_sp_addr, - GARBAGE_ADDR, K, I, J, I); } else { - gemmini_extended_compute_accumulated(A_sp_addr, - GARBAGE_ADDR, K, I, J, I); - } - - ocol += ocol_it; - new_weights = false; - } - } - } - } - } - } - } - } - - #undef DS - #undef UNDILATED - - // mvout output - if (output != NULL) { - if (no_pool) { - for (int b = 0; b < batches; b++) - for (int orow = 0; orow < orows; orow++) - for (int ocol = 0; ocol < ocols; ocol += DIM) { - const int I = ocols - ocol > DIM ? DIM : ocols - ocol; - - for (int och = 0; och < ochs; och += DIM) { - const int J = ochs - och > DIM ? DIM : ochs - och; - - const uint32_t C_sp_addr = C_sp_addr_start + (och / DIM) * - batches * orows * ocols + b * orows * ocols + orow * ocols + ocol; - - elem_t * out = output + (b*out_row_dim*out_col_dim + - orow*out_col_dim + ocol) * out_stride + och; if (trans_output_1203) { out = - output + (orow*out_col_dim*batch_size + ocol*batch_size + b) * out_channels + - och; - } - - gemmini_extended_mvout(out, - C_sp_addr, - J, I); - } - } - } else { - printf("Pooling with rectangular convolutions is currently not - supported.\n"); exit(1); - */ - /* - gemmini_extended2_config_st(out_channels * sizeof(elem_t), act, scale, -pool_stride, pool_size, pool_out_row_dim, porows, pocols, orows, ocols, pupad, -plpad); - - for (int b = 0; b < batches; b++) { - for (int poch = 0; poch < pochs; poch += DIM) { - const int channels = poch + DIM >= pochs ? pochs - poch : DIM; - - elem_t * pout = output + (b * pool_out_row_dim * -pool_out_col_dim)*out_channels + poch; - - const uint32_t C_sp_addr = C_sp_addr_start + (poch / DIM) * batches * -orows * ocols + b * orows * ocols; - - gemmini_extended_mvout(pout, - C_sp_addr, - channels, 0); - } - } - - gemmini_extended_config_st(out_channels * sizeof(elem_t), act, scale); -<<<<<<< HEAD - */ - // } - // } - // } - //} -} - -static int tiled_conv_total_spad_rows_dw(bool acc, bool weight, int stride, - int batches, int porows, int pocols, - int ochs, int krows, int kcols, - int kchs, int pool_size, - int pool_stride) { - - const int orows = porows * pool_stride + pool_size - 1; - const int ocols = pocols * pool_stride + pool_size - 1; - - const int irows = orows * stride + krows - 1; // - 2 * padding; - const int icols = ocols * stride + kcols - 1; // - 2 * padding; - const int ichs = kchs; - - const int in_channels_per_bank = ichs / DIM + (ichs % DIM != 0); - const int out_channels_per_bank = ochs / DIM + (ochs % DIM != 0); - - const int A_rows = in_channels_per_bank * batches * irows * icols; - const int B_rows = out_channels_per_bank * kcols * krows * kchs; - const int C_rows = out_channels_per_bank * batches * orows * ocols; - - if (acc) - return C_rows; - else if (weight) - return B_rows; - else - return A_rows; -} - -static int tiled_conv_total_spad_rows(bool acc, int stride, int input_dilation, - int kernel_dilation, bool downsample, - bool trans_weight_0132, - bool trans_input_3120, int batches, - int porows, int pocols, int ochs, - int krows, int kcols, int kchs, - int pool_size, int pool_stride) { - - const int orows = porows * pool_stride + pool_size - 1; - const int ocols = pocols * pool_stride + pool_size - 1; - - const int krows_dilated = krows + (kernel_dilation - 1) * (krows - 1); - const int kcols_dilated = kcols + (kernel_dilation - 1) * (kcols - 1); - - int irows = orows * stride + krows_dilated - 1; // - 2 * padding; - int icols = ocols * stride + kcols_dilated - 1; // - 2 * padding; - const int ichs = kchs; - - irows = irows / input_dilation + (irows % input_dilation != 0); - icols = icols / input_dilation + (icols % input_dilation != 0); - - const int in_channels_per_bank = ichs / DIM + (ichs % DIM != 0); - const int out_channels_per_bank = ochs / DIM + (ochs % DIM != 0); - const int batches_per_bank = batches / DIM + (batches % DIM != 0); - - const int A_rows = trans_input_3120 - ? (batches_per_bank * ichs * (irows >> downsample) * - (icols >> downsample)) - : (in_channels_per_bank * batches * - (irows >> downsample) * (icols >> downsample)); - - const int B_rows = trans_weight_0132 - ? in_channels_per_bank * kcols * krows * ochs - : out_channels_per_bank * kcols * krows * kchs; - - const int C_rows = out_channels_per_bank * batches * orows * ocols; - - return acc ? C_rows : A_rows + B_rows; -} - -static void conv_cpu_without_pool( - int batch_size, int in_row_dim, int in_col_dim, int in_channels, - int out_channels, int out_row_dim, int out_col_dim, int stride, - int input_dilation, int kernel_dilation, int padding, int kernel_dim, - int in_stride, int weight_stride, int out_stride, bool wrot180, - bool trans_output_1203, bool trans_input_3120, bool trans_weight_1203, - bool trans_weight_0132, - - const elem_t *input, const elem_t *weights, const acc_t *bias, - elem_t *output, - - int act, acc_scale_t scale) { - - bool no_bias = bias == NULL; - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int och = 0; och < out_channels; och++) { - - acc_t opixel = no_bias ? 0 : bias[och]; - - for (int krow = 0; krow < kernel_dim; krow++) { - if ((orow * stride + krow * kernel_dilation - padding) % - input_dilation != - 0) - continue; - - const int irow = - (orow * stride + krow * kernel_dilation - padding) / - input_dilation; - - for (int kcol = 0; kcol < kernel_dim; kcol++) { - if ((ocol * stride + kcol * kernel_dilation - padding) % - input_dilation != - 0) - continue; - - const int icol = - (ocol * stride + kcol * kernel_dilation - padding) / - input_dilation; - - for (int kch = 0; kch < in_channels; kch++) { - const elem_t *in = - input + - (b * in_row_dim * in_col_dim + irow * in_col_dim + icol) * - in_stride + - kch; - if (trans_input_3120) { - // NHWC to CHWN - in = input + - (kch * in_row_dim * in_col_dim + irow * in_col_dim + - icol) * - batch_size + - b; - } - - elem_t ipixel = irow < 0 || irow >= in_row_dim || icol < 0 || - icol >= in_col_dim - ? 0 - : *in; - - const int krow_ = wrot180 ? kernel_dim - krow - 1 : krow; - const int kcol_ = wrot180 ? kernel_dim - kcol - 1 : kcol; - - elem_t weight = *(weights + - (krow_ * kernel_dim * in_channels + - kcol_ * in_channels + kch) * - weight_stride + - och); - if (trans_weight_1203) { - // HWIO to WIHO - weight = *(weights + - (kch * kernel_dim * kernel_dim + - krow_ * kernel_dim + kcol_) * - out_channels + - och); - } else if (trans_weight_0132) { - // HWIO to HWOI - weight = *(weights + - (krow_ * kernel_dim * out_channels + - kcol_ * out_channels + och) * - in_channels + - kch); - } - - opixel += weight * ipixel; - } - } - } - - elem_t *out = - output + - (b * out_row_dim * out_col_dim + orow * out_col_dim + ocol) * - out_stride + - och; - if (trans_output_1203) { - // NHWC to HWNC - out = output + - (orow * out_col_dim * batch_size + ocol * batch_size + b) * - out_channels + - och; - } - - *out = scale_and_sat(opixel, act, scale, 0); - } - } - } - } -} - -static void conv_dw_cpu_without_pool(int batch_size, int in_row_dim, - int in_col_dim, int channels, - int out_row_dim, int out_col_dim, - int stride, int padding, int kernel_dim, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale) { - - bool no_bias = bias == NULL; - - for (int b = 0; b < batch_size; b++) { - for (int orow = 0; orow < out_row_dim; orow++) { - for (int ocol = 0; ocol < out_col_dim; ocol++) { - for (int ch = 0; ch < channels; ch++) { - acc_t opixel = no_bias ? 0 : bias[ch]; - - for (int krow = 0; krow < kernel_dim; krow++) { - const int irow = orow * stride + krow - padding; - - for (int kcol = 0; kcol < kernel_dim; kcol++) { - const int icol = ocol * stride + kcol - padding; - - const elem_t *in = - input + - (b * in_row_dim * in_col_dim + irow * in_col_dim + icol) * - channels + - ch; - - const elem_t ipixel = irow < 0 || irow >= in_row_dim || - icol < 0 || icol >= in_col_dim - ? 0 - : *in; - - const elem_t weight = - *(weights + (ch * kernel_dim + krow) * kernel_dim + kcol); - - opixel += weight * ipixel; - } - } - - elem_t *out = - output + - (b * out_row_dim * out_col_dim + orow * out_col_dim + ocol) * - channels + - ch; - - *out = scale_and_sat(opixel, act, scale, 0); - } - } - } - } -} - -static void conv_cpu(int batch_size, int in_row_dim, int in_col_dim, - int in_channels, int out_channels, int out_row_dim, - int out_col_dim, int stride, int input_dilation, - int kernel_dilation, int padding, int kernel_dim, - int in_stride, int weight_stride, int out_stride, - bool wrot180, bool trans_output_1203, - bool trans_input_3120, bool trans_weight_1203, - bool trans_weight_0132, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale, int pool_size, int pool_stride, - int pool_padding) { - - const bool no_pool = pool_stride == 0; - if (no_pool) { - conv_cpu_without_pool( - batch_size, in_row_dim, in_col_dim, in_channels, out_channels, - out_row_dim, out_col_dim, stride, input_dilation, kernel_dilation, - padding, kernel_dim, in_stride, weight_stride, out_stride, wrot180, - trans_output_1203, trans_input_3120, trans_weight_1203, - trans_weight_0132, input, weights, bias, output, act, scale); - return; - } - - const bool no_bias = bias == NULL; - const int pool_out_row_dim = - (out_row_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int pool_out_col_dim = - (out_col_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - - for (int b = 0; b < batch_size; b++) { - for (int porow = 0; porow < pool_out_row_dim; porow++) { - for (int pocol = 0; pocol < pool_out_col_dim; pocol++) { - for (int poch = 0; poch < out_channels; poch++) { - - elem_t running_max = 0; - bool running_max_initialized = false; - - for (int pwrow = 0; pwrow < pool_size; pwrow++) { - const int orow = porow * pool_stride + pwrow - pool_padding; - - for (int pwcol = 0; pwcol < pool_size; pwcol++) { - const int ocol = pocol * pool_stride + pwcol - pool_padding; - - if (orow < 0 || orow >= out_row_dim || ocol < 0 || - ocol >= out_col_dim) { - if (!running_max_initialized || running_max < 0) { - running_max = 0; - running_max_initialized = true; - } - } else { - - acc_t opixel = no_bias ? 0 : bias[poch]; - - for (int krow = 0; krow < kernel_dim; krow++) { - if ((orow * stride + krow * kernel_dilation - padding) % - input_dilation != - 0) - continue; - - const int irow = - (orow * stride + krow * kernel_dilation - padding) / - input_dilation; - - for (int kcol = 0; kcol < kernel_dim; kcol++) { - if ((ocol * stride + kcol * kernel_dilation - padding) % - input_dilation != - 0) - continue; - - const int icol = - (ocol * stride + kcol * kernel_dilation - padding) / - input_dilation; - - for (int kch = 0; kch < in_channels; kch++) { - const elem_t *in = input + - (b * in_row_dim * in_col_dim + - irow * in_col_dim + icol) * - in_stride + - kch; - if (trans_input_3120) { - // NHWC to CHWN - in = input + - (kch * in_row_dim * in_col_dim + - irow * in_col_dim + icol) * - batch_size + - b; - } - - elem_t ipixel = irow < 0 || irow >= in_row_dim || - icol < 0 || icol >= in_col_dim - ? 0 - : *in; - - const int krow_ = wrot180 ? kernel_dim - krow - 1 : krow; - const int kcol_ = wrot180 ? kernel_dim - kcol - 1 : kcol; - - elem_t weight = *(weights + - (krow_ * kernel_dim * in_channels + - kcol_ * in_channels + kch) * - weight_stride + - poch); - if (trans_weight_1203) { - // HWIO to WIHO - weight = *(weights + - (kch * kernel_dim * kernel_dim + - krow_ * kernel_dim + kcol_) * - out_channels + - poch); - } else if (trans_weight_0132) { - // HWIO to HWOI - weight = *(weights + - (krow_ * kernel_dim * out_channels + - kcol_ * out_channels + poch) * - in_channels + - kch); - } - - opixel += weight * ipixel; - } - } - } - - opixel = scale_and_sat(opixel, act, scale, 0); - if (!running_max_initialized || opixel > running_max) { - running_max = opixel; - running_max_initialized = true; - } - } - - if (pwrow == pool_size - 1 && pwcol == pool_size - 1) { - elem_t *out = output + - (b * pool_out_row_dim * pool_out_col_dim + - porow * pool_out_col_dim + pocol) * - out_stride + - poch; - if (trans_output_1203) { - // NHWC to HWNC - out = output + - (porow * pool_out_col_dim * batch_size + - pocol * batch_size + b) * - out_channels + - poch; - } - - *out = running_max; - } - } - } - } - } - } - } -} - -static void conv_dw_cpu(int batch_size, int in_row_dim, int in_col_dim, - int channels, int out_row_dim, int out_col_dim, - int stride, int padding, int kernel_dim, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale, int pool_size, - int pool_stride, int pool_padding) { - - const bool no_pool = pool_stride == 0; - if (no_pool) { - conv_dw_cpu_without_pool( - batch_size, in_row_dim, in_col_dim, channels, out_row_dim, out_col_dim, - stride, padding, kernel_dim, input, weights, bias, output, act, scale); - return; - } - - const bool no_bias = bias == NULL; - const int pool_out_row_dim = - (out_row_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int pool_out_col_dim = - (out_col_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - - for (int b = 0; b < batch_size; b++) { - for (int porow = 0; porow < pool_out_row_dim; porow++) { - for (int pocol = 0; pocol < pool_out_col_dim; pocol++) { - for (int ch = 0; ch < channels; ch++) { - - elem_t running_max = 0; - bool running_max_initialized = false; - - for (int pwrow = 0; pwrow < pool_size; pwrow++) { - const int orow = porow * pool_stride + pwrow - pool_padding; - - for (int pwcol = 0; pwcol < pool_size; pwcol++) { - const int ocol = pocol * pool_stride + pwcol - pool_padding; - - if (orow < 0 || orow >= out_row_dim || ocol < 0 || - ocol >= out_col_dim) { - if (!running_max_initialized || running_max < 0) { - running_max = 0; - running_max_initialized = true; - } - } else { - - acc_t opixel = no_bias ? 0 : bias[ch]; - - for (int krow = 0; krow < kernel_dim; krow++) { - const int irow = orow * stride + krow - padding; - - for (int kcol = 0; kcol < kernel_dim; kcol++) { - const int icol = ocol * stride + kcol - padding; - - const elem_t *in = input + - (b * in_row_dim * in_col_dim + - irow * in_col_dim + icol) * - channels + - ch; - - elem_t ipixel = irow < 0 || irow >= in_row_dim || - icol < 0 || icol >= in_col_dim - ? 0 - : *in; - - const elem_t weight = *( - weights + (ch * kernel_dim + krow) * kernel_dim + kcol); - - opixel += weight * ipixel; - } - } - - opixel = scale_and_sat(opixel, act, scale, 0); - if (!running_max_initialized || opixel > running_max) { - running_max = opixel; - running_max_initialized = true; - } - } - - if (pwrow == pool_size - 1 && pwcol == pool_size - 1) { - elem_t *out = output + - (b * pool_out_row_dim * pool_out_col_dim + - porow * pool_out_col_dim + pocol) * - channels + - ch; - - *out = running_max; - } - } - } - } - } - } - } -} - -static void tiled_conv(int batch_size, int in_row_dim, int in_col_dim, - int in_channels, int out_channels, int out_row_dim, - int out_col_dim, int stride, int input_dilation, - int kernel_dilation, int padding, int kernel_dim, - int in_stride, int weight_stride, int out_stride, - bool wrot180, bool trans_output_1203, - bool trans_input_3120, bool trans_weight_1203, - bool trans_weight_0132, - - int batches, int porows, int pocols, int pochs, - int krows, int kcols, int kchs, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale, int pool_size, - int pool_stride, int pool_padding, - - enum tiled_matmul_type_t tiled_conv_type) { - -#ifdef GEMMINI_ASSERTIONS - if (trans_weight_1203 && trans_weight_0132) { - printf("Only one weight transformation can be applied at a time\n"); - exit(1); - } -#endif - - if (tiled_conv_type == CPU) { - if (pool_size == 1 && pool_stride == 1 && pool_padding == 0) { - pool_stride = 0; - } - - // assume in_dim_rows = in_dim_cols - // and out_dim_rows = out_dim_cols for now - conv_cpu(batch_size, in_row_dim, in_col_dim, in_channels, out_channels, - out_row_dim, out_col_dim, stride, input_dilation, kernel_dilation, - padding, kernel_dim, in_stride, weight_stride, out_stride, wrot180, - trans_output_1203, trans_input_3120, trans_weight_1203, - trans_weight_0132, input, weights, bias, output, act, scale, - pool_size, pool_stride, pool_padding); - return; - } else if (tiled_conv_type == OS) { - printf("Gemmini convs do not currently support OS\n"); - exit(1); - } - - // TODO move everything below this into a tiled_conv_outer function to match - // the tiled_matmul function - - bool no_bias = false; - if (bias == NULL) { - bias = (acc_t *)1; - no_bias = true; - } - - bool no_pool = pool_stride == 0; - if (no_pool) { - pool_size = 1; - pool_stride = 1; - pool_padding = 0; - } - - const bool downsample = stride == 2 && kernel_dim == 1 && - in_row_dim % 2 == 0 && in_col_dim % 2 == 0 && - padding == 0 && no_pool && input_dilation == 1 && - !trans_input_3120; - - const int input_dilated = input_dilation == 2; - -#ifdef GEMMINI_ASSERTIONS - { - // const int orows = porows * pool_stride + pool_size - 1; - // const int ocols = pocols * pool_stride + pool_size - 1; - - // Check that data will fit in scratchpad - const int spad_rows = tiled_conv_total_spad_rows( - false, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, batches, porows, pocols, pochs, - krows, kcols, kchs, pool_size, pool_stride); - const int acc_rows = tiled_conv_total_spad_rows( - true, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, batches, porows, pocols, pochs, - krows, kcols, kchs, pool_size, pool_stride); - - if (spad_rows > BANK_NUM * BANK_ROWS / 2) { - printf("not enough scratchpad space to store inputs and weights, %d\n", - spad_rows); - exit(1); - } - if (acc_rows > ACC_ROWS / 2) { - printf("not enough accumulator space to store outputs\n"); - exit(1); - } - if (kernel_dim <= padding) { - printf("kernel_dim must be larger than padding\n"); - exit(1); - } - if (input_dilation > 2) { - printf("input_dilation > 2 is only supported on CPU\n"); - exit(1); - } - if (input_dilation > 1 && stride > 1) { - printf("input input_dilation is only supported when stride == 1\n"); - exit(1); - } - if (trans_output_1203 && !no_pool) { - printf("Output can only be transposed when pooling is disabled\n"); - exit(1); - } - if (trans_input_3120 && trans_weight_0132) { - printf("Cannot transpose innermost dimensions of both inputs and weights " - "on WS.\n"); - exit(1); - } - } -#endif - - const size_t st_dram_stride = trans_output_1203 - ? batch_size * out_channels * sizeof(elem_t) - : out_stride * sizeof(elem_t); - gemmini_extended_config_st(st_dram_stride, act, scale); - - gemmini_extended3_config_ex(WEIGHT_STATIONARY, 0, 0, 0, input_dilation, - stride >> downsample, trans_input_3120, - trans_weight_0132, false); - - const int pool_out_row_dim = - (out_row_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int pool_out_col_dim = - (out_col_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int dilated_in_row_dim = - in_row_dim + (input_dilation - 1) * (in_row_dim - 1); - const int dilated_in_col_dim = - in_col_dim + (input_dilation - 1) * (in_col_dim - 1); - - size_t a_spad_id = 0; - size_t b_spad_id = 0; - - int porow_end = pool_out_row_dim; - int porow_start = 0; - bool a_reuse = false; - bool b_reuse = false; - size_t num_kch = ceil_divide_int(in_channels, kchs); - size_t num_poch = ceil_divide_int(out_channels, pochs); - size_t num_b = ceil_divide_int(batch_size, batches); - size_t num_porow = ceil_divide_int((porow_end - porow_start), porows); - size_t num_pocol = ceil_divide_int(pool_out_col_dim, pocols); - size_t num_krow = ceil_divide_int(kernel_dim, krows); - size_t num_kcol = ceil_divide_int(kernel_dim, kcols); - - // printf("num_kch: %d, num_poch: %d, num_b: %d, num_porow: %d, num_pocol: - // %d, num_krow: %d, num_kcol: %d\n", num_kch, num_poch, num_b, num_porow, - // num_pocol, num_krow, num_kcol); - - if (num_kch * num_poch * num_krow * num_kcol <= 2) - b_reuse = true; - if (num_kch * num_krow * num_kcol * num_b * num_porow * num_pocol <= 2) - a_reuse = true; - - for (int b = 0; b < batch_size; b += batches) { - for (int porow = porow_start; porow < porow_end; porow += porows) { - const int orow = porow * pool_stride - pool_padding; - - for (int pocol = 0; pocol < pool_out_col_dim; pocol += pocols) { - const int ocol = pocol * pool_stride - pool_padding; - - for (int poch = 0; poch < out_channels; poch += pochs) { - for (int krow = 0; krow < kernel_dim; krow += krows) { - const int orow_floored = orow < 0 ? 0 : orow; - int irow = orow_floored * stride + krow * kernel_dilation - padding; - - for (int kcol = 0; kcol < kernel_dim; kcol += kcols) { - const int ocol_floored = ocol < 0 ? 0 : ocol; - int icol = - ocol_floored * stride + kcol * kernel_dilation - padding; - - for (int kch = 0; kch < in_channels; kch += kchs) { - if (a_reuse) - a_spad_id = (kch + krow + kcol + b + (porow - porow_start) + - pocol) == 0 - ? 1 - : 2; - if (b_reuse) - b_spad_id = (kch + poch + krow + kcol) == 0 ? 1 : 2; - elem_t *out = output + - (b * pool_out_row_dim * pool_out_col_dim + - porow * pool_out_col_dim + pocol) * - out_stride + - poch; - if (trans_output_1203) { - out = output + - (porow * pool_out_col_dim * batch_size + - pocol * batch_size + b) * - out_channels + - poch; - } - - if (krow + krows < kernel_dim || kcol + kcols < kernel_dim || - kch + kchs < in_channels) { - out = NULL; - } - - const acc_t *bias_ = bias + poch; - if (krow > 0 || kcol > 0 || kch > 0) { - bias_ = NULL; - } - - const int batches_ = - batch_size - b > batches ? batches : batch_size - b; - const int porows_ = pool_out_row_dim - porow > porows - ? porows - : pool_out_row_dim - porow; - const int pocols_ = pool_out_col_dim - pocol > pocols - ? pocols - : pool_out_col_dim - pocol; - const int pochs_ = - out_channels - poch > pochs ? pochs : out_channels - poch; - const int krows_ = - kernel_dim - krow > krows ? krows : kernel_dim - krow; - const int kcols_ = - kernel_dim - kcol > kcols ? kcols : kernel_dim - kcol; - const int kchs_ = - in_channels - kch > kchs ? kchs : in_channels - kch; - - const int ocols_ = pocols_ * pool_stride + pool_size - 1; - const int orows_ = porows_ * pool_stride + pool_size - 1; - - const int plpad = ocol < 0 ? -ocol : 0; - const int prpad = ocol + ocols_ > out_col_dim - ? ocol + ocols_ - out_col_dim - : 0; - const int pupad = orow < 0 ? -orow : 0; - const int pdpad = orow + orows_ > out_row_dim - ? orow + orows_ - out_row_dim - : 0; - - const int dilated_krows_ = - krows_ + (kernel_dilation - 1) * (krows_ - 1); - const int dilated_kcols_ = - kcols_ + (kernel_dilation - 1) * (kcols_ - 1); - - const int icols_ = - (ocols_ - plpad - prpad) * stride + dilated_kcols_ - 1; - const int irows_ = - (orows_ - pupad - pdpad) * stride + dilated_krows_ - 1; - - int lpad = icol < 0 ? -icol : 0; - int rpad = icol + icols_ > dilated_in_col_dim - ? icol + icols_ - dilated_in_col_dim - : 0; - int upad = irow < 0 ? -irow : 0; - int dpad = irow + irows_ > dilated_in_row_dim - ? irow + irows_ - dilated_in_row_dim - : 0; - - if (input_dilated) { - lpad += lpad == 0 && icol % 2 != 0; - rpad += rpad == 0 && (icol + icols_) % 2 != 1; - upad += upad == 0 && irow % 2 != 0; - dpad += dpad == 0 && (irow + irows_) % 2 != 1; - } - - int krow_ = krow; - int kcol_ = kcol; - if (wrot180) { - krow_ = kernel_dim - krow - krows_; - kcol_ = kernel_dim - kcol - kcols_; - } - - const elem_t *weights_slice = - weights + - (krow_ * kernel_dim * in_channels + kcol_ * in_channels + - kch) * - weight_stride + - poch; - if (trans_weight_1203) { - weights_slice = weights + - (kch * kernel_dim * kernel_dim + - krow_ * kernel_dim + kcol_) * - out_channels + - poch; - } else if (trans_weight_0132) { - weights_slice = weights + - (krow_ * kernel_dim * out_channels + - kcol_ * out_channels + poch) * - in_channels + - kch; - } - - const elem_t *in = - input + - (b * in_row_dim * in_col_dim + - ((irow + upad) >> input_dilated) * in_col_dim + - ((icol + lpad) >> input_dilated)) * - in_stride + - kch; - if (trans_input_3120) { - in = input + - (kch * in_row_dim * in_col_dim + - ((irow + upad) >> input_dilated) * in_col_dim + - ((icol + lpad) >> input_dilated)) * - batch_size + - b; - } - if (b_reuse && (pocol + (porow - porow_start) + b > 0)) - weights_slice = NULL; - if (a_reuse && (poch > 0)) - in = NULL; - // printf("a_reuse: %d, b_reuse: %d, a_spad_id: %d, b_spad_id: - // %d, in: %llu, weight: %llu \n", a_reuse, b_reuse, a_spad_id, - // b_spad_id, in, weights_slice); - - sp_tiled_conv( - batch_size, in_row_dim, in_col_dim, in_channels, - out_channels, out_row_dim, out_col_dim, pool_out_row_dim, - pool_out_col_dim, - - stride, padding, kernel_dim, kernel_dilation, in_stride, - weight_stride, out_stride, - - pool_size, pool_stride, pool_padding, - - batches_, porows_, pocols_, pochs_, krows_, kcols_, kchs_, - - lpad, rpad, upad, dpad, plpad, prpad, pupad, pdpad, - - in, weights_slice, out, bias_, - - act, scale, - - wrot180, trans_output_1203, trans_input_3120, - trans_weight_1203, trans_weight_0132, - - no_bias, no_pool, downsample, input_dilated, false, - a_spad_id, b_spad_id); - } - } - } - } - } - } - } -} - -static void tiled_conv_dw(int batch_size, int in_row_dim, int in_col_dim, - int channels, int out_row_dim, int out_col_dim, - int stride, int padding, int kernel_dim, - - int batches, int porows, int pocols, int krows, - int kcols, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale, int pool_size, - int pool_stride, int pool_padding, - - enum tiled_matmul_type_t tiled_conv_type) { - - if (tiled_conv_type == CPU) { - if (pool_size == 1 && pool_stride == 1 && pool_padding == 0) { - pool_stride = 0; - } - - conv_dw_cpu(batch_size, in_row_dim, in_col_dim, channels, out_row_dim, - out_col_dim, stride, padding, kernel_dim, input, weights, bias, - output, act, scale, pool_size, pool_stride, pool_padding); - return; - } else if (tiled_conv_type == OS) { - printf("Gemmini convs do not currently support OS\n"); - exit(1); - } - - // TODO move everything below this into a tiled_conv_outer function to match - // the tiled_matmul function - - bool no_bias = false; - if (bias == NULL) { - bias = (acc_t *)1; - no_bias = true; - } - - bool no_pool = pool_stride == 0; - if (no_pool) { - pool_size = 1; - pool_stride = 1; - pool_padding = 0; - } - -#ifdef GEMMINI_ASSERTIONS - { - // const int orows = porows * pool_stride + pool_size - 1; - // const int ocols = pocols * pool_stride + pool_size - 1; - - // Check that data will fit in scratchpad - const int spad_rows = tiled_conv_total_spad_rows( - false, stride, 1, 1, false, false, false, batches, porows, pocols, 1, - krows, kcols, 1, pool_size, pool_stride); - const int acc_rows = tiled_conv_total_spad_rows( - true, stride, 1, 1, false, false, false, batches, porows, pocols, 1, - krows, kcols, 1, pool_size, pool_stride); - - if (spad_rows > BANK_NUM * BANK_ROWS / 2) { - printf("not enough scratchpad space to store inputs and weights, %d\n", - spad_rows); - exit(1); - } - if (acc_rows > ACC_ROWS / 2) { - printf("not enough accumulator space to store outputs\n"); - exit(1); - } - if (kernel_dim <= padding) { - printf("kernel_dim must be larger than padding\n"); - exit(1); - } - } -#endif - - const size_t st_dram_stride = channels * sizeof(elem_t); - gemmini_extended_config_st(st_dram_stride, act, scale); - - gemmini_extended3_config_ex(WEIGHT_STATIONARY, 0, 0, 0, 1, stride, false, - false, false); - - const int pool_out_row_dim = - (out_row_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int pool_out_col_dim = - (out_col_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - - for (int b = 0; b < batch_size; b += batches) { - for (int porow = 0; porow < pool_out_row_dim; porow += porows) { - const int orow = porow * pool_stride - pool_padding; - - for (int pocol = 0; pocol < pool_out_col_dim; pocol += pocols) { - const int ocol = pocol * pool_stride - pool_padding; - - for (int ch = 0; ch < channels; ch++) { - for (int krow = 0; krow < kernel_dim; krow += krows) { - const int orow_floored = orow < 0 ? 0 : orow; - int irow = orow_floored * stride + krow - padding; - - for (int kcol = 0; kcol < kernel_dim; kcol += kcols) { - const int ocol_floored = ocol < 0 ? 0 : ocol; - int icol = ocol_floored * stride + kcol - padding; - - elem_t *out = output + - (b * pool_out_row_dim * pool_out_col_dim + - porow * pool_out_col_dim + pocol) * - channels + - ch; - - if (krow + krows < kernel_dim || kcol + kcols < kernel_dim) { - out = NULL; - } - - const acc_t *bias_ = bias + ch; - if (krow > 0 || kcol > 0) { - bias_ = NULL; - } - - const int batches_ = - batch_size - b > batches ? batches : batch_size - b; - const int porows_ = pool_out_row_dim - porow > porows - ? porows - : pool_out_row_dim - porow; - const int pocols_ = pool_out_col_dim - pocol > pocols - ? pocols - : pool_out_col_dim - pocol; - const int krows_ = - kernel_dim - krow > krows ? krows : kernel_dim - krow; - const int kcols_ = - kernel_dim - kcol > kcols ? kcols : kernel_dim - kcol; - - const int ocols_ = pocols_ * pool_stride + pool_size - 1; - const int orows_ = porows_ * pool_stride + pool_size - 1; - - const int plpad = ocol < 0 ? -ocol : 0; - const int prpad = - ocol + ocols_ > out_col_dim ? ocol + ocols_ - out_col_dim : 0; - const int pupad = orow < 0 ? -orow : 0; - const int pdpad = - orow + orows_ > out_row_dim ? orow + orows_ - out_row_dim : 0; - - const int icols_ = (ocols_ - plpad - prpad) * stride + kcols_ - 1; - const int irows_ = (orows_ - pupad - pdpad) * stride + krows_ - 1; - - int lpad = icol < 0 ? -icol : 0; - int rpad = - icol + icols_ > in_col_dim ? icol + icols_ - in_col_dim : 0; - int upad = irow < 0 ? -irow : 0; - int dpad = - irow + irows_ > in_row_dim ? irow + irows_ - in_row_dim : 0; - - const elem_t *weights_slice = - weights + (ch * kernel_dim + krow) * kernel_dim + kcol; - - const elem_t *in = input + - (b * in_row_dim * in_col_dim + - (irow + upad) * in_col_dim + (icol + lpad)) * - channels + - ch; - - sp_tiled_conv( - batch_size, in_row_dim, in_col_dim, channels, channels, - out_row_dim, out_col_dim, pool_out_row_dim, pool_out_col_dim, - - stride, padding, kernel_dim, 1, channels, 1, channels, - - pool_size, pool_stride, pool_padding, - - batches_, porows_, pocols_, 1, krows_, kcols_, 1, - - lpad, rpad, upad, dpad, plpad, prpad, pupad, pdpad, - - in, weights_slice, out, bias_, - - act, scale, - - false, false, false, false, false, - - no_bias, no_pool, false, false, true, 0, 0); - } - } - } - } - } - } -} - -// need to specify each operand/output's stride -// stride only for trans == false, wrot == false -static void tiled_conv_stride_auto( - int batch_size, int in_row_dim, int in_col_dim, int in_channels, - int out_channels, int out_row_dim, int out_col_dim, int stride, - int input_dilation, int kernel_dilation, int padding, int kernel_dim, - int in_stride, int weight_stride, - int out_stride, // specify in/output's stride - bool wrot180, bool trans_output_1203, bool trans_input_3120, - bool trans_weight_1203, bool trans_weight_0132, - - const elem_t *input, const elem_t *weights, const acc_t *bias, - elem_t *output, - - int act, acc_scale_t scale, int pool_size, int pool_stride, - int pool_padding, - - enum tiled_matmul_type_t tiled_conv_type) { - - const bool no_pool = pool_stride == 0; - if (no_pool) { - pool_size = 1; - pool_stride = 1; - pool_padding = 0; - } - - const int pool_out_row_dim = - (out_row_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int pool_out_col_dim = - (out_col_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - - const bool downsample = stride == 2 && kernel_dim == 1 && padding == 0 && - no_pool && in_row_dim % 2 == 0 && in_col_dim % 2 == 0; - - // Tile convolution params - - // int args[] = {batch_size, porows, pocols, pochs, krows, kcols, kchs}; - int args[] = {batch_size, pool_out_row_dim, pool_out_col_dim, out_channels, - kernel_dim, kernel_dim, in_channels}; - const int max_args[] = {batch_size, pool_out_row_dim, pool_out_col_dim, - out_channels, kernel_dim, kernel_dim, - in_channels}; - - const int orows_idx = 1; - const int ocols_idx = 2; - const int out_channels_idx = 3; - const int in_channels_idx = 6; - - // We divide by 2 for the sake of double-buffering - const int max_spad_rows = (BANK_NUM * BANK_ROWS / 2); - const int max_acc_rows = (ACC_ROWS / 2); - - int spad_rows = tiled_conv_total_spad_rows( - false, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args[0], args[1], args[2], args[3], - args[4], args[5], args[6], pool_size, pool_stride); - int acc_rows = tiled_conv_total_spad_rows( - true, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args[0], args[1], args[2], args[3], - args[4], args[5], args[6], pool_size, pool_stride); - - while (spad_rows > max_spad_rows || acc_rows > max_acc_rows) { - int max_val = -1; - int max_idx = -1; - - for (size_t i = 0; i < sizeof(args) / sizeof(args[0]); i++) { - // We avoid reducing ocols when possible to keep the spatial array fully - // utilized - if (!(i == ocols_idx && args[i] <= DIM && args[orows_idx] > 1) && - args[i] > max_val) { - max_val = args[i]; - max_idx = i; - } - } - - if (max_idx == out_channels_idx || max_idx == in_channels_idx) { - // For input and output channels, there's no point in subtracting by just - // one - if (args[max_idx] % DIM != 0) { - args[max_idx] = (args[max_idx] / DIM) * DIM; - } else { - args[max_idx] -= DIM; - } - args[max_idx] = args[max_idx] == 0 ? 1 : args[max_idx]; - } else { - args[max_idx]--; - } - - spad_rows = tiled_conv_total_spad_rows( - false, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args[0], args[1], args[2], args[3], - args[4], args[5], args[6], pool_size, pool_stride); - acc_rows = tiled_conv_total_spad_rows( - true, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args[0], args[1], args[2], args[3], - args[4], args[5], args[6], pool_size, pool_stride); - } - - // Check if we can increase ocols - bool not_increased = false; - while (!not_increased) { - not_increased = true; - - int args_candidate[] = {args[0], args[1], args[2], args[3], - args[4], args[5], args[6]}; - args_candidate[ocols_idx]++; - - if (args_candidate[ocols_idx] > max_args[ocols_idx]) - continue; - - spad_rows = tiled_conv_total_spad_rows( - false, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - acc_rows = tiled_conv_total_spad_rows( - true, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - - if (spad_rows <= max_spad_rows && acc_rows <= max_acc_rows) { - args[ocols_idx] = args_candidate[ocols_idx]; - not_increased = false; - } - } - - // Check if there are any parameters that we can currently still increase - bool nothing_increased = false; - while (!nothing_increased) { - nothing_increased = true; - - for (size_t i = 0; i < sizeof(args) / sizeof(args[0]); i++) { - int args_candidate[] = {args[0], args[1], args[2], args[3], - args[4], args[5], args[6]}; - args_candidate[i]++; - - if (args_candidate[i] > max_args[i]) - continue; - - spad_rows = tiled_conv_total_spad_rows( - false, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - acc_rows = tiled_conv_total_spad_rows( - true, stride, input_dilation, kernel_dilation, downsample, - trans_weight_0132, trans_input_3120, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - - if (spad_rows <= max_spad_rows && acc_rows <= max_acc_rows) { - args[i] = args_candidate[i]; - nothing_increased = false; - } - } - } - - const int batches = args[0]; - const int orows = args[1]; - const int ocols = args[2]; - const int ochs = args[3]; - const int krows = args[4]; - const int kcols = args[5]; - const int kchs = args[6]; - - /* - spad_rows = tiled_conv_total_spad_rows(false, - stride, input_dilation, kernel_dilation, downsample, trans_weight_0132, - trans_input_3120, args[0], args[1], args[2], args[3], args[4], args[5], - args[6], pool_size, pool_stride); acc_rows = tiled_conv_total_spad_rows(true, - stride, input_dilation, kernel_dilation, downsample, trans_weight_0132, - trans_input_3120, args[0], args[1], args[2], args[3], args[4], args[5], - args[6], pool_size, pool_stride); - */ - -#ifdef PRINT_TILE -#if PRINT_TILE - printf("batches = %d\n", batches); - printf("orows = %d\n", orows); - printf("ocols = %d\n", ocols); - printf("ochs = %d\n", ochs); - printf("krows = %d\n", krows); - printf("kcols = %d\n", kcols); - printf("kchs = %d\n\n", kchs); - - printf("total spad_rows reserved: %d\n", spad_rows); - printf("total acc_rows reserved: %d\n\n", acc_rows); - - printf("scratchpad row utilization: %d%%\n", - (spad_rows * 100) / max_spad_rows); - printf("accumulator row utilization: %d%%\n\n", - (acc_rows * 100) / max_acc_rows); - - printf("inner matmul size: i=%d, j=%d, k=%d\n\n", ocols, ochs, kchs); -#endif -#endif - - tiled_conv(batch_size, in_row_dim, in_col_dim, in_channels, out_channels, - out_row_dim, out_col_dim, stride, input_dilation, kernel_dilation, - padding, kernel_dim, in_stride, weight_stride, out_stride, wrot180, - trans_output_1203, trans_input_3120, trans_weight_1203, - trans_weight_0132, - - batches, orows, ocols, ochs, krows, kcols, kchs, - - input, weights, bias, output, - - act, scale, pool_size, no_pool ? 0 : pool_stride, pool_padding, - - tiled_conv_type); -} - -static void tiled_conv_auto(int batch_size, int in_row_dim, int in_col_dim, - int in_channels, int out_channels, int out_row_dim, - int out_col_dim, int stride, int input_dilation, - int kernel_dilation, int padding, int kernel_dim, - bool wrot180, bool trans_output_1203, - bool trans_input_3120, bool trans_weight_1203, - bool trans_weight_0132, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale, int pool_size, - int pool_stride, int pool_padding, - - enum tiled_matmul_type_t tiled_conv_type) { - - int in_stride = in_channels; - int out_stride = out_channels; - int weight_stride = out_channels; - tiled_conv_stride_auto( - batch_size, in_row_dim, in_col_dim, in_channels, out_channels, - out_row_dim, out_col_dim, stride, input_dilation, kernel_dilation, - padding, kernel_dim, in_stride, weight_stride, out_stride, wrot180, - trans_output_1203, trans_input_3120, trans_weight_1203, trans_weight_0132, - - input, weights, bias, output, - - act, scale, pool_size, pool_stride, pool_padding, tiled_conv_type); -} - -// This function is for a convolution with kernel_dim=1, stride==2, padding=0, -// and no pooling -static void tiled_conv_downsample(int batch_size, int in_row_dim, - int in_col_dim, int in_channels, - int out_channels, int out_row_dim, - int out_col_dim, int in_stride, - int weight_stride, int out_stride, - - const elem_t *input, const elem_t *weights, - const acc_t *bias, elem_t *output, - - int act, acc_scale_t scale, - - enum tiled_matmul_type_t tiled_conv_type) { - - // Rectangular dimensions for this function are currently not supported - if (in_row_dim != in_col_dim || out_row_dim != out_col_dim) { - printf("Rectangular convolutions for tiled_conv_downsample are currently " - "not supported.\n"); - exit(1); - } - - const int in_dim = in_row_dim; - const int out_dim = out_row_dim; - - const int stride = 2; - - for (int b = 0; b < batch_size; b++) { - for (int irow = 0; irow < in_row_dim; irow += stride) { - const int orow = irow / stride; - - const int I = in_col_dim / stride; // number of columns in row - const int J = out_channels; - const int K = in_channels; - - const elem_t *A = input + (b * in_dim + irow) * in_dim * in_stride; - const elem_t *B = weights; - const acc_t *D = bias; - elem_t *C = output + (b * out_dim + orow) * out_dim * out_stride; - - const int A_stride = in_stride * 2; - const int B_stride = weight_stride; - const int D_stride = out_stride; - const int C_stride = out_stride; - - tiled_matmul_auto(I, J, K, A, B, (void *)D, (void *)C, A_stride, B_stride, - D_stride, C_stride, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, act, scale, 0, - true, false, false, false, false, 0, tiled_conv_type); - } - } -} - -// for mobilenet's depthwise convs -static void tiled_conv_dw_auto(int batch_size, int in_row_dim, int in_col_dim, - int channels, int out_row_dim, int out_col_dim, - int stride, int padding, int kernel_dim, - - elem_t *input, elem_t *weights, acc_t *bias, - elem_t *output, - - int act, acc_scale_t scale, int pool_size, - int pool_stride, int pool_padding, - - enum tiled_matmul_type_t tiled_conv_type) { - - const bool no_pool = pool_stride == 0; - if (no_pool) { - pool_size = 1; - pool_stride = 1; - pool_padding = 0; - } - - const int pool_out_row_dim = - (out_row_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - const int pool_out_col_dim = - (out_col_dim + 2 * pool_padding - pool_size) / pool_stride + 1; - - // Tile convolution params - - // int args[] = {batch_size, porows, pocols, pochs, krows, kcols, kchs}; - int args[] = {batch_size, pool_out_row_dim, pool_out_col_dim, - 1, kernel_dim, kernel_dim, - 1}; - const int max_args[] = {batch_size, pool_out_row_dim, pool_out_col_dim, - 1, kernel_dim, kernel_dim, - 1}; - - const int orows_idx = 1; - const int ocols_idx = 2; - const int out_channels_idx = 3; - - // We divide by 2 for the sake of double-buffering - const int max_spad_rows = (BANK_NUM * BANK_ROWS / 2); - const int max_acc_rows = (ACC_ROWS / 2); - - int spad_rows = tiled_conv_total_spad_rows( - false, stride, 1, 1, false, false, false, args[0], args[1], args[2], - args[3], args[4], args[5], args[6], pool_size, pool_stride); - int acc_rows = tiled_conv_total_spad_rows( - true, stride, 1, 1, false, false, false, args[0], args[1], args[2], - args[3], args[4], args[5], args[6], pool_size, pool_stride); - - while (spad_rows > max_spad_rows || acc_rows > max_acc_rows) { - int max_val = -1; - int max_idx = -1; - - for (size_t i = 0; i < sizeof(args) / sizeof(args[0]); i++) { - // We avoid reducing ocols when possible to keep the spatial array fully - // utilized - if (!(i == ocols_idx && args[i] <= DIM && args[orows_idx] > 1) && - args[i] > max_val) { - max_val = args[i]; - max_idx = i; - } - } - - if (max_idx == out_channels_idx) { - // For input and output channels, there's no point in subtracting by just - // one - if (args[max_idx] % DIM != 0) { - args[max_idx] = (args[max_idx] / DIM) * DIM; - } else { - args[max_idx] -= DIM; - } - args[max_idx] = args[max_idx] == 0 ? 1 : args[max_idx]; - } else { - args[max_idx]--; - } - - spad_rows = tiled_conv_total_spad_rows( - false, stride, 1, 1, false, false, false, args[0], args[1], args[2], - args[3], args[4], args[5], args[6], pool_size, pool_stride); - acc_rows = tiled_conv_total_spad_rows( - true, stride, 1, 1, false, false, false, args[0], args[1], args[2], - args[3], args[4], args[5], args[6], pool_size, pool_stride); - } - - // Check if we can increase ocols - bool not_increased = false; - while (!not_increased) { - not_increased = true; - - int args_candidate[] = {args[0], args[1], args[2], args[3], - args[4], args[5], args[6]}; - args_candidate[ocols_idx]++; - - if (args_candidate[ocols_idx] > max_args[ocols_idx]) - continue; - - spad_rows = tiled_conv_total_spad_rows( - false, stride, 1, 1, false, false, false, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - acc_rows = tiled_conv_total_spad_rows( - true, stride, 1, 1, false, false, false, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - - if (spad_rows <= max_spad_rows && acc_rows <= max_acc_rows) { - args[ocols_idx] = args_candidate[ocols_idx]; - not_increased = false; - } - } - - // Check if there are any parameters that we can currently still increase - bool nothing_increased = false; - while (!nothing_increased) { - nothing_increased = true; - - for (size_t i = 0; i < sizeof(args) / sizeof(args[0]); i++) { - int args_candidate[] = {args[0], args[1], args[2], args[3], - args[4], args[5], args[6]}; - args_candidate[i]++; - - if (args_candidate[i] > max_args[i]) - continue; - - spad_rows = tiled_conv_total_spad_rows( - false, stride, 1, 1, false, false, false, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - acc_rows = tiled_conv_total_spad_rows( - true, stride, 1, 1, false, false, false, args_candidate[0], - args_candidate[1], args_candidate[2], args_candidate[3], - args_candidate[4], args_candidate[5], args_candidate[6], pool_size, - pool_stride); - - if (spad_rows <= max_spad_rows && acc_rows <= max_acc_rows) { - args[i] = args_candidate[i]; - nothing_increased = false; - } - } - } - - const int batches = args[0]; - const int orows = args[1]; - const int ocols = args[2]; - const int ochs = 1; // args[3]; - const int krows = args[4]; - const int kcols = args[5]; - const int kchs = 1; // args[6]; - - /* - spad_rows = tiled_conv_total_spad_rows(false, - stride, 1, 1, false, false, false, - args[0], args[1], args[2], args[3], args[4], args[5], args[6], pool_size, - pool_stride); acc_rows = tiled_conv_total_spad_rows(true, stride, 1, 1, false, - false, false, args[0], args[1], args[2], args[3], args[4], args[5], args[6], - pool_size, pool_stride); - - printf("batches = %d\n", batches); - printf("orows = %d\n", orows); - printf("ocols = %d\n", ocols); - printf("ochs = %d\n", ochs); - printf("krows = %d\n", krows); - printf("kcols = %d\n", kcols); - printf("kchs = %d\n\n", kchs); - - printf("total spad_rows reserved: %d\n", spad_rows); - printf("total acc_rows reserved: %d\n\n", acc_rows); - - printf("scratchpad row utilization: %d%%\n", (spad_rows*100) / max_spad_rows); - printf("accumulator row utilization: %d%%\n\n", (acc_rows*100) / - max_acc_rows); - - printf("inner matmul size: i=%d, j=%d, k=%d\n\n", ocols, ochs, kchs); - */ - - tiled_conv_dw(batch_size, in_row_dim, in_col_dim, channels, out_row_dim, - out_col_dim, stride, padding, kernel_dim, - - batches, orows, ocols, krows, kcols, - - input, weights, bias, output, - - act, scale, pool_size, no_pool ? 0 : pool_stride, pool_padding, - - tiled_conv_type); -} - -static void resadd_cpu(const size_t I, const size_t J, const size_t stride, - const scale_t A_scale, const scale_t B_scale, - const acc_scale_t C_scale, const elem_t *A, - const elem_t *B, elem_t *C, bool relu) { - - const int minimum = relu ? 0 : elem_t_min; - - for (size_t i = 0; i < I; i++) { - for (size_t j = 0; j < J; j++) { - const elem_t *a = A + i * stride + j; - const elem_t *b = B + i * stride + j; - elem_t *c = C + i * stride + j; - - acc_t result = MVIN_SCALE(*a, A_scale) + MVIN_SCALE(*b, B_scale); - result = ACC_SCALE(result, C_scale); - result = result > elem_t_max ? elem_t_max - : (result < minimum ? minimum : result); - - *c = result; - } - } -} - -static void sp_tiled_resadd(const size_t I, const size_t J, - const scale_t A_scale, const scale_t B_scale, - const elem_t *A, const elem_t *B, elem_t *C, - size_t A_row_stride, size_t B_row_stride, - size_t C_row_stride, bool relu) { - - int pad_I = ((I % DIM) == 0) ? 0 : DIM - (I % DIM); - int pad_J = ((J % DIM) == 0) ? 0 : DIM - (J % DIM); - int tile_I = (I % DIM == 0) ? (int)(I / DIM) : (int)(I / DIM) + 1; - int tile_J = (J % DIM == 0) ? (int)(J / DIM) : (int)(J / DIM) + 1; - // printf("pad I: %d, pad_J: %d, tile_I: %d, tile_J: %d\n", pad_I, pad_J, - // tile_I, tile_J); - gemmini_loop_ws(tile_I, tile_J, 0, pad_I, pad_J, 0, A, B, NULL, C, - A_row_stride, B_row_stride, 0, C_row_stride, false, false, - false, false, false, relu, 0, 0, true); - /* - // Use the new mvin2 command to overlap mvin A, mvin B, and mvout C - - size_t blocks = (J/DIM + (J % DIM != 0)); - if (blocks > MAX_BLOCK_LEN) blocks = MAX_BLOCK_LEN; - - const uint32_t D_sp_addr_start = 1 << (ADDR_LEN-1); - const uint32_t C_sp_addr_start = 3 << (ADDR_LEN-2); - - const size_t rounded_up_J = (J / DIM + (J % DIM != 0)) * DIM; - - // Mvin A - // printf("Mving A\n"); - for (size_t i = 0; i < I; i += DIM) { - for (size_t j = 0; j < J; j += blocks * DIM) { - const size_t cols = j + blocks*DIM <= J ? blocks*DIM : J-j; - const size_t rows = i + DIM <= I ? DIM : I-i; - - const elem_t * const A_dram_addr = A + i * A_row_stride + j; - const uint32_t A_sp_addr = D_sp_addr_start + i * (rounded_up_J/DIM) + - j; - - gemmini_extended_mvin(A_dram_addr, A_sp_addr, cols, rows); - } - } - - // Mvin B - printf("Mving B\n"); - for (size_t i = 0; i < I; i += DIM) { - for (size_t j = 0; j < J; j += blocks * DIM) { - const size_t cols = j + blocks*DIM <= J ? blocks*DIM : J-j; - const size_t rows = i + DIM <= I ? DIM : I-i; - - const elem_t * const B_dram_addr = B + i * B_row_stride + j; - const uint32_t B_sp_addr = C_sp_addr_start + i * (rounded_up_J/DIM) + - j; gemmini_extended_mvin2(B_dram_addr, B_sp_addr, cols, rows); - } - } - - // Mvout C from accumulator - // printf("Mvout C from accumulator\n"); - for (size_t i = 0; i < I; i += DIM) { - for (size_t j = 0; j < J; j += blocks * DIM) { - const size_t cols = j + blocks*DIM <= J ? blocks*DIM : J-j; - const size_t rows = i + DIM <= I ? DIM : I-i; - - elem_t * const C_dram_addr = C + i * C_row_stride + j; - const uint32_t C_sp_addr = D_sp_addr_start + i * (rounded_up_J/DIM) + - j; gemmini_extended_mvout(C_dram_addr, C_sp_addr, cols, rows); - } - } - */ -} - -// Compute MVIN_SCALE(A, A_scale) + MVIN_SCALE(B, B_scale) = C -static void tiled_resadd(const size_t I, const size_t J, const size_t stride, - const size_t tile_I, const size_t tile_J, - const scale_t A_scale, const scale_t B_scale, - const acc_scale_t C_scale, const elem_t *A, - const elem_t *B, elem_t *C, bool relu, - enum tiled_matmul_type_t matadd_type) { - - gemmini_extended_config_st(stride * sizeof(elem_t), - relu ? RELU : NO_ACTIVATION, C_scale); - gemmini_config_ex(WS, 0, 0); - - gemmini_extended4_config_ld(stride * sizeof(elem_t), A_scale, true, DIM, 0); - gemmini_extended4_config_ld(stride * sizeof(elem_t), B_scale, true, DIM, 1); - - for (size_t i = 0; i < I; i += tile_I) { - for (size_t j = 0; j < J; j += tile_J) { - const size_t I_tile = i + tile_I <= I ? tile_I : I - i; - const size_t J_tile = j + tile_J <= J ? tile_J : J - j; - - const elem_t *a = A + i * stride + j; - const elem_t *b = B + i * stride + j; - elem_t *c = C + i * stride + j; - - sp_tiled_resadd(I_tile, J_tile, A_scale, B_scale, a, b, c, stride, stride, - stride, relu); - } - } - - gemmini_fence(); -} - -// Compute (A >> A_shift) + B = C -// specify stride -static void tiled_resadd_stride_auto(const size_t I, const size_t J, - const scale_t A_scale, - const scale_t B_scale, - const acc_scale_t C_scale, - const size_t stride, const elem_t *A, - const elem_t *B, elem_t *C, bool relu, - enum tiled_matmul_type_t matadd_type) { - - if (matadd_type == CPU) { - resadd_cpu(I, J, stride, A_scale, B_scale, C_scale, A, B, C, relu); - return; - } - - size_t tile_I = I, tile_J = J; - - // size_t total_spad_rows = 2 * (tile_I / DIM + (tile_I % DIM != 0))*DIM * - // (tile_J / DIM + (tile_J % DIM != 0)); - size_t total_acc_rows = (tile_I / DIM + (tile_I % DIM != 0)) * DIM * - (tile_J / DIM + (tile_J % DIM != 0)); - - // TODO this is a very inefficient way of doing this... - while (total_acc_rows > ACC_ROWS / 2) { - // if(tile_J > MAX_BLOCK_LEN * DIM) - // tile_J = MAX_BLOCK_LEN * DIM; - // else - if (tile_I >= tile_J || tile_J <= DIM) - tile_I /= 2; - else - tile_J -= DIM; - - total_acc_rows = (tile_I / DIM + (tile_I % DIM != 0)) * DIM * - (tile_J / DIM + (tile_J % DIM != 0)); - } - - // printf("tile_I: %llu\n", tile_I); - // printf("tile_J: %llu\n", tile_J); - - if (matadd_type == WS) { - tiled_resadd(I, J, stride, tile_I, tile_J, A_scale, B_scale, C_scale, A, B, - C, relu, matadd_type); - } else { - printf("Unsupported type\n"); - exit(1); - } -} - -static void tiled_resadd_auto(const size_t I, const size_t J, - const scale_t A_scale, const scale_t B_scale, - const acc_scale_t C_scale, const elem_t *A, - const elem_t *B, elem_t *C, bool relu, - enum tiled_matmul_type_t matadd_type) { - tiled_resadd_stride_auto(I, J, A_scale, B_scale, C_scale, J, A, B, C, relu, - matadd_type); -} - -static void global_average_cpu(const elem_t *input, elem_t *output, int batches, - int channels, int dim) { - const int count = dim * dim; - - for (int batch = 0; batch < batches; batch++) { - for (int channel = 0; channel < channels; channel++) { - acc_t sum = 0; - for (int row = 0; row < dim; row++) { - for (int col = 0; col < dim; col++) { - size_t pixel = batch * dim * dim + row * dim + col; - - sum += input[pixel * channels + channel]; - } - } - -#ifdef ELEM_T_IS_FLOAT - output[batch * channels + channel] = sum / count; -#else - output[batch * channels + channel] = (sum + count / 2) / count; -#endif - } - } -} - -static void sp_tiled_global_average(const elem_t *input, elem_t *output, - int batches, int channels, int dim, - int channel_tile_size) { - const uint32_t C_acc_addr_start = ((uint32_t)1 << 31); - - size_t blocks = channel_tile_size / DIM + (channel_tile_size % DIM != 0); - if (blocks > MAX_BLOCK_LEN) - blocks = MAX_BLOCK_LEN; - - for (int channel = 0; channel < channel_tile_size; channel += blocks * DIM) { - for (int row = 0; row < dim; row++) { - for (int col = 0; col < dim; col++) { - const elem_t *in = input + (row * dim + col) * channels + channel; - - const uint32_t acc_addr_start = - C_acc_addr_start | ((row != 0 || col != 0) << 30); - - const uint32_t acc_addr = acc_addr_start + channel / DIM; - - const size_t cols = channel + blocks * DIM <= channel_tile_size - ? blocks * DIM - : channel_tile_size - channel; - - const size_t rows = 1; - - gemmini_extended_mvin(in, acc_addr, cols, rows); - } - } - } - - for (int channel = 0; channel < channel_tile_size; channel += DIM) { - elem_t *out = output + channel; - - const uint32_t acc_addr = C_acc_addr_start + channel / DIM; - - const size_t cols = - channel + DIM <= channel_tile_size ? DIM : channel_tile_size - channel; - - const size_t rows = - 1; // TODO we should move out more than just one row here - - gemmini_extended_mvout(out, acc_addr, cols, rows); - } -} - -static void tiled_global_average(const elem_t *input, elem_t *output, - int batches, int channels, int dim, - int channel_tile_size) { - - gemmini_extended4_config_ld(DIM * sizeof(elem_t), MVIN_SCALE_IDENTITY, true, - 1, 0); - gemmini_config_ex(0, NO_ACTIVATION, 0); - gemmini_extended_config_st(0, NO_ACTIVATION, 1.0 / (dim * dim)); - - for (int batch = 0; batch < batches; batch++) { - for (int channel = 0; channel < channels; channel += channel_tile_size) { - const int tile_size = channel + channel_tile_size <= channels - ? channel_tile_size - : channels - channel; - - sp_tiled_global_average(input + batch * dim * dim * channels + channel, - output + batch * channels + channel, batches, - channels, dim, tile_size); - } - } -} - -static void tiled_global_average_auto(const elem_t *input, elem_t *output, - int batches, int channels, int dim, - enum tiled_matmul_type_t type) { - if (type == CPU) { - return global_average_cpu(input, output, batches, channels, dim); - } - - int channel_tile_size = channels; - - int acc_rows = channel_tile_size / DIM + (channel_tile_size % DIM != 0); - while (acc_rows > ACC_ROWS) { - channel_tile_size--; - acc_rows = channel_tile_size / DIM + (channel_tile_size % DIM != 0); - } - - tiled_global_average(input, output, batches, channels, dim, - channel_tile_size); -} - -static void sp_tiled_norm(const size_t I, const size_t J, const acc_t *in, - elem_t *out, size_t A_row_stride, size_t C_row_stride, - int act) { -#ifdef HAS_NORMALIZATIONS - size_t A_blocks = (J / DIM + (J % DIM != 0)); - if (A_blocks > MAX_BLOCK_LEN_ACC) - A_blocks = MAX_BLOCK_LEN_ACC; - size_t C_blocks = (J / DIM + (J % DIM != 0)); - if (C_blocks > MAX_BLOCK_LEN) - C_blocks = MAX_BLOCK_LEN; - - const uint32_t D_sp_addr_start = 1 << (ADDR_LEN - 1); - const uint32_t C_sp_addr_start = 3 << (ADDR_LEN - 2); - - const size_t rounded_up_J = (J / DIM + (J % DIM != 0)) * DIM; - - for (size_t i = 0; i < I; i += DIM) { - // Mvin - for (size_t j = 0; j < J; j += A_blocks * DIM) { - const size_t cols = j + A_blocks * DIM <= J ? A_blocks * DIM : J - j; - const size_t rows = i + DIM <= I ? DIM : I - i; - - const acc_t *const A_dram_addr = in + i * A_row_stride + j; - const uint32_t A_sp_addr = D_sp_addr_start + i * (rounded_up_J / DIM) + j; - - gemmini_extended_mvin(A_dram_addr, A_sp_addr, cols, rows); - } - - // Mvout - if (act == LAYERNORM) { - uint32_t norm_cmds[][2] = {{1, 2}, {3, 4}, {0, 0}}; - const int norm_cmds_size = sizeof(norm_cmds) / sizeof(norm_cmds[0]); - const size_t rows = I - i < DIM ? I - i : DIM; - for (size_t row = 0; row < rows; row += NORM_STAT_IDS) { - const size_t stat_ids = - rows - row > NORM_STAT_IDS ? NORM_STAT_IDS : rows - row; - for (int cmd = 0; cmd < norm_cmds_size; cmd++) { - for (size_t stat_id = 0; stat_id < stat_ids; stat_id++) { - gemmini_config_norm(0, 0, 0, 0, stat_id, 0, 0); - const size_t r = row + stat_id; - for (size_t jj = 0; jj < J; jj += C_blocks * DIM) { - uint32_t norm_C_sp_addr = - C_sp_addr_start + i * (rounded_up_J / DIM) + jj + r; - if (jj + C_blocks * DIM >= J) { - norm_C_sp_addr |= (norm_cmds[cmd][1] - << 26); // Final mean/inv-std-dev calculation - } else { - norm_C_sp_addr |= - (norm_cmds[cmd][0] << 26); // Accumulate sum/variance - } - void *const C_dram_addr = - (int8_t *)out + (i * C_row_stride + jj) * sizeof(elem_t) + - r * C_row_stride * sizeof(elem_t); - const size_t cols = - J - jj < C_blocks * DIM ? J - jj : C_blocks * DIM; - gemmini_extended_mvout(C_dram_addr, norm_C_sp_addr, cols, 1); - } - } - } - } - } else if (act == SOFTMAX) { - uint32_t norm_cmds[][2] = {{5, 5}, {6, 7}, {0, 0}}; - const int norm_cmds_size = sizeof(norm_cmds) / sizeof(norm_cmds[0]); - const size_t rows = I - i < DIM ? I - i : DIM; - for (size_t row = 0; row < rows; row += NORM_STAT_IDS) { - const size_t stat_ids = - rows - row > NORM_STAT_IDS ? NORM_STAT_IDS : rows - row; - for (int cmd = 0; cmd < norm_cmds_size; cmd++) { - for (size_t stat_id = 0; stat_id < stat_ids; stat_id++) { - // set stat id only - gemmini_config_norm(0, 0, 1, 0, stat_id, 0, 0); - const size_t r = row + stat_id; - for (size_t jj = 0; jj < J; jj += C_blocks * DIM) { - uint32_t norm_C_sp_addr = - C_sp_addr_start + i * (rounded_up_J / DIM) + jj + r; - if (jj + C_blocks * DIM >= J) { - norm_C_sp_addr |= (norm_cmds[cmd][1] - << 26); // Final mean/inv-std-dev calculation - } else { - norm_C_sp_addr |= - (norm_cmds[cmd][0] << 26); // Accumulate sum/variance - } - void *const C_dram_addr = - (int8_t *)out + (i * C_row_stride + jj) * sizeof(elem_t) + - r * C_row_stride * sizeof(elem_t); - const size_t cols = - J - jj < C_blocks * DIM ? J - jj : C_blocks * DIM; - gemmini_extended_mvout(C_dram_addr, norm_C_sp_addr, cols, 1); - } - } - } - } - } - } -#else - printf("Normalizations not supported in this Gemmini config\n"); - exit(1); -#endif -} - -static void tiled_norm(const size_t I, const size_t J, const size_t tile_I, - const size_t tile_J, const acc_t *in, elem_t *out, - const acc_scale_t C_scale, int act, - enum tiled_matmul_type_t norm_type) { - - gemmini_extended_config_st(J * sizeof(elem_t), act & 3, C_scale); - gemmini_config_ex(WS, 0, 0); // TODO is this actually required? - - gemmini_extended4_config_ld(J * sizeof(acc_t), MVIN_SCALE_IDENTITY, false, - DIM, 0); - gemmini_extended4_config_ld(J * sizeof(acc_t), MVIN_SCALE_IDENTITY, false, - DIM, 1); - - if (act == SOFTMAX) { - const scale_t a = 0.3585; - const scale_t b = 1.353; - const scale_t c = 0.344; - - // TODO let bert-scale be set by the programmer - acc_scale_t bert_scale = 0.05; - const acc_t qln2 = (int)(0.693147 / bert_scale); - const acc_t qln2_inv = 65536 / qln2; - const acc_t qb = b / bert_scale; - const acc_t qc = c / (a * bert_scale * bert_scale); - - gemmini_config_norm(qln2, 0, 0, 1, 0, qb, qc); - gemmini_config_norm(qln2_inv, 1, 0, 1, 0, qb, qc); - } - - for (size_t i = 0; i < I; i += tile_I) { - for (size_t j = 0; j < J; j += tile_J) { - const size_t I_tile = i + tile_I <= I ? tile_I : I - i; - const size_t J_tile = j + tile_J <= J ? tile_J : J - j; - - const acc_t *in_ = in + i * J + j; - elem_t *out_ = out + i * J + j; - - sp_tiled_norm(I_tile, J_tile, in_, out_, J, J, act); - } - } - - gemmini_fence(); -} - -static void tiled_norm_auto(const size_t I, const size_t J, const acc_t *in, - elem_t *out, const acc_scale_t C_scale, int act, - enum tiled_matmul_type_t norm_type) { - - size_t tile_I = I, tile_J = J; - size_t total_acc_rows = (tile_I / DIM + (tile_I % DIM != 0)) * DIM * - (tile_J / DIM + (tile_J % DIM != 0)); - - while (total_acc_rows > ACC_ROWS) { - if (tile_I > 1) { - tile_I--; - } else { - // TODO we should be able to tile over J as well to avoid this issue - printf("Can't fit pre-normalized tensor into accumulator"); - exit(1); - } - - total_acc_rows = (tile_I / DIM + (tile_I % DIM != 0)) * DIM * - (tile_J / DIM + (tile_J % DIM != 0)); - } - - if (norm_type) { - tiled_norm(I, J, tile_I, tile_J, in, out, C_scale, act, norm_type); - } else { - printf("Unsupported type\n"); - exit(1); - } -} - -#undef abs - -#endif // SRC_MAIN_C_GEMMINI_H diff --git a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_counter.h b/bb-tests/workloads/src/CTest/gemmini/include/gemmini_counter.h deleted file mode 100644 index 6050ed74..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_counter.h +++ /dev/null @@ -1,79 +0,0 @@ -// See LICENSE for license details. - -#ifndef COUNTER_H_ -#define COUNTER_H_ - -#define DISABLE 0 - -#define INCREMENTAL_COUNTERS 44 - -// All existing Gemmini performance counters - -#define MAIN_LD_CYCLES 1 -#define MAIN_ST_CYCLES 2 -#define MAIN_EX_CYCLES 3 -#define MAIN_LD_ST_CYCLES 4 -#define MAIN_LD_EX_CYCLES 5 -#define MAIN_ST_EX_CYCLES 6 -#define MAIN_LD_ST_EX_CYCLES 7 - -#define LOAD_DMA_WAIT_CYCLE 8 -#define LOAD_ACTIVE_CYCLE 9 -#define LOAD_SCRATCHPAD_WAIT_CYCLE 10 - -#define STORE_DMA_WAIT_CYCLE 11 -#define STORE_ACTIVE_CYCLE 12 -#define STORE_POOLING_CYCLE 13 -#define STORE_SCRATCHPAD_WAIT_CYCLE 14 - -#define DMA_TLB_MISS_CYCLE 15 -#define DMA_TLB_HIT_REQ 16 -#define DMA_TLB_TOTAL_REQ 17 - -#define RDMA_ACTIVE_CYCLE 18 -#define RDMA_TLB_WAIT_CYCLES 19 -#define RDMA_TL_WAIT_CYCLES 20 - -#define WDMA_ACTIVE_CYCLE 21 -#define WDMA_TLB_WAIT_CYCLES 22 -#define WDMA_TL_WAIT_CYCLES 23 - -#define EXE_ACTIVE_CYCLE 24 -#define EXE_FLUSH_CYCLE 25 -#define EXE_CONTROL_Q_BLOCK_CYCLE 26 -#define EXE_PRELOAD_HAZ_CYCLE 27 -#define EXE_OVERLAP_HAZ_CYCLE 28 - -#define SCRATCHPAD_A_WAIT_CYCLE 29 -#define SCRATCHPAD_B_WAIT_CYCLE 30 -#define SCRATCHPAD_D_WAIT_CYCLE 31 - -#define ACC_A_WAIT_CYCLE 32 -#define ACC_B_WAIT_CYCLE 33 -#define ACC_D_WAIT_CYCLE 34 - -#define A_GARBAGE_CYCLES 35 -#define B_GARBAGE_CYCLES 36 -#define D_GARBAGE_CYCLES 37 - -#define IM2COL_MEM_CYCLES 38 -#define IM2COL_ACTIVE_CYCLES 39 -#define IM2COL_TRANSPOSER_WAIT_CYCLE 40 - -#define RESERVATION_STATION_FULL_CYCLES 41 -#define RESERVATION_STATION_ACTIVE_CYCLES 42 - -#define LOOP_MATMUL_ACTIVE_CYCLES 43 -#define TRANSPOSE_PRELOAD_UNROLLER_ACTIVE_CYCLES 44 - -#define RESERVATION_STATION_LD_COUNT (INCREMENTAL_COUNTERS + 1) -#define RESERVATION_STATION_ST_COUNT (INCREMENTAL_COUNTERS + 2) -#define RESERVATION_STATION_EX_COUNT (INCREMENTAL_COUNTERS + 3) - -#define RDMA_BYTES_REC (INCREMENTAL_COUNTERS + 4) -#define WDMA_BYTES_SENT (INCREMENTAL_COUNTERS + 5) - -#define RDMA_TOTAL_LATENCY (INCREMENTAL_COUNTERS + 6) -#define WDMA_TOTAL_LATENCY (INCREMENTAL_COUNTERS + 7) - -#endif diff --git a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_nn.h b/bb-tests/workloads/src/CTest/gemmini/include/gemmini_nn.h deleted file mode 100644 index 16b3ebbd..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_nn.h +++ /dev/null @@ -1,584 +0,0 @@ -#ifndef GEMMINI_NN_H -#define GEMMINI_NN_H - -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini.h" -#include "include/gemmini_testutils.h" - -struct ConvParams { - int batch_size; - int in_row_dim; - int in_col_dim; - int out_row_dim; - int out_col_dim; - int kernel_size; - int in_channels; - int out_channels; - int in_stride; - int weight_stride; - int out_stride; - int stride; - int padding; - bool bias; - bool depthwise; - int n_patches; - int patch_size; - acc_scale_t output_scale; - scale_t res_scale; - int pool_size, pool_stride, pool_padding, out_dim_pooled; - - int I, J, K; -}; - -struct FcParams { - int batch_size; - int in_features; - int out_features; - acc_scale_t output_scale; - bool bias; - - int I, J, K; -}; - -#define HIST_IMAGES(IMAGES) \ - for (int num = -128; num <= 127; num++) { \ - int count = 0; \ - for (int i = 0; i < sizeof(IMAGES) / sizeof(IMAGES[0]); i++) { \ - for (int j = 0; j < sizeof(IMAGES[0]) / sizeof(IMAGES[0][0]); j++) { \ - for (int k = 0; k < sizeof(IMAGES[0][0]) / sizeof(IMAGES[0][0][0]); \ - k++) { \ - for (int l = 0; \ - l < sizeof(IMAGES[0][0][0]) / sizeof(IMAGES[0][0][0][0]); \ - l++) { \ - if (IMAGES[i][j][k][l] == num) { \ - count++; \ - } \ - } \ - } \ - } \ - } \ - if (count > 0) \ - printf("%d: %d times\n", num, count); \ - } - -#define HIST_MATRIX(MATRIX) \ - for (int num = -128; num <= 127; num++) { \ - int count = 0; \ - for (int i = 0; i < sizeof(MATRIX) / sizeof(MATRIX[0]); i++) { \ - for (int j = 0; j < sizeof(MATRIX[0]) / sizeof(MATRIX[0][0]); j++) { \ - if (MATRIX[i][j] == num) { \ - count++; \ - } \ - } \ - } \ - if (count > 0) \ - printf("%d: %d times\n", num, count); \ - } - -// This function runs a tiled matrix multiplication, with explicit tiling -// factors -static void tiled_matmul_nn(size_t dim_I, size_t dim_J, size_t dim_K, - const elem_t A[dim_I][dim_K], - const elem_t B[dim_K][dim_J], const void *D, - elem_t C[dim_I][dim_J], int act, acc_scale_t scale, - bool repeating_bias, size_t tile_I, size_t tile_J, - size_t tile_K, - enum tiled_matmul_type_t tiled_matmul_type, - bool check, char *layer_name) { - if (check) - printf("%s: gemmini\n", layer_name); - - tiled_matmul(dim_I, dim_J, dim_K, (elem_t *)A, (elem_t *)B, D, (elem_t *)C, - dim_K, dim_J, dim_J, dim_J, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, act, scale, 0, - repeating_bias, tile_I, tile_J, tile_K, false, false, false, - false, 0, tiled_matmul_type); - - if (check) { - printf("%s: CPU\n", layer_name); - elem_t gold[dim_I][dim_J]; - tiled_matmul_auto(dim_I, dim_J, dim_K, (elem_t *)A, (elem_t *)B, D, - (elem_t *)gold, dim_K, dim_J, dim_J, dim_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, act, scale, 0, repeating_bias, false, - false, false, false, 0, CPU); - - if (!MAT_IS_EQUAL(dim_I, dim_J, C, gold)) { - printf("Layer calculated incorrectly: %s\n", layer_name); - exit(1); - } - } -} - -// This function runs a tiled matrix multiplication, with automatically -// calculated tiling factors -// With default auto-stride calc (A_stride = dim_K, B_stride/C_stride/D_stride = -// dim_J) -static void tiled_matmul_nn_auto(size_t dim_I, size_t dim_J, size_t dim_K, - const elem_t A[dim_I][dim_K], - const elem_t B[dim_K][dim_J], const void *D, - elem_t C[dim_I][dim_J], int act, - acc_scale_t scale, bool repeating_bias, - enum tiled_matmul_type_t tiled_matmul_type, - bool check, char *layer_name) { - if (check) - printf("%s: gemmini\n", layer_name); - - tiled_matmul_auto(dim_I, dim_J, dim_K, (elem_t *)A, (elem_t *)B, D, - (elem_t *)C, dim_K, dim_J, dim_J, dim_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, act, scale, 0, repeating_bias, false, - false, false, false, 0, tiled_matmul_type); - - if (check) { - printf("%s: CPU\n", layer_name); - elem_t gold[dim_I][dim_J]; - tiled_matmul_auto(dim_I, dim_J, dim_K, (elem_t *)A, (elem_t *)B, D, - (elem_t *)gold, dim_K, dim_J, dim_J, dim_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, act, scale, 0, repeating_bias, false, - false, false, false, 0, CPU); - - if (!MAT_IS_EQUAL(dim_I, dim_J, C, gold)) { - printf("Layer calculated incorrectly: %s\n", layer_name); - exit(1); - } - } -} - -// need to specify stride -// auto tiling calc -static void tiled_matmul_nn_stride_auto( - size_t dim_I, size_t dim_J, size_t dim_K, const size_t A_stride, - const size_t B_stride, const size_t C_stride, const elem_t *A, - const elem_t *B, const void *D, const elem_t *C, int act, acc_scale_t scale, - bool repeating_bias, enum tiled_matmul_type_t tiled_matmul_type) { - - tiled_matmul_auto(dim_I, dim_J, dim_K, (elem_t *)A, (elem_t *)B, D, - (elem_t *)C, A_stride, B_stride, C_stride, C_stride, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, act, scale, 0, repeating_bias, false, - false, false, false, 0, tiled_matmul_type); -} -static void conv_dw( - size_t I, size_t J, const size_t batch_size, const size_t channels, - const size_t in_row_dim, const size_t in_col_dim, const size_t out_row_dim, - const size_t out_col_dim, const size_t kernel_size, - const elem_t input[batch_size][in_row_dim][in_col_dim][channels], - const elem_t weight[channels][kernel_size][kernel_size], const acc_t *bias, - // elem_t output [batch_size][out_row_dim][out_col_dim][channels], - elem_t output[I][J], const struct ConvParams *params) { - for (int batch = 0; batch < batch_size; batch++) { - for (int channel = 0; channel < channels; channel++) { - for (int out_row = 0; out_row < out_row_dim; out_row++) { - for (int out_col = 0; out_col < out_col_dim; out_col++) { - int in_row = out_row * params->stride - params->padding; - - acc_t result = 0; - if (params->bias) { - result = bias[channel]; - } - - for (int kernel_row = 0; kernel_row < params->kernel_size; - kernel_row++) { - int in_col = out_col * params->stride - params->padding; - - for (int kernel_col = 0; kernel_col < params->kernel_size; - kernel_col++) { - if (in_row >= 0 && in_row < params->in_row_dim && in_col >= 0 && - in_col < params->in_col_dim) { - result += input[batch][in_row][in_col][channel] * - weight[channel][kernel_row][kernel_col]; - } - - in_col++; - } - - in_row++; - } - - if (result < 0) { - result = 0; - } - - acc_t scaled = ACC_SCALE(result, params->output_scale); - - if (scaled > elem_t_max) { - scaled = elem_t_max; - } else if (scaled < elem_t_min) { - scaled = elem_t_min; - } - - size_t r = batch * params->out_row_dim * params->out_col_dim + - out_row * params->out_col_dim + out_col; - output[r][channel] = scaled; - // output[batch][out_row][out_col][channel] = scaled; - } - } - } - } -} - -static void conv_dw_with_col2im( - size_t prev_I, size_t prev_J, size_t I, size_t J, const size_t batch_size, - const size_t channels, const size_t out_row_dim, const size_t out_col_dim, - const size_t kernel_size, const elem_t input[prev_I][prev_J], - const elem_t weight[channels][kernel_size][kernel_size], const acc_t *bias, - // elem_t output [batch_size][out_dim][out_dim][channels], - elem_t output[I][J], const struct ConvParams *params) { - for (int batch = 0; batch < batch_size; batch++) { - for (int channel = 0; channel < channels; channel++) { - for (int out_row = 0; out_row < out_row_dim; out_row++) { - for (int out_col = 0; out_col < out_col_dim; out_col++) { - int in_row = out_row * params->stride - params->padding; - - acc_t result = 0; - if (params->bias) { - result = bias[channel]; - } - - for (int kernel_row = 0; kernel_row < params->kernel_size; - kernel_row++) { - int in_col = out_col * params->stride - params->padding; - - for (int kernel_col = 0; kernel_col < params->kernel_size; - kernel_col++) { - if (in_row >= 0 && in_row < params->in_row_dim && in_col >= 0 && - in_col < params->in_col_dim) { - // result += input[batch][in_row][in_col][channel] * - // weight[channel][kernel_row][kernel_col]; - - size_t r = batch * params->in_row_dim * params->in_col_dim + - in_row * params->in_col_dim + in_col; - - result += - input[r][channel] * weight[channel][kernel_row][kernel_col]; - } - - in_col++; - } - - in_row++; - } - - if (result < 0) { - result = 0; - } - - acc_t scaled = ACC_SCALE(result, params->output_scale); - - if (scaled > elem_t_max) { - scaled = elem_t_max; - } else if (scaled < elem_t_min) { - scaled = elem_t_min; - } - - size_t r = batch * params->out_row_dim * params->out_col_dim + - out_row * params->out_col_dim + out_col; - output[r][channel] = scaled; - // output[batch][out_row][out_col][channel] = scaled; - } - } - } - } -} - -static void -im2col(size_t batch_size, size_t channels, size_t im_row_dim, size_t im_col_dim, - size_t I, size_t K, - const elem_t input[batch_size][im_row_dim][im_col_dim][channels], - elem_t output[I][K], const struct ConvParams *params) { - int patch_row = 0; - - for (int n_batch = 0; n_batch < params->batch_size; n_batch++) { - for (int im_row = -params->padding; - im_row < - params->in_row_dim - params->kernel_size + params->padding + 1; - im_row += params->stride) { - for (int im_col = -params->padding; - im_col < - params->in_col_dim - params->kernel_size + params->padding + 1; - im_col += params->stride) { - int patch_col = 0; - - for (int filter_row = 0; filter_row < params->kernel_size; - filter_row++) { - for (int filter_col = 0; filter_col < params->kernel_size; - filter_col++) { - for (int im_channel = 0; im_channel < params->in_channels; - im_channel++) { - int pixel_row = im_row + filter_row; - int pixel_col = im_col + filter_col; - - if (pixel_row < 0 || pixel_row >= params->in_row_dim || - pixel_col < 0 || pixel_col >= params->in_col_dim) { - // output[patch_row][patch_col] = 0; - } else { - output[patch_row][patch_col] = - input[n_batch][pixel_row][pixel_col][im_channel]; - } - - patch_col++; - } - } - } - - patch_row++; - } - } - } -} - -static void im2col_with_col2im(size_t prev_I, size_t prev_J, size_t next_I, - size_t next_K, - const elem_t input[prev_I][prev_J], - elem_t output[next_I][next_K], - const struct ConvParams *params) { - int out_row = 0; - - for (int n_batch = 0; n_batch < params->batch_size; n_batch++) { - for (int im_row = -params->padding; - im_row < - params->in_row_dim - params->kernel_size + params->padding + 1; - im_row += params->stride) { - for (int im_col = -params->padding; - im_col < - params->in_col_dim - params->kernel_size + params->padding + 1; - im_col += params->stride) { - int out_col = 0; - - for (int filter_row = 0; filter_row < params->kernel_size; - filter_row++) { - for (int filter_col = 0; filter_col < params->kernel_size; - filter_col++) { - for (int im_channel = 0; im_channel < params->in_channels; - im_channel++) { - int pixel_row = im_row + filter_row; - int pixel_col = im_col + filter_col; - - if (pixel_row < 0 || pixel_row >= params->in_row_dim || - pixel_col < 0 || pixel_col >= params->in_col_dim) { - // output[out_row][out_col] = 0; - } else { - int in_row = n_batch * params->in_row_dim * params->in_col_dim + - pixel_row * params->in_col_dim + pixel_col; - int in_col = im_channel; - - output[out_row][out_col] = input[in_row][in_col]; - } - - out_col++; - } - } - } - - out_row++; - } - } - } -} - -// Compute C = A + B with saturating add -void vecadd(size_t len, const elem_t *A, const elem_t *B, elem_t *C, - scale_t A_shift) { - for (size_t i = 0; i < len; i++) { - acc_t result = MVIN_SCALE(A[i], A_shift) + B[i]; - - if (result > elem_t_max) { - result = elem_t_max; - } else if (result < elem_t_min) { - result = elem_t_min; - } - - C[i] = result; - } -} - -void resadd1(const size_t batch_size, const size_t channels, - const size_t im_dim, - const elem_t A[batch_size][im_dim][im_dim][channels], - const elem_t B[batch_size][im_dim][im_dim][channels], - elem_t C[batch_size][im_dim][im_dim][channels], bool relu, - const struct ConvParams *params) { - - const int minimum = relu ? 0 : elem_t_min; - - for (size_t batch = 0; batch < params->batch_size; batch++) { - for (size_t row = 0; row < params->out_dim_pooled; row++) { - for (size_t col = 0; col < params->out_dim_pooled; col++) { - for (size_t channel = 0; channel < params->out_channels; channel++) { - acc_t result = - MVIN_SCALE(A[batch][row][col][channel], params->res_scale) + - B[batch][row][col][channel]; - - if (result > elem_t_max) { - result = elem_t_max; - } else if (result < minimum) { - result = minimum; - } - - C[batch][row][col][channel] = result; - } - } - } - } -} - -void resadd2(const size_t I, const size_t J, const size_t batch_size, - const size_t channels, const size_t im_dim, const elem_t A[I][J], - const elem_t B[batch_size][im_dim][im_dim][channels], - elem_t C[batch_size][im_dim][im_dim][channels], bool relu, - const struct ConvParams *params) { - - const int minimum = relu ? 0 : elem_t_min; - - for (size_t batch = 0; batch < params->batch_size; batch++) { - for (size_t row = 0; row < params->out_dim_pooled; row++) { - for (size_t col = 0; col < params->out_dim_pooled; col++) { - for (size_t channel = 0; channel < params->out_channels; channel++) { - size_t r = batch * params->out_dim_pooled * params->out_dim_pooled + - row * params->out_dim_pooled + col; - - acc_t result = MVIN_SCALE(A[r][channel], params->res_scale) + - B[batch][row][col][channel]; - - if (result > elem_t_max) { - result = elem_t_max; - } else if (result < minimum) { - result = minimum; - } - - C[batch][row][col][channel] = result; - } - } - } - } -} - -void resadd3(const size_t I, const size_t J, const elem_t A[I][J], - const elem_t B[I][J], elem_t C[I][J], bool relu, - const struct ConvParams *params) { - - const int minimum = relu ? 0 : elem_t_min; - - for (size_t batch = 0; batch < params->batch_size; batch++) { - for (size_t row = 0; row < params->out_dim_pooled; row++) { - for (size_t col = 0; col < params->out_dim_pooled; col++) { - for (size_t channel = 0; channel < params->out_channels; channel++) { - size_t r = batch * params->out_dim_pooled * params->out_dim_pooled + - row * params->out_dim_pooled + col; - - acc_t result = - MVIN_SCALE(A[r][channel], params->res_scale) + B[r][channel]; - - if (result > elem_t_max) { - result = elem_t_max; - } else if (result < minimum) { - result = minimum; - } - - C[r][channel] = result; - } - } - } - } -} - -// Pooling -void pool(size_t batch_size, size_t channels, size_t in_row_dim, - size_t in_col_dim, size_t out_row_dim, size_t out_col_dim, - elem_t input[batch_size][in_row_dim][in_col_dim][channels], - elem_t output[batch_size][out_row_dim][out_col_dim][channels], - const struct ConvParams *params) { - size_t kernel_size = params->pool_size; - size_t stride = params->pool_stride; - // size_t in_dim = params->out_dim; - size_t padding = params->pool_padding; - - for (int batch = 0; batch < batch_size; batch++) { - for (int channel = 0; channel < channels; channel++) { - for (int out_row = 0; out_row < out_row_dim; out_row++) { - for (int out_col = 0; out_col < out_col_dim; out_col++) { - int in_row = out_row * stride - padding; - - elem_t result = elem_t_min; - - for (int kernel_row = 0; kernel_row < kernel_size; kernel_row++) { - int in_col = out_col * stride - padding; - - for (int kernel_col = 0; kernel_col < kernel_size; kernel_col++) { - if (in_row >= 0 && in_row < in_row_dim && in_col >= 0 && - in_col < in_col_dim) { - if (input[batch][in_row][in_col][channel] > result) { - result = input[batch][in_row][in_col][channel]; - } - } else if (0 > result) { - result = 0; - } - - in_col++; - } - - in_row++; - } - - output[batch][out_row][out_col][channel] = result; - } - } - } - } -} - -void pool_with_col2im( - size_t I, size_t J, size_t batch_size, size_t channels, size_t out_row_dim, - size_t out_col_dim, elem_t input[I][J], - elem_t output[batch_size][out_row_dim][out_col_dim][channels], - const struct ConvParams *params) { - size_t kernel_size = params->pool_size; - size_t stride = params->pool_stride; - size_t in_row_dim = params->out_row_dim; - size_t in_col_dim = params->out_col_dim; - size_t padding = params->pool_padding; - - for (int batch = 0; batch < batch_size; batch++) { - for (int channel = 0; channel < channels; channel++) { - for (int out_row = 0; out_row < out_row_dim; out_row++) { - for (int out_col = 0; out_col < out_col_dim; out_col++) { - int in_row = out_row * stride - padding; - - elem_t result = elem_t_min; - - for (int kernel_row = 0; kernel_row < kernel_size; kernel_row++) { - int in_col = out_col * stride - padding; - - for (int kernel_col = 0; kernel_col < kernel_size; kernel_col++) { - if (in_row >= 0 && in_row < in_row_dim && in_col >= 0 && - in_col < in_col_dim) { - if (input[batch * in_row_dim * in_col_dim + - in_row * in_col_dim + in_col][channel] > result) { - result = input[batch * in_row_dim * in_col_dim + - in_row * in_col_dim + in_col][channel]; - } - } else if (0 > result) { - result = 0; - } - - in_col++; - } - - in_row++; - } - - output[batch][out_row][out_col][channel] = result; - } - } - } - } -} - -#endif // GEMMINI_NN_H diff --git a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_params.h b/bb-tests/workloads/src/CTest/gemmini/include/gemmini_params.h deleted file mode 100644 index 119859f7..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_params.h +++ /dev/null @@ -1,102 +0,0 @@ -#ifndef GEMMINI_PARAMS_H -#define GEMMINI_PARAMS_H - -#include -#include - -#define XCUSTOM_ACC 3 -#define DIM 16 -#define ADDR_LEN 32 -#define BANK_NUM 4 -#define BANK_ROWS 4096 -#define ACC_ROWS 1024 -#define MAX_BYTES 64 -#define MAX_BLOCK_LEN (MAX_BYTES / (DIM * 1)) -#define MAX_BLOCK_LEN_ACC (MAX_BYTES / (DIM * 4)) - -typedef int8_t elem_t; -static const elem_t elem_t_max = 127; -static const elem_t elem_t_min = -128; -typedef int32_t acc_t; -typedef int64_t full_t; - -#define HAS_MVIN_SCALE -typedef float scale_t; -typedef uint32_t scale_t_bits; - -typedef int32_t scale_acc_t; -typedef uint32_t scale_acc_t_bits; - -typedef float acc_scale_t; -typedef uint32_t acc_scale_t_bits; - -#define row_align(blocks) \ - __attribute__((aligned(blocks * DIM * sizeof(elem_t)))) -#define row_align_acc(blocks) \ - __attribute__((aligned(blocks * DIM * sizeof(acc_t)))) - -#define MVIN_SCALE_IDENTITY 1.0 - -#define ACC_SCALE_IDENTITY 1.0 - -// Rounding right shift equation: -// https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm -#define ROUNDING_RIGHT_SHIFT(x, shift) \ - ((shift) > 0 \ - ? (((x) >> (shift)) + \ - (((shift) == 0 ? 0 : (((x) >> ((shift) - 1)) & 1)) & \ - ((((shift) <= 1 ? 0 : ((x) & ((1 << ((shift) - 1)) - 1))) != 0) | \ - (((x) >> (shift)) & 1)))) \ - : ((x) << (-(shift)))) - -#ifdef __cplusplus -#define SAME_TYPE(x) decltype(x) -#else -#define SAME_TYPE(x) typeof(x) -#endif - -#define ROUND_NEAR_EVEN(x) \ - ({ \ - const SAME_TYPE(x) x_ = (x); \ - const long long i = x_; \ - const long long next = x_ < 0 ? x_ - 1 : x_ + 1; \ - SAME_TYPE(x) rem = x_ - i; \ - rem = rem < 0 ? -rem : rem; \ - SAME_TYPE(x) \ - result = rem < 0.5 ? i : (rem > 0.5 ? next : (i % 2 == 0 ? i : next)); \ - result; \ - }) - -// Rounding right shift equation: -// https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm -#define ROUNDING_RIGHT_SHIFT_BITS(x, shift) \ - ((shift) > 0 \ - ? (((x) >> (shift)) + \ - (((shift) == 0 ? 0 : (((x) >> ((shift) - 1)) & 1)) & \ - ((((shift) <= 1 ? 0 : ((x) & ((1 << ((shift) - 1)) - 1))) != 0) | \ - (((x) >> (shift)) & 1)))) \ - : ((x) << (-(shift)))) - -#define ACC_SCALE(x, scale) \ - ({ \ - float y = ROUND_NEAR_EVEN((x) * (scale)); \ - y > INT8_MAX ? INT8_MAX : (y < INT8_MIN ? INT8_MIN : (acc_t)y); \ - }) - -#define MVIN_SCALE(x, scale) \ - ({ \ - float y = ROUND_NEAR_EVEN((x) * (scale)); \ - y > INT8_MAX ? INT8_MAX : (y < INT8_MIN ? INT8_MIN : (elem_t)y); \ - }) - -#define MVIN_SCALE_ACC(x, scale) (x) - -#define ACC_SCALE_T_IS_FLOAT -#define ACC_SCALE_EXP_BITS 8 -#define ACC_SCALE_SIG_BITS 24 - -#define ACC_READ_SMALL_WIDTH - -#define HAS_FIRST_LAYER_OPTIMIZATIONS - -#endif // GEMMINI_PARAMS_H diff --git a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_testutils.h b/bb-tests/workloads/src/CTest/gemmini/include/gemmini_testutils.h deleted file mode 100644 index 3cfd4d00..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/gemmini_testutils.h +++ /dev/null @@ -1,307 +0,0 @@ -// See LICENSE for license details. - -#ifndef SRC_MAIN_C_GEMMINI_TESTUTILS_H -#define SRC_MAIN_C_GEMMINI_TESTUTILS_H - -#undef abs - -#include -#include -#include -#include -#include -#include - -#include "include/gemmini.h" -#include "include/gemmini_params.h" - -#ifdef BAREMETAL -#undef assert -#define assert(expr) \ - if (!(expr)) { \ - printf("Failed assertion: " #expr "\n " __FILE__ ":%u\n", __LINE__); \ - exit(1); \ - } -#endif - -// #define GEMMINI_ASSERTIONS - -// Matmul utility functions -static void matmul(elem_t A[DIM][DIM], elem_t B[DIM][DIM], elem_t D[DIM][DIM], - full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -static void matmul_short(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], elem_t C[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C[r][c] += A[r][k] * B[k][c]; - } -} - -static void matmul_full(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - full_t D[DIM][DIM], full_t C_full[DIM][DIM]) { - // Identical to the other matmul function, but with a 64-bit bias - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -static void matmul_A_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[k][r] * B[k][c]; - } -} - -static void matmul_short_A_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], elem_t C[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C[r][c] += A[k][r] * B[k][c]; - } -} - -static void matmul_full_A_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - full_t D[DIM][DIM], - full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[k][r] * B[k][c]; - } -} - -static void matmul_B_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[r][k] * B[c][k]; - } -} - -static void matmul_short_B_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], elem_t C[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C[r][c] += A[r][k] * B[c][k]; - } -} - -static void matmul_full_B_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - full_t D[DIM][DIM], - full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[r][k] * B[c][k]; - } -} - -static void matmul_AB_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[k][r] * B[c][k]; - } -} - -static void matmul_short_AB_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - elem_t D[DIM][DIM], elem_t C[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C[r][c] += A[k][r] * B[c][k]; - } -} - -static void matmul_full_AB_transposed(elem_t A[DIM][DIM], elem_t B[DIM][DIM], - full_t D[DIM][DIM], - full_t C_full[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < DIM; k++) - C_full[r][c] += A[k][r] * B[c][k]; - } -} - -static void matadd(full_t sum[DIM][DIM], full_t m1[DIM][DIM], - full_t m2[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) - sum[r][c] = m1[r][c] + m2[r][c]; -} - -// THIS IS A ROUNDING SHIFT! It also performs a saturating cast -static void matshift(full_t full[DIM][DIM], elem_t out[DIM][DIM], int shift) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - // Bitshift and round element - full_t shifted = ROUNDING_RIGHT_SHIFT(full[r][c], shift); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = shifted > elem_t_max - ? elem_t_max - : (shifted < elem_t_min ? elem_t_min : shifted); - out[r][c] = elem; -#else - out[r][c] = shifted; // TODO should we also saturate when using floats? -#endif - } -} - -static void matscale(full_t full[DIM][DIM], elem_t out[DIM][DIM], - acc_scale_t scale) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) { - // Bitshift and round element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -static void matrelu(elem_t in[DIM][DIM], elem_t out[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) - out[r][c] = in[r][c] > 0 ? in[r][c] : 0; -} - -static void transpose(elem_t in[DIM][DIM], elem_t out[DIM][DIM]) { - for (size_t r = 0; r < DIM; r++) - for (size_t c = 0; c < DIM; c++) - out[c][r] = in[r][c]; -} - -int rand() { - static uint32_t x = 777; - x = x * 1664525 + 1013904223; - return x >> 24; -} - -#ifdef ELEM_T_IS_FLOAT -double rand_double() { - double a = (double)(rand() % 128) / (double)(1 + (rand() % 64)); - double b = (double)(rand() % 128) / (double)(1 + (rand() % 64)); - return a - b; -} -#endif - -static void printMatrix(elem_t m[DIM][DIM]) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", m[i][j]); -#else - printf("%x ", elem_t_to_elem_t_bits(m[i][j])); -#endif - printf("\n"); - } -} - -static void printMatrixAcc(acc_t m[DIM][DIM]) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", m[i][j]); -#else - printf("%x ", acc_t_to_acc_t_bits(m[i][j])); -#endif - printf("\n"); - } -} - -static int is_equal(elem_t x[DIM][DIM], elem_t y[DIM][DIM]) { - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - if (x[i][j] != y[i][j]) -#else - bool isnanx = elem_t_isnan(x[i][j]); - bool isnany = elem_t_isnan(y[i][j]); - - if (x[i][j] != y[i][j] && !(isnanx && isnany)) -#endif - return 0; - } - return 1; -} - -static int is_equal_transposed(elem_t x[DIM][DIM], elem_t y[DIM][DIM]) { - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - if (x[i][j] != y[j][i]) -#else - bool isnanx = elem_t_isnan(x[i][j]); - bool isnany = elem_t_isnan(y[j][i]); - - if (x[i][j] != y[j][i] && !(isnanx && isnany)) -#endif - return 0; - } - return 1; -} - -// This is a GNU extension known as statment expressions -#define MAT_IS_EQUAL(dim_i, dim_j, x, y) \ - ({ \ - int result = 1; \ - for (size_t i = 0; i < dim_i; i++) \ - for (size_t j = 0; j < dim_j; ++j) { \ - if (x[i][j] != y[i][j]) { \ - result = 0; \ - break; \ - } \ - } \ - result; \ - }) - -static uint64_t read_cycles() { - uint64_t cycles; - asm volatile("rdcycle %0" : "=r"(cycles)); - return cycles; - - // const uint32_t * mtime = (uint32_t *)(33554432 + 0xbff8); - // const uint32_t * mtime = (uint32_t *)(33554432 + 0xbffc); - // return *mtime; -} - -#undef abs - -#endif // SRC_MAIN_C_GEMMINI_TESTUTILS_H diff --git a/bb-tests/workloads/src/CTest/gemmini/include/translator.h b/bb-tests/workloads/src/CTest/gemmini/include/translator.h deleted file mode 100644 index 748ad4d0..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/include/translator.h +++ /dev/null @@ -1,12 +0,0 @@ -// See LICENSE for license details. - -#ifndef SRC_MAIN_C_TRANSLATOR_H -#define SRC_MAIN_C_TRANSLATOR_H - -#include "rocc-software/src/xcustom.h" - -#define XCUSTOM_TRANS 1 - -#define doTranslate(y, vaddr) ROCC_INSTRUCTION(XCUSTOM_TRANS, y, vaddr, 0, 0); - -#endif // SRC_MAIN_C_TRANSLATOR_H diff --git a/bb-tests/workloads/src/CTest/gemmini/matmul.c b/bb-tests/workloads/src/CTest/gemmini/matmul.c deleted file mode 100644 index 8c37de4f..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/matmul.c +++ /dev/null @@ -1,460 +0,0 @@ -// See LICENSE for license details. -// The main point of this test is just to check whether we can switch between -// output- and weight-stationary dataflows - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" -#include - -static elem_t ZERO[DIM][DIM]; - -#ifdef FAST -#define AINIT RELU -#define SINIT 4 -#define RAND (rand()) -#define N 1 -#else -#define AINIT NO_ACTIVATION -#define SINIT 0 -#define RAND (rand()) -#define N 2 -#endif - -void operands(int c, int *a, int *b, int *d) { - *d = c % N; - *b = (c / N) % N; - *a = c / (N * N); -} - -void test_os(bool A_transpose, bool B_transpose) { - // Output stationary - printf("Output-stationary\n"); - - void (*matmul_ptr)(elem_t[DIM][DIM], elem_t[DIM][DIM], elem_t[DIM][DIM], - full_t[DIM][DIM]); - void (*matmul_full_ptr)(elem_t[DIM][DIM], elem_t[DIM][DIM], full_t[DIM][DIM], - full_t[DIM][DIM]); - - if (!A_transpose && !B_transpose) { - matmul_ptr = &matmul; - matmul_full_ptr = &matmul_full; - } else if (A_transpose && !B_transpose) { - matmul_ptr = &matmul_A_transposed; - matmul_full_ptr = &matmul_full_A_transposed; - } else if (!A_transpose && B_transpose) { - // Just return immediately because we don't support this - return; - } else if (A_transpose && B_transpose) { - matmul_ptr = &matmul_AB_transposed; - matmul_full_ptr = &matmul_full_AB_transposed; - } - - for (int activation = AINIT; activation <= RELU; ++activation) { - for (int shift = SINIT; shift <= 4; shift += 4) { - // printf("activation: %d, shift: %d\n", activation, shift); - - static elem_t A[N][DIM][DIM] row_align(1); - static elem_t B[N][DIM][DIM] row_align(1); - static elem_t D[N][DIM][DIM] row_align(1); - - // We will try out every combination of A, B, D possible - static elem_t C[N * N * N][DIM][DIM] row_align(1); - static full_t gold_full[N * N * N][DIM][DIM]; - static elem_t gold[N * N * N][DIM][DIM]; - - // ...taking into account the preloads or accumulates - static int preload[N * N * N] = {1}; - for (int i = 1; i < N * N * N; ++i) - preload[i] = 1; // rand() % 2; - - // ...and for the actual preloads, do we just preload zeros? - static int preload_zeros[N * N * N]; - for (int i = 0; i < N * N * N; ++i) - preload_zeros[i] = 1; // rand() % 2; - - // ...and finally, which results won't produce any output - static int no_output[N * N * N]; - for (int i = 0; i < N * N * N - 1; ++i) - no_output[i] = !preload[i + 1]; - no_output[N * N * N - 1] = 0; - - // Print the sequence out - /*printf("Preloads: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", preload[i]); - printf("\n"); - printf("Zeros: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", preload_zeros[i]); - printf("\n"); - printf("No outputs: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", no_output[i]); - printf("\n");*/ - - for (size_t n = 0; n < N; ++n) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - A[n][i][j] = (RAND % 64) - 32; - B[n][i][j] = (RAND % 64) - 32; - D[n][i][j] = (RAND % 64) - 32; - } - } - } -#ifdef FAST1 - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - gold[0][i][j] = 1; - } - } -#else - for (size_t g = 0; g < N * N * N; ++g) { - int a, b, d; - operands(g, &a, &b, &d); - - if (!preload[g]) - (*matmul_full_ptr)(A[a], B[b], gold_full[g - 1], gold_full[g]); - else if (preload_zeros[g]) { - (*matmul_ptr)(A[a], B[b], ZERO, gold_full[g]); - } else { - (*matmul_ptr)(A[a], B[b], D[d], gold_full[g]); - } - } - - for (size_t g = 0; g < N * N * N; ++g) { - matshift(gold_full[g], gold[g], shift); - if (activation == RELU) - matrelu(gold[g], gold[g]); - } -#endif - int A_addr = 0; - int B_addr = N * DIM; - int D_addr = 2 * N * DIM; - int C_addr = 3 * N * DIM; - - // printf("Moving in\n"); - for (size_t n = 0; n < N; ++n) - gemmini_mvin(A[n], A_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) - gemmini_mvin(B[n], B_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) { - gemmini_mvin(D[n], D_addr + n * DIM); - } - - // printf("Setting mode\n"); - gemmini_extended_config_ex(OUTPUT_STATIONARY, activation, shift, 1, - A_transpose, B_transpose); - - // printf("Matmulling\n"); - for (size_t c = 0; c < N * N * N; ++c) { - int a, b, d; - operands(c, &a, &b, &d); - - uint64_t out_addr = C_addr + c * DIM; - if (no_output[c]) - out_addr = GARBAGE_ADDR; - - if (!preload[c]) { - gemmini_preload_zeros(out_addr); - gemmini_compute_accumulated(A_addr + a * DIM, B_addr + b * DIM); - } else if (preload_zeros[c]) { - gemmini_preload_zeros(out_addr); - gemmini_compute_preloaded(A_addr + a * DIM, B_addr + b * DIM); - } else { - gemmini_preload(D_addr + d * DIM, out_addr); - gemmini_compute_preloaded(A_addr + a * DIM, B_addr + b * DIM); - } - } - - // printf("Moving out\n"); - for (size_t c = 0; c < N * N * N; ++c) - if (!no_output[c]) { - gemmini_mvout(C[c], C_addr + c * DIM); - } - - gemmini_fence(); - - /* - printf("Moved out\n"); - - printf("A[0]:\n"); - printMatrix(A[0]); - printf("B[0]:\n"); - printMatrix(B[0]); - - for (int n = 0; n < N*N*N; ++n) { - if (!no_output[n]) { - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("\n"); - } - } - */ - - for (int n = 0; n < N * N * N; ++n) - if (!no_output[n] && !is_equal(C[n], gold[n])) { - printf("activation: %d, shift: %d, n: %d, A_transpose: %d, " - "B_transpose: %d\n", - activation, shift, n, A_transpose, B_transpose); - - printf("A:\n"); - printMatrix(A[n]); - printf("B:\n"); - printMatrix(B[n]); - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("\n"); - - exit(1); - } - } - } -} - -void test_ws(bool A_transpose, bool B_transpose) { - // Weight-stationary - printf("Weight-stationary\n"); - - void (*matmul_ptr)(elem_t[DIM][DIM], elem_t[DIM][DIM], elem_t[DIM][DIM], - full_t[DIM][DIM]); - - if (!A_transpose && !B_transpose) { - matmul_ptr = &matmul; - } else if (A_transpose && !B_transpose) { - matmul_ptr = &matmul_A_transposed; - } else if (!A_transpose && B_transpose) { - matmul_ptr = &matmul_B_transposed; - } else if (A_transpose && B_transpose) { - return; - } - - for (int activation = AINIT; activation <= RELU; ++activation) { - for (int scale = SINIT; scale <= 4; scale += 4) { - static elem_t A[N][DIM][DIM] row_align(1); - static elem_t B[N][DIM][DIM] row_align(1); - static elem_t D[N][DIM][DIM] row_align(1); - - // We will try out every combination of A, B, D possible - static elem_t C[N * N * N][DIM][DIM] row_align(1); - static full_t gold_full[N * N * N][DIM][DIM]; - static elem_t gold[N * N * N][DIM][DIM]; - - // ...taking into account whether we preload new weights or re-use the old - // ones - static int preload[N * N * N] = {1}; - for (int i = 1; i < N * N * N; ++i) - preload[i] = RAND % 2; - - // ...whether we pass in a D or just use zeros - static int add_to_zeros[N * N * N]; - for (int i = 0; i < N * N * N; ++i) - add_to_zeros[i] = RAND % 2; - - // ...and whether we accumulate on top of the previous result - static int accumulate[N * N * N] = {0}; - for (int i = 1; i < N * N * N; ++i) - accumulate[i] = RAND % 2; - - static int no_output[N * N * N]; - for (int i = 0; i < N * N * N - 1; ++i) - no_output[i] = accumulate[i + 1]; - no_output[N * N * N - 1] = 0; - - // Print the sequence out - /*printf("Preloads: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", preload[i]); - printf("\n"); - printf("Zeros: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", add_to_zeros[i]); - printf("\n"); - printf("Accumulates: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", accumulate[i]); - printf("\n"); - printf("No outputs: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", no_output[i]); - printf("\n");*/ - - for (size_t n = 0; n < N; ++n) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - A[n][i][j] = (RAND % 64) - 32; - B[n][i][j] = (RAND % 64) - 32; - D[n][i][j] = (RAND % 64) - 32; - } - } - } -#ifdef FAST1 - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - gold[0][i][j] = 64; - } - } -#else - for (size_t g = 0; g < N * N * N; ++g) { - int a, b, d; - operands(g, &a, &b, &d); - - // We need to find the last B value in case we aren't preloading new - // weights - for (int last_g = g; last_g >= 0; --last_g) { - int tmp_a, tmp_d; - if (preload[last_g]) { - operands(last_g, &tmp_a, &b, &tmp_d); - break; - } - } - - if (add_to_zeros[g]) { - (*matmul_ptr)(A[a], B[b], ZERO, gold_full[g]); - } else { - (*matmul_ptr)(A[a], B[b], D[d], gold_full[g]); - } - - if (accumulate[g]) - matadd(gold_full[g], gold_full[g - 1], gold_full[g]); - } - - for (size_t g = 0; g < N * N * N; ++g) { - matscale(gold_full[g], gold[g], scale); - if (activation == RELU) - matrelu(gold[g], gold[g]); - } -#endif - uint32_t A_addr = 0; - uint32_t B_addr = N * DIM; - uint32_t D_addr = 2 * N * DIM; - uint32_t C_addr_acc = 1 << (ADDR_LEN - 1); - - // Calculate the proper destination addresses of everything - uint32_t C_addrs[N * N * N]; - for (size_t c = 0; c < N * N * N; ++c) - C_addrs[c] = C_addr_acc + c * DIM; - for (size_t c = 0; c < N * N * N; ++c) { - int last_c; - for (last_c = c; last_c >= 0; --last_c) - if (!accumulate[last_c]) - break; - if (c != last_c) - C_addrs[c] = C_addrs[last_c] | (1 << (ADDR_LEN - 2)); - } - - // printf("Moving in\n"); - for (size_t n = 0; n < N; ++n) - gemmini_mvin(A[n], A_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) - gemmini_mvin(B[n], B_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) - gemmini_mvin(D[n], D_addr + n * DIM); - - // printf("Setting mode\n"); - gemmini_extended_config_ex(WEIGHT_STATIONARY, 0, 0, 1, A_transpose, - B_transpose); - gemmini_extended_config_st(DIM * sizeof(elem_t), activation, scale); - - // printf("Matmulling\n"); - for (size_t c = 0; c < N * N * N; ++c) { - int a, b, d; - operands(c, &a, &b, &d); - - uint64_t d_addr = D_addr + d * DIM; - if (add_to_zeros[c]) - d_addr = GARBAGE_ADDR; - - if (!preload[c]) { - gemmini_preload_zeros(C_addrs[c]); - gemmini_compute_accumulated(A_addr + a * DIM, d_addr); - } else { - gemmini_preload(B_addr + b * DIM, C_addrs[c]); - gemmini_compute_preloaded(A_addr + a * DIM, d_addr); - } - } - - // printf("Moving out\n"); - for (size_t c = 0; c < N * N * N; ++c) - if (!no_output[c]) { - gemmini_mvout(C[c], C_addrs[c] & ~(1 << (ADDR_LEN - 2))); - } - - gemmini_fence(); - - /*printf("Moved out\n"); - for (int n = 0; n < N*N*N; ++n) { - if (!no_output[n]) { - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("\n"); - } - }*/ - - for (int n = 0; n < N * N * N; ++n) - if (!no_output[n] && !is_equal(C[n], gold[n])) { - printf("activation: %d, scale: %d, n: %d, A_transpose: %d, " - "B_transpose: %d\n", - activation, scale, n, A_transpose, B_transpose); - - printf("A:\n"); - printMatrix(A[n]); - printf("B:\n"); - printMatrix(B[n]); - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("\n"); - - exit(1); - } - } - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - for (int A_transpose = 0; A_transpose < 2; A_transpose++) { - for (int B_transpose = 0; B_transpose < 2; B_transpose++) { - for (int dataflow = OUTPUT_STATIONARY; dataflow <= WEIGHT_STATIONARY; - dataflow++) { - printf("A_transpose: %d, B_transpose: %d, dataflow: %d\n", A_transpose, - B_transpose, dataflow); - - if (dataflow == OUTPUT_STATIONARY) - test_os(A_transpose, B_transpose); - else - test_ws(A_transpose, B_transpose); - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/matmul_os.c b/bb-tests/workloads/src/CTest/gemmini/matmul_os.c deleted file mode 100644 index e57733b2..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/matmul_os.c +++ /dev/null @@ -1,206 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" -#include - -#ifdef FAST -#define AINIT RELU -#define SINIT 12 -#define N 1 -#else -#define AINIT NO_ACTIVATION -#define SINIT 0 -#define N 2 -#endif - -void operands(int c, int *a, int *b, int *d) { - *d = c % N; - *b = (c / N) % N; - *a = c / (N * N); -} - -#if (3 * N + N * N * N) * DIM > (BANK_NUM * BANK_ROWS) -#error scratchpad not big enough -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - static elem_t ZERO[DIM][DIM]; - - for (int activation = AINIT; activation <= RELU; ++activation) { - for (int shift = SINIT; shift <= 12; shift += 4) { - // printf("activation: %d, shift: %d\n", activation, shift); - - static elem_t A[N][DIM][DIM] row_align(1); - static elem_t B[N][DIM][DIM] row_align(1); - static elem_t D[N][DIM][DIM] row_align(1); - - // We will try out every combination of A, B, D possible - static elem_t C[N * N * N][DIM][DIM] row_align(1); - static full_t gold_full[N * N * N][DIM][DIM]; - static elem_t gold[N * N * N][DIM][DIM]; - - // ...taking into account the preloads or accumulates - static int preload[N * N * N] = {1}; - for (int i = 1; i < N * N * N; ++i) - preload[i] = rand() % 2; - - // ...and for the actual preloads, do we just preload zeros? - static int preload_zeros[N * N * N]; - for (int i = 0; i < N * N * N; ++i) - preload_zeros[i] = rand() % 2; - - // ...and finally, which results won't produce any output - static int no_output[N * N * N]; - for (int i = 0; i < N * N * N - 1; ++i) - no_output[i] = !preload[i + 1]; - no_output[N * N * N - 1] = 0; - - // Print the sequence out - /*printf("Preloads: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", preload[i]); - printf("\n"); - printf("Zeros: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", preload_zeros[i]); - printf("\n"); - printf("No outputs: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", no_output[i]); - printf("\n");*/ - - for (size_t n = 0; n < N; ++n) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - A[n][i][j] = (rand() % 64) - 32; - B[n][i][j] = (rand() % 64) - 32; - D[n][i][j] = (rand() % 64) - 32; - } - } - } - - for (size_t g = 0; g < N * N * N; ++g) { - int a, b, d; - operands(g, &a, &b, &d); - - if (!preload[g]) - matmul_full(A[a], B[b], gold_full[g - 1], gold_full[g]); - else if (preload_zeros[g]) - matmul(A[a], B[b], ZERO, gold_full[g]); - else - matmul(A[a], B[b], D[d], gold_full[g]); - } - - for (size_t g = 0; g < N * N * N; ++g) { - matshift(gold_full[g], gold[g], shift); - if (activation == RELU) - matrelu(gold[g], gold[g]); - } - - int A_addr = 0; - int B_addr = N * DIM; - int D_addr = 2 * N * DIM; - int C_addr = 3 * N * DIM; - - // printf("Moving in\n"); - for (size_t n = 0; n < N; ++n) - gemmini_mvin(A[n], A_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) - gemmini_mvin(B[n], B_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) { - gemmini_mvin(D[n], D_addr + n * DIM); - } - - // printf("Setting mode\n"); - gemmini_config_ex(OUTPUT_STATIONARY, activation, shift); - - // printf("Matmulling\n"); - for (size_t c = 0; c < N * N * N; ++c) { - // printf("\tc: %u\n", c); - - int a, b, d; - operands(c, &a, &b, &d); - - uint64_t out_addr = C_addr + c * DIM; - if (no_output[c]) - out_addr = GARBAGE_ADDR; - - if (!preload[c]) { - gemmini_preload_zeros(out_addr); - gemmini_compute_accumulated(A_addr + a * DIM, B_addr + b * DIM); - } else if (preload_zeros[c]) { - gemmini_preload_zeros(out_addr); - gemmini_compute_preloaded(A_addr + a * DIM, B_addr + b * DIM); - } else { - gemmini_preload(D_addr + d * DIM, out_addr); - gemmini_compute_preloaded(A_addr + a * DIM, B_addr + b * DIM); - } - } - - // printf("Moving out\n"); - for (size_t c = 0; c < N * N * N; ++c) - if (!no_output[c]) { - // printf("\tc: %u\n", c); - gemmini_mvout(&C[c][0][0], C_addr + c * DIM); - } - - // printf("Fencing\n"); - gemmini_fence(); - - /*printf("Moved out\n"); - for (int n = 0; n < N*N*N; ++n) { - if (!no_output[n]) { - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("\n"); - } - }*/ - - // printf("Checking\n"); - for (int n = 0; n < N * N * N; ++n) - if (!no_output[n] && !is_equal(C[n], gold[n])) { - printf("activation: %d, shift: %d\n", activation, shift); - - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("Gold_full:\n"); - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - printf("%lld ", gold_full[n][i][j]); - } - printf("\n"); - } - printf("\n"); - - exit(1); - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/matmul_ws.c b/bb-tests/workloads/src/CTest/gemmini/matmul_ws.c deleted file mode 100644 index cd30940c..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/matmul_ws.c +++ /dev/null @@ -1,227 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" -#include - -#ifdef FAST -#define AINIT RELU -#define SINIT 12 -#define N 1 -#else -#define AINIT NO_ACTIVATION -#define SINIT 0 -#define N 2 -#endif - -void operands(int c, int *a, int *b, int *d) { - *d = c % N; - *b = (c / N) % N; - *a = c / (N * N); -} - -#if 3 * N * DIM > (BANK_NUM * BANK_ROWS) || N * N * N * DIM > ACC_ROWS -// #error scratchpad or accumulator not big enough -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - static elem_t ZERO[DIM][DIM]; - - gemmini_flush(0); - gemmini_config_ld(DIM * sizeof(elem_t)); - - for (int activation = AINIT; activation <= RELU; ++activation) { -#ifdef ACC_SCALE_T_IS_FLOAT - for (acc_scale_t scale = 0; scale <= 1.5; scale += 0.5) { -#else - for (acc_scale_t scale = SINIT; scale <= 12; scale += 4) { -#endif - static elem_t A[N][DIM][DIM] row_align(1); - static elem_t B[N][DIM][DIM] row_align(1); - static elem_t D[N][DIM][DIM] row_align(1); - - // We will try out every combination of A, B, D possible - static elem_t C[N * N * N][DIM][DIM] row_align(1); - static full_t gold_full[N * N * N][DIM][DIM]; - static elem_t gold[N * N * N][DIM][DIM]; - - // ...taking into account whether we preload new weights or re-use the old - // ones - static int preload[N * N * N] = {1}; - for (int i = 1; i < N * N * N; ++i) - preload[i] = rand() % 2; - - // ...whether we pass in a D or just use zeros - static int add_to_zeros[N * N * N]; - for (int i = 0; i < N * N * N; ++i) - add_to_zeros[i] = rand() % 2; - - // ...and whether we accumulate on top of the previous result - static int accumulate[N * N * N] = {0}; - for (int i = 1; i < N * N * N; ++i) - accumulate[i] = rand() % 2; - - static int no_output[N * N * N]; - for (int i = 0; i < N * N * N - 1; ++i) - no_output[i] = accumulate[i + 1]; - no_output[N * N * N - 1] = 0; - - // Print the sequence out - /*printf("Preloads: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", preload[i]); - printf("\n"); - printf("Zeros: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", add_to_zeros[i]); - printf("\n"); - printf("Accumulates: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", accumulate[i]); - printf("\n"); - printf("No outputs: "); - for (int i = 0; i < N*N*N; ++i) - printf("%d, ", no_output[i]); - printf("\n");*/ - - for (size_t n = 0; n < N; ++n) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) { - A[n][i][j] = (rand() % 64) - 32; - B[n][i][j] = (rand() % 64) - 32; - D[n][i][j] = (rand() % 64) - 32; - } - } - } - - for (size_t g = 0; g < N * N * N; ++g) { - int a, b, d; - operands(g, &a, &b, &d); - - // We need to find the last B value in case we aren't preloading new - // weights - for (int last_g = g; last_g >= 0; --last_g) { - int tmp_a, tmp_d; - if (preload[last_g]) { - operands(last_g, &tmp_a, &b, &tmp_d); - break; - } - } - - if (add_to_zeros[g]) - matmul(A[a], B[b], ZERO, gold_full[g]); - else - matmul(A[a], B[b], D[d], gold_full[g]); - - if (accumulate[g]) - matadd(gold_full[g], gold_full[g - 1], gold_full[g]); - } - - for (size_t g = 0; g < N * N * N; ++g) { - matscale(gold_full[g], gold[g], scale); - if (activation == RELU) - matrelu(gold[g], gold[g]); - } - - uint32_t A_addr = 0; - uint32_t B_addr = N * DIM; - uint32_t D_addr = 2 * N * DIM; - uint32_t C_addr_acc = 1 << (ADDR_LEN - 1); - - // Calculate the proper destination addresses of everything - uint32_t C_addrs[N * N * N]; - for (size_t c = 0; c < N * N * N; ++c) - C_addrs[c] = C_addr_acc + c * DIM; - for (size_t c = 0; c < N * N * N; ++c) { - int last_c; - for (last_c = c; last_c >= 0; --last_c) - if (!accumulate[last_c]) - break; - if (c != last_c) - C_addrs[c] = C_addrs[last_c] | (1 << (ADDR_LEN - 2)); - } - - // printf("Moving in\n"); - for (size_t n = 0; n < N; ++n) - gemmini_mvin(A[n], A_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) - gemmini_mvin(B[n], B_addr + n * DIM); - - for (size_t n = 0; n < N; ++n) - if (n == N - 1) { - gemmini_mvin(D[n], D_addr + n * DIM); - } else { - gemmini_mvin(D[n], D_addr + n * DIM); - } - - // printf("Setting mode\n"); - gemmini_config_ex(WEIGHT_STATIONARY, 0, 0); - gemmini_extended_config_st(DIM * sizeof(elem_t), activation, scale); - - // printf("Matmulling\n"); - for (size_t c = 0; c < N * N * N; ++c) { - int a, b, d; - operands(c, &a, &b, &d); - - uint32_t d_addr = D_addr + d * DIM; - if (add_to_zeros[c]) - d_addr = GARBAGE_ADDR; - - if (!preload[c]) { - gemmini_preload_zeros(C_addrs[c]); - gemmini_compute_accumulated(A_addr + a * DIM, d_addr); - } else { - gemmini_preload(B_addr + b * DIM, C_addrs[c]); - gemmini_compute_preloaded(A_addr + a * DIM, d_addr); - } - } - - // printf("Moving out\n"); - for (size_t c = 0; c < N * N * N; ++c) - if (!no_output[c]) { - gemmini_mvout(C[c], C_addrs[c] & ~(1 << (ADDR_LEN - 2))); - } - - gemmini_fence(); - - /*printf("Moved out\n"); - for (int n = 0; n < N*N*N; ++n) { - if (!no_output[n]) { - printf("C:\n"); - printMatrix(C[n]); - printf("Gold:\n"); - printMatrix(gold[n]); - printf("\n"); - } - }*/ - - // printf("Checking\n"); - for (int n = 0; n < N * N * N; ++n) - if (!no_output[n] && !is_equal(C[n], gold[n])) { - printf("activation: %d, scale: %d\n", activation, scale); - printf("Actual (%d):\n", n); - printMatrix(C[n]); - printf("\nGold:\n"); - printMatrix(gold[n]); - exit(1); - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/matrix_add.c b/bb-tests/workloads/src/CTest/gemmini/matrix_add.c deleted file mode 100644 index a54a719e..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/matrix_add.c +++ /dev/null @@ -1,72 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" -#include - -int main() { - elem_t A[DIM][DIM]; - elem_t B[DIM][DIM]; - elem_t C[DIM][DIM]; - elem_t gold[DIM][DIM]; - - for (size_t i = 0; i < DIM; i++) - for (size_t j = 0; j < DIM; j++) { - A[i][j] = (rand() % 16) - 8; - B[i][j] = (rand() % 16) - 8; - } - - for (int ascale = -2; ascale < 2; ascale++) { - for (int bscale = -2; bscale < 2; bscale++) { - for (size_t i = 0; i < DIM; i++) - for (size_t j = 0; j < DIM; j++) { - acc_t sum = MVIN_SCALE(A[i][j], ascale) + MVIN_SCALE(B[i][j], bscale); - gold[i][j] = sum > elem_t_max ? elem_t_max - : (sum < elem_t_min ? elem_t_min : sum); - } - - uint32_t A_acc_addr = 1 << (ADDR_LEN - 1); - uint32_t B_acc_addr = (1 << (ADDR_LEN - 1)) | (1 << (ADDR_LEN - 2)); - uint32_t C_acc_addr = 1 << (ADDR_LEN - 1); - - gemmini_extended2_config_ld(DIM * sizeof(elem_t), ascale, true); - gemmini_mvin(A, A_acc_addr); - - gemmini_extended2_config_ld(DIM * sizeof(elem_t), bscale, true); - gemmini_mvin(B, B_acc_addr); - - gemmini_config_ex(0, NO_ACTIVATION, 0); - gemmini_config_st(DIM * sizeof(elem_t)); - gemmini_mvout(C, C_acc_addr); - - gemmini_fence(); - - if (!is_equal(C, gold)) { - printf("Wrong (ascale: %d, bscale: %d)\n", ascale, bscale); - printf("\"C\" matrix:\n"); - printMatrix(C); - printf("\n"); - printf("\"Gold\" matrix:\n"); - printMatrix(gold); - printf("\n"); - printf("\"A\" matrix:\n"); - printMatrix(A); - printf("\n"); - printf("\"B\" matrix:\n"); - printMatrix(B); - printf("\n"); - printf("Wrong (ascale: %d, bscale: %d)\n", ascale, bscale); - exit(1); - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout.c deleted file mode 100644 index a93a258a..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout.c +++ /dev/null @@ -1,62 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define N 8 - -#if (N * DIM) > (BANK_NUM * BANK_ROWS) -#error not enough scratchpad space -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - // printf("Flush\n"); - gemmini_flush(0); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - static elem_t In[N][DIM][DIM] row_align(1); - static elem_t Out[N][DIM][DIM] row_align(1); - - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) - In[n][i][j] = i * DIM + j + n; - - for (size_t n = 0; n < N; ++n) { - // printf("Mvin %d\n", n); - gemmini_mvin(In[n], n * DIM); - // printf("Mvout %d\n", n); - gemmini_mvout(Out[n], n * DIM); - } - - // printf("Fence"); - gemmini_fence(); - - for (size_t n = 0; n < N; ++n) - if (!is_equal(In[n], Out[n])) { - printf("Matrix %u:\n", n); - printMatrix(In[n]); - printf("Matrix %u output:\n", n); - printMatrix(Out[n]); - printf("\n"); - - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc.c deleted file mode 100644 index f3485e53..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc.c +++ /dev/null @@ -1,132 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifdef FAST -#define N 2 -#define AINIT RELU -#define SINIT 12 -#else -#define N 4 -#define AINIT NO_ACTIVATION -#define SINIT 12 -#endif - -#if (N * DIM) > ACC_ROWS -#error not enough accumulator space -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - for (int activation = AINIT; activation <= RELU; ++activation) { - for (int scale = SINIT; scale <= 12; scale += 4) { - // printf("activation: %d, scale: %d\n", activation, scale); - - static acc_t In[N][DIM][DIM] row_align_acc(1); - static full_t In_full[N][DIM][DIM]; - static elem_t Out[N][DIM][DIM] row_align(1); - static elem_t Out_gold[N][DIM][DIM]; - - // printf("Initializing matrices\n"); - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - In[n][i][j] = 0; -#ifdef FAST -#define RAND (j + i) -#else -#define RAND rand() -#endif - int bytes = RAND % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - In[n][i][j] |= (RAND % 255) << (b * 8); - } -#else - acc_t_bits data; - - do { - data = 0; - - int bytes = rand() % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - data |= (uint64_t)(rand() % 255) << (b * 8); - } - - In[n][i][j] = acc_t_bits_to_acc_t(data); - } while (acc_t_isnan(In[n][i][j])); -#endif - - In_full[n][i][j] = In[n][i][j]; - } - - // printf("Shifting and activating matrices\n"); - for (size_t n = 0; n < N; ++n) { - matscale(In_full[n], Out_gold[n], scale); - - if (activation == RELU) - matrelu(Out_gold[n], Out_gold[n]); - } - - const uint32_t acc_addr = 1 << (ADDR_LEN - 1); - - // printf("Config\n"); - gemmini_config_ld(DIM * sizeof(acc_t)); - gemmini_config_ex(0, 0, 0); - gemmini_extended_config_st(DIM * sizeof(elem_t), activation, scale); - - // printf("Mvin and mvout\n"); - for (size_t n = 0; n < N; ++n) { - // printf("Mvin n: %u\n", n); - gemmini_mvin(In[n], acc_addr + n * DIM); - // printf("Mvout n: %u\n", n); - gemmini_mvout(Out[n], acc_addr + n * DIM); - } - - // printf("Fence\n"); - gemmini_fence(); - - // printf("Check\n"); - for (size_t n = 0; n < N; ++n) - if (!is_equal(Out[n], Out_gold[n])) { - printf("activation: %d, scale: %d\n", activation, scale); - - printf("Matrix %u:\n", n); - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", In[n][i][j]); -#else - printf("%llx ", acc_t_to_acc_t_bits(In[n][i][j])); -#endif - printf("\n"); - } - printf("Matrix %u output:\n", n); - printMatrix(Out[n]); - printf("Matrix %u gold output:\n", n); - printMatrix(Out_gold[n]); - printf("\n"); - - exit(1); - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_full.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_full.c deleted file mode 100644 index d0208af7..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_full.c +++ /dev/null @@ -1,119 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define N 4 - -#if (N * DIM) > ACC_ROWS -#error not enough accumulator space -#endif - -int main() { -#ifdef ACC_READ_FULL_WIDTH - -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static acc_t In[N][DIM][DIM] row_align_acc(1); - static acc_t Out[N][DIM][DIM] row_align_acc(1); - - // printf("Initializing matrices\n"); - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - In[n][i][j] = 0; -#ifdef FAST -#define RAND (j + i) -#else -#define RAND rand() -#endif - - int bytes = RAND % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - In[n][i][j] |= (RAND % 255) << (b * 8); - } -#else - acc_t_bits data; - - do { - data = 0; - - int bytes = rand() % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - data |= (uint64_t)(rand() % 255) << (b * 8); - } - - In[n][i][j] = acc_t_bits_to_acc_t(data); - } while (acc_t_isnan(In[n][i][j])); -#endif - } - - const uint32_t acc_addr = 5 << (ADDR_LEN - 3); - - // printf("Config\n"); - gemmini_config_ld(DIM * sizeof(acc_t)); - gemmini_config_ex(0, NO_ACTIVATION, 0); - gemmini_config_st(DIM * sizeof(acc_t)); - - // printf("Mvin and mvout\n"); - for (size_t n = 0; n < N; ++n) { - // printf("Mvin n: %u\n", n); - gemmini_mvin(In[n], acc_addr + n * DIM); - // printf("Mvout n: %u\n", n); - gemmini_mvout(Out[n], acc_addr + n * DIM); - } - - // printf("Fence\n"); - gemmini_fence(); - - // printf("Check\n"); - for (size_t n = 0; n < N; ++n) - if (!MAT_IS_EQUAL(DIM, DIM, Out[n], In[n])) { - printf("Matrix %u:\n", n); - - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", In[n][i][j]); -#else - printf("%llx ", acc_t_to_acc_t_bits(In[n][i][j])); -#endif - printf("\n"); - } - - printf("\nMatrix %u output:\n", n); - - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", Out[n][i][j]); -#else - printf("%llx ", acc_t_to_acc_t_bits(Out[n][i][j])); -#endif - printf("\n"); - } - - printf("\n"); - - exit(1); - } - -#endif // #ifdef ACC_READ_FULL_WIDTH - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_full_stride.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_full_stride.c deleted file mode 100644 index 60ad293b..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_full_stride.c +++ /dev/null @@ -1,177 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifdef FAST -#define BIG_DIM (DIM * 2) -#define BINIT MIN(MAX_BLOCK_LEN_ACC, BIG_DIM / DIM) -#else -#define BIG_DIM 64 -#define BINIT 1 -#endif - -#if (BIG_DIM % DIM) != 0 -#error incorrect dimensions -#endif - -#if (BIG_DIM * BIG_DIM / DIM) > ACC_ROWS -#error not enough accumulator space -#endif - -#define MIN(a, b) ((a > b) ? b : a) - -int is_equal_big(acc_t x[BIG_DIM][BIG_DIM], acc_t y[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) - for (size_t j = 0; j < BIG_DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - if (x[i][j] != y[i][j]) { -#else - bool isnanx = acc_t_isnan(x[i][j]); - bool isnany = acc_t_isnan(y[i][j]); - - if (x[i][j] != y[i][j] && !(isnanx && isnany)) { - printf("x[i][j] == %x\n", acc_t_to_acc_t_bits(x[i][j])); - printf("y[i][j] == %x\n", acc_t_to_acc_t_bits(y[i][j])); - -#endif - printf("Unequal in row %u and column %u\n", i, j); - return 0; - } - } - return 1; -} - -void printMatrix_acc_big(acc_t m[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) { - for (size_t j = 0; j < BIG_DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", m[i][j]); -#else - printf("%llx ", acc_t_to_acc_t_bits(m[i][j])); -#endif - printf("\n"); - } -} - -int main() { -#ifdef ACC_READ_FULL_WIDTH - -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - for (int block_len = BINIT; - block_len <= BIG_DIM / DIM && block_len <= MAX_BLOCK_LEN_ACC; - block_len++) { - static acc_t In[BIG_DIM][BIG_DIM] row_align_acc(1); - static acc_t Out[BIG_DIM][BIG_DIM] row_align(1); - - for (size_t i = 0; i < BIG_DIM; ++i) { - for (size_t j = 0; j < BIG_DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - In[i][j] = 0; -#ifdef FAST -#define RAND (j + i) -#else -#define RAND rand() -#endif - int bytes = RAND % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - In[i][j] |= (RAND % 255) << (b * 8); - } -#else - acc_t_bits data; - - do { - data = 0; - - int bytes = rand() % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - data |= (uint64_t)(rand() % 255) << (b * 8); - } - - In[i][j] = acc_t_bits_to_acc_t(data); - } while (acc_t_isnan(In[i][j])); -#endif - } - } - - const uint32_t acc_addr = 5 << (ADDR_LEN - 3); - - gemmini_config_ld(BIG_DIM * sizeof(acc_t)); - gemmini_config_ex(0, NO_ACTIVATION, 0); - gemmini_config_st(BIG_DIM * sizeof(acc_t)); - - for (size_t i = 0; i < BIG_DIM; i += DIM) { - for (size_t j = 0; j < BIG_DIM; j += DIM) { - // printf("i: %u, j: %u\n", i, j); - - acc_t *dram_addr_in = &In[i][j]; - acc_t *dram_addr_out = &Out[i][j]; - uint32_t sp_addr = acc_addr + i * (BIG_DIM / DIM) + j; - - int already_moved_in = (j / DIM) % block_len != 0; - - if (!already_moved_in) { - int len = - j + block_len * DIM <= BIG_DIM ? block_len : (BIG_DIM - j) / DIM; - // printf("Moving in with len: %d\n", len); - gemmini_block_mvin(dram_addr_in, sp_addr, len); - gemmini_mvout(dram_addr_out, sp_addr); - } else { - // printf("Already moved in\n"); - gemmini_mvout(dram_addr_out, sp_addr); - } - } - } - - // printf("Fence\n"); - gemmini_fence(); - - // printf("Check\n"); - if (!is_equal_big(Out, In)) { - /*printf("Out:\n"); - for (size_t i = 0; i < BIG_DIM; i++) { - for (size_t j = 0; j < BIG_DIM; j++) { - printf("%d, ", Out[i][j]); - } - printf("\n"); - } - - printf("\n"); - - printf("Gold:\n"); - for (size_t i = 0; i < BIG_DIM; i++) { - for (size_t j = 0; j < BIG_DIM; j++) { - printf("%d, ", Out[i][j]); - } - printf("\n"); - }*/ - - printf("Matrix:\n"); - printMatrix_acc_big(In); - printf("Matrix output:\n"); - printMatrix_acc_big(Out); - printf("\n"); - - exit(1); - } - } - -#endif // #ifdef ACC_READ_FULL_WIDTH - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_stride.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_stride.c deleted file mode 100644 index 11e56285..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_stride.c +++ /dev/null @@ -1,235 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define MIN(a, b) ((a > b) ? b : a) - -#ifdef FAST -#define BIG_DIM (DIM * 2) -#define BINIT MIN(MAX_BLOCK_LEN_ACC, BIG_DIM / DIM) -#define AINIT 2 -#define SINIT 12 -#else -#define BIG_DIM 64 -#define BINIT 1 -#define AINIT 0 -#define SINIT 0 -#endif - -#if (BIG_DIM % DIM) != 0 -#error incorrect dimensions -#endif - -#if (BIG_DIM * BIG_DIM / DIM) > ACC_ROWS -#error not enough accumulator space -#endif - -int is_equal_big(elem_t x[BIG_DIM][BIG_DIM], elem_t y[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) - for (size_t j = 0; j < BIG_DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - if (x[i][j] != y[i][j]) { -#else - bool isnanx = elem_t_isnan(x[i][j]); - bool isnany = elem_t_isnan(y[i][j]); - - if (x[i][j] != y[i][j] && !(isnanx && isnany)) { - printf("x[i][j] == %x\n", elem_t_to_elem_t_bits(x[i][j])); - printf("y[i][j] == %x\n", elem_t_to_elem_t_bits(y[i][j])); - -#endif - printf("Unequal in row %u and column %u\n", i, j); - return 0; - } - } - return 1; -} - -void matscale_big(full_t full[BIG_DIM][BIG_DIM], elem_t out[BIG_DIM][BIG_DIM], - acc_scale_t scale) { - for (size_t r = 0; r < BIG_DIM; r++) - for (size_t c = 0; c < BIG_DIM; c++) { - // Scale element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -void matrelu_big(elem_t in[BIG_DIM][BIG_DIM], elem_t out[BIG_DIM][BIG_DIM]) { - for (size_t r = 0; r < BIG_DIM; r++) - for (size_t c = 0; c < BIG_DIM; c++) - out[r][c] = in[r][c] > 0 ? in[r][c] : 0; -} - -void printMatrix_big(elem_t m[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) { - for (size_t j = 0; j < BIG_DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", m[i][j]); -#else - printf("%x ", elem_t_to_elem_t_bits(m[i][j])); -#endif - printf("\n"); - } -} - -void printMatrix_acc_big(acc_t m[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) { - for (size_t j = 0; j < BIG_DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", m[i][j]); -#else - printf("%llx ", acc_t_to_acc_t_bits(m[i][j])); -#endif - printf("\n"); - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - for (int block_len = BINIT; - block_len <= BIG_DIM / DIM && block_len <= MAX_BLOCK_LEN_ACC; - block_len++) { - for (int activation = AINIT; activation <= RELU; ++activation) { - for (int scale = SINIT; scale <= 12; scale += 4) { - // printf("block_len: %d, activation: %d, scale: %d\n", block_len, - // activation, scale); - - static acc_t In[BIG_DIM][BIG_DIM] row_align_acc(1); - static full_t In_full[BIG_DIM][BIG_DIM]; - static elem_t Out[BIG_DIM][BIG_DIM] row_align(1); - static elem_t Out_gold[BIG_DIM][BIG_DIM]; - - for (size_t i = 0; i < BIG_DIM; ++i) { - for (size_t j = 0; j < BIG_DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - In[i][j] = 0; -#ifdef FAST -#define RAND (j + i) -#else -#define RAND rand() -#endif - int bytes = RAND % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - In[i][j] |= (RAND % 255) << (b * 8); - } -#else - acc_t_bits data; - - do { - data = 0; - - int bytes = rand() % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - data |= (uint64_t)(rand() % 255) << (b * 8); - } - - In[i][j] = acc_t_bits_to_acc_t(data); - } while (acc_t_isnan(In[i][j])); -#endif - - In_full[i][j] = In[i][j]; - } - } - - matscale_big(In_full, Out_gold, scale); - - if (activation == RELU) - matrelu_big(Out_gold, Out_gold); - - const uint32_t acc_addr = 1 << (ADDR_LEN - 1); - - gemmini_config_ld(BIG_DIM * sizeof(acc_t)); - gemmini_config_ex(0, 0, 0); - gemmini_extended_config_st(BIG_DIM * sizeof(elem_t), activation, scale); - - for (size_t i = 0; i < BIG_DIM; i += DIM) { - for (size_t j = 0; j < BIG_DIM; j += DIM) { - // printf("i: %u, j: %u\n", i, j); - - acc_t *dram_addr_in = &In[i][j]; - elem_t *dram_addr_out = &Out[i][j]; - uint32_t sp_addr = acc_addr + i * (BIG_DIM / DIM) + j; - - int already_moved_in = (j / DIM) % block_len != 0; - - if (!already_moved_in) { - int len = j + block_len * DIM <= BIG_DIM ? block_len - : (BIG_DIM - j) / DIM; - // printf("Moving in with len: %d\n", len); - gemmini_block_mvin(dram_addr_in, sp_addr, len); - gemmini_mvout(dram_addr_out, sp_addr); - } else { - // printf("Already moved in\n"); - gemmini_mvout(dram_addr_out, sp_addr); - } - } - } - - // printf("Fence\n"); - gemmini_fence(); - - // printf("Check\n"); - if (!is_equal_big(Out, Out_gold)) { - printf("block_len: %d, activation: %d, scale: %d\n", block_len, - activation, scale); - - /*printf("Out:\n"); - for (size_t i = 0; i < BIG_DIM; i++) { - for (size_t j = 0; j < BIG_DIM; j++) { - printf("%d, ", Out[i][j]); - } - printf("\n"); - } - - printf("\n"); - - printf("Gold:\n"); - for (size_t i = 0; i < BIG_DIM; i++) { - for (size_t j = 0; j < BIG_DIM; j++) { - printf("%d, ", Out[i][j]); - } - printf("\n"); - }*/ - - printf("Matrix:\n"); - printMatrix_acc_big(In); - printf("Matrix output:\n"); - printMatrix_big(Out); - printf("Matrix gold output:\n"); - printMatrix_big(Out_gold); - printf("\n"); - - exit(1); - } - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_zero_stride.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_zero_stride.c deleted file mode 100644 index bcb27b1e..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_acc_zero_stride.c +++ /dev/null @@ -1,104 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define N 4 - -#if (N * DIM) > ACC_ROWS -#error not enough accumulator space -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static acc_t In[N][DIM] row_align_acc(1); - static elem_t Out[N][DIM][DIM] row_align(1); - static elem_t Out_gold[N][DIM][DIM]; - - for (size_t n = 0; n < N; ++n) - for (size_t j = 0; j < DIM; ++j) { -#ifndef ELEM_T_IS_FLOAT - In[n][j] = 0; - - int bytes = rand() % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - In[n][j] |= (rand() % 255) << (b * 8); - } -#else - acc_t_bits data; - - do { - data = 0; - - int bytes = rand() % 2 ? sizeof(acc_t) : sizeof(elem_t); - for (size_t b = 0; b < bytes; ++b) { - data |= (uint64_t)(rand() % 255) << (b * 8); - } - - In[n][j] = acc_t_bits_to_acc_t(data); - } while (acc_t_isnan(In[n][j])); -#endif - } - - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { - Out_gold[n][i][j] = ACC_SCALE(In[n][j], ACC_SCALE_IDENTITY); - } - - const uint32_t acc_addr = 1 << (ADDR_LEN - 1); - - // printf("Config\n"); - gemmini_config_ld(0); - gemmini_config_ex(0, NO_ACTIVATION, 0); - gemmini_config_st(DIM * sizeof(elem_t)); - - // printf("Mvin and mvout\n"); - for (size_t n = 0; n < N; ++n) { - // printf("Mvin n: %u\n", n); - gemmini_mvin(In[n], acc_addr + n * DIM); - // printf("Mvout n: %u\n", n); - gemmini_mvout(Out[n], acc_addr + n * DIM); - } - - // printf("Fence\n"); - gemmini_fence(); - - // printf("Check\n"); - for (size_t n = 0; n < N; ++n) - if (!is_equal(Out[n], Out_gold[n])) { - printf("Matrix %u:\n", n); - for (size_t j = 0; j < DIM; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", In[n][j]); -#else - printf("%llx ", acc_t_to_acc_t_bits(In[n][j])); -#endif - printf("\n"); - - printf("Matrix %u output:\n", n); - printMatrix(Out[n]); - printf("Matrix %u gold output:\n", n); - printMatrix(Out_gold[n]); - printf("\n"); - - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_block_stride.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_block_stride.c deleted file mode 100644 index d014b32c..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_block_stride.c +++ /dev/null @@ -1,71 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define BLOCK_STRIDE (DIM * 2) -#define COLS (DIM * MAX_BLOCK_LEN) - -void printMatrixFull(elem_t m[DIM][COLS]) { - for (size_t i = 0; i < DIM; ++i) { - for (size_t j = 0; j < COLS; ++j) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", m[i][j]); -#else - printf("%x ", elem_t_to_elem_t_bits(m[i][j])); -#endif - printf("\n"); - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - static elem_t In[DIM][COLS] row_align(1); - static elem_t Out[DIM][COLS] row_align(1); - - // printf("Flush\n"); - gemmini_flush(0); - gemmini_extended4_config_ld(COLS * sizeof(elem_t), MVIN_SCALE_IDENTITY, false, - BLOCK_STRIDE, 0); - gemmini_config_st(COLS * sizeof(elem_t)); - - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < COLS; ++j) - In[i][j] = i * COLS + j; - - gemmini_block_mvin(In, 0, MAX_BLOCK_LEN); - - gemmini_fence(); - - for (size_t n = 0; n < MAX_BLOCK_LEN; ++n) { - gemmini_mvout((elem_t *)Out + n * DIM, n * BLOCK_STRIDE); - } - - // printf("Fence"); - gemmini_fence(); - - if (!MAT_IS_EQUAL(DIM, COLS, In, Out)) { - printf("Matrix:\n"); - printMatrixFull(In); - printf("\nMatrix output:\n"); - printMatrixFull(Out); - printf("\n"); - - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_stride.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_stride.c deleted file mode 100644 index 3b88b58d..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_stride.c +++ /dev/null @@ -1,116 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define MIN(a, b) ((a > b) ? b : a) -#ifdef FAST -#define BIG_DIM (DIM * 2) -#define BINIT MIN(MAX_BLOCK_LEN_ACC, BIG_DIM / DIM) -#else -#define BIG_DIM 64 -#define BINIT 1 -#endif - -#if (BIG_DIM % DIM) != 0 -#error incorrect dimensions -#endif - -#if (BIG_DIM * BIG_DIM / DIM) > (BANK_ROWS * BANK_NUM) -#error not enough rows -#endif - -int is_equal_big(elem_t x[BIG_DIM][BIG_DIM], elem_t y[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) - for (size_t j = 0; j < BIG_DIM; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void printMatrix_big(elem_t m[BIG_DIM][BIG_DIM]) { - for (size_t i = 0; i < BIG_DIM; ++i) { - for (size_t j = 0; j < BIG_DIM; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - for (int block_len = BINIT; - block_len <= BIG_DIM / DIM && block_len <= MAX_BLOCK_LEN; block_len++) { - // printf("block_len: %d\n", block_len); - - static elem_t In[BIG_DIM][BIG_DIM] row_align(1); - static elem_t Out[BIG_DIM][BIG_DIM] row_align(1); - - for (size_t i = 0; i < BIG_DIM; ++i) - for (size_t j = 0; j < BIG_DIM; ++j) { -#ifdef FAST -#define RAND (j + i) -#else -#define RAND rand() -#endif - In[i][j] = (RAND % 64) - 32; // i*BIG_DIM + j; - Out[i][j] = 0; - } - - gemmini_config_ld(BIG_DIM * sizeof(elem_t)); - gemmini_config_st(BIG_DIM * sizeof(elem_t)); - - for (size_t i = 0; i < BIG_DIM; i += DIM) { - for (size_t j = 0; j < BIG_DIM; j += DIM) { - // printf("i: %u, j: %u\n", i, j); - - elem_t *dram_addr_in = &In[i][j]; - elem_t *dram_addr_out = &Out[i][j]; - uint32_t sp_addr = i * (BIG_DIM / DIM) + j; - - int already_moved_in = (j / DIM) % block_len != 0; - - if (!already_moved_in) { - int len = - j + block_len * DIM <= BIG_DIM ? block_len : (BIG_DIM - j) / DIM; - // printf("Moving in with len: %d\n", len); - gemmini_block_mvin(dram_addr_in, sp_addr, len); - gemmini_mvout(dram_addr_out, sp_addr); - } else { - // printf("Already moved in, so moving out\n"); - gemmini_mvout(dram_addr_out, sp_addr); - } - } - } - - gemmini_fence(); - - if (!is_equal_big(In, Out)) { - printf("fails at block_len: %d\n", block_len); - - // printf("Matrix output:\n"); - // printMatrix_big(Out); - // printf("Matrix gold:\n"); - // printMatrix_big(In); - // printf("\n"); - - exit(1); - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_zeros.c b/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_zeros.c deleted file mode 100644 index f7272065..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_mvout_zeros.c +++ /dev/null @@ -1,52 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - // printf("Flush\n"); - gemmini_flush(0); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - static elem_t Out[DIM][DIM] row_align(1); - - // printf("Mvin %d\n", n); - gemmini_mvin(NULL, 0); - // printf("Mvout %d\n", n); - gemmini_mvout(Out, 0); - - // printf("Fence"); - gemmini_fence(); - - bool success = true; - - for (size_t i = 0; i < DIM; i++) - for (size_t j = 0; j < DIM; j++) - if (Out[i][j] != 0) - success = false; - - if (!success) { - printf("Matrix:\n"); - printMatrix(Out); - printf("\n"); - - exit(1); - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/mvin_scale.c b/bb-tests/workloads/src/CTest/gemmini/mvin_scale.c deleted file mode 100644 index 941328b3..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/mvin_scale.c +++ /dev/null @@ -1,126 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define N 8 - -#if (N * DIM) > (BANK_NUM * BANK_ROWS) -#error not enough scratchpad space -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - // printf("Flush\n"); - gemmini_flush(0); - -#ifdef HAS_MVIN_SCALE - elem_t In[N][DIM][DIM] row_align(1); - elem_t Out[N][DIM][DIM] row_align(1); - - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) - In[n][i][j] = i * DIM + j + n; - - gemmini_config_st(DIM * sizeof(elem_t)); - - for (int n = 0; n < N; ++n) { - gemmini_extended_config_ld(DIM * sizeof(elem_t), n); - gemmini_mvin(In[n], n * DIM); - gemmini_mvout(Out[n], n * DIM); - } - - gemmini_fence(); - - for (int n = 0; n < N; ++n) { - bool is_correct = true; - - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { - if (Out[n][i][j] != (elem_t)(MVIN_SCALE(In[n][i][j], n))) { - is_correct = false; - break; - } - } - - if (!is_correct) { - printf("Matrix %u:\n", n); - printMatrix(In[n]); - printf("Matrix %u output:\n", n); - printMatrix(Out[n]); - printf("\n"); - printf("Scale: %d", n); - - exit(1); - } - } -#endif - -#ifdef HAS_MVIN_ACC_SCALE - acc_t In_acc[N][DIM][DIM] row_align_acc(1); - elem_t Out_acc[N][DIM][DIM] row_align(1); - - const uint64_t acc_addr = (uint64_t)(1) << (ADDR_LEN - 1); - - for (size_t n = 0; n < N; ++n) - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) - In_acc[n][i][j] = i * DIM + j + n; - - gemmini_config_st(DIM * sizeof(elem_t)); - - for (int n = 0; n < N; ++n) { - gemmini_extended_config_ld(DIM * sizeof(acc_t), (n + 1)); - gemmini_mvin(In_acc[n], acc_addr | (n * DIM)); - gemmini_mvout(Out_acc[n], acc_addr | (n * DIM)); - } - - gemmini_fence(); - - for (int n = 0; n < N; ++n) { - bool is_correct = true; - - for (size_t i = 0; i < DIM; ++i) - for (size_t j = 0; j < DIM; ++j) { - // acc_t gold = (n+1) * In_acc[n][i][j]; - acc_t gold = ACC_SCALE(In_acc[n][i][j], n + 1); - if (gold > elem_t_max) { - gold = elem_t_max; - } else if (gold < elem_t_min) { - gold = elem_t_min; - } - - if (Out_acc[n][i][j] != gold) { - is_correct = false; - break; - } - } - - if (!is_correct) { - printf("Accumulator matrix %u:\n", n); - printMatrixAcc(In_acc[n]); - printf("Accumulator matrix %u output:\n", n); - printMatrix(Out_acc[n]); - printf("\n"); - - exit(1); - } - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/padded.c b/bb-tests/workloads/src/CTest/gemmini/padded.c deleted file mode 100644 index 2977d5dd..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/padded.c +++ /dev/null @@ -1,190 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -void print_matrix(size_t rows, size_t cols, elem_t mat[rows][cols]) { - for (size_t r = 0; r < rows; r++) { - for (size_t c = 0; c < cols; c++) -#ifndef ELEM_T_IS_FLOAT - printf("%d ", mat[r][c]); -#else - printf("%x ", elem_t_to_elem_t_bits(mat[r][c])); -#endif - printf("\n"); - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - // Test padded mvins - { - const size_t rows = rand() % (DIM - 1) + 1; - const size_t cols = rand() % (DIM - 1) + 1; - elem_t input[rows][cols]; - elem_t output[DIM][DIM]; - - for (size_t r = 0; r < rows; r++) - for (size_t c = 0; c < cols; c++) -#ifndef ELEM_T_IS_FLOAT - input[r][c] = rand() % elem_t_max; -#else - input[r][c] = rand_double(); -#endif - - const size_t sp_addr = 0; - - gemmini_config_ld(cols * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - gemmini_extended_mvin(input, sp_addr, cols, rows); - gemmini_mvout(output, sp_addr); - gemmini_fence(); - - for (size_t r = 0; r < rows; r++) - for (size_t c = 0; c < cols; c++) - if (input[r][c] != output[r][c]) { - printf("Matrices don't match!\n"); - - printf("input:\n"); - print_matrix(rows, cols, input); - - printf("output:\n"); - printMatrix(output); - - exit(1); - } - } - - // Test padded mvins and padded mvouts - { - const size_t rows = rand() % (DIM - 1) + 1; - const size_t cols = rand() % (DIM - 1) + 1; - elem_t input[rows][cols]; - elem_t output[rows][cols]; - - for (size_t r = 0; r < rows; r++) - for (size_t c = 0; c < cols; c++) -#ifndef ELEM_T_IS_FLOAT - input[r][c] = rand() % elem_t_max; -#else - input[r][c] = rand_double(); -#endif - - const size_t sp_addr = 0; - - gemmini_config_ld(cols * sizeof(elem_t)); - gemmini_config_st(cols * sizeof(elem_t)); - - gemmini_extended_mvin(input, sp_addr, cols, rows); - gemmini_extended_mvout(output, sp_addr, cols, rows); - gemmini_fence(); - - for (size_t r = 0; r < rows; r++) - for (size_t c = 0; c < cols; c++) - if (input[r][c] != output[r][c]) { - printf("Matrices don't match!\n"); - - printf("input:\n"); - print_matrix(rows, cols, input); - - printf("output:\n"); - print_matrix(rows, cols, output); - - exit(1); - } - } - - // Test padded matmuls - for (int dataflow = 0; dataflow <= 1; dataflow++) { - const size_t I = rand() % (DIM - 1) + 1; - const size_t J = rand() % (DIM - 1) + 1; - const size_t K = rand() % (DIM - 1) + 1; - elem_t A[I][K]; - elem_t B[K][J]; - elem_t D[I][J]; - elem_t C[I][J]; - elem_t gold[I][J]; - - for (size_t i = 0; i < I; i++) - for (size_t k = 0; k < K; k++) - A[i][k] = rand() % 5; - - for (size_t k = 0; k < K; k++) - for (size_t j = 0; j < J; j++) - B[k][j] = rand() % 5; - - for (size_t i = 0; i < I; i++) - for (size_t j = 0; j < J; j++) - D[i][j] = rand() % 5; - - for (size_t i = 0; i < I; i++) - for (size_t j = 0; j < J; j++) { - acc_t result = D[i][j]; - for (size_t k = 0; k < K; k++) - result += A[i][k] * B[k][j]; - - gold[i][j] = result < elem_t_min - ? elem_t_min - : (result > elem_t_max ? elem_t_max : result); - } - - const size_t A_sp_addr = 0; - const size_t B_sp_addr = DIM; - const size_t D_sp_addr = 2 * DIM; - const size_t C_sp_addr = 3 * DIM; - - gemmini_config_ex(dataflow, NO_ACTIVATION, 0); - gemmini_config_st(J * sizeof(elem_t)); - - gemmini_config_ld(K * sizeof(elem_t)); - gemmini_extended_mvin(A, A_sp_addr, K, I); - - gemmini_config_ld(J * sizeof(elem_t)); - gemmini_extended_mvin(B, B_sp_addr, J, K); - - gemmini_config_ld(J * sizeof(elem_t)); - gemmini_extended_mvin(D, D_sp_addr, J, I); - - if (dataflow == OUTPUT_STATIONARY) { - gemmini_extended_preload(D_sp_addr, C_sp_addr, J, I, J, I); - gemmini_extended_compute_preloaded(A_sp_addr, B_sp_addr, K, I, J, K); - } else { - gemmini_extended_preload(B_sp_addr, C_sp_addr, J, K, J, I); - gemmini_extended_compute_preloaded(A_sp_addr, D_sp_addr, K, I, J, I); - } - - gemmini_extended_mvout(C, C_sp_addr, J, I); - - gemmini_fence(); - - for (size_t r = 0; r < I; r++) - for (size_t c = 0; c < J; c++) - if (C[r][c] != gold[r][c]) { - printf("Matrices don't match! (dataflow == %d)\n", dataflow); - - printf("C:\n"); - print_matrix(I, J, C); - - printf("gold:\n"); - print_matrix(I, J, gold); - - exit(1); - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/raw_hazard.c b/bb-tests/workloads/src/CTest/gemmini/raw_hazard.c deleted file mode 100644 index b4b57f4d..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/raw_hazard.c +++ /dev/null @@ -1,132 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#if BANK_NUM * BANK_ROWS < 5 * DIM -#error need more memory capacity -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - - const int a_additions = 10; - const int b_additions = 10; - const int d_additions = 10; - - static elem_t IDENTITY[DIM][DIM] row_align(1); - - static elem_t result_A[DIM][DIM] row_align(1); - static elem_t result_B[DIM][DIM] row_align(1); - static elem_t result_D[DIM][DIM] row_align(1); - - static elem_t gold_A[DIM][DIM]; - static elem_t gold_B[DIM][DIM]; - static elem_t gold_D[DIM][DIM]; - - for (size_t i = 0; i < DIM; i++) { - for (size_t j = 0; j < DIM; j++) { - IDENTITY[i][j] = i == j; - gold_A[i][j] = i == j ? (a_additions + 1) : 0; - gold_B[i][j] = i == j ? (b_additions + 1) : 0; - gold_D[i][j] = i == j ? (d_additions + 1) : 0; - } - } - - int IDENTITY1_addr = 0; - int IDENTITY2_addr = DIM; - int A_addr = 2 * DIM; - int B_addr = 3 * DIM; - int D_addr = 4 * DIM; - - // printf("Moving in\n"); - gemmini_mvin(IDENTITY, IDENTITY1_addr); - gemmini_mvin(IDENTITY, IDENTITY2_addr); - gemmini_mvin(IDENTITY, A_addr); - gemmini_mvin(IDENTITY, B_addr); - gemmini_mvin(IDENTITY, D_addr); - - // printf("Setting mode\n"); - gemmini_config_ex(OUTPUT_STATIONARY, 0, 0); - - // printf("RAW with A\n"); - for (int i = 0; i < a_additions; i++) { - // printf(" %d\n", i); - - gemmini_preload(IDENTITY1_addr, A_addr); - gemmini_compute_preloaded(A_addr, IDENTITY2_addr); - } - - // printf("RAW with B\n"); - for (int i = 0; i < b_additions; i++) { - gemmini_preload(IDENTITY1_addr, B_addr); - gemmini_compute_preloaded(IDENTITY2_addr, B_addr); - } - - // printf("RAW with D\n"); - for (int i = 0; i < d_additions; i++) { - gemmini_preload(D_addr, D_addr); - gemmini_compute_preloaded(IDENTITY1_addr, IDENTITY2_addr); - } - - // printf("Moving out A\n"); - gemmini_mvout(result_A, A_addr); - // printf("Moving out B\n"); - gemmini_mvout(result_B, B_addr); - // printf("Moving out D\n"); - gemmini_mvout(result_D, D_addr); - - // printf("Fencing\n"); - gemmini_fence(); - - // printf("Checking\n"); - int fail = 0; - - if (!is_equal(result_A, gold_A)) { - printf("A:\n"); - printMatrix(result_A); - printf("\n"); - // printMatrix(gold_A); - // printf("\n"); - - fail = 1; - } - - if (!is_equal(result_B, gold_B)) { - printf("B:\n"); - printMatrix(result_B); - printf("\n"); - // printMatrix(gold_B); - // printf("\n"); - - fail = 1; - } - - if (!is_equal(result_D, gold_D)) { - printf("D:\n"); - printMatrix(result_D); - printf("\n"); - // printMatrix(gold_D); - // printf("\n"); - - fail = 1; - } - - exit(fail); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/resadd.c b/bb-tests/workloads/src/CTest/gemmini/resadd.c deleted file mode 100644 index e5d462d7..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/resadd.c +++ /dev/null @@ -1,105 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 0 // 1 - -#ifndef BAREMETAL - -#define MAT_DIM_I 128 -#define MAT_DIM_J 512 - -#else -#define MAT_DIM_I 35 -#define MAT_DIM_J 27 -#endif - -#define A_SCALE 2 -#define B_SCALE MVIN_SCALE_IDENTITY -#define C_SCALE ACC_SCALE_IDENTITY -#define USE_RELU true - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("I: %d, J: %d\n", MAT_DIM_I, MAT_DIM_J); - - gemmini_flush(0); - - static elem_t A[MAT_DIM_I][MAT_DIM_J] row_align(1); - static elem_t B[MAT_DIM_I][MAT_DIM_J] row_align(1); - static elem_t C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A and B\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - A[i][j] = (rand() % 64) - 32; - B[i][j] = (rand() % 8) - 4; - } - } - - printf("Starting slow CPU resadd\n"); - unsigned long cpu_start = read_cycles(); - resadd_cpu(MAT_DIM_I, MAT_DIM_J, A_SCALE, B_SCALE, C_SCALE, (elem_t *)A, - (elem_t *)B, (elem_t *)gold, USE_RELU); - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); -#endif - - printf("Starting gemmini resadd\n"); - unsigned long start = read_cycles(); - tiled_resadd_auto(MAT_DIM_I, MAT_DIM_J, A_SCALE, B_SCALE, C_SCALE, - (elem_t *)A, (elem_t *)B, (elem_t *)C, USE_RELU, WS); - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(C, gold)) { - printf("C:\n"); - full_printMatrix(C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("A:\n"); - full_printMatrix(A); - printf("B:\n"); - full_printMatrix(B); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/resadd_stride.c b/bb-tests/workloads/src/CTest/gemmini/resadd_stride.c deleted file mode 100644 index 94056538..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/resadd_stride.c +++ /dev/null @@ -1,108 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#ifndef BAREMETAL - -#define MAT_DIM_I 128 -#define MAT_DIM_J 251 - -#else -#define MAT_DIM_I 54 -#define MAT_DIM_J 27 -#endif - -#define J_STRIDE (MAT_DIM_J + 5) - -#define A_SCALE 2 -#define B_SCALE MVIN_SCALE_IDENTITY -#define C_SCALE ACC_SCALE_IDENTITY -#define USE_RELU true - -void full_printMatrix(elem_t m[MAT_DIM_I][J_STRIDE]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][J_STRIDE], - elem_t y[MAT_DIM_I][J_STRIDE]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("I: %d, J: %d\n", MAT_DIM_I, MAT_DIM_J); - - gemmini_flush(0); - - static elem_t A[MAT_DIM_I][J_STRIDE] row_align(1) = {0}; - static elem_t B[MAT_DIM_I][J_STRIDE] row_align(1) = {0}; - static elem_t C[MAT_DIM_I][J_STRIDE] row_align(1) = {0}; - static elem_t gold[MAT_DIM_I][J_STRIDE] = {0}; - -#if CHECK_RESULT == 1 - // printf("Init A and B\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - A[i][j] = (rand() % 64) - 32; - B[i][j] = (rand() % 8) - 4; - } - } - - printf("Starting slow CPU resadd\n"); - unsigned long cpu_start = read_cycles(); - resadd_cpu(MAT_DIM_I, MAT_DIM_J, J_STRIDE, A_SCALE, B_SCALE, C_SCALE, - (elem_t *)A, (elem_t *)B, (elem_t *)gold, USE_RELU); - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); -#endif - - printf("Starting gemmini resadd\n"); - unsigned long start = read_cycles(); - tiled_resadd_stride_auto(MAT_DIM_I, MAT_DIM_J, A_SCALE, B_SCALE, C_SCALE, - J_STRIDE, (elem_t *)A, (elem_t *)B, (elem_t *)C, - USE_RELU, WS); - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(C, gold)) { - printf("C:\n"); - full_printMatrix(C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("A:\n"); - full_printMatrix(A); - printf("B:\n"); - full_printMatrix(B); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/rocc-software/.gitignore b/bb-tests/workloads/src/CTest/gemmini/rocc-software/.gitignore deleted file mode 100644 index 8bf29476..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/rocc-software/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -*~ -*# -*.#* diff --git a/bb-tests/workloads/src/CTest/gemmini/rocc-software/CONTRIBUTING.md b/bb-tests/workloads/src/CTest/gemmini/rocc-software/CONTRIBUTING.md deleted file mode 100644 index 6e97de44..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/rocc-software/CONTRIBUTING.md +++ /dev/null @@ -1,46 +0,0 @@ -All contributors must agree to the Developer Certificate of Origin Version 1.1. (DCO 1.1) by signing their commits with: - -``` -DCO 1.1 Signed-off-by: [NAME] <[EMAIL]> -``` - -The full text of the DCO 1.1 is as follows: - -``` -Developer Certificate of Origin -Version 1.1 - -Copyright (C) 2004, 2006 The Linux Foundation and its contributors. -660 York Street, Suite 102, -San Francisco, CA 94110 USA - -Everyone is permitted to copy and distribute verbatim copies of this -license document, but changing it is not allowed. - - -Developer's Certificate of Origin 1.1 - -By making a contribution to this project, I certify that: - -(a) The contribution was created in whole or in part by me and I -have the right to submit it under the open source license -indicated in the file; or - -(b) The contribution is based upon previous work that, to the best -of my knowledge, is covered under an appropriate open source -license and I have the right under that license to submit that -work with modifications, whether created in whole or in part -by me, under the same open source license (unless I am -permitted to submit under a different license), as indicated -in the file; or - -(c) The contribution was provided directly to me by some other -person who certified (a), (b) or (c) and I have not modified -it. - -(d) I understand and agree that this project and the contribution -are public and that a record of the contribution (including all -personal information I submit with it, including my sign-off) is -maintained indefinitely and may be redistributed consistent with -this project or the open source license(s) involved. -``` diff --git a/bb-tests/workloads/src/CTest/gemmini/rocc-software/LICENSE b/bb-tests/workloads/src/CTest/gemmini/rocc-software/LICENSE deleted file mode 100644 index 8dada3ed..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/rocc-software/LICENSE +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright {yyyy} {name of copyright owner} - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/bb-tests/workloads/src/CTest/gemmini/rocc-software/README.md b/bb-tests/workloads/src/CTest/gemmini/rocc-software/README.md deleted file mode 100644 index 237b3902..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/rocc-software/README.md +++ /dev/null @@ -1,4 +0,0 @@ -Rocket Custom Coprocessor (RoCC) Software -======================================== - -This is a set of C and RISC-V Assembly macros that help with emitting custom RISC-V instructions for talking with Rocket Custom Coprocessors (RoCCs). diff --git a/bb-tests/workloads/src/CTest/gemmini/rocc-software/src/riscv_test_rocc.h b/bb-tests/workloads/src/CTest/gemmini/rocc-software/src/riscv_test_rocc.h deleted file mode 100644 index 0dbd9109..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/rocc-software/src/riscv_test_rocc.h +++ /dev/null @@ -1,26 +0,0 @@ -// Copyright 2018 IBM -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef ROCC_SOFTWARE_SRC_RISCV_TEST_ROCC_H_ -#define ROCC_SOFTWARE_SRC_RISCV_TEST_ROCC_H_ - -#define RVTEST_XS_ENABLE \ - li a0, MSTATUS_XS &(MSTATUS_XS >> 1); \ - csrs mstatus, a0; - -#define RVTEST_WITH_ROCC \ - .macro init; \ - RVTEST_XS_ENABLE.endm - -#endif // ROCC_SOFTWARE_SRC_RISCV_TEST_ROCC_H_ diff --git a/bb-tests/workloads/src/CTest/gemmini/rocc-software/src/xcustom.h b/bb-tests/workloads/src/CTest/gemmini/rocc-software/src/xcustom.h deleted file mode 100644 index 1880ff56..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/rocc-software/src/xcustom.h +++ /dev/null @@ -1,170 +0,0 @@ -// Copyright 2018--2020 IBM -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef ROCC_SOFTWARE_SRC_XCUSTOM_H_ -#define ROCC_SOFTWARE_SRC_XCUSTOM_H_ - -#define STR1(x) #x -#ifndef STR -#define STR(x) STR1(x) -#endif - -#define CAT_(A, B) A##B -#define CAT(A, B) CAT_(A, B) - -/** Assembly macro for creating "raw" Rocket Custom Coproessor (RoCC) - * assembly language instructions that will return data in rd. These - * are to be used only in assembly language programs (not C/C++). - * - * Example: - * - * Consider the following macro consisting of a CUSTOM_0 instruction - * with func7 "42" that is doing some operation of "a0 = op(a1, a2)": - * - * ROCC_INSTRUCTION_RAW_R_R_R(0, a0, a1, a2, 42) - * - * This will produce the following pseudo assembly language - * instruction: - * - * .insn r CUSTOM_0, 7, 42, a0, a1, a2 - * - * @param x the custom instruction number: 0, 1, 2, or 3 - * @param rd the destination register, e.g., a0 or x10 - * @param rs1 the first source register, e.g., a0 or x10 - * @param rs2 the second source register, e.g., a0 or x10 - * @param func7 the value of the func7 field - * @return a raw .insn RoCC instruction - */ -#define ROCC_INSTRUCTION_RAW_R_R_R(x, rd, rs1, rs2, func7) \ - .insn r CAT(CUSTOM_, x), 7, func7, rd, rs1, rs2 - -/** Assembly macro for creating "raw" Rocket Custom Coproessor (RoCC) - * assembly language instructions that will *NOT* return data in rd. - * These are to be used only in assembly language programs (not - * C/C++). - * - * Example: - * - * Consider the following macro consisting of a CUSTOM_1 instruction - * with func7 "42" that is doing some operation of "op(a1, a2)". *NO* - * data is returned: - * - * ROCC_INSTRUCTION_RAW_R_R_R(1, a1, a2, 42) - * - * This will produce the following pseudo assembly language - * instruction: - * - * .insn r CUSTOM_1, 3, 42, x0, a1, a2 - * - * @param x the custom instruction number: 0, 1, 2, or 3 - * @param rs1 the first source register, e.g., a0 or x10 - * @param rs2 the second source register, e.g., a0 or x10 - * @param func7 the value of the func7 field - * @return a raw .insn RoCC instruction - */ -#define ROCC_INSTRUCTION_RAW_0_R_R(x, rs1, rs2, func7) \ - .insn r CAT(CUSTOM_, x), 3, func7, x0, rs1, rs2 - -/** C/C++ inline assembly macro for creating Rocket Custom Coprocessor - * (RoCC) instructions that return data in rd. These are to be used - * only in C/C++ programs (not bare assembly). - * - * This is equivalent to ROCC_INSTRUCTION_R_R_R. See it's - * documentation. - */ -#define ROCC_INSTRUCTION(x, rd, rs1, rs2, func7) \ - ROCC_INSTRUCTION_R_R_R(x, rd, rs1, rs2, func7) - -/** C/C++ inline assembly macro for creating Rocket Custom Coprocessor - * (RoCC) instructions that return data in C variable rd. - * These are to be used only in C/C++ programs (not bare assembly). - * - * Example: - * - * Consider the following macro consisting of a CUSTOM_2 instruction - * with func7 "42" that is doing some operation of "a0 = op(a1, a2)" - * (where a0, a1, and a2 are variables defined in C): - * - * ROCC_INSTRUCTION(2, a0, a1, a2, 42) - * - * This will produce the following inline assembly: - * - * asm volatile( - * ".insn r CUSTOM_2, 0x7, 42, %0, %1, %2" - * : "=r"(rd) - * : "r"(rs1), "r"(rs2)); - * - * @param x the custom instruction number: 0, 1, 2, or 3 - * @param rd the C variable to capture as destination operand - * @param rs1 the C variable to capture for first source register - * @param rs2 the C variable to capture for second source register - * @param func7 the value of the func7 field - * @return an inline assembly RoCC instruction - */ -#define ROCC_INSTRUCTION_R_R_R(x, rd, rs1, rs2, func7) \ - { \ - asm volatile(".insn r " STR(CAT(CUSTOM_, x)) ", " STR(0x7) ", " STR( \ - func7) ", %0, %1, %2" \ - : "=r"(rd) \ - : "r"(rs1), "r"(rs2)); \ - } - -/** C/C++ inline assembly macro for creating Rocket Custom Coprocessor - * (RoCC) instructions that return data in C variable rd. - * These are to be used only in C/C++ programs (not bare assembly). - * - * Example: - * - * Consider the following macro consisting of a CUSTOM_3 instruction - * with func7 "42" that is doing some operation of "a0 = op(a1, a2)" - * (where a0, a1, and a2 are variables defined in C): - * - * ROCC_INSTRUCTION(3, a0, a1, a2, 42) - * - * This will produce the following inline assembly: - * - * asm volatile( - * ".insn r CUSTOM_3, 0x7, 42, %0, %1, %2" - * :: "r"(rs1), "r"(rs2)); - * - * @param x the custom instruction number: 0, 1, 2, or 3 - * @param rs1 the C variable to capture for first source register - * @param rs2 the C variable to capture for second source register - * @param funct7 the value of the funct7 f - * @return an inline assembly RoCC instruction - */ -#define ROCC_INSTRUCTION_0_R_R(x, rs1, rs2, func7) \ - { \ - asm volatile(".insn r " STR(CAT(CUSTOM_, x)) ", " STR(0x3) ", " STR( \ - func7) ", x0, %0, %1" \ - : \ - : "r"(rs1), "r"(rs2)); \ - } - -// [TODO] fix these to align with the above approach -// Macro to pass rs2_ as an immediate -/* -#define ROCC_INSTRUCTION_R_R_I(XCUSTOM_, rd_, rs1_, rs2_, funct_) \ - asm volatile (XCUSTOM_" %[rd], %[rs1], %[rs2], %[funct]" \ - : [rd] "=r" (rd_) \ - : [rs1] "r" (rs1_), [rs2] "i" (rs2_), [funct] "i" (funct_)) - -// Macro to pass rs1_ and rs2_ as immediates -#define ROCC_INSTRUCTION_R_I_I(XCUSTOM_, rd_, rs1_, rs2_, funct_) \ - asm volatile (XCUSTOM_" %[rd], %[rs1], %[rs2], %[funct]" \ - : [rd] "=r" (rd_) \ - : [rs1] "i" (rs1_), [rs2] "i" (rs2_), [funct] "i" (funct_)) -*/ - -#endif // ROCC_SOFTWARE_SRC_XCUSTOM_H_ diff --git a/bb-tests/workloads/src/CTest/gemmini/template.c b/bb-tests/workloads/src/CTest/gemmini/template.c deleted file mode 100644 index f8026e6c..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/template.c +++ /dev/null @@ -1,75 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("Flush Gemmini TLB of stale virtual addresses\n"); - gemmini_flush(0); - - printf("Initialize our input and output matrices in main memory\n"); - elem_t In[DIM][DIM]; - elem_t Out[DIM][DIM]; - - elem_t Identity[DIM][DIM]; - for (size_t i = 0; i < DIM; i++) - for (size_t j = 0; j < DIM; j++) - Identity[i][j] = i == j; - - printf("Calculate the scratchpad addresses of all our matrices\n"); - printf(" Note: The scratchpad is \"row-addressed\", where each address " - "contains one matrix row\n"); - size_t In_sp_addr = 0; - size_t Out_sp_addr = DIM; - size_t Identity_sp_addr = 2 * DIM; - - printf("Move \"In\" matrix from main memory into Gemmini's scratchpad\n"); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - gemmini_mvin(In, In_sp_addr); - - printf( - "Move \"Identity\" matrix from main memory into Gemmini's scratchpad\n"); - gemmini_mvin(Identity, Identity_sp_addr); - - printf("Multiply \"In\" matrix with \"Identity\" matrix with a bias of 0\n"); - gemmini_config_ex(OUTPUT_STATIONARY, 0, 0); - gemmini_preload_zeros(Out_sp_addr); - gemmini_compute_preloaded(In_sp_addr, Identity_sp_addr); - - printf("Move \"Out\" matrix from Gemmini's scratchpad into main memory\n"); - gemmini_config_st(DIM * sizeof(elem_t)); - gemmini_mvout(Out, Out_sp_addr); - - printf("Fence till Gemmini completes all memory operations\n"); - gemmini_fence(); - - printf("Check whether \"In\" and \"Out\" matrices are identical\n"); - if (!is_equal(In, Out)) { - printf("Input and output matrices are different!\n"); - printf("\"In\" matrix:\n"); - printMatrix(In); - printf("\"Out\" matrix:\n"); - printMatrix(Out); - printf("\n"); - - exit(1); - } - - printf("Input and output matrices are identical, as expected\n"); - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_cpu.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_cpu.c deleted file mode 100644 index 10b6840f..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_cpu.c +++ /dev/null @@ -1,167 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#error variable-bitwidth bias not currently supported -#endif - -#ifndef BAREMETAL -#define MAT_DIM_I 512 -#define MAT_DIM_K 512 -#define MAT_DIM_J 512 -#else -#define MAT_DIM_I 64 -#define MAT_DIM_K 64 -#define MAT_DIM_J 64 -#endif - -void print_tile(elem_t *in, int tile_dim) { - for (size_t r = 0; r < tile_dim; r++) { - printf("row starts at: %p\n", in + r * MAT_DIM_J); - for (size_t c = 0; c < tile_dim; c++) { - printf("%d ", *(in + r * MAT_DIM_J + c)); - } - printf("\n"); - } -} - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_K][MAT_DIM_J], - ACC_T D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void full_matscale(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], acc_scale_t scale) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Scale element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc( - 1); // TODO don't use row_align_acc when ACC_T is elem_t - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = rand() % 2; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = rand() % 2; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : rand() % 2; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); - full_matmul(full_A, full_B, full_D, gold_full); - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - full_matscale(gold_full, gold, ACC_SCALE_IDENTITY); -#endif - - printf("Starting fast CPU matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, false, false, false, false, 0, CPU); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_option.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_option.c deleted file mode 100644 index bde638c8..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_option.c +++ /dev/null @@ -1,245 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#ifndef BAREMETAL -#define MAT_DIM_I 300 -#define MAT_DIM_K 200 -#define MAT_DIM_J 100 -#else -#define MAT_DIM_I 33 -#define MAT_DIM_K 28 -#define MAT_DIM_J 32 -#endif - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_K][MAT_DIM_J], - acc_t D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J], bool repeating_bias) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[repeating_bias ? 0 : r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -void full_matmul_At(elem_t A[MAT_DIM_K][MAT_DIM_I], - elem_t B[MAT_DIM_K][MAT_DIM_J], - acc_t D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J], bool repeating_bias) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[repeating_bias ? 0 : r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[k][r] * B[k][c]; - } -} - -void full_matmul_Bt(elem_t A[MAT_DIM_I][MAT_DIM_K], - elem_t B[MAT_DIM_J][MAT_DIM_K], - acc_t D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J], bool repeating_bias) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[repeating_bias ? 0 : r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[c][k]; - } -} - -void full_matmul_At_Bt(elem_t A[MAT_DIM_K][MAT_DIM_I], - elem_t B[MAT_DIM_J][MAT_DIM_K], - acc_t D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J], - bool repeating_bias) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[repeating_bias ? 0 : r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[k][r] * B[c][k]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -void full_printMatrix64Bit(full_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%lld ", m[i][j]); - printf("\n"); - } -} - -void full_matscale(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], acc_scale_t scale) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Bitshift and round element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -void full_matrelu(elem_t in[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) - out[r][c] = in[r][c] > 0 ? in[r][c] : 0; -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - -#ifdef BAREMETAL - for (enum tiled_matmul_type_t option = OS; option <= WS; option++) { - for (int activation = 0; activation <= 1; activation++) { - for (int scale = 0; scale <= 1; scale += 1) { -#else - for (enum tiled_matmul_type_t option = OS; option <= CPU; option++) { - for (int activation = 0; activation <= 2; activation++) { - for (int scale = 0; scale <= 12; scale += 6) { -#endif - for (int no_bias = 0; no_bias < 2; no_bias++) { - for (int repeating_bias = 0; repeating_bias < 2; repeating_bias++) { - for (int a_transpose = 0; a_transpose < 2; a_transpose++) { - for (int b_transpose = 0; b_transpose < 2; b_transpose++) { - - if (((option == OS || option == CPU) && - (a_transpose || b_transpose)) || - (option == WS && a_transpose && b_transpose)) { - continue; - } - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static acc_t full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = (rand() % 3) - 1; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = (rand() % 3) - 1; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < (repeating_bias ? 1 : MAT_DIM_I); ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = no_bias ? 0 : ((rand() % 3) - 1); - } - } - -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wincompatible-pointer-types" - printf("Starting CPU matmul\n"); - if (!a_transpose && !b_transpose) { - full_matmul(full_A, full_B, full_D, gold_full, - repeating_bias); - } else if (a_transpose && !b_transpose) { - full_matmul_At(full_A, full_B, full_D, gold_full, - repeating_bias); - } else if (!a_transpose && b_transpose) { - full_matmul_Bt(full_A, full_B, full_D, gold_full, - repeating_bias); - } else if (a_transpose && b_transpose) { - full_matmul_At_Bt(full_A, full_B, full_D, gold_full, - repeating_bias); - } - full_matscale(gold_full, gold, scale); -#pragma GCC diagnostic pop - - if (activation == RELU) { - full_matrelu(gold, gold); - } - - size_t stride_A = a_transpose ? MAT_DIM_I : MAT_DIM_K; - size_t stride_B = b_transpose ? MAT_DIM_K : MAT_DIM_J; - - printf("Starting gemmini matmul\n"); - tiled_matmul_auto( - MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, no_bias ? NULL : &full_D[0][0], - (elem_t *)full_C, stride_A, stride_B, MAT_DIM_J, MAT_DIM_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, activation, scale, 0, repeating_bias, - a_transpose, b_transpose, false, false, 0, option); - - if (!full_is_equal(full_C, gold)) { - printf("\nINCORRECT!\n"); - printf("option: %d\n", option); - printf("activation: %d\n", activation); - printf("scale: %d\n", scale); - printf("no_bias: %d\n", no_bias); - printf("repeating_bias: %d\n", repeating_bias); - printf("a_transpose: %d\n", a_transpose); - printf("b_transpose: %d\n", b_transpose); - - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("Gold full:\n"); - full_printMatrix64Bit(gold_full); - printf("\n"); - - exit(1); - } - } - } - } - } - } - } - } - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_os.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_os.c deleted file mode 100644 index ce28bfb4..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_os.c +++ /dev/null @@ -1,180 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#error variable-bitwidth bias not currently supported -#endif - -#ifndef BAREMETAL -#define MAT_DIM_I 512 -#define MAT_DIM_K 512 -#define MAT_DIM_J 512 -#else -#define MAT_DIM_I 64 -#define MAT_DIM_K 64 -#define MAT_DIM_J 64 -#endif - -void print_tile(elem_t *in, int tile_dim) { - for (size_t r = 0; r < tile_dim; r++) { - printf("row starts at: %p\n", in + r * MAT_DIM_J); - for (size_t c = 0; c < tile_dim; c++) { - printf("%d ", *(in + r * MAT_DIM_J + c)); - } - printf("\n"); - } -} - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_K][MAT_DIM_J], - ACC_T D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void full_matshift(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], int shift) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Bitshift and round element - full_t shifted = ROUNDING_RIGHT_SHIFT(full[r][c], shift); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = shifted > elem_t_max - ? elem_t_max - : (shifted < elem_t_min ? elem_t_min : shifted); - out[r][c] = elem; -#else - out[r][c] = shifted; // TODO should we also saturate when using floats? -#endif - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); -#ifdef FAST -#define RAND 1 -#else -#define RAND rand() -#endif - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = RAND % 2; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = RAND % 2; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : RAND % 2; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); -#ifndef FAST - full_matmul(full_A, full_B, full_D, gold_full); -#else - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - gold_full[i][j] = MAT_DIM_K + (NO_BIAS ? 0 : (RAND % 2)); - } - } - -#endif - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - full_matshift(gold_full, gold, 0); -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, false, false, false, false, 0, OS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws.c deleted file mode 100644 index dd07cd5f..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws.c +++ /dev/null @@ -1,182 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifndef BAREMETAL -#define MAT_DIM_I 512 -#define MAT_DIM_K 512 -#define MAT_DIM_J 512 -#else -#define MAT_DIM_I 64 -#define MAT_DIM_K 64 -#define MAT_DIM_J 64 -#endif - -void print_tile(elem_t *in, int tile_dim) { - for (size_t r = 0; r < tile_dim; r++) { - printf("row starts at: %p\n", in + r * MAT_DIM_J); - for (size_t c = 0; c < tile_dim; c++) { - printf("%d ", *(in + r * MAT_DIM_J + c)); - } - printf("\n"); - } -} - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_K][MAT_DIM_J], - ACC_T D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void full_matscale(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], acc_scale_t scale) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Scale element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("MAT_DIM_I: %d\n", MAT_DIM_I); - printf("MAT_DIM_J: %d\n", MAT_DIM_J); - printf("MAT_DIM_K: %d\n", MAT_DIM_K); - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 -#ifdef FAST -#define RAND 1 -#else -#define RAND rand() -#endif - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = RAND % 2; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = RAND % 2; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : RAND % 2; - } - } - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, false, false, false, !FULL_BIAS_WIDTH, 0, WS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); -#ifdef FAST - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - gold_full[i][j] = MAT_DIM_K + (NO_BIAS ? 0 : (RAND % 2)); - } - } - -#else - full_matmul(full_A, full_B, full_D, gold_full); -#endif - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - full_matscale(gold_full, gold, ACC_SCALE_IDENTITY); -#endif - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_At.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_At.c deleted file mode 100644 index 847efb8a..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_At.c +++ /dev/null @@ -1,200 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifdef FAST - -#define MAT_DIM_I 19 -#define MAT_DIM_K 18 -#define MAT_DIM_J 17 - -#else - -#ifndef BAREMETAL -#define MAT_DIM_I 500 -#define MAT_DIM_K 412 -#define MAT_DIM_J 300 -#else -#define MAT_DIM_I 60 -#define MAT_DIM_K 50 -#define MAT_DIM_J 30 -#endif - -#endif // ifdef FAST - -void print_tile(elem_t *in, int tile_dim) { - for (size_t r = 0; r < tile_dim; r++) { - printf("row starts at: %p\n", in + r * MAT_DIM_J); - for (size_t c = 0; c < tile_dim; c++) { - printf("%d ", *(in + r * MAT_DIM_J + c)); - } - printf("\n"); - } -} - -void full_matmul(elem_t A[MAT_DIM_K][MAT_DIM_I], elem_t B[MAT_DIM_K][MAT_DIM_J], - ACC_T D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[k][r] * B[k][c]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void full_matscale(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], acc_scale_t scale) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Scale element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_K][MAT_DIM_I] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_I; ++j) { -#ifdef FAST - full_A[i][j] = 1; -#else - full_A[i][j] = rand() % 2; -#endif - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { -#ifdef FAST - full_B[i][j] = 1; -#else - full_B[i][j] = rand() % 2; -#endif - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { -#ifdef FAST - full_D[i][j] = NO_BIAS ? 0 : 1; -#else - full_D[i][j] = NO_BIAS ? 0 : rand() % 2; -#endif - } - } - -#ifdef FAST - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - gold[i][j] = MAT_DIM_K + !NO_BIAS; - } - } -#else - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); - full_matmul(full_A, full_B, full_D, gold_full); - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - full_matscale(gold_full, gold, ACC_SCALE_IDENTITY); -#endif // #ifdef FAST - -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_I, MAT_DIM_J, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, true, false, false, !FULL_BIAS_WIDTH, 0, WS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); -#ifdef FAST - printf("All elements must be %d\n", MAT_DIM_K + !NO_BIAS); -#else - full_printMatrix(gold); - printf("\n"); -#endif // ifdef FAST - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_Bt.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_Bt.c deleted file mode 100644 index cb47be42..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_Bt.c +++ /dev/null @@ -1,201 +0,0 @@ - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifdef FAST - -#define MAT_DIM_I 19 -#define MAT_DIM_K 18 -#define MAT_DIM_J 17 - -#else - -#ifndef BAREMETAL -#define MAT_DIM_I 500 -#define MAT_DIM_K 412 -#define MAT_DIM_J 300 -#else -#define MAT_DIM_I 60 -#define MAT_DIM_K 50 -#define MAT_DIM_J 30 - -#endif - -#endif // ifdef FAST - -void print_tile(elem_t *in, int tile_dim) { - for (size_t r = 0; r < tile_dim; r++) { - printf("row starts at: %p\n", in + r * MAT_DIM_J); - for (size_t c = 0; c < tile_dim; c++) { - printf("%d ", *(in + r * MAT_DIM_J + c)); - } - printf("\n"); - } -} - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_J][MAT_DIM_K], - ACC_T D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[c][k]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void full_matscale(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], acc_scale_t scale) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Scale element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_J][MAT_DIM_K] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { -#ifdef FAST - full_A[i][j] = 1; -#else - full_A[i][j] = rand() % 2; -#endif - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_J; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { -#ifdef FAST - full_B[i][j] = 1; -#else - full_B[i][j] = rand() % 2; -#endif - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { -#ifdef FAST - full_D[i][j] = NO_BIAS ? 0 : 1; -#else - full_D[i][j] = NO_BIAS ? 0 : rand() % 2; -#endif - } - } - -#ifdef FAST - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - gold[i][j] = MAT_DIM_K + !NO_BIAS; - } - } -#else - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); - full_matmul(full_A, full_B, full_D, gold_full); - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - full_matscale(gold_full, gold, ACC_SCALE_IDENTITY); -#endif // #ifdef FAST - -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_K, MAT_DIM_K, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, false, true, false, !FULL_BIAS_WIDTH, 0, WS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - - printf("Gold:\n"); -#ifdef FAST - printf("All elements must be %d\n", MAT_DIM_K + !NO_BIAS); -#else - full_printMatrix(gold); - printf("\n"); -#endif // ifdef FAST - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_full_C.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_full_C.c deleted file mode 100644 index 87c7e277..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_full_C.c +++ /dev/null @@ -1,149 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifndef BAREMETAL -#define MAT_DIM_I 512 -#define MAT_DIM_K 512 -#define MAT_DIM_J 512 -#else -#define MAT_DIM_I 60 -#define MAT_DIM_K 40 -#define MAT_DIM_J 30 -#endif - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_K][MAT_DIM_J], - ACC_T D[MAT_DIM_I][MAT_DIM_J], acc_t C[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C[r][c] += A[r][k] * B[k][c]; - } -} - -void full_printMatrix(acc_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(acc_t x[MAT_DIM_I][MAT_DIM_J], - acc_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static acc_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static acc_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - -#ifdef FAST -#define RAND 1 -#else -#define RAND rand() -#endif - - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = RAND % 2; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = RAND % 2; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : RAND % 2; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); -#ifdef FAST - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - gold[i][j] = MAT_DIM_K + (NO_BIAS ? 0 : (RAND % 2)); - } - } - -#else - full_matmul(full_A, full_B, full_D, gold); -#endif - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], full_C, - MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, MAT_DIM_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, false, false, true, !FULL_BIAS_WIDTH, 0, WS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_igelu.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_igelu.c deleted file mode 100644 index 61b01ec8..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_igelu.c +++ /dev/null @@ -1,144 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#define BERT_SCALE 0.8 - -#ifndef BAREMETAL - -#define MAT_DIM_I 128 -#define MAT_DIM_K 512 -#define MAT_DIM_J 512 - -#else -#define MAT_DIM_I 30 -#define MAT_DIM_K 30 -#define MAT_DIM_J 30 -#endif - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#if defined(FAST) || !defined(HAS_NORMALIZATIONS) - exit(0); -#endif - -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("I: %d, J: %d, K: %d\n", MAT_DIM_I, MAT_DIM_J, MAT_DIM_K); - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = (rand() % 3) - 1; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = (rand() % 3) - 1; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : (rand() % 3) - 1; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)gold, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, MAT_DIM_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, IGELU, ACC_SCALE_IDENTITY, BERT_SCALE, - false, false, false, false, !FULL_BIAS_WIDTH, 0, CPU); - - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - -#endif - - printf("Starting gemmini matmul\n"); - printf("I: %d, J: %d, K: %d\n", MAT_DIM_I, MAT_DIM_J, MAT_DIM_K); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, IGELU, ACC_SCALE_IDENTITY, BERT_SCALE, - false, false, false, false, !FULL_BIAS_WIDTH, 0, WS); - - gemmini_fence(); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_layernorm.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_layernorm.c deleted file mode 100644 index 5374d0c2..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_layernorm.c +++ /dev/null @@ -1,174 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 0 -#define FULL_BIAS_WIDTH 1 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifndef BAREMETAL - -#define MAT_DIM_I 32 -#define MAT_DIM_K 240 -#define MAT_DIM_J 512 - -#else -#define MAT_DIM_I 31 -#define MAT_DIM_K 30 -#define MAT_DIM_J 66 -#endif - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -void full_printMatrix_acc(acc_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#if defined(FAST) || !defined(HAS_NORMALIZATIONS) - exit(0); -#endif - -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("MAT_DIM_I: %d\n", MAT_DIM_I); - printf("MAT_DIM_J: %d\n", MAT_DIM_J); - printf("MAT_DIM_K: %d\n", MAT_DIM_K); - printf("NO_BIAS: %d\n", NO_BIAS); - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static acc_t unnormed_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = (rand() % 3) - 1; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = (rand() % 3) - 1; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : (rand() % 3) - 1; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)gold, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, MAT_DIM_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, LAYERNORM, ACC_SCALE_IDENTITY, 0, - false, false, false, false, !FULL_BIAS_WIDTH, 0, CPU); - - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - /* - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, - (elem_t*)full_A, (elem_t*)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t*)full_C, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, MAT_DIM_J, - MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - LAYERNORM, ACC_SCALE_IDENTITY, 0, false, - - false, false, - false, !FULL_BIAS_WIDTH, - 0, - WS); - */ - - tiled_matmul_auto( - MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, (elem_t *)full_B, - NO_BIAS ? NULL : &full_D[0][0], (acc_t *)unnormed_C, MAT_DIM_K, MAT_DIM_J, - MAT_DIM_J, MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, false, - - false, false, true, !FULL_BIAS_WIDTH, 0, WS); - - gemmini_fence(); - - tiled_norm_auto(MAT_DIM_I, MAT_DIM_J, (acc_t *)unnormed_C, (elem_t *)full_C, - ACC_SCALE_IDENTITY, LAYERNORM, WS); - - gemmini_fence(); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("\nUnnormed:\n"); - full_printMatrix_acc(unnormed_C); - printf("\nGold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_low_D.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_low_D.c deleted file mode 100644 index ed8c39f7..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_low_D.c +++ /dev/null @@ -1,179 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 0 -#define FULL_BIAS_WIDTH 0 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifndef BAREMETAL -#define MAT_DIM_I 500 -#define MAT_DIM_K 400 -#define MAT_DIM_J 300 -#else -#define MAT_DIM_I 60 -#define MAT_DIM_K 40 -#define MAT_DIM_J 30 -#endif - -void print_tile(elem_t *in, int tile_dim) { - for (size_t r = 0; r < tile_dim; r++) { - printf("row starts at: %p\n", in + r * MAT_DIM_J); - for (size_t c = 0; c < tile_dim; c++) { - printf("%d ", *(in + r * MAT_DIM_J + c)); - } - printf("\n"); - } -} - -void full_matmul(elem_t A[MAT_DIM_I][MAT_DIM_K], elem_t B[MAT_DIM_K][MAT_DIM_J], - ACC_T D[MAT_DIM_I][MAT_DIM_J], - full_t C_full[MAT_DIM_I][MAT_DIM_J]) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - C_full[r][c] = D[r][c]; - for (size_t k = 0; k < MAT_DIM_K; k++) - C_full[r][c] += A[r][k] * B[k][c]; - } -} - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -void full_matscale(full_t full[MAT_DIM_I][MAT_DIM_J], - elem_t out[MAT_DIM_I][MAT_DIM_J], acc_scale_t scale) { - for (size_t r = 0; r < MAT_DIM_I; r++) - for (size_t c = 0; c < MAT_DIM_J; c++) { - // Scale element - full_t scaled = ACC_SCALE(full[r][c], scale); - - // Saturate and cast element -#ifndef ELEM_T_IS_FLOAT - full_t elem = scaled > elem_t_max - ? elem_t_max - : (scaled < elem_t_min ? elem_t_min : scaled); - out[r][c] = elem; -#else - out[r][c] = scaled; // TODO should we also saturate when using floats? -#endif - } -} - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 -#ifdef FAST -#define RAND 1 -#else -#define RAND rand() -#endif - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = RAND % 2; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = RAND % 2; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : RAND % 2; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); -#ifdef FAST - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - gold_full[i][j] = MAT_DIM_K + (NO_BIAS ? 0 : (RAND % 2)); - } - } - -#else - full_matmul(full_A, full_B, full_D, gold_full); -#endif - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - full_matscale(gold_full, gold, ACC_SCALE_IDENTITY); -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto(MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, - (elem_t *)full_B, NO_BIAS ? NULL : &full_D[0][0], - (elem_t *)full_C, MAT_DIM_K, MAT_DIM_J, MAT_DIM_J, - MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, NO_ACTIVATION, ACC_SCALE_IDENTITY, 0, - false, false, false, false, !FULL_BIAS_WIDTH, 0, WS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_perf.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_perf.c deleted file mode 100644 index 02b8ff8e..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_perf.c +++ /dev/null @@ -1,108 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define ACTIVATION NO_ACTIVATION - -#define NO_BIAS 0 -#define REPEATING_BIAS 1 - -#define A_TRANSPOSE 0 -#define B_TRANSPOSE 0 - -#ifndef BAREMETAL - -#define MAT_DIM_I 128 -#define MAT_DIM_K 512 -#define MAT_DIM_J 256 - -#else - -#define MAT_DIM_I 128 -#define MAT_DIM_K 256 -#define MAT_DIM_J 256 - -#endif - -#if A_TRANSPOSE == 0 -#define A_STRIDE MAT_DIM_K -#else -#define A_STRIDE MAT_DIM_I -#endif - -#if B_TRANSPOSE == 0 -#define B_STRIDE MAT_DIM_J -#else -#define B_STRIDE MAT_DIM_K -#endif - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - -#if A_TRANSPOSE == 0 - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); -#else - static elem_t full_A[MAT_DIM_K][MAT_DIM_I] row_align(1); -#endif - -#if B_TRANSPOSE == 0 - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); -#else - static elem_t full_B[MAT_DIM_J][MAT_DIM_K] row_align(1); -#endif - - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static acc_t full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static full_t gold_full[MAT_DIM_I][MAT_DIM_J]; - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - - counter_configure(0, RDMA_BYTES_REC); - counter_configure(1, WDMA_BYTES_SENT); - counter_reset(); - - printf("Starting gemmini matmul\n"); - printf("I: %d, J: %d, K: %d\n", MAT_DIM_I, MAT_DIM_J, MAT_DIM_K); - printf("NO_BIAS: %d, REPEATING_BIAS: %d\n", NO_BIAS, REPEATING_BIAS); - printf("A_TRANSPOSE: %d, B_TRANSPOSE: %d\n", A_TRANSPOSE, B_TRANSPOSE); - uint64_t start = read_cycles(); - - tiled_matmul_auto( - MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, (elem_t *)full_B, - NO_BIAS ? NULL : &full_D[0][0], (elem_t *)full_C, A_STRIDE, B_STRIDE, - MAT_DIM_J, MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, ACTIVATION, ACC_SCALE_IDENTITY, 0, REPEATING_BIAS, - A_TRANSPOSE, B_TRANSPOSE, false, false, 0, WS); - - gemmini_fence(); - - uint64_t end = read_cycles(); - printf("Cycles taken: %llu\n", end - start); - - const uint64_t total_macs = MAT_DIM_I * MAT_DIM_J * MAT_DIM_K; - const uint64_t ideal_cycles = total_macs / (DIM * DIM); - const uint64_t utilization = 100 * ideal_cycles / (end - start); - printf("Total macs: %llu\n", total_macs); - printf("Ideal cycles: %llu\n", ideal_cycles); - printf("Utilization: %llu%%\n", utilization); - - printf("RDMA_BYTES_REC: %u\n", counter_read(0)); - printf("WDMA_BYTES_SENT: %u\n", counter_read(1)); - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_softmax.c b/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_softmax.c deleted file mode 100644 index a36ccd01..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/tiled_matmul_ws_softmax.c +++ /dev/null @@ -1,136 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -#define CHECK_RESULT 1 - -#define NO_BIAS 1 -#define FULL_BIAS_WIDTH 1 -#define BERT_SCALE 0.05 - -#if FULL_BIAS_WIDTH -typedef acc_t ACC_T; -#else -typedef elem_t ACC_T; -#endif - -#ifndef BAREMETAL -#define MAT_DIM_I 128 -#define MAT_DIM_K 64 -#define MAT_DIM_J 128 -#else -#define MAT_DIM_I 31 -#define MAT_DIM_K 30 -#define MAT_DIM_J 66 -#endif - -void full_printMatrix(elem_t m[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) - printf("%d ", m[i][j]); - printf("\n"); - } -} - -int full_is_equal(elem_t x[MAT_DIM_I][MAT_DIM_J], - elem_t y[MAT_DIM_I][MAT_DIM_J]) { - for (size_t i = 0; i < MAT_DIM_I; ++i) - for (size_t j = 0; j < MAT_DIM_J; ++j) - if (x[i][j] != y[i][j]) - return 0; - return 1; -} - -int main() { -#if defined(FAST) || !defined(HAS_NORMALIZATIONS) - exit(0); -#endif - -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - gemmini_flush(0); - - static elem_t full_A[MAT_DIM_I][MAT_DIM_K] row_align(1); - static elem_t full_B[MAT_DIM_K][MAT_DIM_J] row_align(1); - static elem_t full_C[MAT_DIM_I][MAT_DIM_J] row_align(1); - static ACC_T full_D[MAT_DIM_I][MAT_DIM_J] row_align_acc(1); - - static elem_t gold[MAT_DIM_I][MAT_DIM_J]; - -#if CHECK_RESULT == 1 - // printf("Init A\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_K; ++j) { - full_A[i][j] = (rand() % 7) - 3; - } - } - - // printf("Init B\n"); - for (size_t i = 0; i < MAT_DIM_K; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_B[i][j] = (rand() % 7) - 3; - } - } - - // printf("Init D\n"); - for (size_t i = 0; i < MAT_DIM_I; ++i) { - for (size_t j = 0; j < MAT_DIM_J; ++j) { - full_D[i][j] = NO_BIAS ? 0 : (rand() % 3) - 1; - } - } - - printf("Starting slow CPU matmul\n"); - unsigned long cpu_start = read_cycles(); - - tiled_matmul_auto( - MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, (elem_t *)full_B, - NO_BIAS ? NULL : &full_D[0][0], (elem_t *)gold, MAT_DIM_K, MAT_DIM_J, - MAT_DIM_J, MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, SOFTMAX, ACC_SCALE_IDENTITY, BERT_SCALE, false, - false, false, false, !FULL_BIAS_WIDTH, 0, CPU); - - unsigned long cpu_end = read_cycles(); - printf("Cycles taken: %u\n", cpu_end - cpu_start); - -#endif - - printf("Starting gemmini matmul\n"); - unsigned long start = read_cycles(); - - tiled_matmul_auto( - MAT_DIM_I, MAT_DIM_J, MAT_DIM_K, (elem_t *)full_A, (elem_t *)full_B, - NO_BIAS ? NULL : &full_D[0][0], (elem_t *)full_C, MAT_DIM_K, MAT_DIM_J, - MAT_DIM_J, MAT_DIM_J, MVIN_SCALE_IDENTITY, MVIN_SCALE_IDENTITY, - MVIN_SCALE_IDENTITY, SOFTMAX, ACC_SCALE_IDENTITY, BERT_SCALE, false, - false, false, false, !FULL_BIAS_WIDTH, 0, WS); - - unsigned long end = read_cycles(); - printf("Cycles taken: %u\n", end - start); - -#if CHECK_RESULT == 1 - if (!full_is_equal(full_C, gold)) { - printf("C:\n"); - full_printMatrix(full_C); - printf("Gold:\n"); - full_printMatrix(gold); - printf("\n"); - - exit(1); - } -#endif - - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/gemmini/transpose.c b/bb-tests/workloads/src/CTest/gemmini/transpose.c deleted file mode 100644 index 4ad4329b..00000000 --- a/bb-tests/workloads/src/CTest/gemmini/transpose.c +++ /dev/null @@ -1,77 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#ifndef BAREMETAL -#include -#endif -#include "include/gemmini_testutils.h" - -int main() { -#ifndef BAREMETAL - if (mlockall(MCL_CURRENT | MCL_FUTURE) != 0) { - perror("mlockall failed"); - exit(1); - } -#endif - - printf("Flush Gemmini TLB of stale virtual addresses\n"); - gemmini_flush(0); - - printf("Initialize our input and output matrices in main memory\n"); - elem_t In[DIM][DIM]; - elem_t Out[DIM][DIM]; - - elem_t Identity[DIM][DIM]; - for (size_t i = 0; i < DIM; i++) - for (size_t j = 0; j < DIM; j++) { - In[i][j] = rand() % 10; - Identity[i][j] = i == j; - } - - printf("Calculate the scratchpad addresses of all our matrices\n"); - printf(" Note: The scratchpad is \"row-addressed\", where each address " - "contains one matrix row\n"); - size_t In_sp_addr = 0; - size_t Out_sp_addr = DIM; - size_t Identity_sp_addr = 2 * DIM; - - printf("Move \"In\" matrix from main memory into Gemmini's scratchpad\n"); - gemmini_config_ld(DIM * sizeof(elem_t)); - gemmini_config_st(DIM * sizeof(elem_t)); - gemmini_mvin(In, In_sp_addr); - - printf( - "Move \"Identity\" matrix from main memory into Gemmini's scratchpad\n"); - gemmini_mvin(Identity, Identity_sp_addr); - - printf("Multiply \"In\" matrix with \"Identity\" matrix with a bias of 0\n"); - gemmini_extended_config_ex(OUTPUT_STATIONARY, 0, 0, 1, true, false) - gemmini_preload_zeros(Out_sp_addr); - gemmini_compute_preloaded(In_sp_addr, Identity_sp_addr); - - printf("Move \"Out\" matrix from Gemmini's scratchpad into main memory\n"); - gemmini_config_st(DIM * sizeof(elem_t)); - gemmini_mvout(Out, Out_sp_addr); - - printf("Fence till Gemmini completes all memory operations\n"); - gemmini_fence(); - - printf("Check whether \"In\" and \"Out\" matrices are identical\n"); - if (!is_equal_transposed(In, Out)) { - printf("Input and output matrices are different!\n"); - printf("\"In\" matrix:\n"); - printMatrix(In); - printf("\"Out\" matrix:\n"); - printMatrix(Out); - printf("\n"); - - exit(1); - } - - printf("Input and output matrices are identical, as expected\n"); - exit(0); -} diff --git a/bb-tests/workloads/src/CTest/goban/CMakeLists.txt b/bb-tests/workloads/src/CTest/goban/CMakeLists.txt index 08126947..ac0c7652 100644 --- a/bb-tests/workloads/src/CTest/goban/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/goban/CMakeLists.txt @@ -5,12 +5,13 @@ set(ELF_CC "riscv64-unknown-elf-gcc") # All cores run the ELF simultaneously; divergence is by mhartid. #------------------------------------------------------------------------------- set(CTEST_GOBAN_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/goban) +set(GOBAN_LD ${CTEST_GOBAN_WORKLOAD_DIR}/goban.ld) set(GOBAN_C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf - -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} + -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles + -Wl,-T,${GOBAN_LD} -I${WORKLOAD_LIB_DIR} -I${CTEST_GOBAN_WORKLOAD_DIR} ) diff --git a/bb-tests/workloads/src/CTest/goban/goban.ld b/bb-tests/workloads/src/CTest/goban/goban.ld new file mode 100644 index 00000000..e3284422 --- /dev/null +++ b/bb-tests/workloads/src/CTest/goban/goban.ld @@ -0,0 +1,41 @@ +/* goban.ld — baremetal linker script for Goban multi-core workloads (BBSimHarness) */ +OUTPUT_ARCH("riscv") +ENTRY(_start) + +SECTIONS { + . = 0x80000000; + + .text : { + *(.text.init) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } + + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + *(.gnu.linkonce.r.*) + } + + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + } + + .bss (NOLOAD) : { + PROVIDE(__bss_start = .); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + PROVIDE(__bss_end = .); + } + + . = ALIGN(16); + PROVIDE(end = .); + PROVIDE(_end = .); +} diff --git a/bb-tests/workloads/src/CTest/goban/start.S b/bb-tests/workloads/src/CTest/goban/start.S index 63e67e71..177d8504 100644 --- a/bb-tests/workloads/src/CTest/goban/start.S +++ b/bb-tests/workloads/src/CTest/goban/start.S @@ -1,6 +1,8 @@ # Multi-core SPMD startup for Goban (nCores=4 by default). # All harts jump to main(); divergence is done via mhartid inside main(). # Stack layout: base = 0x80020000, each hart gets 4 KB downward. +# On return from main(), hart 0 writes exit code to BBSimHarness MMIO exit +# register (0x60000000); other harts spin forever. .section .text.init .global _start @@ -16,6 +18,13 @@ _start: call main + # Only hart 0 writes the MMIO exit register + csrr t0, mhartid + bnez t0, 1f + li t1, 0x60000000 + sw a0, 0(t1) # write exit code; C++ mmio_tick() calls sim_exit() +1: j 1b # spin forever (all harts) + .align 12 stack_space: .space 0x8000 # 32 KB total stack space (8 harts × 4 KB) diff --git a/bb-tests/workloads/src/CTest/rvv/.gitignore b/bb-tests/workloads/src/CTest/rvv/.gitignore deleted file mode 100644 index e69de29b..00000000 diff --git a/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt b/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt deleted file mode 100644 index 24f20150..00000000 --- a/bb-tests/workloads/src/CTest/rvv/CMakeLists.txt +++ /dev/null @@ -1,100 +0,0 @@ -set(ELF_CC "riscv64-unknown-elf-gcc") -set(LINUX_CC "riscv64-unknown-linux-gnu-g++") - -#------------------------------------------------------------------------------- -# Set baremetal compilation flags with RVV support -#------------------------------------------------------------------------------- -set(C_FLAGS -g -fno-common -O1 -static -march=rv64gcv -mabi=lp64d -mcmodel=medany - -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} ) - -#------------------------------------------------------------------------------- -# Define common compilation step functions -#------------------------------------------------------------------------------- - -#------------------------------------------------------------------------------- -# Generate executables for different platforms -#------------------------------------------------------------------------------- -set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-g++") -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gcv") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gcv") - -# Generate Linux version executables -function(add_linux_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}-linux") - - add_executable(${EXECUTABLE} ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE}) - target_compile_options(${EXECUTABLE} PRIVATE -march=rv64gcv -mabi=lp64d) -endfunction() - -# Generate multicore baremetal version executables -function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}_multicore-baremetal") - - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} ${CTEST_RVV_WORKLOAD_DIR}/start.S - -DMULTICORE=3 - ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} - DEPENDS ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} - ${CTEST_RVV_WORKLOAD_DIR}/start.S - COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - - add_custom_target(${TEST_NAME}_multicore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - ) -endfunction() - -# Generate singlecore baremetal version executables -function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}_singlecore-baremetal") - - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} - ${CTEST_RVV_WORKLOAD_DIR}/start.S - ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} - DEPENDS ${CTEST_RVV_WORKLOAD_DIR}/${SOURCE_FILE} - ${CTEST_RVV_WORKLOAD_DIR}/start.S - COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - - add_custom_target(${TEST_NAME}_singlecore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - ) -endfunction() - -# Create cross-platform test targets -function(add_cross_platform_test_target TEST_NAME SOURCE_FILE) - add_linux_test_target(${TEST_NAME} ${SOURCE_FILE}) - add_multicore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - add_singlecore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - - # Create a master target that builds all platforms simultaneously - add_custom_target(${TEST_NAME} - DEPENDS ${TEST_NAME}-linux ${TEST_NAME}_multicore_baremetal ${TEST_NAME}_singlecore_baremetal - COMMENT "Building ${TEST_NAME} for all platforms" - ) -endfunction() - -#------------------------------------------------------------------------------- -# build linux version workload -#------------------------------------------------------------------------------- -set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") -set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${LINK_FLAGS}") - -#------------------------------------------------------------------------------- -# Build list - use cross-platform function to generate all test targets -#------------------------------------------------------------------------------- -add_cross_platform_test_target(ctest_rvv_vadd vadd_test.c) -add_cross_platform_test_target(ctest_rvv_vdot vdot_test.c) - -# Create master build target -add_custom_target(buckyball-rvv-build ALL DEPENDS - ctest_rvv_vadd - ctest_rvv_vdot - COMMENT "Building all RVV workloads for Buckyball" - VERBATIM) diff --git a/bb-tests/workloads/src/CTest/rvv/start.S b/bb-tests/workloads/src/CTest/rvv/start.S deleted file mode 100644 index 53992e9d..00000000 --- a/bb-tests/workloads/src/CTest/rvv/start.S +++ /dev/null @@ -1,22 +0,0 @@ -.section .text.init -.global _start - -_start: - # Get hart ID - csrr t0, mhartid - - # Set up stack pointer for each hart - # Each hart gets 4KB stack space (0x1000 bytes) - li sp, 0x80020000 - li t1, 0x1000 - mul t1, t0, t1 - sub sp, sp, t1 - # Jump to main for all harts (let MLIR code handle hart filtering) - call main - - - -.align 12 -stack_space: - # 32KB stack space - .space 0x8000 diff --git a/bb-tests/workloads/src/CTest/rvv/vadd_test.c b/bb-tests/workloads/src/CTest/rvv/vadd_test.c deleted file mode 100644 index dbb22d04..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vadd_test.c +++ /dev/null @@ -1,40 +0,0 @@ -#include -#include - -int main() { - printf("Testing RVV vector addition with intrinsics\n"); - - // Test parameters - const int n = 16; - int a[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; - int b[16] = {16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}; - int c[16] = {0}; - int expected[16] = {17, 17, 17, 17, 17, 17, 17, 17, - 17, 17, 17, 17, 17, 17, 17, 17}; - - // Perform vector addition using RVV intrinsics - size_t vl; - for (size_t i = 0; i < n;) { - vl = __riscv_vsetvl_e32m1(n - i); // Set vector length - vint32m1_t va = __riscv_vle32_v_i32m1(&a[i], vl); // Load vector a - vint32m1_t vb = __riscv_vle32_v_i32m1(&b[i], vl); // Load vector b - vint32m1_t vc = __riscv_vadd_vv_i32m1(va, vb, vl); // Vector add - __riscv_vse32_v_i32m1(&c[i], vc, vl); // Store result - i += vl; - } - - // Verify results - int passed = 1; - for (int i = 0; i < n; i++) { - if (c[i] != expected[i]) { - printf("FAILED at index %d: expected %d, got %d\n", i, expected[i], c[i]); - passed = 0; - } - } - - if (passed) { - printf("Test PASSED - Vector addition works correctly!\n"); - } - - return passed ? 0 : 1; -} diff --git a/bb-tests/workloads/src/CTest/rvv/vdot_test.c b/bb-tests/workloads/src/CTest/rvv/vdot_test.c deleted file mode 100644 index 480af9d3..00000000 --- a/bb-tests/workloads/src/CTest/rvv/vdot_test.c +++ /dev/null @@ -1,39 +0,0 @@ -#include -#include - -int main() { - printf("Testing RVV vector dot product with intrinsics\n"); - - // Test parameters - const int n = 8; - int a[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - int b[8] = {8, 7, 6, 5, 4, 3, 2, 1}; - int result = 0; - // Expected: 1*8 + 2*7 + 3*6 + 4*5 + 5*4 + 6*3 + 7*2 + 8*1 - // = 8 + 14 + 18 + 20 + 20 + 18 + 14 + 8 = 120 - int expected = 120; - - // Perform vector dot product using RVV intrinsics - size_t vl = __riscv_vsetvl_e32m1(n); // Set vector length for entire array - - vint32m1_t va = __riscv_vle32_v_i32m1(a, vl); // Load vector a - vint32m1_t vb = __riscv_vle32_v_i32m1(b, vl); // Load vector b - vint32m1_t vmul = __riscv_vmul_vv_i32m1(va, vb, vl); // Element-wise multiply - - // Manual reduction: store to temp array and sum - int temp[8]; - __riscv_vse32_v_i32m1(temp, vmul, vl); - - for (int i = 0; i < n; i++) { - result += temp[i]; - } - - // Verify result - if (result == expected) { - printf("Test PASSED - Dot product result: %d\n", result); - return 0; - } else { - printf("Test FAILED - Expected %d, got %d\n", expected, result); - return 1; - } -} diff --git a/bb-tests/workloads/src/OpTest/CMakeLists.txt b/bb-tests/workloads/src/OpTest/CMakeLists.txt index 6d2f6993..685e67a3 100644 --- a/bb-tests/workloads/src/OpTest/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/CMakeLists.txt @@ -1,13 +1,10 @@ set(OPTEST_TOY_DIR ${OPTEST_WORKLOAD_DIR}/toy) set(OPTEST_TILE_DIR ${OPTEST_WORKLOAD_DIR}/tile) -set(OPTEST_GEMMINI_DIR ${OPTEST_WORKLOAD_DIR}/gemmini) add_subdirectory(toy) add_subdirectory(tile) -add_subdirectory(gemmini) add_custom_target(OpTest-all ALL DEPENDS - OpTest-gemmini OpTest-toy OpTest-tile ) diff --git a/bb-tests/workloads/src/OpTest/gemmini/.gitignore b/bb-tests/workloads/src/OpTest/gemmini/.gitignore deleted file mode 100644 index b65d24ce..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -log.* -core -*pk -a.out diff --git a/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt b/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt deleted file mode 100644 index 23b2c5a0..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/CMakeLists.txt +++ /dev/null @@ -1,164 +0,0 @@ - - - -#------------------------------------------------------------------------------- -# Define common compilation step functions .mlir -> .o -#------------------------------------------------------------------------------- - -#------------------------------------------------------------------------------- -# Generate executables for different platforms -#------------------------------------------------------------------------------- -# Generate baremetal executables -function(add_baremetal_target TARGET_NAME MLIR_FILE) - set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-baremetal.o") - set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-baremetal") - - # Compile xx.mlir to xx-baremetal.o - add_custom_command( - OUTPUT ${OBJ_FILE} - COMMAND ${BUDDY_OPT} ${MLIR_FILE} - -convert-linalg-to-gemmini - -expand-strided-metadata - -convert-linalg-to-loops - -lower-gemmini | - ${BUDDY_TRANSLATE} --buddy-to-llvmir | - ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 - -mattr=+buddyext,+D -float-abi=hard - -relocation-model=pic - -o ${OBJ_FILE} - DEPENDS ${MLIR_FILE} - COMMENT "Compiling ${MLIR_FILE} to object file" - ) - - # Link xx-baremetal.o to xx-baremetal - add_custom_command( - - OUTPUT ${EXECUTABLE} - COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} - ${OBJ_FILE} -o ${EXECUTABLE} - DEPENDS ${OBJ_FILE} - COMMENT "Linking baremetal executable: ${EXECUTABLE}" - ) - - # Create target for xx-baremetal - add_custom_target(${TARGET_NAME}_baremetal - DEPENDS ${EXECUTABLE} - ) -endfunction() - -# Generate Linux executables -function(add_linux_target TARGET_NAME MLIR_FILE) - set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-linux.o") - set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}-linux") - - # Compile xx.mlir to xx-linux.o - add_custom_command( - OUTPUT ${OBJ_FILE} - COMMAND ${BUDDY_OPT} ${MLIR_FILE} - -convert-linalg-to-gemmini - -expand-strided-metadata - -convert-linalg-to-loops - -lower-gemmini | - ${BUDDY_TRANSLATE} --buddy-to-llvmir | - ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 - -mattr=+buddyext,+D -float-abi=hard - -relocation-model=static - -o ${OBJ_FILE} - DEPENDS ${MLIR_FILE} - COMMENT "Compiling ${MLIR_FILE} to Linux object file" - ) - - # Link xx-linux.o to xx-linux - add_custom_command( - OUTPUT ${EXECUTABLE} - COMMAND ${LINUX_CC} -O2 -static -Wl,--no-relax ${OBJ_FILE} -o ${EXECUTABLE} - DEPENDS ${OBJ_FILE} - COMMENT "Linking Linux executable: ${EXECUTABLE}" - ) - - # Create target for xx-linux - use target name prefix to avoid conflicts - add_custom_target(${TARGET_NAME}_linux - DEPENDS ${EXECUTABLE} - ) -endfunction() - -# Create executables for different platforms -function(add_cross_platform_target TARGET_NAME MLIR_FILE) - add_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) - add_linux_target(${TARGET_NAME} ${MLIR_FILE}) - - # Create a master target that builds both platforms simultaneously - add_custom_target(${TARGET_NAME} - DEPENDS ${TARGET_NAME}_baremetal ${TARGET_NAME}_linux - COMMENT "Building ${TARGET_NAME} for both baremetal and Linux" - ) -endfunction() - -#------------------------------------------------------------------------------- -# Build list -#------------------------------------------------------------------------------- -add_cross_platform_target(matrix-add ${OPTEST_GEMMINI_DIR}/matrix-add.mlir) -add_cross_platform_target(matrix-add-scale ${OPTEST_GEMMINI_DIR}/matrix-add-scale.mlir) -add_cross_platform_target(mvin-mvout ${OPTEST_GEMMINI_DIR}/mvin-mvout.mlir) -add_cross_platform_target(transpose ${OPTEST_GEMMINI_DIR}/transpose.mlir) -add_cross_platform_target(compute-accumulated ${OPTEST_GEMMINI_DIR}/compute-accumulated.mlir) - -add_cross_platform_target(matmul ${OPTEST_GEMMINI_DIR}/matmul.mlir) -add_cross_platform_target(matmul-os ${OPTEST_GEMMINI_DIR}/matmul-os.mlir) -add_cross_platform_target(matmul-ws ${OPTEST_GEMMINI_DIR}/matmul-ws.mlir) -add_cross_platform_target(batch_matmul ${OPTEST_GEMMINI_DIR}/batch_matmul.mlir) - -add_cross_platform_target(tile-matmul ${OPTEST_GEMMINI_DIR}/tile-matmul.mlir) -add_cross_platform_target(tile-matmul-os ${OPTEST_GEMMINI_DIR}/tile-matmul-os.mlir) -add_cross_platform_target(tile-matmul-ws-relu ${OPTEST_GEMMINI_DIR}/tile-matmul-ws-relu.mlir) -add_cross_platform_target(tile-matmul-ws-igelu ${OPTEST_GEMMINI_DIR}/tile-matmul-ws-igelu.mlir) -add_cross_platform_target(tile-matmul-ws-softmax ${OPTEST_GEMMINI_DIR}/tile-matmul-ws-softmax.mlir) -add_cross_platform_target(tile-matmul-ws-layernorm ${OPTEST_GEMMINI_DIR}/tile-matmul-ws-layernorm.mlir) - -add_cross_platform_target(conv_2d_nchw_fchw_f32 ${OPTEST_GEMMINI_DIR}/conv_2d_nchw_fchw_f32.mlir) -add_cross_platform_target(conv_2d_nchw_fchw_i8 ${OPTEST_GEMMINI_DIR}/conv_2d_nchw_fchw_i8.mlir) -add_cross_platform_target(conv_2d_nhwc_hwcf_i8 ${OPTEST_GEMMINI_DIR}/conv_2d_nhwc_hwcf_i8.mlir) -add_cross_platform_target(conv_2d_nhwc_hwcf_f32 ${OPTEST_GEMMINI_DIR}/conv_2d_nhwc_hwcf_f32.mlir) -add_cross_platform_target(conv_2d_nhwc_hwcf_5x5_i8 ${OPTEST_GEMMINI_DIR}/conv_2d_nhwc_hwcf_5x5_i8.mlir) -add_cross_platform_target(conv_2d_nhwc_fhwc_f32 ${OPTEST_GEMMINI_DIR}/conv_2d_nhwc_fhwc_f32.mlir) -add_cross_platform_target(conv_2d_nhwc_fhwc_i8 ${OPTEST_GEMMINI_DIR}/conv_2d_nhwc_fhwc_i8.mlir) -add_cross_platform_target(conv_2d_nhwc_fhwc_5x5_i8 ${OPTEST_GEMMINI_DIR}/conv_2d_nhwc_fhwc_5x5_i8.mlir) - -add_cross_platform_target(tile-conv ${OPTEST_GEMMINI_DIR}/tile-conv.mlir) -add_cross_platform_target(tile-conv-relu ${OPTEST_GEMMINI_DIR}/tile-conv-relu.mlir) -add_cross_platform_target(tile-conv-softmax ${OPTEST_GEMMINI_DIR}/tile-conv-softmax.mlir) -add_cross_platform_target(tile-rect-conv ${OPTEST_GEMMINI_DIR}/tile-rect-conv.mlir) -add_cross_platform_target(tile-conv-igelu ${OPTEST_GEMMINI_DIR}/tile-conv-igelu.mlir) -add_cross_platform_target(tile-conv-layernorm ${OPTEST_GEMMINI_DIR}/tile-conv-layernorm.mlir) - -add_custom_target(OpTest-gemmini ALL DEPENDS - matrix-add - matrix-add-scale - mvin-mvout - transpose - compute-accumulated - matmul - matmul-os - matmul-ws - batch_matmul - tile-matmul - tile-matmul-os - tile-matmul-ws-relu - tile-matmul-ws-igelu - tile-matmul-ws-softmax - tile-matmul-ws-layernorm - conv_2d_nchw_fchw_f32 - conv_2d_nchw_fchw_i8 - conv_2d_nhwc_hwcf_i8 - conv_2d_nhwc_hwcf_f32 - conv_2d_nhwc_hwcf_5x5_i8 - conv_2d_nhwc_fhwc_f32 - conv_2d_nhwc_fhwc_i8 - conv_2d_nhwc_fhwc_5x5_i8 - tile-conv - tile-conv-relu - tile-conv-softmax - tile-rect-conv - tile-conv-igelu - tile-conv-layernorm -) diff --git a/bb-tests/workloads/src/OpTest/gemmini/batch_matmul.mlir b/bb-tests/workloads/src/OpTest/gemmini/batch_matmul.mlir deleted file mode 100644 index 0244443c..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/batch_matmul.mlir +++ /dev/null @@ -1,30 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %1 = arith.constant 1 : i8 - %2 = arith.constant 2 : i8 - %input0 = memref.alloc() : memref<3x3x3xi8> - %input1 = memref.alloc() : memref<3x3x3xi8> - %output = memref.alloc() : memref<3x3x3xi8> - linalg.fill - ins(%1 : i8) - outs(%input0 : memref<3x3x3xi8>) - linalg.fill - ins(%2 : i8) - outs(%input1 : memref<3x3x3xi8>) - // CHECK: gemmini.tile_matmul %subview %subview_2 %subview_3 %alloc_4 : - // CHECK-SAME: memref<3x3xi8, strided<[3, 1]>> memref<3x3xi8, strided<[3, 1]>> memref<3x3xi8, strided<[3, 1]>> memref<3x3xi32> - // CHECK: gemmini.tile_matmul %subview_5 %subview_6 %subview_7 %alloc_8 : - // CHECK-SAME: memref<3x3xi8, strided<[3, 1], offset: 9>> memref<3x3xi8, strided<[3, 1], offset: 9>> memref<3x3xi8, strided<[3, 1], offset: 9>> memref<3x3xi32> - // CHECK: gemmini.tile_matmul %subview_10 %subview_11 %subview_12 %alloc_13 : - // CHECK-SAME: memref<3x3xi8, strided<[3, 1], offset: 18>> memref<3x3xi8, strided<[3, 1], offset: 18>> memref<3x3xi8, strided<[3, 1], offset: 18>> memref<3x3xi32> - linalg.batch_matmul - ins(%input0, %input1: memref<3x3x3xi8>, memref<3x3x3xi8>) - outs(%output : memref<3x3x3xi8>) - gemmini.print %output : memref<3x3x3xi8> - memref.dealloc %output : memref<3x3x3xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/compute-accumulated.mlir b/bb-tests/workloads/src/OpTest/gemmini/compute-accumulated.mlir deleted file mode 100644 index 154a4f60..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/compute-accumulated.mlir +++ /dev/null @@ -1,49 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @gv1 : memref<4x4xi8> = dense<[[1, 2, 3, 4], - [5, 6, 7, 8], - [9, 10, 11, 12], - [13, 14, 15, 16]]> -memref.global "private" @gv2 : memref<4x4xi8> = dense<[[1, 1, 1, 1], - [1, 1, 1, 1], - [1, 1, 1, 1], - [1, 1, 1, 1]]> - -func.func @main() -> i64 { - %in = memref.get_global @gv1 : memref<4x4xi8> - %identity = memref.get_global @gv2 : memref<4x4xi8> - %out = memref.alloc() : memref<4x4xi8> - gemmini.print %out : memref<4x4xi8> - %inSpAddr = arith.constant 0 : i64 - %outSpAddr = arith.constant 4 : i64 - %identitySpAddr = arith.constant 8 : i64 - %cst4 = arith.constant 4 : i64 - %cst0 = arith.constant 0 : i64 - // CHECK: "gemmini.intr.config_st" - gemmini.config_st %cst4 : i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %in %inSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %identity %identitySpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ex" - gemmini.config_ex - // CHECK: "gemmini.intr.preload" - gemmini.preload_zeros %outSpAddr %cst4 %cst4 : i64 i64 i64 - // CHECK: "gemmini.intr.compute_preloaded" - gemmini.compute_preloaded %inSpAddr %identitySpAddr %cst4 %cst4 %cst4 %cst4 : i64 i64 i64 i64 i64 i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %out %outSpAddr : memref<4x4xi8> i64 - gemmini.print %out : memref<4x4xi8> - // CHECK: "gemmini.intr.compute_accumulated" - gemmini.compute_accumulated %inSpAddr %identitySpAddr %cst4 %cst4 %cst4 %cst4 : i64 i64 i64 i64 i64 i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %out %outSpAddr : memref<4x4xi8> i64 - gemmini.print %out : memref<4x4xi8> - return %cst0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nchw_fchw_f32.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nchw_fchw_f32.mlir deleted file mode 100644 index eda6cb2c..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nchw_fchw_f32.mlir +++ /dev/null @@ -1,51 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini="acc_t=f32" | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<2x2x5x5xf32> = dense<[[[[1., 0., -1., 0., 1.], - [1., 0., -1., 0., 1.], - [1., 0., -1., 0., 1.], - [1., 0., -1., 0., 1.], - [-1., 0., 1., 0., -1.]], - [[-1., 0., 1., 0., -1.], - [-1., 0., 1., 0., -1.], - [-1., 0., 1., 0., -1.], - [-1., 0., 1., 0., -1.], - [-1., 0., 1., 0., -1.]]], - [[[1., 0., 2., 0., 1.], - [1., 0., 2., 0., 1.], - [1., 0., 2., 0., 1.], - [1., 0., 2., 0., 1.], - [-1., 0., 2., 0., -1.]], - [[-1., 0., 2., 0., -1.], - [-1., 0., 2., 0., -1.], - [-1., 0., 2., 0., -1.], - [-1., 0., 2., 0., -1.], - [-1., 0., 2., 0., -1.]]]]> - -memref.global "private" @weight : memref<2x2x3x3xf32> = dense<[[[[1., 2., 3.], - [3., 2., 1.], - [1., 2., 3.]], - [[3., 2., 1.], - [1., 2., 3.], - [3., 2., 1.]]], - [[[1., 2., 3.], - [3., 2., 1.], - [1., 2., 3.]], - [[3., 2., 1.], - [1., 2., 3.], - [3., 2., 1.]]]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %mem0 = memref.get_global @input : memref<2x2x5x5xf32> - %mem1 = memref.get_global @weight : memref<2x2x3x3xf32> - %mem2 = memref.alloc() : memref<2x2x3x3xf32> - // CHECK: gemmini.tile_conv %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK-SAME: memref<2x5x5x2xf32> memref<18x2xf32> memref<2xf32> memref<18x2xf32> i64 i64 - linalg.conv_2d_nchw_fchw - ins (%mem0, %mem1 : memref<2x2x5x5xf32>, memref<2x2x3x3xf32>) - outs(%mem2 : memref<2x2x3x3xf32>) - gemmini.print %mem2 : memref<2x2x3x3xf32> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nchw_fchw_i8.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nchw_fchw_i8.mlir deleted file mode 100644 index eaec8b32..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nchw_fchw_i8.mlir +++ /dev/null @@ -1,51 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<2x2x5x5xi8> = dense<[[[[1, 0, -1, 0, 1], - [1, 0, -1, 0, 1], - [1, 0, -1, 0, 1], - [1, 0, -1, 0, 1], - [-1, 0, 1, 0, -1]], - [[-1, 0, 1, 0, -1], - [-1, 0, 1, 0, -1], - [-1, 0, 1, 0, -1], - [-1, 0, 1, 0, -1], - [-1, 0, 1, 0, -1]]], - [[[1, 0, 2, 0, 1], - [1, 0, 2, 0, 1], - [1, 0, 2, 0, 1], - [1, 0, 2, 0, 1], - [-1, 0, 2, 0, -1]], - [[-1, 0, 2, 0, -1], - [-1, 0, 2, 0, -1], - [-1, 0, 2, 0, -1], - [-1, 0, 2, 0, -1], - [-1, 0, 2, 0, -1]]]]> - -memref.global "private" @weight : memref<2x2x3x3xi8> = dense<[[[[1, 2, 3], - [3, 2, 1], - [1, 2, 3]], - [[3, 2, 1], - [1, 2, 3], - [3, 2, 1]]], - [[[1, 2, 3], - [3, 2, 1], - [1, 2, 3]], - [[3, 2, 1], - [1, 2, 3], - [3, 2, 1]]]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %mem0 = memref.get_global @input : memref<2x2x5x5xi8> - %mem1 = memref.get_global @weight : memref<2x2x3x3xi8> - %mem2 = memref.alloc() : memref<2x2x3x3xi8> - // CHECK: gemmini.tile_conv %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // memref<2x5x5x2xi8> memref<18x2xi8> memref<2xi32> memref<18x2xi8> i64 i64 - linalg.conv_2d_nchw_fchw - ins (%mem0, %mem1 : memref<2x2x5x5xi8>, memref<2x2x3x3xi8>) - outs(%mem2 : memref<2x2x3x3xi8>) - gemmini.print %mem2 : memref<2x2x3x3xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_5x5_i8.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_5x5_i8.mlir deleted file mode 100644 index a7d7662b..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_5x5_i8.mlir +++ /dev/null @@ -1,32 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<1x7x7x1xi8> = dense<[[[[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]]]]> - -memref.global "private" @kernel : memref<1x5x5x1xi8> = dense<[[[[1], [1], [1], [1], [1]], - [[1], [1], [1], [1], [1]], - [[1], [1], [1], [1], [1]], - [[1], [1], [1], [1], [1]], - [[1], [1], [1], [1], [1]]]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %input = memref.get_global @input : memref<1x7x7x1xi8> - %kernel = memref.get_global @kernel : memref<1x5x5x1xi8> - %output = memref.alloc() : memref<1x3x3x1xi8> - - // CHECK: gemmini.tile_conv %{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK-SAME: memref<1x7x7x1xi8> memref<25x1xi8> memref<1xi32> memref<9x1xi8> i64 i64 - linalg.conv_2d_nhwc_fhwc - ins(%input, %kernel : memref<1x7x7x1xi8>, memref<1x5x5x1xi8>) - outs(%output : memref<1x3x3x1xi8>) - gemmini.print %output : memref<1x3x3x1xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_f32.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_f32.mlir deleted file mode 100644 index 998b2d43..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_f32.mlir +++ /dev/null @@ -1,31 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini="acc_t=f32" | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<1x5x5x1xf32> = dense<[[[[1.],[2.],[3.],[4.],[5.]], - [[6.],[7.],[8.],[9.],[10.]], - [[11.],[12.],[13.],[14.],[15.]], - [[16.],[17.],[18.],[19.],[20.]], - [[21.],[22.],[23.],[24.],[25.]]]]> - -memref.global "private" @kernel : memref<1x3x3x1xf32> = dense<[[[[1.], [1.], [1.]], - [[1.], [1.], [1.]], - [[1.], [1.], [1.]]]]> - - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - // batchsize = 2 inputchannel = 2 - %input = memref.get_global @input : memref<1x5x5x1xf32> - // outputchannel = 3 - %kernel = memref.get_global @kernel : memref<1x3x3x1xf32> - // batchsize h w outputchannel - %output = memref.alloc() : memref<1x3x3x1xf32> - // CHECK: gemmini.tile_conv %{{.+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK: memref<1x5x5x1xf32> memref<9x1xf32> memref<1xf32> memref<9x1xf32> i64 i64 - linalg.conv_2d_nhwc_fhwc - ins(%input, %kernel : memref<1x5x5x1xf32>, memref<1x3x3x1xf32>) - outs(%output : memref<1x3x3x1xf32>) - gemmini.print %output : memref<1x3x3x1xf32> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_i8.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_i8.mlir deleted file mode 100644 index 0bfeafca..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_fhwc_i8.mlir +++ /dev/null @@ -1,30 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<1x7x7x1xi8> = dense<[[[[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]]]]> - -memref.global "private" @kernel : memref<1x3x3x1xi8> = dense<[[[[1], [1], [1]], - [[1], [1], [1]], - [[1], [1], [1]]]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %input = memref.get_global @input : memref<1x7x7x1xi8> - %kernel = memref.get_global @kernel : memref<1x3x3x1xi8> - %output = memref.alloc() : memref<1x5x5x1xi8> - - // CHECK: gemmini.tile_conv %{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK-SAME: memref<1x7x7x1xi8> memref<9x1xi8> memref<1xi32> memref<25x1xi8> i64 i64 - linalg.conv_2d_nhwc_fhwc - ins(%input, %kernel : memref<1x7x7x1xi8>, memref<1x3x3x1xi8>) - outs(%output : memref<1x5x5x1xi8>) - gemmini.print %output : memref<1x5x5x1xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_5x5_i8.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_5x5_i8.mlir deleted file mode 100644 index ee9af7d2..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_5x5_i8.mlir +++ /dev/null @@ -1,32 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<1x7x7x1xi8> = dense<[[[[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]], - [[1],[1],[1],[1],[1],[1],[1]]]]> - -memref.global "private" @kernel : memref<5x5x1x1xi8> = dense<[[[[1]], [[1]], [[1]], [[1]], [[1]]], - [[[1]], [[1]], [[1]], [[1]], [[1]]], - [[[1]], [[1]], [[1]], [[1]], [[1]]], - [[[1]], [[1]], [[1]], [[1]], [[1]]], - [[[1]], [[1]], [[1]], [[1]], [[1]]]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %input = memref.get_global @input : memref<1x7x7x1xi8> - %kernel = memref.get_global @kernel : memref<5x5x1x1xi8> - %output = memref.alloc() : memref<1x3x3x1xi8> - - // CHECK: gemmini.tile_conv %{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK-SAME: memref<1x7x7x1xi8> memref<25x1xi8> memref<1xi32> memref<9x1xi8> i64 i64 - linalg.conv_2d_nhwc_hwcf - ins(%input, %kernel : memref<1x7x7x1xi8>, memref<5x5x1x1xi8>) - outs(%output : memref<1x3x3x1xi8>) - gemmini.print %output : memref<1x3x3x1xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_f32.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_f32.mlir deleted file mode 100644 index f3c094dc..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_f32.mlir +++ /dev/null @@ -1,30 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini="acc_t=f32" | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<1x5x5x1xf32> = dense<[[[[1.],[2.],[3.],[4.],[5.]], - [[6.],[7.],[8.],[9.],[10.]], - [[11.],[12.],[13.],[14.],[15.]], - [[16.],[17.],[18.],[19.],[20.]], - [[21.],[22.],[23.],[24.],[25.]]]]> -memref.global "private" @kernel : memref<3x3x1x1xf32> = dense<[[[[1.]], [[1.]], [[1.]]], - [[[1.]], [[1.]], [[1.]]], - [[[1.]], [[1.]], [[1.]]]]> - - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - // batchsize = 2 inputchannel = 2 - %input = memref.get_global @input : memref<1x5x5x1xf32> - // outputchannel = 3 - %kernel = memref.get_global @kernel : memref<3x3x1x1xf32> - // batchsize h w outputchannel - %output = memref.alloc() : memref<1x3x3x1xf32> - // CHECK: gemmini.tile_conv %{{.+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK: memref<1x5x5x1xf32> memref<9x1xf32> memref<1xf32> memref<9x1xf32> i64 i64 - linalg.conv_2d_nhwc_hwcf - ins(%input, %kernel : memref<1x5x5x1xf32>, memref<3x3x1x1xf32>) - outs(%output : memref<1x3x3x1xf32>) - gemmini.print %output : memref<1x3x3x1xf32> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_i8.mlir b/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_i8.mlir deleted file mode 100644 index c6472d1b..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/conv_2d_nhwc_hwcf_i8.mlir +++ /dev/null @@ -1,30 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @input : memref<1x5x5x1xi8> = dense<[[[[1],[2],[3],[4],[5]], - [[6],[7],[8],[9],[10]], - [[11],[12],[13],[14],[15]], - [[16],[17],[18],[19],[20]], - [[21],[22],[23],[24],[25]]]]> -memref.global "private" @kernel : memref<3x3x1x1xi8> = dense<[[[[1]], [[1]], [[1]]], - [[[1]], [[1]], [[1]]], - [[[1]], [[1]], [[1]]]]> - - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - // batchsize = 2 inputchannel = 2 - %input = memref.get_global @input : memref<1x5x5x1xi8> - // outputchannel = 3 - %kernel = memref.get_global @kernel : memref<3x3x1x1xi8> - // batchsize h w outputchannel - %output = memref.alloc() : memref<1x3x3x1xi8> - // CHECK: gemmini.tile_conv %{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %{{.+}} %{{.+}} : - // CHECK-SAME: memref<1x5x5x1xi8> memref<9x1xi8> memref<1xi32> memref<9x1xi8> i64 i64 - linalg.conv_2d_nhwc_hwcf - ins(%input, %kernel : memref<1x5x5x1xi8>, memref<3x3x1x1xi8>) - outs(%output : memref<1x3x3x1xi8>) - gemmini.print %output : memref<1x3x3x1xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/matmul-os.mlir b/bb-tests/workloads/src/OpTest/gemmini/matmul-os.mlir deleted file mode 100644 index 9d704586..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/matmul-os.mlir +++ /dev/null @@ -1,44 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @gv1 : memref<4x4xi8> = dense<[[1, 2, 3, 4], - [5, 6, 7, 8], - [9, 10, 11, 12], - [13, 14, 15, 16]]> -memref.global "private" @gv2 : memref<4x4xi8> = dense<[[1, 1, 1, 1], - [1, 1, 1, 1], - [1, 1, 1, 1], - [1, 1, 1, 1]]> - -func.func @main() -> i64 { - %in = memref.get_global @gv1 : memref<4x4xi8> - %identity = memref.get_global @gv2 : memref<4x4xi8> - %out = memref.alloc() : memref<4x4xi8> - gemmini.print %out : memref<4x4xi8> - %inSpAddr = arith.constant 0 : i64 - %outSpAddr = arith.constant 4 : i64 - %identitySpAddr = arith.constant 8 : i64 - %cst4 = arith.constant 4 : i64 - %cst0 = arith.constant 0 : i64 - // CHECK: "gemmini.intr.config_st" - gemmini.config_st %cst4 : i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %in %inSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %identity %identitySpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ex" - gemmini.config_ex {dataflow = 0 } - // CHECK: "gemmini.intr.preload" - gemmini.preload_zeros %outSpAddr %cst4 %cst4 : i64 i64 i64 - // CHECK: "gemmini.intr.compute_preloaded" - gemmini.compute_preloaded %inSpAddr %identitySpAddr %cst4 %cst4 %cst4 %cst4 : i64 i64 i64 i64 i64 i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %out %outSpAddr : memref<4x4xi8> i64 - gemmini.print %out : memref<4x4xi8> - return %cst0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/matmul-ws.mlir b/bb-tests/workloads/src/OpTest/gemmini/matmul-ws.mlir deleted file mode 100644 index 0152565b..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/matmul-ws.mlir +++ /dev/null @@ -1,52 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @gv1 : memref<4x4xi8> = dense<[[1, 2, 3, 4], - [5, 6, 7, 8], - [9, 10, 11, 12], - [13, 14, 15, 16]]> -memref.global "private" @gv2 : memref<4x4xi8> = dense<[[1, 1, 1, 1], - [1, 1, 1, 1], - [1, 1, 1, 1], - [1, 1, 1, 1]]> -memref.global "private" @gv3 : memref<4x4xi8> = dense<[[2, 2, 2, 2], - [2, 2, 2, 2], - [2, 2, 2, 2], - [2, 2, 2, 2]]> - -func.func @main() -> i64 { - %aArray = memref.get_global @gv1 : memref<4x4xi8> - %bArray = memref.get_global @gv2 : memref<4x4xi8> - %cArray = memref.alloc() : memref<4x4xi8> - %dArray = memref.get_global @gv3 : memref<4x4xi8> - gemmini.print %cArray : memref<4x4xi8> - %aSpAddr = arith.constant 0 : i64 - %bSpAddr = arith.constant 4 : i64 - %cSpAddr = arith.constant 8 : i64 - %dSpAddr = arith.constant 12 : i64 - %cst4 = arith.constant 4 : i64 - %cst0 = arith.constant 0 : i64 - // CHECK: "gemmini.intr.config_st" - gemmini.config_st %cst4 : i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %aArray %aSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %bArray %bSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %cArray %cSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %dArray %dSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ex" - gemmini.config_ex {dataflow = 1} - // CHECK: "gemmini.intr.preload" - gemmini.preload %bSpAddr %cSpAddr %cst4 %cst4 %cst4 %cst4: i64 i64 i64 i64 i64 i64 - // CHECK: "gemmini.intr.compute_preloaded" - gemmini.compute_preloaded %aSpAddr %dSpAddr %cst4 %cst4 %cst4 %cst4 : i64 i64 i64 i64 i64 i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %cArray %cSpAddr : memref<4x4xi8> i64 - gemmini.print %cArray : memref<4x4xi8> - return %cst0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/matmul.mlir b/bb-tests/workloads/src/OpTest/gemmini/matmul.mlir deleted file mode 100644 index ee53ea39..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/matmul.mlir +++ /dev/null @@ -1,28 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --convert-linalg-to-gemmini | \ -// RUN: FileCheck %s - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %1 = arith.constant 1 : i8 - %2 = arith.constant 2 : i8 - %mem0 = memref.alloc() : memref<8x8xi8> - %mem1 = memref.alloc() : memref<8x8xi8> - %mem2 = memref.alloc() : memref<8x8xi8> - linalg.fill - ins(%2 : i8) - outs(%mem0 : memref<8x8xi8>) - linalg.fill - ins(%1 : i8) - outs(%mem1 : memref<8x8xi8>) - // CHECK: gemmini.tile_matmul %alloc %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} %alloc_{{[0-9]+}} - // CHECK-SAME: memref<8x8xi8> memref<8x8xi8> memref<8x8xi8> memref<8x8xi32> - linalg.matmul - ins(%mem0, %mem1 : memref<8x8xi8>, memref<8x8xi8>) - outs(%mem2 : memref<8x8xi8>) - gemmini.print %mem2 : memref<8x8xi8> - memref.dealloc %mem0 : memref<8x8xi8> - memref.dealloc %mem1 : memref<8x8xi8> - memref.dealloc %mem2 : memref<8x8xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/matrix-add-scale.mlir b/bb-tests/workloads/src/OpTest/gemmini/matrix-add-scale.mlir deleted file mode 100644 index babebf85..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/matrix-add-scale.mlir +++ /dev/null @@ -1,40 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s -memref.global "private" @gv1 : memref<4x4xi8> = dense<[[1, 2, 3, 4], - [5, 6, 7, 8], - [9, 10, 11, 12], - [13, 14, 15, 16]]> -memref.global "private" @gv2 : memref<4x4xi8> = dense<[[17, 18, 19, 20], - [21, 22, 23, 24], - [25, 26, 27, 28], - [29, 30, 31, 32]]> - -func.func @main() -> i64 { - %arrayA = memref.get_global @gv1 : memref<4x4xi8> - %arrayB = memref.get_global @gv2 : memref<4x4xi8> - %arrayC = memref.alloc() : memref<4x4xi8> - gemmini.print %arrayC : memref<4x4xi8> - // 10000000000000000000000000000000 - %aAccAddr = arith.constant 2147483648 : i64 - // 11000000000000000000000000000000 - %bAccAddr = arith.constant 3221225472 : i64 - // 10000000000000000000000000000000 - %cAccAddr = arith.constant 2147483648 - %cst4 = arith.constant 4 : i64 - %cst0 = arith.constant 0 : i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 {shrunk = true, scale = 2.0 : f32 } : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %arrayA %aAccAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 {shrunk = true, scale = 2.0 : f32 } : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %arrayB %bAccAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_st" - gemmini.config_st %cst4 : i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %arrayC %cAccAddr : memref<4x4xi8> i64 - gemmini.print %arrayC : memref<4x4xi8> - return %cst0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/matrix-add.mlir b/bb-tests/workloads/src/OpTest/gemmini/matrix-add.mlir deleted file mode 100644 index 3011f562..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/matrix-add.mlir +++ /dev/null @@ -1,41 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @gv1 : memref<4x4xi8> = dense<[[1, 2, 3, 4], - [5, 6, 7, 8], - [9, 10, 11, 12], - [13, 14, 15, 16]]> -memref.global "private" @gv2 : memref<4x4xi8> = dense<[[17, 18, 19, 20], - [21, 22, 23, 24], - [25, 26, 27, 28], - [29, 30, 31, 32]]> - -func.func @main() -> i64 { - %arrayA = memref.get_global @gv1 : memref<4x4xi8> - %arrayB = memref.get_global @gv2 : memref<4x4xi8> - %arrayC = memref.alloc() : memref<4x4xi8> - gemmini.print %arrayC : memref<4x4xi8> - // 10000000000000000000000000000000 - %aAccAddr = arith.constant 2147483648 : i64 - // 11000000000000000000000000000000 - %bAccAddr = arith.constant 3221225472 : i64 - // 10000000000000000000000000000000 - %cAccAddr = arith.constant 2147483648 - %cst4 = arith.constant 4 : i64 - %cst0 = arith.constant 0 : i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 {shrunk = true} : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %arrayA %aAccAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 {shrunk = true} : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %arrayB %bAccAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_st" - gemmini.config_st %cst4 : i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %arrayC %cAccAddr : memref<4x4xi8> i64 - gemmini.print %arrayC : memref<4x4xi8> - return %cst0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/mvin-mvout.mlir b/bb-tests/workloads/src/OpTest/gemmini/mvin-mvout.mlir deleted file mode 100644 index bf3c5c88..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/mvin-mvout.mlir +++ /dev/null @@ -1,36 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @gv : memref<2x16xi8> = dense<[[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15], - [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %stride16 = arith.constant 16 : i64 - %stride8 = arith.constant 8 : i64 - %spadAddr = arith.constant 0 : i64 - %arrayA = memref.get_global @gv : memref<2x16xi8> - %arrayB = memref.alloc() : memref<3x16xi8> - %arrayC = memref.alloc() : memref<2x8xi8> - gemmini.print %arrayB : memref<3x16xi8> - gemmini.print %arrayC : memref<2x8xi8> - // CHECK: "gemmini.intr.config_st" - // The mvout op's stride is 16. - gemmini.config_st %stride16 : i64 - // CHECK: "gemmini.intr.config_ld" - // The mvin op's stride is 16 - gemmini.config_ld %stride16 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %arrayA %spadAddr : memref<2x16xi8> i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %arrayB %spadAddr : memref<3x16xi8> i64 - // CHECK: "gemmini.intr.config_st" - // The mvout op's stride is 8 - gemmini.config_st %stride8 : i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %arrayC %spadAddr : memref<2x8xi8> i64 - gemmini.print %arrayB : memref<3x16xi8> - gemmini.print %arrayC : memref<2x8xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-igelu.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-conv-igelu.mlir deleted file mode 100644 index cea3487c..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-igelu.mlir +++ /dev/null @@ -1,52 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -// batchSize = 1 inputDim = 5 inChannels = 1 -memref.global "private" @input : memref<1x5x5x1xi8> = dense<[[[[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]]]]> - -// outChannels = 2 kernelDim = 3 inChannels = 1 -memref.global "private" @weight : memref<9x2xi8> = dense<[[-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2]]> - -// outChannels = 2 -memref.global "private" @bias : memref<2xi32> = dense<[1,1]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %3 = arith.constant 3 : i64 - %input = memref.get_global @input : memref<1x5x5x1xi8> - %weight = memref.get_global @weight : memref<9x2xi8> - %bias = memref.get_global @bias : memref<2xi32> - %output = memref.alloc() : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1, act = 3}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-layernorm.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-conv-layernorm.mlir deleted file mode 100644 index 8d89ca89..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-layernorm.mlir +++ /dev/null @@ -1,52 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -// batchSize = 1 inputDim = 5 inChannels = 1 -memref.global "private" @input : memref<1x5x5x1xi8> = dense<[[[[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]]]]> - -// outChannels = 2 kernelDim = 3 inChannels = 1 -memref.global "private" @weight : memref<9x2xi8> = dense<[[-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2]]> - -// outChannels = 2 -memref.global "private" @bias : memref<2xi32> = dense<[1,1]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %3 = arith.constant 3 : i64 - %input = memref.get_global @input : memref<1x5x5x1xi8> - %weight = memref.get_global @weight : memref<9x2xi8> - %bias = memref.get_global @bias : memref<2xi32> - %output = memref.alloc() : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1, act = 2}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-relu.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-conv-relu.mlir deleted file mode 100644 index d2bac046..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-relu.mlir +++ /dev/null @@ -1,52 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -// batchSize = 1 inputDim = 5 inChannels = 1 -memref.global "private" @input : memref<1x5x5x1xi8> = dense<[[[[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]]]]> - -// outChannels = 2 kernelDim = 3 inChannels = 1 -memref.global "private" @weight : memref<9x2xi8> = dense<[[-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2]]> - -// outChannels = 2 -memref.global "private" @bias : memref<2xi32> = dense<[1,1]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %3 = arith.constant 3 : i64 - %input = memref.get_global @input : memref<1x5x5x1xi8> - %weight = memref.get_global @weight : memref<9x2xi8> - %bias = memref.get_global @bias : memref<2xi32> - %output = memref.alloc() : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1, act = 1}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-softmax.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-conv-softmax.mlir deleted file mode 100644 index a2958bf1..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-conv-softmax.mlir +++ /dev/null @@ -1,52 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -// batchSize = 1 inputDim = 5 inChannels = 1 -memref.global "private" @input : memref<1x5x5x1xi8> = dense<[[[[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]]]]> - -// outChannels = 2 kernelDim = 3 inChannels = 1 -memref.global "private" @weight : memref<9x2xi8> = dense<[[-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2], - [-1, 2], [-1, 2], [-1, 2]]> - -// outChannels = 2 -memref.global "private" @bias : memref<2xi32> = dense<[1,1]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %3 = arith.constant 3 : i64 - %input = memref.get_global @input : memref<1x5x5x1xi8> - %weight = memref.get_global @weight : memref<9x2xi8> - %bias = memref.get_global @bias : memref<2xi32> - %output = memref.alloc() : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1, act = 4}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-conv.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-conv.mlir deleted file mode 100644 index 567e657b..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-conv.mlir +++ /dev/null @@ -1,39 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -// batchSize = 1 inputDim = 5 inChannels = 1 -memref.global "private" @input : memref<1x5x5x1xi8> = dense<[[[[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1]]]]> - -// outChannels = 2 kernelDim = 3 inChannels = 1 -memref.global "private" @weight : memref<9x2xi8> = dense<[[1, 2], [1, 2], [1, 2], - [1, 2], [1, 2], [1, 2], - [1, 2], [1, 2], [1, 2]]> - -// outChannels = 2 -memref.global "private" @bias : memref<2xi32> = dense<[1,1]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %3 = arith.constant 3 : i64 - %input = memref.get_global @input : memref<1x5x5x1xi8> - %weight = memref.get_global @weight : memref<9x2xi8> - %bias = memref.get_global @bias : memref<2xi32> - %output = memref.alloc() : memref<9x2xi8> - // CHECK: "gemmini.intr.loop_conv_ws_config1" - // CHECK: "gemmini.intr.loop_conv_ws_config2" - // CHECK: "gemmini.intr.loop_conv_ws_config3" - // CHECK: "gemmini.intr.loop_conv_ws_config4" - // CHECK: "gemmini.intr.loop_conv_ws_config5" - // CHECK: "gemmini.intr.loop_conv_ws_config6" - // CHECK: "gemmini.intr.loop_conv_ws" - // CHECK: "gemmini.intr.flush" - gemmini.tile_conv %input %weight %bias %output %3 %3 %3 {stride = 1}: - memref<1x5x5x1xi8> memref<9x2xi8> memref<2xi32> memref<9x2xi8> i64 i64 i64 - gemmini.print %output : memref<9x2xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-os.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-os.mlir deleted file mode 100644 index 78412703..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-os.mlir +++ /dev/null @@ -1,37 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -func.func @main() -> i8 { - %i0 = arith.constant 0 : i8 - %i1I8 = arith.constant 1 : i8 - %i2I8 = arith.constant 2 : i8 - %i2I32 = arith.constant 2 : i32 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %aArray = memref.alloc() {alignment = 16} : memref<64x64xi8> - %bArray = memref.alloc() {alignment = 16}: memref<64x64xi8> - %cArray = memref.alloc() {alignment = 16}: memref<64x64xi8> - %dArray = memref.alloc() {alignment = 64} : memref<64x64xi32> - %dim = memref.dim %aArray, %c0 : memref<64x64xi8> - scf.for %i = %c0 to %dim step %c1 { - scf.for %j = %c0 to %dim step %c1 { - memref.store %i1I8, %aArray[%i, %j] : memref<64x64xi8> - memref.store %i1I8, %bArray[%i, %j] : memref<64x64xi8> - memref.store %i2I32, %dArray[%i, %j] : memref<64x64xi32> - } - } - - gemmini.print %aArray : memref<64x64xi8> - gemmini.print %bArray : memref<64x64xi8> - gemmini.print %dArray : memref<64x64xi32> - // CHECK: "gemmini.intr.config_ld" - // CHECK: "gemmini.intr.mvin" - // CHECK: "gemmini.intr.preload" - // CHECK: "gemmini.intr.compute_preloaded" - // CHECK: "gemmini.intr.compute_accumulated" - // CHECK: "gemmini.intr.mvout" - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=0} : memref<64x64xi8> memref<64x64xi8> memref<64x64xi8> memref <64x64xi32> - gemmini.print %cArray : memref<64x64xi8> - return %i0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-igelu.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-igelu.mlir deleted file mode 100644 index fdc318bf..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-igelu.mlir +++ /dev/null @@ -1,49 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @g1 : memref<5x5xi8> = dense<[[1, 0, 0, 1, 0], [1, -1, 1, 0, 0], [-1, 0, 1, -1, 1], [1, 0, 0, 1, 0], [-1, 0, 0, -1, 0]]> -memref.global "private" @g2 : memref<5x5xi8> = dense<[[1, -1, 0, 0, 1], [1, 0, -1, 0, -1], [-1, -1, 0, -1, 1], [-1, 0, 0, 1, 0], [1, 0, 0, -1, 0]]> - - -func.func @main() -> i8 { - %i0 = arith.constant 0 : i8 - %i1I8 = arith.constant 1 : i8 - %minus1 = arith.constant -2 : i8 - %i2I8 = arith.constant 2 : i8 - %i2I32 = arith.constant 2 : i32 - %dI32 = arith.constant 0 : i32 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %aArray = memref.get_global @g1 : memref<5x5xi8> - %bArray = memref.get_global @g2 : memref<5x5xi8> - %cArray = memref.alloc() : memref<5x5xi8> - %dArray = memref.alloc() : memref<5x5xi32> - %dim_I = memref.dim %aArray, %c0 : memref<5x5xi8> - %dim_J = memref.dim %bArray, %c1 : memref<5x5xi8> - %dim_K = memref.dim %aArray, %c1 : memref<5x5xi8> - - scf.for %i3 = %c0 to %dim_I step %c1 { - scf.for %j3 = %c0 to %dim_J step %c1 { - memref.store %dI32, %dArray[%i3, %j3] : memref<5x5xi32> - } - } - - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - - // CHECK: "gemmini.intr.config_ex" - // CHECK: "gemmini.intr.config_st" - // CHECK: "gemmini.intr.config_ld" - // CHECK: "gemmini.intr.config_norm" - // CHECK: "gemmini.intr.loop_ws_config_bounds" - // CHECK: "gemmini.intr.loop_ws_config_addrs_ab" - // CHECK: "gemmini.intr.loop_ws_config_addrs_dc" - // CHECK: "gemmini.intr.loop_ws_config_strides_ab" - // CHECK: "gemmini.intr.loop_ws_config_strides_dc" - // CHECK: "gemmini.intr.loop_ws" - // CHECk: "gemmini.intr.flush" - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1, act=3, bertScale=0.8:f32}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - return %i0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-layernorm.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-layernorm.mlir deleted file mode 100644 index b9e5d933..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-layernorm.mlir +++ /dev/null @@ -1,48 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @g1 : memref<5x5xi8> = dense<[[1, 0, 0, 0, 0], [0, -1, 1, 0, 1], [-1, 0, -1, -1, 0], [-1, 0, 0, 1, 0], [0, 0, 0, 0, 0]]> -memref.global "private" @g2 : memref<5x5xi8> = dense<[[-1, 0, 1, 0, -1], [1, -1, 1, 0, -1], [-1, -1, -1, 1, 1], [-1, 1, 0, -1, 1], [-1, 0, 1, 1, 1]]> - - -func.func @main() -> i8 { - %i0 = arith.constant 0 : i8 - %i1I8 = arith.constant 1 : i8 - %minus1 = arith.constant -2 : i8 - %i2I8 = arith.constant 2 : i8 - %i2I32 = arith.constant 2 : i32 - %dI32 = arith.constant 0 : i32 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %aArray = memref.get_global @g1 : memref<5x5xi8> - %bArray = memref.get_global @g2 : memref<5x5xi8> - %cArray = memref.alloc() : memref<5x5xi8> - %dArray = memref.alloc() : memref<5x5xi32> - %dim_I = memref.dim %aArray, %c0 : memref<5x5xi8> - %dim_J = memref.dim %bArray, %c1 : memref<5x5xi8> - %dim_K = memref.dim %aArray, %c1 : memref<5x5xi8> - - scf.for %i3 = %c0 to %dim_I step %c1 { - scf.for %j3 = %c0 to %dim_J step %c1 { - memref.store %dI32, %dArray[%i3, %j3] : memref<5x5xi32> - } - } - - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - - // CHECK: "gemmini.intr.config_ex" - // CHECK: "gemmini.intr.config_st" - // CHECK: "gemmini.intr.config_ld" - // CHECK: "gemmini.intr.loop_ws_config_bounds" - // CHECK: "gemmini.intr.loop_ws_config_addrs_ab" - // CHECK: "gemmini.intr.loop_ws_config_addrs_dc" - // CHECK: "gemmini.intr.loop_ws_config_strides_ab" - // CHECK: "gemmini.intr.loop_ws_config_strides_dc" - // CHECK: "gemmini.intr.loop_ws" - // CHECk: "gemmini.intr.flush" - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1, act=2}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - return %i0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-relu.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-relu.mlir deleted file mode 100644 index 2e63385d..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-relu.mlir +++ /dev/null @@ -1,48 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @g1 : memref<5x5xi8> = dense<[[1, 0, 0, 1, 0], [1, -1, 1, 0, 0], [-1, 0, 1, -1, 1], [1, 0, 0, 1, 0], [-1, 0, 0, -1, 0]]> -memref.global "private" @g2 : memref<5x5xi8> = dense<[[1, -1, 0, 0, 1], [1, 0, -1, 0, -1], [-1, -1, 0, -1, 1], [-1, 0, 0, 1, 0], [1, 0, 0, -1, 0]]> - - -func.func @main() -> i8 { - %i0 = arith.constant 0 : i8 - %i1I8 = arith.constant 1 : i8 - %minus1 = arith.constant -2 : i8 - %i2I8 = arith.constant 2 : i8 - %i2I32 = arith.constant 2 : i32 - %dI32 = arith.constant 0 : i32 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %aArray = memref.get_global @g1 : memref<5x5xi8> - %bArray = memref.get_global @g2 : memref<5x5xi8> - %cArray = memref.alloc() : memref<5x5xi8> - %dArray = memref.alloc() : memref<5x5xi32> - %dim_I = memref.dim %aArray, %c0 : memref<5x5xi8> - %dim_J = memref.dim %bArray, %c1 : memref<5x5xi8> - %dim_K = memref.dim %aArray, %c1 : memref<5x5xi8> - - scf.for %i3 = %c0 to %dim_I step %c1 { - scf.for %j3 = %c0 to %dim_J step %c1 { - memref.store %dI32, %dArray[%i3, %j3] : memref<5x5xi32> - } - } - - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - - // CHECK: "gemmini.intr.config_ex" - // CHECK: "gemmini.intr.config_st" - // CHECK: "gemmini.intr.config_ld" - // CHECK: "gemmini.intr.loop_ws_config_bounds" - // CHECK: "gemmini.intr.loop_ws_config_addrs_ab" - // CHECK: "gemmini.intr.loop_ws_config_addrs_dc" - // CHECK: "gemmini.intr.loop_ws_config_strides_ab" - // CHECK: "gemmini.intr.loop_ws_config_strides_dc" - // CHECK: "gemmini.intr.loop_ws" - // CHECk: "gemmini.intr.flush" - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1, act=1}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - return %i0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-softmax.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-softmax.mlir deleted file mode 100644 index 18c46ad9..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul-ws-softmax.mlir +++ /dev/null @@ -1,49 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @g1 : memref<5x5xi8> = dense<[[1, 0, 0, 1, 0], [1, -1, 1, 0, 0], [-1, 0, 1, -1, 1], [1, 0, 0, 1, 0], [-1, 0, 0, -1, 0]]> -memref.global "private" @g2 : memref<5x5xi8> = dense<[[1, -1, 0, 0, 1], [1, 0, -1, 0, -1], [-1, -1, 0, -1, 1], [-1, 0, 0, 1, 0], [1, 0, 0, -1, 0]]> - - -func.func @main() -> i8 { - %i0 = arith.constant 0 : i8 - %i1I8 = arith.constant 1 : i8 - %minus1 = arith.constant -2 : i8 - %i2I8 = arith.constant 2 : i8 - %i2I32 = arith.constant 2 : i32 - %dI32 = arith.constant 0 : i32 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %aArray = memref.get_global @g1 : memref<5x5xi8> - %bArray = memref.get_global @g2 : memref<5x5xi8> - %cArray = memref.alloc() : memref<5x5xi8> - %dArray = memref.alloc() : memref<5x5xi32> - %dim_I = memref.dim %aArray, %c0 : memref<5x5xi8> - %dim_J = memref.dim %bArray, %c1 : memref<5x5xi8> - %dim_K = memref.dim %aArray, %c1 : memref<5x5xi8> - - scf.for %i3 = %c0 to %dim_I step %c1 { - scf.for %j3 = %c0 to %dim_J step %c1 { - memref.store %dI32, %dArray[%i3, %j3] : memref<5x5xi32> - } - } - - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - - // CHECK: "gemmini.intr.config_ex" - // CHECK: "gemmini.intr.config_st" - // CHECK: "gemmini.intr.config_ld" - // CHECK: "gemmini.intr.config_norm" - // CHECK: "gemmini.intr.loop_ws_config_bounds" - // CHECK: "gemmini.intr.loop_ws_config_addrs_ab" - // CHECK: "gemmini.intr.loop_ws_config_addrs_dc" - // CHECK: "gemmini.intr.loop_ws_config_strides_ab" - // CHECK: "gemmini.intr.loop_ws_config_strides_dc" - // CHECK: "gemmini.intr.loop_ws" - // CHECk: "gemmini.intr.flush" - gemmini.tile_matmul %aArray %bArray %cArray %dArray {dataflow=1, act=4, bertScale=0.05:f32}: memref<5x5xi8> memref<5x5xi8> memref<5x5xi8> memref<5x5xi32> - gemmini.print %cArray : memref<5x5xi8> - return %i0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-matmul.mlir deleted file mode 100644 index ef8e0041..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-matmul.mlir +++ /dev/null @@ -1,37 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -func.func @main() -> i8 { - %i0 = arith.constant 0 : i8 - %i1I8 = arith.constant 1 : i8 - %i2I8 = arith.constant 2 : i8 - %i2I32 = arith.constant 2 : i32 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %aArray = memref.alloc() : memref<64x64xi8> - %bArray = memref.alloc() : memref<64x64xi8> - %cArray = memref.alloc() : memref<64x64xi8> - %dArray = memref.alloc() : memref<64x64xi32> - %dim = memref.dim %aArray, %c0 : memref<64x64xi8> - scf.for %i = %c0 to %dim step %c1 { - scf.for %j = %c0 to %dim step %c1 { - memref.store %i1I8, %aArray[%i, %j] : memref<64x64xi8> - memref.store %i1I8, %bArray[%i, %j] : memref<64x64xi8> - memref.store %i2I32, %dArray[%i, %j] : memref<64x64xi32> - } - } - gemmini.print %aArray : memref<64x64xi8> - gemmini.print %bArray : memref<64x64xi8> - gemmini.print %dArray : memref<64x64xi32> - // CHECK: "gemmini.intr.loop_ws_config_bounds" - // CHECK: "gemmini.intr.loop_ws_config_addrs_ab" - // CHECK: "gemmini.intr.loop_ws_config_addrs_dc" - // CHECK: "gemmini.intr.loop_ws_config_strides_ab" - // CHECK: "gemmini.intr.loop_ws_config_strides_dc" - // CHECK: "gemmini.intr.loop_ws" - // CHECk: "gemmini.intr.flush" - gemmini.tile_matmul %aArray %bArray %cArray %dArray : memref<64x64xi8> memref<64x64xi8> memref<64x64xi8> memref <64x64xi32> - gemmini.print %cArray : memref<64x64xi8> - return %i0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/tile-rect-conv.mlir b/bb-tests/workloads/src/OpTest/gemmini/tile-rect-conv.mlir deleted file mode 100644 index 6d083d73..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/tile-rect-conv.mlir +++ /dev/null @@ -1,42 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -// batchSize = 1 inputRowDim = 5 inputColDim = 10 inChannels = 1 -memref.global "private" @input : memref<1x5x10x1xi8> = dense<[[[[1], [0], [-1], [0], [1], [1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1], [1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1], [1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1], [1], [0], [-1], [0], [1]], - [[1], [0], [-1], [0], [1], [1], [0], [-1], [0], [1]]]]> - -// outChannels = 2 kernelDim = 3 inChannels = 1 -memref.global "private" @weight : memref<9x2xi8> = dense<[[1, 2], [1, 2], [1, 2], - [1, 2], [1, 2], [1, 2], - [1, 2], [1, 2], [1, 2]]> - -// outChannels = 2 -memref.global "private" @bias : memref<2xi32> = dense<[1,1]> - -func.func @main() -> i64 { - %0 = arith.constant 0 : i64 - %3 = arith.constant 3 : i64 - %8 = arith.constant 8 : i64 - - %input = memref.get_global @input : memref<1x5x10x1xi8> - %weight = memref.get_global @weight : memref<9x2xi8> - %bias = memref.get_global @bias : memref<2xi32> - %output = memref.alloc() : memref<24x2xi8> - // CHECK: "gemmini.intr.config_st" - // CHECK: "gemmini.intr.config_ex" - // CHECK: "gemmini.intr.config_ld" - // CHECK: "gemmini.intr.mvin3" - // CHECK: "gemmini.intr.mvin" - // CHECK: "gemmini.intr.mvin2" - // CHECK: "gemmini.intr.preload" - // CHECK: "gemmini.intr.compute_preloaded" - // CHECK: "gemmini.intr.compute_accumulated" - gemmini.tile_conv %input %weight %bias %output %3 %8 %3 {stride = 1}: - memref<1x5x10x1xi8> memref<9x2xi8> memref<2xi32> memref<24x2xi8> i64 i64 i64 - gemmini.print %output : memref<24x2xi8> - return %0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/gemmini/transpose.mlir b/bb-tests/workloads/src/OpTest/gemmini/transpose.mlir deleted file mode 100644 index 07508383..00000000 --- a/bb-tests/workloads/src/OpTest/gemmini/transpose.mlir +++ /dev/null @@ -1,44 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: --lower-gemmini | \ -// RUN: FileCheck %s - -memref.global "private" @gv1 : memref<4x4xi8> = dense<[[1, 2, 3, 4], - [5, 6, 7, 8], - [9, 10, 11, 12], - [13, 14, 15, 16]]> -memref.global "private" @gv2 : memref<4x4xi8> = dense<[[1, 0, 0, 0], - [0, 1, 0, 0], - [0, 0, 1, 0], - [0, 0, 0, 1]]> - -func.func @main() -> i64 { - %in = memref.get_global @gv1 : memref<4x4xi8> - %identity = memref.get_global @gv2 : memref<4x4xi8> - %out = memref.alloc() : memref<4x4xi8> - gemmini.print %out : memref<4x4xi8> - %inSpAddr = arith.constant 0 : i64 - %outSpAddr = arith.constant 4 : i64 - %identitySpAddr = arith.constant 8 : i64 - %cst4 = arith.constant 4 : i64 - %cst0 = arith.constant 0 : i64 - // CHECK: "gemmini.intr.config_st" - gemmini.config_st %cst4 : i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %in %inSpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ld" - gemmini.config_ld %cst4 : i64 - // CHECK: "gemmini.intr.mvin" - gemmini.mvin %identity %identitySpAddr : memref<4x4xi8> i64 - // CHECK: "gemmini.intr.config_ex" - gemmini.config_ex {dataflow = 0, aTranspose = true } - // CHECK: "gemmini.intr.preload" - gemmini.preload_zeros %outSpAddr %cst4 %cst4 : i64 i64 i64 - // CHECK: "gemmini.intr.compute_preloaded" - gemmini.compute_preloaded %inSpAddr %identitySpAddr %cst4 %cst4 %cst4 %cst4 : i64 i64 i64 i64 i64 i64 - // CHECK: "gemmini.intr.mvout" - gemmini.mvout %out %outSpAddr : memref<4x4xi8> i64 - gemmini.print %out : memref<4x4xi8> - return %cst0 : i64 -} diff --git a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt index bc3531ac..19e13f0f 100644 --- a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt @@ -3,6 +3,10 @@ # Generate executables for different platforms #------------------------------------------------------------------------------- +# Resolve toy runtime paths +set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) +set(CRT0_S ${CTEST_TOY_WORKLOAD_DIR}/crt0.S) + # singlecore baremetal function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal.o") @@ -33,12 +37,14 @@ function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) COMMENT "Compiling ${MLIR_FILE} to singlecore baremetal object" ) - # Link (use htif_nano.specs crt0) + # Link with toy bbsim runtime (BBSimHarness MMIO) add_custom_command( OUTPUT ${EXECUTABLE} - COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} - ${OBJ_FILE} -o ${EXECUTABLE} - DEPENDS ${OBJ_FILE} + COMMAND ${ELF_CC} -O2 -static -march=rv64gc -mcmodel=medany -nostartfiles + -specs=nano.specs -specs=nosys.specs + -Wl,-T,${BBSIM_LD} + ${CRT0_S} ${OBJ_FILE} -o ${EXECUTABLE} + DEPENDS ${OBJ_FILE} ${CRT0_S} ${BBSIM_LD} COMMENT "Linking singlecore baremetal executable: ${EXECUTABLE}" ) diff --git a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt index 72d3ed5f..38e1f058 100644 --- a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt @@ -3,6 +3,10 @@ # Generate executables for different platforms #------------------------------------------------------------------------------- +# Resolve toy runtime paths +set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) +set(CRT0_S ${CTEST_TOY_WORKLOAD_DIR}/crt0.S) + # singlecore baremetal function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal.o") @@ -30,12 +34,14 @@ function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) COMMENT "Compiling ${MLIR_FILE} to singlecore baremetal object" ) - # Link (same as CTest singlecore: no start.S, use htif_nano.specs crt0) + # Link with toy bbsim runtime (BBSimHarness MMIO) add_custom_command( OUTPUT ${EXECUTABLE} - COMMAND ${ELF_CC} -O2 -static -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR} - ${OBJ_FILE} -o ${EXECUTABLE} - DEPENDS ${OBJ_FILE} + COMMAND ${ELF_CC} -O2 -static -march=rv64gc -mcmodel=medany -nostartfiles + -specs=nano.specs -specs=nosys.specs + -Wl,-T,${BBSIM_LD} + ${CRT0_S} ${OBJ_FILE} -o ${EXECUTABLE} + DEPENDS ${OBJ_FILE} ${CRT0_S} ${BBSIM_LD} COMMENT "Linking singlecore baremetal executable: ${EXECUTABLE}" ) diff --git a/bb-tests/workloads/src/tutorial/CMakeLists.txt b/bb-tests/workloads/src/tutorial/CMakeLists.txt index 7f31808a..2225d399 100644 --- a/bb-tests/workloads/src/tutorial/CMakeLists.txt +++ b/bb-tests/workloads/src/tutorial/CMakeLists.txt @@ -3,33 +3,40 @@ project(tutorial C) #------------------------------------------------------------------------------- # build linux version workload #------------------------------------------------------------------------------- -set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") -set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${LINK_FLAGS}") +set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc") -set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-g++") add_executable(tutorial-linux ${TUTORIAL_WORKLOAD_DIR}/tutorial.c) -add_custom_target(tutorial-linux-build ALL DEPENDS - tutorial-linux +add_custom_target(tutorial-linux-build ALL DEPENDS tutorial-linux COMMENT "Building linux workloads for tutorial" VERBATIM) #------------------------------------------------------------------------------- -# build baremetal version workload +# build baremetal version workload (BBSimHarness, same flags as toy) #------------------------------------------------------------------------------- set(ELF_CC "riscv64-unknown-elf-gcc") +set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) -set(C_FLAGS -std=c11 -g -fno-common -O2 -static - -fno-builtin-printf -specs=${HTIF_DIR}/htif_nano.specs -L${HTIF_DIR}) +set(C_FLAGS -std=c11 -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany + -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles + -Wl,-T,${BBSIM_LD} -I${WORKLOAD_LIB_DIR}) add_custom_target(tutorial-baremetal-build ALL - COMMAND ${ELF_CC} ${C_FLAGS} -o tutorial-baremetal ${TUTORIAL_WORKLOAD_DIR}/tutorial.c - DEPENDS ${TUTORIAL_WORKLOAD_DIR}/tutorial.c + COMMAND ${ELF_CC} ${C_FLAGS} + -o tutorial-baremetal + ${CTEST_TOY_WORKLOAD_DIR}/crt0.S + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c + ${TUTORIAL_WORKLOAD_DIR}/tutorial.c + DEPENDS + ${TUTORIAL_WORKLOAD_DIR}/tutorial.c + ${CTEST_TOY_WORKLOAD_DIR}/crt0.S + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c COMMENT "Building baremetal workloads for tutorial" VERBATIM) #------------------------------------------------------------------------------- -# build all version workload +# build all #------------------------------------------------------------------------------- add_custom_target(tutorial-build ALL DEPENDS tutorial-linux-build diff --git a/bbdev b/bbdev index 0d8ecd96..3ae5a826 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 0d8ecd9650673ef8a430642fc1524d7082efefc1 +Subproject commit 3ae5a826fa9e1dc563fd08dd904d70f5ed6adfd8 diff --git a/scripts/nix/build-env-riscv.nix b/scripts/nix/build-env-riscv.nix index fbedd598..ea5c7eef 100644 --- a/scripts/nix/build-env-riscv.nix +++ b/scripts/nix/build-env-riscv.nix @@ -33,53 +33,14 @@ let }) ]; }; - - # Build libgloss-htif library from upstream - libgloss-htif = pkgs.stdenv.mkDerivation { - pname = "libgloss-htif"; - version = "0.1"; - - src = pkgs.fetchFromGitHub { - owner = "ucb-bar"; - repo = "libgloss-htif"; - rev = "master"; - sha256 = "sha256-FXuN1xK5133QqoHI4EG7mvhk7K8J6//ar7Y1+IUPER0="; - }; - - nativeBuildInputs = [ pkgsCrossWithNano.buildPackages.gcc ]; - - configureFlags = [ - "--host=riscv64-unknown-elf" - ]; - - preConfigure = '' - export CC=riscv64-none-elf-gcc - export AR=riscv64-none-elf-ar - export RANLIB=riscv64-none-elf-ranlib - ''; - - enableParallelBuilding = true; - - installPhase = '' - mkdir -p $out/riscv64-unknown-elf/lib - - # Install library and specs files manually to bypass the Makefile check - install -m 644 libgloss_htif.a $out/riscv64-unknown-elf/lib/ - install -m 644 util/htif.specs $out/riscv64-unknown-elf/lib/ - install -m 644 util/htif_nano.specs $out/riscv64-unknown-elf/lib/ - install -m 644 util/htif_wrap.specs $out/riscv64-unknown-elf/lib/ - install -m 644 util/htif_argv.specs $out/riscv64-unknown-elf/lib/ - install -m 644 util/htif.ld $out/riscv64-unknown-elf/lib/ - ''; - }; in { # RISC-V embedded toolchain (bare metal), with riscv64-unknown-elf-* symlinks - # Now includes newlib-nano and libgloss-htif support + # Uses newlib-nano; baremetal runtime provided by bb-tests/workloads/src/CTest/toy/crt0.S riscv-embedded-gcc = pkgs.symlinkJoin { name = "riscv64-unknown-elf-gcc"; - paths = [ pkgsCrossWithNano.buildPackages.gcc libgloss-htif ]; + paths = [ pkgsCrossWithNano.buildPackages.gcc ]; postBuild = '' cd $out/bin for f in riscv64-none-elf-*; do From 908259ffbfc8a9a6aa910711beedda327b162c9f Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 18:35:08 +0800 Subject: [PATCH 170/238] [bb-tests] fix: update CMakeLists for workload directories and compilation flags --- bb-tests/workloads/src/CMakeLists.txt | 3 +- .../workloads/src/CTest/bebop/CMakeLists.txt | 44 ++++++++----------- .../workloads/src/CTest/toy/CMakeLists.txt | 17 +++---- .../workloads/src/tutorial/CMakeLists.txt | 2 +- 4 files changed, 26 insertions(+), 40 deletions(-) diff --git a/bb-tests/workloads/src/CMakeLists.txt b/bb-tests/workloads/src/CMakeLists.txt index 950d9a2f..5ca8cd9b 100644 --- a/bb-tests/workloads/src/CMakeLists.txt +++ b/bb-tests/workloads/src/CMakeLists.txt @@ -1,10 +1,9 @@ set(CTEST_WORKLOAD_DIR ${WORKLOAD_SRC_DIR}/CTest) -set(SPARSE_WORKLOAD_DIR ${WORKLOAD_SRC_DIR}/sparse) +set(CTEST_TOY_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/toy) set(MODELTEST_WORKLOAD_DIR ${WORKLOAD_SRC_DIR}/ModelTest) set(OPTEST_WORKLOAD_DIR ${WORKLOAD_SRC_DIR}/OpTest) set(TUTORIAL_WORKLOAD_DIR ${WORKLOAD_SRC_DIR}/tutorial) -# add_subdirectory(sparse) add_subdirectory(CTest) add_subdirectory(ModelTest) add_subdirectory(OpTest) diff --git a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt index 3eff5fcf..dca2b4dc 100644 --- a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt @@ -1,5 +1,4 @@ set(ELF_CC "riscv64-unknown-elf-gcc") -set(LINUX_CC "riscv64-unknown-linux-gnu-g++") #------------------------------------------------------------------------------- # Set baremetal compilation flags @@ -9,25 +8,21 @@ set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles -Wl,-T,${BBSIM_LD} -I${CTEST_TOY_WORKLOAD_DIR}) -#------------------------------------------------------------------------------- -# Define common compilation step functions -#------------------------------------------------------------------------------- - #------------------------------------------------------------------------------- # Generate executables for different platforms #------------------------------------------------------------------------------- set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-g++") set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gc") + # Generate Linux version executables function(add_linux_test_target TEST_NAME SOURCE_FILE) set(EXECUTABLE "${TEST_NAME}-linux") - add_executable(${EXECUTABLE} ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c) - target_include_directories(${EXECUTABLE} PRIVATE - ${WORKLOAD_LIB_DIR} - ) + add_executable(${EXECUTABLE} + ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c) + target_include_directories(${EXECUTABLE} PRIVATE ${WORKLOAD_LIB_DIR}) + set_target_properties(${EXECUTABLE} PROPERTIES LINKER_LANGUAGE C) endfunction() # Generate multicore baremetal version executables @@ -36,12 +31,14 @@ function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} ${CTEST_TOY_WORKLOAD_DIR}/start.S + COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} + ${CTEST_TOY_WORKLOAD_DIR}/start.S -DMULTICORE=3 ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} - DEPENDS ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + DEPENDS + ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/start.S COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} @@ -61,7 +58,8 @@ function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} -I${WORKLOAD_LIB_DIR} - DEPENDS ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} + DEPENDS + ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} @@ -77,30 +75,24 @@ function(add_cross_platform_test_target TEST_NAME SOURCE_FILE) add_multicore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) add_singlecore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - # Create a master target that builds all platforms simultaneously add_custom_target(${TEST_NAME} - DEPENDS ${TEST_NAME}-linux ${TEST_NAME}_multicore_baremetal ${TEST_NAME}_singlecore_baremetal + DEPENDS + ${TEST_NAME}-linux + ${TEST_NAME}_multicore_baremetal + ${TEST_NAME}_singlecore_baremetal COMMENT "Building ${TEST_NAME} for all platforms" ) endfunction() #------------------------------------------------------------------------------- -# build linux version workload (current not supported) +# Build list #------------------------------------------------------------------------------- -set(LINK_FLAGS "-static -Wl,--no-dynamic-linker") -set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${LINK_FLAGS}") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static -Wl,--no-dynamic-linker") -# add_library(buckyball-lib STATIC ${CTEST_WORKLOAD_DIR}/buckyball.c) -# target_include_directories(buckyball-lib PRIVATE ${WORKLOAD_LIB_DIR}) - -#------------------------------------------------------------------------------- -# Build list - use cross-platform function to generate all test targets -#------------------------------------------------------------------------------- add_cross_platform_test_target(ctest_mvin_mvout_bebop_test mvin_mvout_test.c) add_cross_platform_test_target(ctest_mvin_mvout_mset_bebop_test mvin_mvout_mset_test.c) add_cross_platform_test_target(ctest_mvin_mvout_acc_bebop_test mvin_mvout_acc_test.c) -# Create master build target add_custom_target(buckyball-CTest-bebop-build ALL DEPENDS ctest_mvin_mvout_bebop_test ctest_mvin_mvout_mset_bebop_test diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 292ffaf5..0f717c69 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -1,5 +1,4 @@ set(ELF_CC "riscv64-unknown-elf-gcc") -set(LINUX_CC "riscv64-unknown-linux-gnu-g++") #------------------------------------------------------------------------------- # Set baremetal compilation flags @@ -9,25 +8,21 @@ set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles -Wl,-T,${BBSIM_LD} -I${CTEST_TOY_WORKLOAD_DIR}) -#------------------------------------------------------------------------------- -# Define common compilation step functions -#------------------------------------------------------------------------------- - #------------------------------------------------------------------------------- # Generate executables for different platforms #------------------------------------------------------------------------------- set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_CXX_COMPILER "riscv64-unknown-linux-gnu-g++") set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gc") + # Generate Linux version executables function(add_linux_test_target TEST_NAME SOURCE_FILE) set(EXECUTABLE "${TEST_NAME}-linux") - add_executable(${EXECUTABLE} ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c) - target_include_directories(${EXECUTABLE} PRIVATE - ${WORKLOAD_LIB_DIR} - ) + add_executable(${EXECUTABLE} + ${CTEST_TOY_WORKLOAD_DIR}/${SOURCE_FILE} + ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c) + target_include_directories(${EXECUTABLE} PRIVATE ${WORKLOAD_LIB_DIR}) + set_target_properties(${EXECUTABLE} PROPERTIES LINKER_LANGUAGE C) endfunction() # Generate multicore baremetal version executables diff --git a/bb-tests/workloads/src/tutorial/CMakeLists.txt b/bb-tests/workloads/src/tutorial/CMakeLists.txt index 2225d399..5eb6ba04 100644 --- a/bb-tests/workloads/src/tutorial/CMakeLists.txt +++ b/bb-tests/workloads/src/tutorial/CMakeLists.txt @@ -18,7 +18,7 @@ add_custom_target(tutorial-linux-build ALL DEPENDS tutorial-linux set(ELF_CC "riscv64-unknown-elf-gcc") set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) -set(C_FLAGS -std=c11 -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany +set(C_FLAGS -std=gnu11 -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles -Wl,-T,${BBSIM_LD} -I${WORKLOAD_LIB_DIR}) From 127aea54c75930e6cfe3af52110dce44d9478cf0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 19:11:46 +0800 Subject: [PATCH 171/238] [bbdev] update: bump bbdev to the latest version --- arch/src/csrc/src/monitor/ioe/tsi_stub.cc | 12 ++++++++++++ bbdev | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 arch/src/csrc/src/monitor/ioe/tsi_stub.cc diff --git a/arch/src/csrc/src/monitor/ioe/tsi_stub.cc b/arch/src/csrc/src/monitor/ioe/tsi_stub.cc new file mode 100644 index 00000000..36647b0f --- /dev/null +++ b/arch/src/csrc/src/monitor/ioe/tsi_stub.cc @@ -0,0 +1,12 @@ +// tsi_stub.cc — stub for SimTSI DPI-C symbol. +// SimTSI is instantiated by chipyard's AbstractConfig via +// WithSimTSIOverSerialTL, but we don't use TSI. This stub satisfies the linker +// without pulling in fesvr. +extern "C" int tsi_tick(int chip_id, unsigned char out_valid, + unsigned char *out_ready, int out_bits, + unsigned char *in_valid, unsigned char in_ready, + int *in_bits) { + *out_ready = 0; + *in_valid = 0; + return 0; +} diff --git a/bbdev b/bbdev index 3ae5a826..8eb1303b 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 3ae5a826fa9e1dc563fd08dd904d70f5ed6adfd8 +Subproject commit 8eb1303b9d7ae16f1b3bc0a9cdec2ff50f8a4775 From 7684f0f9768c30ed80cd9dd7bd1118fdcaa3ad66 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 21:52:19 +0800 Subject: [PATCH 172/238] [arch] fix: update mmio_tick for rising-edge detection and clean up BBSimHarness configuration --- arch/src/csrc/src/monitor/ioe/mmio.cc | 10 ++-- .../scala/sims/verilator/BBSimHarness.scala | 31 ++++------- arch/src/main/scala/sims/verilator/README.md | 31 ----------- .../scala/sims/verilator/TargetConfig.scala | 53 +++---------------- bbdev | 2 +- 5 files changed, 27 insertions(+), 100 deletions(-) delete mode 100644 arch/src/main/scala/sims/verilator/README.md diff --git a/arch/src/csrc/src/monitor/ioe/mmio.cc b/arch/src/csrc/src/monitor/ioe/mmio.cc index 78fdd49b..f7ff0560 100644 --- a/arch/src/csrc/src/monitor/ioe/mmio.cc +++ b/arch/src/csrc/src/monitor/ioe/mmio.cc @@ -25,10 +25,14 @@ static void uart_putchar(char ch) { } // Called once per posedge after eval(). -// io_mmio_fire is RegNext(wFire) — a 1-cycle register pulse. addr and data -// are stable registers latched on wFire, so they are always valid when fire=1. +// Rising-edge detection guards against MMIO clock being slower than the +// sim fast-clock — without it each character would be repeated multiple times. void mmio_tick() { - if (!top->io_mmio_fire) + static uint8_t prev_fire = 0; + uint8_t cur_fire = top->io_mmio_fire ? 1 : 0; + bool rising = (!prev_fire && cur_fire); + prev_fire = cur_fire; + if (!rising) return; uint64_t addr = top->io_mmio_fire_addr; diff --git a/arch/src/main/scala/sims/verilator/BBSimHarness.scala b/arch/src/main/scala/sims/verilator/BBSimHarness.scala index 1a80df9f..7f9404be 100644 --- a/arch/src/main/scala/sims/verilator/BBSimHarness.scala +++ b/arch/src/main/scala/sims/verilator/BBSimHarness.scala @@ -4,21 +4,19 @@ import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Config, Parameters} -import freechips.rocketchip.subsystem.WithDefaultMMIOPort import chipyard.harness.{HarnessBinder, HasHarnessInstantiators} import chipyard.iobinders.{AXI4MMIOPort, UARTPort} // ============================================================================= -// WithBBSimMMIO: wire AXI4 MMIO port. +// WithBBSimMMIO: wire AXI4 MMIO port to C++ mmio_tick(). // -// All registers run in port.io.clock domain (= harness clock = 1 GHz, thanks -// to WithUniformBusFrequencies(1000)). C++ samples three stable register -// outputs each posedge: -// - firePulse = RegNext(wFire) — 1-cycle pulse, no debounce needed -// - latchedAddr = Reg latched on AW — stable address -// - latchedData = RegEnable on wFire — stable write data -// bPending is set on wFire (not delayed) so the B response reaches the CPU +// All registers run in port.io.clock domain (= 1 GHz, from WithUniformBusFrequencies). +// C++ samples three stable register outputs each posedge: +// - firePulse = RegNext(wFire) — 1-cycle pulse, no debounce needed +// - latchedAddr = Reg latched on AW — stable address +// - latchedData = RegEnable on wFire — stable write data +// bPending is set on wFire (not delayed) so B response reaches the CPU // one cycle before C++ processes the event. // ============================================================================= class WithBBSimMMIO @@ -62,7 +60,6 @@ class WithBBSimMMIO port.io.bits.b.bits.resp := 0.U // --- Fire pulse for C++ mmio_tick() --- - // RegNext delays 1 cycle; addr/data are stable registers at that point. val firePulse = RegNext(wFire, false.B) th.io.mmio_fire := firePulse th.io.mmio_fire_addr := latchedAddr @@ -92,14 +89,15 @@ class WithNoUARTAdapter }) // ============================================================================= -// BBSimConfig +// BBSimConfig: harness-level config for BBSimHarness. +// Concrete VerilatorConfigs (e.g. BuckyballToyVerilatorConfig) extend this +// with WithDefaultMMIOPort + SoC config. // ============================================================================= class BBSimConfig extends Config( new WithNoUARTAdapter ++ new WithBBSimMMIO ++ - new WithDefaultMMIOPort ++ - new chipyard.config.WithUniformBusFrequencies(1000.0) ++ // match harness 1 GHz so MMIO clock = harness clock + new chipyard.config.WithUniformBusFrequencies(1000.0) ++ new chipyard.harness.WithBlackBoxSimMem ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithTieOffInterrupts ++ @@ -113,13 +111,6 @@ class BBSimConfig new chipyard.iobinders.WithNMITiedOff ) -class BuckyballToyBBSimConfig - extends Config( - new BBSimConfig ++ - new WithCustomBootROM ++ - new examples.toy.BuckyballToyConfig - ) - // ============================================================================= // BBSimHarness // ============================================================================= diff --git a/arch/src/main/scala/sims/verilator/README.md b/arch/src/main/scala/sims/verilator/README.md deleted file mode 100644 index 5971340d..00000000 --- a/arch/src/main/scala/sims/verilator/README.md +++ /dev/null @@ -1,31 +0,0 @@ -# Verilator Simulation Configuration - -## Overview - -This directory contains Buckyball system simulation configuration for the Verilator platform. Verilator is an open-source Verilog/SystemVerilog simulator that compiles RTL code into high-performance C++ simulation models, providing a fast functional simulation and verification environment. - -## File Structure - -``` -verilator/ -└── Elaborate.scala - Verilator elaboration configuration -``` - -## Core Implementation - -### Elaborate.scala - -This file implements the Verilog generation and elaboration process for the Buckyball system: - -```scala -object Elaborate extends App { - val config = new examples.toy.BuckyballToyConfig - val params = config.toInstance - - ChiselStage.emitSystemVerilogFile( - new chipyard.harness.TestHarness()(config.toInstance), - firtoolOpts = args, - args = Array.empty // Pass command line arguments directly - ) -} -``` diff --git a/arch/src/main/scala/sims/verilator/TargetConfig.scala b/arch/src/main/scala/sims/verilator/TargetConfig.scala index b364724e..f67860e5 100644 --- a/arch/src/main/scala/sims/verilator/TargetConfig.scala +++ b/arch/src/main/scala/sims/verilator/TargetConfig.scala @@ -2,10 +2,10 @@ package sims.verilator import chisel3._ import _root_.circt.stage.ChiselStage -import org.chipsalliance.cde.config.{Config, Parameters} +import org.chipsalliance.cde.config.Config import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} -import freechips.rocketchip.subsystem.InSubsystem +import freechips.rocketchip.subsystem.{InSubsystem, WithDefaultMMIOPort} class WithCustomBootROM extends Config((site, here, up) => { @@ -16,22 +16,20 @@ class WithCustomBootROM class BuckyballToyVerilatorConfig extends Config( - new WithCustomBootROM ++ + new BBSimConfig ++ + new WithDefaultMMIOPort ++ + new WithCustomBootROM ++ new examples.toy.BuckyballToyConfig ) class BuckyballGobanVerilatorConfig extends Config( - new WithCustomBootROM ++ + new BBSimConfig ++ + new WithDefaultMMIOPort ++ + new WithCustomBootROM ++ new examples.goban.BuckyballGobanConfig ) -class BuckyballGemminiVerilatorConfig - extends Config( - new WithCustomBootROM ++ - new gemmini.DefaultGemminiConfig - ) - object Elaborate extends App { if (args.isEmpty) { println("Usage: Elaborate [firtool-opts...]") @@ -39,41 +37,6 @@ object Elaborate extends App { sys.exit(1) } - val configClassName = args(0) - println(s"Elaborating with config class: $configClassName") - - val config: Config = - try { - val configClass = Class.forName(configClassName) - configClass.getDeclaredConstructor().newInstance().asInstanceOf[Config] - } catch { - case e: ClassNotFoundException => - println(s"Error: Config class not found: $configClassName") - sys.exit(1) - case e: Exception => - println(s"Error loading config class: ${e.getMessage}") - e.printStackTrace() - sys.exit(1) - } - - ChiselStage.emitSystemVerilogFile( - new chipyard.harness.TestHarness()(config.toInstance), - // Remaining parameters passed to firtool - firtoolOpts = args.drop(1), - args = Array.empty - ) -} - -// BBSimElaborate: elaborates BBSimHarness instead of TestHarness. -// Used for bdb-based simulation (no fesvr, ELF loaded via libelf). -// Usage: BBSimElaborate sims.verilator.BuckyballToyBBSimConfig [firtool-opts...] -object BBSimElaborate extends App { - if (args.isEmpty) { - println("Usage: BBSimElaborate [firtool-opts...]") - println("Example: BBSimElaborate sims.verilator.BuckyballToyBBSimConfig") - sys.exit(1) - } - val configClassName = args(0) println(s"Elaborating BBSimHarness with config: $configClassName") diff --git a/bbdev b/bbdev index 8eb1303b..d7c8a24f 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 8eb1303b9d7ae16f1b3bc0a9cdec2ff50f8a4775 +Subproject commit d7c8a24fda92a1aa152157e4ad7445fae91a335f From 38dc6085b06555cf4e72866bac5046fb083f051c Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 12 Mar 2026 22:14:15 +0800 Subject: [PATCH 173/238] [ci] fix: update verilator configuration in CI workflows --- .github/workflows/pr.yml | 2 +- .github/workflows/test.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/pr.yml b/.github/workflows/pr.yml index 462abe80..c7310683 100644 --- a/.github/workflows/pr.yml +++ b/.github/workflows/pr.yml @@ -49,7 +49,7 @@ jobs: run: | cd ~/Code/buckyball nix develop -c bbdev verilator --clean - nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyBBSimConfig' + nix develop -c bbdev verilator --verilog '--config sims.verilator.sims.verilator.BuckyballToyVerilatorConfig' nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index e1d20c25..da390933 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -44,7 +44,7 @@ jobs: run: | cd ~/Code/buckyball nix develop -c bbdev verilator --clean - nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyBBSimConfig' + nix develop -c bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' nix develop -c bbdev verilator --build '--jobs 16' - name: Smoke Test From 02d799383509b082b498af96e6c9cc7d82757e8e Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Mar 2026 09:48:58 +0800 Subject: [PATCH 174/238] [arch] refactor: simplified RoB design and remove outdated limitation --- .../scala/framework/balldomain/rs/rob.scala | 191 -------- .../frontend/globalrs/GlobalROB.scala | 255 ++++------ .../frontend/globalrs/ITraceDPI.scala | 48 ++ .../frontend/scoreboard/BankScoreboard.scala | 56 +-- .../scala/sims/pegasus/PegasusHarness.scala | 218 ++++----- .../sims/pegasus/PegasusHarnessBinders.scala | 128 ++--- .../scala/sims/pegasus/TargetConfigs.scala | 80 +-- pegasus/.gitignore | 5 - pegasus/README.md | 2 - .../src/main/scala/pegasus/PegasusShell.scala | 462 ------------------ .../chisel/src/main/scala/pegasus/SCU.scala | 207 -------- .../src/main/scala/pegasus/UARTCapture.scala | 128 ----- .../scala/pegasus/blackbox/HBM2BlackBox.scala | 115 ----- .../scala/pegasus/blackbox/XDMABlackBox.scala | 170 ------- pegasus/driver/.gitignore | 2 - pegasus/driver/CMakeLists.txt | 35 -- pegasus/driver/include/pegasus.h | 132 ----- pegasus/driver/src/elf.cc | 185 ------- pegasus/driver/src/main.cc | 156 ------ pegasus/driver/src/scu.cc | 49 -- pegasus/driver/src/uart.cc | 17 - pegasus/driver/src/xdma.cc | 124 ----- pegasus/flake.lock | 61 --- pegasus/flake.nix | 89 ---- pegasus/vivado/au280.xdc | 79 --- pegasus/vivado/build.tcl | 169 ------- pegasus/vivado/ip/axi_crossbar_ip.tcl | 37 -- pegasus/vivado/ip/hbm2_ip.tcl | 31 -- pegasus/vivado/ip/xdma_ip.tcl | 25 - pegasus/vivado/synth_only.tcl | 58 --- 30 files changed, 373 insertions(+), 2941 deletions(-) delete mode 100644 arch/src/main/scala/framework/balldomain/rs/rob.scala create mode 100644 arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala delete mode 100644 pegasus/.gitignore delete mode 100644 pegasus/README.md delete mode 100644 pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala delete mode 100644 pegasus/chisel/src/main/scala/pegasus/SCU.scala delete mode 100644 pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala delete mode 100644 pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala delete mode 100644 pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala delete mode 100644 pegasus/driver/.gitignore delete mode 100644 pegasus/driver/CMakeLists.txt delete mode 100644 pegasus/driver/include/pegasus.h delete mode 100644 pegasus/driver/src/elf.cc delete mode 100644 pegasus/driver/src/main.cc delete mode 100644 pegasus/driver/src/scu.cc delete mode 100644 pegasus/driver/src/uart.cc delete mode 100644 pegasus/driver/src/xdma.cc delete mode 100644 pegasus/flake.lock delete mode 100644 pegasus/flake.nix delete mode 100644 pegasus/vivado/au280.xdc delete mode 100644 pegasus/vivado/build.tcl delete mode 100644 pegasus/vivado/ip/axi_crossbar_ip.tcl delete mode 100644 pegasus/vivado/ip/hbm2_ip.tcl delete mode 100644 pegasus/vivado/ip/xdma_ip.tcl delete mode 100644 pegasus/vivado/synth_only.tcl diff --git a/arch/src/main/scala/framework/balldomain/rs/rob.scala b/arch/src/main/scala/framework/balldomain/rs/rob.scala deleted file mode 100644 index 37d2e0ca..00000000 --- a/arch/src/main/scala/framework/balldomain/rs/rob.scala +++ /dev/null @@ -1,191 +0,0 @@ -package framework.balldomain.rs - -import chisel3._ -import chisel3.util._ -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.top.GlobalConfig - -// ROB entry data structure - preserves ROB ID to support out-of-order completion -class RobEntry(val b: GlobalConfig) extends Bundle { - val cmd = new BallRsIssue(b) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -class ROB(val b: GlobalConfig) extends Module { - - val io = IO(new Bundle { - // Allocation interface - val alloc = Flipped(new DecoupledIO(new BallRsIssue(b))) - // Externally specified rob_id - val alloc_rob_id = Input(UInt(log2Up(b.frontend.rob_entries).W)) - - // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new RobEntry(b)) - - // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(b.frontend.rob_entries).W))) - - // Commit interface - commit completed head instruction - // val commit = new DecoupledIO(new RobEntry) - - // Status signals - exposed to reservation station for decision making - val empty = Output(Bool()) - val full = Output(Bool()) - // head pointer position - val head_ptr = Output(UInt(log2Up(b.frontend.rob_entries).W)) - // Number of issued but uncompleted instructions - val issued_count = Output(UInt(log2Up(b.frontend.rob_entries + 1).W)) - // Whether each entry is valid - val entry_valid = Output(Vec(b.frontend.rob_entries, Bool())) - // Whether each entry is complete - val entry_complete = Output(Vec(b.frontend.rob_entries, Bool())) - }) - - // Circular ROB structure - // Initialize to zero to avoid X states in FPGA - val robEntries = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(0.U.asTypeOf(new RobEntry(b))))) - // Whether entry is valid - val robValid = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) - // Whether entry is issued - val robIssued = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) - // Whether entry is complete - val robComplete = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) - - // Circular queue pointers - // Points to oldest uncommitted instruction - val headPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - // Points to next position to allocate - val tailPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - // ROB ID circular counter - val robIdCounter = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - - // Number of issued but uncompleted instructions (used to limit issue) - val issuedCount = RegInit(0.U(log2Up(b.frontend.rob_entries + 1).W)) - // Maximum issue limit: half of ROB depth - val maxIssueLimit = (b.frontend.rob_entries / 2).U - - // Queue status - val isEmpty = headPtr === tailPtr && !robValid(headPtr) - val isFull = headPtr === tailPtr && robValid(headPtr) - - val count = Mux( - isFull, - b.frontend.rob_entries.U, - Mux(tailPtr >= headPtr, tailPtr - headPtr, b.frontend.rob_entries.U + tailPtr - headPtr) - ) - -// ----------------------------------------------------------------------------- -// Inbound - instruction allocation -// ----------------------------------------------------------------------------- - io.alloc.ready := !isFull - - when(io.alloc.fire) { - robEntries(tailPtr).cmd := io.alloc.bits - robEntries(tailPtr).rob_id := robIdCounter - robValid(tailPtr) := true.B - robIssued(tailPtr) := false.B - robComplete(tailPtr) := false.B - - // Update tail pointer and rob_id counter (circular) - tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) - robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) - } - -// ----------------------------------------------------------------------------- -// Completion signal processing -// ----------------------------------------------------------------------------- - io.complete.ready := true.B - when(io.complete.fire) { - val completeId = io.complete.bits - robComplete(completeId) := true.B - // When complete, decrement issued count - when(robIssued(completeId)) { - issuedCount := issuedCount - 1.U - } - } - -// ----------------------------------------------------------------------------- -// Outbound - issue instructions in order (starting from head) -// ----------------------------------------------------------------------------- - // Find first valid and unissued instruction starting from head - val canIssue = Wire(Bool()) - val issuePtr = Wire(UInt(log2Up(b.frontend.rob_entries).W)) - - // Default values - canIssue := false.B - issuePtr := headPtr - - // Scan from head to find first issuable instruction - val scanValid = Wire(Vec(b.frontend.rob_entries, Bool())) - for (i <- 0 until b.frontend.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) - scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) - } - - // Find first issuable position - val firstValid = PriorityEncoder(scanValid.asUInt) - val hasValid = scanValid.asUInt.orR - - val actualIssuePtr = Mux( - headPtr + firstValid >= b.frontend.rob_entries.U, - headPtr + firstValid - b.frontend.rob_entries.U, - headPtr + firstValid - ) - - // Can only issue if issue limit is not reached - val canIssueMore = issuedCount < maxIssueLimit - canIssue := hasValid && canIssueMore - issuePtr := actualIssuePtr - - io.issue.valid := canIssue - io.issue.bits := robEntries(issuePtr) - - when(io.issue.fire) { - robIssued(issuePtr) := true.B - issuedCount := issuedCount + 1.U - } - -// ----------------------------------------------------------------------------- -// Instruction commit - commit all completed instructions out-of-order -// ----------------------------------------------------------------------------- - for (i <- 0 until b.frontend.rob_entries) { - when(robValid(i.U) && robComplete(i.U)) { - robValid(i.U) := false.B - robIssued(i.U) := false.B - robComplete(i.U) := false.B - } - } - - // Update head pointer: skip all completed (about to be cleared) positions - // Find first "valid and incomplete" instruction position starting from head - val nextHeadCandidates = Wire(Vec(b.frontend.rob_entries, Bool())) - for (i <- 0 until b.frontend.rob_entries) { - val ptr = Mux(headPtr + i.U >= b.frontend.rob_entries.U, headPtr + i.U - b.frontend.rob_entries.U, headPtr + i.U) - // Entry is valid and incomplete (will not be committed) - nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) - } - - val hasUncommitted = nextHeadCandidates.asUInt.orR - val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) - - val nextHeadPtr = Mux( - headPtr + nextHeadOffset >= b.frontend.rob_entries.U, - headPtr + nextHeadOffset - b.frontend.rob_entries.U, - headPtr + nextHeadOffset - ) - - // Update head pointer: - // - If there are uncompleted instructions, move head to first uncompleted position - // - If there are no uncompleted instructions (all complete), move head to tail (ROB is empty) - headPtr := Mux(hasUncommitted, nextHeadPtr, tailPtr) - -// ----------------------------------------------------------------------------- -// Status signals - exposed to reservation station -// ----------------------------------------------------------------------------- - io.empty := isEmpty - io.full := isFull - io.head_ptr := headPtr - io.issued_count := issuedCount - io.entry_valid := robValid - io.entry_complete := robComplete -} diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index e39aebe6..f1efba2a 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -8,83 +8,35 @@ import framework.top.GlobalConfig import framework.frontend.decoder.PostGDCmd import framework.frontend.scoreboard.BankScoreboard -// DPI-C BlackBox for instruction trace -class ITraceDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val is_issue = Input(UInt(8.W)) - val rob_id = Input(UInt(32.W)) - val domain_id = Input(UInt(32.W)) - val funct = Input(UInt(32.W)) - val rs1 = Input(UInt(64.W)) - val rs2 = Input(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "ITraceDPI.v", - """ - |import "DPI-C" function void dpi_itrace( - | input byte unsigned is_issue, - | input int unsigned rob_id, - | input int unsigned domain_id, - | input int unsigned funct, - | input longint unsigned rs1, - | input longint unsigned rs2 - |); - | - |module ITraceDPI( - | input [7:0] is_issue, - | input [31:0] rob_id, - | input [31:0] domain_id, - | input [31:0] funct, - | input [63:0] rs1, - | input [63:0] rs2, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2); - | end - | end - |endmodule - """.stripMargin - ) -} - @instantiable class GlobalROB(val b: GlobalConfig) extends Module { + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) val bankIdLen = b.frontend.bank_id_len @public val io = IO(new Bundle { - // Allocation interface - val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) - - // Issue interface - issue uncompleted head instruction - val issue = new DecoupledIO(new GlobalRobEntry(b)) - - // Completion interface - report instruction completion - val complete = Flipped(new DecoupledIO(UInt(log2Up(b.frontend.rob_entries).W))) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) + val issue = new DecoupledIO(new GlobalRobEntry(b)) + val complete = Flipped(new DecoupledIO(UInt(idWidth.W))) - // Status signals - exposed to reservation station for decision making val empty = Output(Bool()) val full = Output(Bool()) - // head pointer position - val head_ptr = Output(UInt(log2Up(b.frontend.rob_entries).W)) - // Number of issued but uncompleted instructions - val issued_count = Output(UInt(log2Up(b.frontend.rob_entries + 1).W)) - // Whether each entry is valid - val entry_valid = Output(Vec(b.frontend.rob_entries, Bool())) - // Whether each entry is complete - val entry_complete = Output(Vec(b.frontend.rob_entries, Bool())) + val head_ptr = Output(UInt(idWidth.W)) + val issued_count = Output(UInt(log2Up(robDepth + 1).W)) + val entry_valid = Output(Vec(robDepth, Bool())) + val entry_complete = Output(Vec(robDepth, Bool())) }) - // Bank Scoreboard — instruction-agnostic hazard detection - val scoreboard: Instance[BankScoreboard] = Instantiate(new BankScoreboard(b.memDomain.bankNum, b.frontend.rob_entries)) + // --------------------------------------------------------------------------- + // Bank Scoreboard + // --------------------------------------------------------------------------- + val scoreboard: Instance[BankScoreboard] = Instantiate(new BankScoreboard(b.memDomain.bankNum, robDepth)) - // Instruction trace DPI-C module + // --------------------------------------------------------------------------- + // Instruction trace (DPI-C, defined in ITraceDPI.scala) + // --------------------------------------------------------------------------- val itrace = Module(new ITraceDPI) itrace.io.is_issue := 0.U itrace.io.rob_id := 0.U @@ -94,166 +46,131 @@ class GlobalROB(val b: GlobalConfig) extends Module { itrace.io.rs2 := 0.U itrace.io.enable := false.B - // Circular ROB structure - val robEntries = - RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(0.U.asTypeOf(new GlobalRobEntry(b))))) - // Whether entry is valid - val robValid = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) - // Whether entry is issued - val robIssued = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) - // Whether entry is complete - val robComplete = RegInit(VecInit(Seq.fill(b.frontend.rob_entries)(false.B))) - // Points to oldest uncommitted instruction - val headPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - // Points to next position to allocate - val tailPtr = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - // ROB ID circular counter - val robIdCounter = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - // Number of issued but uncompleted instructions (used to limit issue) - val issuedCount = RegInit(0.U(log2Up(b.frontend.rob_entries + 1).W)) - // Maximum issue limit: half of ROB depth - val maxIssueLimit = (b.frontend.rob_entries / 2).U - // Queue status - val isEmpty = headPtr === tailPtr && !robValid(headPtr) - val isFull = headPtr === tailPtr && robValid(headPtr) + // --------------------------------------------------------------------------- + // Storage + // --------------------------------------------------------------------------- + val robEntries = RegInit(VecInit(Seq.fill(robDepth)(0.U.asTypeOf(new GlobalRobEntry(b))))) + val robValid = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(robDepth)(false.B))) - // Helper: circular pointer arithmetic - def wrapPtr(v: UInt): UInt = Mux(v >= b.frontend.rob_entries.U, v - b.frontend.rob_entries.U, v) + val headPtr = RegInit(0.U(idWidth.W)) + val tailPtr = RegInit(0.U(idWidth.W)) + val issuedCount = RegInit(0.U(log2Up(robDepth + 1).W)) -// ============================================================================= -// Inbound - instruction allocation -// Fence instructions are filtered out by GlobalReservationStation and never enter ROB. -// ============================================================================= + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) + + def nextPtr(p: UInt): UInt = Mux(p === (robDepth - 1).U, 0.U, p + 1.U) + def wrapPtr(v: UInt): UInt = Mux(v >= robDepth.U, v - robDepth.U, v) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- io.alloc.ready := !isFull when(io.alloc.fire) { robEntries(tailPtr).cmd := io.alloc.bits - robEntries(tailPtr).rob_id := robIdCounter + robEntries(tailPtr).rob_id := tailPtr robValid(tailPtr) := true.B robIssued(tailPtr) := false.B robComplete(tailPtr) := false.B - - // Update tail pointer and rob_id counter (circular) - tailPtr := Mux(tailPtr === (b.frontend.rob_entries - 1).U, 0.U, tailPtr + 1.U) - robIdCounter := Mux(robIdCounter === (b.frontend.rob_entries - 1).U, 0.U, robIdCounter + 1.U) + tailPtr := nextPtr(tailPtr) } -// ============================================================================= -// Completion signal processing -// ============================================================================= + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- io.complete.ready := true.B - // Default: scoreboard complete not active scoreboard.complete.valid := false.B scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) when(io.complete.fire) { - val completeId = io.complete.bits - robComplete(completeId) := true.B - // When complete, decrement issued count - when(robIssued(completeId)) { + val cid = io.complete.bits + robComplete(cid) := true.B + when(robIssued(cid)) { issuedCount := issuedCount - 1.U } - // Update scoreboard: release bank resources scoreboard.complete.valid := true.B - scoreboard.complete.bits := robEntries(completeId).cmd.bankAccess + scoreboard.complete.bits := robEntries(cid).cmd.bankAccess - // Instruction trace: complete itrace.io.is_issue := 0.U - itrace.io.rob_id := completeId - itrace.io.domain_id := robEntries(completeId).cmd.domain_id - itrace.io.funct := robEntries(completeId).cmd.cmd.funct - itrace.io.rs1 := robEntries(completeId).cmd.cmd.rs1 - itrace.io.rs2 := robEntries(completeId).cmd.cmd.rs2 + itrace.io.rob_id := cid + itrace.io.domain_id := robEntries(cid).cmd.domain_id + itrace.io.funct := robEntries(cid).cmd.cmd.funct + itrace.io.rs1 := robEntries(cid).cmd.cmd.rs1 + itrace.io.rs2 := robEntries(cid).cmd.cmd.rs2 itrace.io.enable := true.B } -// ============================================================================= -// Outbound - issue instructions with hazard detection -// -// Scan from head to find the first issuable instruction that: -// 1. is valid && !issued && !complete -// 2. has no bank hazard (checked via scoreboard) -// ============================================================================= - val canIssue = Wire(Bool()) - val issuePtr = Wire(UInt(log2Up(b.frontend.rob_entries).W)) - - // Default values - canIssue := false.B - issuePtr := headPtr - - val scanValid = Wire(Vec(b.frontend.rob_entries, Bool())) - for (i <- 0 until b.frontend.rob_entries) { + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { val ptr = wrapPtr(headPtr + i.U) scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) } - // Find first candidate - val firstValid = PriorityEncoder(scanValid.asUInt) - val hasValid = scanValid.asUInt.orR - + val hasValid = scanValid.asUInt.orR + val firstValid = PriorityEncoder(scanValid.asUInt) val actualIssuePtr = wrapPtr(headPtr + firstValid) - // Scoreboard hazard query for the selected candidate scoreboard.query := robEntries(actualIssuePtr).cmd.bankAccess val noHazard = !scoreboard.hasHazard - - // Can only issue if issue limit is not reached and no bank hazard - val canIssueMore = issuedCount < maxIssueLimit - canIssue := hasValid && canIssueMore && noHazard - issuePtr := actualIssuePtr + val canIssue = hasValid && noHazard io.issue.valid := canIssue - io.issue.bits := robEntries(issuePtr) + io.issue.bits := robEntries(actualIssuePtr) - // Default: scoreboard issue not active scoreboard.issue.valid := false.B scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) when(io.issue.fire) { - robIssued(issuePtr) := true.B - issuedCount := issuedCount + 1.U - // Update scoreboard: claim bank resources - scoreboard.issue.valid := true.B - scoreboard.issue.bits := robEntries(issuePtr).cmd.bankAccess + robIssued(actualIssuePtr) := true.B + issuedCount := issuedCount + 1.U + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).cmd.bankAccess - // Instruction trace: issue itrace.io.is_issue := 1.U - itrace.io.rob_id := robEntries(issuePtr).rob_id - itrace.io.domain_id := robEntries(issuePtr).cmd.domain_id - itrace.io.funct := robEntries(issuePtr).cmd.cmd.funct - itrace.io.rs1 := robEntries(issuePtr).cmd.cmd.rs1 - itrace.io.rs2 := robEntries(issuePtr).cmd.cmd.rs2 + itrace.io.rob_id := robEntries(actualIssuePtr).rob_id + itrace.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itrace.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itrace.io.rs1 := robEntries(actualIssuePtr).cmd.cmd.rs1 + itrace.io.rs2 := robEntries(actualIssuePtr).cmd.cmd.rs2 itrace.io.enable := true.B } -// ============================================================================= -// Instruction commit - commit all completed instructions out-of-order -// ============================================================================= - for (i <- 0 until b.frontend.rob_entries) { - when(robValid(i.U) && robComplete(i.U)) { - robValid(i.U) := false.B - robIssued(i.U) := false.B - robComplete(i.U) := false.B + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val beingAllocated = io.alloc.fire && (tailPtr === i.U) + val beingCompleted = io.complete.fire && (io.complete.bits === i.U) + when(robValid(i) && robComplete(i) && !beingAllocated && !beingCompleted) { + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B } } - // Update head pointer: skip all completed (about to be cleared) positions - val nextHeadCandidates = Wire(Vec(b.frontend.rob_entries, Bool())) - for (i <- 0 until b.frontend.rob_entries) { + // Update head pointer: advance past all committed entries + val nextHeadCandidates = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { val ptr = wrapPtr(headPtr + i.U) nextHeadCandidates(i) := robValid(ptr) && !robComplete(ptr) } val hasUncommitted = nextHeadCandidates.asUInt.orR val nextHeadOffset = PriorityEncoder(nextHeadCandidates.asUInt) - val nextHeadPtr = wrapPtr(headPtr + nextHeadOffset) - - headPtr := Mux(hasUncommitted, nextHeadPtr, tailPtr) + headPtr := Mux(hasUncommitted, wrapPtr(headPtr + nextHeadOffset), tailPtr) -// ============================================================================= -// Status signals -// ============================================================================= + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- io.empty := isEmpty io.full := isFull io.head_ptr := headPtr diff --git a/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala b/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala new file mode 100644 index 00000000..91a9abc1 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala @@ -0,0 +1,48 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ + +// DPI-C BlackBox for instruction trace (issue / complete events) +class ITraceDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val is_issue = Input(UInt(8.W)) + val rob_id = Input(UInt(32.W)) + val domain_id = Input(UInt(32.W)) + val funct = Input(UInt(32.W)) + val rs1 = Input(UInt(64.W)) + val rs2 = Input(UInt(64.W)) + val enable = Input(Bool()) + }) + + setInline( + "ITraceDPI.v", + """ + |import "DPI-C" function void dpi_itrace( + | input byte unsigned is_issue, + | input int unsigned rob_id, + | input int unsigned domain_id, + | input int unsigned funct, + | input longint unsigned rs1, + | input longint unsigned rs2 + |); + | + |module ITraceDPI( + | input [7:0] is_issue, + | input [31:0] rob_id, + | input [31:0] domain_id, + | input [31:0] funct, + | input [63:0] rs1, + | input [63:0] rs2, + | input enable + |); + | always @(*) begin + | if (enable) begin + | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2); + | end + | end + |endmodule + """.stripMargin + ) +} diff --git a/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala b/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala index 7da04924..e41d267d 100644 --- a/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala +++ b/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala @@ -43,6 +43,9 @@ object BankAccessInfo { * * bankRdCount: multi-bit counter (multiple concurrent readers allowed, RR is OK) * bankWrBusy: 1-bit flag (WAW rule guarantees at most 1 writer in-flight) + * + * Issue and complete may fire in the same cycle. Updates are computed + * combinationally so both increments and decrements take effect. */ @instantiable class BankScoreboard(val bankNum: Int, val robEntries: Int) extends Module { @@ -50,24 +53,19 @@ class BankScoreboard(val bankNum: Int, val robEntries: Int) extends Module { val bankIdLen = log2Up(bankNum) val cntWidth = log2Ceil(robEntries + 1) - // Issue: increment counters for the accessed banks @public val issue = IO(Flipped(Valid(new BankAccessInfo(bankIdLen)))) - // Complete: decrement counters for the accessed banks @public val complete = IO(Flipped(Valid(new BankAccessInfo(bankIdLen)))) - // Hazard query: check if the given access would conflict @public val query = IO(Input(new BankAccessInfo(bankIdLen))) @public val hasHazard = IO(Output(Bool())) - // Read counter: multi-bit, allows concurrent readers val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) - // Write flag: 1-bit, WAW ensures at most 1 writer in-flight per bank val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) - // --- Hazard detection --- + // --- Hazard detection (reads current register state) --- val q = query val rd0_hazard = q.rd_bank_0_valid && bankWrBusy(q.rd_bank_0_id) val rd1_hazard = q.rd_bank_1_valid && bankWrBusy(q.rd_bank_1_id) @@ -79,31 +77,29 @@ class BankScoreboard(val bankNum: Int, val robEntries: Int) extends Module { hasHazard := rd0_hazard || rd1_hazard || wr_hazard - // --- Issue: increment counters --- - when(issue.valid) { - val info = issue.bits - when(info.rd_bank_0_valid) { - bankRdCount(info.rd_bank_0_id) := bankRdCount(info.rd_bank_0_id) + 1.U - } - when(info.rd_bank_1_valid) { - bankRdCount(info.rd_bank_1_id) := bankRdCount(info.rd_bank_1_id) + 1.U - } - when(info.wr_bank_valid) { - bankWrBusy(info.wr_bank_id) := true.B - } - } + // --- Compute per-bank deltas to handle simultaneous issue + complete --- + for (bank <- 0 until bankNum) { + val bankU = bank.U(bankIdLen.W) - // --- Complete: decrement counters --- - when(complete.valid) { - val info = complete.bits - when(info.rd_bank_0_valid) { - bankRdCount(info.rd_bank_0_id) := bankRdCount(info.rd_bank_0_id) - 1.U - } - when(info.rd_bank_1_valid) { - bankRdCount(info.rd_bank_1_id) := bankRdCount(info.rd_bank_1_id) - 1.U - } - when(info.wr_bank_valid) { - bankWrBusy(info.wr_bank_id) := false.B + // Read counter: +1 per issue read, -1 per complete read + val issRd0 = issue.valid && issue.bits.rd_bank_0_valid && (issue.bits.rd_bank_0_id === bankU) + val issRd1 = issue.valid && issue.bits.rd_bank_1_valid && (issue.bits.rd_bank_1_id === bankU) + val cmpRd0 = complete.valid && complete.bits.rd_bank_0_valid && (complete.bits.rd_bank_0_id === bankU) + val cmpRd1 = complete.valid && complete.bits.rd_bank_1_valid && (complete.bits.rd_bank_1_id === bankU) + + val rdInc = issRd0.asUInt +& issRd1.asUInt + val rdDec = cmpRd0.asUInt +& cmpRd1.asUInt + bankRdCount(bank) := bankRdCount(bank) + rdInc - rdDec + + // Write flag: issue sets, complete clears. If both happen to same bank, + // complete takes priority (the completing instruction frees the bank). + val issWr = issue.valid && issue.bits.wr_bank_valid && (issue.bits.wr_bank_id === bankU) + val cmpWr = complete.valid && complete.bits.wr_bank_valid && (complete.bits.wr_bank_id === bankU) + + when(issWr && !cmpWr) { + bankWrBusy(bank) := true.B + }.elsewhen(cmpWr) { + bankWrBusy(bank) := false.B } } } diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index 7a1ce414..cd8a7310 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -1,124 +1,124 @@ -package sims.pegasus +// package sims.pegasus -import chisel3._ -import chisel3.util._ +// import chisel3._ +// import chisel3.util._ -import org.chipsalliance.cde.config.{Parameters} -import freechips.rocketchip.util.{ResetCatchAndSync} +// import org.chipsalliance.cde.config.{Parameters} +// import freechips.rocketchip.util.{ResetCatchAndSync} -import chipyard.harness.{HasHarnessInstantiators} -import chipyard.iobinders.{AXI4MemPort} +// import chipyard.harness.{HasHarnessInstantiators} +// import chipyard.iobinders.{AXI4MemPort} -import pegasus._ +// import pegasus._ -// PegasusHarness: top-level Chisel Module for AU280 FPGA. -// Integrates PegasusShell (FPGA IPs) with ChipTop (SoC DUT) via Chipyard -// harness infrastructure. -// -// PCIe and HBM2 reference clock pins are the top-level IOs. -// ChipTop is instantiated inside via instantiateChipTops(). -// HarnessBinders connect ChipTop's exposed ports (AXI4MemPort, UARTPort, etc.) -// to pegasusShell's interface signals. -// -class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { +// // PegasusHarness: top-level Chisel Module for AU280 FPGA. +// // Integrates PegasusShell (FPGA IPs) with ChipTop (SoC DUT) via Chipyard +// // harness infrastructure. +// // +// // PCIe and HBM2 reference clock pins are the top-level IOs. +// // ChipTop is instantiated inside via instantiateChipTops(). +// // HarnessBinders connect ChipTop's exposed ports (AXI4MemPort, UARTPort, etc.) +// // to pegasusShell's interface signals. +// // +// class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { - val io = IO(new Bundle { - // PCIe physical interface - val pcie_sys_clk = Input(Clock()) - val pcie_sys_clk_gt = Input(Clock()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) +// val io = IO(new Bundle { +// // PCIe physical interface +// val pcie_sys_clk = Input(Clock()) +// val pcie_sys_clk_gt = Input(Clock()) +// val pcie_sys_rst_n = Input(Bool()) +// val pcie_exp_txp = Output(UInt(16.W)) +// val pcie_exp_txn = Output(UInt(16.W)) +// val pcie_exp_rxp = Input(UInt(16.W)) +// val pcie_exp_rxn = Input(UInt(16.W)) - // HBM2 reference clock (100 MHz) - val hbm_ref_clk = Input(Clock()) - }) +// // HBM2 reference clock (100 MHz) +// val hbm_ref_clk = Input(Clock()) +// }) - // --- Instantiate PegasusShell --- - val pegasusShell = Module(new PegasusShell) - pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk - pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt - pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n - io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp - io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn - pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp - pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn - pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk +// // --- Instantiate PegasusShell --- +// val pegasusShell = Module(new PegasusShell) +// pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk +// pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt +// pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n +// io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp +// io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn +// pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp +// pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn +// pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk - // UART TX: default idle high until ChipTop provides real signal - pegasusShell.io.uart_tx := true.B +// // UART TX: default idle high until ChipTop provides real signal +// pegasusShell.io.uart_tx := true.B - // Chip mem: tie off until ChipTop provides real signals - pegasusShell.io.chip_mem_awid := 0.U - pegasusShell.io.chip_mem_awaddr := 0.U - pegasusShell.io.chip_mem_awlen := 0.U - pegasusShell.io.chip_mem_awsize := 0.U - pegasusShell.io.chip_mem_awburst := 0.U - pegasusShell.io.chip_mem_awvalid := false.B - pegasusShell.io.chip_mem_wdata := 0.U - pegasusShell.io.chip_mem_wstrb := 0.U - pegasusShell.io.chip_mem_wlast := false.B - pegasusShell.io.chip_mem_wvalid := false.B - pegasusShell.io.chip_mem_bready := false.B - pegasusShell.io.chip_mem_arid := 0.U - pegasusShell.io.chip_mem_araddr := 0.U - pegasusShell.io.chip_mem_arlen := 0.U - pegasusShell.io.chip_mem_arsize := 0.U - pegasusShell.io.chip_mem_arburst := 0.U - pegasusShell.io.chip_mem_arvalid := false.B - pegasusShell.io.chip_mem_rready := false.B +// // Chip mem: tie off until ChipTop provides real signals +// pegasusShell.io.chip_mem_awid := 0.U +// pegasusShell.io.chip_mem_awaddr := 0.U +// pegasusShell.io.chip_mem_awlen := 0.U +// pegasusShell.io.chip_mem_awsize := 0.U +// pegasusShell.io.chip_mem_awburst := 0.U +// pegasusShell.io.chip_mem_awvalid := false.B +// pegasusShell.io.chip_mem_wdata := 0.U +// pegasusShell.io.chip_mem_wstrb := 0.U +// pegasusShell.io.chip_mem_wlast := false.B +// pegasusShell.io.chip_mem_wvalid := false.B +// pegasusShell.io.chip_mem_bready := false.B +// pegasusShell.io.chip_mem_arid := 0.U +// pegasusShell.io.chip_mem_araddr := 0.U +// pegasusShell.io.chip_mem_arlen := 0.U +// pegasusShell.io.chip_mem_arsize := 0.U +// pegasusShell.io.chip_mem_arburst := 0.U +// pegasusShell.io.chip_mem_arvalid := false.B +// pegasusShell.io.chip_mem_rready := false.B - // --- HasHarnessInstantiators required interface --- - def referenceClockFreqMHz: Double = 200.0 - def referenceClock: Clock = pegasusShell.io.dut_clk - def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset +// // --- HasHarnessInstantiators required interface --- +// def referenceClockFreqMHz: Double = 200.0 +// def referenceClock: Clock = pegasusShell.io.dut_clk +// def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset - val success = WireInit(false.B) +// val success = WireInit(false.B) - // --- Instantiate ChipTop and apply HarnessBinders --- - // HarnessBinders for UART and AXI4Mem will override the defaults above - // by calling connectChipMem() and driving pegasusShell.io.uart_tx - val lazyDuts = instantiateChipTops() +// // --- Instantiate ChipTop and apply HarnessBinders --- +// // HarnessBinders for UART and AXI4Mem will override the defaults above +// // by calling connectChipMem() and driving pegasusShell.io.uart_tx +// val lazyDuts = instantiateChipTops() - // Called by WithPegasusAXIMem HarnessBinder to connect ChipTop ExtMem AXI4 - def connectChipMem(port: AXI4MemPort): Unit = { - val axi = port.io.bits - // Write address channel - pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(6.W)) - pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(33.W)) - pegasusShell.io.chip_mem_awlen := axi.aw.bits.len - pegasusShell.io.chip_mem_awsize := axi.aw.bits.size - pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst - pegasusShell.io.chip_mem_awvalid := axi.aw.valid - axi.aw.ready := pegasusShell.io.chip_mem_awready - // Write data channel - pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(256.W)) - pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(32.W)) - pegasusShell.io.chip_mem_wlast := axi.w.bits.last - pegasusShell.io.chip_mem_wvalid := axi.w.valid - axi.w.ready := pegasusShell.io.chip_mem_wready - // Write response channel - axi.b.bits.id := pegasusShell.io.chip_mem_bid.asTypeOf(axi.b.bits.id) - axi.b.bits.resp := pegasusShell.io.chip_mem_bresp - axi.b.valid := pegasusShell.io.chip_mem_bvalid - pegasusShell.io.chip_mem_bready := axi.b.ready - // Read address channel - pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(6.W)) - pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(33.W)) - pegasusShell.io.chip_mem_arlen := axi.ar.bits.len - pegasusShell.io.chip_mem_arsize := axi.ar.bits.size - pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst - pegasusShell.io.chip_mem_arvalid := axi.ar.valid - axi.ar.ready := pegasusShell.io.chip_mem_arready - // Read data channel - axi.r.bits.id := pegasusShell.io.chip_mem_rid.asTypeOf(axi.r.bits.id) - axi.r.bits.data := pegasusShell.io.chip_mem_rdata.asTypeOf(axi.r.bits.data) - axi.r.bits.resp := pegasusShell.io.chip_mem_rresp - axi.r.bits.last := pegasusShell.io.chip_mem_rlast - axi.r.valid := pegasusShell.io.chip_mem_rvalid - pegasusShell.io.chip_mem_rready := axi.r.ready - } +// // Called by WithPegasusAXIMem HarnessBinder to connect ChipTop ExtMem AXI4 +// def connectChipMem(port: AXI4MemPort): Unit = { +// val axi = port.io.bits +// // Write address channel +// pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(6.W)) +// pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(33.W)) +// pegasusShell.io.chip_mem_awlen := axi.aw.bits.len +// pegasusShell.io.chip_mem_awsize := axi.aw.bits.size +// pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst +// pegasusShell.io.chip_mem_awvalid := axi.aw.valid +// axi.aw.ready := pegasusShell.io.chip_mem_awready +// // Write data channel +// pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(256.W)) +// pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(32.W)) +// pegasusShell.io.chip_mem_wlast := axi.w.bits.last +// pegasusShell.io.chip_mem_wvalid := axi.w.valid +// axi.w.ready := pegasusShell.io.chip_mem_wready +// // Write response channel +// axi.b.bits.id := pegasusShell.io.chip_mem_bid.asTypeOf(axi.b.bits.id) +// axi.b.bits.resp := pegasusShell.io.chip_mem_bresp +// axi.b.valid := pegasusShell.io.chip_mem_bvalid +// pegasusShell.io.chip_mem_bready := axi.b.ready +// // Read address channel +// pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(6.W)) +// pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(33.W)) +// pegasusShell.io.chip_mem_arlen := axi.ar.bits.len +// pegasusShell.io.chip_mem_arsize := axi.ar.bits.size +// pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst +// pegasusShell.io.chip_mem_arvalid := axi.ar.valid +// axi.ar.ready := pegasusShell.io.chip_mem_arready +// // Read data channel +// axi.r.bits.id := pegasusShell.io.chip_mem_rid.asTypeOf(axi.r.bits.id) +// axi.r.bits.data := pegasusShell.io.chip_mem_rdata.asTypeOf(axi.r.bits.data) +// axi.r.bits.resp := pegasusShell.io.chip_mem_rresp +// axi.r.bits.last := pegasusShell.io.chip_mem_rlast +// axi.r.valid := pegasusShell.io.chip_mem_rvalid +// pegasusShell.io.chip_mem_rready := axi.r.ready +// } -} +// } diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala index aa335b13..23087123 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala @@ -1,73 +1,73 @@ -package sims.pegasus +// package sims.pegasus -import chisel3._ -import chisel3.util._ +// import chisel3._ +// import chisel3.util._ -import org.chipsalliance.cde.config.{Config} +// import org.chipsalliance.cde.config.{Config} -import chipyard.harness._ -import chipyard.iobinders._ +// import chipyard.harness._ +// import chipyard.iobinders._ -import pegasus._ +// import pegasus._ -// HarnessBinder: connect ChipTop ExtMem AXI4 port to PegasusShell chip_mem interface -// Replaces WithBlackBoxSimMem (Verilator simulation DRAM model) -class WithPegasusAXIMem - extends HarnessBinder({ - case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => { - th.connectChipMem(port) - } - }) +// // HarnessBinder: connect ChipTop ExtMem AXI4 port to PegasusShell chip_mem interface +// // Replaces WithBlackBoxSimMem (Verilator simulation DRAM model) +// class WithPegasusAXIMem +// extends HarnessBinder({ +// case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => { +// th.connectChipMem(port) +// } +// }) -// HarnessBinder: connect ChipTop UART TX to PegasusShell (goes to UARTCapture) -// Replaces WithUARTAdapter (Verilator stdout adapter) -class WithPegasusUART - extends HarnessBinder({ - case (th: PegasusHarness, port: UARTPort, chipId: Int) => { - th.pegasusShell.io.uart_tx := port.io.txd - port.io.rxd := true.B // UART RX idle high (no input from host) - } - }) +// // HarnessBinder: connect ChipTop UART TX to PegasusShell (goes to UARTCapture) +// // Replaces WithUARTAdapter (Verilator stdout adapter) +// class WithPegasusUART +// extends HarnessBinder({ +// case (th: PegasusHarness, port: UARTPort, chipId: Int) => { +// th.pegasusShell.io.uart_tx := port.io.txd +// port.io.rxd := true.B // UART RX idle high (no input from host) +// } +// }) -// Tie off JTAG (not used on FPGA; debug via GDB/OpenOCD over UART is possible but not in scope) -class WithPegasusTiedOffJTAG - extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => { - port.io.TCK := true.B.asClock - port.io.TMS := true.B - port.io.TDI := true.B - } - }) +// // Tie off JTAG (not used on FPGA; debug via GDB/OpenOCD over UART is possible but not in scope) +// class WithPegasusTiedOffJTAG +// extends HarnessBinder({ +// case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => { +// port.io.TCK := true.B.asClock +// port.io.TMS := true.B +// port.io.TDI := true.B +// } +// }) -// Tie off DMI (no simulation-side debug model needed on FPGA) -class WithPegasusTiedOffDMI - extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => { - port.io.dmi.req.valid := false.B - port.io.dmi.req.bits := DontCare - port.io.dmi.resp.ready := true.B - port.io.dmiClock := false.B.asClock - port.io.dmiReset := true.B - } - }) +// // Tie off DMI (no simulation-side debug model needed on FPGA) +// class WithPegasusTiedOffDMI +// extends HarnessBinder({ +// case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => { +// port.io.dmi.req.valid := false.B +// port.io.dmi.req.bits := DontCare +// port.io.dmi.resp.ready := true.B +// port.io.dmiClock := false.B.asClock +// port.io.dmiReset := true.B +// } +// }) -// Aggregate config fragment: select PegasusHarness binders -// and override Verilator-only simulation models -class WithPegasusHarness - extends Config( - new WithPegasusAXIMem ++ - new WithPegasusUART ++ - new WithPegasusTiedOffJTAG ++ - new WithPegasusTiedOffDMI ++ - // Standard binders that are safe to keep on FPGA - new chipyard.harness.WithTieOffInterrupts ++ - new chipyard.harness.WithTieOffL2FBusAXI ++ - new chipyard.harness.WithGPIOTiedOff ++ - new chipyard.harness.WithGPIOPinsTiedOff ++ - new chipyard.harness.WithDriveChipIdPin ++ - new chipyard.harness.WithCustomBootPinPlusArg ++ - new chipyard.harness.WithSerialTLTiedOff ++ - new chipyard.harness.WithClockFromHarness ++ - new chipyard.harness.WithResetFromHarness ++ - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator - ) +// // Aggregate config fragment: select PegasusHarness binders +// // and override Verilator-only simulation models +// class WithPegasusHarness +// extends Config( +// new WithPegasusAXIMem ++ +// new WithPegasusUART ++ +// new WithPegasusTiedOffJTAG ++ +// new WithPegasusTiedOffDMI ++ +// // Standard binders that are safe to keep on FPGA +// new chipyard.harness.WithTieOffInterrupts ++ +// new chipyard.harness.WithTieOffL2FBusAXI ++ +// new chipyard.harness.WithGPIOTiedOff ++ +// new chipyard.harness.WithGPIOPinsTiedOff ++ +// new chipyard.harness.WithDriveChipIdPin ++ +// new chipyard.harness.WithCustomBootPinPlusArg ++ +// new chipyard.harness.WithSerialTLTiedOff ++ +// new chipyard.harness.WithClockFromHarness ++ +// new chipyard.harness.WithResetFromHarness ++ +// new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator +// ) diff --git a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala index 6e3f252a..fa2a121d 100644 --- a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala +++ b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala @@ -1,46 +1,46 @@ -package sims.pegasus +// package sims.pegasus -import chisel3._ -import _root_.circt.stage.ChiselStage -import org.chipsalliance.cde.config.Config +// import chisel3._ +// import _root_.circt.stage.ChiselStage +// import org.chipsalliance.cde.config.Config -import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} -import freechips.rocketchip.subsystem.InSubsystem +// import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} +// import freechips.rocketchip.subsystem.InSubsystem -// import pegasus.{PegasusHarness, WithPegasusHarness} +// // import pegasus.{PegasusHarness, WithPegasusHarness} -// BootROM for FPGA (points to the same bootrom image as the Verilator target) -class WithPegasusBootROM - extends Config((site, here, up) => { - case BootROMLocated(InSubsystem) => Some(BootROMParams( - contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" - )) - }) +// // BootROM for FPGA (points to the same bootrom image as the Verilator target) +// class WithPegasusBootROM +// extends Config((site, here, up) => { +// case BootROMLocated(InSubsystem) => Some(BootROMParams( +// contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" +// )) +// }) -// PegasusBuckyballToyConfig: Buckyball Toy SoC on AU280 FPGA -// -// Target clock: 200 MHz. If timing closure yields a different Fmax, -// update all WithXxxBusFrequency values and re-elaborate so the DTB -// gets the correct UART baud divisor (otherwise UART output will be garbled). -class PegasusBuckyballToyConfig - extends Config( - new WithPegasusHarness ++ - new WithPegasusBootROM ++ - new chipyard.config.WithSystemBusFrequency(200.0) ++ - new chipyard.config.WithMemoryBusFrequency(200.0) ++ - new chipyard.config.WithPeripheryBusFrequency(200.0) ++ - new chipyard.config.WithControlBusFrequency(200.0) ++ - new chipyard.config.WithFrontBusFrequency(200.0) ++ - new chipyard.config.WithOffchipBusFrequency(200.0) ++ - new examples.toy.BuckyballToyConfig - ) +// // PegasusBuckyballToyConfig: Buckyball Toy SoC on AU280 FPGA +// // +// // Target clock: 200 MHz. If timing closure yields a different Fmax, +// // update all WithXxxBusFrequency values and re-elaborate so the DTB +// // gets the correct UART baud divisor (otherwise UART output will be garbled). +// class PegasusBuckyballToyConfig +// extends Config( +// new WithPegasusHarness ++ +// new WithPegasusBootROM ++ +// new chipyard.config.WithSystemBusFrequency(200.0) ++ +// new chipyard.config.WithMemoryBusFrequency(200.0) ++ +// new chipyard.config.WithPeripheryBusFrequency(200.0) ++ +// new chipyard.config.WithControlBusFrequency(200.0) ++ +// new chipyard.config.WithFrontBusFrequency(200.0) ++ +// new chipyard.config.WithOffchipBusFrequency(200.0) ++ +// new examples.toy.BuckyballToyConfig +// ) -// Elaborate entry point: generate SystemVerilog for PegasusHarness -// Usage: mill pegasus.runMain sims.pegasus.ElaboratePegasus [firtool options] -object ElaboratePegasus extends App { - ChiselStage.emitSystemVerilogFile( - new PegasusHarness()(new PegasusBuckyballToyConfig().toInstance), - firtoolOpts = args, - args = Array.empty - ) -} +// // Elaborate entry point: generate SystemVerilog for PegasusHarness +// // Usage: mill pegasus.runMain sims.pegasus.ElaboratePegasus [firtool options] +// object ElaboratePegasus extends App { +// ChiselStage.emitSystemVerilogFile( +// new PegasusHarness()(new PegasusBuckyballToyConfig().toInstance), +// firtoolOpts = args, +// args = Array.empty +// ) +// } diff --git a/pegasus/.gitignore b/pegasus/.gitignore deleted file mode 100644 index 499f6904..00000000 --- a/pegasus/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -generated/ -*jou -*.log -*_proj -.Xil diff --git a/pegasus/README.md b/pegasus/README.md deleted file mode 100644 index 85964e7b..00000000 --- a/pegasus/README.md +++ /dev/null @@ -1,2 +0,0 @@ - -适配xx版本的Vivado \ No newline at end of file diff --git a/pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala b/pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala deleted file mode 100644 index 678ece2c..00000000 --- a/pegasus/chisel/src/main/scala/pegasus/PegasusShell.scala +++ /dev/null @@ -1,462 +0,0 @@ -package pegasus - -import chisel3._ -import chisel3.util._ -import pegasus.blackbox.{XDMABlackBox, HBM2BlackBox} - -// AXI4 Crossbar black box (Vivado axi_crossbar IP) -// 2 masters (XDMA DMA + ChipTop ExtMem), 1 slave (HBM2 PC0) -// Data width: 256-bit (narrowed from XDMA's 512-bit via width converter) -// Address width: 33-bit (HBM2 address space) -class AXICrossbarBlackBox extends BlackBox { - override def desiredName = "axi_crossbar_0" - val io = IO(new Bundle { - val aclk = Input(Clock()) - val aresetn = Input(Bool()) - - // Master port 0: XDMA DMA (width-converted to 256-bit) - val s_axi_awid_0 = Input(UInt(6.W)) - val s_axi_awaddr_0 = Input(UInt(33.W)) - val s_axi_awlen_0 = Input(UInt(8.W)) - val s_axi_awsize_0 = Input(UInt(3.W)) - val s_axi_awburst_0 = Input(UInt(2.W)) - val s_axi_awvalid_0 = Input(Bool()) - val s_axi_awready_0 = Output(Bool()) - val s_axi_wdata_0 = Input(UInt(256.W)) - val s_axi_wstrb_0 = Input(UInt(32.W)) - val s_axi_wlast_0 = Input(Bool()) - val s_axi_wvalid_0 = Input(Bool()) - val s_axi_wready_0 = Output(Bool()) - val s_axi_bid_0 = Output(UInt(6.W)) - val s_axi_bresp_0 = Output(UInt(2.W)) - val s_axi_bvalid_0 = Output(Bool()) - val s_axi_bready_0 = Input(Bool()) - val s_axi_arid_0 = Input(UInt(6.W)) - val s_axi_araddr_0 = Input(UInt(33.W)) - val s_axi_arlen_0 = Input(UInt(8.W)) - val s_axi_arsize_0 = Input(UInt(3.W)) - val s_axi_arburst_0 = Input(UInt(2.W)) - val s_axi_arvalid_0 = Input(Bool()) - val s_axi_arready_0 = Output(Bool()) - val s_axi_rid_0 = Output(UInt(6.W)) - val s_axi_rdata_0 = Output(UInt(256.W)) - val s_axi_rresp_0 = Output(UInt(2.W)) - val s_axi_rlast_0 = Output(Bool()) - val s_axi_rvalid_0 = Output(Bool()) - val s_axi_rready_0 = Input(Bool()) - - // Master port 1: ChipTop ExtMem AXI4 - val s_axi_awid_1 = Input(UInt(6.W)) - val s_axi_awaddr_1 = Input(UInt(33.W)) - val s_axi_awlen_1 = Input(UInt(8.W)) - val s_axi_awsize_1 = Input(UInt(3.W)) - val s_axi_awburst_1 = Input(UInt(2.W)) - val s_axi_awvalid_1 = Input(Bool()) - val s_axi_awready_1 = Output(Bool()) - val s_axi_wdata_1 = Input(UInt(256.W)) - val s_axi_wstrb_1 = Input(UInt(32.W)) - val s_axi_wlast_1 = Input(Bool()) - val s_axi_wvalid_1 = Input(Bool()) - val s_axi_wready_1 = Output(Bool()) - val s_axi_bid_1 = Output(UInt(6.W)) - val s_axi_bresp_1 = Output(UInt(2.W)) - val s_axi_bvalid_1 = Output(Bool()) - val s_axi_bready_1 = Input(Bool()) - val s_axi_arid_1 = Input(UInt(6.W)) - val s_axi_araddr_1 = Input(UInt(33.W)) - val s_axi_arlen_1 = Input(UInt(8.W)) - val s_axi_arsize_1 = Input(UInt(3.W)) - val s_axi_arburst_1 = Input(UInt(2.W)) - val s_axi_arvalid_1 = Input(Bool()) - val s_axi_arready_1 = Output(Bool()) - val s_axi_rid_1 = Output(UInt(6.W)) - val s_axi_rdata_1 = Output(UInt(256.W)) - val s_axi_rresp_1 = Output(UInt(2.W)) - val s_axi_rlast_1 = Output(Bool()) - val s_axi_rvalid_1 = Output(Bool()) - val s_axi_rready_1 = Input(Bool()) - - // Slave port 0: HBM2 PC0 - val m_axi_awid_0 = Output(UInt(6.W)) - val m_axi_awaddr_0 = Output(UInt(33.W)) - val m_axi_awlen_0 = Output(UInt(8.W)) - val m_axi_awsize_0 = Output(UInt(3.W)) - val m_axi_awburst_0 = Output(UInt(2.W)) - val m_axi_awvalid_0 = Output(Bool()) - val m_axi_awready_0 = Input(Bool()) - val m_axi_wdata_0 = Output(UInt(256.W)) - val m_axi_wstrb_0 = Output(UInt(32.W)) - val m_axi_wlast_0 = Output(Bool()) - val m_axi_wvalid_0 = Output(Bool()) - val m_axi_wready_0 = Input(Bool()) - val m_axi_bid_0 = Input(UInt(6.W)) - val m_axi_bresp_0 = Input(UInt(2.W)) - val m_axi_bvalid_0 = Input(Bool()) - val m_axi_bready_0 = Output(Bool()) - val m_axi_arid_0 = Output(UInt(6.W)) - val m_axi_araddr_0 = Output(UInt(33.W)) - val m_axi_arlen_0 = Output(UInt(8.W)) - val m_axi_arsize_0 = Output(UInt(3.W)) - val m_axi_arburst_0 = Output(UInt(2.W)) - val m_axi_arvalid_0 = Output(Bool()) - val m_axi_arready_0 = Input(Bool()) - val m_axi_rid_0 = Input(UInt(6.W)) - val m_axi_rdata_0 = Input(UInt(256.W)) - val m_axi_rresp_0 = Input(UInt(2.W)) - val m_axi_rlast_0 = Input(Bool()) - val m_axi_rvalid_0 = Input(Bool()) - val m_axi_rready_0 = Output(Bool()) - }) -} - -// AXI Width Converter: 512-bit → 256-bit (for XDMA DMA → Crossbar) -class AXIWidthConverterBlackBox extends BlackBox { - override def desiredName = "axi_dwidth_converter_0" - val io = IO(new Bundle { - val aclk = Input(Clock()) - val aresetn = Input(Bool()) - - // Slave side: 512-bit (from XDMA DMA) - val s_axi_awid = Input(UInt(4.W)) - val s_axi_awaddr = Input(UInt(64.W)) - val s_axi_awlen = Input(UInt(8.W)) - val s_axi_awsize = Input(UInt(3.W)) - val s_axi_awburst = Input(UInt(2.W)) - val s_axi_awvalid = Input(Bool()) - val s_axi_awready = Output(Bool()) - val s_axi_wdata = Input(UInt(512.W)) - val s_axi_wstrb = Input(UInt(64.W)) - val s_axi_wlast = Input(Bool()) - val s_axi_wvalid = Input(Bool()) - val s_axi_wready = Output(Bool()) - val s_axi_bid = Output(UInt(4.W)) - val s_axi_bresp = Output(UInt(2.W)) - val s_axi_bvalid = Output(Bool()) - val s_axi_bready = Input(Bool()) - val s_axi_arid = Input(UInt(4.W)) - val s_axi_araddr = Input(UInt(64.W)) - val s_axi_arlen = Input(UInt(8.W)) - val s_axi_arsize = Input(UInt(3.W)) - val s_axi_arburst = Input(UInt(2.W)) - val s_axi_arvalid = Input(Bool()) - val s_axi_arready = Output(Bool()) - val s_axi_rid = Output(UInt(4.W)) - val s_axi_rdata = Output(UInt(512.W)) - val s_axi_rresp = Output(UInt(2.W)) - val s_axi_rlast = Output(Bool()) - val s_axi_rvalid = Output(Bool()) - val s_axi_rready = Input(Bool()) - - // Master side: 256-bit (to crossbar) - val m_axi_awid = Output(UInt(6.W)) - val m_axi_awaddr = Output(UInt(33.W)) - val m_axi_awlen = Output(UInt(8.W)) - val m_axi_awsize = Output(UInt(3.W)) - val m_axi_awburst = Output(UInt(2.W)) - val m_axi_awvalid = Output(Bool()) - val m_axi_awready = Input(Bool()) - val m_axi_wdata = Output(UInt(256.W)) - val m_axi_wstrb = Output(UInt(32.W)) - val m_axi_wlast = Output(Bool()) - val m_axi_wvalid = Output(Bool()) - val m_axi_wready = Input(Bool()) - val m_axi_bid = Input(UInt(6.W)) - val m_axi_bresp = Input(UInt(2.W)) - val m_axi_bvalid = Input(Bool()) - val m_axi_bready = Output(Bool()) - val m_axi_arid = Output(UInt(6.W)) - val m_axi_araddr = Output(UInt(33.W)) - val m_axi_arlen = Output(UInt(8.W)) - val m_axi_arsize = Output(UInt(3.W)) - val m_axi_arburst = Output(UInt(2.W)) - val m_axi_arvalid = Output(Bool()) - val m_axi_arready = Input(Bool()) - val m_axi_rid = Input(UInt(6.W)) - val m_axi_rdata = Input(UInt(256.W)) - val m_axi_rresp = Input(UInt(2.W)) - val m_axi_rlast = Input(Bool()) - val m_axi_rvalid = Input(Bool()) - val m_axi_rready = Output(Bool()) - }) -} - -// PegasusShell: top-level Verilog module for AU280 FPGA -// -// Connects: -// XDMA IP <→> SCU (AXI-Lite BAR0) -// XDMA IP <→> AXI Crossbar master 0 (DMA) -// ChipTop <→> AXI Crossbar master 1 (ExtMem) -// Crossbar <→> HBM2 PC0 (slave) -// ChipTop UART TX → UARTCapture → XDMA AXI-Stream C2H -// SCU BUFGCE → ChipTop clock -// SCU dut_reset → ChipTop reset -// -// The ChipTop is NOT instantiated here — it is connected via the PegasusHarness -// (Chipyard's LazyModule infrastructure). PegasusShell only contains the IP -// blackboxes and glue logic. The PegasusHarness wraps PegasusShell and adds ChipTop. -// -class PegasusShell extends Module { - val io = IO(new Bundle { - // PCIe physical pins (to AU280 edge connector) - val pcie_sys_clk = Input(Clock()) - val pcie_sys_clk_gt = Input(Clock()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) - - // HBM2 reference clock (100 MHz, from MMCM or board clock) - val hbm_ref_clk = Input(Clock()) - - // Exported DUT clock and reset (to PegasusHarness for ChipTop) - val dut_clk = Output(Clock()) - val dut_reset = Output(Bool()) - - // ChipTop AXI4 memory interface (from PegasusHarness, ExtMem punchthrough) - // 256-bit data, 34-bit address (for 4GB address space) - val chip_mem_awid = Input(UInt(6.W)) - val chip_mem_awaddr = Input(UInt(33.W)) - val chip_mem_awlen = Input(UInt(8.W)) - val chip_mem_awsize = Input(UInt(3.W)) - val chip_mem_awburst = Input(UInt(2.W)) - val chip_mem_awvalid = Input(Bool()) - val chip_mem_awready = Output(Bool()) - val chip_mem_wdata = Input(UInt(256.W)) - val chip_mem_wstrb = Input(UInt(32.W)) - val chip_mem_wlast = Input(Bool()) - val chip_mem_wvalid = Input(Bool()) - val chip_mem_wready = Output(Bool()) - val chip_mem_bid = Output(UInt(6.W)) - val chip_mem_bresp = Output(UInt(2.W)) - val chip_mem_bvalid = Output(Bool()) - val chip_mem_bready = Input(Bool()) - val chip_mem_arid = Input(UInt(6.W)) - val chip_mem_araddr = Input(UInt(33.W)) - val chip_mem_arlen = Input(UInt(8.W)) - val chip_mem_arsize = Input(UInt(3.W)) - val chip_mem_arburst = Input(UInt(2.W)) - val chip_mem_arvalid = Input(Bool()) - val chip_mem_arready = Output(Bool()) - val chip_mem_rid = Output(UInt(6.W)) - val chip_mem_rdata = Output(UInt(256.W)) - val chip_mem_rresp = Output(UInt(2.W)) - val chip_mem_rlast = Output(Bool()) - val chip_mem_rvalid = Output(Bool()) - val chip_mem_rready = Input(Bool()) - - // ChipTop UART TX (serial output from DUT) - val uart_tx = Input(Bool()) - }) - - // --- Instantiate XDMA --- - val xdma = Module(new XDMABlackBox) - xdma.io.sys_clk := io.pcie_sys_clk - xdma.io.sys_clk_gt := io.pcie_sys_clk_gt - xdma.io.sys_rst_n := io.pcie_sys_rst_n - io.pcie_exp_txp := xdma.io.pci_exp_txp - io.pcie_exp_txn := xdma.io.pci_exp_txn - xdma.io.pci_exp_rxp := io.pcie_exp_rxp - xdma.io.pci_exp_rxn := io.pcie_exp_rxn - - val axiClk = xdma.io.axi_aclk - val axiResetn = xdma.io.axi_aresetn - - // --- Instantiate SCU (runs on host AXI clock) --- - // The SCU module uses the implicit clock from withClockAndReset context. - // We need it to run on axiClk. - val scu = withClockAndReset(axiClk, !axiResetn) { - Module(new SCU) - } - scu.io.host_clk := axiClk - - // Connect XDMA AXI-Lite master to SCU - scu.io.axil.awvalid := xdma.io.m_axil_awvalid - xdma.io.m_axil_awready := scu.io.axil.awready - scu.io.axil.awaddr := xdma.io.m_axil_awaddr - scu.io.axil.awprot := xdma.io.m_axil_awprot - scu.io.axil.wvalid := xdma.io.m_axil_wvalid - xdma.io.m_axil_wready := scu.io.axil.wready - scu.io.axil.wdata := xdma.io.m_axil_wdata - scu.io.axil.wstrb := xdma.io.m_axil_wstrb - xdma.io.m_axil_bvalid := scu.io.axil.bvalid - scu.io.axil.bready := xdma.io.m_axil_bready - xdma.io.m_axil_bresp := scu.io.axil.bresp - scu.io.axil.arvalid := xdma.io.m_axil_arvalid - xdma.io.m_axil_arready := scu.io.axil.arready - scu.io.axil.araddr := xdma.io.m_axil_araddr - scu.io.axil.arprot := xdma.io.m_axil_arprot - xdma.io.m_axil_rvalid := scu.io.axil.rvalid - scu.io.axil.rready := xdma.io.m_axil_rready - xdma.io.m_axil_rdata := scu.io.axil.rdata - xdma.io.m_axil_rresp := scu.io.axil.rresp - - // Export DUT clock and reset - io.dut_clk := scu.io.dut_clk - io.dut_reset := scu.io.dut_reset - - // --- Instantiate UARTCapture --- - val uartCapture = withClockAndReset(axiClk, !axiResetn) { - Module(new UARTCapture()) - } - uartCapture.io.uart_tx := io.uart_tx - - // Connect UART FIFO to XDMA AXI-Stream C2H channel 0 - // XDMA C2H channel expects 512-bit wide tdata; pad the 8-bit byte - xdma.io.s_axis_c2h_tvalid_0 := uartCapture.io.axis_tvalid - uartCapture.io.axis_tready := xdma.io.s_axis_c2h_tready_0 - xdma.io.s_axis_c2h_tdata_0 := Cat(0.U(504.W), uartCapture.io.axis_tdata) - xdma.io.s_axis_c2h_tlast_0 := uartCapture.io.axis_tlast - xdma.io.s_axis_c2h_tkeep_0 := Cat(0.U(63.W), uartCapture.io.axis_tkeep) - - // --- Instantiate AXI Width Converter (XDMA 512-bit → 256-bit) --- - val widthConv = Module(new AXIWidthConverterBlackBox) - widthConv.io.aclk := axiClk - widthConv.io.aresetn := axiResetn - - // Connect XDMA DMA AXI4 master to width converter - widthConv.io.s_axi_awid := xdma.io.m_axi_awid - widthConv.io.s_axi_awaddr := xdma.io.m_axi_awaddr - widthConv.io.s_axi_awlen := xdma.io.m_axi_awlen - widthConv.io.s_axi_awsize := xdma.io.m_axi_awsize - widthConv.io.s_axi_awburst := xdma.io.m_axi_awburst - widthConv.io.s_axi_awvalid := xdma.io.m_axi_awvalid - xdma.io.m_axi_awready := widthConv.io.s_axi_awready - widthConv.io.s_axi_wdata := xdma.io.m_axi_wdata - widthConv.io.s_axi_wstrb := xdma.io.m_axi_wstrb - widthConv.io.s_axi_wlast := xdma.io.m_axi_wlast - widthConv.io.s_axi_wvalid := xdma.io.m_axi_wvalid - xdma.io.m_axi_wready := widthConv.io.s_axi_wready - xdma.io.m_axi_bid := widthConv.io.s_axi_bid - xdma.io.m_axi_bresp := widthConv.io.s_axi_bresp - xdma.io.m_axi_bvalid := widthConv.io.s_axi_bvalid - widthConv.io.s_axi_bready := xdma.io.m_axi_bready - widthConv.io.s_axi_arid := xdma.io.m_axi_arid - widthConv.io.s_axi_araddr := xdma.io.m_axi_araddr - widthConv.io.s_axi_arlen := xdma.io.m_axi_arlen - widthConv.io.s_axi_arsize := xdma.io.m_axi_arsize - widthConv.io.s_axi_arburst := xdma.io.m_axi_arburst - widthConv.io.s_axi_arvalid := xdma.io.m_axi_arvalid - xdma.io.m_axi_arready := widthConv.io.s_axi_arready - xdma.io.m_axi_rid := widthConv.io.s_axi_rid - xdma.io.m_axi_rdata := widthConv.io.s_axi_rdata - xdma.io.m_axi_rresp := widthConv.io.s_axi_rresp - xdma.io.m_axi_rlast := widthConv.io.s_axi_rlast - xdma.io.m_axi_rvalid := widthConv.io.s_axi_rvalid - widthConv.io.s_axi_rready := xdma.io.m_axi_rready - - // --- Instantiate AXI Crossbar --- - val crossbar = Module(new AXICrossbarBlackBox) - crossbar.io.aclk := axiClk - crossbar.io.aresetn := axiResetn - - // Connect width converter output to crossbar master port 0 (XDMA DMA) - crossbar.io.s_axi_awid_0 := widthConv.io.m_axi_awid - crossbar.io.s_axi_awaddr_0 := widthConv.io.m_axi_awaddr - crossbar.io.s_axi_awlen_0 := widthConv.io.m_axi_awlen - crossbar.io.s_axi_awsize_0 := widthConv.io.m_axi_awsize - crossbar.io.s_axi_awburst_0 := widthConv.io.m_axi_awburst - crossbar.io.s_axi_awvalid_0 := widthConv.io.m_axi_awvalid - widthConv.io.m_axi_awready := crossbar.io.s_axi_awready_0 - crossbar.io.s_axi_wdata_0 := widthConv.io.m_axi_wdata - crossbar.io.s_axi_wstrb_0 := widthConv.io.m_axi_wstrb - crossbar.io.s_axi_wlast_0 := widthConv.io.m_axi_wlast - crossbar.io.s_axi_wvalid_0 := widthConv.io.m_axi_wvalid - widthConv.io.m_axi_wready := crossbar.io.s_axi_wready_0 - widthConv.io.m_axi_bid := crossbar.io.s_axi_bid_0 - widthConv.io.m_axi_bresp := crossbar.io.s_axi_bresp_0 - widthConv.io.m_axi_bvalid := crossbar.io.s_axi_bvalid_0 - crossbar.io.s_axi_bready_0 := widthConv.io.m_axi_bready - crossbar.io.s_axi_arid_0 := widthConv.io.m_axi_arid - crossbar.io.s_axi_araddr_0 := widthConv.io.m_axi_araddr - crossbar.io.s_axi_arlen_0 := widthConv.io.m_axi_arlen - crossbar.io.s_axi_arsize_0 := widthConv.io.m_axi_arsize - crossbar.io.s_axi_arburst_0 := widthConv.io.m_axi_arburst - crossbar.io.s_axi_arvalid_0 := widthConv.io.m_axi_arvalid - widthConv.io.m_axi_arready := crossbar.io.s_axi_arready_0 - widthConv.io.m_axi_rid := crossbar.io.s_axi_rid_0 - widthConv.io.m_axi_rdata := crossbar.io.s_axi_rdata_0 - widthConv.io.m_axi_rresp := crossbar.io.s_axi_rresp_0 - widthConv.io.m_axi_rlast := crossbar.io.s_axi_rlast_0 - widthConv.io.m_axi_rvalid := crossbar.io.s_axi_rvalid_0 - crossbar.io.s_axi_rready_0 := widthConv.io.m_axi_rready - - // Connect ChipTop ExtMem to crossbar master port 1 - // Address offset: SoC physical addr 0x80000000 → HBM2 addr 0x0 - // The address translation is done here: chip_mem_araddr - 0x80000000 - crossbar.io.s_axi_awid_1 := io.chip_mem_awid - crossbar.io.s_axi_awaddr_1 := io.chip_mem_awaddr - 0x80000000L.U(33.W) - crossbar.io.s_axi_awlen_1 := io.chip_mem_awlen - crossbar.io.s_axi_awsize_1 := io.chip_mem_awsize - crossbar.io.s_axi_awburst_1 := io.chip_mem_awburst - crossbar.io.s_axi_awvalid_1 := io.chip_mem_awvalid - io.chip_mem_awready := crossbar.io.s_axi_awready_1 - crossbar.io.s_axi_wdata_1 := io.chip_mem_wdata - crossbar.io.s_axi_wstrb_1 := io.chip_mem_wstrb - crossbar.io.s_axi_wlast_1 := io.chip_mem_wlast - crossbar.io.s_axi_wvalid_1 := io.chip_mem_wvalid - io.chip_mem_wready := crossbar.io.s_axi_wready_1 - io.chip_mem_bid := crossbar.io.s_axi_bid_1 - io.chip_mem_bresp := crossbar.io.s_axi_bresp_1 - io.chip_mem_bvalid := crossbar.io.s_axi_bvalid_1 - crossbar.io.s_axi_bready_1 := io.chip_mem_bready - crossbar.io.s_axi_arid_1 := io.chip_mem_arid - crossbar.io.s_axi_araddr_1 := io.chip_mem_araddr - 0x80000000L.U(33.W) - crossbar.io.s_axi_arlen_1 := io.chip_mem_arlen - crossbar.io.s_axi_arsize_1 := io.chip_mem_arsize - crossbar.io.s_axi_arburst_1 := io.chip_mem_arburst - crossbar.io.s_axi_arvalid_1 := io.chip_mem_arvalid - io.chip_mem_arready := crossbar.io.s_axi_arready_1 - io.chip_mem_rid := crossbar.io.s_axi_rid_1 - io.chip_mem_rdata := crossbar.io.s_axi_rdata_1 - io.chip_mem_rresp := crossbar.io.s_axi_rresp_1 - io.chip_mem_rlast := crossbar.io.s_axi_rlast_1 - io.chip_mem_rvalid := crossbar.io.s_axi_rvalid_1 - crossbar.io.s_axi_rready_1 := io.chip_mem_rready - - // --- Instantiate HBM2 --- - val hbm2 = Module(new HBM2BlackBox) - hbm2.io.HBM_REF_CLK_0 := io.hbm_ref_clk - hbm2.io.AXI_00_ACLK := axiClk - hbm2.io.AXI_00_ARESET_N := axiResetn - - // Connect crossbar slave port 0 to HBM2 PC0 - hbm2.io.AXI_00_AWID := crossbar.io.m_axi_awid_0 - hbm2.io.AXI_00_AWADDR := crossbar.io.m_axi_awaddr_0 - hbm2.io.AXI_00_AWLEN := crossbar.io.m_axi_awlen_0(3, 0) // HBM2 only has 4-bit len - hbm2.io.AXI_00_AWSIZE := crossbar.io.m_axi_awsize_0 - hbm2.io.AXI_00_AWBURST := crossbar.io.m_axi_awburst_0 - hbm2.io.AXI_00_AWVALID := crossbar.io.m_axi_awvalid_0 - crossbar.io.m_axi_awready_0 := hbm2.io.AXI_00_AWREADY - hbm2.io.AXI_00_WDATA := crossbar.io.m_axi_wdata_0 - hbm2.io.AXI_00_WSTRB := crossbar.io.m_axi_wstrb_0 - hbm2.io.AXI_00_WLAST := crossbar.io.m_axi_wlast_0 - hbm2.io.AXI_00_WVALID := crossbar.io.m_axi_wvalid_0 - crossbar.io.m_axi_wready_0 := hbm2.io.AXI_00_WREADY - crossbar.io.m_axi_bid_0 := hbm2.io.AXI_00_BID - crossbar.io.m_axi_bresp_0 := hbm2.io.AXI_00_BRESP - crossbar.io.m_axi_bvalid_0 := hbm2.io.AXI_00_BVALID - hbm2.io.AXI_00_BREADY := crossbar.io.m_axi_bready_0 - hbm2.io.AXI_00_ARID := crossbar.io.m_axi_arid_0 - hbm2.io.AXI_00_ARADDR := crossbar.io.m_axi_araddr_0 - hbm2.io.AXI_00_ARLEN := crossbar.io.m_axi_arlen_0(3, 0) - hbm2.io.AXI_00_ARSIZE := crossbar.io.m_axi_arsize_0 - hbm2.io.AXI_00_ARBURST := crossbar.io.m_axi_arburst_0 - hbm2.io.AXI_00_ARVALID := crossbar.io.m_axi_arvalid_0 - crossbar.io.m_axi_arready_0 := hbm2.io.AXI_00_ARREADY - crossbar.io.m_axi_rid_0 := hbm2.io.AXI_00_RID - crossbar.io.m_axi_rdata_0 := hbm2.io.AXI_00_RDATA - crossbar.io.m_axi_rresp_0 := hbm2.io.AXI_00_RRESP - crossbar.io.m_axi_rlast_0 := hbm2.io.AXI_00_RLAST - crossbar.io.m_axi_rvalid_0 := hbm2.io.AXI_00_RVALID - hbm2.io.AXI_00_RREADY := crossbar.io.m_axi_rready_0 - - // HBM2 APB configuration interface: tie off (no runtime config needed) - hbm2.io.APB_0_PWDATA := 0.U - hbm2.io.APB_0_PADDR := 0.U - hbm2.io.APB_0_PCLK := axiClk - hbm2.io.APB_0_PENABLE := false.B - hbm2.io.APB_0_PRESET_N := axiResetn - hbm2.io.APB_0_PSEL := false.B - hbm2.io.APB_0_PWRITE := false.B -} diff --git a/pegasus/chisel/src/main/scala/pegasus/SCU.scala b/pegasus/chisel/src/main/scala/pegasus/SCU.scala deleted file mode 100644 index 20a26db8..00000000 --- a/pegasus/chisel/src/main/scala/pegasus/SCU.scala +++ /dev/null @@ -1,207 +0,0 @@ -package pegasus - -import chisel3._ -import chisel3.util._ - -// BUFGCE Xilinx primitive for glitch-free clock gating -// Must be instantiated as a BlackBox — never use Chisel when() to gate a clock -class BUFGCE extends BlackBox { - val io = IO(new Bundle { - val I = Input(Clock()) - val CE = Input(Bool()) - val O = Output(Clock()) - }) -} - -// AXI-Lite slave interface (from XDMA AXI-Lite master, BAR0) -// Signal direction is from the perspective of the AXI-Lite slave (SCU) -class SCUAXILiteIO extends Bundle { - // Write address channel (Input from master) - val awvalid = Input(Bool()) - val awready = Output(Bool()) - val awaddr = Input(UInt(16.W)) - val awprot = Input(UInt(3.W)) - - // Write data channel - val wvalid = Input(Bool()) - val wready = Output(Bool()) - val wdata = Input(UInt(32.W)) - val wstrb = Input(UInt(4.W)) - - // Write response channel - val bvalid = Output(Bool()) - val bready = Input(Bool()) - val bresp = Output(UInt(2.W)) - - // Read address channel - val arvalid = Input(Bool()) - val arready = Output(Bool()) - val araddr = Input(UInt(16.W)) - val arprot = Input(UInt(3.W)) - - // Read data channel - val rvalid = Output(Bool()) - val rready = Input(Bool()) - val rdata = Output(UInt(32.W)) - val rresp = Output(UInt(2.W)) -} - -// Simulation Control Unit -// -// Register map (AXI-Lite, BAR0 offsets): -// 0x0000 CTRL W [0]=freeRun, [1]=stepMode enter -// 0x0004 STEP_N W [31:0] = number of cycles to execute; writing triggers single-step -// 0x0008 STATUS R [0]=idle, [1]=stepDone -// 0x000C CYCLE_LO R [31:0] = cycle counter low -// 0x0010 CYCLE_HI R [31:0] = cycle counter high -// 0x0014 RESET W [0] = DUT reset (1=assert, 0=deassert) -// -// Clock gating: SCU uses a BUFGCE primitive to gate the host clock. -// The SCU itself runs on the host (AXI) clock. DUT gets the gated clock. -// -class SCU extends Module { - val io = IO(new Bundle { - val axil = new SCUAXILiteIO // AXI-Lite slave (from XDMA BAR0 master) - val host_clk = Input(Clock()) // Host clock input (XDMA axi_aclk, 250 MHz) - val dut_clk = Output(Clock()) // Gated DUT clock output - val dut_reset = Output(Bool()) // DUT reset signal (active high) - }) - - // --- Clock gate --- - val bufgce = Module(new BUFGCE) - bufgce.io.I := io.host_clk - - // --- Control registers (run on host clock domain, i.e. the module's implicit clock) --- - val freeRunMode = RegInit(false.B) - val stepMode = RegInit(false.B) - val stepCount = RegInit(0.U(32.W)) - val cycleCounter = RegInit(0.U(64.W)) - val stepDone = RegInit(false.B) - val dutReset = RegInit(true.B) // DUT starts in reset - - // Clock enable logic - val clkEnable = Wire(Bool()) - when(stepMode) { - clkEnable := stepCount > 0.U - when(clkEnable) { - stepCount := stepCount - 1.U - cycleCounter := cycleCounter + 1.U - } - // Mark step done when last cycle fires - when(stepCount === 1.U && clkEnable) { - stepDone := true.B - } - }.otherwise { - clkEnable := freeRunMode - when(clkEnable) { - cycleCounter := cycleCounter + 1.U - } - } - - bufgce.io.CE := clkEnable - io.dut_clk := bufgce.io.O - io.dut_reset := dutReset - - // --- AXI-Lite state machine --- - // Simple two-state machine: IDLE and handle write/read - // AW and W channels are accepted together; B response sent immediately (OKAY) - // AR channel is accepted; R response sent with register data - - val sIdle :: sWriteResp :: sReadData :: Nil = Enum(3) - val state = RegInit(sIdle) - - // Captured write address and data - val wrAddr = RegInit(0.U(16.W)) - val wrData = RegInit(0.U(32.W)) - val wrStrb = RegInit(0.U(4.W)) - - // Captured read address - val rdAddr = RegInit(0.U(16.W)) - val rdData = RegInit(0.U(32.W)) - - // Default outputs - io.axil.awready := false.B - io.axil.wready := false.B - io.axil.bvalid := false.B - io.axil.bresp := 0.U // OKAY - io.axil.arready := false.B - io.axil.rvalid := false.B - io.axil.rdata := 0.U - io.axil.rresp := 0.U // OKAY - - switch(state) { - is(sIdle) { - // Accept write if both AW and W are valid - when(io.axil.awvalid && io.axil.wvalid) { - io.axil.awready := true.B - io.axil.wready := true.B - wrAddr := io.axil.awaddr - wrData := io.axil.wdata - wrStrb := io.axil.wstrb - state := sWriteResp - }.elsewhen(io.axil.arvalid) { - // Accept read - io.axil.arready := true.B - rdAddr := io.axil.araddr - state := sReadData - } - } - is(sWriteResp) { - // Apply the write and send B response - io.axil.bvalid := true.B - when(io.axil.bready) { - state := sIdle - } - // Register writes - switch(wrAddr(7, 0)) { - is(0x00.U) { // CTRL - when(wrData(0)) { - // CTRL[0] = 1: start free running, clear step mode - freeRunMode := true.B - stepMode := false.B - }.otherwise { - // CTRL[0] = 0: halt - freeRunMode := false.B - } - when(wrData(1)) { - // CTRL[1] = 1: enter step mode (halts freeRun) - stepMode := true.B - freeRunMode := false.B - } - } - is(0x04.U) { // STEP_N: write N → single-step N cycles - stepCount := wrData - stepMode := true.B - freeRunMode := false.B - stepDone := false.B - } - is(0x14.U) { // RESET - dutReset := wrData(0) - } - } - } - is(sReadData) { - // Compute read data - val rdat = Wire(UInt(32.W)) - rdat := 0.U - switch(rdAddr(7, 0)) { - is(0x08.U) { // STATUS - rdat := Cat(0.U(30.W), stepDone, (!freeRunMode && !clkEnable)) - } - is(0x0C.U) { // CYCLE_LO - rdat := cycleCounter(31, 0) - } - is(0x10.U) { // CYCLE_HI - rdat := cycleCounter(63, 32) - } - } - rdData := rdat - - io.axil.rvalid := true.B - io.axil.rdata := rdData - when(io.axil.rready) { - state := sIdle - } - } - } -} diff --git a/pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala b/pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala deleted file mode 100644 index 36a8ef43..00000000 --- a/pegasus/chisel/src/main/scala/pegasus/UARTCapture.scala +++ /dev/null @@ -1,128 +0,0 @@ -package pegasus - -import chisel3._ -import chisel3.util._ - -// UARTCapture: receives UART TX from DUT, decodes bytes, buffers in FIFO, -// and outputs via AXI-Stream to the XDMA C2H channel. -// -// UART frame format: 1 start bit (0), 8 data bits (LSB first), 1 stop bit (1) -// Baud rate: 115200 baud by default -// Clock: host_clk (250 MHz from XDMA) -// -// The DUT's UART TX is already a standard async serial signal (the DUT's -// UART peripheral encodes the bytes into UART frames internally). -// This module acts as a UART receiver (RX) that samples the DUT's TX line. -// -// Parameters: -// clockFreqHz : host clock frequency in Hz (default 250 MHz) -// baudRate : UART baud rate (default 115200) -// fifoDepth : byte FIFO depth (default 4096) -// -class UARTCapture( - clockFreqHz: Int = 250_000_000, - baudRate: Int = 115200, - fifoDepth: Int = 4096 -) extends Module { - val io = IO(new Bundle { - val uart_tx = Input(Bool()) // DUT UART TX line (idle high) - - // AXI-Stream master output → XDMA C2H channel - val axis_tvalid = Output(Bool()) - val axis_tready = Input(Bool()) - val axis_tdata = Output(UInt(8.W)) - val axis_tlast = Output(Bool()) - val axis_tkeep = Output(UInt(1.W)) - }) - - // --- Baud rate configuration --- - // Number of clock cycles per UART bit - val cyclesPerBit = (clockFreqHz / baudRate).U - // Half period offset for sampling in middle of bit - val halfCyclesPerBit = (clockFreqHz / baudRate / 2).U - - // --- Input synchronizer (2-FF for metastability) --- - val rxd_sync0 = RegNext(io.uart_tx, true.B) - val rxd_sync1 = RegNext(rxd_sync0, true.B) - val rxd = rxd_sync1 - - // --- UART RX state machine --- - val sIdle :: sStart :: sData :: sStop :: Nil = Enum(4) - val state = RegInit(sIdle) - - val bitCounter = RegInit(0.U(4.W)) // counts 0..7 data bits - val clockCount = RegInit(0.U(32.W)) // counts cycles within a bit period - val shiftReg = RegInit(0.U(8.W)) // shift register for received byte - val byteValid = RegInit(false.B) // pulse: one byte received - val receivedByte = RegInit(0.U(8.W)) - - byteValid := false.B // default - - switch(state) { - is(sIdle) { - // Wait for start bit (falling edge: idle is 1, start bit is 0) - when(!rxd) { - state := sStart - clockCount := 0.U - } - } - is(sStart) { - // Wait half a bit period, then verify start bit is still low - clockCount := clockCount + 1.U - when(clockCount >= halfCyclesPerBit - 1.U) { - when(!rxd) { - // Valid start bit; begin receiving data bits - state := sData - clockCount := 0.U - bitCounter := 0.U - shiftReg := 0.U - }.otherwise { - // Spurious glitch, return to idle - state := sIdle - } - } - } - is(sData) { - // Sample each data bit at center of bit period - clockCount := clockCount + 1.U - when(clockCount >= cyclesPerBit - 1.U) { - clockCount := 0.U - // Sample bit (LSB first) - shiftReg := Cat(rxd, shiftReg(7, 1)) - bitCounter := bitCounter + 1.U - when(bitCounter === 7.U) { - state := sStop - } - } - } - is(sStop) { - // Wait for stop bit - clockCount := clockCount + 1.U - when(clockCount >= cyclesPerBit - 1.U) { - when(rxd) { - // Valid stop bit: byte received - byteValid := true.B - receivedByte := shiftReg - } - // Return to idle regardless (even on framing errors, resync) - state := sIdle - clockCount := 0.U - } - } - } - - // --- Byte FIFO --- - val fifo = Module(new Queue(UInt(8.W), fifoDepth)) - fifo.io.enq.valid := byteValid - fifo.io.enq.bits := receivedByte - - // AXI-Stream output from FIFO - io.axis_tvalid := fifo.io.deq.valid - io.axis_tdata := fifo.io.deq.bits - io.axis_tlast := false.B // No natural frame boundary for UART bytes - io.axis_tkeep := 1.U // 1 valid byte per beat - fifo.io.deq.ready := io.axis_tready - - // Drop silently if FIFO is full (overflow protection) - // The FIFO's enq.ready going low just means we lose bytes -} diff --git a/pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala b/pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala deleted file mode 100644 index d0688dc6..00000000 --- a/pegasus/chisel/src/main/scala/pegasus/blackbox/HBM2BlackBox.scala +++ /dev/null @@ -1,115 +0,0 @@ -package pegasus.blackbox - -import chisel3._ -import chisel3.util._ - -// AXI4 HBM2 slave port bundle (one pseudo-channel) -// Data width: 256-bit, addr width: 33-bit, id width: 6-bit -class HBM2AXI4Bundle extends Bundle { - // Write address channel - val awid = Input(UInt(6.W)) - val awaddr = Input(UInt(33.W)) - val awlen = Input(UInt(4.W)) // HBM2 supports burst length up to 16 - val awsize = Input(UInt(3.W)) - val awburst = Input(UInt(2.W)) - val awvalid = Input(Bool()) - val awready = Output(Bool()) - - // Write data channel - val wdata = Input(UInt(256.W)) - val wstrb = Input(UInt(32.W)) - val wlast = Input(Bool()) - val wvalid = Input(Bool()) - val wready = Output(Bool()) - - // Write response channel - val bid = Output(UInt(6.W)) - val bresp = Output(UInt(2.W)) - val bvalid = Output(Bool()) - val bready = Input(Bool()) - - // Read address channel - val arid = Input(UInt(6.W)) - val araddr = Input(UInt(33.W)) - val arlen = Input(UInt(4.W)) - val arsize = Input(UInt(3.W)) - val arburst = Input(UInt(2.W)) - val arvalid = Input(Bool()) - val arready = Output(Bool()) - - // Read data channel - val rid = Output(UInt(6.W)) - val rdata = Output(UInt(256.W)) - val rresp = Output(UInt(2.W)) - val rlast = Output(Bool()) - val rvalid = Output(Bool()) - val rready = Input(Bool()) -} - -// Xilinx HBM2 IP black box for AU280 (xcu280) -// AU280 has 2 HBM stacks, each with 8 pseudo-channels. -// MVP uses Stack 0, PC0 only. -// AXI interface: 256-bit data, 33-bit address, 6-bit ID, 250 MHz -class HBM2BlackBox extends BlackBox { - override def desiredName = "hbm_0" - val io = IO(new Bundle { - // Reference clocks for HBM2 (provided by MMCM) - val HBM_REF_CLK_0 = Input(Clock()) // 100 MHz reference for stack 0 - - // AXI interface clock (250 MHz, from XDMA axi_aclk) - val AXI_00_ACLK = Input(Clock()) - val AXI_00_ARESET_N = Input(Bool()) - - // AXI slave port for PC0 (Stack 0, Pseudo-channel 0) - val AXI_00_AWID = Input(UInt(6.W)) - val AXI_00_AWADDR = Input(UInt(33.W)) - val AXI_00_AWLEN = Input(UInt(4.W)) - val AXI_00_AWSIZE = Input(UInt(3.W)) - val AXI_00_AWBURST = Input(UInt(2.W)) - val AXI_00_AWVALID = Input(Bool()) - val AXI_00_AWREADY = Output(Bool()) - - val AXI_00_WDATA = Input(UInt(256.W)) - val AXI_00_WSTRB = Input(UInt(32.W)) - val AXI_00_WLAST = Input(Bool()) - val AXI_00_WVALID = Input(Bool()) - val AXI_00_WREADY = Output(Bool()) - - val AXI_00_BID = Output(UInt(6.W)) - val AXI_00_BRESP = Output(UInt(2.W)) - val AXI_00_BVALID = Output(Bool()) - val AXI_00_BREADY = Input(Bool()) - - val AXI_00_ARID = Input(UInt(6.W)) - val AXI_00_ARADDR = Input(UInt(33.W)) - val AXI_00_ARLEN = Input(UInt(4.W)) - val AXI_00_ARSIZE = Input(UInt(3.W)) - val AXI_00_ARBURST = Input(UInt(2.W)) - val AXI_00_ARVALID = Input(Bool()) - val AXI_00_ARREADY = Output(Bool()) - - val AXI_00_RID = Output(UInt(6.W)) - val AXI_00_RDATA = Output(UInt(256.W)) - val AXI_00_RRESP = Output(UInt(2.W)) - val AXI_00_RLAST = Output(Bool()) - val AXI_00_RVALID = Output(Bool()) - val AXI_00_RREADY = Input(Bool()) - - // APB (configuration) interface - val APB_0_PWDATA = Input(UInt(32.W)) - val APB_0_PADDR = Input(UInt(22.W)) - val APB_0_PCLK = Input(Clock()) - val APB_0_PENABLE = Input(Bool()) - val APB_0_PRESET_N = Input(Bool()) - val APB_0_PSEL = Input(Bool()) - val APB_0_PWRITE = Input(Bool()) - val APB_0_PRDATA = Output(UInt(32.W)) - val APB_0_PREADY = Output(Bool()) - val APB_0_PSLVERR = Output(Bool()) - - // HBM2 initialization status - val apb_complete_0 = Output(Bool()) - val DRAM_0_STAT_CATTRIP = Output(Bool()) - val DRAM_0_STAT_TEMP = Output(UInt(7.W)) - }) -} diff --git a/pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala b/pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala deleted file mode 100644 index 22adabed..00000000 --- a/pegasus/chisel/src/main/scala/pegasus/blackbox/XDMABlackBox.scala +++ /dev/null @@ -1,170 +0,0 @@ -package pegasus.blackbox - -import chisel3._ -import chisel3.util._ - -// AXI4-Lite bundle for XDMA AXI-Lite master interface -class AXILiteBundle(addrWidth: Int = 32, dataWidth: Int = 32) extends Bundle { - val awvalid = Output(Bool()) - val awready = Input(Bool()) - val awaddr = Output(UInt(addrWidth.W)) - val awprot = Output(UInt(3.W)) - - val wvalid = Output(Bool()) - val wready = Input(Bool()) - val wdata = Output(UInt(dataWidth.W)) - val wstrb = Output(UInt((dataWidth / 8).W)) - - val bvalid = Input(Bool()) - val bready = Output(Bool()) - val bresp = Input(UInt(2.W)) - - val arvalid = Output(Bool()) - val arready = Input(Bool()) - val araddr = Output(UInt(addrWidth.W)) - val arprot = Output(UInt(3.W)) - - val rvalid = Input(Bool()) - val rready = Output(Bool()) - val rdata = Input(UInt(dataWidth.W)) - val rresp = Input(UInt(2.W)) -} - -// AXI4 bundle for XDMA DMA master interface (connects to HBM2 via crossbar) -class AXI4Bundle( - addrWidth: Int = 64, - dataWidth: Int = 512, - idWidth: Int = 4 -) extends Bundle { - val awid = Output(UInt(idWidth.W)) - val awaddr = Output(UInt(addrWidth.W)) - val awlen = Output(UInt(8.W)) - val awsize = Output(UInt(3.W)) - val awburst = Output(UInt(2.W)) - val awvalid = Output(Bool()) - val awready = Input(Bool()) - - val wdata = Output(UInt(dataWidth.W)) - val wstrb = Output(UInt((dataWidth / 8).W)) - val wlast = Output(Bool()) - val wvalid = Output(Bool()) - val wready = Input(Bool()) - - val bid = Input(UInt(idWidth.W)) - val bresp = Input(UInt(2.W)) - val bvalid = Input(Bool()) - val bready = Output(Bool()) - - val arid = Output(UInt(idWidth.W)) - val araddr = Output(UInt(addrWidth.W)) - val arlen = Output(UInt(8.W)) - val arsize = Output(UInt(3.W)) - val arburst = Output(UInt(2.W)) - val arvalid = Output(Bool()) - val arready = Input(Bool()) - - val rid = Input(UInt(idWidth.W)) - val rdata = Input(UInt(dataWidth.W)) - val rresp = Input(UInt(2.W)) - val rlast = Input(Bool()) - val rvalid = Input(Bool()) - val rready = Output(Bool()) -} - -// AXI-Stream bundle (XDMA C2H channel for UART) -class AXIStreamBundle(dataWidth: Int = 8) extends Bundle { - val tvalid = Input(Bool()) - val tready = Output(Bool()) - val tdata = Input(UInt(dataWidth.W)) - val tlast = Input(Bool()) - val tkeep = Input(UInt((dataWidth / 8).W)) -} - -// Xilinx XDMA IP black box -// PCIe x16 Gen3, 512-bit AXI, 250 MHz AXI clock -// Exposes: -// - axi_aclk / axi_aresetn : AXI clock/reset outputs (driven by IP) -// - m_axil_* : AXI-Lite master (for SCU MMIO) -// - m_axi_* : AXI4 master (DMA, 512-bit, to HBM2 via crossbar) -// - s_axis_c2h_* : AXI-Stream slave (C2H, for UART upload) -// - pcie_* : PCIe PHY pins -class XDMABlackBox extends BlackBox { - override def desiredName = "xdma_0" - val io = IO(new Bundle { - // PCIe reference clock (100 MHz differential) - val sys_clk = Input(Clock()) - val sys_clk_gt = Input(Clock()) - val sys_rst_n = Input(Bool()) - - // Clocks/reset outputs (driven by XDMA IP) - val axi_aclk = Output(Clock()) - val axi_aresetn = Output(Bool()) - - // AXI-Lite master (MMIO, BAR0) - val m_axil_awvalid = Output(Bool()) - val m_axil_awready = Input(Bool()) - val m_axil_awaddr = Output(UInt(32.W)) - val m_axil_awprot = Output(UInt(3.W)) - val m_axil_wvalid = Output(Bool()) - val m_axil_wready = Input(Bool()) - val m_axil_wdata = Output(UInt(32.W)) - val m_axil_wstrb = Output(UInt(4.W)) - val m_axil_bvalid = Input(Bool()) - val m_axil_bready = Output(Bool()) - val m_axil_bresp = Input(UInt(2.W)) - val m_axil_arvalid = Output(Bool()) - val m_axil_arready = Input(Bool()) - val m_axil_araddr = Output(UInt(32.W)) - val m_axil_arprot = Output(UInt(3.W)) - val m_axil_rvalid = Input(Bool()) - val m_axil_rready = Output(Bool()) - val m_axil_rdata = Input(UInt(32.W)) - val m_axil_rresp = Input(UInt(2.W)) - - // AXI4 master (DMA, 512-bit data bus) - val m_axi_awid = Output(UInt(4.W)) - val m_axi_awaddr = Output(UInt(64.W)) - val m_axi_awlen = Output(UInt(8.W)) - val m_axi_awsize = Output(UInt(3.W)) - val m_axi_awburst = Output(UInt(2.W)) - val m_axi_awprot = Output(UInt(3.W)) - val m_axi_awvalid = Output(Bool()) - val m_axi_awready = Input(Bool()) - val m_axi_wdata = Output(UInt(512.W)) - val m_axi_wstrb = Output(UInt(64.W)) - val m_axi_wlast = Output(Bool()) - val m_axi_wvalid = Output(Bool()) - val m_axi_wready = Input(Bool()) - val m_axi_bid = Input(UInt(4.W)) - val m_axi_bresp = Input(UInt(2.W)) - val m_axi_bvalid = Input(Bool()) - val m_axi_bready = Output(Bool()) - val m_axi_arid = Output(UInt(4.W)) - val m_axi_araddr = Output(UInt(64.W)) - val m_axi_arlen = Output(UInt(8.W)) - val m_axi_arsize = Output(UInt(3.W)) - val m_axi_arburst = Output(UInt(2.W)) - val m_axi_arprot = Output(UInt(3.W)) - val m_axi_arvalid = Output(Bool()) - val m_axi_arready = Input(Bool()) - val m_axi_rid = Input(UInt(4.W)) - val m_axi_rdata = Input(UInt(512.W)) - val m_axi_rresp = Input(UInt(2.W)) - val m_axi_rlast = Input(Bool()) - val m_axi_rvalid = Input(Bool()) - val m_axi_rready = Output(Bool()) - - // AXI-Stream slave C2H channel 0 (host-bound, e.g. UART output) - val s_axis_c2h_tvalid_0 = Input(Bool()) - val s_axis_c2h_tready_0 = Output(Bool()) - val s_axis_c2h_tdata_0 = Input(UInt(512.W)) - val s_axis_c2h_tlast_0 = Input(Bool()) - val s_axis_c2h_tkeep_0 = Input(UInt(64.W)) - - // PCIe differential pairs (x16) - val pci_exp_txp = Output(UInt(16.W)) - val pci_exp_txn = Output(UInt(16.W)) - val pci_exp_rxp = Input(UInt(16.W)) - val pci_exp_rxn = Input(UInt(16.W)) - }) -} diff --git a/pegasus/driver/.gitignore b/pegasus/driver/.gitignore deleted file mode 100644 index 6654b8d8..00000000 --- a/pegasus/driver/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -build/ -compile_commands.json diff --git a/pegasus/driver/CMakeLists.txt b/pegasus/driver/CMakeLists.txt deleted file mode 100644 index ff794d95..00000000 --- a/pegasus/driver/CMakeLists.txt +++ /dev/null @@ -1,35 +0,0 @@ -cmake_minimum_required(VERSION 3.16) -project(pegasus-driver CXX) - -set(CMAKE_CXX_STANDARD 17) -set(CMAKE_CXX_STANDARD_REQUIRED ON) - -# Compiler flags -add_compile_options(-Wall -Wextra -O2) - -# Find libelf (required for ELF parsing) -find_library(LIBELF_LIB elf REQUIRED) -find_path(LIBELF_INCLUDE libelf.h - PATHS /usr/include /usr/local/include - REQUIRED) - -# ---- pegasus-run executable ---- -add_executable(pegasus-run - src/xdma.cc - src/scu.cc - src/uart.cc - src/elf.cc - src/main.cc -) - -target_include_directories(pegasus-run PRIVATE - include - ${LIBELF_INCLUDE} -) - -target_link_libraries(pegasus-run PRIVATE - ${LIBELF_LIB} -) - -# Install target (optional) -install(TARGETS pegasus-run DESTINATION bin) diff --git a/pegasus/driver/include/pegasus.h b/pegasus/driver/include/pegasus.h deleted file mode 100644 index a95fe38f..00000000 --- a/pegasus/driver/include/pegasus.h +++ /dev/null @@ -1,132 +0,0 @@ -#pragma once -#include -#include -#include -#include - -// ============================================================ -// Pegasus FPGA Simulation Framework — Public API -// ============================================================ - -// ---- SCU register offsets (BAR0 MMIO) ---- -#define SCU_CTRL_OFFSET 0x0000U // W: [0]=run, [1]=enter step mode -#define SCU_STEP_N_OFFSET 0x0004U // W: write N → execute N DUT cycles, auto-stop -#define SCU_STATUS_OFFSET 0x0008U // R: [0]=idle, [1]=step_done -#define SCU_CYCLE_LO_OFFSET 0x000CU // R: cycle counter bits [31:0] -#define SCU_CYCLE_HI_OFFSET 0x0010U // R: cycle counter bits [63:32] -#define SCU_RESET_OFFSET 0x0014U // W: [0]=assert DUT reset (1=reset, 0=run) - -// ---- HBM2 address space (as seen by XDMA DMA engine) ---- -#define HBM2_BASE 0x000000000ULL // FPGA-internal HBM2 base address -#define HBM2_SIZE 0x100000000ULL // 4 GB (single pseudo-channel) - -// ---- SoC memory map (Rocket core physical address space) ---- -#define SOC_DRAM_BASE 0x080000000ULL // SoC DRAM starts here (physical) - -// Address translation: SoC physical → HBM2 DMA address -#define SOC_TO_HBM2(paddr) ((paddr) - SOC_DRAM_BASE + HBM2_BASE) - -// ---- XDMA device file paths ---- -// UART data comes from C2H channel 1 (channel 0 used for DMA) -#define XDMA_H2C_CHAN "/dev/xdma0_h2c_0" -#define XDMA_C2H_CHAN "/dev/xdma0_c2h_0" -#define XDMA_USER_BAR "/dev/xdma0_user" -#define XDMA_UART_C2H "/dev/xdma0_c2h_1" - -// ============================================================ -// XDMA device handle -// ============================================================ -struct PegasusXDMA { - int h2c_fd; // H2C DMA file descriptor (write to FPGA) - int c2h_fd; // C2H DMA file descriptor (read from FPGA) - int uart_fd; // C2H channel 1 (UART stream) - int bar_fd; // BAR0 mmap file descriptor - void *bar0_base; // mmap'd BAR0 base pointer - uint32_t bar0_size; // BAR0 size in bytes -}; - -// ============================================================ -// ELF information extracted from ELF file -// ============================================================ -struct ELFSegment { - uint64_t paddr; // SoC physical load address - uint64_t vaddr; // Virtual address (unused) - uint64_t filesz; // Bytes to copy from file - uint64_t memsz; // Bytes in memory (filesz ≤ memsz, zero-fill rest) - uint64_t offset; // Offset in ELF file -}; - -struct ELFInfo { - std::string path; - uint64_t entry; // Entry point (SoC physical) - uint64_t tohost_paddr; // SoC physical address of tohost symbol - uint64_t fromhost_paddr; // SoC physical address of fromhost symbol - std::vector segments; // PT_LOAD segments -}; - -// ============================================================ -// XDMA device open/close -// ============================================================ - -// Open XDMA device. -// dev_prefix: e.g. "/dev/xdma0" — appended with "_h2c_0", "_c2h_0", etc. -// Returns nullptr on failure. -PegasusXDMA *xdma_open(const char *dev_prefix = "/dev/xdma0"); -void xdma_close(PegasusXDMA *xdma); - -// ============================================================ -// BAR0 MMIO (32-bit registers) -// ============================================================ -void mmio_write32(PegasusXDMA *xdma, uint64_t offset, uint32_t val); -uint32_t mmio_read32(PegasusXDMA *xdma, uint64_t offset); - -// ============================================================ -// DMA read/write (pread/pwrite on /dev/xdma0_h2c_0 and c2h_0) -// ============================================================ - -// Write buf[0..len) to FPGA HBM2 at fpga_addr. -// fpga_addr is the DMA address (e.g., 0x0 for start of HBM2). -ssize_t dma_write(PegasusXDMA *xdma, uint64_t fpga_addr, const void *buf, size_t len); - -// Read len bytes from FPGA HBM2 at fpga_addr into buf. -ssize_t dma_read(PegasusXDMA *xdma, uint64_t fpga_addr, void *buf, size_t len); - -// ============================================================ -// SCU control -// ============================================================ - -// Assert DUT reset for ~10ms, then deassert. -void scu_reset(PegasusXDMA *xdma); - -// Start free-running DUT clock (CTRL[0]=1, CTRL[1]=0). -void scu_run(PegasusXDMA *xdma); - -// Halt DUT clock (CTRL[0]=0). -void scu_halt(PegasusXDMA *xdma); - -// Execute exactly n_cycles DUT clock cycles, then stop. -// Blocks until STATUS[1] (step_done) is set. -void scu_step(PegasusXDMA *xdma, uint32_t n_cycles); - -// Read current DUT cycle counter (64-bit). -uint64_t scu_read_cycles(PegasusXDMA *xdma); - -// ============================================================ -// UART polling -// ============================================================ - -// Non-blocking read from UART FIFO (XDMA C2H channel 1). -// Writes received bytes to stdout. Call repeatedly in a loop. -void uart_poll(PegasusXDMA *xdma); - -// ============================================================ -// ELF loading -// ============================================================ - -// Parse ELF file: extract LOAD segments and tohost/fromhost symbol addresses. -// Exits on fatal error (file not found, not a valid RISC-V ELF, etc.). -ELFInfo elf_parse(const char *elf_path); - -// Load all PT_LOAD segments from the parsed ELF into HBM2 via DMA. -// Address translation: SoC physical paddr → HBM2 DMA addr via SOC_TO_HBM2(). -void elf_load(PegasusXDMA *xdma, const ELFInfo *info); diff --git a/pegasus/driver/src/elf.cc b/pegasus/driver/src/elf.cc deleted file mode 100644 index 6c623d61..00000000 --- a/pegasus/driver/src/elf.cc +++ /dev/null @@ -1,185 +0,0 @@ -#include "pegasus.h" - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -// libelf headers -#include -#include - -// Parse an ELF file and return load segment info + tohost/fromhost symbol addresses -ELFInfo elf_parse(const char *elf_path) { - ELFInfo info; - info.path = elf_path; - info.entry = 0; - info.tohost_paddr = 0; - info.fromhost_paddr = 0; - - if (elf_version(EV_CURRENT) == EV_NONE) { - fprintf(stderr, "[pegasus] libelf init failed: %s\n", elf_errmsg(-1)); - exit(1); - } - - int fd = open(elf_path, O_RDONLY); - if (fd < 0) { - fprintf(stderr, "[pegasus] Cannot open ELF: %s: %s\n", - elf_path, strerror(errno)); - exit(1); - } - - Elf *elf = elf_begin(fd, ELF_C_READ, nullptr); - if (!elf) { - fprintf(stderr, "[pegasus] elf_begin failed: %s\n", elf_errmsg(-1)); - close(fd); - exit(1); - } - - if (elf_kind(elf) != ELF_K_ELF) { - fprintf(stderr, "[pegasus] %s is not an ELF file\n", elf_path); - elf_end(elf); - close(fd); - exit(1); - } - - GElf_Ehdr ehdr; - if (!gelf_getehdr(elf, &ehdr)) { - fprintf(stderr, "[pegasus] gelf_getehdr failed: %s\n", elf_errmsg(-1)); - elf_end(elf); - close(fd); - exit(1); - } - - if (ehdr.e_machine != EM_RISCV) { - fprintf(stderr, "[pegasus] Warning: ELF machine type is not RISC-V (got %u)\n", - ehdr.e_machine); - } - - info.entry = ehdr.e_entry; - - // --- Walk program headers to find PT_LOAD segments --- - size_t phnum = 0; - elf_getphdrnum(elf, &phnum); - - for (size_t i = 0; i < phnum; i++) { - GElf_Phdr phdr; - if (!gelf_getphdr(elf, static_cast(i), &phdr)) continue; - if (phdr.p_type != PT_LOAD) continue; - if (phdr.p_filesz == 0) continue; - - ELFSegment seg; - seg.paddr = phdr.p_paddr; - seg.vaddr = phdr.p_vaddr; - seg.filesz = phdr.p_filesz; - seg.memsz = phdr.p_memsz; - seg.offset = phdr.p_offset; - info.segments.push_back(seg); - } - - // --- Walk symbol table for tohost / fromhost --- - Elf_Scn *scn = nullptr; - while ((scn = elf_nextscn(elf, scn)) != nullptr) { - GElf_Shdr shdr; - gelf_getshdr(scn, &shdr); - if (shdr.sh_type != SHT_SYMTAB && shdr.sh_type != SHT_DYNSYM) continue; - - Elf_Data *data = elf_getdata(scn, nullptr); - size_t sym_count = (data && shdr.sh_entsize) ? - data->d_size / shdr.sh_entsize : 0; - - for (size_t j = 0; j < sym_count; j++) { - GElf_Sym sym; - gelf_getsym(data, static_cast(j), &sym); - const char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); - if (!name) continue; - if (strcmp(name, "tohost") == 0) { - info.tohost_paddr = sym.st_value; - } else if (strcmp(name, "fromhost") == 0) { - info.fromhost_paddr = sym.st_value; - } - } - } - - elf_end(elf); - close(fd); - - if (info.segments.empty()) { - fprintf(stderr, "[pegasus] Warning: No PT_LOAD segments found in %s\n", elf_path); - } - if (info.tohost_paddr == 0) { - fprintf(stderr, "[pegasus] Warning: 'tohost' symbol not found in %s\n", elf_path); - } - - return info; -} - -// Load all PT_LOAD segments into FPGA HBM2 via DMA -// Address translation: SoC physical → HBM2 DMA address (subtract SOC_DRAM_BASE) -void elf_load(PegasusXDMA *xdma, const ELFInfo *info) { - // Open ELF file for raw reads - int fd = open(info->path.c_str(), O_RDONLY); - if (fd < 0) { - fprintf(stderr, "[pegasus] Cannot open ELF for loading: %s: %s\n", - info->path.c_str(), strerror(errno)); - exit(1); - } - - for (const auto &seg : info->segments) { - // Translate SoC physical address to HBM2 DMA address - if (seg.paddr < SOC_DRAM_BASE) { - fprintf(stderr, "[pegasus] Segment at 0x%" PRIx64 " is below SOC_DRAM_BASE " - "(0x%" PRIx64 ") — skipping\n", - seg.paddr, (uint64_t)SOC_DRAM_BASE); - continue; - } - uint64_t hbm2_addr = SOC_TO_HBM2(seg.paddr); - - fprintf(stderr, "[pegasus] Loading segment: SoC 0x%08" PRIx64 - " -> HBM2 0x%09" PRIx64 " (%" PRIu64 " bytes)\n", - seg.paddr, hbm2_addr, seg.filesz); - - // Read segment from ELF file - std::vector buf(seg.filesz); - ssize_t n = pread(fd, buf.data(), seg.filesz, - static_cast(seg.offset)); - if (n != static_cast(seg.filesz)) { - fprintf(stderr, "[pegasus] Short read from ELF (got %zd, expected %" PRIu64 ")\n", - n, seg.filesz); - close(fd); - exit(1); - } - - // DMA write to HBM2 - ssize_t written = dma_write(xdma, hbm2_addr, buf.data(), seg.filesz); - if (written != static_cast(seg.filesz)) { - fprintf(stderr, "[pegasus] DMA write failed at HBM2 0x%09" PRIx64 ": " - "wrote %zd of %" PRIu64 " bytes\n", - hbm2_addr, written, seg.filesz); - close(fd); - exit(1); - } - - // Zero-fill remaining memsz (BSS region) - if (seg.memsz > seg.filesz) { - size_t bss_size = seg.memsz - seg.filesz; - std::vector zeros(bss_size, 0); - uint64_t bss_addr = hbm2_addr + seg.filesz; - ssize_t w = dma_write(xdma, bss_addr, zeros.data(), bss_size); - if (w != static_cast(bss_size)) { - fprintf(stderr, "[pegasus] BSS zero-fill failed at HBM2 0x%09" PRIx64 "\n", - bss_addr); - } - } - } - - close(fd); - fprintf(stderr, "[pegasus] ELF loaded: entry=0x%" PRIx64 ", tohost=0x%" PRIx64 "\n", - info->entry, info->tohost_paddr); -} diff --git a/pegasus/driver/src/main.cc b/pegasus/driver/src/main.cc deleted file mode 100644 index 912674d1..00000000 --- a/pegasus/driver/src/main.cc +++ /dev/null @@ -1,156 +0,0 @@ -#include "pegasus.h" - -#include -#include -#include -#include -#include -#include -#include - -// ============================================================ -// Usage: -// pegasus-run Bare-metal: poll tohost, exit on done -// pegasus-run --linux Linux mode: forward UART, Ctrl+C to stop -// ============================================================ - -static volatile bool g_interrupted = false; - -static void sigint_handler(int) { - g_interrupted = true; -} - -static void print_usage(const char *argv0) { - fprintf(stderr, "Usage:\n"); - fprintf(stderr, " %s bare-metal mode (poll tohost)\n", argv0); - fprintf(stderr, " %s --linux Linux mode (UART only, Ctrl+C to exit)\n", argv0); -} - -int main(int argc, char **argv) { - if (argc < 2) { - print_usage(argv[0]); - return 1; - } - - bool linux_mode = false; - const char *elf_path = nullptr; - - if (argc >= 3 && strcmp(argv[1], "--linux") == 0) { - linux_mode = true; - elf_path = argv[2]; - } else if (argc >= 2 && argv[1][0] != '-') { - elf_path = argv[1]; - } else { - print_usage(argv[0]); - return 1; - } - - fprintf(stderr, "[pegasus] Mode: %s\n", linux_mode ? "Linux" : "bare-metal"); - fprintf(stderr, "[pegasus] ELF: %s\n", elf_path); - - // 1. Parse ELF - ELFInfo elf = elf_parse(elf_path); - - // 2. Open XDMA device - PegasusXDMA *xdma = xdma_open("/dev/xdma0"); - if (!xdma) { - fprintf(stderr, "[pegasus] Failed to open XDMA device\n"); - return 1; - } - - // 3. Reset DUT - fprintf(stderr, "[pegasus] Resetting DUT...\n"); - scu_reset(xdma); - - // 4. Load ELF into HBM2 - fprintf(stderr, "[pegasus] Loading ELF into HBM2...\n"); - elf_load(xdma, &elf); - - // 5. Start DUT (free-running) - fprintf(stderr, "[pegasus] Starting DUT...\n"); - scu_run(xdma); - - // 6. Run loop - signal(SIGINT, sigint_handler); - - if (linux_mode) { - // Linux mode: forward UART output until Ctrl+C - fprintf(stderr, "[pegasus] Linux mode running. Press Ctrl+C to stop.\n"); - while (!g_interrupted) { - uart_poll(xdma); - usleep(1000); // 1ms poll interval - } - fprintf(stderr, "\n[pegasus] Interrupted by user.\n"); - - } else { - // Bare-metal mode: poll tohost + forward UART - if (elf.tohost_paddr == 0) { - fprintf(stderr, "[pegasus] Warning: tohost not found in ELF; " - "cannot detect program exit. Running indefinitely.\n"); - while (!g_interrupted) { - uart_poll(xdma); - usleep(1000); - } - } else { - uint64_t tohost_hbm2 = SOC_TO_HBM2(elf.tohost_paddr); - uint64_t tohost_val = 0; - - while (tohost_val == 0 && !g_interrupted) { - uart_poll(xdma); - - ssize_t n = dma_read(xdma, tohost_hbm2, &tohost_val, sizeof(tohost_val)); - if (n != sizeof(tohost_val)) { - fprintf(stderr, "[pegasus] Warning: DMA read tohost returned %zd\n", n); - tohost_val = 0; - } - - // tohost format: - // bit0=1 → exit event: exit_code = tohost >> 1 - // bit0=0 → syscall request (e.g. printf → write syscall) - // respond by writing 1 to fromhost - if (tohost_val != 0 && (tohost_val & 1) == 0) { - // Syscall: acknowledge by writing 1 to fromhost - if (elf.fromhost_paddr != 0) { - uint64_t resp = 1; - uint64_t fromhost_hbm2 = SOC_TO_HBM2(elf.fromhost_paddr); - dma_write(xdma, fromhost_hbm2, &resp, sizeof(resp)); - } - tohost_val = 0; // Reset and keep polling - } - - if (tohost_val == 0) { - usleep(1000); // 1ms poll interval - } - } - - if (g_interrupted) { - fprintf(stderr, "\n[pegasus] Interrupted by user.\n"); - scu_halt(xdma); - xdma_close(xdma); - return 130; - } - - // Decode exit code - int exit_code = 0; - if ((tohost_val & 1) == 1) { - exit_code = static_cast((tohost_val >> 1) & 0x7FFFFFFF); - } - - if (exit_code == 0) { - fprintf(stderr, "[pegasus] Program exited successfully (exit code 0)\n"); - } else { - fprintf(stderr, "[pegasus] Program exited with code %d\n", exit_code); - } - - scu_halt(xdma); - uint64_t cycles = scu_read_cycles(xdma); - fprintf(stderr, "[pegasus] Total DUT cycles: %lu\n", cycles); - xdma_close(xdma); - return exit_code; - } - } - - scu_halt(xdma); - xdma_close(xdma); - return 0; -} diff --git a/pegasus/driver/src/scu.cc b/pegasus/driver/src/scu.cc deleted file mode 100644 index 9f2db268..00000000 --- a/pegasus/driver/src/scu.cc +++ /dev/null @@ -1,49 +0,0 @@ -#include "pegasus.h" - -#include -#include -#include - -// Assert DUT reset (high), hold for 10ms, then deassert (low) -void scu_reset(PegasusXDMA *xdma) { - mmio_write32(xdma, SCU_RESET_OFFSET, 1); // assert reset - usleep(10000); // hold 10ms - mmio_write32(xdma, SCU_RESET_OFFSET, 0); // deassert reset - usleep(1000); // settle 1ms -} - -// Start free-running DUT clock: CTRL[0]=1, CTRL[1]=0 -void scu_run(PegasusXDMA *xdma) { - mmio_write32(xdma, SCU_CTRL_OFFSET, 0x1); -} - -// Halt DUT clock: CTRL[0]=0 -void scu_halt(PegasusXDMA *xdma) { - mmio_write32(xdma, SCU_CTRL_OFFSET, 0x0); -} - -// Single-step: write STEP_N (enters step mode automatically), wait for step_done -void scu_step(PegasusXDMA *xdma, uint32_t n_cycles) { - if (n_cycles == 0) return; - // Write STEP_N: SCU enters step mode, starts counting - mmio_write32(xdma, SCU_STEP_N_OFFSET, n_cycles); - // Poll STATUS[1] (step_done) until set - while (true) { - uint32_t status = mmio_read32(xdma, SCU_STATUS_OFFSET); - if (status & 0x2) break; // step_done set - usleep(100); - } -} - -// Read current 64-bit DUT cycle counter -uint64_t scu_read_cycles(PegasusXDMA *xdma) { - // Read low first, then high — if high changes between reads, - // re-read until consistent (handles 32→64 bit rollover) - uint32_t lo, hi, hi2; - do { - hi = mmio_read32(xdma, SCU_CYCLE_HI_OFFSET); - lo = mmio_read32(xdma, SCU_CYCLE_LO_OFFSET); - hi2 = mmio_read32(xdma, SCU_CYCLE_HI_OFFSET); - } while (hi != hi2); - return (static_cast(hi) << 32) | lo; -} diff --git a/pegasus/driver/src/uart.cc b/pegasus/driver/src/uart.cc deleted file mode 100644 index 863c5487..00000000 --- a/pegasus/driver/src/uart.cc +++ /dev/null @@ -1,17 +0,0 @@ -#include "pegasus.h" - -#include -#include - -// Non-blocking UART poll: read bytes from XDMA C2H channel 1, write to stdout -void uart_poll(PegasusXDMA *xdma) { - if (xdma->uart_fd < 0) return; - - static char buf[4096]; - while (true) { - ssize_t n = read(xdma->uart_fd, buf, sizeof(buf)); - if (n <= 0) break; // EAGAIN or no data (non-blocking fd) - fwrite(buf, 1, static_cast(n), stdout); - fflush(stdout); - } -} diff --git a/pegasus/driver/src/xdma.cc b/pegasus/driver/src/xdma.cc deleted file mode 100644 index bd7a5ccb..00000000 --- a/pegasus/driver/src/xdma.cc +++ /dev/null @@ -1,124 +0,0 @@ -#include "pegasus.h" - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -// Open XDMA device files and mmap BAR0 -PegasusXDMA *xdma_open(const char *dev_prefix) { - auto *xdma = new PegasusXDMA(); - xdma->bar0_size = 0x1000; // 4 KB BAR0 for SCU registers - xdma->bar0_base = nullptr; - - std::string prefix(dev_prefix); - - // Open H2C (host-to-card, i.e., write to FPGA) - std::string h2c_path = prefix + "_h2c_0"; - xdma->h2c_fd = open(h2c_path.c_str(), O_WRONLY); - if (xdma->h2c_fd < 0) { - fprintf(stderr, "[pegasus] Failed to open %s: %s\n", - h2c_path.c_str(), strerror(errno)); - delete xdma; - return nullptr; - } - - // Open C2H (card-to-host, i.e., read from FPGA) - std::string c2h_path = prefix + "_c2h_0"; - xdma->c2h_fd = open(c2h_path.c_str(), O_RDONLY); - if (xdma->c2h_fd < 0) { - fprintf(stderr, "[pegasus] Failed to open %s: %s\n", - c2h_path.c_str(), strerror(errno)); - close(xdma->h2c_fd); - delete xdma; - return nullptr; - } - - // Open UART C2H stream (channel 1) - std::string uart_path = prefix + "_c2h_1"; - xdma->uart_fd = open(uart_path.c_str(), O_RDONLY | O_NONBLOCK); - if (xdma->uart_fd < 0) { - // Non-fatal: UART stream may not be configured - fprintf(stderr, "[pegasus] Warning: Failed to open UART stream %s: %s\n", - uart_path.c_str(), strerror(errno)); - xdma->uart_fd = -1; - } - - // Open and mmap BAR0 (user BAR for MMIO) - std::string bar_path = prefix + "_user"; - xdma->bar_fd = open(bar_path.c_str(), O_RDWR | O_SYNC); - if (xdma->bar_fd < 0) { - fprintf(stderr, "[pegasus] Failed to open BAR0 %s: %s\n", - bar_path.c_str(), strerror(errno)); - close(xdma->h2c_fd); - close(xdma->c2h_fd); - if (xdma->uart_fd >= 0) close(xdma->uart_fd); - delete xdma; - return nullptr; - } - - xdma->bar0_base = mmap(nullptr, xdma->bar0_size, - PROT_READ | PROT_WRITE, MAP_SHARED, - xdma->bar_fd, 0); - if (xdma->bar0_base == MAP_FAILED) { - fprintf(stderr, "[pegasus] Failed to mmap BAR0: %s\n", strerror(errno)); - close(xdma->h2c_fd); - close(xdma->c2h_fd); - if (xdma->uart_fd >= 0) close(xdma->uart_fd); - close(xdma->bar_fd); - delete xdma; - return nullptr; - } - - return xdma; -} - -void xdma_close(PegasusXDMA *xdma) { - if (!xdma) return; - if (xdma->bar0_base && xdma->bar0_base != MAP_FAILED) { - munmap(xdma->bar0_base, xdma->bar0_size); - } - if (xdma->bar_fd >= 0) close(xdma->bar_fd); - if (xdma->h2c_fd >= 0) close(xdma->h2c_fd); - if (xdma->c2h_fd >= 0) close(xdma->c2h_fd); - if (xdma->uart_fd >= 0) close(xdma->uart_fd); - delete xdma; -} - -// BAR0 MMIO (32-bit aligned reads/writes) -void mmio_write32(PegasusXDMA *xdma, uint64_t offset, uint32_t val) { - assert(xdma && xdma->bar0_base); - assert(offset + 4 <= xdma->bar0_size); - volatile uint32_t *reg = reinterpret_cast( - static_cast(xdma->bar0_base) + offset); - *reg = val; -} - -uint32_t mmio_read32(PegasusXDMA *xdma, uint64_t offset) { - assert(xdma && xdma->bar0_base); - assert(offset + 4 <= xdma->bar0_size); - volatile uint32_t *reg = reinterpret_cast( - static_cast(xdma->bar0_base) + offset); - return *reg; -} - -// DMA write: host → FPGA HBM2 via H2C channel -ssize_t dma_write(PegasusXDMA *xdma, uint64_t fpga_addr, - const void *buf, size_t len) { - assert(xdma && xdma->h2c_fd >= 0); - return pwrite(xdma->h2c_fd, buf, len, static_cast(fpga_addr)); -} - -// DMA read: FPGA HBM2 → host via C2H channel -ssize_t dma_read(PegasusXDMA *xdma, uint64_t fpga_addr, - void *buf, size_t len) { - assert(xdma && xdma->c2h_fd >= 0); - return pread(xdma->c2h_fd, buf, len, static_cast(fpga_addr)); -} diff --git a/pegasus/flake.lock b/pegasus/flake.lock deleted file mode 100644 index 38483124..00000000 --- a/pegasus/flake.lock +++ /dev/null @@ -1,61 +0,0 @@ -{ - "nodes": { - "flake-utils": { - "inputs": { - "systems": "systems" - }, - "locked": { - "lastModified": 1731533236, - "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=", - "owner": "numtide", - "repo": "flake-utils", - "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b", - "type": "github" - }, - "original": { - "owner": "numtide", - "repo": "flake-utils", - "type": "github" - } - }, - "nixpkgs": { - "locked": { - "lastModified": 1772963539, - "narHash": "sha256-9jVDGZnvCckTGdYT53d/EfznygLskyLQXYwJLKMPsZs=", - "owner": "NixOS", - "repo": "nixpkgs", - "rev": "9dcb002ca1690658be4a04645215baea8b95f31d", - "type": "github" - }, - "original": { - "owner": "NixOS", - "ref": "nixos-unstable", - "repo": "nixpkgs", - "type": "github" - } - }, - "root": { - "inputs": { - "flake-utils": "flake-utils", - "nixpkgs": "nixpkgs" - } - }, - "systems": { - "locked": { - "lastModified": 1681028828, - "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", - "owner": "nix-systems", - "repo": "default", - "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", - "type": "github" - }, - "original": { - "owner": "nix-systems", - "repo": "default", - "type": "github" - } - } - }, - "root": "root", - "version": 7 -} diff --git a/pegasus/flake.nix b/pegasus/flake.nix deleted file mode 100644 index a8ab1a46..00000000 --- a/pegasus/flake.nix +++ /dev/null @@ -1,89 +0,0 @@ -{ - description = "Pegasus FPGA simulation framework for AU280 (Buckyball project)"; - - inputs = { - nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; - flake-utils.url = "github:numtide/flake-utils"; - }; - - outputs = { self, nixpkgs, flake-utils }: - flake-utils.lib.eachDefaultSystem (system: - let - pkgs = import nixpkgs { inherit system; }; - in - { - # nix develop — C++ driver build + Vivado environment - devShells.default = pkgs.mkShell { - name = "pegasus-dev"; - packages = with pkgs; [ - cmake - gcc - gnumake - pkg-config - libelf - python3 - python3Packages.pyelftools - git - ]; - shellHook = '' - for ver in 2024.1 2023.2 2022.2; do - if [ -f /tools/Xilinx/Vivado/$ver/settings64.sh ]; then - source /tools/Xilinx/Vivado/$ver/settings64.sh - echo "Vivado $ver loaded." - break - fi - done - echo "Pegasus dev shell ready." - echo " Build driver: cmake -B driver/build driver && cmake --build driver/build" - echo " Install XDMA: nix run .#install-xdma" - ''; - }; - - # nix build .#install-xdma — produces result/bin/install-xdma - # nix run .#install-xdma — build + run directly - # - # Clones XDMA sources and compiles against the *running* kernel at - # execution time, so the .ko matches whatever kernel the server has. - packages.install-xdma = pkgs.writeShellApplication { - name = "install-xdma"; - runtimeInputs = with pkgs; [ git gnumake gcc kmod ]; - text = '' - KERNEL=$(uname -r) - KBUILD=/lib/modules/$KERNEL/build - - if [ ! -d "$KBUILD" ]; then - echo "ERROR: Kernel headers not found at $KBUILD" - echo " Run: sudo apt install linux-headers-$KERNEL" - exit 1 - fi - - TMPDIR=$(mktemp -d) - trap "rm -rf $TMPDIR" EXIT - - echo "==> Cloning XDMA driver source..." - git clone https://github.com/joonho3020/dma_ip_drivers "$TMPDIR/src" - git -C "$TMPDIR/src" checkout ubuntu-24-xdma - - echo "==> Building against kernel $KERNEL..." - make -C "$TMPDIR/src/XDMA/linux-kernel/xdma" KERNELDIR="$KBUILD" - - echo "==> Installing (requires sudo)..." - sudo make -C "$TMPDIR/src/XDMA/linux-kernel/xdma" KERNELDIR="$KBUILD" install - sudo modprobe xdma - - echo "==> Verifying..." - if ls /dev/xdma* 2>/dev/null; then - echo "XDMA installed successfully!" - else - echo "Module loaded. No /dev/xdma* yet — connect AU280 and re-run: sudo modprobe xdma" - fi - ''; - }; - - apps.install-xdma = { - type = "app"; - program = "${pkgs.lib.getExe self.packages.${system}.install-xdma}"; - }; - } - ); -} diff --git a/pegasus/vivado/au280.xdc b/pegasus/vivado/au280.xdc deleted file mode 100644 index 7c9224d5..00000000 --- a/pegasus/vivado/au280.xdc +++ /dev/null @@ -1,79 +0,0 @@ -# Xilinx AU280 (xcu280-fsvh2892-2L-e) Pin and Timing Constraints -# For Pegasus FPGA simulation framework - -################################################################################ -# PCIe Interface (x16, connected to AU280 PCIe edge connector) -################################################################################ - -# PCIe reference clock (100 MHz differential, from PCIe slot) -set_property PACKAGE_PIN BF41 [get_ports pcie_sys_clk_p] -set_property PACKAGE_PIN BG41 [get_ports pcie_sys_clk_n] -create_clock -period 10.000 -name pcie_refclk [get_ports pcie_sys_clk_p] - -# PCIe reset (active low, from PCIe slot) -set_property PACKAGE_PIN BJ44 [get_ports pcie_sys_rst_n] -set_property IOSTANDARD LVCMOS12 [get_ports pcie_sys_rst_n] -set_property PULLUP true [get_ports pcie_sys_rst_n] -set_false_path -from [get_ports pcie_sys_rst_n] - -# PCIe TX/RX differential pairs (x16) -# Note: actual pin assignments depend on AU280 board schematic / Vivado auto-assign -# These are placeholders; real assignments come from xdma IP's XDC output -# set_property PACKAGE_PIN [get_ports {pcie_exp_txp[0]}] -# ... (x16 lanes, auto-assigned by XDMA IP) - -################################################################################ -# HBM2 Reference Clock (from MMCM or direct board clock) -################################################################################ - -# HBM2 cattrip override (required for AU280 to prevent thermal shutdown) -# Must be driven by MMCM output at 100 MHz -# set_property PACKAGE_PIN [get_ports hbm_cattrip] - -################################################################################ -# Main AXI Clock (250 MHz from XDMA IP axi_aclk output) -################################################################################ - -# The axi_aclk is generated inside XDMA IP — create a generated clock constraint -create_generated_clock -name axi_aclk \ - -source [get_pins xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O] \ - -multiply_by 1 \ - [get_pins xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O] - -################################################################################ -# DUT Clock (gated by SCU BUFGCE, derived from axi_aclk) -################################################################################ - -# The DUT clock is axi_aclk gated by BUFGCE. -# Vivado will automatically detect the BUFGCE hierarchy and propagate the clock. -# Add a multicycle path constraint since BUFGCE introduces enable-based gating. -set_multicycle_path -setup 1 \ - -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */bufgce/O}]] \ - -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */bufgce/O}]] - -################################################################################ -# False paths (async reset signals) -################################################################################ - -set_false_path -from [get_ports pcie_sys_rst_n] - -################################################################################ -# I/O Timing (set_input_delay / set_output_delay not needed for PCIe — XDMA IP handles it) -################################################################################ - -################################################################################ -# Placement hints -################################################################################ - -# Place XDMA IP near PCIe lanes (right side of AU280) -# Place HBM2 controller near HBM2 stacks (left side of AU280) -# These are Pblock suggestions; actual placement by Vivado - -################################################################################ -# Bitstream settings -################################################################################ - -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property CFGBVS GND [current_design] diff --git a/pegasus/vivado/build.tcl b/pegasus/vivado/build.tcl deleted file mode 100644 index b373401b..00000000 --- a/pegasus/vivado/build.tcl +++ /dev/null @@ -1,169 +0,0 @@ -# Pegasus Vivado Build Script -# Synthesizes and implements the Pegasus FPGA design for AU280 -# -# Usage: -# vivado -mode batch -source build.tcl -# -# Prerequisites: -# 1. Run ElaboratePegasus to generate Verilog: -# cd arch && sbt "runMain sims.pegasus.ElaboratePegasus" -# Then copy generated/*.sv to ./generated/ -# 2. Vivado 2021.1+ must be installed and in PATH - -set PART xcu280-fsvh2892-2L-e -set TOP PegasusHarness -set PROJ_NAME pegasus_proj -set PROJ_DIR ./${PROJ_NAME} -set GEN_DIR ./generated -set IP_DIR ./ip -set XDC_FILE ./au280.xdc - -################################################################################ -# Step 1: Create project -################################################################################ - -create_project ${PROJ_NAME} ${PROJ_DIR} -part ${PART} -force - -# Set project properties -set_property target_language Verilog [current_project] -set_property simulator_language Mixed [current_project] - -################################################################################ -# Step 2: Create IPs -################################################################################ - -puts "==> Creating IP cores..." -source ${IP_DIR}/xdma_ip.tcl -source ${IP_DIR}/hbm2_ip.tcl -source ${IP_DIR}/axi_crossbar_ip.tcl - -# Synthesize IPs out-of-context so their netlists are available to synth_design -puts "==> Synthesizing IP cores (OOC)..." -set top_ips [list xdma_0 hbm_0 axi_crossbar_0 axi_dwidth_converter_0] -foreach ip_name $top_ips { - set ip [get_ips $ip_name -quiet] - if {$ip ne ""} { - puts " synth_ip: ${ip_name}" - synth_ip $ip - } -} - -# After synth_ip, exclude unisim/secureip library files from top-level synthesis -foreach f [get_files -filter {FILE_TYPE == "Verilog" && NAME =~ "*/unisim*"}] { - set_property USED_IN_SYNTHESIS false $f -} -foreach f [get_files -filter {FILE_TYPE == "Verilog" && NAME =~ "*/secureip*"}] { - set_property USED_IN_SYNTHESIS false $f -} -# Also exclude unisim_comp.v which is in scripts/rt/data/ -foreach f [get_files -filter {NAME =~ "*/scripts/rt/data/*"}] { - set_property USED_IN_SYNTHESIS false $f -} - -################################################################################ -# Step 3: Add generated Verilog sources -# Exclude simulation-only files: DPI-C wrappers, clock generators, IO cell models -################################################################################ - -# Patterns for simulation-only files to exclude from synthesis -set sim_only_patterns { - BackdoorGet* BackdoorPut* - *DPI.v *DPI.sv - ClockSource* EICG_wrapper* - GenericDigital*IOCell* -} - -proc is_sim_only {fname patterns} { - set base [file tail $fname] - foreach pat $patterns { - if {[string match $pat $base]} { return 1 } - } - return 0 -} - -puts "==> Adding Verilog sources (excluding simulation-only files)..." - -set sv_files [glob -nocomplain ${GEN_DIR}/*.sv] -set v_files [glob -nocomplain ${GEN_DIR}/*.v] - -set synth_files {} -foreach f [concat $sv_files $v_files] { - if {![is_sim_only $f $sim_only_patterns]} { - lappend synth_files $f - } else { - puts " skipping sim-only: [file tail $f]" - } -} - -if {[llength $synth_files] > 0} { - add_files $synth_files -} - -set_property top ${TOP} [current_fileset] - -################################################################################ -# Step 4: Add constraints -################################################################################ - -puts "==> Adding constraints..." -add_files -fileset constrs_1 ${XDC_FILE} - -################################################################################ -# Step 5: Synthesis -################################################################################ - -# Multi-threading + runtime-optimized strategy (256-core server) -set_param general.maxThreads 32 - -puts "==> Running synthesis..." -synth_design -top ${TOP} -part ${PART} \ - -flatten_hierarchy rebuilt \ - -gated_clock_conversion auto \ - -fsm_extraction one_hot \ - -directive RuntimeOptimized - -write_checkpoint -force ${PROJ_DIR}/post_synth.dcp -report_utilization -file ${PROJ_DIR}/utilization_synth.rpt - -################################################################################ -# Step 6: Implementation -################################################################################ - -puts "==> Optimizing design..." -opt_design -directive RuntimeOptimized - -puts "==> Placing design..." -place_design -directive RuntimeOptimized - -puts "==> Routing design..." -route_design -directive RuntimeOptimized - -# Post-implementation reports -write_checkpoint -force ${PROJ_DIR}/post_route.dcp -report_timing_summary -file ${PROJ_DIR}/timing_summary.rpt -warn_on_violation -report_utilization -file ${PROJ_DIR}/utilization_impl.rpt -report_power -file ${PROJ_DIR}/power.rpt - -# Check timing -if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { - puts "WARNING: Setup timing violations detected. Check timing_summary.rpt" - puts "WARNING: You may need to reduce PegasusConfig frequency and re-elaborate." -} else { - puts "INFO: Timing closure achieved." -} - -################################################################################ -# Step 7: Generate bitstream -################################################################################ - -puts "==> Generating bitstream..." -write_bitstream -force ${PROJ_DIR}/pegasus.bit - -puts "==> Build complete: ${PROJ_DIR}/pegasus.bit" -puts "" -puts "Next steps:" -puts " 1. Check timing_summary.rpt for actual Fmax" -puts " 2. If Fmax differs from 200 MHz, update PegasusConfig frequencies and re-elaborate" -puts " 3. Program FPGA: source scripts/program_fpga.sh" -puts " 4. Install XDMA driver: nix run .#install-xdma" -puts " 5. Run workload: pegasus-run ./workload.elf" diff --git a/pegasus/vivado/ip/axi_crossbar_ip.tcl b/pegasus/vivado/ip/axi_crossbar_ip.tcl deleted file mode 100644 index 3e845969..00000000 --- a/pegasus/vivado/ip/axi_crossbar_ip.tcl +++ /dev/null @@ -1,37 +0,0 @@ -# AXI Crossbar IP configuration -# 2 master ports (XDMA DMA + ChipTop ExtMem), 1 slave port (HBM2 PC0) -# Data width: 256-bit, address width: 33-bit, ID width: 6-bit, 250 MHz - -create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 \ - -module_name axi_crossbar_0 - -set_property -dict [list \ - CONFIG.NUM_SI {2} \ - CONFIG.NUM_MI {1} \ - CONFIG.STRATEGY {1} \ - CONFIG.DATA_WIDTH {256} \ - CONFIG.ADDR_WIDTH {33} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \ - CONFIG.M00_A00_ADDR_WIDTH {33} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.WUSER_WIDTH {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ -] [get_ips axi_crossbar_0] - -generate_target all [get_ips axi_crossbar_0] - -# AXI Data Width Converter: 512-bit (XDMA) → 256-bit (HBM2/Crossbar) -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 \ - -module_name axi_dwidth_converter_0 - -set_property -dict [list \ - CONFIG.ADDR_WIDTH {33} \ - CONFIG.MI_DATA_WIDTH {256} \ - CONFIG.SI_DATA_WIDTH {512} \ - CONFIG.SI_ID_WIDTH {4} \ -] [get_ips axi_dwidth_converter_0] - -generate_target all [get_ips axi_dwidth_converter_0] diff --git a/pegasus/vivado/ip/hbm2_ip.tcl b/pegasus/vivado/ip/hbm2_ip.tcl deleted file mode 100644 index 892a90e0..00000000 --- a/pegasus/vivado/ip/hbm2_ip.tcl +++ /dev/null @@ -1,31 +0,0 @@ -# HBM2 IP configuration for AU280 (xcu280) -# Uses Stack 0, Pseudo-channel 0 only (MVP) -# AXI4 interface: 256-bit data, 33-bit address, 250 MHz -# Compatible with Vivado 2021.1 (HBM IP v1.0) - -create_ip -name hbm -vendor xilinx.com -library ip -version 1.0 \ - -module_name hbm_0 - -set_property -dict [list \ - CONFIG.USER_HBM_STACK {1} \ - CONFIG.USER_HBM_DENSITY {8GB} \ - CONFIG.USER_SINGLE_STACK_SELECTION {LEFT} \ - CONFIG.USER_SWITCH_ENABLE_00 {TRUE} \ - CONFIG.USER_SWITCH_ENABLE_01 {FALSE} \ - CONFIG.USER_MC_ENABLE_00 {TRUE} \ - CONFIG.USER_MC_ENABLE_01 {FALSE} \ - CONFIG.USER_MC_ENABLE_02 {FALSE} \ - CONFIG.USER_MC_ENABLE_03 {FALSE} \ - CONFIG.USER_MC_ENABLE_04 {FALSE} \ - CONFIG.USER_MC_ENABLE_05 {FALSE} \ - CONFIG.USER_MC_ENABLE_06 {FALSE} \ - CONFIG.USER_MC_ENABLE_07 {FALSE} \ - CONFIG.USER_AXI_CLK_FREQ {250} \ - CONFIG.USER_CLK_SEL_00 {FALSE} \ - CONFIG.USER_SAXI_00 {true} \ - CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {TRUE} \ - CONFIG.USER_MC0_LOOKAHEAD_PCH {TRUE} \ - CONFIG.USER_MC0_MAINTAIN_COHERENCY {TRUE} \ -] [get_ips hbm_0] - -generate_target all [get_ips hbm_0] diff --git a/pegasus/vivado/ip/xdma_ip.tcl b/pegasus/vivado/ip/xdma_ip.tcl deleted file mode 100644 index 86d630a0..00000000 --- a/pegasus/vivado/ip/xdma_ip.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# XDMA PCIe IP configuration for AU280 -# PCIe x16 Gen3, AXI4 data width 512-bit, 250 MHz AXI clock -# AXI-Lite master (BAR0) + AXI4 DMA master + AXI-Stream C2H channel -# Compatible with Vivado 2021.1 (XDMA IP v4.1) - -create_ip -name xdma -vendor xilinx.com -library ip -version 4.1 \ - -module_name xdma_0 - -set_property -dict [list \ - CONFIG.pl_link_cap_max_link_width {X16} \ - CONFIG.pl_link_cap_max_link_speed {8.0_GT/s} \ - CONFIG.axi_data_width {512_bit} \ - CONFIG.axisten_freq {250} \ - CONFIG.axilite_master_en {true} \ - CONFIG.axilite_master_size {32} \ - CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ - CONFIG.xdma_rnum_chnl {1} \ - CONFIG.xdma_wnum_chnl {1} \ - CONFIG.pf0_msix_cap_table_bir {BAR_1} \ - CONFIG.pf0_msix_cap_pba_bir {BAR_1} \ - CONFIG.dsc_bypass_rd {0000} \ - CONFIG.dsc_bypass_wr {0000} \ -] [get_ips xdma_0] - -generate_target all [get_ips xdma_0] diff --git a/pegasus/vivado/synth_only.tcl b/pegasus/vivado/synth_only.tcl deleted file mode 100644 index cdb8d58c..00000000 --- a/pegasus/vivado/synth_only.tcl +++ /dev/null @@ -1,58 +0,0 @@ -# Pegasus Synthesis-Only Script -# Assumes IP cores already created (pegasus_proj exists with IPs synthesized) -# -# Usage (from vivado/ directory): -# vivado -mode batch -source synth_only.tcl - -set PART xcu280-fsvh2892-2L-e -set TOP PegasusHarness -set PROJ_NAME pegasus_proj -set PROJ_DIR ./${PROJ_NAME} -set GEN_DIR ./generated - -# Open existing project -open_project ${PROJ_DIR}/${PROJ_NAME}.xpr - -# Replace user RTL sources (keep IP files intact) -set old_rtl [get_files -quiet -filter {NAME =~ "*/generated/*"}] -if {[llength $old_rtl] > 0} { - remove_files $old_rtl -} - -# Patterns for simulation-only files -proc is_sim_only {fname} { - set base [file tail $fname] - foreach pat {BackdoorGet* BackdoorPut* *DPI.v *DPI.sv ClockSource* EICG_wrapper* GenericDigital*IOCell*} { - if {[string match $pat $base]} { return 1 } - } - return 0 -} - -set synth_files {} -foreach f [concat [glob -nocomplain ${GEN_DIR}/*.sv] [glob -nocomplain ${GEN_DIR}/*.v]] { - if {![is_sim_only $f]} { - lappend synth_files $f - } else { - puts " skipping sim-only: [file tail $f]" - } -} -if {[llength $synth_files] > 0} { add_files $synth_files } -set_property top ${TOP} [current_fileset] - -# Lock IP OOC runs so synth_design uses their DCPs directly -foreach run [get_runs -filter {IS_SYNTHESIS == 1 && NAME != "synth_1"}] { - set_property IS_ENABLED false $run -} - -set_param general.maxThreads 32 - -puts "==> Running synthesis..." -synth_design -top ${TOP} -part ${PART} \ - -flatten_hierarchy rebuilt \ - -gated_clock_conversion auto \ - -fsm_extraction one_hot \ - -directive RuntimeOptimized - -write_checkpoint -force ${PROJ_DIR}/post_synth.dcp -report_utilization -file ${PROJ_DIR}/utilization_synth.rpt -puts "==> Synthesis complete: ${PROJ_DIR}/post_synth.dcp" From e6ddb6ab25ba12148afebd43779e75c782334d94 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 14 Mar 2026 14:34:48 +0800 Subject: [PATCH 175/238] [arch] feat: integrate SubROB into GlobalRS --- .../examples/toy/balldomain/BallDomain.scala | 26 ++- .../framework/balldomain/bbus/bbus.scala | 10 +- .../balldomain/blink/SubRobRow.scala | 49 +++++ .../framework/balldomain/blink/blink.scala | 1 + .../prototype/dequant/Dequant.scala | 16 +- .../prototype/dequant/DequantBall.scala | 5 +- .../prototype/gemmini/GemminiBall.scala | 5 +- .../prototype/gemmini/GemminiExCtrl.scala | 28 +-- .../balldomain/prototype/im2col/Im2col.scala | 22 ++- .../prototype/im2col/Im2colBall.scala | 5 +- .../balldomain/prototype/quant/Quant.scala | 16 +- .../prototype/quant/QuantBall.scala | 5 +- .../balldomain/prototype/relu/Relu.scala | 16 +- .../balldomain/prototype/relu/ReluBall.scala | 4 +- .../systolicarray/SystolicArrayBall.scala | 5 +- .../systolicarray/SystolicArrayCtrl.scala | 56 +++--- .../balldomain/prototype/trace/Trace.scala | 16 +- .../prototype/trace/TraceBall.scala | 5 +- .../prototype/transpose/Transpose.scala | 18 +- .../prototype/transpose/TransposeBall.scala | 4 +- .../balldomain/prototype/vector/VecBall.scala | 4 +- .../prototype/vector/VecCtrlUnit.scala | 62 +++--- .../balldomain/rs/reservationStation.scala | 44 +++-- .../core/bbtile/BuckyballAccelerator.scala | 5 + .../scala/framework/frontend/Frontend.scala | 9 + .../frontend/configs/FrontendParam.scala | 3 +- .../framework/frontend/configs/default.json | 3 +- .../frontend/globalrs/GlobalROB.scala | 4 +- .../globalrs/GlobalReservationStation.scala | 132 ++++++++++--- .../framework/frontend/globalrs/SubROB.scala | 177 ++++++++++++++++++ .../scala/framework/gpdomain/GPDomain.scala | 6 +- .../memdomain/frontend/MemFrontend.scala | 16 +- .../cmd_channel/rs/reservationStation.scala | 60 +++--- .../outside_channel/MemConfiger.scala | 52 ++--- .../frontend/outside_channel/MemLoader.scala | 26 ++- .../frontend/outside_channel/MemStorer.scala | 18 +- 36 files changed, 710 insertions(+), 223 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala create mode 100644 arch/src/main/scala/framework/frontend/globalrs/SubROB.scala diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index aeeb961a..f8085f32 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.tile._ import framework.top.GlobalConfig import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} -import framework.balldomain.blink.{BankRead, BankWrite} +import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} import framework.balldomain.rs.BallReservationStation import framework.top.channels.{ChannelClusterIO, ChannelIO} @@ -30,6 +30,9 @@ class BallDomain(val b: GlobalConfig) extends Module { @public val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + @public + val subRobReq = IO(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) + val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) val ballRs: Instance[BallReservationStation] = Instantiate(new BallReservationStation(b)) @@ -48,10 +51,12 @@ class BallDomain(val b: GlobalConfig) extends Module { //--------------------------------------------------------------------------- // Connect decoded instruction and global rob_id - ballRs.ball_decode_cmd_i.valid := ballDecoder.ball_decode_cmd_o.valid - ballRs.ball_decode_cmd_i.bits.cmd := ballDecoder.ball_decode_cmd_o.bits - ballRs.ball_decode_cmd_i.bits.rob_id := global_issue_i.bits.rob_id - ballDecoder.ball_decode_cmd_o.ready := ballRs.ball_decode_cmd_i.ready + ballRs.ball_decode_cmd_i.valid := ballDecoder.ball_decode_cmd_o.valid + ballRs.ball_decode_cmd_i.bits.cmd := ballDecoder.ball_decode_cmd_o.bits + ballRs.ball_decode_cmd_i.bits.rob_id := global_issue_i.bits.rob_id + ballRs.ball_decode_cmd_i.bits.is_sub := global_issue_i.bits.is_sub + ballRs.ball_decode_cmd_i.bits.sub_rob_id := global_issue_i.bits.sub_rob_id + ballDecoder.ball_decode_cmd_o.ready := ballRs.ball_decode_cmd_i.ready //--------------------------------------------------------------------------- // Local BallRS -> BBus (multi-channel) @@ -65,9 +70,18 @@ class BallDomain(val b: GlobalConfig) extends Module { bbus.bankRead <> bankRead bbus.bankWrite <> bankWrite + // BBus -> SubROB + for (i <- 0 until b.ballDomain.ballNum) { + subRobReq(i) <> bbus.subRobReq(i) + } + //--------------------------------------------------------------------------- // Local RS completion signal -> Global RS (single channel, includes global rob_id) //--------------------------------------------------------------------------- - global_complete_o <> ballRs.complete_o + global_complete_o.valid := ballRs.complete_o.valid + global_complete_o.bits.rob_id := ballRs.complete_o.bits.rob_id + global_complete_o.bits.is_sub := ballRs.complete_o.bits.is_sub + global_complete_o.bits.sub_rob_id := ballRs.complete_o.bits.sub_rob_id + ballRs.complete_o.ready := global_complete_o.ready } diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 6945f548..81294445 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -8,7 +8,7 @@ import framework.balldomain.rs.{BallRsComplete, BallRsIssue} import framework.balldomain.blink.HasBlink import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter -import framework.balldomain.blink.{BankRead, BankWrite} +import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} import framework.top.channels.{Channel, ChannelClusterIO, ChannelIO} /** @@ -30,6 +30,9 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) + // balls - bbus - SubROB + @public + val subRobReq = IO(Vec(numBalls, Decoupled(new SubRobRow(b)))) val balls = ballGenerators.map(gen => Module(gen())) val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) @@ -87,4 +90,9 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) } } + // Connect balls' subRobReq + for (i <- 0 until numBalls) { + subRobReq(i) <> balls(i).blink.subRobReq + } + } diff --git a/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala b/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala new file mode 100644 index 00000000..4edccdea --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala @@ -0,0 +1,49 @@ +package framework.balldomain.blink + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig +import framework.frontend.decoder.PostGDCmd +import framework.frontend.scoreboard.BankAccessInfo + +class SubRobSlot(val b: GlobalConfig) extends Bundle { + val valid = Bool() + val cmd = new PostGDCmd(b) +} + +class SubRobRow(val b: GlobalConfig) extends Bundle { + val slots = Vec(4, new SubRobSlot(b)) + val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) + val master_rob_id = UInt(log2Up(b.frontend.rob_entries).W) +} + +/** Tie-off for subRobReq when a Ball does not use SubROB. */ +object SubRobRow { + + def tieOff(b: GlobalConfig): SubRobRow = { + val w = Wire(new SubRobRow(b)) + w.ball_id := 0.U + w.master_rob_id := 0.U + val bankIdLen = log2Up(b.memDomain.bankNum) + for (i <- 0 until 4) { + w.slots(i).valid := false.B + w.slots(i).cmd.domain_id := 0.U + w.slots(i).cmd.cmd.raw_inst := 0.U + w.slots(i).cmd.cmd.funct := 0.U + w.slots(i).cmd.cmd.rs2 := 0.U + w.slots(i).cmd.cmd.rs1 := 0.U + w.slots(i).cmd.cmd.xd := false.B + w.slots(i).cmd.cmd.xs1 := false.B + w.slots(i).cmd.cmd.xs2 := false.B + w.slots(i).cmd.cmd.rd := 0.U + w.slots(i).cmd.cmd.opcode := 0.U + w.slots(i).cmd.cmd.rs1Data := 0.U + w.slots(i).cmd.cmd.rs2Data := 0.U + w.slots(i).cmd.bankAccess := BankAccessInfo.none(bankIdLen) + w.slots(i).cmd.isFence := false.B + w.slots(i).cmd.isBarrier := false.B + } + w + } + +} diff --git a/arch/src/main/scala/framework/balldomain/blink/blink.scala b/arch/src/main/scala/framework/balldomain/blink/blink.scala index 3f63fcb8..2f068ff5 100644 --- a/arch/src/main/scala/framework/balldomain/blink/blink.scala +++ b/arch/src/main/scala/framework/balldomain/blink/blink.scala @@ -13,4 +13,5 @@ class BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int) extends Bundle with HasBal val cmdResp = Decoupled(new BallRsComplete(b)) val bankRead = Vec(inBW, Flipped(new BankRead(b))) val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) + val subRobReq = Decoupled(new SubRobRow(b)) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala b/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala index 91f8219a..b231ebd2 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/Dequant.scala @@ -37,9 +37,13 @@ class Dequant(val b: GlobalConfig) extends Module { val status = new BallStatus }) - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id } for (i <- 0 until inBW) { @@ -86,9 +90,11 @@ class Dequant(val b: GlobalConfig) extends Module { io.bankWrite(i).group_id := 0.U } - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg // INT32 to FP32 def int32ToFp32(intVal: UInt): UInt = { diff --git a/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala b/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala index 857a65a6..efd2d167 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/dequant/DequantBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.dequant import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.top.GlobalConfig @instantiable @@ -33,4 +33,7 @@ class DequantBall(val b: GlobalConfig) extends Module with HasBlink { } io.status <> dequantUnit.io.status + + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala index 6c3ece31..8db589a9 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.gemmini import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.top.GlobalConfig @instantiable @@ -54,4 +54,7 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall } io.status <> exCtrl.io.status + + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala index a2c93bd8..be1ade87 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala @@ -98,7 +98,9 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { Enum(11) val state = RegInit(sIdle) - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) // Saved rs1/rs2 from the command (latched at sIdle when cmdReq fires) val saved_rs1 = Reg(UInt(64.W)) @@ -142,8 +144,10 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // ========================================================================= io.cmdReq.ready := state === sIdle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg for (i <- 0 until inBW) { io.bankReadReq(i).valid := false.B @@ -182,14 +186,16 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { is(sIdle) { io.cmdReq.ready := true.B when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id - op1_bank := io.cmdReq.bits.cmd.op1_bank - op2_bank := io.cmdReq.bits.cmd.op2_bank - wr_bank := io.cmdReq.bits.cmd.wr_bank - saved_rs1 := io.cmdReq.bits.cmd.rs1 - saved_rs2 := io.cmdReq.bits.cmd.rs2 - saved_sub_cmd := sub_cmd - total_rows := Mux(io.cmdReq.bits.cmd.iter === 0.U, DIM.U, io.cmdReq.bits.cmd.iter) + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op2_bank := io.cmdReq.bits.cmd.op2_bank + wr_bank := io.cmdReq.bits.cmd.wr_bank + saved_rs1 := io.cmdReq.bits.cmd.rs1 + saved_rs2 := io.cmdReq.bits.cmd.rs2 + saved_sub_cmd := sub_cmd + total_rows := Mux(io.cmdReq.bits.cmd.iter === 0.U, DIM.U, io.cmdReq.bits.cmd.iter) when(sub_cmd === GemminiSubCmd.CONFIG) { // CONFIG: decode from special field (rs2 with sub_cmd in [3:0]) diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala index 593d7792..97e67d7d 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2col.scala @@ -48,6 +48,8 @@ class Im2col(val b: GlobalConfig) extends Module { // --- Registers --- private val robIdReg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + private val isSubReg = RegInit(false.B) + private val subRobIdReg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) private val rBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) private val wBankReg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) private val rBaseBeatReg = RegInit(0.U(32.W)) @@ -75,11 +77,13 @@ class Im2col(val b: GlobalConfig) extends Module { private val isLastWindow = rowEnd && colEnd // --- Top-level IO defaults --- - io.cmdReq.ready := (state === idle) - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := robIdReg - io.status.idle := (state === idle) - io.status.running := (state =/= idle) && (state =/= complete) + io.cmdReq.ready := (state === idle) + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := robIdReg + io.cmdResp.bits.is_sub := isSubReg + io.cmdResp.bits.sub_rob_id := subRobIdReg + io.status.idle := (state === idle) + io.status.running := (state =/= idle) && (state =/= complete) // --- Wire up LineBufferManager --- for (i <- 0 until inBW) { @@ -116,9 +120,11 @@ class Im2col(val b: GlobalConfig) extends Module { switch(state) { is(idle) { when(io.cmdReq.fire) { - robIdReg := io.cmdReq.bits.rob_id - rBankReg := io.cmdReq.bits.cmd.op1_bank - wBankReg := io.cmdReq.bits.cmd.wr_bank + robIdReg := io.cmdReq.bits.rob_id + isSubReg := io.cmdReq.bits.is_sub + subRobIdReg := io.cmdReq.bits.sub_rob_id + rBankReg := io.cmdReq.bits.cmd.op1_bank + wBankReg := io.cmdReq.bits.cmd.wr_bank kColReg := io.cmdReq.bits.cmd.special(3, 0) kRowReg := io.cmdReq.bits.cmd.special(7, 4) diff --git a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala index dce1c8ae..0a47fd06 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/im2col/Im2colBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.im2col import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.balldomain.prototype.im2col.Im2col import framework.top.GlobalConfig @@ -40,4 +40,7 @@ class Im2colBall(val b: GlobalConfig) extends Module with HasBlink { // Connect Status signals - directly obtained from internal unit io.status <> im2colUnit.io.status + // Ball does not use SubROB: tie off subRobReq + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala b/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala index fc6239d8..d3627d5b 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/Quant.scala @@ -47,9 +47,13 @@ class Quant(val b: GlobalConfig) extends Module { val status = new BallStatus }) - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id } for (i <- 0 until inBW) { @@ -113,9 +117,11 @@ class Quant(val b: GlobalConfig) extends Module { io.bankWrite(i).group_id := 0.U } - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg // ---- FP32 multiply ---- def fp32Multiply(a: UInt, bv: UInt): UInt = { diff --git a/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala b/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala index 99a21c48..37c412b1 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/quant/QuantBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.quant import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.top.GlobalConfig @instantiable @@ -33,4 +33,7 @@ class QuantBall(val b: GlobalConfig) extends Module with HasBlink { } io.status <> quantUnit.io.status + + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala index 0abc7e2f..fd889310 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/Relu.scala @@ -33,9 +33,13 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { val status = new BallStatus }) - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id } for (i <- 0 until inBW) { @@ -94,9 +98,11 @@ class PipelinedRelu(val b: GlobalConfig) extends Module { io.bankWrite(i).group_id := 0.U } - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg switch(state) { is(idle) { diff --git a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala index d74f9108..d1322e9a 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.relu import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.balldomain.prototype.relu.PipelinedRelu import framework.top.GlobalConfig @@ -40,4 +40,6 @@ class ReluBall(val b: GlobalConfig) extends Module with HasBlink { io.status <> reluUnit.io.status + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala index e2e1830f..85fba75b 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.systolicarray import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.top.GlobalConfig @instantiable @@ -34,4 +34,7 @@ class SystolicArrayBall(val b: GlobalConfig) extends Module with HasBlink with H } io.status <> systolicArrayUnit.io.status + + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala index 97d84024..da7ba33f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/systolicarray/SystolicArrayCtrl.scala @@ -22,15 +22,17 @@ class SystolicArrayCtrl(val b: GlobalConfig) extends Module { val cmdResp_i = Flipped(Valid(new Bundle { val commit = Bool() })) }) - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - val iter = RegInit(0.U(b.frontend.iter_len.W)) - val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val op1_bank_addr = RegInit(0.U(12.W)) - val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val op2_bank_addr = RegInit(0.U(12.W)) - val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank_addr = RegInit(0.U(12.W)) - val has_send = RegInit(false.B) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_bank_addr = RegInit(0.U(12.W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank_addr = RegInit(0.U(12.W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(12.W)) + val has_send = RegInit(false.B) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) @@ -38,15 +40,17 @@ class SystolicArrayCtrl(val b: GlobalConfig) extends Module { io.cmdReq.ready := state === idle when(io.cmdReq.fire) { - iter := io.cmdReq.bits.cmd.iter - rob_id_reg := io.cmdReq.bits.rob_id - op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := 0.U - op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := 0.U - wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := 0.U - state := busy + iter := io.cmdReq.bits.cmd.iter + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op1_bank_addr := 0.U + op2_bank := io.cmdReq.bits.cmd.op2_bank + op2_bank_addr := 0.U + wr_bank := io.cmdReq.bits.cmd.wr_bank + wr_bank_addr := 0.U + state := busy } when(state === busy && !has_send) { @@ -84,12 +88,16 @@ class SystolicArrayCtrl(val b: GlobalConfig) extends Module { } when(io.cmdResp_i.valid) { - io.cmdResp_o.valid := true.B - io.cmdResp_o.bits.rob_id := rob_id_reg - state := idle - has_send := false.B + io.cmdResp_o.valid := true.B + io.cmdResp_o.bits.rob_id := rob_id_reg + io.cmdResp_o.bits.is_sub := is_sub_reg + io.cmdResp_o.bits.sub_rob_id := sub_rob_id_reg + state := idle + has_send := false.B }.otherwise { - io.cmdResp_o.valid := false.B - io.cmdResp_o.bits.rob_id := 0.U + io.cmdResp_o.valid := false.B + io.cmdResp_o.bits.rob_id := 0.U + io.cmdResp_o.bits.is_sub := false.B + io.cmdResp_o.bits.sub_rob_id := 0.U } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala index a87ea846..6ee8fa89 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala @@ -63,7 +63,9 @@ class Trace(val b: GlobalConfig) extends Module { // ============================================================ // Registers // ============================================================ - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) // Command decode registers val isRead_reg = RegInit(false.B) // BB_RD0 flag @@ -170,9 +172,11 @@ class Trace(val b: GlobalConfig) extends Module { // ============================================================ // Command interface // ============================================================ - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdReq.ready := state === idle + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg // ============================================================ // State machine @@ -180,7 +184,9 @@ class Trace(val b: GlobalConfig) extends Module { switch(state) { is(idle) { when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id val cmd = io.cmdReq.bits.cmd val rs2 = cmd.rs2 diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala index 9c9d6cad..fe41b2be 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.trace import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.top.GlobalConfig /** @@ -42,4 +42,7 @@ class TraceBall(val b: GlobalConfig) extends Module with HasBlink { } io.status <> traceUnit.io.status + + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala index 404d10d6..8ec247a0 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/Transpose.scala @@ -37,8 +37,14 @@ class Transpose(val b: GlobalConfig) extends Module { // ------------------------------- // ROB / IDs // ------------------------------- - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - when(io.cmdReq.fire)(rob_id_reg := io.cmdReq.bits.rob_id) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + } for (i <- 0 until inBW) { io.bankRead(i).rob_id := rob_id_reg @@ -99,9 +105,11 @@ class Transpose(val b: GlobalConfig) extends Module { io.bankWrite(i).group_id := 0.U } - io.cmdReq.ready := (state === idle) - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdReq.ready := (state === idle) + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg io.bankRead(0).io.resp.ready := (state =/= idle) io.bankWrite(0).io.resp.ready := (state =/= idle) diff --git a/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala b/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala index 6ce8623f..2d8a8b32 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/transpose/TransposeBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.transpose import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.balldomain.prototype.transpose.Transpose import framework.top.GlobalConfig @@ -35,4 +35,6 @@ class TransposeBall(val b: GlobalConfig) extends Module with HasBlink { io.status <> transposeUnit.io.status + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala index 0b9e0bd6..f9d6b820 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecBall.scala @@ -3,7 +3,7 @@ package framework.balldomain.prototype.vector import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} import framework.balldomain.prototype.vector.VecUnit import framework.top.GlobalConfig @@ -39,4 +39,6 @@ class VecBall(val b: GlobalConfig) extends Module with HasBlink with HasBallStat io.status <> vecUnit.io.status + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala index 0467beaf..44af26da 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/vector/VecCtrlUnit.scala @@ -22,17 +22,19 @@ class VecCtrlUnit(val b: GlobalConfig) extends Module { val cmdResp_i = Flipped(Valid(new Bundle { val commit = Bool() })) // from store unit }) - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - val iter = RegInit(0.U(b.frontend.iter_len.W)) - val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility - val is_acc = RegInit(false.B) // Deprecated: use wmode instead - val has_send = RegInit(false.B) - val mode = RegInit(0.U(1.W)) + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val iter = RegInit(0.U(b.frontend.iter_len.W)) + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op1_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val op2_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank_addr = RegInit(0.U(12.W)) // New ISA: always 0, but keep for compatibility + val is_acc = RegInit(false.B) // Deprecated: use wmode instead + val has_send = RegInit(false.B) + val mode = RegInit(0.U(1.W)) val idle :: busy :: Nil = Enum(2) val state = RegInit(idle) @@ -42,16 +44,18 @@ class VecCtrlUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- when(io.cmdReq.fire) { - iter := io.cmdReq.bits.cmd.iter - rob_id_reg := io.cmdReq.bits.rob_id - op1_bank := io.cmdReq.bits.cmd.op1_bank - op1_bank_addr := 0.U // New ISA: all operations start from row 0 - op2_bank := io.cmdReq.bits.cmd.op2_bank - op2_bank_addr := 0.U // New ISA: all operations start from row 0 - wr_bank := io.cmdReq.bits.cmd.wr_bank - wr_bank_addr := 0.U // New ISA: all operations start from row 0 - is_acc := false.B // Deprecated: use wmode instead - mode := io.cmdReq.bits.cmd.special(0) + iter := io.cmdReq.bits.cmd.iter + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op1_bank_addr := 0.U // New ISA: all operations start from row 0 + op2_bank := io.cmdReq.bits.cmd.op2_bank + op2_bank_addr := 0.U // New ISA: all operations start from row 0 + wr_bank := io.cmdReq.bits.cmd.wr_bank + wr_bank_addr := 0.U // New ISA: all operations start from row 0 + is_acc := false.B // Deprecated: use wmode instead + mode := io.cmdReq.bits.cmd.special(0) state := busy } @@ -101,13 +105,17 @@ class VecCtrlUnit(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- when(io.cmdResp_i.valid) { - io.cmdResp_o.valid := true.B - io.cmdResp_o.bits.rob_id := rob_id_reg - state := idle - has_send := false.B + io.cmdResp_o.valid := true.B + io.cmdResp_o.bits.rob_id := rob_id_reg + io.cmdResp_o.bits.is_sub := is_sub_reg + io.cmdResp_o.bits.sub_rob_id := sub_rob_id_reg + state := idle + has_send := false.B }.otherwise { - io.cmdResp_o.valid := false.B - io.cmdResp_o.bits.rob_id := 0.U + io.cmdResp_o.valid := false.B + io.cmdResp_o.bits.rob_id := 0.U + io.cmdResp_o.bits.is_sub := false.B + io.cmdResp_o.bits.sub_rob_id := 0.U } io.cmdReq.ready := state === idle diff --git a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala index 0058ea8b..35cb7f67 100644 --- a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala @@ -8,14 +8,18 @@ import examples.toy.balldomain.BallDecodeCmd // Ball domain issue interface - includes global rob_id class BallRsIssue(b: GlobalConfig) extends Bundle { - val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) + val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) // Global ROB ID - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) } // Ball domain completion interface class BallRsComplete(b: GlobalConfig) extends Bundle { - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) } // Generic Ball domain issue interface - supports dynamic number of Ball devices @@ -34,9 +38,11 @@ class BallReservationStation(val b: GlobalConfig) extends Module { @public val ball_decode_cmd_i = IO(Flipped(new DecoupledIO(new Bundle { - val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) + val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) // Global ROB ID - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) }))) // Rs -> BallController (multi-channel issue) @@ -53,8 +59,10 @@ class BallReservationStation(val b: GlobalConfig) extends Module { // Simple FIFO queue, only for buffering val fifo = Module(new Queue( new Bundle { - val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val cmd = new BallDecodeCmd(b.memDomain.bankNum, b.frontend.iter_len) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) }, entries = 4 )) // Small buffer is sufficient @@ -79,14 +87,18 @@ class BallReservationStation(val b: GlobalConfig) extends Module { for (i <- 0 until b.ballDomain.ballNum) { if (i < numConfiguredBalls) { val configuredBallId = b.ballDomain.ballIdMappings(i).ballId.U - issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === configuredBallId - issue_o.balls(i).bits.cmd := headEntry.cmd - issue_o.balls(i).bits.rob_id := headEntry.rob_id + issue_o.balls(i).valid := fifo.io.deq.valid && headEntry.cmd.bid === configuredBallId + issue_o.balls(i).bits.cmd := headEntry.cmd + issue_o.balls(i).bits.rob_id := headEntry.rob_id + issue_o.balls(i).bits.is_sub := headEntry.is_sub + issue_o.balls(i).bits.sub_rob_id := headEntry.sub_rob_id } else { // Unused slots - no valid signal - issue_o.balls(i).valid := false.B - issue_o.balls(i).bits.cmd := DontCare - issue_o.balls(i).bits.rob_id := DontCare + issue_o.balls(i).valid := false.B + issue_o.balls(i).bits.cmd := DontCare + issue_o.balls(i).bits.rob_id := DontCare + issue_o.balls(i).bits.is_sub := DontCare + issue_o.balls(i).bits.sub_rob_id := DontCare } } @@ -106,17 +118,17 @@ class BallReservationStation(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), b.ballDomain.ballNum)) + val completeArb = Module(new Arbiter(new BallRsComplete(b), b.ballDomain.ballNum)) // Connect completion signals from all Ball devices to arbiter for (i <- 0 until b.ballDomain.ballNum) { completeArb.io.in(i).valid := commit_i.balls(i).valid - completeArb.io.in(i).bits := commit_i.balls(i).bits.rob_id + completeArb.io.in(i).bits := commit_i.balls(i).bits commit_i.balls(i).ready := completeArb.io.in(i).ready } // Forward completion signal (with global rob_id) complete_o.valid := completeArb.io.out.valid - complete_o.bits.rob_id := completeArb.io.out.bits + complete_o.bits := completeArb.io.out.bits completeArb.io.out.ready := complete_o.ready } diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index 71dcfed2..e489cb83 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -75,6 +75,11 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module ballDomain.global_issue_i <> frontend.io.ball_issue_o frontend.io.ball_complete_i <> ballDomain.global_complete_o + // --- BallDomain -> Frontend (SubROB requests) --- + for (i <- 0 until b.ballDomain.ballNum) { + frontend.io.ball_subrob_req_i(i) <> ballDomain.subRobReq(i) + } + // --- Frontend -> MemDomain --- memDomain.io.global_issue_i <> frontend.io.mem_issue_o frontend.io.mem_complete_i <> memDomain.io.global_complete_o diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala index 43d529e7..f27bb088 100644 --- a/arch/src/main/scala/framework/frontend/Frontend.scala +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -7,6 +7,7 @@ import framework.frontend.decoder.{GlobalDecoder, PostGDCmd} import framework.frontend.globalrs.{GlobalReservationStation, GlobalRsComplete, GlobalRsIssue} import framework.top.GlobalConfig import framework.core.bbtile.{RoCCCommandBB, RoCCResponseBB} +import framework.balldomain.blink.SubRobRow /** * Frontend Module @@ -32,6 +33,9 @@ class Frontend(val b: GlobalConfig) extends Module { val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + // Ball -> SubROB request passthrough + val ball_subrob_req_i = Flipped(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) + // RoCC response val resp = Decoupled(new RoCCResponseBB(b.core.xLen)) val busy = Output(Bool()) @@ -58,6 +62,11 @@ class Frontend(val b: GlobalConfig) extends Module { globalRs.io.mem_complete_i <> io.mem_complete_i globalRs.io.gp_complete_i <> io.gp_complete_i + // Wire SubROB request from BallDomain through to GlobalRS + for (i <- 0 until b.ballDomain.ballNum) { + globalRs.io.ball_subrob_req_i(i) <> io.ball_subrob_req_i(i) + } + io.resp <> globalRs.io.rs_rocc_o.resp io.busy := globalRs.io.rs_rocc_o.busy diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index 767e5d17..912efe81 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -9,7 +9,8 @@ case class FrontendParam( rob_entries: Int, rs_out_of_order_response: Boolean, bank_id_len: Int, - iter_len: Int) + iter_len: Int, + sub_rob_depth: Int) object FrontendParam { implicit val rw: ReadWriter[FrontendParam] = macroRW diff --git a/arch/src/main/scala/framework/frontend/configs/default.json b/arch/src/main/scala/framework/frontend/configs/default.json index 6be04f87..f9c67882 100644 --- a/arch/src/main/scala/framework/frontend/configs/default.json +++ b/arch/src/main/scala/framework/frontend/configs/default.json @@ -2,5 +2,6 @@ "rob_entries": 16, "rs_out_of_order_response": true, "bank_id_len": 15, - "iter_len": 16 + "iter_len": 16, + "sub_rob_depth": 64 } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index f1efba2a..9997fb1d 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -27,6 +27,8 @@ class GlobalROB(val b: GlobalConfig) extends Module { val issued_count = Output(UInt(log2Up(robDepth + 1).W)) val entry_valid = Output(Vec(robDepth, Bool())) val entry_complete = Output(Vec(robDepth, Bool())) + + val subRobActive = Input(Bool()) }) // --------------------------------------------------------------------------- @@ -122,7 +124,7 @@ class GlobalROB(val b: GlobalConfig) extends Module { val noHazard = !scoreboard.hasHazard val canIssue = hasValid && noHazard - io.issue.valid := canIssue + io.issue.valid := canIssue && !io.subRobActive io.issue.bits := robEntries(actualIssuePtr) scoreboard.issue.valid := false.B diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala index 1a6c830c..134113c4 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala @@ -9,6 +9,7 @@ import framework.frontend.decoder.{DomainId, PostGDCmd} import framework.frontend.decoder.GISA._ import framework.frontend.scoreboard.{BankAccessInfo, BankScoreboard} import framework.core.bbtile.RoCCResponseBB +import framework.balldomain.blink.SubRobRow // Global ROB entry - contains instruction + bank access info class GlobalRobEntry(val b: GlobalConfig) extends Bundle { @@ -17,11 +18,16 @@ class GlobalRobEntry(val b: GlobalConfig) extends Bundle { } // Global RS issue interface -class GlobalRsIssue(b: GlobalConfig) extends GlobalRobEntry(b) +class GlobalRsIssue(b: GlobalConfig) extends GlobalRobEntry(b) { + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) +} // Global RS completion interface class GlobalRsComplete(b: GlobalConfig) extends Bundle { - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) } // Global reservation station - between GlobalDecoder and each Domain @@ -45,6 +51,9 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + // Ball -> SubROB: write a row of sub-instructions + val ball_subrob_req_i = Flipped(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) + // RoCC response val rs_rocc_o = new Bundle { val resp = new DecoupledIO(new RoCCResponseBB(b.core.xLen)) @@ -56,7 +65,8 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { val barrier_release = Input(Bool()) }) - val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) + val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) + val subRob: Instance[SubROB] = Instantiate(new SubROB(b)) // ----------------------------------------------------------------------------- // Fence handling — fence does NOT enter ROB. @@ -114,61 +124,131 @@ class GlobalReservationStation(val b: GlobalConfig) extends Module { rob.io.alloc.ready && !anyStall // Normal cmd: ROB ready and no stall ) +// ----------------------------------------------------------------------------- +// SubROB write arbiter +// ----------------------------------------------------------------------------- + val subRobWriteArb = Module(new Arbiter(new SubRobRow(b), b.ballDomain.ballNum)) + for (i <- 0 until b.ballDomain.ballNum) { + subRobWriteArb.io.in(i) <> io.ball_subrob_req_i(i) + } + subRob.io.write <> subRobWriteArb.io.out + // ----------------------------------------------------------------------------- // Outbound - instruction issue (dispatch to corresponding domain based on domain_id) +// SubROB issues take priority over main ROB issues. // ----------------------------------------------------------------------------- val is_ball_domain = rob.io.issue.bits.cmd.domain_id === DomainId.BALL val is_mem_domain = rob.io.issue.bits.cmd.domain_id === DomainId.MEM val is_gp_domain = rob.io.issue.bits.cmd.domain_id === DomainId.GP - // Ball domain issue - io.ball_issue_o.valid := rob.io.issue.valid && is_ball_domain - io.ball_issue_o.bits := rob.io.issue.bits + val subRobIssueValid = subRob.io.issue.valid + val subRobCmd = subRob.io.issue.bits // PostGDCmd + + // Build a GlobalRsIssue for the sub-instruction + val subRobIssueEntry = Wire(new GlobalRsIssue(b)) + subRobIssueEntry.cmd := subRobCmd + subRobIssueEntry.rob_id := subRob.io.issueMasterRobId + subRobIssueEntry.is_sub := true.B + subRobIssueEntry.sub_rob_id := subRob.io.issueSubId + + val subRobIssBall = subRobCmd.domain_id === DomainId.BALL + val subRobIssMem = subRobCmd.domain_id === DomainId.MEM + val subRobIssGp = subRobCmd.domain_id === DomainId.GP - // Mem domain issue - io.mem_issue_o.valid := rob.io.issue.valid && is_mem_domain - io.mem_issue_o.bits := rob.io.issue.bits + // Build main ROB issue entry with is_sub/sub_rob_id cleared + val mainIssueEntry = Wire(new GlobalRsIssue(b)) + mainIssueEntry.cmd := rob.io.issue.bits.cmd + mainIssueEntry.rob_id := rob.io.issue.bits.rob_id + mainIssueEntry.is_sub := false.B + mainIssueEntry.sub_rob_id := 0.U - // GP domain issue - io.gp_issue_o.valid := rob.io.issue.valid && is_gp_domain - io.gp_issue_o.bits := rob.io.issue.bits + // Ball issue: SubROB priority + io.ball_issue_o.valid := Mux( + subRobIssueValid && subRobIssBall, + true.B, + rob.io.issue.valid && is_ball_domain && !subRobIssueValid + ) + io.ball_issue_o.bits := Mux(subRobIssueValid && subRobIssBall, subRobIssueEntry, mainIssueEntry) + + // Mem issue: SubROB priority + io.mem_issue_o.valid := Mux( + subRobIssueValid && subRobIssMem, + true.B, + rob.io.issue.valid && is_mem_domain && !subRobIssueValid + ) + io.mem_issue_o.bits := Mux(subRobIssueValid && subRobIssMem, subRobIssueEntry, mainIssueEntry) - // Set ROB ready signal - can only issue when target domain is ready - rob.io.issue.ready := + // GP issue: SubROB priority + io.gp_issue_o.valid := Mux( + subRobIssueValid && subRobIssGp, + true.B, + rob.io.issue.valid && is_gp_domain && !subRobIssueValid + ) + io.gp_issue_o.bits := Mux(subRobIssueValid && subRobIssGp, subRobIssueEntry, mainIssueEntry) + + // SubROB issue ready + subRob.io.issue.ready := + (subRobIssBall && io.ball_issue_o.ready) || + (subRobIssMem && io.mem_issue_o.ready) || + (subRobIssGp && io.gp_issue_o.ready) + + // Main ROB issue ready: yield when SubROB is issuing + rob.io.issue.ready := !subRobIssueValid && ( (is_ball_domain && io.ball_issue_o.ready) || (is_mem_domain && io.mem_issue_o.ready) || (is_gp_domain && io.gp_issue_o.ready) + ) + + // Tell GlobalROB to suppress its own issue when SubROB is active + rob.io.subRobActive := subRobIssueValid // ----------------------------------------------------------------------------- // Completion signal processing // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), 3)) + val completeArb = Module(new Arbiter(new GlobalRsComplete(b), 3)) // Connect Ball, Mem, and GP domain completion signals to arbiter completeArb.io.in(0).valid := io.ball_complete_i.valid - completeArb.io.in(0).bits := io.ball_complete_i.bits.rob_id + completeArb.io.in(0).bits := io.ball_complete_i.bits io.ball_complete_i.ready := completeArb.io.in(0).ready completeArb.io.in(1).valid := io.mem_complete_i.valid - completeArb.io.in(1).bits := io.mem_complete_i.bits.rob_id + completeArb.io.in(1).bits := io.mem_complete_i.bits io.mem_complete_i.ready := completeArb.io.in(1).ready completeArb.io.in(2).valid := io.gp_complete_i.valid - completeArb.io.in(2).bits := io.gp_complete_i.bits.rob_id + completeArb.io.in(2).bits := io.gp_complete_i.bits io.gp_complete_i.ready := completeArb.io.in(2).ready - // Decide whether to filter completion signals based on configuration + val completeBits = completeArb.io.out.bits + + // Route sub-completions to SubROB, main completions to main ROB + subRob.io.subComplete.valid := completeArb.io.out.valid && completeBits.is_sub + subRob.io.subComplete.bits := completeBits.sub_rob_id + + subRob.io.masterComplete.ready := true.B // main ROB always ready to accept masterComplete + + val normalComplete = completeArb.io.out.valid && !completeBits.is_sub + if (b.frontend.rs_out_of_order_response) { - // Out-of-order mode: accept all completion signals, ROB commits out-of-order internally - rob.io.complete <> completeArb.io.out + rob.io.complete.valid := normalComplete || subRob.io.masterComplete.valid + rob.io.complete.bits := Mux(subRob.io.masterComplete.valid, subRob.io.masterComplete.bits, completeBits.rob_id) } else { - // Sequential mode: only accept completion signals where rob_id == head_ptr - val isHeadComplete = completeArb.io.out.bits === rob.io.head_ptr - rob.io.complete.valid := completeArb.io.out.valid && isHeadComplete - rob.io.complete.bits := completeArb.io.out.bits - completeArb.io.out.ready := rob.io.complete.ready && isHeadComplete + val isHeadComplete = Mux( + subRob.io.masterComplete.valid, + subRob.io.masterComplete.bits === rob.io.head_ptr, + completeBits.rob_id === rob.io.head_ptr + ) + rob.io.complete.valid := (normalComplete || subRob.io.masterComplete.valid) && isHeadComplete + rob.io.complete.bits := Mux(subRob.io.masterComplete.valid, subRob.io.masterComplete.bits, completeBits.rob_id) } + completeArb.io.out.ready := Mux( + completeBits.is_sub, + subRob.io.subComplete.ready, + rob.io.complete.ready + ) + // ----------------------------------------------------------------------------- // Response generation // ----------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala b/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala new file mode 100644 index 00000000..1dca1bd7 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala @@ -0,0 +1,177 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.blink.SubRobRow +import framework.frontend.decoder.PostGDCmd + +@instantiable +class SubROB(val b: GlobalConfig) extends Module { + val subRobDepth = b.frontend.sub_rob_depth + val subIdBits = log2Up(subRobDepth * 4) + val robIdBits = log2Up(b.frontend.rob_entries) + val ballIdBits = log2Up(b.ballDomain.ballNum) + val rowIdBits = log2Up(subRobDepth) + + @public + val io = IO(new Bundle { + // Ball → SubROB: write a row of sub-instructions + val write = Flipped(Decoupled(new SubRobRow(b))) + // SubROB → GlobalRS: issue one slot at a time (PostGDCmd, domain_id determines target) + val issue = Decoupled(new PostGDCmd(b)) + val issueSubId = Output(UInt(subIdBits.W)) + val issueMasterRobId = Output(UInt(robIdBits.W)) + // GlobalRS → SubROB: a sub-instruction completed (sub_rob_id) + val subComplete = Flipped(Decoupled(UInt(subIdBits.W))) + // SubROB → main ROB: all sub-instructions done + val masterComplete = Decoupled(UInt(robIdBits.W)) + // Status + val occupied = Output(Bool()) + val lockedBallId = Output(UInt(ballIdBits.W)) + }) + + // ------------------------------------------------------------------------- + // Storage + // ------------------------------------------------------------------------- + val sram = SyncReadMem(subRobDepth, new SubRobRow(b)) + + val writePtr = RegInit(0.U(rowIdBits.W)) + val readPtr = RegInit(0.U(rowIdBits.W)) + val rowCount = RegInit(0.U((log2Up(subRobDepth) + 1).W)) + val lockedBallId = RegInit(0.U(ballIdBits.W)) + val masterRobId = RegInit(0.U(robIdBits.W)) + + def nextPtr(p: UInt): UInt = Mux(p === (subRobDepth - 1).U, 0.U, p + 1.U) + + val occupied = rowCount > 0.U + val isFull = rowCount === subRobDepth.U + val ballMatch = !occupied || (io.write.bits.ball_id === lockedBallId) + + // Write path: accept if not full AND ball_id matches (or not occupied yet) + io.write.ready := !isFull && ballMatch + + when(io.write.fire) { + sram.write(writePtr, io.write.bits) + writePtr := nextPtr(writePtr) + rowCount := rowCount + 1.U + when(!occupied) { + lockedBallId := io.write.bits.ball_id + masterRobId := io.write.bits.master_rob_id + } + } + + // ------------------------------------------------------------------------- + // FSM + // ------------------------------------------------------------------------- + // States: + // sIdle - nothing to do (rowCount == 0) + // sReadReq - issue SRAM read request for readPtr row + // sReadResp - SRAM data valid; dispatch valid slots one per cycle + // sWaitSlots - all slots issued; wait for all subCompletes + // sWaitMaster - all rows done; fire masterComplete then return to sIdle + val sIdle :: sReadReq :: sReadResp :: sWaitSlots :: sWaitMaster :: Nil = Enum(5) + val state = RegInit(sIdle) + + // SyncReadMem: request on cycle N → data valid on cycle N+1 + val sramReadEn = state === sReadReq + val sramData = sram.read(readPtr, sramReadEn) + val sramDataReg = RegNext(sramData) + val readPtrReg = RegNext(readPtr) + + // Per-row tracking registers (reset when moving to next row) + // slotIssued: have we already sent this slot to a domain? + // slotDone: have we received subComplete for this slot? + val slotIssued = RegInit(VecInit(Seq.fill(4)(false.B))) + val slotDone = RegInit(VecInit(Seq.fill(4)(false.B))) + + // Combinational: which slots still need to be issued? + val slotNeedsIssue = VecInit((0 until 4).map(i => sramDataReg.slots(i).valid && !slotIssued(i))) + val hasSlotToIssue = slotNeedsIssue.asUInt.orR + val firstSlotIdx = PriorityEncoder(slotNeedsIssue.asUInt) + + // Combinational: are all valid slots done? + val allSlotsDone = VecInit((0 until 4).map(i => !sramDataReg.slots(i).valid || slotDone(i))).asUInt.andR + + // Issue output (valid only in sReadResp when there's a slot to issue) + io.issue.valid := (state === sReadResp) && hasSlotToIssue + io.issue.bits := sramDataReg.slots(firstSlotIdx).cmd + io.issueSubId := readPtrReg * 4.U + firstSlotIdx + io.issueMasterRobId := masterRobId + + // subComplete: always ready, mark the corresponding slot done + io.subComplete.ready := true.B + when(io.subComplete.fire) { + val subId = io.subComplete.bits + val slotIdx = subId(1, 0) + slotDone(slotIdx) := true.B + } + + // masterComplete + io.masterComplete.valid := state === sWaitMaster + io.masterComplete.bits := masterRobId + + // Status outputs + io.occupied := occupied + io.lockedBallId := lockedBallId + + // ------------------------------------------------------------------------- + // FSM transitions + // ------------------------------------------------------------------------- + // Helper: advance past current row (called when row is complete) + def advanceRow(): Unit = { + readPtr := nextPtr(readPtr) + rowCount := rowCount - 1.U + slotIssued.foreach(_ := false.B) + slotDone.foreach(_ := false.B) + } + + switch(state) { + is(sIdle) { + when(occupied)(state := sReadReq) + } + is(sReadReq) { + // SRAM read issued, data will be valid next cycle + state := sReadResp + } + is(sReadResp) { + // Fire issued slot + when(io.issue.fire) { + slotIssued(firstSlotIdx) := true.B + } + // Check if all slots have been issued + // After marking current slot issued, recalculate + val allIssued = VecInit((0 until 4).map(i => + !sramDataReg.slots(i).valid || slotIssued(i) || + (io.issue.fire && firstSlotIdx === i.U) + )).asUInt.andR + + when(allIssued) { + // Check fast path: all already done (e.g., empty row or immediate completion) + val allDoneNow = VecInit((0 until 4).map(i => !sramDataReg.slots(i).valid || slotDone(i))).asUInt.andR + when(allDoneNow) { + // Fast path: skip sWaitSlots + advanceRow() + state := Mux(rowCount === 1.U, sWaitMaster, sReadReq) + }.otherwise { + state := sWaitSlots + } + } + // else: stay in sReadResp to dispatch remaining slots + } + is(sWaitSlots) { + when(allSlotsDone) { + advanceRow() + state := Mux(rowCount === 1.U, sWaitMaster, sReadReq) + } + } + is(sWaitMaster) { + when(io.masterComplete.fire) { + lockedBallId := 0.U + masterRobId := 0.U + state := sIdle + } + } + } +} diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index 8985787f..bdc9f6ea 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -28,8 +28,10 @@ class GpDomain(val b: GlobalConfig) extends Module { decoder.io.inst_i <> io.global_issue_i.bits.cmd.cmd val decoded = decoder.io.decoded_o - io.global_complete_o.valid := io.global_issue_i.valid - io.global_complete_o.bits.rob_id := io.global_issue_i.bits.rob_id + io.global_complete_o.valid := io.global_issue_i.valid + io.global_complete_o.bits.rob_id := io.global_issue_i.bits.rob_id + io.global_complete_o.bits.is_sub := io.global_issue_i.bits.is_sub + io.global_complete_o.bits.sub_rob_id := io.global_issue_i.bits.sub_rob_id io.busy := false.B diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index 6d713206..c2813773 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -97,10 +97,12 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // MemDecoder -> MemReservationStation // ----------------------------------------------------------------------------- // Connect decoded instruction and global rob_id - memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid - memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits - memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id - memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready + memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid + memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits + memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id + memRs.io.mem_decode_cmd_i.bits.is_sub := io.global_issue_i.bits.is_sub + memRs.io.mem_decode_cmd_i.bits.sub_rob_id := io.global_issue_i.bits.sub_rob_id + memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready // ----------------------------------------------------------------------------- // MemReservationStation -> MemLoader/MemStorer @@ -171,7 +173,11 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.interdma.write_is_shared := memLoader.io.is_shared // Completion signal connected to global RS - io.global_complete_o <> memRs.io.complete_o + io.global_complete_o.valid := memRs.io.complete_o.valid + io.global_complete_o.bits.rob_id := memRs.io.complete_o.bits.rob_id + io.global_complete_o.bits.is_sub := memRs.io.complete_o.bits.is_sub + io.global_complete_o.bits.sub_rob_id := memRs.io.complete_o.bits.sub_rob_id + memRs.io.complete_o.ready := io.global_complete_o.ready // Busy signal // Simple busy signal diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala index 9769f09f..81343d23 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/rs/reservationStation.scala @@ -9,14 +9,18 @@ import framework.top.GlobalConfig // Mem domain issue interface - includes global rob_id class MemRsIssue(val b: GlobalConfig) extends Bundle { - val cmd = new MemDecodeCmd(b) + val cmd = new MemDecodeCmd(b) // Global ROB ID - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) } // Mem domain completion interface class MemRsComplete(val b: GlobalConfig) extends Bundle { - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) } // Mem domain issue interface combination (Load + Store) @@ -42,9 +46,11 @@ class MemReservationStation(val b: GlobalConfig) extends Module { // Decoded instruction input (with global rob_id) val mem_decode_cmd_i = Flipped(new DecoupledIO(new Bundle { - val cmd = new MemDecodeCmd(b) + val cmd = new MemDecodeCmd(b) // Global ROB ID - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) })) // Rs -> MemLoader/MemStorer @@ -58,8 +64,10 @@ class MemReservationStation(val b: GlobalConfig) extends Module { // Simple FIFO queue, only for buffering val fifo = Module(new Queue( new Bundle { - val cmd = new MemDecodeCmd(b) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val cmd = new MemDecodeCmd(b) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) }, entries = 4 )) // Small buffer is sufficient @@ -75,19 +83,25 @@ class MemReservationStation(val b: GlobalConfig) extends Module { val headEntry = fifo.io.deq.bits // Load issue - io.issue_o.ld.valid := fifo.io.deq.valid && headEntry.cmd.is_load - io.issue_o.ld.bits.cmd := headEntry.cmd - io.issue_o.ld.bits.rob_id := headEntry.rob_id + io.issue_o.ld.valid := fifo.io.deq.valid && headEntry.cmd.is_load + io.issue_o.ld.bits.cmd := headEntry.cmd + io.issue_o.ld.bits.rob_id := headEntry.rob_id + io.issue_o.ld.bits.is_sub := headEntry.is_sub + io.issue_o.ld.bits.sub_rob_id := headEntry.sub_rob_id // Store issue - io.issue_o.st.valid := fifo.io.deq.valid && headEntry.cmd.is_store - io.issue_o.st.bits.cmd := headEntry.cmd - io.issue_o.st.bits.rob_id := headEntry.rob_id + io.issue_o.st.valid := fifo.io.deq.valid && headEntry.cmd.is_store + io.issue_o.st.bits.cmd := headEntry.cmd + io.issue_o.st.bits.rob_id := headEntry.rob_id + io.issue_o.st.bits.is_sub := headEntry.is_sub + io.issue_o.st.bits.sub_rob_id := headEntry.sub_rob_id // Config issue - io.issue_o.cf.valid := fifo.io.deq.valid && headEntry.cmd.is_config - io.issue_o.cf.bits.cmd := headEntry.cmd - io.issue_o.cf.bits.rob_id := headEntry.rob_id + io.issue_o.cf.valid := fifo.io.deq.valid && headEntry.cmd.is_config + io.issue_o.cf.bits.cmd := headEntry.cmd + io.issue_o.cf.bits.rob_id := headEntry.rob_id + io.issue_o.cf.bits.is_sub := headEntry.is_sub + io.issue_o.cf.bits.sub_rob_id := headEntry.sub_rob_id // FIFO deq.ready - can only dequeue when target unit is ready fifo.io.deq.ready := @@ -98,22 +112,22 @@ class MemReservationStation(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- // Completion signal processing - directly forward to global RS // ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(UInt(log2Up(b.frontend.rob_entries).W), 3)) + val completeArb = Module(new Arbiter(new MemRsComplete(b), 3)) completeArb.io.in(0).valid := io.commit_i.ld.valid - completeArb.io.in(0).bits := io.commit_i.ld.bits.rob_id + completeArb.io.in(0).bits := io.commit_i.ld.bits io.commit_i.ld.ready := completeArb.io.in(0).ready completeArb.io.in(1).valid := io.commit_i.st.valid - completeArb.io.in(1).bits := io.commit_i.st.bits.rob_id + completeArb.io.in(1).bits := io.commit_i.st.bits io.commit_i.st.ready := completeArb.io.in(1).ready completeArb.io.in(2).valid := io.commit_i.cf.valid - completeArb.io.in(2).bits := io.commit_i.cf.bits.rob_id + completeArb.io.in(2).bits := io.commit_i.cf.bits io.commit_i.cf.ready := completeArb.io.in(2).ready // Forward completion signal (with global rob_id) - io.complete_o.valid := completeArb.io.out.valid - io.complete_o.bits.rob_id := completeArb.io.out.bits - completeArb.io.out.ready := io.complete_o.ready + io.complete_o.valid := completeArb.io.out.valid + io.complete_o.bits := completeArb.io.out.bits + completeArb.io.out.ready := io.complete_o.ready } diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala index 4718a7e6..819ffec1 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemConfiger.scala @@ -37,27 +37,33 @@ class MemConfiger(val b: GlobalConfig) extends Module { val col_reg = RegInit(0.U(log2Up(b.memDomain.bankEntries).W)) val vbank_id_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) val counter = RegInit(0.U(4.W)) - io.config.bits.is_multi := false.B - io.config.bits.is_shared := false.B - io.config.bits.alloc := false.B - io.config.bits.vbank_id := 0.U(8.W) - io.config.bits.group_id := 0.U(3.W) - io.config.bits.hart_id := io.hartid - io.config.valid := false.B - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + io.config.bits.is_multi := false.B + io.config.bits.is_shared := false.B + io.config.bits.alloc := false.B + io.config.bits.vbank_id := 0.U(8.W) + io.config.bits.group_id := 0.U(3.W) + io.config.bits.hart_id := io.hartid + io.config.valid := false.B + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := 0.U(rob_id_width.W) + io.cmdResp.bits.is_sub := false.B + io.cmdResp.bits.sub_rob_id := 0.U when(state === idle) { when(io.cmdReq.valid) { when(io.cmdReq.bits.cmd.special(9, 5) > 1.U) { //is multi bank (col > 1) - state := config - col_reg := io.cmdReq.bits.cmd.special(9, 5) - alloc_reg := io.cmdReq.bits.cmd.special(10) - is_shared_reg := io.cmdReq.bits.cmd.is_shared - vbank_id_reg := io.cmdReq.bits.cmd.bank_id - rob_id_reg := io.cmdReq.bits.rob_id + state := config + col_reg := io.cmdReq.bits.cmd.special(9, 5) + alloc_reg := io.cmdReq.bits.cmd.special(10) + is_shared_reg := io.cmdReq.bits.cmd.is_shared + vbank_id_reg := io.cmdReq.bits.cmd.bank_id + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id }.otherwise { //not multi bank io.config.bits.alloc := io.cmdReq.bits.cmd.special(10) @@ -65,8 +71,10 @@ class MemConfiger(val b: GlobalConfig) extends Module { io.config.bits.vbank_id := io.cmdReq.bits.cmd.bank_id io.config.valid := true.B - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := io.cmdReq.bits.rob_id + io.cmdResp.bits.is_sub := io.cmdReq.bits.is_sub + io.cmdResp.bits.sub_rob_id := io.cmdReq.bits.sub_rob_id } } @@ -83,10 +91,12 @@ class MemConfiger(val b: GlobalConfig) extends Module { } when(counter >= col_reg) { - state := idle - counter := 0.U - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := rob_id_reg + state := idle + counter := 0.U + io.cmdResp.valid := true.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg } } io.cmdReq.ready := state === idle diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala index 72835299..372dec51 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemLoader.scala @@ -36,13 +36,15 @@ class MemLoader(val b: GlobalConfig) extends Module { val s_idle :: s_dma_req :: s_dma_wait :: s_wait_last_write :: s_done :: Nil = Enum(5) val state = RegInit(s_idle) - val rob_id_reg = RegInit(0.U(rob_id_width.W)) - val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) - val iter_reg = Reg(UInt(b.frontend.iter_len.W)) - val resp_count = RegInit(0.U(log2Up(16).W)) - val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) - val stride_reg = Reg(UInt(11.W)) - val is_shared_reg = RegInit(false.B) + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) + val iter_reg = Reg(UInt(b.frontend.iter_len.W)) + val resp_count = RegInit(0.U(log2Up(16).W)) + val wr_bank_reg = Reg(UInt(log2Up(b.memDomain.bankNum).W)) + val stride_reg = Reg(UInt(11.W)) + val is_shared_reg = RegInit(false.B) // Group counter for multi-bank writes val group_counter = RegInit(0.U(4.W)) @@ -87,9 +89,11 @@ class MemLoader(val b: GlobalConfig) extends Module { io.is_shared := is_shared_reg // cmdResp (Decoupled): hold valid until accepted - io.cmdResp.valid := (state === s_done) - io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.valid := (state === s_done) + io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg // ----------------------------- // Receive load instruction @@ -97,6 +101,8 @@ class MemLoader(val b: GlobalConfig) extends Module { when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { state := s_dma_req rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id mem_addr_reg := io.cmdReq.bits.cmd.mem_addr wr_bank_reg := io.cmdReq.bits.cmd.bank_id // stride from rs2[57:39] diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala index 92826014..2c2516e0 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/MemStorer.scala @@ -44,6 +44,8 @@ class MemStorer(val b: GlobalConfig) extends Module { val state = RegInit(s_idle) val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) val mem_addr_reg = RegInit(0.U(b.memDomain.memAddrLen.W)) val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) val stride_reg = RegInit(0.U(10.W)) @@ -79,10 +81,12 @@ class MemStorer(val b: GlobalConfig) extends Module { io.cmdReq.ready := (state === s_idle) when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { - rob_id_reg := io.cmdReq.bits.rob_id - mem_addr_reg := io.cmdReq.bits.cmd.mem_addr - rd_bank_reg := io.cmdReq.bits.cmd.bank_id - stride_reg := io.cmdReq.bits.cmd.special(57, 39) + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + rd_bank_reg := io.cmdReq.bits.cmd.bank_id + stride_reg := io.cmdReq.bits.cmd.special(57, 39) // Query and save group count group_count_reg := io.query_group_count @@ -297,8 +301,10 @@ class MemStorer(val b: GlobalConfig) extends Module { // ----------------------------- // Completion // ----------------------------- - io.cmdResp.valid := (state === s_done) - io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.valid := (state === s_done) + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg when(io.cmdResp.fire) { state := s_idle From 47b15aaaab6ebe4cbdcd5f759c3aebfda1673d1b Mon Sep 17 00:00:00 2001 From: sjm Date: Sun, 15 Mar 2026 17:38:45 +0800 Subject: [PATCH 176/238] [arch] Make MemMidend more general --- .../scala/framework/memdomain/MemDomain.scala | 23 ++-- .../memdomain/midend/MemMidend.scala | 121 ++++++++---------- 2 files changed, 70 insertions(+), 74 deletions(-) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 75c0737f..86331731 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -82,14 +82,21 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { io.tl_reader <> frontend.io.tl_reader io.tl_writer <> frontend.io.tl_writer - // Ball Domain interface connects directly to midend - midend.io.balldomain.bankRead <> io.ballDomain.bankRead - midend.io.balldomain.bankWrite <> io.ballDomain.bankWrite - midend.io.frontend.bankRead <> frontend.io.interdma.bankRead - midend.io.frontend.bankWrite <> frontend.io.interdma.bankWrite - midend.io.frontend.read_is_shared := frontend.io.interdma.read_is_shared - midend.io.frontend.write_is_shared := frontend.io.interdma.write_is_shared - midend.io.hartid := io.hartid + // Ball Domain interface connects to midend unified bankRead/bankWrite + // Indices [0, totalBallRead) are balldomain; last index is frontend (DMA) + for (i <- 0 until totalBallRead) { + midend.io.bankRead(i).bankRead <> io.ballDomain.bankRead(i) + midend.io.bankRead(i).is_shared := false.B + } + for (i <- 0 until totalBallWrite) { + midend.io.bankWrite(i).bankWrite <> io.ballDomain.bankWrite(i) + midend.io.bankWrite(i).is_shared := false.B + } + midend.io.bankRead(totalBallRead).bankRead <> frontend.io.interdma.bankRead + midend.io.bankRead(totalBallRead).is_shared := frontend.io.interdma.read_is_shared + midend.io.bankWrite(totalBallWrite).bankWrite <> frontend.io.interdma.bankWrite + midend.io.bankWrite(totalBallWrite).is_shared := frontend.io.interdma.write_is_shared + midend.io.hartid := io.hartid midend.io.mem_req <> backend.io.mem_req backend.io.config <> frontend.io.config diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index e501a3f0..99162f18 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -2,55 +2,62 @@ package framework.memdomain.midend import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.Parameters import framework.top.GlobalConfig import framework.balldomain.blink.{BankRead, BankWrite} -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public} import framework.memdomain.backend.MemRequestIO +// BankRead/BankWrite with is_shared flag, used for unified midend interface +class BankReadWithShared(val b: GlobalConfig) extends Bundle { + val bankRead = new BankRead(b) + val is_shared = Input(Bool()) +} + +class BankWriteWithShared(val b: GlobalConfig) extends Bundle { + val bankWrite = new BankWrite(b) + val is_shared = Input(Bool()) +} + /** * MemMidend: Midend module for memory scheduling * Connects MemFrontend to MemManager * - * Basic direct connection: routes requests from frontend to backend channels + * Unified interface: bankRead/bankWrite Vecs include both balldomain and frontend requests. + * The last entry (index totalBallRead / totalBallWrite) is the frontend (DMA). + * All requests go through the same mapping table and channel allocation logic. */ @instantiable class MemMidend(val b: GlobalConfig) extends Module { val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + // Total slots: balldomain entries + 1 frontend entry + val totalRead = totalBallRead + 1 + val totalWrite = totalBallWrite + 1 + @public val io = IO(new Bundle { - - // Input from frontend (Ball Domain read/write requests) - receiver perspective - val frontend = new Bundle { - val bankRead = new BankRead(b) - val bankWrite = new BankWrite(b) - val read_is_shared = Input(Bool()) - val write_is_shared = Input(Bool()) - } + // Unified read/write interfaces: indices [0, totalBallRead) are balldomain, + // index totalBallRead is frontend (DMA). Same for write. + val bankRead = Vec(totalRead, new BankReadWithShared(b)) + val bankWrite = Vec(totalWrite, new BankWriteWithShared(b)) val hartid = Input(UInt(b.core.xLen.W)) - val balldomain = new Bundle { - val bankRead = Vec(totalBallRead, new BankRead(b)) - val bankWrite = Vec(totalBallWrite, new BankWrite(b)) - } - - // Output to backend (MemManager) - MemManager expects Flipped, so we don't flip here + // Output to backend (MemManager) val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) }) // ----------------------------------------------------------------------------- - // Mapping table for tracking balldomain requests + // Mapping table for tracking all requests (balldomain + frontend) // ----------------------------------------------------------------------------- class MappingTableEntry extends Bundle { val valid = Bool() val isRead = Bool() - val id = UInt(log2Ceil(math.max(totalBallRead, totalBallWrite)).W) + val id = UInt(log2Ceil(math.max(totalRead, totalWrite)).W) } - val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel - 1)(0.U.asTypeOf(new MappingTableEntry)))) + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(0.U.asTypeOf(new MappingTableEntry)))) def addEntry(idx: UInt, isRead: Bool, id: UInt): Unit = { mappingTable(idx).valid := true.B @@ -68,13 +75,13 @@ class MemMidend(val b: GlobalConfig) extends Module { def isAllocated(isRead: Bool, id: UInt): Bool = mappingTable.map(entry => entry.valid && entry.isRead === isRead && entry.id === id).reduce(_ || _) - for (i <- 0 until totalBallRead) { - //Default values - io.balldomain.bankRead(i).io.req.ready := false.B - io.balldomain.bankRead(i).io.resp.valid := false.B; - io.balldomain.bankRead(i).io.resp.bits := DontCare + // Allocate channels for reads (all entries including frontend) + for (i <- 0 until totalRead) { + io.bankRead(i).bankRead.io.req.ready := false.B + io.bankRead(i).bankRead.io.resp.valid := false.B + io.bankRead(i).bankRead.io.resp.bits := DontCare - when(io.balldomain.bankRead(i).io.req.valid && !isAllocated(true.B, i.U)) { + when(io.bankRead(i).bankRead.io.req.valid && !isAllocated(true.B, i.U)) { val (hasFree, chanId) = allocateChannel() when(hasFree) { addEntry(chanId, true.B, i.U) @@ -82,20 +89,17 @@ class MemMidend(val b: GlobalConfig) extends Module { } } - // For ball writes, only allocate one request per cycle to avoid conflicts - // Find the first unallocated request and allocate it - val pendingWrites = - VecInit((0 until totalBallWrite).map(i => io.balldomain.bankWrite(i).io.req.valid && !isAllocated(false.B, i.U))) + // Allocate channels for writes: one per cycle to avoid conflicts + val pendingWrites = + VecInit((0 until totalWrite).map(i => io.bankWrite(i).bankWrite.io.req.valid && !isAllocated(false.B, i.U))) val hasPendingWrite = pendingWrites.asUInt.orR val nextWriteToAllocate = PriorityEncoder(pendingWrites) - for (i <- 0 until totalBallWrite) { - //Default values - io.balldomain.bankWrite(i).io.req.ready := false.B - io.balldomain.bankWrite(i).io.resp.valid := false.B; - io.balldomain.bankWrite(i).io.resp.bits := DontCare + for (i <- 0 until totalWrite) { + io.bankWrite(i).bankWrite.io.req.ready := false.B + io.bankWrite(i).bankWrite.io.resp.valid := false.B + io.bankWrite(i).bankWrite.io.resp.bits := DontCare - // Only allocate if this is the selected request when(hasPendingWrite && nextWriteToAllocate === i.U) { val (hasFree, chanId) = allocateChannel() when(hasFree) { @@ -104,9 +108,8 @@ class MemMidend(val b: GlobalConfig) extends Module { } } - //Connect balldomain to backend - for (i <- 0 until b.top.memBallChannelNum) { - //Default values + // Connect mapped entries to backend channels + for (i <- 0 until b.memDomain.bankChannel) { io.mem_req(i).read.req.valid := false.B io.mem_req(i).read.req.bits := DontCare io.mem_req(i).read.resp.ready := false.B @@ -119,48 +122,34 @@ class MemMidend(val b: GlobalConfig) extends Module { io.mem_req(i).hart_id := io.hartid val isRead = mappingTable(i).isRead - val ballRead = io.balldomain.bankRead(mappingTable(i).id).io - val ballWrite = io.balldomain.bankWrite(mappingTable(i).id).io - val rbank_id = io.balldomain.bankRead(mappingTable(i).id).bank_id - val wbank_id = io.balldomain.bankWrite(mappingTable(i).id).bank_id - val rgroup_id = io.balldomain.bankRead(mappingTable(i).id).group_id - val wgroup_id = io.balldomain.bankWrite(mappingTable(i).id).group_id + val rid = mappingTable(i).id + val wid = mappingTable(i).id + val ballRead = io.bankRead(rid).bankRead.io + val ballWrite = io.bankWrite(wid).bankWrite.io + val rbank_id = io.bankRead(rid).bankRead.bank_id + val wbank_id = io.bankWrite(wid).bankWrite.bank_id + val rgroup_id = io.bankRead(rid).bankRead.group_id + val wgroup_id = io.bankWrite(wid).bankWrite.group_id + val r_shared = io.bankRead(rid).is_shared + val w_shared = io.bankWrite(wid).is_shared when(mappingTable(i).valid) { when(isRead) { io.mem_req(i).read <> ballRead io.mem_req(i).bank_id := rbank_id io.mem_req(i).group_id := rgroup_id + io.mem_req(i).is_shared := r_shared }.otherwise { io.mem_req(i).write <> ballWrite io.mem_req(i).bank_id := wbank_id io.mem_req(i).group_id := wgroup_id + io.mem_req(i).is_shared := w_shared } } } - //Connect frontend to backend - io.mem_req(b.top.memBallChannelNum).write <> io.frontend.bankWrite.io - io.mem_req(b.top.memBallChannelNum).read <> io.frontend.bankRead.io - io.mem_req(b.top.memBallChannelNum).bank_id := Mux( - io.frontend.bankRead.io.req.valid, - io.frontend.bankRead.bank_id, - io.frontend.bankWrite.bank_id - ) - io.mem_req(b.top.memBallChannelNum).group_id := Mux( - io.frontend.bankRead.io.req.valid, - io.frontend.bankRead.group_id, - io.frontend.bankWrite.group_id - ) - io.mem_req(b.top.memBallChannelNum).is_shared := Mux( - io.frontend.bankRead.io.req.valid, - io.frontend.read_is_shared, - io.frontend.write_is_shared - ) - io.mem_req(b.top.memBallChannelNum).hart_id := io.hartid - // Mapping table release - for (i <- 0 until b.top.memBallChannelNum - 1) { + for (i <- 0 until b.memDomain.bankChannel) { val releaseCounter = RegInit(0.U(5.W)) when(mappingTable(i).valid && !(io.mem_req(i).read.resp.valid || From 8bd6970fd82308664d3bd2d182186818ae9e3758 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 16 Mar 2026 04:19:29 +0800 Subject: [PATCH 177/238] [arch] fix: fix bugs in gemminiball [bb-tests] refacotr: update DISA for new funct7 encoding [arch] feat: enhance instruction tracing with bank enable support [bb-tests] feat: add different gemmini tests --- arch/src/csrc/include/monitor/trace.h | 8 +- arch/src/csrc/src/monitor/trace/itrace.cc | 33 ++- .../scala/examples/toy/balldomain/DISA.scala | 58 ++-- .../toy/balldomain/DomainDecoder.scala | 134 +++++---- .../balldomain/blink/SubRobRow.scala | 1 + .../prototype/gemmini/GemminiBall.scala | 191 ++++++++++++- .../prototype/gemmini/GemminiExCtrl.scala | 267 +++++++++++++----- .../prototype/gemmini/LoopCmd.scala | 74 +++++ .../prototype/gemmini/LoopCmdEncoder.scala | 125 ++++++++ .../prototype/gemmini/LoopConvAddrGen.scala | 77 +++++ .../prototype/gemmini/LoopConvUnroller.scala | 256 +++++++++++++++++ .../gemmini/LoopMatmulUnroller.scala | 262 +++++++++++++++++ .../framework/core/bbtile/RoCCTypes.scala | 1 + .../framework/core/bbtile/RocketCoreBB.scala | 1 + .../framework/frontend/configs/default.json | 4 +- .../framework/frontend/decoder/GISA.scala | 5 +- .../frontend/decoder/GobalDecoder.scala | 42 ++- .../frontend/globalrs/GlobalROB.scala | 45 +-- .../frontend/globalrs/ITraceDPI.scala | 21 +- .../framework/frontend/globalrs/SubROB.scala | 39 ++- .../scala/framework/memdomain/MemDomain.scala | 2 +- .../frontend/cmd_channel/decoder/DISA.scala | 9 +- .../cmd_channel/decoder/DomainDecoder.scala | 16 +- .../memdomain/midend/MemMidend.scala | 10 +- bb-tests/sardine/tests/test_ctest.py | 52 ++++ .../lib/bbhw/isa/{31_fence.c => 00_fence.c} | 2 +- .../bbhw/isa/{50_barrier.c => 01_barrier.c} | 2 +- ...2_gemmini_config.c => 02_gemmini_config.c} | 2 +- ...{46_gemmini_flush.c => 03_gemmini_flush.c} | 2 +- .../{48_bdb_counter.c => 04_bdb_counter.c} | 12 +- .../lib/bbhw/isa/105_gemmini_loop_conv_ws.c | 72 +++++ .../lib/bbhw/isa/{25_mvout.c => 16_mvout.c} | 4 +- .../lib/bbhw/isa/{23_mset.c => 32_mset.c} | 11 +- bb-tests/workloads/lib/bbhw/isa/33_im2col.c | 17 -- .../lib/bbhw/isa/{24_mvin.c => 33_mvin.c} | 4 +- .../workloads/lib/bbhw/isa/34_transpose.c | 13 - bb-tests/workloads/lib/bbhw/isa/38_relu.c | 13 - bb-tests/workloads/lib/bbhw/isa/40_quant.c | 18 -- bb-tests/workloads/lib/bbhw/isa/48_im2col.c | 17 ++ .../workloads/lib/bbhw/isa/49_transpose.c | 13 + bb-tests/workloads/lib/bbhw/isa/50_relu.c | 13 + bb-tests/workloads/lib/bbhw/isa/51_quant.c | 17 ++ .../bbhw/isa/{41_dequant.c => 52_dequant.c} | 11 +- ...gemmini_preload.c => 53_gemmini_preload.c} | 8 +- .../{49_bdb_backdoor.c => 54_bdb_backdoor.c} | 15 +- .../isa/{32_mul_warp16.c => 64_mul_warp16.c} | 5 +- .../lib/bbhw/isa/{39_bfp.c => 65_bfp.c} | 5 +- ...oaded.c => 66_gemmini_compute_preloaded.c} | 5 +- ...ted.c => 67_gemmini_compute_accumulated.c} | 5 +- .../lib/bbhw/isa/87_gemmini_loop_ws.c | 52 ++++ bb-tests/workloads/lib/bbhw/isa/isa.h | 64 ++--- .../workloads/src/CTest/toy/CMakeLists.txt | 28 +- .../src/CTest/toy/gemmini_matmul_test.c | 75 ----- .../toy/gemmini_os_cisc_atranspose_test.c | 43 +++ .../CTest/toy/gemmini_os_cisc_basic_test.c | 41 +++ .../toy/gemmini_os_cisc_btranspose_test.c | 43 +++ .../CTest/toy/gemmini_os_cisc_shift_test.c | 44 +++ .../toy/gemmini_os_risc_abtranspose_test.c | 46 +++ .../toy/gemmini_os_risc_atranspose_test.c | 44 +++ .../CTest/toy/gemmini_os_risc_basic_test.c | 42 +++ .../toy/gemmini_os_risc_btranspose_test.c | 44 +++ .../CTest/toy/gemmini_os_risc_shift_test.c | 45 +++ .../src/CTest/toy/gemmini_ws_cisc_conv_test.c | 71 +++++ .../CTest/toy/gemmini_ws_risc_basic_test.c | 47 +++ .../toy/gemmini_ws_risc_btranspose_test.c | 48 ++++ .../CTest/toy/gemmini_ws_risc_shift_test.c | 49 ++++ 66 files changed, 2386 insertions(+), 459 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmd.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvAddrGen.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvUnroller.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopMatmulUnroller.scala rename bb-tests/workloads/lib/bbhw/isa/{31_fence.c => 00_fence.c} (85%) rename bb-tests/workloads/lib/bbhw/isa/{50_barrier.c => 01_barrier.c} (95%) rename bb-tests/workloads/lib/bbhw/isa/{42_gemmini_config.c => 02_gemmini_config.c} (96%) rename bb-tests/workloads/lib/bbhw/isa/{46_gemmini_flush.c => 03_gemmini_flush.c} (89%) rename bb-tests/workloads/lib/bbhw/isa/{48_bdb_counter.c => 04_bdb_counter.c} (85%) create mode 100644 bb-tests/workloads/lib/bbhw/isa/105_gemmini_loop_conv_ws.c rename bb-tests/workloads/lib/bbhw/isa/{25_mvout.c => 16_mvout.c} (73%) rename bb-tests/workloads/lib/bbhw/isa/{23_mset.c => 32_mset.c} (73%) delete mode 100644 bb-tests/workloads/lib/bbhw/isa/33_im2col.c rename bb-tests/workloads/lib/bbhw/isa/{24_mvin.c => 33_mvin.c} (73%) delete mode 100644 bb-tests/workloads/lib/bbhw/isa/34_transpose.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/38_relu.c delete mode 100644 bb-tests/workloads/lib/bbhw/isa/40_quant.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/48_im2col.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/49_transpose.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/50_relu.c create mode 100644 bb-tests/workloads/lib/bbhw/isa/51_quant.c rename bb-tests/workloads/lib/bbhw/isa/{41_dequant.c => 52_dequant.c} (50%) rename bb-tests/workloads/lib/bbhw/isa/{43_gemmini_preload.c => 53_gemmini_preload.c} (61%) rename bb-tests/workloads/lib/bbhw/isa/{49_bdb_backdoor.c => 54_bdb_backdoor.c} (53%) rename bb-tests/workloads/lib/bbhw/isa/{32_mul_warp16.c => 64_mul_warp16.c} (63%) rename bb-tests/workloads/lib/bbhw/isa/{39_bfp.c => 65_bfp.c} (62%) rename bb-tests/workloads/lib/bbhw/isa/{44_gemmini_compute_preloaded.c => 66_gemmini_compute_preloaded.c} (76%) rename bb-tests/workloads/lib/bbhw/isa/{45_gemmini_compute_accumulated.c => 67_gemmini_compute_accumulated.c} (75%) create mode 100644 bb-tests/workloads/lib/bbhw/isa/87_gemmini_loop_ws.c delete mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c create mode 100644 bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index bf2572e6..9ce95c4d 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -11,14 +11,14 @@ extern "C" { // Called from GlobalROB when instructions are issued or completed void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete unsigned int rob_id, unsigned int domain_id, unsigned int funct, - unsigned long long rs1, unsigned long long rs2); + unsigned long long rs1, unsigned long long rs2, + unsigned char bank_enable); // DPI-C function for memory trace (mtrace) // Called from MemBackend when read/write requests are made void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read - unsigned char is_shared, - unsigned int channel, unsigned long long hart_id, - unsigned int vbank_id, + unsigned char is_shared, unsigned int channel, + unsigned long long hart_id, unsigned int vbank_id, unsigned int group_id, unsigned int addr, unsigned long long data_lo, unsigned long long data_hi); diff --git a/arch/src/csrc/src/monitor/trace/itrace.cc b/arch/src/csrc/src/monitor/trace/itrace.cc index f17d576a..dad62f6c 100644 --- a/arch/src/csrc/src/monitor/trace/itrace.cc +++ b/arch/src/csrc/src/monitor/trace/itrace.cc @@ -17,23 +17,44 @@ static void init_itrace() { } } +// bank_enable encoding (funct7[6:4]): +// 000 = none, 001 = 1rd, 010 = 1wr, 011 = 1rd+1wr, 100 = 2rd+1wr +// 101/110/111 = none (extended opcode space) +static const char *bank_enable_str(unsigned char enable) { + switch (enable) { + case 0: + return "---"; + case 1: + return "R--"; + case 2: + return "--W"; + case 3: + return "R-W"; + case 4: + return "RRW"; + default: + return "---"; // 5,6,7 = no bank access (extended) + } +} + // DPI-C function for instruction trace (itrace) // Called when an instruction is issued or completed in GlobalROB extern "C" void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete unsigned int rob_id, unsigned int domain_id, unsigned int funct, unsigned long long rs1, - unsigned long long rs2) { + unsigned long long rs2, unsigned char bank_enable) { init_itrace(); if (itrace_fp) { if (is_issue) { fprintf(itrace_fp, - "[ITRACE] ISSUE rob_id=%u domain=%u funct=0x%02x rs1=0x%016llx " - "rs2=0x%016llx\n", - rob_id, domain_id, funct, rs1, rs2); + "[ITRACE] ISSUE rob_id=%u domain=%u funct=0x%02x " + "bank=%s rs1=0x%016llx rs2=0x%016llx\n", + rob_id, domain_id, funct, bank_enable_str(bank_enable), rs1, rs2); } else { - fprintf(itrace_fp, "[ITRACE] COMPLETE rob_id=%u domain=%u funct=0x%02x\n", - rob_id, domain_id, funct); + fprintf(itrace_fp, + "[ITRACE] COMPLETE rob_id=%u domain=%u funct=0x%02x bank=%s\n", + rob_id, domain_id, funct, bank_enable_str(bank_enable)); } fflush(itrace_fp); } diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala index 7db99acc..71922b88 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DISA.scala @@ -3,23 +3,49 @@ package examples.toy.balldomain import chisel3._ import chisel3.util._ +// funct7 encoding: [6:4] = enable, [3:0] = opcode +// enable: 000=no_bank, 001=1rd, 010=1wr, 011=1rd+1wr, 100=2rd+1wr +// 101/110/111 = no_bank (extended space) object DISA { - val MATMUL_WARP16 = BitPat("b0100000") // 32 - val IM2COL = BitPat("b0100001") // 33 - val TRANSPOSE = BitPat("b0100010") // 34 - val RELU = BitPat("b0100110") // 38 - val SYSTOLIC = BitPat("b0100111") // 39 - val QUANT = BitPat("b0101000") // 40 - val DEQUANT = BitPat("b0101001") // 41 + // enable=100 (2 read + 1 write): opcode 0-3 + val MATMUL_WARP16 = BitPat("b1000000") // 64 (0x40) + val SYSTOLIC = BitPat("b1000001") // 65 (0x41) + val GEMMINI_COMPUTE_PRELOADED = BitPat("b1000010") // 66 (0x42) + val GEMMINI_COMPUTE_ACCUMULATED = BitPat("b1000011") // 67 (0x43) - // Gemmini systolic array instructions - val GEMMINI_CONFIG = BitPat("b0101010") // 42 - val GEMMINI_PRELOAD = BitPat("b0101011") // 43 - val GEMMINI_COMPUTE_PRELOADED = BitPat("b0101100") // 44 - val GEMMINI_COMPUTE_ACCUMULATED = BitPat("b0101101") // 45 - val GEMMINI_FLUSH = BitPat("b0101110") // 46 + // enable=011 (1 read + 1 write): opcode 0-6 + val IM2COL = BitPat("b0110000") // 48 (0x30) + val TRANSPOSE = BitPat("b0110001") // 49 (0x31) + val RELU = BitPat("b0110010") // 50 (0x32) + val QUANT = BitPat("b0110011") // 51 (0x33) + val DEQUANT = BitPat("b0110100") // 52 (0x34) + val GEMMINI_PRELOAD = BitPat("b0110101") // 53 (0x35) + val BDB_BACKDOOR = BitPat("b0110110") // 54 (0x36) - // TraceBall instructions - val BDB_COUNTER = BitPat("b0110000") // 48 - val BDB_BACKDOOR = BitPat("b0110001") // 49 + // enable=000 (no bank access): opcode 2-4 + val GEMMINI_CONFIG = BitPat("b0000010") // 2 (0x02) + val GEMMINI_FLUSH = BitPat("b0000011") // 3 (0x03) + val BDB_COUNTER = BitPat("b0000100") // 4 (0x04) + + // enable=101 (no bank, extended): Loop WS config, opcode 0-7 + val GEMMINI_LOOP_WS_CONFIG_BOUNDS = BitPat("b1010000") // 80 (0x50) + val GEMMINI_LOOP_WS_CONFIG_ADDR_A = BitPat("b1010001") // 81 (0x51) + val GEMMINI_LOOP_WS_CONFIG_ADDR_B = BitPat("b1010010") // 82 (0x52) + val GEMMINI_LOOP_WS_CONFIG_ADDR_D = BitPat("b1010011") // 83 (0x53) + val GEMMINI_LOOP_WS_CONFIG_ADDR_C = BitPat("b1010100") // 84 (0x54) + val GEMMINI_LOOP_WS_CONFIG_STRIDES_AB = BitPat("b1010101") // 85 (0x55) + val GEMMINI_LOOP_WS_CONFIG_STRIDES_DC = BitPat("b1010110") // 86 (0x56) + val GEMMINI_LOOP_WS = BitPat("b1010111") // 87 (0x57) + + // enable=110 (no bank, extended): Loop Conv WS config, opcode 0-9 + val GEMMINI_LOOP_CONV_WS_CONFIG_1 = BitPat("b1100000") // 96 (0x60) + val GEMMINI_LOOP_CONV_WS_CONFIG_2 = BitPat("b1100001") // 97 (0x61) + val GEMMINI_LOOP_CONV_WS_CONFIG_3 = BitPat("b1100010") // 98 (0x62) + val GEMMINI_LOOP_CONV_WS_CONFIG_4 = BitPat("b1100011") // 99 (0x63) + val GEMMINI_LOOP_CONV_WS_CONFIG_5 = BitPat("b1100100") // 100 (0x64) + val GEMMINI_LOOP_CONV_WS_CONFIG_6 = BitPat("b1100101") // 101 (0x65) + val GEMMINI_LOOP_CONV_WS_CONFIG_7 = BitPat("b1100110") // 102 (0x66) + val GEMMINI_LOOP_CONV_WS_CONFIG_8 = BitPat("b1100111") // 103 (0x67) + val GEMMINI_LOOP_CONV_WS_CONFIG_9 = BitPat("b1101000") // 104 (0x68) + val GEMMINI_LOOP_CONV_WS = BitPat("b1101001") // 105 (0x69) } diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala index 6f4de21e..5cf43e6b 100644 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala @@ -10,9 +10,10 @@ import framework.top.GlobalConfig // Detailed decode output for Ball domain class BallDecodeCmd(numBanks: Int, iterLen: Int) extends Bundle { - val bid = UInt(5.W) + val bid = UInt(5.W) + val funct7 = UInt(7.W) // raw funct7 for instruction routing // Iteration count - val iter = UInt(iterLen.W) + val iter = UInt(iterLen.W) // Ball-specific fields val op1_en = Bool() @@ -35,7 +36,7 @@ class BallDecodeCmd(numBanks: Int, iterLen: Int) extends Bundle { // Ball decode fields object BallDecodeFields extends Enumeration { type Field = Value - val OP1_EN, OP2_EN, WR_SPAD, OP1_FROM_SPAD, OP2_FROM_SPAD, OP1_SPADDR, OP2_SPADDR, WR_SPADDR, BID, SPECIAL = + val OP1_FROM_SPAD, OP2_FROM_SPAD, OP1_SPADDR, OP2_SPADDR, WR_SPADDR, BID, SPECIAL = Value } @@ -43,7 +44,7 @@ object BallDecodeFields extends Enumeration { object BallDefaultConstants { val Y = true.B val N = false.B - val DADDR = 0.U(15.W) + val DADDR = 0.U(10.W) val DBID = 0.U(5.W) val DSPECIAL = 0.U(64.W) } @@ -67,44 +68,44 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { val rs2 = cmd_i.bits.cmd.rs2Data // Unified rs1 layout: - // rs1[14:0] = BANK0 (op1 bank) - // rs1[29:15] = BANK1 (op2 bank) - // rs1[44:30] = BANK2 (wr bank) - // rs1[45] = BB_RD0 - // rs1[46] = BB_RD1 - // rs1[47] = BB_WR - // rs1[63:48] = ITER + // rs1[9:0] = BANK0 (op1 bank / 1st read) + // rs1[19:10] = BANK1 (op2 bank / 2nd read) + // rs1[29:20] = BANK2 (wr bank) + // rs1[63:30] = ITER (34-bit) + // + // Enable encoding in funct7[6:4]: + // 000 = no bank access + // 001 = 1 read (bank0) + // 010 = 1 write (bank2) + // 011 = 1 read + 1 write (bank0 read, bank2 write) + // 100 = 2 read + 1 write (bank0+bank1 read, bank2 write) + // 101,110,111 = no bank access (extended opcode space) // rs2 = special (full 64-bit) val op1_bank_raw = rs1(bankIdLen - 1, 0) - val op2_bank_raw = rs1(bankIdLen + 14, 15) - val wr_bank_raw = rs1(bankIdLen + 29, 30) - val iter_raw = rs1(63, 48) + val op2_bank_raw = rs1(bankIdLen + 9, 10) + val wr_bank_raw = rs1(bankIdLen + 19, 20) + val iter_raw = rs1(63, 30) + + // Enable decoding from funct7[6:4] + val enableBits = func7(6, 4) + val hasRd0 = enableBits === 1.U || enableBits === 3.U || enableBits === 4.U + val hasRd1 = enableBits === 4.U + val hasWr = enableBits === 2.U || enableBits === 3.U || enableBits === 4.U // Ball instruction decoding import BallDecodeFields._ - val ball_default_decode = List(N, N, N, N, N, 0.U, 0.U, 0.U, DBID, DSPECIAL) + val ball_default_decode = List(N, N, 0.U, 0.U, 0.U, DBID, DSPECIAL) val ball_decode_list = ListLookup( func7, ball_default_decode, Array( - // Unified encoding: banks from rs1[14:0]/[29:15]/[44:30], iter from rs1[63:48], special = rs2 - // op1 op2 wr op1s op2s op1_bank op2_bank wr_bank bid special - // Gemmini systolic array instructions — all share bid=7, sub-command in special[3:0] - MATMUL_WARP16 -> List(Y, Y, Y, Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 0.U, rs2), - RELU -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 1.U, rs2), - TRANSPOSE -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 2.U, rs2), - IM2COL -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 3.U, rs2), - SYSTOLIC -> List(Y, Y, Y, Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 4.U, rs2), - QUANT -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 5.U, rs2), - DEQUANT -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 6.U, rs2), - GEMMINI_CONFIG -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 7.U, Cat(rs2(63, 4), 0.U(4.W))), - GEMMINI_PRELOAD -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 7.U, Cat(rs2(63, 4), 1.U(4.W))), - GEMMINI_COMPUTE_PRELOADED -> List( - Y, - Y, - Y, + // enable=100 (2rd+1wr): bank0 read, bank1 read, bank2 write + // op1s op2s op1_bank op2_bank wr_bank bid special + MATMUL_WARP16 -> List(Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 0.U, rs2), + SYSTOLIC -> List(Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 4.U, rs2), + GEMMINI_COMPUTE_PRELOADED -> List( Y, Y, op1_bank_raw, @@ -113,10 +114,7 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { 7.U, Cat(rs2(63, 4), 2.U(4.W)) ), - GEMMINI_COMPUTE_ACCUMULATED -> List( - Y, - Y, - Y, + GEMMINI_COMPUTE_ACCUMULATED -> List( Y, Y, op1_bank_raw, @@ -125,10 +123,38 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { 7.U, Cat(rs2(63, 4), 3.U(4.W)) ), - GEMMINI_FLUSH -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 7.U, Cat(0.U(60.W), 4.U(4.W))), - // TraceBall instructions - BDB_COUNTER -> List(N, N, N, N, N, DADDR, DADDR, DADDR, 8.U, rs2), - BDB_BACKDOOR -> List(Y, N, Y, Y, N, op1_bank_raw, DADDR, wr_bank_raw, 8.U, rs2) + // enable=011 (1rd+1wr): bank0 read, bank2 write + RELU -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 1.U, rs2), + TRANSPOSE -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 2.U, rs2), + IM2COL -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 3.U, rs2), + QUANT -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 5.U, rs2), + DEQUANT -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 6.U, rs2), + GEMMINI_PRELOAD -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 7.U, Cat(rs2(63, 4), 1.U(4.W))), + BDB_BACKDOOR -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 8.U, rs2), + // enable=000 (no bank): config/flush/counter + GEMMINI_CONFIG -> List(N, N, DADDR, DADDR, DADDR, 7.U, Cat(rs2(63, 4), 0.U(4.W))), + GEMMINI_FLUSH -> List(N, N, DADDR, DADDR, DADDR, 7.U, Cat(0.U(60.W), 4.U(4.W))), + BDB_COUNTER -> List(N, N, DADDR, DADDR, DADDR, 8.U, rs2), + // enable=101 (no bank, extended): Loop WS config/trigger + GEMMINI_LOOP_WS_CONFIG_BOUNDS -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS_CONFIG_ADDR_A -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS_CONFIG_ADDR_B -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS_CONFIG_ADDR_D -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS_CONFIG_ADDR_C -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS_CONFIG_STRIDES_AB -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS_CONFIG_STRIDES_DC -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_WS -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + // enable=110 (no bank, extended): Loop Conv WS config/trigger + GEMMINI_LOOP_CONV_WS_CONFIG_1 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_2 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_3 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_4 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_5 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_6 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_7 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_8 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS_CONFIG_9 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), + GEMMINI_LOOP_CONV_WS -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2) ) ) @@ -137,34 +163,26 @@ class BallDomainDecoder(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------------- ball_decode_cmd_o.valid := cmd_i.valid && (cmd_i.bits.domain_id === DomainId.BALL) - ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) + ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) + ball_decode_cmd_o.bits.funct7 := Mux(ball_decode_cmd_o.valid, func7, 0.U) - // iter is always from rs1[63:48] - ball_decode_cmd_o.bits.iter := Mux( + // iter is always from rs1[63:30] + ball_decode_cmd_o.bits.iter := Mux( ball_decode_cmd_o.valid, iter_raw, 0.U(iterLen.W) ) - ball_decode_cmd_o.bits.special := Mux( + ball_decode_cmd_o.bits.special := Mux( ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.SPECIAL.id).asUInt, DSPECIAL ) - ball_decode_cmd_o.bits.op1_en := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.OP1_EN.id).asBool, - false.B - ) - ball_decode_cmd_o.bits.op2_en := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.OP2_EN.id).asBool, - false.B - ) - ball_decode_cmd_o.bits.wr_spad_en := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.WR_SPAD.id).asBool, - false.B - ) + + // Enable bits from funct7[6:4] + ball_decode_cmd_o.bits.op1_en := ball_decode_cmd_o.valid && hasRd0 + ball_decode_cmd_o.bits.op2_en := ball_decode_cmd_o.valid && hasRd1 + ball_decode_cmd_o.bits.wr_spad_en := ball_decode_cmd_o.valid && hasWr + ball_decode_cmd_o.bits.op1_from_spad := Mux( ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.OP1_FROM_SPAD.id).asBool, diff --git a/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala b/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala index 4edccdea..fe36732f 100644 --- a/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala +++ b/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala @@ -30,6 +30,7 @@ object SubRobRow { w.slots(i).cmd.domain_id := 0.U w.slots(i).cmd.cmd.raw_inst := 0.U w.slots(i).cmd.cmd.funct := 0.U + w.slots(i).cmd.cmd.funct3 := 0.U w.slots(i).cmd.cmd.rs2 := 0.U w.slots(i).cmd.cmd.rs1 := 0.U w.slots(i).cmd.cmd.xd := false.B diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala index 8db589a9..dd685459 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} +import framework.balldomain.rs.BallRsComplete import framework.top.GlobalConfig @instantiable @@ -20,18 +21,194 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall def blink: BlinkIO = io def status: BallStatus = io.status - val exCtrl: Instance[GemminiExCtrl] = Instantiate(new GemminiExCtrl(b)) + // ========================================================================= + // Sub-modules + // ========================================================================= + val exCtrl: Instance[GemminiExCtrl] = Instantiate(new GemminiExCtrl(b)) + val matmulUnroller: Instance[LoopMatmulUnroller] = Instantiate(new LoopMatmulUnroller(b)) + val convUnroller: Instance[LoopConvUnroller] = Instantiate(new LoopConvUnroller(b)) + val encoder: Instance[LoopCmdEncoder] = Instantiate(new LoopCmdEncoder(b)) + // ========================================================================= + // Config registers for Loop modes + // ========================================================================= + val loopWsConfig = Reg(new LoopWsConfig(b)) + val loopConvConfig = Reg(new LoopConvWsConfig(b)) + + // rob_id tracking for bank metadata val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) when(io.cmdReq.fire) { rob_id_reg := io.cmdReq.bits.rob_id } - // Command interface - exCtrl.io.cmdReq <> io.cmdReq - exCtrl.io.cmdResp <> io.cmdResp + // ========================================================================= + // Instruction routing by funct7 + // ========================================================================= + val funct7 = io.cmdReq.bits.cmd.funct7 + + val isConfig = funct7 === 0x02.U // GEMMINI_CONFIG (enable=000, opcode=2) + val isPreload = funct7 === 0x35.U // GEMMINI_PRELOAD (enable=011, opcode=5) + val isComputePre = funct7 === 0x42.U // GEMMINI_COMPUTE_PRELOADED (enable=100, opcode=2) + val isComputeAcc = funct7 === 0x43.U // GEMMINI_COMPUTE_ACCUMULATED (enable=100, opcode=3) + val isFlush = funct7 === 0x03.U // GEMMINI_FLUSH (enable=000, opcode=3) + val isExUnit = isConfig || isPreload || isComputePre || isComputeAcc || isFlush + + val isLoopWsConfig = funct7 >= 0x50.U && funct7 <= 0x56.U + val isLoopWsTrigger = funct7 === 0x57.U + val isLoopConvConfig = funct7 >= 0x60.U && funct7 <= 0x68.U + val isLoopConvTrigger = funct7 === 0x69.U + + // ========================================================================= + // ExUnit path (non-Loop: CONFIG/PRELOAD/COMPUTE/FLUSH) + // ========================================================================= + exCtrl.io.cmdReq.valid := io.cmdReq.valid && isExUnit + exCtrl.io.cmdReq.bits := io.cmdReq.bits + + // ========================================================================= + // Config latch path (immediate cmdResp) + // ========================================================================= + val configRespValid = RegInit(false.B) + val configRespBits = Reg(new BallRsComplete(b)) + configRespValid := false.B // default: pulse + + val rs2Data = io.cmdReq.bits.cmd.special + + when(io.cmdReq.fire && isLoopWsConfig) { + configRespValid := true.B + configRespBits.rob_id := io.cmdReq.bits.rob_id + configRespBits.is_sub := io.cmdReq.bits.is_sub + configRespBits.sub_rob_id := io.cmdReq.bits.sub_rob_id + switch(funct7) { + is(0x50.U) { + loopWsConfig.max_k := rs2Data(15, 0) + loopWsConfig.max_j := rs2Data(31, 16) + loopWsConfig.max_i := rs2Data(47, 32) + } + is(0x51.U)(loopWsConfig.dram_addr_a := rs2Data(38, 0)) + is(0x52.U)(loopWsConfig.dram_addr_b := rs2Data(38, 0)) + is(0x53.U)(loopWsConfig.dram_addr_d := rs2Data(38, 0)) + is(0x54.U)(loopWsConfig.dram_addr_c := rs2Data(38, 0)) + is(0x55.U) { + loopWsConfig.stride_a := rs2Data(31, 0) + loopWsConfig.stride_b := rs2Data(63, 32) + } + is(0x56.U) { + loopWsConfig.stride_d := rs2Data(31, 0) + loopWsConfig.stride_c := rs2Data(63, 32) + } + } + } + + when(io.cmdReq.fire && isLoopConvConfig) { + configRespValid := true.B + configRespBits.rob_id := io.cmdReq.bits.rob_id + configRespBits.is_sub := io.cmdReq.bits.is_sub + configRespBits.sub_rob_id := io.cmdReq.bits.sub_rob_id + switch(funct7) { + is(0x60.U) { + loopConvConfig.batch_size := rs2Data(15, 0) + loopConvConfig.in_dim := rs2Data(31, 16) + loopConvConfig.in_channels := rs2Data(47, 32) + } + is(0x61.U) { + loopConvConfig.out_channels := rs2Data(15, 0) + loopConvConfig.out_dim := rs2Data(31, 16) + loopConvConfig.stride := rs2Data(39, 32) + loopConvConfig.padding := rs2Data(47, 40) + } + is(0x62.U) { + loopConvConfig.kernel_dim := rs2Data(7, 0) + loopConvConfig.pool_size := rs2Data(15, 8) + loopConvConfig.pool_stride := rs2Data(23, 16) + loopConvConfig.pool_padding := rs2Data(31, 24) + } + is(0x63.U)(loopConvConfig.dram_addr_bias := rs2Data(38, 0)) + is(0x64.U)(loopConvConfig.dram_addr_input := rs2Data(38, 0)) + is(0x65.U)(loopConvConfig.dram_addr_weight := rs2Data(38, 0)) + is(0x66.U)(loopConvConfig.dram_addr_output := rs2Data(38, 0)) + is(0x67.U) { + loopConvConfig.input_stride := rs2Data(31, 0) + loopConvConfig.weight_stride := rs2Data(63, 32) + } + is(0x68.U)(loopConvConfig.output_stride := rs2Data(31, 0)) + } + } + + // ========================================================================= + // Loop trigger: latch bank IDs and start unroller (no cmdResp) + // Bank values come from rs2Data in the trigger instruction, but loopWsConfig + // Reg won't update until next edge. Override start.bits combinationally. + // ========================================================================= + matmulUnroller.io.start.valid := false.B + matmulUnroller.io.start.bits := loopWsConfig - // Bank read ports + when(io.cmdReq.fire && isLoopWsTrigger) { + loopWsConfig.bank_a := rs2Data(9, 0) + loopWsConfig.bank_b := rs2Data(19, 10) + loopWsConfig.bank_c := rs2Data(29, 20) + loopWsConfig.low_d := rs2Data(30) + matmulUnroller.io.start.valid := true.B + matmulUnroller.io.start.bits.bank_a := rs2Data(9, 0) + matmulUnroller.io.start.bits.bank_b := rs2Data(19, 10) + matmulUnroller.io.start.bits.bank_c := rs2Data(29, 20) + matmulUnroller.io.start.bits.low_d := rs2Data(30) + } + + convUnroller.io.start.valid := false.B + convUnroller.io.start.bits := loopConvConfig + + when(io.cmdReq.fire && isLoopConvTrigger) { + loopConvConfig.bank_input := rs2Data(9, 0) + loopConvConfig.bank_weight := rs2Data(19, 10) + loopConvConfig.bank_output := rs2Data(29, 20) + loopConvConfig.no_bias := rs2Data(30) + convUnroller.io.start.valid := true.B + convUnroller.io.start.bits.bank_input := rs2Data(9, 0) + convUnroller.io.start.bits.bank_weight := rs2Data(19, 10) + convUnroller.io.start.bits.bank_output := rs2Data(29, 20) + convUnroller.io.start.bits.no_bias := rs2Data(30) + } + + // ========================================================================= + // LoopUnrollers → Arbiter → LoopCmdEncoder → io.subRobReq + // ========================================================================= + val cmdArb = Module(new Arbiter(new LoopCmd(b), 2)) + cmdArb.io.in(0) <> matmulUnroller.io.cmd + cmdArb.io.in(1) <> convUnroller.io.cmd + encoder.io.cmd <> cmdArb.io.out + encoder.io.subRobRow <> io.subRobReq + encoder.io.ballId := ballCommonConfig.ballId.U + encoder.io.masterRobId := rob_id_reg + + // ========================================================================= + // cmdReq.ready: route to correct consumer + // ========================================================================= + io.cmdReq.ready := Mux( + isExUnit, + exCtrl.io.cmdReq.ready, + Mux( + isLoopWsConfig || isLoopConvConfig, + true.B, + Mux( + isLoopWsTrigger, + !matmulUnroller.io.busy, + Mux(isLoopConvTrigger, !convUnroller.io.busy, false.B) + ) + ) + ) + + // ========================================================================= + // cmdResp: mux between exUnit and config immediate response + // ========================================================================= + io.cmdResp <> exCtrl.io.cmdResp + when(configRespValid) { + io.cmdResp.valid := true.B + io.cmdResp.bits := configRespBits + } + + // ========================================================================= + // Bank connections (unchanged from original) + // ========================================================================= for (i <- 0 until inBW) { io.bankRead(i).io.req <> exCtrl.io.bankReadReq(i) exCtrl.io.bankReadResp(i) <> io.bankRead(i).io.resp @@ -44,7 +221,6 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall io.bankRead(1).bank_id := exCtrl.io.op2_bank_o } - // Bank write ports for (i <- 0 until outBW) { io.bankWrite(i).io <> exCtrl.io.bankWrite(i) io.bankWrite(i).bank_id := exCtrl.io.wr_bank_o @@ -54,7 +230,4 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall } io.status <> exCtrl.io.status - - io.subRobReq.valid := false.B - io.subRobReq.bits := SubRobRow.tieOff(b) } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala index be1ade87..fcd041ec 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala @@ -94,9 +94,9 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // ========================================================================= // State machine // ========================================================================= - val sIdle :: sPreloadReq :: sPreloadRead :: sPreloadFeed :: sComputeReq :: sComputeRead :: sComputeFeed :: sFlush :: sDrain :: sStore :: sCommit :: Nil = - Enum(11) - val state = RegInit(sIdle) + val sIdle :: sPreloadReq :: sPreloadRead :: sPreloadFeed :: sComputeReq :: sComputeRead :: sComputeFeed :: sComputeFlush :: sFlush :: sDrain :: sStore :: sCommit :: Nil = + Enum(12) + val state = RegInit(sIdle) val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) val is_sub_reg = RegInit(false.B) @@ -119,9 +119,10 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // Iteration counters val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val skip_rows_cnt = RegInit(0.U(log2Up(DIM + 1).W)) // OS mode: count COMPUTE resp rows to discard val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) - val req_sent = RegInit(false.B) // whether mesh.io.req has fired for this matmul + val req_sent = RegInit(false.B) // whether mesh.io.req has fired for this matmul // Sub-command from special field (live wire, only valid when cmdReq is valid) val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) @@ -133,8 +134,11 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { rdQueue1.io.enq <> io.bankReadResp(1) // Output buffer: collect mesh responses row by row - val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, outputType)))) - val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) + val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, outputType)))) + val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) + // OS mode: mesh outputs C rows in REVERSE order (last tile row first). + // outBufCollected counts how many resp rows have been collected (0..total_rows) + val outBufCollected = RegInit(0.U(log2Up(DIM + 1).W)) // Per-port write completion tracking for sStore val port_written = RegInit(VecInit(Seq.fill(outBW)(false.B))) @@ -217,11 +221,13 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { req_sent := false.B state := sPreloadRead }.elsewhen(sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED) { - read_row_cnt := 0.U - feed_row_cnt := 0.U - outBufRows := 0.U - req_sent := false.B - state := sComputeRead + read_row_cnt := 0.U + feed_row_cnt := 0.U + skip_rows_cnt := 0.U + outBufRows := 0.U + outBufCollected := 0.U + req_sent := false.B + state := sComputeRead }.elsewhen(sub_cmd === GemminiSubCmd.FLUSH) { state := sFlush } @@ -229,10 +235,15 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { } // ----------------------------------------------------------------------- - // PRELOAD_READ: read D/B matrix from SRAM bank into rdQueue - // Address starts from 0 (beginning of the bank allocation) + // PRELOAD_READ: read A matrix (OS mode) or B/D weights (WS mode) from SRAM + // OS mode: read A from op1_bank into rdQueue0, then send A through transposer + // in sPreloadFeed to pre-fill the AlwaysOutTransposer for later use + // in COMPUTE. The transposer accumulates A during PRELOAD, then + // naturally outputs A rows during COMPUTE (after dir switch). + // WS mode: read weights (B/D) from op1_bank into rdQueue0 // ----------------------------------------------------------------------- is(sPreloadRead) { + // Both OS and WS: read op1_bank (A for OS, B/D for WS) when(read_row_cnt < total_rows) { io.bankReadReq(0).valid := true.B io.bankReadReq(0).bits.addr := read_row_cnt @@ -245,9 +256,13 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { } // ----------------------------------------------------------------------- - // PRELOAD_FEED: send req to mesh, then feed D/B data row by row - // For OS mode: preload bias/D into mesh via d input, a=0, b=0 - // For WS mode: preload weights via b input, a=0, d=0 + // PRELOAD_FEED: send req to mesh, then feed data row by row + // For OS mode: preload A through transposer (a=A, b=0, d=0); propagate=1 + // in_prop XOR: 0 XOR 1 = 1 → PE prop=1 (PROPAGATE): c1=d=0, outputs old c1 + // After DIM rows of A, AlwaysOutTransposer dir flips; during COMPUTE, + // transposer outputs the A rows (as needed by systolic array). + // For WS mode: preload weights via b input (a=0, b=B, d=0); propagate=0 + // in_prop XOR: 0 XOR 0 = 0 → PE prop=0 (COMPUTE): c1 stays, b accumulated // ----------------------------------------------------------------------- is(sPreloadFeed) { // Step 1: fire mesh.io.req (once) @@ -270,25 +285,25 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { when(req_sent && feed_row_cnt < total_rows) { when(rdQueue0.io.deq.valid) { val row_data = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - - // a = 0 always for preload - mesh.io.a.valid := true.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS: preload accumulator via d input + // OS mode: feed A matrix through mesh.io.a → AlwaysOutTransposer + // This pre-fills the transposer (DIM rows → dir flips to UP mode) + // During COMPUTE, transposer outputs A rows from the top + mesh.io.a.valid := true.B + mesh.io.a.bits := VecInit(row_data.grouped(config.tileRows).map(g => VecInit(g)).toSeq) mesh.io.b.valid := true.B mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) mesh.io.d.valid := true.B - mesh.io.d.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) }.otherwise { - // WS: preload weights via b input + // WS mode: preload weights via b input + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) mesh.io.b.valid := true.B mesh.io.b.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) mesh.io.d.valid := true.B mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) } - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { rdQueue0.io.deq.ready := true.B feed_row_cnt := feed_row_cnt + 1.U @@ -306,40 +321,71 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { } // ----------------------------------------------------------------------- - // COMPUTE_READ: read A (port 0) and B/D (port 1) from SRAM banks - // Both start from address 0 + // COMPUTE_READ: read operands from SRAM banks + // OS mode: only read B matrix from op2_bank (port 1) + // A matrix was already sent to transposer during PRELOAD + // WS mode: read A from op1_bank (port 0) and D from op2_bank (port 1) // ----------------------------------------------------------------------- is(sComputeRead) { - when(read_row_cnt < total_rows) { - io.bankReadReq(0).valid := true.B - io.bankReadReq(0).bits.addr := read_row_cnt - io.bankReadReq(1).valid := true.B - io.bankReadReq(1).bits.addr := read_row_cnt - - when(io.bankReadReq(0).ready && io.bankReadReq(1).ready) { - read_row_cnt := read_row_cnt + 1.U + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS mode: only read B from op2_bank + when(read_row_cnt < total_rows) { + io.bankReadReq(1).valid := true.B + io.bankReadReq(1).bits.addr := read_row_cnt + when(io.bankReadReq(1).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sComputeFeed } }.otherwise { - state := sComputeFeed + // WS mode: read A from op1_bank (port 0) and D from op2_bank (port 1) + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := read_row_cnt + io.bankReadReq(1).valid := true.B + io.bankReadReq(1).bits.addr := read_row_cnt + + when(io.bankReadReq(0).ready && io.bankReadReq(1).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sComputeFeed + } } } // ----------------------------------------------------------------------- // COMPUTE_FEED: send req to mesh, then feed A and B/D row by row - // Collect mesh responses in parallel + // OS mode: propagate=1 → in_prop XOR: 1 XOR 1 = 0 → PE prop=0 (COMPUTE) + // PE accumulates A*B into c1, outputs c2 (old/zero, discarded) + // A comes from AlwaysOutTransposer (pre-filled during PRELOAD); send a=0 + // B comes from rdQueue1 (op2_bank) + // WS mode: propagate=1 → in_prop XOR: 0 XOR 1 = 1 → PE prop=1 (PROPAGATE) + // PE outputs c1 (weights * activations), b passes through + // A comes from rdQueue0 (op1_bank), D from rdQueue1 (op2_bank) // ----------------------------------------------------------------------- is(sComputeFeed) { - // Always collect mesh output when valid + // Collect/skip mesh output: + // WS mode: outputs A*B here (collect) + // OS mode: outputs c2=0 (garbage, discard but count for synchronization) when(mesh.io.resp.valid) { - outBuf(outBufRows) := mesh.io.resp.bits.data - outBufRows := outBufRows + 1.U + when(cfg_dataflow =/= Dataflow.OS.id.U) { + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows + 1.U + }.otherwise { + // OS mode: discard COMPUTE response (c2=0), just count + skip_rows_cnt := skip_rows_cnt + 1.U + } } // Step 1: fire mesh.io.req (once) when(!req_sent) { mesh.io.req.valid := true.B mesh.io.req.bits.pe_control.dataflow := cfg_dataflow - mesh.io.req.bits.pe_control.propagate := cfg_dataflow // OS: propagate=0, WS: propagate=1 for compute + // OS: propagate=1 → in_prop XOR: 1→0, PE prop=0 (COMPUTE), c1 accumulates A*B + // WS: propagate=1 → in_prop XOR: 0→1, PE prop=1 (PROPAGATE), outputs accumulated c1 + mesh.io.req.bits.pe_control.propagate := 1.U mesh.io.req.bits.pe_control.shift := cfg_in_shift mesh.io.req.bits.a_transpose := cfg_a_transpose mesh.io.req.bits.bd_transpose := cfg_b_transpose @@ -353,36 +399,113 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // Step 2: feed data rows (only after req has fired) when(req_sent && feed_row_cnt < total_rows) { - when(rdQueue0.io.deq.valid && rdQueue1.io.deq.valid) { - val a_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - val bd_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - - mesh.io.a.valid := true.B - mesh.io.a.bits := VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) - - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS: b carries multiply operand, d = 0 (accumulator already preloaded) + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS mode: A from transposer (pre-filled during PRELOAD); send a=0 to mesh.io.a + // B from rdQueue1 (op2_bank) + when(rdQueue1.io.deq.valid) { + val b_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + // a=0: transposer already outputs A rows (accumulated during PRELOAD phase dir=LEFT) + // After PRELOAD's DIM rows, transposer dir flips to UP, outputting A rows + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) // a=0: let transposer output PRELOAD A mesh.io.b.valid := true.B - mesh.io.b.bits := VecInit(bd_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.b.bits := VecInit(b_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - }.otherwise { + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) // d=0: don't overwrite c1 + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue1.io.deq.ready := true.B + feed_row_cnt := feed_row_cnt + 1.U + } + } + }.otherwise { + // WS mode: A from rdQueue0 (op1_bank), D from rdQueue1 (op2_bank) + when(rdQueue0.io.deq.valid && rdQueue1.io.deq.valid) { + val a_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val bd_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + + mesh.io.a.valid := true.B + mesh.io.a.bits := VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) // WS: d carries input activations, b = 0 mesh.io.b.valid := true.B mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) mesh.io.d.valid := true.B mesh.io.d.bits := VecInit(bd_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := true.B + rdQueue1.io.deq.ready := true.B + feed_row_cnt := feed_row_cnt + 1.U + } } + } + } - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { - rdQueue0.io.deq.ready := true.B - rdQueue1.io.deq.ready := true.B - feed_row_cnt := feed_row_cnt + 1.U + // Step 3: all rows fed; OS mode waits until COMPUTE responses are discarded + when(req_sent && feed_row_cnt >= total_rows) { + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS mode: wait until all COMPUTE resp (c2=0) have been counted/discarded + // skip_rows_cnt is incremented whenever resp.valid is true (above) + when(skip_rows_cnt >= total_rows) { + // OS mode: mesh outputs C rows in REVERSE order (last tile row first). + // Initialize outBufRows to total_rows-1 so first resp → outBuf[total_rows-1], + // last resp → outBuf[0], reversing back to correct row order. + outBufRows := total_rows - 1.U + outBufCollected := 0.U + req_sent := false.B + state := sComputeFlush } + }.otherwise { + // WS: output already collected during feed + state := sDrain + } + } + } + + // ----------------------------------------------------------------------- + // COMPUTE_FLUSH (OS mode only): issue flush req with propagate=1 + // in_prop XOR: 0 XOR 1 = 1 → PE prop=1 (PROPAGATE) → outputs c1 (A*B result) + // Feed zeros to advance rows through the pipeline + // ----------------------------------------------------------------------- + is(sComputeFlush) { + // Collect mesh output (this is the real A*B result from c1) + // OS PROPAGATE outputs rows in reverse: last tile row first, first tile row last. + // Count down outBufRows so outBuf[total_rows-1] = first resp, outBuf[0] = last resp. + when(mesh.io.resp.valid) { + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows - 1.U + outBufCollected := outBufCollected + 1.U + } + + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U // XOR: 0→1, PE prop=1, outputs c1 + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := cfg_a_transpose + mesh.io.req.bits.bd_transpose := cfg_b_transpose + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := rob_id_reg + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + feed_row_cnt := 0.U + } + } + + // Feed zeros to advance pipeline + when(req_sent && feed_row_cnt < total_rows) { + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + feed_row_cnt := feed_row_cnt + 1.U } } - // Step 3: all rows fed → wait for all mesh responses + // All flush rows fed → proceed to drain to collect any remaining responses when(req_sent && feed_row_cnt >= total_rows) { state := sDrain } @@ -393,13 +516,29 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------- is(sDrain) { when(mesh.io.resp.valid) { - outBuf(outBufRows) := mesh.io.resp.bits.data - outBufRows := outBufRows + 1.U + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS mode: continue reverse collection + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows - 1.U + outBufCollected := outBufCollected + 1.U + }.otherwise { + // WS mode: forward collection + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows + 1.U + } } - when(outBufRows >= total_rows) { - store_row_cnt := 0.U - port_written.foreach(_ := false.B) - state := sStore + when(cfg_dataflow === Dataflow.OS.id.U) { + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + }.otherwise { + when(outBufRows >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmd.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmd.scala new file mode 100644 index 00000000..e4076235 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmd.scala @@ -0,0 +1,74 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig + +object LoopSubCmdType { + val MSET_ALLOC = 0.U(3.W) + val MSET_FREE = 1.U(3.W) + val MVIN = 2.U(3.W) + val MVOUT = 3.U(3.W) + val PRELOAD = 4.U(3.W) + val COMPUTE = 5.U(3.W) +} + +class LoopSubCmd(val b: GlobalConfig) extends Bundle { + val cmdType = UInt(3.W) + val bank_id = UInt(log2Up(b.memDomain.bankNum).W) + val dram_addr = UInt(b.memDomain.memAddrLen.W) + val iter = UInt(b.frontend.iter_len.W) + val bank_row = UInt(5.W) + val bank_col = UInt(5.W) + val op1_bank = UInt(log2Up(b.memDomain.bankNum).W) + val op2_bank = UInt(log2Up(b.memDomain.bankNum).W) + val wr_bank = UInt(log2Up(b.memDomain.bankNum).W) + val compute_mode = UInt(2.W) +} + +class LoopCmd(val b: GlobalConfig) extends Bundle { + val slots = Vec(4, Valid(new LoopSubCmd(b))) +} + +class LoopWsConfig(val b: GlobalConfig) extends Bundle { + val max_i = UInt(16.W) + val max_j = UInt(16.W) + val max_k = UInt(16.W) + val dram_addr_a = UInt(b.memDomain.memAddrLen.W) + val dram_addr_b = UInt(b.memDomain.memAddrLen.W) + val dram_addr_d = UInt(b.memDomain.memAddrLen.W) + val dram_addr_c = UInt(b.memDomain.memAddrLen.W) + val stride_a = UInt(32.W) + val stride_b = UInt(32.W) + val stride_d = UInt(32.W) + val stride_c = UInt(32.W) + val bank_a = UInt(log2Up(b.memDomain.bankNum).W) + val bank_b = UInt(log2Up(b.memDomain.bankNum).W) + val bank_c = UInt(log2Up(b.memDomain.bankNum).W) + val low_d = Bool() +} + +class LoopConvWsConfig(val b: GlobalConfig) extends Bundle { + val batch_size = UInt(16.W) + val in_dim = UInt(16.W) + val in_channels = UInt(16.W) + val out_channels = UInt(16.W) + val out_dim = UInt(16.W) + val stride = UInt(8.W) + val padding = UInt(8.W) + val kernel_dim = UInt(8.W) + val pool_size = UInt(8.W) + val pool_stride = UInt(8.W) + val pool_padding = UInt(8.W) + val dram_addr_bias = UInt(b.memDomain.memAddrLen.W) + val dram_addr_input = UInt(b.memDomain.memAddrLen.W) + val dram_addr_weight = UInt(b.memDomain.memAddrLen.W) + val dram_addr_output = UInt(b.memDomain.memAddrLen.W) + val input_stride = UInt(32.W) + val weight_stride = UInt(32.W) + val output_stride = UInt(32.W) + val bank_input = UInt(log2Up(b.memDomain.bankNum).W) + val bank_weight = UInt(log2Up(b.memDomain.bankNum).W) + val bank_output = UInt(log2Up(b.memDomain.bankNum).W) + val no_bias = Bool() +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala new file mode 100644 index 00000000..077a5558 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala @@ -0,0 +1,125 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.blink.SubRobRow +import framework.frontend.decoder.PostGDCmd +import framework.frontend.scoreboard.BankAccessInfo +import framework.frontend.decoder.DomainId + +/** Converts LoopCmd (logical) → SubRobRow (hardware PostGDCmd) for SubROB. */ +@instantiable +class LoopCmdEncoder(val b: GlobalConfig) extends Module { + val bankIdLen = log2Up(b.memDomain.bankNum) + + @public + val io = IO(new Bundle { + val cmd = Flipped(Decoupled(new LoopCmd(b))) + val subRobRow = Decoupled(new SubRobRow(b)) + val ballId = Input(UInt(log2Up(b.ballDomain.ballNum).W)) + val masterRobId = Input(UInt(log2Up(b.frontend.rob_entries).W)) + }) + + // Passthrough handshake + io.subRobRow.valid := io.cmd.valid + io.cmd.ready := io.subRobRow.ready + + io.subRobRow.bits.ball_id := io.ballId + io.subRobRow.bits.master_rob_id := io.masterRobId + + for (i <- 0 until 4) { + val slot = io.subRobRow.bits.slots(i) + val lsub = io.cmd.bits.slots(i) + slot.valid := lsub.valid + + // Defaults — all unused RoCCCommandBB fields zero + slot.cmd.domain_id := 0.U + slot.cmd.cmd.raw_inst := 0.U + slot.cmd.cmd.funct := 0.U + slot.cmd.cmd.funct3 := 0.U + slot.cmd.cmd.rs2 := 0.U + slot.cmd.cmd.rs1 := 0.U + slot.cmd.cmd.xd := false.B + slot.cmd.cmd.xs1 := false.B + slot.cmd.cmd.xs2 := false.B + slot.cmd.cmd.rd := 0.U + slot.cmd.cmd.opcode := 0.U + slot.cmd.cmd.rs1Data := 0.U + slot.cmd.cmd.rs2Data := 0.U + slot.cmd.bankAccess := BankAccessInfo.none(bankIdLen) + slot.cmd.isFence := false.B + slot.cmd.isBarrier := false.B + + when(lsub.valid) { + switch(lsub.bits.cmdType) { + is(LoopSubCmdType.MSET_ALLOC) { + slot.cmd.domain_id := DomainId.MEM + slot.cmd.cmd.funct := 0x20.U // MSET (enable=010, opcode=0) + slot.cmd.cmd.rs1Data := lsub.bits.bank_id + slot.cmd.cmd.rs2Data := lsub.bits.bank_row.asUInt | + (lsub.bits.bank_col.asUInt << 5) | + (1.U << 10) // alloc=1 + slot.cmd.bankAccess.wr_bank_valid := true.B + slot.cmd.bankAccess.wr_bank_id := lsub.bits.bank_id + } + is(LoopSubCmdType.MSET_FREE) { + slot.cmd.domain_id := DomainId.MEM + slot.cmd.cmd.funct := 0x20.U // MSET + slot.cmd.cmd.rs1Data := lsub.bits.bank_id + slot.cmd.cmd.rs2Data := 0.U // alloc=0 + slot.cmd.bankAccess.wr_bank_valid := true.B + slot.cmd.bankAccess.wr_bank_id := lsub.bits.bank_id + } + is(LoopSubCmdType.MVIN) { + slot.cmd.domain_id := DomainId.MEM + slot.cmd.cmd.funct := 0x21.U // MVIN (enable=010, opcode=1) + slot.cmd.cmd.rs1Data := lsub.bits.bank_id | (lsub.bits.iter << 30) + slot.cmd.cmd.rs2Data := lsub.bits.dram_addr + slot.cmd.bankAccess.wr_bank_valid := true.B + slot.cmd.bankAccess.wr_bank_id := lsub.bits.bank_id + } + is(LoopSubCmdType.MVOUT) { + slot.cmd.domain_id := DomainId.MEM + slot.cmd.cmd.funct := 0x10.U // MVOUT (enable=001, opcode=0) + slot.cmd.cmd.rs1Data := lsub.bits.bank_id | (lsub.bits.iter << 30) + slot.cmd.cmd.rs2Data := lsub.bits.dram_addr + slot.cmd.bankAccess.rd_bank_0_valid := true.B + slot.cmd.bankAccess.rd_bank_0_id := lsub.bits.bank_id + } + is(LoopSubCmdType.PRELOAD) { + slot.cmd.domain_id := DomainId.BALL + slot.cmd.cmd.funct := 0x35.U // GEMMINI_PRELOAD (enable=011, opcode=5) + slot.cmd.cmd.rs1Data := lsub.bits.op1_bank | + (lsub.bits.wr_bank << 20) | + (lsub.bits.iter << 30) + slot.cmd.cmd.rs2Data := 0.U + slot.cmd.bankAccess.rd_bank_0_valid := true.B + slot.cmd.bankAccess.rd_bank_0_id := lsub.bits.op1_bank + slot.cmd.bankAccess.wr_bank_valid := true.B + slot.cmd.bankAccess.wr_bank_id := lsub.bits.wr_bank + } + is(LoopSubCmdType.COMPUTE) { + slot.cmd.domain_id := DomainId.BALL + slot.cmd.cmd.funct := Mux( + lsub.bits.compute_mode === 0.U, + 0x42.U, // COMPUTE_PRELOADED (enable=100, opcode=2) + 0x43.U // COMPUTE_ACCUMULATED (enable=100, opcode=3) + ) + slot.cmd.cmd.rs1Data := lsub.bits.op1_bank | + (lsub.bits.op2_bank << 10) | + (lsub.bits.wr_bank << 20) | + (lsub.bits.iter << 30) + slot.cmd.cmd.rs2Data := 0.U + slot.cmd.bankAccess.rd_bank_0_valid := true.B + slot.cmd.bankAccess.rd_bank_0_id := lsub.bits.op1_bank + slot.cmd.bankAccess.rd_bank_1_valid := true.B + slot.cmd.bankAccess.rd_bank_1_id := lsub.bits.op2_bank + slot.cmd.bankAccess.wr_bank_valid := true.B + slot.cmd.bankAccess.wr_bank_id := lsub.bits.wr_bank + } + } + } + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvAddrGen.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvAddrGen.scala new file mode 100644 index 00000000..209522e8 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvAddrGen.scala @@ -0,0 +1,77 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.prototype.gemmini.configs.GemminiBallParam + +/** + * LoopConvAddrGen — combinational im2col address computation. + * + * Given loop indices and conv config, computes: + * - Input DRAM address (with padding detection) + * - Weight DRAM address + * - Output DRAM address + * - Bias DRAM address + */ +@instantiable +class LoopConvAddrGen(val b: GlobalConfig) extends Module { + val config = GemminiBallParam() + val DIM = config.blockSize + val elemSize = config.inputWidth / 8 + val accBytes = config.accWidth / 8 + + @public + val io = IO(new Bundle { + // Conv config + val cfg = Input(new LoopConvWsConfig(b)) + // Loop indices + val batch = Input(UInt(16.W)) + val orow = Input(UInt(16.W)) + val ocol = Input(UInt(16.W)) + val och = Input(UInt(16.W)) + val krow = Input(UInt(16.W)) + val kcol = Input(UInt(16.W)) + val kch = Input(UInt(16.W)) + // Outputs + val inputAddr = Output(UInt(b.memDomain.memAddrLen.W)) + val weightAddr = Output(UInt(b.memDomain.memAddrLen.W)) + val outputAddr = Output(UInt(b.memDomain.memAddrLen.W)) + val biasAddr = Output(UInt(b.memDomain.memAddrLen.W)) + val isPadding = Output(Bool()) + }) + + val cfg = io.cfg + + // im2col: irow = orow * stride + krow - padding + val irow = (io.orow * cfg.stride).asSInt + io.krow.asSInt - cfg.padding.asSInt + val icol = (io.ocol * cfg.stride).asSInt + io.kcol.asSInt - cfg.padding.asSInt + + // Padding detection + io.isPadding := irow < 0.S || irow >= cfg.in_dim.asSInt || + icol < 0.S || icol >= cfg.in_dim.asSInt + + // Input address: base + ((batch * in_dim * in_dim + irow * in_dim + icol) * in_channels + kch) * elemSize + val inputOffset = + (io.batch * cfg.in_dim * cfg.in_dim + + irow.asUInt * cfg.in_dim + icol.asUInt) * cfg.in_channels + io.kch + + io.inputAddr := cfg.dram_addr_input + inputOffset * elemSize.U + + // Weight address: base + ((krow * kernel_dim + kcol) * in_channels + kch) * out_channels * elemSize + // + och * elemSize + val weightOffset = ((io.krow * cfg.kernel_dim + io.kcol) * cfg.in_channels + io.kch) * + cfg.out_channels + io.och + io.weightAddr := cfg.dram_addr_weight + weightOffset * elemSize.U + + // Output address: base + ((batch * out_dim * out_dim + orow * out_dim + ocol) * out_channels + och) * accBytes + val outputOffset = + (io.batch * cfg.out_dim * cfg.out_dim + + io.orow * cfg.out_dim + io.ocol) * cfg.out_channels + io.och + + io.outputAddr := cfg.dram_addr_output + outputOffset * accBytes.U + + // Bias address: base + och * accBytes + io.biasAddr := cfg.dram_addr_bias + io.och * accBytes.U +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvUnroller.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvUnroller.scala new file mode 100644 index 00000000..a16a3265 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopConvUnroller.scala @@ -0,0 +1,256 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.balldomain.prototype.gemmini.configs.GemminiBallParam + +/** + * LoopConvUnroller — expands LOOP_CONV_WS into LoopCmd rows. + * + * Simplified iteration: + * batch → orow → ocol → och → krow → kcol → kch (innermost) + * + * Each (orow, ocol, och, krow, kcol, kch) tile generates: + * MVIN input + MVIN weight → PRELOAD + COMPUTE → (on last k-iter) MVOUT + * + * First implementation: no pooling, no im2col tiling, single DIM×DIM tiles. + */ +@instantiable +class LoopConvUnroller(val b: GlobalConfig) extends Module { + val config = GemminiBallParam() + val DIM = config.blockSize + val elemSize = config.inputWidth / 8 + val accBytes = config.accWidth / 8 + + @public + val io = IO(new Bundle { + val start = Flipped(Decoupled(new LoopConvWsConfig(b))) + val cmd = Decoupled(new LoopCmd(b)) + val busy = Output(Bool()) + }) + + val addrGen: Instance[LoopConvAddrGen] = Instantiate(new LoopConvAddrGen(b)) + + // FSM states + val sIdle :: sAlloc :: sMvinInput :: sMvinWeight :: sCompute :: sMvout :: sFree :: sDone :: Nil = Enum(8) + val state = RegInit(sIdle) + + val cfg = Reg(new LoopConvWsConfig(b)) + + // Iterator registers + val batch_reg = RegInit(0.U(16.W)) + val orow_reg = RegInit(0.U(16.W)) + val ocol_reg = RegInit(0.U(16.W)) + val och_reg = RegInit(0.U(16.W)) + val krow_reg = RegInit(0.U(16.W)) + val kcol_reg = RegInit(0.U(16.W)) + val kch_reg = RegInit(0.U(16.W)) + + // Is this the first k-iteration for this (orow, ocol, och)? + val isFirstK = krow_reg === 0.U && kcol_reg === 0.U && kch_reg === 0.U + + // Is this the last k-iteration? + val isLastK = (krow_reg === cfg.kernel_dim - 1.U) && + (kcol_reg === cfg.kernel_dim - 1.U) && + (kch_reg + DIM.U >= cfg.in_channels) // Tile boundary + + // Connect address generator + addrGen.io.cfg := cfg + addrGen.io.batch := batch_reg + addrGen.io.orow := orow_reg + addrGen.io.ocol := ocol_reg + addrGen.io.och := och_reg + addrGen.io.krow := krow_reg + addrGen.io.kcol := kcol_reg + addrGen.io.kch := kch_reg + + // Defaults + io.start.ready := state === sIdle + io.cmd.valid := false.B + io.cmd.bits := 0.U.asTypeOf(new LoopCmd(b)) + io.busy := state =/= sIdle + + def emptySlot(): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := false.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v + } + + def msetSlot( + bankId: UInt, + alloc: Boolean, + row: Int, + col: Int + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := (if (alloc) LoopSubCmdType.MSET_ALLOC else LoopSubCmdType.MSET_FREE) + v.bits.bank_id := bankId + v.bits.bank_row := row.U + v.bits.bank_col := col.U + v + } + + def mvinSlot(bankId: UInt, addr: UInt): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVIN + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.iter := DIM.U + v + } + + // Advance k-iterators (kch → kcol → krow), then output iterators (och → ocol → orow → batch) + def advanceIter(): Unit = { + when(kch_reg + DIM.U < cfg.in_channels) { + kch_reg := kch_reg + DIM.U + }.elsewhen(kcol_reg + 1.U < cfg.kernel_dim) { + kch_reg := 0.U; kcol_reg := kcol_reg + 1.U + }.elsewhen(krow_reg + 1.U < cfg.kernel_dim) { + kch_reg := 0.U; kcol_reg := 0.U; krow_reg := krow_reg + 1.U + }.elsewhen(och_reg + DIM.U < cfg.out_channels) { + kch_reg := 0.U; kcol_reg := 0.U; krow_reg := 0.U; och_reg := och_reg + DIM.U + }.elsewhen(ocol_reg + 1.U < cfg.out_dim) { + kch_reg := 0.U; kcol_reg := 0.U; krow_reg := 0.U; och_reg := 0.U + ocol_reg := ocol_reg + 1.U + }.elsewhen(orow_reg + 1.U < cfg.out_dim) { + kch_reg := 0.U; kcol_reg := 0.U; krow_reg := 0.U; och_reg := 0.U; ocol_reg := 0.U + orow_reg := orow_reg + 1.U + }.elsewhen(batch_reg + 1.U < cfg.batch_size) { + kch_reg := 0.U; kcol_reg := 0.U; krow_reg := 0.U; och_reg := 0.U; ocol_reg := 0.U; orow_reg := 0.U + batch_reg := batch_reg + 1.U + }.otherwise { + state := sFree // All iterations done + } + } + + // Track whether all iterations are done (used to decide next state) + val allDone = (batch_reg === cfg.batch_size - 1.U) && + (orow_reg === cfg.out_dim - 1.U) && (ocol_reg === cfg.out_dim - 1.U) && + (och_reg + DIM.U >= cfg.out_channels) && isLastK + + switch(state) { + is(sIdle) { + io.start.ready := true.B + when(io.start.fire) { + cfg := io.start.bits + batch_reg := 0.U; orow_reg := 0.U; ocol_reg := 0.U; och_reg := 0.U + krow_reg := 0.U; kcol_reg := 0.U; kch_reg := 0.U + state := sAlloc + } + } + + // [MSET_alloc(input), MSET_alloc(weight), MSET_alloc(output), --] + is(sAlloc) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := msetSlot(cfg.bank_input, alloc = true, row = 1, col = 1) + io.cmd.bits.slots(1) := msetSlot(cfg.bank_weight, alloc = true, row = 1, col = 1) + io.cmd.bits.slots(2) := msetSlot(cfg.bank_output, alloc = true, row = 1, col = 4) + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sMvinInput + } + } + + // [MVIN_input, MVIN_weight, --, --] + is(sMvinInput) { + io.cmd.valid := true.B + val inputSlot = Mux( + addrGen.io.isPadding, + emptySlot(), // Skip MVIN if padding (load zeros implicitly) + mvinSlot(cfg.bank_input, addrGen.io.inputAddr) + ) + io.cmd.bits.slots(0) := inputSlot + io.cmd.bits.slots(1) := mvinSlot(cfg.bank_weight, addrGen.io.weightAddr) + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sCompute + } + } + + // [PRELOAD, COMPUTE, --, --] + is(sCompute) { + io.cmd.valid := true.B + val preSlot = Wire(Valid(new LoopSubCmd(b))) + preSlot.valid := true.B + preSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + preSlot.bits.cmdType := LoopSubCmdType.PRELOAD + preSlot.bits.op1_bank := cfg.bank_weight + preSlot.bits.wr_bank := cfg.bank_output + preSlot.bits.iter := DIM.U + + val compSlot = Wire(Valid(new LoopSubCmd(b))) + compSlot.valid := true.B + compSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + compSlot.bits.cmdType := LoopSubCmdType.COMPUTE + compSlot.bits.op1_bank := cfg.bank_weight + compSlot.bits.op2_bank := cfg.bank_input + compSlot.bits.wr_bank := cfg.bank_output + compSlot.bits.compute_mode := Mux(isFirstK, 0.U, 1.U) // PRELOADED first, then ACCUMULATED + compSlot.bits.iter := DIM.U + + io.cmd.bits.slots(0) := preSlot + io.cmd.bits.slots(1) := compSlot + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + when(isLastK) { + state := sMvout // Need to output results after last k iteration + }.otherwise { + advanceIter() + when(state =/= sFree)(state := sMvinInput) + } + } + } + + // [MVOUT, --, --, --] + is(sMvout) { + io.cmd.valid := true.B + val mvSlot = Wire(Valid(new LoopSubCmd(b))) + mvSlot.valid := true.B + mvSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + mvSlot.bits.cmdType := LoopSubCmdType.MVOUT + mvSlot.bits.bank_id := cfg.bank_output + mvSlot.bits.dram_addr := addrGen.io.outputAddr + mvSlot.bits.iter := DIM.U + + io.cmd.bits.slots(0) := mvSlot + io.cmd.bits.slots(1) := emptySlot() + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + when(allDone) { + state := sFree + }.otherwise { + advanceIter() + when(state =/= sFree)(state := sMvinInput) + } + } + } + + // [MSET_free(input), MSET_free(weight), MSET_free(output), --] + is(sFree) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := msetSlot(cfg.bank_input, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(1) := msetSlot(cfg.bank_weight, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(2) := msetSlot(cfg.bank_output, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sDone + } + } + + is(sDone) { + state := sIdle + } + } +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopMatmulUnroller.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopMatmulUnroller.scala new file mode 100644 index 00000000..453dd074 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopMatmulUnroller.scala @@ -0,0 +1,262 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.prototype.gemmini.configs.GemminiBallParam + +/** + * LoopMatmulUnroller — expands LOOP_WS into a stream of LoopCmd rows. + * + * FSM: sIdle → sAllocBanks → sPrimeLoad → sMainLoop (Row1/Row2) → sDrainLast → sFreeBanks → sDone + * + * Row layout per iteration: + * Row 1: [PRELOAD(cur), COMPUTE(cur)] + * Row 2: [MVOUT(cur), MVIN_A(next), MVIN_B(next)] + * Last iteration: only Row 1, then sDrainLast handles final MVOUT. + */ +@instantiable +class LoopMatmulUnroller(val b: GlobalConfig) extends Module { + val config = GemminiBallParam() + val DIM = config.blockSize + val elemSize = config.inputWidth / 8 + val accBytes = config.accWidth / 8 + val bankIdLen = log2Up(b.memDomain.bankNum) + + @public + val io = IO(new Bundle { + val start = Flipped(Decoupled(new LoopWsConfig(b))) + val cmd = Decoupled(new LoopCmd(b)) + val busy = Output(Bool()) + }) + + // FSM states + val sIdle :: sAllocBanks :: sPrimeLoad :: sMainRow1 :: sMainRow2 :: sDrainLast :: sFreeBanks :: sDone :: Nil = + Enum(8) + val state = RegInit(sIdle) + + // Config registers (latched at start) + val cfg = Reg(new LoopWsConfig(b)) + + // Loop iterator registers + val i_reg = RegInit(0.U(16.W)) + val j_reg = RegInit(0.U(16.W)) + val k_reg = RegInit(0.U(16.W)) + + // Total iterations and current iteration index + val totalIter = cfg.max_i * cfg.max_j * cfg.max_k + val curIter = RegInit(0.U(32.W)) + + // Whether this is the last iteration + val isLastIter = curIter === (totalIter - 1.U) + + // Defaults + io.start.ready := state === sIdle + io.cmd.valid := false.B + io.cmd.bits := 0.U.asTypeOf(new LoopCmd(b)) + io.busy := state =/= sIdle + + // Helper to build an invalid LoopSubCmd slot + def emptySlot(): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := false.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v + } + + // Helper to build an MSET slot + def msetSlot( + bankId: UInt, + alloc: Boolean, + row: Int, + col: Int + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := (if (alloc) LoopSubCmdType.MSET_ALLOC else LoopSubCmdType.MSET_FREE) + v.bits.bank_id := bankId + v.bits.bank_row := row.U + v.bits.bank_col := col.U + v + } + + // Helper to build an MVIN slot + def mvinSlot(bankId: UInt, addr: UInt, iter: UInt): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVIN + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.iter := iter + v + } + + // Helper to build an MVOUT slot + def mvoutSlot(bankId: UInt, addr: UInt, iter: UInt): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVOUT + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.iter := iter + v + } + + // Address computation + // addr_a(i,k) = dram_addr_a + i * stride_a + k * DIM * elemSize + // addr_b(k,j) = dram_addr_b + k * stride_b + j * DIM * elemSize + // addr_c(i,j) = dram_addr_c + i * stride_c + j * DIM * accBytes + def addrA(i: UInt, k: UInt): UInt = + cfg.dram_addr_a + i * cfg.stride_a + k * (DIM * elemSize).U + + def addrB(k: UInt, j: UInt): UInt = + cfg.dram_addr_b + k * cfg.stride_b + j * (DIM * elemSize).U + + def addrC(i: UInt, j: UInt): UInt = + cfg.dram_addr_c + i * cfg.stride_c + j * (DIM * accBytes).U + + // Next iterator values (advance k, then j, then i) + val next_k = Wire(UInt(16.W)) + val next_j = Wire(UInt(16.W)) + val next_i = Wire(UInt(16.W)) + + when(k_reg + 1.U < cfg.max_k) { + next_k := k_reg + 1.U + next_j := j_reg + next_i := i_reg + }.elsewhen(j_reg + 1.U < cfg.max_j) { + next_k := 0.U + next_j := j_reg + 1.U + next_i := i_reg + }.otherwise { + next_k := 0.U + next_j := 0.U + next_i := i_reg + 1.U + } + + // Compute mode: first k iteration uses PRELOADED (0), rest use ACCUMULATED (1) + val computeMode = Mux(k_reg === 0.U, 0.U(2.W), 1.U(2.W)) + + switch(state) { + is(sIdle) { + io.start.ready := true.B + when(io.start.fire) { + cfg := io.start.bits + i_reg := 0.U + j_reg := 0.U + k_reg := 0.U + curIter := 0.U + state := sAllocBanks + } + } + + // Row 0: [MSET_alloc(A), MSET_alloc(B), MSET_alloc(C), --] + is(sAllocBanks) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := msetSlot(cfg.bank_a, alloc = true, row = 1, col = 1) + io.cmd.bits.slots(1) := msetSlot(cfg.bank_b, alloc = true, row = 1, col = 1) + io.cmd.bits.slots(2) := msetSlot(cfg.bank_c, alloc = true, row = 1, col = 4) // accWidth = 4x inputWidth + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sPrimeLoad + } + } + + // Row 1: [MVIN_A(0), MVIN_B(0), --, --] + is(sPrimeLoad) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvinSlot(cfg.bank_a, addrA(0.U, 0.U), DIM.U) + io.cmd.bits.slots(1) := mvinSlot(cfg.bank_b, addrB(0.U, 0.U), DIM.U) + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sMainRow1 + } + } + + // Main loop Row 1: [PRELOAD(cur), COMPUTE(cur), --, --] + is(sMainRow1) { + io.cmd.valid := true.B + val preSlot = Wire(Valid(new LoopSubCmd(b))) + preSlot.valid := true.B + preSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + preSlot.bits.cmdType := LoopSubCmdType.PRELOAD + preSlot.bits.op1_bank := cfg.bank_a // preload A (activations) into systolic array + preSlot.bits.wr_bank := cfg.bank_c + preSlot.bits.iter := DIM.U + + val compSlot = Wire(Valid(new LoopSubCmd(b))) + compSlot.valid := true.B + compSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + compSlot.bits.cmdType := LoopSubCmdType.COMPUTE + compSlot.bits.op1_bank := cfg.bank_a + compSlot.bits.op2_bank := cfg.bank_b + compSlot.bits.wr_bank := cfg.bank_c + compSlot.bits.compute_mode := computeMode + compSlot.bits.iter := DIM.U + + io.cmd.bits.slots(0) := preSlot + io.cmd.bits.slots(1) := compSlot + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + when(isLastIter) { + state := sDrainLast // Skip Row 2 for last iteration + }.otherwise { + state := sMainRow2 + } + } + } + + // Main loop Row 2: [MVOUT(cur), MVIN_A(next), MVIN_B(next), --] + is(sMainRow2) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvoutSlot(cfg.bank_c, addrC(i_reg, j_reg), DIM.U) + io.cmd.bits.slots(1) := mvinSlot(cfg.bank_a, addrA(next_i, next_k), DIM.U) + io.cmd.bits.slots(2) := mvinSlot(cfg.bank_b, addrB(next_k, next_j), DIM.U) + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + // Advance iterators + i_reg := next_i + j_reg := next_j + k_reg := next_k + curIter := curIter + 1.U + state := sMainRow1 + } + } + + // Drain: emit final MVOUT for last iteration + is(sDrainLast) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvoutSlot(cfg.bank_c, addrC(i_reg, j_reg), DIM.U) + io.cmd.bits.slots(1) := emptySlot() + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sFreeBanks + } + } + + // Free: [MSET_free(A), MSET_free(B), MSET_free(C), --] + is(sFreeBanks) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := msetSlot(cfg.bank_a, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(1) := msetSlot(cfg.bank_b, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(2) := msetSlot(cfg.bank_c, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sDone + } + } + + is(sDone) { + state := sIdle + } + } +} diff --git a/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala b/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala index e17559d0..e969cfde 100644 --- a/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala +++ b/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala @@ -10,6 +10,7 @@ import freechips.rocketchip.rocket.HellaCacheIO class RoCCCommandBB(xLen: Int = 64) extends Bundle { val raw_inst = UInt(32.W) val funct = UInt(7.W) + val funct3 = UInt(3.W) val rs2 = Bits(5.W) val rs1 = Bits(5.W) val xd = Bool() diff --git a/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala index 6ce50bee..bbc02b9b 100644 --- a/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala @@ -1240,6 +1240,7 @@ class RocketBB(tile: BBTile)(implicit p: Parameters) io.rocc.cmd.bits.raw_inst := wb_reg_inst val inst_bits = wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.funct := inst_bits.funct + io.rocc.cmd.bits.funct3 := wb_reg_inst(14, 12) io.rocc.cmd.bits.rs2 := inst_bits.rs2 io.rocc.cmd.bits.rs1 := inst_bits.rs1 io.rocc.cmd.bits.xd := inst_bits.xd diff --git a/arch/src/main/scala/framework/frontend/configs/default.json b/arch/src/main/scala/framework/frontend/configs/default.json index f9c67882..f5df56ce 100644 --- a/arch/src/main/scala/framework/frontend/configs/default.json +++ b/arch/src/main/scala/framework/frontend/configs/default.json @@ -1,7 +1,7 @@ { "rob_entries": 16, "rs_out_of_order_response": true, - "bank_id_len": 15, - "iter_len": 16, + "bank_id_len": 10, + "iter_len": 34, "sub_rob_depth": 64 } diff --git a/arch/src/main/scala/framework/frontend/decoder/GISA.scala b/arch/src/main/scala/framework/frontend/decoder/GISA.scala index 7a4db238..ec0b1616 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GISA.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GISA.scala @@ -4,8 +4,9 @@ import chisel3._ import chisel3.util._ object GISA { - val FENCE_BITPAT = BitPat("b0011111") // 31 (0x1F) - val BARRIER_BITPAT = BitPat("b0110010") // 50 (0x32) + // enable=000, opcode group for no-bank-access instructions + val FENCE_BITPAT = BitPat("b0000000") // 0 (0x00) — enable=000, opcode=0 + val BARRIER_BITPAT = BitPat("b0000001") // 1 (0x01) — enable=000, opcode=1 } // Domain ID constants diff --git a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala index a574e9db..46cd70c2 100644 --- a/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala +++ b/arch/src/main/scala/framework/frontend/decoder/GobalDecoder.scala @@ -46,6 +46,7 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { io.id_i.ready := io.id_o.ready val func7 = io.id_i.bits.cmd.funct + val funct3 = io.id_i.bits.cmd.funct3 val opcode = io.id_i.bits.cmd.opcode val rs1 = io.id_i.bits.cmd.rs1Data @@ -76,27 +77,38 @@ class GlobalDecoder(val b: GlobalConfig) extends Module { ) // ------------------------------------------------------------------------- - // Bank access info extraction — read valid flags from rs1[45:47] + // Bank access info extraction — enable flags from funct7[6:4] // // Unified rs1 layout (defined in isa.h): - // rs1[14:0] = bank_0 (rd_bank_0 or wr_bank for MVIN/MSET) - // rs1[29:15] = bank_1 (rd_bank_1, dual-operand only) - // rs1[44:30] = bank_2 (wr_bank for Ball instructions) - // rs1[45] = rd_bank_0_valid flag (BB_RD0) - // rs1[46] = rd_bank_1_valid flag (BB_RD1) - // rs1[47] = wr_bank_valid flag (BB_WR) - // rs1[63:48] = iter (16-bit) + // rs1[9:0] = bank_0 (rd_bank_0 or wr_bank for MVIN/MSET) + // rs1[19:10] = bank_1 (rd_bank_1, dual-operand only) + // rs1[29:20] = bank_2 (wr_bank for Ball instructions) + // rs1[63:30] = iter (34-bit) + // + // funct7[6:4] enable encoding: + // 000 = no bank access + // 001 = 1 read (bank0) + // 010 = 1 write (bank2) + // 011 = 1 read + 1 write (bank0 read, bank2 write) + // 100 = 2 read + 1 write (bank0+bank1 read, bank2 write) + // 101,110,111 = no bank access (extended opcode space) // ------------------------------------------------------------------------- val bankAccess = Wire(new BankAccessInfo(bankIdLen)) + val enableBits = func7(6, 4) + + // Decode enable from funct7[6:4] + val hasRd0 = enableBits === 1.U || enableBits === 3.U || enableBits === 4.U + val hasRd1 = enableBits === 4.U + val hasWr = enableBits === 2.U || enableBits === 3.U || enableBits === 4.U - bankAccess.rd_bank_0_valid := rs1(45) + bankAccess.rd_bank_0_valid := hasRd0 bankAccess.rd_bank_0_id := rs1(bankIdLen - 1, 0) - bankAccess.rd_bank_1_valid := rs1(46) - bankAccess.rd_bank_1_id := rs1(bankIdLen + 14, 15) - bankAccess.wr_bank_valid := rs1(47) - // For Mem instructions (MVIN/MSET), wr_bank is bank_0 (rs1[14:0]) - // For Ball instructions, wr_bank is bank_2 (rs1[44:30]) - bankAccess.wr_bank_id := Mux(is_mem_inst, rs1(bankIdLen - 1, 0), rs1(bankIdLen + 29, 30)) + bankAccess.rd_bank_1_valid := hasRd1 + bankAccess.rd_bank_1_id := rs1(bankIdLen + 9, 10) + bankAccess.wr_bank_valid := hasWr + // For Mem instructions (MVIN/MSET), wr_bank is bank_0 (rs1[9:0]) + // For Ball instructions, wr_bank is bank_2 (rs1[29:20]) + bankAccess.wr_bank_id := Mux(is_mem_inst, rs1(bankIdLen - 1, 0), rs1(bankIdLen + 19, 20)) // Output control io.id_o.valid := io.id_i.valid diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 9997fb1d..5d9a0b9b 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -40,13 +40,14 @@ class GlobalROB(val b: GlobalConfig) extends Module { // Instruction trace (DPI-C, defined in ITraceDPI.scala) // --------------------------------------------------------------------------- val itrace = Module(new ITraceDPI) - itrace.io.is_issue := 0.U - itrace.io.rob_id := 0.U - itrace.io.domain_id := 0.U - itrace.io.funct := 0.U - itrace.io.rs1 := 0.U - itrace.io.rs2 := 0.U - itrace.io.enable := false.B + itrace.io.is_issue := 0.U + itrace.io.rob_id := 0.U + itrace.io.domain_id := 0.U + itrace.io.funct := 0.U + itrace.io.rs1 := 0.U + itrace.io.rs2 := 0.U + itrace.io.bank_enable := 0.U + itrace.io.enable := false.B // --------------------------------------------------------------------------- // Storage @@ -98,13 +99,14 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.complete.valid := true.B scoreboard.complete.bits := robEntries(cid).cmd.bankAccess - itrace.io.is_issue := 0.U - itrace.io.rob_id := cid - itrace.io.domain_id := robEntries(cid).cmd.domain_id - itrace.io.funct := robEntries(cid).cmd.cmd.funct - itrace.io.rs1 := robEntries(cid).cmd.cmd.rs1 - itrace.io.rs2 := robEntries(cid).cmd.cmd.rs2 - itrace.io.enable := true.B + itrace.io.is_issue := 0.U + itrace.io.rob_id := cid + itrace.io.domain_id := robEntries(cid).cmd.domain_id + itrace.io.funct := robEntries(cid).cmd.cmd.funct + itrace.io.rs1 := robEntries(cid).cmd.cmd.rs1 + itrace.io.rs2 := robEntries(cid).cmd.cmd.rs2 + itrace.io.bank_enable := robEntries(cid).cmd.cmd.funct(6, 4) + itrace.io.enable := true.B } // --------------------------------------------------------------------------- @@ -136,13 +138,14 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.issue.valid := true.B scoreboard.issue.bits := robEntries(actualIssuePtr).cmd.bankAccess - itrace.io.is_issue := 1.U - itrace.io.rob_id := robEntries(actualIssuePtr).rob_id - itrace.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id - itrace.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct - itrace.io.rs1 := robEntries(actualIssuePtr).cmd.cmd.rs1 - itrace.io.rs2 := robEntries(actualIssuePtr).cmd.cmd.rs2 - itrace.io.enable := true.B + itrace.io.is_issue := 1.U + itrace.io.rob_id := robEntries(actualIssuePtr).rob_id + itrace.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itrace.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itrace.io.rs1 := robEntries(actualIssuePtr).cmd.cmd.rs1 + itrace.io.rs2 := robEntries(actualIssuePtr).cmd.cmd.rs2 + itrace.io.bank_enable := robEntries(actualIssuePtr).cmd.cmd.funct(6, 4) + itrace.io.enable := true.B } // --------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala b/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala index 91a9abc1..f744e56d 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala @@ -7,13 +7,14 @@ import chisel3.util._ class ITraceDPI extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { - val is_issue = Input(UInt(8.W)) - val rob_id = Input(UInt(32.W)) - val domain_id = Input(UInt(32.W)) - val funct = Input(UInt(32.W)) - val rs1 = Input(UInt(64.W)) - val rs2 = Input(UInt(64.W)) - val enable = Input(Bool()) + val is_issue = Input(UInt(8.W)) + val rob_id = Input(UInt(32.W)) + val domain_id = Input(UInt(32.W)) + val funct = Input(UInt(32.W)) + val rs1 = Input(UInt(64.W)) + val rs2 = Input(UInt(64.W)) + val bank_enable = Input(UInt(8.W)) + val enable = Input(Bool()) }) setInline( @@ -25,7 +26,8 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { | input int unsigned domain_id, | input int unsigned funct, | input longint unsigned rs1, - | input longint unsigned rs2 + | input longint unsigned rs2, + | input byte unsigned bank_enable |); | |module ITraceDPI( @@ -35,11 +37,12 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { | input [31:0] funct, | input [63:0] rs1, | input [63:0] rs2, + | input [7:0] bank_enable, | input enable |); | always @(*) begin | if (enable) begin - | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2); + | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2, bank_enable); | end | end |endmodule diff --git a/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala b/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala index 1dca1bd7..1af3e7cf 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala @@ -68,17 +68,21 @@ class SubROB(val b: GlobalConfig) extends Module { // States: // sIdle - nothing to do (rowCount == 0) // sReadReq - issue SRAM read request for readPtr row - // sReadResp - SRAM data valid; dispatch valid slots one per cycle + // sReadWait - wait 1 cycle for sramRaw to be latched into sramData + // sReadResp - sramData valid; dispatch valid slots one per cycle // sWaitSlots - all slots issued; wait for all subCompletes // sWaitMaster - all rows done; fire masterComplete then return to sIdle - val sIdle :: sReadReq :: sReadResp :: sWaitSlots :: sWaitMaster :: Nil = Enum(5) - val state = RegInit(sIdle) - - // SyncReadMem: request on cycle N → data valid on cycle N+1 - val sramReadEn = state === sReadReq - val sramData = sram.read(readPtr, sramReadEn) - val sramDataReg = RegNext(sramData) - val readPtrReg = RegNext(readPtr) + val sIdle :: sReadReq :: sReadWait :: sReadResp :: sWaitSlots :: sWaitMaster :: Nil = Enum(6) + val state = RegInit(sIdle) + + // SyncReadMem: read issued in sReadReq (cycle N), data valid on cycle N+1. + // We latch it into sramData with RegEnable so it stays stable during sReadResp + // and sWaitSlots, even when the read port is not enabled. + val sramReadEn = state === sReadReq + val sramRaw = sram.read(readPtr, sramReadEn) + val dataFresh = RegNext(sramReadEn, false.B) // pulse on first cycle of sReadResp + val sramData = RegEnable(sramRaw, dataFresh) + val readPtrReg = RegEnable(readPtr, sramReadEn) // Per-row tracking registers (reset when moving to next row) // slotIssued: have we already sent this slot to a domain? @@ -87,16 +91,16 @@ class SubROB(val b: GlobalConfig) extends Module { val slotDone = RegInit(VecInit(Seq.fill(4)(false.B))) // Combinational: which slots still need to be issued? - val slotNeedsIssue = VecInit((0 until 4).map(i => sramDataReg.slots(i).valid && !slotIssued(i))) + val slotNeedsIssue = VecInit((0 until 4).map(i => sramData.slots(i).valid && !slotIssued(i))) val hasSlotToIssue = slotNeedsIssue.asUInt.orR val firstSlotIdx = PriorityEncoder(slotNeedsIssue.asUInt) // Combinational: are all valid slots done? - val allSlotsDone = VecInit((0 until 4).map(i => !sramDataReg.slots(i).valid || slotDone(i))).asUInt.andR + val allSlotsDone = VecInit((0 until 4).map(i => !sramData.slots(i).valid || slotDone(i))).asUInt.andR // Issue output (valid only in sReadResp when there's a slot to issue) io.issue.valid := (state === sReadResp) && hasSlotToIssue - io.issue.bits := sramDataReg.slots(firstSlotIdx).cmd + io.issue.bits := sramData.slots(firstSlotIdx).cmd io.issueSubId := readPtrReg * 4.U + firstSlotIdx io.issueMasterRobId := masterRobId @@ -132,7 +136,12 @@ class SubROB(val b: GlobalConfig) extends Module { when(occupied)(state := sReadReq) } is(sReadReq) { - // SRAM read issued, data will be valid next cycle + // SRAM read issued, data available on sramRaw next cycle + state := sReadWait + } + is(sReadWait) { + // sramRaw is valid; RegEnable latches it into sramData at this clock edge. + // sramData will be stable starting next cycle (sReadResp). state := sReadResp } is(sReadResp) { @@ -143,13 +152,13 @@ class SubROB(val b: GlobalConfig) extends Module { // Check if all slots have been issued // After marking current slot issued, recalculate val allIssued = VecInit((0 until 4).map(i => - !sramDataReg.slots(i).valid || slotIssued(i) || + !sramData.slots(i).valid || slotIssued(i) || (io.issue.fire && firstSlotIdx === i.U) )).asUInt.andR when(allIssued) { // Check fast path: all already done (e.g., empty row or immediate completion) - val allDoneNow = VecInit((0 until 4).map(i => !sramDataReg.slots(i).valid || slotDone(i))).asUInt.andR + val allDoneNow = VecInit((0 until 4).map(i => !sramData.slots(i).valid || slotDone(i))).asUInt.andR when(allDoneNow) { // Fast path: skip sWaitSlots advanceRow() diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 86331731..86bab3a0 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -96,7 +96,7 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { midend.io.bankRead(totalBallRead).is_shared := frontend.io.interdma.read_is_shared midend.io.bankWrite(totalBallWrite).bankWrite <> frontend.io.interdma.bankWrite midend.io.bankWrite(totalBallWrite).is_shared := frontend.io.interdma.write_is_shared - midend.io.hartid := io.hartid + midend.io.hartid := io.hartid midend.io.mem_req <> backend.io.mem_req backend.io.config <> frontend.io.config diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala index bbe01ab3..4d3e073d 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DISA.scala @@ -4,8 +4,9 @@ import chisel3._ import chisel3.util._ object DISA { - - val MSET_BITPAT = BitPat("b0010111") // 23 - val MVIN_BITPAT = BitPat("b0011000") // 24 - val MVOUT_BITPAT = BitPat("b0011001") // 25 + // enable=010 (1 write), opcode group + val MSET_BITPAT = BitPat("b0100000") // 32 (0x20) — enable=010, opcode=0 + val MVIN_BITPAT = BitPat("b0100001") // 33 (0x21) — enable=010, opcode=1 + // enable=001 (1 read), opcode group + val MVOUT_BITPAT = BitPat("b0010000") // 16 (0x10) — enable=001, opcode=0 } diff --git a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala index 6aeeb0e1..8890a58a 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/cmd_channel/decoder/DomainDecoder.scala @@ -61,9 +61,9 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { val rs2 = io.cmd_i.bits.cmd.rs2Data // Unified encoding: - // rs1[14:0] = bank_id (BANK0) - // rs1[45:47] = bank access valid flags (used by scoreboard, ignored here) - // rs1[63:48] = iter + // rs1[9:0] = bank_id (BANK0) + // rs1[63:30] = iter (34-bit) + // funct7[6:4] = enable (bank access flags, decoded by GlobalDecoder) // rs2[38:0] = mem_addr (for MVIN/MVOUT, 39-bit) // rs2[63:0] = special (full 64-bit) import LSDecodeFields._ @@ -77,7 +77,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { N, N, 0.U(memAddrLen.W), // mem_addr: not used for MSET - rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[9:0] rs2, // special = full rs2 Y ), // mset @@ -85,7 +85,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { Y, N, rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] - rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[9:0] rs2, // special = full rs2 Y ), // mvin @@ -93,7 +93,7 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { N, Y, rs2(memAddrLen - 1, 0), // mem_addr from rs2[38:0] - rs1(bankIdLen - 1, 0), // bank_id from rs1[14:0] + rs1(bankIdLen - 1, 0), // bank_id from rs1[9:0] rs2, // special = full rs2 Y ) // mvout @@ -133,10 +133,10 @@ class MemDomainDecoder(val b: GlobalConfig) extends Module { ls_decode_list(LSDecodeFields.MEMADDR.id).asUInt, 0.U(b.memDomain.memAddrLen.W) ) - // iter is always from rs1[63:48] + // iter is always from rs1[63:30] io.mem_decode_cmd_o.bits.iter := Mux( io.mem_decode_cmd_o.valid, - rs1(63, 48), + rs1(63, 30), 0.U(iterLen.W) ) diff --git a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala index 99162f18..4ef02ff6 100644 --- a/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala +++ b/arch/src/main/scala/framework/memdomain/midend/MemMidend.scala @@ -90,7 +90,7 @@ class MemMidend(val b: GlobalConfig) extends Module { } // Allocate channels for writes: one per cycle to avoid conflicts - val pendingWrites = + val pendingWrites = VecInit((0 until totalWrite).map(i => io.bankWrite(i).bankWrite.io.req.valid && !isAllocated(false.B, i.U))) val hasPendingWrite = pendingWrites.asUInt.orR val nextWriteToAllocate = PriorityEncoder(pendingWrites) @@ -136,13 +136,13 @@ class MemMidend(val b: GlobalConfig) extends Module { when(mappingTable(i).valid) { when(isRead) { io.mem_req(i).read <> ballRead - io.mem_req(i).bank_id := rbank_id - io.mem_req(i).group_id := rgroup_id + io.mem_req(i).bank_id := rbank_id + io.mem_req(i).group_id := rgroup_id io.mem_req(i).is_shared := r_shared }.otherwise { io.mem_req(i).write <> ballWrite - io.mem_req(i).bank_id := wbank_id - io.mem_req(i).group_id := wgroup_id + io.mem_req(i).bank_id := wbank_id + io.mem_req(i).group_id := wgroup_id io.mem_req(i).is_shared := w_shared } } diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 1f72bed0..ea598d63 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -95,6 +95,58 @@ "ctest_tlb_test_singlecore-baremetal", "ctest_tlb_test_singlecore-baremetal", ), + ( + "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", + "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", + "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", + "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", + "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", + "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", + "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", + "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", + "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", + "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", + ), ] diff --git a/bb-tests/workloads/lib/bbhw/isa/31_fence.c b/bb-tests/workloads/lib/bbhw/isa/00_fence.c similarity index 85% rename from bb-tests/workloads/lib/bbhw/isa/31_fence.c rename to bb-tests/workloads/lib/bbhw/isa/00_fence.c index 46fb4878..4ec9514e 100644 --- a/bb-tests/workloads/lib/bbhw/isa/31_fence.c +++ b/bb-tests/workloads/lib/bbhw/isa/00_fence.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BB_FENCE_FUNC7 31 +#define BB_FENCE_FUNC7 0 #define bb_fence() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7) diff --git a/bb-tests/workloads/lib/bbhw/isa/50_barrier.c b/bb-tests/workloads/lib/bbhw/isa/01_barrier.c similarity index 95% rename from bb-tests/workloads/lib/bbhw/isa/50_barrier.c rename to bb-tests/workloads/lib/bbhw/isa/01_barrier.c index 2768897c..5bfbff3c 100644 --- a/bb-tests/workloads/lib/bbhw/isa/50_barrier.c +++ b/bb-tests/workloads/lib/bbhw/isa/01_barrier.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BB_BARRIER_FUNC7 50 +#define BB_BARRIER_FUNC7 1 /** * bb_barrier() - hardware multi-core barrier synchronization. diff --git a/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c b/bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c similarity index 96% rename from bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c rename to bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c index ae5cd61f..d8e66904 100644 --- a/bb-tests/workloads/lib/bbhw/isa/42_gemmini_config.c +++ b/bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BB_GEMMINI_CONFIG_FUNC7 42 +#define BB_GEMMINI_CONFIG_FUNC7 2 // Configure Gemmini systolic array // All config parameters go in rs2 (special), starting from bit 4 diff --git a/bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c b/bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c similarity index 89% rename from bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c rename to bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c index c589f0b8..0d19750a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/46_gemmini_flush.c +++ b/bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BB_GEMMINI_FLUSH_FUNC7 46 +#define BB_GEMMINI_FLUSH_FUNC7 3 // Flush the systolic array state #define bb_gemmini_flush() \ diff --git a/bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c b/bb-tests/workloads/lib/bbhw/isa/04_bdb_counter.c similarity index 85% rename from bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c rename to bb-tests/workloads/lib/bbhw/isa/04_bdb_counter.c index a3694757..449a6a8e 100644 --- a/bb-tests/workloads/lib/bbhw/isa/48_bdb_counter.c +++ b/bb-tests/workloads/lib/bbhw/isa/04_bdb_counter.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BDB_COUNTER_FUNC7 48 +#define BDB_COUNTER_FUNC7 4 // subcmd values #define BDB_CTR_START 0 @@ -12,22 +12,22 @@ // rs2 layout: [3:0]=subcmd, [7:4]=ctr_id, [63:8]=payload #define BDB_CTR_RS2(subcmd, ctr_id, payload) \ - (((unsigned long long)(payload) << 8) | (((ctr_id)&0xF) << 4) | \ - ((subcmd)&0xF)) + (((unsigned long long)(payload) << 8) | (((ctr_id) & 0xF) << 4) | \ + ((subcmd) & 0xF)) // Start counter ctr_id with user tag #define bdb_counter_start(ctr_id, tag) \ - BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_START, ctr_id, tag), \ + BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_START, ctr_id, tag), \ BDB_COUNTER_FUNC7) // Stop counter ctr_id, output elapsed to trace #define bdb_counter_stop(ctr_id) \ - BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_STOP, ctr_id, 0), \ + BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_STOP, ctr_id, 0), \ BDB_COUNTER_FUNC7) // Read counter ctr_id current value (non-destructive), output to trace #define bdb_counter_read(ctr_id) \ - BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_READ, ctr_id, 0), \ + BUCKYBALL_INSTRUCTION_R_R(0, BDB_CTR_RS2(BDB_CTR_READ, ctr_id, 0), \ BDB_COUNTER_FUNC7) #endif // _BDB_COUNTER_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/105_gemmini_loop_conv_ws.c b/bb-tests/workloads/lib/bbhw/isa/105_gemmini_loop_conv_ws.c new file mode 100644 index 00000000..7e551a2a --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/105_gemmini_loop_conv_ws.c @@ -0,0 +1,72 @@ +#ifndef _BB_GEMMINI_LOOP_CONV_WS_H +#define _BB_GEMMINI_LOOP_CONV_WS_H + +#include "isa.h" + +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_1_FUNC7 96 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_2_FUNC7 97 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_3_FUNC7 98 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_4_FUNC7 99 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_5_FUNC7 100 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_6_FUNC7 101 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_7_FUNC7 102 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_8_FUNC7 103 +#define BB_GEMMINI_LOOP_CONV_WS_CONFIG_9_FUNC7 104 +#define BB_GEMMINI_LOOP_CONV_WS_FUNC7 105 + +#define bb_gemmini_loop_conv_ws_config_1(batch_size, in_dim, in_channels) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(batch_size, 0, 15) | \ + FIELD(in_dim, 16, 31) | \ + FIELD(in_channels, 32, 47)), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_1_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_2(out_channels, out_dim, stride, \ + padding) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(out_channels, 0, 15) | \ + FIELD(out_dim, 16, 31) | FIELD(stride, 32, 39) | \ + FIELD(padding, 40, 47)), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_2_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_3(kernel_dim, pool_size, pool_stride, \ + pool_padding) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(kernel_dim, 0, 7) | FIELD(pool_size, 8, 15) | \ + FIELD(pool_stride, 16, 23) | FIELD(pool_padding, 24, 31)), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_3_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_4(addr_bias) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_bias, 0, 38), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_4_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_5(addr_input) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_input, 0, 38), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_5_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_6(addr_weight) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_weight, 0, 38), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_6_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_7(addr_output) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_output, 0, 38), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_7_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_8(input_stride, weight_stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(input_stride, 0, 31) | FIELD(weight_stride, 32, 63)), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_8_FUNC7) + +#define bb_gemmini_loop_conv_ws_config_9(output_stride) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(output_stride, 0, 31), \ + BB_GEMMINI_LOOP_CONV_WS_CONFIG_9_FUNC7) + +#define bb_gemmini_loop_conv_ws(bank_input, bank_weight, bank_output, no_bias) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(bank_input, 0, 9) | FIELD(bank_weight, 10, 19) | \ + FIELD(bank_output, 20, 29) | FIELD(no_bias, 30, 30)), \ + BB_GEMMINI_LOOP_CONV_WS_FUNC7) + +#endif diff --git a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c b/bb-tests/workloads/lib/bbhw/isa/16_mvout.c similarity index 73% rename from bb-tests/workloads/lib/bbhw/isa/25_mvout.c rename to bb-tests/workloads/lib/bbhw/isa/16_mvout.c index 4fa645c0..faffc689 100644 --- a/bb-tests/workloads/lib/bbhw/isa/25_mvout.c +++ b/bb-tests/workloads/lib/bbhw/isa/16_mvout.c @@ -3,10 +3,10 @@ #include "isa.h" -#define BB_MVOUT_FUNC7 25 +#define BB_MVOUT_FUNC7 16 #define bb_mvout(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_RD0 | BB_ITER(depth)), \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_ITER(depth)), \ (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ BB_MVOUT_FUNC7) diff --git a/bb-tests/workloads/lib/bbhw/isa/23_mset.c b/bb-tests/workloads/lib/bbhw/isa/32_mset.c similarity index 73% rename from bb-tests/workloads/lib/bbhw/isa/23_mset.c rename to bb-tests/workloads/lib/bbhw/isa/32_mset.c index 31988429..d9851bcf 100644 --- a/bb-tests/workloads/lib/bbhw/isa/23_mset.c +++ b/bb-tests/workloads/lib/bbhw/isa/32_mset.c @@ -3,17 +3,16 @@ #include "isa.h" -#define BB_MSET_FUNC7 23 +#define BB_MSET_FUNC7 32 -#define bb_mset(bank_id, alloc, row, col) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_WR), \ - (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10)), \ +#define bb_mset(bank_id, alloc, row, col) \ + BUCKYBALL_INSTRUCTION_R_R( \ + BB_BANK0(bank_id), \ + (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10)), \ BB_MSET_FUNC7) #define bb_mem_release(bank_id) bb_mset(bank_id, 0, 0, 0); #define bb_mem_alloc(bank_id, row, col) bb_mset(bank_id, 1, row, col) - #endif // _BB_MSET_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c b/bb-tests/workloads/lib/bbhw/isa/33_im2col.c deleted file mode 100644 index a0eaafcb..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/33_im2col.c +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _BB_IM2COL_H_ -#define _BB_IM2COL_H_ - -#include "isa.h" - -#define BB_IM2COL_FUNC7 33 - -#define bb_im2col(op1_bank_id, wr_bank_id, krow, kcol, inrow, incol, startrow, \ - startcol) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_RD0 | BB_WR), \ - (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | FIELD(incol, 8, 12) | \ - FIELD(inrow, 13, 22) | FIELD(startcol, 23, 27) | \ - FIELD(startrow, 28, 37)), \ - BB_IM2COL_FUNC7) - -#endif // _BB_IM2COL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c b/bb-tests/workloads/lib/bbhw/isa/33_mvin.c similarity index 73% rename from bb-tests/workloads/lib/bbhw/isa/24_mvin.c rename to bb-tests/workloads/lib/bbhw/isa/33_mvin.c index 79198d99..e45fec13 100644 --- a/bb-tests/workloads/lib/bbhw/isa/24_mvin.c +++ b/bb-tests/workloads/lib/bbhw/isa/33_mvin.c @@ -3,10 +3,10 @@ #include "isa.h" -#define BB_MVIN_FUNC7 24 +#define BB_MVIN_FUNC7 33 #define bb_mvin(mem_addr, bank_id, depth, stride) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_WR | BB_ITER(depth)), \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_ITER(depth)), \ (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ BB_MVIN_FUNC7) diff --git a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c b/bb-tests/workloads/lib/bbhw/isa/34_transpose.c deleted file mode 100644 index be296040..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/34_transpose.c +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BB_TRANSPOSE_H_ -#define _BB_TRANSPOSE_H_ - -#include "isa.h" - -#define BB_TRANSPOSE_FUNC7 34 - -#define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | \ - BB_RD0 | BB_WR | BB_ITER(iter)), \ - (FIELD(mode, 0, 63)), BB_TRANSPOSE_FUNC7) - -#endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/38_relu.c b/bb-tests/workloads/lib/bbhw/isa/38_relu.c deleted file mode 100644 index a4271878..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/38_relu.c +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BB_RELU_H_ -#define _BB_RELU_H_ - -#include "isa.h" - -#define BB_RELU_FUNC7 38 - -#define bb_relu(bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ - BB_RD0 | BB_WR | BB_ITER(iter)), \ - 0, BB_RELU_FUNC7) - -#endif // _BB_RELU_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/40_quant.c b/bb-tests/workloads/lib/bbhw/isa/40_quant.c deleted file mode 100644 index 338c62a0..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/40_quant.c +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _BB_QUANT_H_ -#define _BB_QUANT_H_ - -#include "isa.h" - -#define BB_QUANT_FUNC7 40 - -// bb_quant(bank_id, wr_bank_id, iter, scale_fp32) -// scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern -// Encoding: rs1 = banks | enables | iter -// rs2 = scale_fp32 -#define bb_quant(bank_id, wr_bank_id, iter, scale_fp32) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ - BB_RD0 | BB_WR | BB_ITER(iter)), \ - (FIELD((uint64_t)(scale_fp32), 0, 31)), \ - BB_QUANT_FUNC7) - -#endif // _BB_QUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/48_im2col.c b/bb-tests/workloads/lib/bbhw/isa/48_im2col.c new file mode 100644 index 00000000..eaaa8488 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/48_im2col.c @@ -0,0 +1,17 @@ +#ifndef _BB_IM2COL_H_ +#define _BB_IM2COL_H_ + +#include "isa.h" + +#define BB_IM2COL_FUNC7 48 + +#define bb_im2col(op1_bank_id, wr_bank_id, krow, kcol, inrow, incol, startrow, \ + startcol) \ + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id)), \ + (FIELD(kcol, 0, 3) | FIELD(krow, 4, 7) | \ + FIELD(incol, 8, 12) | FIELD(inrow, 13, 22) | \ + FIELD(startcol, 23, 27) | \ + FIELD(startrow, 28, 37)), \ + BB_IM2COL_FUNC7) + +#endif // _BB_IM2COL_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/49_transpose.c b/bb-tests/workloads/lib/bbhw/isa/49_transpose.c new file mode 100644 index 00000000..7421b5b2 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/49_transpose.c @@ -0,0 +1,13 @@ +#ifndef _BB_TRANSPOSE_H_ +#define _BB_TRANSPOSE_H_ + +#include "isa.h" + +#define BB_TRANSPOSE_FUNC7 49 + +#define bb_transpose(op1_bank_id, wr_bank_id, iter, mode) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ + (FIELD(mode, 0, 63)), BB_TRANSPOSE_FUNC7) + +#endif // _BB_TRANSPOSE_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/50_relu.c b/bb-tests/workloads/lib/bbhw/isa/50_relu.c new file mode 100644 index 00000000..4bb12ec6 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/50_relu.c @@ -0,0 +1,13 @@ +#ifndef _BB_RELU_H_ +#define _BB_RELU_H_ + +#include "isa.h" + +#define BB_RELU_FUNC7 50 + +#define bb_relu(bank_id, wr_bank_id, iter) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), 0, \ + BB_RELU_FUNC7) + +#endif // _BB_RELU_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/51_quant.c b/bb-tests/workloads/lib/bbhw/isa/51_quant.c new file mode 100644 index 00000000..7cde739d --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/51_quant.c @@ -0,0 +1,17 @@ +#ifndef _BB_QUANT_H_ +#define _BB_QUANT_H_ + +#include "isa.h" + +#define BB_QUANT_FUNC7 51 + +// bb_quant(bank_id, wr_bank_id, iter, scale_fp32) +// scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern +// Encoding: rs1 = banks | iter +// rs2 = scale_fp32 +#define bb_quant(bank_id, wr_bank_id, iter, scale_fp32) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ + (FIELD((uint64_t)(scale_fp32), 0, 31)), BB_QUANT_FUNC7) + +#endif // _BB_QUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/41_dequant.c b/bb-tests/workloads/lib/bbhw/isa/52_dequant.c similarity index 50% rename from bb-tests/workloads/lib/bbhw/isa/41_dequant.c rename to bb-tests/workloads/lib/bbhw/isa/52_dequant.c index dd268d04..6bbba87e 100644 --- a/bb-tests/workloads/lib/bbhw/isa/41_dequant.c +++ b/bb-tests/workloads/lib/bbhw/isa/52_dequant.c @@ -3,16 +3,15 @@ #include "isa.h" -#define BB_DEQUANT_FUNC7 41 +#define BB_DEQUANT_FUNC7 52 // bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) // scale_fp32 is a 32-bit FP32 value passed as uint32_t bit pattern -// Encoding: rs1 = banks | enables | iter +// Encoding: rs1 = banks | iter // rs2 = FIELD(scale_fp32, 0, 31) #define bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ - BB_RD0 | BB_WR | BB_ITER(iter)), \ - (FIELD((uint64_t)(scale_fp32), 0, 31)), \ - BB_DEQUANT_FUNC7) + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ + (FIELD((uint64_t)(scale_fp32), 0, 31)), BB_DEQUANT_FUNC7) #endif // _BB_DEQUANT_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c b/bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c similarity index 61% rename from bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c rename to bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c index 0d07bfeb..fc700fa1 100644 --- a/bb-tests/workloads/lib/bbhw/isa/43_gemmini_preload.c +++ b/bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c @@ -3,15 +3,15 @@ #include "isa.h" -#define BB_GEMMINI_PRELOAD_FUNC7 43 +#define BB_GEMMINI_PRELOAD_FUNC7 53 // Preload D/B matrix into systolic array // op1_bank_id: source bank for D (OS) or B (WS) // wr_bank_id: destination bank for C output // iter: number of rows to preload #define bb_gemmini_preload(op1_bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | \ - BB_RD0 | BB_WR | BB_ITER(iter)), \ - 0, BB_GEMMINI_PRELOAD_FUNC7) + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), 0, \ + BB_GEMMINI_PRELOAD_FUNC7) #endif // _BB_GEMMINI_PRELOAD_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c b/bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c similarity index 53% rename from bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c rename to bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c index d19e867a..27d981be 100644 --- a/bb-tests/workloads/lib/bbhw/isa/49_bdb_backdoor.c +++ b/bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c @@ -3,24 +3,23 @@ #include "isa.h" -#define BDB_BACKDOOR_FUNC7 49 +#define BDB_BACKDOOR_FUNC7 54 // Backdoor write: DPI-C provides data, write to external bank // bank_id = target bank, iter = number of rows #define bdb_backdoor_write(bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK2(bank_id) | BB_WR | BB_ITER(iter)), 0, BDB_BACKDOOR_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK2(bank_id) | BB_ITER(iter)), 0, \ + BDB_BACKDOOR_FUNC7) // Backdoor read: read from external bank, output via DPI-C // bank_id = source bank, iter = number of rows #define bdb_backdoor_read(bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_RD0 | BB_ITER(iter)), 0, BDB_BACKDOOR_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_ITER(iter)), 0, \ + BDB_BACKDOOR_FUNC7) // Backdoor peek: read single row from external bank #define bdb_backdoor_peek(bank_id, row_count) \ - BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(bank_id) | BB_RD0 | BB_ITER(row_count)), 0, \ - BDB_BACKDOOR_FUNC7) + BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_ITER(row_count)), 0, \ + BDB_BACKDOOR_FUNC7) #endif // _BDB_BACKDOOR_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c b/bb-tests/workloads/lib/bbhw/isa/64_mul_warp16.c similarity index 63% rename from bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c rename to bb-tests/workloads/lib/bbhw/isa/64_mul_warp16.c index 5ebedc37..2f732742 100644 --- a/bb-tests/workloads/lib/bbhw/isa/32_mul_warp16.c +++ b/bb-tests/workloads/lib/bbhw/isa/64_mul_warp16.c @@ -3,12 +3,11 @@ #include "isa.h" -#define BB_MUL_WARP16_FUNC7 32 +#define BB_MUL_WARP16_FUNC7 64 #define bb_mul_warp16(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ - BB_ITER(iter)), \ + BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ (FIELD(mode, 0, 63)), BB_MUL_WARP16_FUNC7) #endif // _BB_MUL_WARP16_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/39_bfp.c b/bb-tests/workloads/lib/bbhw/isa/65_bfp.c similarity index 62% rename from bb-tests/workloads/lib/bbhw/isa/39_bfp.c rename to bb-tests/workloads/lib/bbhw/isa/65_bfp.c index 32f365e7..fdde6a91 100644 --- a/bb-tests/workloads/lib/bbhw/isa/39_bfp.c +++ b/bb-tests/workloads/lib/bbhw/isa/65_bfp.c @@ -3,12 +3,11 @@ #include "isa.h" -#define BB_BFP_FUNC7 39 +#define BB_BFP_FUNC7 65 #define bb_BFP(op1_bank_id, op2_bank_id, wr_bank_id, iter, mode) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ - BB_ITER(iter)), \ + BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ (FIELD(mode, 0, 63)), BB_BFP_FUNC7) #endif // _BB_BFP_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c b/bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c similarity index 76% rename from bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c rename to bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c index 609edf5b..6bd6fa6a 100644 --- a/bb-tests/workloads/lib/bbhw/isa/44_gemmini_compute_preloaded.c +++ b/bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BB_GEMMINI_COMPUTE_PRELOADED_FUNC7 44 +#define BB_GEMMINI_COMPUTE_PRELOADED_FUNC7 66 // Compute matmul using preloaded data: C = A * B + D(preloaded) // op1_bank_id: bank for A matrix @@ -13,8 +13,7 @@ #define bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, wr_bank_id, \ iter) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ - BB_ITER(iter)), \ + BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ 0, BB_GEMMINI_COMPUTE_PRELOADED_FUNC7) #endif // _BB_GEMMINI_COMPUTE_PRELOADED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c b/bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c similarity index 75% rename from bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c rename to bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c index d3e25a9e..93239d52 100644 --- a/bb-tests/workloads/lib/bbhw/isa/45_gemmini_compute_accumulated.c +++ b/bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c @@ -3,7 +3,7 @@ #include "isa.h" -#define BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7 45 +#define BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7 67 // Compute matmul reusing previously accumulated results // op1_bank_id: bank for A matrix @@ -13,8 +13,7 @@ #define bb_gemmini_compute_accumulated(op1_bank_id, op2_bank_id, wr_bank_id, \ iter) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ - BB_BANK2(wr_bank_id) | BB_RD0 | BB_RD1 | BB_WR | \ - BB_ITER(iter)), \ + BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ 0, BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7) #endif // _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/87_gemmini_loop_ws.c b/bb-tests/workloads/lib/bbhw/isa/87_gemmini_loop_ws.c new file mode 100644 index 00000000..3b99ec94 --- /dev/null +++ b/bb-tests/workloads/lib/bbhw/isa/87_gemmini_loop_ws.c @@ -0,0 +1,52 @@ +#ifndef _BB_GEMMINI_LOOP_WS_H +#define _BB_GEMMINI_LOOP_WS_H + +#include "isa.h" + +#define BB_GEMMINI_LOOP_WS_CONFIG_BOUNDS_FUNC7 80 +#define BB_GEMMINI_LOOP_WS_CONFIG_ADDR_A_FUNC7 81 +#define BB_GEMMINI_LOOP_WS_CONFIG_ADDR_B_FUNC7 82 +#define BB_GEMMINI_LOOP_WS_CONFIG_ADDR_D_FUNC7 83 +#define BB_GEMMINI_LOOP_WS_CONFIG_ADDR_C_FUNC7 84 +#define BB_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB_FUNC7 85 +#define BB_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC_FUNC7 86 +#define BB_GEMMINI_LOOP_WS_FUNC7 87 + +#define bb_gemmini_loop_ws_config_bounds(max_i, max_j, max_k) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(max_k, 0, 15) | FIELD(max_j, 16, 31) | FIELD(max_i, 32, 47)), \ + BB_GEMMINI_LOOP_WS_CONFIG_BOUNDS_FUNC7) + +#define bb_gemmini_loop_ws_config_addr_a(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_GEMMINI_LOOP_WS_CONFIG_ADDR_A_FUNC7) + +#define bb_gemmini_loop_ws_config_addr_b(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_GEMMINI_LOOP_WS_CONFIG_ADDR_B_FUNC7) + +#define bb_gemmini_loop_ws_config_addr_d(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_GEMMINI_LOOP_WS_CONFIG_ADDR_D_FUNC7) + +#define bb_gemmini_loop_ws_config_addr_c(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_GEMMINI_LOOP_WS_CONFIG_ADDR_C_FUNC7) + +#define bb_gemmini_loop_ws_config_strides_ab(stride_a, stride_b) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(stride_a, 0, 31) | FIELD(stride_b, 32, 63)), \ + BB_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB_FUNC7) + +#define bb_gemmini_loop_ws_config_strides_dc(stride_d, stride_c) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(stride_d, 0, 31) | FIELD(stride_c, 32, 63)), \ + BB_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC_FUNC7) + +#define bb_gemmini_loop_ws(bank_a, bank_b, bank_c, low_d) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(bank_a, 0, 9) | FIELD(bank_b, 10, 19) | \ + FIELD(bank_c, 20, 29) | FIELD(low_d, 30, 30)), \ + BB_GEMMINI_LOOP_WS_FUNC7) + +#endif diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 07afc1c1..02ab92d9 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -21,46 +21,46 @@ typedef int32_t result_t; #define FIELD(val, start_bit, end_bit) \ (((val) & ((2UL << ((end_bit) - (start_bit))) - 1)) << (start_bit)) -// Unified rs1 bank encoding flags (bits 45-47) -// bit 45 = rd_bank_0_valid, bit 46 = rd_bank_1_valid, bit 47 = wr_bank_valid -#define BB_RD0 (1UL << 45) -#define BB_RD1 (1UL << 46) -#define BB_WR (1UL << 47) +// rs1 bank field helpers (10-bit each) +#define BB_BANK0(id) FIELD(id, 0, 9) +#define BB_BANK1(id) FIELD(id, 10, 19) +#define BB_BANK2(id) FIELD(id, 20, 29) -// rs1 bank field helpers (15-bit each) -#define BB_BANK0(id) FIELD(id, 0, 14) -#define BB_BANK1(id) FIELD(id, 15, 29) -#define BB_BANK2(id) FIELD(id, 30, 44) +// rs1 iter field (34-bit, bits 30-63) +#define BB_ITER(n) FIELD(n, 30, 63) -// rs1 iter field (16-bit, bits 48-63) -#define BB_ITER(n) FIELD(n, 48, 63) +// funct7 encoding: [6:4]=enable, [3:0]=opcode +// enable: 000=none, 001=1rd, 010=1wr, 011=1rd+1wr, 100=2rd+1wr +// 101/110/111 = none (extended opcode space) -// Generic RISC-V custom instruction macro +// Generic RISC-V custom instruction macro (funct3 always 0x3 = CUSTOM3_RS1_RS2) #define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ - asm volatile(".insn r " STR(CUSTOM_3) ", 0x3, %c2, x0, %0, %1" \ + asm volatile(".insn r " STR(CUSTOM_3) ", 3, %c2, x0, %0, %1" \ : \ : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ : "memory") // Include all instruction definitions -#include "23_mset.c" -#include "24_mvin.c" -#include "25_mvout.c" -#include "31_fence.c" -#include "32_mul_warp16.c" -#include "33_im2col.c" -#include "34_transpose.c" -#include "38_relu.c" -#include "39_bfp.c" -#include "40_quant.c" -#include "41_dequant.c" -#include "42_gemmini_config.c" -#include "43_gemmini_preload.c" -#include "44_gemmini_compute_preloaded.c" -#include "45_gemmini_compute_accumulated.c" -#include "46_gemmini_flush.c" -#include "48_bdb_counter.c" -#include "49_bdb_backdoor.c" -#include "50_barrier.c" +#include "00_fence.c" +#include "01_barrier.c" +#include "02_gemmini_config.c" +#include "03_gemmini_flush.c" +#include "04_bdb_counter.c" +#include "105_gemmini_loop_conv_ws.c" +#include "16_mvout.c" +#include "32_mset.c" +#include "33_mvin.c" +#include "48_im2col.c" +#include "49_transpose.c" +#include "50_relu.c" +#include "51_quant.c" +#include "52_dequant.c" +#include "53_gemmini_preload.c" +#include "54_bdb_backdoor.c" +#include "64_mul_warp16.c" +#include "65_bfp.c" +#include "66_gemmini_compute_preloaded.c" +#include "67_gemmini_compute_accumulated.c" +#include "87_gemmini_loop_ws.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index 0f717c69..ef6eebc0 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -117,10 +117,22 @@ add_cross_platform_test_target(ctest_vsetvli test_vsetvli.c) add_cross_platform_test_target(ctest_bfp_test bfp_test.c) add_cross_platform_test_target(ctest_quant_test quant_test.c) add_cross_platform_test_target(ctest_dequant_test dequant_test.c) -add_cross_platform_test_target(ctest_gemmini_matmul_test gemmini_matmul_test.c) add_cross_platform_test_target(ctest_tlb_test tlb_test.c) add_cross_platform_test_target(ctest_bdb_counter_test bdb_counter_test.c) add_cross_platform_test_target(ctest_bdb_backdoor_test bdb_backdoor_test.c) +add_cross_platform_test_target(ctest_gemmini_os_risc_basic_test gemmini_os_risc_basic_test.c) +add_cross_platform_test_target(ctest_gemmini_os_risc_shift_test gemmini_os_risc_shift_test.c) +add_cross_platform_test_target(ctest_gemmini_os_risc_atranspose_test gemmini_os_risc_atranspose_test.c) +add_cross_platform_test_target(ctest_gemmini_os_risc_btranspose_test gemmini_os_risc_btranspose_test.c) +add_cross_platform_test_target(ctest_gemmini_os_risc_abtranspose_test gemmini_os_risc_abtranspose_test.c) +add_cross_platform_test_target(ctest_gemmini_ws_risc_basic_test gemmini_ws_risc_basic_test.c) +add_cross_platform_test_target(ctest_gemmini_ws_risc_shift_test gemmini_ws_risc_shift_test.c) +add_cross_platform_test_target(ctest_gemmini_ws_risc_btranspose_test gemmini_ws_risc_btranspose_test.c) +add_cross_platform_test_target(ctest_gemmini_os_cisc_basic_test gemmini_os_cisc_basic_test.c) +add_cross_platform_test_target(ctest_gemmini_os_cisc_shift_test gemmini_os_cisc_shift_test.c) +add_cross_platform_test_target(ctest_gemmini_os_cisc_atranspose_test gemmini_os_cisc_atranspose_test.c) +add_cross_platform_test_target(ctest_gemmini_os_cisc_btranspose_test gemmini_os_cisc_btranspose_test.c) +add_cross_platform_test_target(ctest_gemmini_ws_cisc_conv_test gemmini_ws_cisc_conv_test.c) # Create master build target add_custom_target(buckyball-CTest-build ALL DEPENDS @@ -148,9 +160,21 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_bfp_test ctest_quant_test ctest_dequant_test - ctest_gemmini_matmul_test ctest_tlb_test ctest_bdb_counter_test ctest_bdb_backdoor_test + ctest_gemmini_os_risc_basic_test + ctest_gemmini_os_risc_shift_test + ctest_gemmini_os_risc_atranspose_test + ctest_gemmini_os_risc_btranspose_test + ctest_gemmini_os_risc_abtranspose_test + ctest_gemmini_ws_risc_basic_test + ctest_gemmini_ws_risc_shift_test + ctest_gemmini_ws_risc_btranspose_test + ctest_gemmini_os_cisc_basic_test + ctest_gemmini_os_cisc_shift_test + ctest_gemmini_os_cisc_atranspose_test + ctest_gemmini_os_cisc_btranspose_test + ctest_gemmini_ws_cisc_conv_test COMMENT "Building all workloads for Buckyball" VERBATIM) diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c deleted file mode 100644 index c78f0e0c..00000000 --- a/bb-tests/workloads/src/CTest/toy/gemmini_matmul_test.c +++ /dev/null @@ -1,75 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM 16 - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); - -void hw_gemmini_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { - uint32_t op1_bank_id = 0; // A matrix - uint32_t op2_bank_id = 1; // B matrix - int acc_bank_id = 2; // C output (accumulator width) - - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - - // Load A and B into SRAM banks - bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); - bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); - - // Configure: OS mode, no activation, no transpose, no shift - bb_gemmini_config(0, 0, 0, 0, 0); - - // Preload D=0 (zero bias), set output bank - bb_gemmini_preload(op1_bank_id, acc_bank_id, size); - - // Compute: A * B + D(preloaded) - bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, acc_bank_id, size); - - // Read results back - bb_mvout((uintptr_t)c, acc_bank_id, size << 2, 1); - bb_fence(); -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - cpu_matmul(a, b, expected_matrix, size, size, size); - hw_gemmini_matmul(test_name, a, b, output_matrix, size); - - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { - printf("Test %s PASSED\n", test_name); - return 1; - } else { - printf("Test %s FAILED\n", test_name); - return 0; - } -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - init_u8_random_matrix(input_matrix_a, DIM, DIM, 42); - init_u8_random_matrix(input_matrix_b, DIM, DIM, 84); - - int passed = - run_test("Gemmini OS Matmul", input_matrix_a, input_matrix_b, DIM); - if (passed) { - printf("Gemmini matmul test PASSED\n"); - return 0; - } else { - printf("Gemmini matmul test FAILED\n"); - return 1; - } - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c new file mode 100644 index 00000000..171a605a --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c @@ -0,0 +1,43 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC a_transpose Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c new file mode 100644 index 00000000..05744b89 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c @@ -0,0 +1,41 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC Basic Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c new file mode 100644 index 00000000..9d484f25 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c @@ -0,0 +1,43 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC b_transpose Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c new file mode 100644 index 00000000..cc59230a --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c @@ -0,0 +1,44 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC in_shift Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] >>= SHIFT; + + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c new file mode 100644 index 00000000..3f97c8ac --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c @@ -0,0 +1,46 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC ab_transpose Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_at, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c new file mode 100644 index 00000000..6391b356 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c @@ -0,0 +1,44 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC a_transpose Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_preload(bank_a, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c new file mode 100644 index 00000000..a74f399f --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c @@ -0,0 +1,42 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC Basic Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, 0); + bb_gemmini_preload(bank_a, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c new file mode 100644 index 00000000..72a26432 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c @@ -0,0 +1,44 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC b_transpose Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c new file mode 100644 index 00000000..50fc68de --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c @@ -0,0 +1,45 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC in_shift Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 42); + init_u8_random_matrix(mat_b, DIM, DIM, 84); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] >>= SHIFT; + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_a, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c new file mode 100644 index 00000000..fbfad470 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c @@ -0,0 +1,71 @@ +#include "buckyball.h" +#include +#include +#include + +// Pointwise conv: batch=1, in_dim=1, in_channels=DIM, out_channels=DIM, +// kernel=1 Degenerates to a single DIM x DIM matmul (input[1x1xIC] * +// weight[1x1xICxOC]) +#define DIM 16 +#define BATCH 1 +#define IN_DIM 1 +#define OUT_DIM 1 +#define IN_CH DIM +#define OUT_CH DIM +#define KERNEL_DIM 1 + +// input layout: [batch, in_dim, in_dim, in_ch] = [1, 1, 1, 16] = 16 bytes +// weight layout: [krow, kcol, in_ch, out_ch] = [1, 1, 16, 16] = 256 bytes +// output layout: [batch, out_dim, out_dim, out_ch] = [1, 1, 1, 16] x 4 bytes = +// 64 bytes +static elem_t input[BATCH * IN_DIM * IN_DIM * IN_CH] + __attribute__((aligned(64))); +static elem_t weight[KERNEL_DIM * KERNEL_DIM * IN_CH * OUT_CH] + __attribute__((aligned(64))); +static result_t output[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); +static result_t expected[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS CISC Loop Conv Test ===\n"); + + // Initialize: input = 1x16 row vector, weight = 16x16 matrix + init_u8_random_matrix(input, IN_CH, 1, 42); + init_u8_random_matrix(weight, IN_CH, OUT_CH, 84); + + // CPU reference: output[0..OUT_CH] = sum_k(input[k] * weight[k][j]) + // cpu_matmul(A[M×K], B[K×N], C[M×N]) — here A=input(1×IN_CH), + // B=weight(IN_CH×OUT_CH) + cpu_matmul(input, weight, expected, 1, OUT_CH, IN_CH); + + // Strides: + // input_stride = in_ch * elemSize = 16 * 1 = 16 (bytes per spatial step) + // weight_stride = in_ch * out_ch * elemSize = 16 * 16 * 1 = 256 (bytes per + // kernel step) output_stride = out_ch * accBytes = 16 * 4 = 64 + bb_gemmini_config(0, 0, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_1(BATCH, IN_DIM, IN_CH); + bb_gemmini_loop_conv_ws_config_2(OUT_CH, OUT_DIM, 1, 0); + bb_gemmini_loop_conv_ws_config_3(KERNEL_DIM, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_4(0); // no bias + bb_gemmini_loop_conv_ws_config_5((uintptr_t)input); + bb_gemmini_loop_conv_ws_config_6((uintptr_t)weight); + bb_gemmini_loop_conv_ws_config_7((uintptr_t)output); + bb_gemmini_loop_conv_ws_config_8( + IN_CH, IN_CH * OUT_CH); // input_stride, weight_stride + bb_gemmini_loop_conv_ws_config_9(OUT_CH * 4); // output_stride (accBytes=4) + bb_gemmini_loop_conv_ws( + 0, 1, 2, 1); // bank_input=0, bank_weight=1, bank_output=2, no_bias=1 + bb_fence(); + + if (compare_u32_matrices(output, expected, 1, OUT_CH)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c new file mode 100644 index 00000000..6e6b17c1 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS RISC Basic Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 55); + init_u8_random_matrix(mat_b, DIM, DIM, 77); + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + // WS: bank_w=weights(B), bank_a=activations(A), bank_d=bias(0), bank_c=output + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_preload(bank_w, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c new file mode 100644 index 00000000..ec7c2b38 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c @@ -0,0 +1,48 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS RISC b_transpose Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 55); + init_u8_random_matrix(mat_b, DIM, DIM, 77); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 1, 0); + bb_gemmini_preload(bank_w, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c new file mode 100644 index 00000000..eb68f243 --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c @@ -0,0 +1,49 @@ +#include "buckyball.h" +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS RISC in_shift Test ===\n"); + + init_u8_random_matrix(mat_a, DIM, DIM, 55); + init_u8_random_matrix(mat_b, DIM, DIM, 77); + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] >>= SHIFT; + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_w, bank_c, DIM); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Test PASSED\n"); + return 0; + } + printf("Test FAILED\n"); + return 1; +} From f1c28359ae9c158bcd6a080882209119f70e2bad Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 17 Mar 2026 18:20:01 +0800 Subject: [PATCH 178/238] [arch] fix: fix bugs in gemminiball --- .../prototype/gemmini/GemminiExCtrl.scala | 159 ++++++++++++------ .../prototype/gemmini/configs/default.json | 8 +- bb-tests/sardine/tests/test_ctest.py | 114 ++++++------- .../toy/gemmini_os_cisc_atranspose_test.c | 4 +- .../CTest/toy/gemmini_os_cisc_basic_test.c | 4 +- .../toy/gemmini_os_cisc_btranspose_test.c | 4 +- .../CTest/toy/gemmini_os_cisc_shift_test.c | 4 +- .../toy/gemmini_os_risc_abtranspose_test.c | 4 +- .../toy/gemmini_os_risc_atranspose_test.c | 4 +- .../CTest/toy/gemmini_os_risc_basic_test.c | 4 +- .../toy/gemmini_os_risc_btranspose_test.c | 4 +- .../CTest/toy/gemmini_os_risc_shift_test.c | 4 +- .../src/CTest/toy/gemmini_ws_cisc_conv_test.c | 4 +- .../CTest/toy/gemmini_ws_risc_basic_test.c | 18 +- .../toy/gemmini_ws_risc_btranspose_test.c | 10 +- .../CTest/toy/gemmini_ws_risc_shift_test.c | 10 +- 16 files changed, 212 insertions(+), 147 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala index fcd041ec..00acbb5a 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala @@ -117,12 +117,13 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { io.wr_bank_o := wr_bank // Iteration counters - val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) - val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) - val skip_rows_cnt = RegInit(0.U(log2Up(DIM + 1).W)) // OS mode: count COMPUTE resp rows to discard - val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) - val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) - val req_sent = RegInit(false.B) // whether mesh.io.req has fired for this matmul + val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val skip_rows_cnt = RegInit(0.U(log2Up(DIM + 1).W)) // OS mode: count COMPUTE resp rows to discard + val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) + val req_sent = RegInit(false.B) // whether mesh.io.req has fired for this matmul + val preload_pad_cnt = RegInit(0.U(log2Up(DIM + 1).W)) // WS+b_transpose: extra transposer drain rows // Sub-command from special field (live wire, only valid when cmdReq is valid) val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) @@ -216,10 +217,11 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // Since cmdReq.fire and cmdResp can both happen in same cycle: state := sCommit }.elsewhen(sub_cmd === GemminiSubCmd.PRELOAD) { - read_row_cnt := 0.U - feed_row_cnt := 0.U - req_sent := false.B - state := sPreloadRead + read_row_cnt := 0.U + feed_row_cnt := 0.U + preload_pad_cnt := 0.U + req_sent := false.B + state := sPreloadRead }.elsewhen(sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED) { read_row_cnt := 0.U feed_row_cnt := 0.U @@ -240,18 +242,38 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // in sPreloadFeed to pre-fill the AlwaysOutTransposer for later use // in COMPUTE. The transposer accumulates A during PRELOAD, then // naturally outputs A rows during COMPUTE (after dir switch). - // WS mode: read weights (B/D) from op1_bank into rdQueue0 + // WS mode: read weights (B/D) from op1_bank into rdQueue0 in REVERSE row order. + // MeshWithDelays uses a shift-chain for d: d[0] enters PE[0] first, then + // propagates down via out_c. After DIM PROPAGATE cycles, PE[r].c1 = d[DIM-1-r]. + // To get PE[r].c1 = B[r][c] (correct WS weight layout), we must feed d in + // reverse: d[0]=B[DIM-1], d[1]=B[DIM-2], ..., d[DIM-1]=B[0]. + // Reading SRAM in reverse (addr DIM-1 down to 0) achieves this. // ----------------------------------------------------------------------- is(sPreloadRead) { - // Both OS and WS: read op1_bank (A for OS, B/D for WS) - when(read_row_cnt < total_rows) { - io.bankReadReq(0).valid := true.B - io.bankReadReq(0).bits.addr := read_row_cnt - when(io.bankReadReq(0).ready) { - read_row_cnt := read_row_cnt + 1.U + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS mode: read A in forward order + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := read_row_cnt + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed } }.otherwise { - state := sPreloadFeed + // WS mode: read weights. For WS+b_transpose we feed B rows 0..DIM-1 so the + // transposer outputs B's columns in order (col 0 = B[0][0],B[1][0],..). For WS + // without transpose, reverse row order is used for c1 <- d mapping. + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := Mux(cfg_b_transpose, read_row_cnt, total_rows - 1.U - read_row_cnt) + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } } } @@ -265,17 +287,25 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // in_prop XOR: 0 XOR 0 = 0 → PE prop=0 (COMPUTE): c1 stays, b accumulated // ----------------------------------------------------------------------- is(sPreloadFeed) { + val wsNeedTransposeDrain = cfg_dataflow =/= Dataflow.OS.id.U && cfg_b_transpose + val preload_rows = Wire(UInt(mesh.io.req.bits.total_rows.getWidth.W)) + preload_rows := total_rows + when(wsNeedTransposeDrain) { + preload_rows := total_rows +& total_rows + } + val preload_flush = 0.U + // Step 1: fire mesh.io.req (once) when(!req_sent) { mesh.io.req.valid := true.B mesh.io.req.bits.pe_control.dataflow := cfg_dataflow - mesh.io.req.bits.pe_control.propagate := ~cfg_dataflow // OS: propagate=1, WS: propagate=0 for preload + mesh.io.req.bits.pe_control.propagate := 1.U // OS: propagate=1 (PROPAGATE, preload A into transposer); WS: propagate=1 (PROPAGATE, c1=d stores weight) mesh.io.req.bits.pe_control.shift := cfg_in_shift mesh.io.req.bits.a_transpose := cfg_a_transpose mesh.io.req.bits.bd_transpose := cfg_b_transpose - mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.total_rows := preload_rows mesh.io.req.bits.tag.rob := rob_id_reg - mesh.io.req.bits.flush := 0.U + mesh.io.req.bits.flush := preload_flush when(mesh.io.req.fire) { req_sent := true.B } @@ -296,26 +326,38 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { mesh.io.d.valid := true.B mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) }.otherwise { - // WS mode: preload weights via b input + // WS mode: preload weights via d input (PE WS PROPAGATE: c1 = d) mesh.io.a.valid := true.B mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) mesh.io.b.valid := true.B - mesh.io.b.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + mesh.io.d.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) } when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { rdQueue0.io.deq.ready := true.B feed_row_cnt := feed_row_cnt + 1.U } } + }.elsewhen(req_sent && wsNeedTransposeDrain && preload_pad_cnt < total_rows) { + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + preload_pad_cnt := preload_pad_cnt + 1.U + } } // Step 3: all rows fed → commit when(req_sent && feed_row_cnt >= total_rows) { - io.cmdResp.valid := true.B - when(io.cmdResp.fire) { - state := sIdle + when(!wsNeedTransposeDrain || preload_pad_cnt >= total_rows) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } } } } @@ -366,25 +408,23 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // A comes from rdQueue0 (op1_bank), D from rdQueue1 (op2_bank) // ----------------------------------------------------------------------- is(sComputeFeed) { - // Collect/skip mesh output: - // WS mode: outputs A*B here (collect) - // OS mode: outputs c2=0 (garbage, discard but count for synchronization) + // Collect/skip mesh output during COMPUTE feed phase. + // WS mode: PRELOAD residual resp may still be trickling out here (the last few + // resp from PRELOAD's PROPAGATE phase overlap with the start of sComputeFeed). + // Discard all resp seen here; count them in skip_rows_cnt so that sDrain + // knows how many PRELOAD resp have already been flushed. + // OS mode: COMPUTE resp (c2=0, garbage); discard and count in skip_rows_cnt. when(mesh.io.resp.valid) { - when(cfg_dataflow =/= Dataflow.OS.id.U) { - outBuf(outBufRows) := mesh.io.resp.bits.data - outBufRows := outBufRows + 1.U - }.otherwise { - // OS mode: discard COMPUTE response (c2=0), just count - skip_rows_cnt := skip_rows_cnt + 1.U - } + skip_rows_cnt := skip_rows_cnt + 1.U } // Step 1: fire mesh.io.req (once) when(!req_sent) { mesh.io.req.valid := true.B mesh.io.req.bits.pe_control.dataflow := cfg_dataflow - // OS: propagate=1 → in_prop XOR: 1→0, PE prop=0 (COMPUTE), c1 accumulates A*B - // WS: propagate=1 → in_prop XOR: 0→1, PE prop=1 (PROPAGATE), outputs accumulated c1 + // MeshWithDelays applies req.propagate with XOR semantics on in_prop. + // After PRELOAD (req.propagate=1), WS compute must also send 1 to toggle + // effective PE mode from PROPAGATE -> COMPUTE. mesh.io.req.bits.pe_control.propagate := 1.U mesh.io.req.bits.pe_control.shift := cfg_in_shift mesh.io.req.bits.a_transpose := cfg_a_transpose @@ -418,18 +458,18 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { } } }.otherwise { - // WS mode: A from rdQueue0 (op1_bank), D from rdQueue1 (op2_bank) + // WS mode: activations from rdQueue0 via mesh.io.a, bias from rdQueue1 via mesh.io.b, d=0. + // Keep normal 3-way handshake to avoid mesh backpressure lockup. when(rdQueue0.io.deq.valid && rdQueue1.io.deq.valid) { - val a_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - val bd_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val act_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val bias_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) mesh.io.a.valid := true.B - mesh.io.a.bits := VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) - // WS: d carries input activations, b = 0 + mesh.io.a.bits := VecInit(act_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) mesh.io.b.valid := true.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.b.bits := VecInit(bias_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) mesh.io.d.valid := true.B - mesh.io.d.bits := VecInit(bd_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { rdQueue0.io.deq.ready := true.B @@ -443,8 +483,7 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // Step 3: all rows fed; OS mode waits until COMPUTE responses are discarded when(req_sent && feed_row_cnt >= total_rows) { when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: wait until all COMPUTE resp (c2=0) have been counted/discarded - // skip_rows_cnt is incremented whenever resp.valid is true (above) + // OS mode: wait until all COMPUTE resp (c2=0, garbage) have been discarded when(skip_rows_cnt >= total_rows) { // OS mode: mesh outputs C rows in REVERSE order (last tile row first). // Initialize outBufRows to total_rows-1 so first resp → outBuf[total_rows-1], @@ -455,8 +494,11 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { state := sComputeFlush } }.otherwise { - // WS: output already collected during feed - state := sDrain + // WS: COMPUTE resp will appear in sDrain after the pipeline drains. + // skip_rows_cnt already tracks how many PRELOAD resp have been seen here; + // sDrain will skip the remaining PRELOAD resp (total_rows - skip_rows_cnt). + outBufRows := 0.U + state := sDrain } } } @@ -522,7 +564,7 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { outBufRows := outBufRows - 1.U outBufCollected := outBufCollected + 1.U }.otherwise { - // WS mode: forward collection + // WS mode: collect responses directly. outBuf(outBufRows) := mesh.io.resp.bits.data outBufRows := outBufRows + 1.U } @@ -550,9 +592,18 @@ class GemminiExCtrl(val b: GlobalConfig) extends Module { // ----------------------------------------------------------------------- is(sStore) { when(store_row_cnt < total_rows) { - val row = outBuf(store_row_cnt) - val flat_row = VecInit(row.flatten) // Vec of DIM SInt(accWidth) - val row_bits = Cat(flat_row.reverse.map(_.asUInt)) // DIM * accWidth total bits + val row = outBuf(store_row_cnt) + // MeshWithDelays d path reverses element order within each write-port chunk. + // For WS+b_transpose we reverse each chunk so stored order is col0..col15. + val flat_raw = VecInit(row.flatten) + val tileW = b.memDomain.bankWidth / config.accWidth + val flat_order = VecInit((0 until DIM).map { i => + val t = i / tileW + val j = t * tileW + (tileW - 1 - (i % tileW)) + Mux(cfg_dataflow =/= Dataflow.OS.id.U && cfg_b_transpose, flat_raw(j), flat_raw(i)) + }) + val flat_row = VecInit(flat_order.map(x => (x >> cfg_in_shift).asSInt)) + val row_bits = Cat(flat_row.reverse.map(_.asUInt)) val bitsPerPort = b.memDomain.bankWidth diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json index 4299a30f..44eea666 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json @@ -1,8 +1,8 @@ { - "meshRows": 4, - "meshColumns": 4, - "tileRows": 4, - "tileColumns": 4, + "meshRows": 16, + "meshColumns": 16, + "tileRows": 1, + "tileColumns": 1, "inputWidth": 8, "accWidth": 32, "tileLatency": 0, diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index ea598d63..554caee8 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -15,6 +15,62 @@ # Define all ctest workloads with absolute paths and corresponding IDs ctest_workloads = [ + ( + "ctest_tlb_test_singlecore-baremetal", + "ctest_tlb_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", + "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", + "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", + "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", + "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", + "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", + "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", + "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", + "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", + "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", + ), + ( + "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", + "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", + ), ( "ctest_mvin_mvout_test_singlecore-baremetal", "ctest_mvin_mvout_test_singlecore-baremetal", @@ -91,62 +147,6 @@ "ctest_dequant_test_singlecore-baremetal", "ctest_dequant_test_singlecore-baremetal", ), - ( - "ctest_tlb_test_singlecore-baremetal", - "ctest_tlb_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", - "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", - "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", - "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", - "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", - "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", - "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", - "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", - "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", - "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", - ), ] @@ -162,7 +162,7 @@ def test_ctest_workload_debug( ): caplog.set_level(logging.INFO) - time.sleep(test_index * 20) + time.sleep(test_index * 15) start_time = time.time() coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c index 171a605a..a76635ad 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c @@ -35,9 +35,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS CISC a_transpose Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS CISC a_transpose Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c index 05744b89..ee8298ca 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c @@ -33,9 +33,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS CISC Basic Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS CISC Basic Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c index 9d484f25..8a59b615 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c @@ -35,9 +35,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS CISC b_transpose Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS CISC b_transpose Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c index cc59230a..38698d03 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c @@ -36,9 +36,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS CISC in_shift Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS CISC in_shift Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c index 3f97c8ac..004ccd8c 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c @@ -38,9 +38,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS RISC ab_transpose Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS RISC ab_transpose Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c index 6391b356..1d3a6da9 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c @@ -36,9 +36,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS RISC a_transpose Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS RISC a_transpose Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c index a74f399f..cf721ce2 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c @@ -34,9 +34,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS RISC Basic Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS RISC Basic Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c index 72a26432..05c16d9b 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c @@ -36,9 +36,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS RISC b_transpose Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS RISC b_transpose Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c index 50fc68de..382cf066 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c @@ -37,9 +37,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini OS RISC in_shift Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini OS RISC in_shift Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c index fbfad470..7f26bf8f 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c @@ -63,9 +63,9 @@ int main() { bb_fence(); if (compare_u32_matrices(output, expected, 1, OUT_CH)) { - printf("Test PASSED\n"); + printf("Gemmini WS CISC Loop Conv Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini WS CISC Loop Conv Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c index 6e6b17c1..15af17b1 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c @@ -18,10 +18,14 @@ int main() { setvbuf(stdout, NULL, _IONBF, 0); printf("=== Gemmini WS RISC Basic Test ===\n"); - init_u8_random_matrix(mat_a, DIM, DIM, 55); - init_u8_random_matrix(mat_b, DIM, DIM, 77); + // Deterministic: mat_a[i] = i+1, mat_b[i] = 2*(i+1) (mod 128) + for (int i = 0; i < DIM * DIM; i++) { + mat_a[i] = (elem_t)((i + 1) % 128); + mat_b[i] = (elem_t)((2 * (i + 1)) % 128); + } clear_u8_matrix(mat_d, DIM, DIM); cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + printf("expected[0] = %d\n", (int)expected[0]); // WS: bank_w=weights(B), bank_a=activations(A), bank_d=bias(0), bank_c=output uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; @@ -39,9 +43,15 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini WS RISC Basic Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + // // Print first few mismatches + // for (int i = 0; i < DIM * DIM && i < 8; i++) { + // if (mat_c[i] != expected[i]) + // printf(" [%d] got=%d expected=%d\n", i, (int)mat_c[i], + // (int)expected[i]); + // } + // printf("Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c index ec7c2b38..99109b41 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c @@ -19,8 +19,10 @@ int main() { setvbuf(stdout, NULL, _IONBF, 0); printf("=== Gemmini WS RISC b_transpose Test ===\n"); - init_u8_random_matrix(mat_a, DIM, DIM, 55); - init_u8_random_matrix(mat_b, DIM, DIM, 77); + for (int i = 0; i < DIM * DIM; i++) { + mat_a[i] = (elem_t)((i + 1) % 128); + mat_b[i] = (elem_t)((2 * (i + 1)) % 128); + } transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); clear_u8_matrix(mat_d, DIM, DIM); cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); @@ -40,9 +42,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini WS RISC b_transpose Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini WS RISC b_transpose Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c index eb68f243..40364f1d 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c @@ -19,8 +19,10 @@ int main() { setvbuf(stdout, NULL, _IONBF, 0); printf("=== Gemmini WS RISC in_shift Test ===\n"); - init_u8_random_matrix(mat_a, DIM, DIM, 55); - init_u8_random_matrix(mat_b, DIM, DIM, 77); + for (int i = 0; i < DIM * DIM; i++) { + mat_a[i] = (elem_t)((i + 1) % 128); + mat_b[i] = (elem_t)((2 * (i + 1)) % 128); + } clear_u8_matrix(mat_d, DIM, DIM); cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); for (int i = 0; i < DIM * DIM; i++) @@ -41,9 +43,9 @@ int main() { bb_fence(); if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { - printf("Test PASSED\n"); + printf("Gemmini WS RISC in_shift Test PASSED\n"); return 0; } - printf("Test FAILED\n"); + printf("Gemmini WS RISC in_shift Test FAILED\n"); return 1; } From 2cc269a580b312d0f358412764ee459876f8a025 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 20 Mar 2026 06:13:38 +0800 Subject: [PATCH 179/238] [arch] fix: fix bugs in gemminiball --- .../prototype/gemmini/GemminiBall.scala | 26 +- .../prototype/gemmini/GemminiExCtrl.scala | 677 +----------------- .../gemmini/GemminiExCtrlCmdStates.scala | 73 ++ .../GemminiExCtrlComputeFeedState.scala | 68 ++ .../GemminiExCtrlComputeReadState.scala | 27 + .../gemmini/GemminiExCtrlDefaults.scala | 44 ++ .../prototype/gemmini/GemminiExCtrlDefs.scala | 103 +++ .../prototype/gemmini/GemminiExCtrlFsm.scala | 43 ++ .../gemmini/GemminiExCtrlPreloadStates.scala | 84 +++ .../gemmini/GemminiExCtrlStoreOps.scala | 104 +++ .../gemmini/GemminiExCtrlTypes.scala | 19 + bb-tests/sardine/tests/test_ctest.py | 40 -- .../toy/gemmini_os_cisc_atranspose_test.c | 2 +- .../CTest/toy/gemmini_os_cisc_basic_test.c | 8 +- .../toy/gemmini_os_cisc_btranspose_test.c | 2 +- .../CTest/toy/gemmini_os_cisc_shift_test.c | 2 +- .../toy/gemmini_os_risc_abtranspose_test.c | 2 +- .../toy/gemmini_os_risc_atranspose_test.c | 2 +- .../CTest/toy/gemmini_os_risc_basic_test.c | 38 +- .../toy/gemmini_os_risc_btranspose_test.c | 2 +- .../CTest/toy/gemmini_os_risc_shift_test.c | 2 +- .../src/CTest/toy/gemmini_ws_cisc_conv_test.c | 2 +- .../CTest/toy/gemmini_ws_risc_basic_test.c | 10 - .../toy/gemmini_ws_risc_btranspose_test.c | 2 +- .../CTest/toy/gemmini_ws_risc_shift_test.c | 2 +- 25 files changed, 640 insertions(+), 744 deletions(-) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlCmdStates.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeFeedState.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeReadState.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefaults.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlFsm.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlPreloadStates.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlTypes.scala diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala index dd685459..cfc26d46 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiBall.scala @@ -46,6 +46,8 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall // ========================================================================= val funct7 = io.cmdReq.bits.cmd.funct7 + val rs2Data = io.cmdReq.bits.cmd.special + val isConfig = funct7 === 0x02.U // GEMMINI_CONFIG (enable=000, opcode=2) val isPreload = funct7 === 0x35.U // GEMMINI_PRELOAD (enable=011, opcode=5) val isComputePre = funct7 === 0x42.U // GEMMINI_COMPUTE_PRELOADED (enable=100, opcode=2) @@ -61,8 +63,8 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall // ========================================================================= // ExUnit path (non-Loop: CONFIG/PRELOAD/COMPUTE/FLUSH) // ========================================================================= - exCtrl.io.cmdReq.valid := io.cmdReq.valid && isExUnit - exCtrl.io.cmdReq.bits := io.cmdReq.bits + exCtrl.exio.cmdReq.valid := io.cmdReq.valid && isExUnit + exCtrl.exio.cmdReq.bits := io.cmdReq.bits // ========================================================================= // Config latch path (immediate cmdResp) @@ -71,8 +73,6 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall val configRespBits = Reg(new BallRsComplete(b)) configRespValid := false.B // default: pulse - val rs2Data = io.cmdReq.bits.cmd.special - when(io.cmdReq.fire && isLoopWsConfig) { configRespValid := true.B configRespBits.rob_id := io.cmdReq.bits.rob_id @@ -185,7 +185,7 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall // ========================================================================= io.cmdReq.ready := Mux( isExUnit, - exCtrl.io.cmdReq.ready, + exCtrl.exio.cmdReq.ready, Mux( isLoopWsConfig || isLoopConvConfig, true.B, @@ -200,7 +200,7 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall // ========================================================================= // cmdResp: mux between exUnit and config immediate response // ========================================================================= - io.cmdResp <> exCtrl.io.cmdResp + io.cmdResp <> exCtrl.exio.cmdResp when(configRespValid) { io.cmdResp.valid := true.B io.cmdResp.bits := configRespBits @@ -210,24 +210,24 @@ class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBall // Bank connections (unchanged from original) // ========================================================================= for (i <- 0 until inBW) { - io.bankRead(i).io.req <> exCtrl.io.bankReadReq(i) - exCtrl.io.bankReadResp(i) <> io.bankRead(i).io.resp + io.bankRead(i).io.req <> exCtrl.exio.bankReadReq(i) + exCtrl.exio.bankReadResp(i) <> io.bankRead(i).io.resp io.bankRead(i).rob_id := rob_id_reg io.bankRead(i).ball_id := 0.U io.bankRead(i).group_id := 0.U } - io.bankRead(0).bank_id := exCtrl.io.op1_bank_o + io.bankRead(0).bank_id := exCtrl.exio.op1_bank_o if (inBW > 1) { - io.bankRead(1).bank_id := exCtrl.io.op2_bank_o + io.bankRead(1).bank_id := exCtrl.exio.op2_bank_o } for (i <- 0 until outBW) { - io.bankWrite(i).io <> exCtrl.io.bankWrite(i) - io.bankWrite(i).bank_id := exCtrl.io.wr_bank_o + io.bankWrite(i).io <> exCtrl.exio.bankWrite(i) + io.bankWrite(i).bank_id := exCtrl.exio.wr_bank_o io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).ball_id := 0.U io.bankWrite(i).group_id := i.U } - io.status <> exCtrl.io.status + io.status <> exCtrl.exio.status } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala index 00acbb5a..d23f1506 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrl.scala @@ -1,674 +1,25 @@ package framework.balldomain.prototype.gemmini import chisel3._ -import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} -import framework.memdomain.backend.banks.{SramReadReq, SramReadResp, SramWriteIO} import framework.top.GlobalConfig -import framework.balldomain.prototype.gemmini.configs.GemminiBallParam -import gemmini._ -import gemmini.Util._ -/** Minimal tag for MeshWithDelays that satisfies TagQueueTag */ -class SimpleTag extends Bundle with TagQueueTag { - val rob = UInt(8.W) - override def make_this_garbage(dummy: Int = 0): Unit = - rob := 0.U -} - -/** Sub-command encoding within the special field */ -object GemminiSubCmd { - val CONFIG = 0.U(4.W) - val PRELOAD = 1.U(4.W) - val COMPUTE_PRELOADED = 2.U(4.W) - val COMPUTE_ACCUMULATED = 3.U(4.W) - val FLUSH = 4.U(4.W) -} - -/** - * GemminiExCtrl — Execute controller adapter for MeshWithDelays. - * - * Receives BallRsIssue commands (config / preload / compute / flush), - * drives gemmini.MeshWithDelays, reads data from SRAM banks, and - * writes results back to SRAM banks. - */ @instantiable -class GemminiExCtrl(val b: GlobalConfig) extends Module { - val config = GemminiBallParam() - val DIM = config.blockSize // e.g., 16 - - val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "GemminiBall") - .getOrElse(throw new IllegalArgumentException("GemminiBall not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW - - val inputType = SInt(config.inputWidth.W) - val accType = SInt(config.accWidth.W) - val outputType = SInt(config.accWidth.W) - - @public - val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) - val cmdResp = Decoupled(new BallRsComplete(b)) - val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) - val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) - val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) - val op1_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val op2_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val wr_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) - val status = new BallStatus - }) - - // ========================================================================= - // Instantiate Gemmini's MeshWithDelays (the real systolic array) - // ========================================================================= - val mesh = Module(new MeshWithDelays( - inputType = inputType, - outputType = outputType, - accType = accType, - tagType = new SimpleTag, - df = Dataflow.BOTH, - tree_reduction = false, - tile_latency = config.tileLatency, - output_delay = config.outputDelay, - tileRows = config.tileRows, - tileColumns = config.tileColumns, - meshRows = config.meshRows, - meshColumns = config.meshColumns, - leftBanks = 1, - upBanks = 1, - n_simultaneous_matmuls = 5 - )) - - // ========================================================================= - // Configuration registers (updated by CONFIG sub-command) - // ========================================================================= - val cfg_dataflow = RegInit(0.U(1.W)) // 0=OS, 1=WS - val cfg_activation = RegInit(0.U(2.W)) // 0=none, 1=relu - val cfg_a_transpose = RegInit(false.B) - val cfg_b_transpose = RegInit(false.B) - val cfg_in_shift = RegInit(0.U(log2Up(config.accWidth).W)) - - // ========================================================================= - // State machine - // ========================================================================= - val sIdle :: sPreloadReq :: sPreloadRead :: sPreloadFeed :: sComputeReq :: sComputeRead :: sComputeFeed :: sComputeFlush :: sFlush :: sDrain :: sStore :: sCommit :: Nil = - Enum(12) - val state = RegInit(sIdle) - - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - val is_sub_reg = RegInit(false.B) - val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) - - // Saved rs1/rs2 from the command (latched at sIdle when cmdReq fires) - val saved_rs1 = Reg(UInt(64.W)) - val saved_rs2 = Reg(UInt(64.W)) - val saved_sub_cmd = Reg(UInt(4.W)) - - // Bank addressing - val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - - io.op1_bank_o := op1_bank - io.op2_bank_o := op2_bank - io.wr_bank_o := wr_bank - - // Iteration counters - val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) - val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) - val skip_rows_cnt = RegInit(0.U(log2Up(DIM + 1).W)) // OS mode: count COMPUTE resp rows to discard - val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) - val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) - val req_sent = RegInit(false.B) // whether mesh.io.req has fired for this matmul - val preload_pad_cnt = RegInit(0.U(log2Up(DIM + 1).W)) // WS+b_transpose: extra transposer drain rows - - // Sub-command from special field (live wire, only valid when cmdReq is valid) - val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) - - // Read response queues - val rdQueue0 = Module(new Queue(new SramReadResp(b), entries = DIM)) - val rdQueue1 = Module(new Queue(new SramReadResp(b), entries = DIM)) - rdQueue0.io.enq <> io.bankReadResp(0) - rdQueue1.io.enq <> io.bankReadResp(1) - - // Output buffer: collect mesh responses row by row - val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, outputType)))) - val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) - // OS mode: mesh outputs C rows in REVERSE order (last tile row first). - // outBufCollected counts how many resp rows have been collected (0..total_rows) - val outBufCollected = RegInit(0.U(log2Up(DIM + 1).W)) - - // Per-port write completion tracking for sStore - val port_written = RegInit(VecInit(Seq.fill(outBW)(false.B))) - - // ========================================================================= - // Defaults - // ========================================================================= - io.cmdReq.ready := state === sIdle - - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg - io.cmdResp.bits.is_sub := is_sub_reg - io.cmdResp.bits.sub_rob_id := sub_rob_id_reg - - for (i <- 0 until inBW) { - io.bankReadReq(i).valid := false.B - io.bankReadReq(i).bits.addr := 0.U - } - - rdQueue0.io.deq.ready := false.B - rdQueue1.io.deq.ready := false.B - - mesh.io.a.valid := false.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) - mesh.io.b.valid := false.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) - mesh.io.d.valid := false.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - mesh.io.req.valid := false.B - mesh.io.req.bits := 0.U.asTypeOf(mesh.io.req.bits) - - io.bankWrite.foreach { bw => - bw.req.valid := false.B - bw.req.bits.addr := 0.U - bw.req.bits.data := 0.U - bw.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) - bw.req.bits.wmode := true.B - bw.resp.ready := true.B - } - - // ========================================================================= - // State Machine - // ========================================================================= - switch(state) { - - // ----------------------------------------------------------------------- - // IDLE: accept new command, latch rs1/rs2/sub_cmd - // ----------------------------------------------------------------------- - is(sIdle) { - io.cmdReq.ready := true.B - when(io.cmdReq.fire) { - rob_id_reg := io.cmdReq.bits.rob_id - is_sub_reg := io.cmdReq.bits.is_sub - sub_rob_id_reg := io.cmdReq.bits.sub_rob_id - op1_bank := io.cmdReq.bits.cmd.op1_bank - op2_bank := io.cmdReq.bits.cmd.op2_bank - wr_bank := io.cmdReq.bits.cmd.wr_bank - saved_rs1 := io.cmdReq.bits.cmd.rs1 - saved_rs2 := io.cmdReq.bits.cmd.rs2 - saved_sub_cmd := sub_cmd - total_rows := Mux(io.cmdReq.bits.cmd.iter === 0.U, DIM.U, io.cmdReq.bits.cmd.iter) - - when(sub_cmd === GemminiSubCmd.CONFIG) { - // CONFIG: decode from special field (rs2 with sub_cmd in [3:0]) - // Config params start at bit 4: [4]=dataflow, [6:5]=activation, [7]=a_transpose, [8]=b_transpose, - // [40:9]=in_shift - cfg_dataflow := io.cmdReq.bits.cmd.special(4) - cfg_activation := io.cmdReq.bits.cmd.special(6, 5) - cfg_a_transpose := io.cmdReq.bits.cmd.special(7) - cfg_b_transpose := io.cmdReq.bits.cmd.special(8) - cfg_in_shift := io.cmdReq.bits.cmd.special(log2Up(config.accWidth) + 8, 9) - // Commit immediately - io.cmdResp.valid := true.B - // Stay in sIdle if resp fires, else we need a config state - // Since cmdReq.fire and cmdResp can both happen in same cycle: - state := sCommit - }.elsewhen(sub_cmd === GemminiSubCmd.PRELOAD) { - read_row_cnt := 0.U - feed_row_cnt := 0.U - preload_pad_cnt := 0.U - req_sent := false.B - state := sPreloadRead - }.elsewhen(sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED) { - read_row_cnt := 0.U - feed_row_cnt := 0.U - skip_rows_cnt := 0.U - outBufRows := 0.U - outBufCollected := 0.U - req_sent := false.B - state := sComputeRead - }.elsewhen(sub_cmd === GemminiSubCmd.FLUSH) { - state := sFlush - } - } - } - - // ----------------------------------------------------------------------- - // PRELOAD_READ: read A matrix (OS mode) or B/D weights (WS mode) from SRAM - // OS mode: read A from op1_bank into rdQueue0, then send A through transposer - // in sPreloadFeed to pre-fill the AlwaysOutTransposer for later use - // in COMPUTE. The transposer accumulates A during PRELOAD, then - // naturally outputs A rows during COMPUTE (after dir switch). - // WS mode: read weights (B/D) from op1_bank into rdQueue0 in REVERSE row order. - // MeshWithDelays uses a shift-chain for d: d[0] enters PE[0] first, then - // propagates down via out_c. After DIM PROPAGATE cycles, PE[r].c1 = d[DIM-1-r]. - // To get PE[r].c1 = B[r][c] (correct WS weight layout), we must feed d in - // reverse: d[0]=B[DIM-1], d[1]=B[DIM-2], ..., d[DIM-1]=B[0]. - // Reading SRAM in reverse (addr DIM-1 down to 0) achieves this. - // ----------------------------------------------------------------------- - is(sPreloadRead) { - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: read A in forward order - when(read_row_cnt < total_rows) { - io.bankReadReq(0).valid := true.B - io.bankReadReq(0).bits.addr := read_row_cnt - when(io.bankReadReq(0).ready) { - read_row_cnt := read_row_cnt + 1.U - } - }.otherwise { - state := sPreloadFeed - } - }.otherwise { - // WS mode: read weights. For WS+b_transpose we feed B rows 0..DIM-1 so the - // transposer outputs B's columns in order (col 0 = B[0][0],B[1][0],..). For WS - // without transpose, reverse row order is used for c1 <- d mapping. - when(read_row_cnt < total_rows) { - io.bankReadReq(0).valid := true.B - io.bankReadReq(0).bits.addr := Mux(cfg_b_transpose, read_row_cnt, total_rows - 1.U - read_row_cnt) - when(io.bankReadReq(0).ready) { - read_row_cnt := read_row_cnt + 1.U - } - }.otherwise { - state := sPreloadFeed - } - } - } - - // ----------------------------------------------------------------------- - // PRELOAD_FEED: send req to mesh, then feed data row by row - // For OS mode: preload A through transposer (a=A, b=0, d=0); propagate=1 - // in_prop XOR: 0 XOR 1 = 1 → PE prop=1 (PROPAGATE): c1=d=0, outputs old c1 - // After DIM rows of A, AlwaysOutTransposer dir flips; during COMPUTE, - // transposer outputs the A rows (as needed by systolic array). - // For WS mode: preload weights via b input (a=0, b=B, d=0); propagate=0 - // in_prop XOR: 0 XOR 0 = 0 → PE prop=0 (COMPUTE): c1 stays, b accumulated - // ----------------------------------------------------------------------- - is(sPreloadFeed) { - val wsNeedTransposeDrain = cfg_dataflow =/= Dataflow.OS.id.U && cfg_b_transpose - val preload_rows = Wire(UInt(mesh.io.req.bits.total_rows.getWidth.W)) - preload_rows := total_rows - when(wsNeedTransposeDrain) { - preload_rows := total_rows +& total_rows - } - val preload_flush = 0.U - - // Step 1: fire mesh.io.req (once) - when(!req_sent) { - mesh.io.req.valid := true.B - mesh.io.req.bits.pe_control.dataflow := cfg_dataflow - mesh.io.req.bits.pe_control.propagate := 1.U // OS: propagate=1 (PROPAGATE, preload A into transposer); WS: propagate=1 (PROPAGATE, c1=d stores weight) - mesh.io.req.bits.pe_control.shift := cfg_in_shift - mesh.io.req.bits.a_transpose := cfg_a_transpose - mesh.io.req.bits.bd_transpose := cfg_b_transpose - mesh.io.req.bits.total_rows := preload_rows - mesh.io.req.bits.tag.rob := rob_id_reg - mesh.io.req.bits.flush := preload_flush - when(mesh.io.req.fire) { - req_sent := true.B - } - } - - // Step 2: feed data rows (only after req has fired) - when(req_sent && feed_row_cnt < total_rows) { - when(rdQueue0.io.deq.valid) { - val row_data = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: feed A matrix through mesh.io.a → AlwaysOutTransposer - // This pre-fills the transposer (DIM rows → dir flips to UP mode) - // During COMPUTE, transposer outputs A rows from the top - mesh.io.a.valid := true.B - mesh.io.a.bits := VecInit(row_data.grouped(config.tileRows).map(g => VecInit(g)).toSeq) - mesh.io.b.valid := true.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) - mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - }.otherwise { - // WS mode: preload weights via d input (PE WS PROPAGATE: c1 = d) - mesh.io.a.valid := true.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) - mesh.io.b.valid := true.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) - mesh.io.d.valid := true.B - mesh.io.d.bits := VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) - } - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { - rdQueue0.io.deq.ready := true.B - feed_row_cnt := feed_row_cnt + 1.U - } - } - }.elsewhen(req_sent && wsNeedTransposeDrain && preload_pad_cnt < total_rows) { - mesh.io.a.valid := true.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) - mesh.io.b.valid := true.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) - mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { - preload_pad_cnt := preload_pad_cnt + 1.U - } - } - - // Step 3: all rows fed → commit - when(req_sent && feed_row_cnt >= total_rows) { - when(!wsNeedTransposeDrain || preload_pad_cnt >= total_rows) { - io.cmdResp.valid := true.B - when(io.cmdResp.fire) { - state := sIdle - } - } - } - } - - // ----------------------------------------------------------------------- - // COMPUTE_READ: read operands from SRAM banks - // OS mode: only read B matrix from op2_bank (port 1) - // A matrix was already sent to transposer during PRELOAD - // WS mode: read A from op1_bank (port 0) and D from op2_bank (port 1) - // ----------------------------------------------------------------------- - is(sComputeRead) { - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: only read B from op2_bank - when(read_row_cnt < total_rows) { - io.bankReadReq(1).valid := true.B - io.bankReadReq(1).bits.addr := read_row_cnt - when(io.bankReadReq(1).ready) { - read_row_cnt := read_row_cnt + 1.U - } - }.otherwise { - state := sComputeFeed - } - }.otherwise { - // WS mode: read A from op1_bank (port 0) and D from op2_bank (port 1) - when(read_row_cnt < total_rows) { - io.bankReadReq(0).valid := true.B - io.bankReadReq(0).bits.addr := read_row_cnt - io.bankReadReq(1).valid := true.B - io.bankReadReq(1).bits.addr := read_row_cnt - - when(io.bankReadReq(0).ready && io.bankReadReq(1).ready) { - read_row_cnt := read_row_cnt + 1.U - } - }.otherwise { - state := sComputeFeed - } - } - } - - // ----------------------------------------------------------------------- - // COMPUTE_FEED: send req to mesh, then feed A and B/D row by row - // OS mode: propagate=1 → in_prop XOR: 1 XOR 1 = 0 → PE prop=0 (COMPUTE) - // PE accumulates A*B into c1, outputs c2 (old/zero, discarded) - // A comes from AlwaysOutTransposer (pre-filled during PRELOAD); send a=0 - // B comes from rdQueue1 (op2_bank) - // WS mode: propagate=1 → in_prop XOR: 0 XOR 1 = 1 → PE prop=1 (PROPAGATE) - // PE outputs c1 (weights * activations), b passes through - // A comes from rdQueue0 (op1_bank), D from rdQueue1 (op2_bank) - // ----------------------------------------------------------------------- - is(sComputeFeed) { - // Collect/skip mesh output during COMPUTE feed phase. - // WS mode: PRELOAD residual resp may still be trickling out here (the last few - // resp from PRELOAD's PROPAGATE phase overlap with the start of sComputeFeed). - // Discard all resp seen here; count them in skip_rows_cnt so that sDrain - // knows how many PRELOAD resp have already been flushed. - // OS mode: COMPUTE resp (c2=0, garbage); discard and count in skip_rows_cnt. - when(mesh.io.resp.valid) { - skip_rows_cnt := skip_rows_cnt + 1.U - } - - // Step 1: fire mesh.io.req (once) - when(!req_sent) { - mesh.io.req.valid := true.B - mesh.io.req.bits.pe_control.dataflow := cfg_dataflow - // MeshWithDelays applies req.propagate with XOR semantics on in_prop. - // After PRELOAD (req.propagate=1), WS compute must also send 1 to toggle - // effective PE mode from PROPAGATE -> COMPUTE. - mesh.io.req.bits.pe_control.propagate := 1.U - mesh.io.req.bits.pe_control.shift := cfg_in_shift - mesh.io.req.bits.a_transpose := cfg_a_transpose - mesh.io.req.bits.bd_transpose := cfg_b_transpose - mesh.io.req.bits.total_rows := total_rows - mesh.io.req.bits.tag.rob := rob_id_reg - mesh.io.req.bits.flush := 0.U - when(mesh.io.req.fire) { - req_sent := true.B - } - } - - // Step 2: feed data rows (only after req has fired) - when(req_sent && feed_row_cnt < total_rows) { - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: A from transposer (pre-filled during PRELOAD); send a=0 to mesh.io.a - // B from rdQueue1 (op2_bank) - when(rdQueue1.io.deq.valid) { - val b_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - // a=0: transposer already outputs A rows (accumulated during PRELOAD phase dir=LEFT) - // After PRELOAD's DIM rows, transposer dir flips to UP, outputting A rows - mesh.io.a.valid := true.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) // a=0: let transposer output PRELOAD A - mesh.io.b.valid := true.B - mesh.io.b.bits := VecInit(b_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) - mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) // d=0: don't overwrite c1 - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { - rdQueue1.io.deq.ready := true.B - feed_row_cnt := feed_row_cnt + 1.U - } - } - }.otherwise { - // WS mode: activations from rdQueue0 via mesh.io.a, bias from rdQueue1 via mesh.io.b, d=0. - // Keep normal 3-way handshake to avoid mesh backpressure lockup. - when(rdQueue0.io.deq.valid && rdQueue1.io.deq.valid) { - val act_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - val bias_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) - - mesh.io.a.valid := true.B - mesh.io.a.bits := VecInit(act_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) - mesh.io.b.valid := true.B - mesh.io.b.bits := VecInit(bias_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) - mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { - rdQueue0.io.deq.ready := true.B - rdQueue1.io.deq.ready := true.B - feed_row_cnt := feed_row_cnt + 1.U - } - } - } - } - - // Step 3: all rows fed; OS mode waits until COMPUTE responses are discarded - when(req_sent && feed_row_cnt >= total_rows) { - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: wait until all COMPUTE resp (c2=0, garbage) have been discarded - when(skip_rows_cnt >= total_rows) { - // OS mode: mesh outputs C rows in REVERSE order (last tile row first). - // Initialize outBufRows to total_rows-1 so first resp → outBuf[total_rows-1], - // last resp → outBuf[0], reversing back to correct row order. - outBufRows := total_rows - 1.U - outBufCollected := 0.U - req_sent := false.B - state := sComputeFlush - } - }.otherwise { - // WS: COMPUTE resp will appear in sDrain after the pipeline drains. - // skip_rows_cnt already tracks how many PRELOAD resp have been seen here; - // sDrain will skip the remaining PRELOAD resp (total_rows - skip_rows_cnt). - outBufRows := 0.U - state := sDrain - } - } - } - - // ----------------------------------------------------------------------- - // COMPUTE_FLUSH (OS mode only): issue flush req with propagate=1 - // in_prop XOR: 0 XOR 1 = 1 → PE prop=1 (PROPAGATE) → outputs c1 (A*B result) - // Feed zeros to advance rows through the pipeline - // ----------------------------------------------------------------------- - is(sComputeFlush) { - // Collect mesh output (this is the real A*B result from c1) - // OS PROPAGATE outputs rows in reverse: last tile row first, first tile row last. - // Count down outBufRows so outBuf[total_rows-1] = first resp, outBuf[0] = last resp. - when(mesh.io.resp.valid) { - outBuf(outBufRows) := mesh.io.resp.bits.data - outBufRows := outBufRows - 1.U - outBufCollected := outBufCollected + 1.U - } - - when(!req_sent) { - mesh.io.req.valid := true.B - mesh.io.req.bits.pe_control.dataflow := cfg_dataflow - mesh.io.req.bits.pe_control.propagate := 1.U // XOR: 0→1, PE prop=1, outputs c1 - mesh.io.req.bits.pe_control.shift := cfg_in_shift - mesh.io.req.bits.a_transpose := cfg_a_transpose - mesh.io.req.bits.bd_transpose := cfg_b_transpose - mesh.io.req.bits.total_rows := total_rows - mesh.io.req.bits.tag.rob := rob_id_reg - mesh.io.req.bits.flush := 0.U - when(mesh.io.req.fire) { - req_sent := true.B - feed_row_cnt := 0.U - } - } - - // Feed zeros to advance pipeline - when(req_sent && feed_row_cnt < total_rows) { - mesh.io.a.valid := true.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) - mesh.io.b.valid := true.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) - mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { - feed_row_cnt := feed_row_cnt + 1.U - } - } - - // All flush rows fed → proceed to drain to collect any remaining responses - when(req_sent && feed_row_cnt >= total_rows) { - state := sDrain - } - } - - // ----------------------------------------------------------------------- - // DRAIN: wait for remaining mesh responses - // ----------------------------------------------------------------------- - is(sDrain) { - when(mesh.io.resp.valid) { - when(cfg_dataflow === Dataflow.OS.id.U) { - // OS mode: continue reverse collection - outBuf(outBufRows) := mesh.io.resp.bits.data - outBufRows := outBufRows - 1.U - outBufCollected := outBufCollected + 1.U - }.otherwise { - // WS mode: collect responses directly. - outBuf(outBufRows) := mesh.io.resp.bits.data - outBufRows := outBufRows + 1.U - } - } - when(cfg_dataflow === Dataflow.OS.id.U) { - when(outBufCollected >= total_rows) { - store_row_cnt := 0.U - port_written.foreach(_ := false.B) - state := sStore - } - }.otherwise { - when(outBufRows >= total_rows) { - store_row_cnt := 0.U - port_written.foreach(_ := false.B) - state := sStore - } - } - } - - // ----------------------------------------------------------------------- - // STORE: write results back to SRAM bank - // Each row: DIM elements × accWidth bits = 512 bits - // bankWidth = 128 bits, outBW = 4 write ports → 4×128 = 512 bits per cycle - // Use per-port written flags to handle non-simultaneous ready signals - // ----------------------------------------------------------------------- - is(sStore) { - when(store_row_cnt < total_rows) { - val row = outBuf(store_row_cnt) - // MeshWithDelays d path reverses element order within each write-port chunk. - // For WS+b_transpose we reverse each chunk so stored order is col0..col15. - val flat_raw = VecInit(row.flatten) - val tileW = b.memDomain.bankWidth / config.accWidth - val flat_order = VecInit((0 until DIM).map { i => - val t = i / tileW - val j = t * tileW + (tileW - 1 - (i % tileW)) - Mux(cfg_dataflow =/= Dataflow.OS.id.U && cfg_b_transpose, flat_raw(j), flat_raw(i)) - }) - val flat_row = VecInit(flat_order.map(x => (x >> cfg_in_shift).asSInt)) - val row_bits = Cat(flat_row.reverse.map(_.asUInt)) - - val bitsPerPort = b.memDomain.bankWidth - - for (i <- 0 until outBW) { - when(!port_written(i)) { - val slice = row_bits((i + 1) * bitsPerPort - 1, i * bitsPerPort) - io.bankWrite(i).req.valid := true.B - io.bankWrite(i).req.bits.addr := store_row_cnt - io.bankWrite(i).req.bits.data := slice - io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) - io.bankWrite(i).req.bits.wmode := true.B - when(io.bankWrite(i).req.ready) { - port_written(i) := true.B - } - } - } - - // All ports done for this row → advance to next row - when(port_written.asUInt.andR) { - store_row_cnt := store_row_cnt + 1.U - port_written.foreach(_ := false.B) - } - }.otherwise { - state := sCommit - } - } - - // ----------------------------------------------------------------------- - // COMMIT: send completion response - // ----------------------------------------------------------------------- - is(sCommit) { - io.cmdResp.valid := true.B - when(io.cmdResp.fire) { - state := sIdle - } - } - - // ----------------------------------------------------------------------- - // FLUSH: send flush to mesh, commit - // ----------------------------------------------------------------------- - is(sFlush) { - mesh.io.req.valid := true.B - mesh.io.req.bits.flush := 2.U - mesh.io.req.bits.total_rows := DIM.U - mesh.io.req.bits.tag.rob := rob_id_reg - - mesh.io.a.valid := true.B - mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) - mesh.io.b.valid := true.B - mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) - mesh.io.d.valid := true.B - mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) - - when(mesh.io.req.ready) { - io.cmdResp.valid := true.B - when(io.cmdResp.fire) { - state := sIdle - } - } - } - } +class GemminiExCtrl(val b: GlobalConfig) + extends Module + with GemminiExCtrlDefs + with GemminiExCtrlDefaults + with GemminiExCtrlCmdStates + with GemminiExCtrlPreloadStates + with GemminiExCtrlComputeReadState + with GemminiExCtrlComputeFeedState + with GemminiExCtrlStoreOps + with GemminiExCtrlFsm { + @public val exio = io + + applyDefaults() + runFsm() - // ========================================================================= - // Status - // ========================================================================= io.status.idle := state === sIdle io.status.running := state =/= sIdle } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlCmdStates.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlCmdStates.scala new file mode 100644 index 00000000..e6273245 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlCmdStates.scala @@ -0,0 +1,73 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlCmdStates { this: GemminiExCtrl => + + protected def handleIdleState(): Unit = { + io.cmdReq.ready := true.B + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op2_bank := io.cmdReq.bits.cmd.op2_bank + wr_bank := io.cmdReq.bits.cmd.wr_bank + total_rows := Mux(io.cmdReq.bits.cmd.iter === 0.U, DIM.U, io.cmdReq.bits.cmd.iter) + + when(sub_cmd === GemminiSubCmd.CONFIG) { + cfg_dataflow := io.cmdReq.bits.cmd.special(4) + cfg_a_transpose := io.cmdReq.bits.cmd.special(7) + cfg_bd_transpose := io.cmdReq.bits.cmd.special(8) + cfg_in_shift := io.cmdReq.bits.cmd.special(log2Up(config.accWidth) + 8, 9) + io.cmdResp.valid := true.B + state := sCommit + }.elsewhen(sub_cmd === GemminiSubCmd.PRELOAD) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + req_sent := false.B + state := sPreloadRead + }.elsewhen(sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + outBufRows := 0.U + outBufCollected := 0.U + req_sent := false.B + state := sComputeRead + }.elsewhen(sub_cmd === GemminiSubCmd.FLUSH) { + state := sFlush + } + } + } + + protected def handleCommitState(): Unit = { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + + protected def handleFlushState(): Unit = { + mesh.io.req.valid := true.B + mesh.io.req.bits.flush := 2.U + mesh.io.req.bits.total_rows := DIM.U + mesh.io.req.bits.tag.rob := robIdAsTag8(rob_id_reg) + + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + + when(mesh.io.req.ready) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeFeedState.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeFeedState.scala new file mode 100644 index 00000000..3e77649e --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeFeedState.scala @@ -0,0 +1,68 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlComputeFeedState { this: GemminiExCtrl => + + protected def handleComputeFeedState(): Unit = { + // OS: do not collect mesh rows here — preload matmul responses still drain during feed; + // sComputeFlush drops tag=0xff (garbage) resps and collects non-garbage rows only. + + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux(cfg_dataflow === Dataflow.OS.id.U, !cfg_a_transpose, cfg_a_transpose) + mesh.io.req.bits.bd_transpose := cfg_bd_transpose + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := robIdAsTag8(rob_id_reg) + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + when(req_sent && feed_row_cnt < total_rows) { + when(rdQueue0.io.deq.valid && rdQueue1.io.deq.valid) { + val a_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val x_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + mesh.io.a.valid := true.B + mesh.io.a.bits := VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS: stream A/B, D=0 + mesh.io.b.valid := true.B + mesh.io.b.bits := VecInit(x_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + }.otherwise { + // WS: stream A/D, B comes from preloaded weights + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := VecInit(x_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + } + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := true.B + rdQueue1.io.deq.ready := true.B + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + when(req_sent && feed_row_cnt >= total_rows) { + when(cfg_dataflow === Dataflow.OS.id.U) { + outBufRows := total_rows - 1.U + req_sent := false.B + feed_row_cnt := 0.U + state := sComputeFlush + }.otherwise { + outBufRows := 0.U + state := sDrain + } + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeReadState.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeReadState.scala new file mode 100644 index 00000000..948ed2fb --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlComputeReadState.scala @@ -0,0 +1,27 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlComputeReadState { this: GemminiExCtrl => + + protected def handleComputeReadState(): Unit = { + // Drain stale preload data from shared queues before issuing compute reads + when(read_row_cnt === 0.U && (rdQueue0.io.deq.valid || rdQueue1.io.deq.valid)) { + rdQueue0.io.deq.ready := true.B + rdQueue1.io.deq.ready := true.B + }.elsewhen(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := read_row_cnt + io.bankReadReq(1).valid := true.B + io.bankReadReq(1).bits.addr := read_row_cnt + when(io.bankReadReq(0).ready && io.bankReadReq(1).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sComputeFeed + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefaults.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefaults.scala new file mode 100644 index 00000000..08e1d393 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefaults.scala @@ -0,0 +1,44 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ + +trait GemminiExCtrlDefaults { this: GemminiExCtrl => + + protected def applyDefaults(): Unit = { + io.cmdReq.ready := state === sIdle + + io.cmdResp.valid := false.B + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg + + for (i <- 0 until inBW) { + io.bankReadReq(i).valid := false.B + io.bankReadReq(i).bits.addr := 0.U + } + + rdQueue0.io.deq.ready := false.B + rdQueue1.io.deq.ready := false.B + + mesh.io.a.valid := false.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := false.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := false.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + mesh.io.req.valid := false.B + mesh.io.req.bits := 0.U.asTypeOf(mesh.io.req.bits) + // mesh.io.resp is Valid-only (no ready); MeshWithDelays assumes immediate observation when valid + + io.bankWrite.foreach { bw => + bw.req.valid := false.B + bw.req.bits.addr := 0.U + bw.req.bits.data := 0.U + bw.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(false.B)) + bw.req.bits.wmode := true.B + bw.resp.ready := true.B + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala new file mode 100644 index 00000000..a10cdfaa --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala @@ -0,0 +1,103 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.public +import framework.balldomain.blink.BallStatus +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp, SramWriteIO} +import framework.top.GlobalConfig +import framework.balldomain.prototype.gemmini.configs.GemminiBallParam +import gemmini._ +import gemmini.Util._ + +trait GemminiExCtrlDefs { this: GemminiExCtrl => + val config = GemminiBallParam() + val DIM = config.blockSize + + val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "GemminiBall") + .getOrElse(throw new IllegalArgumentException("GemminiBall not found in config")) + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + val inputType = SInt(config.inputWidth.W) + val accType = SInt(config.accWidth.W) + val outputType = SInt(config.accWidth.W) + + val ctrlIo = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) + val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) + val op1_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val op2_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val wr_bank_o = Output(UInt(log2Up(b.memDomain.bankNum).W)) + val status = new BallStatus + }) + + val io = ctrlIo + + val mesh = Module(new MeshWithDelays( + inputType = inputType, + outputType = outputType, + accType = accType, + tagType = new SimpleTag, + df = Dataflow.BOTH, + tree_reduction = false, + tile_latency = config.tileLatency, + output_delay = config.outputDelay, + tileRows = config.tileRows, + tileColumns = config.tileColumns, + meshRows = config.meshRows, + meshColumns = config.meshColumns, + leftBanks = 1, + upBanks = 1, + n_simultaneous_matmuls = 5 + )) + + val cfg_dataflow = RegInit(0.U(1.W)) + val cfg_in_shift = RegInit(0.U(log2Up(config.accWidth).W)) + val cfg_a_transpose = RegInit(false.B) + val cfg_bd_transpose = RegInit(false.B) + + val sIdle :: sPreloadRead :: sPreloadFeed :: sComputeRead :: sComputeFeed :: sComputeFlush :: sFlush :: sDrain :: sStore :: sCommit :: Nil = + Enum(10) + val state = RegInit(sIdle) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + + /** Match SimpleTag.rob (8b); must match mesh req tag bits */ + protected def robIdAsTag8(x: UInt): UInt = { + val w = x.getWidth + if (w >= 8) x(7, 0) else Cat(0.U((8 - w).W), x) + } + + val op1_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val op2_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + val wr_bank = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank + io.wr_bank_o := wr_bank + + val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) + val req_sent = RegInit(false.B) + + val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) + + val rdQueue0 = Module(new Queue(new SramReadResp(b), entries = DIM)) + val rdQueue1 = Module(new Queue(new SramReadResp(b), entries = DIM)) + rdQueue0.io.enq <> io.bankReadResp(0) + rdQueue1.io.enq <> io.bankReadResp(1) + + val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, outputType)))) + val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) + val outBufCollected = RegInit(0.U(log2Up(DIM + 1).W)) + + val port_written = RegInit(VecInit(Seq.fill(outBW)(false.B))) +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlFsm.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlFsm.scala new file mode 100644 index 00000000..90d12ffb --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlFsm.scala @@ -0,0 +1,43 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ + +trait GemminiExCtrlFsm { this: GemminiExCtrl => + + protected def runFsm(): Unit = { + switch(state) { + is(sIdle) { + handleIdleState() + } + is(sPreloadRead) { + handlePreloadReadState() + } + is(sPreloadFeed) { + handlePreloadFeedState() + } + is(sComputeRead) { + handleComputeReadState() + } + is(sComputeFeed) { + handleComputeFeedState() + } + is(sComputeFlush) { + handleComputeFlushState() + } + is(sDrain) { + handleDrainState() + } + is(sStore) { + handleStoreState() + } + is(sCommit) { + handleCommitState() + } + is(sFlush) { + handleFlushState() + } + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlPreloadStates.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlPreloadStates.scala new file mode 100644 index 00000000..22044514 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlPreloadStates.scala @@ -0,0 +1,84 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlPreloadStates { this: GemminiExCtrl => + + protected def handlePreloadReadState(): Unit = { + when(cfg_dataflow === Dataflow.OS.id.U) { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := read_row_cnt + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + }.otherwise { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := total_rows - 1.U - read_row_cnt + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + } + } + + protected def handlePreloadFeedState(): Unit = { + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + // Buckyball sends preload/compute as separate commands, so the + // AlwaysOutTransposer inside MeshWithDelays cannot be primed with + // compute-A during preload (unlike Chipyard's interleaved flow). + // Negate here so MeshWithDelays' internal !a_transpose yields false, + // keeping the transposer inactive. Software must pre-transpose A. + mesh.io.req.bits.a_transpose := Mux(cfg_dataflow === Dataflow.OS.id.U, !cfg_a_transpose, cfg_a_transpose) + mesh.io.req.bits.bd_transpose := cfg_bd_transpose + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := robIdAsTag8(rob_id_reg) + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + when(req_sent && feed_row_cnt < total_rows) { + when(rdQueue0.io.deq.valid) { + val row_data = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + // OS preload in Buckyball is used to prime pipeline state before compute. + // Feed D=0 to avoid injecting bias-like data into the following matmul. + mesh.io.d.bits := Mux( + cfg_dataflow === Dataflow.OS.id.U, + 0.U.asTypeOf(mesh.D_TYPE), + VecInit(row_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq) + ) + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := true.B + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + when(req_sent && feed_row_cnt >= total_rows) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala new file mode 100644 index 00000000..38dfcb80 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala @@ -0,0 +1,104 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlStoreOps { this: GemminiExCtrl => + + protected def handleComputeFlushState(): Unit = { + when(mesh.io.resp.fire && mesh.io.resp.bits.total_rows === total_rows) { + when(outBufCollected < total_rows && mesh.io.resp.bits.tag.rob =/= 0xff.U) { + outBuf(total_rows - 1.U - outBufCollected) := mesh.io.resp.bits.data + outBufCollected := outBufCollected + 1.U + }.otherwise {} + } + + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + }.otherwise { + // Flush once to drain remaining rows after feeding is complete. + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux(cfg_dataflow === Dataflow.OS.id.U, !cfg_a_transpose, cfg_a_transpose) + mesh.io.req.bits.bd_transpose := cfg_bd_transpose + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := robIdAsTag8(rob_id_reg) + mesh.io.req.bits.flush := 1.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + } + } + + protected def handleDrainState(): Unit = { + when(mesh.io.resp.valid) { + when(cfg_dataflow === Dataflow.OS.id.U) { + when(mesh.io.resp.bits.total_rows === total_rows) { + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows - 1.U + outBufCollected := outBufCollected + 1.U + } + }.otherwise { + outBuf(outBufRows) := mesh.io.resp.bits.data + outBufRows := outBufRows + 1.U + } + } + + when(cfg_dataflow === Dataflow.OS.id.U) { + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + }.otherwise { + when(outBufRows >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + } + } + + protected def handleStoreState(): Unit = { + when(store_row_cnt < total_rows) { + // One row = DIM elements; split across outBW ports (group_id 0..outBW-1). + // mvout reads (addr, group 0), (addr, group 1), ... and concatenates as row. + // So port i (group_id=i) must get elements [i*elemsPerPort .. (i+1)*elemsPerPort). + val rowIdx = store_row_cnt + val row = outBuf(rowIdx) + val flat_raw = VecInit(row.flatten) + val row_bits = Cat(flat_raw.map(_.asUInt).reverse) + + val bitsPerPort = b.memDomain.bankWidth + + for (i <- 0 until outBW) { + when(!port_written(i)) { + val slice = row_bits((i + 1) * bitsPerPort - 1, i * bitsPerPort) + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := store_row_cnt + io.bankWrite(i).req.bits.data := slice + io.bankWrite(i).req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + io.bankWrite(i).req.bits.wmode := true.B + when(io.bankWrite(i).req.ready) { + port_written(i) := true.B + } + } + } + + when(port_written.asUInt.andR) { + store_row_cnt := store_row_cnt + 1.U + port_written.foreach(_ := false.B) + } + }.otherwise { + state := sCommit + } + } + +} diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlTypes.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlTypes.scala new file mode 100644 index 00000000..710e7825 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlTypes.scala @@ -0,0 +1,19 @@ +package framework.balldomain.prototype.gemmini + +import chisel3._ + +/** Minimal tag for MeshWithDelays that satisfies TagQueueTag */ +class SimpleTag extends Bundle with gemmini.TagQueueTag { + val rob = UInt(8.W) + override def make_this_garbage(dummy: Int = 0): Unit = + rob := 0xff.U +} + +/** Sub-command encoding within the special field */ +object GemminiSubCmd { + val CONFIG = 0.U(4.W) + val PRELOAD = 1.U(4.W) + val COMPUTE_PRELOADED = 2.U(4.W) + val COMPUTE_ACCUMULATED = 3.U(4.W) + val FLUSH = 4.U(4.W) +} diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 554caee8..2eb1a083 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -23,54 +23,14 @@ "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", "ctest_gemmini_os_risc_basic_test_singlecore-baremetal", ), - ( - "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", - "ctest_gemmini_os_risc_shift_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", - "ctest_gemmini_os_risc_atranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", - "ctest_gemmini_os_risc_btranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", - "ctest_gemmini_os_risc_abtranspose_test_singlecore-baremetal", - ), ( "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", "ctest_gemmini_ws_risc_basic_test_singlecore-baremetal", ), - ( - "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", - "ctest_gemmini_ws_risc_shift_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", - "ctest_gemmini_ws_risc_btranspose_test_singlecore-baremetal", - ), ( "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", "ctest_gemmini_os_cisc_basic_test_singlecore-baremetal", ), - ( - "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_shift_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_atranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", - "ctest_gemmini_os_cisc_btranspose_test_singlecore-baremetal", - ), - ( - "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", - "ctest_gemmini_ws_cisc_conv_test_singlecore-baremetal", - ), ( "ctest_mvin_mvout_test_singlecore-baremetal", "ctest_mvin_mvout_test_singlecore-baremetal", diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c index a76635ad..f9d80866 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_atranspose_test.c @@ -15,7 +15,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC a_transpose Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c index ee8298ca..a0f0ea1d 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_basic_test.c @@ -6,6 +6,7 @@ #define DIM 16 static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_a_t[DIM * DIM] __attribute__((aligned(64))); static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); static result_t expected[DIM * DIM] __attribute__((aligned(64))); @@ -14,16 +15,19 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC Basic Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); init_u8_random_matrix(mat_b, DIM, DIM, 84); + // OS mode (transposer disabled): mesh computes A_loaded^T * B. + // Pre-transpose A so result = mat_a_t^T * mat_b = mat_a * mat_b. + transpose_u8_matrix(mat_a, mat_a_t, DIM, DIM); cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); bb_gemmini_config(0, 0, 0, 0, 0); bb_gemmini_loop_ws_config_bounds(1, 1, 1); - bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a_t); bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); bb_gemmini_loop_ws_config_addr_d(0); bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c index 8a59b615..dc2d2575 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_btranspose_test.c @@ -15,7 +15,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC b_transpose Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c index 38698d03..d66bd470 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_cisc_shift_test.c @@ -15,7 +15,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS CISC in_shift Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c index 004ccd8c..c15dbe32 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_abtranspose_test.c @@ -16,7 +16,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC ab_transpose Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c index 1d3a6da9..c4bbddcb 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_atranspose_test.c @@ -15,7 +15,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC a_transpose Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c index cf721ce2..bdde74fb 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_basic_test.c @@ -6,7 +6,9 @@ #define DIM 16 static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_a_t[DIM * DIM] __attribute__((aligned(64))); static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t zeros[DIM * DIM] __attribute__((aligned(64))); static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); static result_t expected[DIM * DIM] __attribute__((aligned(64))); @@ -14,21 +16,27 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); printf("=== Gemmini OS RISC Basic Test ===\n"); - init_u8_random_matrix(mat_a, DIM, DIM, 42); - init_u8_random_matrix(mat_b, DIM, DIM, 84); + for (int i = 0; i < DIM * DIM; i++) { + mat_a[i] = (elem_t)((i + 1) % 128); + mat_b[i] = (elem_t)((2 * (i + 1)) % 128); + } + transpose_u8_matrix(mat_a, mat_a_t, DIM, DIM); + // Hardware (transposer disabled) computes mat_a_t^T * mat_b = mat_a * mat_b cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); - uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + uint32_t bank_a = 0, bank_b = 1, bank_c = 2, bank_d_zeros = 3; bb_mem_alloc(bank_a, 1, 1); bb_mem_alloc(bank_b, 1, 1); bb_mem_alloc(bank_c, 1, 4); - bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mem_alloc(bank_d_zeros, 1, 1); + bb_mvin((uintptr_t)mat_a_t, bank_a, DIM, 1); bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_mvin((uintptr_t)zeros, bank_d_zeros, DIM, 1); bb_gemmini_config(0, 0, 0, 0, 0); - bb_gemmini_preload(bank_a, bank_c, DIM); + /* Preload D from zeros bank so C = A*B + D = A*B (not A*B + A) */ + bb_gemmini_preload(bank_d_zeros, bank_c, DIM); bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM); bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); bb_fence(); @@ -37,6 +45,24 @@ int main() { printf("Gemmini OS RISC Basic Test PASSED\n"); return 0; } + + printf("got mat_c: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", mat_c[i]); + } + printf("\n"); + // for (int i = 0; i < DIM; i++) { + // for (int j = 0; j < DIM; j++) { + // printf("%d ", mat_c[i * DIM + j]); + // } + // printf("\n"); + // } + + printf("exp row0: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", expected[i]); + } + printf("\n"); printf("Gemmini OS RISC Basic Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c index 05c16d9b..1aa09779 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_btranspose_test.c @@ -15,7 +15,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC b_transpose Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c index 382cf066..8921bb66 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_os_risc_shift_test.c @@ -15,7 +15,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini OS RISC in_shift Test ===\n"); init_u8_random_matrix(mat_a, DIM, DIM, 42); diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c index 7f26bf8f..e19af1a0 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_cisc_conv_test.c @@ -31,7 +31,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS CISC Loop Conv Test ===\n"); // Initialize: input = 1x16 row vector, weight = 16x16 matrix diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c index 15af17b1..66a71950 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_basic_test.c @@ -15,17 +15,14 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); printf("=== Gemmini WS RISC Basic Test ===\n"); - // Deterministic: mat_a[i] = i+1, mat_b[i] = 2*(i+1) (mod 128) for (int i = 0; i < DIM * DIM; i++) { mat_a[i] = (elem_t)((i + 1) % 128); mat_b[i] = (elem_t)((2 * (i + 1)) % 128); } clear_u8_matrix(mat_d, DIM, DIM); cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); - printf("expected[0] = %d\n", (int)expected[0]); // WS: bank_w=weights(B), bank_a=activations(A), bank_d=bias(0), bank_c=output uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; @@ -46,12 +43,5 @@ int main() { printf("Gemmini WS RISC Basic Test PASSED\n"); return 0; } - // // Print first few mismatches - // for (int i = 0; i < DIM * DIM && i < 8; i++) { - // if (mat_c[i] != expected[i]) - // printf(" [%d] got=%d expected=%d\n", i, (int)mat_c[i], - // (int)expected[i]); - // } - // printf("Test FAILED\n"); return 1; } diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c index 99109b41..b7063a1a 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_btranspose_test.c @@ -16,7 +16,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS RISC b_transpose Test ===\n"); for (int i = 0; i < DIM * DIM; i++) { diff --git a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c index 40364f1d..305a07f7 100644 --- a/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c +++ b/bb-tests/workloads/src/CTest/toy/gemmini_ws_risc_shift_test.c @@ -16,7 +16,7 @@ int main() { #ifdef MULTICORE multicore(MULTICORE); #endif - setvbuf(stdout, NULL, _IONBF, 0); + printf("=== Gemmini WS RISC in_shift Test ===\n"); for (int i = 0; i < DIM * DIM; i++) { From 9f8e47bd9dae3a43a071594e37789fcd90190730 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 20 Mar 2026 16:05:37 +0800 Subject: [PATCH 180/238] [arch] del: remove unused channel and memory router components --- .../examples/toy/balldomain/BallDomain.scala | 1 - .../framework/balldomain/bbus/bbus.scala | 1 - .../bbus/memrouter/ChannelMapping.scala | 66 ---- .../bbus/memrouter/ReadReqGen.scala | 88 ------ .../bbus/memrouter/WriteReqGen.scala | 88 ------ .../balldomain/bbus/memrouter/memRouter.scala | 289 ------------------ .../framework/top/channels/Channel.scala | 47 --- .../top/channels/ChannelCluster.scala | 58 ---- .../framework/top/channels/headerBuffer.scala | 30 -- docs | 2 +- 10 files changed, 1 insertion(+), 669 deletions(-) delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala delete mode 100644 arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala delete mode 100644 arch/src/main/scala/framework/top/channels/Channel.scala delete mode 100644 arch/src/main/scala/framework/top/channels/ChannelCluster.scala delete mode 100644 arch/src/main/scala/framework/top/channels/headerBuffer.scala diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index f8085f32..9c274b9f 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -10,7 +10,6 @@ import examples.toy.balldomain.bbus.BBusModule import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} import framework.balldomain.rs.BallReservationStation -import framework.top.channels.{ChannelClusterIO, ChannelIO} @instantiable class BallDomain(val b: GlobalConfig) extends Module { diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 81294445..62391adb 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -9,7 +9,6 @@ import framework.balldomain.blink.HasBlink import framework.balldomain.bbus.pmc.BallCyclePMC import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} -import framework.top.channels.{Channel, ChannelClusterIO, ChannelIO} /** * BBus - Ball bus, manages connections and arbitration of multiple Ball devices diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala deleted file mode 100644 index a3559cd2..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ChannelMapping.scala +++ /dev/null @@ -1,66 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import framework.top.GlobalConfig - -@instantiable -class ChannelMappingTable(val b: GlobalConfig, val entryNum: Int) extends Module { - val EntryNum = entryNum - val MappedChannels = b.top.ballMemChannelNum - - // 多写口数量：与输出通道数一致（一次最多派发这么多条） - val WritePorts = MappedChannels - - @public - val io = IO(new Bundle { - - val write = Flipped(Vec( - WritePorts, - Decoupled(new Bundle { - val idx = UInt(log2Up(EntryNum).W) - val outCh = UInt(log2Up(MappedChannels).W) - }) - )) - - // 条目级清理：每个写口对应一条可能的派发通道（通常用 outCh 作为端口号） - val invalidate = Input(Vec(WritePorts, Valid(UInt(log2Up(EntryNum).W)))) - - val routeMap = Output(Vec(EntryNum, UInt(log2Up(MappedChannels).W))) - val routeValid = Output(Vec(EntryNum, Bool())) - }) - - val routeMap = Reg(Vec(EntryNum, UInt(log2Up(MappedChannels).W))) - val routeValid = RegInit(VecInit(Seq.fill(EntryNum)(false.B))) - - for (w <- 0 until WritePorts) { - io.write(w).ready := true.B - - // 先处理清理：把对应 idx 的 valid 清掉 - when(io.invalidate(w).valid) { - routeValid(io.invalidate(w).bits) := false.B - } - - // 再处理写入：同拍既清又写时，让写入优先（最终为 valid=true） - when(io.write(w).fire) { - routeMap(io.write(w).bits.idx) := io.write(w).bits.outCh - routeValid(io.write(w).bits.idx) := true.B - } - } - - io.routeMap := routeMap - io.routeValid := routeValid - - // Assert: in the same cycle, different write ports must not target the same idx - for (p <- 0 until WritePorts) { - for (q <- p + 1 until WritePorts) { - when(io.write(p).valid && io.write(q).valid) { - assert( - io.write(p).bits.idx =/= io.write(q).bits.idx, - "ChannelMappingTable: multiple write ports target the same idx in one cycle" - ) - } - } - } -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala deleted file mode 100644 index a5941865..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/ReadReqGen.scala +++ /dev/null @@ -1,88 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import framework.top.GlobalConfig - -class ReadReq(val b: GlobalConfig) extends Bundle { - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) - val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -class BankReadProbe(val b: GlobalConfig) extends Bundle { - val valid = Bool() - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -@instantiable -class ReadReqGen(val b: GlobalConfig) extends Module { - val ballIdMappings = b.ballDomain.ballIdMappings - val numBalls = b.ballDomain.ballNum - val totalReadChannels = ballIdMappings.map(_.inBW).sum - val numBanks = b.memDomain.bankNum - - require( - ballIdMappings.forall(_.inBW > 0), - "ReadReqGen assumes every ball has at least one read channel (inBW > 0); otherwise robId indexing is invalid." - ) - - @public - val io = IO(new Bundle { - val bank_read_i = Input(Vec(totalReadChannels, new BankReadProbe(b))) - val read_req_o = Decoupled(new ReadReq(b)) - }) - - val reqGroupsWithRobId = (0 until numBalls).flatMap { ballId => - (0 until numBanks).map { bankId => - val ballOffset = ballIdMappings.take(ballId).map(_.inBW).sum - val ballInBW = ballIdMappings(ballId).inBW - val matchingChannels = (ballOffset until ballOffset + ballInBW).toSeq - - val matchConds = matchingChannels.map { ch => - io.bank_read_i(ch).valid && - io.bank_read_i(ch).ball_id === ballId.U && - io.bank_read_i(ch).bank_id === bankId.U - } - - val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) - val channelCountRaw = PopCount(matchConds) - - val maxCh = b.top.ballMemChannelNum.U - val channelCount = Mux(channelCountRaw > maxCh, maxCh, channelCountRaw) - - val robId = io.bank_read_i(ballOffset).rob_id - - (hasReq, channelCount, bankId.U, ballId.U, robId) - } - } - - val arb = Module(new Arbiter( - new Bundle { - val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) - val bank_id = UInt(log2Up(numBanks).W) - val ball_id = UInt(log2Up(numBalls).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) - }, - reqGroupsWithRobId.length - )) - - for (i <- reqGroupsWithRobId.indices) { - arb.io.in(i).valid := reqGroupsWithRobId(i)._1 - arb.io.in(i).bits.channel_num := reqGroupsWithRobId(i)._2 - arb.io.in(i).bits.bank_id := reqGroupsWithRobId(i)._3 - arb.io.in(i).bits.ball_id := reqGroupsWithRobId(i)._4 - arb.io.in(i).bits.rob_id := reqGroupsWithRobId(i)._5 - } - - io.read_req_o.valid := arb.io.out.valid - io.read_req_o.bits.bank_id := arb.io.out.bits.bank_id - io.read_req_o.bits.ball_id := arb.io.out.bits.ball_id - io.read_req_o.bits.channel_num := arb.io.out.bits.channel_num - io.read_req_o.bits.rob_id := arb.io.out.bits.rob_id - arb.io.out.ready := io.read_req_o.ready -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala deleted file mode 100644 index 0b483bb7..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/WriteReqGen.scala +++ /dev/null @@ -1,88 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import framework.top.GlobalConfig - -class WriteReq(val b: GlobalConfig) extends Bundle { - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) - val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -class BankWriteProbe(val b: GlobalConfig) extends Bundle { - val valid = Bool() - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val ball_id = UInt(log2Up(b.ballDomain.ballNum).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -@instantiable -class WriteReqGen(val b: GlobalConfig) extends Module { - val ballIdMappings = b.ballDomain.ballIdMappings - val numBalls = b.ballDomain.ballNum - val totalWriteChannels = ballIdMappings.map(_.outBW).sum - val numBanks = b.memDomain.bankNum - - require( - ballIdMappings.forall(_.outBW > 0), - "WriteReqGen assumes every ball has at least one write channel (outBW > 0); otherwise robId indexing is invalid." - ) - - @public - val io = IO(new Bundle { - val bank_write_i = Input(Vec(totalWriteChannels, new BankWriteProbe(b))) - val write_req_o = Decoupled(new WriteReq(b)) - }) - - val reqGroupsWithRobId = (0 until numBalls).flatMap { ballId => - (0 until numBanks).map { bankId => - val ballOffset = ballIdMappings.take(ballId).map(_.outBW).sum - val ballOutBW = ballIdMappings(ballId).outBW - val matchingChannels = (ballOffset until ballOffset + ballOutBW).toSeq - - val matchConds = matchingChannels.map { ch => - io.bank_write_i(ch).valid && - io.bank_write_i(ch).ball_id === ballId.U && - io.bank_write_i(ch).bank_id === bankId.U - } - - val hasReq = matchConds.reduceOption(_ || _).getOrElse(false.B) - val channelCountRaw = PopCount(matchConds) - - val maxCh = b.top.ballMemChannelNum.U - val channelCount = Mux(channelCountRaw > maxCh, maxCh, channelCountRaw) - - val robId = io.bank_write_i(ballOffset).rob_id - - (hasReq, channelCount, bankId.U, ballId.U, robId) - } - } - - val arb = Module(new Arbiter( - new Bundle { - val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) - val bank_id = UInt(log2Up(numBanks).W) - val ball_id = UInt(log2Up(numBalls).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) - }, - reqGroupsWithRobId.length - )) - - for (i <- reqGroupsWithRobId.indices) { - arb.io.in(i).valid := reqGroupsWithRobId(i)._1 - arb.io.in(i).bits.channel_num := reqGroupsWithRobId(i)._2 - arb.io.in(i).bits.bank_id := reqGroupsWithRobId(i)._3 - arb.io.in(i).bits.ball_id := reqGroupsWithRobId(i)._4 - arb.io.in(i).bits.rob_id := reqGroupsWithRobId(i)._5 - } - - io.write_req_o.valid := arb.io.out.valid - io.write_req_o.bits.bank_id := arb.io.out.bits.bank_id - io.write_req_o.bits.ball_id := arb.io.out.bits.ball_id - io.write_req_o.bits.channel_num := arb.io.out.bits.channel_num - io.write_req_o.bits.rob_id := arb.io.out.bits.rob_id - arb.io.out.ready := io.write_req_o.ready -} diff --git a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala b/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala deleted file mode 100644 index 56f9700d..00000000 --- a/arch/src/main/scala/framework/balldomain/bbus/memrouter/memRouter.scala +++ /dev/null @@ -1,289 +0,0 @@ -package framework.balldomain.bbus.memrouter - -import chisel3._ -import chisel3.util._ -import framework.balldomain.blink.{BankRead, BankWrite} -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig - -class PeakChannelReq(val b: GlobalConfig) extends Bundle { - val needed_channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -class FreeChannelResp(val b: GlobalConfig) extends Bundle { - val is_free = Bool() - val channel_ids = Vec(b.top.ballMemChannelNum, UInt(log2Up(b.top.ballMemChannelNum).W)) - val channel_num = UInt(log2Up(b.top.ballMemChannelNum + 1).W) -} - -@instantiable -class MemRouter(val b: GlobalConfig) extends Module { - val bbusProducerChannels = b.top.ballMemChannelNum - val totalReadChannels = b.ballDomain.ballIdMappings.map(_.inBW).sum - val totalWriteChannels = b.ballDomain.ballIdMappings.map(_.outBW).sum - - @public - val io = IO(new Bundle { - val bankRead_i = Vec(totalReadChannels, new BankRead(b)) - val bankRead_o = Vec(bbusProducerChannels, Flipped(new BankRead(b))) - - val bankWrite_i = Vec(totalWriteChannels, new BankWrite(b)) - val bankWrite_o = Vec(bbusProducerChannels, Flipped(new BankWrite(b))) - - val peakChannelReq = Decoupled(new PeakChannelReq(b)) - val freeChannelResp = Flipped(Decoupled(new FreeChannelResp(b))) - }) - - // --------------------------------------------------------------------------- - // Step1: probe -> ReadReqGen / WriteReqGen - // --------------------------------------------------------------------------- - val readReqGen: Instance[ReadReqGen] = Instantiate(new ReadReqGen(b)) - val writeReqGen: Instance[WriteReqGen] = Instantiate(new WriteReqGen(b)) - - val readMap: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b, totalReadChannels)) - val writeMap: Instance[ChannelMappingTable] = Instantiate(new ChannelMappingTable(b, totalWriteChannels)) - - for (i <- 0 until totalReadChannels) { - readReqGen.io.bank_read_i(i).valid := io.bankRead_i(i).io.req.valid - readReqGen.io.bank_read_i(i).ball_id := io.bankRead_i(i).ball_id - readReqGen.io.bank_read_i(i).bank_id := io.bankRead_i(i).bank_id - readReqGen.io.bank_read_i(i).rob_id := io.bankRead_i(i).rob_id - } - for (i <- 0 until totalWriteChannels) { - writeReqGen.io.bank_write_i(i).valid := io.bankWrite_i(i).io.req.valid - writeReqGen.io.bank_write_i(i).ball_id := io.bankWrite_i(i).ball_id - writeReqGen.io.bank_write_i(i).bank_id := io.bankWrite_i(i).bank_id - writeReqGen.io.bank_write_i(i).rob_id := io.bankWrite_i(i).rob_id - } - - // --------------------------------------------------------------------------- - // Step2: one allocator, RR choose read/write group - // --------------------------------------------------------------------------- - val hasReadReq = readReqGen.io.read_req_o.valid - val hasWriteReq = writeReqGen.io.write_req_o.valid - - val rrLastWasRead = RegInit(true.B) // 用于读写公平：true 表示上次发的是读 - - val chooseRead = WireDefault(false.B) - when(hasReadReq && !hasWriteReq) { - chooseRead := true.B - }.elsewhen(!hasReadReq && hasWriteReq) { - chooseRead := false.B - }.elsewhen(hasReadReq && hasWriteReq) { - chooseRead := !rrLastWasRead - } - - val chooseWrite = hasReadReq && hasWriteReq && !chooseRead || (!hasReadReq && hasWriteReq) - - io.peakChannelReq.valid := hasReadReq || hasWriteReq - io.peakChannelReq.bits.needed_channel_num := Mux( - chooseRead, - readReqGen.io.read_req_o.bits.channel_num, - writeReqGen.io.write_req_o.bits.channel_num - ) - io.peakChannelReq.bits.bank_id := Mux( - chooseRead, - readReqGen.io.read_req_o.bits.bank_id, - writeReqGen.io.write_req_o.bits.bank_id - ) - io.peakChannelReq.bits.rob_id := Mux( - chooseRead, - readReqGen.io.read_req_o.bits.rob_id, - writeReqGen.io.write_req_o.bits.rob_id - ) - - // allocator 这里当“组合查询”用 - io.freeChannelResp.ready := true.B - val isChannelFree = io.freeChannelResp.valid && io.freeChannelResp.bits.is_free && io.peakChannelReq.valid - val dispatchChannels = io.freeChannelResp.bits.channel_ids - - readReqGen.io.read_req_o.ready := isChannelFree && chooseRead - writeReqGen.io.write_req_o.ready := isChannelFree && chooseWrite - - val didDispatchRead = readReqGen.io.read_req_o.fire - val didDispatchWrite = writeReqGen.io.write_req_o.fire - - when(didDispatchRead)(rrLastWasRead := true.B) - when(didDispatchWrite)(rrLastWasRead := false.B) - - // --------------------------------------------------------------------------- - // defaults: mapping write/invalidate off - // --------------------------------------------------------------------------- - for (w <- 0 until bbusProducerChannels) { - readMap.io.write(w).valid := false.B - readMap.io.write(w).bits.idx := 0.U - readMap.io.write(w).bits.outCh := 0.U - readMap.io.invalidate(w).valid := false.B - readMap.io.invalidate(w).bits := 0.U - - writeMap.io.write(w).valid := false.B - writeMap.io.write(w).bits.idx := 0.U - writeMap.io.write(w).bits.outCh := 0.U - writeMap.io.invalidate(w).valid := false.B - writeMap.io.invalidate(w).bits := 0.U - } - - // --------------------------------------------------------------------------- - // Step4: batch write mapping for chosen side - // --------------------------------------------------------------------------- - when(didDispatchRead) { - val matchVec = VecInit((0 until totalReadChannels).map { i => - io.bankRead_i(i).ball_id === readReqGen.io.read_req_o.bits.ball_id && - io.bankRead_i(i).bank_id === readReqGen.io.read_req_o.bits.bank_id && - io.bankRead_i(i).io.req.valid - }) - - val matchCount = PopCount(matchVec) - val channelNum = readReqGen.io.read_req_o.bits.channel_num - val portLimit = bbusProducerChannels.U - val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) - val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) - - for (p <- 0 until bbusProducerChannels) { - for (q <- p + 1 until bbusProducerChannels) { - when((p.U < dispatchCount) && (q.U < dispatchCount)) { - assert( - dispatchChannels(p) =/= dispatchChannels(q), - "MemRouter(Read): duplicate outCh in dispatchChannels within dispatchCount" - ) - } - } - } - - for (i <- 0 until totalReadChannels) { - when(matchVec(i)) { - val priorMatchCount = PopCount(matchVec.take(i)) - when(priorMatchCount < dispatchCount) { - readMap.io.write(priorMatchCount).valid := true.B - readMap.io.write(priorMatchCount).bits.idx := i.U - readMap.io.write(priorMatchCount).bits.outCh := dispatchChannels(priorMatchCount) - } - } - } - } - - when(didDispatchWrite) { - val matchVec = VecInit((0 until totalWriteChannels).map { i => - io.bankWrite_i(i).ball_id === writeReqGen.io.write_req_o.bits.ball_id && - io.bankWrite_i(i).bank_id === writeReqGen.io.write_req_o.bits.bank_id && - io.bankWrite_i(i).io.req.valid - }) - - val matchCount = PopCount(matchVec) - val channelNum = writeReqGen.io.write_req_o.bits.channel_num - val portLimit = bbusProducerChannels.U - val wantCount = Mux(matchCount > channelNum, channelNum, matchCount) - val dispatchCount = Mux(wantCount > portLimit, portLimit, wantCount) - - for (p <- 0 until bbusProducerChannels) { - for (q <- p + 1 until bbusProducerChannels) { - when((p.U < dispatchCount) && (q.U < dispatchCount)) { - assert( - dispatchChannels(p) =/= dispatchChannels(q), - "MemRouter(Write): duplicate outCh in dispatchChannels within dispatchCount" - ) - } - } - } - - for (i <- 0 until totalWriteChannels) { - when(matchVec(i)) { - val priorMatchCount = PopCount(matchVec.take(i)) - when(priorMatchCount < dispatchCount) { - writeMap.io.write(priorMatchCount).valid := true.B - writeMap.io.write(priorMatchCount).bits.idx := i.U - writeMap.io.write(priorMatchCount).bits.outCh := dispatchChannels(priorMatchCount) - } - } - } - } - - // --------------------------------------------------------------------------- - // defaults: out ports idle; in ports backpressured; resp invalid - // --------------------------------------------------------------------------- - for (o <- 0 until bbusProducerChannels) { - io.bankRead_o(o).io.req.valid := false.B - io.bankRead_o(o).io.req.bits := DontCare - io.bankRead_o(o).io.resp.ready := false.B - io.bankRead_o(o).bank_id := DontCare - io.bankRead_o(o).ball_id := DontCare - io.bankRead_o(o).rob_id := DontCare - - io.bankWrite_o(o).io.req.valid := false.B - io.bankWrite_o(o).io.req.bits := DontCare - io.bankWrite_o(o).io.resp.ready := false.B - io.bankWrite_o(o).bank_id := DontCare - io.bankWrite_o(o).ball_id := DontCare - io.bankWrite_o(o).rob_id := DontCare - } - - for (i <- 0 until totalReadChannels) { - io.bankRead_i(i).io.req.ready := false.B - io.bankRead_i(i).io.resp.valid := false.B - io.bankRead_i(i).io.resp.bits := DontCare - } - for (i <- 0 until totalWriteChannels) { - io.bankWrite_i(i).io.req.ready := false.B - io.bankWrite_i(i).io.resp.valid := false.B - io.bankWrite_i(i).io.resp.bits := DontCare - } - - // --------------------------------------------------------------------------- - // Step5: route req/resp by outCh, invalidate on resp.fire - // --------------------------------------------------------------------------- - for (o <- 0 until bbusProducerChannels) { - val readIdxOH = VecInit((0 until totalReadChannels).map { i => - readMap.io.routeValid(i) && (readMap.io.routeMap(i) === o.U) - }) - val writeIdxOH = VecInit((0 until totalWriteChannels).map { i => - writeMap.io.routeValid(i) && (writeMap.io.routeMap(i) === o.U) - }) - - val hasRead = readIdxOH.asUInt.orR - val hasWrite = writeIdxOH.asUInt.orR - - assert(!(hasRead && hasWrite), "MemRouter: one outCh is mapped by both read and write") - - when(hasRead) { - val ridx = PriorityEncoder(readIdxOH.asUInt) - - io.bankRead_o(o).io.req.valid := io.bankRead_i(ridx).io.req.valid - io.bankRead_o(o).io.req.bits := io.bankRead_i(ridx).io.req.bits - io.bankRead_o(o).bank_id := io.bankRead_i(ridx).bank_id - io.bankRead_o(o).ball_id := io.bankRead_i(ridx).ball_id - io.bankRead_o(o).rob_id := io.bankRead_i(ridx).rob_id - - io.bankRead_i(ridx).io.req.ready := io.bankRead_o(o).io.req.ready - - io.bankRead_i(ridx).io.resp.valid := io.bankRead_o(o).io.resp.valid - io.bankRead_i(ridx).io.resp.bits := io.bankRead_o(o).io.resp.bits - io.bankRead_o(o).io.resp.ready := io.bankRead_i(ridx).io.resp.ready - - when(io.bankRead_o(o).io.resp.fire) { - readMap.io.invalidate(o).valid := true.B - readMap.io.invalidate(o).bits := ridx - } - }.elsewhen(hasWrite) { - val widx = PriorityEncoder(writeIdxOH.asUInt) - - io.bankWrite_o(o).io.req.valid := io.bankWrite_i(widx).io.req.valid - io.bankWrite_o(o).io.req.bits := io.bankWrite_i(widx).io.req.bits - io.bankWrite_o(o).bank_id := io.bankWrite_i(widx).bank_id - io.bankWrite_o(o).ball_id := io.bankWrite_i(widx).ball_id - io.bankWrite_o(o).rob_id := io.bankWrite_i(widx).rob_id - - io.bankWrite_i(widx).io.req.ready := io.bankWrite_o(o).io.req.ready - - io.bankWrite_i(widx).io.resp.valid := io.bankWrite_o(o).io.resp.valid - io.bankWrite_i(widx).io.resp.bits := io.bankWrite_o(o).io.resp.bits - io.bankWrite_o(o).io.resp.ready := io.bankWrite_i(widx).io.resp.ready - - when(io.bankWrite_o(o).io.resp.fire) { - writeMap.io.invalidate(o).valid := true.B - writeMap.io.invalidate(o).bits := widx - } - } - } -} diff --git a/arch/src/main/scala/framework/top/channels/Channel.scala b/arch/src/main/scala/framework/top/channels/Channel.scala deleted file mode 100644 index 366156b5..00000000 --- a/arch/src/main/scala/framework/top/channels/Channel.scala +++ /dev/null @@ -1,47 +0,0 @@ -package framework.top.channels - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig -import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} - -class ChannelIO(val b: GlobalConfig) extends Bundle { - val data = Decoupled(UInt(b.memDomain.bankWidth.W)) -} - -@instantiable -class Channel(val b: GlobalConfig) extends Module { - - @public - val io = IO(new Bundle { - val in = Flipped(new ChannelIO(b)) - val out = new ChannelIO(b) - - val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) - val freeChannelResp = Decoupled(new FreeChannelResp(b)) - }) - - val headerBuffer: Instance[HeaderBuffer] = Instantiate(new HeaderBuffer(b)) - - val isFree = !headerBuffer.io.read.lock - val hasEnoughChannel = isFree - - io.freeChannelResp.valid := io.peakChannelReq.valid - io.freeChannelResp.bits.is_free := hasEnoughChannel - io.freeChannelResp.bits.channel_ids := DontCare - io.freeChannelResp.bits.channel_num := io.peakChannelReq.bits.needed_channel_num - io.peakChannelReq.ready := io.freeChannelResp.ready - - when(io.peakChannelReq.fire && hasEnoughChannel) { - headerBuffer.io.set.valid := true.B - headerBuffer.io.set.bits.rob_id := io.peakChannelReq.bits.rob_id - headerBuffer.io.set.bits.bank_id := io.peakChannelReq.bits.bank_id - headerBuffer.io.set.bits.lock := true.B - }.otherwise { - headerBuffer.io.set.valid := false.B - headerBuffer.io.set.bits := DontCare - } - - io.out <> io.in -} diff --git a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala b/arch/src/main/scala/framework/top/channels/ChannelCluster.scala deleted file mode 100644 index 9143781d..00000000 --- a/arch/src/main/scala/framework/top/channels/ChannelCluster.scala +++ /dev/null @@ -1,58 +0,0 @@ -package framework.top.channels - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig -import framework.balldomain.bbus.memrouter.{FreeChannelResp, PeakChannelReq} - -class ChannelClusterIO(val b: GlobalConfig, numChannels: Int) extends Bundle { - val channelIn = Vec(numChannels, Flipped(new ChannelIO(b))) - val channelOut = Vec(numChannels, new ChannelIO(b)) - val peakChannelReq = Flipped(Decoupled(new PeakChannelReq(b))) - val freeChannelResp = Decoupled(new FreeChannelResp(b)) -} - -@instantiable -class ChannelCluster(val b: GlobalConfig, numChannels: Int) extends Module { - @public - val io = IO(new ChannelClusterIO(b, numChannels)) - - val channels = (0 until numChannels).map(_ => Instantiate(new Channel(b))) - - // Connect channels - for (i <- 0 until numChannels) { - channels(i).io.in <> io.channelIn(i) - channels(i).io.out <> io.channelOut(i) - channels(i).io.peakChannelReq.valid := io.peakChannelReq.valid - channels(i).io.peakChannelReq.bits := io.peakChannelReq.bits - channels(i).io.freeChannelResp.ready := true.B - } - - val freeChannels = VecInit(channels.map(ch => ch.io.freeChannelResp.bits.is_free)) - val freeChannelCount = PopCount(freeChannels) - val hasEnoughChannels = freeChannelCount >= io.peakChannelReq.bits.needed_channel_num - - val selectedChannelIds = Wire(Vec(numChannels, UInt(log2Up(numChannels).W))) - val selectedMask = Wire(Vec(numChannels, Bool())) - - val masks = Wire(Vec(numChannels + 1, Vec(numChannels, Bool()))) - masks(0) := freeChannels - - for (i <- 0 until numChannels) { - val maskVec = masks(i) - val selOH = PriorityEncoderOH(maskVec.asUInt) - val selIdx = PriorityEncoder(maskVec.asUInt) - selectedMask(i) := maskVec.asUInt.orR && (i.U < io.peakChannelReq.bits.needed_channel_num) - selectedChannelIds(i) := Mux(selectedMask(i), selIdx, 0.U) - if (i < numChannels) { - masks(i + 1) := VecInit(maskVec.zip(selOH.asBools).map { case (free, sel) => free && !sel }) - } - } - - io.freeChannelResp.valid := io.peakChannelReq.valid - io.freeChannelResp.bits.is_free := hasEnoughChannels - io.freeChannelResp.bits.channel_ids := selectedChannelIds - io.freeChannelResp.bits.channel_num := io.peakChannelReq.bits.needed_channel_num - io.peakChannelReq.ready := io.freeChannelResp.ready -} diff --git a/arch/src/main/scala/framework/top/channels/headerBuffer.scala b/arch/src/main/scala/framework/top/channels/headerBuffer.scala deleted file mode 100644 index f6a90de7..00000000 --- a/arch/src/main/scala/framework/top/channels/headerBuffer.scala +++ /dev/null @@ -1,30 +0,0 @@ -package framework.top.channels - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import framework.top.GlobalConfig - -class HeaderBufferData(val b: GlobalConfig) extends Bundle { - val lock = Bool() - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) - val bank_id = UInt(log2Up(b.memDomain.bankNum).W) -} - -@instantiable -class HeaderBuffer(val b: GlobalConfig) extends Module { - - @public - val io = IO(new Bundle { - val read = Output(new HeaderBufferData(b)) - val set = Flipped(Decoupled(new HeaderBufferData(b))) - }) - - val reg = RegInit(0.U.asTypeOf(new HeaderBufferData(b))) - - io.read := reg - io.set.ready := !reg.lock || (io.set.bits.lock === false.B) - when(io.set.fire) { - reg := io.set.bits - } -} diff --git a/docs b/docs index ae40fa84..476014bb 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit ae40fa845f9d8463d588f6d85bef9214074396a5 +Subproject commit 476014bb12802817a5d70e61298935b8c4195a23 From 031619355431f5b71f7ff680b8edc3d5b9461123 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 20 Mar 2026 19:30:10 +0800 Subject: [PATCH 181/238] [arch] feat: introduce GlobalScheduler and BAT to support new scheduling mechanism [bdb] refactor: refomat trace files --- arch/src/csrc/include/bdb.h | 3 +- arch/src/csrc/include/monitor/trace_cfg.h | 22 ++ arch/src/csrc/include/utils/macro.h | 32 +++ arch/src/csrc/src/monitor/monitor.cc | 75 ++++- arch/src/csrc/src/monitor/trace/ctrace.cc | 50 +++- arch/src/csrc/src/monitor/trace/itrace.cc | 30 +- arch/src/csrc/src/monitor/trace/mtrace.cc | 55 ++-- arch/src/csrc/src/monitor/trace/pmctrace.cc | 23 +- .../examples/toy/balldomain/BallDomain.scala | 6 +- .../scala/framework/frontend/Frontend.scala | 46 ++-- .../frontend/configs/FrontendParam.scala | 1 + .../framework/frontend/configs/default.json | 1 + .../frontend/globalrs/GlobalROB.scala | 59 ++-- .../globalrs/GlobalReservationStation.scala | 260 ------------------ .../frontend/globalrs/GlobalScheduler.scala | 194 +++++++++++++ .../framework/frontend/globalrs/SubROB.scala | 9 + .../frontend/scoreboard/BankAliasTable.scala | 128 +++++++++ .../scala/framework/gpdomain/GPDomain.scala | 6 +- .../gpdomain/sequencer/Sequencer.scala | 6 +- .../scala/framework/memdomain/MemDomain.scala | 6 +- .../memdomain/frontend/MemFrontend.scala | 6 +- bbdev | 2 +- 22 files changed, 646 insertions(+), 374 deletions(-) create mode 100644 arch/src/csrc/include/monitor/trace_cfg.h delete mode 100644 arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala create mode 100644 arch/src/main/scala/framework/frontend/globalrs/GlobalScheduler.scala create mode 100644 arch/src/main/scala/framework/frontend/scoreboard/BankAliasTable.scala diff --git a/arch/src/csrc/include/bdb.h b/arch/src/csrc/include/bdb.h index 9a5e4704..5ba2d7f3 100644 --- a/arch/src/csrc/include/bdb.h +++ b/arch/src/csrc/include/bdb.h @@ -2,12 +2,13 @@ #define _BDB_H_ // DPI-C -#include "verilated_dpi.h" #include "svdpi.h" +#include "verilated_dpi.h" // verilator #include "verilated.h" #include "VBBSimHarness.h" +#include "monitor/trace_cfg.h" #include "verilated_fst_c.h" #if VM_COVERAGE #include "verilated_cov.h" diff --git a/arch/src/csrc/include/monitor/trace_cfg.h b/arch/src/csrc/include/monitor/trace_cfg.h new file mode 100644 index 00000000..2837ff04 --- /dev/null +++ b/arch/src/csrc/include/monitor/trace_cfg.h @@ -0,0 +1,22 @@ +#ifndef MONITOR_TRACE_CFG_H_ +#define MONITOR_TRACE_CFG_H_ + +#include + +enum { + BDB_TR_ITRACE = 1u << 0, + BDB_TR_MTRACE = 1u << 1, + BDB_TR_PMCTRACE = 1u << 2, + BDB_TR_CTRACE = 1u << 3, + BDB_TR_BANKTRACE = 1u << 4, + BDB_TR_ALL = BDB_TR_ITRACE | BDB_TR_MTRACE | BDB_TR_PMCTRACE | BDB_TR_CTRACE | + BDB_TR_BANKTRACE +}; + +extern uint32_t bdb_trace_mask; + +static inline int bdb_trace_on(uint32_t bit) { + return (bdb_trace_mask & bit) != 0; +} + +#endif diff --git a/arch/src/csrc/include/utils/macro.h b/arch/src/csrc/include/utils/macro.h index e1b6eae9..7f5ab44c 100644 --- a/arch/src/csrc/include/utils/macro.h +++ b/arch/src/csrc/include/utils/macro.h @@ -4,6 +4,8 @@ // macro stringizing #define str_temp(x) #x #define str(x) str_temp(x) +#define concat_temp(x, y) x##y +#define concat(x, y) concat_temp(x, y) // array length #define ARRLEN(arr) (int)(sizeof(arr) / sizeof(arr[0])) @@ -17,4 +19,34 @@ #define unlikely(cond) __builtin_expect(cond, 0) #endif +// See +// https://stackoverflow.com/questions/26099745/test-if-preprocessor-symbol-is-defined-inside-macro +#define CHOOSE2nd(a, b, ...) b +#define MUX_WITH_COMMA(contain_comma, a, b) CHOOSE2nd(contain_comma a, b) +#define MUX_MACRO_PROPERTY(p, macro, a, b) \ + MUX_WITH_COMMA(concat(p, macro), a, b) +// define placeholders for some property +#define __P_DEF_0 X, +#define __P_DEF_1 X, +#define __P_ONE_1 X, +#define __P_ZERO_0 X, +// define some selection functions based on the properties of BOOLEAN macro +#define MUXDEF(macro, X, Y) MUX_MACRO_PROPERTY(__P_DEF_, macro, X, Y) +// if defined, then X, otherwise Y +#define MUXNDEF(macro, X, Y) MUX_MACRO_PROPERTY(__P_DEF_, macro, Y, X) +#define MUXONE(macro, X, Y) MUX_MACRO_PROPERTY(__P_ONE_, macro, X, Y) +#define MUXZERO(macro, X, Y) MUX_MACRO_PROPERTY(__P_ZERO_, macro, X, Y) + +// simplification for conditional compilation +#define __IGNORE(...) +#define __KEEP(...) __VA_ARGS__ +// keep the code if a boolean macro is defined +#define IFDEF(macro, ...) MUXDEF(macro, __KEEP, __IGNORE)(__VA_ARGS__) +// keep the code if a boolean macro is undefined +#define IFNDEF(macro, ...) MUXNDEF(macro, __KEEP, __IGNORE)(__VA_ARGS__) +// keep the code if a boolean macro is defined to 1 +#define IFONE(macro, ...) MUXONE(macro, __KEEP, __IGNORE)(__VA_ARGS__) +// keep the code if a boolean macro is defined to 0 +#define IFZERO(macro, ...) MUXZERO(macro, __KEEP, __IGNORE)(__VA_ARGS__) + #endif diff --git a/arch/src/csrc/src/monitor/monitor.cc b/arch/src/csrc/src/monitor/monitor.cc index 185cce3c..b10219df 100644 --- a/arch/src/csrc/src/monitor/monitor.cc +++ b/arch/src/csrc/src/monitor/monitor.cc @@ -10,14 +10,46 @@ #include "utils/welcome.cc" // Define global path variables -const char *log_path = nullptr; -const char *fst_path = nullptr; +const char *log_path = nullptr; +const char *fst_path = nullptr; const char *stdout_path = nullptr; +uint32_t bdb_trace_mask = BDB_TR_ALL; -// Raw stdout fd saved before dup2 redirect — used by UART putchar for real-time display. +// Raw stdout fd saved before dup2 redirect — used by UART putchar for real-time +// display. int raw_stdout_fd = -1; static int parse_args(int argc, char *argv[]) { + auto parse_trace_list = [](const char *list) { + if (list == nullptr || *list == '\0') { + return; + } + char buf[256]; + int n = snprintf(buf, sizeof(buf), "%s", list); + Assert(n >= 0 && n < (int)sizeof(buf), "trace option too long: %s", list); + char *tok = strtok(buf, ","); + while (tok != NULL) { + if (strcmp(tok, "all") == 0) { + bdb_trace_mask = BDB_TR_ALL; + } else if (strcmp(tok, "none") == 0) { + bdb_trace_mask = 0; + } else if (strcmp(tok, "itrace") == 0) { + bdb_trace_mask |= BDB_TR_ITRACE; + } else if (strcmp(tok, "mtrace") == 0) { + bdb_trace_mask |= BDB_TR_MTRACE; + } else if (strcmp(tok, "pmctrace") == 0) { + bdb_trace_mask |= BDB_TR_PMCTRACE; + } else if (strcmp(tok, "ctrace") == 0) { + bdb_trace_mask |= BDB_TR_CTRACE; + } else if (strcmp(tok, "banktrace") == 0) { + bdb_trace_mask |= BDB_TR_BANKTRACE; + } else { + panic("Unknown +trace item: %s", tok); + } + tok = strtok(NULL, ","); + } + }; + for (int i = 1; i < argc; i++) { if (strncmp(argv[i], "+fst=", 5) == 0) { fst_path = argv[i] + 5; @@ -25,6 +57,15 @@ static int parse_args(int argc, char *argv[]) { log_path = argv[i] + 5; } else if (strncmp(argv[i], "+stdout=", 8) == 0) { stdout_path = argv[i] + 8; + } else if (strncmp(argv[i], "+trace_mask=", 12) == 0) { + char *end = NULL; + unsigned long v = strtoul(argv[i] + 12, &end, 0); + Assert(end && *end == '\0', "Invalid +trace_mask value: %s", + argv[i] + 12); + bdb_trace_mask = (uint32_t)v; + } else if (strncmp(argv[i], "+trace=", 7) == 0) { + bdb_trace_mask = 0; + parse_trace_list(argv[i] + 7); } else if (strcmp(argv[i], "+batch") == 0) { bdb_set_batch_mode(); } else if (strcmp(argv[i], "+help") == 0) { @@ -33,10 +74,15 @@ static int parse_args(int argc, char *argv[]) { printf("\t+log= specify log file path\n"); printf("\t+stdout= specify UART output file path\n"); printf("\t+fst= specify FST waveform file path\n"); + printf("\t+trace= trace list: " + "none|all|itrace,mtrace,pmctrace,ctrace,banktrace\n"); + printf("\t+trace_mask= bitfield itrace=1 mtrace=2 pmctrace=4 " + "ctrace=8 banktrace=16\n"); printf("\n"); exit(0); } - // +elf= is parsed by SimDRAM_bb.cc via vpi_get_vlog_info (Verilator plusargs) + // +elf= is parsed by SimDRAM_bb.cc via vpi_get_vlog_info (Verilator + // plusargs) } Assert(log_path, "Log file path is required. Use +log= to specify."); @@ -46,16 +92,25 @@ static int parse_args(int argc, char *argv[]) { static void init_log(const char *log_file) { if (log_file != NULL) { - // Save original stdout fd for UART real-time display + // Keep a dedicated fd for UART real-time display. + // Do not redirect stdout to trace file, otherwise NDJSON is polluted. raw_stdout_fd = dup(STDOUT_FILENO); + Assert(raw_stdout_fd >= 0, "dup(STDOUT_FILENO) failed"); FILE *fp = fopen(log_file, "w"); Assert(fp, "Can not open '%s'", log_file); - // Redirect stdout to bdb.log for Log() / DPI-C printf output - fflush(stdout); - dup2(fileno(fp), STDOUT_FILENO); - fclose(fp); + fclose(fp); // truncate/create file; trace writers append NDJSON later + } + if (log_file) { + fprintf(stderr, "NDJSON trace is written to %s\n", log_file); + fprintf(stderr, + "Trace mask=0x%X [itrace=%d mtrace=%d pmctrace=%d ctrace=%d " + "banktrace=%d]\n", + bdb_trace_mask, bdb_trace_on(BDB_TR_ITRACE), + bdb_trace_on(BDB_TR_MTRACE), bdb_trace_on(BDB_TR_PMCTRACE), + bdb_trace_on(BDB_TR_CTRACE), bdb_trace_on(BDB_TR_BANKTRACE)); + } else { + fprintf(stderr, "NDJSON trace path is not set\n"); } - Log("Log is written to %s", log_file ? log_file : "stdout"); } static void init_io() { diff --git a/arch/src/csrc/src/monitor/trace/ctrace.cc b/arch/src/csrc/src/monitor/trace/ctrace.cc index aa9d30db..5b14ca5b 100644 --- a/arch/src/csrc/src/monitor/trace/ctrace.cc +++ b/arch/src/csrc/src/monitor/trace/ctrace.cc @@ -1,4 +1,5 @@ #include "monitor/trace.h" +#include "monitor/trace_cfg.h" #include "utils/debug.h" #include #include @@ -42,6 +43,14 @@ static void init_ctrace() { } } +static void u128_hex(char *buf, size_t n, unsigned long long hi, + unsigned long long lo) { + int ret = snprintf(buf, n, "0x%016llX%016llX", hi, lo); + if (ret < 0 || (size_t)ret >= n) { + panic("snprintf failed in ctrace u128_hex"); + } +} + // ================================================================ // Cycle counter DPI-C // ================================================================ @@ -49,23 +58,30 @@ static void init_ctrace() { extern "C" void dpi_ctrace(unsigned char subcmd, unsigned int ctr_id, unsigned long long tag, unsigned long long elapsed, unsigned long long cycle) { + if (!bdb_trace_on(BDB_TR_CTRACE)) { + return; + } init_ctrace(); if (ctrace_fp) { switch (subcmd) { case 0: // CTR_START - fprintf(ctrace_fp, "[CTRACE] CTR_START ctr=%u tag=0x%llX cycle=%llu\n", + fprintf(ctrace_fp, + "{\"type\":\"ctrace\",\"event\":\"ctr_start\",\"ctr_id\":%u," + "\"tag\":\"0x%llX\",\"cycle\":%llu}\n", ctr_id, tag, cycle); break; case 1: // CTR_STOP fprintf(ctrace_fp, - "[CTRACE] CTR_STOP ctr=%u tag=0x%llX elapsed=%llu cycle=%llu\n", + "{\"type\":\"ctrace\",\"event\":\"ctr_stop\",\"ctr_id\":%u," + "\"tag\":\"0x%llX\",\"elapsed\":%llu,\"cycle\":%llu}\n", ctr_id, tag, elapsed, cycle); break; case 2: // CTR_READ fprintf(ctrace_fp, - "[CTRACE] CTR_READ ctr=%u current=%llu cycle=%llu\n", ctr_id, - elapsed, cycle); + "{\"type\":\"ctrace\",\"event\":\"ctr_read\",\"ctr_id\":%u," + "\"current\":%llu,\"cycle\":%llu}\n", + ctr_id, elapsed, cycle); break; } fflush(ctrace_fp); @@ -104,32 +120,42 @@ extern "C" void dpi_backdoor_get_write_data(unsigned long long *data_lo, *data_hi = bd_write_data_hi; } -// RTL calls this after reading SRAM — logs the data to bdb.log +// RTL calls this after reading SRAM — logs the data to NDJSON trace file extern "C" void dpi_backdoor_put_read_data(unsigned int bank_id, unsigned int row, unsigned long long data_lo, unsigned long long data_hi) { + if (!bdb_trace_on(BDB_TR_BANKTRACE)) { + return; + } init_ctrace(); if (ctrace_fp) { + char data_hex[35]; + u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); fprintf(ctrace_fp, - "[BANK-TRACE] BACKDOOR_READ bank=%u row=%u " - "data=0x%016llX%016llX\n", - bank_id, row, data_hi, data_lo); + "{\"type\":\"banktrace\",\"event\":\"backdoor_read\"," + "\"bank_id\":%u,\"row\":%u,\"data\":\"%s\"}\n", + bank_id, row, data_hex); fflush(ctrace_fp); } } -// RTL calls this after writing SRAM — logs the write to bdb.log +// RTL calls this after writing SRAM — logs the write to NDJSON trace file extern "C" void dpi_backdoor_put_write_done(unsigned int bank_id, unsigned int row, unsigned long long data_lo, unsigned long long data_hi) { + if (!bdb_trace_on(BDB_TR_BANKTRACE)) { + return; + } init_ctrace(); if (ctrace_fp) { + char data_hex[35]; + u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); fprintf(ctrace_fp, - "[BANK-TRACE] BACKDOOR_WRITE bank=%u row=%u " - "data=0x%016llX%016llX\n", - bank_id, row, data_hi, data_lo); + "{\"type\":\"banktrace\",\"event\":\"backdoor_write\"," + "\"bank_id\":%u,\"row\":%u,\"data\":\"%s\"}\n", + bank_id, row, data_hex); fflush(ctrace_fp); } } diff --git a/arch/src/csrc/src/monitor/trace/itrace.cc b/arch/src/csrc/src/monitor/trace/itrace.cc index dad62f6c..46fe57a2 100644 --- a/arch/src/csrc/src/monitor/trace/itrace.cc +++ b/arch/src/csrc/src/monitor/trace/itrace.cc @@ -1,4 +1,5 @@ #include "monitor/trace.h" +#include "monitor/trace_cfg.h" #include "utils/debug.h" #include #include @@ -37,24 +38,43 @@ static const char *bank_enable_str(unsigned char enable) { } } +static void u64_hex(char *buf, size_t n, unsigned long long v) { + int ret = snprintf(buf, n, "0x%016llx", v); + if (ret < 0 || (size_t)ret >= n) { + panic("snprintf failed in itrace u64_hex"); + } +} + // DPI-C function for instruction trace (itrace) // Called when an instruction is issued or completed in GlobalROB extern "C" void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete unsigned int rob_id, unsigned int domain_id, unsigned int funct, unsigned long long rs1, unsigned long long rs2, unsigned char bank_enable) { + if (!bdb_trace_on(BDB_TR_ITRACE)) { + return; + } init_itrace(); if (itrace_fp) { + char rs1_hex[19]; + char rs2_hex[19]; + u64_hex(rs1_hex, sizeof(rs1_hex), rs1); + u64_hex(rs2_hex, sizeof(rs2_hex), rs2); if (is_issue) { fprintf(itrace_fp, - "[ITRACE] ISSUE rob_id=%u domain=%u funct=0x%02x " - "bank=%s rs1=0x%016llx rs2=0x%016llx\n", - rob_id, domain_id, funct, bank_enable_str(bank_enable), rs1, rs2); + "{\"type\":\"itrace\",\"event\":\"issue\",\"rob_id\":%u," + "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," + "\"bank\":\"%s\",\"rs1\":\"%s\",\"rs2\":\"%s\"}\n", + rob_id, domain_id, funct, bank_enable, + bank_enable_str(bank_enable), rs1_hex, rs2_hex); } else { fprintf(itrace_fp, - "[ITRACE] COMPLETE rob_id=%u domain=%u funct=0x%02x bank=%s\n", - rob_id, domain_id, funct, bank_enable_str(bank_enable)); + "{\"type\":\"itrace\",\"event\":\"complete\",\"rob_id\":%u," + "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," + "\"bank\":\"%s\"}\n", + rob_id, domain_id, funct, bank_enable, + bank_enable_str(bank_enable)); } fflush(itrace_fp); } diff --git a/arch/src/csrc/src/monitor/trace/mtrace.cc b/arch/src/csrc/src/monitor/trace/mtrace.cc index 5ce7b3c6..cd6a8169 100644 --- a/arch/src/csrc/src/monitor/trace/mtrace.cc +++ b/arch/src/csrc/src/monitor/trace/mtrace.cc @@ -1,4 +1,5 @@ #include "monitor/trace.h" +#include "monitor/trace_cfg.h" #include "utils/debug.h" #include #include @@ -8,46 +9,50 @@ extern const char *log_path; static FILE *mtrace_fp = NULL; // Initialize mtrace logging -static void init_mtrace() -{ - if (mtrace_fp == NULL && log_path != NULL) - { +static void init_mtrace() { + if (mtrace_fp == NULL && log_path != NULL) { mtrace_fp = fopen(log_path, "a"); - if (mtrace_fp == NULL) - { + if (mtrace_fp == NULL) { panic("Failed to open mtrace log file: %s", log_path); } } } +static void u128_hex(char *buf, size_t n, unsigned long long hi, + unsigned long long lo) { + int ret = snprintf(buf, n, "0x%016llx%016llx", hi, lo); + if (ret < 0 || (size_t)ret >= n) { + panic("snprintf failed in mtrace u128_hex"); + } +} + // DPI-C function for memory trace (mtrace) // Called when MemBackend performs read/write operations extern "C" void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read - unsigned char is_shared, - unsigned int channel, unsigned long long hart_id, - unsigned int vbank_id, + unsigned char is_shared, unsigned int channel, + unsigned long long hart_id, unsigned int vbank_id, unsigned int group_id, unsigned int addr, unsigned long long data_lo, - unsigned long long data_hi) -{ + unsigned long long data_hi) { + if (!bdb_trace_on(BDB_TR_MTRACE)) { + return; + } init_mtrace(); - if (mtrace_fp) - { - if (is_write) - { + if (mtrace_fp) { + char data_hex[35]; + if (is_write) { + u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); fprintf(mtrace_fp, - "[MTRACE] WRITE ch=%u hart=%llu shared=%u vbank=%u group=%u " - "addr=0x%08x " - "data=0x%016llx%016llx\n", - channel, hart_id, is_shared, vbank_id, group_id, addr, data_hi, - data_lo); - } - else - { + "{\"type\":\"mtrace\",\"event\":\"write\",\"channel\":%u," + "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," + "\"group_id\":%u,\"addr\":\"0x%08x\",\"data\":\"%s\"}\n", + channel, hart_id, is_shared, vbank_id, group_id, addr, data_hex); + } else { fprintf(mtrace_fp, - "[MTRACE] READ ch=%u hart=%llu shared=%u vbank=%u group=%u " - "addr=0x%08x\n", + "{\"type\":\"mtrace\",\"event\":\"read\",\"channel\":%u," + "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," + "\"group_id\":%u,\"addr\":\"0x%08x\"}\n", channel, hart_id, is_shared, vbank_id, group_id, addr); } fflush(mtrace_fp); diff --git a/arch/src/csrc/src/monitor/trace/pmctrace.cc b/arch/src/csrc/src/monitor/trace/pmctrace.cc index ec5784c4..daefcb89 100644 --- a/arch/src/csrc/src/monitor/trace/pmctrace.cc +++ b/arch/src/csrc/src/monitor/trace/pmctrace.cc @@ -1,4 +1,5 @@ #include "monitor/trace.h" +#include "monitor/trace_cfg.h" #include "utils/debug.h" #include #include @@ -21,10 +22,15 @@ static void init_pmctrace() { // Called when a Ball completes a task, reports elapsed cycles extern "C" void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, unsigned long long elapsed) { + if (!bdb_trace_on(BDB_TR_PMCTRACE)) { + return; + } init_pmctrace(); if (pmctrace_fp) { - fprintf(pmctrace_fp, "[PMCTRACE] BALL ball_id=%u rob_id=%u elapsed=%llu\n", + fprintf(pmctrace_fp, + "{\"type\":\"pmctrace\",\"event\":\"ball\",\"ball_id\":%u," + "\"rob_id\":%u,\"elapsed\":%llu}\n", ball_id, rob_id, elapsed); fflush(pmctrace_fp); } @@ -34,15 +40,22 @@ extern "C" void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, // Called when a load/store completes, reports elapsed cycles extern "C" void dpi_mem_pmctrace(unsigned char is_store, unsigned int rob_id, unsigned long long elapsed) { + if (!bdb_trace_on(BDB_TR_PMCTRACE)) { + return; + } init_pmctrace(); if (pmctrace_fp) { if (is_store) { - fprintf(pmctrace_fp, "[PMCTRACE] STORE rob_id=%u elapsed=%llu\n", rob_id, - elapsed); + fprintf(pmctrace_fp, + "{\"type\":\"pmctrace\",\"event\":\"store\"," + "\"rob_id\":%u,\"elapsed\":%llu}\n", + rob_id, elapsed); } else { - fprintf(pmctrace_fp, "[PMCTRACE] LOAD rob_id=%u elapsed=%llu\n", rob_id, - elapsed); + fprintf(pmctrace_fp, + "{\"type\":\"pmctrace\",\"event\":\"load\"," + "\"rob_id\":%u,\"elapsed\":%llu}\n", + rob_id, elapsed); } fflush(pmctrace_fp); } diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala index 9c274b9f..9e9541e3 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala @@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import framework.top.GlobalConfig import examples.toy.balldomain.bbus.BBusModule -import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} import framework.balldomain.rs.BallReservationStation @@ -18,10 +18,10 @@ class BallDomain(val b: GlobalConfig) extends Module { val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum @public - val global_issue_i = IO(Flipped(Decoupled(new GlobalRsIssue(b)))) + val global_issue_i = IO(Flipped(Decoupled(new GlobalSchedIssue(b)))) @public - val global_complete_o = IO(Decoupled(new GlobalRsComplete(b))) + val global_complete_o = IO(Decoupled(new GlobalSchedComplete(b))) @public val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) diff --git a/arch/src/main/scala/framework/frontend/Frontend.scala b/arch/src/main/scala/framework/frontend/Frontend.scala index f27bb088..85e5053f 100644 --- a/arch/src/main/scala/framework/frontend/Frontend.scala +++ b/arch/src/main/scala/framework/frontend/Frontend.scala @@ -4,14 +4,14 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.frontend.decoder.{GlobalDecoder, PostGDCmd} -import framework.frontend.globalrs.{GlobalReservationStation, GlobalRsComplete, GlobalRsIssue} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue, GlobalScheduler} import framework.top.GlobalConfig import framework.core.bbtile.{RoCCCommandBB, RoCCResponseBB} import framework.balldomain.blink.SubRobRow /** * Frontend Module - * Encapsulates GlobalDecoder and GlobalReservationStation + * Encapsulates GlobalDecoder and global scheduler */ @instantiable class Frontend(val b: GlobalConfig) extends Module { @@ -25,13 +25,13 @@ class Frontend(val b: GlobalConfig) extends Module { })) // Issue to domains - val ball_issue_o = Decoupled(new GlobalRsIssue(b)) - val mem_issue_o = Decoupled(new GlobalRsIssue(b)) - val gp_issue_o = Decoupled(new GlobalRsIssue(b)) + val ball_issue_o = Decoupled(new GlobalSchedIssue(b)) + val mem_issue_o = Decoupled(new GlobalSchedIssue(b)) + val gp_issue_o = Decoupled(new GlobalSchedIssue(b)) // Complete from domains - val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) - val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) - val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) + val ball_complete_i = Flipped(Decoupled(new GlobalSchedComplete(b))) + val mem_complete_i = Flipped(Decoupled(new GlobalSchedComplete(b))) + val gp_complete_i = Flipped(Decoupled(new GlobalSchedComplete(b))) // Ball -> SubROB request passthrough val ball_subrob_req_i = Flipped(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) @@ -45,33 +45,33 @@ class Frontend(val b: GlobalConfig) extends Module { val barrier_release = Input(Bool()) }) - val gDecoder: Instance[GlobalDecoder] = Instantiate(new GlobalDecoder(b)) - val globalRs: Instance[GlobalReservationStation] = Instantiate(new GlobalReservationStation(b)) + val gDecoder: Instance[GlobalDecoder] = Instantiate(new GlobalDecoder(b)) + val scheduler: Instance[GlobalScheduler] = Instantiate(new GlobalScheduler(b)) gDecoder.io.id_i.valid := io.cmd.valid gDecoder.io.id_i.bits.cmd := io.cmd.bits.cmd io.cmd.ready := gDecoder.io.id_i.ready - globalRs.io.global_decode_cmd_i <> gDecoder.io.id_o + scheduler.io.decode_cmd_i <> gDecoder.io.id_o - io.ball_issue_o <> globalRs.io.ball_issue_o - io.mem_issue_o <> globalRs.io.mem_issue_o - io.gp_issue_o <> globalRs.io.gp_issue_o + io.ball_issue_o <> scheduler.io.ball_issue_o + io.mem_issue_o <> scheduler.io.mem_issue_o + io.gp_issue_o <> scheduler.io.gp_issue_o - globalRs.io.ball_complete_i <> io.ball_complete_i - globalRs.io.mem_complete_i <> io.mem_complete_i - globalRs.io.gp_complete_i <> io.gp_complete_i + scheduler.io.ball_complete_i <> io.ball_complete_i + scheduler.io.mem_complete_i <> io.mem_complete_i + scheduler.io.gp_complete_i <> io.gp_complete_i - // Wire SubROB request from BallDomain through to GlobalRS + // Wire SubROB request from BallDomain through to scheduler for (i <- 0 until b.ballDomain.ballNum) { - globalRs.io.ball_subrob_req_i(i) <> io.ball_subrob_req_i(i) + scheduler.io.ball_subrob_req_i(i) <> io.ball_subrob_req_i(i) } - io.resp <> globalRs.io.rs_rocc_o.resp - io.busy := globalRs.io.rs_rocc_o.busy + io.resp <> scheduler.io.scheduler_rocc_o.resp + io.busy := scheduler.io.scheduler_rocc_o.busy // Barrier passthrough - io.barrier_arrive := globalRs.io.barrier_arrive - globalRs.io.barrier_release := io.barrier_release + io.barrier_arrive := scheduler.io.barrier_arrive + scheduler.io.barrier_release := io.barrier_release } diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index 912efe81..fbfcab33 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -9,6 +9,7 @@ case class FrontendParam( rob_entries: Int, rs_out_of_order_response: Boolean, bank_id_len: Int, + vbank_id_upper_bound: Int, iter_len: Int, sub_rob_depth: Int) diff --git a/arch/src/main/scala/framework/frontend/configs/default.json b/arch/src/main/scala/framework/frontend/configs/default.json index f5df56ce..7612f4c0 100644 --- a/arch/src/main/scala/framework/frontend/configs/default.json +++ b/arch/src/main/scala/framework/frontend/configs/default.json @@ -2,6 +2,7 @@ "rob_entries": 16, "rs_out_of_order_response": true, "bank_id_len": 10, + "vbank_id_upper_bound": 31, "iter_len": 34, "sub_rob_depth": 64 } diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index 5d9a0b9b..f35b03fa 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -6,14 +6,19 @@ import chisel3.experimental._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig import framework.frontend.decoder.PostGDCmd -import framework.frontend.scoreboard.BankScoreboard +import framework.frontend.scoreboard.{BankAliasTable, BankScoreboard} @instantiable class GlobalROB(val b: GlobalConfig) extends Module { - val robDepth = b.frontend.rob_entries - val idWidth = log2Up(robDepth) - val bankIdLen = b.frontend.bank_id_len + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) + val scoreBankNum = 1 << b.frontend.bank_id_len + + require( + b.frontend.vbank_id_upper_bound < b.memDomain.bankNum, + s"vbank_id_upper_bound(${b.frontend.vbank_id_upper_bound}) must be < memDomain.bankNum(${b.memDomain.bankNum})" + ) @public val io = IO(new Bundle { @@ -32,9 +37,17 @@ class GlobalROB(val b: GlobalConfig) extends Module { }) // --------------------------------------------------------------------------- - // Bank Scoreboard + // BAT + Bank Scoreboard // --------------------------------------------------------------------------- - val scoreboard: Instance[BankScoreboard] = Instantiate(new BankScoreboard(b.memDomain.bankNum, robDepth)) + val bat: Instance[BankAliasTable] = Instantiate( + new BankAliasTable( + bankIdLen = b.frontend.bank_id_len, + vbankUpper = b.frontend.vbank_id_upper_bound, + robEntries = robDepth + ) + ) + + val scoreboard: Instance[BankScoreboard] = Instantiate(new BankScoreboard(scoreBankNum, robDepth)) // --------------------------------------------------------------------------- // Instruction trace (DPI-C, defined in ITraceDPI.scala) @@ -71,15 +84,26 @@ class GlobalROB(val b: GlobalConfig) extends Module { // Allocate: enqueue decoded instruction into ROB // rob_id == tailPtr at allocation time (no separate counter needed) // --------------------------------------------------------------------------- - io.alloc.ready := !isFull + io.alloc.ready := !isFull + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask when(io.alloc.fire) { - robEntries(tailPtr).cmd := io.alloc.bits - robEntries(tailPtr).rob_id := tailPtr - robValid(tailPtr) := true.B - robIssued(tailPtr) := false.B - robComplete(tailPtr) := false.B - tailPtr := nextPtr(tailPtr) + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + tailPtr := nextPtr(tailPtr) } // --------------------------------------------------------------------------- @@ -97,7 +121,7 @@ class GlobalROB(val b: GlobalConfig) extends Module { issuedCount := issuedCount - 1.U } scoreboard.complete.valid := true.B - scoreboard.complete.bits := robEntries(cid).cmd.bankAccess + scoreboard.complete.bits := robEntries(cid).renamedBankAccess itrace.io.is_issue := 0.U itrace.io.rob_id := cid @@ -122,7 +146,7 @@ class GlobalROB(val b: GlobalConfig) extends Module { val firstValid = PriorityEncoder(scanValid.asUInt) val actualIssuePtr = wrapPtr(headPtr + firstValid) - scoreboard.query := robEntries(actualIssuePtr).cmd.bankAccess + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess val noHazard = !scoreboard.hasHazard val canIssue = hasValid && noHazard @@ -136,7 +160,7 @@ class GlobalROB(val b: GlobalConfig) extends Module { robIssued(actualIssuePtr) := true.B issuedCount := issuedCount + 1.U scoreboard.issue.valid := true.B - scoreboard.issue.bits := robEntries(actualIssuePtr).cmd.bankAccess + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess itrace.io.is_issue := 1.U itrace.io.rob_id := robEntries(actualIssuePtr).rob_id @@ -155,7 +179,8 @@ class GlobalROB(val b: GlobalConfig) extends Module { for (i <- 0 until robDepth) { val beingAllocated = io.alloc.fire && (tailPtr === i.U) val beingCompleted = io.complete.fire && (io.complete.bits === i.U) - when(robValid(i) && robComplete(i) && !beingAllocated && !beingCompleted) { + commitMask(i) := robValid(i) && robComplete(i) && !beingAllocated && !beingCompleted + when(commitMask(i)) { robValid(i) := false.B robIssued(i) := false.B robComplete(i) := false.B diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala deleted file mode 100644 index 134113c4..00000000 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalReservationStation.scala +++ /dev/null @@ -1,260 +0,0 @@ -package framework.frontend.globalrs - -import chisel3._ -import chisel3.util._ -import chisel3.experimental._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.top.GlobalConfig -import framework.frontend.decoder.{DomainId, PostGDCmd} -import framework.frontend.decoder.GISA._ -import framework.frontend.scoreboard.{BankAccessInfo, BankScoreboard} -import framework.core.bbtile.RoCCResponseBB -import framework.balldomain.blink.SubRobRow - -// Global ROB entry - contains instruction + bank access info -class GlobalRobEntry(val b: GlobalConfig) extends Bundle { - val cmd = new PostGDCmd(b) - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) -} - -// Global RS issue interface -class GlobalRsIssue(b: GlobalConfig) extends GlobalRobEntry(b) { - val is_sub = Bool() - val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) -} - -// Global RS completion interface -class GlobalRsComplete(b: GlobalConfig) extends Bundle { - val rob_id = UInt(log2Up(b.frontend.rob_entries).W) - val is_sub = Bool() - val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) -} - -// Global reservation station - between GlobalDecoder and each Domain -@instantiable -class GlobalReservationStation(val b: GlobalConfig) extends Module { - - @public - val io = IO(new Bundle { - // GlobalDecoder -> Global RS - val global_decode_cmd_i = Flipped(new DecoupledIO(new PostGDCmd(b))) - // Global RS -> BallDomain - // -> MemDomain - // -> GpDomain - val ball_issue_o = Decoupled(new GlobalRsIssue(b)) - val mem_issue_o = Decoupled(new GlobalRsIssue(b)) - val gp_issue_o = Decoupled(new GlobalRsIssue(b)) - // BallDomain -> Global RS - // MemDomain -> - // GpDomain -> - val ball_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) - val mem_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) - val gp_complete_i = Flipped(Decoupled(new GlobalRsComplete(b))) - - // Ball -> SubROB: write a row of sub-instructions - val ball_subrob_req_i = Flipped(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) - - // RoCC response - val rs_rocc_o = new Bundle { - val resp = new DecoupledIO(new RoCCResponseBB(b.core.xLen)) - val busy = Output(Bool()) - } - - // Barrier interface — connected to tile-level BarrierUnit via BuckyballAccelerator - val barrier_arrive = Output(Bool()) - val barrier_release = Input(Bool()) - }) - - val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) - val subRob: Instance[SubROB] = Instantiate(new SubROB(b)) - -// ----------------------------------------------------------------------------- -// Fence handling — fence does NOT enter ROB. -// When a fence arrives, hold busy (stop CPU) until ROB drains completely. -// ----------------------------------------------------------------------------- - val isFenceCmd = io.global_decode_cmd_i.valid && io.global_decode_cmd_i.bits.isFence - - // Fence active state: set when fence arrives, cleared when ROB is empty - val fenceActive = RegInit(false.B) - when(isFenceCmd && !fenceActive) { - fenceActive := true.B - } - when(fenceActive && rob.io.empty) { - fenceActive := false.B - } - -// ----------------------------------------------------------------------------- -// Barrier handling — barrier does NOT enter ROB. -// Two phases: -// 1. barrierWaitROB: wait for own ROB to drain (implicit fence) -// 2. barrierWaitRelease: arrive at BarrierUnit, wait for all cores -// ----------------------------------------------------------------------------- - val isBarrierCmd = io.global_decode_cmd_i.valid && io.global_decode_cmd_i.bits.isBarrier - - val barrierWaitROB = RegInit(false.B) - val barrierWaitRelease = RegInit(false.B) - - when(isBarrierCmd && !barrierWaitROB && !barrierWaitRelease && !fenceActive) { - barrierWaitROB := true.B - } - when(barrierWaitROB && rob.io.empty) { - barrierWaitROB := false.B - barrierWaitRelease := true.B - } - when(barrierWaitRelease && io.barrier_release) { - barrierWaitRelease := false.B - } - - io.barrier_arrive := barrierWaitRelease - -// ----------------------------------------------------------------------------- -// Inbound - instruction allocation (fence/barrier do not enter ROB) -// ----------------------------------------------------------------------------- - val isFrontendCmd = io.global_decode_cmd_i.bits.isFence || io.global_decode_cmd_i.bits.isBarrier - val anyStall = fenceActive || barrierWaitROB || barrierWaitRelease - - rob.io.alloc.valid := io.global_decode_cmd_i.valid && !isFrontendCmd && !anyStall - rob.io.alloc.bits := io.global_decode_cmd_i.bits - - // Backpressure: fence/barrier are consumed immediately (if not already active), - // normal cmds wait for ROB ready and no stall. - io.global_decode_cmd_i.ready := Mux( - isFrontendCmd, - !anyStall, // Accept fence/barrier if no stall active - rob.io.alloc.ready && !anyStall // Normal cmd: ROB ready and no stall - ) - -// ----------------------------------------------------------------------------- -// SubROB write arbiter -// ----------------------------------------------------------------------------- - val subRobWriteArb = Module(new Arbiter(new SubRobRow(b), b.ballDomain.ballNum)) - for (i <- 0 until b.ballDomain.ballNum) { - subRobWriteArb.io.in(i) <> io.ball_subrob_req_i(i) - } - subRob.io.write <> subRobWriteArb.io.out - -// ----------------------------------------------------------------------------- -// Outbound - instruction issue (dispatch to corresponding domain based on domain_id) -// SubROB issues take priority over main ROB issues. -// ----------------------------------------------------------------------------- - val is_ball_domain = rob.io.issue.bits.cmd.domain_id === DomainId.BALL - val is_mem_domain = rob.io.issue.bits.cmd.domain_id === DomainId.MEM - val is_gp_domain = rob.io.issue.bits.cmd.domain_id === DomainId.GP - - val subRobIssueValid = subRob.io.issue.valid - val subRobCmd = subRob.io.issue.bits // PostGDCmd - - // Build a GlobalRsIssue for the sub-instruction - val subRobIssueEntry = Wire(new GlobalRsIssue(b)) - subRobIssueEntry.cmd := subRobCmd - subRobIssueEntry.rob_id := subRob.io.issueMasterRobId - subRobIssueEntry.is_sub := true.B - subRobIssueEntry.sub_rob_id := subRob.io.issueSubId - - val subRobIssBall = subRobCmd.domain_id === DomainId.BALL - val subRobIssMem = subRobCmd.domain_id === DomainId.MEM - val subRobIssGp = subRobCmd.domain_id === DomainId.GP - - // Build main ROB issue entry with is_sub/sub_rob_id cleared - val mainIssueEntry = Wire(new GlobalRsIssue(b)) - mainIssueEntry.cmd := rob.io.issue.bits.cmd - mainIssueEntry.rob_id := rob.io.issue.bits.rob_id - mainIssueEntry.is_sub := false.B - mainIssueEntry.sub_rob_id := 0.U - - // Ball issue: SubROB priority - io.ball_issue_o.valid := Mux( - subRobIssueValid && subRobIssBall, - true.B, - rob.io.issue.valid && is_ball_domain && !subRobIssueValid - ) - io.ball_issue_o.bits := Mux(subRobIssueValid && subRobIssBall, subRobIssueEntry, mainIssueEntry) - - // Mem issue: SubROB priority - io.mem_issue_o.valid := Mux( - subRobIssueValid && subRobIssMem, - true.B, - rob.io.issue.valid && is_mem_domain && !subRobIssueValid - ) - io.mem_issue_o.bits := Mux(subRobIssueValid && subRobIssMem, subRobIssueEntry, mainIssueEntry) - - // GP issue: SubROB priority - io.gp_issue_o.valid := Mux( - subRobIssueValid && subRobIssGp, - true.B, - rob.io.issue.valid && is_gp_domain && !subRobIssueValid - ) - io.gp_issue_o.bits := Mux(subRobIssueValid && subRobIssGp, subRobIssueEntry, mainIssueEntry) - - // SubROB issue ready - subRob.io.issue.ready := - (subRobIssBall && io.ball_issue_o.ready) || - (subRobIssMem && io.mem_issue_o.ready) || - (subRobIssGp && io.gp_issue_o.ready) - - // Main ROB issue ready: yield when SubROB is issuing - rob.io.issue.ready := !subRobIssueValid && ( - (is_ball_domain && io.ball_issue_o.ready) || - (is_mem_domain && io.mem_issue_o.ready) || - (is_gp_domain && io.gp_issue_o.ready) - ) - - // Tell GlobalROB to suppress its own issue when SubROB is active - rob.io.subRobActive := subRobIssueValid - -// ----------------------------------------------------------------------------- -// Completion signal processing -// ----------------------------------------------------------------------------- - val completeArb = Module(new Arbiter(new GlobalRsComplete(b), 3)) - - // Connect Ball, Mem, and GP domain completion signals to arbiter - completeArb.io.in(0).valid := io.ball_complete_i.valid - completeArb.io.in(0).bits := io.ball_complete_i.bits - io.ball_complete_i.ready := completeArb.io.in(0).ready - - completeArb.io.in(1).valid := io.mem_complete_i.valid - completeArb.io.in(1).bits := io.mem_complete_i.bits - io.mem_complete_i.ready := completeArb.io.in(1).ready - - completeArb.io.in(2).valid := io.gp_complete_i.valid - completeArb.io.in(2).bits := io.gp_complete_i.bits - io.gp_complete_i.ready := completeArb.io.in(2).ready - - val completeBits = completeArb.io.out.bits - - // Route sub-completions to SubROB, main completions to main ROB - subRob.io.subComplete.valid := completeArb.io.out.valid && completeBits.is_sub - subRob.io.subComplete.bits := completeBits.sub_rob_id - - subRob.io.masterComplete.ready := true.B // main ROB always ready to accept masterComplete - - val normalComplete = completeArb.io.out.valid && !completeBits.is_sub - - if (b.frontend.rs_out_of_order_response) { - rob.io.complete.valid := normalComplete || subRob.io.masterComplete.valid - rob.io.complete.bits := Mux(subRob.io.masterComplete.valid, subRob.io.masterComplete.bits, completeBits.rob_id) - } else { - val isHeadComplete = Mux( - subRob.io.masterComplete.valid, - subRob.io.masterComplete.bits === rob.io.head_ptr, - completeBits.rob_id === rob.io.head_ptr - ) - rob.io.complete.valid := (normalComplete || subRob.io.masterComplete.valid) && isHeadComplete - rob.io.complete.bits := Mux(subRob.io.masterComplete.valid, subRob.io.masterComplete.bits, completeBits.rob_id) - } - - completeArb.io.out.ready := Mux( - completeBits.is_sub, - subRob.io.subComplete.ready, - rob.io.complete.ready - ) - -// ----------------------------------------------------------------------------- -// Response generation -// ----------------------------------------------------------------------------- - io.rs_rocc_o.resp.valid := false.B - io.rs_rocc_o.resp.bits.rd := 0.U - io.rs_rocc_o.resp.bits.data := 0.U - // busy when ROB is not empty OR fence/barrier is active - io.rs_rocc_o.busy := !rob.io.empty || fenceActive || barrierWaitROB || barrierWaitRelease -} diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalScheduler.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalScheduler.scala new file mode 100644 index 00000000..427edde9 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalScheduler.scala @@ -0,0 +1,194 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.decoder.GISA._ +import framework.frontend.scoreboard.BankAccessInfo +import framework.core.bbtile.RoCCResponseBB +import framework.balldomain.blink.SubRobRow + +class GlobalRobEntry(val b: GlobalConfig) extends Bundle { + val cmd = new PostGDCmd(b) + val renamedBankAccess = new BankAccessInfo(b.frontend.bank_id_len) + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) +} + +class GlobalSchedIssue(b: GlobalConfig) extends GlobalRobEntry(b) { + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) +} + +class GlobalSchedComplete(b: GlobalConfig) extends Bundle { + val rob_id = UInt(log2Up(b.frontend.rob_entries).W) + val is_sub = Bool() + val sub_rob_id = UInt(log2Up(b.frontend.sub_rob_depth * 4).W) +} + +@instantiable +class GlobalScheduler(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val decode_cmd_i = Flipped(new DecoupledIO(new PostGDCmd(b))) + val ball_issue_o = Decoupled(new GlobalSchedIssue(b)) + val mem_issue_o = Decoupled(new GlobalSchedIssue(b)) + val gp_issue_o = Decoupled(new GlobalSchedIssue(b)) + val ball_complete_i = Flipped(Decoupled(new GlobalSchedComplete(b))) + val mem_complete_i = Flipped(Decoupled(new GlobalSchedComplete(b))) + val gp_complete_i = Flipped(Decoupled(new GlobalSchedComplete(b))) + val ball_subrob_req_i = Flipped(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) + + val scheduler_rocc_o = new Bundle { + val resp = new DecoupledIO(new RoCCResponseBB(b.core.xLen)) + val busy = Output(Bool()) + } + + val barrier_arrive = Output(Bool()) + val barrier_release = Input(Bool()) + }) + + val rob: Instance[GlobalROB] = Instantiate(new GlobalROB(b)) + val subRob: Instance[SubROB] = Instantiate(new SubROB(b)) + + val isFenceCmd = io.decode_cmd_i.valid && io.decode_cmd_i.bits.isFence + val fenceActive = RegInit(false.B) + when(isFenceCmd && !fenceActive) { + fenceActive := true.B + } + when(fenceActive && rob.io.empty) { + fenceActive := false.B + } + + val isBarrierCmd = io.decode_cmd_i.valid && io.decode_cmd_i.bits.isBarrier + val barrierWaitROB = RegInit(false.B) + val barrierWaitRelease = RegInit(false.B) + when(isBarrierCmd && !barrierWaitROB && !barrierWaitRelease && !fenceActive) { + barrierWaitROB := true.B + } + when(barrierWaitROB && rob.io.empty) { + barrierWaitROB := false.B + barrierWaitRelease := true.B + } + when(barrierWaitRelease && io.barrier_release) { + barrierWaitRelease := false.B + } + io.barrier_arrive := barrierWaitRelease + + val isFrontendCmd = io.decode_cmd_i.bits.isFence || io.decode_cmd_i.bits.isBarrier + val anyStall = fenceActive || barrierWaitROB || barrierWaitRelease + rob.io.alloc.valid := io.decode_cmd_i.valid && !isFrontendCmd && !anyStall + rob.io.alloc.bits := io.decode_cmd_i.bits + io.decode_cmd_i.ready := Mux( + isFrontendCmd, + !anyStall, + rob.io.alloc.ready && !anyStall + ) + + val subRobWriteArb = Module(new Arbiter(new SubRobRow(b), b.ballDomain.ballNum)) + for (i <- 0 until b.ballDomain.ballNum) { + subRobWriteArb.io.in(i) <> io.ball_subrob_req_i(i) + } + subRob.io.write <> subRobWriteArb.io.out + + val is_ball_domain = rob.io.issue.bits.cmd.domain_id === DomainId.BALL + val is_mem_domain = rob.io.issue.bits.cmd.domain_id === DomainId.MEM + val is_gp_domain = rob.io.issue.bits.cmd.domain_id === DomainId.GP + + val subRobIssueValid = subRob.io.issue.valid + val subRobCmd = subRob.io.issue.bits + + val subRobIssueEntry = Wire(new GlobalSchedIssue(b)) + subRobIssueEntry.cmd := subRobCmd + subRobIssueEntry.renamedBankAccess := 0.U.asTypeOf(subRobIssueEntry.renamedBankAccess) + subRobIssueEntry.rob_id := subRob.io.issueMasterRobId + subRobIssueEntry.is_sub := true.B + subRobIssueEntry.sub_rob_id := subRob.io.issueSubId + + val subRobIssBall = subRobCmd.domain_id === DomainId.BALL + val subRobIssMem = subRobCmd.domain_id === DomainId.MEM + val subRobIssGp = subRobCmd.domain_id === DomainId.GP + + val mainIssueEntry = Wire(new GlobalSchedIssue(b)) + mainIssueEntry.cmd := rob.io.issue.bits.cmd + mainIssueEntry.renamedBankAccess := rob.io.issue.bits.renamedBankAccess + mainIssueEntry.rob_id := rob.io.issue.bits.rob_id + mainIssueEntry.is_sub := false.B + mainIssueEntry.sub_rob_id := 0.U + + io.ball_issue_o.valid := Mux( + subRobIssueValid && subRobIssBall, + true.B, + rob.io.issue.valid && is_ball_domain && !subRobIssueValid + ) + io.ball_issue_o.bits := Mux(subRobIssueValid && subRobIssBall, subRobIssueEntry, mainIssueEntry) + + io.mem_issue_o.valid := Mux( + subRobIssueValid && subRobIssMem, + true.B, + rob.io.issue.valid && is_mem_domain && !subRobIssueValid + ) + io.mem_issue_o.bits := Mux(subRobIssueValid && subRobIssMem, subRobIssueEntry, mainIssueEntry) + + io.gp_issue_o.valid := Mux( + subRobIssueValid && subRobIssGp, + true.B, + rob.io.issue.valid && is_gp_domain && !subRobIssueValid + ) + io.gp_issue_o.bits := Mux(subRobIssueValid && subRobIssGp, subRobIssueEntry, mainIssueEntry) + + subRob.io.issue.ready := + (subRobIssBall && io.ball_issue_o.ready) || + (subRobIssMem && io.mem_issue_o.ready) || + (subRobIssGp && io.gp_issue_o.ready) + + rob.io.issue.ready := !subRobIssueValid && ( + (is_ball_domain && io.ball_issue_o.ready) || + (is_mem_domain && io.mem_issue_o.ready) || + (is_gp_domain && io.gp_issue_o.ready) + ) + rob.io.subRobActive := subRobIssueValid + + val completeArb = Module(new Arbiter(new GlobalSchedComplete(b), 3)) + completeArb.io.in(0).valid := io.ball_complete_i.valid + completeArb.io.in(0).bits := io.ball_complete_i.bits + io.ball_complete_i.ready := completeArb.io.in(0).ready + completeArb.io.in(1).valid := io.mem_complete_i.valid + completeArb.io.in(1).bits := io.mem_complete_i.bits + io.mem_complete_i.ready := completeArb.io.in(1).ready + completeArb.io.in(2).valid := io.gp_complete_i.valid + completeArb.io.in(2).bits := io.gp_complete_i.bits + io.gp_complete_i.ready := completeArb.io.in(2).ready + + val completeBits = completeArb.io.out.bits + subRob.io.subComplete.valid := completeArb.io.out.valid && completeBits.is_sub + subRob.io.subComplete.bits := completeBits.sub_rob_id + subRob.io.masterComplete.ready := true.B + + val normalComplete = completeArb.io.out.valid && !completeBits.is_sub + if (b.frontend.rs_out_of_order_response) { + rob.io.complete.valid := normalComplete || subRob.io.masterComplete.valid + rob.io.complete.bits := Mux(subRob.io.masterComplete.valid, subRob.io.masterComplete.bits, completeBits.rob_id) + } else { + val isHeadComplete = Mux( + subRob.io.masterComplete.valid, + subRob.io.masterComplete.bits === rob.io.head_ptr, + completeBits.rob_id === rob.io.head_ptr + ) + rob.io.complete.valid := (normalComplete || subRob.io.masterComplete.valid) && isHeadComplete + rob.io.complete.bits := Mux(subRob.io.masterComplete.valid, subRob.io.masterComplete.bits, completeBits.rob_id) + } + completeArb.io.out.ready := Mux( + completeBits.is_sub, + subRob.io.subComplete.ready, + rob.io.complete.ready + ) + + io.scheduler_rocc_o.resp.valid := false.B + io.scheduler_rocc_o.resp.bits.rd := 0.U + io.scheduler_rocc_o.resp.bits.data := 0.U + io.scheduler_rocc_o.busy := !rob.io.empty || fenceActive || barrierWaitROB || barrierWaitRelease +} diff --git a/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala b/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala index 1af3e7cf..13eb888b 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/SubROB.scala @@ -53,6 +53,9 @@ class SubROB(val b: GlobalConfig) extends Module { io.write.ready := !isFull && ballMatch when(io.write.fire) { + when(occupied) { + assert(io.write.bits.master_rob_id === masterRobId, "SubROB row master_rob_id mismatch") + } sram.write(writePtr, io.write.bits) writePtr := nextPtr(writePtr) rowCount := rowCount + 1.U @@ -108,7 +111,13 @@ class SubROB(val b: GlobalConfig) extends Module { io.subComplete.ready := true.B when(io.subComplete.fire) { val subId = io.subComplete.bits + val subRow = subId / 4.U val slotIdx = subId(1, 0) + assert( + state === sReadResp || state === sWaitSlots || state === sWaitMaster, + "SubROB subComplete arrived in invalid state" + ) + assert(subRow === readPtrReg, "SubROB subComplete points to non-active row") slotDone(slotIdx) := true.B } diff --git a/arch/src/main/scala/framework/frontend/scoreboard/BankAliasTable.scala b/arch/src/main/scala/framework/frontend/scoreboard/BankAliasTable.scala new file mode 100644 index 00000000..8c6dd1a3 --- /dev/null +++ b/arch/src/main/scala/framework/frontend/scoreboard/BankAliasTable.scala @@ -0,0 +1,128 @@ +package framework.frontend.scoreboard + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} + +/** + * BAT (Bank Alias Table) + * + * Rename virtual bank IDs into the high-ID alias namespace for scoreboard. + * Lifetime policy: per ROB entry. + * + * ID partition: + * [0, vbankUpper] : virtual/architected bank IDs + * [vbankUpper + 1, maxBankId] : renamed alias IDs (one alias per ROB entry) + */ +@instantiable +class BankAliasTable(val bankIdLen: Int, val vbankUpper: Int, val robEntries: Int) extends Module { + private val aliasIdLen = bankIdLen + private val robIdLen = log2Up(robEntries) + private val vbankNum = vbankUpper + 1 + private val vbankIdLen = log2Up(vbankNum) + private val maxBankId = (1 << bankIdLen) - 1 + private val aliasBase = vbankNum + + @public + val io = IO(new Bundle { + + val alloc = Input(new Bundle { + val valid = Bool() + val rob_id = UInt(robIdLen.W) + val raw = new BankAccessInfo(aliasIdLen) + }) + + val alloc_renamed = Output(new BankAccessInfo(aliasIdLen)) + + val free = Input(new Bundle { + val valid = Bool() + val mask = Vec(robEntries, Bool()) + }) + + }) + + // Current architectural alias for each virtual bank. + val v2a = RegInit(VecInit((0 until vbankNum).map(_.U(aliasIdLen.W)))) + + // Extra aliases [aliasBase, aliasBase + robEntries - 1] are one-per-ROB. + val aliasInUse = RegInit(VecInit(Seq.fill(robEntries)(false.B))) + + // Per-entry metadata for commit-time free. + val entHasWrite = RegInit(VecInit(Seq.fill(robEntries)(false.B))) + val entOldAlias = RegInit(VecInit(Seq.fill(robEntries)(0.U(aliasIdLen.W)))) + val entNewAlias = RegInit(VecInit(Seq.fill(robEntries)(0.U(aliasIdLen.W)))) + val entWrVbank = RegInit(VecInit(Seq.fill(robEntries)(0.U(vbankIdLen.W)))) + + require(vbankUpper >= 0, s"BAT vbankUpper must be non-negative, got $vbankUpper") + require(vbankUpper < maxBankId, s"BAT vbankUpper must be < maxBankId($maxBankId), got $vbankUpper") + require( + aliasBase + robEntries - 1 <= maxBankId, + s"BAT alias range exceeds bank_id_len space: base=$aliasBase entries=$robEntries max=$maxBankId" + ) + + private def extraAlias(robId: UInt): UInt = aliasBase.U(aliasIdLen.W) + robId + private def toVbankIdx(v: UInt): UInt = v(vbankIdLen - 1, 0) + + private def mapVbank(v: UInt): UInt = { + val idx = toVbankIdx(v) + val out = WireDefault(0.U(aliasIdLen.W)) + for (i <- 0 until vbankNum) { + when(idx === i.U(vbankIdLen.W)) { + out := v2a(i) + } + } + out + } + + val q = io.alloc.raw + io.alloc_renamed.rd_bank_0_valid := q.rd_bank_0_valid + io.alloc_renamed.rd_bank_1_valid := q.rd_bank_1_valid + io.alloc_renamed.wr_bank_valid := q.wr_bank_valid + io.alloc_renamed.rd_bank_0_id := Mux(q.rd_bank_0_valid, mapVbank(q.rd_bank_0_id), 0.U) + io.alloc_renamed.rd_bank_1_id := Mux(q.rd_bank_1_valid, mapVbank(q.rd_bank_1_id), 0.U) + io.alloc_renamed.wr_bank_id := Mux(q.wr_bank_valid, extraAlias(io.alloc.rob_id), 0.U) + + when(io.alloc.valid) { + val rid = io.alloc.rob_id + when(q.rd_bank_0_valid) { + assert(q.rd_bank_0_id <= vbankUpper.U, "BAT rd_bank_0_id exceeds virtual bank upper bound") + } + when(q.rd_bank_1_valid) { + assert(q.rd_bank_1_id <= vbankUpper.U, "BAT rd_bank_1_id exceeds virtual bank upper bound") + } + when(q.wr_bank_valid) { + assert(q.wr_bank_id <= vbankUpper.U, "BAT wr_bank_id exceeds virtual bank upper bound") + } + + entHasWrite(rid) := q.wr_bank_valid + entOldAlias(rid) := Mux(q.wr_bank_valid, mapVbank(q.wr_bank_id), 0.U) + entNewAlias(rid) := Mux(q.wr_bank_valid, extraAlias(rid), 0.U) + entWrVbank(rid) := toVbankIdx(q.wr_bank_id) + + when(q.wr_bank_valid) { + assert(!aliasInUse(rid), "BAT alias reused before free") + aliasInUse(rid) := true.B + v2a(toVbankIdx(q.wr_bank_id)) := extraAlias(rid) + } + } + + when(io.free.valid) { + for (i <- 0 until robEntries) { + when(io.free.mask(i)) { + when(entHasWrite(i)) { + assert(aliasInUse(i), "BAT free on non-allocated alias") + aliasInUse(i) := false.B + + // Restore old alias only if mapping still points to this entry's alias. + when(v2a(entWrVbank(i)) === entNewAlias(i)) { + v2a(entWrVbank(i)) := entOldAlias(i) + } + } + entHasWrite(i) := false.B + entOldAlias(i) := 0.U + entNewAlias(i) := 0.U + entWrVbank(i) := 0.U + } + } + } +} diff --git a/arch/src/main/scala/framework/gpdomain/GPDomain.scala b/arch/src/main/scala/framework/gpdomain/GPDomain.scala index bdc9f6ea..0cd62dfa 100644 --- a/arch/src/main/scala/framework/gpdomain/GPDomain.scala +++ b/arch/src/main/scala/framework/gpdomain/GPDomain.scala @@ -2,7 +2,7 @@ package framework.gpdomain import chisel3._ import chisel3.util._ -import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig @@ -11,8 +11,8 @@ class GpDomain(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) - val global_complete_o = Decoupled(new GlobalRsComplete(b)) + val global_issue_i = Flipped(Decoupled(new GlobalSchedIssue(b))) + val global_complete_o = Decoupled(new GlobalSchedComplete(b)) // Status signal val busy = Output(Bool()) }) diff --git a/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala b/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala index c7560fb1..b1c6c1c8 100644 --- a/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala +++ b/arch/src/main/scala/framework/gpdomain/sequencer/Sequencer.scala @@ -9,7 +9,7 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import chisel3.util._ import chisel3.util.experimental.decode.DecodeBundle import framework.top.GlobalConfig -import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} import framework.gpdomain.sequencer.decoder.{Decoder, DomainDecoder} /** @@ -39,8 +39,8 @@ class Sequencer(val b: GlobalConfig) extends Module { @public val io = IO(new Bundle { // Interface with global RS - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) - val global_complete_o = Decoupled(new GlobalRsComplete(b)) + val global_issue_i = Flipped(Decoupled(new GlobalSchedIssue(b))) + val global_complete_o = Decoupled(new GlobalSchedComplete(b)) // TODO: Interface with lanes (placeholder) // val laneRequest = Vec(laneNumber, Decoupled(new LaneRequest(...))) diff --git a/arch/src/main/scala/framework/memdomain/MemDomain.scala b/arch/src/main/scala/framework/memdomain/MemDomain.scala index 86bab3a0..56cf7eb4 100644 --- a/arch/src/main/scala/framework/memdomain/MemDomain.scala +++ b/arch/src/main/scala/framework/memdomain/MemDomain.scala @@ -6,7 +6,7 @@ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantia import freechips.rocketchip.tile._ import framework.balldomain.blink.{BankRead, BankWrite} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} -import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} import framework.top.GlobalConfig import framework.memdomain.backend.MemRequestIO import framework.memdomain.frontend.MemFrontend @@ -25,8 +25,8 @@ class MemDomain(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { // ------------------------------------------------- // Command Channel // ------------------------------------------------- - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) - val global_complete_o = Decoupled(new GlobalRsComplete(b)) + val global_issue_i = Flipped(Decoupled(new GlobalSchedIssue(b))) + val global_complete_o = Decoupled(new GlobalSchedComplete(b)) val busy = Output(Bool()) // ------------------------------------------------- diff --git a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala index c2813773..ac6ba3c2 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/MemFrontend.scala @@ -7,7 +7,7 @@ import framework.memdomain.frontend.outside_channel.dma.{StreamReader, StreamWri import framework.memdomain.frontend.outside_channel.{MemConfiger, MemConfigerIO, MemLoader, MemStorer} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} -import framework.frontend.globalrs.{GlobalRsComplete, GlobalRsIssue} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} import framework.balldomain.blink.{BankRead, BankWrite} import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import framework.top.GlobalConfig @@ -25,9 +25,9 @@ class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { @public val io = IO(new Bundle { // Issue interface from global RS (single channel) - val global_issue_i = Flipped(Decoupled(new GlobalRsIssue(b))) + val global_issue_i = Flipped(Decoupled(new GlobalSchedIssue(b))) // Report completion to global RS (single channel) - val global_complete_o = Decoupled(new GlobalRsComplete(b)) + val global_complete_o = Decoupled(new GlobalSchedComplete(b)) // Bank read/write interface - used by load/store val interdma = new Bundle { diff --git a/bbdev b/bbdev index d7c8a24f..84b95e39 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit d7c8a24fda92a1aa152157e4ad7445fae91a335f +Subproject commit 84b95e39e8da29dcb56845c37dad96bf796d7da9 From d39bea7d0feb0ac93d91e7af9487b165c8a01c56 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 20 Mar 2026 21:31:18 +0800 Subject: [PATCH 182/238] [arch] feat: add NDJSON visualization script and enhance tracing with clock cycle support --- arch/scripts/bdb_ndjson_annotate.py | 78 +++++++ arch/scripts/bdb_ndjson_viz.py | 201 ++++++++++++++++++ arch/src/csrc/include/bdb.h | 4 + arch/src/csrc/include/monitor/trace.h | 4 + arch/src/csrc/include/monitor/trace_cfg.h | 1 + arch/src/csrc/src/main.cc | 10 +- arch/src/csrc/src/monitor/monitor.cc | 49 ++++- arch/src/csrc/src/monitor/trace/bdb_clk.cc | 9 + arch/src/csrc/src/monitor/trace/ctrace.cc | 23 +- arch/src/csrc/src/monitor/trace/itrace.cc | 20 +- arch/src/csrc/src/monitor/trace/mtrace.cc | 18 +- arch/src/csrc/src/monitor/trace/pmctrace.cc | 17 +- .../scala/sims/verilator/BBSimHarness.scala | 4 + .../main/scala/sims/verilator/BdbClkDPI.scala | 38 ++++ bb-tests/sardine/tests/test_ctest.py | 7 +- .../workloads/src/CTest/toy/CMakeLists.txt | 4 +- .../src/CTest/toy/vecunit_matmul_random3.c | 74 ------- .../src/CTest/toy/vecunit_tiled_matmul.c | 96 +++++++++ bbdev | 2 +- scripts/nix/build-env-python.nix | 1 + 20 files changed, 533 insertions(+), 127 deletions(-) create mode 100644 arch/scripts/bdb_ndjson_annotate.py create mode 100644 arch/scripts/bdb_ndjson_viz.py create mode 100644 arch/src/csrc/src/monitor/trace/bdb_clk.cc create mode 100644 arch/src/main/scala/sims/verilator/BdbClkDPI.scala delete mode 100644 bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c create mode 100644 bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c diff --git a/arch/scripts/bdb_ndjson_annotate.py b/arch/scripts/bdb_ndjson_annotate.py new file mode 100644 index 00000000..eeaa1df4 --- /dev/null +++ b/arch/scripts/bdb_ndjson_annotate.py @@ -0,0 +1,78 @@ +#!/usr/bin/env python3 +""" +Lookup instruction name by funct id. + +Example: + python3 arch/scripts/bdb_ndjson_annotate.py 0x20 +""" + +from __future__ import annotations + +import argparse +import re +from pathlib import Path +from typing import Any + +FILE_RE = re.compile(r"^(\d+)_([a-z0-9_]+)\.c$") + + +def parse_funct_id(v: Any) -> int: + try: + if isinstance(v, int): + return v + if isinstance(v, str): + return int(v, 0) + except ValueError as e: + raise SystemExit(f"invalid funct id: {v!r}") from e + raise SystemExit(f"invalid funct id type: {type(v)}") + + +def build_funct_map(isa_dir: Path) -> dict[int, str]: + if not isa_dir.is_dir(): + raise SystemExit(f"ISA dir not found: {isa_dir}") + mp: dict[int, str] = {} + for p in isa_dir.glob("*.c"): + m = FILE_RE.match(p.name) + if not m: + continue + fid = int(m.group(1)) + name = m.group(2) + mp[fid] = name + if not mp: + raise SystemExit(f"no ISA funct mapping found under: {isa_dir}") + return mp + + +def resolve_funct_name(fid: int, funct_map: dict[int, str]) -> str: + if fid not in funct_map: + raise SystemExit(f"unknown funct id: 0x{fid:x}") + return funct_map[fid] + + +def default_isa_dir() -> Path: + return ( + Path(__file__).resolve().parents[2] + / "bb-tests" + / "workloads" + / "lib" + / "bbhw" + / "isa" + ) + + +def main() -> None: + p = argparse.ArgumentParser(description="Lookup instruction name by funct id") + p.add_argument("funct_id", help="funct id, e.g. 0x20 or 32") + p.add_argument( + "--isa-dir", type=Path, default=default_isa_dir(), help="ISA macro dir" + ) + args = p.parse_args() + + fid = parse_funct_id(args.funct_id) + fmap = build_funct_map(args.isa_dir) + name = resolve_funct_name(fid, fmap) + print(name) + + +if __name__ == "__main__": + main() diff --git a/arch/scripts/bdb_ndjson_viz.py b/arch/scripts/bdb_ndjson_viz.py new file mode 100644 index 00000000..b58c39ce --- /dev/null +++ b/arch/scripts/bdb_ndjson_viz.py @@ -0,0 +1,201 @@ +#!/usr/bin/env python3 +""" +Parse BDB NDJSON trace and draw a single RoB-state figure. + +Only itrace issue->complete intervals are plotted. +Idle gaps (no RoB active) are not shown. + +Requires: matplotlib (pip install matplotlib) +""" + +from __future__ import annotations + +import argparse +import json +from pathlib import Path +from typing import Any + +from bdb_ndjson_annotate import build_funct_map, default_isa_dir, parse_funct_id + + +def load_records(path: Path) -> list[dict[str, Any]]: + rows: list[dict[str, Any]] = [] + with path.open(encoding="utf-8", errors="replace") as f: + for i, line in enumerate(f, 1): + line = line.strip() + if not line: + continue + try: + rows.append(json.loads(line)) + except json.JSONDecodeError as e: + raise SystemExit(f"{path}:{i}: invalid JSON: {e}") from e + return rows + + +def clk_of(rec: dict[str, Any], fallback: int | None) -> int | None: + if "clk" in rec: + return int(rec["clk"]) + return fallback + + +def build_rob_intervals( + records: list[dict[str, Any]], +) -> tuple[list[tuple[int, int, int, int, str]], bool]: + """ + Build RoB active windows from itrace issue/complete pairs. + Returns (t0, t1, domain_id, rob_id), used_real_clk. + """ + fmap = build_funct_map(default_isa_dir()) + open_by_key: dict[tuple[int, int], tuple[int, str]] = {} + out: list[tuple[int, int, int, int, str]] = [] + used_clk = False + seq = 0 + + for rec in records: + if rec.get("type") != "itrace": + seq += 1 + continue + + ev = str(rec.get("event", "")) + dom = int(rec.get("domain_id", 0)) + rid = int(rec.get("rob_id", -1)) + if rid < 0: + seq += 1 + continue + t = clk_of(rec, seq) + if t is None: + t = seq + else: + used_clk = True + + key = (dom, rid) + funct_lbl = "" + if "funct" in rec: + try: + fid = parse_funct_id(rec["funct"]) + funct_lbl = fmap.get(fid, f"0x{fid:x}") + except SystemExit: + funct_lbl = str(rec["funct"]) + + if ev == "issue": + open_by_key[key] = (int(t), funct_lbl) + elif ev == "complete" and key in open_by_key: + t0, flbl = open_by_key.pop(key) + t1 = int(t) + if t1 < t0: + t0, t1 = t1, t0 + if t1 == t0: + t1 += 1 + out.append((t0, t1, dom, rid, flbl)) + seq += 1 + + return out, used_clk + + +def plot_timeline( + records: list[dict[str, Any]], + path: Path, + out_path: Path | None, + show: bool, +) -> None: + try: + import matplotlib.pyplot as plt + except ImportError as e: + raise SystemExit("matplotlib is required: pip install matplotlib") from e + + if not records: + raise SystemExit("empty trace") + + rob_itv, used_clk = build_rob_intervals(records) + if not rob_itv: + raise SystemExit("no itrace issue/complete pairs found") + g0 = min(t0 for t0, _, _, _, _ in rob_itv) + g1 = max(t1 for _, t1, _, _, _ in rob_itv) + if g1 <= g0: + g1 = g0 + 1 + + fig, ax = plt.subplots(1, 1, figsize=(14, 6)) + rows = sorted({(dom, rid) for _, _, dom, rid, _ in rob_itv}) + y_of = {k: i for i, k in enumerate(rows)} + + for t0, t1, dom, rid, flbl in rob_itv: + y = y_of[(dom, rid)] + ax.vlines( + t0, + ymin=-0.5, + ymax=y, + colors="0.45", + linestyles="-", + linewidth=0.6, + alpha=0.6, + ) + ax.barh( + y, + width=t1 - t0, + left=t0, + height=0.65, + color=f"C{dom % 10}", + alpha=0.9, + edgecolor="black", + linewidth=0.3, + ) + if (t1 - t0) > 10 and flbl: + ax.text( + (t0 + t1) * 0.5, + y, + flbl, + ha="center", + va="center", + fontsize=7, + color="white", + ) + + ax.set_xlim(g0, g1) + ax.set_yticks(range(len(rows))) + ax.set_yticklabels([f"d{dom}:r{rid}" for dom, rid in rows], fontsize=8) + ax.set_xlabel("clk" if used_clk else "record order") + ax.set_ylabel("RoB entry (active only)") + title_clk = "harness clk" if used_clk else "fallback order index" + ax.set_title(f"RoB active timeline — {path.name} ({title_clk})") + + plt.tight_layout() + if out_path: + out_path.parent.mkdir(parents=True, exist_ok=True) + fig.savefig(out_path, dpi=150, bbox_inches="tight") + if show: + plt.show() + else: + plt.close(fig) + + +def main() -> None: + p = argparse.ArgumentParser(description="Parse and visualize BDB NDJSON trace") + p.add_argument("ndjson", type=Path, help="Path to bdb.ndjson") + p.add_argument( + "-o", + "--output", + type=Path, + default=None, + help="Output PNG path (default: .timeline.png if not --show-only)", + ) + p.add_argument( + "--show", + action="store_true", + help="Open interactive window (requires display)", + ) + args = p.parse_args() + + if not args.ndjson.is_file(): + raise SystemExit(f"not a file: {args.ndjson}") + + records = load_records(args.ndjson) + + out = args.output + if out is None and not args.show: + out = args.ndjson.with_suffix(".timeline.png") + + plot_timeline(records, args.ndjson, out, args.show) + + +if __name__ == "__main__": + main() diff --git a/arch/src/csrc/include/bdb.h b/arch/src/csrc/include/bdb.h index 5ba2d7f3..3b688b02 100644 --- a/arch/src/csrc/include/bdb.h +++ b/arch/src/csrc/include/bdb.h @@ -26,6 +26,10 @@ extern const char *stdout_path; // Raw stdout fd saved before dup2 — UART writes here for real-time display extern int raw_stdout_fd; +// If set (bbdev sim), NDJSON banner goes here; stdout may be piped to +// spike-dasm. +const char *bdb_sim_meta_path(void); + void init_monitor(int argc, char *argv[]); void bdb_mainloop(); void ball_exec_once(); diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index 9ce95c4d..9f47f5f6 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -7,6 +7,10 @@ extern "C" { #endif +// Harness clock cycle index (BBSimHarness posedge); must run before other trace +// DPI in same eval. +void dpi_bdb_set_clk(unsigned long long c); + // DPI-C function for instruction trace (itrace) // Called from GlobalROB when instructions are issued or completed void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete diff --git a/arch/src/csrc/include/monitor/trace_cfg.h b/arch/src/csrc/include/monitor/trace_cfg.h index 2837ff04..6625e453 100644 --- a/arch/src/csrc/include/monitor/trace_cfg.h +++ b/arch/src/csrc/include/monitor/trace_cfg.h @@ -14,6 +14,7 @@ enum { }; extern uint32_t bdb_trace_mask; +extern uint64_t bdb_rtl_clk; static inline int bdb_trace_on(uint32_t bit) { return (bdb_trace_mask & bit) != 0; diff --git a/arch/src/csrc/src/main.cc b/arch/src/csrc/src/main.cc index 830afd51..49c3fae1 100644 --- a/arch/src/csrc/src/main.cc +++ b/arch/src/csrc/src/main.cc @@ -45,7 +45,9 @@ void sim_init(int argc, char **argv) { top->trace(tfp, 0); tfp->open(fst_path); - Log("The waveform will be saved to the FST file: %s", fst_path); + if (bdb_sim_meta_path() == nullptr) { + Log("The waveform will be saved to the FST file: %s", fst_path); + } top->reset = 1; top->clock = 0; @@ -68,7 +70,9 @@ void sim_exit() { contextp->timeInc(1); tfp->dump(contextp->time()); tfp->close(); - printf("The wave data has been saved to the FST file: %s\n", fst_path); + if (bdb_sim_meta_path() == nullptr) { + printf("The wave data has been saved to the FST file: %s\n", fst_path); + } exit(0); } @@ -76,7 +80,7 @@ void ball_exec_once() { // posedge: clock=1, eval (FF outputs settle), read fire pulse from RTL slave top->clock = 1; top->eval(); - mmio_tick(); // read io_mmio_fire; all AXI4 handshaking done in RTL + mmio_tick(); // read io_mmio_fire; all AXI4 handshaking done in RTL contextp->timeInc(1); tfp->dump(contextp->time()); sim_time++; diff --git a/arch/src/csrc/src/monitor/monitor.cc b/arch/src/csrc/src/monitor/monitor.cc index b10219df..cd3bc981 100644 --- a/arch/src/csrc/src/monitor/monitor.cc +++ b/arch/src/csrc/src/monitor/monitor.cc @@ -19,6 +19,14 @@ uint32_t bdb_trace_mask = BDB_TR_ALL; // display. int raw_stdout_fd = -1; +const char *bdb_sim_meta_path(void) { + const char *m = getenv("BDB_SIM_META"); + if (m != nullptr && m[0] != '\0') { + return m; + } + return nullptr; +} + static int parse_args(int argc, char *argv[]) { auto parse_trace_list = [](const char *list) { if (list == nullptr || *list == '\0') { @@ -100,16 +108,37 @@ static void init_log(const char *log_file) { Assert(fp, "Can not open '%s'", log_file); fclose(fp); // truncate/create file; trace writers append NDJSON later } + const char *meta = bdb_sim_meta_path(); if (log_file) { - fprintf(stderr, "NDJSON trace is written to %s\n", log_file); - fprintf(stderr, - "Trace mask=0x%X [itrace=%d mtrace=%d pmctrace=%d ctrace=%d " - "banktrace=%d]\n", - bdb_trace_mask, bdb_trace_on(BDB_TR_ITRACE), - bdb_trace_on(BDB_TR_MTRACE), bdb_trace_on(BDB_TR_PMCTRACE), - bdb_trace_on(BDB_TR_CTRACE), bdb_trace_on(BDB_TR_BANKTRACE)); + if (meta != nullptr) { + FILE *mf = fopen(meta, "w"); + Assert(mf, "Can not open BDB_SIM_META '%s'", meta); + fprintf(mf, "NDJSON trace is written to %s\n", log_file); + fprintf(mf, + "Trace mask=0x%X [itrace=%d mtrace=%d pmctrace=%d ctrace=%d " + "banktrace=%d]\n", + bdb_trace_mask, bdb_trace_on(BDB_TR_ITRACE), + bdb_trace_on(BDB_TR_MTRACE), bdb_trace_on(BDB_TR_PMCTRACE), + bdb_trace_on(BDB_TR_CTRACE), bdb_trace_on(BDB_TR_BANKTRACE)); + fclose(mf); + } else { + fprintf(stderr, "NDJSON trace is written to %s\n", log_file); + fprintf(stderr, + "Trace mask=0x%X [itrace=%d mtrace=%d pmctrace=%d ctrace=%d " + "banktrace=%d]\n", + bdb_trace_mask, bdb_trace_on(BDB_TR_ITRACE), + bdb_trace_on(BDB_TR_MTRACE), bdb_trace_on(BDB_TR_PMCTRACE), + bdb_trace_on(BDB_TR_CTRACE), bdb_trace_on(BDB_TR_BANKTRACE)); + } } else { - fprintf(stderr, "NDJSON trace path is not set\n"); + if (meta != nullptr) { + FILE *mf = fopen(meta, "w"); + Assert(mf, "Can not open BDB_SIM_META '%s'", meta); + fprintf(mf, "NDJSON trace path is not set\n"); + fclose(mf); + } else { + fprintf(stderr, "NDJSON trace path is not set\n"); + } } } @@ -129,5 +158,7 @@ void init_monitor(int argc, char *argv[]) { parse_args(argc, argv); init_log(log_path); init_io(); - welcome(); + if (bdb_sim_meta_path() == nullptr) { + welcome(); + } } diff --git a/arch/src/csrc/src/monitor/trace/bdb_clk.cc b/arch/src/csrc/src/monitor/trace/bdb_clk.cc new file mode 100644 index 00000000..b11a72f7 --- /dev/null +++ b/arch/src/csrc/src/monitor/trace/bdb_clk.cc @@ -0,0 +1,9 @@ +#include "monitor/trace_cfg.h" + +// Harness reference clock cycle index (updated from RTL via dpi_bdb_set_clk +// each posedge). +uint64_t bdb_rtl_clk = 0; + +extern "C" void dpi_bdb_set_clk(unsigned long long c) { + bdb_rtl_clk = (uint64_t)c; +} diff --git a/arch/src/csrc/src/monitor/trace/ctrace.cc b/arch/src/csrc/src/monitor/trace/ctrace.cc index 5b14ca5b..039411c8 100644 --- a/arch/src/csrc/src/monitor/trace/ctrace.cc +++ b/arch/src/csrc/src/monitor/trace/ctrace.cc @@ -67,21 +67,24 @@ extern "C" void dpi_ctrace(unsigned char subcmd, unsigned int ctr_id, switch (subcmd) { case 0: // CTR_START fprintf(ctrace_fp, - "{\"type\":\"ctrace\",\"event\":\"ctr_start\",\"ctr_id\":%u," + "{\"type\":\"ctrace\",\"clk\":%llu,\"event\":\"ctr_start\",\"ctr_" + "id\":%u," "\"tag\":\"0x%llX\",\"cycle\":%llu}\n", - ctr_id, tag, cycle); + (unsigned long long)bdb_rtl_clk, ctr_id, tag, cycle); break; case 1: // CTR_STOP fprintf(ctrace_fp, - "{\"type\":\"ctrace\",\"event\":\"ctr_stop\",\"ctr_id\":%u," + "{\"type\":\"ctrace\",\"clk\":%llu,\"event\":\"ctr_stop\",\"ctr_" + "id\":%u," "\"tag\":\"0x%llX\",\"elapsed\":%llu,\"cycle\":%llu}\n", - ctr_id, tag, elapsed, cycle); + (unsigned long long)bdb_rtl_clk, ctr_id, tag, elapsed, cycle); break; case 2: // CTR_READ fprintf(ctrace_fp, - "{\"type\":\"ctrace\",\"event\":\"ctr_read\",\"ctr_id\":%u," + "{\"type\":\"ctrace\",\"clk\":%llu,\"event\":\"ctr_read\",\"ctr_" + "id\":%u," "\"current\":%llu,\"cycle\":%llu}\n", - ctr_id, elapsed, cycle); + (unsigned long long)bdb_rtl_clk, ctr_id, elapsed, cycle); break; } fflush(ctrace_fp); @@ -133,9 +136,9 @@ extern "C" void dpi_backdoor_put_read_data(unsigned int bank_id, char data_hex[35]; u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); fprintf(ctrace_fp, - "{\"type\":\"banktrace\",\"event\":\"backdoor_read\"," + "{\"type\":\"banktrace\",\"clk\":%llu,\"event\":\"backdoor_read\"," "\"bank_id\":%u,\"row\":%u,\"data\":\"%s\"}\n", - bank_id, row, data_hex); + (unsigned long long)bdb_rtl_clk, bank_id, row, data_hex); fflush(ctrace_fp); } } @@ -153,9 +156,9 @@ extern "C" void dpi_backdoor_put_write_done(unsigned int bank_id, char data_hex[35]; u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); fprintf(ctrace_fp, - "{\"type\":\"banktrace\",\"event\":\"backdoor_write\"," + "{\"type\":\"banktrace\",\"clk\":%llu,\"event\":\"backdoor_write\"," "\"bank_id\":%u,\"row\":%u,\"data\":\"%s\"}\n", - bank_id, row, data_hex); + (unsigned long long)bdb_rtl_clk, bank_id, row, data_hex); fflush(ctrace_fp); } } diff --git a/arch/src/csrc/src/monitor/trace/itrace.cc b/arch/src/csrc/src/monitor/trace/itrace.cc index 46fe57a2..f1f647e6 100644 --- a/arch/src/csrc/src/monitor/trace/itrace.cc +++ b/arch/src/csrc/src/monitor/trace/itrace.cc @@ -62,19 +62,21 @@ extern "C" void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete u64_hex(rs1_hex, sizeof(rs1_hex), rs1); u64_hex(rs2_hex, sizeof(rs2_hex), rs2); if (is_issue) { - fprintf(itrace_fp, - "{\"type\":\"itrace\",\"event\":\"issue\",\"rob_id\":%u," - "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," - "\"bank\":\"%s\",\"rs1\":\"%s\",\"rs2\":\"%s\"}\n", - rob_id, domain_id, funct, bank_enable, - bank_enable_str(bank_enable), rs1_hex, rs2_hex); + fprintf( + itrace_fp, + "{\"type\":\"itrace\",\"clk\":%llu,\"event\":\"issue\",\"rob_id\":%u," + "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," + "\"bank\":\"%s\",\"rs1\":\"%s\",\"rs2\":\"%s\"}\n", + (unsigned long long)bdb_rtl_clk, rob_id, domain_id, funct, + bank_enable, bank_enable_str(bank_enable), rs1_hex, rs2_hex); } else { fprintf(itrace_fp, - "{\"type\":\"itrace\",\"event\":\"complete\",\"rob_id\":%u," + "{\"type\":\"itrace\",\"clk\":%llu,\"event\":\"complete\",\"rob_" + "id\":%u," "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," "\"bank\":\"%s\"}\n", - rob_id, domain_id, funct, bank_enable, - bank_enable_str(bank_enable)); + (unsigned long long)bdb_rtl_clk, rob_id, domain_id, funct, + bank_enable, bank_enable_str(bank_enable)); } fflush(itrace_fp); } diff --git a/arch/src/csrc/src/monitor/trace/mtrace.cc b/arch/src/csrc/src/monitor/trace/mtrace.cc index cd6a8169..9e339e1e 100644 --- a/arch/src/csrc/src/monitor/trace/mtrace.cc +++ b/arch/src/csrc/src/monitor/trace/mtrace.cc @@ -44,16 +44,20 @@ extern "C" void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read if (is_write) { u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); fprintf(mtrace_fp, - "{\"type\":\"mtrace\",\"event\":\"write\",\"channel\":%u," + "{\"type\":\"mtrace\",\"clk\":%llu,\"event\":\"write\"," + "\"channel\":%u," "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," "\"group_id\":%u,\"addr\":\"0x%08x\",\"data\":\"%s\"}\n", - channel, hart_id, is_shared, vbank_id, group_id, addr, data_hex); + (unsigned long long)bdb_rtl_clk, channel, hart_id, is_shared, + vbank_id, group_id, addr, data_hex); } else { - fprintf(mtrace_fp, - "{\"type\":\"mtrace\",\"event\":\"read\",\"channel\":%u," - "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," - "\"group_id\":%u,\"addr\":\"0x%08x\"}\n", - channel, hart_id, is_shared, vbank_id, group_id, addr); + fprintf( + mtrace_fp, + "{\"type\":\"mtrace\",\"clk\":%llu,\"event\":\"read\",\"channel\":%u," + "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," + "\"group_id\":%u,\"addr\":\"0x%08x\"}\n", + (unsigned long long)bdb_rtl_clk, channel, hart_id, is_shared, + vbank_id, group_id, addr); } fflush(mtrace_fp); } diff --git a/arch/src/csrc/src/monitor/trace/pmctrace.cc b/arch/src/csrc/src/monitor/trace/pmctrace.cc index daefcb89..62fee501 100644 --- a/arch/src/csrc/src/monitor/trace/pmctrace.cc +++ b/arch/src/csrc/src/monitor/trace/pmctrace.cc @@ -28,10 +28,11 @@ extern "C" void dpi_pmctrace(unsigned int ball_id, unsigned int rob_id, init_pmctrace(); if (pmctrace_fp) { - fprintf(pmctrace_fp, - "{\"type\":\"pmctrace\",\"event\":\"ball\",\"ball_id\":%u," - "\"rob_id\":%u,\"elapsed\":%llu}\n", - ball_id, rob_id, elapsed); + fprintf( + pmctrace_fp, + "{\"type\":\"pmctrace\",\"clk\":%llu,\"event\":\"ball\",\"ball_id\":%u," + "\"rob_id\":%u,\"elapsed\":%llu}\n", + (unsigned long long)bdb_rtl_clk, ball_id, rob_id, elapsed); fflush(pmctrace_fp); } } @@ -48,14 +49,14 @@ extern "C" void dpi_mem_pmctrace(unsigned char is_store, unsigned int rob_id, if (pmctrace_fp) { if (is_store) { fprintf(pmctrace_fp, - "{\"type\":\"pmctrace\",\"event\":\"store\"," + "{\"type\":\"pmctrace\",\"clk\":%llu,\"event\":\"store\"," "\"rob_id\":%u,\"elapsed\":%llu}\n", - rob_id, elapsed); + (unsigned long long)bdb_rtl_clk, rob_id, elapsed); } else { fprintf(pmctrace_fp, - "{\"type\":\"pmctrace\",\"event\":\"load\"," + "{\"type\":\"pmctrace\",\"clk\":%llu,\"event\":\"load\"," "\"rob_id\":%u,\"elapsed\":%llu}\n", - rob_id, elapsed); + (unsigned long long)bdb_rtl_clk, rob_id, elapsed); } fflush(pmctrace_fp); } diff --git a/arch/src/main/scala/sims/verilator/BBSimHarness.scala b/arch/src/main/scala/sims/verilator/BBSimHarness.scala index 7f9404be..dd7a5bde 100644 --- a/arch/src/main/scala/sims/verilator/BBSimHarness.scala +++ b/arch/src/main/scala/sims/verilator/BBSimHarness.scala @@ -127,6 +127,10 @@ class BBSimHarness(implicit val p: Parameters) extends Module with HasHarnessIns io.mmio_fire_addr := 0.U io.mmio_fire_data := 0.U + val bdbClkDpi = Module(new BdbClkDPI) + bdbClkDpi.io.clock := clock + bdbClkDpi.io.reset := reset.asBool + def referenceClockFreqMHz: Double = 1000.0 def referenceClock: Clock = clock def referenceReset: Reset = reset diff --git a/arch/src/main/scala/sims/verilator/BdbClkDPI.scala b/arch/src/main/scala/sims/verilator/BdbClkDPI.scala new file mode 100644 index 00000000..b1fc4aa8 --- /dev/null +++ b/arch/src/main/scala/sims/verilator/BdbClkDPI.scala @@ -0,0 +1,38 @@ +package sims.verilator + +import chisel3._ +import chisel3.util.HasBlackBoxInline + +/** + * Pushes harness reference clock cycle index into C++ via DPI each posedge. + * Matches BBSimHarness.clock (see ball_exec_once: clock=1 half-cycle). + */ +class BdbClkDPI extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val clock = Input(Clock()) + val reset = Input(Bool()) + }) + + setInline( + "BdbClkDPI.v", + """ + |import "DPI-C" function void dpi_bdb_set_clk(input longint unsigned c); + |module BdbClkDPI( + | input wire clock, + | input wire reset + |); + | reg [63:0] cnt; + | always @(posedge clock) begin + | if (reset) begin + | cnt <= 64'd0; + | dpi_bdb_set_clk(64'd0); + | end else begin + | dpi_bdb_set_clk(cnt); + | cnt <= cnt + 64'd1; + | end + | end + |endmodule + """.stripMargin + ) +} diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 2eb1a083..1814b48b 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -75,10 +75,9 @@ "ctest_vecunit_matmul_random2_singlecore-baremetal", "ctest_vecunit_matmul_random2_singlecore-baremetal", ), - ( - "ctest_vecunit_matmul_random3_singlecore-baremetal", - "ctest_vecunit_matmul_random3_singlecore-baremetal", - ), + # ( "ctest_vecunit_tiled_matmul_singlecore-baremetal", + # "ctest_vecunit_tiled_matmul_singlecore-baremetal", + # ), ( "ctest_vecunit_matmul_zero_random_singlecore-baremetal", "ctest_vecunit_matmul_zero_random_singlecore-baremetal", diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index ef6eebc0..fbbf56ba 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -101,7 +101,7 @@ add_cross_platform_test_target(ctest_vecunit_matmul_row_col_vector vecunit_matmu add_cross_platform_test_target(ctest_vecunit_matmul_col_row_vector vecunit_matmul_col_row_vector.c) add_cross_platform_test_target(ctest_vecunit_matmul_random1 vecunit_matmul_random1.c) add_cross_platform_test_target(ctest_vecunit_matmul_random2 vecunit_matmul_random2.c) -add_cross_platform_test_target(ctest_vecunit_matmul_random3 vecunit_matmul_random3.c) +add_cross_platform_test_target(ctest_vecunit_tiled_matmul vecunit_tiled_matmul.c) add_cross_platform_test_target(ctest_vecunit_matmul_zero_random vecunit_matmul_zero_random.c) add_cross_platform_test_target(ctest_vecunit_matmul_16xn_ones vecunit_matmul_16xn_ones.c) add_cross_platform_test_target(ctest_vecunit_matmul_16xn_random1 vecunit_matmul_16xn_random1.c) @@ -144,7 +144,7 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_vecunit_matmul_col_row_vector ctest_vecunit_matmul_random1 ctest_vecunit_matmul_random2 - ctest_vecunit_matmul_random3 + ctest_vecunit_tiled_matmul ctest_vecunit_matmul_zero_random ctest_vecunit_matmul_16xn_ones ctest_vecunit_matmul_16xn_random1 diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c b/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c deleted file mode 100644 index c2bf167c..00000000 --- a/bb-tests/workloads/src/CTest/toy/vecunit_matmul_random3.c +++ /dev/null @@ -1,74 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include - -#define DIM 16 - -static elem_t input_matrix_a[DIM * DIM] __attribute__((aligned(64))); -static elem_t input_matrix_b[DIM * DIM] __attribute__((aligned(64))); -static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); -static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); - -void hw_matmul(const char *test_name, elem_t *a, elem_t *b, result_t *c, - int size) { - // spad0: original A - uint32_t op1_bank_id = 0; - // spad1: operand B - uint32_t op2_bank_id = 1; - // acc0: write to accumulator - int acc_bank_id = 2; // virtual bank id - // spad3: transposed A - uint32_t a_transposed_bank_id = 3; - - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(op2_bank_id, 1, 1); - bb_mem_alloc(acc_bank_id, 1, 4); - bb_mem_alloc(a_transposed_bank_id, 1, 1); - - bb_mvin((uintptr_t)a, op1_bank_id, DIM, 1); - bb_mvin((uintptr_t)b, op2_bank_id, DIM, 1); - bb_transpose(op1_bank_id, a_transposed_bank_id, size, 0); - - bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, size, 0); - bb_mvout((uintptr_t)c, acc_bank_id, size, 1); - bb_fence(); -} - -int run_test(const char *test_name, elem_t *a, elem_t *b, int size) { - cpu_matmul(a, b, expected_matrix, size, size, size); - hw_matmul(test_name, a, b, output_matrix, size); - if (compare_u32_matrices(output_matrix, expected_matrix, size, size)) { - printf("Test %s PASSED\n", test_name); - return 1; - } else { - printf("Test %s FAILED\n", test_name); - return 0; - } -} - -int test_random() { - init_u8_random_matrix(input_matrix_a, DIM, DIM, 333); - init_u8_random_matrix(input_matrix_b, DIM, DIM, 444); - return run_test("Random matrices", input_matrix_a, input_matrix_b, DIM); -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = test_random(); - - if (passed) { - printf("vecunit_matmul_random test PASSED\n"); - return 0; - } else { - printf("vecunit_matmul_random test FAILED\n"); - return 1; - } - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c new file mode 100644 index 00000000..7c93a66f --- /dev/null +++ b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c @@ -0,0 +1,96 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define KDIM 64 +#define KTILE 16 + +_Static_assert(KDIM % KTILE == 0, "KDIM must be divisible by KTILE"); +_Static_assert(KDIM % DIM == 0, "KDIM must be divisible by DIM"); + +static elem_t input_matrix_a[DIM * KDIM] __attribute__((aligned(64))); +static elem_t input_matrix_b[KDIM * DIM] __attribute__((aligned(64))); +static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); +static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); +static result_t zero_matrix[DIM * DIM] __attribute__((aligned(64))) = {0}; + +void hw_matmul_tiled(const char *test_name, elem_t *a, elem_t *b, result_t *c) { + uint32_t op1_bank_id = 0; + uint32_t op2_bank_id = 1; + int acc_bank_id = 2; + uint32_t a_transposed_bank_id = 3; + + bb_mem_alloc(op1_bank_id, 1, 1); + bb_mem_alloc(op2_bank_id, 1, 1); + bb_mem_alloc(acc_bank_id, 1, 4); + bb_mem_alloc(a_transposed_bank_id, 1, 1); + + bb_mvin((uintptr_t)zero_matrix, acc_bank_id, DIM, 1); + + for (int k0 = 0; k0 < KDIM; k0 += KTILE) { + bb_mvin((uintptr_t)(a + k0), op1_bank_id, KTILE, 1); + bb_mvin((uintptr_t)(b + k0 * DIM), op2_bank_id, KTILE, 1); + bb_transpose(op1_bank_id, a_transposed_bank_id, KTILE, 0); + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, KTILE, 0); + } + + bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); + bb_fence(); +} + +void init_diag_ones(elem_t *a, elem_t *b, result_t *expected) { + clear_u8_matrix(a, DIM, KDIM); + clear_u8_matrix(b, KDIM, DIM); + clear_u32_matrix(expected, DIM, DIM); + + // One 1 per k: A[r,k]=1 iff r==k%DIM, B[k,c]=1 iff c==k%DIM => only C[r,r] + // nonzero. + for (int k = 0; k < KDIM; k++) { + int i = k % DIM; + a[i * KDIM + k] = 1; + b[k * DIM + i] = 1; + } + + int diag_val = KDIM / DIM; + for (int r = 0; r < DIM; r++) { + expected[r * DIM + r] = diag_val; + } +} + +int run_test(const char *test_name, elem_t *a, elem_t *b) { + hw_matmul_tiled(test_name, a, b, output_matrix); + // if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { + // printf("Test %s PASSED\n", test_name); + // return 1; + // } else { + // printf("Test %s FAILED\n", test_name); + // return 0; + // } +} + +int test_tiled_matmul() { + init_diag_ones(input_matrix_a, input_matrix_b, expected_matrix); + return run_test("K-tiled diag-ones matmul", input_matrix_a, input_matrix_b); +} + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + int passed = test_tiled_matmul(); + + if (passed) { + printf("tiled_matmul test PASSED\n"); + return 0; + } else { + printf("tiled_matmul test FAILED\n"); + return 1; + } + +#ifdef MULTICORE + exit(0); +#endif +} diff --git a/bbdev b/bbdev index 84b95e39..8fae4219 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 84b95e39e8da29dcb56845c37dad96bf796d7da9 +Subproject commit 8fae421972381c16fb66ab82192102245541a3f9 diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix index 41386472..80634b18 100644 --- a/scripts/nix/build-env-python.nix +++ b/scripts/nix/build-env-python.nix @@ -16,6 +16,7 @@ requests pysocks allure-pytest + matplotlib # pre-commit hooks (language: system use) black From 9cd49a7628b5d36c9797d0d9681003167a1b0b15 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 21 Mar 2026 16:58:08 +0800 Subject: [PATCH 183/238] [arch] del: remove bebop submodule and related files; refactor build scripts to use rust toolchain --- .gitmodules | 3 - arch/scripts/bdb_ndjson_viz.py | 86 +++++++++++---- arch/src/csrc/include/monitor/trace.h | 8 +- arch/src/csrc/src/monitor/trace/itrace.cc | 31 ++++-- .../balldomain/blink/SubRobRow.scala | 1 + .../prototype/gemmini/LoopCmdEncoder.scala | 1 + .../core/bbtile/BuckyballAccelerator.scala | 2 +- .../framework/core/bbtile/RoCCTypes.scala | 1 + .../framework/core/bbtile/RocketCoreBB.scala | 1 + .../frontend/globalrs/GlobalROB.scala | 82 ++++++++------ .../frontend/globalrs/ITraceDPI.scala | 5 +- .../frontend/scoreboard/BankScoreboard.scala | 26 +++-- bb-tests/workloads/src/CTest/CMakeLists.txt | 2 - .../workloads/src/CTest/bebop/CMakeLists.txt | 101 ------------------ .../src/CTest/bebop/mvin_mvout_acc_test.c | 48 --------- .../src/CTest/bebop/mvin_mvout_mset_test.c | 48 --------- .../src/CTest/bebop/mvin_mvout_test.c | 47 -------- .../src/CTest/toy/vecunit_tiled_matmul.c | 13 ++- bebop | 1 - docs | 2 +- flake.nix | 13 +-- scripts/nix/build-all.sh | 23 ++-- ...build-env-bebop.nix => build-env-rust.nix} | 2 +- scripts/nix/overlay.nix | 3 +- sourceme.sh | 5 - 25 files changed, 192 insertions(+), 363 deletions(-) delete mode 100644 bb-tests/workloads/src/CTest/bebop/CMakeLists.txt delete mode 100644 bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c delete mode 100644 bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c delete mode 100644 bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c delete mode 160000 bebop rename scripts/nix/{build-env-bebop.nix => build-env-rust.nix} (73%) diff --git a/.gitmodules b/.gitmodules index f37eca4a..0bd70752 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,9 +10,6 @@ [submodule "arch/thirdparty/t1"] path = arch/thirdparty/t1 url = https://github.com/DangoSys/t1.git -[submodule "bebop"] - path = bebop - url = https://github.com/DangoSys/bebop.git [submodule "bbdev"] path = bbdev url = https://github.com/DangoSys/bbdev.git diff --git a/arch/scripts/bdb_ndjson_viz.py b/arch/scripts/bdb_ndjson_viz.py index b58c39ce..4fb2406f 100644 --- a/arch/scripts/bdb_ndjson_viz.py +++ b/arch/scripts/bdb_ndjson_viz.py @@ -40,14 +40,19 @@ def clk_of(rec: dict[str, Any], fallback: int | None) -> int | None: def build_rob_intervals( records: list[dict[str, Any]], -) -> tuple[list[tuple[int, int, int, int, str]], bool]: +) -> tuple[list[tuple[int, int, int, int, str]], list[tuple[int, int, int, int]], bool]: """ - Build RoB active windows from itrace issue/complete pairs. - Returns (t0, t1, domain_id, rob_id), used_real_clk. + Build RoB intervals from itrace events. + Returns: + - active windows: issue->complete (t0, t1, domain_id, rob_id, funct_label) + - in-rob windows: alloc->complete (t0, t1, domain_id, rob_id) + - used_real_clk """ fmap = build_funct_map(default_isa_dir()) - open_by_key: dict[tuple[int, int], tuple[int, str]] = {} - out: list[tuple[int, int, int, int, str]] = [] + issue_open: dict[tuple[int, int], tuple[int, str]] = {} + alloc_open: dict[tuple[int, int], int] = {} + active_out: list[tuple[int, int, int, int, str]] = [] + inrob_out: list[tuple[int, int, int, int]] = [] used_clk = False seq = 0 @@ -77,19 +82,30 @@ def build_rob_intervals( except SystemExit: funct_lbl = str(rec["funct"]) - if ev == "issue": - open_by_key[key] = (int(t), funct_lbl) - elif ev == "complete" and key in open_by_key: - t0, flbl = open_by_key.pop(key) - t1 = int(t) - if t1 < t0: - t0, t1 = t1, t0 - if t1 == t0: - t1 += 1 - out.append((t0, t1, dom, rid, flbl)) + if ev == "alloc": + alloc_open[key] = int(t) + elif ev == "issue": + issue_open[key] = (int(t), funct_lbl) + elif ev == "complete": + if key in issue_open: + t0, flbl = issue_open.pop(key) + t1 = int(t) + if t1 < t0: + t0, t1 = t1, t0 + if t1 == t0: + t1 += 1 + active_out.append((t0, t1, dom, rid, flbl)) + if key in alloc_open: + t0 = alloc_open.pop(key) + t1 = int(t) + if t1 < t0: + t0, t1 = t1, t0 + if t1 == t0: + t1 += 1 + inrob_out.append((t0, t1, dom, rid)) seq += 1 - return out, used_clk + return active_out, inrob_out, used_clk def plot_timeline( @@ -106,18 +122,43 @@ def plot_timeline( if not records: raise SystemExit("empty trace") - rob_itv, used_clk = build_rob_intervals(records) - if not rob_itv: + rob_itv, inrob_itv, used_clk = build_rob_intervals(records) + if not rob_itv and not inrob_itv: raise SystemExit("no itrace issue/complete pairs found") - g0 = min(t0 for t0, _, _, _, _ in rob_itv) - g1 = max(t1 for _, t1, _, _, _ in rob_itv) + all_t0: list[int] = [] + all_t1: list[int] = [] + if rob_itv: + all_t0.extend(t0 for t0, _, _, _, _ in rob_itv) + all_t1.extend(t1 for _, t1, _, _, _ in rob_itv) + if inrob_itv: + all_t0.extend(t0 for t0, _, _, _ in inrob_itv) + all_t1.extend(t1 for _, t1, _, _ in inrob_itv) + g0 = min(all_t0) + g1 = max(all_t1) if g1 <= g0: g1 = g0 + 1 fig, ax = plt.subplots(1, 1, figsize=(14, 6)) - rows = sorted({(dom, rid) for _, _, dom, rid, _ in rob_itv}) + rows = sorted( + {(dom, rid) for _, _, dom, rid, _ in rob_itv} + | {(dom, rid) for _, _, dom, rid in inrob_itv} + ) y_of = {k: i for i, k in enumerate(rows)} + # Draw in-ROB occupancy (alloc->complete) as light gray background. + for t0, t1, dom, rid in inrob_itv: + y = y_of[(dom, rid)] + ax.barh( + y, + width=t1 - t0, + left=t0, + height=0.80, + color="#d9d9d9", + alpha=0.55, + edgecolor="none", + zorder=0, + ) + for t0, t1, dom, rid, flbl in rob_itv: y = y_of[(dom, rid)] ax.vlines( @@ -128,6 +169,7 @@ def plot_timeline( linestyles="-", linewidth=0.6, alpha=0.6, + zorder=1, ) ax.barh( y, @@ -138,6 +180,7 @@ def plot_timeline( alpha=0.9, edgecolor="black", linewidth=0.3, + zorder=2, ) if (t1 - t0) > 10 and flbl: ax.text( @@ -148,6 +191,7 @@ def plot_timeline( va="center", fontsize=7, color="white", + zorder=3, ) ax.set_xlim(g0, g1) diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index 9f47f5f6..afe79e5b 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -12,11 +12,11 @@ extern "C" { void dpi_bdb_set_clk(unsigned long long c); // DPI-C function for instruction trace (itrace) -// Called from GlobalROB when instructions are issued or completed -void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete +// Called from GlobalROB when instructions are allocated/issued/completed +void dpi_itrace(unsigned char is_issue, // 2 = alloc, 1 = issue, 0 = complete unsigned int rob_id, unsigned int domain_id, unsigned int funct, - unsigned long long rs1, unsigned long long rs2, - unsigned char bank_enable); + unsigned long long pc, unsigned long long rs1, + unsigned long long rs2, unsigned char bank_enable); // DPI-C function for memory trace (mtrace) // Called from MemBackend when read/write requests are made diff --git a/arch/src/csrc/src/monitor/trace/itrace.cc b/arch/src/csrc/src/monitor/trace/itrace.cc index f1f647e6..4262d322 100644 --- a/arch/src/csrc/src/monitor/trace/itrace.cc +++ b/arch/src/csrc/src/monitor/trace/itrace.cc @@ -46,37 +46,48 @@ static void u64_hex(char *buf, size_t n, unsigned long long v) { } // DPI-C function for instruction trace (itrace) -// Called when an instruction is issued or completed in GlobalROB -extern "C" void dpi_itrace(unsigned char is_issue, // 1 = issue, 0 = complete - unsigned int rob_id, unsigned int domain_id, - unsigned int funct, unsigned long long rs1, - unsigned long long rs2, unsigned char bank_enable) { +// Called when an instruction is allocated/issued/completed in GlobalROB +extern "C" void +dpi_itrace(unsigned char is_issue, // 2 = alloc, 1 = issue, 0 = complete + unsigned int rob_id, unsigned int domain_id, unsigned int funct, + unsigned long long pc, unsigned long long rs1, + unsigned long long rs2, unsigned char bank_enable) { if (!bdb_trace_on(BDB_TR_ITRACE)) { return; } init_itrace(); if (itrace_fp) { + char pc_hex[19]; char rs1_hex[19]; char rs2_hex[19]; + u64_hex(pc_hex, sizeof(pc_hex), pc); u64_hex(rs1_hex, sizeof(rs1_hex), rs1); u64_hex(rs2_hex, sizeof(rs2_hex), rs2); - if (is_issue) { + if (is_issue == 2) { + fprintf( + itrace_fp, + "{\"type\":\"itrace\",\"clk\":%llu,\"event\":\"alloc\",\"rob_id\":%u," + "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," + "\"bank\":\"%s\",\"pc\":\"%s\",\"rs1\":\"%s\",\"rs2\":\"%s\"}\n", + (unsigned long long)bdb_rtl_clk, rob_id, domain_id, funct, + bank_enable, bank_enable_str(bank_enable), pc_hex, rs1_hex, rs2_hex); + } else if (is_issue == 1) { fprintf( itrace_fp, "{\"type\":\"itrace\",\"clk\":%llu,\"event\":\"issue\",\"rob_id\":%u," "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," - "\"bank\":\"%s\",\"rs1\":\"%s\",\"rs2\":\"%s\"}\n", + "\"bank\":\"%s\",\"pc\":\"%s\",\"rs1\":\"%s\",\"rs2\":\"%s\"}\n", (unsigned long long)bdb_rtl_clk, rob_id, domain_id, funct, - bank_enable, bank_enable_str(bank_enable), rs1_hex, rs2_hex); + bank_enable, bank_enable_str(bank_enable), pc_hex, rs1_hex, rs2_hex); } else { fprintf(itrace_fp, "{\"type\":\"itrace\",\"clk\":%llu,\"event\":\"complete\",\"rob_" "id\":%u," "\"domain_id\":%u,\"funct\":\"0x%02x\",\"bank_enable\":%u," - "\"bank\":\"%s\"}\n", + "\"bank\":\"%s\",\"pc\":\"%s\"}\n", (unsigned long long)bdb_rtl_clk, rob_id, domain_id, funct, - bank_enable, bank_enable_str(bank_enable)); + bank_enable, bank_enable_str(bank_enable), pc_hex); } fflush(itrace_fp); } diff --git a/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala b/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala index fe36732f..288761b3 100644 --- a/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala +++ b/arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala @@ -29,6 +29,7 @@ object SubRobRow { w.slots(i).valid := false.B w.slots(i).cmd.domain_id := 0.U w.slots(i).cmd.cmd.raw_inst := 0.U + w.slots(i).cmd.cmd.pc := 0.U w.slots(i).cmd.cmd.funct := 0.U w.slots(i).cmd.cmd.funct3 := 0.U w.slots(i).cmd.cmd.rs2 := 0.U diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala index 077a5558..96f21030 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala @@ -37,6 +37,7 @@ class LoopCmdEncoder(val b: GlobalConfig) extends Module { // Defaults — all unused RoCCCommandBB fields zero slot.cmd.domain_id := 0.U slot.cmd.cmd.raw_inst := 0.U + slot.cmd.cmd.pc := 0.U slot.cmd.cmd.funct := 0.U slot.cmd.cmd.funct3 := 0.U slot.cmd.cmd.rs2 := 0.U diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index e489cb83..81c1901c 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -161,5 +161,5 @@ class BuckyballAccelerator(val b: GlobalConfig)(edge: TLEdgeOut) extends Module // --- Busy watchdog --- val busy_counter = RegInit(0.U(32.W)) busy_counter := Mux(frontend.io.busy, busy_counter + 1.U, 0.U) - assert(busy_counter < 10000.U, "BuckyballAccelerator: busy for too long!") + assert(busy_counter < 100000.U, "BuckyballAccelerator: busy for too long!") } diff --git a/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala b/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala index e969cfde..b77c8077 100644 --- a/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala +++ b/arch/src/main/scala/framework/core/bbtile/RoCCTypes.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.rocket.HellaCacheIO /** RoCC command bundle */ class RoCCCommandBB(xLen: Int = 64) extends Bundle { val raw_inst = UInt(32.W) + val pc = UInt(xLen.W) val funct = UInt(7.W) val funct3 = UInt(3.W) val rs2 = Bits(5.W) diff --git a/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala index bbc02b9b..bb742f56 100644 --- a/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala @@ -1243,6 +1243,7 @@ class RocketBB(tile: BBTile)(implicit p: Parameters) io.rocc.cmd.bits.funct3 := wb_reg_inst(14, 12) io.rocc.cmd.bits.rs2 := inst_bits.rs2 io.rocc.cmd.bits.rs1 := inst_bits.rs1 + io.rocc.cmd.bits.pc := wb_reg_pc io.rocc.cmd.bits.xd := inst_bits.xd io.rocc.cmd.bits.xs1 := inst_bits.xs1 io.rocc.cmd.bits.xs2 := inst_bits.xs2 diff --git a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala index f35b03fa..8545d583 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/GlobalROB.scala @@ -52,15 +52,21 @@ class GlobalROB(val b: GlobalConfig) extends Module { // --------------------------------------------------------------------------- // Instruction trace (DPI-C, defined in ITraceDPI.scala) // --------------------------------------------------------------------------- - val itrace = Module(new ITraceDPI) - itrace.io.is_issue := 0.U - itrace.io.rob_id := 0.U - itrace.io.domain_id := 0.U - itrace.io.funct := 0.U - itrace.io.rs1 := 0.U - itrace.io.rs2 := 0.U - itrace.io.bank_enable := 0.U - itrace.io.enable := false.B + val itraceAlloc = Module(new ITraceDPI) + val itraceIssue = Module(new ITraceDPI) + val itraceComp = Module(new ITraceDPI) + + for (t <- Seq(itraceAlloc, itraceIssue, itraceComp)) { + t.io.is_issue := 0.U + t.io.rob_id := 0.U + t.io.domain_id := 0.U + t.io.funct := 0.U + t.io.pc := 0.U + t.io.rs1 := 0.U + t.io.rs2 := 0.U + t.io.bank_enable := 0.U + t.io.enable := false.B + } // --------------------------------------------------------------------------- // Storage @@ -97,6 +103,16 @@ class GlobalROB(val b: GlobalConfig) extends Module { bat.io.free.mask := commitMask when(io.alloc.fire) { + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1 := io.alloc.bits.cmd.rs1 + itraceAlloc.io.rs2 := io.alloc.bits.cmd.rs2 + itraceAlloc.io.bank_enable := io.alloc.bits.cmd.funct(6, 4) + itraceAlloc.io.enable := true.B + robEntries(tailPtr).cmd := io.alloc.bits robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed robEntries(tailPtr).rob_id := tailPtr @@ -123,32 +139,35 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.complete.valid := true.B scoreboard.complete.bits := robEntries(cid).renamedBankAccess - itrace.io.is_issue := 0.U - itrace.io.rob_id := cid - itrace.io.domain_id := robEntries(cid).cmd.domain_id - itrace.io.funct := robEntries(cid).cmd.cmd.funct - itrace.io.rs1 := robEntries(cid).cmd.cmd.rs1 - itrace.io.rs2 := robEntries(cid).cmd.cmd.rs2 - itrace.io.bank_enable := robEntries(cid).cmd.cmd.funct(6, 4) - itrace.io.enable := true.B + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1 := robEntries(cid).cmd.cmd.rs1 + itraceComp.io.rs2 := robEntries(cid).cmd.cmd.rs2 + itraceComp.io.bank_enable := robEntries(cid).cmd.cmd.funct(6, 4) + itraceComp.io.enable := true.B } // --------------------------------------------------------------------------- // Issue: scan from head for first issuable entry (valid && !issued && !complete) // --------------------------------------------------------------------------- val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) for (i <- 0 until robDepth) { val ptr = wrapPtr(headPtr + i.U) - scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) } - val hasValid = scanValid.asUInt.orR - val firstValid = PriorityEncoder(scanValid.asUInt) - val actualIssuePtr = wrapPtr(headPtr + firstValid) + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = wrapPtr(headPtr + firstReady) scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess - val noHazard = !scoreboard.hasHazard - val canIssue = hasValid && noHazard + val canIssue = hasReady io.issue.valid := canIssue && !io.subRobActive io.issue.bits := robEntries(actualIssuePtr) @@ -162,14 +181,15 @@ class GlobalROB(val b: GlobalConfig) extends Module { scoreboard.issue.valid := true.B scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess - itrace.io.is_issue := 1.U - itrace.io.rob_id := robEntries(actualIssuePtr).rob_id - itrace.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id - itrace.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct - itrace.io.rs1 := robEntries(actualIssuePtr).cmd.cmd.rs1 - itrace.io.rs2 := robEntries(actualIssuePtr).cmd.cmd.rs2 - itrace.io.bank_enable := robEntries(actualIssuePtr).cmd.cmd.funct(6, 4) - itrace.io.enable := true.B + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1 := robEntries(actualIssuePtr).cmd.cmd.rs1 + itraceIssue.io.rs2 := robEntries(actualIssuePtr).cmd.cmd.rs2 + itraceIssue.io.bank_enable := robEntries(actualIssuePtr).cmd.cmd.funct(6, 4) + itraceIssue.io.enable := true.B } // --------------------------------------------------------------------------- diff --git a/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala b/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala index f744e56d..f93975cf 100644 --- a/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala +++ b/arch/src/main/scala/framework/frontend/globalrs/ITraceDPI.scala @@ -11,6 +11,7 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { val rob_id = Input(UInt(32.W)) val domain_id = Input(UInt(32.W)) val funct = Input(UInt(32.W)) + val pc = Input(UInt(64.W)) val rs1 = Input(UInt(64.W)) val rs2 = Input(UInt(64.W)) val bank_enable = Input(UInt(8.W)) @@ -25,6 +26,7 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { | input int unsigned rob_id, | input int unsigned domain_id, | input int unsigned funct, + | input longint unsigned pc, | input longint unsigned rs1, | input longint unsigned rs2, | input byte unsigned bank_enable @@ -35,6 +37,7 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { | input [31:0] rob_id, | input [31:0] domain_id, | input [31:0] funct, + | input [63:0] pc, | input [63:0] rs1, | input [63:0] rs2, | input [7:0] bank_enable, @@ -42,7 +45,7 @@ class ITraceDPI extends BlackBox with HasBlackBoxInline { |); | always @(*) begin | if (enable) begin - | dpi_itrace(is_issue, rob_id, domain_id, funct, rs1, rs2, bank_enable); + | dpi_itrace(is_issue, rob_id, domain_id, funct, pc, rs1, rs2, bank_enable); | end | end |endmodule diff --git a/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala b/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala index e41d267d..6270d0aa 100644 --- a/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala +++ b/arch/src/main/scala/framework/frontend/scoreboard/BankScoreboard.scala @@ -61,21 +61,29 @@ class BankScoreboard(val bankNum: Int, val robEntries: Int) extends Module { val query = IO(Input(new BankAccessInfo(bankIdLen))) @public val hasHazard = IO(Output(Bool())) + @public + val queryVec = IO(Input(Vec(robEntries, new BankAccessInfo(bankIdLen)))) + @public + val hazardVec = IO(Output(Vec(robEntries, Bool()))) val bankRdCount = RegInit(VecInit(Seq.fill(bankNum)(0.U(cntWidth.W)))) val bankWrBusy = RegInit(VecInit(Seq.fill(bankNum)(false.B))) // --- Hazard detection (reads current register state) --- - val q = query - val rd0_hazard = q.rd_bank_0_valid && bankWrBusy(q.rd_bank_0_id) - val rd1_hazard = q.rd_bank_1_valid && bankWrBusy(q.rd_bank_1_id) - - val wr_hazard = q.wr_bank_valid && ( - bankRdCount(q.wr_bank_id) =/= 0.U || - bankWrBusy(q.wr_bank_id) - ) + private def hazardOf(q: BankAccessInfo): Bool = { + val rd0_hazard = q.rd_bank_0_valid && bankWrBusy(q.rd_bank_0_id) + val rd1_hazard = q.rd_bank_1_valid && bankWrBusy(q.rd_bank_1_id) + val wr_hazard = q.wr_bank_valid && ( + bankRdCount(q.wr_bank_id) =/= 0.U || + bankWrBusy(q.wr_bank_id) + ) + rd0_hazard || rd1_hazard || wr_hazard + } - hasHazard := rd0_hazard || rd1_hazard || wr_hazard + hasHazard := hazardOf(query) + for (i <- 0 until robEntries) { + hazardVec(i) := hazardOf(queryVec(i)) + } // --- Compute per-bank deltas to handle simultaneous issue + complete --- for (bank <- 0 until bankNum) { diff --git a/bb-tests/workloads/src/CTest/CMakeLists.txt b/bb-tests/workloads/src/CTest/CMakeLists.txt index 38766598..65ce0354 100644 --- a/bb-tests/workloads/src/CTest/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/CMakeLists.txt @@ -1,6 +1,4 @@ set(CTEST_TOY_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/toy) -set(CTEST_BEBOP_WORKLOAD_DIR ${CTEST_WORKLOAD_DIR}/bebop) add_subdirectory(toy) -add_subdirectory(bebop) add_subdirectory(goban) diff --git a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt b/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt deleted file mode 100644 index dca2b4dc..00000000 --- a/bb-tests/workloads/src/CTest/bebop/CMakeLists.txt +++ /dev/null @@ -1,101 +0,0 @@ -set(ELF_CC "riscv64-unknown-elf-gcc") - -#------------------------------------------------------------------------------- -# Set baremetal compilation flags -#------------------------------------------------------------------------------- -set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) -set(C_FLAGS -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany - -fno-builtin-printf -specs=nano.specs -specs=nosys.specs -nostartfiles - -Wl,-T,${BBSIM_LD} -I${CTEST_TOY_WORKLOAD_DIR}) - -#------------------------------------------------------------------------------- -# Generate executables for different platforms -#------------------------------------------------------------------------------- -set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc") - -# Generate Linux version executables -function(add_linux_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}-linux") - - add_executable(${EXECUTABLE} - ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} - ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c) - target_include_directories(${EXECUTABLE} PRIVATE ${WORKLOAD_LIB_DIR}) - set_target_properties(${EXECUTABLE} PROPERTIES LINKER_LANGUAGE C) -endfunction() - -# Generate multicore baremetal version executables -function(add_multicore_baremetal_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}_multicore-baremetal") - - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} - ${CTEST_TOY_WORKLOAD_DIR}/start.S - -DMULTICORE=3 - ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c - ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} - -I${WORKLOAD_LIB_DIR} - DEPENDS - ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} - ${CTEST_TOY_WORKLOAD_DIR}/start.S - COMMENT "Building multicore baremetal executable: ${EXECUTABLE}" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - - add_custom_target(${TEST_NAME}_multicore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) -endfunction() - -# Generate singlecore baremetal version executables -function(add_singlecore_baremetal_test_target TEST_NAME SOURCE_FILE) - set(EXECUTABLE "${TEST_NAME}_singlecore-baremetal") - - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE} - COMMAND ${ELF_CC} ${C_FLAGS} -o ${EXECUTABLE} - ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c - ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} - -I${WORKLOAD_LIB_DIR} - DEPENDS - ${CTEST_BEBOP_WORKLOAD_DIR}/${SOURCE_FILE} - ${CTEST_TOY_WORKLOAD_DIR}/buckyball.c - COMMENT "Building singlecore baremetal executable: ${EXECUTABLE}" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - - add_custom_target(${TEST_NAME}_singlecore_baremetal - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${EXECUTABLE}) -endfunction() - -# Create cross-platform test targets -function(add_cross_platform_test_target TEST_NAME SOURCE_FILE) - add_linux_test_target(${TEST_NAME} ${SOURCE_FILE}) - add_multicore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - add_singlecore_baremetal_test_target(${TEST_NAME} ${SOURCE_FILE}) - - add_custom_target(${TEST_NAME} - DEPENDS - ${TEST_NAME}-linux - ${TEST_NAME}_multicore_baremetal - ${TEST_NAME}_singlecore_baremetal - COMMENT "Building ${TEST_NAME} for all platforms" - ) -endfunction() - -#------------------------------------------------------------------------------- -# Build list -#------------------------------------------------------------------------------- -set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static -Wl,--no-dynamic-linker") - -add_cross_platform_test_target(ctest_mvin_mvout_bebop_test mvin_mvout_test.c) -add_cross_platform_test_target(ctest_mvin_mvout_mset_bebop_test mvin_mvout_mset_test.c) -add_cross_platform_test_target(ctest_mvin_mvout_acc_bebop_test mvin_mvout_acc_test.c) - -add_custom_target(buckyball-CTest-bebop-build ALL DEPENDS - ctest_mvin_mvout_bebop_test - ctest_mvin_mvout_mset_bebop_test - ctest_mvin_mvout_acc_bebop_test - COMMENT "Building all workloads for Buckyball" - VERBATIM) diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c deleted file mode 100644 index 0f1a9259..00000000 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_acc_test.c +++ /dev/null @@ -1,48 +0,0 @@ -#include "../toy/buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) - -// Test matrices -static int32_t input_matrix[DIM * DIM] __attribute__((aligned(16))); -static int32_t output_matrix[DIM * DIM] __attribute__((aligned(16))); - -int mvin_mvout_acc_test() { - for (int i = 0; i < 4; i++) { - init_i32_random_matrix(input_matrix, DIM, DIM, 111); - int acc_bank_id = 2; // virtual bank id - bb_mem_alloc(acc_bank_id, 1, 4); // bank_id, row, col - bb_mvin((uintptr_t)input_matrix, acc_bank_id, DIM, 1); - clear_i32_matrix(output_matrix, DIM, DIM); - bb_fence(); - bb_mvout((uintptr_t)output_matrix, acc_bank_id, DIM, 1); - bb_fence(); - bb_mem_release(acc_bank_id); - if (!compare_i32_matrices(output_matrix, input_matrix, DIM, DIM)) { - printf("Test mvin/mvout simple %d FAILED\n", i); - return 0; - } else { - printf("Test mvin/mvout simple %d PASSED\n", i); - } - } - return 1; -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = mvin_mvout_acc_test(); - if (passed) { - printf("mvin/mvout simple test PASSED\n"); - } else { - printf("mvin/mvout simple test FAILED\n"); - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c deleted file mode 100644 index a0526404..00000000 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_mset_test.c +++ /dev/null @@ -1,48 +0,0 @@ -#include "../toy/buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) -#define DIM2 1024 - -// Test matrices -static elem_t input_matrix[DIM * DIM2] __attribute__((aligned(16))); -static elem_t output_matrix[DIM * DIM2] __attribute__((aligned(16))); - -int mvin_mvout_simple_test() { - for (int i = 0; i < 4; i++) { - init_u8_random_matrix(input_matrix, DIM, DIM2, 111); - int vbank_id = 2; // virtual bank id - bb_mem_alloc(vbank_id, 4, 1); - bb_mvin((uintptr_t)input_matrix, vbank_id, DIM2, 1); - clear_u8_matrix(output_matrix, DIM, DIM2); - bb_mvout((uintptr_t)output_matrix, vbank_id, DIM2, 1); - bb_mem_release(vbank_id); - bb_fence(); - if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM2)) { - printf("Test mvin/mvout simple %d FAILED\n", i); - return 0; - } else { - printf("Test mvin/mvout simple %d PASSED\n", i); - } - } - return 1; -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = mvin_mvout_simple_test(); - if (passed) { - printf("mvin/mvout simple test PASSED\n"); - } else { - printf("mvin/mvout simple test FAILED\n"); - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c b/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c deleted file mode 100644 index 02a389dd..00000000 --- a/bb-tests/workloads/src/CTest/bebop/mvin_mvout_test.c +++ /dev/null @@ -1,47 +0,0 @@ -#include "../toy/buckyball.h" -#include -#include -#include -#include -#include - -#define DIM (BANK_WIDTH / sizeof(elem_t) / 8) -#define DIM2 1024 - -// Test matrices -static elem_t input_matrix[DIM * DIM2] __attribute__((aligned(16))); -static elem_t output_matrix[DIM * DIM2] __attribute__((aligned(16))); - -int mvin_mvout_simple_test() { - for (int i = 0; i < 4; i++) { - init_u8_random_matrix(input_matrix, DIM, DIM2, 111); - bb_mem_alloc(0, 1, 1); - bb_mvin((uintptr_t)input_matrix, 0, DIM2, 1); - clear_u8_matrix(output_matrix, DIM, DIM2); - bb_mvout((uintptr_t)output_matrix, 0, DIM2, 1); - bb_mem_release(0); - bb_fence(); - if (!compare_u8_matrices(output_matrix, input_matrix, DIM, DIM2)) { - printf("Test mvin/mvout simple %d FAILED\n", i); - return 0; - } else { - printf("Test mvin/mvout simple %d PASSED\n", i); - } - } - return 1; -} - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - int passed = mvin_mvout_simple_test(); - if (passed) { - printf("mvin/mvout simple test PASSED\n"); - } else { - printf("mvin/mvout simple test FAILED\n"); - } -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c index 7c93a66f..cf9e163b 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c @@ -5,8 +5,9 @@ #include #define DIM 16 -#define KDIM 64 -#define KTILE 16 +#define KDIM 1024 +#define KTILE 512 +#define MUL_REPEAT 4 _Static_assert(KDIM % KTILE == 0, "KDIM must be divisible by KTILE"); _Static_assert(KDIM % DIM == 0, "KDIM must be divisible by DIM"); @@ -30,11 +31,13 @@ void hw_matmul_tiled(const char *test_name, elem_t *a, elem_t *b, result_t *c) { bb_mvin((uintptr_t)zero_matrix, acc_bank_id, DIM, 1); - for (int k0 = 0; k0 < KDIM; k0 += KTILE) { + for (int k0 = 0; k0 < KDIM / KTILE; k0 += KTILE) { bb_mvin((uintptr_t)(a + k0), op1_bank_id, KTILE, 1); bb_mvin((uintptr_t)(b + k0 * DIM), op2_bank_id, KTILE, 1); bb_transpose(op1_bank_id, a_transposed_bank_id, KTILE, 0); - bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, KTILE, 0); + for (int rep = 0; rep < MUL_REPEAT; rep++) { + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, KTILE, 0); + } } bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); @@ -54,7 +57,7 @@ void init_diag_ones(elem_t *a, elem_t *b, result_t *expected) { b[k * DIM + i] = 1; } - int diag_val = KDIM / DIM; + int diag_val = (KDIM / DIM) * MUL_REPEAT; for (int r = 0; r < DIM; r++) { expected[r * DIM + r] = diag_val; } diff --git a/bebop b/bebop deleted file mode 160000 index cabf424a..00000000 --- a/bebop +++ /dev/null @@ -1 +0,0 @@ -Subproject commit cabf424ae58ed80e287869b1a211e53d62056953 diff --git a/docs b/docs index 476014bb..597d0cd9 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 476014bb12802817a5d70e61298935b8c4195a23 +Subproject commit 597d0cd91dbbfc9e9de338ae00f7e7384ae925a9 diff --git a/flake.nix b/flake.nix index 024e3115..d635928b 100644 --- a/flake.nix +++ b/flake.nix @@ -37,11 +37,11 @@ pkgs."pre-commit" pkgs.clang-tools # clang-format for pre-commit (language: system) - # Bebop dependencies (rust toolchain) - bebop.rustc - bebop.cargo - bebop.rustfmt - bebop.clippy + # Rust toolchain + rustTools.rustc + rustTools.cargo + rustTools.rustfmt + rustTools.clippy # bbdev dependencies bbdev.nodejs @@ -93,9 +93,6 @@ echo "Verilator: $(verilator --version 2>&1 | head -1)" echo "RISC-V Embedded GCC: $(riscv64-unknown-elf-gcc --version 2>&1 | head -1)" echo "RISC-V Linux GCC: $(riscv64-unknown-linux-gnu-gcc --version 2>&1 | head -1)" - echo "Bebop: $(which bebop)" - echo "Spike: $(which spike)" - echo "Bebop Gem5: $(which gem5.opt)" echo "Mill: $(mill --version 2>&1 | head -1)" echo "Cargo: $(cargo --version 2>&1 | head -1)" echo "npm: $(npm --version 2>&1 | head -1)" diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index eaafab92..41995485 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -14,10 +14,9 @@ usage() { echo " 1. bbdev install" echo " 2. Compiler installation" echo " 3. RTL pre-compile sources" - echo " 4. bebop install" - echo " 5. bb-tests pre-compile sources" - echo " 6. waveform-mcp build" - echo " 7. pre-commit hooks installation" + echo " 4. bb-tests pre-compile sources" + echo " 5. waveform-mcp build" + echo " 6. pre-commit hooks installation" echo "" echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" echo "" @@ -143,24 +142,18 @@ if run_step "3"; then fi if run_step "4"; then - begin_step "4" "bebop install" - cd ${BBDIR}/bebop - ./scripts/install.sh -fi - -if run_step "5"; then - begin_step "5" "bb-tests pre-compile sources" + begin_step "4" "bb-tests pre-compile sources" bbdev workload --build fi -if run_step "6"; then - begin_step "6" "waveform-mcp build" +if run_step "5"; then + begin_step "5" "waveform-mcp build" cd ${BBDIR}/thirdparty/waveform-mcp cargo build --release fi -if run_step "7"; then - begin_step "7" "pre-commit hooks installation" +if run_step "6"; then + begin_step "6" "pre-commit hooks installation" cd ${BBDIR} pre-commit install # Replace with wrapper so git commit gets nix env (result/bin in PATH) diff --git a/scripts/nix/build-env-bebop.nix b/scripts/nix/build-env-rust.nix similarity index 73% rename from scripts/nix/build-env-bebop.nix rename to scripts/nix/build-env-rust.nix index 2bcf3b8d..57cc5d90 100644 --- a/scripts/nix/build-env-bebop.nix +++ b/scripts/nix/build-env-rust.nix @@ -1,7 +1,7 @@ { pkgs }: { - # Rust toolchain (for building bebop) + # Rust toolchain (waveform-mcp, etc.) rustc = pkgs.rustc; cargo = pkgs.cargo; rustfmt = pkgs.rustfmt; diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 93f4af3f..90bd8b39 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -1,7 +1,8 @@ final: prev: { bbdev = final.callPackage ./build-env-bbdev.nix { }; - bebop = final.callPackage ./build-env-bebop.nix { }; + # Named rustTools to avoid shadowing nixpkgs `rust` (used by rust hooks) + rustTools = final.callPackage ./build-env-rust.nix { }; clibs = final.callPackage ./build-env-clibs.nix { }; doc = final.callPackage ./build-env-doc.nix { }; python = final.callPackage ./build-env-python.nix { }; diff --git a/sourceme.sh b/sourceme.sh index 5ad7ccef..2d4c8785 100644 --- a/sourceme.sh +++ b/sourceme.sh @@ -31,11 +31,6 @@ export PATH="${BBDIR}/thirdparty/libgloss/install/lib:$PATH" export PATH="${RESULT_PATH}/riscv64-unknown-elf/lib:${PATH}" export PATH="${RESULT_PATH}/bin:${PATH}" -# bebop / spike / gem5 (local builds) -export PATH="${BBDIR}/bebop/bebop/target/release:${PATH}" -export PATH="${BBDIR}/bebop/host/spike/riscv-isa-sim/install/bin:${PATH}" -export PATH="${BBDIR}/bebop/host/gem5/gem5/build/RISCV:${PATH}" - # bbdev CLI and Python utils export PATH="${BBDIR}/bbdev:${PATH}" export PYTHONPATH="${BBDIR}/bbdev/api:${PYTHONPATH}" From d5fd4719c4799a0888b943ffad5b4b84d266e1c2 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 21 Mar 2026 17:01:25 +0800 Subject: [PATCH 184/238] [bebop] feat: add bebop next --- .gitmodules | 4 ++++ bebop | 1 + 2 files changed, 5 insertions(+) create mode 160000 bebop diff --git a/.gitmodules b/.gitmodules index 0bd70752..48ff281c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -22,3 +22,7 @@ [submodule "thirdparty/waveform-mcp"] path = thirdparty/waveform-mcp url = https://github.com/jiegec/waveform-mcp.git +[submodule "bebop"] + path = bebop + url = https://github.com/DangoSys/bebop + branch = next diff --git a/bebop b/bebop new file mode 160000 index 00000000..ee033b8f --- /dev/null +++ b/bebop @@ -0,0 +1 @@ +Subproject commit ee033b8fc5c4d5eb65645c9cb07291e3254930c4 From 0bbb8fc39b5662ac48f685501798bed4832465f9 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 21 Mar 2026 19:59:04 +0800 Subject: [PATCH 185/238] [bebop] update: bump bebop version [bb-tests] fix: Linux workload use bdb bug --- bb-tests/workloads/src/CTest/toy/buckyball.c | 10 ++++++++-- bebop | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/buckyball.c b/bb-tests/workloads/src/CTest/toy/buckyball.c index 91e8c57e..331adb1c 100644 --- a/bb-tests/workloads/src/CTest/toy/buckyball.c +++ b/bb-tests/workloads/src/CTest/toy/buckyball.c @@ -274,11 +274,15 @@ unsigned long long read_cycle(void) { return c; } +// MMIO stubs are for baremetal/BBSim only. +// Linux user-mode tests (`*-linux` under `spike pk`) must use libc/syscall exit +// path. +#if !defined(__linux__) // MMIO address map (BBSimHarness, WithDefaultMMIOPort base=0x6000_0000): // 0x6000_0000 : simulation exit — write triggers sim_exit() // 0x6002_0000 : UART0 TX — write low byte → putchar in C++ #define MMIO_SIM_EXIT ((volatile uint32_t *)0x60000000UL) -#define MMIO_UART_TX ((volatile uint32_t *)0x60020000UL) +#define MMIO_UART_TX ((volatile uint32_t *)0x60020000UL) // _write: route stdout/stderr through MMIO UART so printf works in simulation. // nosys.specs provides a weak _write stub; we override it here. @@ -294,5 +298,7 @@ int _write(int fd, const char *buf, int len) { // this and calls sim_exit(). void __attribute__((noreturn)) _exit(int code) { *MMIO_SIM_EXIT = (uint32_t)code; - while (1) {} // wait for C++ to process the MMIO write and call sim_exit() + while (1) { + } // wait for C++ to process the MMIO write and call sim_exit() } +#endif diff --git a/bebop b/bebop index ee033b8f..2734c088 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit ee033b8fc5c4d5eb65645c9cb07291e3254930c4 +Subproject commit 2734c088b54686e89eb19c96578046f2092920e7 From 298af92dd939d05061a001c4e7240783c728c9fc Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 21 Mar 2026 22:25:19 +0800 Subject: [PATCH 186/238] [bb-tests] fix: correct_tiled_matmul --- .../src/CTest/toy/vecunit_tiled_matmul.c | 42 ++++++++++++------- bebop | 2 +- 2 files changed, 27 insertions(+), 17 deletions(-) diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c index cf9e163b..a98bc83d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c @@ -3,22 +3,28 @@ #include #include #include +#include #define DIM 16 #define KDIM 1024 #define KTILE 512 -#define MUL_REPEAT 4 _Static_assert(KDIM % KTILE == 0, "KDIM must be divisible by KTILE"); _Static_assert(KDIM % DIM == 0, "KDIM must be divisible by DIM"); +_Static_assert(KTILE % 16 == 0, + "KTILE must be multiple of 16 (mvin line size)"); static elem_t input_matrix_a[DIM * KDIM] __attribute__((aligned(64))); static elem_t input_matrix_b[KDIM * DIM] __attribute__((aligned(64))); +static elem_t tile_a[DIM * KTILE] __attribute__((aligned(64))); static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t zero_matrix[DIM * DIM] __attribute__((aligned(64))) = {0}; +/// C = A * B with A row-major DIM×KDIM, B row-major KDIM×DIM; K 维按 KTILE +/// 分块累加到 acc。 void hw_matmul_tiled(const char *test_name, elem_t *a, elem_t *b, result_t *c) { + (void)test_name; uint32_t op1_bank_id = 0; uint32_t op2_bank_id = 1; int acc_bank_id = 2; @@ -31,13 +37,17 @@ void hw_matmul_tiled(const char *test_name, elem_t *a, elem_t *b, result_t *c) { bb_mvin((uintptr_t)zero_matrix, acc_bank_id, DIM, 1); - for (int k0 = 0; k0 < KDIM / KTILE; k0 += KTILE) { - bb_mvin((uintptr_t)(a + k0), op1_bank_id, KTILE, 1); + for (int k0 = 0; k0 < KDIM; k0 += KTILE) { + /* Row-major A: column block [k0, k0+KTILE) is not contiguous across rows; + * pack to tile_a. */ + for (int r = 0; r < DIM; r++) { + memcpy(&tile_a[r * KTILE], &a[r * KDIM + k0], (size_t)KTILE); + } + bb_mvin((uintptr_t)tile_a, op1_bank_id, DIM * (KTILE / 16), 1); + /* B rows k0..k0+KTILE-1 are contiguous: each row is DIM bytes. */ bb_mvin((uintptr_t)(b + k0 * DIM), op2_bank_id, KTILE, 1); bb_transpose(op1_bank_id, a_transposed_bank_id, KTILE, 0); - for (int rep = 0; rep < MUL_REPEAT; rep++) { - bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, KTILE, 0); - } + bb_mul_warp16(a_transposed_bank_id, op2_bank_id, acc_bank_id, KTILE, 0); } bb_mvout((uintptr_t)c, acc_bank_id, DIM, 1); @@ -49,15 +59,15 @@ void init_diag_ones(elem_t *a, elem_t *b, result_t *expected) { clear_u8_matrix(b, KDIM, DIM); clear_u32_matrix(expected, DIM, DIM); - // One 1 per k: A[r,k]=1 iff r==k%DIM, B[k,c]=1 iff c==k%DIM => only C[r,r] - // nonzero. + /* One 1 per k: A[r,k]=1 iff r==k%DIM, B[k,c]=1 iff c==k%DIM => C[r,c] nonzero + * only on diagonal. */ for (int k = 0; k < KDIM; k++) { int i = k % DIM; a[i * KDIM + k] = 1; b[k * DIM + i] = 1; } - int diag_val = (KDIM / DIM) * MUL_REPEAT; + int diag_val = KDIM / DIM; for (int r = 0; r < DIM; r++) { expected[r * DIM + r] = diag_val; } @@ -65,13 +75,13 @@ void init_diag_ones(elem_t *a, elem_t *b, result_t *expected) { int run_test(const char *test_name, elem_t *a, elem_t *b) { hw_matmul_tiled(test_name, a, b, output_matrix); - // if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { - // printf("Test %s PASSED\n", test_name); - // return 1; - // } else { - // printf("Test %s FAILED\n", test_name); - // return 0; - // } + if (compare_u32_matrices(output_matrix, expected_matrix, DIM, DIM)) { + printf("Test %s PASSED\n", test_name); + return 1; + } else { + printf("Test %s FAILED\n", test_name); + return 0; + } } int test_tiled_matmul() { diff --git a/bebop b/bebop index 2734c088..6a037eb7 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 2734c088b54686e89eb19c96578046f2092920e7 +Subproject commit 6a037eb7eaeb8a5477202621a17d433416bd37bb From ab998be982cdb8db3abe378cd2f7c41f3b20cab0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 22 Mar 2026 23:34:17 +0800 Subject: [PATCH 187/238] [compiler] update: bump compiler to support latest buckyball ISAs --- .gitignore | 1 + bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir | 5 +++-- bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir | 13 +++++++------ bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir | 5 +++-- .../workloads/src/OpTest/toy/bb_mvin_mvout.mlir | 5 +++-- bebop | 2 +- compiler | 2 +- flake.nix | 15 +++++++++++++++ scripts/nix/build-env-clibs.nix | 6 ++++++ sourceme.sh | 10 ++++++---- 10 files changed, 46 insertions(+), 18 deletions(-) diff --git a/.gitignore b/.gitignore index 1dd60dae..5421eb21 100644 --- a/.gitignore +++ b/.gitignore @@ -4,6 +4,7 @@ .cursor/ .bsp/ out/ +.Xil/ result CLAUDE.local.md diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir index 142f474f..5d7975d6 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir @@ -19,6 +19,7 @@ func.func @main() -> i8 { %0 = arith.constant 0 : i8 // Bank ID for data storage %bankId = arith.constant 0 : i64 + %depth = arith.constant 4 : i64 %stride = arith.constant 1 : i64 %arrayA = memref.get_global @input_matrix_aligned : memref<4x16xi8> @@ -34,9 +35,9 @@ func.func @main() -> i8 { // Use mvin to move data from 16-byte aligned address to scratchpad // CHECK: mvin // Use mvout to move data from scratchpad to 16-byte aligned target address - buckyball.bb_mvin %arrayA %bankId %stride : memref<4x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId : memref<4x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 // Print output matrix after move [CHECK2] buckyball.bb_print_memref %arrayB : memref<4x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir index 6fdafbe9..ccbae12d 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir @@ -20,6 +20,7 @@ func.func @main() -> i8 { // Bank IDs %bankId0 = arith.constant 0 : i64 %bankId1 = arith.constant 1 : i64 + %depth = arith.constant 2 : i64 %stride = arith.constant 1 : i64 %arrayA = memref.get_global @input_matrix_a : memref<2x16xi8> @@ -40,23 +41,23 @@ func.func @main() -> i8 { // Step 1: A -> bank 0 // CHECK: mvin // Step 2: scratchpad 1 -> temp - buckyball.bb_mvin %arrayA %bankId0 %stride : memref<2x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayTemp %bankId0 : memref<2x16xi8> i64 + buckyball.bb_mvout %arrayTemp %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 // Step 3: B -> bank 1 // CHECK: mvin // Step 4: bank 1 -> A - buckyball.bb_mvin %arrayB %bankId1 %stride : memref<2x16xi8> i64 i64 + buckyball.bb_mvin %arrayB %bankId1 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayA %bankId1 : memref<2x16xi8> i64 + buckyball.bb_mvout %arrayA %bankId1 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 // Step 5: temp -> bank 0 // CHECK: mvin // Step 6: bank 0 -> B - buckyball.bb_mvin %arrayTemp %bankId0 %stride : memref<2x16xi8> i64 i64 + buckyball.bb_mvin %arrayTemp %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId0 : memref<2x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 // Print swapped matrices [CHECK2] buckyball.bb_print_memref %arrayA : memref<2x16xi8> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir index 939f7591..a98f5df9 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir @@ -19,6 +19,7 @@ func.func @main() -> i8 { %c127 = arith.constant 127 : index // Bank ID for storage %bankId = arith.constant 0 : i64 + %depth = arith.constant 1023 : i64 %stride = arith.constant 1 : i64 // ========== Row count configuration area (only modify here) ========== @@ -67,11 +68,11 @@ func.func @main() -> i8 { // Execute long read/write operations // Step 1: long read - read large amount of data from memory into scratchpad // CHECK: mvin - buckyball.bb_mvin %arrayA %bankId %stride : memref<1023x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId %depth %stride : memref<1023x16xi8> i64 i64 i64 i64 // Step 2: long write - write large amount of data from scratchpad to memory // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId : memref<1023x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId %depth %stride : memref<1023x16xi8> i64 i64 i64 i64 // Print first two rows and last two rows of output matrix after move [CHECK2] %arrayB_head_after = memref.subview %arrayB[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> diff --git a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir index 50f2cd28..facf61ca 100644 --- a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir +++ b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir @@ -20,6 +20,7 @@ func.func @main() -> i8 { // === Main program === %0 = arith.constant 0 : i8 %bankId = arith.constant 0 : i64 + %depth = arith.constant 4 : i64 %stride = arith.constant 1 : i64 %arrayA = memref.get_global @input_matrix : memref<4x16xi8> %arrayB = memref.alloc() : memref<4x16xi8> @@ -27,10 +28,10 @@ func.func @main() -> i8 { buckyball.bb_mset %bankId : i64 // Use mvin to move data from memory to bank 0 // CHECK: mvin - buckyball.bb_mvin %arrayA %bankId %stride : memref<4x16xi8> i64 i64 + buckyball.bb_mvin %arrayA %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 // Use mvout to move data from bank 0 back to output memory // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId : memref<4x16xi8> i64 + buckyball.bb_mvout %arrayB %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 // Print moved output matrix buckyball.bb_print_memref %arrayB : memref<4x16xi8> // Release allocated memory diff --git a/bebop b/bebop index 6a037eb7..d72d4931 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 6a037eb7eaeb8a5477202621a17d433416bd37bb +Subproject commit d72d49313be2b75268d0ac6d0249b7d3f92a4c03 diff --git a/compiler b/compiler index 71fbdf72..0fa1448a 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit 71fbdf72c3361b22064fc5596c3e7d22beda4b38 +Subproject commit 0fa1448ac9d10deb3b14ef5dffc46d8da1a8ed52 diff --git a/flake.nix b/flake.nix index d635928b..6332fda7 100644 --- a/flake.nix +++ b/flake.nix @@ -57,6 +57,10 @@ clibs.zlib clibs.readline-dev clibs.readline + clibs.jpeg-dev + clibs.jpeg + clibs.png-dev + clibs.png # Scala tools scala.mill @@ -75,6 +79,16 @@ # nix develop devShells.default = pkgs.mkShell { + buildInputs = with pkgs; [ + clibs.zlib-dev + clibs.zlib + clibs.readline-dev + clibs.readline + clibs.jpeg-dev + clibs.jpeg + clibs.png-dev + clibs.png + ]; shellHook = '' if [ -d "$PWD/result/bin" ]; then export PATH="$PWD/result/bin:$PATH" @@ -100,6 +114,7 @@ echo "RISCV: $RISCV" echo "Yosys: $(yosys --version 2>&1 | head -1)" echo "OpenSTA: $(sta -version 2>&1 | head -1)" + echo "Buddy MLIR: $(which buddy-opt)" echo "===========================================================================" fi ''; diff --git a/scripts/nix/build-env-clibs.nix b/scripts/nix/build-env-clibs.nix index fa452534..90a2f9c4 100644 --- a/scripts/nix/build-env-clibs.nix +++ b/scripts/nix/build-env-clibs.nix @@ -7,4 +7,10 @@ # C libraries needed by bdb debugger readline-dev = pkgs.readline.dev; readline = pkgs.readline; + # buddy DIP imgcodecs (grfmt_jpeg.h) + jpeg-dev = pkgs.libjpeg.dev; + jpeg = pkgs.libjpeg; + # buddy DIP imgcodecs (grfmt_png.h) + png-dev = pkgs.libpng.dev; + png = pkgs.libpng; } diff --git a/sourceme.sh b/sourceme.sh index 2d4c8785..2cdffb4f 100644 --- a/sourceme.sh +++ b/sourceme.sh @@ -6,10 +6,10 @@ BBDIR=$(dirname "$(readlink -f "${BASH_SOURCE[0]}")") RESULT_PATH="${BBDIR}/result" -if [ ! -d "$RESULT_PATH" ]; then - echo "Warning: result not found at $RESULT_PATH. Run 'nix build' first." >&2 - return 1 2>/dev/null || exit 1 -fi +# if [ ! -d "$RESULT_PATH" ]; then +# echo "Warning: result not found at $RESULT_PATH. Run 'nix build' first." >&2 +# return 1 2>/dev/null || exit 1 +# fi #===----------------------------------------------------------------------------=== # Source each submodule's ShellHooks @@ -22,8 +22,10 @@ fi export BUDDY_MLIR_BUILD_DIR="${BBDIR}/compiler/build" export LLVM_MLIR_BUILD_DIR="${BBDIR}/compiler/llvm/build" export PYTHONPATH="${BBDIR}/compiler/llvm/build/tools/mlir/python_packages/mlir_core:${BBDIR}/compiler/build/python_packages:$PYTHONPATH" +export BUDDY_BINARY_DIR="${BBDIR}/compiler/build/bin" export RISCV="${BBDIR}/result" export PATH="${BBDIR}/thirdparty/libgloss/install/lib:$PATH" +export PATH="${BUDDY_BINARY_DIR}:${PATH}" #===----------------------------------------------------------------------------=== # Export each submodule's PATH From e27a4da8555fd8a9e42b45779aa82f44e0e0cfd8 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 23 Mar 2026 22:32:35 +0800 Subject: [PATCH 188/238] [bb-tests] del: remove OpTest toy and tile workloads, update CMakeLists to reflect changes --- bb-tests/workloads/src/OpTest/CMakeLists.txt | 7 +- .../workloads/src/OpTest/tile/CMakeLists.txt | 77 --------------- bb-tests/workloads/src/OpTest/tile/README.md | 43 --------- .../src/OpTest/tile/buckyball-to-llvm.mlir | 10 -- .../workloads/src/OpTest/tile/end-to-end.mlir | 16 ---- .../src/OpTest/tile/tile-matmul.mlir | 14 --- .../src/OpTest/tile/tile-to-buckyball.mlir | 7 -- .../src/OpTest/tile/tile-transpose.mlir | 13 --- .../src/OpTest/tile/tile_conv2d.mlir | 40 -------- .../src/OpTest/tile/tile_matmul.mlir | 93 ------------------- .../src/OpTest/tile/tile_transpose.mlir | 56 ----------- .../workloads/src/OpTest/toy/CMakeLists.txt | 82 ---------------- .../workloads/src/OpTest/toy/bb_conv2d.mlir | 43 --------- .../workloads/src/OpTest/toy/bb_dma1.mlir | 48 ---------- .../workloads/src/OpTest/toy/bb_dma2.mlir | 69 -------------- .../workloads/src/OpTest/toy/bb_dma3.mlir | 87 ----------------- .../workloads/src/OpTest/toy/bb_im2col.mlir | 46 --------- .../src/OpTest/toy/bb_mul_warp16.mlir | 55 ----------- .../src/OpTest/toy/bb_mvin_mvout.mlir | 40 -------- .../src/OpTest/toy/bb_quant_dequant.mlir | 51 ---------- compiler | 2 +- 21 files changed, 4 insertions(+), 895 deletions(-) delete mode 100644 bb-tests/workloads/src/OpTest/tile/CMakeLists.txt delete mode 100644 bb-tests/workloads/src/OpTest/tile/README.md delete mode 100644 bb-tests/workloads/src/OpTest/tile/buckyball-to-llvm.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/end-to-end.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/tile-matmul.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/tile-to-buckyball.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/tile-transpose.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir delete mode 100644 bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/CMakeLists.txt delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir delete mode 100644 bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir diff --git a/bb-tests/workloads/src/OpTest/CMakeLists.txt b/bb-tests/workloads/src/OpTest/CMakeLists.txt index 685e67a3..0640aae5 100644 --- a/bb-tests/workloads/src/OpTest/CMakeLists.txt +++ b/bb-tests/workloads/src/OpTest/CMakeLists.txt @@ -1,10 +1,9 @@ set(OPTEST_TOY_DIR ${OPTEST_WORKLOAD_DIR}/toy) set(OPTEST_TILE_DIR ${OPTEST_WORKLOAD_DIR}/tile) -add_subdirectory(toy) -add_subdirectory(tile) +# add_subdirectory(toy) +# add_subdirectory(tile) add_custom_target(OpTest-all ALL DEPENDS - OpTest-toy - OpTest-tile + ) diff --git a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt b/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt deleted file mode 100644 index 19e13f0f..00000000 --- a/bb-tests/workloads/src/OpTest/tile/CMakeLists.txt +++ /dev/null @@ -1,77 +0,0 @@ - -#------------------------------------------------------------------------------- -# Generate executables for different platforms -#------------------------------------------------------------------------------- - -# Resolve toy runtime paths -set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) -set(CRT0_S ${CTEST_TOY_WORKLOAD_DIR}/crt0.S) - -# singlecore baremetal -function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) - set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal.o") - set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal") - - # Compile xx.mlir to xx-baremetal.o - # Tile-level tests need: linalg->tile->buckyball->llvm pipeline - add_custom_command( - OUTPUT ${OBJ_FILE} - COMMAND ${BUDDY_OPT} ${MLIR_FILE} - -convert-linalg-to-tile - -convert-tile-to-buckyball - -expand-strided-metadata - -convert-linalg-to-loops - -lower-buckyball - -convert-scf-to-cf - -finalize-memref-to-llvm - -convert-arith-to-llvm - -convert-cf-to-llvm - -convert-func-to-llvm - -reconcile-unrealized-casts | - ${BUDDY_TRANSLATE} --buddy-to-llvmir | - ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 - -mattr=+buddyext,+D -float-abi=hard - -relocation-model=pic - -o ${OBJ_FILE} - DEPENDS ${MLIR_FILE} - COMMENT "Compiling ${MLIR_FILE} to singlecore baremetal object" - ) - - # Link with toy bbsim runtime (BBSimHarness MMIO) - add_custom_command( - OUTPUT ${EXECUTABLE} - COMMAND ${ELF_CC} -O2 -static -march=rv64gc -mcmodel=medany -nostartfiles - -specs=nano.specs -specs=nosys.specs - -Wl,-T,${BBSIM_LD} - ${CRT0_S} ${OBJ_FILE} -o ${EXECUTABLE} - DEPENDS ${OBJ_FILE} ${CRT0_S} ${BBSIM_LD} - COMMENT "Linking singlecore baremetal executable: ${EXECUTABLE}" - ) - - add_custom_target(${TARGET_NAME}_singlecore_baremetal - DEPENDS ${EXECUTABLE} - ) -endfunction() - -# Unified build function -function(add_optest_target TARGET_NAME MLIR_FILE) - add_singlecore_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) - - add_custom_target(${TARGET_NAME} - DEPENDS ${TARGET_NAME}_singlecore_baremetal - COMMENT "Building ${TARGET_NAME}" - ) -endfunction() - -#------------------------------------------------------------------------------- -# Build list -#------------------------------------------------------------------------------- -add_optest_target(tile_matmul ${OPTEST_TILE_DIR}/tile_matmul.mlir) -add_optest_target(tile_transpose ${OPTEST_TILE_DIR}/tile_transpose.mlir) -add_optest_target(tile_conv2d ${OPTEST_TILE_DIR}/tile_conv2d.mlir) - -add_custom_target(OpTest-tile ALL DEPENDS - tile_matmul - tile_transpose - tile_conv2d -) diff --git a/bb-tests/workloads/src/OpTest/tile/README.md b/bb-tests/workloads/src/OpTest/tile/README.md deleted file mode 100644 index 2ce05f8b..00000000 --- a/bb-tests/workloads/src/OpTest/tile/README.md +++ /dev/null @@ -1,43 +0,0 @@ -# Tile Dialect Test Cases - -## Test Files - -### Stage-by-Stage Tests -- `tile-matmul.mlir` - Test Linalg → Tile conversion -- `tile-to-buckyball.mlir` - Test Tile → Buckyball conversion -- `buckyball-to-llvm.mlir` - Test Buckyball MatMulOp → LLVM Intrinsics conversion - -### End-to-End Tests -- `end-to-end.mlir` - Complete conversion pipeline test (Linalg → Tile → Buckyball → LLVM) - -## Running Tests - -```bash -# Stage 1: Linalg → Tile -./compiler/build/bin/buddy-opt bb-tests/workloads/src/OpTest/tile/tile-matmul.mlir -convert-linalg-to-tile - -# Stage 2: Tile → Buckyball -./compiler/build/bin/buddy-opt bb-tests/workloads/src/OpTest/tile/tile-to-buckyball.mlir -convert-tile-to-buckyball - -# Stage 3: Buckyball → LLVM Intrinsics -./compiler/build/bin/buddy-opt bb-tests/workloads/src/OpTest/tile/buckyball-to-llvm.mlir \ - -lower-buckyball="dim=16 sp_addr_len=14 spad_rows=1024 acc_rows=1024 warp=16 lane=16" - -# End-to-end test: Complete pipeline -./compiler/build/bin/buddy-opt bb-tests/workloads/src/OpTest/tile/end-to-end.mlir \ - -convert-linalg-to-tile \ - -convert-tile-to-buckyball \ - -lower-buckyball="dim=16 sp_addr_len=14 spad_rows=1024 acc_rows=1024 warp=16 lane=16" -``` - -## New Architecture Description - -``` -Linalg MatmulOp - ↓ (convert-linalg-to-tile) -Tile TileMatMulOp - ↓ (convert-tile-to-buckyball) -Buckyball MatMulOp - ↓ (lower-buckyball) -LLVM Intrinsics (mvin/mvout/mul_warp16) -``` diff --git a/bb-tests/workloads/src/OpTest/tile/buckyball-to-llvm.mlir b/bb-tests/workloads/src/OpTest/tile/buckyball-to-llvm.mlir deleted file mode 100644 index ea10d8a3..00000000 --- a/bb-tests/workloads/src/OpTest/tile/buckyball-to-llvm.mlir +++ /dev/null @@ -1,10 +0,0 @@ -// RUN: buddy-opt %s -lower-buckyball="dim=16 sp_addr_len=14 spad_rows=1024 acc_rows=1024 warp=16 lane=16" | FileCheck %s - -func.func @buckyball_matmul_to_llvm(%arg0: memref<32x16xi8>, %arg1: memref<16x32xi8>, %arg2: memref<32x32xi32>) { - // CHECK: buckyball.intr.bb_mvin - // CHECK: buckyball.intr.bb_mvin - // CHECK: buckyball.intr.bb_mul_warp16 - // CHECK: buckyball.intr.bb_mvout - buckyball.bb_matmul %arg0 %arg1 %arg2 : memref<32x16xi8> memref<16x32xi8> memref<32x32xi32> - return -} diff --git a/bb-tests/workloads/src/OpTest/tile/end-to-end.mlir b/bb-tests/workloads/src/OpTest/tile/end-to-end.mlir deleted file mode 100644 index 09b69d2a..00000000 --- a/bb-tests/workloads/src/OpTest/tile/end-to-end.mlir +++ /dev/null @@ -1,16 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: -convert-linalg-to-tile \ -// RUN: -convert-tile-to-buckyball \ -// RUN: -lower-buckyball="dim=16 sp_addr_len=14 spad_rows=1024 acc_rows=1024 warp=16 lane=16" \ -// RUN: | FileCheck %s - -// Complete conversion flow test: linalg.matmul → tile.tile_matmul → buckyball.bb_matmul → intrinsics -func.func @end_to_end_test(%arg0: memref<32x32xi8>, %arg1: memref<32x32xi8>, %arg2: memref<32x32xi32>) { - // CHECK: buckyball.intr.bb_mvin - // CHECK: buckyball.intr.bb_mul_warp16 - // CHECK: buckyball.intr.bb_mvout - linalg.matmul - ins(%arg0, %arg1 : memref<32x32xi8>, memref<32x32xi8>) - outs(%arg2 : memref<32x32xi32>) - return -} diff --git a/bb-tests/workloads/src/OpTest/tile/tile-matmul.mlir b/bb-tests/workloads/src/OpTest/tile/tile-matmul.mlir deleted file mode 100644 index 1df68ff5..00000000 --- a/bb-tests/workloads/src/OpTest/tile/tile-matmul.mlir +++ /dev/null @@ -1,14 +0,0 @@ -// RUN: buddy-opt %s -convert-linalg-to-tile | FileCheck %s - -#map0 = affine_map<(d0, d1) -> (d0, d1)> -#map1 = affine_map<(d0, d1, d2) -> (d0, d2)> -#map2 = affine_map<(d0, d1, d2) -> (d2, d1)> -#map3 = affine_map<(d0, d1, d2) -> (d0, d1)> - -func.func @matmul_tile(%arg0: memref<32x32xi8>, %arg1: memref<32x32xi8>, %arg2: memref<32x32xi32>) { - // CHECK: tile.tile_matmul - linalg.matmul - ins(%arg0, %arg1 : memref<32x32xi8>, memref<32x32xi8>) - outs(%arg2 : memref<32x32xi32>) - return -} diff --git a/bb-tests/workloads/src/OpTest/tile/tile-to-buckyball.mlir b/bb-tests/workloads/src/OpTest/tile/tile-to-buckyball.mlir deleted file mode 100644 index 3ea2f41a..00000000 --- a/bb-tests/workloads/src/OpTest/tile/tile-to-buckyball.mlir +++ /dev/null @@ -1,7 +0,0 @@ -// RUN: buddy-opt %s -convert-tile-to-buckyball | FileCheck %s - -func.func @tile_to_buckyball(%arg0: memref<32x32xi8>, %arg1: memref<32x32xi8>, %arg2: memref<32x32xi32>) { - // CHECK: buckyball.bb_matmul - tile.tile_matmul %arg0 %arg1 %arg2 : memref<32x32xi8> memref<32x32xi8> memref<32x32xi32> - return -} diff --git a/bb-tests/workloads/src/OpTest/tile/tile-transpose.mlir b/bb-tests/workloads/src/OpTest/tile/tile-transpose.mlir deleted file mode 100644 index f281e9bd..00000000 --- a/bb-tests/workloads/src/OpTest/tile/tile-transpose.mlir +++ /dev/null @@ -1,13 +0,0 @@ -// RUN: buddy-opt %s -convert-linalg-to-tile | FileCheck %s - -#map0 = affine_map<(d0, d1) -> (d0, d1)> -#map1 = affine_map<(d0, d1) -> (d1, d0)> - -func.func @transpose_tile(%arg0: memref<32x32xi8>, %arg1: memref<32x32xi8>) { - // CHECK: tile.tile_transpose - linalg.transpose - ins(%arg0 : memref<32x32xi8>) - outs(%arg1 : memref<32x32xi8>) - permutation = [1, 0] - return -} diff --git a/bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir b/bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir deleted file mode 100644 index 4db5b905..00000000 --- a/bb-tests/workloads/src/OpTest/tile/tile_conv2d.mlir +++ /dev/null @@ -1,40 +0,0 @@ -// Test for tile-level conv2d: linalg.conv_2d_nhwc_hwcf -> tile.tile_conv2d -> buckyball -// Pipeline: -convert-linalg-to-tile -convert-tile-to-buckyball -lower-buckyball -// Input: [1,6,6,1], Filter: [3,3,1,1], Output: [1,4,4,1] - -// Input image: 6x6 with incrementing values -memref.global "private" @input : memref<1x6x6x1xi8> = dense<[[ - [[1],[2],[3],[4],[5],[6]], - [[7],[8],[9],[10],[11],[12]], - [[13],[14],[15],[16],[17],[18]], - [[19],[20],[21],[22],[23],[24]], - [[25],[26],[27],[28],[29],[30]], - [[31],[32],[33],[34],[35],[36]] -]]> - -// Filter: 3x3 all ones (sum pooling equivalent) -memref.global "private" @filter : memref<3x3x1x1xi8> = dense<[[ - [[1]],[[1]],[[1]] -],[ - [[1]],[[1]],[[1]] -],[ - [[1]],[[1]],[[1]] -]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - - %input = memref.get_global @input : memref<1x6x6x1xi8> - %filter = memref.get_global @filter : memref<3x3x1x1xi8> - %output = memref.alloc() : memref<1x4x4x1xi32> - - // linalg.conv_2d_nhwc_hwcf -> tile.tile_conv2d -> im2col + matmul - linalg.conv_2d_nhwc_hwcf - ins(%input, %filter : memref<1x6x6x1xi8>, memref<3x3x1x1xi8>) - outs(%output : memref<1x4x4x1xi32>) - - buckyball.bb_print_memref %output : memref<1x4x4x1xi32> - - memref.dealloc %output : memref<1x4x4x1xi32> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir b/bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir deleted file mode 100644 index 19a72228..00000000 --- a/bb-tests/workloads/src/OpTest/tile/tile_matmul.mlir +++ /dev/null @@ -1,93 +0,0 @@ -// Test for tile-level matmul: linalg.matmul -> tile.tile_matmul -> buckyball -// Pipeline: -convert-linalg-to-tile -convert-tile-to-buckyball -lower-buckyball - -// Matrix A: 32x32 identity matrix -memref.global "private" @matrix_a : memref<32x32xi8> = dense<[ - [1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0], - [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1] -]> - -// Matrix B: 32x32 with row pattern -memref.global "private" @matrix_b : memref<32x32xi8> = dense<[ - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16] -]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - - %arrayA = memref.get_global @matrix_a : memref<32x32xi8> - %arrayB = memref.get_global @matrix_b : memref<32x32xi8> - %arrayC = memref.alloc() : memref<32x32xi32> - - // linalg.matmul -> tile.tile_matmul -> buckyball.bb_matmul -> intrinsics - // Identity * B = B (result should equal matrix B) - linalg.matmul - ins(%arrayA, %arrayB : memref<32x32xi8>, memref<32x32xi8>) - outs(%arrayC : memref<32x32xi32>) - - buckyball.bb_print_memref %arrayC : memref<32x32xi32> - - memref.dealloc %arrayC : memref<32x32xi32> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir b/bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir deleted file mode 100644 index 916e1d7e..00000000 --- a/bb-tests/workloads/src/OpTest/tile/tile_transpose.mlir +++ /dev/null @@ -1,56 +0,0 @@ -// Test for tile-level transpose: linalg.transpose -> tile.tile_transpose -> buckyball -// Pipeline: -convert-linalg-to-tile -convert-tile-to-buckyball -lower-buckyball - -// Matrix: 32x32 with distinct values for verification -memref.global "private" @matrix_input : memref<32x32xi8> = dense<[ - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64], - [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32], - [33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64] -]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - - %input = memref.get_global @matrix_input : memref<32x32xi8> - %output = memref.alloc() : memref<32x32xi8> - - // linalg.transpose -> tile.tile_transpose -> buckyball.bb_transpose -> intrinsics - linalg.transpose - ins(%input : memref<32x32xi8>) - outs(%output : memref<32x32xi8>) - permutation = [1, 0] - - buckyball.bb_print_memref %output : memref<32x32xi8> - - memref.dealloc %output : memref<32x32xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt b/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt deleted file mode 100644 index 38e1f058..00000000 --- a/bb-tests/workloads/src/OpTest/toy/CMakeLists.txt +++ /dev/null @@ -1,82 +0,0 @@ - -#------------------------------------------------------------------------------- -# Generate executables for different platforms -#------------------------------------------------------------------------------- - -# Resolve toy runtime paths -set(BBSIM_LD ${CTEST_TOY_WORKLOAD_DIR}/bbsim.ld) -set(CRT0_S ${CTEST_TOY_WORKLOAD_DIR}/crt0.S) - -# singlecore baremetal -function(add_singlecore_baremetal_target TARGET_NAME MLIR_FILE) - set(OBJ_FILE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal.o") - set(EXECUTABLE "${CMAKE_CURRENT_BINARY_DIR}/${TARGET_NAME}_singlecore-baremetal") - - # Compile xx.mlir to xx-baremetal.o - add_custom_command( - OUTPUT ${OBJ_FILE} - COMMAND ${BUDDY_OPT} ${MLIR_FILE} - -expand-strided-metadata - -convert-linalg-to-loops - -lower-buckyball - -convert-scf-to-cf - -finalize-memref-to-llvm - -convert-arith-to-llvm - -convert-cf-to-llvm - -convert-func-to-llvm - -reconcile-unrealized-casts | - ${BUDDY_TRANSLATE} --buddy-to-llvmir | - ${BUDDY_LLC} -filetype=obj -mtriple=riscv64 - -mattr=+buddyext,+D -float-abi=hard - -relocation-model=pic - -o ${OBJ_FILE} - DEPENDS ${MLIR_FILE} - COMMENT "Compiling ${MLIR_FILE} to singlecore baremetal object" - ) - - # Link with toy bbsim runtime (BBSimHarness MMIO) - add_custom_command( - OUTPUT ${EXECUTABLE} - COMMAND ${ELF_CC} -O2 -static -march=rv64gc -mcmodel=medany -nostartfiles - -specs=nano.specs -specs=nosys.specs - -Wl,-T,${BBSIM_LD} - ${CRT0_S} ${OBJ_FILE} -o ${EXECUTABLE} - DEPENDS ${OBJ_FILE} ${CRT0_S} ${BBSIM_LD} - COMMENT "Linking singlecore baremetal executable: ${EXECUTABLE}" - ) - - add_custom_target(${TARGET_NAME}_singlecore_baremetal - DEPENDS ${EXECUTABLE} - ) -endfunction() - -# Unified build function -function(add_optest_target TARGET_NAME MLIR_FILE) - add_singlecore_baremetal_target(${TARGET_NAME} ${MLIR_FILE}) - - add_custom_target(${TARGET_NAME} - DEPENDS ${TARGET_NAME}_singlecore_baremetal - COMMENT "Building ${TARGET_NAME}" - ) -endfunction() - -#------------------------------------------------------------------------------- -# Build list -#------------------------------------------------------------------------------- -add_optest_target(bb_mvin_mvout ${OPTEST_TOY_DIR}/bb_mvin_mvout.mlir) -add_optest_target(bb_dma1 ${OPTEST_TOY_DIR}/bb_dma1.mlir) -add_optest_target(bb_dma2 ${OPTEST_TOY_DIR}/bb_dma2.mlir) -add_optest_target(bb_dma3 ${OPTEST_TOY_DIR}/bb_dma3.mlir) -add_optest_target(bb_mul_warp16 ${OPTEST_TOY_DIR}/bb_mul_warp16.mlir) -add_optest_target(bb_im2col ${OPTEST_TOY_DIR}/bb_im2col.mlir) -add_optest_target(bb_quant_dequant ${OPTEST_TOY_DIR}/bb_quant_dequant.mlir) - -add_custom_target(OpTest-toy ALL DEPENDS - bb_mvin_mvout - bb_dma1 - bb_dma2 - bb_dma3 - bb_mul_warp16 - bb_im2col - bb_quant_dequant -) diff --git a/bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir b/bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir deleted file mode 100644 index 82ba009d..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_conv2d.mlir +++ /dev/null @@ -1,43 +0,0 @@ -// Test for conv2d end-to-end: tile_conv2d -> im2col + matmul -// RUN: buddy-opt %s \ -// RUN: -convert-tile-to-buckyball \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: verify conv2d tiling and lowering through Tile -> Buckyball -> LLVM -// Input: [1, 4, 4, 1] (N=1, H=4, W=4, C=1) -// Filter: [3, 3, 1, 1] (KH=3, KW=3, C=1, OC=1) -// Output: [1, 2, 2, 1] (N=1, OH=2, OW=2, OC=1) - -// Input: 1x4x4x1 -memref.global "private" @conv_input : memref<1x4x4x1xi8> = dense<[[ - [[1], [2], [3], [4]], - [[5], [6], [7], [8]], - [[9], [10], [11], [12]], - [[13], [14], [15], [16]] -]]> - -// Filter: 3x3x1x1 -memref.global "private" @conv_filter : memref<3x3x1x1xi8> = dense<[[ - [[1]], [[0]], [[0]], - [[0]], [[1]], [[0]], - [[0]], [[0]], [[1]] -]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - - %input = memref.get_global @conv_input : memref<1x4x4x1xi8> - %filter = memref.get_global @conv_filter : memref<3x3x1x1xi8> - %output = memref.alloc() : memref<1x2x2x1xi8> - - // Print input - // buckyball.print %input : memref<1x4x4x1xi8> - - // CHECK: tile_conv2d - tile.tile_conv2d %input %filter %output : memref<1x4x4x1xi8> memref<3x3x1x1xi8> memref<1x2x2x1xi8> - - memref.dealloc %output : memref<1x2x2x1xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir deleted file mode 100644 index 5d7975d6..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma1.mlir +++ /dev/null @@ -1,48 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: verify correctness of DMA module when facing 16-byte aligned addresses -// 1. Print input matrix -// 2. Print matrix at target address before move [CHECK1] print result should be all-zero matrix -// 3. Use mvin to move data from 16-byte aligned source address to scratchpad -// 4. Use mvout to move data from scratchpad to 16-byte aligned target address -// 5. Print matrix at target address after move [CHECK2] print result should be same as input matrix - -memref.global "private" @input_matrix_aligned : memref<4x16xi8> = dense<[[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15], - [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], - [32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47], - [48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - // Bank ID for data storage - %bankId = arith.constant 0 : i64 - %depth = arith.constant 4 : i64 - %stride = arith.constant 1 : i64 - - %arrayA = memref.get_global @input_matrix_aligned : memref<4x16xi8> - %arrayB = memref.alloc() {alignment = 16} : memref<4x16xi8> - - // Print input matrix - // Print target matrix before move [CHECK1] - buckyball.bb_print_memref %arrayA : memref<4x16xi8> - buckyball.bb_print_memref %arrayB : memref<4x16xi8> - - // Allocate bank 0 before mvin - buckyball.bb_mset %bankId : i64 - // Use mvin to move data from 16-byte aligned address to scratchpad - // CHECK: mvin - // Use mvout to move data from scratchpad to 16-byte aligned target address - buckyball.bb_mvin %arrayA %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 - // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 - - // Print output matrix after move [CHECK2] - buckyball.bb_print_memref %arrayB : memref<4x16xi8> - - // Release allocated memory - memref.dealloc %arrayB : memref<4x16xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir deleted file mode 100644 index ccbae12d..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma2.mlir +++ /dev/null @@ -1,69 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: verify correctness of DMA module's fast alternating read/write -// 1. Print input matrices A and B -// 2. Print matrix at target address before move [CHECK1] print result should be all-zero matrix -// 3. Execute fast alternating operations: use mvin to read row by row, mvout to write -// 4. Print matrix at target address after move [CHECK2] print result should show A and B contents swapped - -memref.global "private" @input_matrix_a : memref<2x16xi8> = dense<[[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15], - [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]]> - -memref.global "private" @input_matrix_b : memref<2x16xi8> = dense<[[100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115], - [116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 126, 125, 124, 123]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - // Bank IDs - %bankId0 = arith.constant 0 : i64 - %bankId1 = arith.constant 1 : i64 - %depth = arith.constant 2 : i64 - %stride = arith.constant 1 : i64 - - %arrayA = memref.get_global @input_matrix_a : memref<2x16xi8> - %arrayB = memref.get_global @input_matrix_b : memref<2x16xi8> - %arrayTemp = memref.alloc() {alignment = 16} : memref<2x16xi8> - - // Print input matrices A and B - buckyball.bb_print_memref %arrayA : memref<2x16xi8> - buckyball.bb_print_memref %arrayB : memref<2x16xi8> - // Print temporary matrix before move [CHECK1] - buckyball.bb_print_memref %arrayTemp : memref<2x16xi8> - - // Allocate banks before use - buckyball.bb_mset %bankId0 : i64 - buckyball.bb_mset %bankId1 : i64 - - // Fast alternating mvin/mvout operation sequence - // Step 1: A -> bank 0 - // CHECK: mvin - // Step 2: scratchpad 1 -> temp - buckyball.bb_mvin %arrayA %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 - // CHECK: mvout - buckyball.bb_mvout %arrayTemp %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 - - // Step 3: B -> bank 1 - // CHECK: mvin - // Step 4: bank 1 -> A - buckyball.bb_mvin %arrayB %bankId1 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 - // CHECK: mvout - buckyball.bb_mvout %arrayA %bankId1 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 - - // Step 5: temp -> bank 0 - // CHECK: mvin - // Step 6: bank 0 -> B - buckyball.bb_mvin %arrayTemp %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 - // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId0 %depth %stride : memref<2x16xi8> i64 i64 i64 i64 - - // Print swapped matrices [CHECK2] - buckyball.bb_print_memref %arrayA : memref<2x16xi8> - buckyball.bb_print_memref %arrayB : memref<2x16xi8> - - // Release allocated memory - memref.dealloc %arrayTemp : memref<2x16xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir b/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir deleted file mode 100644 index a98f5df9..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_dma3.mlir +++ /dev/null @@ -1,87 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: verify correctness of DMA module's long read/write operations -// 1. Dynamically generate large input matrix, repeatedly fill with data 0~127 -// 2. Print matrix at target address before move [CHECK1] print result should be all-zero matrix -// 3. Use mvin to read large amount of data from memory into scratchpad -// 4. Use mvout to write large amount of data from scratchpad to memory -// 5. Print matrix at target address after move [CHECK2] print result should be same as input matrix - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %c0 = arith.constant 0 : index - %c1 = arith.constant 1 : index - %c2 = arith.constant 2 : index - %c16 = arith.constant 16 : index - %c127 = arith.constant 127 : index - // Bank ID for storage - %bankId = arith.constant 0 : i64 - %depth = arith.constant 1023 : i64 - %stride = arith.constant 1 : i64 - - // ========== Row count configuration area (only modify here) ========== - // Total number of rows - %total_rows = arith.constant 1024 : index - // Last two rows start = total_rows - 2 - %last_rows_start = arith.constant 1022 : index - // %offset_elements = arith.constant 16336 : index // Offset = last_rows_start × 16 - // Offset = last_rows_start × 16 - %offset_elements = arith.constant 16352 : index - // ================================================ - - // Allocate large matrix - %arrayA = memref.alloc() {alignment = 16} : memref<1023x16xi8> - %arrayB = memref.alloc() {alignment = 16} : memref<1023x16xi8> - - // Use linalg.fill to initialize arrayB to 0 - linalg.fill ins(%0 : i8) outs(%arrayB : memref<1023x16xi8>) - - // Dynamically fill arrayA: repeatedly fill with 0~127 - scf.for %i = %c0 to %total_rows step %c1 { - scf.for %j = %c0 to %c16 step %c1 { - %row_offset = arith.muli %i, %c16 : index - %linear_idx = arith.addi %row_offset, %j : index - %mod_val = arith.remui %linear_idx, %c127 : index - %val = arith.index_cast %mod_val : index to i8 - memref.store %val, %arrayA[%i, %j] : memref<1023x16xi8> - } - } - - // Print first two rows and last two rows of input matrix - %arrayA_head = memref.subview %arrayA[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> - %arrayA_tail = memref.subview %arrayA[1021, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1], offset: 16336>> - buckyball.bb_print_memref %arrayA_head : memref<2x16xi8, strided<[16, 1]>> - buckyball.bb_print_memref %arrayA_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> - - // Print first two rows and last two rows of target matrix before move [CHECK1] - %arrayB_head = memref.subview %arrayB[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> - %arrayB_tail = memref.subview %arrayB[1021, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1], offset: 16336>> - buckyball.bb_print_memref %arrayB_head : memref<2x16xi8, strided<[16, 1]>> - buckyball.bb_print_memref %arrayB_tail : memref<2x16xi8, strided<[16, 1], offset: 16336>> - - // Allocate bank 0 before mvin - buckyball.bb_mset %bankId : i64 - - // Execute long read/write operations - // Step 1: long read - read large amount of data from memory into scratchpad - // CHECK: mvin - buckyball.bb_mvin %arrayA %bankId %depth %stride : memref<1023x16xi8> i64 i64 i64 i64 - - // Step 2: long write - write large amount of data from scratchpad to memory - // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId %depth %stride : memref<1023x16xi8> i64 i64 i64 i64 - - // Print first two rows and last two rows of output matrix after move [CHECK2] - %arrayB_head_after = memref.subview %arrayB[0, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1]>> - %arrayB_tail_after = memref.subview %arrayB[1021, 0] [2, 16] [1, 1] : memref<1023x16xi8> to memref<2x16xi8, strided<[16, 1], offset: 16336>> - buckyball.bb_print_memref %arrayB_head_after : memref<2x16xi8, strided<[16, 1]>> - buckyball.bb_print_memref %arrayB_tail_after : memref<2x16xi8, strided<[16, 1], offset: 16336>> - - // Release allocated memory - memref.dealloc %arrayA : memref<1023x16xi8> - memref.dealloc %arrayB : memref<1023x16xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir b/bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir deleted file mode 100644 index 940f48bb..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_im2col.mlir +++ /dev/null @@ -1,46 +0,0 @@ -// Test for bb_im2col: extract 3x3 patches from 4x16 input -// RUN: buddy-opt %s \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: verify correctness of im2col operation -// 1. Load input matrix (4x16) -// 2. Im2col with 3x3 kernel extracts patches into output matrix -// 3. Print output matrix to verify patch extraction - -// Input: 4x16 matrix -memref.global "private" @input : memref<4x16xi8> = dense<[ - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32], - [33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48], - [49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - - %arrayIn = memref.get_global @input : memref<4x16xi8> - // Output for im2col: 2 output rows, 3*3*1=9 patch cols (padded to 16) - %arrayOut = memref.alloc() : memref<2x16xi8> - - // Im2col parameters - %kRow = arith.constant 3 : i64 - %kCol = arith.constant 3 : i64 - %inRow = arith.constant 4 : i64 - %inCol = arith.constant 16 : i64 - %startRow = arith.constant 0 : i64 - %startCol = arith.constant 0 : i64 - - // Print input - buckyball.bb_print_memref %arrayIn : memref<4x16xi8> - - // CHECK: im2col - buckyball.bb_im2col %arrayIn %arrayOut %kRow %kCol %inRow %inCol %startRow %startCol - : memref<4x16xi8> memref<2x16xi8> - - // Print output - buckyball.bb_print_memref %arrayOut : memref<2x16xi8> - - memref.dealloc %arrayOut : memref<2x16xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir b/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir deleted file mode 100644 index ee72220a..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_mul_warp16.mlir +++ /dev/null @@ -1,55 +0,0 @@ -// Test for bb_matmul: 16x16 * 16x16 = 16x16 matrix multiplication -// Uses bb_matmul Op which lowers to mvin + mul_warp16 + mvout - -// Matrix A: 16x16 (identity-like matrix for easier verification) -memref.global "private" @matrix_a : memref<16x16xi8> = dense<[[1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [-1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [-1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [-1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0], - [-1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0], - [1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0], - [-1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0], - [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0], - [-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0], - [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0], - [-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0], - [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0], - [-1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1]]> - -// Matrix B: 16x16 (test matrix with simple pattern) -memref.global "private" @matrix_b : memref<16x16xi8> = dense<[[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]]> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - - %arrayA = memref.get_global @matrix_a : memref<16x16xi8> - %arrayB = memref.get_global @matrix_b : memref<16x16xi8> - %arrayC = memref.alloc() : memref<16x16xi8> - - // bb_matmul: lowers to mvin A + mvin B + mul_warp16 + mvout C - buckyball.bb_matmul %arrayA %arrayB %arrayC : memref<16x16xi8> memref<16x16xi8> memref<16x16xi8> - - // Print result matrix - buckyball.bb_print_memref %arrayC : memref<16x16xi8> - - memref.dealloc %arrayC : memref<16x16xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir b/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir deleted file mode 100644 index facf61ca..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_mvin_mvout.mlir +++ /dev/null @@ -1,40 +0,0 @@ -// RUN: buddy-opt %s \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: correctness of mvin and mvout instructions -// 1. Print input matrix -// 2. Print matrix at target address before move [CHECK] print result should be all-zero matrix -// 3. Use mvin to move data from memory to scratchpad -// 4. Use mvout to move data from scratchpad back to output memory -// 5. Print matrix at target address after move [CHECK] print result should be same as input matrix - -// Matrix B: 4x16 (test matrix with simple pattern) -memref.global "private" @input_matrix : memref<4x16xi8> = dense<[[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16], - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]]> - -func.func @main() -> i8 { - // === Main program === - %0 = arith.constant 0 : i8 - %bankId = arith.constant 0 : i64 - %depth = arith.constant 4 : i64 - %stride = arith.constant 1 : i64 - %arrayA = memref.get_global @input_matrix : memref<4x16xi8> - %arrayB = memref.alloc() : memref<4x16xi8> - // Allocate bank 0 before mvin - buckyball.bb_mset %bankId : i64 - // Use mvin to move data from memory to bank 0 - // CHECK: mvin - buckyball.bb_mvin %arrayA %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 - // Use mvout to move data from bank 0 back to output memory - // CHECK: mvout - buckyball.bb_mvout %arrayB %bankId %depth %stride : memref<4x16xi8> i64 i64 i64 i64 - // Print moved output matrix - buckyball.bb_print_memref %arrayB : memref<4x16xi8> - // Release allocated memory - memref.dealloc %arrayB : memref<4x16xi8> - return %0 : i8 -} diff --git a/bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir b/bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir deleted file mode 100644 index 81d81b7c..00000000 --- a/bb-tests/workloads/src/OpTest/toy/bb_quant_dequant.mlir +++ /dev/null @@ -1,51 +0,0 @@ -// Test for bb_quant and bb_dequant: quantize FP32 to INT8 then dequantize back -// RUN: buddy-opt %s \ -// RUN: -lower-buckyball | \ -// RUN: FileCheck %s - -// Spec: -// Purpose: verify quant -> matmul -> dequant pipeline -// 1. Quantize FP32 input to INT8 using scale factor -// 2. Perform matmul on quantized data -// 3. Dequantize result back to FP32 - -// FP32 input matrix A: 16x16 -memref.global "private" @fp_input_a : memref<16x16xf32> = dense<1.0> -// FP32 input matrix B: 16x16 -memref.global "private" @fp_input_b : memref<16x16xf32> = dense<2.0> - -func.func @main() -> i8 { - %0 = arith.constant 0 : i8 - %scale = arith.constant 0.1 : f32 - - // Load FP32 inputs - %fpA = memref.get_global @fp_input_a : memref<16x16xf32> - %fpB = memref.get_global @fp_input_b : memref<16x16xf32> - - // Allocate INT8 buffers for quantized data - %qA = memref.alloc() : memref<16x16xi8> - %qB = memref.alloc() : memref<16x16xi8> - - // Quantize A and B - // CHECK: quant - buckyball.bb_quant %fpA %qA %scale : memref<16x16xf32> memref<16x16xi8> f32 - buckyball.bb_quant %fpB %qB %scale : memref<16x16xf32> memref<16x16xi8> f32 - - // MatMul on quantized data - %qC = memref.alloc() : memref<16x16xi8> - buckyball.bb_matmul %qA %qB %qC : memref<16x16xi8> memref<16x16xi8> memref<16x16xi8> - - // Dequantize result - %fpC = memref.alloc() : memref<16x16xf32> - // CHECK: dequant - buckyball.bb_dequant %qC %fpC %scale : memref<16x16xi8> memref<16x16xf32> f32 - - // Print dequantized result - buckyball.bb_print_memref %fpC : memref<16x16xf32> - - memref.dealloc %qA : memref<16x16xi8> - memref.dealloc %qB : memref<16x16xi8> - memref.dealloc %qC : memref<16x16xi8> - memref.dealloc %fpC : memref<16x16xf32> - return %0 : i8 -} diff --git a/compiler b/compiler index 0fa1448a..26bc5292 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit 0fa1448ac9d10deb3b14ef5dffc46d8da1a8ed52 +Subproject commit 26bc5292f47d20b09771128bff6694454c3db5a8 From 35136a735c4549520064c8bf5947c941d1e22915 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 25 Mar 2026 03:53:29 +0800 Subject: [PATCH 189/238] [bebop] update: bump bebop [compiler] update: bump compiler --- bebop | 2 +- compiler | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bebop b/bebop index d72d4931..ec38f886 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit d72d49313be2b75268d0ac6d0249b7d3f92a4c03 +Subproject commit ec38f886fb7e9eec9f2715fb4eaeae52107e4c29 diff --git a/compiler b/compiler index 26bc5292..d5e80948 160000 --- a/compiler +++ b/compiler @@ -1 +1 @@ -Subproject commit 26bc5292f47d20b09771128bff6694454c3db5a8 +Subproject commit d5e809481d7ff2a5009101d5135df99e851a4f69 From 606b10a8551eb9c9142ed4def08d7170e3fa1e6e Mon Sep 17 00:00:00 2001 From: daiyongyuan <1533208939@qq.com> Date: Mon, 30 Mar 2026 14:35:44 +0800 Subject: [PATCH 190/238] feat(bebop): Add Spike and Verilator cosimulation module --- .../scala/sims/bebop/BebopCosimBlocks.scala | 39 +++++++++++++++++++ .../scala/sims/bebop/BebopSpikeCosimTop.scala | 24 ++++++++++++ .../bebop/EmitBebopSpikeCosimVerilog.scala | 16 ++++++++ bebop | 2 +- 4 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala create mode 100644 arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala create mode 100644 arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala diff --git a/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala b/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala new file mode 100644 index 00000000..61b86a45 --- /dev/null +++ b/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala @@ -0,0 +1,39 @@ +package sims.bebop + +import chisel3._ +import chisel3.util._ + +/** Per-`funct` hooks for Spike↔Verilator cosim. Keep literals in sync with `bebop/src/emu/inst/decode.rs`. */ +object BebopCosimBlocks { + + // FUNCT_* (7-bit RoCC custom field) + val F_MSET: UInt = 32.U(7.W) + val F_MVIN: UInt = 33.U(7.W) + val F_MVOUT: UInt = 16.U(7.W) + val F_FENCE: UInt = 0.U(7.W) + + /** Mirrors `decode::execute_known` inner `u64` return (`ret` before iss maps rd). */ + def execRet(funct: UInt, xs1: UInt, xs2: UInt): UInt = { + val _ = (xs1, xs2) + MuxLookup( + funct, + 0.U(64.W), + )( + Seq( + F_FENCE -> 0.U(64.W), + F_MSET -> 0.U(64.W), + F_MVIN -> 0.U(64.W), + F_MVOUT -> 0.U(64.W), + 48.U(7.W) -> 0.U(64.W), // FUNCT_IM2COL + 49.U(7.W) -> 0.U(64.W), // FUNCT_TRANSPOSE + 64.U(7.W) -> 0.U(64.W), // FUNCT_MUL_WARP16 + ), + ) + } + + /** Optional observable for bank difftest; 0 = not implemented. Wire Ball SRAM hash later. */ + def bankDigestPeek(funct: UInt, xs1: UInt, xs2: UInt): UInt = { + val _ = (funct, xs1, xs2) + 0.U(64.W) + } +} diff --git a/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala b/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala new file mode 100644 index 00000000..9c98b7cc --- /dev/null +++ b/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala @@ -0,0 +1,24 @@ +package sims.bebop + +import chisel3._ +import chisel3.util.Cat + +/** Verilator cosim top: RoCC insn → rd + optional `bankDigestPeek` for future BEMU bank hash compare. + * + * `execRet` comes from [[BebopCosimBlocks.execRet]] (per-funct). rd rule matches + * `bebop/src/emu/iss/iss.rs`: `rd = if v == 0 { funct } else { 0 }`. + */ +class BebopSpikeCosimTop extends RawModule { + val funct = IO(Input(UInt(7.W))) + val xs1 = IO(Input(UInt(64.W))) + val xs2 = IO(Input(UInt(64.W))) + + val result = IO(Output(UInt(64.W))) + + /** 0 until Ball exposes a 64-bit digest; then compare in bebop `vl_worker` when enabled. */ + val bankDigestPeek = IO(Output(UInt(64.W))) + + val execRet = BebopCosimBlocks.execRet(funct, xs1, xs2) + result := Mux(execRet === 0.U, Cat(0.U(57.W), funct), 0.U(64.W)) + bankDigestPeek := BebopCosimBlocks.bankDigestPeek(funct, xs1, xs2) +} diff --git a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala new file mode 100644 index 00000000..7c87cce4 --- /dev/null +++ b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala @@ -0,0 +1,16 @@ +package sims.bebop + +import _root_.circt.stage.ChiselStage + +/** `mill buckyball.runMain sims.bebop.EmitBebopSpikeCosimVerilog ` */ +object EmitBebopSpikeCosimVerilog { + def main(args: Array[String]): Unit = { + val dir = if (args.nonEmpty) args(0) else "gen-bebop-cosim" + ChiselStage.emitSystemVerilogFile( + new BebopSpikeCosimTop, + firtoolOpts = Array.empty, + args = Array("-td", dir), + ) + println(s"EmitBebopSpikeCosimVerilog: wrote under $dir") + } +} diff --git a/bebop b/bebop index ec38f886..61b95ad4 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit ec38f886fb7e9eec9f2715fb4eaeae52107e4c29 +Subproject commit 61b95ad4d25811ab656f58c472cdac8d2108c96b From 24c29714d89df2649be12785c3ed16eee62d6dbc Mon Sep 17 00:00:00 2001 From: daiyongyuan <1533208939@qq.com> Date: Mon, 30 Mar 2026 17:17:03 +0800 Subject: [PATCH 191/238] feat(bebop): feat: add vector computation support and enhance bebop_accel functionality --- .../scala/sims/bebop/BebopCosimBlocks.scala | 125 ++++++++++++++++-- .../scala/sims/bebop/BebopSpikeCosimTop.scala | 3 +- .../bebop/EmitBebopSpikeCosimVerilog.scala | 5 + .../main/scala/sims/bebop/VecComputeTop.scala | 64 +++++++++ bebop | 2 +- 5 files changed, 187 insertions(+), 12 deletions(-) create mode 100644 arch/src/main/scala/sims/bebop/VecComputeTop.scala diff --git a/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala b/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala index 61b86a45..531ba63b 100644 --- a/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala +++ b/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala @@ -7,10 +7,85 @@ import chisel3.util._ object BebopCosimBlocks { // FUNCT_* (7-bit RoCC custom field) - val F_MSET: UInt = 32.U(7.W) - val F_MVIN: UInt = 33.U(7.W) - val F_MVOUT: UInt = 16.U(7.W) val F_FENCE: UInt = 0.U(7.W) + val F_BARRIER: UInt = 1.U(7.W) + val F_GEMMINI_CONFIG: UInt = 2.U(7.W) + val F_GEMMINI_FLUSH: UInt = 3.U(7.W) + val F_BDB_COUNTER: UInt = 4.U(7.W) + val F_MVOUT: UInt = 16.U(7.W) + val F_MSET: UInt = 32.U(7.W) + val F_MVIN: UInt = 33.U(7.W) + val F_IM2COL: UInt = 48.U(7.W) + val F_TRANSPOSE: UInt = 49.U(7.W) + val F_RELU: UInt = 50.U(7.W) + val F_QUANT: UInt = 51.U(7.W) + val F_DEQUANT: UInt = 52.U(7.W) + val F_GEMMINI_PRELOAD: UInt = 53.U(7.W) + val F_BDB_BACKDOOR: UInt = 54.U(7.W) + val F_MUL_WARP16: UInt = 64.U(7.W) + val F_BFP: UInt = 65.U(7.W) + val F_GEMMINI_COMPUTE_PRELOADED: UInt = 66.U(7.W) + val F_GEMMINI_COMPUTE_ACCUMULATED: UInt = 67.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_BOUNDS: UInt = 80.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_A: UInt = 81.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_B: UInt = 82.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_D: UInt = 83.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_C: UInt = 84.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB: UInt = 85.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC: UInt = 86.U(7.W) + val F_GEMMINI_LOOP_WS: UInt = 87.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_1: UInt = 96.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_2: UInt = 97.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_3: UInt = 98.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_4: UInt = 99.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_5: UInt = 100.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_6: UInt = 101.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_7: UInt = 102.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_8: UInt = 103.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_9: UInt = 104.U(7.W) + val F_GEMMINI_LOOP_CONV_WS: UInt = 105.U(7.W) + + val knownFuncts: Seq[UInt] = Seq( + F_FENCE, + F_BARRIER, + F_GEMMINI_CONFIG, + F_GEMMINI_FLUSH, + F_BDB_COUNTER, + F_MVOUT, + F_MSET, + F_MVIN, + F_IM2COL, + F_TRANSPOSE, + F_RELU, + F_QUANT, + F_DEQUANT, + F_GEMMINI_PRELOAD, + F_BDB_BACKDOOR, + F_MUL_WARP16, + F_BFP, + F_GEMMINI_COMPUTE_PRELOADED, + F_GEMMINI_COMPUTE_ACCUMULATED, + F_GEMMINI_LOOP_WS_CONFIG_BOUNDS, + F_GEMMINI_LOOP_WS_CONFIG_ADDR_A, + F_GEMMINI_LOOP_WS_CONFIG_ADDR_B, + F_GEMMINI_LOOP_WS_CONFIG_ADDR_D, + F_GEMMINI_LOOP_WS_CONFIG_ADDR_C, + F_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB, + F_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC, + F_GEMMINI_LOOP_WS, + F_GEMMINI_LOOP_CONV_WS_CONFIG_1, + F_GEMMINI_LOOP_CONV_WS_CONFIG_2, + F_GEMMINI_LOOP_CONV_WS_CONFIG_3, + F_GEMMINI_LOOP_CONV_WS_CONFIG_4, + F_GEMMINI_LOOP_CONV_WS_CONFIG_5, + F_GEMMINI_LOOP_CONV_WS_CONFIG_6, + F_GEMMINI_LOOP_CONV_WS_CONFIG_7, + F_GEMMINI_LOOP_CONV_WS_CONFIG_8, + F_GEMMINI_LOOP_CONV_WS_CONFIG_9, + F_GEMMINI_LOOP_CONV_WS, + ) + + def isKnownFunct(funct: UInt): Bool = knownFuncts.map(_ === funct).reduce(_ || _) /** Mirrors `decode::execute_known` inner `u64` return (`ret` before iss maps rd). */ def execRet(funct: UInt, xs1: UInt, xs2: UInt): UInt = { @@ -20,13 +95,43 @@ object BebopCosimBlocks { 0.U(64.W), )( Seq( - F_FENCE -> 0.U(64.W), - F_MSET -> 0.U(64.W), - F_MVIN -> 0.U(64.W), - F_MVOUT -> 0.U(64.W), - 48.U(7.W) -> 0.U(64.W), // FUNCT_IM2COL - 49.U(7.W) -> 0.U(64.W), // FUNCT_TRANSPOSE - 64.U(7.W) -> 0.U(64.W), // FUNCT_MUL_WARP16 + F_FENCE -> 0.U(64.W), + F_BARRIER -> 0.U(64.W), + F_GEMMINI_CONFIG -> 0.U(64.W), + F_GEMMINI_FLUSH -> 0.U(64.W), + F_BDB_COUNTER -> 0.U(64.W), + F_MVOUT -> 0.U(64.W), + F_MSET -> 0.U(64.W), + F_MVIN -> 0.U(64.W), + F_IM2COL -> 0.U(64.W), + F_TRANSPOSE -> 0.U(64.W), + F_RELU -> 0.U(64.W), + F_QUANT -> 0.U(64.W), + F_DEQUANT -> 0.U(64.W), + F_GEMMINI_PRELOAD -> 0.U(64.W), + F_BDB_BACKDOOR -> 0.U(64.W), + F_MUL_WARP16 -> 0.U(64.W), + F_BFP -> 0.U(64.W), + F_GEMMINI_COMPUTE_PRELOADED -> 0.U(64.W), + F_GEMMINI_COMPUTE_ACCUMULATED -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_BOUNDS -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_A -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_B -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_D -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_C -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC -> 0.U(64.W), + F_GEMMINI_LOOP_WS -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_1 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_2 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_3 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_4 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_5 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_6 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_7 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_8 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_9 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS -> 0.U(64.W), ), ) } diff --git a/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala b/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala index 9c98b7cc..dd631759 100644 --- a/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala +++ b/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala @@ -19,6 +19,7 @@ class BebopSpikeCosimTop extends RawModule { val bankDigestPeek = IO(Output(UInt(64.W))) val execRet = BebopCosimBlocks.execRet(funct, xs1, xs2) - result := Mux(execRet === 0.U, Cat(0.U(57.W), funct), 0.U(64.W)) + val known = BebopCosimBlocks.isKnownFunct(funct) + result := Mux(known && execRet === 0.U, Cat(0.U(57.W), funct), 0.U(64.W)) bankDigestPeek := BebopCosimBlocks.bankDigestPeek(funct, xs1, xs2) } diff --git a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala index 7c87cce4..1edb83e4 100644 --- a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala +++ b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala @@ -11,6 +11,11 @@ object EmitBebopSpikeCosimVerilog { firtoolOpts = Array.empty, args = Array("-td", dir), ) + ChiselStage.emitSystemVerilogFile( + new VecComputeTop, + firtoolOpts = Array.empty, + args = Array("-td", dir), + ) println(s"EmitBebopSpikeCosimVerilog: wrote under $dir") } } diff --git a/arch/src/main/scala/sims/bebop/VecComputeTop.scala b/arch/src/main/scala/sims/bebop/VecComputeTop.scala new file mode 100644 index 00000000..20f8f83c --- /dev/null +++ b/arch/src/main/scala/sims/bebop/VecComputeTop.scala @@ -0,0 +1,64 @@ +package sims.bebop + +import chisel3._ +import chisel3.util._ +import framework.balldomain.prototype.vector.configs.VectorBallParam +import framework.balldomain.prototype.vector.op.MulOp + +class VecComputeTop extends Module { + private val cfg = VectorBallParam() + require(cfg.lane == 16, s"VecComputeTop requires lane=16, got ${cfg.lane}") + require(cfg.inputWidth == 8, s"VecComputeTop requires inputWidth=8, got ${cfg.inputWidth}") + require(cfg.outputWidth == 32, s"VecComputeTop requires outputWidth=32, got ${cfg.outputWidth}") + + val io = IO(new Bundle { + val start = Input(Bool()) + val iter = Input(UInt(16.W)) + val op1 = Input(Vec(16, UInt(8.W))) + val op2 = Input(Vec(16, UInt(8.W))) + val res = Output(Vec(16, UInt(32.W))) + val valid = Output(Bool()) + val done = Output(Bool()) + }) + + val mul = Module(new MulOp(cfg)) + + val op1Reg = Reg(Vec(16, UInt(8.W))) + val op2Reg = Reg(Vec(16, UInt(8.W))) + val inFire = RegInit(false.B) + + val rowCnt = RegInit(0.U(4.W)) + val active = RegInit(false.B) + val doneR = RegInit(false.B) + + when(io.start) { + assert(io.iter =/= 0.U, "VecComputeTop: iter must be non-zero") + op1Reg := io.op1 + op2Reg := io.op2 + inFire := true.B + rowCnt := 0.U + active := true.B + doneR := false.B + }.otherwise { + inFire := false.B + when(active && mul.io.out.valid) { + when(rowCnt === 15.U) { + active := false.B + doneR := true.B + }.otherwise { + rowCnt := rowCnt + 1.U + } + }.elsewhen(doneR) { + doneR := false.B + } + } + + mul.io.in.valid := inFire + mul.io.in.bits.in1 := op1Reg + mul.io.in.bits.in2 := op2Reg + mul.io.out.ready := true.B + + io.res := mul.io.out.bits.out + io.valid := active && mul.io.out.valid + io.done := doneR +} diff --git a/bebop b/bebop index 61b95ad4..8c4414a4 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 61b95ad4d25811ab656f58c472cdac8d2108c96b +Subproject commit 8c4414a474d67962b135b952bd4dc650d543b398 From 31a85a0a8b72154daefac09cfe3b81bb62c5d1d3 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 31 Mar 2026 23:23:26 +0800 Subject: [PATCH 192/238] fix: add necessary tools (cmake, java, dtc, spike) to build environment --- bebop | 2 +- flake.nix | 4 ++++ scripts/nix/build-env-tools.nix | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/bebop b/bebop index 8c4414a4..fab484da 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 8c4414a474d67962b135b952bd4dc650d543b398 +Subproject commit fab484da78a44b15bf0b3f723e103f02c5d1f876 diff --git a/flake.nix b/flake.nix index 6332fda7..a3c2703f 100644 --- a/flake.nix +++ b/flake.nix @@ -24,6 +24,10 @@ tools.dramsim2 tools.ccache tools.lld + tools.cmake + tools.java + tools.dtc + tools.spike tools.yosys tools.opensta tools.lcov diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index f54d01fe..07edb2d0 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -83,6 +83,10 @@ in # Build acceleration tools ccache = pkgs.ccache; lld = pkgs.lld; + cmake = pkgs.cmake; + java = pkgs.jdk; + dtc = pkgs.dtc; + spike = pkgs.spike; # Synthesis tools yosys = pkgs.yosys; From 3d36720c336b226462929534c069d71ad5925ef1 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 1 Apr 2026 00:16:29 +0800 Subject: [PATCH 193/238] feat: add Edein submodule and update bebop reference --- .gitmodules | 3 +++ bebop | 2 +- thirdparty/edein | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) create mode 160000 thirdparty/edein diff --git a/.gitmodules b/.gitmodules index 48ff281c..8c0ac899 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,3 +26,6 @@ path = bebop url = https://github.com/DangoSys/bebop branch = next +[submodule "thirdparty/edein"] + path = thirdparty/edein + url = https://github.com/DangoSys/Edein.git diff --git a/bebop b/bebop index fab484da..9c47331f 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit fab484da78a44b15bf0b3f723e103f02c5d1f876 +Subproject commit 9c47331f6da8b52bc85c76aaded49edc5ecfaad1 diff --git a/thirdparty/edein b/thirdparty/edein new file mode 160000 index 00000000..a5445031 --- /dev/null +++ b/thirdparty/edein @@ -0,0 +1 @@ +Subproject commit a5445031ba0067a7cbbac43a36f9429536acdf28 From 30f2af0f39d01cf927dbe96822da5fdc22202507 Mon Sep 17 00:00:00 2001 From: daiyongyuan <1533208939@qq.com> Date: Wed, 1 Apr 2026 00:16:44 +0800 Subject: [PATCH 194/238] feat(bebop): addBebopBuckyballSubsystemCosim for Spike-Verilator --- .../bebop/BebopBuckyballSubsystemCosim.scala | 193 ++++++++++++++++++ .../bebop/EmitBebopSpikeCosimVerilog.scala | 13 +- .../main/scala/sims/bebop/VecComputeTop.scala | 4 +- bebop | 2 +- 4 files changed, 209 insertions(+), 3 deletions(-) create mode 100644 arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala diff --git a/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala b/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala new file mode 100644 index 00000000..5bf59800 --- /dev/null +++ b/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala @@ -0,0 +1,193 @@ +package sims.bebop + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.diplomacy.{AddressSet, IdRange} +import freechips.rocketchip.devices.tilelink.TLTestRAM +import freechips.rocketchip.rocket.{HStatus, MStatus} +import freechips.rocketchip.tilelink._ + +import framework.core.bbtile.{BarrierUnit, BuckyballAccelerator, RoCCCommandBB} +import framework.memdomain.backend.shared.SharedMemBackend +import framework.top.GlobalConfig + +object BebopBuckyballSubsystemCosim { + val custom3Opcode: UInt = 0x7b.U(7.W) + + def roccCmd(funct: UInt, xs1: UInt, xs2: UInt, xLen: Int): RoCCCommandBB = { + val cmd = Wire(new RoCCCommandBB(xLen)) + val f7 = funct(6, 0) + cmd.raw_inst := Cat(f7, 0.U(5.W), 0.U(5.W), 3.U(3.W), 0.U(5.W), custom3Opcode) + cmd.pc := 0.U(xLen.W) + cmd.funct := funct + cmd.funct3 := 3.U + cmd.rs2 := 0.U + cmd.rs1 := 0.U + cmd.xd := true.B + cmd.xs1 := true.B + cmd.xs2 := true.B + cmd.rd := 0.U + cmd.opcode := custom3Opcode + cmd.rs1Data := xs1 + cmd.rs2Data := xs2 + cmd + } +} + +/** Full toy-config accelerator (Frontend + 9 balls + MemDomain + GpDomain) for Spike–Verilator cosim. */ +class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { + + val b: GlobalConfig = GlobalConfig() + + val beatBytes = b.memDomain.dma_buswidth / 8 + val ramMask = (BigInt(1) << b.memDomain.memAddrLen) - 1 + require((ramMask & (beatBytes - 1)) == beatBytes - 1, "TLTestRAM mask must align to dma beatBytes") + + val readerNode = TLClientNode( + Seq( + TLMasterPortParameters.v1( + Seq( + TLClientParameters( + name = "bebop-cosim-reader", + sourceId = IdRange(0, b.memDomain.dma_n_xacts), + ), + ), + ), + ), + ) + + val writerNode = TLClientNode( + Seq( + TLMasterPortParameters.v1( + Seq( + TLClientParameters( + name = "bebop-cosim-writer", + sourceId = IdRange(0, b.memDomain.dma_n_xacts), + ), + ), + ), + ), + ) + + val xbar = TLXbar() + val ram = LazyModule(new TLTestRAM(AddressSet(0x0, ramMask), beatBytes = beatBytes)) + + ram.node := xbar + xbar := TLBuffer() := readerNode + xbar := TLBuffer() := writerNode + + lazy val module = new LazyModuleImp(this) { + override def desiredName: String = "BebopBuckyballSubsystemCosim" + + val start = IO(Input(Bool())) + val funct = IO(Input(UInt(7.W))) + val xs1 = IO(Input(UInt(64.W))) + val xs2 = IO(Input(UInt(64.W))) + + val done = IO(Output(Bool())) + val result = IO(Output(UInt(64.W))) + + val (tlReader, edge) = readerNode.out(0) + val (tlWriter, _) = writerNode.out(0) + + val acc = Module(new BuckyballAccelerator(b)(edge)) + acc.io.tl_reader <> tlReader + acc.io.tl_writer <> tlWriter + + acc.io.sfence := false.B + acc.io.hartid := 0.U(b.core.xLen.W) + + acc.io.ptw(0).req.ready := true.B + acc.io.ptw(0).resp.valid := false.B + acc.io.ptw(0).resp.bits := 0.U.asTypeOf(acc.io.ptw(0).resp.bits) + acc.io.ptw(0).ptbr.mode := 0.U + acc.io.ptw(0).ptbr.asid := 0.U + acc.io.ptw(0).ptbr.ppn := 0.U + acc.io.ptw(0).hgatp.mode := 0.U + acc.io.ptw(0).hgatp.asid := 0.U + acc.io.ptw(0).hgatp.ppn := 0.U + acc.io.ptw(0).vsatp.mode := 0.U + acc.io.ptw(0).vsatp.asid := 0.U + acc.io.ptw(0).vsatp.ppn := 0.U + acc.io.ptw(0).status := 0.U.asTypeOf(new MStatus()) + acc.io.ptw(0).hstatus := 0.U.asTypeOf(new HStatus()) + acc.io.ptw(0).gstatus := 0.U.asTypeOf(new MStatus()) + for (i <- 0 until b.core.nPMPs) { + acc.io.ptw(0).pmp(i).cfg.l := false.B + acc.io.ptw(0).pmp(i).cfg.res := 0.U + acc.io.ptw(0).pmp(i).cfg.a := 0.U + acc.io.ptw(0).pmp(i).cfg.x := false.B + acc.io.ptw(0).pmp(i).cfg.w := false.B + acc.io.ptw(0).pmp(i).cfg.r := false.B + acc.io.ptw(0).pmp(i).addr := 0.U + acc.io.ptw(0).pmp(i).mask := 0.U + } + + val shared = Module(new SharedMemBackend(b)) + for (ch <- 0 until b.memDomain.bankChannel) { + shared.io.mem_req(ch) <> acc.io.shared_mem_req(ch) + } + shared.io.config <> acc.io.shared_config + shared.io.query_vbank_id := acc.io.shared_query_vbank_id + acc.io.shared_query_group_count := shared.io.query_group_count + + val barrier = Module(new BarrierUnit(1)) + barrier.io.arrive(0) := acc.io.barrier_arrive + acc.io.barrier_release := barrier.io.release(0) + + acc.io.tlbExp(0).flush_skip := false.B + acc.io.tlbExp(0).flush_retry := false.B + + val sIdle :: sCmd :: sWait :: sDone :: Nil = Enum(4) + val state = RegInit(sIdle) + + val cmdReg = Reg(new RoCCCommandBB(b.core.xLen)) + val resReg = RegInit(0.U(64.W)) + + done := state === sDone + result := resReg + + acc.io.cmd.valid := state === sCmd + acc.io.cmd.bits := cmdReg + acc.io.resp.ready := state === sWait + + val waitCycles = RegInit(0.U(24.W)) + when(state === sWait) { + waitCycles := waitCycles + 1.U + }.otherwise { + waitCycles := 0.U + } + assert(waitCycles < (1 << 23).U, "BebopBuckyballSubsystemCosim: RoCC wait timeout") + + switch(state) { + is(sIdle) { + when(start) { + cmdReg := BebopBuckyballSubsystemCosim.roccCmd(funct, xs1, xs2, b.core.xLen) + state := sCmd + } + } + is(sCmd) { + when(acc.io.cmd.fire) { + state := sWait + } + } + is(sWait) { + when(acc.io.resp.fire) { + resReg := acc.io.resp.bits.data.asUInt + state := sDone + }.elsewhen(!acc.io.busy) { + resReg := Cat(0.U(57.W), cmdReg.funct) + state := sDone + } + } + is(sDone) { + when(!start) { + state := sIdle + } + } + } + } +} diff --git a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala index 1edb83e4..5aeb0fbf 100644 --- a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala +++ b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala @@ -1,16 +1,27 @@ package sims.bebop import _root_.circt.stage.ChiselStage +import org.chipsalliance.cde.config.Parameters +import org.chipsalliance.diplomacy.lazymodule.LazyModule /** `mill buckyball.runMain sims.bebop.EmitBebopSpikeCosimVerilog ` */ object EmitBebopSpikeCosimVerilog { def main(args: Array[String]): Unit = { val dir = if (args.nonEmpty) args(0) else "gen-bebop-cosim" + implicit val p: Parameters = org.chipsalliance.cde.config.Parameters.empty + val bbCosim = LazyModule(new BebopBuckyballSubsystemCosim()(p)) ChiselStage.emitSystemVerilogFile( - new BebopSpikeCosimTop, + bbCosim.module, firtoolOpts = Array.empty, args = Array("-td", dir), ) + val bbPath = java.nio.file.Paths.get(dir, "BebopBuckyballSubsystemCosim.sv") + val bbText = java.nio.file.Files.readString(bbPath) + val marker = "// ----- 8< ----- FILE \"firrtl_black_box_resource_files.f\"" + val cut = bbText.indexOf(marker) + if (cut >= 0) { + java.nio.file.Files.writeString(bbPath, bbText.substring(0, cut)) + } ChiselStage.emitSystemVerilogFile( new VecComputeTop, firtoolOpts = Array.empty, diff --git a/arch/src/main/scala/sims/bebop/VecComputeTop.scala b/arch/src/main/scala/sims/bebop/VecComputeTop.scala index 20f8f83c..9a0f4149 100644 --- a/arch/src/main/scala/sims/bebop/VecComputeTop.scala +++ b/arch/src/main/scala/sims/bebop/VecComputeTop.scala @@ -21,7 +21,9 @@ class VecComputeTop extends Module { val done = Output(Bool()) }) - val mul = Module(new MulOp(cfg)) + val mul = Module(new MulOp(cfg) { + override def desiredName = "MulOpVecComputeTop" + }) val op1Reg = Reg(Vec(16, UInt(8.W))) val op2Reg = Reg(Vec(16, UInt(8.W))) diff --git a/bebop b/bebop index 8c4414a4..fab484da 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 8c4414a474d67962b135b952bd4dc650d543b398 +Subproject commit fab484da78a44b15bf0b3f723e103f02c5d1f876 From 4f6ba3433484864f9dcc0988e25fbf8190113756 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 3 Apr 2026 00:42:00 +0800 Subject: [PATCH 195/238] [bbdev] update: new bbdev with iii [docs] fix: fix bugs in docs and edein --- bb-tests/sardine/tests/test_ctest.py | 2 +- bb-tests/sardine/tests/test_mlir.py | 5 +++-- bbdev | 2 +- docs | 2 +- flake.nix | 3 +-- scripts/nix/build-all.sh | 10 +++------ scripts/nix/build-env-bbdev.nix | 32 ++++++++++++++++++++++++---- thirdparty/edein | 2 +- 8 files changed, 39 insertions(+), 19 deletions(-) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 1814b48b..1470713f 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -121,7 +121,7 @@ def test_ctest_workload_debug( ): caplog.set_level(logging.INFO) - time.sleep(test_index * 15) + time.sleep(test_index * 5) start_time = time.time() coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' diff --git a/bb-tests/sardine/tests/test_mlir.py b/bb-tests/sardine/tests/test_mlir.py index b9d273aa..bf18cd66 100644 --- a/bb-tests/sardine/tests/test_mlir.py +++ b/bb-tests/sardine/tests/test_mlir.py @@ -43,7 +43,8 @@ def test_mlir_optest(command_run, caplog, workload_path, workload_id, test_index): caplog.set_level(logging.INFO) - time.sleep(test_index * 20) + # no longer needed: bbdev uses dynamic port allocation + time.sleep(test_index * 5) start_time = time.time() coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' @@ -87,7 +88,7 @@ def test_mlir_optest(command_run, caplog, workload_path, workload_id, test_index def test_mlir_tile_optest(command_run, caplog, workload_path, workload_id, test_index): caplog.set_level(logging.INFO) - time.sleep(test_index * 20) + time.sleep(test_index * 5) start_time = time.time() coverage_flag = " --coverage" if os.environ.get("SARDINE_COVERAGE") else "" command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' diff --git a/bbdev b/bbdev index 8fae4219..b5cc63c8 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 8fae421972381c16fb66ab82192102245541a3f9 +Subproject commit b5cc63c8de7953984a7969c278f175c90a1d2b37 diff --git a/docs b/docs index 597d0cd9..1f006478 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 597d0cd91dbbfc9e9de338ae00f7e7384ae925a9 +Subproject commit 1f00647846612b9bb92d6f9eda31050b34aa82fd diff --git a/flake.nix b/flake.nix index a3c2703f..3ede8364 100644 --- a/flake.nix +++ b/flake.nix @@ -48,8 +48,7 @@ rustTools.clippy # bbdev dependencies - bbdev.nodejs - bbdev.pnpm + bbdev.iii bbdev.uv bbdev.allure bbdev.gcc diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 41995485..d5045376 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -93,14 +93,10 @@ fi if run_step "1"; then begin_step "1" "bbdev install" - # Create python_modules venv FIRST (uses Nix Python with pydantic/requests) - # Motia postinstall would run pip install -> SOCKS proxy fails. Use Nix instead. - echo "Setting up bbdev Python environment (from Nix)..." - python3 -m venv --without-pip --system-site-packages "${BBDIR}/bbdev/api/python_modules" - - echo "Installing bbdev node dependencies..." + echo "Installing bbdev Python dependencies..." cd ${BBDIR}/bbdev/api - pnpm install --ignore-scripts --frozen-lockfile 2>/dev/null + uv venv .venv --python python3 --seed + uv pip install --python .venv/bin/python -r pyproject.toml fi if run_step "2"; then diff --git a/scripts/nix/build-env-bbdev.nix b/scripts/nix/build-env-bbdev.nix index f38471e8..419fbacd 100644 --- a/scripts/nix/build-env-bbdev.nix +++ b/scripts/nix/build-env-bbdev.nix @@ -1,11 +1,35 @@ { pkgs }: +let + iiiVersion = "0.10.0"; + iiiBinary = pkgs.stdenv.mkDerivation { + pname = "iii"; + version = iiiVersion; + + src = pkgs.fetchurl { + url = "https://github.com/iii-hq/iii/releases/download/iii/v${iiiVersion}/iii-x86_64-unknown-linux-gnu.tar.gz"; + sha256 = "sha256-XMSqKQKHL4XCQTw5r9BNbdcPS4c6HZkg4GW0XXVKg00="; + }; + + nativeBuildInputs = [ pkgs.autoPatchelfHook ]; + buildInputs = [ pkgs.stdenv.cc.cc.lib ]; + + unpackPhase = '' + tar xzf $src + ''; + + installPhase = '' + mkdir -p $out/bin + cp iii $out/bin/iii + chmod +x $out/bin/iii + ''; + }; +in { - # Node.js environment (for bbdev Motia backend) - nodejs = pkgs.nodejs_22; - pnpm = pkgs.nodePackages.pnpm; + # iii engine binary + iii = iiiBinary; - # UV (motia install uses it for Python deps; avoid auto-install via broken pip) + # UV (for creating .venv and installing motia + deps) uv = pkgs.uv; # Allure CLI for sardine Allure reports allure = pkgs.allure; diff --git a/thirdparty/edein b/thirdparty/edein index a5445031..60bab4c9 160000 --- a/thirdparty/edein +++ b/thirdparty/edein @@ -1 +1 @@ -Subproject commit a5445031ba0067a7cbbac43a36f9429536acdf28 +Subproject commit 60bab4c9cc216a4be50c0bcedc9869cacdb59059 From bd4887ab9bf7a76ad70365b59232dc3c86e9f47c Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sun, 5 Apr 2026 21:27:06 +0800 Subject: [PATCH 196/238] [arch/gemminiball] refactor: align gemminiball config with original gemmini --- .../prototype/gemmini/GemminiExCtrlDefs.scala | 16 +- .../gemmini/GemminiExCtrlStoreOps.scala | 6 +- .../gemmini/configs/GemminiBallParam.scala | 17 +- .../prototype/gemmini/configs/default.json | 3 +- .../bebop/BebopBuckyballSubsystemCosim.scala | 103 ++++---- .../scala/sims/bebop/BebopCosimBlocks.scala | 147 ++++++------ .../scala/sims/bebop/BebopSpikeCosimTop.scala | 7 +- .../bebop/EmitBebopSpikeCosimVerilog.scala | 14 +- .../main/scala/sims/bebop/VecComputeTop.scala | 8 +- .../scala/sims/pegasus/PegasusHarness.scala | 225 ++++++++---------- .../sims/pegasus/PegasusHarnessBinders.scala | 145 ++++++----- .../scala/sims/pegasus/TargetConfigs.scala | 66 ++--- 12 files changed, 376 insertions(+), 381 deletions(-) diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala index a10cdfaa..4b544685 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlDefs.scala @@ -20,9 +20,9 @@ trait GemminiExCtrlDefs { this: GemminiExCtrl => val inBW = ballMapping.inBW val outBW = ballMapping.outBW - val inputType = SInt(config.inputWidth.W) - val accType = SInt(config.accWidth.W) - val outputType = SInt(config.accWidth.W) + val inputType = SInt(config.inputWidth.W) + val accType = SInt(config.accWidth.W) + val meshOutputType = SInt(config.spatialOutputWidth.W) val ctrlIo = IO(new Bundle { val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) @@ -40,7 +40,7 @@ trait GemminiExCtrlDefs { this: GemminiExCtrl => val mesh = Module(new MeshWithDelays( inputType = inputType, - outputType = outputType, + outputType = meshOutputType, accType = accType, tagType = new SimpleTag, df = Dataflow.BOTH, @@ -52,10 +52,12 @@ trait GemminiExCtrlDefs { this: GemminiExCtrl => meshRows = config.meshRows, meshColumns = config.meshColumns, leftBanks = 1, - upBanks = 1, - n_simultaneous_matmuls = 5 + upBanks = 1 )) + protected def widenMeshToAcc(src: Vec[Vec[SInt]]): Vec[Vec[SInt]] = + VecInit(src.map(col => VecInit(col.map(_.asTypeOf(accType))))) + val cfg_dataflow = RegInit(0.U(1.W)) val cfg_in_shift = RegInit(0.U(log2Up(config.accWidth).W)) val cfg_a_transpose = RegInit(false.B) @@ -95,7 +97,7 @@ trait GemminiExCtrlDefs { this: GemminiExCtrl => rdQueue0.io.enq <> io.bankReadResp(0) rdQueue1.io.enq <> io.bankReadResp(1) - val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, outputType)))) + val outBuf = Reg(Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, accType)))) val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) val outBufCollected = RegInit(0.U(log2Up(DIM + 1).W)) diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala index 38dfcb80..79521a9f 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/GemminiExCtrlStoreOps.scala @@ -9,7 +9,7 @@ trait GemminiExCtrlStoreOps { this: GemminiExCtrl => protected def handleComputeFlushState(): Unit = { when(mesh.io.resp.fire && mesh.io.resp.bits.total_rows === total_rows) { when(outBufCollected < total_rows && mesh.io.resp.bits.tag.rob =/= 0xff.U) { - outBuf(total_rows - 1.U - outBufCollected) := mesh.io.resp.bits.data + outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc(mesh.io.resp.bits.data) outBufCollected := outBufCollected + 1.U }.otherwise {} } @@ -41,12 +41,12 @@ trait GemminiExCtrlStoreOps { this: GemminiExCtrl => when(mesh.io.resp.valid) { when(cfg_dataflow === Dataflow.OS.id.U) { when(mesh.io.resp.bits.total_rows === total_rows) { - outBuf(outBufRows) := mesh.io.resp.bits.data + outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) outBufRows := outBufRows - 1.U outBufCollected := outBufCollected + 1.U } }.otherwise { - outBuf(outBufRows) := mesh.io.resp.bits.data + outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) outBufRows := outBufRows + 1.U } } diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala index db5015c4..91909207 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/GemminiBallParam.scala @@ -3,14 +3,15 @@ package framework.balldomain.prototype.gemmini.configs import upickle.default._ case class GemminiBallParam( - meshRows: Int, - meshColumns: Int, - tileRows: Int, - tileColumns: Int, - inputWidth: Int, - accWidth: Int, - tileLatency: Int, - outputDelay: Int) { + meshRows: Int, + meshColumns: Int, + tileRows: Int, + tileColumns: Int, + inputWidth: Int, + accWidth: Int, + spatialOutputWidth: Int, + tileLatency: Int, + outputDelay: Int) { val totalRows: Int = meshRows * tileRows val totalColumns: Int = meshColumns * tileColumns diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json index 44eea666..4bd585c5 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/configs/default.json @@ -5,6 +5,7 @@ "tileColumns": 1, "inputWidth": 8, "accWidth": 32, + "spatialOutputWidth": 20, "tileLatency": 0, - "outputDelay": 0 + "outputDelay": 1 } diff --git a/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala b/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala index 5bf59800..b0b6cfe0 100644 --- a/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala +++ b/arch/src/main/scala/sims/bebop/BebopBuckyballSubsystemCosim.scala @@ -17,24 +17,30 @@ import framework.top.GlobalConfig object BebopBuckyballSubsystemCosim { val custom3Opcode: UInt = 0x7b.U(7.W) - def roccCmd(funct: UInt, xs1: UInt, xs2: UInt, xLen: Int): RoCCCommandBB = { + def roccCmd( + funct: UInt, + xs1: UInt, + xs2: UInt, + xLen: Int + ): RoCCCommandBB = { val cmd = Wire(new RoCCCommandBB(xLen)) val f7 = funct(6, 0) cmd.raw_inst := Cat(f7, 0.U(5.W), 0.U(5.W), 3.U(3.W), 0.U(5.W), custom3Opcode) - cmd.pc := 0.U(xLen.W) - cmd.funct := funct - cmd.funct3 := 3.U - cmd.rs2 := 0.U - cmd.rs1 := 0.U - cmd.xd := true.B - cmd.xs1 := true.B - cmd.xs2 := true.B - cmd.rd := 0.U - cmd.opcode := custom3Opcode - cmd.rs1Data := xs1 - cmd.rs2Data := xs2 + cmd.pc := 0.U(xLen.W) + cmd.funct := funct + cmd.funct3 := 3.U + cmd.rs2 := 0.U + cmd.rs1 := 0.U + cmd.xd := true.B + cmd.xs1 := true.B + cmd.xs2 := true.B + cmd.rd := 0.U + cmd.opcode := custom3Opcode + cmd.rs1Data := xs1 + cmd.rs2Data := xs2 cmd } + } /** Full toy-config accelerator (Frontend + 9 balls + MemDomain + GpDomain) for Spike–Verilator cosim. */ @@ -43,7 +49,7 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { val b: GlobalConfig = GlobalConfig() val beatBytes = b.memDomain.dma_buswidth / 8 - val ramMask = (BigInt(1) << b.memDomain.memAddrLen) - 1 + val ramMask = (BigInt(1) << b.memDomain.memAddrLen) - 1 require((ramMask & (beatBytes - 1)) == beatBytes - 1, "TLTestRAM mask must align to dma beatBytes") val readerNode = TLClientNode( @@ -52,11 +58,11 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { Seq( TLClientParameters( name = "bebop-cosim-reader", - sourceId = IdRange(0, b.memDomain.dma_n_xacts), - ), - ), - ), - ), + sourceId = IdRange(0, b.memDomain.dma_n_xacts) + ) + ) + ) + ) ) val writerNode = TLClientNode( @@ -65,19 +71,19 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { Seq( TLClientParameters( name = "bebop-cosim-writer", - sourceId = IdRange(0, b.memDomain.dma_n_xacts), - ), - ), - ), - ), + sourceId = IdRange(0, b.memDomain.dma_n_xacts) + ) + ) + ) + ) ) val xbar = TLXbar() val ram = LazyModule(new TLTestRAM(AddressSet(0x0, ramMask), beatBytes = beatBytes)) ram.node := xbar - xbar := TLBuffer() := readerNode - xbar := TLBuffer() := writerNode + xbar := TLBuffer() := readerNode + xbar := TLBuffer() := writerNode lazy val module = new LazyModuleImp(this) { override def desiredName: String = "BebopBuckyballSubsystemCosim" @@ -100,30 +106,30 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { acc.io.sfence := false.B acc.io.hartid := 0.U(b.core.xLen.W) - acc.io.ptw(0).req.ready := true.B + acc.io.ptw(0).req.ready := true.B acc.io.ptw(0).resp.valid := false.B - acc.io.ptw(0).resp.bits := 0.U.asTypeOf(acc.io.ptw(0).resp.bits) - acc.io.ptw(0).ptbr.mode := 0.U - acc.io.ptw(0).ptbr.asid := 0.U - acc.io.ptw(0).ptbr.ppn := 0.U + acc.io.ptw(0).resp.bits := 0.U.asTypeOf(acc.io.ptw(0).resp.bits) + acc.io.ptw(0).ptbr.mode := 0.U + acc.io.ptw(0).ptbr.asid := 0.U + acc.io.ptw(0).ptbr.ppn := 0.U acc.io.ptw(0).hgatp.mode := 0.U acc.io.ptw(0).hgatp.asid := 0.U - acc.io.ptw(0).hgatp.ppn := 0.U + acc.io.ptw(0).hgatp.ppn := 0.U acc.io.ptw(0).vsatp.mode := 0.U acc.io.ptw(0).vsatp.asid := 0.U - acc.io.ptw(0).vsatp.ppn := 0.U - acc.io.ptw(0).status := 0.U.asTypeOf(new MStatus()) - acc.io.ptw(0).hstatus := 0.U.asTypeOf(new HStatus()) - acc.io.ptw(0).gstatus := 0.U.asTypeOf(new MStatus()) + acc.io.ptw(0).vsatp.ppn := 0.U + acc.io.ptw(0).status := 0.U.asTypeOf(new MStatus()) + acc.io.ptw(0).hstatus := 0.U.asTypeOf(new HStatus()) + acc.io.ptw(0).gstatus := 0.U.asTypeOf(new MStatus()) for (i <- 0 until b.core.nPMPs) { - acc.io.ptw(0).pmp(i).cfg.l := false.B + acc.io.ptw(0).pmp(i).cfg.l := false.B acc.io.ptw(0).pmp(i).cfg.res := 0.U - acc.io.ptw(0).pmp(i).cfg.a := 0.U - acc.io.ptw(0).pmp(i).cfg.x := false.B - acc.io.ptw(0).pmp(i).cfg.w := false.B - acc.io.ptw(0).pmp(i).cfg.r := false.B - acc.io.ptw(0).pmp(i).addr := 0.U - acc.io.ptw(0).pmp(i).mask := 0.U + acc.io.ptw(0).pmp(i).cfg.a := 0.U + acc.io.ptw(0).pmp(i).cfg.x := false.B + acc.io.ptw(0).pmp(i).cfg.w := false.B + acc.io.ptw(0).pmp(i).cfg.r := false.B + acc.io.ptw(0).pmp(i).addr := 0.U + acc.io.ptw(0).pmp(i).mask := 0.U } val shared = Module(new SharedMemBackend(b)) @@ -131,14 +137,14 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { shared.io.mem_req(ch) <> acc.io.shared_mem_req(ch) } shared.io.config <> acc.io.shared_config - shared.io.query_vbank_id := acc.io.shared_query_vbank_id + shared.io.query_vbank_id := acc.io.shared_query_vbank_id acc.io.shared_query_group_count := shared.io.query_group_count val barrier = Module(new BarrierUnit(1)) - barrier.io.arrive(0) := acc.io.barrier_arrive + barrier.io.arrive(0) := acc.io.barrier_arrive acc.io.barrier_release := barrier.io.release(0) - acc.io.tlbExp(0).flush_skip := false.B + acc.io.tlbExp(0).flush_skip := false.B acc.io.tlbExp(0).flush_retry := false.B val sIdle :: sCmd :: sWait :: sDone :: Nil = Enum(4) @@ -150,8 +156,8 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { done := state === sDone result := resReg - acc.io.cmd.valid := state === sCmd - acc.io.cmd.bits := cmdReg + acc.io.cmd.valid := state === sCmd + acc.io.cmd.bits := cmdReg acc.io.resp.ready := state === sWait val waitCycles = RegInit(0.U(24.W)) @@ -190,4 +196,5 @@ class BebopBuckyballSubsystemCosim(implicit p: Parameters) extends LazyModule { } } } + } diff --git a/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala b/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala index 531ba63b..b773dfa2 100644 --- a/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala +++ b/arch/src/main/scala/sims/bebop/BebopCosimBlocks.scala @@ -7,43 +7,43 @@ import chisel3.util._ object BebopCosimBlocks { // FUNCT_* (7-bit RoCC custom field) - val F_FENCE: UInt = 0.U(7.W) - val F_BARRIER: UInt = 1.U(7.W) - val F_GEMMINI_CONFIG: UInt = 2.U(7.W) - val F_GEMMINI_FLUSH: UInt = 3.U(7.W) - val F_BDB_COUNTER: UInt = 4.U(7.W) - val F_MVOUT: UInt = 16.U(7.W) - val F_MSET: UInt = 32.U(7.W) - val F_MVIN: UInt = 33.U(7.W) - val F_IM2COL: UInt = 48.U(7.W) - val F_TRANSPOSE: UInt = 49.U(7.W) - val F_RELU: UInt = 50.U(7.W) - val F_QUANT: UInt = 51.U(7.W) - val F_DEQUANT: UInt = 52.U(7.W) - val F_GEMMINI_PRELOAD: UInt = 53.U(7.W) - val F_BDB_BACKDOOR: UInt = 54.U(7.W) - val F_MUL_WARP16: UInt = 64.U(7.W) - val F_BFP: UInt = 65.U(7.W) - val F_GEMMINI_COMPUTE_PRELOADED: UInt = 66.U(7.W) - val F_GEMMINI_COMPUTE_ACCUMULATED: UInt = 67.U(7.W) - val F_GEMMINI_LOOP_WS_CONFIG_BOUNDS: UInt = 80.U(7.W) - val F_GEMMINI_LOOP_WS_CONFIG_ADDR_A: UInt = 81.U(7.W) - val F_GEMMINI_LOOP_WS_CONFIG_ADDR_B: UInt = 82.U(7.W) - val F_GEMMINI_LOOP_WS_CONFIG_ADDR_D: UInt = 83.U(7.W) - val F_GEMMINI_LOOP_WS_CONFIG_ADDR_C: UInt = 84.U(7.W) + val F_FENCE: UInt = 0.U(7.W) + val F_BARRIER: UInt = 1.U(7.W) + val F_GEMMINI_CONFIG: UInt = 2.U(7.W) + val F_GEMMINI_FLUSH: UInt = 3.U(7.W) + val F_BDB_COUNTER: UInt = 4.U(7.W) + val F_MVOUT: UInt = 16.U(7.W) + val F_MSET: UInt = 32.U(7.W) + val F_MVIN: UInt = 33.U(7.W) + val F_IM2COL: UInt = 48.U(7.W) + val F_TRANSPOSE: UInt = 49.U(7.W) + val F_RELU: UInt = 50.U(7.W) + val F_QUANT: UInt = 51.U(7.W) + val F_DEQUANT: UInt = 52.U(7.W) + val F_GEMMINI_PRELOAD: UInt = 53.U(7.W) + val F_BDB_BACKDOOR: UInt = 54.U(7.W) + val F_MUL_WARP16: UInt = 64.U(7.W) + val F_BFP: UInt = 65.U(7.W) + val F_GEMMINI_COMPUTE_PRELOADED: UInt = 66.U(7.W) + val F_GEMMINI_COMPUTE_ACCUMULATED: UInt = 67.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_BOUNDS: UInt = 80.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_A: UInt = 81.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_B: UInt = 82.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_D: UInt = 83.U(7.W) + val F_GEMMINI_LOOP_WS_CONFIG_ADDR_C: UInt = 84.U(7.W) val F_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB: UInt = 85.U(7.W) val F_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC: UInt = 86.U(7.W) - val F_GEMMINI_LOOP_WS: UInt = 87.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_1: UInt = 96.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_2: UInt = 97.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_3: UInt = 98.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_4: UInt = 99.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_5: UInt = 100.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_6: UInt = 101.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_7: UInt = 102.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_8: UInt = 103.U(7.W) - val F_GEMMINI_LOOP_CONV_WS_CONFIG_9: UInt = 104.U(7.W) - val F_GEMMINI_LOOP_CONV_WS: UInt = 105.U(7.W) + val F_GEMMINI_LOOP_WS: UInt = 87.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_1: UInt = 96.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_2: UInt = 97.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_3: UInt = 98.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_4: UInt = 99.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_5: UInt = 100.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_6: UInt = 101.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_7: UInt = 102.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_8: UInt = 103.U(7.W) + val F_GEMMINI_LOOP_CONV_WS_CONFIG_9: UInt = 104.U(7.W) + val F_GEMMINI_LOOP_CONV_WS: UInt = 105.U(7.W) val knownFuncts: Seq[UInt] = Seq( F_FENCE, @@ -82,7 +82,7 @@ object BebopCosimBlocks { F_GEMMINI_LOOP_CONV_WS_CONFIG_7, F_GEMMINI_LOOP_CONV_WS_CONFIG_8, F_GEMMINI_LOOP_CONV_WS_CONFIG_9, - F_GEMMINI_LOOP_CONV_WS, + F_GEMMINI_LOOP_CONV_WS ) def isKnownFunct(funct: UInt): Bool = knownFuncts.map(_ === funct).reduce(_ || _) @@ -92,47 +92,47 @@ object BebopCosimBlocks { val _ = (xs1, xs2) MuxLookup( funct, - 0.U(64.W), + 0.U(64.W) )( Seq( - F_FENCE -> 0.U(64.W), - F_BARRIER -> 0.U(64.W), - F_GEMMINI_CONFIG -> 0.U(64.W), - F_GEMMINI_FLUSH -> 0.U(64.W), - F_BDB_COUNTER -> 0.U(64.W), - F_MVOUT -> 0.U(64.W), - F_MSET -> 0.U(64.W), - F_MVIN -> 0.U(64.W), - F_IM2COL -> 0.U(64.W), - F_TRANSPOSE -> 0.U(64.W), - F_RELU -> 0.U(64.W), - F_QUANT -> 0.U(64.W), - F_DEQUANT -> 0.U(64.W), - F_GEMMINI_PRELOAD -> 0.U(64.W), - F_BDB_BACKDOOR -> 0.U(64.W), - F_MUL_WARP16 -> 0.U(64.W), - F_BFP -> 0.U(64.W), - F_GEMMINI_COMPUTE_PRELOADED -> 0.U(64.W), - F_GEMMINI_COMPUTE_ACCUMULATED -> 0.U(64.W), - F_GEMMINI_LOOP_WS_CONFIG_BOUNDS -> 0.U(64.W), - F_GEMMINI_LOOP_WS_CONFIG_ADDR_A -> 0.U(64.W), - F_GEMMINI_LOOP_WS_CONFIG_ADDR_B -> 0.U(64.W), - F_GEMMINI_LOOP_WS_CONFIG_ADDR_D -> 0.U(64.W), - F_GEMMINI_LOOP_WS_CONFIG_ADDR_C -> 0.U(64.W), + F_FENCE -> 0.U(64.W), + F_BARRIER -> 0.U(64.W), + F_GEMMINI_CONFIG -> 0.U(64.W), + F_GEMMINI_FLUSH -> 0.U(64.W), + F_BDB_COUNTER -> 0.U(64.W), + F_MVOUT -> 0.U(64.W), + F_MSET -> 0.U(64.W), + F_MVIN -> 0.U(64.W), + F_IM2COL -> 0.U(64.W), + F_TRANSPOSE -> 0.U(64.W), + F_RELU -> 0.U(64.W), + F_QUANT -> 0.U(64.W), + F_DEQUANT -> 0.U(64.W), + F_GEMMINI_PRELOAD -> 0.U(64.W), + F_BDB_BACKDOOR -> 0.U(64.W), + F_MUL_WARP16 -> 0.U(64.W), + F_BFP -> 0.U(64.W), + F_GEMMINI_COMPUTE_PRELOADED -> 0.U(64.W), + F_GEMMINI_COMPUTE_ACCUMULATED -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_BOUNDS -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_A -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_B -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_D -> 0.U(64.W), + F_GEMMINI_LOOP_WS_CONFIG_ADDR_C -> 0.U(64.W), F_GEMMINI_LOOP_WS_CONFIG_STRIDES_AB -> 0.U(64.W), F_GEMMINI_LOOP_WS_CONFIG_STRIDES_DC -> 0.U(64.W), - F_GEMMINI_LOOP_WS -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_1 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_2 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_3 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_4 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_5 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_6 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_7 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_8 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS_CONFIG_9 -> 0.U(64.W), - F_GEMMINI_LOOP_CONV_WS -> 0.U(64.W), - ), + F_GEMMINI_LOOP_WS -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_1 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_2 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_3 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_4 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_5 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_6 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_7 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_8 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS_CONFIG_9 -> 0.U(64.W), + F_GEMMINI_LOOP_CONV_WS -> 0.U(64.W) + ) ) } @@ -141,4 +141,5 @@ object BebopCosimBlocks { val _ = (funct, xs1, xs2) 0.U(64.W) } + } diff --git a/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala b/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala index dd631759..877968ca 100644 --- a/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala +++ b/arch/src/main/scala/sims/bebop/BebopSpikeCosimTop.scala @@ -3,7 +3,8 @@ package sims.bebop import chisel3._ import chisel3.util.Cat -/** Verilator cosim top: RoCC insn → rd + optional `bankDigestPeek` for future BEMU bank hash compare. +/** + * Verilator cosim top: RoCC insn → rd + optional `bankDigestPeek` for future BEMU bank hash compare. * * `execRet` comes from [[BebopCosimBlocks.execRet]] (per-funct). rd rule matches * `bebop/src/emu/iss/iss.rs`: `rd = if v == 0 { funct } else { 0 }`. @@ -19,7 +20,7 @@ class BebopSpikeCosimTop extends RawModule { val bankDigestPeek = IO(Output(UInt(64.W))) val execRet = BebopCosimBlocks.execRet(funct, xs1, xs2) - val known = BebopCosimBlocks.isKnownFunct(funct) - result := Mux(known && execRet === 0.U, Cat(0.U(57.W), funct), 0.U(64.W)) + val known = BebopCosimBlocks.isKnownFunct(funct) + result := Mux(known && execRet === 0.U, Cat(0.U(57.W), funct), 0.U(64.W)) bankDigestPeek := BebopCosimBlocks.bankDigestPeek(funct, xs1, xs2) } diff --git a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala index 5aeb0fbf..0d5a78dc 100644 --- a/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala +++ b/arch/src/main/scala/sims/bebop/EmitBebopSpikeCosimVerilog.scala @@ -6,6 +6,7 @@ import org.chipsalliance.diplomacy.lazymodule.LazyModule /** `mill buckyball.runMain sims.bebop.EmitBebopSpikeCosimVerilog ` */ object EmitBebopSpikeCosimVerilog { + def main(args: Array[String]): Unit = { val dir = if (args.nonEmpty) args(0) else "gen-bebop-cosim" implicit val p: Parameters = org.chipsalliance.cde.config.Parameters.empty @@ -13,20 +14,21 @@ object EmitBebopSpikeCosimVerilog { ChiselStage.emitSystemVerilogFile( bbCosim.module, firtoolOpts = Array.empty, - args = Array("-td", dir), + args = Array("-td", dir) ) - val bbPath = java.nio.file.Paths.get(dir, "BebopBuckyballSubsystemCosim.sv") - val bbText = java.nio.file.Files.readString(bbPath) - val marker = "// ----- 8< ----- FILE \"firrtl_black_box_resource_files.f\"" - val cut = bbText.indexOf(marker) + val bbPath = java.nio.file.Paths.get(dir, "BebopBuckyballSubsystemCosim.sv") + val bbText = java.nio.file.Files.readString(bbPath) + val marker = "// ----- 8< ----- FILE \"firrtl_black_box_resource_files.f\"" + val cut = bbText.indexOf(marker) if (cut >= 0) { java.nio.file.Files.writeString(bbPath, bbText.substring(0, cut)) } ChiselStage.emitSystemVerilogFile( new VecComputeTop, firtoolOpts = Array.empty, - args = Array("-td", dir), + args = Array("-td", dir) ) println(s"EmitBebopSpikeCosimVerilog: wrote under $dir") } + } diff --git a/arch/src/main/scala/sims/bebop/VecComputeTop.scala b/arch/src/main/scala/sims/bebop/VecComputeTop.scala index 9a0f4149..26e32bbc 100644 --- a/arch/src/main/scala/sims/bebop/VecComputeTop.scala +++ b/arch/src/main/scala/sims/bebop/VecComputeTop.scala @@ -55,12 +55,12 @@ class VecComputeTop extends Module { } } - mul.io.in.valid := inFire + mul.io.in.valid := inFire mul.io.in.bits.in1 := op1Reg mul.io.in.bits.in2 := op2Reg - mul.io.out.ready := true.B + mul.io.out.ready := true.B - io.res := mul.io.out.bits.out + io.res := mul.io.out.bits.out io.valid := active && mul.io.out.valid - io.done := doneR + io.done := doneR } diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index cd8a7310..6cf46f13 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -1,124 +1,101 @@ -// package sims.pegasus - -// import chisel3._ -// import chisel3.util._ - -// import org.chipsalliance.cde.config.{Parameters} -// import freechips.rocketchip.util.{ResetCatchAndSync} - -// import chipyard.harness.{HasHarnessInstantiators} -// import chipyard.iobinders.{AXI4MemPort} - -// import pegasus._ - -// // PegasusHarness: top-level Chisel Module for AU280 FPGA. -// // Integrates PegasusShell (FPGA IPs) with ChipTop (SoC DUT) via Chipyard -// // harness infrastructure. -// // -// // PCIe and HBM2 reference clock pins are the top-level IOs. -// // ChipTop is instantiated inside via instantiateChipTops(). -// // HarnessBinders connect ChipTop's exposed ports (AXI4MemPort, UARTPort, etc.) -// // to pegasusShell's interface signals. -// // -// class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { - -// val io = IO(new Bundle { -// // PCIe physical interface -// val pcie_sys_clk = Input(Clock()) -// val pcie_sys_clk_gt = Input(Clock()) -// val pcie_sys_rst_n = Input(Bool()) -// val pcie_exp_txp = Output(UInt(16.W)) -// val pcie_exp_txn = Output(UInt(16.W)) -// val pcie_exp_rxp = Input(UInt(16.W)) -// val pcie_exp_rxn = Input(UInt(16.W)) - -// // HBM2 reference clock (100 MHz) -// val hbm_ref_clk = Input(Clock()) -// }) - -// // --- Instantiate PegasusShell --- -// val pegasusShell = Module(new PegasusShell) -// pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk -// pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt -// pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n -// io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp -// io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn -// pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp -// pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn -// pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk - -// // UART TX: default idle high until ChipTop provides real signal -// pegasusShell.io.uart_tx := true.B - -// // Chip mem: tie off until ChipTop provides real signals -// pegasusShell.io.chip_mem_awid := 0.U -// pegasusShell.io.chip_mem_awaddr := 0.U -// pegasusShell.io.chip_mem_awlen := 0.U -// pegasusShell.io.chip_mem_awsize := 0.U -// pegasusShell.io.chip_mem_awburst := 0.U -// pegasusShell.io.chip_mem_awvalid := false.B -// pegasusShell.io.chip_mem_wdata := 0.U -// pegasusShell.io.chip_mem_wstrb := 0.U -// pegasusShell.io.chip_mem_wlast := false.B -// pegasusShell.io.chip_mem_wvalid := false.B -// pegasusShell.io.chip_mem_bready := false.B -// pegasusShell.io.chip_mem_arid := 0.U -// pegasusShell.io.chip_mem_araddr := 0.U -// pegasusShell.io.chip_mem_arlen := 0.U -// pegasusShell.io.chip_mem_arsize := 0.U -// pegasusShell.io.chip_mem_arburst := 0.U -// pegasusShell.io.chip_mem_arvalid := false.B -// pegasusShell.io.chip_mem_rready := false.B - -// // --- HasHarnessInstantiators required interface --- -// def referenceClockFreqMHz: Double = 200.0 -// def referenceClock: Clock = pegasusShell.io.dut_clk -// def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset - -// val success = WireInit(false.B) - -// // --- Instantiate ChipTop and apply HarnessBinders --- -// // HarnessBinders for UART and AXI4Mem will override the defaults above -// // by calling connectChipMem() and driving pegasusShell.io.uart_tx -// val lazyDuts = instantiateChipTops() - -// // Called by WithPegasusAXIMem HarnessBinder to connect ChipTop ExtMem AXI4 -// def connectChipMem(port: AXI4MemPort): Unit = { -// val axi = port.io.bits -// // Write address channel -// pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(6.W)) -// pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(33.W)) -// pegasusShell.io.chip_mem_awlen := axi.aw.bits.len -// pegasusShell.io.chip_mem_awsize := axi.aw.bits.size -// pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst -// pegasusShell.io.chip_mem_awvalid := axi.aw.valid -// axi.aw.ready := pegasusShell.io.chip_mem_awready -// // Write data channel -// pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(256.W)) -// pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(32.W)) -// pegasusShell.io.chip_mem_wlast := axi.w.bits.last -// pegasusShell.io.chip_mem_wvalid := axi.w.valid -// axi.w.ready := pegasusShell.io.chip_mem_wready -// // Write response channel -// axi.b.bits.id := pegasusShell.io.chip_mem_bid.asTypeOf(axi.b.bits.id) -// axi.b.bits.resp := pegasusShell.io.chip_mem_bresp -// axi.b.valid := pegasusShell.io.chip_mem_bvalid -// pegasusShell.io.chip_mem_bready := axi.b.ready -// // Read address channel -// pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(6.W)) -// pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(33.W)) -// pegasusShell.io.chip_mem_arlen := axi.ar.bits.len -// pegasusShell.io.chip_mem_arsize := axi.ar.bits.size -// pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst -// pegasusShell.io.chip_mem_arvalid := axi.ar.valid -// axi.ar.ready := pegasusShell.io.chip_mem_arready -// // Read data channel -// axi.r.bits.id := pegasusShell.io.chip_mem_rid.asTypeOf(axi.r.bits.id) -// axi.r.bits.data := pegasusShell.io.chip_mem_rdata.asTypeOf(axi.r.bits.data) -// axi.r.bits.resp := pegasusShell.io.chip_mem_rresp -// axi.r.bits.last := pegasusShell.io.chip_mem_rlast -// axi.r.valid := pegasusShell.io.chip_mem_rvalid -// pegasusShell.io.chip_mem_rready := axi.r.ready -// } - -// } +package sims.pegasus + +import chisel3._ + +import org.chipsalliance.cde.config.Parameters + +import chipyard.harness.HasHarnessInstantiators +import chipyard.iobinders.AXI4MemPort + +import pegasus.PegasusShell + +class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { + + val io = IO(new Bundle { + val pcie_sys_clk = Input(Clock()) + val pcie_sys_clk_gt = Input(Clock()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) + val hbm_ref_clk = Input(Clock()) + }) + + val pegasusShell = Module(new PegasusShell) + pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk + pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt + pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n + io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp + io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn + pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp + pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn + pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk + + pegasusShell.io.uart_tx := true.B + + pegasusShell.io.chip_mem_awid := 0.U + pegasusShell.io.chip_mem_awaddr := 0.U + pegasusShell.io.chip_mem_awlen := 0.U + pegasusShell.io.chip_mem_awsize := 0.U + pegasusShell.io.chip_mem_awburst := 0.U + pegasusShell.io.chip_mem_awvalid := false.B + pegasusShell.io.chip_mem_wdata := 0.U + pegasusShell.io.chip_mem_wstrb := 0.U + pegasusShell.io.chip_mem_wlast := false.B + pegasusShell.io.chip_mem_wvalid := false.B + pegasusShell.io.chip_mem_bready := false.B + pegasusShell.io.chip_mem_arid := 0.U + pegasusShell.io.chip_mem_araddr := 0.U + pegasusShell.io.chip_mem_arlen := 0.U + pegasusShell.io.chip_mem_arsize := 0.U + pegasusShell.io.chip_mem_arburst := 0.U + pegasusShell.io.chip_mem_arvalid := false.B + pegasusShell.io.chip_mem_rready := false.B + + def referenceClockFreqMHz: Double = 200.0 + def referenceClock: Clock = pegasusShell.io.dut_clk + def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset + + val success = WireInit(false.B) + + val lazyDuts = instantiateChipTops() + + def connectChipMem(port: AXI4MemPort): Unit = { + val axi = port.io.bits + pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(6.W)) + pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(33.W)) + pegasusShell.io.chip_mem_awlen := axi.aw.bits.len + pegasusShell.io.chip_mem_awsize := axi.aw.bits.size + pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst + pegasusShell.io.chip_mem_awvalid := axi.aw.valid + axi.aw.ready := pegasusShell.io.chip_mem_awready + + pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(256.W)) + pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(32.W)) + pegasusShell.io.chip_mem_wlast := axi.w.bits.last + pegasusShell.io.chip_mem_wvalid := axi.w.valid + axi.w.ready := pegasusShell.io.chip_mem_wready + + axi.b.bits.id := pegasusShell.io.chip_mem_bid.asTypeOf(axi.b.bits.id) + axi.b.bits.resp := pegasusShell.io.chip_mem_bresp + axi.b.valid := pegasusShell.io.chip_mem_bvalid + pegasusShell.io.chip_mem_bready := axi.b.ready + + pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(6.W)) + pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(33.W)) + pegasusShell.io.chip_mem_arlen := axi.ar.bits.len + pegasusShell.io.chip_mem_arsize := axi.ar.bits.size + pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst + pegasusShell.io.chip_mem_arvalid := axi.ar.valid + axi.ar.ready := pegasusShell.io.chip_mem_arready + + axi.r.bits.id := pegasusShell.io.chip_mem_rid.asTypeOf(axi.r.bits.id) + axi.r.bits.data := pegasusShell.io.chip_mem_rdata.asTypeOf(axi.r.bits.data) + axi.r.bits.resp := pegasusShell.io.chip_mem_rresp + axi.r.bits.last := pegasusShell.io.chip_mem_rlast + axi.r.valid := pegasusShell.io.chip_mem_rvalid + pegasusShell.io.chip_mem_rready := axi.r.ready + } + +} diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala index 23087123..bbfdd12a 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala @@ -1,73 +1,90 @@ -// package sims.pegasus +package sims.pegasus -// import chisel3._ -// import chisel3.util._ +import chisel3._ -// import org.chipsalliance.cde.config.{Config} +import org.chipsalliance.cde.config.Config -// import chipyard.harness._ -// import chipyard.iobinders._ +import chipyard.harness.{HarnessBinder, HasHarnessInstantiators} +import chipyard.iobinders.{AXI4MMIOPort, AXI4MemPort, DMIPort, JTAGPort, UARTPort} -// import pegasus._ +class WithPegasusAXIMem + extends HarnessBinder({ + case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => + th.connectChipMem(port) + }) -// // HarnessBinder: connect ChipTop ExtMem AXI4 port to PegasusShell chip_mem interface -// // Replaces WithBlackBoxSimMem (Verilator simulation DRAM model) -// class WithPegasusAXIMem -// extends HarnessBinder({ -// case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => { -// th.connectChipMem(port) -// } -// }) +class WithPegasusUART + extends HarnessBinder({ + case (th: PegasusHarness, port: UARTPort, chipId: Int) => + th.pegasusShell.io.uart_tx := port.io.txd + port.io.rxd := true.B + }) -// // HarnessBinder: connect ChipTop UART TX to PegasusShell (goes to UARTCapture) -// // Replaces WithUARTAdapter (Verilator stdout adapter) -// class WithPegasusUART -// extends HarnessBinder({ -// case (th: PegasusHarness, port: UARTPort, chipId: Int) => { -// th.pegasusShell.io.uart_tx := port.io.txd -// port.io.rxd := true.B // UART RX idle high (no input from host) -// } -// }) +class WithPegasusAXIMMIO + extends HarnessBinder({ + case (th: PegasusHarness, port: AXI4MMIOPort, chipId: Int) => + withClockAndReset(port.io.clock, th.reset) { + val idBits = port.io.bits.aw.bits.id.getWidth + val bId = RegInit(0.U(idBits.W)) + val bValid = RegInit(false.B) -// // Tie off JTAG (not used on FPGA; debug via GDB/OpenOCD over UART is possible but not in scope) -// class WithPegasusTiedOffJTAG -// extends HarnessBinder({ -// case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => { -// port.io.TCK := true.B.asClock -// port.io.TMS := true.B -// port.io.TDI := true.B -// } -// }) + port.io.bits.aw.ready := !bValid + port.io.bits.w.ready := !bValid + when(!bValid && port.io.bits.aw.valid && port.io.bits.w.valid) { + bId := port.io.bits.aw.bits.id + bValid := true.B + } + when(port.io.bits.b.valid && port.io.bits.b.ready) { + bValid := false.B + } -// // Tie off DMI (no simulation-side debug model needed on FPGA) -// class WithPegasusTiedOffDMI -// extends HarnessBinder({ -// case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => { -// port.io.dmi.req.valid := false.B -// port.io.dmi.req.bits := DontCare -// port.io.dmi.resp.ready := true.B -// port.io.dmiClock := false.B.asClock -// port.io.dmiReset := true.B -// } -// }) + port.io.bits.b.valid := bValid + port.io.bits.b.bits.id := bId + port.io.bits.b.bits.resp := 0.U -// // Aggregate config fragment: select PegasusHarness binders -// // and override Verilator-only simulation models -// class WithPegasusHarness -// extends Config( -// new WithPegasusAXIMem ++ -// new WithPegasusUART ++ -// new WithPegasusTiedOffJTAG ++ -// new WithPegasusTiedOffDMI ++ -// // Standard binders that are safe to keep on FPGA -// new chipyard.harness.WithTieOffInterrupts ++ -// new chipyard.harness.WithTieOffL2FBusAXI ++ -// new chipyard.harness.WithGPIOTiedOff ++ -// new chipyard.harness.WithGPIOPinsTiedOff ++ -// new chipyard.harness.WithDriveChipIdPin ++ -// new chipyard.harness.WithCustomBootPinPlusArg ++ -// new chipyard.harness.WithSerialTLTiedOff ++ -// new chipyard.harness.WithClockFromHarness ++ -// new chipyard.harness.WithResetFromHarness ++ -// new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator -// ) + port.io.bits.ar.ready := true.B + port.io.bits.r.valid := RegNext(port.io.bits.ar.valid, false.B) + port.io.bits.r.bits.id := RegNext(port.io.bits.ar.bits.id) + port.io.bits.r.bits.data := 0.U + port.io.bits.r.bits.resp := 0.U + port.io.bits.r.bits.last := true.B + port.io.bits.r.bits.user := 0.U.asTypeOf(port.io.bits.r.bits.user) + } + }) + +class WithPegasusTiedOffJTAG + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => + port.io.TCK := true.B.asClock + port.io.TMS := true.B + port.io.TDI := true.B + }) + +class WithPegasusTiedOffDMI + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => + port.io.dmi.req.valid := false.B + port.io.dmi.req.bits := DontCare + port.io.dmi.resp.ready := true.B + port.io.dmiClock := false.B.asClock + port.io.dmiReset := true.B + }) + +class WithPegasusHarness + extends Config( + new WithPegasusAXIMem ++ + new WithPegasusAXIMMIO ++ + new WithPegasusUART ++ + new WithPegasusTiedOffJTAG ++ + new WithPegasusTiedOffDMI ++ + new chipyard.harness.WithSerialTLTiedOff ++ + new chipyard.harness.WithTieOffInterrupts ++ + new chipyard.harness.WithGPIOTiedOff ++ + new chipyard.harness.WithTieOffL2FBusAXI ++ + new chipyard.harness.WithClockFromHarness ++ + new chipyard.harness.WithResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ + new chipyard.iobinders.WithNMITiedOff + ) diff --git a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala index fa2a121d..42b600e6 100644 --- a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala +++ b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala @@ -1,46 +1,32 @@ -// package sims.pegasus +package sims.pegasus -// import chisel3._ -// import _root_.circt.stage.ChiselStage -// import org.chipsalliance.cde.config.Config +import _root_.circt.stage.ChiselStage +import org.chipsalliance.cde.config.Config -// import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} -// import freechips.rocketchip.subsystem.InSubsystem +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} +import freechips.rocketchip.subsystem.{InSubsystem, WithDefaultMMIOPort} -// // import pegasus.{PegasusHarness, WithPegasusHarness} +class WithPegasusBootROM + extends Config((site, here, up) => { + case BootROMLocated(InSubsystem) => Some(BootROMParams( + contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" + )) + }) -// // BootROM for FPGA (points to the same bootrom image as the Verilator target) -// class WithPegasusBootROM -// extends Config((site, here, up) => { -// case BootROMLocated(InSubsystem) => Some(BootROMParams( -// contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" -// )) -// }) +class PegasusConfig + extends Config( + new WithPegasusHarness ++ + new WithDefaultMMIOPort ++ + new WithPegasusBootROM ++ + new examples.toy.BuckyballToyConfig + ) -// // PegasusBuckyballToyConfig: Buckyball Toy SoC on AU280 FPGA -// // -// // Target clock: 200 MHz. If timing closure yields a different Fmax, -// // update all WithXxxBusFrequency values and re-elaborate so the DTB -// // gets the correct UART baud divisor (otherwise UART output will be garbled). -// class PegasusBuckyballToyConfig -// extends Config( -// new WithPegasusHarness ++ -// new WithPegasusBootROM ++ -// new chipyard.config.WithSystemBusFrequency(200.0) ++ -// new chipyard.config.WithMemoryBusFrequency(200.0) ++ -// new chipyard.config.WithPeripheryBusFrequency(200.0) ++ -// new chipyard.config.WithControlBusFrequency(200.0) ++ -// new chipyard.config.WithFrontBusFrequency(200.0) ++ -// new chipyard.config.WithOffchipBusFrequency(200.0) ++ -// new examples.toy.BuckyballToyConfig -// ) +class PegasusBuckyballToyConfig extends PegasusConfig -// // Elaborate entry point: generate SystemVerilog for PegasusHarness -// // Usage: mill pegasus.runMain sims.pegasus.ElaboratePegasus [firtool options] -// object ElaboratePegasus extends App { -// ChiselStage.emitSystemVerilogFile( -// new PegasusHarness()(new PegasusBuckyballToyConfig().toInstance), -// firtoolOpts = args, -// args = Array.empty -// ) -// } +object ElaboratePegasus extends App { + ChiselStage.emitSystemVerilogFile( + new PegasusHarness()(new PegasusConfig().toInstance), + firtoolOpts = args, + args = Array.empty + ) +} From fe47e755fcfd89c7a5696583db9f654da652093b Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 8 Apr 2026 15:55:54 +0800 Subject: [PATCH 197/238] [docs] misc: update documentation and skills with English translations --- .claude/CLAUDE.md | 174 ++++----- .claude/skills/ball/SKILL.md | 332 +++--------------- .claude/skills/check/SKILL.md | 46 +-- .claude/skills/debug/SKILL.md | 174 ++++----- .claude/skills/optimize/SKILL.md | 164 ++++----- .claude/skills/verify/SKILL.md | 82 ++--- .claude/skills/waveform/SKILL.md | 134 +++---- .../balldomain/prototype/trace/README.md | 117 +++--- .../frontend/configs/FrontendParam.scala | 2 +- .../gpdomain/configs/GpDomainParam.scala | 2 +- .../outside_channel/dma/StreamReader.scala | 2 +- bb-tests/sardine/pytest.ini | 12 +- bb-tests/sardine/run_tests.py | 2 +- bb-tests/sardine/tests/test_ctest.py | 2 +- bb-tests/workloads/src/CTest/toy/relu_test.c | 10 +- .../src/CTest/toy/vecunit_tiled_matmul.c | 4 +- bebop | 2 +- scripts/claude/README.md | 160 ++++----- 18 files changed, 598 insertions(+), 823 deletions(-) diff --git a/.claude/CLAUDE.md b/.claude/CLAUDE.md index 28ea2439..748fcf24 100644 --- a/.claude/CLAUDE.md +++ b/.claude/CLAUDE.md @@ -1,111 +1,111 @@ # Buckyball -基于 RISC-V 的 DSA（Domain Specific Architecture）框架。Chisel 6.5.0，Nix Flake 构建。 - -## 项目结构 - -- `arch/src/main/scala/framework/` — 框架核心 - - `balldomain/prototype/` — Ball 算子实现（每个 Ball 一个子目录） - - `balldomain/blink/` — Blink 协议定义（BlinkIO、BankRead/Write、BallStatus） - - `balldomain/configs/` — BallDomainParam + default.json（ballIdMappings） - - `balldomain/bbus/` — BBus 总线 - - `balldomain/rs/` — BallRsIssue / BallRsComplete（命令/完成接口） - - `memdomain/backend/banks/` — SramReadIO / SramWriteIO - - `core/bbtile/` — BBTile 集成（Rocket core + Buckyball） - - `top/` — GlobalConfig（顶层参数汇聚） -- `arch/src/main/scala/examples/toy/balldomain/` — toy 配置 - - `DISA.scala` — 指令 opcode（funct7 BitPat） - - `DomainDecoder.scala` — 指令解码表（ListLookup） - - `bbus/busRegister.scala` — Ball 生成器注册（match case） -- `arch/src/main/scala/sims/` — 仿真配置 - - `verilator/` — Verilator 配置 - - `verify/` — 单 Ball elaboration（BallTopMain） -- `bb-tests/` — 测试 - - `workloads/lib/bbhw/isa/` — ISA C 宏（每条指令一个 .c 文件） - - `workloads/src/CTest/toy/` — C 测试用例 - - `sardine/` — pytest 测试框架 -- `bbdev/` — 开发工具链（Motia 工作流后端） - -## Blink 协议 - -Ball 通过 Blink 协议接入 BBus。每个 Ball 实现 `HasBlink` trait。 +A RISC-V based DSA (Domain Specific Architecture) framework. Built with Chisel 6.5.0 and Nix Flake. + +## Project Structure + +- `arch/src/main/scala/framework/` — framework core + - `balldomain/prototype/` — Ball operator implementations (one subdirectory per Ball) + - `balldomain/blink/` — Blink protocol definitions (`BlinkIO`, `BankRead/Write`, `BallStatus`) + - `balldomain/configs/` — `BallDomainParam` + `default.json` (`ballIdMappings`) + - `balldomain/bbus/` — BBus interconnect + - `balldomain/rs/` — `BallRsIssue` / `BallRsComplete` (issue/complete interfaces) + - `memdomain/backend/banks/` — `SramReadIO` / `SramWriteIO` + - `core/bbtile/` — BBTile integration (Rocket core + Buckyball) + - `top/` — `GlobalConfig` (top-level parameter aggregation) +- `arch/src/main/scala/examples/toy/balldomain/` — toy config + - `DISA.scala` — instruction opcodes (`funct7` BitPat) + - `DomainDecoder.scala` — instruction decode table (`ListLookup`) + - `bbus/busRegister.scala` — Ball generator registration (`match case`) +- `arch/src/main/scala/sims/` — simulation configs + - `verilator/` — Verilator config + - `verify/` — single-Ball elaboration (`BallTopMain`) +- `bb-tests/` — tests + - `workloads/lib/bbhw/isa/` — ISA C macros (one `.c` file per instruction) + - `workloads/src/CTest/toy/` — C test cases + - `sardine/` — pytest test framework +- `bbdev/` — developer toolchain (Motia workflow backend) + +## Blink Protocol + +Balls connect to BBus through the Blink protocol. Every Ball implements the `HasBlink` trait. ``` BlinkIO(b: GlobalConfig, inBW: Int, outBW: Int): - cmdReq: Flipped(Decoupled(BallRsIssue)) // 命令输入（含 BallDecodeCmd + rob_id） - cmdResp: Decoupled(BallRsComplete) // 完成输出（含 rob_id） - bankRead: Vec(inBW, Flipped(BankRead)) // SRAM 读端口 - bankWrite: Vec(outBW, Flipped(BankWrite)) // SRAM 写端口 - status: BallStatus { idle, running } // 状态信号 + cmdReq: Flipped(Decoupled(BallRsIssue)) // command input (includes BallDecodeCmd + rob_id) + cmdResp: Decoupled(BallRsComplete) // completion output (includes rob_id) + bankRead: Vec(inBW, Flipped(BankRead)) // SRAM read ports + bankWrite: Vec(outBW, Flipped(BankWrite)) // SRAM write ports + status: BallStatus { idle, running } // status signals -BankRead/BankWrite 元数据字段（均为 Input）: +BankRead/BankWrite metadata fields (all Input): bank_id, rob_id, ball_id, group_id -SramReadIO: req.valid/ready + req.bits.addr → resp.valid + resp.bits.data -SramWriteIO: req.valid/ready + req.bits(addr, data, mask, wmode) → resp.valid + resp.bits.ok +SramReadIO: req.valid/ready + req.bits.addr -> resp.valid + resp.bits.data +SramWriteIO: req.valid/ready + req.bits(addr, data, mask, wmode) -> resp.valid + resp.bits.ok ``` -关键时序：SRAM 读延迟 = 1 cycle（req.fire 后下一周期 resp.valid 拉高）。 +Key timing rule: SRAM read latency is 1 cycle (`resp.valid` is asserted in the next cycle after `req.fire`). -## 注册不变量 +## Registration Invariants -添加或修改 Ball 注册时，以下 6 项必须同时满足： +When adding or modifying Ball registrations, all six conditions below must hold: -1. `default.json` 的 `ballNum` == `ballIdMappings` 数组长度 -2. `ballId` 严格递增（0, 1, 2, ...），不跳号 -3. `ballId` 无重复 -4. `DISA.scala` 中 funct7 无重复 -5. `busRegister.scala` 中的 case 名称集合 == `default.json` 中的 ballName 集合 -6. `DomainDecoder.scala` 中的 BID 值集合 == `default.json` 中的 ballId 集合 +1. `ballNum` in `default.json` equals the length of `ballIdMappings` +2. `ballId` is strictly increasing (`0, 1, 2, ...`) with no gaps +3. No duplicated `ballId` +4. No duplicated `funct7` values in `DISA.scala` +5. Case names in `busRegister.scala` equal `ballName` set in `default.json` +6. BID values in `DomainDecoder.scala` equal `ballId` set in `default.json` -用 `/check` skill 可以自动检查所有不变量并可选自动修复。 +Use the `/check` skill to validate all invariants and optionally auto-fix issues. -## MCP 工具 +## MCP Tools -项目配置了 `buckyball-dev` MCP Server，提供以下工具。 +The project configures the `buckyball-dev` MCP server with the following tools. -**重要：编译、仿真、综合、测试等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** -bbdev CLI 是给人类程序员用的，MCP 工具是给 agent 用的——MCP 工具内部会自动管理 bbdev server 生命周期并通过 HTTP API 调用。 +**Important: build, simulation, synthesis, and tests must be invoked via MCP tools. Do not call `bbdev` CLI or `nix develop` directly.** +`bbdev` CLI is for human developers, while MCP tools are for agents. MCP tools manage bbdev server lifecycle and call it through HTTP APIs. -### 校验 -- `validate` — 检查 6 项注册不变量 +### Validation +- `validate` — check all 6 registration invariants -### bbdev API 封装（自动管理 server 生命周期） -- `bbdev_workload_build` — 编译 CTest -- `bbdev_verilator_run(binary, config?, batch?, coverage?)` — 全流程 clean→verilog→build→sim -- `bbdev_verilator_verilog(config, balltype?)` — 生成 Verilog；`config` 必传，`balltype` 可选（单 Ball elaborate） -- `bbdev_verilator_build(jobs?, coverage?)` — 编译 Verilator 仿真器 -- `bbdev_verilator_sim(binary, batch?, coverage?)` — 跑仿真（需先 build） -- `bbdev_sardine_run(workload?, coverage?)` — 批量测试 -- `bbdev_yosys_synth(top?, config?)` — Yosys 综合 + OpenSTA 时序分析 +### bbdev API wrappers (with automatic server lifecycle management) +- `bbdev_workload_build` — build CTests +- `bbdev_verilator_run(binary, config?, batch?, coverage?)` — full flow: clean -> verilog -> build -> sim +- `bbdev_verilator_verilog(config, balltype?)` — generate Verilog; `config` is required, `balltype` optional (single-Ball elaboration) +- `bbdev_verilator_build(jobs?, coverage?)` — build Verilator simulator +- `bbdev_verilator_sim(binary, batch?, coverage?)` — run simulation (requires prior build) +- `bbdev_sardine_run(workload?, coverage?)` — run batch tests +- `bbdev_yosys_synth(top?, config?)` — Yosys synthesis + OpenSTA timing analysis -默认 config 值：`sims.verilator.BuckyballToyVerilatorConfig` -仿真 binary 命名格式：`ctest__test_singlecore-baremetal` +Default config value: `sims.verilator.BuckyballToyVerilatorConfig` +Simulation binary naming format: `ctest__test_singlecore-baremetal` -### 分析报告路径 -- 面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解）、`area_report.txt`（顶层） -- 时序报告：`bbdev/api/steps/yosys/log/timing_report.txt` -- 覆盖率报告：`bb-tests/sardine/reports/coverage/html/` -- 仿真日志：`arch/log//stdout.log`、`disasm.log` -- bdb 调试日志：`arch/log//bdb.log`，包含三种 DPI-C trace： - - `[ITRACE]` — 指令发射/完成 - - `[MTRACE]` — SRAM 读写 - - `[PMCTRACE]` — Ball/Mem 性能计数（elapsed cycles） +### Analysis report paths +- Area reports: `bbdev/api/steps/yosys/log/hierarchy_report.txt` (submodule breakdown), `area_report.txt` (top-level) +- Timing report: `bbdev/api/steps/yosys/log/timing_report.txt` +- Coverage report: `bb-tests/sardine/reports/coverage/html/` +- Simulation logs: `arch/log//stdout.log`, `disasm.log` +- bdb debug log: `arch/log//bdb.log`, with three DPI-C traces: + - `[ITRACE]` — instruction issue/complete + - `[MTRACE]` — SRAM reads/writes + - `[PMCTRACE]` — Ball/Mem performance counters (elapsed cycles) ## Skills -项目 skill 位于 `.claude/skills/` 下： -- `/ball` — 创建新 Ball 算子（全流程：实现→注册→ISA→CTest→仿真） -- `/check` — 注册状态校验 + 自动修复 -- `/verify` — Ball 功能验证（编译→仿真→覆盖率→PMC 分析） -- `/optimize` — RTL 模块面积/延迟优化（适用于任意模块，不限 Ball） -- `/debug` — 仿真调试（日志分析→波形→故障模式库） -- `/waveform` — 波形分析（waveform-mcp 使用指南） - -## 约定 - -- 改 Ball 实现时不要碰注册文件，改注册文件时不要碰实现文件 -- Chisel 版本 6.5.0，不要使用 6.6+ 新 API -- CTest 用 `add_cross_platform_test_target` 注册到 CMakeLists.txt -- **禁止直接调用 `bbdev` CLI 或 `nix develop -c bbdev ...`**，必须通过 MCP 工具调用 -- Ball wrapper 类名必须和 `default.json` 中 `ballName` 一致 +Project skills are under `.claude/skills/`: +- `/ball` — create a new Ball operator (full flow: implementation -> registration -> ISA -> CTest -> simulation) +- `/check` — registration consistency check + auto-fix +- `/verify` — Ball functional verification (build -> simulation -> coverage -> PMC analysis) +- `/optimize` — RTL area/latency optimization (applies to any module, not only Balls) +- `/debug` — simulation debugging (log analysis -> waveform -> failure pattern matching) +- `/waveform` — waveform analysis (`waveform-mcp` usage guide) + +## Conventions + +- Do not edit registration files while changing Ball implementation; do not edit implementation files while changing registration +- Chisel version is 6.5.0; do not use 6.6+ APIs +- Register CTests in CMakeLists via `add_cross_platform_test_target` +- **Do not call `bbdev` CLI or `nix develop -c bbdev ...` directly**; use MCP tools +- Ball wrapper class names must match `ballName` in `default.json` diff --git a/.claude/skills/ball/SKILL.md b/.claude/skills/ball/SKILL.md index 416dea2b..fa11a4a2 100644 --- a/.claude/skills/ball/SKILL.md +++ b/.claude/skills/ball/SKILL.md @@ -1,285 +1,63 @@ --- name: ball -description: 创建一个名为 $ARGUMENTS 的新 Buckyball Ball 算子，完成从实现到验证的全流程。当用户要求创建新 Ball、新算子、新加速单元，或说"加一个 XX Ball"、"实现 XX 操作"时，使用此 skill。即使用户没有明确说"Ball"，只要意图是在 Buckyball 框架中增加一个新的计算算子，都应触发。 +description: Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification. --- -**重要：编译、仿真等操作必须通过 MCP 工具（validate、bbdev_workload_build、bbdev_verilator_run 等）调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** +**Important: all build/simulation operations must go through MCP tools (`validate`, `bbdev_workload_build`, `bbdev_verilator_run`, etc.). Do not use bbdev CLI or nix develop directly.** -## 阶段 1 — 需求收集 +## Phase 1 - Requirement Collection -1. 读取当前注册状态，确定新 Ball 的 ballId 和 funct7： +1. Inspect registration state and decide `ballId` + `funct7`: - `arch/src/main/scala/framework/balldomain/configs/default.json` - `arch/src/main/scala/examples/toy/balldomain/DISA.scala` -2. 检查是否已部分存在（增量模式）： - - 搜索 `arch/src/main/scala/framework/balldomain/prototype/` 下是否有同名目录 - - 搜索 `bb-tests/workloads/lib/bbhw/isa/` 下是否有对应的 ISA 宏文件 - - 搜索 `bb-tests/workloads/src/CTest/toy/` 下是否有对应的 CTest - - 如果部分文件已存在，只补齐缺失部分 -3. 向用户确认以下信息： - - Ball 的计算语义（做什么运算） - - inBW / outBW（读/写 bank 端口数量） - - 是否需要第二个操作数（op2） - - iter（迭代次数）的含义 - -## 阶段 2 — 实现 Ball - -1. 读取参考代码，理解 Blink 协议和现有 Ball 的写法： - - 简单参考：`arch/src/main/scala/framework/balldomain/prototype/relu/ReluBall.scala` 和 `Relu.scala` - - 复杂参考：`arch/src/main/scala/framework/balldomain/prototype/systolicarray/` - - Blink 协议：`arch/src/main/scala/framework/balldomain/blink/blink.scala`、`bank.scala`、`status.scala` - - SRAM 接口：`arch/src/main/scala/framework/memdomain/backend/banks/SramIO.scala` -2. 在 `arch/src/main/scala/framework/balldomain/prototype//` 下创建文件，使用 `references/` 中的模板作为起点。 - -### Ball wrapper 模板（`Ball.scala`） - -```scala -package framework.balldomain.prototype. - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink} -import framework.top.GlobalConfig - -@instantiable -class Ball(val b: GlobalConfig) extends Module with HasBlink { - val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "Ball") - .getOrElse(throw new IllegalArgumentException("Ball not found in config")) - val inBW = ballCommonConfig.inBW - val outBW = ballCommonConfig.outBW - - @public - val io = IO(new BlinkIO(b, inBW, outBW)) - def blink: BlinkIO = io - - val core: Instance[] = Instantiate(new (b)) - - core.io.cmdReq <> io.cmdReq - core.io.cmdResp <> io.cmdResp - for (i <- 0 until inBW) { core.io.bankRead(i) <> io.bankRead(i) } - for (i <- 0 until outBW) { core.io.bankWrite(i) <> io.bankWrite(i) } - io.status <> core.io.status -} -``` - -### Core 模板（`.scala`） - -```scala -package framework.balldomain.prototype. - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import framework.balldomain.rs.{BallRsComplete, BallRsIssue} -import framework.balldomain.blink.{BallStatus, BankRead, BankWrite} -import framework.top.GlobalConfig - -@instantiable -class (val b: GlobalConfig) extends Module { - val ballMapping = b.ballDomain.ballIdMappings.find(_.ballName == "Ball") - .getOrElse(throw new IllegalArgumentException("Ball not found in config")) - val inBW = ballMapping.inBW - val outBW = ballMapping.outBW - - @public - val io = IO(new Bundle { - val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) - val cmdResp = Decoupled(new BallRsComplete(b)) - val bankRead = Vec(inBW, Flipped(new BankRead(b))) - val bankWrite = Vec(outBW, Flipped(new BankWrite(b))) - val status = new BallStatus - }) - - // Latch rob_id on cmdReq.fire - val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) - when(io.cmdReq.fire) { rob_id_reg := io.cmdReq.bits.rob_id } - - // Propagate rob_id to bank metadata - for (i <- 0 until inBW) { - io.bankRead(i).rob_id := rob_id_reg - io.bankRead(i).ball_id := 0.U - } - for (i <- 0 until outBW) { - io.bankWrite(i).rob_id := rob_id_reg - io.bankWrite(i).ball_id := 0.U - } - - // FSM: idle -> read -> compute -> write -> complete -> idle - val idle :: sRead :: sCompute :: sWrite :: complete :: Nil = Enum(5) - val state = RegInit(idle) - - // Default port assignments (override in FSM states) - for (i <- 0 until inBW) { - io.bankRead(i).io.req.valid := false.B - io.bankRead(i).io.req.bits.addr := 0.U - io.bankRead(i).io.resp.ready := false.B - io.bankRead(i).bank_id := 0.U - io.bankRead(i).group_id := 0.U - } - for (i <- 0 until outBW) { - io.bankWrite(i).io.req.valid := false.B - io.bankWrite(i).io.req.bits.addr := 0.U - io.bankWrite(i).io.req.bits.data := 0.U - io.bankWrite(i).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(0.U(1.W))) - io.bankWrite(i).io.req.bits.wmode := false.B - io.bankWrite(i).io.resp.ready := false.B - io.bankWrite(i).bank_id := 0.U - io.bankWrite(i).group_id := 0.U - } - - io.cmdReq.ready := state === idle - io.cmdResp.valid := false.B - io.cmdResp.bits.rob_id := rob_id_reg - - // Latch command fields - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) - - switch(state) { - is(idle) { - when(io.cmdReq.fire) { - rbank_reg := io.cmdReq.bits.cmd.op1_bank - wbank_reg := io.cmdReq.bits.cmd.wr_bank - iter_reg := io.cmdReq.bits.cmd.iter - state := sRead - } - } - is(sRead) { - // TODO: implement read logic - // Key: SRAM read latency = 1 cycle (resp.valid on next cycle after req.fire) - } - is(sCompute) { - // TODO: implement compute logic - } - is(sWrite) { - // TODO: implement write logic - } - is(complete) { - io.cmdResp.valid := true.B - io.cmdResp.bits.rob_id := rob_id_reg - when(io.cmdResp.fire) { state := idle } - } - } - - io.status.idle := (state === idle) - io.status.running := (state =/= idle) && (state =/= complete) -} -``` - -### Param 模板（`configs/BallParam.scala`） - -```scala -package framework.balldomain.prototype..configs - -import upickle.default._ - -case class BallParam( - // TODO: add Ball-specific parameters -) - -object BallParam { - implicit val rw: ReadWriter[BallParam] = macroRW - - def apply(): BallParam = { - val jsonStr = scala.io.Source - .fromFile("src/main/scala/framework/balldomain/prototype//configs/default.json") - .mkString - read[BallParam](jsonStr) - } -} -``` - -关键约束： -- SRAM 读延迟 = 1 cycle（req.fire 后下一周期 resp.valid） -- cmdReq.fire 时 latch 命令字段到寄存器 -- FSM 基本模式：idle → 读数据 → 计算 → 写数据 → complete → idle -- status.idle 和 status.running 必须映射 FSM 状态 - -## 阶段 3 — 注册 - -按顺序更新以下四个文件： -1. `arch/src/main/scala/framework/balldomain/configs/default.json` — 追加 ballIdMappings 条目，更新 ballNum -2. `arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala` — 添加 import 和 match case -3. `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — 添加 `val XXX = BitPat("bxxxxxxx")` -4. `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — 添加 ListLookup 解码行，BID = ballId.U - -## 阶段 4 — ISA C 宏 - -在 `bb-tests/workloads/lib/bbhw/isa/` 下创建 `_.c`： - -```c -#ifndef _BB__H_ -#define _BB__H_ - -#include "isa.h" - -#define BB__FUNC7 - -#define bb_(bank_id, wr_bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_BANK2(wr_bank_id) | \ - BB_RD0 | BB_WR | BB_ITER(iter)), \ - 0, BB__FUNC7) - -#endif // _BB__H_ -``` - -在 `bb-tests/workloads/lib/bbhw/isa/isa.h` 中 `#include` 新文件。 - -## 阶段 5 — CTest - -在 `bb-tests/workloads/src/CTest/toy/` 下创建 `_test.c`： - -```c -#include "buckyball.h" -#include -#include -#include -#include -#include - -#define DIM 16 - -// Fixed input and expected output matrices -static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))) = { /* ... */ }; -static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { /* ... */ }; -static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); - -void hw_(const char *test_name, elem_t *a, elem_t *b, int size) { - uint32_t op1_bank_id = 0; - uint32_t wr_bank_id = 1; - - bb_mem_alloc(op1_bank_id, 1, 1); - bb_mem_alloc(wr_bank_id, 1, 1); - - bb_mvin((uintptr_t)a, op1_bank_id, size, 1); - bb_(op1_bank_id, wr_bank_id, size); - bb_mvout((uintptr_t)b, wr_bank_id, size, 1); - bb_fence(); -} - -int main() { - clear_i8_matrix(output_matrix, DIM, DIM); - hw_("", input_matrix, output_matrix, DIM); - - if (compare_i8_matrices(output_matrix, expected_matrix, DIM, DIM)) { - printf(" test PASSED\n"); - return 0; - } else { - printf(" test FAILED\n"); - return 1; - } -} -``` - -在 `bb-tests/workloads/src/CTest/toy/CMakeLists.txt` 中用 `add_cross_platform_test_target` 注册。 -在 `bb-tests/sardine/tests/test_ctest.py` 的 `ctest_workloads` 列表中追加对应条目。 - -## 阶段 6 — 校验 + 编译 + 仿真 - -1. 调用 MCP 工具 `validate` 做静态校验，确认 6 项不变量全部通过 -2. 调用 MCP 工具 `bbdev_workload_build` 编译 CTest -3. 调用 MCP 工具 `bbdev_verilator_run` 跑仿真，指定新 Ball 的 CTest binary -4. 解析仿真结果： - - PASSED → 完成 - - FAILED → 使用 `/debug` skill 进入调试流程 +2. Check for partial existing implementation (incremental mode): + - existing directory in `arch/src/main/scala/framework/balldomain/prototype/` + - existing ISA macro in `bb-tests/workloads/lib/bbhw/isa/` + - existing CTest in `bb-tests/workloads/src/CTest/toy/` +3. Confirm with user: + - operator semantics + - `inBW` / `outBW` + - whether `op2` is needed + - meaning of `iter` + +## Phase 2 - Implement the Ball + +1. Read references: + - simple example: `.../prototype/relu/ReluBall.scala`, `Relu.scala` + - complex example: `.../prototype/systolicarray/` + - Blink protocol: `.../blink/blink.scala`, `bank.scala`, `status.scala` + - SRAM IO: `.../memdomain/backend/banks/SramIO.scala` +2. Create files under `arch/src/main/scala/framework/balldomain/prototype//` using templates from `references/`. + +### Key constraints +- SRAM read latency is 1 cycle (`resp.valid` in the cycle after `req.fire`) +- Latch command fields when `cmdReq.fire` +- Base FSM pattern: `idle -> read -> compute -> write -> complete -> idle` +- `status.idle` and `status.running` must map correctly to FSM states + +## Phase 3 - Register the Ball + +Update files in order: +1. `.../configs/default.json` - append `ballIdMappings` entry and update `ballNum` +2. `.../bbus/busRegister.scala` - add import + `match case` +3. `.../DISA.scala` - add `val XXX = BitPat("bxxxxxxx")` +4. `.../DomainDecoder.scala` - add decode row (`BID = ballId.U`) + +## Phase 4 - Add ISA C Macro + +Create `_.c` under `bb-tests/workloads/lib/bbhw/isa/`, then include it in `isa.h`. + +## Phase 5 - Add CTest + +1. Create `_test.c` under `bb-tests/workloads/src/CTest/toy/` +2. Register in `bb-tests/workloads/src/CTest/toy/CMakeLists.txt` using `add_cross_platform_test_target` +3. Append workload entry in `bb-tests/sardine/tests/test_ctest.py` (`ctest_workloads`) + +## Phase 6 - Validate, Build, and Simulate + +1. Run `validate` and ensure all 6 invariants pass +2. Run `bbdev_workload_build` +3. Run `bbdev_verilator_run` for this Ball's CTest binary +4. Interpret results: + - `PASSED` -> done + - `FAILED` -> switch to `/debug` diff --git a/.claude/skills/check/SKILL.md b/.claude/skills/check/SKILL.md index 6ffc9edd..9711c10b 100644 --- a/.claude/skills/check/SKILL.md +++ b/.claude/skills/check/SKILL.md @@ -1,42 +1,42 @@ --- name: check -description: 对 Buckyball Ball 注册状态做静态校验，并可选自动修复不一致。当用户要求检查注册状态、校验 Ball 配置、排查注册问题，或在修改注册文件后需要验证一致性时使用此 skill。 +description: Staticaly validate Buckyball Ball registration consistency and optionally auto-fix mismatches. Use this skill when users ask to inspect registration status, validate Ball configuration, troubleshoot registration issues, or verify consistency after registration edits. --- -## 校验流程 +## Validation Flow -调用 MCP 工具 `validate`，检查以下 6 项注册不变量： -1. ballNum == ballIdMappings 数组长度 -2. ballId 严格递增（0, 1, 2, ...），不跳号 -3. ballId 无重复 -4. DISA.scala funct7 无重复 -5. busRegister.scala case 名称与 default.json ballName 一致 -6. DomainDecoder.scala BID 与 default.json ballId 一致 +Call MCP tool `validate` to check these 6 invariants: +1. `ballNum` equals `ballIdMappings` array length +2. `ballId` is strictly increasing (`0, 1, 2, ...`) with no gaps +3. no duplicated `ballId` +4. no duplicated `funct7` in `DISA.scala` +5. case names in `busRegister.scala` match `ballName` in `default.json` +6. BID values in `DomainDecoder.scala` match `ballId` in `default.json` -每项报告 pass/fail 状态。 +Report pass/fail for each item. -## 注册状态概览 +## Registration Summary -校验后生成一张汇总表，展示当前所有 Ball 的注册信息。数据源： +After validation, generate a summary table for all Ball registrations. Data sources: -- `arch/src/main/scala/framework/balldomain/configs/default.json` — ballId, ballName, inBW, outBW -- `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — funct7 值 -- `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — 解码行中的 BID +- `arch/src/main/scala/framework/balldomain/configs/default.json` — `ballId`, `ballName`, `inBW`, `outBW` +- `arch/src/main/scala/examples/toy/balldomain/DISA.scala` — `funct7` values +- `arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` — BID in decode rows -表格格式： +Table format: | ballId | ballName | funct7 | inBW | outBW | DISA | busReg | Decoder | |--------|----------|--------|------|-------|------|--------|---------| | 0 | VecBall | 32 | 2 | 4 | ok | ok | ok | | ... | ... | ... | ... | ... | ... | ... | ... | -## 自动修复 +## Auto Fix -如果校验发现不一致，且属于以下可确定性修复的类型，提示用户是否自动修复： +If validation finds inconsistencies and they are deterministic to fix, ask whether to auto-fix: -1. **ballNum 不匹配** — 自动将 ballNum 更新为 ballIdMappings 数组长度 -2. **ballId 不连续** — 自动重编号为 0, 1, 2, ...（同步更新 DomainDecoder.scala 中的 BID） -3. **busRegister.scala 缺少 case** — 提示缺少哪些 Ball，给出需要添加的 import 和 match case 代码 -4. **DomainDecoder.scala BID 不一致** — 自动更新 BID 值与 default.json 匹配 +1. **`ballNum` mismatch** — update `ballNum` to `ballIdMappings` length +2. **non-contiguous `ballId`** — renumber to `0, 1, 2, ...` (and sync BID in `DomainDecoder.scala`) +3. **missing cases in `busRegister.scala`** — list missing Balls and provide required imports and `match case` entries +4. **BID mismatch in `DomainDecoder.scala`** — update BID values to match `default.json` -对于无法自动修复的问题（如 funct7 冲突），给出原因分析和手动修复建议。 +For non-auto-fixable issues (for example, `funct7` conflicts), provide root-cause analysis and manual fix guidance. diff --git a/.claude/skills/debug/SKILL.md b/.claude/skills/debug/SKILL.md index 62bac63d..87b68a29 100644 --- a/.claude/skills/debug/SKILL.md +++ b/.claude/skills/debug/SKILL.md @@ -1,116 +1,116 @@ --- name: debug -description: 系统性调试 Buckyball 仿真失败。当仿真返回 FAILED、CTest 测试不通过、Chisel 编译报错，或用户报告 Ball 行为异常时使用此 skill。涵盖日志分析、波形分析、常见故障模式匹配。即使用户只是说"仿真失败了"或"跑不过"也应触发。 +description: Systematically debug Buckyball simulation failures. Use this skill when simulation returns FAILED, CTest fails, Chisel compilation errors appear, or users report abnormal Ball behavior. It covers log analysis, waveform analysis, and common failure pattern matching. --- -**重要：编译、仿真等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** +**Important: build and simulation operations must be called through MCP tools. Do not use bbdev CLI or nix develop directly.** -## 第一步 — 定位日志 +## Step 1 - Locate Logs -1. 找到日志目录： - - MCP 工具返回的 JSON 中包含 `log_dir` 字段 - - 如果没有，用 `ls -t arch/log/ | head -5` 找最近的日志目录 -2. 确认关键日志文件存在： - - `stdout.log` — 程序标准输出（PASSED/FAILED、printf） - - `disasm.log` — 反汇编指令流 - - `bdb.log` — Buckyball 硬件调试日志（最重要） - - `bbdev/server.log` — bbdev server 日志（编译错误在这里） +1. Find the log directory: + - MCP tool JSON output includes `log_dir` + - If absent, use `ls -t arch/log/ | head -5` to find recent log dirs +2. Confirm key log files exist: + - `stdout.log` - program stdout (`PASSED`/`FAILED`, `printf`) + - `disasm.log` - disassembled instruction stream + - `bdb.log` - Buckyball hardware debug log (most important) + - `bbdev/server.log` - bbdev server log (compilation errors usually appear here) -## 第二步 — 分层分析 +## Step 2 - Layered Analysis -按照从高层到底层的顺序分析，先排除简单问题： +Analyze from high level to low level, ruling out simple issues first. -### Level 1: 编译错误（bbdev/server.log） +### Level 1: Compilation errors (`bbdev/server.log`) -如果 MCP 工具返回 HTTP 500 或 returncode=1，先看 server.log： -- Chisel 编译错误（类型不匹配、缺少注册等） -- mill 构建错误（依赖问题） -- CTest 编译错误（C 语法、链接问题） +If MCP tools return HTTP 500 or `returncode=1`, inspect `server.log` first: +- Chisel compile errors (type mismatch, missing registration, etc.) +- mill build errors (dependency issues) +- CTest compile errors (C syntax/link errors) -### Level 2: 程序输出（stdout.log） +### Level 2: Program output (`stdout.log`) -- 搜索 `PASSED` / `FAILED` 确认测试结果 -- 搜索 `printf` 输出，检查实际值 vs 预期值 -- 搜索 `panic` / `abort` / `trap` 看是否有异常 +- Search for `PASSED` / `FAILED` to confirm test results +- Search for `printf` outputs and compare actual vs expected values +- Search for `panic` / `abort` / `trap` to detect exceptions -### Level 3: 指令流（disasm.log） +### Level 3: Instruction stream (`disasm.log`) -- 确认 Ball 的 custom 指令确实被执行了（搜索 `custom3`） -- 检查指令顺序是否正确（mvin → ball_op → mvout → fence） -- 检查是否有 trap 或 exception +- Confirm custom Ball instructions were executed (search `custom3`) +- Check instruction order (`mvin -> ball_op -> mvout -> fence`) +- Check for traps or exceptions -### Level 4: 硬件跟踪（bdb.log） +### Level 4: Hardware tracing (`bdb.log`) -这是定位 Ball 逻辑错误最重要的日志，包含三种 trace： +This is the most important log for Ball logic bugs. It contains three traces: -**[ITRACE] 指令 trace：** -- `ISSUE rob_id=X domain=Y funct=0xZZ` — 指令发射 -- `COMPLETE rob_id=X` — 指令完成 -- 检查：指令是否被发射？是否完成？完成顺序是否正确？ +**[ITRACE] instruction trace:** +- `ISSUE rob_id=X domain=Y funct=0xZZ` - instruction issued +- `COMPLETE rob_id=X` - instruction completed +- Check: issued? completed? completion order correct? -**[MTRACE] 内存 trace：** -- `READ ch=X vbank=Y group=Z addr=0xAA` — SRAM 读 -- `WRITE ch=X vbank=Y group=Z addr=0xAA data=0x...` — SRAM 写 -- 检查：读写地址是否正确？数据是否正确？bank_id 是否匹配？ +**[MTRACE] memory trace:** +- `READ ch=X vbank=Y group=Z addr=0xAA` - SRAM read +- `WRITE ch=X vbank=Y group=Z addr=0xAA data=0x...` - SRAM write +- Check: addresses correct? data correct? `bank_id` matches? -**[PMCTRACE] 性能计数 trace：** -- `BALL ball_id=X rob_id=Y elapsed=Z` — Ball 操作耗时 -- `LOAD/STORE rob_id=X elapsed=Y` — 内存操作耗时 -- 检查：elapsed 是否合理？是否有异常长的操作？ +**[PMCTRACE] performance trace:** +- `BALL ball_id=X rob_id=Y elapsed=Z` - Ball operation latency +- `LOAD/STORE rob_id=X elapsed=Y` - memory operation latency +- Check: elapsed reasonable? any unusually long operations? -### Level 5: 波形分析（waveform-mcp） +### Level 5: Waveform analysis (`waveform-mcp`) -如果日志分析无法定位问题，使用 waveform-mcp 做 cycle-level 分析。详见 `/waveform` skill。 +If logs are not enough, use waveform-mcp for cycle-level analysis. See `/waveform` skill. -## 第三步 — 常见故障模式 +## Step 3 - Common Failure Patterns -### 1. Ball 没有响应（cmdResp 永远不 fire） -**症状：** 仿真超时或死锁，bdb.log 中有 ISSUE 但没有 COMPLETE -**原因：** -- FSM 卡在某个状态（检查 state 转移条件） -- SRAM resp.valid 没被处理（忘了 resp.ready := true.B） -- cmdResp.valid 没有被拉高 +### 1. Ball not responding (`cmdResp` never fires) +**Symptoms:** timeout or deadlock; `bdb.log` has `ISSUE` but no `COMPLETE` +**Causes:** +- FSM stuck in a state (check transition conditions) +- `SRAM resp.valid` not consumed (for example, missing `resp.ready := true.B`) +- `cmdResp.valid` never asserted -### 2. 数据全零 -**症状：** CTest 报 FAILED，输出矩阵全是 0 -**原因：** -- 写操作 addr 错误（waddr 没有递增） -- 写操作 mask 全零（忘了设置 mask := 1） -- bank_id 错误（写到了错误的 bank） +### 2. All-zero output data +**Symptoms:** CTest FAILED; output matrix is all zeros +**Causes:** +- write address bug (`waddr` not incremented) +- write mask all zero (for example, forgot `mask := 1`) +- wrong `bank_id` (writes into wrong bank) -### 3. 数据不变（输出 == 输入） -**症状：** CTest 报 FAILED，输出矩阵等于输入矩阵 -**原因：** -- 计算逻辑没有生效（跳过了 compute 状态） -- 读到的数据没有被处理就直接写回了 +### 3. Output unchanged (`output == input`) +**Symptoms:** CTest FAILED; output equals input +**Causes:** +- compute logic not executed (compute state skipped) +- read data written back without processing -### 4. 部分数据错误 -**症状：** CTest 报 FAILED，部分行正确部分行错误 -**原因：** -- iter 次数计算错误（少读/少写了几行） -- 地址偏移量计算错误（行之间的 stride） -- 边界条件处理错误 +### 4. Partial data errors +**Symptoms:** CTest FAILED; some rows correct, others wrong +**Causes:** +- `iter` count miscalculated (missing reads/writes for some rows) +- address offset bug (row stride error) +- boundary condition bug -### 5. SRAM 时序错误 -**症状：** 数据看起来"偏移了一行" -**原因：** -- SRAM 读延迟是 1 cycle，但代码在 req.fire 的同一个 cycle 就取了 resp.bits.data -- 正确做法：req.fire 后等一个 cycle，在下一个 cycle resp.valid 时读取数据 +### 5. SRAM timing error +**Symptoms:** data appears shifted by one row +**Causes:** +- SRAM read latency is 1 cycle, but code reads `resp.bits.data` in the same cycle as `req.fire` +- Correct behavior: wait one cycle and read when `resp.valid` is high -### 6. bank_id 冲突 -**症状：** assertion failure 或数据错乱 -**原因：** -- op1_bank 和 wr_bank 使用了同一个 bank（读写冲突） -- 多个 Ball 同时访问同一个 bank +### 6. `bank_id` conflict +**Symptoms:** assertion failure or corrupted data +**Causes:** +- `op1_bank` and `wr_bank` use the same bank (read/write conflict) +- multiple Balls access the same bank concurrently -### 7. rob_id 不匹配 -**症状：** 指令完成顺序混乱 -**原因：** -- cmdResp.bits.rob_id 没有返回正确的 rob_id -- rob_id 没有在 cmdReq.fire 时被 latch - -## 第四步 — 修复 + 验证 - -1. 结合日志/波形分析定位到的问题，修改 Chisel 源码 -2. 重新通过 MCP 工具编译和仿真验证修复结果 -3. 如果修复引入新问题，回到第二步重新分析 +### 7. `rob_id` mismatch +**Symptoms:** completion order looks incorrect +**Causes:** +- `cmdResp.bits.rob_id` is wrong +- `rob_id` was not latched on `cmdReq.fire` + +## Step 4 - Fix and Verify + +1. Modify Chisel source code based on issues found in logs/waveforms +2. Rebuild and rerun simulation through MCP tools to verify fixes +3. If new failures appear, return to Step 2 and reanalyze diff --git a/.claude/skills/optimize/SKILL.md b/.claude/skills/optimize/SKILL.md index ea59425e..bcef8e19 100644 --- a/.claude/skills/optimize/SKILL.md +++ b/.claude/skills/optimize/SKILL.md @@ -1,116 +1,116 @@ --- name: optimize -description: 分析并优化名为 $ARGUMENTS 的 RTL 模块的延迟和面积。适用于任何 RTL 模块（Ball、MemFrontend、BBus、GlobalROB 等），不限于 Ball 算子。当用户要求优化某个模块的面积、延迟、时序、性能，或说"XX 太大了"、"XX 太慢了"、"分析一下 XX 的面积"时使用此 skill。 +description: Analyze and optimize latency and area for the RTL module named $ARGUMENTS. Applies to any RTL module (Ball, MemFrontend, BBus, GlobalROB, etc.), not limited to Ball operators. --- -**重要：综合、仿真等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** +**Important: synthesis and simulation operations must be invoked through MCP tools. Do not call bbdev CLI or nix develop directly.** -## 阶段 1 — 基线测量 +## Phase 1 - Baseline Measurement -1. 调用 MCP 工具 `bbdev_yosys_synth` 跑 Yosys 综合 + OpenSTA 时序分析 -2. 读取面积报告：`bbdev/api/steps/yosys/log/hierarchy_report.txt`（子模块分解） -3. 读取时序报告：`bbdev/api/steps/yosys/log/timing_report.txt`（关键路径） +1. Run MCP tool `bbdev_yosys_synth` for Yosys synthesis + OpenSTA timing analysis +2. Read area report: `bbdev/api/steps/yosys/log/hierarchy_report.txt` (submodule breakdown) +3. Read timing report: `bbdev/api/steps/yosys/log/timing_report.txt` (critical paths) -### hierarchy_report.txt 解析指引 +### How to parse `hierarchy_report.txt` -报告格式为 Yosys `stat -top` 输出，关键字段： -- `Chip area for module` 行后面是每个子模块的面积分解 -- `Number of cells` — 单元数量 -- `Sequential` — 寄存器面积（flip-flops） -- `Combinational` — 组合逻辑面积 -- 搜索目标模块名定位其层次结构 +This report uses Yosys `stat -top` format. Key fields: +- `Chip area for module` followed by submodule area breakdown +- `Number of cells` - cell count +- `Sequential` - register area (flip-flops) +- `Combinational` - combinational logic area +- search target module name to locate hierarchy -### timing_report.txt 解析指引 +### How to parse `timing_report.txt` -OpenSTA 输出格式： -- `Startpoint:` / `Endpoint:` — 关键路径起止点 -- `Path Delay` — 路径延迟 -- `Slack` — 时序裕量（负值表示违约） -- 搜索目标模块名看是否在关键路径上 +OpenSTA output format: +- `Startpoint:` / `Endpoint:` - critical path endpoints +- `Path Delay` - path delay +- `Slack` - timing margin (negative means violation) +- search target module name to see whether it is on critical paths -### 延迟测量 +### Latency measurement -**如果是 Ball 模块：** -1. 检查仿真 bdb.log 中的 PMC trace 数据（`[PMCTRACE] BALL ball_id=X`），提取 elapsed cycles -2. 如果 CTest 中有 `read_rdcycle()` 计时代码，也可以从 stdout.log 获取 cycle 数 -3. 如果两者都没有，可以用 waveform-mcp 精确测量： - - 用 `find_conditional_events` 找 `cmdReq.valid && cmdReq.ready` 的时刻 - - 用 `find_conditional_events` 找 `cmdResp.valid` 的时刻 - - 两者之差即为操作延迟 +**For Ball modules:** +1. Extract elapsed cycles from PMC traces in `bdb.log` (`[PMCTRACE] BALL ball_id=X`) +2. If CTest uses `read_rdcycle()`, also collect cycle counts from `stdout.log` +3. If neither is available, measure precisely with waveform-mcp: + - find `cmdReq.valid && cmdReq.ready` timestamps via `find_conditional_events` + - find `cmdResp.valid` timestamps + - difference is operation latency -**如果是其他模块：** -1. 用 waveform-mcp 在波形上测量关键操作的 cycle 数 -2. 或在 CTest 中加入 `read_rdcycle()` 前后对比代码 +**For non-Ball modules:** +1. Use waveform-mcp to measure cycle counts of key operations +2. Or add `read_rdcycle()` instrumentation in CTests -## 阶段 2 — 面积分析 +## Phase 2 - Area Analysis -从 hierarchy_report.txt 提取目标模块及其子模块的面积数据： -- 总面积（Chip area） -- Sequential 占比（寄存器面积） -- Combinational 占比（组合逻辑面积） -- 子模块面积排名 +Extract area data for target module and submodules from `hierarchy_report.txt`: +- total area (`Chip area`) +- sequential ratio (register area) +- combinational ratio (logic area) +- submodule area ranking -识别面积大户： -- Sequential 占比高 → 寄存器多，考虑是否可用 SRAM 替代 -- Combinational 占比高 → 逻辑复杂，考虑是否可以简化或共享 +Identify major area contributors: +- high sequential ratio -> many registers; consider SRAM replacement +- high combinational ratio -> complex logic; consider simplification/sharing -对比同类模块面积，找出效率差距。 +Compare with similar modules to identify efficiency gaps. -## 阶段 3 — 时序/延迟分析 +## Phase 3 - Timing/Latency Analysis -1. 从 timing_report.txt 看关键路径是否经过该模块，以及路径延迟 -2. 从 PMC trace 或波形数据看操作延迟（cycle 数） -3. 如果是 Ball 或有 FSM 的模块，读取 Chisel 源码分析 FSM： - - 绘制 FSM 状态转移图 - - 计算每个状态的 cycle 数（最佳/最坏情况） - - 识别瓶颈状态（哪个状态耗时最多） - - 分析 SRAM 读写模式（串行 vs 流水 vs 多端口并行） +1. Check whether critical paths pass through target module and inspect path delays in `timing_report.txt` +2. Measure operation latency from PMC traces or waveform data +3. For Ball/FSM modules, analyze FSM in Chisel source: + - draw FSM state transitions + - estimate cycles per state (best/worst case) + - identify bottleneck states + - analyze SRAM access pattern (serial vs pipelined vs multi-port parallel) -## 阶段 4 — 优化方案 +## Phase 4 - Optimization Proposals -提出可量化的优化方案，每个方案包含： -- 优化手段描述 -- 预期面积变化（参考 hierarchy_report 数据量化） -- 预期延迟变化（cycle 数） -- 预期频率影响 -- trade-off 说明 +Provide quantifiable optimization options. Each option should include: +- optimization method +- expected area delta (quantified from hierarchy report) +- expected latency delta (cycles) +- expected frequency impact +- trade-off explanation -常见优化模式： +Common optimization patterns: -**降延迟**： -- 读写流水化：让写操作和下一轮读操作重叠，面积略增，延迟显著降 -- 多 bank 端口并行读：利用 inBW > 1 同时读多行，面积不变，延迟与端口数成比例降 -- 去中间等待状态：合并不必要的 FSM 状态，面积略降 -- 边读边算：计算嵌入读响应周期，利用 SRAM 1-cycle 延迟的下降沿做计算 +**Reduce latency:** +- read/write pipelining: overlap writes with next-round reads; slight area increase, notable latency drop +- multi-bank parallel read: use `inBW > 1` to read multiple rows concurrently; area stable, latency drops with port count +- remove idle wait states: merge unnecessary FSM states; slight area reduction +- compute while reading: overlap computation with SRAM response timing -**降面积**： -- regArray 改 SRAM：大块寄存器阵列换成 SRAM 端口访问，面积显著降，可能增延迟 -- 共享计算单元：多操作时分复用同一计算单元，面积降，延迟可能增 -- 减少 counter 位宽：根据实际范围缩减位宽，面积微降 +**Reduce area:** +- replace large reg arrays with SRAM accesses; strong area reduction, possible latency increase +- share compute units across operations (time-multiplexing); lower area, possible latency increase +- reduce counter bit-width based on real bounds; small area reduction -**提频率**： -- 拆分组合逻辑长路径：在关键路径中间插入寄存器，面积略增，可能增 1 cycle 延迟 +**Improve frequency:** +- split long combinational paths by adding pipeline regs; slight area increase, possibly +1 cycle latency -列出方案后让用户选择。 +Present options and let the user choose. -## 阶段 5 — 实施 +## Phase 5 - Implementation -根据用户选择的方案修改 Chisel 代码。 +Apply the selected optimization in Chisel code. -## 阶段 6 — 优化后测量 +## Phase 6 - Post-Optimization Measurement -1. 再次调用 `bbdev_yosys_synth`，对比 hierarchy_report -2. 如果有 CTest，再次调用 `bbdev_verilator_run` 跑仿真，对比 PMC trace 中的 cycle 数 -3. 调用 `validate` 确认注册一致性未被破坏 -4. 输出优化前后对比报告： +1. Run `bbdev_yosys_synth` again and compare hierarchy reports +2. If CTest exists, rerun simulation with `bbdev_verilator_run` and compare cycle counts in PMC traces +3. Run `validate` to ensure registration consistency is preserved +4. Output before/after comparison report: -| 指标 | 优化前 | 优化后 | 变化 | +| Metric | Before | After | Delta | |------|--------|--------|------| -| 面积 | X | Y | -Z% | -| Cycle 数 | A | B | -C% | -| 关键路径延迟 | D | E | -F% | +| Area | X | Y | -Z% | +| Cycles | A | B | -C% | +| Critical path delay | D | E | -F% | -## 故障排查 +## Troubleshooting -如果 MCP 工具返回 HTTP 500 或 returncode=1： -- 读取 `bbdev/server.log` 获取详细错误信息 +If MCP tools return HTTP 500 or `returncode=1`: +- read `bbdev/server.log` for detailed error information diff --git a/.claude/skills/verify/SKILL.md b/.claude/skills/verify/SKILL.md index fb34ff41..9b97d14d 100644 --- a/.claude/skills/verify/SKILL.md +++ b/.claude/skills/verify/SKILL.md @@ -1,59 +1,59 @@ --- name: verify -description: 验证名为 $ARGUMENTS 的 Ball 的功能正确性。当用户要求验证、测试某个 Ball，检查 Ball 是否工作正常，或说"验证 XX Ball"、"跑一下 XX 测试"时使用此 skill。也适用于用户新建完 Ball 后想确认其正确性的场景。 +description: Verify functional correctness of the Ball named $ARGUMENTS. Use this skill when users ask to verify/test a Ball, check whether a Ball works correctly, or validate a newly created Ball. --- -**重要：编译、仿真、测试等操作必须通过 MCP 工具调用，禁止直接使用 bbdev CLI 或 nix develop 命令。** +**Important: build, simulation, and test operations must be invoked via MCP tools. Do not call bbdev CLI or nix develop directly.** -## 阶段 1 — 完整性检查 +## Phase 1 - Completeness Check -使用 `/check` 的逻辑检查注册一致性，然后检查以下各项是否存在，缺什么补什么： -1. Ball 实现：`arch/src/main/scala/framework/balldomain/prototype//` 目录是否存在 -2. 注册：`arch/src/main/scala/framework/balldomain/configs/default.json` 中是否有条目 -3. ISA 宏：`bb-tests/workloads/lib/bbhw/isa/` 下对应的 .c 文件 -4. CTest：`bb-tests/workloads/src/CTest/toy/` 下对应的 _test.c 文件 -5. sardine 列表：`bb-tests/sardine/tests/test_ctest.py` 的 ctest_workloads 列表 +Use `/check` logic to validate registration consistency, then ensure all required artifacts exist and fill missing pieces: +1. Ball implementation: `arch/src/main/scala/framework/balldomain/prototype//` +2. Registration entry in `arch/src/main/scala/framework/balldomain/configs/default.json` +3. ISA macro file in `bb-tests/workloads/lib/bbhw/isa/` +4. CTest file in `bb-tests/workloads/src/CTest/toy/` +5. Sardine workload entry in `bb-tests/sardine/tests/test_ctest.py` (`ctest_workloads`) -## 阶段 2 — 编译 + 仿真 +## Phase 2 - Build and Simulate -1. 调用 MCP 工具 `bbdev_workload_build` 编译所有 CTest -2. 调用 MCP 工具 `bbdev_verilator_run` 仿真该 Ball 的 CTest - - binary 名称格式：`ctest__test_singlecore-baremetal` - - 设置 batch=true -3. 如果编译或仿真失败，使用 `/debug` skill 进入调试流程 +1. Run MCP tool `bbdev_workload_build` to build all CTests +2. Run MCP tool `bbdev_verilator_run` for this Ball's CTest + - binary naming format: `ctest__test_singlecore-baremetal` + - set `batch=true` +3. If build/simulation fails, switch to `/debug` flow -## 阶段 3 — 覆盖率分析 +## Phase 3 - Coverage Analysis -1. 调用 MCP 工具 `bbdev_sardine_run`，设置 coverage=true -2. 读取覆盖率报告： - - 行覆盖数据在 `bb-tests/sardine/reports/coverage/annotated/` 下 - - 找到对应 Ball 的文件：grep 搜索 Ball 类名 -3. 分析该 Ball 的 RTL 行覆盖情况： - - 查看未覆盖的行（标记为 `000000`） - - 重点关注 FSM 状态、边界条件、错误路径 -4. 如果覆盖率不足，建议或自动补充测试用例，补充后重新编译和仿真验证 +1. Run MCP tool `bbdev_sardine_run` with `coverage=true` +2. Read coverage reports: + - line coverage data under `bb-tests/sardine/reports/coverage/annotated/` + - locate target Ball file by searching Ball class name +3. Analyze RTL line coverage of the Ball: + - inspect uncovered lines (marked `000000`) + - focus on FSM states, boundary conditions, and error paths +4. If coverage is insufficient, propose or add tests, then rebuild and rerun simulation -## 阶段 4 — PMC 性能分析 +## Phase 4 - PMC Performance Analysis -仿真通过后，读取 bdb.log 中的 PMC trace 数据来分析性能： +After simulation passes, analyze PMC traces from `bdb.log`: -1. 找到日志目录（`ls -t arch/log/ | head -5`） -2. 在 bdb.log 中搜索 `[PMCTRACE] BALL` 条目，提取该 Ball 的 elapsed cycle 数据 -3. 汇总报告： - - 平均 elapsed cycles per task - - 最大/最小 elapsed cycles - - 总调用次数 +1. Locate log directory (`ls -t arch/log/ | head -5`) +2. Search `[PMCTRACE] BALL` entries in `bdb.log` and extract elapsed cycles for the target Ball +3. Summarize: + - average elapsed cycles per task + - max/min elapsed cycles + - total invocation count -## 阶段 5 — 波形分析（仿真失败时） +## Phase 5 - Waveform Analysis (when simulation fails) -如果仿真失败，除了读日志外，还可以用 waveform-mcp 做精确的时序分析。详见 `/waveform` skill。 +If simulation fails, use waveform-mcp for precise timing analysis in addition to logs. See `/waveform`. -关键信号检查清单： -- `cmdReq.valid && cmdReq.ready`（命令握手） -- SRAM `req.valid/ready` 和 `resp.valid`（读写时序） -- FSM state 寄存器（状态转移） -- `cmdResp.valid && cmdResp.fire`（完成握手） +Key signal checklist: +- `cmdReq.valid && cmdReq.ready` (command handshake) +- SRAM `req.valid/ready` and `resp.valid` (read/write timing) +- FSM state register (state transitions) +- `cmdResp.valid && cmdResp.fire` (completion handshake) -## 失败分析 +## Failure Handling -如果仿真结果为 FAILED，使用 `/debug` skill 进行系统性调试。 +If simulation result is FAILED, run `/debug` for systematic troubleshooting. diff --git a/.claude/skills/waveform/SKILL.md b/.claude/skills/waveform/SKILL.md index 82dccfd5..47992724 100644 --- a/.claude/skills/waveform/SKILL.md +++ b/.claude/skills/waveform/SKILL.md @@ -1,34 +1,34 @@ --- name: waveform -description: 使用 waveform-mcp 工具分析 VCD/FST 波形文件，检查 Buckyball 模块的信号时序。当需要做 cycle-level 的时序分析、调试握手协议、检查 FSM 状态转移，或用户要求"看波形"、"分析信号"时使用此 skill。也适用于 `/debug` 和 `/optimize` 中需要波形分析的场景。 +description: Use waveform-mcp tools to analyze VCD/FST waveforms and inspect Buckyball signal timing. Use this skill for cycle-level timing analysis, handshake debugging, FSM transition checks, or whenever waveform-level evidence is needed. --- -## 工具概览 +## Tool Overview -项目配置了 `waveform-mcp` MCP server，提供以下工具： -- `open_waveform(file_path)` — 打开 VCD/FST 文件 -- `list_signals(waveform_id, hierarchy_prefix?, name_pattern?, recursive?)` — 列出信号 -- `read_signal(waveform_id, signal_path, time_index|time_indices)` — 读取信号值 -- `get_signal_info(waveform_id, signal_path)` — 获取信号元数据 -- `find_signal_events(waveform_id, signal_path, start?, end?, limit?)` — 找信号变化 -- `find_conditional_events(waveform_id, condition, start?, end?, limit?)` — 条件搜索 -- `close_waveform(waveform_id)` — 关闭波形 +The project uses `waveform-mcp` with these tools: +- `open_waveform(file_path)` - open a VCD/FST file +- `list_signals(waveform_id, hierarchy_prefix?, name_pattern?, recursive?)` - list signals +- `read_signal(waveform_id, signal_path, time_index|time_indices)` - read signal values +- `get_signal_info(waveform_id, signal_path)` - get signal metadata +- `find_signal_events(waveform_id, signal_path, start?, end?, limit?)` - find signal transitions +- `find_conditional_events(waveform_id, condition, start?, end?, limit?)` - search by condition +- `close_waveform(waveform_id)` - close waveform -## 波形文件位置 +## Waveform File Locations -仿真生成的波形文件通常在： -- `arch/log//` 目录下 -- 文件格式：`.vcd` 或 `.fst` -- 用 `find arch/log -name "*.vcd" -o -name "*.fst" | head -5` 查找 +Waveforms generated by simulation are usually in: +- `arch/log//` +- format: `.vcd` or `.fst` +- use `find arch/log -name "*.vcd" -o -name "*.fst" | head -5` to locate files -## 信号层次结构 +## Signal Hierarchy -Buckyball 的信号层次大致为： +Typical Buckyball signal hierarchy: ``` TOP -├── BuckyballToy (顶层) +├── BuckyballToy (top) │ ├── bbtile (BBTile) -│ │ ├── buckyball (Buckyball 主体) +│ │ ├── buckyball (Buckyball core) │ │ │ ├── frontend │ │ │ │ ├── globalDecoder │ │ │ │ └── globalROB @@ -36,7 +36,7 @@ TOP │ │ │ │ └── bbus (BBus) │ │ │ │ ├── cmdRouter │ │ │ │ ├── pmc (BallCyclePMC) -│ │ │ │ ├── balls_0 (第一个 Ball，按 ballId 排序) +│ │ │ │ ├── balls_0 (first Ball, sorted by ballId) │ │ │ │ ├── balls_1 │ │ │ │ └── ... │ │ │ └── memDomain @@ -44,69 +44,69 @@ TOP │ │ │ └── memBackend ``` -### 定位 Ball 信号 +### Locating Ball Signals -要找到特定 Ball 的信号： -1. `list_signals(waveform_id, recursive=false)` — 先看顶层 -2. 逐级向下：`list_signals(waveform_id, hierarchy_prefix="TOP.BuckyballToy")` 等 -3. 或直接用 `name_pattern` 搜索：`list_signals(waveform_id, name_pattern="relu", recursive=true)` +To locate signals for a specific Ball: +1. `list_signals(waveform_id, recursive=false)` - inspect top level first +2. Drill down with hierarchy prefixes, for example `hierarchy_prefix="TOP.BuckyballToy"` +3. Or search directly by pattern: `list_signals(waveform_id, name_pattern="relu", recursive=true)` -## 常用检查模板 +## Common Check Templates -### 1. 握手检查（Decoupled valid/ready） +### 1. Handshake check (`Decoupled` valid/ready) -检查 cmdReq 握手是否成功： +Check whether `cmdReq` handshakes succeed: ``` find_conditional_events(waveform_id, condition="TOP...cmdReq_valid && TOP...cmdReq_ready") ``` -检查 cmdResp 握手： +Check `cmdResp` handshakes: ``` find_conditional_events(waveform_id, condition="TOP...cmdResp_valid && TOP...cmdResp_ready") ``` -### 2. SRAM 读时序检查 +### 2. SRAM read timing check -验证 SRAM 1-cycle 读延迟： +Verify 1-cycle SRAM read latency: ``` -# 找到读请求 +# Find read request events find_conditional_events(waveform_id, condition="TOP...bankRead_0_io_req_valid && TOP...bankRead_0_io_req_ready") -# 检查下一个 cycle 是否有 resp.valid -# 取上面事件的 time_index + 1，然后 +# Check `resp.valid` in the next cycle +# Use time_index + 1 from request events read_signal(waveform_id, "TOP...bankRead_0_io_resp_valid", time_index=) ``` -### 3. FSM 状态转移追踪 +### 3. FSM transition trace -找 state 寄存器的所有变化： +Find all transitions of the `state` register: ``` find_signal_events(waveform_id, signal_path="TOP...state") ``` -然后读取每个变化点的值来重建状态转移序列。 +Then read values at each transition point to reconstruct state evolution. -### 4. Ball 操作延迟测量 +### 4. Ball operation latency measurement -测量从 cmdReq.fire 到 cmdResp.fire 的 cycle 数： +Measure cycles from `cmdReq.fire` to `cmdResp.fire`: ``` -# 找 cmdReq 握手时刻 +# Find cmdReq handshake timestamps req_events = find_conditional_events(waveform_id, condition="TOP...cmdReq_valid && TOP...cmdReq_ready") -# 找 cmdResp 握手时刻 +# Find cmdResp handshake timestamps resp_events = find_conditional_events(waveform_id, condition="TOP...cmdResp_valid && TOP...cmdResp_ready") -# 对应的 resp - req 即为延迟 +# Matching resp_time - req_time gives latency ``` -### 5. Bank 地址/数据检查 +### 5. Bank address/data check -在某个时刻读取 SRAM 读写的地址和数据： +Read SRAM read/write addresses and data at a specific time: ``` read_signal(waveform_id, "TOP...bankRead_0_io_req_bits_addr", time_index=T) read_signal(waveform_id, "TOP...bankRead_0_io_resp_bits_data", time_index=T+1) @@ -114,26 +114,26 @@ read_signal(waveform_id, "TOP...bankWrite_0_io_req_bits_addr", time_index=T) read_signal(waveform_id, "TOP...bankWrite_0_io_req_bits_data", time_index=T) ``` -## 条件搜索语法 - -`find_conditional_events` 的 condition 支持： -- 信号路径：`TOP.module.signal` -- 位运算：`~`(NOT), `&`(AND), `|`(OR), `^`(XOR) -- 布尔运算：`&&`, `||`, `!` -- 比较：`==`, `!=` -- 位提取：`signal[bit]` 或 `signal[msb:lsb]` -- 前值：`$past(signal)` — 前一个 time_index 的值 -- Verilog 字面量：`4'b0001`, `8'hFF` - -常用 pattern： -- 上升沿：`!$past(TOP.signal) && TOP.signal` -- 下降沿：`$past(TOP.signal) && !TOP.signal` -- 握手：`TOP.valid && TOP.ready` -- 某位为 1：`TOP.flags & 4'b0001` - -## 使用建议 - -1. **先 list_signals 再 read** — 信号路径名可能和 Chisel 源码中的名称略有不同（Chisel 会做 name mangling），先搜索确认 -2. **用 find_conditional_events 而不是逐 cycle read** — 效率差几个数量级 -3. **限制 limit** — 波形可能很长，设置合理的 limit 避免返回过多数据 -4. **用完记得 close_waveform** — 释放内存 +## Conditional Search Syntax + +`find_conditional_events` conditions support: +- signal paths: `TOP.module.signal` +- bitwise operators: `~`(NOT), `&`(AND), `|`(OR), `^`(XOR) +- boolean operators: `&&`, `||`, `!` +- comparisons: `==`, `!=` +- bit slicing: `signal[bit]` or `signal[msb:lsb]` +- previous value: `$past(signal)` - value at previous `time_index` +- Verilog literals: `4'b0001`, `8'hFF` + +Common patterns: +- rising edge: `!$past(TOP.signal) && TOP.signal` +- falling edge: `$past(TOP.signal) && !TOP.signal` +- handshake: `TOP.valid && TOP.ready` +- specific bit set: `TOP.flags & 4'b0001` + +## Usage Tips + +1. **List before read** - signal names may differ from Chisel source due to name mangling +2. **Prefer conditional search over cycle-by-cycle reads** - much faster +3. **Set reasonable limits** - waveforms can be very long +4. **Close waveform when done** - release memory diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/README.md b/arch/src/main/scala/framework/balldomain/prototype/trace/README.md index 21e085ee..713df5fe 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/README.md +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/README.md @@ -1,103 +1,103 @@ -# TraceBall — 调试追踪 Ball +# TraceBall — debug/trace Ball -## 概述 +## Overview -TraceBall 是一个不做计算的特殊 Ball，通过 Buckyball 指令通道提供运行时调试能力。它有两个核心功能： +TraceBall is a non-computing Ball that exposes runtime debug features through the Buckyball instruction channel. It has two main roles: -1. **Cycle Counter（计数器管理）**— 通过指令 set/release 多个独立的 cycle 计数器，用于测量任意代码区间的执行周期 -2. **Bank Backdoor（SRAM 后门读写）**— 通过 DPI-C 注入数据写入 SRAM bank，或读取 SRAM bank 数据通过 DPI-C 输出 +1. **Cycle counter** — set/release multiple independent cycle counters via instructions to measure elapsed cycles over arbitrary code regions +2. **Bank backdoor** — inject data into SRAM banks or read bank data out via DPI-C -所有 DPI-C 接口仅存在于 TraceBall 内部，不影响其他模块。 +All DPI-C hooks live inside TraceBall only and do not affect other modules. --- -## 指令编码 +## Instruction encoding -TraceBall 使用 **两个 funct7 编码**。 +TraceBall uses **two funct7 encodings**. -### 指令 1：`bdb_counter` (funct7 = 48, 0x30) +### Instruction 1: `bdb_counter` (funct7 = 48, 0x30) -Cycle counter 管理。**不访问 SRAM，不需要 bank 端口，1 cycle 完成。** +Cycle counter control. **Does not touch SRAM, needs no bank ports, completes in 1 cycle.** -rs1 布局： -- rs1 = 任意（不使用，不需要设 BB_RD0/BB_WR 标志） +rs1 layout: +- rs1 = don’t care (unused; no need to set BB_RD0/BB_WR) -rs2 布局（64-bit）： +rs2 layout (64-bit): ``` -rs2[3:0] = subcmd 子命令 (0=START, 1=STOP, 2=READ) -rs2[7:4] = ctr_id 计数器编号 (0-15，最多 16 个独立计数器) +rs2[3:0] = subcmd subcommand (0=START, 1=STOP, 2=READ) +rs2[7:4] = ctr_id counter id (0–15, up to 16 independent counters) rs2[63:8] = payload ``` -子命令定义： +Subcommands: -| subcmd | 名称 | 行为 | payload 含义 | -|--------|------|------|-------------| -| 0 | `CTR_START` | 启动计数器 ctr_id，记录当前 cycle 为起始点 | payload = tag（用户自定义标签，会输出到 trace） | -| 1 | `CTR_STOP` | 停止计数器 ctr_id，输出 elapsed cycles 到 DPI-C trace，然后释放计数器 | payload = 忽略 | -| 2 | `CTR_READ` | 读取计数器 ctr_id 当前值（不停止），输出到 DPI-C trace | payload = 忽略 | +| subcmd | name | behavior | payload meaning | +|--------|------|----------|-----------------| +| 0 | `CTR_START` | Start counter `ctr_id`, record current cycle as start | payload = tag (user tag, echoed in trace) | +| 1 | `CTR_STOP` | Stop `ctr_id`, emit elapsed cycles to DPI-C trace, then free the counter | payload = ignored | +| 2 | `CTR_READ` | Read current value of `ctr_id` (does not stop), emit to DPI-C trace | payload = ignored | -DPI-C 输出格式（写入 bdb.log）： +DPI-C trace format (written to bdb.log): ``` [CTRACE] CTR_START ctr=0 tag=0xDEAD cycle=10042 [CTRACE] CTR_STOP ctr=0 tag=0xDEAD elapsed=387 cycle=10429 [CTRACE] CTR_READ ctr=0 current=200 cycle=10242 ``` -### 指令 2：`bdb_backdoor` (funct7 = 49, 0x31) +### Instruction 2: `bdb_backdoor` (funct7 = 49, 0x31) -SRAM 后门读写，**所有参数（bank_id, row, data）由 DPI-C 提供**。**需要 bank 端口（inBW=1, outBW=1）。** +SRAM backdoor read/write; **all parameters (bank_id, row, data) come from DPI-C**. **Requires bank ports (inBW=1, outBW=1).** -rs1 布局： +rs1 layout: ``` -rs1[45] = BB_RD0 读模式：从 DPI-C 获取地址，读 SRAM，输出数据到 DPI-C -rs1[47] = BB_WR 写模式：从 DPI-C 获取地址+数据，写 SRAM -rs1[63:48] = iter 操作次数（0 = 单次，>0 = 循环 iter 次） +rs1[45] = BB_RD0 read: get address from DPI-C, read SRAM, send data to DPI-C +rs1[47] = BB_WR write: get address+data from DPI-C, write SRAM +rs1[63:48] = iter repeat count (0 = once, >0 = loop `iter` times) ``` -rs2 布局： -- rs2 = 任意（不使用） +rs2 layout: +- rs2 = don’t care (unused) -操作模式： +Modes: -| rs1 flag | 行为 | DPI-C 交互 | -|----------|------|-----------| -| BB_RD0 | 读模式 | RTL 调用 `dpi_backdoor_get_read_addr()` 获取 (bank_id, row)，读 SRAM，调用 `dpi_backdoor_put_read_data()` 输出数据 | -| BB_WR | 写模式 | RTL 调用 `dpi_backdoor_get_write_req()` 获取 (bank_id, row, data)，写 SRAM | +| rs1 flag | behavior | DPI-C interaction | +|----------|----------|-------------------| +| BB_RD0 | read | RTL calls `dpi_backdoor_get_read_addr()` for (bank_id, row), reads SRAM, `dpi_backdoor_put_read_data()` for data | +| BB_WR | write | RTL calls `dpi_backdoor_get_write_req()` for (bank_id, row, data), writes SRAM | -DPI-C 输出格式： +DPI-C trace format: ``` [BANK-TRACE] BACKDOOR_READ bank=2 row=5 data=0x00010002000300040005000600070008 [BANK-TRACE] BACKDOOR_WRITE bank=3 row=10 data=0xDEADBEEFDEADBEEFDEADBEEFDEADBEEF ``` -## 使用示例 +## Examples -### 测量算子执行周期 +### Measure kernel cycles ```c -// 测量一次 matmul 的 cycle -bdb_counter_start(0, 0xA001); // 计数器 0，tag=matmul +// One matmul region +bdb_counter_start(0, 0xA001); // counter 0, tag=matmul bb_mul_warp16(A, B, C, 16); bb_fence(); -bdb_counter_stop(0); // 输出 elapsed +bdb_counter_stop(0); // prints elapsed -// 测量嵌套区间 -bdb_counter_start(0, 0xB001); // 外层：整个 conv - bdb_counter_start(1, 0xB002); // 内层：im2col +// Nested regions +bdb_counter_start(0, 0xB001); // outer: whole conv + bdb_counter_start(1, 0xB002); // inner: im2col bb_im2col(...); bb_fence(); bdb_counter_stop(1); - bdb_counter_start(2, 0xB003); // 内层：matmul + bdb_counter_start(2, 0xB003); // inner: matmul bb_mul_warp16(...); bb_fence(); bdb_counter_stop(2); -bdb_counter_stop(0); // 外层结束 +bdb_counter_stop(0); // outer end ``` -bdb.log 输出： +bdb.log sample: ``` [CTRACE] CTR_START ctr=0 tag=0xB001 cycle=0 [CTRACE] CTR_START ctr=1 tag=0xB002 cycle=0 @@ -107,26 +107,23 @@ bdb.log 输出： [CTRACE] CTR_STOP ctr=0 tag=0xB001 elapsed=456 cycle=456 ``` -### SRAM 后门注入测试数据 +### Backdoor test data into SRAM -TraceBall内有一个私有bank，不会被配置看到 +TraceBall has a private bank that is not visible to normal configuration. ```c -// 不走 DMA，直接通过 DPI-C 注入测试数据到 bank 0 -// （C++ 先通过 DPI-C 注入数据到TraceBall内的bank） -bb_alloc(0, 1, 1) -bdb_backdoor_mvin(16); // 注入 16 行到 私有bank -bdb_backdoor_write(0, 16); // 将私有bank的数据 注入 16 行到 bank 0 +// No DMA: inject test data into bank 0 via DPI-C +// (C++ first injects into TraceBall’s internal bank via DPI-C) +bb_alloc(0, 1, 1); +bdb_backdoor_mvin(16); // inject 16 rows into private bank +bdb_backdoor_write(0, 16); // move 16 rows from private bank to bank 0 -// 跑 Transpose bb_transpose(0, 1, 16); -// 检查部分结果 -bdb_backdoor_peek(0, 15); // 检查最后一行 +bdb_backdoor_peek(0, 15); // inspect last row -// 读出全部结果 -bdb_backdoor_read(1, 16); // dump bank 1 的 16 行到 trace +bdb_backdoor_read(1, 16); // dump 16 rows from bank 1 to trace ``` -注意，所有RTL修改都在traceball内部，不允许动外部bank等地方 +All RTL changes stay inside TraceBall; do not modify external banks or shared infrastructure there. diff --git a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala index fbfcab33..88aafc88 100644 --- a/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala +++ b/arch/src/main/scala/framework/frontend/configs/FrontendParam.scala @@ -3,7 +3,7 @@ package framework.frontend.configs import upickle.default._ /** - * Frontend Parameter - 包含前端所有配置 + * Frontend parameters - includes all frontend configuration. */ case class FrontendParam( rob_entries: Int, diff --git a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala index 620b0109..23dff5d1 100644 --- a/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala +++ b/arch/src/main/scala/framework/gpdomain/configs/GpDomainParam.scala @@ -23,7 +23,7 @@ object GpDomainParam { implicit val rw: ReadWriter[GpDomainParam] = macroRW /** - * 从默认的局部JSON文件加载 + * Load from the default local JSON file. */ def apply(): GpDomainParam = { val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/gpdomain/configs/default.json").mkString diff --git a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala index d4df131e..5d53d816 100644 --- a/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala +++ b/arch/src/main/scala/framework/memdomain/frontend/outside_channel/dma/StreamReader.scala @@ -13,7 +13,7 @@ class BBReadRequest extends Bundle { val vaddr = UInt(64.W) val len = UInt(16.W) val status = new MStatus - val stride = UInt(10.W) // 暂时不用 + val stride = UInt(10.W) // currently unused } class BBReadResponse(dataWidth: Int) extends Bundle { diff --git a/bb-tests/sardine/pytest.ini b/bb-tests/sardine/pytest.ini index ec881495..6dc693c8 100644 --- a/bb-tests/sardine/pytest.ini +++ b/bb-tests/sardine/pytest.ini @@ -1,11 +1,11 @@ [pytest] -# 测试发现 +# Test discovery testpaths = tests python_files = test_*.py *_test.py python_classes = Test* python_functions = test_* -# 输出配置 +# Output configuration addopts = -v -s @@ -20,12 +20,12 @@ addopts = --log-file-level=DEBUG --log-cli-level=INFO --capture=no -# Allure 配置（当使用 --allure 时） +# Allure configuration (when using --allure) --alluredir=reports/allure-results --clean-alluredir -# 测试标记定义 +# Test marker definitions markers = smoke: Quick smoke tests verilator: Verilator simulation tests @@ -37,8 +37,8 @@ markers = ctest: CTest tests mlir: MLIR OpTest tests -# 最小版本要求 +# Minimum version requirement minversion = 6.0 -# 测试目录 +# Test directories norecursedirs = .git .tox dist build *.egg .venv diff --git a/bb-tests/sardine/run_tests.py b/bb-tests/sardine/run_tests.py index eb98cc10..2fff978c 100644 --- a/bb-tests/sardine/run_tests.py +++ b/bb-tests/sardine/run_tests.py @@ -46,7 +46,7 @@ def run_pytest(args=None): # Build pytest command cmd = ["python3", "-m", "pytest", "-s", "-v", "-n", "auto"] - # Allure 配置 + # Allure configuration allure_results_dir = reports_dir / "allure-results" allure_results_dir.mkdir(exist_ok=True) cmd.extend(["--alluredir", str(allure_results_dir), "--clean-alluredir"]) diff --git a/bb-tests/sardine/tests/test_ctest.py b/bb-tests/sardine/tests/test_ctest.py index 1470713f..b0d0ac24 100644 --- a/bb-tests/sardine/tests/test_ctest.py +++ b/bb-tests/sardine/tests/test_ctest.py @@ -127,7 +127,7 @@ def test_ctest_workload_debug( command = f'bbdev verilator --sim "--binary {workload_path} --batch{coverage_flag}"' logging.info(f"Running command: {command}") - # 使用 command_run 执行命令，带提前退出检测 + # Run command via command_run with early-exit detection. early_exit_pattern = ( r"Task completed\. Command running on http://localhost:\d+ is finished" ) diff --git a/bb-tests/workloads/src/CTest/toy/relu_test.c b/bb-tests/workloads/src/CTest/toy/relu_test.c index 88490015..d22118f4 100644 --- a/bb-tests/workloads/src/CTest/toy/relu_test.c +++ b/bb-tests/workloads/src/CTest/toy/relu_test.c @@ -5,10 +5,10 @@ #include #include -#define DIM 16 // 强制 16x16 +#define DIM 16 // fixed 16x16 // ======================= -// 固定输入矩阵（4行周期） +// Fixed input matrix (4 cycle pattern) // ======================= static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))) = { // ---- Cycle 1 ---- @@ -40,7 +40,7 @@ static elem_t input_matrix[DIM * DIM] __attribute__((aligned(64))) = { -31, 30, 31, 32, 33, 34, 35, 36, 37, 38}; // ======================= -// 直接写死 ReLU 结果 +// Hardcoded ReLU output // ======================= static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { // ---- Cycle 1 ---- @@ -66,7 +66,7 @@ static elem_t expected_matrix[DIM * DIM] __attribute__((aligned(64))) = { static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); // ======================= -// HW ReLU Flow（保持不变） +// HW ReLU flow (unchanged) // ======================= void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { uint32_t op1_bank_id = 0; @@ -84,7 +84,7 @@ void hw_relu(const char *test_name, elem_t *a, elem_t *b, int size) { } // ======================= -// 测试函数（去掉 CPU 计算） +// Test function (without CPU-side calculation) // ======================= int run_test(const char *test_name, elem_t *a, int size) { clear_i8_matrix(output_matrix, size, size); diff --git a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c index a98bc83d..eff37e5d 100644 --- a/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c +++ b/bb-tests/workloads/src/CTest/toy/vecunit_tiled_matmul.c @@ -21,8 +21,8 @@ static result_t output_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t expected_matrix[DIM * DIM] __attribute__((aligned(64))); static result_t zero_matrix[DIM * DIM] __attribute__((aligned(64))) = {0}; -/// C = A * B with A row-major DIM×KDIM, B row-major KDIM×DIM; K 维按 KTILE -/// 分块累加到 acc。 +/// C = A * B with A row-major DIMxKDIM and B row-major KDIMxDIM; K is tiled by +/// KTILE and accumulated into acc. void hw_matmul_tiled(const char *test_name, elem_t *a, elem_t *b, result_t *c) { (void)test_name; uint32_t op1_bank_id = 0; diff --git a/bebop b/bebop index 9c47331f..9f18f0de 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 9c47331f6da8b52bc85c76aaded49edc5ecfaad1 +Subproject commit 9f18f0dec7a97863fe1eec624144dd48a5ff67ab diff --git a/scripts/claude/README.md b/scripts/claude/README.md index 70c88eec..d489d9c9 100644 --- a/scripts/claude/README.md +++ b/scripts/claude/README.md @@ -1,97 +1,97 @@ # Buckyball Claude Code Workflow -Claude Code 作为交互前端，bbdev 作为执行后端。Claude 通过 MCP Server 调用 bbdev 的 HTTP API（server 模式，自动管理生命周期）。 +Claude Code is the interactive frontend, and bbdev is the execution backend. Claude calls bbdev HTTP APIs through the MCP server (server mode with automatic lifecycle management). -## 三个 Workflow +## Three Workflows -| # | 触发 | 功能 | +| # | Trigger | Function | |---|------|------| -| 1 | `/ball ` | 新建 Ball：实现 → 注册 → ISA 宏 → CTest → 编译 → 仿真验证 | -| 2 | `/verify ` | 验证 Ball：完整性检查 → 补全 → 编译 → 仿真 → 覆盖率分析 | -| 3 | `/optimize ` | 优化 Ball：面积(yosys) + 时序(OpenSTA) + 延迟(仿真cycle) → 优化 → 回归验证 | +| 1 | `/ball ` | Create a new Ball: implementation -> registration -> ISA macro -> CTest -> build -> simulation verification | +| 2 | `/verify ` | Verify a Ball: completeness check -> fill missing parts -> build -> simulation -> coverage analysis | +| 3 | `/optimize ` | Optimize a Ball: area (Yosys) + timing (OpenSTA) + latency (simulation cycles) -> optimize -> regression verification | -## 架构 +## Architecture ``` -用户 ──→ Claude Code (slash commands + CLAUDE.md) +User ──→ Claude Code (slash commands + CLAUDE.md) │ - ├── 读写代码：Read/Edit/Write - ├── 静态校验：MCP validate - └── 编译/仿真/综合/测试：MCP bbdev_* → bbdev HTTP API + ├── Code read/write: Read/Edit/Write + ├── Static validation: MCP validate + └── Build/sim/synth/test: MCP bbdev_* -> bbdev HTTP API │ - └── bbdev server (Motia workflow 后端，MCP 自动管理生命周期) - ├── POST /verilator/run 全流程 clean→verilog→build→sim - ├── POST /verilator/verilog 生成 Verilog（支持 --balltype） - ├── POST /verilator/build 编译 Verilator（支持 --coverage） - ├── POST /verilator/sim 跑仿真（支持 --coverage） - ├── POST /workload/build 编译 CTest - ├── POST /sardine/run 批量测试（支持 --coverage → 覆盖率报告） - └── POST /yosys/synth Yosys 综合 + OpenSTA 时序分析 + └── bbdev server (Motia workflow backend, lifecycle managed by MCP) + ├── POST /verilator/run Full flow: clean->verilog->build->sim + ├── POST /verilator/verilog Generate Verilog (supports --balltype) + ├── POST /verilator/build Build Verilator (supports --coverage) + ├── POST /verilator/sim Run simulation (supports --coverage) + ├── POST /workload/build Build CTest + ├── POST /sardine/run Batch tests (supports --coverage -> coverage report) + └── POST /yosys/synth Yosys synthesis + OpenSTA timing analysis ``` -## 文件清单 +## File List -| 文件 | 说明 | +| File | Description | |------|------| -| `scripts/claude/mcp_server.py` | MCP Server：validate + bbdev API 封装 + server 生命周期管理 | -| `.claude/settings.json` | MCP 配置 | -| `CLAUDE.md` | 全局指令：项目结构、Blink 协议、注册不变量、工具使用 | -| `.claude/commands/ball.md` | `/ball ` 新建 Ball 全流程 | -| `.claude/commands/verify.md` | `/verify ` 验证 Ball | -| `.claude/commands/optimize.md` | `/optimize ` 优化 Ball | -| `.claude/commands/check.md` | `/check` 静态校验 | - -## MCP Server 工具列表 - -### 校验 -| 工具 | 功能 | +| `scripts/claude/mcp_server.py` | MCP server: validate + bbdev API wrappers + server lifecycle management | +| `.claude/settings.json` | MCP configuration | +| `CLAUDE.md` | Global instructions: project structure, Blink protocol, registration invariants, tool usage | +| `.claude/commands/ball.md` | Full flow for creating a Ball via `/ball ` | +| `.claude/commands/verify.md` | Ball verification via `/verify ` | +| `.claude/commands/optimize.md` | Ball optimization via `/optimize ` | +| `.claude/commands/check.md` | Static validation via `/check` | + +## MCP Server Tool List + +### Validation +| Tool | Function | |------|------| -| `validate` | 检查 6 项注册不变量（ballId 递增/funct7 唯一/bid 对齐等） | +| `validate` | Check 6 registration invariants (`ballId` increasing, unique `funct7`, BID alignment, etc.) | -### bbdev API 封装 -| 工具 | API | 说明 | +### bbdev API Wrappers +| Tool | API | Description | |------|-----|------| -| `bbdev_workload_build` | `/workload/build` | 编译 CTest | -| `bbdev_verilator_run` | `/verilator/run` | 全流程 clean→verilog→build→sim | -| `bbdev_verilator_verilog` | `/verilator/verilog` | 生成 Verilog | -| `bbdev_verilator_build` | `/verilator/build` | 编译 Verilator | -| `bbdev_verilator_sim` | `/verilator/sim` | 跑仿真 | -| `bbdev_sardine_run` | `/sardine/run` | 批量测试 | -| `bbdev_yosys_synth` | `/yosys/synth` | Yosys 综合 + OpenSTA | - -## bbdev Server 生命周期 - -MCP Server 自动管理 bbdev server： -- 首次调用 bbdev_* 时自动启动（`pnpm dev --port `） -- 启动前清理 BullMQ AOF 防止重放旧事件 -- 端口从 5100-5500 自动选择 -- 健康检查通过后才返回 -- 每次调用前检查存活，挂了自动重启 -- MCP Server 退出时自动清理 - -## Workflow 详细流程 - -### `/ball ` — 新建 Ball - -1. **需求收集**：读 default.json/DISA.scala 确定 ballId/funct7，问用户功能/inBW/outBW/op2 -2. **实现 Ball**：参考现有 Ball 代码，在 prototype/ 下创建 wrapper/core/config -3. **注册**：更新 default.json + busRegister + DISA + DomainDecoder -4. **ISA 宏**：创建 C 宏文件，更新 isa.h -5. **CTest**：创建测试 .c，注册 CMakeLists.txt，追加 sardine 列表 -6. **验证**：validate → bbdev_workload_build → bbdev_verilator_run → PASS/FAIL - -### `/verify ` — 验证 Ball - -1. **完整性检查**：注册/ISA 宏/CTest/sardine 条目是否完整，缺什么补什么 -2. **编译 + 仿真**：bbdev_workload_build → bbdev_verilator_run -3. **覆盖率分析**：bbdev_sardine_run(coverage=true) → 读覆盖率报告 → 建议补测试 -4. **失败分析**：读仿真 log → 分析 Chisel 代码 → 提修复方案 - -### `/optimize ` — 优化 Ball - -1. **基线测量**：bbdev_yosys_synth（面积+时序）+ bbdev_verilator_run（cycle 数） -2. **面积分析**：从 hierarchy_report 提取子模块面积，识别面积大户 -3. **时序/延迟分析**：timing_report 关键路径 + 仿真 cycle 数 + FSM 源码分析 -4. **优化方案**：量化的方案列表（手段/面积变化/延迟变化/频率影响/trade-off） -5. **实施**：修改 Chisel 代码 -6. **优化后测量**：再跑 yosys + verilator，输出前后对比报告 +| `bbdev_workload_build` | `/workload/build` | Build CTest | +| `bbdev_verilator_run` | `/verilator/run` | Full flow: clean->verilog->build->sim | +| `bbdev_verilator_verilog` | `/verilator/verilog` | Generate Verilog | +| `bbdev_verilator_build` | `/verilator/build` | Build Verilator | +| `bbdev_verilator_sim` | `/verilator/sim` | Run simulation | +| `bbdev_sardine_run` | `/sardine/run` | Batch tests | +| `bbdev_yosys_synth` | `/yosys/synth` | Yosys synthesis + OpenSTA | + +## bbdev Server Lifecycle + +MCP server manages bbdev server automatically: +- Auto-start on first `bbdev_*` call (`pnpm dev --port `) +- Clean BullMQ AOF before startup to avoid replaying stale events +- Auto-select port from 5100-5500 +- Return only after health check passes +- Check liveness before each call, auto-restart if down +- Clean up automatically when MCP server exits + +## Detailed Workflow + +### `/ball ` - Create Ball + +1. **Requirement collection**: read `default.json`/`DISA.scala` to determine `ballId`/`funct7`, then confirm function/inBW/outBW/op2 with user +2. **Implement Ball**: reference existing Ball code and create wrapper/core/config under `prototype/` +3. **Register**: update `default.json` + `busRegister` + `DISA` + `DomainDecoder` +4. **ISA macro**: create C macro file and update `isa.h` +5. **CTest**: create test `.c`, register in `CMakeLists.txt`, append sardine list +6. **Verification**: `validate` -> `bbdev_workload_build` -> `bbdev_verilator_run` -> PASS/FAIL + +### `/verify ` - Verify Ball + +1. **Completeness check**: verify registration/ISA macro/CTest/sardine entries, fill missing parts +2. **Build + simulation**: `bbdev_workload_build` -> `bbdev_verilator_run` +3. **Coverage analysis**: `bbdev_sardine_run(coverage=true)` -> inspect report -> propose extra tests +4. **Failure analysis**: read simulation logs -> analyze Chisel code -> propose fixes + +### `/optimize ` - Optimize Ball + +1. **Baseline measurement**: `bbdev_yosys_synth` (area + timing) + `bbdev_verilator_run` (cycle count) +2. **Area analysis**: extract submodule area from `hierarchy_report`, identify large contributors +3. **Timing/latency analysis**: critical paths in `timing_report` + simulation cycle count + FSM source analysis +4. **Optimization plan**: quantified options (method/area delta/latency delta/frequency impact/trade-off) +5. **Implementation**: modify Chisel code +6. **Post-opt measurement**: rerun Yosys + Verilator and output before/after report From eeadeacaaa83143310d3674c653a7ee47f892a5c Mon Sep 17 00:00:00 2001 From: daiyongyuan <1533208939@qq.com> Date: Wed, 8 Apr 2026 17:05:58 +0800 Subject: [PATCH 198/238] feat(pegasus): add PegasusShell --- arch/build.sc | 6 +- .../src/main/scala/pegasus/PegasusShell.scala | 73 +++++++++++++++++++ bbdev | 2 +- docs | 2 +- 4 files changed, 78 insertions(+), 5 deletions(-) create mode 100644 arch/src/main/scala/pegasus/PegasusShell.scala diff --git a/arch/build.sc b/arch/build.sc index 9c8180f5..6b39bda9 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -10,6 +10,7 @@ import mill.bsp._ object buckyball extends SbtModule { m => override def millSourcePath = os.pwd override def scalaVersion = "2.13.12" + private val hasPegasus = os.exists(os.pwd / os.up / "pegasus" / "chisel") override def scalacOptions = Seq( "-language:reflectiveCalls", @@ -23,9 +24,8 @@ object buckyball extends SbtModule { m => override def moduleDeps = Seq( chipyard, firechip, - palladium, - pegasus - ) + palladium + ) ++ (if (hasPegasus) Seq(pegasus) else Seq.empty) override def ivyDeps = Agg( // ivy"org.chipsalliance::chisel:6.5.0", diff --git a/arch/src/main/scala/pegasus/PegasusShell.scala b/arch/src/main/scala/pegasus/PegasusShell.scala new file mode 100644 index 00000000..94ad4cce --- /dev/null +++ b/arch/src/main/scala/pegasus/PegasusShell.scala @@ -0,0 +1,73 @@ +package pegasus + +import chisel3._ + +class PegasusShell extends Module { + val io = IO(new Bundle { + val pcie_sys_clk = Input(Clock()) + val pcie_sys_clk_gt = Input(Clock()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) + val hbm_ref_clk = Input(Clock()) + + val uart_tx = Input(Bool()) + + val chip_mem_awid = Input(UInt(6.W)) + val chip_mem_awaddr = Input(UInt(33.W)) + val chip_mem_awlen = Input(UInt(8.W)) + val chip_mem_awsize = Input(UInt(3.W)) + val chip_mem_awburst = Input(UInt(2.W)) + val chip_mem_awvalid = Input(Bool()) + val chip_mem_awready = Output(Bool()) + + val chip_mem_wdata = Input(UInt(256.W)) + val chip_mem_wstrb = Input(UInt(32.W)) + val chip_mem_wlast = Input(Bool()) + val chip_mem_wvalid = Input(Bool()) + val chip_mem_wready = Output(Bool()) + + val chip_mem_bid = Output(UInt(6.W)) + val chip_mem_bresp = Output(UInt(2.W)) + val chip_mem_bvalid = Output(Bool()) + val chip_mem_bready = Input(Bool()) + + val chip_mem_arid = Input(UInt(6.W)) + val chip_mem_araddr = Input(UInt(33.W)) + val chip_mem_arlen = Input(UInt(8.W)) + val chip_mem_arsize = Input(UInt(3.W)) + val chip_mem_arburst = Input(UInt(2.W)) + val chip_mem_arvalid = Input(Bool()) + val chip_mem_arready = Output(Bool()) + + val chip_mem_rid = Output(UInt(6.W)) + val chip_mem_rdata = Output(UInt(256.W)) + val chip_mem_rresp = Output(UInt(2.W)) + val chip_mem_rlast = Output(Bool()) + val chip_mem_rvalid = Output(Bool()) + val chip_mem_rready = Input(Bool()) + + val dut_clk = Output(Clock()) + val dut_reset = Output(Bool()) + }) + + io.pcie_exp_txp := 0.U + io.pcie_exp_txn := 0.U + + io.chip_mem_awready := false.B + io.chip_mem_wready := false.B + io.chip_mem_bid := 0.U + io.chip_mem_bresp := 0.U + io.chip_mem_bvalid := false.B + io.chip_mem_arready := false.B + io.chip_mem_rid := 0.U + io.chip_mem_rdata := 0.U + io.chip_mem_rresp := 0.U + io.chip_mem_rlast := false.B + io.chip_mem_rvalid := false.B + + io.dut_clk := io.pcie_sys_clk + io.dut_reset := !io.pcie_sys_rst_n +} diff --git a/bbdev b/bbdev index b5cc63c8..8fae4219 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit b5cc63c8de7953984a7969c278f175c90a1d2b37 +Subproject commit 8fae421972381c16fb66ab82192102245541a3f9 diff --git a/docs b/docs index 1f006478..597d0cd9 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 1f00647846612b9bb92d6f9eda31050b34aa82fd +Subproject commit 597d0cd91dbbfc9e9de338ae00f7e7384ae925a9 From 96cd4daba4481dc0bb1421ddb82a55b0acda4ed2 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 14 Apr 2026 01:18:07 +0800 Subject: [PATCH 199/238] [pegasus] feat: add Pegasus submodule to test on au280 --- .gitmodules | 3 + arch/build.sc | 4 +- arch/scripts/bdb_ndjson_annotate.py | 78 ------ arch/scripts/bdb_ndjson_viz.py | 245 ------------------ .../src/main/scala/pegasus/PegasusShell.scala | 73 ------ .../sims/pegasus/PegasusHarnessBinders.scala | 1 - .../main/scala/sims/pegasus/PegasusTop.scala | 145 +++++++++++ bbdev | 2 +- docs | 2 +- thirdparty/pegasus | 1 + 10 files changed, 153 insertions(+), 401 deletions(-) delete mode 100644 arch/scripts/bdb_ndjson_annotate.py delete mode 100644 arch/scripts/bdb_ndjson_viz.py delete mode 100644 arch/src/main/scala/pegasus/PegasusShell.scala create mode 100644 arch/src/main/scala/sims/pegasus/PegasusTop.scala create mode 160000 thirdparty/pegasus diff --git a/.gitmodules b/.gitmodules index 8c0ac899..844a0b02 100644 --- a/.gitmodules +++ b/.gitmodules @@ -29,3 +29,6 @@ [submodule "thirdparty/edein"] path = thirdparty/edein url = https://github.com/DangoSys/Edein.git +[submodule "thirdparty/pegasus"] + path = thirdparty/pegasus + url = https://github.com/DangoSys/pegasus.git diff --git a/arch/build.sc b/arch/build.sc index 6b39bda9..42dc2e15 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -10,7 +10,7 @@ import mill.bsp._ object buckyball extends SbtModule { m => override def millSourcePath = os.pwd override def scalaVersion = "2.13.12" - private val hasPegasus = os.exists(os.pwd / os.up / "pegasus" / "chisel") + private val hasPegasus = os.exists(os.pwd / os.up / "thirdparty" / "pegasus" / "chisel") override def scalacOptions = Seq( "-language:reflectiveCalls", @@ -969,7 +969,7 @@ object palladium extends SbtModule { // Pure Chisel only — no Chipyard dependency (avoids circular dep with buckyball) // buckyball depends on pegasus (one-way) object pegasus extends SbtModule { - override def millSourcePath = os.pwd / os.up / "pegasus" / "chisel" + override def millSourcePath = os.pwd / os.up / "thirdparty" / "pegasus" / "chisel" override def scalaVersion = "2.13.12" override def ivyDeps = Agg( diff --git a/arch/scripts/bdb_ndjson_annotate.py b/arch/scripts/bdb_ndjson_annotate.py deleted file mode 100644 index eeaa1df4..00000000 --- a/arch/scripts/bdb_ndjson_annotate.py +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/env python3 -""" -Lookup instruction name by funct id. - -Example: - python3 arch/scripts/bdb_ndjson_annotate.py 0x20 -""" - -from __future__ import annotations - -import argparse -import re -from pathlib import Path -from typing import Any - -FILE_RE = re.compile(r"^(\d+)_([a-z0-9_]+)\.c$") - - -def parse_funct_id(v: Any) -> int: - try: - if isinstance(v, int): - return v - if isinstance(v, str): - return int(v, 0) - except ValueError as e: - raise SystemExit(f"invalid funct id: {v!r}") from e - raise SystemExit(f"invalid funct id type: {type(v)}") - - -def build_funct_map(isa_dir: Path) -> dict[int, str]: - if not isa_dir.is_dir(): - raise SystemExit(f"ISA dir not found: {isa_dir}") - mp: dict[int, str] = {} - for p in isa_dir.glob("*.c"): - m = FILE_RE.match(p.name) - if not m: - continue - fid = int(m.group(1)) - name = m.group(2) - mp[fid] = name - if not mp: - raise SystemExit(f"no ISA funct mapping found under: {isa_dir}") - return mp - - -def resolve_funct_name(fid: int, funct_map: dict[int, str]) -> str: - if fid not in funct_map: - raise SystemExit(f"unknown funct id: 0x{fid:x}") - return funct_map[fid] - - -def default_isa_dir() -> Path: - return ( - Path(__file__).resolve().parents[2] - / "bb-tests" - / "workloads" - / "lib" - / "bbhw" - / "isa" - ) - - -def main() -> None: - p = argparse.ArgumentParser(description="Lookup instruction name by funct id") - p.add_argument("funct_id", help="funct id, e.g. 0x20 or 32") - p.add_argument( - "--isa-dir", type=Path, default=default_isa_dir(), help="ISA macro dir" - ) - args = p.parse_args() - - fid = parse_funct_id(args.funct_id) - fmap = build_funct_map(args.isa_dir) - name = resolve_funct_name(fid, fmap) - print(name) - - -if __name__ == "__main__": - main() diff --git a/arch/scripts/bdb_ndjson_viz.py b/arch/scripts/bdb_ndjson_viz.py deleted file mode 100644 index 4fb2406f..00000000 --- a/arch/scripts/bdb_ndjson_viz.py +++ /dev/null @@ -1,245 +0,0 @@ -#!/usr/bin/env python3 -""" -Parse BDB NDJSON trace and draw a single RoB-state figure. - -Only itrace issue->complete intervals are plotted. -Idle gaps (no RoB active) are not shown. - -Requires: matplotlib (pip install matplotlib) -""" - -from __future__ import annotations - -import argparse -import json -from pathlib import Path -from typing import Any - -from bdb_ndjson_annotate import build_funct_map, default_isa_dir, parse_funct_id - - -def load_records(path: Path) -> list[dict[str, Any]]: - rows: list[dict[str, Any]] = [] - with path.open(encoding="utf-8", errors="replace") as f: - for i, line in enumerate(f, 1): - line = line.strip() - if not line: - continue - try: - rows.append(json.loads(line)) - except json.JSONDecodeError as e: - raise SystemExit(f"{path}:{i}: invalid JSON: {e}") from e - return rows - - -def clk_of(rec: dict[str, Any], fallback: int | None) -> int | None: - if "clk" in rec: - return int(rec["clk"]) - return fallback - - -def build_rob_intervals( - records: list[dict[str, Any]], -) -> tuple[list[tuple[int, int, int, int, str]], list[tuple[int, int, int, int]], bool]: - """ - Build RoB intervals from itrace events. - Returns: - - active windows: issue->complete (t0, t1, domain_id, rob_id, funct_label) - - in-rob windows: alloc->complete (t0, t1, domain_id, rob_id) - - used_real_clk - """ - fmap = build_funct_map(default_isa_dir()) - issue_open: dict[tuple[int, int], tuple[int, str]] = {} - alloc_open: dict[tuple[int, int], int] = {} - active_out: list[tuple[int, int, int, int, str]] = [] - inrob_out: list[tuple[int, int, int, int]] = [] - used_clk = False - seq = 0 - - for rec in records: - if rec.get("type") != "itrace": - seq += 1 - continue - - ev = str(rec.get("event", "")) - dom = int(rec.get("domain_id", 0)) - rid = int(rec.get("rob_id", -1)) - if rid < 0: - seq += 1 - continue - t = clk_of(rec, seq) - if t is None: - t = seq - else: - used_clk = True - - key = (dom, rid) - funct_lbl = "" - if "funct" in rec: - try: - fid = parse_funct_id(rec["funct"]) - funct_lbl = fmap.get(fid, f"0x{fid:x}") - except SystemExit: - funct_lbl = str(rec["funct"]) - - if ev == "alloc": - alloc_open[key] = int(t) - elif ev == "issue": - issue_open[key] = (int(t), funct_lbl) - elif ev == "complete": - if key in issue_open: - t0, flbl = issue_open.pop(key) - t1 = int(t) - if t1 < t0: - t0, t1 = t1, t0 - if t1 == t0: - t1 += 1 - active_out.append((t0, t1, dom, rid, flbl)) - if key in alloc_open: - t0 = alloc_open.pop(key) - t1 = int(t) - if t1 < t0: - t0, t1 = t1, t0 - if t1 == t0: - t1 += 1 - inrob_out.append((t0, t1, dom, rid)) - seq += 1 - - return active_out, inrob_out, used_clk - - -def plot_timeline( - records: list[dict[str, Any]], - path: Path, - out_path: Path | None, - show: bool, -) -> None: - try: - import matplotlib.pyplot as plt - except ImportError as e: - raise SystemExit("matplotlib is required: pip install matplotlib") from e - - if not records: - raise SystemExit("empty trace") - - rob_itv, inrob_itv, used_clk = build_rob_intervals(records) - if not rob_itv and not inrob_itv: - raise SystemExit("no itrace issue/complete pairs found") - all_t0: list[int] = [] - all_t1: list[int] = [] - if rob_itv: - all_t0.extend(t0 for t0, _, _, _, _ in rob_itv) - all_t1.extend(t1 for _, t1, _, _, _ in rob_itv) - if inrob_itv: - all_t0.extend(t0 for t0, _, _, _ in inrob_itv) - all_t1.extend(t1 for _, t1, _, _ in inrob_itv) - g0 = min(all_t0) - g1 = max(all_t1) - if g1 <= g0: - g1 = g0 + 1 - - fig, ax = plt.subplots(1, 1, figsize=(14, 6)) - rows = sorted( - {(dom, rid) for _, _, dom, rid, _ in rob_itv} - | {(dom, rid) for _, _, dom, rid in inrob_itv} - ) - y_of = {k: i for i, k in enumerate(rows)} - - # Draw in-ROB occupancy (alloc->complete) as light gray background. - for t0, t1, dom, rid in inrob_itv: - y = y_of[(dom, rid)] - ax.barh( - y, - width=t1 - t0, - left=t0, - height=0.80, - color="#d9d9d9", - alpha=0.55, - edgecolor="none", - zorder=0, - ) - - for t0, t1, dom, rid, flbl in rob_itv: - y = y_of[(dom, rid)] - ax.vlines( - t0, - ymin=-0.5, - ymax=y, - colors="0.45", - linestyles="-", - linewidth=0.6, - alpha=0.6, - zorder=1, - ) - ax.barh( - y, - width=t1 - t0, - left=t0, - height=0.65, - color=f"C{dom % 10}", - alpha=0.9, - edgecolor="black", - linewidth=0.3, - zorder=2, - ) - if (t1 - t0) > 10 and flbl: - ax.text( - (t0 + t1) * 0.5, - y, - flbl, - ha="center", - va="center", - fontsize=7, - color="white", - zorder=3, - ) - - ax.set_xlim(g0, g1) - ax.set_yticks(range(len(rows))) - ax.set_yticklabels([f"d{dom}:r{rid}" for dom, rid in rows], fontsize=8) - ax.set_xlabel("clk" if used_clk else "record order") - ax.set_ylabel("RoB entry (active only)") - title_clk = "harness clk" if used_clk else "fallback order index" - ax.set_title(f"RoB active timeline — {path.name} ({title_clk})") - - plt.tight_layout() - if out_path: - out_path.parent.mkdir(parents=True, exist_ok=True) - fig.savefig(out_path, dpi=150, bbox_inches="tight") - if show: - plt.show() - else: - plt.close(fig) - - -def main() -> None: - p = argparse.ArgumentParser(description="Parse and visualize BDB NDJSON trace") - p.add_argument("ndjson", type=Path, help="Path to bdb.ndjson") - p.add_argument( - "-o", - "--output", - type=Path, - default=None, - help="Output PNG path (default: .timeline.png if not --show-only)", - ) - p.add_argument( - "--show", - action="store_true", - help="Open interactive window (requires display)", - ) - args = p.parse_args() - - if not args.ndjson.is_file(): - raise SystemExit(f"not a file: {args.ndjson}") - - records = load_records(args.ndjson) - - out = args.output - if out is None and not args.show: - out = args.ndjson.with_suffix(".timeline.png") - - plot_timeline(records, args.ndjson, out, args.show) - - -if __name__ == "__main__": - main() diff --git a/arch/src/main/scala/pegasus/PegasusShell.scala b/arch/src/main/scala/pegasus/PegasusShell.scala deleted file mode 100644 index 94ad4cce..00000000 --- a/arch/src/main/scala/pegasus/PegasusShell.scala +++ /dev/null @@ -1,73 +0,0 @@ -package pegasus - -import chisel3._ - -class PegasusShell extends Module { - val io = IO(new Bundle { - val pcie_sys_clk = Input(Clock()) - val pcie_sys_clk_gt = Input(Clock()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) - val hbm_ref_clk = Input(Clock()) - - val uart_tx = Input(Bool()) - - val chip_mem_awid = Input(UInt(6.W)) - val chip_mem_awaddr = Input(UInt(33.W)) - val chip_mem_awlen = Input(UInt(8.W)) - val chip_mem_awsize = Input(UInt(3.W)) - val chip_mem_awburst = Input(UInt(2.W)) - val chip_mem_awvalid = Input(Bool()) - val chip_mem_awready = Output(Bool()) - - val chip_mem_wdata = Input(UInt(256.W)) - val chip_mem_wstrb = Input(UInt(32.W)) - val chip_mem_wlast = Input(Bool()) - val chip_mem_wvalid = Input(Bool()) - val chip_mem_wready = Output(Bool()) - - val chip_mem_bid = Output(UInt(6.W)) - val chip_mem_bresp = Output(UInt(2.W)) - val chip_mem_bvalid = Output(Bool()) - val chip_mem_bready = Input(Bool()) - - val chip_mem_arid = Input(UInt(6.W)) - val chip_mem_araddr = Input(UInt(33.W)) - val chip_mem_arlen = Input(UInt(8.W)) - val chip_mem_arsize = Input(UInt(3.W)) - val chip_mem_arburst = Input(UInt(2.W)) - val chip_mem_arvalid = Input(Bool()) - val chip_mem_arready = Output(Bool()) - - val chip_mem_rid = Output(UInt(6.W)) - val chip_mem_rdata = Output(UInt(256.W)) - val chip_mem_rresp = Output(UInt(2.W)) - val chip_mem_rlast = Output(Bool()) - val chip_mem_rvalid = Output(Bool()) - val chip_mem_rready = Input(Bool()) - - val dut_clk = Output(Clock()) - val dut_reset = Output(Bool()) - }) - - io.pcie_exp_txp := 0.U - io.pcie_exp_txn := 0.U - - io.chip_mem_awready := false.B - io.chip_mem_wready := false.B - io.chip_mem_bid := 0.U - io.chip_mem_bresp := 0.U - io.chip_mem_bvalid := false.B - io.chip_mem_arready := false.B - io.chip_mem_rid := 0.U - io.chip_mem_rdata := 0.U - io.chip_mem_rresp := 0.U - io.chip_mem_rlast := false.B - io.chip_mem_rvalid := false.B - - io.dut_clk := io.pcie_sys_clk - io.dut_reset := !io.pcie_sys_rst_n -} diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala index bbfdd12a..3cd2896b 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala @@ -83,7 +83,6 @@ class WithPegasusHarness new chipyard.harness.WithTieOffL2FBusAXI ++ new chipyard.harness.WithClockFromHarness ++ new chipyard.harness.WithResetFromHarness ++ - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ new chipyard.iobinders.WithNMITiedOff diff --git a/arch/src/main/scala/sims/pegasus/PegasusTop.scala b/arch/src/main/scala/sims/pegasus/PegasusTop.scala new file mode 100644 index 00000000..feb39953 --- /dev/null +++ b/arch/src/main/scala/sims/pegasus/PegasusTop.scala @@ -0,0 +1,145 @@ +package sims.pegasus + +import chisel3._ +import chisel3.util.HasBlackBoxInline + +import pegasus.PegasusShell + +// PegasusTop — Vivado bitstream top-level for AU280 bring-up. +// Inline Verilog BlackBox that connects PegasusShell (XDMA) to DigitalTop (SoC). +// Skips ChipTop/PegasusHarness harness layers entirely — no simulation primitives. +class PegasusTop extends BlackBox with HasBlackBoxInline { + + val io = IO(new Bundle { + val pcie_sys_clk = Input(Clock()) + val pcie_sys_clk_gt = Input(Clock()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) + val hbm_ref_clk = Input(Clock()) + val uart_txd = Output(Bool()) + }) + + setInline( + "PegasusTop.v", + """module PegasusTop( + | input pcie_sys_clk, + | input pcie_sys_clk_gt, + | input pcie_sys_rst_n, + | output [15:0] pcie_exp_txp, + | output [15:0] pcie_exp_txn, + | input [15:0] pcie_exp_rxp, + | input [15:0] pcie_exp_rxn, + | input hbm_ref_clk, + | output uart_txd + |); + | + | wire soc_clk; + | wire soc_reset; + | + | PegasusShell shell ( + | .pcie_sys_clk (pcie_sys_clk), + | .pcie_sys_clk_gt (pcie_sys_clk_gt), + | .pcie_sys_rst_n (pcie_sys_rst_n), + | .pcie_exp_txp (pcie_exp_txp), + | .pcie_exp_txn (pcie_exp_txn), + | .pcie_exp_rxp (pcie_exp_rxp), + | .pcie_exp_rxn (pcie_exp_rxn), + | .hbm_ref_clk (hbm_ref_clk), + | .dut_clk (soc_clk), + | .dut_reset (soc_reset), + | .uart_tx (1'b1), + | .chip_mem_awid(6'h0), .chip_mem_awaddr(33'h0), .chip_mem_awlen(8'h0), + | .chip_mem_awsize(3'h0), .chip_mem_awburst(2'h0), .chip_mem_awvalid(1'b0), + | .chip_mem_wdata(256'h0), .chip_mem_wstrb(32'h0), + | .chip_mem_wlast(1'b0), .chip_mem_wvalid(1'b0), .chip_mem_bready(1'b0), + | .chip_mem_arid(6'h0), .chip_mem_araddr(33'h0), .chip_mem_arlen(8'h0), + | .chip_mem_arsize(3'h0), .chip_mem_arburst(2'h0), .chip_mem_arvalid(1'b0), + | .chip_mem_rready(1'b0) + | ); + | + | DigitalTop soc ( + | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (soc_clk), + | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset (soc_reset), + | .resetctrl_hartIsInReset_0 (soc_reset), + | .debug_clock (soc_clk), + | .debug_reset (soc_reset), + | .debug_systemjtag_reset (soc_reset), + | .debug_systemjtag_jtag_TCK (1'b0), + | .debug_systemjtag_jtag_TMS (1'b1), + | .debug_systemjtag_jtag_TDI (1'b1), + | .debug_dmactiveAck (1'b0), + | .uart_0_txd (uart_txd), + | .uart_0_rxd (1'b1), + | .mem_axi4_0_aw_ready (1'b0), + | .mem_axi4_0_w_ready (1'b0), + | .mem_axi4_0_b_valid (1'b0), + | .mem_axi4_0_b_bits_id (4'h0), + | .mem_axi4_0_b_bits_resp (2'h0), + | .mem_axi4_0_ar_ready (1'b0), + | .mem_axi4_0_r_valid (1'b0), + | .mem_axi4_0_r_bits_id (4'h0), + | .mem_axi4_0_r_bits_data (64'h0), + | .mem_axi4_0_r_bits_resp (2'h0), + | .mem_axi4_0_r_bits_last (1'b0), + | .mmio_axi4_0_aw_ready (1'b0), + | .mmio_axi4_0_w_ready (1'b0), + | .mmio_axi4_0_b_valid (1'b0), + | .mmio_axi4_0_b_bits_id (4'h0), + | .mmio_axi4_0_b_bits_resp (2'h0), + | .mmio_axi4_0_ar_ready (1'b0), + | .mmio_axi4_0_r_valid (1'b0), + | .mmio_axi4_0_r_bits_id (4'h0), + | .mmio_axi4_0_r_bits_data (64'h0), + | .mmio_axi4_0_r_bits_resp (2'h0), + | .mmio_axi4_0_r_bits_last (1'b0), + | .serial_tl_0_in_valid (1'b0), + | .serial_tl_0_in_bits_phit (32'h0), + | .serial_tl_0_out_ready (1'b0), + | .serial_tl_0_clock_in (1'b0), + | .custom_boot (1'b0) + | ); + | + |endmodule + |""".stripMargin + ) +} + +object ElaboratePegasusTop extends App { + import _root_.circt.stage.ChiselStage + + // PegasusTop is a BlackBox with inline Verilog — wrap in a thin RawModule to elaborate + class PegasusTopWrapper extends RawModule { + + val io = IO(new Bundle { + val pcie_sys_clk = Input(Clock()) + val pcie_sys_clk_gt = Input(Clock()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) + val hbm_ref_clk = Input(Clock()) + val uart_txd = Output(Bool()) + }) + + val top = Module(new PegasusTop) + top.io.pcie_sys_clk := io.pcie_sys_clk + top.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt + top.io.pcie_sys_rst_n := io.pcie_sys_rst_n + top.io.pcie_exp_rxp := io.pcie_exp_rxp + top.io.pcie_exp_rxn := io.pcie_exp_rxn + io.pcie_exp_txp := top.io.pcie_exp_txp + io.pcie_exp_txn := top.io.pcie_exp_txn + top.io.hbm_ref_clk := io.hbm_ref_clk + io.uart_txd := top.io.uart_txd + } + + ChiselStage.emitSystemVerilogFile( + new PegasusTopWrapper, + firtoolOpts = args, + args = Array.empty + ) +} diff --git a/bbdev b/bbdev index 8fae4219..0a7ee0a4 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 8fae421972381c16fb66ab82192102245541a3f9 +Subproject commit 0a7ee0a4b325ff77a2bed36e68462c7f72b532ac diff --git a/docs b/docs index 597d0cd9..1f006478 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 597d0cd91dbbfc9e9de338ae00f7e7384ae925a9 +Subproject commit 1f00647846612b9bb92d6f9eda31050b34aa82fd diff --git a/thirdparty/pegasus b/thirdparty/pegasus new file mode 160000 index 00000000..aaaac6b9 --- /dev/null +++ b/thirdparty/pegasus @@ -0,0 +1 @@ +Subproject commit aaaac6b9cb2ba07cefb720cc96f08a8a2342bc89 From 860f09da11541f19ef07d634db753df3a6e3cec7 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 14 Apr 2026 01:34:23 +0800 Subject: [PATCH 200/238] [repo] del: remove unused submodules --- .gitmodules | 6 ------ arch/thirdparty/t1 | 1 - thirdparty/circt | 1 - 3 files changed, 8 deletions(-) delete mode 160000 arch/thirdparty/t1 delete mode 160000 thirdparty/circt diff --git a/.gitmodules b/.gitmodules index 844a0b02..7db79403 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,15 +1,9 @@ -[submodule "thirdparty/circt"] - path = thirdparty/circt - url = https://github.com/llvm/circt.git [submodule "arch/thirdparty/chipyard"] path = arch/thirdparty/chipyard url = https://github.com/ucb-bar/chipyard.git [submodule "compiler"] path = compiler url = https://github.com/DangoSys/bb-compiler.git -[submodule "arch/thirdparty/t1"] - path = arch/thirdparty/t1 - url = https://github.com/DangoSys/t1.git [submodule "bbdev"] path = bbdev url = https://github.com/DangoSys/bbdev.git diff --git a/arch/thirdparty/t1 b/arch/thirdparty/t1 deleted file mode 160000 index 07c71ebd..00000000 --- a/arch/thirdparty/t1 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 07c71ebd150aa4cbcd5968a5949413829a7a3f71 diff --git a/thirdparty/circt b/thirdparty/circt deleted file mode 160000 index faf237a5..00000000 --- a/thirdparty/circt +++ /dev/null @@ -1 +0,0 @@ -Subproject commit faf237a581e194823cedc586c36ee9bfeaae0838 From d62c556f5c9e191079579df581269eed56b3d8bb Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 14 Apr 2026 01:50:01 +0800 Subject: [PATCH 201/238] [nix] fix: add missing system utilities (rsync, nodejs) to build environment --- flake.nix | 4 ++++ scripts/nix/build-env-system.nix | 6 ++++++ scripts/nix/overlay.nix | 1 + 3 files changed, 11 insertions(+) create mode 100644 scripts/nix/build-env-system.nix diff --git a/flake.nix b/flake.nix index 3ede8364..d235760a 100644 --- a/flake.nix +++ b/flake.nix @@ -77,6 +77,10 @@ doc.mdbook-pdf doc.mdbook-toc doc.mdbook-mermaid + + # System utilities + systemTools.rsync + systemTools.nodejs ]; }; diff --git a/scripts/nix/build-env-system.nix b/scripts/nix/build-env-system.nix new file mode 100644 index 00000000..bc5a34e6 --- /dev/null +++ b/scripts/nix/build-env-system.nix @@ -0,0 +1,6 @@ +{ pkgs }: + +{ + rsync = pkgs.rsync; + nodejs = pkgs.nodejs; +} diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 90bd8b39..9085b968 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -8,5 +8,6 @@ final: prev: python = final.callPackage ./build-env-python.nix { }; riscv = final.callPackage ./build-env-riscv.nix { }; scala = final.callPackage ./build-env-scala.nix { }; + systemTools = final.callPackage ./build-env-system.nix { }; tools = final.callPackage ./build-env-tools.nix { }; } From 52629d9b2d1d17518bc9481ab8c82c474ada2e40 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 14 Apr 2026 04:36:42 +0800 Subject: [PATCH 202/238] [workflow] feat: add bluefolk --- .gitmodules | 3 +++ arch/.gitignore | 2 +- bbdev | 2 +- bluefolk | 1 + 4 files changed, 6 insertions(+), 2 deletions(-) create mode 160000 bluefolk diff --git a/.gitmodules b/.gitmodules index 7db79403..28f0c9f9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,3 +26,6 @@ [submodule "thirdparty/pegasus"] path = thirdparty/pegasus url = https://github.com/DangoSys/pegasus.git +[submodule "bluefolk"] + path = bluefolk + url = https://github.com/DangoSys/bluefolk.git diff --git a/arch/.gitignore b/arch/.gitignore index c3be7247..1c604c0d 100644 --- a/arch/.gitignore +++ b/arch/.gitignore @@ -15,4 +15,4 @@ build/ log/ -.kiro/ +*.sv diff --git a/bbdev b/bbdev index 0a7ee0a4..1dd8274c 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 0a7ee0a4b325ff77a2bed36e68462c7f72b532ac +Subproject commit 1dd8274c6e4ab949db69378460a8eb6f633ca6e0 diff --git a/bluefolk b/bluefolk new file mode 160000 index 00000000..ddd60509 --- /dev/null +++ b/bluefolk @@ -0,0 +1 @@ +Subproject commit ddd6050947b647c701b509a35535aea11d82bf5a From 6003106f4de0d610607c6c0dde75cf221f2dd7ed Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 15 Apr 2026 01:57:02 +0800 Subject: [PATCH 203/238] [pegasus] feat: add linux kernel build step del: split edein and bluefolk to alternate repo --- .github/workflows/test.yml | 2 +- .gitignore | 2 +- .gitmodules | 15 +++++++++------ bb-tests/thirdparty/busybox | 1 + bb-tests/thirdparty/linux | 1 + bb-tests/workloads/lib/CMakeLists.txt | 3 +-- bb-tests/workloads/lib/kernel | 1 + bebop | 2 +- bluefolk | 1 - flake.nix | 6 ++++++ scripts/nix/build-all.sh | 6 ++++++ scripts/nix/build-env-kernel.nix | 7 +++++++ scripts/nix/build-env-python.nix | 5 +++++ scripts/nix/build-env-riscv.nix | 17 ++++++++++++----- scripts/nix/overlay.nix | 1 + thirdparty/edein | 1 - thirdparty/pegasus | 2 +- 17 files changed, 54 insertions(+), 19 deletions(-) create mode 160000 bb-tests/thirdparty/busybox create mode 160000 bb-tests/thirdparty/linux create mode 160000 bb-tests/workloads/lib/kernel delete mode 160000 bluefolk create mode 100644 scripts/nix/build-env-kernel.nix delete mode 160000 thirdparty/edein diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index da390933..aaf4ec52 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -51,7 +51,7 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball - nix develop -c bbdev sardine --run '--workload ctest' + # nix develop -c bbdev sardine --run '--workload ctest' # if check failed, revert the branch # - name: Revert Bad Commit diff --git a/.gitignore b/.gitignore index 5421eb21..311fffbb 100644 --- a/.gitignore +++ b/.gitignore @@ -18,7 +18,7 @@ index.html *.fst *.log *.dot - +*.txt .clangd .kiro diff --git a/.gitmodules b/.gitmodules index 28f0c9f9..35308260 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,12 +20,15 @@ path = bebop url = https://github.com/DangoSys/bebop branch = next -[submodule "thirdparty/edein"] - path = thirdparty/edein - url = https://github.com/DangoSys/Edein.git [submodule "thirdparty/pegasus"] path = thirdparty/pegasus url = https://github.com/DangoSys/pegasus.git -[submodule "bluefolk"] - path = bluefolk - url = https://github.com/DangoSys/bluefolk.git +[submodule "bb-tests/workloads/lib/kernel"] + path = bb-tests/workloads/lib/kernel + url = https://github.com/DangoSys/bbkernel.git +[submodule "bb-tests/thirdparty/busybox"] + path = bb-tests/thirdparty/busybox + url = https://github.com/mirror/busybox.git +[submodule "bb-tests/thirdparty/linux"] + path = bb-tests/thirdparty/linux + url = https://github.com/firesim/linux.git diff --git a/bb-tests/thirdparty/busybox b/bb-tests/thirdparty/busybox new file mode 160000 index 00000000..1a64f6a2 --- /dev/null +++ b/bb-tests/thirdparty/busybox @@ -0,0 +1 @@ +Subproject commit 1a64f6a20aaf6ea4dbba68bbfa8cc1ab7e5c57c4 diff --git a/bb-tests/thirdparty/linux b/bb-tests/thirdparty/linux new file mode 160000 index 00000000..ffc25326 --- /dev/null +++ b/bb-tests/thirdparty/linux @@ -0,0 +1 @@ +Subproject commit ffc253263a1375a65fa6c9f62a893e9767fbebfa diff --git a/bb-tests/workloads/lib/CMakeLists.txt b/bb-tests/workloads/lib/CMakeLists.txt index 67636989..7f34428d 100644 --- a/bb-tests/workloads/lib/CMakeLists.txt +++ b/bb-tests/workloads/lib/CMakeLists.txt @@ -1,3 +1,2 @@ - - add_subdirectory(bbhw) +add_subdirectory(kernel) diff --git a/bb-tests/workloads/lib/kernel b/bb-tests/workloads/lib/kernel new file mode 160000 index 00000000..7e2d56dd --- /dev/null +++ b/bb-tests/workloads/lib/kernel @@ -0,0 +1 @@ +Subproject commit 7e2d56dd4d7fce7b79612d79d0c37e3cfc22311f diff --git a/bebop b/bebop index 9f18f0de..e9c07bba 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 9f18f0dec7a97863fe1eec624144dd48a5ff67ab +Subproject commit e9c07bba541730f853f4062845dac30f60762573 diff --git a/bluefolk b/bluefolk deleted file mode 160000 index ddd60509..00000000 --- a/bluefolk +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ddd6050947b647c701b509a35535aea11d82bf5a diff --git a/flake.nix b/flake.nix index d235760a..9112a79b 100644 --- a/flake.nix +++ b/flake.nix @@ -55,6 +55,9 @@ bbdev.gnumake bbdev.pkg-config + # Kernel build tools (RISC-V kernel + rootfs for Pegasus) + kernel.e2fsprogs + # C libraries (headers + link libs) clibs.zlib-dev clibs.zlib @@ -81,12 +84,15 @@ # System utilities systemTools.rsync systemTools.nodejs + + git ]; }; # nix develop devShells.default = pkgs.mkShell { buildInputs = with pkgs; [ + git clibs.zlib-dev clibs.zlib clibs.readline-dev diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index d5045376..7bbcc3a6 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -140,6 +140,12 @@ fi if run_step "4"; then begin_step "4" "bb-tests pre-compile sources" bbdev workload --build + + # FireMarshal nested submodules — same entrypoint as Chipyard: + # arch/thirdparty/chipyard/software/firemarshal/init-submodules.sh + # (identical script here: wlutil/busybox, linux, opensbi, buildroot, boards/firechip/drivers/*) + cd "${BBDIR}/thirdparty/firemarshal" + bash -e ./init-submodules.sh fi if run_step "5"; then diff --git a/scripts/nix/build-env-kernel.nix b/scripts/nix/build-env-kernel.nix new file mode 100644 index 00000000..314d3c00 --- /dev/null +++ b/scripts/nix/build-env-kernel.nix @@ -0,0 +1,7 @@ +{ pkgs }: + +{ + # Host tools for RISC-V kernel/rootfs assembly + # mke2fs: pack rootfs directory into ext4 image + e2fsprogs = pkgs.e2fsprogs; +} diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix index 80634b18..d0057416 100644 --- a/scripts/nix/build-env-python.nix +++ b/scripts/nix/build-env-python.nix @@ -50,5 +50,10 @@ pytest-cov allure-pytest colorlog + + # firemarshal + gitpython + humanfriendly + doit ]); } diff --git a/scripts/nix/build-env-riscv.nix b/scripts/nix/build-env-riscv.nix index ea5c7eef..d87cbdee 100644 --- a/scripts/nix/build-env-riscv.nix +++ b/scripts/nix/build-env-riscv.nix @@ -37,7 +37,6 @@ in { # RISC-V embedded toolchain (bare metal), with riscv64-unknown-elf-* symlinks - # Uses newlib-nano; baremetal runtime provided by bb-tests/workloads/src/CTest/toy/crt0.S riscv-embedded-gcc = pkgs.symlinkJoin { name = "riscv64-unknown-elf-gcc"; paths = [ pkgsCrossWithNano.buildPackages.gcc ]; @@ -51,7 +50,8 @@ in ''; }; - # RISC-V Linux toolchain + # RISC-V Linux toolchain: inject static libc -L only for gcc/g++. Wrapping ar/nm/… + # breaks Kbuild/busybox (ar must not see linker -L flags). riscv-linux-gcc = let cc = pkgs.pkgsCross.riscv64.stdenv.cc; libcStatic = pkgs.pkgsCross.riscv64.stdenv.cc.libc.static; @@ -60,9 +60,16 @@ in for f in ${cc}/bin/riscv64-unknown-linux-gnu-*; do [ -e "$f" ] || continue name=$(basename "$f") - echo '#!${pkgs.stdenv.shell}' > $out/bin/$name - echo 'exec "'"$f"'" -L${libcStatic}/lib "$@"' >> $out/bin/$name - chmod +x $out/bin/$name + case "$name" in + riscv64-unknown-linux-gnu-gcc|riscv64-unknown-linux-gnu-g++|riscv64-unknown-linux-gnu-c++) + echo '#!${pkgs.stdenv.shell}' > $out/bin/$name + echo 'exec "'"$f"'" -L${libcStatic}/lib "$@"' >> $out/bin/$name + chmod +x $out/bin/$name + ;; + *) + ln -s "$f" $out/bin/$name + ;; + esac done ''; } diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 9085b968..729a6150 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -10,4 +10,5 @@ final: prev: scala = final.callPackage ./build-env-scala.nix { }; systemTools = final.callPackage ./build-env-system.nix { }; tools = final.callPackage ./build-env-tools.nix { }; + kernel = final.callPackage ./build-env-kernel.nix { }; } diff --git a/thirdparty/edein b/thirdparty/edein deleted file mode 160000 index 60bab4c9..00000000 --- a/thirdparty/edein +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 60bab4c9cc216a4be50c0bcedc9869cacdb59059 diff --git a/thirdparty/pegasus b/thirdparty/pegasus index aaaac6b9..fb2ca754 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit aaaac6b9cb2ba07cefb720cc96f08a8a2342bc89 +Subproject commit fb2ca7540e23e22eecf3433ba404f966331e44f5 From 82f6d27dfdba8c3c4c108899c7a78518c43d463d Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 15 Apr 2026 15:08:38 +0800 Subject: [PATCH 204/238] [pegasus] feat: add functions to flash bitstream and run workload on AU280 --- .claude/CLAUDE.md | 2 + .../scala/sims/pegasus/PegasusHarness.scala | 16 +-- .../main/scala/sims/pegasus/PegasusTop.scala | 107 +++++++++++++----- bbdev | 2 +- flake.nix | 4 + scripts/claude/mcp_server.py | 57 ++++++++++ scripts/nix/build-env-clibs.nix | 3 + thirdparty/pegasus | 2 +- 8 files changed, 154 insertions(+), 39 deletions(-) diff --git a/.claude/CLAUDE.md b/.claude/CLAUDE.md index 748fcf24..d91c69c3 100644 --- a/.claude/CLAUDE.md +++ b/.claude/CLAUDE.md @@ -78,6 +78,8 @@ The project configures the `buckyball-dev` MCP server with the following tools. - `bbdev_verilator_sim(binary, batch?, coverage?)` — run simulation (requires prior build) - `bbdev_sardine_run(workload?, coverage?)` — run batch tests - `bbdev_yosys_synth(top?, config?)` — Yosys synthesis + OpenSTA timing analysis +- `bbdev_pegasus_flashbitstream(bitstream?, serial?, bus_id?)` — flash bitstream onto AU280 via Vivado + PCIe remove/rescan +- `bbdev_pegasus_runworkload(workload?, board?, timeout?, uart?, control?, h2c?)` — load kernel+rootfs into HBM2 and run on AU280; UART log at `arch/log//pegasus_uart.log` Default config value: `sims.verilator.BuckyballToyVerilatorConfig` Simulation binary naming format: `ctest__test_singlecore-baremetal` diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index 6cf46f13..671e2fa5 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -19,7 +19,7 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI val pcie_exp_txn = Output(UInt(16.W)) val pcie_exp_rxp = Input(UInt(16.W)) val pcie_exp_rxn = Input(UInt(16.W)) - val hbm_ref_clk = Input(Clock()) + // DDR4 physical pins are auto-handled by Vivado board interface — no ports here. }) val pegasusShell = Module(new PegasusShell) @@ -30,7 +30,7 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn - pegasusShell.io.hbm_ref_clk := io.hbm_ref_clk + // DDR4 sys_clk no longer connected from harness — board interface handles physical pins. pegasusShell.io.uart_tx := true.B @@ -63,16 +63,16 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI def connectChipMem(port: AXI4MemPort): Unit = { val axi = port.io.bits - pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(6.W)) - pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(33.W)) + pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(4.W)) + pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(32.W)) pegasusShell.io.chip_mem_awlen := axi.aw.bits.len pegasusShell.io.chip_mem_awsize := axi.aw.bits.size pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst pegasusShell.io.chip_mem_awvalid := axi.aw.valid axi.aw.ready := pegasusShell.io.chip_mem_awready - pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(256.W)) - pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(32.W)) + pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(64.W)) + pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(8.W)) pegasusShell.io.chip_mem_wlast := axi.w.bits.last pegasusShell.io.chip_mem_wvalid := axi.w.valid axi.w.ready := pegasusShell.io.chip_mem_wready @@ -82,8 +82,8 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI axi.b.valid := pegasusShell.io.chip_mem_bvalid pegasusShell.io.chip_mem_bready := axi.b.ready - pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(6.W)) - pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(33.W)) + pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(4.W)) + pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(32.W)) pegasusShell.io.chip_mem_arlen := axi.ar.bits.len pegasusShell.io.chip_mem_arsize := axi.ar.bits.size pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst diff --git a/arch/src/main/scala/sims/pegasus/PegasusTop.scala b/arch/src/main/scala/sims/pegasus/PegasusTop.scala index feb39953..388b2275 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusTop.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusTop.scala @@ -5,9 +5,9 @@ import chisel3.util.HasBlackBoxInline import pegasus.PegasusShell -// PegasusTop — Vivado bitstream top-level for AU280 bring-up. -// Inline Verilog BlackBox that connects PegasusShell (XDMA) to DigitalTop (SoC). -// Skips ChipTop/PegasusHarness harness layers entirely — no simulation primitives. +// PegasusTop — Vivado bitstream top-level for AU280. +// XDMA (DMA mode) + DDR4 + SCU + DigitalTop SoC. +// H2C pwrite offset = SoC paddr - 0x80000000 (DDR4 base). class PegasusTop extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { @@ -18,7 +18,7 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { val pcie_exp_txn = Output(UInt(16.W)) val pcie_exp_rxp = Input(UInt(16.W)) val pcie_exp_rxn = Input(UInt(16.W)) - val hbm_ref_clk = Input(Clock()) + // DDR4 physical pins are auto-handled by Vivado board interface — no ports here. val uart_txd = Output(Bool()) }) @@ -32,12 +32,36 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | output [15:0] pcie_exp_txn, | input [15:0] pcie_exp_rxp, | input [15:0] pcie_exp_rxn, - | input hbm_ref_clk, + | // DDR4 physical pins handled by Vivado board interface — no RTL ports here. | output uart_txd |); | - | wire soc_clk; - | wire soc_reset; + | wire soc_clk; + | wire soc_reset; + | + | // mem_axi4_0 wires (64-bit, 32-bit addr, 4-bit id) + | wire [3:0] mem_awid; + | wire [31:0] mem_awaddr; + | wire [7:0] mem_awlen; + | wire [2:0] mem_awsize; + | wire [1:0] mem_awburst; + | wire mem_awvalid, mem_awready; + | wire [63:0] mem_wdata; + | wire [7:0] mem_wstrb; + | wire mem_wlast, mem_wvalid, mem_wready; + | wire [3:0] mem_bid; + | wire [1:0] mem_bresp; + | wire mem_bvalid, mem_bready; + | wire [3:0] mem_arid; + | wire [31:0] mem_araddr; + | wire [7:0] mem_arlen; + | wire [2:0] mem_arsize; + | wire [1:0] mem_arburst; + | wire mem_arvalid, mem_arready; + | wire [3:0] mem_rid; + | wire [63:0] mem_rdata; + | wire [1:0] mem_rresp; + | wire mem_rlast, mem_rvalid, mem_rready; | | PegasusShell shell ( | .pcie_sys_clk (pcie_sys_clk), @@ -47,17 +71,26 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .pcie_exp_txn (pcie_exp_txn), | .pcie_exp_rxp (pcie_exp_rxp), | .pcie_exp_rxn (pcie_exp_rxn), - | .hbm_ref_clk (hbm_ref_clk), + | // DDR4 physical pins: no connections — handled by Vivado board interface. | .dut_clk (soc_clk), | .dut_reset (soc_reset), | .uart_tx (1'b1), - | .chip_mem_awid(6'h0), .chip_mem_awaddr(33'h0), .chip_mem_awlen(8'h0), - | .chip_mem_awsize(3'h0), .chip_mem_awburst(2'h0), .chip_mem_awvalid(1'b0), - | .chip_mem_wdata(256'h0), .chip_mem_wstrb(32'h0), - | .chip_mem_wlast(1'b0), .chip_mem_wvalid(1'b0), .chip_mem_bready(1'b0), - | .chip_mem_arid(6'h0), .chip_mem_araddr(33'h0), .chip_mem_arlen(8'h0), - | .chip_mem_arsize(3'h0), .chip_mem_arburst(2'h0), .chip_mem_arvalid(1'b0), - | .chip_mem_rready(1'b0) + | .chip_mem_awid (mem_awid), .chip_mem_awaddr (mem_awaddr), + | .chip_mem_awlen (mem_awlen), .chip_mem_awsize (mem_awsize), + | .chip_mem_awburst(mem_awburst), .chip_mem_awvalid(mem_awvalid), + | .chip_mem_awready(mem_awready), + | .chip_mem_wdata (mem_wdata), .chip_mem_wstrb (mem_wstrb), + | .chip_mem_wlast (mem_wlast), .chip_mem_wvalid (mem_wvalid), + | .chip_mem_wready (mem_wready), + | .chip_mem_bid (mem_bid), .chip_mem_bresp (mem_bresp), + | .chip_mem_bvalid (mem_bvalid), .chip_mem_bready (mem_bready), + | .chip_mem_arid (mem_arid), .chip_mem_araddr (mem_araddr), + | .chip_mem_arlen (mem_arlen), .chip_mem_arsize (mem_arsize), + | .chip_mem_arburst(mem_arburst), .chip_mem_arvalid(mem_arvalid), + | .chip_mem_arready(mem_arready), + | .chip_mem_rid (mem_rid), .chip_mem_rdata (mem_rdata), + | .chip_mem_rresp (mem_rresp), .chip_mem_rlast (mem_rlast), + | .chip_mem_rvalid (mem_rvalid), .chip_mem_rready (mem_rready) | ); | | DigitalTop soc ( @@ -73,17 +106,35 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .debug_dmactiveAck (1'b0), | .uart_0_txd (uart_txd), | .uart_0_rxd (1'b1), - | .mem_axi4_0_aw_ready (1'b0), - | .mem_axi4_0_w_ready (1'b0), - | .mem_axi4_0_b_valid (1'b0), - | .mem_axi4_0_b_bits_id (4'h0), - | .mem_axi4_0_b_bits_resp (2'h0), - | .mem_axi4_0_ar_ready (1'b0), - | .mem_axi4_0_r_valid (1'b0), - | .mem_axi4_0_r_bits_id (4'h0), - | .mem_axi4_0_r_bits_data (64'h0), - | .mem_axi4_0_r_bits_resp (2'h0), - | .mem_axi4_0_r_bits_last (1'b0), + | .mem_axi4_0_aw_ready (mem_awready), + | .mem_axi4_0_aw_valid (mem_awvalid), + | .mem_axi4_0_aw_bits_id (mem_awid), + | .mem_axi4_0_aw_bits_addr (mem_awaddr), + | .mem_axi4_0_aw_bits_len (mem_awlen), + | .mem_axi4_0_aw_bits_size (mem_awsize), + | .mem_axi4_0_aw_bits_burst (mem_awburst), + | .mem_axi4_0_w_ready (mem_wready), + | .mem_axi4_0_w_valid (mem_wvalid), + | .mem_axi4_0_w_bits_data (mem_wdata), + | .mem_axi4_0_w_bits_strb (mem_wstrb), + | .mem_axi4_0_w_bits_last (mem_wlast), + | .mem_axi4_0_b_valid (mem_bvalid), + | .mem_axi4_0_b_ready (mem_bready), + | .mem_axi4_0_b_bits_id (mem_bid), + | .mem_axi4_0_b_bits_resp (mem_bresp), + | .mem_axi4_0_ar_ready (mem_arready), + | .mem_axi4_0_ar_valid (mem_arvalid), + | .mem_axi4_0_ar_bits_id (mem_arid), + | .mem_axi4_0_ar_bits_addr (mem_araddr), + | .mem_axi4_0_ar_bits_len (mem_arlen), + | .mem_axi4_0_ar_bits_size (mem_arsize), + | .mem_axi4_0_ar_bits_burst (mem_arburst), + | .mem_axi4_0_r_valid (mem_rvalid), + | .mem_axi4_0_r_ready (mem_rready), + | .mem_axi4_0_r_bits_id (mem_rid), + | .mem_axi4_0_r_bits_data (mem_rdata), + | .mem_axi4_0_r_bits_resp (mem_rresp), + | .mem_axi4_0_r_bits_last (mem_rlast), | .mmio_axi4_0_aw_ready (1'b0), | .mmio_axi4_0_w_ready (1'b0), | .mmio_axi4_0_b_valid (1'b0), @@ -110,7 +161,6 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { object ElaboratePegasusTop extends App { import _root_.circt.stage.ChiselStage - // PegasusTop is a BlackBox with inline Verilog — wrap in a thin RawModule to elaborate class PegasusTopWrapper extends RawModule { val io = IO(new Bundle { @@ -121,7 +171,7 @@ object ElaboratePegasusTop extends App { val pcie_exp_txn = Output(UInt(16.W)) val pcie_exp_rxp = Input(UInt(16.W)) val pcie_exp_rxn = Input(UInt(16.W)) - val hbm_ref_clk = Input(Clock()) + // DDR4 physical pins are auto-handled by Vivado board interface — no ports here. val uart_txd = Output(Bool()) }) @@ -133,7 +183,6 @@ object ElaboratePegasusTop extends App { top.io.pcie_exp_rxn := io.pcie_exp_rxn io.pcie_exp_txp := top.io.pcie_exp_txp io.pcie_exp_txn := top.io.pcie_exp_txn - top.io.hbm_ref_clk := io.hbm_ref_clk io.uart_txd := top.io.uart_txd } diff --git a/bbdev b/bbdev index 1dd8274c..2305b007 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 1dd8274c6e4ab949db69378460a8eb6f633ca6e0 +Subproject commit 2305b00700b74b7107f5ad495b5e9967e104942c diff --git a/flake.nix b/flake.nix index 9112a79b..e24c9a7a 100644 --- a/flake.nix +++ b/flake.nix @@ -67,6 +67,8 @@ clibs.jpeg clibs.png-dev clibs.png + clibs.elfutils-dev + clibs.elfutils # Scala tools scala.mill @@ -101,6 +103,8 @@ clibs.jpeg clibs.png-dev clibs.png + clibs.elfutils-dev + clibs.elfutils ]; shellHook = '' if [ -d "$PWD/result/bin" ]; then diff --git a/scripts/claude/mcp_server.py b/scripts/claude/mcp_server.py index a0586014..a5502120 100644 --- a/scripts/claude/mcp_server.py +++ b/scripts/claude/mcp_server.py @@ -366,5 +366,62 @@ def bbdev_yosys_synth( return _fmt(result) +@mcp.tool() +def bbdev_pegasus_flashbitstream( + bitstream: Optional[str] = None, + serial: Optional[str] = None, + bus_id: Optional[str] = None, +) -> str: + """Flash bitstream onto AU280 via Vivado hw_server + PCIe remove/rescan. Calls bbdev POST /pegasus/flashbitstream. + + Args: + bitstream: Path to .bit file (default: thirdparty/pegasus/vivado/build/PegasusTop.bit) + serial: hw_server target serial/URL (default: auto, first target) + bus_id: PCIe BDF to remove before flashing, e.g. '0000:65:00.0' (default: auto-detect xdma) + """ + api_params: Dict[str, Any] = {} + if bitstream: + api_params["bitstream"] = bitstream + if serial: + api_params["serial"] = serial + if bus_id: + api_params["bus_id"] = bus_id + result = _bbdev_call("/pegasus/flashbitstream", api_params, timeout=600) + return _fmt(result) + + +@mcp.tool() +def bbdev_pegasus_runworkload( + workload: str = "interactive", + board: str = "chipyard", + timeout: int = 300, + uart: str = "/dev/ttyUSB0", + control: str = "/dev/xdma0_user", + h2c: str = "/dev/xdma0_h2c_0", +) -> str: + """Load Linux image into HBM2 and run on AU280. Calls bbdev POST /pegasus/runworkload. + Requires kernel + rootfs images at bb-tests/output/kernel/ (run bbdev kernel --build first). + UART log is saved to arch/log//pegasus_uart.log. + + Args: + workload: Workload name (default: interactive) + board: Board name (default: chipyard) + timeout: UART collection timeout in seconds (default: 300) + uart: UART device path (default: /dev/ttyUSB0) + control: XDMA control device path (default: /dev/xdma0_control) + h2c: XDMA H2C DMA device path (default: /dev/xdma0_h2c_0) + """ + api_params: Dict[str, Any] = { + "workload": workload, + "board": board, + "timeout": timeout, + "uart": uart, + "control": control, + "h2c": h2c, + } + result = _bbdev_call("/pegasus/runworkload", api_params, timeout=timeout + 120) + return _fmt(result) + + if __name__ == "__main__": mcp.run(transport="stdio") diff --git a/scripts/nix/build-env-clibs.nix b/scripts/nix/build-env-clibs.nix index 90a2f9c4..4474e1c0 100644 --- a/scripts/nix/build-env-clibs.nix +++ b/scripts/nix/build-env-clibs.nix @@ -13,4 +13,7 @@ # buddy DIP imgcodecs (grfmt_png.h) png-dev = pkgs.libpng.dev; png = pkgs.libpng; + # pegasus-driver: ELF parsing for kernel loading + elfutils-dev = pkgs.elfutils.dev; + elfutils = pkgs.elfutils; } diff --git a/thirdparty/pegasus b/thirdparty/pegasus index fb2ca754..56974230 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit fb2ca7540e23e22eecf3433ba404f966331e44f5 +Subproject commit 56974230eb20b4022dc80f38f00fc91ad256b8f2 From 4632cef467cb802a8a53d2541f33f50d14f7a508 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 16 Apr 2026 00:11:48 +0800 Subject: [PATCH 205/238] [scripts] update: remove linux submodule initialization avoid long time init --- .github/workflows/test.yml | 2 +- scripts/nix/build-all.sh | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index aaf4ec52..6e44cca3 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -25,7 +25,7 @@ jobs: git clean -fd git checkout ${{ github.head_ref }} git pull - git submodule update + git submodule update bbdev bebop compiler - name: Nix build shell: zsh {0} diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 7bbcc3a6..b73f7bb5 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -74,9 +74,20 @@ function begin_step } begin_step "0-1" "submodules init" -git submodule update --init +# git submodule update --init --progress --jobs 8 +cd ${BBDIR} +git submodule update --init --progress --jobs 8 \ + arch/thirdparty/chipyard \ + bb-tests/workloads/lib/kernel \ + bbdev \ + bebop \ + compiler \ + docs \ + thirdparty/palladium \ + thirdparty/pegasus \ + thirdparty/waveform-mcp # fpga/fpga-shells is needed by palladium -cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init fpga/fpga-shells generators/* tools/* sims/firesim +cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim begin_step "0-2" "Nix environment setup" cd ${BBDIR} From b02f04538ccd8f507891235c576dc807f0790d17 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 16 Apr 2026 02:40:48 +0800 Subject: [PATCH 206/238] [scripts] cleanup: remove FireMarshal submodule initialization from build-all.sh --- scripts/nix/build-all.sh | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index b73f7bb5..dd581d43 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -85,9 +85,9 @@ git submodule update --init --progress --jobs 8 \ docs \ thirdparty/palladium \ thirdparty/pegasus \ - thirdparty/waveform-mcp + thirdparty/waveform-mcp # fpga/fpga-shells is needed by palladium -cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim +cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim begin_step "0-2" "Nix environment setup" cd ${BBDIR} @@ -151,12 +151,6 @@ fi if run_step "4"; then begin_step "4" "bb-tests pre-compile sources" bbdev workload --build - - # FireMarshal nested submodules — same entrypoint as Chipyard: - # arch/thirdparty/chipyard/software/firemarshal/init-submodules.sh - # (identical script here: wlutil/busybox, linux, opensbi, buildroot, boards/firechip/drivers/*) - cd "${BBDIR}/thirdparty/firemarshal" - bash -e ./init-submodules.sh fi if run_step "5"; then From dc7a25965f3d62da38c31540d14f823dd8fd8d68 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 16 Apr 2026 10:00:46 +0800 Subject: [PATCH 207/238] [pegasus] update: bump to the latest version --- .gitignore | 8 ++++++++ thirdparty/pegasus | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 311fffbb..5f29e55a 100644 --- a/.gitignore +++ b/.gitignore @@ -20,6 +20,14 @@ index.html *.dot *.txt +# Vivado / Webtalk session files (root-level) +/vivado*.jou +/vivado*.log +/webtalk*.jou +/webtalk*.log +/iter_*.txt +/log.txt + .clangd .kiro diff --git a/thirdparty/pegasus b/thirdparty/pegasus index 56974230..ef27dc84 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit 56974230eb20b4022dc80f38f00fc91ad256b8f2 +Subproject commit ef27dc847827204513a50081b4ce67221e33e8a1 From 8e9fb4e08d7deb2f962e6757470bf8c076417296 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 17 Apr 2026 11:29:01 +0800 Subject: [PATCH 208/238] [pegasus] update: add DDR4 signal connections --- .gitignore | 2 +- .../scala/sims/pegasus/PegasusHarness.scala | 3 +- .../main/scala/sims/pegasus/PegasusTop.scala | 75 ++++++++++++++++++- thirdparty/pegasus | 2 +- 4 files changed, 75 insertions(+), 7 deletions(-) diff --git a/.gitignore b/.gitignore index 5f29e55a..0ab80118 100644 --- a/.gitignore +++ b/.gitignore @@ -30,5 +30,5 @@ index.html .clangd .kiro - +.tmpCRC/ __pycache__/ diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index 671e2fa5..3962d82e 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -30,7 +30,8 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn - // DDR4 sys_clk no longer connected from harness — board interface handles physical pins. + pegasusShell.io.c0_sys_clk_p := false.B + pegasusShell.io.c0_sys_clk_n := false.B pegasusShell.io.uart_tx := true.B diff --git a/arch/src/main/scala/sims/pegasus/PegasusTop.scala b/arch/src/main/scala/sims/pegasus/PegasusTop.scala index 388b2275..f0ffcca2 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusTop.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusTop.scala @@ -18,7 +18,19 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { val pcie_exp_txn = Output(UInt(16.W)) val pcie_exp_rxp = Input(UInt(16.W)) val pcie_exp_rxn = Input(UInt(16.W)) - // DDR4 physical pins are auto-handled by Vivado board interface — no ports here. + val c0_sys_clk_p = Input(Bool()) + val c0_sys_clk_n = Input(Bool()) + val c0_ddr4_act_n = Output(Bool()) + val c0_ddr4_adr = Output(UInt(17.W)) + val c0_ddr4_ba = Output(UInt(2.W)) + val c0_ddr4_bg = Output(UInt(2.W)) + val c0_ddr4_cke = Output(UInt(1.W)) + val c0_ddr4_odt = Output(UInt(1.W)) + val c0_ddr4_cs_n = Output(UInt(1.W)) + val c0_ddr4_ck_t = Output(UInt(1.W)) + val c0_ddr4_ck_c = Output(UInt(1.W)) + val c0_ddr4_reset_n = Output(Bool()) + val c0_ddr4_parity = Output(Bool()) val uart_txd = Output(Bool()) }) @@ -32,7 +44,22 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | output [15:0] pcie_exp_txn, | input [15:0] pcie_exp_rxp, | input [15:0] pcie_exp_rxn, - | // DDR4 physical pins handled by Vivado board interface — no RTL ports here. + | input c0_sys_clk_p, + | input c0_sys_clk_n, + | output c0_ddr4_act_n, + | output [16:0] c0_ddr4_adr, + | output [1:0] c0_ddr4_ba, + | output [1:0] c0_ddr4_bg, + | output [0:0] c0_ddr4_cke, + | output [0:0] c0_ddr4_odt, + | output [0:0] c0_ddr4_cs_n, + | output [0:0] c0_ddr4_ck_t, + | output [0:0] c0_ddr4_ck_c, + | output c0_ddr4_reset_n, + | output c0_ddr4_parity, + | inout [71:0] c0_ddr4_dq, + | inout [17:0] c0_ddr4_dqs_c, + | inout [17:0] c0_ddr4_dqs_t, | output uart_txd |); | @@ -71,7 +98,22 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .pcie_exp_txn (pcie_exp_txn), | .pcie_exp_rxp (pcie_exp_rxp), | .pcie_exp_rxn (pcie_exp_rxn), - | // DDR4 physical pins: no connections — handled by Vivado board interface. + | .c0_sys_clk_p (c0_sys_clk_p), + | .c0_sys_clk_n (c0_sys_clk_n), + | .c0_ddr4_act_n (c0_ddr4_act_n), + | .c0_ddr4_adr (c0_ddr4_adr), + | .c0_ddr4_ba (c0_ddr4_ba), + | .c0_ddr4_bg (c0_ddr4_bg), + | .c0_ddr4_cke (c0_ddr4_cke), + | .c0_ddr4_odt (c0_ddr4_odt), + | .c0_ddr4_cs_n (c0_ddr4_cs_n), + | .c0_ddr4_ck_t (c0_ddr4_ck_t), + | .c0_ddr4_ck_c (c0_ddr4_ck_c), + | .c0_ddr4_reset_n (c0_ddr4_reset_n), + | .c0_ddr4_parity (c0_ddr4_parity), + | .c0_ddr4_dq (c0_ddr4_dq), + | .c0_ddr4_dqs_c (c0_ddr4_dqs_c), + | .c0_ddr4_dqs_t (c0_ddr4_dqs_t), | .dut_clk (soc_clk), | .dut_reset (soc_reset), | .uart_tx (1'b1), @@ -171,7 +213,19 @@ object ElaboratePegasusTop extends App { val pcie_exp_txn = Output(UInt(16.W)) val pcie_exp_rxp = Input(UInt(16.W)) val pcie_exp_rxn = Input(UInt(16.W)) - // DDR4 physical pins are auto-handled by Vivado board interface — no ports here. + val c0_sys_clk_p = Input(Bool()) + val c0_sys_clk_n = Input(Bool()) + val c0_ddr4_act_n = Output(Bool()) + val c0_ddr4_adr = Output(UInt(17.W)) + val c0_ddr4_ba = Output(UInt(2.W)) + val c0_ddr4_bg = Output(UInt(2.W)) + val c0_ddr4_cke = Output(UInt(1.W)) + val c0_ddr4_odt = Output(UInt(1.W)) + val c0_ddr4_cs_n = Output(UInt(1.W)) + val c0_ddr4_ck_t = Output(UInt(1.W)) + val c0_ddr4_ck_c = Output(UInt(1.W)) + val c0_ddr4_reset_n = Output(Bool()) + val c0_ddr4_parity = Output(Bool()) val uart_txd = Output(Bool()) }) @@ -181,8 +235,21 @@ object ElaboratePegasusTop extends App { top.io.pcie_sys_rst_n := io.pcie_sys_rst_n top.io.pcie_exp_rxp := io.pcie_exp_rxp top.io.pcie_exp_rxn := io.pcie_exp_rxn + top.io.c0_sys_clk_p := io.c0_sys_clk_p + top.io.c0_sys_clk_n := io.c0_sys_clk_n io.pcie_exp_txp := top.io.pcie_exp_txp io.pcie_exp_txn := top.io.pcie_exp_txn + io.c0_ddr4_act_n := top.io.c0_ddr4_act_n + io.c0_ddr4_adr := top.io.c0_ddr4_adr + io.c0_ddr4_ba := top.io.c0_ddr4_ba + io.c0_ddr4_bg := top.io.c0_ddr4_bg + io.c0_ddr4_cke := top.io.c0_ddr4_cke + io.c0_ddr4_odt := top.io.c0_ddr4_odt + io.c0_ddr4_cs_n := top.io.c0_ddr4_cs_n + io.c0_ddr4_ck_t := top.io.c0_ddr4_ck_t + io.c0_ddr4_ck_c := top.io.c0_ddr4_ck_c + io.c0_ddr4_reset_n := top.io.c0_ddr4_reset_n + io.c0_ddr4_parity := top.io.c0_ddr4_parity io.uart_txd := top.io.uart_txd } diff --git a/thirdparty/pegasus b/thirdparty/pegasus index ef27dc84..bddd7248 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit ef27dc847827204513a50081b4ce67221e33e8a1 +Subproject commit bddd7248859d272bde36291ffa695b90fcbe8c0f From 2ef1d17b12a51435c7171bbd64096371fe833255 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 17 Apr 2026 16:06:16 +0800 Subject: [PATCH 209/238] [pegasus] update: add DDR4 signal connections --- bbdev | 2 +- thirdparty/pegasus | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bbdev b/bbdev index 2305b007..22fcec02 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 2305b00700b74b7107f5ad495b5e9967e104942c +Subproject commit 22fcec0213327e348edf93dc5519f4ae4fa1bf02 diff --git a/thirdparty/pegasus b/thirdparty/pegasus index bddd7248..a56b27b8 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit bddd7248859d272bde36291ffa695b90fcbe8c0f +Subproject commit a56b27b80b1fe7c6194e0732846951a67a21e673 From e28c16af3e436c1fbeccdf37915a53c9842e2129 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 17 Apr 2026 16:19:12 +0800 Subject: [PATCH 210/238] [pegasus] fix: correct clock signal assignments to use elements map --- .../scala/sims/pegasus/PegasusHarness.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index 3962d82e..930df5a0 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -23,15 +23,15 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI }) val pegasusShell = Module(new PegasusShell) - pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk - pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt - pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n - io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp - io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn - pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp - pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn - pegasusShell.io.c0_sys_clk_p := false.B - pegasusShell.io.c0_sys_clk_n := false.B + pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk + pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt + pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n + io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp + io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn + pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp + pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn + pegasusShell.io.elements.get("c0_sys_clk_p").foreach(_.asInstanceOf[Bool] := false.B) + pegasusShell.io.elements.get("c0_sys_clk_n").foreach(_.asInstanceOf[Bool] := false.B) pegasusShell.io.uart_tx := true.B From 5ddda5b7e48e8535329f326c1645501639d2ab43 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Sat, 18 Apr 2026 15:50:18 +0800 Subject: [PATCH 211/238] [trace]add:enable to monitor the pbank --- arch/src/csrc/include/monitor/trace.h | 2 +- arch/src/csrc/src/monitor/trace/mtrace.cc | 23 ++++++++++--------- .../framework/memdomain/backend/MTrace.scala | 5 +++- .../privatepath/PrivateMemBackend.scala | 17 +++++++++++++- .../backend/shared/SharedMemBackend.scala | 19 ++++++++++++++- 5 files changed, 51 insertions(+), 15 deletions(-) diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index afe79e5b..31f1474e 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -23,7 +23,7 @@ void dpi_itrace(unsigned char is_issue, // 2 = alloc, 1 = issue, 0 = complete void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read unsigned char is_shared, unsigned int channel, unsigned long long hart_id, unsigned int vbank_id, - unsigned int group_id, unsigned int addr, + unsigned int pbank_id, unsigned int group_id, unsigned int addr, unsigned long long data_lo, unsigned long long data_hi); // DPI-C function for Ball PMC trace (pmctrace) diff --git a/arch/src/csrc/src/monitor/trace/mtrace.cc b/arch/src/csrc/src/monitor/trace/mtrace.cc index 9e339e1e..319d3bb5 100644 --- a/arch/src/csrc/src/monitor/trace/mtrace.cc +++ b/arch/src/csrc/src/monitor/trace/mtrace.cc @@ -31,8 +31,8 @@ static void u128_hex(char *buf, size_t n, unsigned long long hi, extern "C" void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read unsigned char is_shared, unsigned int channel, unsigned long long hart_id, unsigned int vbank_id, - unsigned int group_id, unsigned int addr, - unsigned long long data_lo, + unsigned int pbank_id, unsigned int group_id, + unsigned int addr, unsigned long long data_lo, unsigned long long data_hi) { if (!bdb_trace_on(BDB_TR_MTRACE)) { return; @@ -43,21 +43,22 @@ extern "C" void dpi_mtrace(unsigned char is_write, // 1 = write, 0 = read char data_hex[35]; if (is_write) { u128_hex(data_hex, sizeof(data_hex), data_hi, data_lo); - fprintf(mtrace_fp, - "{\"type\":\"mtrace\",\"clk\":%llu,\"event\":\"write\"," - "\"channel\":%u," - "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," - "\"group_id\":%u,\"addr\":\"0x%08x\",\"data\":\"%s\"}\n", - (unsigned long long)bdb_rtl_clk, channel, hart_id, is_shared, - vbank_id, group_id, addr, data_hex); + fprintf( + mtrace_fp, + "{\"type\":\"mtrace\",\"clk\":%llu,\"event\":\"write\"," + "\"channel\":%u," + "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u,\"pbank_id\":%u," + "\"group_id\":%u,\"addr\":\"0x%08x\",\"data\":\"%s\"}\n", + (unsigned long long)bdb_rtl_clk, channel, hart_id, is_shared, + vbank_id, pbank_id, group_id, addr, data_hex); } else { fprintf( mtrace_fp, "{\"type\":\"mtrace\",\"clk\":%llu,\"event\":\"read\",\"channel\":%u," - "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u," + "\"hart_id\":%llu,\"is_shared\":%u,\"vbank_id\":%u,\"pbank_id\":%u," "\"group_id\":%u,\"addr\":\"0x%08x\"}\n", (unsigned long long)bdb_rtl_clk, channel, hart_id, is_shared, - vbank_id, group_id, addr); + vbank_id, pbank_id, group_id, addr); } fflush(mtrace_fp); } diff --git a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala index 769d0677..41c3260a 100644 --- a/arch/src/main/scala/framework/memdomain/backend/MTrace.scala +++ b/arch/src/main/scala/framework/memdomain/backend/MTrace.scala @@ -12,6 +12,7 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { val channel = Input(UInt(32.W)) val hart_id = Input(UInt(64.W)) val vbank_id = Input(UInt(32.W)) + val pbank_id = Input(UInt(32.W)) val group_id = Input(UInt(32.W)) val addr = Input(UInt(32.W)) val data_lo = Input(UInt(64.W)) @@ -28,6 +29,7 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { | input int unsigned channel, | input longint unsigned hart_id, | input int unsigned vbank_id, + | input int unsigned pbank_id, | input int unsigned group_id, | input int unsigned addr, | input longint unsigned data_lo, @@ -40,6 +42,7 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { | input [31:0] channel, | input [63:0] hart_id, | input [31:0] vbank_id, + | input [31:0] pbank_id, | input [31:0] group_id, | input [31:0] addr, | input [63:0] data_lo, @@ -48,7 +51,7 @@ class MTraceDPI extends BlackBox with HasBlackBoxInline { |); | always @(*) begin | if (enable) begin - | dpi_mtrace(is_write, is_shared, channel, hart_id, vbank_id, group_id, addr, data_lo, data_hi); + | dpi_mtrace(is_write, is_shared, channel, hart_id, vbank_id, pbank_id, group_id, addr, data_lo, data_hi); | end | end |endmodule diff --git a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala index 389616a9..d34fbf95 100644 --- a/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/privatepath/PrivateMemBackend.scala @@ -33,6 +33,7 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { mt.io.channel := 0.U mt.io.hart_id := 0.U mt.io.vbank_id := 0.U + mt.io.pbank_id := 0.U mt.io.group_id := 0.U mt.io.addr := 0.U mt.io.data_lo := 0.U @@ -151,6 +152,7 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { private def emitTrace( ch: Int, isWrite: UInt, + pbankId: UInt, addr: UInt, dataLo: UInt, dataHi: UInt, @@ -161,6 +163,7 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { mtraces(ch).io.channel := ch.U mtraces(ch).io.hart_id := io.mem_req(ch).hart_id mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.pbank_id := pbankId mtraces(ch).io.group_id := io.mem_req(ch).group_id mtraces(ch).io.addr := addr mtraces(ch).io.data_lo := dataLo @@ -171,9 +174,20 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until b.memDomain.bankChannel) { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + val tracePbankId = Wire(UInt(32.W)) + tracePbankId := 0.U + for (j <- 0 until b.memDomain.bankNum) { + val trace_hit_bank = mappingTable(j).valid && (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + (!mappingTable(j).is_multi || + (mappingTable(j).is_multi && (mappingTable(j).group_id === io.mem_req(i).group_id))) + when(trace_hit_bank) { + tracePbankId := j.U + } + } + // Memory trace: read request when(io.mem_req(i).read.req.fire) { - emitTrace(i, 0.U, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) + emitTrace(i, 0.U, tracePbankId, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) } // Memory trace: write request @@ -181,6 +195,7 @@ class PrivateMemBackend(val b: GlobalConfig) extends Module { emitTrace( i, 1.U, + tracePbankId, io.mem_req(i).write.req.bits.addr, io.mem_req(i).write.req.bits.data(63, 0), io.mem_req(i).write.req.bits.data(127, 64), diff --git a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala index c93da78e..7eb3f292 100644 --- a/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala +++ b/arch/src/main/scala/framework/memdomain/backend/shared/SharedMemBackend.scala @@ -36,6 +36,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { mt.io.channel := 0.U mt.io.hart_id := 0.U mt.io.vbank_id := 0.U + mt.io.pbank_id := 0.U mt.io.group_id := 0.U mt.io.addr := 0.U mt.io.data_lo := 0.U @@ -165,6 +166,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { private def emitTrace( ch: Int, isWrite: UInt, + pbankId: UInt, addr: UInt, dataLo: UInt, dataHi: UInt, @@ -175,6 +177,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { mtraces(ch).io.channel := ch.U mtraces(ch).io.hart_id := io.mem_req(ch).hart_id mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.pbank_id := pbankId mtraces(ch).io.group_id := io.mem_req(ch).group_id mtraces(ch).io.addr := addr mtraces(ch).io.data_lo := dataLo @@ -185,9 +188,22 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { for (i <- 0 until totalChannel) { val req_valid = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + val tracePbankId = Wire(UInt(32.W)) + tracePbankId := 0.U + for (j <- 0 until totalBanks) { + val trace_hit_bank = mappingTable(j).valid && + (mappingTable(j).hart_id === io.mem_req(i).hart_id) && + (mappingTable(j).vbank_id === io.mem_req(i).bank_id) && + (!mappingTable(j).is_multi || + (mappingTable(j).is_multi && (mappingTable(j).group_id === io.mem_req(i).group_id))) + when(trace_hit_bank) { + tracePbankId := j.U + } + } + // Memory trace: read request when(io.mem_req(i).read.req.fire) { - emitTrace(i, 0.U, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) + emitTrace(i, 0.U, tracePbankId, io.mem_req(i).read.req.bits.addr, 0.U, 0.U, true.B) } // Memory trace: write request @@ -195,6 +211,7 @@ class SharedMemBackend(val b: GlobalConfig) extends Module { emitTrace( i, 1.U, + tracePbankId, io.mem_req(i).write.req.bits.addr, io.mem_req(i).write.req.bits.data(63, 0), io.mem_req(i).write.req.bits.data(127, 64), From 8ca423983685aaa2e5f884aa3e6ec26d335a3bc8 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 01:27:58 +0800 Subject: [PATCH 212/238] [arch/pegasus] refactor: replace clock signals with reference clock inputs and change MMIO connections --- .../scala/sims/pegasus/PegasusHarness.scala | 56 ++++-- .../sims/pegasus/PegasusHarnessBinders.scala | 58 +++--- .../main/scala/sims/pegasus/PegasusTop.scala | 180 +++++++++++------- bbdev | 2 +- thirdparty/pegasus | 2 +- 5 files changed, 184 insertions(+), 114 deletions(-) diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index 930df5a0..b1e0540a 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -12,29 +12,29 @@ import pegasus.PegasusShell class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { val io = IO(new Bundle { - val pcie_sys_clk = Input(Clock()) - val pcie_sys_clk_gt = Input(Clock()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) - // DDR4 physical pins are auto-handled by Vivado board interface — no ports here. + val pcie_refclk_p = Input(Bool()) + val pcie_refclk_n = Input(Bool()) + val pcie_sys_rst_n = Input(Bool()) + val pcie_exp_txp = Output(UInt(16.W)) + val pcie_exp_txn = Output(UInt(16.W)) + val pcie_exp_rxp = Input(UInt(16.W)) + val pcie_exp_rxn = Input(UInt(16.W)) }) val pegasusShell = Module(new PegasusShell) - pegasusShell.io.pcie_sys_clk := io.pcie_sys_clk - pegasusShell.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt - pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n - io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp - io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn - pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp - pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn - pegasusShell.io.elements.get("c0_sys_clk_p").foreach(_.asInstanceOf[Bool] := false.B) - pegasusShell.io.elements.get("c0_sys_clk_n").foreach(_.asInstanceOf[Bool] := false.B) + pegasusShell.io.pcie_refclk_p := io.pcie_refclk_p + pegasusShell.io.pcie_refclk_n := io.pcie_refclk_n + pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n + io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp + io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn + pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp + pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn + pegasusShell.io.c0_sys_clk_p := false.B + pegasusShell.io.c0_sys_clk_n := false.B pegasusShell.io.uart_tx := true.B + // Default tie-offs for chip_mem (overridden by connectChipMem) pegasusShell.io.chip_mem_awid := 0.U pegasusShell.io.chip_mem_awaddr := 0.U pegasusShell.io.chip_mem_awlen := 0.U @@ -54,7 +54,27 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI pegasusShell.io.chip_mem_arvalid := false.B pegasusShell.io.chip_mem_rready := false.B - def referenceClockFreqMHz: Double = 200.0 + // Default tie-offs for mmio (overridden by connectChipMMIO) + pegasusShell.io.mmio_awid := 0.U + pegasusShell.io.mmio_awaddr := 0.U + pegasusShell.io.mmio_awlen := 0.U + pegasusShell.io.mmio_awsize := 0.U + pegasusShell.io.mmio_awburst := 0.U + pegasusShell.io.mmio_awvalid := false.B + pegasusShell.io.mmio_wdata := 0.U + pegasusShell.io.mmio_wstrb := 0.U + pegasusShell.io.mmio_wlast := false.B + pegasusShell.io.mmio_wvalid := false.B + pegasusShell.io.mmio_bready := false.B + pegasusShell.io.mmio_arid := 0.U + pegasusShell.io.mmio_araddr := 0.U + pegasusShell.io.mmio_arlen := 0.U + pegasusShell.io.mmio_arsize := 0.U + pegasusShell.io.mmio_arburst := 0.U + pegasusShell.io.mmio_arvalid := false.B + pegasusShell.io.mmio_rready := false.B + + def referenceClockFreqMHz: Double = 250.0 def referenceClock: Clock = pegasusShell.io.dut_clk def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala index 3cd2896b..014602a3 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala @@ -23,33 +23,42 @@ class WithPegasusUART class WithPegasusAXIMMIO extends HarnessBinder({ case (th: PegasusHarness, port: AXI4MMIOPort, chipId: Int) => - withClockAndReset(port.io.clock, th.reset) { - val idBits = port.io.bits.aw.bits.id.getWidth - val bId = RegInit(0.U(idBits.W)) - val bValid = RegInit(false.B) + val axi = port.io.bits + val shell = th.pegasusShell.io + // Connect mmio_axi4 to shell's MMIO SCU + shell.mmio_awid := axi.aw.bits.id.asTypeOf(UInt(4.W)) + shell.mmio_awaddr := axi.aw.bits.addr.asTypeOf(UInt(32.W)) + shell.mmio_awlen := axi.aw.bits.len + shell.mmio_awsize := axi.aw.bits.size + shell.mmio_awburst := axi.aw.bits.burst + shell.mmio_awvalid := axi.aw.valid + axi.aw.ready := shell.mmio_awready - port.io.bits.aw.ready := !bValid - port.io.bits.w.ready := !bValid - when(!bValid && port.io.bits.aw.valid && port.io.bits.w.valid) { - bId := port.io.bits.aw.bits.id - bValid := true.B - } - when(port.io.bits.b.valid && port.io.bits.b.ready) { - bValid := false.B - } + shell.mmio_wdata := axi.w.bits.data.asTypeOf(UInt(64.W)) + shell.mmio_wstrb := axi.w.bits.strb.asTypeOf(UInt(8.W)) + shell.mmio_wlast := axi.w.bits.last + shell.mmio_wvalid := axi.w.valid + axi.w.ready := shell.mmio_wready - port.io.bits.b.valid := bValid - port.io.bits.b.bits.id := bId - port.io.bits.b.bits.resp := 0.U + axi.b.bits.id := shell.mmio_bid.asTypeOf(axi.b.bits.id) + axi.b.bits.resp := shell.mmio_bresp + axi.b.valid := shell.mmio_bvalid + shell.mmio_bready := axi.b.ready - port.io.bits.ar.ready := true.B - port.io.bits.r.valid := RegNext(port.io.bits.ar.valid, false.B) - port.io.bits.r.bits.id := RegNext(port.io.bits.ar.bits.id) - port.io.bits.r.bits.data := 0.U - port.io.bits.r.bits.resp := 0.U - port.io.bits.r.bits.last := true.B - port.io.bits.r.bits.user := 0.U.asTypeOf(port.io.bits.r.bits.user) - } + shell.mmio_arid := axi.ar.bits.id.asTypeOf(UInt(4.W)) + shell.mmio_araddr := axi.ar.bits.addr.asTypeOf(UInt(32.W)) + shell.mmio_arlen := axi.ar.bits.len + shell.mmio_arsize := axi.ar.bits.size + shell.mmio_arburst := axi.ar.bits.burst + shell.mmio_arvalid := axi.ar.valid + axi.ar.ready := shell.mmio_arready + + axi.r.bits.id := shell.mmio_rid.asTypeOf(axi.r.bits.id) + axi.r.bits.data := shell.mmio_rdata.asTypeOf(axi.r.bits.data) + axi.r.bits.resp := shell.mmio_rresp + axi.r.bits.last := shell.mmio_rlast + axi.r.valid := shell.mmio_rvalid + shell.mmio_rready := axi.r.ready }) class WithPegasusTiedOffJTAG @@ -80,7 +89,6 @@ class WithPegasusHarness new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithTieOffInterrupts ++ new chipyard.harness.WithGPIOTiedOff ++ - new chipyard.harness.WithTieOffL2FBusAXI ++ new chipyard.harness.WithClockFromHarness ++ new chipyard.harness.WithResetFromHarness ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++ diff --git a/arch/src/main/scala/sims/pegasus/PegasusTop.scala b/arch/src/main/scala/sims/pegasus/PegasusTop.scala index f0ffcca2..923ba9b7 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusTop.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusTop.scala @@ -5,14 +5,11 @@ import chisel3.util.HasBlackBoxInline import pegasus.PegasusShell -// PegasusTop — Vivado bitstream top-level for AU280. -// XDMA (DMA mode) + DDR4 + SCU + DigitalTop SoC. -// H2C pwrite offset = SoC paddr - 0x80000000 (DDR4 base). class PegasusTop extends BlackBox with HasBlackBoxInline { val io = IO(new Bundle { - val pcie_sys_clk = Input(Clock()) - val pcie_sys_clk_gt = Input(Clock()) + val pcie_refclk_p = Input(Bool()) + val pcie_refclk_n = Input(Bool()) val pcie_sys_rst_n = Input(Bool()) val pcie_exp_txp = Output(UInt(16.W)) val pcie_exp_txn = Output(UInt(16.W)) @@ -37,8 +34,8 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { setInline( "PegasusTop.v", """module PegasusTop( - | input pcie_sys_clk, - | input pcie_sys_clk_gt, + | input pcie_refclk_p, + | input pcie_refclk_n, | input pcie_sys_rst_n, | output [15:0] pcie_exp_txp, | output [15:0] pcie_exp_txn, @@ -65,34 +62,39 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | | wire soc_clk; | wire soc_reset; + | wire cpu_hold_reset; | - | // mem_axi4_0 wires (64-bit, 32-bit addr, 4-bit id) - | wire [3:0] mem_awid; - | wire [31:0] mem_awaddr; - | wire [7:0] mem_awlen; - | wire [2:0] mem_awsize; - | wire [1:0] mem_awburst; - | wire mem_awvalid, mem_awready; - | wire [63:0] mem_wdata; - | wire [7:0] mem_wstrb; - | wire mem_wlast, mem_wvalid, mem_wready; - | wire [3:0] mem_bid; - | wire [1:0] mem_bresp; - | wire mem_bvalid, mem_bready; - | wire [3:0] mem_arid; - | wire [31:0] mem_araddr; - | wire [7:0] mem_arlen; - | wire [2:0] mem_arsize; - | wire [1:0] mem_arburst; - | wire mem_arvalid, mem_arready; - | wire [3:0] mem_rid; - | wire [63:0] mem_rdata; - | wire [1:0] mem_rresp; - | wire mem_rlast, mem_rvalid, mem_rready; + | // mem_axi4: DigitalTop → shell crossbar → DDR4 + | wire [3:0] mem_awid; wire [31:0] mem_awaddr; + | wire [7:0] mem_awlen; wire [2:0] mem_awsize; + | wire [1:0] mem_awburst; wire mem_awvalid, mem_awready; + | wire [63:0] mem_wdata; wire [7:0] mem_wstrb; + | wire mem_wlast, mem_wvalid, mem_wready; + | wire [3:0] mem_bid; wire [1:0] mem_bresp; + | wire mem_bvalid, mem_bready; + | wire [3:0] mem_arid; wire [31:0] mem_araddr; + | wire [7:0] mem_arlen; wire [2:0] mem_arsize; + | wire [1:0] mem_arburst; wire mem_arvalid, mem_arready; + | wire [3:0] mem_rid; wire [63:0] mem_rdata; + | wire [1:0] mem_rresp; wire mem_rlast, mem_rvalid, mem_rready; + | + | // mmio_axi4: DigitalTop → shell SCU + | wire [3:0] mmio_awid; wire [31:0] mmio_awaddr; + | wire [7:0] mmio_awlen; wire [2:0] mmio_awsize; + | wire [1:0] mmio_awburst; wire mmio_awvalid, mmio_awready; + | wire [63:0] mmio_wdata; wire [7:0] mmio_wstrb; + | wire mmio_wlast, mmio_wvalid, mmio_wready; + | wire [3:0] mmio_bid; wire [1:0] mmio_bresp; + | wire mmio_bvalid, mmio_bready; + | wire [3:0] mmio_arid; wire [31:0] mmio_araddr; + | wire [7:0] mmio_arlen; wire [2:0] mmio_arsize; + | wire [1:0] mmio_arburst; wire mmio_arvalid, mmio_arready; + | wire [3:0] mmio_rid; wire [63:0] mmio_rdata; + | wire [1:0] mmio_rresp; wire mmio_rlast, mmio_rvalid, mmio_rready; | | PegasusShell shell ( - | .pcie_sys_clk (pcie_sys_clk), - | .pcie_sys_clk_gt (pcie_sys_clk_gt), + | .pcie_refclk_p (pcie_refclk_p), + | .pcie_refclk_n (pcie_refclk_n), | .pcie_sys_rst_n (pcie_sys_rst_n), | .pcie_exp_txp (pcie_exp_txp), | .pcie_exp_txn (pcie_exp_txn), @@ -116,7 +118,9 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .c0_ddr4_dqs_t (c0_ddr4_dqs_t), | .dut_clk (soc_clk), | .dut_reset (soc_reset), - | .uart_tx (1'b1), + | .cpu_hold_reset (cpu_hold_reset), + | .uart_tx (uart_txd), + | // mem_axi4 → crossbar → DDR4 | .chip_mem_awid (mem_awid), .chip_mem_awaddr (mem_awaddr), | .chip_mem_awlen (mem_awlen), .chip_mem_awsize (mem_awsize), | .chip_mem_awburst(mem_awburst), .chip_mem_awvalid(mem_awvalid), @@ -132,13 +136,30 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .chip_mem_arready(mem_arready), | .chip_mem_rid (mem_rid), .chip_mem_rdata (mem_rdata), | .chip_mem_rresp (mem_rresp), .chip_mem_rlast (mem_rlast), - | .chip_mem_rvalid (mem_rvalid), .chip_mem_rready (mem_rready) + | .chip_mem_rvalid (mem_rvalid), .chip_mem_rready (mem_rready), + | // mmio_axi4 → SCU + | .mmio_awid (mmio_awid), .mmio_awaddr (mmio_awaddr), + | .mmio_awlen (mmio_awlen), .mmio_awsize (mmio_awsize), + | .mmio_awburst (mmio_awburst), .mmio_awvalid (mmio_awvalid), + | .mmio_awready (mmio_awready), + | .mmio_wdata (mmio_wdata), .mmio_wstrb (mmio_wstrb), + | .mmio_wlast (mmio_wlast), .mmio_wvalid (mmio_wvalid), + | .mmio_wready (mmio_wready), + | .mmio_bid (mmio_bid), .mmio_bresp (mmio_bresp), + | .mmio_bvalid (mmio_bvalid), .mmio_bready (mmio_bready), + | .mmio_arid (mmio_arid), .mmio_araddr (mmio_araddr), + | .mmio_arlen (mmio_arlen), .mmio_arsize (mmio_arsize), + | .mmio_arburst (mmio_arburst), .mmio_arvalid (mmio_arvalid), + | .mmio_arready (mmio_arready), + | .mmio_rid (mmio_rid), .mmio_rdata (mmio_rdata), + | .mmio_rresp (mmio_rresp), .mmio_rlast (mmio_rlast), + | .mmio_rvalid (mmio_rvalid), .mmio_rready (mmio_rready) | ); | | DigitalTop soc ( | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (soc_clk), | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset (soc_reset), - | .resetctrl_hartIsInReset_0 (soc_reset), + | .resetctrl_hartIsInReset_0 (cpu_hold_reset), | .debug_clock (soc_clk), | .debug_reset (soc_reset), | .debug_systemjtag_reset (soc_reset), @@ -148,6 +169,7 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .debug_dmactiveAck (1'b0), | .uart_0_txd (uart_txd), | .uart_0_rxd (1'b1), + | // mem_axi4 → shell → DDR4 | .mem_axi4_0_aw_ready (mem_awready), | .mem_axi4_0_aw_valid (mem_awvalid), | .mem_axi4_0_aw_bits_id (mem_awid), @@ -177,17 +199,37 @@ class PegasusTop extends BlackBox with HasBlackBoxInline { | .mem_axi4_0_r_bits_data (mem_rdata), | .mem_axi4_0_r_bits_resp (mem_rresp), | .mem_axi4_0_r_bits_last (mem_rlast), - | .mmio_axi4_0_aw_ready (1'b0), - | .mmio_axi4_0_w_ready (1'b0), - | .mmio_axi4_0_b_valid (1'b0), - | .mmio_axi4_0_b_bits_id (4'h0), - | .mmio_axi4_0_b_bits_resp (2'h0), - | .mmio_axi4_0_ar_ready (1'b0), - | .mmio_axi4_0_r_valid (1'b0), - | .mmio_axi4_0_r_bits_id (4'h0), - | .mmio_axi4_0_r_bits_data (64'h0), - | .mmio_axi4_0_r_bits_resp (2'h0), - | .mmio_axi4_0_r_bits_last (1'b0), + | // mmio_axi4 → shell → SCU + | .mmio_axi4_0_aw_ready (mmio_awready), + | .mmio_axi4_0_aw_valid (mmio_awvalid), + | .mmio_axi4_0_aw_bits_id (mmio_awid), + | .mmio_axi4_0_aw_bits_addr (mmio_awaddr), + | .mmio_axi4_0_aw_bits_len (mmio_awlen), + | .mmio_axi4_0_aw_bits_size (mmio_awsize), + | .mmio_axi4_0_aw_bits_burst (mmio_awburst), + | .mmio_axi4_0_w_ready (mmio_wready), + | .mmio_axi4_0_w_valid (mmio_wvalid), + | .mmio_axi4_0_w_bits_data (mmio_wdata), + | .mmio_axi4_0_w_bits_strb (mmio_wstrb), + | .mmio_axi4_0_w_bits_last (mmio_wlast), + | .mmio_axi4_0_b_valid (mmio_bvalid), + | .mmio_axi4_0_b_ready (mmio_bready), + | .mmio_axi4_0_b_bits_id (mmio_bid), + | .mmio_axi4_0_b_bits_resp (mmio_bresp), + | .mmio_axi4_0_ar_ready (mmio_arready), + | .mmio_axi4_0_ar_valid (mmio_arvalid), + | .mmio_axi4_0_ar_bits_id (mmio_arid), + | .mmio_axi4_0_ar_bits_addr (mmio_araddr), + | .mmio_axi4_0_ar_bits_len (mmio_arlen), + | .mmio_axi4_0_ar_bits_size (mmio_arsize), + | .mmio_axi4_0_ar_bits_burst (mmio_arburst), + | .mmio_axi4_0_r_valid (mmio_rvalid), + | .mmio_axi4_0_r_ready (mmio_rready), + | .mmio_axi4_0_r_bits_id (mmio_rid), + | .mmio_axi4_0_r_bits_data (mmio_rdata), + | .mmio_axi4_0_r_bits_resp (mmio_rresp), + | .mmio_axi4_0_r_bits_last (mmio_rlast), + | // No inbound DMA port (removed WithCustomSlavePort) | .serial_tl_0_in_valid (1'b0), | .serial_tl_0_in_bits_phit (32'h0), | .serial_tl_0_out_ready (1'b0), @@ -206,8 +248,8 @@ object ElaboratePegasusTop extends App { class PegasusTopWrapper extends RawModule { val io = IO(new Bundle { - val pcie_sys_clk = Input(Clock()) - val pcie_sys_clk_gt = Input(Clock()) + val pcie_refclk_p = Input(Bool()) + val pcie_refclk_n = Input(Bool()) val pcie_sys_rst_n = Input(Bool()) val pcie_exp_txp = Output(UInt(16.W)) val pcie_exp_txn = Output(UInt(16.W)) @@ -230,27 +272,27 @@ object ElaboratePegasusTop extends App { }) val top = Module(new PegasusTop) - top.io.pcie_sys_clk := io.pcie_sys_clk - top.io.pcie_sys_clk_gt := io.pcie_sys_clk_gt - top.io.pcie_sys_rst_n := io.pcie_sys_rst_n - top.io.pcie_exp_rxp := io.pcie_exp_rxp - top.io.pcie_exp_rxn := io.pcie_exp_rxn - top.io.c0_sys_clk_p := io.c0_sys_clk_p - top.io.c0_sys_clk_n := io.c0_sys_clk_n - io.pcie_exp_txp := top.io.pcie_exp_txp - io.pcie_exp_txn := top.io.pcie_exp_txn - io.c0_ddr4_act_n := top.io.c0_ddr4_act_n - io.c0_ddr4_adr := top.io.c0_ddr4_adr - io.c0_ddr4_ba := top.io.c0_ddr4_ba - io.c0_ddr4_bg := top.io.c0_ddr4_bg - io.c0_ddr4_cke := top.io.c0_ddr4_cke - io.c0_ddr4_odt := top.io.c0_ddr4_odt - io.c0_ddr4_cs_n := top.io.c0_ddr4_cs_n - io.c0_ddr4_ck_t := top.io.c0_ddr4_ck_t - io.c0_ddr4_ck_c := top.io.c0_ddr4_ck_c - io.c0_ddr4_reset_n := top.io.c0_ddr4_reset_n - io.c0_ddr4_parity := top.io.c0_ddr4_parity - io.uart_txd := top.io.uart_txd + top.io.pcie_refclk_p := io.pcie_refclk_p + top.io.pcie_refclk_n := io.pcie_refclk_n + top.io.pcie_sys_rst_n := io.pcie_sys_rst_n + top.io.pcie_exp_rxp := io.pcie_exp_rxp + top.io.pcie_exp_rxn := io.pcie_exp_rxn + top.io.c0_sys_clk_p := io.c0_sys_clk_p + top.io.c0_sys_clk_n := io.c0_sys_clk_n + io.pcie_exp_txp := top.io.pcie_exp_txp + io.pcie_exp_txn := top.io.pcie_exp_txn + io.c0_ddr4_act_n := top.io.c0_ddr4_act_n + io.c0_ddr4_adr := top.io.c0_ddr4_adr + io.c0_ddr4_ba := top.io.c0_ddr4_ba + io.c0_ddr4_bg := top.io.c0_ddr4_bg + io.c0_ddr4_cke := top.io.c0_ddr4_cke + io.c0_ddr4_odt := top.io.c0_ddr4_odt + io.c0_ddr4_cs_n := top.io.c0_ddr4_cs_n + io.c0_ddr4_ck_t := top.io.c0_ddr4_ck_t + io.c0_ddr4_ck_c := top.io.c0_ddr4_ck_c + io.c0_ddr4_reset_n := top.io.c0_ddr4_reset_n + io.c0_ddr4_parity := top.io.c0_ddr4_parity + io.uart_txd := top.io.uart_txd } ChiselStage.emitSystemVerilogFile( diff --git a/bbdev b/bbdev index 22fcec02..7f2f3703 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 22fcec0213327e348edf93dc5519f4ae4fa1bf02 +Subproject commit 7f2f3703fab367ea89893ed9adc447e088597cdd diff --git a/thirdparty/pegasus b/thirdparty/pegasus index a56b27b8..338ad5e3 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit a56b27b80b1fe7c6194e0732846951a67a21e673 +Subproject commit 338ad5e3e1aff0f92177e5ee1fbd39b595f683b1 From 19e9bce59b6dd314274238285838faafee30b4bc Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 02:11:36 +0800 Subject: [PATCH 213/238] [arch/pegasus] fix: fix bugs in buildbistream --- .github/workflows/test.yml | 2 +- thirdparty/pegasus | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 6e44cca3..6bd192f4 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -25,7 +25,7 @@ jobs: git clean -fd git checkout ${{ github.head_ref }} git pull - git submodule update bbdev bebop compiler + git submodule update bbdev bebop compiler thirdparty/pegasus - name: Nix build shell: zsh {0} diff --git a/thirdparty/pegasus b/thirdparty/pegasus index 338ad5e3..48872ac4 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit 338ad5e3e1aff0f92177e5ee1fbd39b595f683b1 +Subproject commit 48872ac41e620f048a5c6188ff189d5bcb6161dc From 73e319e813ad180a2791f0c8f4ea22954a96dfdf Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 06:28:09 +0800 Subject: [PATCH 214/238] [arch/pegasus] feat: add CDC for 150MHz --- arch/src/main/scala/sims/pegasus/PegasusHarness.scala | 2 +- thirdparty/pegasus | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala index b1e0540a..46ba7253 100644 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala @@ -74,7 +74,7 @@ class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessI pegasusShell.io.mmio_arvalid := false.B pegasusShell.io.mmio_rready := false.B - def referenceClockFreqMHz: Double = 250.0 + def referenceClockFreqMHz: Double = 150.0 def referenceClock: Clock = pegasusShell.io.dut_clk def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset diff --git a/thirdparty/pegasus b/thirdparty/pegasus index 48872ac4..053536d3 160000 --- a/thirdparty/pegasus +++ b/thirdparty/pegasus @@ -1 +1 @@ -Subproject commit 48872ac41e620f048a5c6188ff189d5bcb6161dc +Subproject commit 053536d3fbc6ff6b9d7fbdedcaaa66944cb8e236 From a7f4a6722718d9ff5c30cd38de70ee75a5e718b8 Mon Sep 17 00:00:00 2001 From: Mikemy666 <2535634982@qq.com> Date: Wed, 22 Apr 2026 12:38:33 +0800 Subject: [PATCH 215/238] [eval]add:add run-dc.sh --- evals/run-dc.sh | 167 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100755 evals/run-dc.sh diff --git a/evals/run-dc.sh b/evals/run-dc.sh new file mode 100755 index 00000000..bef37efa --- /dev/null +++ b/evals/run-dc.sh @@ -0,0 +1,167 @@ +#!/bin/bash + +# exit script if any command fails +set -e +set -o pipefail + +KEEP_HIERARCHY=0 + +# DigitalTop +while [[ $# -gt 0 ]]; do + case $1 in + --srcdir) + SRC_DIR="$2" + shift 2 + ;; + --top) + TOP_MODULE="$2" + shift 2 + ;; + --keep-hierarchy) + KEEP_HIERARCHY=1 + shift + ;; + *) + echo "Unknown option: $1" + echo "Usage: $0 --srcdir [--top ] [--keep-hierarchy]" + echo "Example: $0 --srcdir arch/VecBall_1 --top VecBall_1 --keep-hierarchy" + exit 1 + ;; + esac +done + +if [ -z "$SRC_DIR" ]; then + echo "Error: Missing required parameter: srcdir" + echo "Usage: $0 --srcdir [--top ] [--keep-hierarchy]" + echo "Example: $0 --srcdir arch/VecBall_1 --top VecBall_1 --keep-hierarchy" + exit 1 +fi + + + +CYDIR=$(git rev-parse --show-toplevel) + +WORK_DIR="${CYDIR}/bb-tests/output/dc" +DESIGN_DIR="${CYDIR}/bb-tests/output/dc/design" +REPORT_DIR="${CYDIR}/bb-tests/output/dc/reports" +TMP_DIR="${CYDIR}/bb-tests/output/dc/tmp" +TCL_FILE="${CYDIR}/bb-tests/output/dc/dc_script.tcl" +DB_FILE="/opt/dc/lib/TSMCHOME/SRAM_m4swbsoffg0p99v0c/" + +mkdir -p $WORK_DIR +mkdir -p $DESIGN_DIR +mkdir -p $REPORT_DIR +mkdir -p $TMP_DIR + +#------------------------------------------------------------------- +# Step0 执行build Verilator +#------------------------------------------------------------------- +# ${CYDIR}/voyager-test/scripts/build-verilator.sh --config ${CONFIG} + +#------------------------------------------------------------------- +# Step1 搬运对应Config的Verilog到工作目录 +#------------------------------------------------------------------- +DESIGN_SOURCE_DIR="${CYDIR}/${SRC_DIR}" +rm -rf ${DESIGN_DIR}/* +cp -r ${DESIGN_SOURCE_DIR}/* ${DESIGN_DIR}/ + +#------------------------------------------------------------------- +# Step2 替换SRAM +#------------------------------------------------------------------- +# echo "正在检查SRAM File..." +# python ${CYDIR}/voyager-test/scripts/read_json.py $DB_FILE $DESIGN_DIR "/home/hxm123/tapeout-Voyager/sims/verilator/generated-src/chipyard.harness.TestHarness.GemminiRocketConfig/gen-collateral/metadata/seq_mems.json" + +#------------------------------------------------------------------- +# Step3 编写tcl脚本 +#------------------------------------------------------------------- + + +# 将文件路径格式化为 Tcl 所需的字符串（以空格分隔） +tcl_db_list="" + +COMPILE_CMD="compile_ultra -retime -scan" +HIERARCHY_SETUP="" +if [ "$KEEP_HIERARCHY" -eq 1 ]; then + COMPILE_CMD="compile_ultra -retime -scan -no_autoungroup" + HIERARCHY_SETUP=' +# Keep module boundaries for complete hierarchical reports. +set_ungroup [get_designs *] false +set_boundary_optimization [get_designs *] false +' +fi + +cat > $TCL_FILE << EOF +# 设置搜索路径 +set search_path [list . $DESIGN_DIR] +define_design_lib work -path $TMP_DIR + +set target_library "$tcl_db_list\ +/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_basic.db \ +/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ccs.db \ +/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ecsm.db \ +" +set link_library "$tcl_db_list\ +/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_basic.db \ +/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ccs.db \ +/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ecsm.db \ +" + +# 读取设计文件 +set file_list [glob -nocomplain -directory $DESIGN_DIR *.sv ] +analyze -format sverilog \$file_list +elaborate $TOP_MODULE + +# 设置顶层模块名 +set current_design "$TOP_MODULE" + +# 链接设计 +link + +$HIERARCHY_SETUP + +create_clock -name clock -period 2 [get_ports clock] + +set_clock_uncertainty 0.6 [get_clocks clock] + +set_input_delay 1.2 -clock clock [remove_from_collection [all_inputs] [get_ports clock]] +set_output_delay 0.6 -clock clock [all_outputs] + +#同频同相位 + +set_clock_equivalence clock + +#输出负载 + +set_load 0.08 [all_outputs] + +set_input_transition 0.2 [remove_from_collection [all_inputs] [get_ports clock]] + +set_clock_transition 0.08 [get_clocks clock] + + +$COMPILE_CMD +write -format ddc -hierarchy -output $REPORT_DIR/design_compiled.ddc + +# 生成报告 +report_area -hierarchy -nosplit > $REPORT_DIR/area.rpt +report_hierarchy -noleaf > $REPORT_DIR/hierarchy.rpt +report_timing > $REPORT_DIR/timing.rpt +report_power -hierarchy > $REPORT_DIR/power.rpt + +# 保存网表 +write -format verilog -output $REPORT_DIR/netlist.v + +# 退出 +exit +EOF + +#------------------------------------------------------------------- +# Step4 运行DC +#------------------------------------------------------------------- +echo "Running DC synthesis for design: ${CONFIG}, top module: $TOP_MODULE" +dc_shell -f $TCL_FILE + +# rm $TCL_FILE +rm -rf ${CYDIR}/alib-52 + +echo "Synthesis completed. Reports are available in $REPORT_DIR directory." From 5cf2029425370d3d0eac5d0591acba7322ceefbc Mon Sep 17 00:00:00 2001 From: Bohan Wang <140929282+Mikemy666@users.noreply.github.com> Date: Wed, 22 Apr 2026 13:55:52 +0800 Subject: [PATCH 216/238] [bbdev]: update bbdev for dc workflow (#32) --- bbdev | 2 +- docs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bbdev b/bbdev index 7f2f3703..feed3f76 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 7f2f3703fab367ea89893ed9adc447e088597cdd +Subproject commit feed3f76bbbba8de971b3b98df141f889e69cac0 diff --git a/docs b/docs index 1f006478..8ccb2876 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 1f00647846612b9bb92d6f9eda31050b34aa82fd +Subproject commit 8ccb287649239c9fa2471ea95eaaee93f66a748b From 32c84e414e2ebedbf5f18c5b2c48c77d457315ea Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 14:13:08 +0800 Subject: [PATCH 217/238] [bbdev/dc] refactor: clean up dc step --- bbdev | 2 +- evals/run-dc.sh | 167 ------------------------------------------------ 2 files changed, 1 insertion(+), 168 deletions(-) delete mode 100755 evals/run-dc.sh diff --git a/bbdev b/bbdev index feed3f76..5b44637b 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit feed3f76bbbba8de971b3b98df141f889e69cac0 +Subproject commit 5b44637bcf7480a4731e6fed98a555cb9fb9f2c6 diff --git a/evals/run-dc.sh b/evals/run-dc.sh deleted file mode 100755 index bef37efa..00000000 --- a/evals/run-dc.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash - -# exit script if any command fails -set -e -set -o pipefail - -KEEP_HIERARCHY=0 - -# DigitalTop -while [[ $# -gt 0 ]]; do - case $1 in - --srcdir) - SRC_DIR="$2" - shift 2 - ;; - --top) - TOP_MODULE="$2" - shift 2 - ;; - --keep-hierarchy) - KEEP_HIERARCHY=1 - shift - ;; - *) - echo "Unknown option: $1" - echo "Usage: $0 --srcdir [--top ] [--keep-hierarchy]" - echo "Example: $0 --srcdir arch/VecBall_1 --top VecBall_1 --keep-hierarchy" - exit 1 - ;; - esac -done - -if [ -z "$SRC_DIR" ]; then - echo "Error: Missing required parameter: srcdir" - echo "Usage: $0 --srcdir [--top ] [--keep-hierarchy]" - echo "Example: $0 --srcdir arch/VecBall_1 --top VecBall_1 --keep-hierarchy" - exit 1 -fi - - - -CYDIR=$(git rev-parse --show-toplevel) - -WORK_DIR="${CYDIR}/bb-tests/output/dc" -DESIGN_DIR="${CYDIR}/bb-tests/output/dc/design" -REPORT_DIR="${CYDIR}/bb-tests/output/dc/reports" -TMP_DIR="${CYDIR}/bb-tests/output/dc/tmp" -TCL_FILE="${CYDIR}/bb-tests/output/dc/dc_script.tcl" -DB_FILE="/opt/dc/lib/TSMCHOME/SRAM_m4swbsoffg0p99v0c/" - -mkdir -p $WORK_DIR -mkdir -p $DESIGN_DIR -mkdir -p $REPORT_DIR -mkdir -p $TMP_DIR - -#------------------------------------------------------------------- -# Step0 执行build Verilator -#------------------------------------------------------------------- -# ${CYDIR}/voyager-test/scripts/build-verilator.sh --config ${CONFIG} - -#------------------------------------------------------------------- -# Step1 搬运对应Config的Verilog到工作目录 -#------------------------------------------------------------------- -DESIGN_SOURCE_DIR="${CYDIR}/${SRC_DIR}" -rm -rf ${DESIGN_DIR}/* -cp -r ${DESIGN_SOURCE_DIR}/* ${DESIGN_DIR}/ - -#------------------------------------------------------------------- -# Step2 替换SRAM -#------------------------------------------------------------------- -# echo "正在检查SRAM File..." -# python ${CYDIR}/voyager-test/scripts/read_json.py $DB_FILE $DESIGN_DIR "/home/hxm123/tapeout-Voyager/sims/verilator/generated-src/chipyard.harness.TestHarness.GemminiRocketConfig/gen-collateral/metadata/seq_mems.json" - -#------------------------------------------------------------------- -# Step3 编写tcl脚本 -#------------------------------------------------------------------- - - -# 将文件路径格式化为 Tcl 所需的字符串（以空格分隔） -tcl_db_list="" - -COMPILE_CMD="compile_ultra -retime -scan" -HIERARCHY_SETUP="" -if [ "$KEEP_HIERARCHY" -eq 1 ]; then - COMPILE_CMD="compile_ultra -retime -scan -no_autoungroup" - HIERARCHY_SETUP=' -# Keep module boundaries for complete hierarchical reports. -set_ungroup [get_designs *] false -set_boundary_optimization [get_designs *] false -' -fi - -cat > $TCL_FILE << EOF -# 设置搜索路径 -set search_path [list . $DESIGN_DIR] -define_design_lib work -path $TMP_DIR - -set target_library "$tcl_db_list\ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_basic.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ccs.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ecsm.db \ -" -set link_library "$tcl_db_list\ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_basic.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ccs.db \ -/data0/tools/lib/db/scc28nhkcp_hdc35p140_rvt_ffg_v0p99_0c_ecsm.db \ -" - -# 读取设计文件 -set file_list [glob -nocomplain -directory $DESIGN_DIR *.sv ] -analyze -format sverilog \$file_list -elaborate $TOP_MODULE - -# 设置顶层模块名 -set current_design "$TOP_MODULE" - -# 链接设计 -link - -$HIERARCHY_SETUP - -create_clock -name clock -period 2 [get_ports clock] - -set_clock_uncertainty 0.6 [get_clocks clock] - -set_input_delay 1.2 -clock clock [remove_from_collection [all_inputs] [get_ports clock]] -set_output_delay 0.6 -clock clock [all_outputs] - -#同频同相位 - -set_clock_equivalence clock - -#输出负载 - -set_load 0.08 [all_outputs] - -set_input_transition 0.2 [remove_from_collection [all_inputs] [get_ports clock]] - -set_clock_transition 0.08 [get_clocks clock] - - -$COMPILE_CMD -write -format ddc -hierarchy -output $REPORT_DIR/design_compiled.ddc - -# 生成报告 -report_area -hierarchy -nosplit > $REPORT_DIR/area.rpt -report_hierarchy -noleaf > $REPORT_DIR/hierarchy.rpt -report_timing > $REPORT_DIR/timing.rpt -report_power -hierarchy > $REPORT_DIR/power.rpt - -# 保存网表 -write -format verilog -output $REPORT_DIR/netlist.v - -# 退出 -exit -EOF - -#------------------------------------------------------------------- -# Step4 运行DC -#------------------------------------------------------------------- -echo "Running DC synthesis for design: ${CONFIG}, top module: $TOP_MODULE" -dc_shell -f $TCL_FILE - -# rm $TCL_FILE -rm -rf ${CYDIR}/alib-52 - -echo "Synthesis completed. Reports are available in $REPORT_DIR directory." From 9b83a41a56acd9881ac97042f4709206cf0e412f Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 15:06:37 +0800 Subject: [PATCH 218/238] [bbdev] fix: update bbdev to the correct commit --- bbdev | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bbdev b/bbdev index 5b44637b..104fda38 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 5b44637bcf7480a4731e6fed98a555cb9fb9f2c6 +Subproject commit 104fda380e6d46f661b33f36a7685e543d5b20b7 From 904f300b2e90eed2f41b69bdc0a59ebd45090f8a Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 18:01:24 +0800 Subject: [PATCH 219/238] [bbdev/palladium] del: remove palladium verilog API and related event handling from bbdev --- .gitmodules | 3 --- arch/build.sbt | 4 +--- arch/build.sc | 30 +----------------------------- bbdev | 2 +- scripts/nix/build-all.sh | 26 ++++++++++++++++++-------- thirdparty/palladium | 1 - 6 files changed, 21 insertions(+), 45 deletions(-) delete mode 160000 thirdparty/palladium diff --git a/.gitmodules b/.gitmodules index 35308260..28ee77fe 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,9 +7,6 @@ [submodule "bbdev"] path = bbdev url = https://github.com/DangoSys/bbdev.git -[submodule "thirdparty/palladium"] - path = thirdparty/palladium - url = https://github.com/SEU-ACAL/awesome-palladium.git [submodule "docs"] path = docs url = https://github.com/DangoSys/documents.git diff --git a/arch/build.sbt b/arch/build.sbt index 19c9d68a..a62345ca 100644 --- a/arch/build.sbt +++ b/arch/build.sbt @@ -34,14 +34,12 @@ lazy val scalaTestSettings = Seq( // ------------------------------------------------------------------------------ lazy val chipyard = ProjectRef(file("thirdparty/chipyard"), "chipyard") lazy val firechip = ProjectRef(file("thirdparty/chipyard"), "firechip") -// Palladium FPGA subproject -lazy val palladium = ProjectRef(file("../thirdparty/palladium"), "palladium") // ------------------------------------------------------------------------------ // Project Settings // ------------------------------------------------------------------------------ lazy val buckyball = (project in file(".")) - .dependsOn(chipyard, firechip, palladium) + .dependsOn(chipyard, firechip) .settings( name := "buckyball", organization := "com.buckyball", diff --git a/arch/build.sc b/arch/build.sc index 42dc2e15..48e5fb55 100644 --- a/arch/build.sc +++ b/arch/build.sc @@ -23,8 +23,7 @@ object buckyball extends SbtModule { m => // Add chipyard and rocket-chip dependencies override def moduleDeps = Seq( chipyard, - firechip, - palladium + firechip ) ++ (if (hasPegasus) Seq(pegasus) else Seq.empty) override def ivyDeps = Agg( @@ -937,33 +936,6 @@ object fpga_shells extends SbtModule { } -// Palladium FPGA subproject (external reference) -object palladium extends SbtModule { - override def millSourcePath = os.pwd / os.up / "thirdparty" / "palladium" - override def scalaVersion = "2.13.12" - - // Add chipyard and fpga_shells as dependencies - override def moduleDeps = Seq( - chipyard, - fpga_shells - ) - - override def ivyDeps = Agg( - ivy"org.chipsalliance::chisel:6.5.0" - ) - - override def scalacPluginIvyDeps = Agg( - ivy"org.chipsalliance:::chisel-plugin:6.5.0" - ) - - override def scalacOptions = Seq( - "-deprecation", - "-unchecked", - "-Ymacro-annotations" - ) - -} - // Pegasus FPGA framework Chisel sources // Physical location: pegasus/chisel/ (outside arch/) // Pure Chisel only — no Chipyard dependency (avoids circular dep with buckyball) diff --git a/bbdev b/bbdev index 104fda38..93321b9a 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 104fda380e6d46f661b33f36a7685e543d5b20b7 +Subproject commit 93321b9a1b223eb24230b88468fadb8fc277aab2 diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index dd581d43..1aa94dab 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -30,9 +30,9 @@ SKIP_LIST=() VERBOSE_FLAG="" INSTALL_IN_NIX=0 -while [ "$1" != "" ]; +while [ "$#" -gt 0 ]; do - case $1 in + case "$1" in -h | --help ) usage 3 ;; --verbose | -v) @@ -40,7 +40,11 @@ do set -x ;; --skip | -s) shift - SKIP_LIST+=(${1}) ;; + if [ "$#" -eq 0 ]; then + echo "Error: --skip requires a step number" >&2 + usage 1 + fi + SKIP_LIST+=("$1") ;; --install-in-nix) INSTALL_IN_NIX=1 ;; * ) @@ -76,18 +80,24 @@ function begin_step begin_step "0-1" "submodules init" # git submodule update --init --progress --jobs 8 cd ${BBDIR} -git submodule update --init --progress --jobs 8 \ +git submodule update --init --progress --jobs 8 \ arch/thirdparty/chipyard \ bb-tests/workloads/lib/kernel \ bbdev \ bebop \ compiler \ docs \ - thirdparty/palladium \ thirdparty/pegasus \ thirdparty/waveform-mcp -# fpga/fpga-shells is needed by palladium -cd ${BBDIR}/arch/thirdparty/chipyard && git submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim + +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim +# I dont know why below is need for chipyard submodules, but it is +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde tools/rocket-dsp-utils generators/rocc-acc-utils generators/bar-fetchers +git -C ${BBDIR}/arch/thirdparty/chipyard/tools/cde status --short --branch +git -C ${BBDIR}/arch/thirdparty/chipyard/tools/rocket-dsp-utils status --short --branch +git -C ${BBDIR}/arch/thirdparty/chipyard/generators/rocc-acc-utils status --short --branch +git -C ${BBDIR}/arch/thirdparty/chipyard/generators/bar-fetchers status --short --branch +########################################## begin_step "0-2" "Nix environment setup" cd ${BBDIR} @@ -113,7 +123,7 @@ fi if run_step "2"; then begin_step "2" "Compiler installation" cd ${BBDIR}/compiler - git submodule update --init llvm + git submodule update --init --progress llvm mkdir -p llvm/build && cd llvm/build cmake -G Ninja ../llvm \ diff --git a/thirdparty/palladium b/thirdparty/palladium deleted file mode 160000 index 3990e3ed..00000000 --- a/thirdparty/palladium +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 3990e3edfc5176599d7789bd357ae17c2c6163cc From 8a3a53337155f62203924a068e6bd015ce6c6b39 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 22 Apr 2026 18:28:17 +0800 Subject: [PATCH 220/238] [bb-tests] fix: conditionally add kernel subdirectory and streamline submodule update commands --- bb-tests/workloads/lib/CMakeLists.txt | 5 ++++- scripts/nix/build-all.sh | 12 ++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/bb-tests/workloads/lib/CMakeLists.txt b/bb-tests/workloads/lib/CMakeLists.txt index 7f34428d..992ec47f 100644 --- a/bb-tests/workloads/lib/CMakeLists.txt +++ b/bb-tests/workloads/lib/CMakeLists.txt @@ -1,2 +1,5 @@ add_subdirectory(bbhw) -add_subdirectory(kernel) + +if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/kernel/CMakeLists.txt") + add_subdirectory(kernel) +endif() diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 1aa94dab..946129f4 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -78,9 +78,8 @@ function begin_step } begin_step "0-1" "submodules init" -# git submodule update --init --progress --jobs 8 -cd ${BBDIR} -git submodule update --init --progress --jobs 8 \ + +git -C ${BBDIR} submodule update --init --progress --jobs 8 \ arch/thirdparty/chipyard \ bb-tests/workloads/lib/kernel \ bbdev \ @@ -89,20 +88,17 @@ git submodule update --init --progress --jobs 8 \ docs \ thirdparty/pegasus \ thirdparty/waveform-mcp +# I dont know why below is need for buckyball submodules, but it is +git -C ${BBDIR} submodule update --init --checkout --force thirdparty/pegasus git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim # I dont know why below is need for chipyard submodules, but it is git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde tools/rocket-dsp-utils generators/rocc-acc-utils generators/bar-fetchers -git -C ${BBDIR}/arch/thirdparty/chipyard/tools/cde status --short --branch -git -C ${BBDIR}/arch/thirdparty/chipyard/tools/rocket-dsp-utils status --short --branch -git -C ${BBDIR}/arch/thirdparty/chipyard/generators/rocc-acc-utils status --short --branch -git -C ${BBDIR}/arch/thirdparty/chipyard/generators/bar-fetchers status --short --branch ########################################## begin_step "0-2" "Nix environment setup" cd ${BBDIR} nix build - if [ "${INSTALL_IN_NIX}" != "1" ]; then SKIP_ARGS="" for skip in "${SKIP_LIST[@]}"; do From 6ce6272a4cb10db98e6cbeb378283e96b5391e9e Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 23 Apr 2026 02:36:04 +0800 Subject: [PATCH 221/238] [bbdev] feat: bump bbdev to the latest version with api testing --- bbdev | 2 +- flake.nix | 5 ++--- scripts/nix/build-env-system.nix | 2 ++ sourceme.sh | 1 - 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bbdev b/bbdev index 93321b9a..b270a085 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 93321b9a1b223eb24230b88468fadb8fc277aab2 +Subproject commit b270a08519a1b44604e48db6785e5148264501ae diff --git a/flake.nix b/flake.nix index e24c9a7a..62f276ba 100644 --- a/flake.nix +++ b/flake.nix @@ -86,15 +86,14 @@ # System utilities systemTools.rsync systemTools.nodejs - - git + systemTools.git + # systemTools.npm ]; }; # nix develop devShells.default = pkgs.mkShell { buildInputs = with pkgs; [ - git clibs.zlib-dev clibs.zlib clibs.readline-dev diff --git a/scripts/nix/build-env-system.nix b/scripts/nix/build-env-system.nix index bc5a34e6..53c403f7 100644 --- a/scripts/nix/build-env-system.nix +++ b/scripts/nix/build-env-system.nix @@ -3,4 +3,6 @@ { rsync = pkgs.rsync; nodejs = pkgs.nodejs; + git = pkgs.git; + # npm = pkgs.npm; } diff --git a/sourceme.sh b/sourceme.sh index 2cdffb4f..c197c3bf 100644 --- a/sourceme.sh +++ b/sourceme.sh @@ -24,7 +24,6 @@ export LLVM_MLIR_BUILD_DIR="${BBDIR}/compiler/llvm/build" export PYTHONPATH="${BBDIR}/compiler/llvm/build/tools/mlir/python_packages/mlir_core:${BBDIR}/compiler/build/python_packages:$PYTHONPATH" export BUDDY_BINARY_DIR="${BBDIR}/compiler/build/bin" export RISCV="${BBDIR}/result" -export PATH="${BBDIR}/thirdparty/libgloss/install/lib:$PATH" export PATH="${BUDDY_BINARY_DIR}:${PATH}" #===----------------------------------------------------------------------------=== From afd5dfd2e6bcf66e8da9359b77b1d12dac376cbc Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 23 Apr 2026 05:52:49 +0800 Subject: [PATCH 222/238] [arch/examples feat: update to our band new config system with serialisation --- .../scala/examples/goban/CustomConfigs.scala | 35 +-- .../goban/configs/GobanTopParam.scala | 15 ++ .../scala/examples/goban/configs/default.json | 3 + .../goban/tiles/GobanTilesConfig.scala | 43 ++++ .../goban/tiles/configs/TilesConfig.scala | 15 ++ .../examples/goban/tiles/configs/default.json | 5 + .../tiles/gobantile/GobanTileConfig.scala | 18 ++ .../gobantile/configs/GobanTileParam.scala | 16 ++ .../tiles/gobantile/configs/default.json | 8 + .../gobantile/gobancore/GobanCoreConfig.scala | 16 ++ .../balldomain/configs/BallDomainConfig.scala | 15 ++ .../gobancore/balldomain/configs/default.json | 9 + .../gobancore/configs/GobanCoreParam.scala | 16 ++ .../gobantile/gobancore/configs/default.json | 3 + .../scala/examples/konbi/CustomConfigs.scala | 11 + .../konbi/configs/KonbiTopParam.scala | 15 ++ .../scala/examples/konbi/configs/default.json | 3 + .../konbi/tiles/KonbiTilesConfig.scala | 44 ++++ .../konbi/tiles/configs/TilesConfig.scala | 15 ++ .../examples/konbi/tiles/configs/default.json | 5 + .../tiles/konbitile/KonbiTileConfig.scala | 18 ++ .../konbitile/configs/KonbiTileParam.scala | 16 ++ .../tiles/konbitile/configs/default.json | 9 + .../konbitile/decodecore/Core1Config.scala | 17 ++ .../balldomain/configs/BallDomainConfig.scala | 15 ++ .../balldomain/configs/default.json | 30 +++ .../decodecore/configs/KonbiCoreParam.scala | 17 ++ .../konbitile/decodecore/configs/default.json | 3 + .../konbitile/prefillcore/Core0Config.scala | 17 ++ .../balldomain/configs/BallDomainConfig.scala | 15 ++ .../balldomain/configs/default.json | 30 +++ .../prefillcore/configs/KonbiCoreParam.scala | 19 ++ .../prefillcore/configs/default.json | 3 + .../scala/examples/poly/CustomConfigs.scala | 17 ++ .../examples/poly/configs/PolyTopParam.scala | 15 ++ .../scala/examples/poly/configs/default.json | 3 + .../examples/poly/tiles/PolyTilesConfig.scala | 45 ++++ .../poly/tiles/configs/TilesConfig.scala | 15 ++ .../examples/poly/tiles/configs/default.json | 7 + .../poly/tiles/cputile/CpuTileConfig.scala | 23 ++ .../tiles/cputile/configs/CpuTileParam.scala | 15 ++ .../poly/tiles/cputile/configs/default.json | 5 + .../tiles/cputile/core/CpuCoreConfig.scala | 17 ++ .../cputile/core/configs/CpuCoreParam.scala | 17 ++ .../tiles/cputile/core/configs/default.json | 2 + .../lightdnntile/LightDnnTileConfig.scala | 16 ++ .../poly/tiles/llmtile/LlmTileConfig.scala | 16 ++ .../scala/examples/toy/CustomConfigs.scala | 6 +- .../scala/examples/toy/balldomain/DISA.scala | 51 ---- .../toy/balldomain/DomainDecoder.scala | 226 ------------------ .../scala/examples/toy/balldomain/README.md | 192 --------------- .../examples/toy/balldomain/bbus/README.md | 138 ----------- .../toy/balldomain/bbus/busRegister.scala | 41 ---- .../examples/toy/configs/ToyTopParam.scala | 15 ++ .../scala/examples/toy/configs/default.json | 3 + .../examples/toy/tiles/ToyTilesConfig.scala | 48 ++++ .../toy/tiles/configs/ToyTilesParam.scala | 16 ++ .../examples/toy/tiles/configs/default.json | 5 + .../toy/tiles/toytile/ToyTileConfig.scala | 30 +++ .../tiles/toytile/configs/ToyTileParam.scala | 16 ++ .../toy/tiles/toytile/configs/default.json | 5 + .../tiles/toytile/toycore/ToyCoreConfig.scala | 23 ++ .../balldomain/configs/BallDomainConfig.scala | 14 ++ .../toycore/balldomain/configs/default.json | 48 ++++ .../toycore/configs/ToyCoreParam.scala | 17 ++ .../toytile/toycore/configs/default.json | 3 + .../balldomain/BallDomain.scala | 47 ++-- .../framework/balldomain/bbus/bbus.scala | 18 +- .../balldomain/configs/BallDomainParam.scala | 28 ++- .../framework/balldomain/configs/default.json | 14 -- .../balldomain/decoder/BallDecodeCmd.scala | 29 +++ .../decoder/BallDomainDecoder.scala | 83 +++++++ .../balldomain/rs/reservationStation.scala | 2 +- .../builtin/configloader/ConfigLoader.scala | 20 ++ .../scala/framework/core/bbtile/BBTile.scala | 165 +++++++------ .../framework/core/bbtile/BBTileParams.scala | 42 +++- .../core/bbtile/BuckyballAccelerator.scala | 2 +- .../scala/framework/core/bbtile/Configs.scala | 89 ++++++- .../framework/core/bbtile/RocketCoreBB.scala | 6 +- .../scala/sims/verilator/TargetConfig.scala | 16 ++ .../lib/bbhw/isa/02_gemmini_config.c | 4 +- .../workloads/lib/bbhw/isa/03_gemmini_flush.c | 3 +- .../lib/bbhw/isa/53_gemmini_preload.c | 5 +- .../bbhw/isa/66_gemmini_compute_preloaded.c | 4 +- .../bbhw/isa/67_gemmini_compute_accumulated.c | 4 +- scripts/nix/build-env-scala.nix | 2 +- 86 files changed, 1372 insertions(+), 840 deletions(-) create mode 100644 arch/src/main/scala/examples/goban/configs/GobanTopParam.scala create mode 100644 arch/src/main/scala/examples/goban/configs/default.json create mode 100644 arch/src/main/scala/examples/goban/tiles/GobanTilesConfig.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/configs/TilesConfig.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/configs/default.json create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/GobanTileConfig.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/configs/GobanTileParam.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/configs/default.json create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/GobanCoreConfig.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/BallDomainConfig.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/default.json create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/GobanCoreParam.scala create mode 100644 arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/CustomConfigs.scala create mode 100644 arch/src/main/scala/examples/konbi/configs/KonbiTopParam.scala create mode 100644 arch/src/main/scala/examples/konbi/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/tiles/KonbiTilesConfig.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/configs/TilesConfig.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/KonbiTileConfig.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/configs/KonbiTileParam.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/Core1Config.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/BallDomainConfig.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/KonbiCoreParam.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/Core0Config.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/BallDomainConfig.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/default.json create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/KonbiCoreParam.scala create mode 100644 arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/default.json create mode 100644 arch/src/main/scala/examples/poly/CustomConfigs.scala create mode 100644 arch/src/main/scala/examples/poly/configs/PolyTopParam.scala create mode 100644 arch/src/main/scala/examples/poly/configs/default.json create mode 100644 arch/src/main/scala/examples/poly/tiles/PolyTilesConfig.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/configs/TilesConfig.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/configs/default.json create mode 100644 arch/src/main/scala/examples/poly/tiles/cputile/CpuTileConfig.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/cputile/configs/CpuTileParam.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/cputile/configs/default.json create mode 100644 arch/src/main/scala/examples/poly/tiles/cputile/core/CpuCoreConfig.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/cputile/core/configs/CpuCoreParam.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/cputile/core/configs/default.json create mode 100644 arch/src/main/scala/examples/poly/tiles/lightdnntile/LightDnnTileConfig.scala create mode 100644 arch/src/main/scala/examples/poly/tiles/llmtile/LlmTileConfig.scala delete mode 100644 arch/src/main/scala/examples/toy/balldomain/DISA.scala delete mode 100644 arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala delete mode 100644 arch/src/main/scala/examples/toy/balldomain/README.md delete mode 100644 arch/src/main/scala/examples/toy/balldomain/bbus/README.md delete mode 100644 arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala create mode 100644 arch/src/main/scala/examples/toy/configs/ToyTopParam.scala create mode 100644 arch/src/main/scala/examples/toy/configs/default.json create mode 100644 arch/src/main/scala/examples/toy/tiles/ToyTilesConfig.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/configs/ToyTilesParam.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/configs/default.json create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/ToyTileConfig.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/configs/ToyTileParam.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/configs/default.json create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/toycore/ToyCoreConfig.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/BallDomainConfig.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/ToyCoreParam.scala create mode 100644 arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/default.json rename arch/src/main/scala/{examples/toy => framework}/balldomain/BallDomain.scala (74%) delete mode 100644 arch/src/main/scala/framework/balldomain/configs/default.json create mode 100644 arch/src/main/scala/framework/balldomain/decoder/BallDecodeCmd.scala create mode 100644 arch/src/main/scala/framework/balldomain/decoder/BallDomainDecoder.scala create mode 100644 arch/src/main/scala/framework/builtin/configloader/ConfigLoader.scala diff --git a/arch/src/main/scala/examples/goban/CustomConfigs.scala b/arch/src/main/scala/examples/goban/CustomConfigs.scala index 578e6c57..08bc392a 100644 --- a/arch/src/main/scala/examples/goban/CustomConfigs.scala +++ b/arch/src/main/scala/examples/goban/CustomConfigs.scala @@ -1,44 +1,21 @@ package examples.goban import org.chipsalliance.cde.config.Config -import framework.core.bbtile.WithNBBTiles -import framework.top.GlobalConfig -import framework.top.configs.TopConfig +import examples.goban.tiles.WithNGobanTiles -import freechips.rocketchip.subsystem.InSubsystem - -/** - * Goban: multi-core BBTile configuration. - * - * Each BBTile contains nCores Rocket cores, each paired with a BuckyballAccelerator. - * All accelerators within the tile share a single SharedMemBackend and BarrierUnit. - * The ISA, Ball operators, and memory layout are identical to the toy configuration. - */ -object GobanConfig { - - /** Number of cores inside each BBTile. */ - val nCores: Int = 4 - - /** GlobalConfig for goban: same as toy but with nCores set. */ - def apply(): GlobalConfig = { - val base = GlobalConfig() - base.copy(top = base.top.copy(nCores = nCores)) - } - -} - -/** 1 BBTile × 4 cores (4 Rocket + 4 Buckyball, shared SharedMem + BarrierUnit) */ +/** 1 BBTile × 4 buckyball slots (shared SharedMem + BarrierUnit) */ class BuckyballGobanConfig extends Config( - new WithNBBTiles(1, buckyballConfig = GobanConfig()) ++ + new WithNGobanTiles ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) -/** 2 BBTiles × 4 cores = 8 total cores */ +/** 2 BBTiles × 4 slots = 8 total slots */ class BuckyballGoban2TileConfig extends Config( - new WithNBBTiles(2, buckyballConfig = GobanConfig()) ++ + new WithNGobanTiles ++ + new WithNGobanTiles ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) diff --git a/arch/src/main/scala/examples/goban/configs/GobanTopParam.scala b/arch/src/main/scala/examples/goban/configs/GobanTopParam.scala new file mode 100644 index 00000000..9a9e755e --- /dev/null +++ b/arch/src/main/scala/examples/goban/configs/GobanTopParam.scala @@ -0,0 +1,15 @@ +package examples.goban.configs + +import upickle.default._ + +case class GobanConfig(nTiles: Int) + +object GobanConfig { + implicit val rw: ReadWriter[GobanConfig] = macroRW + + def apply(): GobanConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/goban/configs/default.json").mkString + read[GobanConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/goban/configs/default.json b/arch/src/main/scala/examples/goban/configs/default.json new file mode 100644 index 00000000..caa6eb33 --- /dev/null +++ b/arch/src/main/scala/examples/goban/configs/default.json @@ -0,0 +1,3 @@ +{ + "nTiles": 1 +} diff --git a/arch/src/main/scala/examples/goban/tiles/GobanTilesConfig.scala b/arch/src/main/scala/examples/goban/tiles/GobanTilesConfig.scala new file mode 100644 index 00000000..15b6b170 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/GobanTilesConfig.scala @@ -0,0 +1,43 @@ +package examples.goban.tiles + +import org.chipsalliance.cde.config.{Config, Parameters} +import framework.core.bbtile.WithBBTile +import framework.top.GlobalConfig +import examples.goban.configs.GobanConfig +import framework.builtin.configloader.ConfigLoader +import examples.goban.tiles.configs.TilesConfig + +/** + * Top-level Chipyard config fragment for the goban example. + * + * Same JSON-driven assembly pattern as toy. Goban's distinguishing trait is + * that each tile carries multiple homogeneous Buckyball cores; the per-tile + * core list is described by the corresponding `TileConfig` object. + */ +class WithNGobanTiles(withBuckyball: Boolean = true) extends Config(WithNGobanTiles.assemble(withBuckyball)) + +object WithNGobanTiles { + + def assemble(withBuckyball: Boolean): Parameters = { + val nTiles = GobanConfig().nTiles + val tileConfigs = TilesConfig().tileConfigs + require( + tileConfigs.size == nTiles, + s"goban tiles/configs/default.json lists ${tileConfigs.size} tile configs " + + s"but goban/configs/default.json declares nTiles=$nTiles" + ) + + val fragments: Seq[Config] = tileConfigs.map { name => + val perCore = ConfigLoader.loadApply[Seq[Option[GlobalConfig]]](name) + val resolved = if (withBuckyball) perCore else perCore.map(_ => None) + new WithBBTile( + withBuckyball = resolved.exists(_.isDefined), + nCoresPerTile = perCore.size, + buckyballPerCore = Some(resolved) + ) + } + + fragments.reduce[Parameters](_ ++ _) + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/configs/TilesConfig.scala b/arch/src/main/scala/examples/goban/tiles/configs/TilesConfig.scala new file mode 100644 index 00000000..38816273 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/configs/TilesConfig.scala @@ -0,0 +1,15 @@ +package examples.goban.tiles.configs + +import upickle.default._ + +case class TilesConfig(tileConfigs: Seq[String]) + +object TilesConfig { + implicit val rw: ReadWriter[TilesConfig] = macroRW + + def apply(): TilesConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/goban/tiles/configs/default.json").mkString + read[TilesConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/configs/default.json b/arch/src/main/scala/examples/goban/tiles/configs/default.json new file mode 100644 index 00000000..651a20b3 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/configs/default.json @@ -0,0 +1,5 @@ +{ + "tileConfigs": [ + "examples.goban.tiles.gobantile.GobanTileConfig" + ] +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/GobanTileConfig.scala b/arch/src/main/scala/examples/goban/tiles/gobantile/GobanTileConfig.scala new file mode 100644 index 00000000..1babe66c --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/GobanTileConfig.scala @@ -0,0 +1,18 @@ +package examples.goban.tiles.gobantile + +import framework.top.GlobalConfig +import framework.builtin.configloader.ConfigLoader +import examples.goban.tiles.gobantile.configs.{GobanTileConfig => GobanTileParam} + +object GobanTileConfig { + + def apply(): Seq[Option[GlobalConfig]] = { + val tileParam = GobanTileParam() + val nCores = tileParam.coreConfigs.size + tileParam.coreConfigs.map { name => + val cfg = ConfigLoader.loadApply[GlobalConfig](name) + Some(cfg.copy(top = cfg.top.copy(nCores = nCores))) + } + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/configs/GobanTileParam.scala b/arch/src/main/scala/examples/goban/tiles/gobantile/configs/GobanTileParam.scala new file mode 100644 index 00000000..636f99eb --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/configs/GobanTileParam.scala @@ -0,0 +1,16 @@ +package examples.goban.tiles.gobantile.configs + +import upickle.default._ + +case class GobanTileConfig(coreConfigs: Seq[String]) + +object GobanTileConfig { + implicit val rw: ReadWriter[GobanTileConfig] = macroRW + + def apply(): GobanTileConfig = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/examples/goban/tiles/gobantile/configs/default.json").mkString + read[GobanTileConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/configs/default.json b/arch/src/main/scala/examples/goban/tiles/gobantile/configs/default.json new file mode 100644 index 00000000..febe07ad --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/configs/default.json @@ -0,0 +1,8 @@ +{ + "coreConfigs": [ + "examples.goban.tiles.gobantile.gobancore.GobanCoreConfig", + "examples.goban.tiles.gobantile.gobancore.GobanCoreConfig", + "examples.goban.tiles.gobantile.gobancore.GobanCoreConfig", + "examples.goban.tiles.gobantile.gobancore.GobanCoreConfig" + ] +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/GobanCoreConfig.scala b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/GobanCoreConfig.scala new file mode 100644 index 00000000..e33b33c2 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/GobanCoreConfig.scala @@ -0,0 +1,16 @@ +package examples.goban.tiles.gobantile.gobancore + +import framework.top.GlobalConfig +import framework.balldomain.configs.BallDomainParam +import framework.builtin.configloader.ConfigLoader +import examples.goban.tiles.gobantile.gobancore.configs.{GobanCoreConfig => GobanCoreParam} + +object GobanCoreConfig { + + def apply(): GlobalConfig = { + val coreParam = GobanCoreParam() + val ballDomainParam = ConfigLoader.loadApply[BallDomainParam](coreParam.balldomain) + GlobalConfig().copy(ballDomain = ballDomainParam) + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/BallDomainConfig.scala b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/BallDomainConfig.scala new file mode 100644 index 00000000..5fa9e4e2 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/BallDomainConfig.scala @@ -0,0 +1,15 @@ +package examples.goban.tiles.gobantile.gobancore.balldomain.configs + +import upickle.default._ +import framework.balldomain.configs.{BallDomainParam, BallIdMapping} + +object BallDomainConfig { + private val path = + "src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/default.json" + + def apply(): BallDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + read[BallDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/default.json b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/default.json new file mode 100644 index 00000000..f72f4306 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/balldomain/configs/default.json @@ -0,0 +1,9 @@ +{ + "ballNum": 1, + "ballIdMappings": [ + {"ballId": 0, "ballName": "SystolicArrayBall", "ballClass": "framework.balldomain.prototype.systolicarray.SystolicArrayBall", "inBW": 2, "outBW": 4} + ], + "ballISA": [ + {"mnemonic": "SYSTOLIC", "funct7": 65, "bid": 0} + ] +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/GobanCoreParam.scala b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/GobanCoreParam.scala new file mode 100644 index 00000000..0e9a7220 --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/GobanCoreParam.scala @@ -0,0 +1,16 @@ +package examples.goban.tiles.gobantile.gobancore.configs + +import upickle.default._ + +case class GobanCoreConfig(balldomain: String) + +object GobanCoreConfig { + implicit val rw: ReadWriter[GobanCoreConfig] = macroRW + + def apply(): GobanCoreConfig = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/default.json").mkString + read[GobanCoreConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/default.json b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/default.json new file mode 100644 index 00000000..bd36483c --- /dev/null +++ b/arch/src/main/scala/examples/goban/tiles/gobantile/gobancore/configs/default.json @@ -0,0 +1,3 @@ +{ + "balldomain": "examples.goban.tiles.gobantile.gobancore.balldomain.configs.BallDomainConfig" +} diff --git a/arch/src/main/scala/examples/konbi/CustomConfigs.scala b/arch/src/main/scala/examples/konbi/CustomConfigs.scala new file mode 100644 index 00000000..116fa1a7 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/CustomConfigs.scala @@ -0,0 +1,11 @@ +package examples.konbi + +import org.chipsalliance.cde.config.Config +import examples.konbi.tiles.WithNKonbiTiles + +class BuckyballKonbiConfig + extends Config( + new WithNKonbiTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) diff --git a/arch/src/main/scala/examples/konbi/configs/KonbiTopParam.scala b/arch/src/main/scala/examples/konbi/configs/KonbiTopParam.scala new file mode 100644 index 00000000..221fd393 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/configs/KonbiTopParam.scala @@ -0,0 +1,15 @@ +package examples.konbi.configs + +import upickle.default._ + +case class KonbiConfig(nTiles: Int) + +object KonbiConfig { + implicit val rw: ReadWriter[KonbiConfig] = macroRW + + def apply(): KonbiConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/konbi/configs/default.json").mkString + read[KonbiConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/configs/default.json b/arch/src/main/scala/examples/konbi/configs/default.json new file mode 100644 index 00000000..caa6eb33 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/configs/default.json @@ -0,0 +1,3 @@ +{ + "nTiles": 1 +} diff --git a/arch/src/main/scala/examples/konbi/tiles/KonbiTilesConfig.scala b/arch/src/main/scala/examples/konbi/tiles/KonbiTilesConfig.scala new file mode 100644 index 00000000..391842be --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/KonbiTilesConfig.scala @@ -0,0 +1,44 @@ +package examples.konbi.tiles + +import org.chipsalliance.cde.config.{Config, Parameters} +import framework.core.bbtile.WithBBTile +import framework.top.GlobalConfig +import examples.konbi.configs.KonbiConfig +import framework.builtin.configloader.ConfigLoader +import examples.konbi.tiles.configs.TilesConfig + +/** + * Top-level Chipyard config fragment for the konbi example. + * + * Same JSON-driven assembly pattern as toy / goban. Konbi distinguishes + * itself by carrying *heterogeneous* Buckyball cores within a tile (e.g. + * prefill cores + decode cores); this is expressed by listing different + * Core config objects in `tile-N/configs/default.json`. + */ +class WithNKonbiTiles(withBuckyball: Boolean = true) extends Config(WithNKonbiTiles.assemble(withBuckyball)) + +object WithNKonbiTiles { + + def assemble(withBuckyball: Boolean): Parameters = { + val nTiles = KonbiConfig().nTiles + val tileConfigs = TilesConfig().tileConfigs + require( + tileConfigs.size == nTiles, + s"konbi tiles/configs/default.json lists ${tileConfigs.size} tile configs " + + s"but konbi/configs/default.json declares nTiles=$nTiles" + ) + + val fragments: Seq[Config] = tileConfigs.map { name => + val perCore = ConfigLoader.loadApply[Seq[Option[GlobalConfig]]](name) + val resolved = if (withBuckyball) perCore else perCore.map(_ => None) + new WithBBTile( + withBuckyball = resolved.exists(_.isDefined), + nCoresPerTile = perCore.size, + buckyballPerCore = Some(resolved) + ) + } + + fragments.reduce[Parameters](_ ++ _) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/configs/TilesConfig.scala b/arch/src/main/scala/examples/konbi/tiles/configs/TilesConfig.scala new file mode 100644 index 00000000..8aa88c46 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/configs/TilesConfig.scala @@ -0,0 +1,15 @@ +package examples.konbi.tiles.configs + +import upickle.default._ + +case class TilesConfig(tileConfigs: Seq[String]) + +object TilesConfig { + implicit val rw: ReadWriter[TilesConfig] = macroRW + + def apply(): TilesConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/konbi/tiles/configs/default.json").mkString + read[TilesConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/configs/default.json new file mode 100644 index 00000000..5c749c30 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/configs/default.json @@ -0,0 +1,5 @@ +{ + "tileConfigs": [ + "examples.konbi.tiles.konbitile.KonbiTileConfig" + ] +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/KonbiTileConfig.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/KonbiTileConfig.scala new file mode 100644 index 00000000..b14d708e --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/KonbiTileConfig.scala @@ -0,0 +1,18 @@ +package examples.konbi.tiles.konbitile + +import framework.top.GlobalConfig +import framework.builtin.configloader.ConfigLoader +import examples.konbi.tiles.konbitile.configs.{KonbiTileConfig => KonbiTileParam} + +object KonbiTileConfig { + + def apply(): Seq[Option[GlobalConfig]] = { + val tileParam = KonbiTileParam() + val nCores = tileParam.coreConfigs.size + tileParam.coreConfigs.map { name => + val cfg = ConfigLoader.loadApply[GlobalConfig](name) + Some(cfg.copy(top = cfg.top.copy(nCores = nCores))) + } + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/configs/KonbiTileParam.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/configs/KonbiTileParam.scala new file mode 100644 index 00000000..d5e0ce61 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/configs/KonbiTileParam.scala @@ -0,0 +1,16 @@ +package examples.konbi.tiles.konbitile.configs + +import upickle.default._ + +case class KonbiTileConfig(coreConfigs: Seq[String]) + +object KonbiTileConfig { + implicit val rw: ReadWriter[KonbiTileConfig] = macroRW + + def apply(): KonbiTileConfig = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/examples/konbi/tiles/konbitile/configs/default.json").mkString + read[KonbiTileConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/konbitile/configs/default.json new file mode 100644 index 00000000..dc638ccf --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/configs/default.json @@ -0,0 +1,9 @@ +{ + "coreConfigs": [ + "examples.konbi.tiles.konbitile.prefillcore.Core0Config", + "examples.konbi.tiles.konbitile.prefillcore.Core0Config", + "examples.konbi.tiles.konbitile.decodecore.Core1Config", + "examples.konbi.tiles.konbitile.decodecore.Core1Config", + "examples.konbi.tiles.konbitile.decodecore.Core1Config" + ] +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/Core1Config.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/Core1Config.scala new file mode 100644 index 00000000..a6d904d9 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/Core1Config.scala @@ -0,0 +1,17 @@ +package examples.konbi.tiles.konbitile.decodecore + +import framework.top.GlobalConfig +import framework.balldomain.configs.BallDomainParam +import framework.builtin.configloader.ConfigLoader +import examples.konbi.tiles.konbitile.decodecore.configs.KonbiCoreConfig + +/** Decode core variant. */ +object Core1Config { + + def apply(): GlobalConfig = { + val coreParam = KonbiCoreConfig() + val ballDomainParam = ConfigLoader.loadApply[BallDomainParam](coreParam.balldomain) + GlobalConfig().copy(ballDomain = ballDomainParam) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/BallDomainConfig.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/BallDomainConfig.scala new file mode 100644 index 00000000..a7e87b61 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/BallDomainConfig.scala @@ -0,0 +1,15 @@ +package examples.konbi.tiles.konbitile.decodecore.balldomain.configs + +import upickle.default._ +import framework.balldomain.configs.{BallDomainParam, BallIdMapping} + +object BallDomainConfig { + private val path = + "src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json" + + def apply(): BallDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + read[BallDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json new file mode 100644 index 00000000..a9620a36 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json @@ -0,0 +1,30 @@ +{ + "ballNum": 9, + "ballIdMappings": [ + {"ballId": 0, "ballName": "VecBall", "ballClass": "framework.balldomain.prototype.vector.VecBall", "inBW": 2, "outBW": 4}, + {"ballId": 1, "ballName": "ReluBall", "ballClass": "framework.balldomain.prototype.relu.ReluBall", "inBW": 1, "outBW": 1}, + {"ballId": 2, "ballName": "TransposeBall", "ballClass": "framework.balldomain.prototype.transpose.TransposeBall", "inBW": 1, "outBW": 1}, + {"ballId": 3, "ballName": "Im2colBall", "ballClass": "framework.balldomain.prototype.im2col.Im2colBall", "inBW": 1, "outBW": 1}, + {"ballId": 4, "ballName": "SystolicArrayBall", "ballClass": "framework.balldomain.prototype.systolicarray.SystolicArrayBall","inBW": 2, "outBW": 4}, + {"ballId": 5, "ballName": "QuantBall", "ballClass": "framework.balldomain.prototype.quant.QuantBall", "inBW": 1, "outBW": 1}, + {"ballId": 6, "ballName": "DequantBall", "ballClass": "framework.balldomain.prototype.dequant.DequantBall", "inBW": 1, "outBW": 1}, + {"ballId": 7, "ballName": "GemminiBall", "ballClass": "framework.balldomain.prototype.gemmini.GemminiBall", "inBW": 2, "outBW": 4}, + {"ballId": 8, "ballName": "TraceBall", "ballClass": "framework.balldomain.prototype.trace.TraceBall", "inBW": 1, "outBW": 1} + ], + "ballISA": [ + {"mnemonic": "MATMUL_WARP16", "funct7": 64, "bid": 0}, + {"mnemonic": "RELU", "funct7": 50, "bid": 1}, + {"mnemonic": "TRANSPOSE", "funct7": 49, "bid": 2}, + {"mnemonic": "IM2COL", "funct7": 48, "bid": 3}, + {"mnemonic": "SYSTOLIC", "funct7": 65, "bid": 4}, + {"mnemonic": "QUANT", "funct7": 51, "bid": 5}, + {"mnemonic": "DEQUANT", "funct7": 52, "bid": 6}, + {"mnemonic": "GEMMINI_CONFIG", "funct7": 2, "bid": 7}, + {"mnemonic": "GEMMINI_FLUSH", "funct7": 3, "bid": 7}, + {"mnemonic": "GEMMINI_PRELOAD", "funct7": 53, "bid": 7}, + {"mnemonic": "GEMMINI_COMPUTE_PRELOADED", "funct7": 66, "bid": 7}, + {"mnemonic": "GEMMINI_COMPUTE_ACCUMULATED", "funct7": 67, "bid": 7}, + {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8}, + {"mnemonic": "BDB_BACKDOOR", "funct7": 54, "bid": 8} + ] +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/KonbiCoreParam.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/KonbiCoreParam.scala new file mode 100644 index 00000000..9037705f --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/KonbiCoreParam.scala @@ -0,0 +1,17 @@ +package examples.konbi.tiles.konbitile.decodecore.configs + +import upickle.default._ + +/** Per-core parameters for the decode core variant. */ +case class KonbiCoreConfig(balldomain: String) + +object KonbiCoreConfig { + implicit val rw: ReadWriter[KonbiCoreConfig] = macroRW + + def apply(): KonbiCoreConfig = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/default.json").mkString + read[KonbiCoreConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/default.json new file mode 100644 index 00000000..cd5fe36c --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/configs/default.json @@ -0,0 +1,3 @@ +{ + "balldomain": "examples.konbi.tiles.konbitile.decodecore.balldomain.configs.BallDomainConfig" +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/Core0Config.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/Core0Config.scala new file mode 100644 index 00000000..85aa4334 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/Core0Config.scala @@ -0,0 +1,17 @@ +package examples.konbi.tiles.konbitile.prefillcore + +import framework.top.GlobalConfig +import framework.balldomain.configs.BallDomainParam +import framework.builtin.configloader.ConfigLoader +import examples.konbi.tiles.konbitile.prefillcore.configs.KonbiCoreConfig + +/** Prefill core variant. */ +object Core0Config { + + def apply(): GlobalConfig = { + val coreParam = KonbiCoreConfig() + val ballDomainParam = ConfigLoader.loadApply[BallDomainParam](coreParam.balldomain) + GlobalConfig().copy(ballDomain = ballDomainParam) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/BallDomainConfig.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/BallDomainConfig.scala new file mode 100644 index 00000000..5f7e5118 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/BallDomainConfig.scala @@ -0,0 +1,15 @@ +package examples.konbi.tiles.konbitile.prefillcore.balldomain.configs + +import upickle.default._ +import framework.balldomain.configs.{BallDomainParam, BallIdMapping} + +object BallDomainConfig { + private val path = + "src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/default.json" + + def apply(): BallDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + read[BallDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/default.json new file mode 100644 index 00000000..a9620a36 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/balldomain/configs/default.json @@ -0,0 +1,30 @@ +{ + "ballNum": 9, + "ballIdMappings": [ + {"ballId": 0, "ballName": "VecBall", "ballClass": "framework.balldomain.prototype.vector.VecBall", "inBW": 2, "outBW": 4}, + {"ballId": 1, "ballName": "ReluBall", "ballClass": "framework.balldomain.prototype.relu.ReluBall", "inBW": 1, "outBW": 1}, + {"ballId": 2, "ballName": "TransposeBall", "ballClass": "framework.balldomain.prototype.transpose.TransposeBall", "inBW": 1, "outBW": 1}, + {"ballId": 3, "ballName": "Im2colBall", "ballClass": "framework.balldomain.prototype.im2col.Im2colBall", "inBW": 1, "outBW": 1}, + {"ballId": 4, "ballName": "SystolicArrayBall", "ballClass": "framework.balldomain.prototype.systolicarray.SystolicArrayBall","inBW": 2, "outBW": 4}, + {"ballId": 5, "ballName": "QuantBall", "ballClass": "framework.balldomain.prototype.quant.QuantBall", "inBW": 1, "outBW": 1}, + {"ballId": 6, "ballName": "DequantBall", "ballClass": "framework.balldomain.prototype.dequant.DequantBall", "inBW": 1, "outBW": 1}, + {"ballId": 7, "ballName": "GemminiBall", "ballClass": "framework.balldomain.prototype.gemmini.GemminiBall", "inBW": 2, "outBW": 4}, + {"ballId": 8, "ballName": "TraceBall", "ballClass": "framework.balldomain.prototype.trace.TraceBall", "inBW": 1, "outBW": 1} + ], + "ballISA": [ + {"mnemonic": "MATMUL_WARP16", "funct7": 64, "bid": 0}, + {"mnemonic": "RELU", "funct7": 50, "bid": 1}, + {"mnemonic": "TRANSPOSE", "funct7": 49, "bid": 2}, + {"mnemonic": "IM2COL", "funct7": 48, "bid": 3}, + {"mnemonic": "SYSTOLIC", "funct7": 65, "bid": 4}, + {"mnemonic": "QUANT", "funct7": 51, "bid": 5}, + {"mnemonic": "DEQUANT", "funct7": 52, "bid": 6}, + {"mnemonic": "GEMMINI_CONFIG", "funct7": 2, "bid": 7}, + {"mnemonic": "GEMMINI_FLUSH", "funct7": 3, "bid": 7}, + {"mnemonic": "GEMMINI_PRELOAD", "funct7": 53, "bid": 7}, + {"mnemonic": "GEMMINI_COMPUTE_PRELOADED", "funct7": 66, "bid": 7}, + {"mnemonic": "GEMMINI_COMPUTE_ACCUMULATED", "funct7": 67, "bid": 7}, + {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8}, + {"mnemonic": "BDB_BACKDOOR", "funct7": 54, "bid": 8} + ] +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/KonbiCoreParam.scala b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/KonbiCoreParam.scala new file mode 100644 index 00000000..217cc1af --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/KonbiCoreParam.scala @@ -0,0 +1,19 @@ +package examples.konbi.tiles.konbitile.prefillcore.configs + +import upickle.default._ + +/** Per-core parameters for the prefill core variant. */ +case class KonbiCoreConfig(balldomain: String) + +object KonbiCoreConfig { + implicit val rw: ReadWriter[KonbiCoreConfig] = macroRW + + def apply(): KonbiCoreConfig = { + val jsonStr = + scala.io.Source.fromFile( + "src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/default.json" + ).mkString + read[KonbiCoreConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/default.json new file mode 100644 index 00000000..e4df9480 --- /dev/null +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/prefillcore/configs/default.json @@ -0,0 +1,3 @@ +{ + "balldomain": "examples.konbi.tiles.konbitile.prefillcore.balldomain.configs.BallDomainConfig" +} diff --git a/arch/src/main/scala/examples/poly/CustomConfigs.scala b/arch/src/main/scala/examples/poly/CustomConfigs.scala new file mode 100644 index 00000000..763b452d --- /dev/null +++ b/arch/src/main/scala/examples/poly/CustomConfigs.scala @@ -0,0 +1,17 @@ +package examples.poly + +import org.chipsalliance.cde.config.Config +import examples.poly.tiles.WithNPolyTiles + +/** + * Heterogeneous tile mix: + * - one CPU-only tile (cputile) + * - one toy-style Buckyball tile (lightdnntile) + * - one konbi-style Buckyball tile (llmtile, prefill+decode cores) + */ +class BuckyballPolyConfig + extends Config( + new WithNPolyTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) diff --git a/arch/src/main/scala/examples/poly/configs/PolyTopParam.scala b/arch/src/main/scala/examples/poly/configs/PolyTopParam.scala new file mode 100644 index 00000000..ca2f9be0 --- /dev/null +++ b/arch/src/main/scala/examples/poly/configs/PolyTopParam.scala @@ -0,0 +1,15 @@ +package examples.poly.configs + +import upickle.default._ + +case class PolyConfig(nTiles: Int) + +object PolyConfig { + implicit val rw: ReadWriter[PolyConfig] = macroRW + + def apply(): PolyConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/poly/configs/default.json").mkString + read[PolyConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/poly/configs/default.json b/arch/src/main/scala/examples/poly/configs/default.json new file mode 100644 index 00000000..7c0cf3a0 --- /dev/null +++ b/arch/src/main/scala/examples/poly/configs/default.json @@ -0,0 +1,3 @@ +{ + "nTiles": 3 +} diff --git a/arch/src/main/scala/examples/poly/tiles/PolyTilesConfig.scala b/arch/src/main/scala/examples/poly/tiles/PolyTilesConfig.scala new file mode 100644 index 00000000..4fba5a34 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/PolyTilesConfig.scala @@ -0,0 +1,45 @@ +package examples.poly.tiles + +import org.chipsalliance.cde.config.{Config, Parameters} +import framework.core.bbtile.WithBBTile +import framework.top.GlobalConfig +import examples.poly.configs.PolyConfig +import framework.builtin.configloader.ConfigLoader +import examples.poly.tiles.configs.TilesConfig + +/** + * Top-level Chipyard config fragment for the poly example. + * + * Same JSON-driven assembly pattern as toy / goban / konbi, but each + * `tileConfig` entry can describe a different *kind* of tile — pure CPU, + * a light DNN buckyball, an LLM buckyball, etc. Per-tile `withBuckyball` + * is inferred from the `Option`s the tile assembler returns: a tile whose + * cores are all `None` produces a Rocket-only BBTile, otherwise the + * accelerator slots are wired up. + */ +class WithNPolyTiles extends Config(WithNPolyTiles.assemble) + +object WithNPolyTiles { + + def assemble: Parameters = { + val nTiles = PolyConfig().nTiles + val tileConfigs = TilesConfig().tileConfigs + require( + tileConfigs.size == nTiles, + s"poly tiles/configs/default.json lists ${tileConfigs.size} tile configs " + + s"but poly/configs/default.json declares nTiles=$nTiles" + ) + + val fragments: Seq[Config] = tileConfigs.map { name => + val perCore = ConfigLoader.loadApply[Seq[Option[GlobalConfig]]](name) + new WithBBTile( + withBuckyball = perCore.exists(_.isDefined), + nCoresPerTile = perCore.size, + buckyballPerCore = Some(perCore) + ) + } + + fragments.reduce[Parameters](_ ++ _) + } + +} diff --git a/arch/src/main/scala/examples/poly/tiles/configs/TilesConfig.scala b/arch/src/main/scala/examples/poly/tiles/configs/TilesConfig.scala new file mode 100644 index 00000000..dbf1c803 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/configs/TilesConfig.scala @@ -0,0 +1,15 @@ +package examples.poly.tiles.configs + +import upickle.default._ + +case class TilesConfig(tileConfigs: Seq[String]) + +object TilesConfig { + implicit val rw: ReadWriter[TilesConfig] = macroRW + + def apply(): TilesConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/poly/tiles/configs/default.json").mkString + read[TilesConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/poly/tiles/configs/default.json b/arch/src/main/scala/examples/poly/tiles/configs/default.json new file mode 100644 index 00000000..af93ef60 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/configs/default.json @@ -0,0 +1,7 @@ +{ + "tileConfigs": [ + "examples.poly.tiles.cputile.CpuTileConfig", + "examples.poly.tiles.lightdnntile.LightDnnTileConfig", + "examples.poly.tiles.llmtile.LlmTileConfig" + ] +} diff --git a/arch/src/main/scala/examples/poly/tiles/cputile/CpuTileConfig.scala b/arch/src/main/scala/examples/poly/tiles/cputile/CpuTileConfig.scala new file mode 100644 index 00000000..4da0a3ed --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/cputile/CpuTileConfig.scala @@ -0,0 +1,23 @@ +package examples.poly.tiles.cputile + +import framework.top.GlobalConfig +import framework.builtin.configloader.ConfigLoader +import examples.poly.tiles.cputile.configs.{CpuTileConfig => CpuTileParam} + +/** + * Pure CPU tile entry — no Buckyball accelerator on any core. + * + * Each entry in `coreConfigs` resolves reflectively to a `CpuCoreConfig`, + * whose `apply()` returns `None` so the framework's BBTile drops the + * accelerator slot and ties off RoCC. + */ +object CpuTileConfig { + + def apply(): Seq[Option[GlobalConfig]] = { + val tileParam = CpuTileParam() + tileParam.coreConfigs.map { name => + ConfigLoader.loadApply[Option[GlobalConfig]](name) + } + } + +} diff --git a/arch/src/main/scala/examples/poly/tiles/cputile/configs/CpuTileParam.scala b/arch/src/main/scala/examples/poly/tiles/cputile/configs/CpuTileParam.scala new file mode 100644 index 00000000..eb873ff9 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/cputile/configs/CpuTileParam.scala @@ -0,0 +1,15 @@ +package examples.poly.tiles.cputile.configs + +import upickle.default._ + +case class CpuTileConfig(coreConfigs: Seq[String]) + +object CpuTileConfig { + implicit val rw: ReadWriter[CpuTileConfig] = macroRW + + def apply(): CpuTileConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/poly/tiles/cputile/configs/default.json").mkString + read[CpuTileConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/poly/tiles/cputile/configs/default.json b/arch/src/main/scala/examples/poly/tiles/cputile/configs/default.json new file mode 100644 index 00000000..dd593832 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/cputile/configs/default.json @@ -0,0 +1,5 @@ +{ + "coreConfigs": [ + "examples.poly.tiles.cputile.core.CpuCoreConfig" + ] +} diff --git a/arch/src/main/scala/examples/poly/tiles/cputile/core/CpuCoreConfig.scala b/arch/src/main/scala/examples/poly/tiles/cputile/core/CpuCoreConfig.scala new file mode 100644 index 00000000..b67085f7 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/cputile/core/CpuCoreConfig.scala @@ -0,0 +1,17 @@ +package examples.poly.tiles.cputile.core + +import framework.top.GlobalConfig + +/** + * CPU-only core entry. Returns `None` so the framework's BBTile produces + * a Rocket-only slot for this core (no Buckyball accelerator). + * + * Reading `core/configs/default.json` is intentionally skipped — the CPU + * variant carries no Buckyball-side parameters, but the parameter + * case class still exists for symmetry with other examples. + */ +object CpuCoreConfig { + + def apply(): Option[GlobalConfig] = None + +} diff --git a/arch/src/main/scala/examples/poly/tiles/cputile/core/configs/CpuCoreParam.scala b/arch/src/main/scala/examples/poly/tiles/cputile/core/configs/CpuCoreParam.scala new file mode 100644 index 00000000..9ee7ff78 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/cputile/core/configs/CpuCoreParam.scala @@ -0,0 +1,17 @@ +package examples.poly.tiles.cputile.core.configs + +import upickle.default._ + +/** No fields needed: a CPU-only core has no Buckyball-side parameters. */ +case class CpuCoreConfig() + +object CpuCoreConfig { + implicit val rw: ReadWriter[CpuCoreConfig] = macroRW + + def apply(): CpuCoreConfig = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/examples/poly/tiles/cputile/core/configs/default.json").mkString + read[CpuCoreConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/poly/tiles/cputile/core/configs/default.json b/arch/src/main/scala/examples/poly/tiles/cputile/core/configs/default.json new file mode 100644 index 00000000..2c63c085 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/cputile/core/configs/default.json @@ -0,0 +1,2 @@ +{ +} diff --git a/arch/src/main/scala/examples/poly/tiles/lightdnntile/LightDnnTileConfig.scala b/arch/src/main/scala/examples/poly/tiles/lightdnntile/LightDnnTileConfig.scala new file mode 100644 index 00000000..3c435d91 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/lightdnntile/LightDnnTileConfig.scala @@ -0,0 +1,16 @@ +package examples.poly.tiles.lightdnntile + +import framework.top.GlobalConfig + +/** + * Light DNN tile — directly delegates to toy's `ToyTileConfig`, reusing + * its layered JSON layout and Buckyball wiring. Poly's `lightdnntile` + * directory therefore holds no separate balldomain or core descriptors; + * everything comes from `examples.toy.tiles.toytile`. + */ +object LightDnnTileConfig { + + def apply(): Seq[Option[GlobalConfig]] = + examples.toy.tiles.toytile.ToyTileConfig() + +} diff --git a/arch/src/main/scala/examples/poly/tiles/llmtile/LlmTileConfig.scala b/arch/src/main/scala/examples/poly/tiles/llmtile/LlmTileConfig.scala new file mode 100644 index 00000000..78b4acb4 --- /dev/null +++ b/arch/src/main/scala/examples/poly/tiles/llmtile/LlmTileConfig.scala @@ -0,0 +1,16 @@ +package examples.poly.tiles.llmtile + +import framework.top.GlobalConfig + +/** + * LLM tile — directly delegates to konbi's `KonbiTileConfig`, reusing + * its heterogeneous prefill+decode core layout. Poly's `llmtile` + * directory therefore holds no separate descriptors; everything comes + * from `examples.konbi.tiles.konbitile`. + */ +object LlmTileConfig { + + def apply(): Seq[Option[GlobalConfig]] = + examples.konbi.tiles.konbitile.KonbiTileConfig() + +} diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index 13bcd042..b188a124 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -1,7 +1,7 @@ package examples.toy import org.chipsalliance.cde.config.Config -import framework.core.bbtile.WithNBBTiles +import examples.toy.tiles.WithNToyTiles import freechips.rocketchip.subsystem.{InCluster, InSubsystem} import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} @@ -15,7 +15,7 @@ import scala.collection.immutable.ListMap /** Single BBTile: 1 Rocket core + 1 Buckyball accelerator */ class BuckyballToyConfig extends Config( - new WithNBBTiles(1) ++ + new WithNToyTiles ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) @@ -23,7 +23,7 @@ class BuckyballToyConfig /** Single Rocket core only (no Buckyball) */ class RocketOnlyConfig extends Config( - new WithNBBTiles(1, withBuckyball = false) ++ + new WithNToyTiles(withBuckyball = false) ++ new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) diff --git a/arch/src/main/scala/examples/toy/balldomain/DISA.scala b/arch/src/main/scala/examples/toy/balldomain/DISA.scala deleted file mode 100644 index 71922b88..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/DISA.scala +++ /dev/null @@ -1,51 +0,0 @@ -package examples.toy.balldomain - -import chisel3._ -import chisel3.util._ - -// funct7 encoding: [6:4] = enable, [3:0] = opcode -// enable: 000=no_bank, 001=1rd, 010=1wr, 011=1rd+1wr, 100=2rd+1wr -// 101/110/111 = no_bank (extended space) -object DISA { - // enable=100 (2 read + 1 write): opcode 0-3 - val MATMUL_WARP16 = BitPat("b1000000") // 64 (0x40) - val SYSTOLIC = BitPat("b1000001") // 65 (0x41) - val GEMMINI_COMPUTE_PRELOADED = BitPat("b1000010") // 66 (0x42) - val GEMMINI_COMPUTE_ACCUMULATED = BitPat("b1000011") // 67 (0x43) - - // enable=011 (1 read + 1 write): opcode 0-6 - val IM2COL = BitPat("b0110000") // 48 (0x30) - val TRANSPOSE = BitPat("b0110001") // 49 (0x31) - val RELU = BitPat("b0110010") // 50 (0x32) - val QUANT = BitPat("b0110011") // 51 (0x33) - val DEQUANT = BitPat("b0110100") // 52 (0x34) - val GEMMINI_PRELOAD = BitPat("b0110101") // 53 (0x35) - val BDB_BACKDOOR = BitPat("b0110110") // 54 (0x36) - - // enable=000 (no bank access): opcode 2-4 - val GEMMINI_CONFIG = BitPat("b0000010") // 2 (0x02) - val GEMMINI_FLUSH = BitPat("b0000011") // 3 (0x03) - val BDB_COUNTER = BitPat("b0000100") // 4 (0x04) - - // enable=101 (no bank, extended): Loop WS config, opcode 0-7 - val GEMMINI_LOOP_WS_CONFIG_BOUNDS = BitPat("b1010000") // 80 (0x50) - val GEMMINI_LOOP_WS_CONFIG_ADDR_A = BitPat("b1010001") // 81 (0x51) - val GEMMINI_LOOP_WS_CONFIG_ADDR_B = BitPat("b1010010") // 82 (0x52) - val GEMMINI_LOOP_WS_CONFIG_ADDR_D = BitPat("b1010011") // 83 (0x53) - val GEMMINI_LOOP_WS_CONFIG_ADDR_C = BitPat("b1010100") // 84 (0x54) - val GEMMINI_LOOP_WS_CONFIG_STRIDES_AB = BitPat("b1010101") // 85 (0x55) - val GEMMINI_LOOP_WS_CONFIG_STRIDES_DC = BitPat("b1010110") // 86 (0x56) - val GEMMINI_LOOP_WS = BitPat("b1010111") // 87 (0x57) - - // enable=110 (no bank, extended): Loop Conv WS config, opcode 0-9 - val GEMMINI_LOOP_CONV_WS_CONFIG_1 = BitPat("b1100000") // 96 (0x60) - val GEMMINI_LOOP_CONV_WS_CONFIG_2 = BitPat("b1100001") // 97 (0x61) - val GEMMINI_LOOP_CONV_WS_CONFIG_3 = BitPat("b1100010") // 98 (0x62) - val GEMMINI_LOOP_CONV_WS_CONFIG_4 = BitPat("b1100011") // 99 (0x63) - val GEMMINI_LOOP_CONV_WS_CONFIG_5 = BitPat("b1100100") // 100 (0x64) - val GEMMINI_LOOP_CONV_WS_CONFIG_6 = BitPat("b1100101") // 101 (0x65) - val GEMMINI_LOOP_CONV_WS_CONFIG_7 = BitPat("b1100110") // 102 (0x66) - val GEMMINI_LOOP_CONV_WS_CONFIG_8 = BitPat("b1100111") // 103 (0x67) - val GEMMINI_LOOP_CONV_WS_CONFIG_9 = BitPat("b1101000") // 104 (0x68) - val GEMMINI_LOOP_CONV_WS = BitPat("b1101001") // 105 (0x69) -} diff --git a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala b/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala deleted file mode 100644 index 5cf43e6b..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala +++ /dev/null @@ -1,226 +0,0 @@ -package examples.toy.balldomain - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.{instantiable, public} -import org.chipsalliance.cde.config.Parameters -import framework.frontend.decoder.{DomainId, PostGDCmd} -import examples.toy.balldomain.DISA._ -import framework.top.GlobalConfig - -// Detailed decode output for Ball domain -class BallDecodeCmd(numBanks: Int, iterLen: Int) extends Bundle { - val bid = UInt(5.W) - val funct7 = UInt(7.W) // raw funct7 for instruction routing - // Iteration count - val iter = UInt(iterLen.W) - - // Ball-specific fields - val op1_en = Bool() - val op2_en = Bool() - val wr_spad_en = Bool() - val op1_from_spad = Bool() - val op2_from_spad = Bool() - // Instruction-specific subfield (full rs2) - val special = UInt(64.W) - - // Ball operand bank IDs - val op1_bank = UInt(log2Up(numBanks).W) - val op2_bank = UInt(log2Up(numBanks).W) - val wr_bank = UInt(log2Up(numBanks).W) - - val rs1 = UInt(64.W) - val rs2 = UInt(64.W) -} - -// Ball decode fields -object BallDecodeFields extends Enumeration { - type Field = Value - val OP1_FROM_SPAD, OP2_FROM_SPAD, OP1_SPADDR, OP2_SPADDR, WR_SPADDR, BID, SPECIAL = - Value -} - -// Default constants for EX decoder -object BallDefaultConstants { - val Y = true.B - val N = false.B - val DADDR = 0.U(10.W) - val DBID = 0.U(5.W) - val DSPECIAL = 0.U(64.W) -} - -@instantiable -class BallDomainDecoder(val b: GlobalConfig) extends Module { - import BallDefaultConstants._ - - val bankIdLen = b.frontend.bank_id_len - val iterLen = b.frontend.iter_len - - @public - val cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) - @public - val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum, iterLen))) - - cmd_i.ready := ball_decode_cmd_o.ready - - val func7 = cmd_i.bits.cmd.funct - val rs1 = cmd_i.bits.cmd.rs1Data - val rs2 = cmd_i.bits.cmd.rs2Data - - // Unified rs1 layout: - // rs1[9:0] = BANK0 (op1 bank / 1st read) - // rs1[19:10] = BANK1 (op2 bank / 2nd read) - // rs1[29:20] = BANK2 (wr bank) - // rs1[63:30] = ITER (34-bit) - // - // Enable encoding in funct7[6:4]: - // 000 = no bank access - // 001 = 1 read (bank0) - // 010 = 1 write (bank2) - // 011 = 1 read + 1 write (bank0 read, bank2 write) - // 100 = 2 read + 1 write (bank0+bank1 read, bank2 write) - // 101,110,111 = no bank access (extended opcode space) - // rs2 = special (full 64-bit) - - val op1_bank_raw = rs1(bankIdLen - 1, 0) - val op2_bank_raw = rs1(bankIdLen + 9, 10) - val wr_bank_raw = rs1(bankIdLen + 19, 20) - val iter_raw = rs1(63, 30) - - // Enable decoding from funct7[6:4] - val enableBits = func7(6, 4) - val hasRd0 = enableBits === 1.U || enableBits === 3.U || enableBits === 4.U - val hasRd1 = enableBits === 4.U - val hasWr = enableBits === 2.U || enableBits === 3.U || enableBits === 4.U - - // Ball instruction decoding - import BallDecodeFields._ - val ball_default_decode = List(N, N, 0.U, 0.U, 0.U, DBID, DSPECIAL) - - val ball_decode_list = ListLookup( - func7, - ball_default_decode, - Array( - // enable=100 (2rd+1wr): bank0 read, bank1 read, bank2 write - // op1s op2s op1_bank op2_bank wr_bank bid special - MATMUL_WARP16 -> List(Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 0.U, rs2), - SYSTOLIC -> List(Y, Y, op1_bank_raw, op2_bank_raw, wr_bank_raw, 4.U, rs2), - GEMMINI_COMPUTE_PRELOADED -> List( - Y, - Y, - op1_bank_raw, - op2_bank_raw, - wr_bank_raw, - 7.U, - Cat(rs2(63, 4), 2.U(4.W)) - ), - GEMMINI_COMPUTE_ACCUMULATED -> List( - Y, - Y, - op1_bank_raw, - op2_bank_raw, - wr_bank_raw, - 7.U, - Cat(rs2(63, 4), 3.U(4.W)) - ), - // enable=011 (1rd+1wr): bank0 read, bank2 write - RELU -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 1.U, rs2), - TRANSPOSE -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 2.U, rs2), - IM2COL -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 3.U, rs2), - QUANT -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 5.U, rs2), - DEQUANT -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 6.U, rs2), - GEMMINI_PRELOAD -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 7.U, Cat(rs2(63, 4), 1.U(4.W))), - BDB_BACKDOOR -> List(Y, N, op1_bank_raw, DADDR, wr_bank_raw, 8.U, rs2), - // enable=000 (no bank): config/flush/counter - GEMMINI_CONFIG -> List(N, N, DADDR, DADDR, DADDR, 7.U, Cat(rs2(63, 4), 0.U(4.W))), - GEMMINI_FLUSH -> List(N, N, DADDR, DADDR, DADDR, 7.U, Cat(0.U(60.W), 4.U(4.W))), - BDB_COUNTER -> List(N, N, DADDR, DADDR, DADDR, 8.U, rs2), - // enable=101 (no bank, extended): Loop WS config/trigger - GEMMINI_LOOP_WS_CONFIG_BOUNDS -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS_CONFIG_ADDR_A -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS_CONFIG_ADDR_B -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS_CONFIG_ADDR_D -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS_CONFIG_ADDR_C -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS_CONFIG_STRIDES_AB -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS_CONFIG_STRIDES_DC -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_WS -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - // enable=110 (no bank, extended): Loop Conv WS config/trigger - GEMMINI_LOOP_CONV_WS_CONFIG_1 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_2 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_3 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_4 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_5 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_6 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_7 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_8 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS_CONFIG_9 -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2), - GEMMINI_LOOP_CONV_WS -> List(N, N, DADDR, DADDR, DADDR, 7.U, rs2) - ) - ) - -// ----------------------------------------------------------------------------- -// Output assignment -// ----------------------------------------------------------------------------- - ball_decode_cmd_o.valid := cmd_i.valid && (cmd_i.bits.domain_id === DomainId.BALL) - - ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, ball_decode_list(BallDecodeFields.BID.id).asUInt, DBID) - ball_decode_cmd_o.bits.funct7 := Mux(ball_decode_cmd_o.valid, func7, 0.U) - - // iter is always from rs1[63:30] - ball_decode_cmd_o.bits.iter := Mux( - ball_decode_cmd_o.valid, - iter_raw, - 0.U(iterLen.W) - ) - ball_decode_cmd_o.bits.special := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.SPECIAL.id).asUInt, - DSPECIAL - ) - - // Enable bits from funct7[6:4] - ball_decode_cmd_o.bits.op1_en := ball_decode_cmd_o.valid && hasRd0 - ball_decode_cmd_o.bits.op2_en := ball_decode_cmd_o.valid && hasRd1 - ball_decode_cmd_o.bits.wr_spad_en := ball_decode_cmd_o.valid && hasWr - - ball_decode_cmd_o.bits.op1_from_spad := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.OP1_FROM_SPAD.id).asBool, - false.B - ) - ball_decode_cmd_o.bits.op2_from_spad := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.OP2_FROM_SPAD.id).asBool, - false.B - ) - - // Directly assign bank IDs from decoded values - ball_decode_cmd_o.bits.op1_bank := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.OP1_SPADDR.id).asUInt, - 0.U - ) - ball_decode_cmd_o.bits.op2_bank := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.OP2_SPADDR.id).asUInt, - 0.U - ) - ball_decode_cmd_o.bits.wr_bank := Mux( - ball_decode_cmd_o.valid, - ball_decode_list(BallDecodeFields.WR_SPADDR.id).asUInt, - 0.U - ) - - // Assertion: OpA and OpB in execution instructions must access different banks - assert( - !(ball_decode_cmd_o.valid && ball_decode_cmd_o.bits.op1_en && ball_decode_cmd_o.bits.op2_en && - ball_decode_cmd_o.bits.op1_bank === ball_decode_cmd_o.bits.op2_bank), - "BallDomainDecoder: Ball instruction OpA and OpB cannot access the same bank" - ) - -// ----------------------------------------------------------------------------- -// Continue passing rs1 and rs2 -// ----------------------------------------------------------------------------- - ball_decode_cmd_o.bits.rs1 := rs1 - ball_decode_cmd_o.bits.rs2 := rs2 -} diff --git a/arch/src/main/scala/examples/toy/balldomain/README.md b/arch/src/main/scala/examples/toy/balldomain/README.md deleted file mode 100644 index b2583c30..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/README.md +++ /dev/null @@ -1,192 +0,0 @@ -# BallDomain Example Implementation - -## Overview - -This directory contains a complete example implementation of BallDomain in the Buckyball framework, demonstrating how to build a custom computation domain to manage specialized accelerators. BallDomain is a core concept in Buckyball architecture, used to encapsulate and manage a group of related computation units with unified control and dataflow management. - -This directory implements the ball domain architecture, including: -- **BallDomain**: Top-level module managing the entire computation domain -- **BallController**: Ball domain controller for instruction scheduling and execution control -- **DISA**: Distributed instruction scheduling architecture -- **DomainDecoder**: Domain instruction decoder -- **Specialized accelerators**: Including matrix, vector, im2col and other accelerator implementations - -## Code Structure - -``` -balldomain/ -├── BallDomain.scala - Ball domain top module -├── BallController.scala - Ball domain controller -├── DISA.scala - Distributed instruction scheduling architecture -├── DomainDecoder.scala - Domain instruction decoder -├── bbus/ - Ball domain bus system -├── im2col/ - Image-to-column conversion accelerator -├── matrixball/ - Matrix computation ball domain -├── rs/ - Reservation station implementation -└── vecball/ - Vector computation ball domain -``` - -### File Dependencies - -**BallDomain.scala** (Top-level module) -- Integrates all submodules, provides unified ball domain interface -- Manages dataflow and control flow within ball domain -- Connects to system bus and RoCC interface - -**BallController.scala** (Control layer) -- Implements instruction scheduling and execution control for ball domain -- Manages coordination between multiple accelerators -- Provides state management and error handling - -**DISA.scala** (Scheduling layer) -- Distributed instruction scheduling architecture implementation -- Supports concurrent execution of multiple instructions -- Provides dynamic load balancing - -**DomainDecoder.scala** (Decode layer) -- Ball domain specific instruction decode -- Instruction dispatch to corresponding execution units -- Supports complex instruction decomposition and reorganization - -## Module Description - -### BallDomain.scala - -**Main functionality**: Ball domain top module, integrates all computation units and control logic - -**Key components**: - -```scala -class BallDomain(implicit p: Parameters) extends LazyModule { - val controller = LazyModule(new BallController) - val matrixBall = LazyModule(new MatrixBall) - val vecBall = LazyModule(new VecBall) - val im2colUnit = LazyModule(new Im2colUnit) - - // Ball domain bus connections - val bbus = LazyModule(new BBus) - bbus.node := controller.node - matrixBall.node := bbus.node - vecBall.node := bbus.node -} -``` - -**Inputs/Outputs**: -- Input: RoCC instruction interface, memory access interface -- Output: Computation results, status information -- Edge cases: Instruction conflict handling, resource contention management - -### BallController.scala - -**Main functionality**: Ball domain controller, manages overall ball domain execution control - -**Key components**: - -```scala -class BallController extends Module { - val io = IO(new Bundle { - val rocc = Flipped(new RoCCCoreIO) - val mem = new HellaCacheIO - val domain_ctrl = new DomainControlIO - }) - - // Instruction queue and scheduling logic - val inst_queue = Module(new Queue(new RoCCInstruction, 16)) - val scheduler = Module(new InstructionScheduler) -} -``` - -**Scheduling strategy**: -- Static scheduling based on instruction type -- Dynamic resource allocation and load balancing -- Supports instruction pipelining and concurrent execution - -### DISA.scala - -**Main functionality**: Distributed instruction scheduling architecture - -**Key components**: - -```scala -class DISA extends Module { - val io = IO(new Bundle { - val inst_in = Flipped(Decoupled(new Instruction)) - val exec_units = Vec(numUnits, new ExecutionUnitIO) - val completion = Decoupled(new CompletionInfo) - }) - - // Distributed dispatch table - val dispatch_table = Reg(Vec(numUnits, new DispatchEntry)) - val load_balancer = Module(new LoadBalancer) -} -``` - -**Scheduling algorithms**: -- Round-robin scheduling for fairness -- Priority scheduling for critical tasks -- Dynamic scheduling adapts to load changes - -### DomainDecoder.scala - -**Main functionality**: Ball domain instruction decoder - -**Key components**: - -```scala -class DomainDecoder extends Module { - val io = IO(new Bundle { - val inst = Input(UInt(32.W)) - val decoded = Output(new DecodedInstruction) - val valid = Output(Bool()) - }) - - // Instruction decode table - val decode_table = Array( - MATRIX_OP -> MatrixOpDecoder, - VECTOR_OP -> VectorOpDecoder, - IM2COL_OP -> Im2colOpDecoder - ) -} -``` - -**Decode functionality**: -- Supports multiple instruction formats -- Microcode expansion for complex instructions -- Instruction dependency analysis and optimization - -## Usage - -### Design Features - -1. **Modular architecture**: Each accelerator is an independent module, easy to extend and maintain -2. **Unified interface**: All accelerators communicate through unified ball domain bus -3. **Flexible scheduling**: Supports multiple scheduling strategies, adapts to different computation patterns -4. **Scalability**: Easy to add new accelerator types and functionality - -### Performance Optimization - -1. **Pipeline design**: Instruction decode, scheduling, execution use pipeline architecture -2. **Concurrent execution**: Supports multiple accelerators working simultaneously -3. **Data management**: Data caching and access management -4. **Workload**: Workload distribution - -### Usage Example - -```scala -// Create ball domain instance -val ballDomain = LazyModule(new BallDomain) - -// Connect to RoCC interface -rocc.cmd <> ballDomain.module.io.rocc.cmd -rocc.resp <> ballDomain.module.io.rocc.resp - -// Configure ball domain parameters -ballDomain.module.io.config := ballDomainConfig -``` - -### Notes - -1. **Resource management**: Properly allocate computational resources, avoid resource conflicts -2. **Timing constraints**: Pay attention to timing relationships and data synchronization between different modules -3. **Power control**: Implement dynamic power management, shut down modules when not in use -4. **Debug support**: Debug interface and status monitoring functionality diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/README.md b/arch/src/main/scala/examples/toy/balldomain/bbus/README.md deleted file mode 100644 index 9aca5eb0..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/README.md +++ /dev/null @@ -1,138 +0,0 @@ -# BBus Ball Domain Bus System - -## Overview - -This directory contains the implementation of Buckyball's ball domain bus system, primarily responsible for managing SRAM resource access by multiple Ball nodes within the ball domain. The bus system is implemented based on BBusNode from framework.blink, providing SRAM resource arbitration and routing functionality. - -This directory implements two core components: -- **BallBus**: Ball domain bus main module, manages SRAM access by multiple Ball nodes -- **BBusRouter**: Bus router, provides routing functionality for blink interface - -## Code Structure - -``` -bbus/ -├── BallBus.scala - Ball domain bus main module -└── router.scala - Bus router implementation -``` - -### File Dependencies - -**BallBus.scala** (Main module) -- Creates multiple BBusNode instances to manage Ball nodes -- Connects external SRAM interfaces to each Ball node -- Implements SRAM resource allocation and arbitration - -**router.scala** (Routing module) -- Implements routing functionality based on BBusNode -- Provides blink protocol interface encapsulation - -## Module Description - -### BallBus.scala - -**Main functionality**: Ball domain bus main module, manages SRAM resource access by multiple Ball nodes - -**Key components**: - -```scala -class BallBus(maxReadBW: Int, maxWriteBW: Int, numBalls: Int) extends LazyModule { - // Create multiple BBusNode instances - val ballNodes = Seq.fill(numBalls) { - new BBusNode(BallParams(sramReadBW = maxReadBW, sramWriteBW = maxWriteBW)) - } - - // External SRAM interfaces - val io = IO(new Bundle { - val sramRead = Vec(b.sp_banks, Flipped(new SramReadIO(...))) - val sramWrite = Vec(b.sp_banks, Flipped(new SramWriteIO(...))) - val accRead = Vec(b.acc_banks, Flipped(new SramReadIO(...))) - val accWrite = Vec(b.acc_banks, Flipped(new SramWriteIO(...))) - }) -} -``` - -**Resource allocation strategy**: -- First `sp_banks` ports connected to scratchpad SRAM -- Next `acc_banks` ports connected to accumulator SRAM -- Excess ports set to invalid state -- All Ball nodes share the same SRAM resources - -**Inputs/Outputs**: -- Input: SRAM access requests from each Ball node -- Output: Read/write interfaces connected to external SRAM -- Edge cases: Handle ports beyond configuration range, set to DontCare - -**Dependencies**: framework.balldomain.blink.BBusNode, framework.builtin.memdomain.mem - -### router.scala - -**Main functionality**: Bus router, provides routing functionality for blink protocol interface - -**Key components**: - -```scala -class BBusRouter extends LazyModule { - val node = new BBusNode(BallParams( - sramReadBW = b.sp_banks, - sramWriteBW = b.sp_banks - )) - - val io = IO(new Bundle { - val blink = Flipped(new BlinkBundle(node.edges.in.head)) - }) -} -``` - -**Routing functionality**: -- Implements standard Ball node interface based on BBusNode -- Provides blink protocol encapsulation and conversion -- Supports configurable read/write bandwidth parameters - -**Inputs/Outputs**: -- Input: blink protocol interface -- Output: BBusNode standard interface -- Edge cases: Depends on validity of node.edges.in.head - -**Dependencies**: framework.balldomain.blink.BlinkBundle, framework.balldomain.blink.BBusNode - -## Usage - -### Configuration Parameters - -Bus system configuration is controlled by the following parameters: -- `maxReadBW`: Maximum read bandwidth (port count) -- `maxWriteBW`: Maximum write bandwidth (port count) -- `numBalls`: Ball node count -- `b.sp_banks`: Scratchpad bank count -- `b.acc_banks`: Accumulator bank count - -### Resource Management - -1. **SRAM port allocation**: Allocate ports in order of scratchpad first, accumulator second -2. **Multi-Ball sharing**: All Ball nodes share the same SRAM resource pool -3. **Port reuse**: Ports beyond configuration are set to invalid state to save resources - -### Usage Example - -```scala -// Create ball domain bus -val ballBus = LazyModule(new BallBus( - maxReadBW = 8, - maxWriteBW = 8, - numBalls = 4 -)) - -// Connect external SRAM -scratchpad.io.read <> ballBus.module.io.sramRead -scratchpad.io.write <> ballBus.module.io.sramWrite -accumulator.io.read <> ballBus.module.io.accRead -accumulator.io.write <> ballBus.module.io.accWrite -``` - -### Notes - -1. **Resource conflicts**: Multiple Ball nodes may access the same SRAM resources simultaneously, requiring upper-level coordination -2. **Bandwidth limitations**: Actual available bandwidth is limited by configured maximum read/write bandwidth parameters -3. **Port mapping**: Ensure SRAM port count matches configuration parameters to avoid out-of-bounds access -4. **Timing constraints**: BBusNode timing requirements need to match external SRAM interfaces diff --git a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala b/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala deleted file mode 100644 index 2c247e2e..00000000 --- a/arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala +++ /dev/null @@ -1,41 +0,0 @@ -package examples.toy.balldomain.bbus - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.hierarchy.instantiable -import framework.top.GlobalConfig -import framework.balldomain.bbus.BBus -import framework.balldomain.blink.HasBlink -import framework.balldomain.prototype.vector.VecBall -import framework.balldomain.prototype.relu.ReluBall -import framework.balldomain.prototype.transpose.TransposeBall -import framework.balldomain.prototype.im2col.Im2colBall -import framework.balldomain.prototype.systolicarray.SystolicArrayBall -import framework.balldomain.prototype.quant.QuantBall -import framework.balldomain.prototype.dequant.DequantBall -import framework.balldomain.prototype.gemmini.GemminiBall -import framework.balldomain.prototype.trace.TraceBall - -/** - * BBusModule - Ball bus module that directly extends BBus - */ -@instantiable -class BBusModule(b: GlobalConfig) - extends BBus( - b, - b.ballDomain.ballIdMappings.map { mapping => - val ballGenerator: () => HasBlink with Module = mapping.ballName match { - case "VecBall" => () => new VecBall(b) - case "ReluBall" => () => new ReluBall(b) - case "TransposeBall" => () => new TransposeBall(b) - case "Im2colBall" => () => new Im2colBall(b) - case "SystolicArrayBall" => () => new SystolicArrayBall(b) - case "QuantBall" => () => new QuantBall(b) - case "DequantBall" => () => new DequantBall(b) - case "GemminiBall" => () => new GemminiBall(b) - case "TraceBall" => () => new TraceBall(b) - case name => throw new IllegalArgumentException(s"Unknown ball name: $name") - } - ballGenerator - } - ) {} diff --git a/arch/src/main/scala/examples/toy/configs/ToyTopParam.scala b/arch/src/main/scala/examples/toy/configs/ToyTopParam.scala new file mode 100644 index 00000000..da378c90 --- /dev/null +++ b/arch/src/main/scala/examples/toy/configs/ToyTopParam.scala @@ -0,0 +1,15 @@ +package examples.toy.configs + +import upickle.default._ + +case class ToyConfig(nTiles: Int) + +object ToyConfig { + implicit val rw: ReadWriter[ToyConfig] = macroRW + + def apply(): ToyConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/toy/configs/default.json").mkString + read[ToyConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/toy/configs/default.json b/arch/src/main/scala/examples/toy/configs/default.json new file mode 100644 index 00000000..caa6eb33 --- /dev/null +++ b/arch/src/main/scala/examples/toy/configs/default.json @@ -0,0 +1,3 @@ +{ + "nTiles": 1 +} diff --git a/arch/src/main/scala/examples/toy/tiles/ToyTilesConfig.scala b/arch/src/main/scala/examples/toy/tiles/ToyTilesConfig.scala new file mode 100644 index 00000000..143506b2 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/ToyTilesConfig.scala @@ -0,0 +1,48 @@ +package examples.toy.tiles + +import org.chipsalliance.cde.config.{Config, Parameters} +import framework.core.bbtile.WithBBTile +import framework.top.GlobalConfig +import examples.toy.configs.ToyConfig +import framework.builtin.configloader.ConfigLoader +import examples.toy.tiles.configs.TilesConfig + +/** + * Top-level Chipyard config fragment for the toy example. + * + * Fully JSON-driven: the tile/core/balldomain layout is described by the + * `default.json` files under `examples/toy/...`. Each layer's JSON points + * at a sibling object whose `apply()` produces the next layer's data; + * this assembler reflectively walks that chain and emits one + * `WithBBTile` fragment per tile. + * + * `withBuckyball = false` (used by `RocketOnlyConfig`) keeps the JSON + * topology but tears down every Buckyball slot. + */ +class WithNToyTiles(withBuckyball: Boolean = true) extends Config(WithNToyTiles.assemble(withBuckyball)) + +object WithNToyTiles { + + def assemble(withBuckyball: Boolean): Parameters = { + val nTiles = ToyConfig().nTiles + val tileConfigs = TilesConfig().tileConfigs + require( + tileConfigs.size == nTiles, + s"tiles/configs/default.json lists ${tileConfigs.size} tile configs " + + s"but toy/configs/default.json declares nTiles=$nTiles" + ) + + val fragments: Seq[Config] = tileConfigs.map { name => + val perCore = ConfigLoader.loadApply[Seq[Option[GlobalConfig]]](name) + val resolved = if (withBuckyball) perCore else perCore.map(_ => None) + new WithBBTile( + withBuckyball = resolved.exists(_.isDefined), + nCoresPerTile = perCore.size, + buckyballPerCore = Some(resolved) + ) + } + + fragments.reduce[Parameters](_ ++ _) + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/configs/ToyTilesParam.scala b/arch/src/main/scala/examples/toy/tiles/configs/ToyTilesParam.scala new file mode 100644 index 00000000..6cb87d65 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/configs/ToyTilesParam.scala @@ -0,0 +1,16 @@ +package examples.toy.tiles.configs + +import upickle.default._ + +case class TilesConfig( + tileConfigs: Seq[String]) + +object TilesConfig { + implicit val rw: ReadWriter[TilesConfig] = macroRW + + def apply(): TilesConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/toy/tiles/configs/default.json").mkString + read[TilesConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/configs/default.json b/arch/src/main/scala/examples/toy/tiles/configs/default.json new file mode 100644 index 00000000..5467ed2f --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/configs/default.json @@ -0,0 +1,5 @@ +{ + "tileConfigs": [ + "examples.toy.tiles.toytile.ToyTileConfig" + ] +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/ToyTileConfig.scala b/arch/src/main/scala/examples/toy/tiles/toytile/ToyTileConfig.scala new file mode 100644 index 00000000..59b3a6c6 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/ToyTileConfig.scala @@ -0,0 +1,30 @@ +package examples.toy.tiles.toytile + +import framework.top.GlobalConfig +import framework.builtin.configloader.ConfigLoader +import examples.toy.tiles.toytile.configs.{ToyTileConfig => ToyTileParam} + +/** + * Toy tile assembler. + * + * Reads `toytile/configs/default.json` to learn which Core configs to use, + * dispatches to each reflectively, and produces the per-core + * `Seq[Option[GlobalConfig]]` consumed by the framework's `WithBBTile`. + * + * Each per-core `GlobalConfig`'s `top.nCores` is patched here to equal the + * number of cores in this tile, so that the framework's BBTile invariants + * (`cfg.top.nCores == nCoresPerTile`) hold without each core having to + * know how many siblings it has. + */ +object ToyTileConfig { + + def apply(): Seq[Option[GlobalConfig]] = { + val tileParam = ToyTileParam() + val nCores = tileParam.coreConfigs.size + tileParam.coreConfigs.map { name => + val cfg = ConfigLoader.loadApply[GlobalConfig](name) + Some(cfg.copy(top = cfg.top.copy(nCores = nCores))) + } + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/configs/ToyTileParam.scala b/arch/src/main/scala/examples/toy/tiles/toytile/configs/ToyTileParam.scala new file mode 100644 index 00000000..b0a52447 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/configs/ToyTileParam.scala @@ -0,0 +1,16 @@ +package examples.toy.tiles.toytile.configs + +import upickle.default._ + +case class ToyTileConfig( + coreConfigs: Seq[String]) + +object ToyTileConfig { + implicit val rw: ReadWriter[ToyTileConfig] = macroRW + + def apply(): ToyTileConfig = { + val jsonStr = scala.io.Source.fromFile("src/main/scala/examples/toy/tiles/toytile/configs/default.json").mkString + read[ToyTileConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/configs/default.json b/arch/src/main/scala/examples/toy/tiles/toytile/configs/default.json new file mode 100644 index 00000000..e14aab9b --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/configs/default.json @@ -0,0 +1,5 @@ +{ + "coreConfigs": [ + "examples.toy.tiles.toytile.toycore.ToyCoreConfig" + ] +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/ToyCoreConfig.scala b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/ToyCoreConfig.scala new file mode 100644 index 00000000..350acc72 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/ToyCoreConfig.scala @@ -0,0 +1,23 @@ +package examples.toy.tiles.toytile.toycore + +import framework.top.GlobalConfig +import framework.balldomain.configs.BallDomainParam +import framework.builtin.configloader.ConfigLoader +import examples.toy.tiles.toytile.toycore.configs.{ToyCoreConfig => ToyCoreParam} + +/** + * Toy core assembler. + * + * Reads `toycore/configs/default.json` to learn which Ball domain config + * to use, dispatches to it reflectively, and overrides the framework + * default `ballDomain` with the result. + */ +object ToyCoreConfig { + + def apply(): GlobalConfig = { + val coreParam = ToyCoreParam() + val ballDomainParam = ConfigLoader.loadApply[BallDomainParam](coreParam.balldomain) + GlobalConfig().copy(ballDomain = ballDomainParam) + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/BallDomainConfig.scala b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/BallDomainConfig.scala new file mode 100644 index 00000000..41ec44d9 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/BallDomainConfig.scala @@ -0,0 +1,14 @@ +package examples.toy.tiles.toytile.toycore.balldomain.configs + +import upickle.default._ +import framework.balldomain.configs.{BallDomainParam, BallIdMapping} + +object BallDomainConfig { + private val path = "src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json" + + def apply(): BallDomainParam = { + val jsonStr = scala.io.Source.fromFile(path).mkString + read[BallDomainParam](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json new file mode 100644 index 00000000..99d327d0 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json @@ -0,0 +1,48 @@ +{ + "ballNum": 9, + "ballIdMappings": [ + {"ballId": 0, "ballName": "VecBall", "ballClass": "framework.balldomain.prototype.vector.VecBall", "inBW": 2, "outBW": 4}, + {"ballId": 1, "ballName": "ReluBall", "ballClass": "framework.balldomain.prototype.relu.ReluBall", "inBW": 1, "outBW": 1}, + {"ballId": 2, "ballName": "TransposeBall", "ballClass": "framework.balldomain.prototype.transpose.TransposeBall", "inBW": 1, "outBW": 1}, + {"ballId": 3, "ballName": "Im2colBall", "ballClass": "framework.balldomain.prototype.im2col.Im2colBall", "inBW": 1, "outBW": 1}, + {"ballId": 4, "ballName": "SystolicArrayBall", "ballClass": "framework.balldomain.prototype.systolicarray.SystolicArrayBall","inBW": 2, "outBW": 4}, + {"ballId": 5, "ballName": "QuantBall", "ballClass": "framework.balldomain.prototype.quant.QuantBall", "inBW": 1, "outBW": 1}, + {"ballId": 6, "ballName": "DequantBall", "ballClass": "framework.balldomain.prototype.dequant.DequantBall", "inBW": 1, "outBW": 1}, + {"ballId": 7, "ballName": "GemminiBall", "ballClass": "framework.balldomain.prototype.gemmini.GemminiBall", "inBW": 2, "outBW": 4}, + {"ballId": 8, "ballName": "TraceBall", "ballClass": "framework.balldomain.prototype.trace.TraceBall", "inBW": 1, "outBW": 1} + ], + "ballISA": [ + {"mnemonic": "MATMUL_WARP16", "funct7": 64, "bid": 0}, + {"mnemonic": "RELU", "funct7": 50, "bid": 1}, + {"mnemonic": "TRANSPOSE", "funct7": 49, "bid": 2}, + {"mnemonic": "IM2COL", "funct7": 48, "bid": 3}, + {"mnemonic": "SYSTOLIC", "funct7": 65, "bid": 4}, + {"mnemonic": "QUANT", "funct7": 51, "bid": 5}, + {"mnemonic": "DEQUANT", "funct7": 52, "bid": 6}, + {"mnemonic": "GEMMINI_CONFIG", "funct7": 2, "bid": 7}, + {"mnemonic": "GEMMINI_FLUSH", "funct7": 3, "bid": 7}, + {"mnemonic": "GEMMINI_PRELOAD", "funct7": 53, "bid": 7}, + {"mnemonic": "GEMMINI_COMPUTE_PRELOADED", "funct7": 66, "bid": 7}, + {"mnemonic": "GEMMINI_COMPUTE_ACCUMULATED", "funct7": 67, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_BOUNDS", "funct7": 80, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_ADDR_A", "funct7": 81, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_ADDR_B", "funct7": 82, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_ADDR_D", "funct7": 83, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_ADDR_C", "funct7": 84, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_STRIDES_AB","funct7": 85, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS_CONFIG_STRIDES_DC","funct7": 86, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_WS", "funct7": 87, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_1", "funct7": 96, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_2", "funct7": 97, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_3", "funct7": 98, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_4", "funct7": 99, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_5", "funct7": 100, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_6", "funct7": 101, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_7", "funct7": 102, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_8", "funct7": 103, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_9", "funct7": 104, "bid": 7}, + {"mnemonic": "GEMMINI_LOOP_CONV_WS", "funct7": 105, "bid": 7}, + {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8}, + {"mnemonic": "BDB_BACKDOOR", "funct7": 54, "bid": 8} + ] +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/ToyCoreParam.scala b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/ToyCoreParam.scala new file mode 100644 index 00000000..dfe6e619 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/ToyCoreParam.scala @@ -0,0 +1,17 @@ +package examples.toy.tiles.toytile.toycore.configs + +import upickle.default._ + +case class ToyCoreConfig( + balldomain: String) + +object ToyCoreConfig { + implicit val rw: ReadWriter[ToyCoreConfig] = macroRW + + def apply(): ToyCoreConfig = { + val jsonStr = + scala.io.Source.fromFile("src/main/scala/examples/toy/tiles/toytile/toycore/configs/default.json").mkString + read[ToyCoreConfig](jsonStr) + } + +} diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/default.json b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/default.json new file mode 100644 index 00000000..e51398b5 --- /dev/null +++ b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/configs/default.json @@ -0,0 +1,3 @@ +{ + "balldomain": "examples.toy.tiles.toytile.toycore.balldomain.configs.BallDomainConfig" +} diff --git a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala b/arch/src/main/scala/framework/balldomain/BallDomain.scala similarity index 74% rename from arch/src/main/scala/examples/toy/balldomain/BallDomain.scala rename to arch/src/main/scala/framework/balldomain/BallDomain.scala index 9e9541e3..7af65bba 100644 --- a/arch/src/main/scala/examples/toy/balldomain/BallDomain.scala +++ b/arch/src/main/scala/framework/balldomain/BallDomain.scala @@ -1,55 +1,52 @@ -package examples.toy.balldomain +package framework.balldomain import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.tile._ import framework.top.GlobalConfig -import examples.toy.balldomain.bbus.BBusModule -import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} -import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} +import framework.balldomain.bbus.BBus +import framework.balldomain.decoder.BallDomainDecoder import framework.balldomain.rs.BallReservationStation +import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} +/** + * Ball domain. + * + * BBus reflectively constructs ball instances from `b.ballDomain.ballIdMappings`; + * `BallDomainDecoder` reads `b.ballDomain.ballISA` to route funct7 → bid. + * Both are pure data-driven, so no example needs its own subclass. + */ @instantiable class BallDomain(val b: GlobalConfig) extends Module { - val memChannel = b.top.ballMemChannelNum val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum @public - val global_issue_i = IO(Flipped(Decoupled(new GlobalSchedIssue(b)))) - + val global_issue_i = IO(Flipped(Decoupled(new GlobalSchedIssue(b)))) @public val global_complete_o = IO(Decoupled(new GlobalSchedComplete(b))) - @public - val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) - + val bankRead = IO(Vec(totalBallRead, Flipped(new BankRead(b)))) @public - val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) - + val bankWrite = IO(Vec(totalBallWrite, Flipped(new BankWrite(b)))) @public - val subRobReq = IO(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) + val subRobReq = IO(Vec(b.ballDomain.ballNum, Decoupled(new SubRobRow(b)))) - val bbus: Instance[BBusModule] = Instantiate(new BBusModule(b)) + val bbus: Instance[BBus] = Instantiate(new BBus(b)) val ballDecoder: Instance[BallDomainDecoder] = Instantiate(new BallDomainDecoder(b)) val ballRs: Instance[BallReservationStation] = Instantiate(new BallReservationStation(b)) //--------------------------------------------------------------------------- -// Global RS -> Decoder (receive global issue and construct PostGDCmd) +// Global RS -> Decoder //--------------------------------------------------------------------------- - - // Convert global RS issue to Decoder input format ballDecoder.cmd_i.valid := global_issue_i.valid ballDecoder.cmd_i.bits := global_issue_i.bits.cmd global_issue_i.ready := ballDecoder.cmd_i.ready //--------------------------------------------------------------------------- -// Decoder -> Local BallRS (multi-channel issue to each Ball device) +// Decoder -> Local BallRS //--------------------------------------------------------------------------- - - // Connect decoded instruction and global rob_id ballRs.ball_decode_cmd_i.valid := ballDecoder.ball_decode_cmd_o.valid ballRs.ball_decode_cmd_i.bits.cmd := ballDecoder.ball_decode_cmd_o.bits ballRs.ball_decode_cmd_i.bits.rob_id := global_issue_i.bits.rob_id @@ -58,7 +55,7 @@ class BallDomain(val b: GlobalConfig) extends Module { ballDecoder.ball_decode_cmd_o.ready := ballRs.ball_decode_cmd_i.ready //--------------------------------------------------------------------------- -// Local BallRS -> BBus (multi-channel) +// Local BallRS -> BBus //--------------------------------------------------------------------------- bbus.cmdReq <> ballRs.issue_o.balls ballRs.commit_i.balls <> bbus.cmdResp @@ -69,18 +66,16 @@ class BallDomain(val b: GlobalConfig) extends Module { bbus.bankRead <> bankRead bbus.bankWrite <> bankWrite - // BBus -> SubROB for (i <- 0 until b.ballDomain.ballNum) { subRobReq(i) <> bbus.subRobReq(i) } //--------------------------------------------------------------------------- -// Local RS completion signal -> Global RS (single channel, includes global rob_id) +// Local RS completion -> Global RS //--------------------------------------------------------------------------- global_complete_o.valid := ballRs.complete_o.valid global_complete_o.bits.rob_id := ballRs.complete_o.bits.rob_id global_complete_o.bits.is_sub := ballRs.complete_o.bits.is_sub global_complete_o.bits.sub_rob_id := ballRs.complete_o.bits.sub_rob_id ballRs.complete_o.ready := global_complete_o.ready - } diff --git a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala index 62391adb..9994e54d 100644 --- a/arch/src/main/scala/framework/balldomain/bbus/bbus.scala +++ b/arch/src/main/scala/framework/balldomain/bbus/bbus.scala @@ -11,10 +11,15 @@ import framework.balldomain.bbus.cmdrouter.CmdRouter import framework.balldomain.blink.{BankRead, BankWrite, SubRobRow} /** - * BBus - Ball bus, manages connections and arbitration of multiple Ball devices + * BBus - Ball bus, manages connections and arbitration of multiple Ball devices. + * + * Ball generators are produced reflectively from `b.ballDomain.ballIdMappings`: + * each mapping carries a `ballClass` FQCN whose constructor `(GlobalConfig)` is + * invoked. Framework does not maintain or interpret the list of balls; the + * config layer is the single source of truth. */ @instantiable -class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) extends Module { +class BBus(val b: GlobalConfig) extends Module { val numBalls = b.ballDomain.ballNum val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum @@ -33,7 +38,14 @@ class BBus(val b: GlobalConfig, ballGenerators: Seq[() => HasBlink with Module]) @public val subRobReq = IO(Vec(numBalls, Decoupled(new SubRobRow(b)))) - val balls = ballGenerators.map(gen => Module(gen())) + val balls = b.ballDomain.ballIdMappings.map { mapping => + Module { + val cls = Class.forName(mapping.ballClass) + val ctor = cls.getConstructor(classOf[GlobalConfig]) + ctor.newInstance(b).asInstanceOf[HasBlink with Module] + } + } + val cmdRouter: Instance[CmdRouter] = Instantiate(new CmdRouter(b)) val pmc: Instance[BallCyclePMC] = Instantiate(new BallCyclePMC(b)) diff --git a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala index 92090ece..0c02caa1 100644 --- a/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala +++ b/arch/src/main/scala/framework/balldomain/configs/BallDomainParam.scala @@ -3,22 +3,30 @@ package framework.balldomain.configs import upickle.default._ case class BallIdMapping( - ballId: Int, - ballName: String, - inBW: Int, - outBW: Int) + ballId: Int, + ballName: String, + ballClass: String, + inBW: Int, + outBW: Int) + +case class BallISAEntry( + mnemonic: String, + funct7: Int, + bid: Int) case class BallDomainParam( ballNum: Int, - ballIdMappings: Seq[BallIdMapping]) + ballIdMappings: Seq[BallIdMapping], + ballISA: Seq[BallISAEntry]) object BallDomainParam { implicit val ballIdMappingRW: ReadWriter[BallIdMapping] = macroRW + implicit val ballISAEntryRW: ReadWriter[BallISAEntry] = macroRW implicit val rw: ReadWriter[BallDomainParam] = macroRW - def apply(): BallDomainParam = { - val jsonStr = scala.io.Source.fromFile("src/main/scala/framework/balldomain/configs/default.json").mkString - read[BallDomainParam](jsonStr) - } - + /** + * Empty default. Each example's GlobalConfig assembler is responsible for + * supplying its own `BallDomainParam` (typically via a layered JSON loader). + */ + def apply(): BallDomainParam = BallDomainParam(0, Seq.empty, Seq.empty) } diff --git a/arch/src/main/scala/framework/balldomain/configs/default.json b/arch/src/main/scala/framework/balldomain/configs/default.json deleted file mode 100644 index e4a7df1a..00000000 --- a/arch/src/main/scala/framework/balldomain/configs/default.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "ballNum": 9, - "ballIdMappings": [ - {"ballId": 0, "ballName": "VecBall", "inBW": 2, "outBW": 4}, - {"ballId": 1, "ballName": "ReluBall", "inBW": 1, "outBW": 1}, - {"ballId": 2, "ballName": "TransposeBall", "inBW": 1, "outBW": 1}, - {"ballId": 3, "ballName": "Im2colBall", "inBW": 1, "outBW": 1}, - {"ballId": 4, "ballName": "SystolicArrayBall", "inBW": 2, "outBW": 4}, - {"ballId": 5, "ballName": "QuantBall", "inBW": 1, "outBW": 1}, - {"ballId": 6, "ballName": "DequantBall", "inBW": 1, "outBW": 1}, - {"ballId": 7, "ballName": "GemminiBall", "inBW": 2, "outBW": 4}, - {"ballId": 8, "ballName": "TraceBall", "inBW": 1, "outBW": 1} - ] -} diff --git a/arch/src/main/scala/framework/balldomain/decoder/BallDecodeCmd.scala b/arch/src/main/scala/framework/balldomain/decoder/BallDecodeCmd.scala new file mode 100644 index 00000000..934c661d --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/decoder/BallDecodeCmd.scala @@ -0,0 +1,29 @@ +package framework.balldomain.decoder + +import chisel3._ +import chisel3.util._ + +/** + * Wire-level command bundle exchanged between user-defined Ball decoders + * and framework infrastructure (BallReservationStation, BBus). The + * concrete decode logic (funct7 → BID/operands) lives in user code. + */ +class BallDecodeCmd(numBanks: Int, iterLen: Int) extends Bundle { + val bid = UInt(5.W) + val funct7 = UInt(7.W) + val iter = UInt(iterLen.W) + + val op1_en = Bool() + val op2_en = Bool() + val wr_spad_en = Bool() + val op1_from_spad = Bool() + val op2_from_spad = Bool() + val special = UInt(64.W) + + val op1_bank = UInt(log2Up(numBanks).W) + val op2_bank = UInt(log2Up(numBanks).W) + val wr_bank = UInt(log2Up(numBanks).W) + + val rs1 = UInt(64.W) + val rs2 = UInt(64.W) +} diff --git a/arch/src/main/scala/framework/balldomain/decoder/BallDomainDecoder.scala b/arch/src/main/scala/framework/balldomain/decoder/BallDomainDecoder.scala new file mode 100644 index 00000000..1c8049f2 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/decoder/BallDomainDecoder.scala @@ -0,0 +1,83 @@ +package framework.balldomain.decoder + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.top.GlobalConfig + +/** + * Ball-domain instruction decoder. + * + * - funct7 encoding contract → enable bits, operand/write banks, iter + * count, pass-through of rs1/rs2/funct7 (pure framework concern). + * - funct7 → bid routing, generated from `b.ballDomain.ballISA` + * (a `(mnemonic, funct7, bid)` table the user provides via + * `default.json`); no per-example Scala decoder is needed. + */ +@instantiable +class BallDomainDecoder(val b: GlobalConfig) extends Module { + val bankIdLen = b.frontend.bank_id_len + val iterLen = b.frontend.iter_len + + @public + val cmd_i = IO(Flipped(Decoupled(new PostGDCmd(b)))) + @public + val ball_decode_cmd_o = IO(Decoupled(new BallDecodeCmd(b.memDomain.bankNum, iterLen))) + + cmd_i.ready := ball_decode_cmd_o.ready + + val func7 = cmd_i.bits.cmd.funct + val rs1 = cmd_i.bits.cmd.rs1Data + val rs2 = cmd_i.bits.cmd.rs2Data + + val op1_bank_raw = rs1(bankIdLen - 1, 0) + val op2_bank_raw = rs1(bankIdLen + 9, 10) + val wr_bank_raw = rs1(bankIdLen + 19, 20) + val iter_raw = rs1(63, 30) + + // funct7[6:4] enable encoding: + // 000 no bank 001 1rd 010 1wr 011 1rd+1wr + // 100 2rd+1wr 101/110/111 no bank (extended opcode space) + val enableBits = func7(6, 4) + val hasRd0 = enableBits === 1.U || enableBits === 3.U || enableBits === 4.U + val hasRd1 = enableBits === 4.U + val hasWr = enableBits === 2.U || enableBits === 3.U || enableBits === 4.U + + // funct7 -> bid lookup, generated from b.ballDomain.ballISA + val bidWire = WireDefault(0.U(5.W)) + val isaValidWire = WireDefault(false.B) + b.ballDomain.ballISA.foreach { e => + when(func7 === e.funct7.U(7.W)) { + bidWire := e.bid.U + isaValidWire := true.B + } + } + + ball_decode_cmd_o.valid := cmd_i.valid && (cmd_i.bits.domain_id === DomainId.BALL) + ball_decode_cmd_o.bits.bid := Mux(ball_decode_cmd_o.valid, bidWire, 0.U) + ball_decode_cmd_o.bits.funct7 := Mux(ball_decode_cmd_o.valid, func7, 0.U) + ball_decode_cmd_o.bits.iter := Mux(ball_decode_cmd_o.valid, iter_raw, 0.U(iterLen.W)) + ball_decode_cmd_o.bits.special := Mux(ball_decode_cmd_o.valid, rs2, 0.U(64.W)) + ball_decode_cmd_o.bits.op1_bank := Mux(ball_decode_cmd_o.valid && hasRd0, op1_bank_raw, 0.U) + ball_decode_cmd_o.bits.op2_bank := Mux(ball_decode_cmd_o.valid && hasRd1, op2_bank_raw, 0.U) + ball_decode_cmd_o.bits.wr_bank := Mux(ball_decode_cmd_o.valid && hasWr, wr_bank_raw, 0.U) + ball_decode_cmd_o.bits.op1_en := ball_decode_cmd_o.valid && hasRd0 + ball_decode_cmd_o.bits.op2_en := ball_decode_cmd_o.valid && hasRd1 + ball_decode_cmd_o.bits.wr_spad_en := ball_decode_cmd_o.valid && hasWr + ball_decode_cmd_o.bits.op1_from_spad := ball_decode_cmd_o.valid && hasRd0 + ball_decode_cmd_o.bits.op2_from_spad := ball_decode_cmd_o.valid && hasRd1 + + ball_decode_cmd_o.bits.rs1 := rs1 + ball_decode_cmd_o.bits.rs2 := rs2 + + assert( + !(cmd_i.fire && (cmd_i.bits.domain_id === DomainId.BALL) && !isaValidWire), + "BallDomainDecoder: funct7 has no matching entry in ballISA" + ) + assert( + !(ball_decode_cmd_o.valid && ball_decode_cmd_o.bits.op1_en && ball_decode_cmd_o.bits.op2_en && + ball_decode_cmd_o.bits.op1_bank === ball_decode_cmd_o.bits.op2_bank), + "BallDomainDecoder: Ball instruction OpA and OpB cannot access the same bank" + ) +} diff --git a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala index 35cb7f67..aed683a7 100644 --- a/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala +++ b/arch/src/main/scala/framework/balldomain/rs/reservationStation.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.hierarchy.{instantiable, public} import framework.top.GlobalConfig -import examples.toy.balldomain.BallDecodeCmd +import framework.balldomain.decoder.BallDecodeCmd // Ball domain issue interface - includes global rob_id class BallRsIssue(b: GlobalConfig) extends Bundle { diff --git a/arch/src/main/scala/framework/builtin/configloader/ConfigLoader.scala b/arch/src/main/scala/framework/builtin/configloader/ConfigLoader.scala new file mode 100644 index 00000000..45d6d7bd --- /dev/null +++ b/arch/src/main/scala/framework/builtin/configloader/ConfigLoader.scala @@ -0,0 +1,20 @@ +package framework.builtin.configloader + +/** + * Helper to dynamically dispatch to a sibling config in the JSON-driven + * layered example config systems (toy / goban / konbi / poly / ...). + * + * Each layer's `default.json` carries a string field whose value is the + * fully-qualified name of a Scala `object` providing a no-arg `apply()`. + * `loadApply` resolves that name and invokes `apply()` reflectively. + */ +object ConfigLoader { + + def loadApply[T](objectName: String): T = { + val cls = Class.forName(objectName + "$") + val module = cls.getField("MODULE$").get(null) + val applyMthd = cls.getMethod("apply") + applyMthd.invoke(module).asInstanceOf[T] + } + +} diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index 0cc82421..bcdc40ea 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -42,15 +42,10 @@ import framework.memdomain.backend.shared.SharedMemBackend import framework.memdomain.frontend.outside_channel.MemConfigerIO /** - * BBTile — a composable tile containing Rocket core(s) + optional Buckyball accelerator(s). + * BBTile — a composable tile containing one Rocket core + optional per-core-index Buckyball slots. * - * When nCores=1 (default), behaviour is identical to the original single-core tile. - * When nCores>1, the tile contains N (RocketBB + BuckyballAccelerator) pairs that share - * a single SharedMemBackend and BarrierUnit. - * - * The trait-provided DCache/ICache/PTW serve core-0. Cores 1..N-1 are wired entirely - * inside BBTileModuleImp (no extra diplomacy DCache/ICache — they share core-0's cache - * hierarchy via the same TL xbar for now; independent caches are a future enhancement). + * nCores controls buckyball slot count and shared backend sizing. + * Rocket is still a single core today; RoCC is wired to slot-0. */ class BBTile private ( val bbParams: BBTileParams, @@ -70,9 +65,31 @@ class BBTile private ( )( implicit p: Parameters ) = - this(params, crossing.crossingType, lookup, BBTile.injectBuildRoCC(p, params.withBuckyball)) - - val nCores = bbParams.nCores + this(params, crossing.crossingType, lookup, BBTile.injectBuildRoCC(p, params.withAnyBuckyball)) + + val nCores = bbParams.nCores + val bbPerCore = bbParams.resolvedBuckyballPerCore + require(bbPerCore.size == nCores, s"bbPerCore size (${bbPerCore.size}) must equal nCores ($nCores)") + val bbEnabledCoreIds = bbPerCore.zipWithIndex.collect { case (Some(_), i) => i } + val hasBuckyball = bbEnabledCoreIds.nonEmpty + val bbSharedConfig = bbPerCore.collectFirst { case Some(cfg) => cfg } + if (hasBuckyball) { + require( + bbEnabledCoreIds.contains(0), + "core-0 must enable buckyball because RoCC cmd/resp is currently wired to core-0 only" + ) + val cfg0 = bbSharedConfig.get + require(cfg0.top.nCores == nCores, s"buckyball top.nCores (${cfg0.top.nCores}) must equal tile nCores ($nCores)") + bbEnabledCoreIds.foreach { i => + val cfg = bbPerCore(i).get + require( + cfg.top.nCores == nCores, + s"core-$i buckyball top.nCores (${cfg.top.nCores}) must equal tile nCores ($nCores)" + ) + require(cfg.memDomain.bankChannel == cfg0.memDomain.bankChannel, s"core-$i bankChannel mismatch") + require(cfg.memDomain.dma_buswidth == cfg0.memDomain.dma_buswidth, s"core-$i dma_buswidth mismatch") + } + } // RoCC CSRs — Buckyball doesn't use custom CSRs, so this is always empty val roccCSRs: Seq[Seq[CustomCSR]] = Nil @@ -116,32 +133,31 @@ class BBTile private ( // --------------------------------------------------------------------------- // Buckyball accelerator TileLink nodes (diplomacy layer) — N pairs of DMA // --------------------------------------------------------------------------- - val bbConfig = bbParams.buckyballConfig - val bb_reader_nodes: Seq[Option[TLClientNode]] = (0 until nCores).map { i => - if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = s"bb-dma-reader-$i", - sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) + sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbPerCore(i).get.memDomain.dma_n_xacts) )))))) else None } val bb_writer_nodes: Seq[Option[TLClientNode]] = (0 until nCores).map { i => - if (bbParams.withBuckyball) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = s"bb-dma-writer-$i", - sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbConfig.memDomain.dma_n_xacts) + sourceId = freechips.rocketchip.diplomacy.IdRange(0, bbPerCore(i).get.memDomain.dma_n_xacts) )))))) else None } // Gather all DMA nodes into one xbar - if (bbParams.withBuckyball) { + if (hasBuckyball) { + val cfg0 = bbSharedConfig.get val bb_xbar = TLXbar() - for (i <- 0 until nCores) { + for (i <- bbEnabledCoreIds) { bb_xbar := TLBuffer() := bb_reader_nodes(i).get bb_xbar := TLBuffer() := bb_writer_nodes(i).get } - tlOtherMastersNode :=* TLWidthWidget(bbConfig.memDomain.dma_buswidth / 8) := TLBuffer() := bb_xbar + tlOtherMastersNode :=* TLWidthWidget(cfg0.memDomain.dma_buswidth / 8) := TLBuffer() := bb_xbar } // --------------------------------------------------------------------------- @@ -154,7 +170,7 @@ class BBTile private ( // DCache port count: core + PTW(via usingVM) + DTIM + vector + RoCC tieoff nDCachePorts += 1 + (dtim_adapter.isDefined).toInt + bbParams.core.vector.map(_.useDCache.toInt).getOrElse(0) + - bbParams.withBuckyball.toInt + hasBuckyball.toInt // --------------------------------------------------------------------------- // Device tree properties @@ -187,8 +203,8 @@ class BBTile private ( } // Buckyball needs one PTW port per accelerator - if (bbParams.withBuckyball) { - nPTWPorts += nCores + if (hasBuckyball) { + nPTWPorts += bbEnabledCoreIds.size } override lazy val module = new BBTileModuleImp(this) @@ -223,7 +239,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC val fpuOpt = outer.bbParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) // --- Rocket core (using our fork that accepts BBTile) --- - val core = Module(new RocketBB(outer)(outer.p)) + val core = Module(new RocketBB(outer, outer.bbPerCore.head.isDefined)(outer.p)) // Vector unit connections outer.vector_unit.foreach { v => @@ -356,38 +372,47 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC // --------------------------------------------------------------------------- // Buckyball accelerators — N instances sharing SharedMemBackend + BarrierUnit // --------------------------------------------------------------------------- - if (outer.bbParams.withBuckyball) { - val bankChannel = outer.bbConfig.memDomain.bankChannel - - // Instantiate N accelerators - val accelerators = (0 until nCores).map { i => - val (tl_reader, edge) = outer.bb_reader_nodes(i).get.out(0) - val (tl_writer, _) = outer.bb_writer_nodes(i).get.out(0) - val acc = Module(new BuckyballAccelerator(outer.bbConfig)(edge)) - acc.io.hartid := outer.hartIdSinkNode.bundle + i.U - - // DMA TileLink - tl_reader <> acc.io.tl_reader - tl_writer <> acc.io.tl_writer - - // PTW - wireBBPtw(acc) - - // TLB exception - acc.io.tlbExp(0).flush_skip := false.B - acc.io.tlbExp(0).flush_retry := false.B + def tieOffMemReq(req: MemRequestIO): Unit = { + req.write.req.valid := false.B + req.write.req.bits := DontCare + req.write.resp.ready := true.B + req.read.req.valid := false.B + req.read.req.bits := DontCare + req.read.resp.ready := true.B + req.bank_id := 0.U + req.group_id := 0.U + req.is_shared := false.B + req.hart_id := 0.U + } - // CPU sfence → Buckyball TLB flush - acc.io.sfence := ptw.io.dpath.sfence.valid + if (outer.hasBuckyball) { + val cfg0 = outer.bbSharedConfig.get + val bankChannel = cfg0.memDomain.bankChannel - acc + // Instantiate accelerators for enabled cores only + val accelerators = (0 until nCores).map { i => + outer.bbPerCore(i).map { cfg => + val (tl_reader, edge) = outer.bb_reader_nodes(i).get.out(0) + val (tl_writer, _) = outer.bb_writer_nodes(i).get.out(0) + val acc = Module(new BuckyballAccelerator(cfg)(edge)) + acc.io.hartid := outer.hartIdSinkNode.bundle + i.U + + tl_reader <> acc.io.tl_reader + tl_writer <> acc.io.tl_writer + wireBBPtw(acc) + acc.io.tlbExp(0).flush_skip := false.B + acc.io.tlbExp(0).flush_retry := false.B + acc.io.sfence := ptw.io.dpath.sfence.valid + acc + } } // Core-0 RoCC wiring (the single Rocket core drives accelerator 0) - accelerators(0).io.cmd <> core.io.rocc.cmd - core.io.rocc.resp <> accelerators(0).io.resp - core.io.rocc.busy := accelerators(0).io.busy - core.io.rocc.interrupt := accelerators(0).io.interrupt + val core0Acc = accelerators(0).get + core0Acc.io.cmd <> core.io.rocc.cmd + core.io.rocc.resp <> core0Acc.io.resp + core.io.rocc.busy := core0Acc.io.busy + core.io.rocc.interrupt := core0Acc.io.interrupt // RoCC mem: tied-off HellaCacheIF for the DCache arbiter port count val roccMemIF = Module(new SimpleHellaCacheIF()) @@ -401,39 +426,39 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC core.io.rocc.mem := DontCare // SharedMemBackend (tile-level singleton) - val sharedBackend = Module(new SharedMemBackend(outer.bbConfig)) + val sharedBackend = Module(new SharedMemBackend(cfg0)) // Connect each accelerator's shared ports to the SharedMemBackend for (i <- 0 until nCores) { for (ch <- 0 until bankChannel) { val slot = i * bankChannel + ch - sharedBackend.io.mem_req(slot) <> accelerators(i).io.shared_mem_req(ch) + accelerators(i) match { + case Some(acc) => sharedBackend.io.mem_req(slot) <> acc.io.shared_mem_req(ch) + case None => tieOffMemReq(sharedBackend.io.mem_req(slot)) + } } - // Shared query: connect per-core query to shared backend - // (only one query port on SharedMemBackend — for now use accelerator 0's query; - // each accelerator's MemBackend routes shared queries through its IO) } - // Shared config arbiter: N accelerators → 1 SharedMemBackend config port - val cfgArb = Module(new Arbiter(new MemConfigerIO(outer.bbConfig), nCores)) - for (i <- 0 until nCores) { - cfgArb.io.in(i) <> accelerators(i).io.shared_config + // Shared config arbiter: enabled accelerators -> 1 SharedMemBackend config port + val enabledAccelerators = outer.bbEnabledCoreIds.map(i => accelerators(i).get) + val cfgArb = Module(new Arbiter(new MemConfigerIO(cfg0), enabledAccelerators.size)) + for ((acc, i) <- enabledAccelerators.zipWithIndex) { + cfgArb.io.in(i) <> acc.io.shared_config } sharedBackend.io.config <> cfgArb.io.out - // Shared query — simplified: each accelerator queries independently, - // but SharedMemBackend has one query port. Use accelerator 0's for now. - sharedBackend.io.query_vbank_id := accelerators(0).io.shared_query_vbank_id - accelerators(0).io.shared_query_group_count := sharedBackend.io.query_group_count - for (i <- 1 until nCores) { - accelerators(i).io.shared_query_group_count := sharedBackend.io.query_group_count + sharedBackend.io.query_vbank_id := core0Acc.io.shared_query_vbank_id + for (i <- 0 until nCores) { + accelerators(i).foreach { acc => + acc.io.shared_query_group_count := sharedBackend.io.query_group_count + } } // BarrierUnit (tile-level singleton) - val barrierUnit = Module(new BarrierUnit(nCores)) - for (i <- 0 until nCores) { - barrierUnit.io.arrive(i) := accelerators(i).io.barrier_arrive - accelerators(i).io.barrier_release := barrierUnit.io.release(i) + val barrierUnit = Module(new BarrierUnit(enabledAccelerators.size)) + for ((acc, i) <- enabledAccelerators.zipWithIndex) { + barrierUnit.io.arrive(i) := acc.io.barrier_arrive + acc.io.barrier_release := barrierUnit.io.release(i) } } else { diff --git a/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala b/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala index 6b4c628f..ef66ff4e 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala @@ -11,30 +11,46 @@ import framework.top.GlobalConfig /** * Parameters for a BBTile. * - * A BBTile contains N Rocket cores, each optionally paired with a Buckyball accelerator. + * A BBTile contains one Rocket core and N buckyball slots. + * Each slot can be enabled/disabled independently, with independent GlobalConfig. * Internal modules use @instantiable + config style; diplomacy is only used for TileLink ports. */ case class BBTileParams( - nCores: Int = 1, - withBuckyball: Boolean = true, - core: RocketCoreParams = RocketCoreParams(), - icache: Option[ICacheParams] = Some(ICacheParams()), - dcache: Option[DCacheParams] = Some(DCacheParams()), - btb: Option[BTBParams] = Some(BTBParams()), - buckyballConfig: GlobalConfig = GlobalConfig(), - tileId: Int = 0, - beuAddr: Option[BigInt] = None, - blockerCtrlAddr: Option[BigInt] = None, - clockSinkParams: ClockSinkParameters = ClockSinkParameters(), - boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None) + nCores: Int = 1, + withBuckyball: Boolean = true, + core: RocketCoreParams = RocketCoreParams(), + icache: Option[ICacheParams] = Some(ICacheParams()), + dcache: Option[DCacheParams] = Some(DCacheParams()), + btb: Option[BTBParams] = Some(BTBParams()), + buckyballConfig: GlobalConfig = GlobalConfig(), + buckyballPerCore: Seq[Option[GlobalConfig]] = Nil, + tileId: Int = 0, + beuAddr: Option[BigInt] = None, + blockerCtrlAddr: Option[BigInt] = None, + clockSinkParams: ClockSinkParameters = ClockSinkParameters(), + boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None) extends InstantiableTileParams[BBTile] { require(icache.isDefined) require(dcache.isDefined) require(nCores >= 1) + require( + buckyballPerCore.isEmpty || buckyballPerCore.size == nCores, + s"buckyballPerCore size (${buckyballPerCore.size}) must be 0 or nCores ($nCores)" + ) val baseName = "bbtile" val uniqueName = s"${baseName}_$tileId" + val resolvedBuckyballPerCore: Seq[Option[GlobalConfig]] = + if (buckyballPerCore.nonEmpty) buckyballPerCore + else Seq.fill(nCores)(if (withBuckyball) Some(buckyballConfig) else None) + + val withAnyBuckyball: Boolean = resolvedBuckyballPerCore.exists(_.isDefined) + + val enabledBuckyballCores: Seq[Int] = resolvedBuckyballPerCore.zipWithIndex.collect { + case (Some(_), i) => i + } + def instantiate( crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl diff --git a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala index 81c1901c..25992cae 100644 --- a/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala +++ b/arch/src/main/scala/framework/core/bbtile/BuckyballAccelerator.scala @@ -12,7 +12,7 @@ import framework.memdomain.MemDomain import framework.memdomain.backend.MemRequestIO import framework.memdomain.frontend.outside_channel.{MemConfigerIO} import framework.memdomain.frontend.outside_channel.tlb.{BBTLBExceptionIO, BBTLBPTWIO} -import examples.toy.balldomain.BallDomain +import framework.balldomain.BallDomain /** * Standalone Buckyball accelerator module. diff --git a/arch/src/main/scala/framework/core/bbtile/Configs.scala b/arch/src/main/scala/framework/core/bbtile/Configs.scala index 43f7b911..62ae1c93 100644 --- a/arch/src/main/scala/framework/core/bbtile/Configs.scala +++ b/arch/src/main/scala/framework/core/bbtile/Configs.scala @@ -9,11 +9,11 @@ import framework.top.GlobalConfig /** * Config fragment to add N BBTiles. * - * Each BBTile contains one Rocket core + optional Buckyball accelerator. + * Each BBTile can host nCoresPerTile Buckyball slots. */ object WithNBBTiles { - private def defaultCrossing(location: HierarchicalLocation): RocketCrossingParams = + def defaultCrossing(location: HierarchicalLocation): RocketCrossingParams = RocketCrossingParams( master = HierarchicalElementMasterPortParams.locationDefault(location), slave = HierarchicalElementSlavePortParams.locationDefault(location), @@ -25,20 +25,87 @@ object WithNBBTiles { } +class WithBBTile( + location: HierarchicalLocation = InSubsystem, + withBuckyball: Boolean = true, + buckyballConfig: GlobalConfig = GlobalConfig(), + crossing: Option[RocketCrossingParams] = None, + nCoresPerTile: Int = 1, + buckyballPerCore: Option[Seq[Option[GlobalConfig]]] = None) + extends Config((site, here, up) => { + case TilesLocated(`location`) => + val prev = up(TilesLocated(`location`), site) + val idOffset = up(NumTiles) + val actualCrossing = crossing.getOrElse(WithNBBTiles.defaultCrossing(location)) + val resolvedBuckyballPerCore = buckyballPerCore.getOrElse( + Seq.fill(nCoresPerTile)(if (withBuckyball) Some(buckyballConfig) else None) + ) + require( + resolvedBuckyballPerCore.size == nCoresPerTile, + s"buckyballPerCore size (${resolvedBuckyballPerCore.size}) must equal nCoresPerTile ($nCoresPerTile)" + ) + val tileParams = BBTileParams( + nCores = nCoresPerTile, + withBuckyball = withBuckyball, + buckyballConfig = buckyballConfig, + buckyballPerCore = resolvedBuckyballPerCore, + core = RocketCoreParams( + mulDiv = Some(MulDivParams( + mulUnroll = 8, + mulEarlyOut = true, + divEarlyOut = true + )), + useZba = true, + useZbb = true, + useZbs = true, + fpu = Some(FPUParams(minFLen = 16)) + ), + dcache = Some(DCacheParams( + nSets = 64, + nWays = 8, + rowBits = site(SystemBusKey).beatBits, + nMSHRs = 0, + blockBytes = site(CacheBlockBytes) + )), + icache = Some(ICacheParams( + nSets = 64, + nWays = 8, + rowBits = site(SystemBusKey).beatBits, + blockBytes = site(CacheBlockBytes) + )) + ) + BBTileAttachParams( + tileParams.copy(tileId = idOffset), + actualCrossing + ) +: prev + case NumTiles => up(NumTiles) + 1 + }) + class WithNBBTiles( - n: Int, - location: HierarchicalLocation = InSubsystem, - withBuckyball: Boolean = true, - buckyballConfig: GlobalConfig = GlobalConfig(), - crossing: Option[RocketCrossingParams] = None) + n: Int, + location: HierarchicalLocation = InSubsystem, + withBuckyball: Boolean = true, + buckyballConfig: GlobalConfig = GlobalConfig(), + crossing: Option[RocketCrossingParams] = None, + nCoresPerTile: Int = 1, + buckyballPerCore: Option[Seq[Option[GlobalConfig]]] = None) extends Config((site, here, up) => { case TilesLocated(`location`) => - val prev = up(TilesLocated(`location`), site) - val idOffset = up(NumTiles) - val actualCrossing = crossing.getOrElse(WithNBBTiles.defaultCrossing(location)) - val tileParams = BBTileParams( + val prev = up(TilesLocated(`location`), site) + val idOffset = up(NumTiles) + val actualCrossing = crossing.getOrElse(WithNBBTiles.defaultCrossing(location)) + val resolvedBuckyballPerCore = buckyballPerCore.getOrElse( + Seq.fill(nCoresPerTile)(if (withBuckyball) Some(buckyballConfig) else None) + ) + require( + resolvedBuckyballPerCore.size == nCoresPerTile, + s"buckyballPerCore size (${resolvedBuckyballPerCore.size}) must equal nCoresPerTile ($nCoresPerTile)" + ) + val tileParams = BBTileParams( + nCores = nCoresPerTile, withBuckyball = withBuckyball, buckyballConfig = buckyballConfig, + buckyballPerCore = resolvedBuckyballPerCore, core = RocketCoreParams( mulDiv = Some(MulDivParams( mulUnroll = 8, diff --git a/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala index bb742f56..74d4a76f 100644 --- a/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala +++ b/arch/src/main/scala/framework/core/bbtile/RocketCoreBB.scala @@ -38,7 +38,7 @@ trait HasRocketCoreIOBB extends HasRocketCoreParameters { } -class RocketBB(tile: BBTile)(implicit p: Parameters) +class RocketBB(tile: BBTile, coreHasBuckyball: Boolean)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIOBB { @@ -47,7 +47,7 @@ class RocketBB(tile: BBTile)(implicit p: Parameters) // Override usingRoCC: BBTile doesn't use BuildRoCC/LazyRoCC, but when // withBuckyball is enabled the core must still treat custom instructions as // RoCC commands. - override val usingRoCC = tile.bbParams.withBuckyball + override val usingRoCC = coreHasBuckyball import ALU._ @@ -163,7 +163,7 @@ class RocketBB(tile: BBTile)(implicit p: Parameters) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen - val usingRVVRoCC = tile.bbParams.withBuckyball + val usingRVVRoCC = coreHasBuckyball // Ensure usingVector and usingRVVRoCC are mutually exclusive require( diff --git a/arch/src/main/scala/sims/verilator/TargetConfig.scala b/arch/src/main/scala/sims/verilator/TargetConfig.scala index f67860e5..f099c52d 100644 --- a/arch/src/main/scala/sims/verilator/TargetConfig.scala +++ b/arch/src/main/scala/sims/verilator/TargetConfig.scala @@ -30,6 +30,22 @@ class BuckyballGobanVerilatorConfig new examples.goban.BuckyballGobanConfig ) +class BuckyballKonbiVerilatorConfig + extends Config( + new BBSimConfig ++ + new WithDefaultMMIOPort ++ + new WithCustomBootROM ++ + new examples.konbi.BuckyballKonbiConfig + ) + +class BuckyballPolyVerilatorConfig + extends Config( + new BBSimConfig ++ + new WithDefaultMMIOPort ++ + new WithCustomBootROM ++ + new examples.poly.BuckyballPolyConfig + ) + object Elaborate extends App { if (args.isEmpty) { println("Usage: Elaborate [firtool-opts...]") diff --git a/bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c b/bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c index d8e66904..fa2cf8d2 100644 --- a/bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c +++ b/bb-tests/workloads/lib/bbhw/isa/02_gemmini_config.c @@ -6,8 +6,8 @@ #define BB_GEMMINI_CONFIG_FUNC7 2 // Configure Gemmini systolic array -// All config parameters go in rs2 (special), starting from bit 4 -// (bits [3:0] reserved for sub-command tag in decoder) +// All config parameters go in rs2 (special), starting from bit 4. +// rs2[3:0] is the sub-command field and remains 0 for this instruction. // dataflow: 0=OS, 1=WS // activation: 0=none, 1=relu // a_transpose, b_transpose: transpose flags diff --git a/bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c b/bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c index 0d19750a..7381621b 100644 --- a/bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c +++ b/bb-tests/workloads/lib/bbhw/isa/03_gemmini_flush.c @@ -4,9 +4,10 @@ #include "isa.h" #define BB_GEMMINI_FLUSH_FUNC7 3 +#define BB_GEMMINI_FLUSH_RS2 4ULL // Flush the systolic array state #define bb_gemmini_flush() \ - BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_GEMMINI_FLUSH_FUNC7) + BUCKYBALL_INSTRUCTION_R_R(0, BB_GEMMINI_FLUSH_RS2, BB_GEMMINI_FLUSH_FUNC7) #endif // _BB_GEMMINI_FLUSH_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c b/bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c index fc700fa1..0a3e079c 100644 --- a/bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c +++ b/bb-tests/workloads/lib/bbhw/isa/53_gemmini_preload.c @@ -4,6 +4,7 @@ #include "isa.h" #define BB_GEMMINI_PRELOAD_FUNC7 53 +#define BB_GEMMINI_PRELOAD_RS2 1ULL // Preload D/B matrix into systolic array // op1_bank_id: source bank for D (OS) or B (WS) @@ -11,7 +12,7 @@ // iter: number of rows to preload #define bb_gemmini_preload(op1_bank_id, wr_bank_id, iter) \ BUCKYBALL_INSTRUCTION_R_R( \ - (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), 0, \ - BB_GEMMINI_PRELOAD_FUNC7) + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ + BB_GEMMINI_PRELOAD_RS2, BB_GEMMINI_PRELOAD_FUNC7) #endif // _BB_GEMMINI_PRELOAD_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c b/bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c index 6bd6fa6a..e16d9384 100644 --- a/bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c +++ b/bb-tests/workloads/lib/bbhw/isa/66_gemmini_compute_preloaded.c @@ -4,6 +4,7 @@ #include "isa.h" #define BB_GEMMINI_COMPUTE_PRELOADED_FUNC7 66 +#define BB_GEMMINI_COMPUTE_PRELOADED_RS2 2ULL // Compute matmul using preloaded data: C = A * B + D(preloaded) // op1_bank_id: bank for A matrix @@ -14,6 +15,7 @@ iter) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ - 0, BB_GEMMINI_COMPUTE_PRELOADED_FUNC7) + BB_GEMMINI_COMPUTE_PRELOADED_RS2, \ + BB_GEMMINI_COMPUTE_PRELOADED_FUNC7) #endif // _BB_GEMMINI_COMPUTE_PRELOADED_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c b/bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c index 93239d52..d04bab42 100644 --- a/bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c +++ b/bb-tests/workloads/lib/bbhw/isa/67_gemmini_compute_accumulated.c @@ -4,6 +4,7 @@ #include "isa.h" #define BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7 67 +#define BB_GEMMINI_COMPUTE_ACCUMULATED_RS2 3ULL // Compute matmul reusing previously accumulated results // op1_bank_id: bank for A matrix @@ -14,6 +15,7 @@ iter) \ BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | \ BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ - 0, BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7) + BB_GEMMINI_COMPUTE_ACCUMULATED_RS2, \ + BB_GEMMINI_COMPUTE_ACCUMULATED_FUNC7) #endif // _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ diff --git a/scripts/nix/build-env-scala.nix b/scripts/nix/build-env-scala.nix index 62fedc03..fc940994 100644 --- a/scripts/nix/build-env-scala.nix +++ b/scripts/nix/build-env-scala.nix @@ -42,7 +42,7 @@ in name = "scalafmt"; runtimeInputs = [ pkgs.coursier ]; text = '' - exec coursier launch org.scalameta:scalafmt-cli_2.13:2.7.5 -- "$@" + exec cs launch org.scalameta:scalafmt-cli_2.13:2.7.5 -- "$@" ''; }; From 175567fdd437929c57e1ebab62f2364565a02ee5 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 23 Apr 2026 16:10:37 +0800 Subject: [PATCH 223/238] [bbdev] feat: bump to latest commit for sardine [arch/gemminiball] fix: modify rs2Data assignment logic --- .github/workflows/test.yml | 2 +- .../balldomain/prototype/gemmini/LoopCmdEncoder.scala | 8 ++++++-- bb-tests/CMakeLists.txt | 4 ---- bbdev | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 6bd192f4..988d1e0d 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -51,7 +51,7 @@ jobs: shell: zsh {0} run: | cd ~/Code/buckyball - # nix develop -c bbdev sardine --run '--workload ctest' + nix develop -c bbdev sardine --run '--workload ctest' --dir arch/log # if check failed, revert the branch # - name: Revert Bad Commit diff --git a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala index 96f21030..1381f7f1 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/gemmini/LoopCmdEncoder.scala @@ -95,7 +95,7 @@ class LoopCmdEncoder(val b: GlobalConfig) extends Module { slot.cmd.cmd.rs1Data := lsub.bits.op1_bank | (lsub.bits.wr_bank << 20) | (lsub.bits.iter << 30) - slot.cmd.cmd.rs2Data := 0.U + slot.cmd.cmd.rs2Data := 1.U slot.cmd.bankAccess.rd_bank_0_valid := true.B slot.cmd.bankAccess.rd_bank_0_id := lsub.bits.op1_bank slot.cmd.bankAccess.wr_bank_valid := true.B @@ -112,7 +112,11 @@ class LoopCmdEncoder(val b: GlobalConfig) extends Module { (lsub.bits.op2_bank << 10) | (lsub.bits.wr_bank << 20) | (lsub.bits.iter << 30) - slot.cmd.cmd.rs2Data := 0.U + slot.cmd.cmd.rs2Data := Mux( + lsub.bits.compute_mode === 0.U, + 2.U, + 3.U + ) slot.cmd.bankAccess.rd_bank_0_valid := true.B slot.cmd.bankAccess.rd_bank_0_id := lsub.bits.op1_bank slot.cmd.bankAccess.rd_bank_1_valid := true.B diff --git a/bb-tests/CMakeLists.txt b/bb-tests/CMakeLists.txt index dcdb68dd..df6afe5a 100644 --- a/bb-tests/CMakeLists.txt +++ b/bb-tests/CMakeLists.txt @@ -5,10 +5,6 @@ cmake_policy(SET CMP0003 NEW) set(CMAKE_EXPORT_COMPILE_COMMANDS ON) set(BB_TESTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}) -# set(CUSTOMEXT_DIR ${BB_TESTS_DIR}/customext) set(WORKLOADS_DIR ${BB_TESTS_DIR}/workloads) -# set(UVBB_DIR ${BB_TESTS_DIR}/uvbb) add_subdirectory(workloads) -# add_subdirectory(customext) -# add_subdirectory(uvbb) diff --git a/bbdev b/bbdev index b270a085..87f9f4f1 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit b270a08519a1b44604e48db6785e5148264501ae +Subproject commit 87f9f4f1598b2a8a890a26f00f17a662e107eeed From 6c364f61958a838c6d9c45ce2f82f8e14ca2faf0 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 25 Apr 2026 04:09:07 +0800 Subject: [PATCH 224/238] [arch/sim] feat: add DRAMSim2 memory management implementation --- arch/src/csrc/include/ioe/mm.h | 131 ++++++++ arch/src/csrc/include/ioe/mm_dramsim2.h | 92 ++++++ .../ioe/{SimDRAM_bb.cc => BBSimDRAM.cc} | 76 ++--- arch/src/csrc/src/monitor/ioe/mm.cc | 100 ++++++ arch/src/csrc/src/monitor/ioe/mm_dramsim2.cc | 142 +++++++++ arch/src/csrc/src/monitor/ioe/tsi_stub.cc | 12 - arch/src/csrc/src/monitor/monitor.cc | 2 +- .../scala/sims/verilator/BBSimHarness.scala | 21 +- .../main/scala/sims/verilator/BBsimDRAM.scala | 296 ++++++++++++++++++ bbdev | 2 +- 10 files changed, 813 insertions(+), 61 deletions(-) create mode 100644 arch/src/csrc/include/ioe/mm.h create mode 100644 arch/src/csrc/include/ioe/mm_dramsim2.h rename arch/src/csrc/src/monitor/ioe/{SimDRAM_bb.cc => BBSimDRAM.cc} (58%) create mode 100644 arch/src/csrc/src/monitor/ioe/mm.cc create mode 100644 arch/src/csrc/src/monitor/ioe/mm_dramsim2.cc delete mode 100644 arch/src/csrc/src/monitor/ioe/tsi_stub.cc create mode 100644 arch/src/main/scala/sims/verilator/BBsimDRAM.scala diff --git a/arch/src/csrc/include/ioe/mm.h b/arch/src/csrc/include/ioe/mm.h new file mode 100644 index 00000000..6d65d201 --- /dev/null +++ b/arch/src/csrc/include/ioe/mm.h @@ -0,0 +1,131 @@ +// See LICENSE for license details. + +#ifndef MM_EMULATOR_H +#define MM_EMULATOR_H + +#include +#include +#include +#include +#include + +struct backing_data_t { + uint8_t *data; + size_t size; +}; + +class mm_t { +public: + mm_t(size_t mem_bs, size_t mem_sz, size_t word_sz, size_t line_sz, + backing_data_t &dat) + : data(dat.data), mem_base(mem_bs), mem_size(mem_sz), word_size(word_sz), + line_size(line_sz) { + assert(dat.size == mem_sz); + } + + virtual bool ar_ready() = 0; + virtual bool aw_ready() = 0; + virtual bool w_ready() = 0; + virtual bool b_valid() = 0; + virtual uint64_t b_resp() = 0; + virtual uint64_t b_id() = 0; + virtual bool r_valid() = 0; + virtual uint64_t r_resp() = 0; + virtual uint64_t r_id() = 0; + virtual void *r_data() = 0; + virtual bool r_last() = 0; + + virtual void tick(bool reset, + + bool ar_valid, uint64_t ar_addr, uint64_t ar_id, + uint64_t ar_size, uint64_t ar_len, + + bool aw_valid, uint64_t aw_addr, uint64_t aw_id, + uint64_t aw_size, uint64_t aw_len, + + bool w_valid, uint64_t w_strb, void *w_data, bool w_last, + + bool r_ready, bool b_ready) = 0; + + virtual void *get_data() { return data; } + virtual size_t get_size() { return mem_size; } + virtual size_t get_base() { return mem_base; } + virtual size_t get_word_size() { return word_size; } + virtual size_t get_line_size() { return line_size; } + + void write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size); + std::vector read(uint64_t addr); + + virtual ~mm_t(); + uint8_t *data; + +protected: + size_t mem_base; + size_t mem_size; + int word_size; + int line_size; +}; + +struct mm_rresp_t { + uint64_t id; + std::vector data; + bool last; + + mm_rresp_t(uint64_t id, std::vector data, bool last) { + this->id = id; + this->data = data; + this->last = last; + } + + mm_rresp_t() { + this->id = 0; + this->last = false; + } +}; + +class mm_magic_t : public mm_t { +public: + mm_magic_t(size_t mem_base, size_t mem_sz, size_t word_sz, size_t line_sz, + backing_data_t &dat) + : mm_t(mem_base, mem_sz, word_sz, line_sz, dat), store_inflight(false) {} + + virtual bool ar_ready() { return true; } + virtual bool aw_ready() { return !store_inflight; } + virtual bool w_ready() { return store_inflight; } + virtual bool b_valid() { return !bresp.empty(); } + virtual uint64_t b_resp() { return 0; } + virtual uint64_t b_id() { return b_valid() ? bresp.front() : 0; } + virtual bool r_valid() { return !rresp.empty(); } + virtual uint64_t r_resp() { return 0; } + virtual uint64_t r_id() { return r_valid() ? rresp.front().id : 0; } + virtual void *r_data() { + return r_valid() ? &rresp.front().data[0] : (void *)data; + } + virtual bool r_last() { return r_valid() ? rresp.front().last : false; } + + virtual void tick(bool reset, + + bool ar_valid, uint64_t ar_addr, uint64_t ar_id, + uint64_t ar_size, uint64_t ar_len, + + bool aw_valid, uint64_t aw_addr, uint64_t aw_id, + uint64_t aw_size, uint64_t aw_len, + + bool w_valid, uint64_t w_strb, void *w_data, bool w_last, + + bool r_ready, bool b_ready); + +protected: + bool store_inflight; + uint64_t store_addr; + uint64_t store_id; + uint64_t store_size; + uint64_t store_count; + std::queue bresp; + + std::queue rresp; + + uint64_t cycle; +}; + +#endif diff --git a/arch/src/csrc/include/ioe/mm_dramsim2.h b/arch/src/csrc/include/ioe/mm_dramsim2.h new file mode 100644 index 00000000..375b9ae3 --- /dev/null +++ b/arch/src/csrc/include/ioe/mm_dramsim2.h @@ -0,0 +1,92 @@ +// See LICENSE for license details. + +#ifndef _MM_EMULATOR_DRAMSIM2_H +#define _MM_EMULATOR_DRAMSIM2_H + +#include "mm.h" +#include +#include +#include +#include +#include + +struct mm_req_t { + uint64_t id; + uint64_t size; + uint64_t len; + uint64_t addr; + + mm_req_t(uint64_t id, uint64_t size, uint64_t len, uint64_t addr) { + this->id = id; + this->size = size; + this->len = len; + this->addr = addr; + } + + mm_req_t() { + this->id = 0; + this->size = 0; + this->len = 0; + this->addr = 0; + } +}; + +class mm_dramsim2_t : public mm_t { +public: + mm_dramsim2_t(size_t mem_base, size_t mem_sz, size_t word_sz, size_t line_sz, + backing_data_t &dat, std::string memory_ini, + std::string system_ini, std::string ini_dir, int axi4_ids, + size_t clock_hz); + + virtual bool ar_ready(); + virtual bool aw_ready(); + virtual bool w_ready() { return store_inflight; } + virtual bool b_valid() { return !bresp.empty(); } + virtual uint64_t b_resp() { return 0; } + virtual uint64_t b_id() { return b_valid() ? bresp.front() : 0; } + virtual bool r_valid() { return !rresp.empty(); } + virtual uint64_t r_resp() { return 0; } + virtual uint64_t r_id() { return r_valid() ? rresp.front().id : 0; } + virtual void *r_data() { + return r_valid() ? (void *)&rresp.front().data[0] : data; + } + virtual bool r_last() { return r_valid() ? rresp.front().last : false; } + + virtual void tick(bool reset, + + bool ar_valid, uint64_t ar_addr, uint64_t ar_id, + uint64_t ar_size, uint64_t ar_len, + + bool aw_valid, uint64_t aw_addr, uint64_t aw_id, + uint64_t aw_size, uint64_t aw_len, + + bool w_valid, uint64_t w_strb, void *w_data, bool w_last, + + bool r_ready, bool b_ready); + +protected: + DRAMSim::MultiChannelMemorySystem *mem; + uint64_t cycle; + + bool store_inflight = false; + uint64_t store_addr; + uint64_t store_id; + uint64_t store_size; + uint64_t store_count; + std::queue bresp; + + std::map> wreq; + std::map> rreq; + std::queue rresp; + + std::vector read_id_busy; + std::vector write_id_busy; + std::list rreq_queue; + + uint64_t clock_hz = 0; + + void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle); + void write_complete(unsigned id, uint64_t address, uint64_t clock_cycle); +}; + +#endif diff --git a/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc b/arch/src/csrc/src/monitor/ioe/BBSimDRAM.cc similarity index 58% rename from arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc rename to arch/src/csrc/src/monitor/ioe/BBSimDRAM.cc index 70959f2a..d254c3b2 100644 --- a/arch/src/csrc/src/monitor/ioe/SimDRAM_bb.cc +++ b/arch/src/csrc/src/monitor/ioe/BBSimDRAM.cc @@ -1,7 +1,4 @@ -// SimDRAM_bb.cc — Override memory_init from testchipip's SimDRAM.cc -// Replaces fesvr load_elf with libelf-based ELF loader. -// This file is compiled into the simulation and takes precedence over -// the version embedded in the SimDRAM Verilog blackbox resource. +// BBSim-owned DPI memory backend for BBSimDRAM.v. #include #include @@ -20,46 +17,42 @@ #include #include -#include "mm_dramsim2.h" - -// Global state — defined here since testchipip's SimDRAM.cc is excluded from -// build. -bool use_dramsim = false; -std::string ini_dir = "dramsim2_ini"; -std::vector> backing_mem_data = {}; +#include "ioe/mm_dramsim2.h" +static bool use_dramsim = false; +static std::vector> mem_data = {}; static std::string elf_file = ""; -// --------------------------------------------------------------------------- -// load_elf_to_mem: parse ELF64 and copy PT_LOAD segments into backing data -// --------------------------------------------------------------------------- static void load_elf_to_mem(const char *path, uint8_t *data, uint64_t mem_base, uint64_t mem_size) { int fd = open(path, O_RDONLY); if (fd < 0) { - fprintf(stderr, "[SimDRAM_bb] Cannot open ELF: %s\n", path); + fprintf(stderr, "[BBSimDRAM] Cannot open ELF: %s\n", path); abort(); } struct stat st; - fstat(fd, &st); - size_t file_size = st.st_size; + if (fstat(fd, &st) != 0) { + fprintf(stderr, "[BBSimDRAM] fstat failed for ELF: %s\n", path); + abort(); + } + size_t file_size = st.st_size; uint8_t *file_buf = (uint8_t *)mmap(NULL, file_size, PROT_READ, MAP_PRIVATE, fd, 0); close(fd); if (file_buf == MAP_FAILED) { - fprintf(stderr, "[SimDRAM_bb] mmap failed for ELF: %s\n", path); + fprintf(stderr, "[BBSimDRAM] mmap failed for ELF: %s\n", path); abort(); } Elf64_Ehdr *ehdr = (Elf64_Ehdr *)file_buf; if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG) != 0) { - fprintf(stderr, "[SimDRAM_bb] Not a valid ELF file: %s\n", path); + fprintf(stderr, "[BBSimDRAM] Not a valid ELF file: %s\n", path); abort(); } if (ehdr->e_ident[EI_CLASS] != ELFCLASS64) { - fprintf(stderr, "[SimDRAM_bb] Only ELF64 supported\n"); + fprintf(stderr, "[BBSimDRAM] Only ELF64 supported\n"); abort(); } @@ -75,11 +68,12 @@ static void load_elf_to_mem(const char *path, uint8_t *data, uint64_t mem_base, uint64_t vaddr = ph->p_paddr; if (vaddr < mem_base || vaddr + ph->p_memsz > mem_base + mem_size) { fprintf(stderr, - "[SimDRAM_bb] Segment paddr=0x%lx size=0x%lx outside mem [0x%lx, " + "[BBSimDRAM] Segment paddr=0x%lx size=0x%lx outside mem [0x%lx, " "0x%lx)\n", vaddr, ph->p_memsz, mem_base, mem_base + mem_size); abort(); } + uint64_t offset = vaddr - mem_base; memcpy(data + offset, file_buf + ph->p_offset, ph->p_filesz); if (ph->p_memsz > ph->p_filesz) @@ -88,16 +82,13 @@ static void load_elf_to_mem(const char *path, uint8_t *data, uint64_t mem_base, } munmap(file_buf, file_size); - printf("[SimDRAM_bb] Loaded ELF '%s': %zu bytes\n", path, loaded); + printf("[BBSimDRAM] Loaded ELF '%s': %zu bytes\n", path, loaded); } -// --------------------------------------------------------------------------- -// memory_init — DPI-C from SimDRAM.v, called once at simulation start -// --------------------------------------------------------------------------- -extern "C" void *memory_init(int chip_id, long long int mem_size, - long long int word_size, long long int line_size, - long long int id_bits, long long int clock_hz, - long long int mem_base) { +extern "C" void * +bbsim_memory_init(int chip_id, long long int mem_size, long long int word_size, + long long int line_size, long long int id_bits, + long long int clock_hz, long long int mem_base) { mm_t *mm; s_vpi_vlog_info info; @@ -118,17 +109,16 @@ extern "C" void *memory_init(int chip_id, long long int mem_size, local_ini_dir = arg.substr(strlen("+dramsim_ini_dir=")); } - while (chip_id >= (int)backing_mem_data.size()) - backing_mem_data.push_back(std::map()); + while (chip_id >= (int)mem_data.size()) + mem_data.push_back(std::map()); - if (backing_mem_data[chip_id].find(mem_base) != - backing_mem_data[chip_id].end()) { - assert(backing_mem_data[chip_id][mem_base].size == (size_t)mem_size); + if (mem_data[chip_id].find(mem_base) != mem_data[chip_id].end()) { + assert(mem_data[chip_id][mem_base].size == (size_t)mem_size); } else { uint8_t *data = (uint8_t *)mmap(NULL, mem_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_ANONYMOUS, -1, 0); if (data == MAP_FAILED) { - fprintf(stderr, "[SimDRAM_bb] mmap for backing store failed\n"); + fprintf(stderr, "[BBSimDRAM] mmap for backing store failed\n"); abort(); } memset(data, 0, mem_size); @@ -137,26 +127,22 @@ extern "C" void *memory_init(int chip_id, long long int mem_size, load_elf_to_mem(elf_file.c_str(), data, (uint64_t)mem_base, (uint64_t)mem_size); - backing_mem_data[chip_id][mem_base] = {data, (size_t)mem_size}; + mem_data[chip_id][mem_base] = {data, (size_t)mem_size}; } if (use_dramsim) { - mm = (mm_t *)(new mm_dramsim2_t(mem_base, mem_size, word_size, line_size, - backing_mem_data[chip_id][mem_base], - memory_ini, system_ini, local_ini_dir, - 1 << id_bits, clock_hz)); + mm = (mm_t *)(new mm_dramsim2_t( + mem_base, mem_size, word_size, line_size, mem_data[chip_id][mem_base], + memory_ini, system_ini, local_ini_dir, 1 << id_bits, clock_hz)); } else { mm = (mm_t *)(new mm_magic_t(mem_base, mem_size, word_size, line_size, - backing_mem_data[chip_id][mem_base])); + mem_data[chip_id][mem_base])); } return mm; } -// --------------------------------------------------------------------------- -// memory_tick — DPI-C from SimDRAM.v / SimAXIMem.v, called each cycle -// --------------------------------------------------------------------------- -extern "C" void memory_tick( +extern "C" void bbsim_memory_tick( void *channel, unsigned char reset, unsigned char ar_valid, unsigned char *ar_ready, long long int ar_addr, int ar_id, int ar_size, int ar_len, unsigned char aw_valid, unsigned char *aw_ready, diff --git a/arch/src/csrc/src/monitor/ioe/mm.cc b/arch/src/csrc/src/monitor/ioe/mm.cc new file mode 100644 index 00000000..f6b33df1 --- /dev/null +++ b/arch/src/csrc/src/monitor/ioe/mm.cc @@ -0,0 +1,100 @@ +// See LICENSE for license details. + +#include "ioe/mm.h" +#include +#include +#include +#include +#include +#include +#include +#include + +void mm_t::write(uint64_t faddr, uint8_t *data, uint64_t strb, uint64_t size) { + uint64_t addr = faddr - this->mem_base; + assert(addr < this->mem_size); + auto max_strb_bytes = sizeof(uint64_t) * 8; + assert(size <= max_strb_bytes); // Ensure the strb is wide enough to support + // the desired transaction + if (size != max_strb_bytes) { + strb &= ((1 << size) - 1) << (addr % word_size); + } + + uint8_t *base = this->data + (addr / word_size) * word_size; + for (int i = 0; i < word_size; i++) { + if (strb & 1) + base[i] = data[i]; + strb >>= 1; + } +} + +std::vector mm_t::read(uint64_t faddr) { + uint64_t addr = faddr - this->mem_base; + assert(addr < this->mem_size); + uint8_t *base = this->data + addr; + return std::vector(base, base + word_size); +} + +mm_t::~mm_t() { munmap(data, this->mem_size); } + +void mm_magic_t::tick(bool reset, + + bool ar_valid, uint64_t ar_addr, uint64_t ar_id, + uint64_t ar_size, uint64_t ar_len, + + bool aw_valid, uint64_t aw_addr, uint64_t aw_id, + uint64_t aw_size, uint64_t aw_len, + + bool w_valid, uint64_t w_strb, void *w_data, bool w_last, + + bool r_ready, bool b_ready) { + bool ar_fire = !reset && ar_valid && ar_ready(); + bool aw_fire = !reset && aw_valid && aw_ready(); + bool w_fire = !reset && w_valid && w_ready(); + bool r_fire = !reset && r_valid() && r_ready; + bool b_fire = !reset && b_valid() && b_ready; + + if (ar_fire) { + uint64_t start_addr = (ar_addr / word_size) * word_size; + for (int i = 0; i <= ar_len; i++) { + auto dat = read(start_addr + i * word_size); + rresp.push(mm_rresp_t(ar_id, dat, i == ar_len)); + } + } + + if (aw_fire) { + store_addr = aw_addr; + store_id = aw_id; + store_count = aw_len + 1; + store_size = 1 << aw_size; + store_inflight = true; + } + + if (w_fire) { + write(store_addr, (uint8_t *)w_data, w_strb, store_size); + store_addr += store_size; + store_count--; + + if (store_count == 0) { + store_inflight = false; + bresp.push(store_id); + assert(w_last); + } + } + + if (b_fire) + bresp.pop(); + + if (r_fire) + rresp.pop(); + + cycle++; + + if (reset) { + while (!bresp.empty()) + bresp.pop(); + while (!rresp.empty()) + rresp.pop(); + cycle = 0; + } +} diff --git a/arch/src/csrc/src/monitor/ioe/mm_dramsim2.cc b/arch/src/csrc/src/monitor/ioe/mm_dramsim2.cc new file mode 100644 index 00000000..3dc699e0 --- /dev/null +++ b/arch/src/csrc/src/monitor/ioe/mm_dramsim2.cc @@ -0,0 +1,142 @@ +// See LICENSE for license details. + +#include "ioe/mm_dramsim2.h" +#include "ioe/mm.h" +#include +#include +#include +#include +#include +#include +#include + +// #define DEBUG_DRAMSIM2 + +using namespace DRAMSim; + +void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, + uint64_t clock_cycle) { + assert(!rreq[address].empty()); + auto req = rreq[address].front(); + uint64_t start_addr = (req.addr / word_size) * word_size; + for (size_t i = 0; i < req.len; i++) { + auto dat = read(start_addr + i * word_size); + rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1))); + } + read_id_busy[req.id] = false; + rreq[address].pop(); +} + +void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, + uint64_t clock_cycle) { + assert(!wreq[address].empty()); + auto b_id = wreq[address].front(); + bresp.push(b_id); + write_id_busy[b_id] = false; + wreq[address].pop(); +} + +void power_callback(double a, double b, double c, double d) { + // fprintf(stderr, "power callback: %0.3f, %0.3f, %0.3f, %0.3f\n",a,b,c,d); +} + +mm_dramsim2_t::mm_dramsim2_t(size_t mem_base, size_t mem_sz, size_t word_sz, + size_t line_sz, backing_data_t &dat, + std::string memory_ini, std::string system_ini, + std::string ini_dir, int axi4_ids, size_t clock_hz) + : mm_t(mem_base, mem_sz, word_sz, line_sz, dat), + read_id_busy(axi4_ids, false), write_id_busy(axi4_ids, false) { + + assert(line_sz == 64); // assumed by dramsim2 + assert(mem_sz % (1024 * 1024) == 0); + mem = getMemorySystemInstance(memory_ini, system_ini, ini_dir, "results", + mem_size / (1024 * 1024)); + mem->setCPUClockSpeed(clock_hz); + TransactionCompleteCB *read_cb = + new Callback( + this, &mm_dramsim2_t::read_complete); + TransactionCompleteCB *write_cb = + new Callback( + this, &mm_dramsim2_t::write_complete); + mem->RegisterCallbacks(read_cb, write_cb, power_callback); +}; + +bool mm_dramsim2_t::ar_ready() { return mem->willAcceptTransaction(); } + +bool mm_dramsim2_t::aw_ready() { + return mem->willAcceptTransaction() && !store_inflight; +} + +void mm_dramsim2_t::tick(bool reset, + + bool ar_valid, uint64_t ar_addr, uint64_t ar_id, + uint64_t ar_size, uint64_t ar_len, + + bool aw_valid, uint64_t aw_addr, uint64_t aw_id, + uint64_t aw_size, uint64_t aw_len, + + bool w_valid, uint64_t w_strb, void *w_data, + bool w_last, + + bool r_ready, bool b_ready) { + bool ar_fire = !reset && ar_valid && ar_ready(); + bool aw_fire = !reset && aw_valid && aw_ready(); + bool w_fire = !reset && w_valid && w_ready(); + bool r_fire = !reset && r_valid() && r_ready; + bool b_fire = !reset && b_valid() && b_ready; + + if (mem->willAcceptTransaction()) { + for (auto it = rreq_queue.begin(); it != rreq_queue.end(); it++) { + if (!read_id_busy[it->id]) { + read_id_busy[it->id] = true; + auto transaction = *it; + rreq[transaction.addr].push(transaction); + mem->addTransaction(false, transaction.addr); + rreq_queue.erase(it); + break; + } + } + } + + if (ar_fire) { + rreq_queue.push_back(mm_req_t(ar_id, 1 << ar_size, ar_len + 1, ar_addr)); + } + + if (aw_fire) { + store_addr = aw_addr; + store_id = aw_id; + store_count = aw_len + 1; + store_size = 1 << aw_size; + store_inflight = true; + } + + if (w_fire) { + write(store_addr, (uint8_t *)w_data, w_strb, store_size); + store_addr += store_size; + store_count--; + + if (store_count == 0) { + store_inflight = false; + mem->addTransaction(true, store_addr); + wreq[store_addr].push(store_id); + assert(w_last); + } + } + + if (b_fire) + bresp.pop(); + + if (r_fire) + rresp.pop(); + + mem->update(); + cycle++; + + if (reset) { + while (!bresp.empty()) + bresp.pop(); + while (!rresp.empty()) + rresp.pop(); + cycle = 0; + } +} diff --git a/arch/src/csrc/src/monitor/ioe/tsi_stub.cc b/arch/src/csrc/src/monitor/ioe/tsi_stub.cc deleted file mode 100644 index 36647b0f..00000000 --- a/arch/src/csrc/src/monitor/ioe/tsi_stub.cc +++ /dev/null @@ -1,12 +0,0 @@ -// tsi_stub.cc — stub for SimTSI DPI-C symbol. -// SimTSI is instantiated by chipyard's AbstractConfig via -// WithSimTSIOverSerialTL, but we don't use TSI. This stub satisfies the linker -// without pulling in fesvr. -extern "C" int tsi_tick(int chip_id, unsigned char out_valid, - unsigned char *out_ready, int out_bits, - unsigned char *in_valid, unsigned char in_ready, - int *in_bits) { - *out_ready = 0; - *in_valid = 0; - return 0; -} diff --git a/arch/src/csrc/src/monitor/monitor.cc b/arch/src/csrc/src/monitor/monitor.cc index cd3bc981..4e26af87 100644 --- a/arch/src/csrc/src/monitor/monitor.cc +++ b/arch/src/csrc/src/monitor/monitor.cc @@ -89,7 +89,7 @@ static int parse_args(int argc, char *argv[]) { printf("\n"); exit(0); } - // +elf= is parsed by SimDRAM_bb.cc via vpi_get_vlog_info (Verilator + // +elf= is parsed by BBSimDRAM.cc via vpi_get_vlog_info (Verilator // plusargs) } diff --git a/arch/src/main/scala/sims/verilator/BBSimHarness.scala b/arch/src/main/scala/sims/verilator/BBSimHarness.scala index dd7a5bde..76066583 100644 --- a/arch/src/main/scala/sims/verilator/BBSimHarness.scala +++ b/arch/src/main/scala/sims/verilator/BBSimHarness.scala @@ -6,7 +6,24 @@ import chisel3.util._ import org.chipsalliance.cde.config.{Config, Parameters} import chipyard.harness.{HarnessBinder, HasHarnessInstantiators} -import chipyard.iobinders.{AXI4MMIOPort, UARTPort} +import chipyard.iobinders.{AXI4MMIOPort, AXI4MemPort, UARTPort} + +class WithBBSimMem + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => { + val memSize = port.params.master.size + val memBase = port.params.master.base + val lineSize = 64 + val clockFreq = port.clockFreqMHz + val mem = Module( + new BBSimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle, chipId) + ).suggestName("bbsimdram") + + mem.io.clock := port.io.clock + mem.io.reset := th.harnessBinderReset.asAsyncReset + mem.io.axi <> port.io.bits + } + }) // ============================================================================= // WithBBSimMMIO: wire AXI4 MMIO port to C++ mmio_tick(). @@ -98,7 +115,7 @@ class BBSimConfig new WithNoUARTAdapter ++ new WithBBSimMMIO ++ new chipyard.config.WithUniformBusFrequencies(1000.0) ++ - new chipyard.harness.WithBlackBoxSimMem ++ + new WithBBSimMem ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithTieOffInterrupts ++ new chipyard.harness.WithGPIOTiedOff ++ diff --git a/arch/src/main/scala/sims/verilator/BBsimDRAM.scala b/arch/src/main/scala/sims/verilator/BBsimDRAM.scala new file mode 100644 index 00000000..ba4813a6 --- /dev/null +++ b/arch/src/main/scala/sims/verilator/BBsimDRAM.scala @@ -0,0 +1,296 @@ +package sims.verilator + +import chisel3._ +import chisel3.experimental.IntParam +import chisel3.util.HasBlackBoxInline +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4BundleParameters} + +class BBSimDRAM( + memSize: BigInt, + lineSize: Int, + clockFreqHz: BigInt, + memBase: BigInt, + params: AXI4BundleParameters, + chipId: Int) + extends BlackBox( + Map( + "MEM_SIZE" -> IntParam(memSize), + "LINE_SIZE" -> IntParam(lineSize), + "ADDR_BITS" -> IntParam(params.addrBits), + "DATA_BITS" -> IntParam(params.dataBits), + "ID_BITS" -> IntParam(params.idBits), + "CLOCK_HZ" -> IntParam(clockFreqHz), + "MEM_BASE" -> IntParam(memBase), + "CHIP_ID" -> IntParam(chipId) + ) + ) + with HasBlackBoxInline { + + val io = IO(new Bundle { + val clock = Input(Clock()) + val reset = Input(Reset()) + val axi = Flipped(new AXI4Bundle(params)) + }) + + require(params.dataBits <= 64) + + setInline( + "BBSimDRAM.v", + """ + |import "DPI-C" function chandle bbsim_memory_init + |( + | input int chip_id, + | input longint mem_size, + | input longint word_size, + | input longint line_size, + | input longint id_bits, + | input longint clock_hz, + | input longint mem_base + |); + | + |import "DPI-C" function void bbsim_memory_tick + |( + | input chandle channel, + | + | input bit reset, + | + | input bit ar_valid, + | output bit ar_ready, + | input longint ar_addr, + | input int ar_id, + | input int ar_size, + | input int ar_len, + | + | input bit aw_valid, + | output bit aw_ready, + | input longint aw_addr, + | input int aw_id, + | input int aw_size, + | input int aw_len, + | + | input bit w_valid, + | output bit w_ready, + | input int w_strb, + | input longint w_data, + | input bit w_last, + | + | output bit r_valid, + | input bit r_ready, + | output int r_id, + | output int r_resp, + | output longint r_data, + | output bit r_last, + | + | output bit b_valid, + | input bit b_ready, + | output int b_id, + | output int b_resp + |); + | + |module BBSimDRAM #( + | parameter ADDR_BITS=32, DATA_BITS = 64, ID_BITS = 5, + | MEM_SIZE = 1000 * 1000 * 1000, + | LINE_SIZE = 64, + | WORD_SIZE = DATA_BITS/8, + | CLOCK_HZ = 100000, + | STRB_BITS = DATA_BITS/8, + | MEM_BASE = 0, + | CHIP_ID = 0)( + | input clock, + | input reset, + | output axi_aw_ready, + | input axi_aw_valid, + | input [ADDR_BITS-1:0] axi_aw_bits_addr, + | input [7:0] axi_aw_bits_len, + | input [2:0] axi_aw_bits_size, + | input [1:0] axi_aw_bits_burst, + | input axi_aw_bits_lock, + | input [3:0] axi_aw_bits_cache, + | input [2:0] axi_aw_bits_prot, + | input [3:0] axi_aw_bits_qos, + | input [ID_BITS-1:0] axi_aw_bits_id, + | output axi_w_ready, + | input axi_w_valid, + | input [DATA_BITS-1:0] axi_w_bits_data, + | input axi_w_bits_last, + | input [STRB_BITS-1:0] axi_w_bits_strb, + | input axi_b_ready, + | output axi_b_valid, + | output [1:0] axi_b_bits_resp, + | output [ID_BITS-1:0] axi_b_bits_id, + | output axi_ar_ready, + | input axi_ar_valid, + | input [ADDR_BITS-1:0] axi_ar_bits_addr, + | input [7:0] axi_ar_bits_len, + | input [2:0] axi_ar_bits_size, + | input [1:0] axi_ar_bits_burst, + | input axi_ar_bits_lock, + | input [3:0] axi_ar_bits_cache, + | input [2:0] axi_ar_bits_prot, + | input [3:0] axi_ar_bits_qos, + | input [ID_BITS-1:0] axi_ar_bits_id, + | input axi_r_ready, + | output axi_r_valid, + | output [1:0] axi_r_bits_resp, + | output [DATA_BITS-1:0] axi_r_bits_data, + | output axi_r_bits_last, + | output [ID_BITS-1:0] axi_r_bits_id + |); + | + | reg initialized = 1'b0; + | chandle channel; + | + | wire __ar_valid; + | wire [63:0] __ar_addr; + | wire [31:0] __ar_id; + | wire [31:0] __ar_size; + | wire [31:0] __ar_len; + | + | wire __aw_valid; + | wire [63:0] __aw_addr; + | wire [31:0] __aw_id; + | wire [31:0] __aw_size; + | wire [31:0] __aw_len; + | + | wire __w_valid; + | wire [31:0] __w_strb; + | wire [63:0] __w_data; + | wire __w_last; + | + | wire __r_ready; + | wire __b_ready; + | + | bit __ar_ready; + | bit __aw_ready; + | bit __w_ready; + | bit __r_valid; + | int __r_id; + | int __r_resp; + | longint __r_data; + | bit __r_last; + | bit __b_valid; + | int __b_id; + | int __b_resp; + | + | reg __ar_ready_reg; + | reg __aw_ready_reg; + | reg __w_ready_reg; + | reg __r_valid_reg; + | reg [ID_BITS-1:0] __r_id_reg; + | reg [1:0] __r_resp_reg; + | reg [DATA_BITS-1:0] __r_data_reg; + | reg __r_last_reg; + | reg __b_valid_reg; + | reg [ID_BITS-1:0] __b_id_reg; + | reg [1:0] __b_resp_reg; + | + | always @(posedge clock) begin + | if (reset) begin + | __ar_ready = 1'b0; + | __aw_ready = 1'b0; + | __w_ready = 1'b0; + | __r_valid = 1'b0; + | __b_valid = 1'b0; + | + | __ar_ready_reg <= 1'b0; + | __aw_ready_reg <= 1'b0; + | __w_ready_reg <= 1'b0; + | __r_valid_reg <= 1'b0; + | __b_valid_reg <= 1'b0; + | end else begin + | if (!initialized) begin + | channel = bbsim_memory_init(CHIP_ID, MEM_SIZE, WORD_SIZE, LINE_SIZE, ID_BITS, CLOCK_HZ, MEM_BASE); + | initialized = 1'b1; + | end + | + | bbsim_memory_tick( + | channel, + | + | reset, + | + | __ar_valid, + | __ar_ready, + | __ar_addr, + | __ar_id, + | __ar_size, + | __ar_len, + | + | __aw_valid, + | __aw_ready, + | __aw_addr, + | __aw_id, + | __aw_size, + | __aw_len, + | + | __w_valid, + | __w_ready, + | __w_strb, + | __w_data, + | __w_last, + | + | __r_valid, + | __r_ready, + | __r_id, + | __r_resp, + | __r_data, + | __r_last, + | + | __b_valid, + | __b_ready, + | __b_id, + | __b_resp); + | + | __ar_ready_reg <= __ar_ready; + | __aw_ready_reg <= __aw_ready; + | __w_ready_reg <= __w_ready; + | + | __r_valid_reg <= __r_valid; + | __r_id_reg <= __r_id[ID_BITS-1:0]; + | __r_resp_reg <= __r_resp[1:0]; + | __r_data_reg <= __r_data; + | __r_last_reg <= __r_last; + | + | __b_valid_reg <= __b_valid; + | __b_id_reg <= __b_id[ID_BITS-1:0]; + | __b_resp_reg <= __b_resp[1:0]; + | end + | end + | + | /* verilator lint_off WIDTH */ + | + | assign __ar_valid = axi_ar_valid; + | assign __ar_addr = axi_ar_bits_addr; + | assign __ar_id = axi_ar_bits_id; + | assign __ar_size = axi_ar_bits_size; + | assign __ar_len = axi_ar_bits_len; + | + | assign __aw_valid = axi_aw_valid; + | assign __aw_addr = axi_aw_bits_addr; + | assign __aw_id = axi_aw_bits_id; + | assign __aw_size = axi_aw_bits_size; + | assign __aw_len = axi_aw_bits_len; + | + | assign __w_valid = axi_w_valid; + | assign __w_strb = axi_w_bits_strb; + | assign __w_data = axi_w_bits_data; + | assign __w_last = axi_w_bits_last; + | + | assign __r_ready = axi_r_ready; + | assign __b_ready = axi_b_ready; + | + | assign axi_ar_ready = __ar_ready_reg; + | assign axi_aw_ready = __aw_ready_reg; + | assign axi_w_ready = __w_ready_reg; + | assign axi_r_valid = __r_valid_reg; + | assign axi_r_bits_id = __r_id_reg; + | assign axi_r_bits_resp = __r_resp_reg; + | assign axi_r_bits_data = __r_data_reg; + | assign axi_r_bits_last = __r_last_reg; + | assign axi_b_valid = __b_valid_reg; + | assign axi_b_bits_id = __b_id_reg; + | assign axi_b_bits_resp = __b_resp_reg; + | + |endmodule + """.stripMargin + ) +} diff --git a/bbdev b/bbdev index 87f9f4f1..7ada295e 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 87f9f4f1598b2a8a890a26f00f17a662e107eeed +Subproject commit 7ada295e54b44443222fd79dbe30c1518c34f009 From a1e9b91bf2fec8d60b2f988e8a914286d456c052 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 27 Apr 2026 15:11:22 +0800 Subject: [PATCH 225/238] [compiler] refactor: migrate to buddy-mlir submodule and update sourceme.sh path --- bbdev | 2 +- compiler | 1 - compiler/thirdparty/buddy-mlir | 1 + scripts/nix/build-all.sh | 67 ++++++++++++++++------------------ sourceme.sh | 9 +++-- 5 files changed, 39 insertions(+), 41 deletions(-) delete mode 160000 compiler create mode 160000 compiler/thirdparty/buddy-mlir diff --git a/bbdev b/bbdev index 7ada295e..df84247c 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 7ada295e54b44443222fd79dbe30c1518c34f009 +Subproject commit df84247ce206d0591740bec7db5d898ecab3b0dd diff --git a/compiler b/compiler deleted file mode 160000 index d5e80948..00000000 --- a/compiler +++ /dev/null @@ -1 +0,0 @@ -Subproject commit d5e809481d7ff2a5009101d5135df99e851a4f69 diff --git a/compiler/thirdparty/buddy-mlir b/compiler/thirdparty/buddy-mlir new file mode 160000 index 00000000..ce66e6f3 --- /dev/null +++ b/compiler/thirdparty/buddy-mlir @@ -0,0 +1 @@ +Subproject commit ce66e6f397171d4fad298cac093c939478634661 diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 946129f4..0a2cf8bc 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -30,9 +30,9 @@ SKIP_LIST=() VERBOSE_FLAG="" INSTALL_IN_NIX=0 -while [ "$#" -gt 0 ]; +while [ "$1" != "" ]; do - case "$1" in + case $1 in -h | --help ) usage 3 ;; --verbose | -v) @@ -40,11 +40,7 @@ do set -x ;; --skip | -s) shift - if [ "$#" -eq 0 ]; then - echo "Error: --skip requires a step number" >&2 - usage 1 - fi - SKIP_LIST+=("$1") ;; + SKIP_LIST+=(${1}) ;; --install-in-nix) INSTALL_IN_NIX=1 ;; * ) @@ -78,13 +74,14 @@ function begin_step } begin_step "0-1" "submodules init" - -git -C ${BBDIR} submodule update --init --progress --jobs 8 \ +# git submodule update --init --progress --jobs 8 +cd ${BBDIR} +git submodule update --init --progress --jobs 8 \ arch/thirdparty/chipyard \ bb-tests/workloads/lib/kernel \ bbdev \ bebop \ - compiler \ + compiler/thirdparty/buddy-mlir \ docs \ thirdparty/pegasus \ thirdparty/waveform-mcp @@ -118,31 +115,31 @@ fi if run_step "2"; then begin_step "2" "Compiler installation" - cd ${BBDIR}/compiler - git submodule update --init --progress llvm - - mkdir -p llvm/build && cd llvm/build - cmake -G Ninja ../llvm \ - -DLLVM_ENABLE_PROJECTS="mlir;clang" \ - -DLLVM_TARGETS_TO_BUILD="host;RISCV" \ - -DLLVM_ENABLE_ASSERTIONS=ON \ - -DCMAKE_BUILD_TYPE=RELEASE \ - -DMLIR_ENABLE_BINDINGS_PYTHON=ON \ - -DPython3_EXECUTABLE=$(which python3) - ninja #check-mlir check-clang - - cd ${BBDIR}/compiler - mkdir -p build && cd build - cmake -G Ninja .. \ - -DMLIR_DIR=$PWD/../llvm/build/lib/cmake/mlir \ - -DLLVM_DIR=$PWD/../llvm/build/lib/cmake/llvm \ - -DLLVM_ENABLE_ASSERTIONS=ON \ - -DCMAKE_BUILD_TYPE=RELEASE \ - -DBUDDY_MLIR_ENABLE_PYTHON_PACKAGES=ON \ - -DPython3_EXECUTABLE=$(which python3) \ - -DPython_EXECUTABLE=$(which python3) \ - -DCMAKE_EXPORT_COMPILE_COMMANDS=ON - ninja # check-buddy + cd ${BBDIR}/compiler/thirdparty/buddy-mlir + git submodule update --init llvm + + mkdir -p llvm/build && cd llvm/build + cmake -G Ninja ../llvm \ + -DLLVM_ENABLE_PROJECTS="mlir;clang" \ + -DLLVM_TARGETS_TO_BUILD="host;RISCV" \ + -DLLVM_ENABLE_ASSERTIONS=ON \ + -DCMAKE_BUILD_TYPE=RELEASE \ + -DMLIR_ENABLE_BINDINGS_PYTHON=ON \ + -DPython3_EXECUTABLE=$(which python3) + ninja #check-mlir check-clang + + cd ${BBDIR}/compiler/thirdparty/buddy-mlir + mkdir -p build && cd build + cmake -G Ninja .. \ + -DMLIR_DIR=$PWD/../llvm/build/lib/cmake/mlir \ + -DLLVM_DIR=$PWD/../llvm/build/lib/cmake/llvm \ + -DLLVM_ENABLE_ASSERTIONS=ON \ + -DCMAKE_BUILD_TYPE=RELEASE \ + -DBUDDY_MLIR_ENABLE_PYTHON_PACKAGES=ON \ + -DPython3_EXECUTABLE=$(which python3) \ + -DPython_EXECUTABLE=$(which python3) \ + -DCMAKE_EXPORT_COMPILE_COMMANDS=ON + ninja # check-buddy fi if run_step "3"; then diff --git a/sourceme.sh b/sourceme.sh index c197c3bf..6aae6ef2 100644 --- a/sourceme.sh +++ b/sourceme.sh @@ -19,11 +19,12 @@ RESULT_PATH="${BBDIR}/result" #===----------------------------------------------------------------------------=== # Source Environment Variables #===----------------------------------------------------------------------------=== -export BUDDY_MLIR_BUILD_DIR="${BBDIR}/compiler/build" -export LLVM_MLIR_BUILD_DIR="${BBDIR}/compiler/llvm/build" -export PYTHONPATH="${BBDIR}/compiler/llvm/build/tools/mlir/python_packages/mlir_core:${BBDIR}/compiler/build/python_packages:$PYTHONPATH" -export BUDDY_BINARY_DIR="${BBDIR}/compiler/build/bin" +export BUDDY_MLIR_BUILD_DIR="${BBDIR}/compiler/thirdparty/buddy-mlir/build" +export LLVM_MLIR_BUILD_DIR="${BBDIR}/compiler/thirdparty/buddy-mlir/llvm/build" +export PYTHONPATH="${BBDIR}/compiler/thirdparty/buddy-mlir/llvm/build/tools/mlir/python_packages/mlir_core:${BBDIR}/compiler/thirdparty/buddy-mlir/build/python_packages:$PYTHONPATH" +export BUDDY_BINARY_DIR="${BBDIR}/compiler/thirdparty/buddy-mlir/build/bin" export RISCV="${BBDIR}/result" +export PATH="${BBDIR}/thirdparty/libgloss/install/lib:$PATH" export PATH="${BUDDY_BINARY_DIR}:${PATH}" #===----------------------------------------------------------------------------=== From 4e3489cca066462b8d193f5d2cc5a39cf50ff2d3 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 27 Apr 2026 15:38:55 +0800 Subject: [PATCH 226/238] [compiler] fix: update path of buddy-mlir --- .gitmodules | 4 ++-- scripts/nix/build-all.sh | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index 28ee77fe..5126cf53 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,8 @@ [submodule "arch/thirdparty/chipyard"] path = arch/thirdparty/chipyard url = https://github.com/ucb-bar/chipyard.git -[submodule "compiler"] - path = compiler +[submodule "buddy-mlir"] + path = compiler/thirdparty/buddy-mlir url = https://github.com/DangoSys/bb-compiler.git [submodule "bbdev"] path = bbdev diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 0a2cf8bc..4990486b 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -76,7 +76,7 @@ function begin_step begin_step "0-1" "submodules init" # git submodule update --init --progress --jobs 8 cd ${BBDIR} -git submodule update --init --progress --jobs 8 \ +git submodule update --init --progress \ arch/thirdparty/chipyard \ bb-tests/workloads/lib/kernel \ bbdev \ @@ -88,7 +88,7 @@ git submodule update --init --progress --jobs 8 \ # I dont know why below is need for buckyball submodules, but it is git -C ${BBDIR} submodule update --init --checkout --force thirdparty/pegasus -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress --jobs 8 fpga/fpga-shells generators/* tools/* sims/firesim +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress fpga/fpga-shells generators/* tools/* sims/firesim # I dont know why below is need for chipyard submodules, but it is git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde tools/rocket-dsp-utils generators/rocc-acc-utils generators/bar-fetchers ########################################## From 0bbe89cf1ddbb1289c5ad446dd4444b9521b8dbf Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 27 Apr 2026 18:23:29 +0800 Subject: [PATCH 227/238] [nix] feat: add build environment for FlatBuffers and NUMA libraries --- flake.nix | 7 +++++++ scripts/nix/build-env-compiler.nix | 9 +++++++++ scripts/nix/overlay.nix | 1 + 3 files changed, 17 insertions(+) create mode 100644 scripts/nix/build-env-compiler.nix diff --git a/flake.nix b/flake.nix index 62f276ba..67926ae7 100644 --- a/flake.nix +++ b/flake.nix @@ -70,6 +70,10 @@ clibs.elfutils-dev clibs.elfutils + # Compiler tools + compiler.flatbuffers + compiler.numactl + # Scala tools scala.mill scala.sbt @@ -104,6 +108,9 @@ clibs.png clibs.elfutils-dev clibs.elfutils + + compiler.flatbuffers + compiler.numactl ]; shellHook = '' if [ -d "$PWD/result/bin" ]; then diff --git a/scripts/nix/build-env-compiler.nix b/scripts/nix/build-env-compiler.nix new file mode 100644 index 00000000..322c5124 --- /dev/null +++ b/scripts/nix/build-env-compiler.nix @@ -0,0 +1,9 @@ +{ pkgs }: + +{ + # FlatBuffers - serialization library and compiler + flatbuffers = pkgs.flatbuffers; + + # NUMA (Non-Uniform Memory Access) library + numactl = pkgs.numactl; +} diff --git a/scripts/nix/overlay.nix b/scripts/nix/overlay.nix index 729a6150..4c6c8f7a 100644 --- a/scripts/nix/overlay.nix +++ b/scripts/nix/overlay.nix @@ -4,6 +4,7 @@ final: prev: # Named rustTools to avoid shadowing nixpkgs `rust` (used by rust hooks) rustTools = final.callPackage ./build-env-rust.nix { }; clibs = final.callPackage ./build-env-clibs.nix { }; + compiler = final.callPackage ./build-env-compiler.nix { }; doc = final.callPackage ./build-env-doc.nix { }; python = final.callPackage ./build-env-python.nix { }; riscv = final.callPackage ./build-env-riscv.nix { }; From 5f6850800bd1bc2f35d9bc6c1f311cdd1be2d872 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 28 Apr 2026 05:24:05 +0800 Subject: [PATCH 228/238] [compiler] refactor: move Buckyball intrinsics and lower Tile dialect to separate dir --- bebop | 2 +- compiler/README.md | 0 .../include/IntrinsicsRISCVBuckyball.td | 17 + .../include/IntrinsicsRISCVBuckyballBase.td | 17 + .../include/IntrinsicsRISCVDequantBall.td | 8 + .../include/IntrinsicsRISCVIm2colBall.td | 8 + .../include/IntrinsicsRISCVQuantBall.td | 8 + .../include/IntrinsicsRISCVReluBall.td | 8 + .../IntrinsicsRISCVSystolicArrayBall.td | 8 + .../include/IntrinsicsRISCVTransposeBall.td | 8 + .../Backend/include/IntrinsicsRISCVVecBall.td | 8 + .../lib/RISCVInstrInfoBuckyballBase.td | 45 ++ .../Backend/lib/RISCVInstrInfoBuddyExtBB.td | 32 ++ .../Backend/lib/RISCVInstrInfoDequantBall.td | 17 + .../Backend/lib/RISCVInstrInfoIm2colBall.td | 16 + .../Backend/lib/RISCVInstrInfoQuantBall.td | 17 + .../src/Backend/lib/RISCVInstrInfoReluBall.td | 17 + .../lib/RISCVInstrInfoSystolicArrayBall.td | 16 + .../lib/RISCVInstrInfoTransposeBall.td | 16 + .../src/Backend/lib/RISCVInstrInfoVecBall.td | 16 + .../AssignBuckyballBanksPass.cpp | 296 ++++++++++ .../LowerBuckyball/LowerBuckyballPass.cpp | 493 ++++++++++++++++ .../LowerBuckyballToBankSSAPass.cpp | 161 ++++++ .../LowerBuckyball/ReportBankUsagePass.cpp | 173 ++++++ .../LowerTileToBuckyball.cpp | 532 ++++++++++++++++++ compiler/src/Dialect/Buckyball/Buckyball.td | 48 ++ .../src/Dialect/Buckyball/BuckyballBankSSA.td | 108 ++++ .../src/Dialect/Buckyball/BuckyballBase.td | 103 ++++ .../src/Dialect/Buckyball/BuckyballDialect.h | 25 + .../Dialect/Buckyball/BuckyballIntrinsics.td | 136 +++++ compiler/src/Dialect/Buckyball/BuckyballOps.h | 29 + .../src/Dialect/Buckyball/BuckyballOps.td | 80 +++ compiler/src/Dialect/Buckyball/DequantBall.td | 31 + .../Dialect/Buckyball/IR/BuckyballDialect.cpp | 45 ++ compiler/src/Dialect/Buckyball/Im2colBall.td | 35 ++ compiler/src/Dialect/Buckyball/QuantBall.td | 31 + compiler/src/Dialect/Buckyball/ReluBall.td | 30 + .../Dialect/Buckyball/SystolicArrayBall.td | 30 + compiler/src/Dialect/Buckyball/Transform.h | 36 ++ .../Transforms/LegalizeForLLVMExport.cpp | 527 +++++++++++++++++ .../src/Dialect/Buckyball/TransposeBall.td | 31 + compiler/src/Dialect/Buckyball/VecBall.td | 30 + .../BuckyballToLLVMIRTranslation.cpp | 69 +++ .../Buckyball/BuckyballToLLVMIRTranslation.h | 34 ++ compiler/thirdparty/buddy-mlir | 2 +- scripts/nix/build-all.sh | 1 + 46 files changed, 3398 insertions(+), 2 deletions(-) create mode 100644 compiler/README.md create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVBuckyball.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVBuckyballBase.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVDequantBall.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVIm2colBall.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVQuantBall.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVReluBall.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVSystolicArrayBall.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVTransposeBall.td create mode 100644 compiler/src/Backend/include/IntrinsicsRISCVVecBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoBuckyballBase.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoBuddyExtBB.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoDequantBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoIm2colBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoQuantBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoReluBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoSystolicArrayBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoTransposeBall.td create mode 100644 compiler/src/Backend/lib/RISCVInstrInfoVecBall.td create mode 100644 compiler/src/Conversion/LowerBuckyball/AssignBuckyballBanksPass.cpp create mode 100644 compiler/src/Conversion/LowerBuckyball/LowerBuckyballPass.cpp create mode 100644 compiler/src/Conversion/LowerBuckyball/LowerBuckyballToBankSSAPass.cpp create mode 100644 compiler/src/Conversion/LowerBuckyball/ReportBankUsagePass.cpp create mode 100644 compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp create mode 100644 compiler/src/Dialect/Buckyball/Buckyball.td create mode 100644 compiler/src/Dialect/Buckyball/BuckyballBankSSA.td create mode 100644 compiler/src/Dialect/Buckyball/BuckyballBase.td create mode 100644 compiler/src/Dialect/Buckyball/BuckyballDialect.h create mode 100644 compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td create mode 100644 compiler/src/Dialect/Buckyball/BuckyballOps.h create mode 100644 compiler/src/Dialect/Buckyball/BuckyballOps.td create mode 100644 compiler/src/Dialect/Buckyball/DequantBall.td create mode 100644 compiler/src/Dialect/Buckyball/IR/BuckyballDialect.cpp create mode 100644 compiler/src/Dialect/Buckyball/Im2colBall.td create mode 100644 compiler/src/Dialect/Buckyball/QuantBall.td create mode 100644 compiler/src/Dialect/Buckyball/ReluBall.td create mode 100644 compiler/src/Dialect/Buckyball/SystolicArrayBall.td create mode 100644 compiler/src/Dialect/Buckyball/Transform.h create mode 100644 compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp create mode 100644 compiler/src/Dialect/Buckyball/TransposeBall.td create mode 100644 compiler/src/Dialect/Buckyball/VecBall.td create mode 100644 compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.cpp create mode 100644 compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.h diff --git a/bebop b/bebop index e9c07bba..3fb041cf 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit e9c07bba541730f853f4062845dac30f60762573 +Subproject commit 3fb041cf517dd3eade77f08f2c9947de695f8416 diff --git a/compiler/README.md b/compiler/README.md new file mode 100644 index 00000000..e69de29b diff --git a/compiler/src/Backend/include/IntrinsicsRISCVBuckyball.td b/compiler/src/Backend/include/IntrinsicsRISCVBuckyball.td new file mode 100644 index 00000000..0b0973d2 --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVBuckyball.td @@ -0,0 +1,17 @@ +//===- IntrinsicsRISCVBuckyball.td - Buckyball intrinsics (main) ---------===// +// +// Main file that includes all Buckyball Ball intrinsics +// +//===----------------------------------------------------------------------===// + +// Base intrinsics (common to all Balls) +include "IntrinsicsRISCVBuckyballBase.td" + +// Ball-specific intrinsics +include "IntrinsicsRISCVVecBall.td" +include "IntrinsicsRISCVReluBall.td" +include "IntrinsicsRISCVTransposeBall.td" +include "IntrinsicsRISCVIm2colBall.td" +include "IntrinsicsRISCVSystolicArrayBall.td" +include "IntrinsicsRISCVQuantBall.td" +include "IntrinsicsRISCVDequantBall.td" diff --git a/compiler/src/Backend/include/IntrinsicsRISCVBuckyballBase.td b/compiler/src/Backend/include/IntrinsicsRISCVBuckyballBase.td new file mode 100644 index 00000000..22f6dd36 --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVBuckyballBase.td @@ -0,0 +1,17 @@ +//===- IntrinsicsRISCVBuckyballBase.td - Base intrinsics -----------------===// +// +// Common Buckyball intrinsics (mvin, mvout, mset, fence) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_mvin : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; + +let TargetPrefix = "riscv" in +def int_riscv_bb_mvout : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; + +let TargetPrefix = "riscv" in +def int_riscv_bb_mset : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; + +let TargetPrefix = "riscv" in +def int_riscv_bb_fence : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVDequantBall.td b/compiler/src/Backend/include/IntrinsicsRISCVDequantBall.td new file mode 100644 index 00000000..0573b96a --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVDequantBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVDequantBall.td - DequantBall intrinsics ------------===// +// +// DequantBall intrinsics (dequant) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_dequant : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVIm2colBall.td b/compiler/src/Backend/include/IntrinsicsRISCVIm2colBall.td new file mode 100644 index 00000000..d3807ca8 --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVIm2colBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVIm2colBall.td - Im2colBall intrinsics --------------===// +// +// Im2colBall intrinsics (im2col) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_im2col : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVQuantBall.td b/compiler/src/Backend/include/IntrinsicsRISCVQuantBall.td new file mode 100644 index 00000000..792ec003 --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVQuantBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVQuantBall.td - QuantBall intrinsics ----------------===// +// +// QuantBall intrinsics (quant) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_quant : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVReluBall.td b/compiler/src/Backend/include/IntrinsicsRISCVReluBall.td new file mode 100644 index 00000000..36cda923 --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVReluBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVReluBall.td - ReluBall intrinsics ------------------===// +// +// ReluBall intrinsics (relu) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_relu : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVSystolicArrayBall.td b/compiler/src/Backend/include/IntrinsicsRISCVSystolicArrayBall.td new file mode 100644 index 00000000..8ac19481 --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVSystolicArrayBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVSystolicArrayBall.td - SystolicArrayBall intrinsics ===// +// +// SystolicArrayBall intrinsics (bbfp_mul) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_bbfp_mul : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVTransposeBall.td b/compiler/src/Backend/include/IntrinsicsRISCVTransposeBall.td new file mode 100644 index 00000000..8e4caabe --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVTransposeBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVTransposeBall.td - TransposeBall intrinsics --------===// +// +// TransposeBall intrinsics (transpose) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_transpose : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/include/IntrinsicsRISCVVecBall.td b/compiler/src/Backend/include/IntrinsicsRISCVVecBall.td new file mode 100644 index 00000000..3725424a --- /dev/null +++ b/compiler/src/Backend/include/IntrinsicsRISCVVecBall.td @@ -0,0 +1,8 @@ +//===- IntrinsicsRISCVVecBall.td - VecBall intrinsics --------------------===// +// +// VecBall intrinsics (mul_warp16) +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in +def int_riscv_bb_mul_warp16 : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty], []>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoBuckyballBase.td b/compiler/src/Backend/lib/RISCVInstrInfoBuckyballBase.td new file mode 100644 index 00000000..ca77410f --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoBuckyballBase.td @@ -0,0 +1,45 @@ +//===- RISCVInstrInfoBuckyballBase.td - Base instructions ----------------===// +// +// Common Buckyball instructions (mvin, mvout, mset, fence) +// +//===----------------------------------------------------------------------===// + +// bb_mvin: funct7=33 (0b0100001) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_MVIN : RVInstR<0b0100001, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_mvin", "$rs1, $rs2"> { + let rd = 0; +} + +// bb_mvout: funct7=16 (0b0010000) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_MVOUT : RVInstR<0b0010000, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_mvout", "$rs1, $rs2"> { + let rd = 0; +} + +// bb_mset: funct7=32 (0b0100000) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_MSET : RVInstR<0b0100000, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_mset", "$rs1, $rs2"> { + let rd = 0; +} + +// bb_fence: funct7=0 (0b0000000) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_FENCE : RVInstR<0b0000000, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_fence", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic patterns +let Predicates = [HasBuddyExt] in { + def : Pat<(int_riscv_bb_mvin GPR:$rs1, GPR:$rs2), (BB_MVIN GPR:$rs1, GPR:$rs2)>; + def : Pat<(int_riscv_bb_mvout GPR:$rs1, GPR:$rs2), (BB_MVOUT GPR:$rs1, GPR:$rs2)>; + def : Pat<(int_riscv_bb_mset GPR:$rs1, GPR:$rs2), (BB_MSET GPR:$rs1, GPR:$rs2)>; + def : Pat<(int_riscv_bb_fence GPR:$rs1, GPR:$rs2), (BB_FENCE GPR:$rs1, GPR:$rs2)>; +} diff --git a/compiler/src/Backend/lib/RISCVInstrInfoBuddyExtBB.td b/compiler/src/Backend/lib/RISCVInstrInfoBuddyExtBB.td new file mode 100644 index 00000000..36f37678 --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoBuddyExtBB.td @@ -0,0 +1,32 @@ +//===- RISCVInstrInfoBuddyExtBB.td - Buckyball instructions (main) -------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// Main file that includes all Buckyball Ball instruction definitions. +// This file is included by buddy-mlir's RISCVInstrInfoBuddyExt.td. +// +//===----------------------------------------------------------------------===// + +// Base instructions (common to all Balls) +include "RISCVInstrInfoBuckyballBase.td" + +// Ball-specific instructions +include "RISCVInstrInfoVecBall.td" +include "RISCVInstrInfoReluBall.td" +include "RISCVInstrInfoTransposeBall.td" +include "RISCVInstrInfoIm2colBall.td" +include "RISCVInstrInfoSystolicArrayBall.td" +include "RISCVInstrInfoQuantBall.td" +include "RISCVInstrInfoDequantBall.td" diff --git a/compiler/src/Backend/lib/RISCVInstrInfoDequantBall.td b/compiler/src/Backend/lib/RISCVInstrInfoDequantBall.td new file mode 100644 index 00000000..c6d3e493 --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoDequantBall.td @@ -0,0 +1,17 @@ +//===- RISCVInstrInfoDequantBall.td - DequantBall instructions -----------===// +// +// DequantBall instructions (dequant) +// +//===----------------------------------------------------------------------===// + +// bb_dequant: funct7=52 (0b0110100) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_DEQUANT : RVInstR<0b0110100, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_dequant", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_dequant GPR:$rs1, GPR:$rs2), (BB_DEQUANT GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoIm2colBall.td b/compiler/src/Backend/lib/RISCVInstrInfoIm2colBall.td new file mode 100644 index 00000000..15a2cffc --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoIm2colBall.td @@ -0,0 +1,16 @@ +//===- RISCVInstrInfoIm2colBall.td - Im2colBall instructions -------------===// +// +// Im2colBall instructions (im2col) +// +//===----------------------------------------------------------------------===// + +// bb_im2col: funct7=48 (0b0110000) +let isCodeGenOnly = 1, Predicates = [HasBuddyExt] in +def BB_IM2COL : RVInstR<0b0110000, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_im2col", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_im2col GPR:$rs1, GPR:$rs2), (BB_IM2COL GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoQuantBall.td b/compiler/src/Backend/lib/RISCVInstrInfoQuantBall.td new file mode 100644 index 00000000..0f03e415 --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoQuantBall.td @@ -0,0 +1,17 @@ +//===- RISCVInstrInfoQuantBall.td - QuantBall instructions ---------------===// +// +// QuantBall instructions (quant) +// +//===----------------------------------------------------------------------===// + +// bb_quant: funct7=51 (0b0110011) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_QUANT : RVInstR<0b0110011, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_quant", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_quant GPR:$rs1, GPR:$rs2), (BB_QUANT GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoReluBall.td b/compiler/src/Backend/lib/RISCVInstrInfoReluBall.td new file mode 100644 index 00000000..6791e202 --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoReluBall.td @@ -0,0 +1,17 @@ +//===- RISCVInstrInfoReluBall.td - ReluBall instructions -----------------===// +// +// ReluBall instructions (relu) +// +//===----------------------------------------------------------------------===// + +// bb_relu: funct7=50 (0b0110010) +let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, + Predicates = [HasBuddyExt] in +def BB_RELU : RVInstR<0b0110010, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_relu", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_relu GPR:$rs1, GPR:$rs2), (BB_RELU GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoSystolicArrayBall.td b/compiler/src/Backend/lib/RISCVInstrInfoSystolicArrayBall.td new file mode 100644 index 00000000..c15acacc --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoSystolicArrayBall.td @@ -0,0 +1,16 @@ +//===- RISCVInstrInfoSystolicArrayBall.td - SystolicArrayBall instructions ===// +// +// SystolicArrayBall instructions (bbfp_mul) +// +//===----------------------------------------------------------------------===// + +// bb_bbfp_mul: funct7=65 (0b1000001) +let isCodeGenOnly = 1, Predicates = [HasBuddyExt] in +def BB_BBFP_MUL : RVInstR<0b1000001, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_bbfp_mul", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_bbfp_mul GPR:$rs1, GPR:$rs2), (BB_BBFP_MUL GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoTransposeBall.td b/compiler/src/Backend/lib/RISCVInstrInfoTransposeBall.td new file mode 100644 index 00000000..40c56996 --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoTransposeBall.td @@ -0,0 +1,16 @@ +//===- RISCVInstrInfoTransposeBall.td - TransposeBall instructions -------===// +// +// TransposeBall instructions (transpose) +// +//===----------------------------------------------------------------------===// + +// bb_transpose: funct7=49 (0b0110001) +let isCodeGenOnly = 1, Predicates = [HasBuddyExt] in +def BB_TRANSPOSE : RVInstR<0b0110001, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_transpose", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_transpose GPR:$rs1, GPR:$rs2), (BB_TRANSPOSE GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Backend/lib/RISCVInstrInfoVecBall.td b/compiler/src/Backend/lib/RISCVInstrInfoVecBall.td new file mode 100644 index 00000000..967982ce --- /dev/null +++ b/compiler/src/Backend/lib/RISCVInstrInfoVecBall.td @@ -0,0 +1,16 @@ +//===- RISCVInstrInfoVecBall.td - VecBall instructions -------------------===// +// +// VecBall instructions (mul_warp16) +// +//===----------------------------------------------------------------------===// + +// bb_mul_warp16: funct7=64 (0b1000000) +let isCodeGenOnly = 1, Predicates = [HasBuddyExt] in +def BB_MUL_WARP16 : RVInstR<0b1000000, 0b011, OPC_CUSTOM_3, (outs), + (ins GPR:$rs1, GPR:$rs2), "bb_mul_warp16", "$rs1, $rs2"> { + let rd = 0; +} + +// Intrinsic pattern +let Predicates = [HasBuddyExt] in +def : Pat<(int_riscv_bb_mul_warp16 GPR:$rs1, GPR:$rs2), (BB_MUL_WARP16 GPR:$rs1, GPR:$rs2)>; diff --git a/compiler/src/Conversion/LowerBuckyball/AssignBuckyballBanksPass.cpp b/compiler/src/Conversion/LowerBuckyball/AssignBuckyballBanksPass.cpp new file mode 100644 index 00000000..c4dc7e2f --- /dev/null +++ b/compiler/src/Conversion/LowerBuckyball/AssignBuckyballBanksPass.cpp @@ -0,0 +1,296 @@ +//====- AssignPhysicalBanksPass.cpp - Map virtual handles to physical banks +//-===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// Assign physical banks for Bank-SSA ops. +// - Input ops: bb_bank_alloc/release/mvin/mvout/mul_warp16. +// - Output ops: bb_mset/mvin/mvout/mul_warp16. +// - Model: 16 banks, each 16KB. row*col consumes contiguous banks. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/IR/BuiltinAttributes.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/Pass/Pass.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" + +#include + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" + +using namespace mlir; +using namespace buddy; + +namespace { + +struct BankSlot { + int64_t base = -1; + int64_t row = 1; + int64_t col = 1; +}; + +static uint64_t fieldBits(uint64_t val, int startBit, int endBit) { + uint64_t width = endBit - startBit + 1; + uint64_t mask = (1ULL << width) - 1; + return (val & mask) << startBit; +} + +static Value cstI64(OpBuilder &b, Location loc, uint64_t v) { + return b.create(loc, b.getI64Type(), + b.getI64IntegerAttr(v)); +} + +static buckyball::MsetOp createMset(OpBuilder &b, Location loc, uint64_t bankId, + bool alloc, uint64_t row, uint64_t col) { + auto op = b.create(loc, cstI64(b, loc, bankId)); + op->setAttr("alloc", b.getBoolAttr(alloc)); + op->setAttr("row", b.getI64IntegerAttr(row)); + op->setAttr("col", b.getI64IntegerAttr(col)); + return op; +} + +class AssignPhysicalBanksPass + : public PassWrapper> { +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(AssignPhysicalBanksPass) + AssignPhysicalBanksPass() = default; + AssignPhysicalBanksPass(const AssignPhysicalBanksPass &) {} + StringRef getArgument() const final { return "assign-physical-banks"; } + StringRef getDescription() const final { + return "Assign physical banks for bank-SSA ops."; + } + + Option bankNum{*this, "bank_num", + llvm::cl::desc("Number of physical banks."), + llvm::cl::init(16)}; + + void runOnOperation() override { + func::FuncOp func = getOperation(); + OpBuilder b(func.getContext()); + llvm::DenseMap vm; + llvm::SmallVector used(bankNum, 0); + auto getConstI64 = [&](Value v) -> std::optional { + auto c = v.getDefiningOp(); + if (!c) + return std::nullopt; + auto a = dyn_cast(c.getValue()); + if (!a) + return std::nullopt; + return a.getInt(); + }; + + auto tryAlloc = [&](int64_t row, int64_t col) -> std::optional { + int64_t need = row * col; + for (int64_t s = 0; s + need <= bankNum; ++s) { + bool ok = true; + for (int64_t i = 0; i < need; ++i) { + if (used[s + i]) { + ok = false; + break; + } + } + if (!ok) + continue; + for (int64_t i = 0; i < need; ++i) + used[s + i] = 1; + return s; + } + return std::nullopt; + }; + + auto freeAlloc = [&](const BankSlot &s) { + int64_t need = s.row * s.col; + for (int64_t i = 0; i < need; ++i) + used[s.base + i] = 0; + }; + + for (Block &blk : func.getBlocks()) { + for (Operation &op : llvm::make_early_inc_range(blk.getOperations())) { + b.setInsertionPoint(&op); + Location loc = op.getLoc(); + + if (auto a = dyn_cast(op)) { + int64_t row = a.getRow(); + int64_t col = a.getCol(); + if (row <= 0 || col <= 0) + return signalPassFailure(); + auto base = tryAlloc(row, col); + if (!base) { + op.emitError("assign-physical-banks: out of physical banks"); + return signalPassFailure(); + } + Value bid = cstI64(b, loc, static_cast(*base)); + createMset(b, loc, static_cast(*base), true, row, col); + vm[*base] = BankSlot{*base, row, col}; + a.getBank().replaceAllUsesWith(bid); + op.erase(); + continue; + } + + if (auto r = dyn_cast(op)) { + auto bid = getConstI64(r.getBank()); + if (!bid) { + op.emitError("release expects constant bank id after assignment"); + return signalPassFailure(); + } + auto it = vm.find(*bid); + if (it == vm.end()) { + op.emitError("release of unknown virtual bank handle"); + return signalPassFailure(); + } + createMset(b, loc, static_cast(it->second.base), false, 0, + 0); + freeAlloc(it->second); + vm.erase(it); + op.erase(); + continue; + } + + if (auto mv = dyn_cast(op)) { + b.create(loc, mv.getInput(), mv.getBank(), + mv.getDepth(), mv.getStride()); + mv.getBankOut().replaceAllUsesWith(mv.getBank()); + op.erase(); + continue; + } + + if (auto mv = dyn_cast(op)) { + b.create(loc, mv.getOutput(), mv.getBank(), + mv.getDepth(), mv.getStride()); + mv.getBankOut().replaceAllUsesWith(mv.getBank()); + op.erase(); + continue; + } + + if (auto mm = dyn_cast(op)) { + b.create(loc, mm.getOp1Bank(), + mm.getOp2Bank(), mm.getWrBank(), + mm.getIter(), mm.getMode()); + mm.getWrBankOut().replaceAllUsesWith(mm.getWrBank()); + op.erase(); + continue; + } + + if (auto tp = dyn_cast(op)) { + auto in = getConstI64(tp.getInBank()); + auto out = getConstI64(tp.getOutBank()); + auto iter = getConstI64(tp.getIter()); + if (!in || !out || !iter) { + op.emitError( + "bank_transpose expects constant in/out/iter after assignment"); + return signalPassFailure(); + } + uint64_t rs1 = fieldBits(*in, 0, 9) | fieldBits(*out, 20, 29) | + fieldBits(*iter, 30, 63); + Value rs2 = tp.getMode(); + b.create(loc, cstI64(b, loc, rs1), rs2); + tp.getOutBankOut().replaceAllUsesWith(tp.getOutBank()); + op.erase(); + continue; + } + + if (auto im = dyn_cast(op)) { + auto in = getConstI64(im.getInBank()); + auto out = getConstI64(im.getOutBank()); + if (!in || !out) { + op.emitError( + "bank_im2col expects constant in/out after assignment"); + return signalPassFailure(); + } + uint64_t rs1 = fieldBits(*in, 0, 9) | fieldBits(*out, 20, 29); + Value rs2 = im.getKcol(); + rs2 = b.create( + loc, rs2, + b.create(loc, im.getKrow(), cstI64(b, loc, 4))); + rs2 = b.create( + loc, rs2, + b.create(loc, im.getIncol(), cstI64(b, loc, 8))); + rs2 = b.create( + loc, rs2, + b.create(loc, im.getInrow(), cstI64(b, loc, 13))); + rs2 = b.create( + loc, rs2, + b.create(loc, im.getStartcol(), + cstI64(b, loc, 23))); + rs2 = b.create( + loc, rs2, + b.create(loc, im.getStartrow(), + cstI64(b, loc, 28))); + b.create(loc, cstI64(b, loc, rs1), rs2); + im.getOutBankOut().replaceAllUsesWith(im.getOutBank()); + op.erase(); + continue; + } + + if (auto q = dyn_cast(op)) { + auto in = getConstI64(q.getInBank()); + auto out = getConstI64(q.getOutBank()); + auto iter = getConstI64(q.getIter()); + if (!in || !out || !iter) { + op.emitError( + "bank_quant expects constant in/out/iter after assignment"); + return signalPassFailure(); + } + uint64_t rs1 = fieldBits(*in, 0, 9) | fieldBits(*out, 20, 29) | + fieldBits(*iter, 30, 63); + Value rs2 = q.getScale(); + b.create(loc, cstI64(b, loc, rs1), rs2); + q.getOutBankOut().replaceAllUsesWith(q.getOutBank()); + op.erase(); + continue; + } + + if (auto dq = dyn_cast(op)) { + auto in = getConstI64(dq.getInBank()); + auto out = getConstI64(dq.getOutBank()); + auto iter = getConstI64(dq.getIter()); + if (!in || !out || !iter) { + op.emitError( + "bank_dequant expects constant in/out/iter after assignment"); + return signalPassFailure(); + } + uint64_t rs1 = fieldBits(*in, 0, 9) | fieldBits(*out, 20, 29) | + fieldBits(*iter, 30, 63); + Value rs2 = dq.getScale(); + b.create(loc, cstI64(b, loc, rs1), rs2); + dq.getOutBankOut().replaceAllUsesWith(dq.getOutBank()); + op.erase(); + continue; + } + } + } + + if (!vm.empty()) { + func.emitError("assign-physical-banks: leaked virtual bank handles"); + signalPassFailure(); + } + } +}; + +} // namespace + +namespace mlir { +namespace buddy { +void registerAssignPhysicalBanksPass() { + PassRegistration(); +} +} // namespace buddy +} // namespace mlir diff --git a/compiler/src/Conversion/LowerBuckyball/LowerBuckyballPass.cpp b/compiler/src/Conversion/LowerBuckyball/LowerBuckyballPass.cpp new file mode 100644 index 00000000..0b2a03ae --- /dev/null +++ b/compiler/src/Conversion/LowerBuckyball/LowerBuckyballPass.cpp @@ -0,0 +1,493 @@ +//====- LowerBuckyballPass.cpp - Buckyball Dialect Lowering Pass +//-------------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file defines Buckyball dialect lowering pass. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Conversion/AffineToStandard/AffineToStandard.h" +#include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h" +#include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h" +#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h" +#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVMPass.h" +#include "mlir/Conversion/LLVMCommon/ConversionTarget.h" +#include "mlir/Conversion/LLVMCommon/TypeConverter.h" +#include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" +#include "mlir/Conversion/SCFToControlFlow/SCFToControlFlow.h" +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Bufferization/Transforms/Bufferize.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/Dialect/MemRef/IR/MemRef.h" +#include "mlir/Dialect/SCF/IR/SCF.h" +#include "mlir/Dialect/Vector/IR/VectorOps.h" +#include "mlir/Pass/Pass.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" +#include "Buckyball/Transform.h" + +using namespace mlir; +using namespace buddy; + +class BBPrintMemRefOpLowering : public ConversionPattern { +public: + explicit BBPrintMemRefOpLowering(MLIRContext *context) + : ConversionPattern(buckyball::PrintMemRefOp::getOperationName(), 1, + context) {} + + LogicalResult + matchAndRewrite(Operation *op, ArrayRef operands, + ConversionPatternRewriter &rewriter) const override { + auto context = rewriter.getContext(); + auto memRefType = llvm::cast(*op->operand_type_begin()); + auto memRefShape = memRefType.getShape(); + Type memElementType = memRefType.getElementType(); + auto loc = op->getLoc(); + ModuleOp parentModule = op->getParentOfType(); + auto printfRef = getOrInsertPrintf(rewriter, parentModule); + Value formatSpecifierCst; + if (memElementType == rewriter.getF32Type() || + memElementType == rewriter.getF64Type()) { + formatSpecifierCst = getOrCreateGlobalString( + loc, rewriter, "frmt_spec", StringRef("%f \0", 4), parentModule); + } else if (memElementType == rewriter.getI8Type() || + memElementType == rewriter.getI32Type()) { + formatSpecifierCst = getOrCreateGlobalString( + loc, rewriter, "frmt_spec", StringRef("%d \0", 4), parentModule); + } + Value newLineCst = getOrCreateGlobalString( + loc, rewriter, "nl", StringRef("\n\0", 2), parentModule); + SmallVector loopIvs; + for (unsigned i = 0, e = memRefShape.size(); i != e; ++i) { + auto lowerBound = rewriter.create(loc, 0); + auto upperBound = + rewriter.create(loc, memRefShape[i]); + auto step = rewriter.create(loc, 1); + auto loop = + rewriter.create(loc, lowerBound, upperBound, step); + for (Operation &nested : *loop.getBody()) + rewriter.eraseOp(&nested); + loopIvs.push_back(loop.getInductionVar()); + + rewriter.setInsertionPointToEnd(loop.getBody()); + + if (i != e - 1) + rewriter.create(loc, getPrintfType(context), printfRef, + newLineCst); + rewriter.create(loc); + rewriter.setInsertionPointToStart(loop.getBody()); + } + + auto printOp = cast(op); + Value elementLoad = + rewriter.create(loc, printOp.getInput(), loopIvs); + if (elementLoad.getType() == rewriter.getF32Type()) + elementLoad = rewriter.create( + loc, rewriter.getF64Type(), elementLoad); + else if (elementLoad.getType() == rewriter.getI8Type()) + elementLoad = rewriter.create( + loc, rewriter.getI32Type(), elementLoad); + rewriter.create( + loc, getPrintfType(context), printfRef, + ArrayRef({formatSpecifierCst, elementLoad})); + + rewriter.eraseOp(op); + return success(); + } + +private: + static LLVM::LLVMFunctionType getPrintfType(MLIRContext *context) { + auto llvmI32Ty = IntegerType::get(context, 32); + auto llvmPtr = LLVM::LLVMPointerType::get(context); + return LLVM::LLVMFunctionType::get(llvmI32Ty, llvmPtr, true); + } + + static FlatSymbolRefAttr getOrInsertPrintf(PatternRewriter &rewriter, + ModuleOp module) { + auto *context = module.getContext(); + if (module.lookupSymbol("printf")) + return SymbolRefAttr::get(context, "printf"); + + PatternRewriter::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(module.getBody()); + rewriter.create(module.getLoc(), "printf", + getPrintfType(context)); + return SymbolRefAttr::get(context, "printf"); + } + + static Value getOrCreateGlobalString(Location loc, OpBuilder &builder, + StringRef name, StringRef value, + ModuleOp module) { + LLVM::GlobalOp global; + if (!(global = module.lookupSymbol(name))) { + OpBuilder::InsertionGuard insertGuard(builder); + builder.setInsertionPointToStart(module.getBody()); + auto type = LLVM::LLVMArrayType::get( + IntegerType::get(builder.getContext(), 8), value.size()); + global = builder.create(loc, type, true, + LLVM::Linkage::Internal, name, + builder.getStringAttr(value), 0); + } + + Value globalPtr = builder.create(loc, global); + Value cst0 = builder.create(loc, builder.getI64Type(), + builder.getIndexAttr(0)); + return builder.create( + loc, LLVM::LLVMPointerType::get(builder.getContext()), global.getType(), + globalPtr, ArrayRef({cst0, cst0})); + } +}; + +class BBPrintScalarOpLowering : public ConversionPattern { +public: + explicit BBPrintScalarOpLowering(MLIRContext *context) + : ConversionPattern(buckyball::PrintScalarOp::getOperationName(), 1, + context) {} + + LogicalResult + matchAndRewrite(Operation *op, ArrayRef operands, + ConversionPatternRewriter &rewriter) const override { + auto context = rewriter.getContext(); + auto loc = op->getLoc(); + + ModuleOp parentModule = op->getParentOfType(); + + auto printfRef = getOrInsertPrintf(rewriter, parentModule); + + Type elementType = op->getOperand(0).getType(); + Value formatSpecifierCst; + + if (elementType == rewriter.getF32Type() || + elementType == rewriter.getF64Type()) { + formatSpecifierCst = getOrCreateGlobalString( + loc, rewriter, "scalar_fmt", StringRef("%f\n\0", 5), parentModule); + } else if (elementType == rewriter.getI8Type() || + elementType == rewriter.getI32Type()) { + formatSpecifierCst = getOrCreateGlobalString( + loc, rewriter, "scalar_fmt", StringRef("%d\n\0", 5), parentModule); + } + + Value valueToPrint = op->getOperand(0); + if (elementType == rewriter.getF32Type()) { + valueToPrint = rewriter.create(loc, rewriter.getF64Type(), + valueToPrint); + } else if (elementType == rewriter.getI8Type()) { + valueToPrint = rewriter.create(loc, rewriter.getI32Type(), + valueToPrint); + } + + rewriter.create( + loc, getPrintfType(context), printfRef, + ArrayRef({formatSpecifierCst, valueToPrint})); + + rewriter.eraseOp(op); + return success(); + } + +private: + static LLVM::LLVMFunctionType getPrintfType(MLIRContext *context) { + auto llvmI32Ty = IntegerType::get(context, 32); + auto llvmPtr = LLVM::LLVMPointerType::get(context); + return LLVM::LLVMFunctionType::get(llvmI32Ty, llvmPtr, true); + } + + static FlatSymbolRefAttr getOrInsertPrintf(PatternRewriter &rewriter, + ModuleOp module) { + auto *context = module.getContext(); + if (module.lookupSymbol("printf")) + return SymbolRefAttr::get(context, "printf"); + + PatternRewriter::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(module.getBody()); + rewriter.create(module.getLoc(), "printf", + getPrintfType(context)); + return SymbolRefAttr::get(context, "printf"); + } + + static Value getOrCreateGlobalString(Location loc, OpBuilder &builder, + StringRef name, StringRef value, + ModuleOp module) { + LLVM::GlobalOp global; + if (!(global = module.lookupSymbol(name))) { + OpBuilder::InsertionGuard insertGuard(builder); + builder.setInsertionPointToStart(module.getBody()); + auto type = LLVM::LLVMArrayType::get( + IntegerType::get(builder.getContext(), 8), value.size()); + global = builder.create(loc, type, true, + LLVM::Linkage::Internal, name, + builder.getStringAttr(value), 0); + } + + Value globalPtr = builder.create(loc, global); + Value cst0 = builder.create(loc, builder.getI64Type(), + builder.getIndexAttr(0)); + return builder.create( + loc, LLVM::LLVMPointerType::get(builder.getContext()), global.getType(), + globalPtr, ArrayRef({cst0, cst0})); + } +}; + +class BBCounterStartOpLowering : public ConversionPattern { +public: + explicit BBCounterStartOpLowering(MLIRContext *context) + : ConversionPattern(buckyball::CounterStartOp::getOperationName(), 1, + context) {} + + LogicalResult + matchAndRewrite(Operation *op, ArrayRef operands, + ConversionPatternRewriter &rewriter) const override { + auto loc = op->getLoc(); + auto context = rewriter.getContext(); + auto counterId = op->getOperand(0); + + ModuleOp parentModule = op->getParentOfType(); + + auto counterGlobal = + getOrCreateCounterGlobal(rewriter, parentModule, counterId); + + auto i64Type = rewriter.getI64Type(); + auto rdcycleAsm = rewriter.create( + loc, + /*resultTypes=*/i64Type, + /*operands=*/ValueRange{}, + /*asm_string=*/"rdcycle $0", + /*constraints=*/"=r", + /*has_side_effects=*/false, + /*is_align_stack=*/false, + /*tail_call_kind=*/LLVM::tailcallkind::TailCallKind::None, + /*asm_dialect=*/ + LLVM::AsmDialectAttr::get(context, LLVM::AsmDialect::AD_ATT), + /*operand_attrs=*/ArrayAttr()); + + rewriter.create(loc, rdcycleAsm.getResult(0), counterGlobal); + + rewriter.eraseOp(op); + return success(); + } + +private: + static Value getOrCreateCounterGlobal(PatternRewriter &rewriter, + ModuleOp module, Value counterId) { + auto context = rewriter.getContext(); + auto loc = module.getLoc(); + + std::string globalName = "bb_counter_start"; + + LLVM::GlobalOp global; + if (!(global = module.lookupSymbol(globalName))) { + OpBuilder::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(module.getBody()); + auto i64Type = IntegerType::get(context, 64); + global = rewriter.create( + loc, i64Type, /*isConstant=*/false, LLVM::Linkage::Internal, + globalName, + /*value=*/rewriter.getI64IntegerAttr(0)); + } + + Value globalPtr = rewriter.create(loc, global); + return globalPtr; + } +}; + +class BBCounterStopOpLowering : public ConversionPattern { +public: + explicit BBCounterStopOpLowering(MLIRContext *context) + : ConversionPattern(buckyball::CounterStopOp::getOperationName(), 1, + context) {} + LogicalResult + matchAndRewrite(Operation *op, ArrayRef operands, + ConversionPatternRewriter &rewriter) const override { + auto loc = op->getLoc(); + auto context = rewriter.getContext(); + auto counterId = op->getOperand(0); + + ModuleOp parentModule = op->getParentOfType(); + + auto counterGlobal = getCounterGlobal(rewriter, parentModule, counterId); + + auto i64Type = rewriter.getI64Type(); + Value startCycles = + rewriter.create(loc, i64Type, counterGlobal); + + auto rdcycleAsm = rewriter.create( + loc, + /*resultTypes=*/i64Type, + /*operands=*/ValueRange{}, + /*asm_string=*/"rdcycle $0", + /*constraints=*/"=r", + /*has_side_effects=*/false, + /*is_align_stack=*/false, + /*tail_call_kind=*/LLVM::tailcallkind::TailCallKind::None, + /*asm_dialect=*/ + LLVM::AsmDialectAttr::get(context, LLVM::AsmDialect::AD_ATT), + /*operand_attrs=*/ArrayAttr()); + + Value endCycles = rdcycleAsm.getResult(0); + Value cyclesDiff = + rewriter.create(loc, endCycles, startCycles); + + rewriter.replaceOp(op, cyclesDiff); + return success(); + } + +private: + static Value getCounterGlobal(PatternRewriter &rewriter, ModuleOp module, + Value counterId) { + auto context = rewriter.getContext(); + auto loc = module.getLoc(); + + std::string globalName = "bb_counter_start"; + + LLVM::GlobalOp global = module.lookupSymbol(globalName); + assert(global && "Counter global variable should exist"); + + Value globalPtr = rewriter.create(loc, global); + return globalPtr; + } +}; + +namespace { +class LowerBuckyballToLLVMPass + : public PassWrapper> { +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(LowerBuckyballToLLVMPass) + StringRef getArgument() const final { return "lower-buckyball"; } + StringRef getDescription() const final { + return "buckyball dialect lowering pass."; + } + LowerBuckyballToLLVMPass() = default; + LowerBuckyballToLLVMPass(const LowerBuckyballToLLVMPass &) {} + + Option lane{*this, "lane", llvm::cl::desc("Hardware lane width."), + llvm::cl::init(16)}; + Option warp{*this, "warp", llvm::cl::desc("Hardware warp depth."), + llvm::cl::init(16)}; + Option bankDepth{*this, "bank_depth", + llvm::cl::desc("Depth of each bank."), + llvm::cl::init(4096)}; + Option bankNum{*this, "bank_num", llvm::cl::desc("Number of banks."), + llvm::cl::init(8)}; + Option hartId{*this, "hartId", llvm::cl::desc("The hart id."), + llvm::cl::init(0)}; + + // Override explicitly to allow conditional dialect dependence. + void getDependentDialects(DialectRegistry ®istry) const override { + registry.insert(); + registry.insert(); + registry.insert(); + registry.insert(); + registry.insert(); + registry.insert(); + } + + void runOnOperation() override; +}; + +class LowerBankSSAToIntrinsicsPass + : public PassWrapper> { +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(LowerBankSSAToIntrinsicsPass) + StringRef getArgument() const final { return "lower-bank-ssa-to-intrinsics"; } + StringRef getDescription() const final { + return "Lower bank-SSA and Buckyball ops to intrinsic ops."; + } + LowerBankSSAToIntrinsicsPass() = default; + LowerBankSSAToIntrinsicsPass(const LowerBankSSAToIntrinsicsPass &) {} + + Option lane{*this, "lane", llvm::cl::desc("Hardware lane width."), + llvm::cl::init(16)}; + Option warp{*this, "warp", llvm::cl::desc("Hardware warp depth."), + llvm::cl::init(16)}; + Option bankDepth{*this, "bank_depth", + llvm::cl::desc("Depth of each bank."), + llvm::cl::init(4096)}; + Option bankNum{*this, "bank_num", llvm::cl::desc("Number of banks."), + llvm::cl::init(8)}; + Option hartId{*this, "hartId", llvm::cl::desc("The hart id."), + llvm::cl::init(0)}; + + void getDependentDialects(DialectRegistry ®istry) const override { + registry.insert(); + registry.insert(); + registry.insert(); + registry.insert(); + registry.insert(); + registry.insert(); + } + + void runOnOperation() override; +}; +} // namespace + +void LowerBuckyballToLLVMPass::runOnOperation() { + MLIRContext *context = &getContext(); + ModuleOp module = getOperation(); + LLVMTypeConverter converter(context); + RewritePatternSet patterns(context); + LLVMConversionTarget target(*context); + configureBuckyballLegalizeForExportTarget(target); + populateBuckyballLegalizeForLLVMExportPatterns(converter, patterns, lane, + warp, bankDepth, bankNum); + populateAffineToStdConversionPatterns(patterns); + populateSCFToControlFlowConversionPatterns(patterns); + mlir::arith::populateArithToLLVMConversionPatterns(converter, patterns); + populateFinalizeMemRefToLLVMConversionPatterns(converter, patterns); + cf::populateControlFlowToLLVMConversionPatterns(converter, patterns); + populateFuncToLLVMConversionPatterns(converter, patterns); + patterns.add(&getContext()); + patterns.add(&getContext()); + patterns.add(&getContext()); + patterns.add(&getContext()); + if (failed(applyPartialConversion(module, target, std::move(patterns)))) + signalPassFailure(); +} + +void LowerBankSSAToIntrinsicsPass::runOnOperation() { + MLIRContext *context = &getContext(); + ModuleOp module = getOperation(); + LLVMTypeConverter converter(context); + RewritePatternSet patterns(context); + LLVMConversionTarget target(*context); + configureBuckyballLegalizeForExportTarget(target); + populateBuckyballLegalizeForLLVMExportPatterns(converter, patterns, lane, + warp, bankDepth, bankNum); + populateAffineToStdConversionPatterns(patterns); + populateSCFToControlFlowConversionPatterns(patterns); + mlir::arith::populateArithToLLVMConversionPatterns(converter, patterns); + populateFinalizeMemRefToLLVMConversionPatterns(converter, patterns); + cf::populateControlFlowToLLVMConversionPatterns(converter, patterns); + populateFuncToLLVMConversionPatterns(converter, patterns); + patterns.add(&getContext()); + patterns.add(&getContext()); + patterns.add(&getContext()); + patterns.add(&getContext()); + if (failed(applyPartialConversion(module, target, std::move(patterns)))) + signalPassFailure(); +} + +namespace mlir { +namespace buddy { +void registerLowerBuckyballPass() { + PassRegistration(); +} +void registerLowerBankSSAToIntrinsicsPass() { + PassRegistration(); +} +} // namespace buddy +} // namespace mlir diff --git a/compiler/src/Conversion/LowerBuckyball/LowerBuckyballToBankSSAPass.cpp b/compiler/src/Conversion/LowerBuckyball/LowerBuckyballToBankSSAPass.cpp new file mode 100644 index 00000000..839c7dbd --- /dev/null +++ b/compiler/src/Conversion/LowerBuckyball/LowerBuckyballToBankSSAPass.cpp @@ -0,0 +1,161 @@ +//====- LowerBuckyballToBankSSAPass.cpp - Expand to bank-SSA ops +//-----------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/Pass/Pass.h" +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" + +using namespace mlir; +using namespace buddy; + +namespace { + +static Value cstI64(OpBuilder &b, Location loc, uint64_t v) { + return b.create(loc, b.getI64Type(), + b.getI64IntegerAttr(v)); +} + +static LogicalResult getStaticRowStrideDiv16(MemRefType ty, uint64_t &out) { + SmallVector strides; + int64_t off = 0; + if (failed(ty.getStridesAndOffset(strides, off)) || strides.size() < 2) + return failure(); + if (ShapedType::isDynamic(strides[0]) || strides[0] <= 0 || + strides[0] % 16 != 0) + return failure(); + if (ShapedType::isDynamic(strides[1]) || strides[1] != 1) + return failure(); + out = static_cast(strides[0] / 16); + return success(); +} + +class MatMulToBankSSAPattern : public OpRewritePattern { +public: + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(buckyball::MatMulOp op, + PatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value aMem = op.getAMemArray(); + Value bMem = op.getBMemArray(); + Value cMem = op.getCMemArray(); + + auto aTy = dyn_cast(aMem.getType()); + auto bTy = dyn_cast(bMem.getType()); + auto cTy = dyn_cast(cMem.getType()); + if (!aTy || !bTy || !cTy || !aTy.hasStaticShape() || + !bTy.hasStaticShape() || !cTy.hasStaticShape()) + return rewriter.notifyMatchFailure( + op, "bb_matmul requires static rank-2 memrefs"); + + uint64_t m = aTy.getShape()[0]; + uint64_t k = aTy.getShape()[1]; + uint64_t kb = bTy.getShape()[0]; + uint64_t n = bTy.getShape()[1]; + if (k != kb) + return rewriter.notifyMatchFailure(op, "inner dimensions must match"); + if (k % 16 != 0 || n % 16 != 0) + return rewriter.notifyMatchFailure(op, "K and N must be multiples of 16"); + + uint64_t strideA = 1; + uint64_t strideB = 0; + uint64_t strideC = 0; + if (failed(getStaticRowStrideDiv16(bTy, strideB))) + return rewriter.notifyMatchFailure( + op, "B requires static strided<[row,1]> and row % 16 == 0"); + if (failed(getStaticRowStrideDiv16(cTy, strideC))) + return rewriter.notifyMatchFailure( + op, "C requires static strided<[row,1]> and row % 16 == 0"); + + uint64_t depthA = m * (k / 16); + uint64_t depthB = k * (n / 16); + uint64_t depthC = m * (n / 16); + + auto a0 = + rewriter.create(loc, rewriter.getI64Type()); + auto b0 = + rewriter.create(loc, rewriter.getI64Type()); + auto c0 = + rewriter.create(loc, rewriter.getI64Type()); + c0->setAttr("col", rewriter.getI64IntegerAttr(4)); + + auto a1 = rewriter.create( + loc, rewriter.getI64Type(), aMem, a0.getBank(), + cstI64(rewriter, loc, depthA), cstI64(rewriter, loc, strideA)); + auto b1 = rewriter.create( + loc, rewriter.getI64Type(), bMem, b0.getBank(), + cstI64(rewriter, loc, depthB), cstI64(rewriter, loc, strideB)); + auto c1 = rewriter.create( + loc, rewriter.getI64Type(), a1.getBankOut(), b1.getBankOut(), + c0.getBank(), cstI64(rewriter, loc, k), cstI64(rewriter, loc, 0)); + auto c2 = rewriter.create( + loc, rewriter.getI64Type(), cMem, c1.getWrBankOut(), + cstI64(rewriter, loc, depthC), cstI64(rewriter, loc, strideC)); + + rewriter.create(loc, a1.getBankOut()); + rewriter.create(loc, b1.getBankOut()); + rewriter.create(loc, c2.getBankOut()); + + rewriter.eraseOp(op); + return success(); + } +}; + +// TransposeToBankSSAPattern removed - TransposeOp no longer has memref operands + +// Im2colToBankSSAPattern removed - Im2colOp no longer has memref operands + +// QuantToBankSSAPattern removed - QuantOp no longer has memref operands + +// DequantToBankSSAPattern removed - DequantOp no longer has memref operands + +class LowerBuckyballToBankSSAPass + : public PassWrapper> { +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(LowerBuckyballToBankSSAPass) + StringRef getArgument() const final { return "lower-buckyball-to-bank-ssa"; } + StringRef getDescription() const final { + return "Lower bb_matmul to explicit bank-SSA ops."; + } + + void runOnOperation() override { + RewritePatternSet patterns(&getContext()); + patterns.add(&getContext()); + // TransposeToBankSSAPattern, Im2colToBankSSAPattern, QuantToBankSSAPattern, + // DequantToBankSSAPattern removed - these operations no longer have memref + // operands + if (failed(applyPatternsGreedily(getOperation(), std::move(patterns)))) + signalPassFailure(); + } +}; + +} // namespace + +namespace mlir { +namespace buddy { +void registerLowerBuckyballToBankSSAPass() { + PassRegistration(); +} +} // namespace buddy +} // namespace mlir diff --git a/compiler/src/Conversion/LowerBuckyball/ReportBankUsagePass.cpp b/compiler/src/Conversion/LowerBuckyball/ReportBankUsagePass.cpp new file mode 100644 index 00000000..7d1dba41 --- /dev/null +++ b/compiler/src/Conversion/LowerBuckyball/ReportBankUsagePass.cpp @@ -0,0 +1,173 @@ +//====- ReportBankUsagePass.cpp - Report physical bank usage +//---------------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Pass/Pass.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" + +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/Support/raw_ostream.h" + +#include +#include + +using namespace mlir; +using namespace buddy; + +namespace { + +class ReportBankUsagePass + : public PassWrapper> { +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(ReportBankUsagePass) + ReportBankUsagePass() = default; + ReportBankUsagePass(const ReportBankUsagePass &) {} + + StringRef getArgument() const final { return "report-bank-usage"; } + StringRef getDescription() const final { + return "Report physical bank occupancy from bb_mset alloc/release " + "timeline."; + } + + Option bankNum{*this, "bank_num", + llvm::cl::desc("Number of physical banks."), + llvm::cl::init(16)}; + Option verbose{*this, "verbose", + llvm::cl::desc("Print per-event timeline."), + llvm::cl::init(false)}; + + void runOnOperation() override { + func::FuncOp func = getOperation(); + if (bankNum <= 0) { + func.emitError("report-bank-usage: bank_num must be > 0"); + signalPassFailure(); + return; + } + + llvm::SmallVector used(bankNum, 0); + llvm::DenseMap allocSize; + int64_t cur = 0; + int64_t peak = 0; + int64_t allocCnt = 0; + int64_t relCnt = 0; + int64_t evt = 0; + + auto getConstI64 = [&](Value v) -> std::optional { + auto c = v.getDefiningOp(); + if (!c) + return std::nullopt; + auto ai = dyn_cast(c.getValue()); + if (!ai) + return std::nullopt; + return ai.getInt(); + }; + + for (Block &blk : func.getBlocks()) { + for (Operation &op : blk.getOperations()) { + auto mset = dyn_cast(op); + if (!mset) + continue; + ++evt; + auto bid = getConstI64(mset.getBankId()); + if (!bid) { + func.emitError("report-bank-usage: mset bank id must be constant"); + signalPassFailure(); + return; + } + if (*bid < 0 || *bid >= bankNum) { + func.emitError("report-bank-usage: bank id out of range"); + signalPassFailure(); + return; + } + + if (mset.getAlloc()) { + int64_t row = mset.getRow(); + int64_t col = mset.getCol(); + int64_t need = row * col; + if (row <= 0 || col <= 0 || need <= 0 || *bid + need > bankNum) { + func.emitError("report-bank-usage: invalid alloc row/col or range"); + signalPassFailure(); + return; + } + if (allocSize.count(*bid)) { + func.emitError("report-bank-usage: double alloc on same base bank"); + signalPassFailure(); + return; + } + for (int64_t i = 0; i < need; ++i) { + if (used[*bid + i]) { + func.emitError("report-bank-usage: overlapping bank allocation"); + signalPassFailure(); + return; + } + used[*bid + i] = 1; + } + allocSize[*bid] = need; + cur += need; + peak = std::max(peak, cur); + ++allocCnt; + if (verbose) { + llvm::errs() << "[bank-usage] " << func.getName() << " evt=" << evt + << " alloc b" << *bid << " row=" << row + << " col=" << col << " cur=" << cur << "/" << bankNum + << "\n"; + } + } else { + auto it = allocSize.find(*bid); + if (it == allocSize.end()) { + func.emitError("report-bank-usage: release without prior alloc"); + signalPassFailure(); + return; + } + int64_t need = it->second; + for (int64_t i = 0; i < need; ++i) { + used[*bid + i] = 0; + } + allocSize.erase(it); + cur -= need; + ++relCnt; + if (verbose) { + llvm::errs() << "[bank-usage] " << func.getName() << " evt=" << evt + << " release b" << *bid << " size=" << need + << " cur=" << cur << "/" << bankNum << "\n"; + } + } + } + } + + llvm::errs() << "[bank-usage] " << func.getName() << " peak=" << peak << "/" + << bankNum << " alloc=" << allocCnt << " release=" << relCnt + << " leaked=" << allocSize.size() << "\n"; + + if (!allocSize.empty()) { + func.emitError("report-bank-usage: leaked allocations at function end"); + signalPassFailure(); + } + } +}; + +} // namespace + +namespace mlir { +namespace buddy { +void registerReportBankUsagePass() { PassRegistration(); } +} // namespace buddy +} // namespace mlir diff --git a/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp b/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp new file mode 100644 index 00000000..4eb6c101 --- /dev/null +++ b/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp @@ -0,0 +1,532 @@ +//====- LowerTileToBuckyball.cpp - Tile to Buckyball Lowering Pass -------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file defines the pass to lower Tile dialect to Buckyball dialect. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Dialect/MemRef/IR/MemRef.h" +#include "mlir/Dialect/SCF/IR/SCF.h" +#include "mlir/IR/BuiltinOps.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/Pass/Pass.h" +#include "mlir/Transforms/DialectConversion.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" +#include "Tile/TileDialect.h" +#include "Tile/TileOps.h" + +using namespace mlir; +using namespace buddy; + +//===----------------------------------------------------------------------===// +// Helper: ceil division +//===----------------------------------------------------------------------===// + +static size_t ceilDiv(size_t a, size_t b) { return (a + b - 1) / b; } + +// Matches `BuckyballMatMulLowering` mvout depthC = M * (N/16) on C (i32 acc, +// cols=4). Spike/bebop: BANK_SIZE / (cols*16) = 16384/64 = 256 lines per mvout. +static constexpr size_t kMaxAccMvoutDepthLines = 256; + +static size_t cMvoutDepthLines(size_t mEl, size_t nEl) { + return mEl * (nEl / 16); +} + +// `BuckyballMatMulLowering` mvin: depthA = M*(K/16), depthB = K*(N/16); i8 bank +// line_bytes=16. Spike/bebop: BANK_SIZE/16 = 1024 lines per mvin. +static constexpr size_t kMaxI8MvinDepthLines = 1024; + +static size_t aMvinDepthLines(size_t mEl, size_t kEl) { + return mEl * (kEl / 16); +} + +static size_t bMvinDepthLines(size_t kEl, size_t nEl) { + return kEl * (nEl / 16); +} + +//===----------------------------------------------------------------------===// +// Tile Matmul Lowering Pattern +//===----------------------------------------------------------------------===// + +namespace { + +class TileMatMulLowering : public OpRewritePattern { + // Compute bank rows needed: A occupies mTileLen*kTileLen, B occupies + // kTileLen*nTileLen + size_t computeBankRows(size_t mTileLen, size_t nTileLen, + size_t kTileLen) const { + return mTileLen * kTileLen + kTileLen * nTileLen; + } + +public: + explicit TileMatMulLowering(MLIRContext *context, int64_t lane, int64_t warp, + int64_t bankDepth, int64_t /*bankNum*/) + : OpRewritePattern(context), lane(lane), warp(warp), + bankDepth(bankDepth) {} + + LogicalResult matchAndRewrite(tile::TileMatMulOp tileMatMulOp, + PatternRewriter &rewriter) const override { + Location loc = tileMatMulOp.getLoc(); + + Value aMemArray = tileMatMulOp.getAMemArray(); + Value bMemArray = tileMatMulOp.getBMemArray(); + Value cMemArray = tileMatMulOp.getCMemArray(); + + auto aType = cast(aMemArray.getType()); + auto bType = cast(bMemArray.getType()); + + // A[M][K], B[K][N], C[M][N] + auto aShape = aType.getShape(); + auto bShape = bType.getShape(); + size_t M = aShape[aShape.size() - 2]; + size_t K = aShape[aShape.size() - 1]; + size_t N = bShape[bShape.size() - 1]; + + // Block counts per axis: each unit is lane×lane×warp elements (see + // mTileSize below). + const size_t mMeta = lane; + const size_t nMeta = lane; + const size_t kMeta = warp; + + // Pad dimensions to multiples of meta lengths + const size_t mPad = ceilDiv(M, mMeta) * mMeta; + const size_t nPad = ceilDiv(N, nMeta) * nMeta; + const size_t kPad = ceilDiv(K, kMeta) * kMeta; + + // Tile lengths: grow K first so kTileSize is fixed when checking mvin B + // depth on N; then N (c mvout + mvin B), then M (mvin A). Order avoids + // oversized depthA/B. + size_t mTileLen = 1, nTileLen = 1, kTileLen = 1; + + while ((kTileLen + 1) * kMeta <= kPad && + computeBankRows(1, 1, kTileLen + 1) <= (size_t)bankDepth) + kTileLen++; + + const size_t kTileSize = kTileLen * kMeta; + + while ((nTileLen + 1) * nMeta <= nPad && + computeBankRows(1, nTileLen + 1, kTileLen) <= (size_t)bankDepth && + cMvoutDepthLines(mMeta, (nTileLen + 1) * nMeta) <= + kMaxAccMvoutDepthLines && + bMvinDepthLines(kTileSize, (nTileLen + 1) * nMeta) <= + kMaxI8MvinDepthLines) + nTileLen++; + + while ((mTileLen + 1) * mMeta <= mPad && + computeBankRows(mTileLen + 1, nTileLen, kTileLen) <= + (size_t)bankDepth && + cMvoutDepthLines((mTileLen + 1) * mMeta, nTileLen * nMeta) <= + kMaxAccMvoutDepthLines && + aMvinDepthLines((mTileLen + 1) * mMeta, kTileSize) <= + kMaxI8MvinDepthLines) + mTileLen++; + + const size_t mTileSize = mTileLen * mMeta; + const size_t nTileSize = nTileLen * nMeta; + + const size_t mTileNum = ceilDiv(mPad, mTileSize); + const size_t nTileNum = ceilDiv(nPad, nTileSize); + const size_t kTileNum = ceilDiv(kPad, kTileSize); + + // Generate tiled computation + for (size_t k0 = 0; k0 < kTileNum; k0++) { + for (size_t m0 = 0; m0 < mTileNum; m0++) { + for (size_t n0 = 0; n0 < nTileNum; n0++) { + size_t mStart = m0 * mTileSize, kStart = k0 * kTileSize, + nStart = n0 * nTileSize; + size_t mLen = std::min(mTileSize, mPad - mStart); + size_t kLen = std::min(kTileSize, kPad - kStart); + size_t nLen = std::min(nTileSize, nPad - nStart); + + Value aTile = rewriter.create( + loc, aMemArray, + SmallVector{rewriter.getIndexAttr(mStart), + rewriter.getIndexAttr(kStart)}, + SmallVector{rewriter.getIndexAttr(mLen), + rewriter.getIndexAttr(kLen)}, + SmallVector{rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1)}); + Value bTile = rewriter.create( + loc, bMemArray, + SmallVector{rewriter.getIndexAttr(kStart), + rewriter.getIndexAttr(nStart)}, + SmallVector{rewriter.getIndexAttr(kLen), + rewriter.getIndexAttr(nLen)}, + SmallVector{rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1)}); + Value cTile = rewriter.create( + loc, cMemArray, + SmallVector{rewriter.getIndexAttr(mStart), + rewriter.getIndexAttr(nStart)}, + SmallVector{rewriter.getIndexAttr(mLen), + rewriter.getIndexAttr(nLen)}, + SmallVector{rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1)}); + + rewriter.create(loc, aTile, bTile, cTile); + } + } + } + + rewriter.eraseOp(tileMatMulOp); + return success(); + } + +private: + int64_t lane, warp, bankDepth; +}; + +} // namespace + +//===----------------------------------------------------------------------===// +// Tile Transpose Lowering Pattern +//===----------------------------------------------------------------------===// + +namespace { + +class TileTransposeLowering : public OpRewritePattern { + // Transpose needs both input and output in bank: 2 * rows * cols + size_t computeBankRows(size_t rowsTileLen, size_t colsTileLen) const { + return rowsTileLen * colsTileLen * 2; + } + +public: + explicit TileTransposeLowering(MLIRContext *context, int64_t lane, + int64_t /*warp*/, int64_t bankDepth, + int64_t /*bankNum*/) + : OpRewritePattern(context), lane(lane), bankDepth(bankDepth) {} + + LogicalResult matchAndRewrite(tile::TileTransposeOp tileTransposeOp, + PatternRewriter &rewriter) const override { + Location loc = tileTransposeOp.getLoc(); + + Value inputMemArray = tileTransposeOp.getAMemArray(); + Value outputMemArray = tileTransposeOp.getBMemArray(); + + auto inputType = cast(inputMemArray.getType()); + auto outputType = cast(outputMemArray.getType()); + auto inShape = inputType.getShape(); + auto outShape = outputType.getShape(); + + size_t Rows = inShape[inShape.size() - 2]; + size_t Cols = inShape[inShape.size() - 1]; + + if (outShape[outShape.size() - 2] != (int64_t)Cols || + outShape[outShape.size() - 1] != (int64_t)Rows) + return tileTransposeOp.emitError( + "Output shape must be transposed of input shape"); + + const size_t rowMeta = lane, colMeta = lane; + const size_t rowPad = ceilDiv(Rows, rowMeta) * rowMeta; + const size_t colPad = ceilDiv(Cols, colMeta) * colMeta; + + size_t rowTileLen = 1, colTileLen = 1; + + while ((rowTileLen + 1) * rowMeta <= rowPad && + computeBankRows(rowTileLen + 1, colTileLen) <= (size_t)bankDepth) + rowTileLen++; + + while ((colTileLen + 1) * colMeta <= colPad && + computeBankRows(rowTileLen, colTileLen + 1) <= (size_t)bankDepth) + colTileLen++; + + const size_t rowTileSize = rowTileLen * rowMeta; + const size_t colTileSize = colTileLen * colMeta; + const size_t rowTileNum = ceilDiv(rowPad, rowTileSize); + const size_t colTileNum = ceilDiv(colPad, colTileSize); + + for (size_t r0 = 0; r0 < rowTileNum; r0++) { + for (size_t c0 = 0; c0 < colTileNum; c0++) { + size_t rStart = r0 * rowTileSize, cStart = c0 * colTileSize; + size_t rLen = std::min(rowTileSize, rowPad - rStart); + size_t cLen = std::min(colTileSize, colPad - cStart); + + Value inTile = rewriter.create( + loc, inputMemArray, + SmallVector{rewriter.getIndexAttr(rStart), + rewriter.getIndexAttr(cStart)}, + SmallVector{rewriter.getIndexAttr(rLen), + rewriter.getIndexAttr(cLen)}, + SmallVector{rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1)}); + Value outTile = rewriter.create( + loc, outputMemArray, + SmallVector{rewriter.getIndexAttr(cStart), + rewriter.getIndexAttr(rStart)}, + SmallVector{rewriter.getIndexAttr(cLen), + rewriter.getIndexAttr(rLen)}, + SmallVector{rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1)}); + + // TODO: TransposeOp now uses bankId-only interface, not memref + // This needs to be rewritten to use bank allocation + mvin/mvout + // rewriter.create(loc, inTile, outTile); + } + } + + rewriter.eraseOp(tileTransposeOp); + return success(); + } + +private: + int64_t lane, bankDepth; +}; + +} // namespace + +//===----------------------------------------------------------------------===// +// Tile Conv2d Lowering Pattern +//===----------------------------------------------------------------------===// + +namespace { + +class TileConv2dLowering : public OpRewritePattern { +public: + explicit TileConv2dLowering(MLIRContext *context, int64_t lane, + int64_t /*warp*/, int64_t bankDepth, + int64_t /*bankNum*/) + : OpRewritePattern(context), lane(lane), bankDepth(bankDepth) {} + + LogicalResult matchAndRewrite(tile::TileConv2dOp op, + PatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + + Value input = op.getInput(); // [N, H, W, C] + Value filter = op.getFilter(); // [KH, KW, C, OC] + Value output = op.getOutput(); // [N, OH, OW, OC] + + auto inType = cast(input.getType()); + auto filterType = cast(filter.getType()); + auto outType = cast(output.getType()); + + auto inShape = inType.getShape(); + auto fShape = filterType.getShape(); + auto outShape = outType.getShape(); + + int64_t N = inShape[0], H = inShape[1], W = inShape[2], C = inShape[3]; + int64_t KH = fShape[0], KW = fShape[1], OC = fShape[3]; + int64_t OH = outShape[1], OW = outShape[2]; + + IntegerType i64Type = rewriter.getI64Type(); + + // Im2col patch dimensions: patchRows = OH*OW, patchCols = KH*KW*C + int64_t patchCols = KH * KW * C; + + // Pad patchCols to lane boundary for matmul + int64_t patchColsPad = ceilDiv(patchCols, (int64_t)lane) * lane; + + // Tile OH*OW dimension: how many output rows per tile + // Each tile produces tileOHOW output pixels, requiring tileOHOW rows in + // patch matrix Bank constraint: patch tile (tileOHOW * patchColsPad) must + // fit in bank + int64_t tileOHOW = + std::min((int64_t)bankDepth / std::max(patchColsPad, (int64_t)1), + (int64_t)(OH * OW)); + if (tileOHOW < 1) + tileOHOW = 1; + // Align to lane boundary + tileOHOW = (tileOHOW / lane) * lane; + if (tileOHOW < lane) + tileOHOW = lane; + + int64_t totalOHOW = OH * OW; + int64_t tileNum = ceilDiv(totalOHOW, tileOHOW); + + // For each batch + for (int64_t n = 0; n < N; n++) { + for (int64_t t = 0; t < tileNum; t++) { + int64_t ohowStart = t * tileOHOW; + int64_t ohowLen = std::min(tileOHOW, totalOHOW - ohowStart); + + // Compute start row/col in input space for im2col + int64_t startRow = (ohowStart / OW); // starting OH index + int64_t startCol = (ohowStart % OW); // starting OW index + + // Allocate temporary patch matrix: [ohowLen, patchColsPad] + auto elemType = inType.getElementType(); + auto patchType = MemRefType::get({ohowLen, patchColsPad}, elemType); + Value patchBuf = rewriter.create(loc, patchType); + + // Create subview of input for batch n, then collapse to 2D for im2col + Value inBatch = rewriter.create( + loc, input, + SmallVector{ + rewriter.getIndexAttr(n), rewriter.getIndexAttr(0), + rewriter.getIndexAttr(0), rewriter.getIndexAttr(0)}, + SmallVector{ + rewriter.getIndexAttr(1), rewriter.getIndexAttr(H), + rewriter.getIndexAttr(W), rewriter.getIndexAttr(C)}, + SmallVector{ + rewriter.getIndexAttr(1), rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1), rewriter.getIndexAttr(1)}); + + // Collapse [1, H, W, C] → [H, W*C] for im2col input + auto collapseIn = rewriter.create( + loc, inBatch, SmallVector{{0, 1}, {2, 3}}); + + // Im2col: rearrange input patches into columns + Value kRowVal = rewriter.create( + loc, i64Type, rewriter.getI64IntegerAttr(KH)); + Value kColVal = rewriter.create( + loc, i64Type, rewriter.getI64IntegerAttr(KW)); + Value inRowVal = rewriter.create( + loc, i64Type, rewriter.getI64IntegerAttr(H)); + Value inColVal = rewriter.create( + loc, i64Type, rewriter.getI64IntegerAttr(W * C)); + Value startRowVal = rewriter.create( + loc, i64Type, rewriter.getI64IntegerAttr(startRow)); + Value startColVal = rewriter.create( + loc, i64Type, rewriter.getI64IntegerAttr(startCol)); + + // TODO: Im2colOp now uses bankId-only interface, not memref + // This needs to be rewritten to use bank allocation + mvin/mvout + // rewriter.create(loc, collapseIn, patchBuf, + // kRowVal, + // kColVal, inRowVal, inColVal, + // startRowVal, startColVal); + + // Reshape filter [KH, KW, C, OC] → [KH*KW*C, OC] for matmul + Value filterReshaped = rewriter.create( + loc, filter, SmallVector{{0, 1, 2}, {3}}); + + // Create output subview for this tile: [ohowLen, OC] + Value outBatch = rewriter.create( + loc, output, + SmallVector{ + rewriter.getIndexAttr(n), rewriter.getIndexAttr(0), + rewriter.getIndexAttr(0), rewriter.getIndexAttr(0)}, + SmallVector{ + rewriter.getIndexAttr(1), rewriter.getIndexAttr(OH), + rewriter.getIndexAttr(OW), rewriter.getIndexAttr(OC)}, + SmallVector{ + rewriter.getIndexAttr(1), rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1), rewriter.getIndexAttr(1)}); + + // Collapse [1, OH, OW, OC] → [OH*OW, OC] + auto collapseOut = rewriter.create( + loc, outBatch, SmallVector{{0, 1, 2}, {3}}); + + // Subview for the current tile rows + Value outTile = rewriter.create( + loc, collapseOut, + SmallVector{rewriter.getIndexAttr(ohowStart), + rewriter.getIndexAttr(0)}, + SmallVector{rewriter.getIndexAttr(ohowLen), + rewriter.getIndexAttr(OC)}, + SmallVector{rewriter.getIndexAttr(1), + rewriter.getIndexAttr(1)}); + + // MatMul: patch[ohowLen, patchCols] x filter[patchCols, OC] → + // out[ohowLen, OC] + rewriter.create(loc, patchBuf, filterReshaped, + outTile); + + // Free temporary buffer + rewriter.create(loc, patchBuf); + } + } + + rewriter.eraseOp(op); + return success(); + } + +private: + int64_t lane, bankDepth; +}; + +} // namespace + +//===----------------------------------------------------------------------===// +// Pattern Registration +//===----------------------------------------------------------------------===// + +void populateLowerTileToBuckyballConversionPatterns(RewritePatternSet &patterns, + int64_t lane, int64_t warp, + int64_t bankDepth, + int64_t bankNum) { + patterns.add(patterns.getContext(), lane, warp, bankDepth, + bankNum); + patterns.add(patterns.getContext(), lane, warp, + bankDepth, bankNum); + patterns.add(patterns.getContext(), lane, warp, bankDepth, + bankNum); +} + +//===----------------------------------------------------------------------===// +// LowerTileToBuckyball Pass +//===----------------------------------------------------------------------===// + +namespace { +class LowerTileToBuckyballPass + : public PassWrapper> { +public: + MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(LowerTileToBuckyballPass) + StringRef getArgument() const final { return "convert-tile-to-buckyball"; } + StringRef getDescription() const final { + return "Convert Tile dialect to Buckyball dialect"; + } + LowerTileToBuckyballPass() = default; + LowerTileToBuckyballPass(const LowerTileToBuckyballPass &) {} + + Option lane{*this, "lane", llvm::cl::desc("Hardware lane width."), + llvm::cl::init(16)}; + Option warp{*this, "warp", llvm::cl::desc("Warp depth."), + llvm::cl::init(16)}; + Option bankDepth{*this, "bank_depth", + llvm::cl::desc("Bank depth (rows per bank)."), + llvm::cl::init(4096)}; + Option bankNum{*this, "bank_num", llvm::cl::desc("Number of banks."), + llvm::cl::init(8)}; + + void getDependentDialects(DialectRegistry ®istry) const override { + registry.insert(); + } + + void runOnOperation() override; +}; +} // namespace + +void LowerTileToBuckyballPass::runOnOperation() { + MLIRContext *context = &getContext(); + ModuleOp module = getOperation(); + + ConversionTarget target(*context); + target.addLegalDialect(); + target.addIllegalDialect(); + + RewritePatternSet patterns(context); + populateLowerTileToBuckyballConversionPatterns(patterns, lane, warp, + bankDepth, bankNum); + + if (failed(applyPartialConversion(module, target, std::move(patterns)))) + signalPassFailure(); +} + +namespace mlir { +namespace buddy { +void registerLowerTileToBuckyballPass() { + PassRegistration(); +} +} // namespace buddy +} // namespace mlir diff --git a/compiler/src/Dialect/Buckyball/Buckyball.td b/compiler/src/Dialect/Buckyball/Buckyball.td new file mode 100644 index 00000000..1d2d6aa1 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/Buckyball.td @@ -0,0 +1,48 @@ +//===-- Buckyball.td - Buckyball dialect operations -------*- tablegen -*-===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This is the main file for the Buckyball dialect. +// It includes all Ball-specific operation definitions. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_OPS +#define BUCKYBALL_OPS + +// Base definitions and common operations +include "BuckyballBase.td" + +// Ball-specific operations +include "VecBall.td" +include "ReluBall.td" +include "TransposeBall.td" +include "Im2colBall.td" +include "SystolicArrayBall.td" +include "QuantBall.td" +include "DequantBall.td" + +// Additional operations (MatMul, Print, Counter) +include "BuckyballOps.td" + +// Bank SSA operations +include "BuckyballBankSSA.td" + +// LLVM intrinsic wrapper operations +include "BuckyballIntrinsics.td" + +// Note: GemminiBall operations are not included yet + +#endif // BUCKYBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/BuckyballBankSSA.td b/compiler/src/Dialect/Buckyball/BuckyballBankSSA.td new file mode 100644 index 00000000..51f8f9e4 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/BuckyballBankSSA.td @@ -0,0 +1,108 @@ +//===-- BuckyballBankSSA.td - Bank SSA operations ------------ tablegen --===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file defines Bank SSA operations for the Buckyball dialect. +// These are intermediate representation operations used for bank allocation +// and optimization passes. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_BANK_SSA +#define BUCKYBALL_BANK_SSA + +//===----------------------------------------------------------------------===// +// Bank SSA Operations +//===----------------------------------------------------------------------===// + +def BankAllocOp : Buckyball_Op<"bank_alloc"> { + let summary = "Allocate a virtual on-chip bank resource"; + let description = [{ + Create a virtual bank handle in SSA form. + - row/col encode bank-array shape used by allocator. + - The result i64 is a virtual bank handle, not physical id. + }]; + let arguments = (ins + DefaultValuedAttr:$row, + DefaultValuedAttr:$col); + let results = (outs I64:$bank); + let assemblyFormat = "attr-dict"; +} + +def BankReleaseOp : Buckyball_Op<"bank_release"> { + let summary = "Release a virtual bank handle"; + let arguments = (ins I64:$bank); + let assemblyFormat = "$bank attr-dict `:` type($bank)"; +} + +def BankMvinOp : Buckyball_Op<"bank_mvin"> { + let summary = "Load into a virtual bank handle"; + let arguments = (ins MemRefRankOf<[AnyType], [2]>:$input, I64:$bank, I64:$depth, + I64:$stride); + let results = (outs I64:$bankOut); + let assemblyFormat = + "$input $bank $depth $stride attr-dict `:` type($input) type($bank) type($depth) type($stride)"; +} + +def BankMvoutOp : Buckyball_Op<"bank_mvout"> { + let summary = "Store from a virtual bank handle"; + let arguments = (ins MemRefRankOf<[AnyType], [2]>:$output, I64:$bank, I64:$depth, + I64:$stride); + let results = (outs I64:$bankOut); + let assemblyFormat = + "$output $bank $depth $stride attr-dict `:` type($output) type($bank) type($depth) type($stride)"; +} + +def BankMulWarp16Op : Buckyball_Op<"bank_mul_warp16"> { + let summary = "Warp-16 matmul using virtual bank handles"; + let arguments = (ins I64:$op1Bank, I64:$op2Bank, I64:$wrBank, I64:$iter, I64:$mode); + let results = (outs I64:$wrBankOut); + let assemblyFormat = + "$op1Bank $op2Bank $wrBank $iter $mode attr-dict `:` type($op1Bank) type($op2Bank) type($wrBank) type($iter) type($mode)"; +} + +def BankTransposeOp : Buckyball_Op<"bank_transpose"> { + let summary = "Transpose using virtual bank handles"; + let arguments = (ins I64:$inBank, I64:$outBank, I64:$iter, I64:$mode); + let results = (outs I64:$outBankOut); + let assemblyFormat = "$inBank $outBank $iter $mode attr-dict `:` type($inBank) type($outBank) type($iter) type($mode)"; +} + +def BankIm2colOp : Buckyball_Op<"bank_im2col"> { + let summary = "Im2col using virtual bank handles"; + let arguments = (ins I64:$inBank, I64:$outBank, I64:$krow, I64:$kcol, + I64:$inrow, I64:$incol, I64:$startrow, I64:$startcol); + let results = (outs I64:$outBankOut); + let assemblyFormat = + "$inBank $outBank $krow $kcol $inrow $incol $startrow $startcol attr-dict `:` type($inBank) type($outBank) type($krow) type($kcol) type($inrow) type($incol) type($startrow) type($startcol)"; +} + +def BankQuantOp : Buckyball_Op<"bank_quant"> { + let summary = "Quantization using virtual bank handles"; + let arguments = (ins I64:$inBank, I64:$outBank, I64:$iter, I64:$scale); + let results = (outs I64:$outBankOut); + let assemblyFormat = + "$inBank $outBank $iter $scale attr-dict `:` type($inBank) type($outBank) type($iter) type($scale)"; +} + +def BankDequantOp : Buckyball_Op<"bank_dequant"> { + let summary = "Dequantization using virtual bank handles"; + let arguments = (ins I64:$inBank, I64:$outBank, I64:$iter, I64:$scale); + let results = (outs I64:$outBankOut); + let assemblyFormat = + "$inBank $outBank $iter $scale attr-dict `:` type($inBank) type($outBank) type($iter) type($scale)"; +} + +#endif // BUCKYBALL_BANK_SSA diff --git a/compiler/src/Dialect/Buckyball/BuckyballBase.td b/compiler/src/Dialect/Buckyball/BuckyballBase.td new file mode 100644 index 00000000..7149dffb --- /dev/null +++ b/compiler/src/Dialect/Buckyball/BuckyballBase.td @@ -0,0 +1,103 @@ +//===-- BuckyballBase.td - Buckyball base definitions ----------*- tablegen -*-===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file defines the Buckyball dialect and common base operations. +// Common operations include data movement instructions (mvin, mvout, mset, fence) +// that are used by all Ball implementations. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_BASE +#define BUCKYBALL_BASE + +include "mlir/Dialect/LLVMIR/LLVMOpBase.td" +include "mlir/IR/AttrTypeBase.td" +include "mlir/IR/PatternBase.td" + +//===----------------------------------------------------------------------===// +// Buckyball dialect definition +//===----------------------------------------------------------------------===// + +def Buckyball_Dialect : Dialect { + let name = "buckyball"; + let cppNamespace = "::buddy::buckyball"; + let summary = "Dialect for RISC-V Buckyball NPU extension"; + let description = [{ + Buckyball is an NPU Design Framework with composable Ball units. + Each Ball is a specialized compute unit that can be independently + developed and combined with others. + }]; +} + +//===----------------------------------------------------------------------===// +// Base operation class +//===----------------------------------------------------------------------===// + +class Buckyball_Op traits = []> : + Op {} + +//===----------------------------------------------------------------------===// +// Common data movement operations (used by all Balls) +//===----------------------------------------------------------------------===// + +def MvinOp : Buckyball_Op<"mvin"> { + let summary = "Load data from memory to scratchpad bank"; + let description = [{ + Loads data from DRAM to scratchpad bank. + Corresponds to bb_mvin instruction (funct7=33). + }]; + let arguments = (ins MemRefRankOf<[AnyType], [2]>:$input, + I64:$addr, I64:$depth, I64:$stride); + let assemblyFormat = "$input $addr $depth $stride attr-dict `:` " + "type($input) type($addr) type($depth) type($stride)"; +} + +def MvoutOp : Buckyball_Op<"mvout"> { + let summary = "Store data from scratchpad bank to memory"; + let description = [{ + Stores data from scratchpad bank to DRAM. + Corresponds to bb_mvout instruction (funct7=16). + }]; + let arguments = (ins MemRefRankOf<[AnyType], [2]>:$output, + I64:$addr, I64:$depth, I64:$stride); + let assemblyFormat = "$output $addr $depth $stride attr-dict `:` " + "type($output) type($addr) type($depth) type($stride)"; +} + +def MsetOp : Buckyball_Op<"mset"> { + let summary = "Allocate or release scratchpad bank memory"; + let description = [{ + Allocates or releases scratchpad bank memory. + Corresponds to bb_mset instruction (funct7=32). + }]; + let arguments = (ins I64:$bankId, + DefaultValuedAttr:$alloc, + DefaultValuedAttr:$row, + DefaultValuedAttr:$col); + let assemblyFormat = "$bankId attr-dict `:` type($bankId)"; +} + +def FenceOp : Buckyball_Op<"fence"> { + let summary = "Memory fence for synchronization"; + let description = [{ + Ensures all previous memory operations complete before proceeding. + Corresponds to bb_fence instruction (funct7=0). + }]; + let arguments = (ins); + let assemblyFormat = "attr-dict"; +} + +#endif // BUCKYBALL_BASE diff --git a/compiler/src/Dialect/Buckyball/BuckyballDialect.h b/compiler/src/Dialect/Buckyball/BuckyballDialect.h new file mode 100644 index 00000000..8397706b --- /dev/null +++ b/compiler/src/Dialect/Buckyball/BuckyballDialect.h @@ -0,0 +1,25 @@ +//===- BuckyballDialect.h - MLIR Dialect for RISC-V Gemmmini extension +//------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_BUCKYBALLDIALECT_H +#define BUCKYBALL_BUCKYBALLDIALECT_H + +#include "mlir/IR/Dialect.h" + +#include "Dialect/Buckyball/BuckyballDialect.h.inc" + +#endif // BUCKYBALL_BUCKYBALLDIALECT_H diff --git a/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td b/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td new file mode 100644 index 00000000..cab4d6e3 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td @@ -0,0 +1,136 @@ +//===-- BuckyballIntrinsics.td - Intrinsic operations ----*- tablegen -*-===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file defines LLVM intrinsic wrapper operations for Buckyball. +// These operations map directly to RISC-V custom instructions via LLVM intrinsics. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_INTRINSICS +#define BUCKYBALL_INTRINSICS + +//===----------------------------------------------------------------------===// +// Base class for intrinsic operations +//===----------------------------------------------------------------------===// + +class Buckyball_IntrOp traits = []> : + Buckyball_Op {} + +//===----------------------------------------------------------------------===// +// Common intrinsic operations +//===----------------------------------------------------------------------===// + +def MsetIntrOp : Buckyball_IntrOp<"mset_intr"> { + let summary = "LLVM intrinsic for bb_mset instruction"; + let description = [{ + Wrapper for int_riscv_bb_mset LLVM intrinsic. + Maps to bb_mset custom instruction (funct7=32). + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def FenceIntrOp : Buckyball_IntrOp<"fence_intr"> { + let summary = "LLVM intrinsic for bb_fence instruction"; + let description = [{ + Wrapper for int_riscv_bb_fence LLVM intrinsic. + Maps to bb_fence custom instruction (funct7=0). + }]; + let arguments = (ins); + let assemblyFormat = "attr-dict"; +} + +def MvinIntrOp : Buckyball_IntrOp<"mvin_intr"> { + let summary = "LLVM intrinsic for bb_mvin instruction"; + let description = [{ + Wrapper for int_riscv_bb_mvin LLVM intrinsic. + Maps to bb_mvin custom instruction (funct7=33). + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def MvoutIntrOp : Buckyball_IntrOp<"mvout_intr"> { + let summary = "LLVM intrinsic for bb_mvout instruction"; + let description = [{ + Wrapper for int_riscv_bb_mvout LLVM intrinsic. + Maps to bb_mvout custom instruction (funct7=16). + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def MulWarp16IntrOp : Buckyball_IntrOp<"mul_warp16_intr"> { + let summary = "LLVM intrinsic for bb_mul_warp16 instruction"; + let description = [{ + Wrapper for int_riscv_bb_mul_warp16 LLVM intrinsic. + Maps to bb_mul_warp16 custom instruction. + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def TransposeIntrOp : Buckyball_IntrOp<"transpose_intr"> { + let summary = "LLVM intrinsic for bb_transpose instruction"; + let description = [{ + Wrapper for int_riscv_bb_transpose LLVM intrinsic. + Maps to bb_transpose custom instruction. + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def Im2colIntrOp : Buckyball_IntrOp<"im2col_intr"> { + let summary = "LLVM intrinsic for bb_im2col instruction"; + let description = [{ + Wrapper for int_riscv_bb_im2col LLVM intrinsic. + Maps to bb_im2col custom instruction. + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def QuantIntrOp : Buckyball_IntrOp<"quant_intr"> { + let summary = "LLVM intrinsic for bb_quant instruction"; + let description = [{ + Wrapper for int_riscv_bb_quant LLVM intrinsic. + Maps to bb_quant custom instruction. + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def DequantIntrOp : Buckyball_IntrOp<"dequant_intr"> { + let summary = "LLVM intrinsic for bb_dequant instruction"; + let description = [{ + Wrapper for int_riscv_bb_dequant LLVM intrinsic. + Maps to bb_dequant custom instruction. + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +def ReluIntrOp : Buckyball_IntrOp<"relu_intr"> { + let summary = "LLVM intrinsic for bb_relu instruction"; + let description = [{ + Wrapper for int_riscv_bb_relu LLVM intrinsic. + Maps to bb_relu custom instruction. + }]; + let arguments = (ins I64:$rs1, I64:$rs2); + let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; +} + +#endif // BUCKYBALL_INTRINSICS diff --git a/compiler/src/Dialect/Buckyball/BuckyballOps.h b/compiler/src/Dialect/Buckyball/BuckyballOps.h new file mode 100644 index 00000000..9d1e45d9 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/BuckyballOps.h @@ -0,0 +1,29 @@ +//===- BuckyballOps.h - MLIR Dialect for RISC-V Buckyball extension +//---------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_BUCKYBALLOPS_H +#define BUCKYBALL_BUCKYBALLOPS_H + +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/Dialect.h" +#include "mlir/IR/OpDefinition.h" +#include "mlir/Interfaces/SideEffectInterfaces.h" + +#define GET_OP_CLASSES +#include "Dialect/Buckyball/Buckyball.h.inc" +#endif // BUCKYBALL_BUCKYBALLOPS_H diff --git a/compiler/src/Dialect/Buckyball/BuckyballOps.td b/compiler/src/Dialect/Buckyball/BuckyballOps.td new file mode 100644 index 00000000..1c2507cc --- /dev/null +++ b/compiler/src/Dialect/Buckyball/BuckyballOps.td @@ -0,0 +1,80 @@ +//===-- BuckyballOps.td - Additional Buckyball operations ---- tablegen --===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file defines additional operations for the Buckyball dialect including +// MatMul, debugging, and profiling operations. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_ADDITIONAL_OPS +#define BUCKYBALL_ADDITIONAL_OPS + +// Hardware-level matrix multiplication operation +def MatMulOp : Buckyball_Op<"matmul"> { + let summary = "Hardware-level matrix multiplication"; + let description = [{ + Perform fixed-size matrix multiplication that fits in accelerator resources. + This operation represents a complete matrix multiplication tile that: + - Fits within the scratchpad and accumulator constraints + - Performs data movement (mvin) for input tiles + - Executes computation using warp-level parallelism + - Writes back results (mvout) to main memory + }]; + let arguments = (ins MemRefRankOf<[AnyType], [2]>:$aMemArray, + MemRefRankOf<[AnyType], [2]>:$bMemArray, + MemRefRankOf<[AnyType], [2]>:$cMemArray); + let assemblyFormat = [{$aMemArray $bMemArray $cMemArray attr-dict `:` + type($aMemArray) type($bMemArray) type($cMemArray)}]; +} + +// Debugging and profiling operations +def PrintMemRefOp : Buckyball_Op<"print_memref"> { + let summary = "Print memref contents for debugging"; + let description = [{ + Print the contents of a memref for debugging purposes. + }]; + let arguments = (ins AnyMemRef:$input); + let assemblyFormat = "$input attr-dict `:` type($input)"; +} + +def PrintScalarOp : Buckyball_Op<"print_scalar"> { + let summary = "Print scalar value for debugging"; + let description = [{ + Print a scalar value for debugging purposes. + }]; + let arguments = (ins AnyType:$value); + let assemblyFormat = "$value attr-dict `:` type($value)"; +} + +def CounterStartOp : Buckyball_Op<"counter_start"> { + let summary = "Start performance counter"; + let description = [{ + Start a performance counter for profiling. + }]; + let arguments = (ins); + let assemblyFormat = "attr-dict"; +} + +def CounterStopOp : Buckyball_Op<"counter_stop"> { + let summary = "Stop performance counter"; + let description = [{ + Stop a performance counter and report results. + }]; + let arguments = (ins); + let assemblyFormat = "attr-dict"; +} + +#endif // BUCKYBALL_ADDITIONAL_OPS diff --git a/compiler/src/Dialect/Buckyball/DequantBall.td b/compiler/src/Dialect/Buckyball/DequantBall.td new file mode 100644 index 00000000..c8305221 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/DequantBall.td @@ -0,0 +1,31 @@ +//===-- DequantBall.td - DequantBall operations ------------*- tablegen -*-===// +// +// DequantBall operations for dequantization. +// +//===----------------------------------------------------------------------===// + +#ifndef DEQUANTBALL_OPS +#define DEQUANTBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// DequantBall operations +//===----------------------------------------------------------------------===// + +def DequantOp : Buckyball_Op<"dequant"> { + let summary = "Dequantize fixed-point to floating-point"; + let description = [{ + Dequantizes fixed-point values back to floating-point representation. + Corresponds to bb_dequant instruction (funct7=52). + Belongs to DequantBall (bid=6). + ISA: bb_dequant(bank_id, wr_bank_id, iter, scale_fp32) + }]; + let arguments = (ins I64:$inputBankId, I64:$outputBankId, + I64:$iter, I64:$scale); + let assemblyFormat = "$inputBankId `,` $outputBankId `,` " + "$iter `,` $scale attr-dict `:` " + "type($inputBankId)"; +} + +#endif // DEQUANTBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/IR/BuckyballDialect.cpp b/compiler/src/Dialect/Buckyball/IR/BuckyballDialect.cpp new file mode 100644 index 00000000..e76bc067 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/IR/BuckyballDialect.cpp @@ -0,0 +1,45 @@ +//===- BuckyballDialect.cpp - MLIR Buckyball dialect implementation +//----------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file implements the Buckyball dialect and its operations. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/LLVMIR/LLVMTypes.h" +#include "mlir/Dialect/Vector/IR/VectorOps.h" +#include "mlir/IR/Builders.h" +#include "mlir/IR/DialectImplementation.h" +#include "mlir/IR/OpImplementation.h" +#include "mlir/IR/TypeUtilities.h" +#include "llvm/ADT/TypeSwitch.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" +using namespace mlir; +using namespace buddy::buckyball; + +#include "Buckyball/BuckyballDialect.cpp.inc" + +#define GET_OP_CLASSES +#include "Buckyball/Buckyball.cpp.inc" + +void BuckyballDialect::initialize() { + addOperations< +#define GET_OP_LIST +#include "Buckyball/Buckyball.cpp.inc" + >(); +} diff --git a/compiler/src/Dialect/Buckyball/Im2colBall.td b/compiler/src/Dialect/Buckyball/Im2colBall.td new file mode 100644 index 00000000..574858d5 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/Im2colBall.td @@ -0,0 +1,35 @@ +//===-- Im2colBall.td - Im2colBall operations --------------*- tablegen -*-===// +// +// Im2colBall operations for image-to-column transformation. +// +//===----------------------------------------------------------------------===// + +#ifndef IM2COLBALL_OPS +#define IM2COLBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// Im2colBall operations +//===----------------------------------------------------------------------===// + +def Im2colOp : Buckyball_Op<"im2col"> { + let summary = "Image-to-column transformation for convolution"; + let description = [{ + Transforms image data into column format for efficient convolution. + Corresponds to bb_im2col instruction (funct7=48). + Belongs to Im2colBall (bid=3). + ISA: bb_im2col(op1_bank_id, wr_bank_id, krow, kcol, inrow, incol, startrow, startcol) + }]; + let arguments = (ins I64:$inputBankId, I64:$outputBankId, + I64:$krow, I64:$kcol, + I64:$inrow, I64:$incol, + I64:$startrow, I64:$startcol); + let assemblyFormat = "$inputBankId `,` $outputBankId `,` " + "$krow `,` $kcol `,` " + "$inrow `,` $incol `,` " + "$startrow `,` $startcol attr-dict `:` " + "type($inputBankId)"; +} + +#endif // IM2COLBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/QuantBall.td b/compiler/src/Dialect/Buckyball/QuantBall.td new file mode 100644 index 00000000..2ed0b950 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/QuantBall.td @@ -0,0 +1,31 @@ +//===-- QuantBall.td - QuantBall operations ----------------*- tablegen -*-===// +// +// QuantBall operations for quantization. +// +//===----------------------------------------------------------------------===// + +#ifndef QUANTBALL_OPS +#define QUANTBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// QuantBall operations +//===----------------------------------------------------------------------===// + +def QuantOp : Buckyball_Op<"quant"> { + let summary = "Quantize floating-point to fixed-point"; + let description = [{ + Quantizes floating-point values to fixed-point representation. + Corresponds to bb_quant instruction (funct7=51). + Belongs to QuantBall (bid=5). + ISA: bb_quant(bank_id, wr_bank_id, iter, scale_fp32) + }]; + let arguments = (ins I64:$inputBankId, I64:$outputBankId, + I64:$iter, I64:$scale); + let assemblyFormat = "$inputBankId `,` $outputBankId `,` " + "$iter `,` $scale attr-dict `:` " + "type($inputBankId)"; +} + +#endif // QUANTBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/ReluBall.td b/compiler/src/Dialect/Buckyball/ReluBall.td new file mode 100644 index 00000000..908ed2cf --- /dev/null +++ b/compiler/src/Dialect/Buckyball/ReluBall.td @@ -0,0 +1,30 @@ +//===-- ReluBall.td - ReluBall operations ------------------*- tablegen -*-===// +// +// ReluBall operations for ReLU activation function. +// +//===----------------------------------------------------------------------===// + +#ifndef RELUBALL_OPS +#define RELUBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// ReluBall operations +//===----------------------------------------------------------------------===// + +def ReluOp : Buckyball_Op<"relu"> { + let summary = "ReLU activation function"; + let description = [{ + Applies ReLU (Rectified Linear Unit) activation: max(0, x). + Corresponds to bb_relu instruction (funct7=50). + Belongs to ReluBall (bid=1). + }]; + let arguments = (ins I64:$inputBankId, I64:$outputBankId, + I64:$depth, I64:$stride); + let assemblyFormat = "$inputBankId `,` $outputBankId `,` " + "$depth `,` $stride attr-dict `:` " + "type($inputBankId)"; +} + +#endif // RELUBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/SystolicArrayBall.td b/compiler/src/Dialect/Buckyball/SystolicArrayBall.td new file mode 100644 index 00000000..429b5e79 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/SystolicArrayBall.td @@ -0,0 +1,30 @@ +//===-- SystolicArrayBall.td - SystolicArrayBall ops -------*- tablegen -*-===// +// +// SystolicArrayBall operations for systolic array computation. +// +//===----------------------------------------------------------------------===// + +#ifndef SYSTOLICARRAYBALL_OPS +#define SYSTOLICARRAYBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// SystolicArrayBall operations +//===----------------------------------------------------------------------===// + +def SystolicOp : Buckyball_Op<"systolic"> { + let summary = "Systolic array computation (BBFP multiply)"; + let description = [{ + Performs computation using systolic array with block floating point. + Corresponds to bb_bbfp_mul instruction (funct7=65). + Belongs to SystolicArrayBall (bid=4). + }]; + let arguments = (ins I64:$op1BankId, I64:$op2BankId, + I64:$resultBankId, I64:$config); + let assemblyFormat = "$op1BankId `,` $op2BankId `,` " + "$resultBankId `,` $config attr-dict `:` " + "type($op1BankId)"; +} + +#endif // SYSTOLICARRAYBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/Transform.h b/compiler/src/Dialect/Buckyball/Transform.h new file mode 100644 index 00000000..98beaf3e --- /dev/null +++ b/compiler/src/Dialect/Buckyball/Transform.h @@ -0,0 +1,36 @@ +//===- Transform.h - MLIR Dialect for RISC-V Buckyball extension ---------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_TRANSLATE_H +#define BUCKYBALL_TRANSLATE_H + +#include + +namespace mlir { + +class LLVMConversionTarget; +class LLVMTypeConverter; +class RewritePatternSet; +using OwningRewritePatternList = RewritePatternSet; + +void populateBuckyballLegalizeForLLVMExportPatterns( + LLVMTypeConverter &converter, RewritePatternSet &patterns, int64_t lane, + int64_t warp, int64_t bankDepth, int64_t bankNum); +void configureBuckyballLegalizeForExportTarget(LLVMConversionTarget &target); + +} // namespace mlir + +#endif // BUCKYBALL_TRANSLATE_H diff --git a/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp b/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp new file mode 100644 index 00000000..b5f9a0c8 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp @@ -0,0 +1,527 @@ +//===- LegalizeForLLVMExport.cpp - Prepare Buckyball for LLVM translation +//---===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// Lowers Buckyball dialect ops to RISC-V custom intrinsics. Bit layouts match +// bb-tests/workloads/lib/bbhw/isa/isa.h and the per-instruction *.c wrappers +// +//===----------------------------------------------------------------------===// + +#include "mlir/Conversion/LLVMCommon/ConversionTarget.h" +#include "mlir/Conversion/LLVMCommon/Pattern.h" +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/Dialect/MemRef/IR/MemRef.h" +#include "mlir/IR/BuiltinOps.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/IR/Types.h" +#include "mlir/Pass/Pass.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/Support/ErrorHandling.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" +#include "Buckyball/Transform.h" + +using namespace mlir; +using namespace buddy::buckyball; + +namespace { + +//===----------------------------------------------------------------------===// +// isa.h FIELD(val, start_bit, end_bit) +//===----------------------------------------------------------------------===// + +static uint64_t fieldBits(uint64_t val, int startBit, int endBit) { + uint64_t width = endBit - startBit + 1; + uint64_t mask = (1ULL << width) - 1; + return (val & mask) << startBit; +} + +//===----------------------------------------------------------------------===// +// MemRef / arith helpers +//===----------------------------------------------------------------------===// + +static Value cstI64(OpBuilder &b, Location loc, uint64_t v) { + return b.create(loc, b.getI64Type(), + b.getI64IntegerAttr(v)); +} + +static int64_t elemByteSize(Type el) { + if (auto it = dyn_cast(el)) + return it.getWidth() / 8; + if (auto ft = dyn_cast(el)) + return ft.getWidth() / 8; + return -1; +} + +/// Base aligned pointer + linear byte offset for strided subviews +/// (ExtractAlignedPointer alone misses StridedLayoutAttr offset). +static Value extractPtr(OpBuilder &b, Location loc, Value memref) { + auto ty = cast(memref.getType()); + int64_t eb = elemByteSize(ty.getElementType()); + if (eb <= 0) + llvm_unreachable( + "bb memref intrinsic: unsupported element type for ptr offset"); + auto meta = b.create(loc, memref); + Value base = meta.getBaseBuffer(); + Value off = meta.getOffset(); + Value baseIdx = b.create( + loc, b.getIndexType(), base); + Value baseI64 = b.create(loc, b.getI64Type(), baseIdx); + Value offI64 = b.create(loc, b.getI64Type(), off); + Value offBytes = offI64; + if (eb != 1) { + offBytes = b.create(loc, offI64, cstI64(b, loc, eb)); + } + return b.create(loc, baseI64, offBytes); +} + +/// rs1 = BB_BANK0 | BB_BANK1 | BB_BANK2 | BB_ITER — isa.h +/// BB_BANK0/BB_BANK1: read bank ids (rbank); BB_BANK2: write bank id (wbank). +/// Each id masked to 10 bits; iter to 34 bits (bits [63:30]). +static Value packRs1BanksIter(OpBuilder &b, Location loc, Value rBank0, + Value rBank1, Value wBank, Value iter) { + Value rBank0Field = + b.create(loc, rBank0, cstI64(b, loc, 0x3FF)); + Value rBank1Field = b.create( + loc, b.create(loc, rBank1, cstI64(b, loc, 0x3FF)), + cstI64(b, loc, 10)); + Value wBankField = b.create( + loc, b.create(loc, wBank, cstI64(b, loc, 0x3FF)), + cstI64(b, loc, 20)); + Value iterField = b.create( + loc, b.create(loc, iter, cstI64(b, loc, (1ULL << 34) - 1)), + cstI64(b, loc, 30)); + Value rs1Part01 = b.create(loc, rBank0Field, rBank1Field); + Value rs1Part012 = b.create(loc, rs1Part01, wBankField); + return b.create(loc, rs1Part012, iterField); +} + +/// mvin/mvout: only BB_BANK0 (rbank); BB_BANK1/BB_BANK2 unset (`33_mvin.c`, +/// `16_mvout.c`). +static Value packRs1BankIter(OpBuilder &b, Location loc, Value bankId, + Value depth) { + Value z = cstI64(b, loc, 0); + return packRs1BanksIter(b, loc, bankId, z, z, depth); +} + +/// rs2 = FIELD(mem, 0, 38) | FIELD(stride, 39, 57) +static Value packRs2MemStride(OpBuilder &b, Location loc, Value memAddr, + Value stride) { + Value mem = + b.create(loc, memAddr, cstI64(b, loc, (1ULL << 39) - 1)); + Value s = + b.create(loc, stride, cstI64(b, loc, (1ULL << 19) - 1)); + Value sHi = b.create(loc, s, cstI64(b, loc, 39)); + return b.create(loc, mem, sHi); +} + +/// bb_mset(bank_id, alloc, row, col) — rs1 = BB_BANK0 only (32_mset.c) +static void emitMset(OpBuilder &b, Location loc, uint64_t bankId, uint64_t row, + uint64_t col, uint64_t alloc) { + uint64_t rs1 = fieldBits(bankId, 0, 9); + uint64_t rs2 = + fieldBits(row, 0, 4) | fieldBits(col, 5, 9) | fieldBits(alloc, 10, 10); + b.create(loc, cstI64(b, loc, rs1), cstI64(b, loc, rs2)); +} + +//===----------------------------------------------------------------------===// +// ForwardOperands / ReturnOpTypeConversion +//===----------------------------------------------------------------------===// + +template +class ForwardOperands : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + LogicalResult + matchAndRewrite(OpTy op, typename OpTy::Adaptor adaptor, + ConversionPatternRewriter &rewriter) const final { + if (adaptor.getOperands().getTypes() == op->getOperands().getTypes()) + return rewriter.notifyMatchFailure(op, "operand types already match"); + rewriter.modifyOpInPlace(op, + [&]() { op->setOperands(adaptor.getOperands()); }); + return success(); + } +}; + +class ReturnOpTypeConversion : public OpConversionPattern { +public: + using OpConversionPattern::OpConversionPattern; + LogicalResult + matchAndRewrite(func::ReturnOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const final { + rewriter.modifyOpInPlace(op, + [&]() { op->setOperands(adaptor.getOperands()); }); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Fence — lowers to int_riscv_bb_fence / BB_FENCE when +buddyext-bb. +//===----------------------------------------------------------------------===// + +struct BuckyballFenceLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + LogicalResult + matchAndRewrite(FenceOp op, OpAdaptor, + ConversionPatternRewriter &rewriter) const override { + rewriter.replaceOpWithNewOp(op); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Mset +//===----------------------------------------------------------------------===// + +struct BuckyballMsetLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + LogicalResult + matchAndRewrite(MsetOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value bankId = adaptor.getBankId(); + Value rs1 = rewriter.create(loc, bankId, + cstI64(rewriter, loc, 0x3FF)); + uint64_t allocBit = op.getAlloc() ? 1u : 0u; + uint64_t rowVal = op.getAlloc() ? static_cast(op.getRow()) : 0u; + uint64_t colVal = op.getAlloc() ? static_cast(op.getCol()) : 0u; + uint64_t rs2Val = fieldBits(rowVal, 0, 4) | fieldBits(colVal, 5, 9) | + fieldBits(allocBit, 10, 10); + rewriter.replaceOpWithNewOp(op, rs1, + cstI64(rewriter, loc, rs2Val)); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Mvin / Mvout — 33_mvin.c, 16_mvout.c +//===----------------------------------------------------------------------===// + +struct BuckyballMvinLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + LogicalResult + matchAndRewrite(MvinOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value input = op.getInput(); + Value bankId = adaptor.getAddr(); + Value stride = adaptor.getStride(); + + Value memAddr = extractPtr(rewriter, loc, input); + Value depth = adaptor.getDepth(); + + Value rs1 = packRs1BankIter(rewriter, loc, bankId, depth); + Value rs2 = packRs2MemStride(rewriter, loc, memAddr, stride); + + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +struct BuckyballMvoutLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + LogicalResult + matchAndRewrite(MvoutOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value output = op.getOutput(); + Value bankId = adaptor.getAddr(); + + Value memAddr = extractPtr(rewriter, loc, output); + Value depth = adaptor.getDepth(); + Value stride = adaptor.getStride(); + + Value rs1 = packRs1BankIter(rewriter, loc, bankId, depth); + Value rs2 = packRs2MemStride(rewriter, loc, memAddr, stride); + + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// MatMul — mvin A, mvin B, mul_warp16 (iter = K), mvout C +// Shapes A[M,K], B[K,N], C[M,N]; K and N must be multiples of 16 (i8 cols=1 +// line size). +//===----------------------------------------------------------------------===// + +struct BuckyballMatMulLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(MatMulOp op, OpAdaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value aMem = op.getAMemArray(); + Value bMem = op.getBMemArray(); + Value cMem = op.getCMemArray(); + + auto aTy = cast(aMem.getType()); + auto bTy = cast(bMem.getType()); + auto cTy = cast(cMem.getType()); + + if (!aTy.hasStaticShape() || !bTy.hasStaticShape() || !cTy.hasStaticShape()) + return rewriter.notifyMatchFailure( + op, "bb_matmul requires static memref shapes"); + + uint64_t M = aTy.getShape()[0]; + uint64_t K = aTy.getShape()[1]; + uint64_t Kb = bTy.getShape()[0]; + uint64_t N = bTy.getShape()[1]; + if (K != Kb) + return rewriter.notifyMatchFailure(op, "inner dimensions must match"); + + if (K % 16 != 0 || N % 16 != 0) + return rewriter.notifyMatchFailure( + op, "K and N must be multiples of 16 for this lowering"); + + const uint64_t aBank = 0, bBank = 1, cBank = 2; + uint64_t depthA = M * (K / 16); + uint64_t depthB = K * (N / 16); + uint64_t depthC = M * (N / 16); + + emitMset(rewriter, loc, aBank, 1, 1, 1); + emitMset(rewriter, loc, bBank, 1, 1, 1); + emitMset(rewriter, loc, cBank, 1, 4, 1); + + Value aPtr = extractPtr(rewriter, loc, aMem); + Value bPtr = extractPtr(rewriter, loc, bMem); + Value cPtr = extractPtr(rewriter, loc, cMem); + // Row-major tile A[M,K] is dense: 16-byte mvin lines scan contiguous + // storage (stride=1). + Value strideA = cstI64(rewriter, loc, 1); + // B/C may be subviews: row pitch in memory uses parent leading dim, not + // tile width. bebop mvin/mvout: byte step = 16*rs2_stride*line_blocks -> + // rs2_stride = rowElem/16. + SmallVector bStrides, cStrides; + int64_t bOff = 0, cOff = 0; + if (failed(bTy.getStridesAndOffset(bStrides, bOff)) || bStrides.size() < 2) + return rewriter.notifyMatchFailure( + op, "bb_matmul B memref needs static strides (use subview with " + "strided layout)"); + if (failed(cTy.getStridesAndOffset(cStrides, cOff)) || cStrides.size() < 2) + return rewriter.notifyMatchFailure( + op, "bb_matmul C memref needs static strides (use subview with " + "strided layout)"); + if (ShapedType::isDynamic(bStrides[0]) || + ShapedType::isDynamic(cStrides[0])) + return rewriter.notifyMatchFailure( + op, "bb_matmul: static row stride required"); + if (bStrides[0] % 16 != 0 || cStrides[0] % 16 != 0) + return rewriter.notifyMatchFailure( + op, "bb_matmul: row stride (elements) must be divisible by 16"); + + Value strideBN = cstI64(rewriter, loc, (uint64_t)bStrides[0] / 16); + Value strideCN = cstI64(rewriter, loc, (uint64_t)cStrides[0] / 16); + + Value rs1A = packRs1BankIter(rewriter, loc, cstI64(rewriter, loc, aBank), + cstI64(rewriter, loc, depthA)); + Value rs2A = packRs2MemStride(rewriter, loc, aPtr, strideA); + rewriter.create(loc, rs1A, rs2A); + + Value rs1B = packRs1BankIter(rewriter, loc, cstI64(rewriter, loc, bBank), + cstI64(rewriter, loc, depthB)); + Value rs2B = packRs2MemStride(rewriter, loc, bPtr, strideBN); + rewriter.create(loc, rs1B, rs2B); + + uint64_t rs1Mul = fieldBits(aBank, 0, 9) | fieldBits(bBank, 10, 19) | + fieldBits(cBank, 20, 29) | fieldBits(K, 30, 63); + uint64_t rs2Mul = fieldBits(0, 0, 63); + rewriter.create(loc, cstI64(rewriter, loc, rs1Mul), + cstI64(rewriter, loc, rs2Mul)); + + Value rs1C = packRs1BankIter(rewriter, loc, cstI64(rewriter, loc, cBank), + cstI64(rewriter, loc, depthC)); + Value rs2C = packRs2MemStride(rewriter, loc, cPtr, strideCN); + rewriter.create(loc, rs1C, rs2C); + + emitMset(rewriter, loc, aBank, 0, 0, 0); + emitMset(rewriter, loc, bBank, 0, 0, 0); + emitMset(rewriter, loc, cBank, 0, 0, 0); + + rewriter.eraseOp(op); + return success(); + } +}; + +struct BuckyballMulWarp16Lowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(MulWarp16Op op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value rs1 = packRs1BanksIter(rewriter, loc, adaptor.getOp1BankId(), + adaptor.getOp2BankId(), adaptor.getWrBankId(), + adaptor.getIter()); + Value rs2 = adaptor.getMode(); + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Transpose — 49_transpose.c +// ISA: bb_transpose(op1_bank_id, wr_bank_id, iter, mode) +// rs1 = BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter) +// rs2 = FIELD(mode, 0, 63) +//===----------------------------------------------------------------------===// + +struct BuckyballTransposeLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(TransposeOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value rs1 = packRs1BanksIter(rewriter, loc, adaptor.getInputBankId(), + cstI64(rewriter, loc, 0), + adaptor.getOutputBankId(), adaptor.getIter()); + Value rs2 = adaptor.getMode(); + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Im2col — 48_im2col.c +//===----------------------------------------------------------------------===// + +struct BuckyballIm2colLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(Im2colOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + IntegerType i64 = rewriter.getI64Type(); + + // Pack rs1: BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) + Value bank0Shift = rewriter.create( + loc, i64, adaptor.getInputBankId(), cstI64(rewriter, loc, 0)); + Value bank2Shift = rewriter.create( + loc, i64, adaptor.getOutputBankId(), cstI64(rewriter, loc, 20)); + Value rs1 = rewriter.create(loc, i64, bank0Shift, bank2Shift); + + // Pack rs2: fields at specific bit positions + Value rs2 = adaptor.getKcol(); + rs2 = rewriter.create( + loc, rs2, + rewriter.create(loc, adaptor.getKrow(), + cstI64(rewriter, loc, 4))); + rs2 = rewriter.create( + loc, rs2, + rewriter.create(loc, adaptor.getIncol(), + cstI64(rewriter, loc, 8))); + rs2 = rewriter.create( + loc, rs2, + rewriter.create(loc, adaptor.getInrow(), + cstI64(rewriter, loc, 13))); + rs2 = rewriter.create( + loc, rs2, + rewriter.create(loc, adaptor.getStartcol(), + cstI64(rewriter, loc, 23))); + rs2 = rewriter.create( + loc, rs2, + rewriter.create(loc, adaptor.getStartrow(), + cstI64(rewriter, loc, 28))); + + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Quant / Dequant — 51_quant.c, 52_dequant.c (rs2 = fp32 bits, bits [31:0]) +//===----------------------------------------------------------------------===// + +struct BuckyballQuantLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(QuantOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value rs1 = packRs1BanksIter(rewriter, loc, adaptor.getInputBankId(), + cstI64(rewriter, loc, 0), + adaptor.getOutputBankId(), adaptor.getIter()); + Value rs2 = adaptor.getScale(); + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +struct BuckyballDequantLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(DequantOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value rs1 = packRs1BanksIter(rewriter, loc, adaptor.getInputBankId(), + cstI64(rewriter, loc, 0), + adaptor.getOutputBankId(), adaptor.getIter()); + Value rs2 = adaptor.getScale(); + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +} // namespace + +//===----------------------------------------------------------------------===// +// Registration +//===----------------------------------------------------------------------===// + +void mlir::populateBuckyballLegalizeForLLVMExportPatterns( + LLVMTypeConverter &converter, RewritePatternSet &patterns, int64_t lane, + int64_t warp, int64_t bankDepth, int64_t bankNum) { + (void)lane; + (void)warp; + (void)bankDepth; + (void)bankNum; + + patterns + .add, ForwardOperands, + ForwardOperands>(converter, &converter.getContext()); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); + patterns.add(converter); +} + +void mlir::configureBuckyballLegalizeForExportTarget( + LLVMConversionTarget &target) { + target.addLegalOp(); + target.addIllegalOp(); + target.addLegalDialect(); + target.addLegalDialect(); +} diff --git a/compiler/src/Dialect/Buckyball/TransposeBall.td b/compiler/src/Dialect/Buckyball/TransposeBall.td new file mode 100644 index 00000000..85800813 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/TransposeBall.td @@ -0,0 +1,31 @@ +//===-- TransposeBall.td - TransposeBall operations --------*- tablegen -*-===// +// +// TransposeBall operations for matrix transpose. +// +//===----------------------------------------------------------------------===// + +#ifndef TRANSPOSEBALL_OPS +#define TRANSPOSEBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// TransposeBall operations +//===----------------------------------------------------------------------===// + +def TransposeOp : Buckyball_Op<"transpose"> { + let summary = "Matrix transpose operation"; + let description = [{ + Transposes a matrix in scratchpad memory. + Corresponds to bb_transpose instruction (funct7=49). + Belongs to TransposeBall (bid=2). + ISA: bb_transpose(op1_bank_id, wr_bank_id, iter, mode) + }]; + let arguments = (ins I64:$inputBankId, I64:$outputBankId, + I64:$iter, I64:$mode); + let assemblyFormat = "$inputBankId `,` $outputBankId `,` " + "$iter `,` $mode attr-dict `:` " + "type($inputBankId)"; +} + +#endif // TRANSPOSEBALL_OPS diff --git a/compiler/src/Dialect/Buckyball/VecBall.td b/compiler/src/Dialect/Buckyball/VecBall.td new file mode 100644 index 00000000..359fa996 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/VecBall.td @@ -0,0 +1,30 @@ +//===-- VecBall.td - VecBall operations --------------------*- tablegen -*-===// +// +// VecBall operations for matrix multiplication using warp-16 systolic array. +// +//===----------------------------------------------------------------------===// + +#ifndef VECBALL_OPS +#define VECBALL_OPS + +include "BuckyballBase.td" + +//===----------------------------------------------------------------------===// +// VecBall operations +//===----------------------------------------------------------------------===// + +def MulWarp16Op : Buckyball_Op<"mul_warp16"> { + let summary = "Warp-16 matrix multiplication"; + let description = [{ + Performs matrix multiplication using 16x16 systolic array. + Corresponds to bb_mul_warp16 instruction (funct7=64). + Belongs to VecBall (bid=0). + }]; + let arguments = (ins I64:$op1BankId, I64:$op2BankId, + I64:$wrBankId, I64:$iter, I64:$mode); + let assemblyFormat = "$op1BankId `,` $op2BankId `,` $wrBankId `,` " + "$iter `,` $mode attr-dict `:` " + "type($op1BankId)"; +} + +#endif // VECBALL_OPS diff --git a/compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.cpp b/compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.cpp new file mode 100644 index 00000000..c6485b8c --- /dev/null +++ b/compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.cpp @@ -0,0 +1,69 @@ +//======- BuckyballToLLVMIRTranslation.cpp - Translate Buckyball to LLVM +// IR--====// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This file implements a translation between the Buckyball dialect and LLVM IR. +// +//===----------------------------------------------------------------------===// + +#include "mlir/IR/Operation.h" +#include "mlir/Target/LLVMIR/ModuleTranslation.h" + +#include "backend/include/llvm/IR/IntrinsicsRISCV.h" +#include "llvm/IR/IRBuilder.h" + +#include "Buckyball/BuckyballDialect.h" +#include "Buckyball/BuckyballOps.h" +#include "Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.h" + +using namespace mlir; +using namespace mlir::LLVM; +using namespace buddy; + +namespace { +/// Implementation of the dialect interface that converts operations belonging +/// to the Buckyball dialect to LLVM IR. +class BuckyballDialectLLVMIRTranslationInterface + : public LLVMTranslationDialectInterface { +public: + using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface; + + /// Translates the given operation to LLVM IR using the provided IR builder + /// and saving the state in `moduleTranslation`. + LogicalResult + convertOperation(Operation *op, llvm::IRBuilderBase &builder, + LLVM::ModuleTranslation &moduleTranslation) const final { + Operation &opInst = *op; +#include "Buckyball/BuckyballConversions.inc" + + return failure(); + } +}; +} // end namespace + +void buddy::registerBuckyballDialectTranslation(DialectRegistry ®istry) { + registry.insert(); + registry.addExtension( + +[](MLIRContext *ctx, buckyball::BuckyballDialect *dialect) { + dialect->addInterfaces(); + }); +} + +void buddy::registerBuckyballDialectTranslation(MLIRContext &context) { + DialectRegistry registry; + registerBuckyballDialectTranslation(registry); + context.appendDialectRegistry(registry); +} diff --git a/compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.h b/compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.h new file mode 100644 index 00000000..2244a52f --- /dev/null +++ b/compiler/src/Target/LLVMIR/Dialect/Buckyball/BuckyballToLLVMIRTranslation.h @@ -0,0 +1,34 @@ +//===- BuckyballToLLVMIRTranslation.h - Buckyball to LLVM IR --------*- C++ +//-*-===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// This provides registration calls for Buckyball dialect to LLVM IR +// translation. +// +//===----------------------------------------------------------------------===// + +#ifndef TARGET_LLVMIR_DIALECT_BUCKYBALL_BUCKYBALLTOLLVMIRTRANSLATION_H +#define TARGET_LLVMIR_DIALECT_BUCKYBALL_BUCKYBALLTOLLVMIRTRANSLATION_H + +#include "mlir/IR/DialectRegistry.h" +#include "mlir/IR/MLIRContext.h" + +namespace buddy { +void registerBuckyballDialectTranslation(mlir::DialectRegistry ®istry); +void registerBuckyballDialectTranslation(mlir::MLIRContext &context); +} // namespace buddy + +#endif diff --git a/compiler/thirdparty/buddy-mlir b/compiler/thirdparty/buddy-mlir index ce66e6f3..7c418421 160000 --- a/compiler/thirdparty/buddy-mlir +++ b/compiler/thirdparty/buddy-mlir @@ -1 +1 @@ -Subproject commit ce66e6f397171d4fad298cac093c939478634661 +Subproject commit 7c418421b1cea313246cb68fbe78706db518d66d diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 4990486b..c4851e3b 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -131,6 +131,7 @@ if run_step "2"; then cd ${BBDIR}/compiler/thirdparty/buddy-mlir mkdir -p build && cd build cmake -G Ninja .. \ + -DBUDDY_EXTERNAL_DIALECTS_DIR=${BBDIR}/compiler/src \ -DMLIR_DIR=$PWD/../llvm/build/lib/cmake/mlir \ -DLLVM_DIR=$PWD/../llvm/build/lib/cmake/llvm \ -DLLVM_ENABLE_ASSERTIONS=ON \ From cd0396bc3fb39254b48ecb32bb8143c0407485e6 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 28 Apr 2026 05:46:59 +0800 Subject: [PATCH 229/238] [compiler] fix: fix compilation failed in buddy-mlir --- compiler/thirdparty/buddy-mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/thirdparty/buddy-mlir b/compiler/thirdparty/buddy-mlir index 7c418421..1fe6cef7 160000 --- a/compiler/thirdparty/buddy-mlir +++ b/compiler/thirdparty/buddy-mlir @@ -1 +1 @@ -Subproject commit 7c418421b1cea313246cb68fbe78706db518d66d +Subproject commit 1fe6cef746320d2d8d13e8e98df50eae93fb3555 From f7f5a4b833bc2935a60b55f27ef75f7afedc2ec4 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 28 Apr 2026 16:01:33 +0800 Subject: [PATCH 230/238] [compiler] feat: Unified Bank SSA and compute operations semantics --- bb-tests/workloads/src/CTest/toy/bbsim.ld | 4 +- .../workloads/src/tutorial/CMakeLists.txt | 2 +- bebop | 2 +- .../LowerTileToBuckyball.cpp | 59 ++++++-- .../Dialect/Buckyball/BuckyballIntrinsics.td | 141 +++++------------- .../Transforms/LegalizeForLLVMExport.cpp | 63 +++++++- compiler/src/Utils/BankUtils.h | 103 +++++++++++++ compiler/thirdparty/buddy-mlir | 2 +- 8 files changed, 255 insertions(+), 121 deletions(-) create mode 100644 compiler/src/Utils/BankUtils.h diff --git a/bb-tests/workloads/src/CTest/toy/bbsim.ld b/bb-tests/workloads/src/CTest/toy/bbsim.ld index 7d8e660d..db5be9da 100644 --- a/bb-tests/workloads/src/CTest/toy/bbsim.ld +++ b/bb-tests/workloads/src/CTest/toy/bbsim.ld @@ -1,7 +1,7 @@ /* bbsim.ld — baremetal linker script for BBSimHarness (DRAM at 0x8000_0000) */ -/* Bootrom jumps directly to 0x80000000 (ELF entry), no _start needed. */ +/* Bootrom jumps directly to 0x80000000 (ELF entry), _start must be first. */ OUTPUT_ARCH("riscv") -ENTRY(main) +ENTRY(_start) SECTIONS { . = 0x80000000; diff --git a/bb-tests/workloads/src/tutorial/CMakeLists.txt b/bb-tests/workloads/src/tutorial/CMakeLists.txt index 5eb6ba04..69b11710 100644 --- a/bb-tests/workloads/src/tutorial/CMakeLists.txt +++ b/bb-tests/workloads/src/tutorial/CMakeLists.txt @@ -4,7 +4,7 @@ project(tutorial C) # build linux version workload #------------------------------------------------------------------------------- set(CMAKE_C_COMPILER "riscv64-unknown-linux-gnu-gcc") -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gc -static") add_executable(tutorial-linux ${TUTORIAL_WORKLOAD_DIR}/tutorial.c) diff --git a/bebop b/bebop index 3fb041cf..2c08a098 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 3fb041cf517dd3eade77f08f2c9947de695f8416 +Subproject commit 2c08a098fe5dd446c666d620482ec04f00f89223 diff --git a/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp b/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp index 4eb6c101..4598c75f 100644 --- a/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp +++ b/compiler/src/Conversion/LowerTileToBuckyball/LowerTileToBuckyball.cpp @@ -32,6 +32,8 @@ #include "Tile/TileDialect.h" #include "Tile/TileOps.h" +#include "Utils/BankUtils.h" + using namespace mlir; using namespace buddy; @@ -275,9 +277,31 @@ class TileTransposeLowering : public OpRewritePattern { SmallVector{rewriter.getIndexAttr(1), rewriter.getIndexAttr(1)}); - // TODO: TransposeOp now uses bankId-only interface, not memref - // This needs to be rewritten to use bank allocation + mvin/mvout - // rewriter.create(loc, inTile, outTile); + // Allocate source and destination banks + Value srcBank = buckyball::allocBank(rewriter, loc, rLen, cLen); + Value dstBank = buckyball::allocBank(rewriter, loc, cLen, rLen); + + // Move data from memref to source bank + int64_t depth = rLen * cLen / lane; + Value srcBankAfterMvin = + buckyball::mvinBank(rewriter, loc, inTile, srcBank, depth); + + // Execute transpose operation + Value iterVal = buckyball::createI64Const(rewriter, loc, rLen); + Value modeVal = buckyball::createI64Const(rewriter, loc, 0); + Value dstBankAfterTranspose = + rewriter.create( + loc, dstBank.getType(), srcBankAfterMvin, dstBank, iterVal, + modeVal); + + // Move result from destination bank to memref + int64_t outDepth = cLen * rLen / lane; + buckyball::mvoutBank(rewriter, loc, outTile, dstBankAfterTranspose, + outDepth); + + // Release banks + buckyball::releaseBank(rewriter, loc, srcBankAfterMvin); + buckyball::releaseBank(rewriter, loc, dstBankAfterTranspose); } } @@ -395,12 +419,29 @@ class TileConv2dLowering : public OpRewritePattern { Value startColVal = rewriter.create( loc, i64Type, rewriter.getI64IntegerAttr(startCol)); - // TODO: Im2colOp now uses bankId-only interface, not memref - // This needs to be rewritten to use bank allocation + mvin/mvout - // rewriter.create(loc, collapseIn, patchBuf, - // kRowVal, - // kColVal, inRowVal, inColVal, - // startRowVal, startColVal); + // Allocate source and destination banks + Value srcBank = buckyball::allocBank(rewriter, loc, H, W * C / lane); + Value dstBank = + buckyball::allocBank(rewriter, loc, ohowLen, patchColsPad / lane); + + // Move input data to source bank + int64_t inDepth = H * W * C / lane; + Value srcBankAfterMvin = + buckyball::mvinBank(rewriter, loc, collapseIn, srcBank, inDepth); + + // Execute im2col operation + Value dstBankAfterIm2col = rewriter.create( + loc, dstBank.getType(), srcBankAfterMvin, dstBank, kRowVal, kColVal, + inRowVal, inColVal, startRowVal, startColVal); + + // Move result to patch buffer + int64_t outDepth = ohowLen * patchColsPad / lane; + buckyball::mvoutBank(rewriter, loc, patchBuf, dstBankAfterIm2col, + outDepth); + + // Release banks + buckyball::releaseBank(rewriter, loc, srcBankAfterMvin); + buckyball::releaseBank(rewriter, loc, dstBankAfterIm2col); // Reshape filter [KH, KW, C, OC] → [KH*KW*C, OC] for matmul Value filterReshaped = rewriter.create( diff --git a/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td b/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td index cab4d6e3..d5a4bcfc 100644 --- a/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td +++ b/compiler/src/Dialect/Buckyball/BuckyballIntrinsics.td @@ -26,111 +26,50 @@ // Base class for intrinsic operations //===----------------------------------------------------------------------===// -class Buckyball_IntrOp traits = []> : - Buckyball_Op {} +class Buckyball_IntrOpBase traits = []> : + LLVM_IntrOpBase overloadedResults=*/[], + /*list overloadedOperands=*/[], + /*list traits=*/traits, + /*int numResults=*/0>; //===----------------------------------------------------------------------===// // Common intrinsic operations //===----------------------------------------------------------------------===// -def MsetIntrOp : Buckyball_IntrOp<"mset_intr"> { - let summary = "LLVM intrinsic for bb_mset instruction"; - let description = [{ - Wrapper for int_riscv_bb_mset LLVM intrinsic. - Maps to bb_mset custom instruction (funct7=32). - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def FenceIntrOp : Buckyball_IntrOp<"fence_intr"> { - let summary = "LLVM intrinsic for bb_fence instruction"; - let description = [{ - Wrapper for int_riscv_bb_fence LLVM intrinsic. - Maps to bb_fence custom instruction (funct7=0). - }]; - let arguments = (ins); - let assemblyFormat = "attr-dict"; -} - -def MvinIntrOp : Buckyball_IntrOp<"mvin_intr"> { - let summary = "LLVM intrinsic for bb_mvin instruction"; - let description = [{ - Wrapper for int_riscv_bb_mvin LLVM intrinsic. - Maps to bb_mvin custom instruction (funct7=33). - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def MvoutIntrOp : Buckyball_IntrOp<"mvout_intr"> { - let summary = "LLVM intrinsic for bb_mvout instruction"; - let description = [{ - Wrapper for int_riscv_bb_mvout LLVM intrinsic. - Maps to bb_mvout custom instruction (funct7=16). - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def MulWarp16IntrOp : Buckyball_IntrOp<"mul_warp16_intr"> { - let summary = "LLVM intrinsic for bb_mul_warp16 instruction"; - let description = [{ - Wrapper for int_riscv_bb_mul_warp16 LLVM intrinsic. - Maps to bb_mul_warp16 custom instruction. - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def TransposeIntrOp : Buckyball_IntrOp<"transpose_intr"> { - let summary = "LLVM intrinsic for bb_transpose instruction"; - let description = [{ - Wrapper for int_riscv_bb_transpose LLVM intrinsic. - Maps to bb_transpose custom instruction. - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def Im2colIntrOp : Buckyball_IntrOp<"im2col_intr"> { - let summary = "LLVM intrinsic for bb_im2col instruction"; - let description = [{ - Wrapper for int_riscv_bb_im2col LLVM intrinsic. - Maps to bb_im2col custom instruction. - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def QuantIntrOp : Buckyball_IntrOp<"quant_intr"> { - let summary = "LLVM intrinsic for bb_quant instruction"; - let description = [{ - Wrapper for int_riscv_bb_quant LLVM intrinsic. - Maps to bb_quant custom instruction. - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def DequantIntrOp : Buckyball_IntrOp<"dequant_intr"> { - let summary = "LLVM intrinsic for bb_dequant instruction"; - let description = [{ - Wrapper for int_riscv_bb_dequant LLVM intrinsic. - Maps to bb_dequant custom instruction. - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} - -def ReluIntrOp : Buckyball_IntrOp<"relu_intr"> { - let summary = "LLVM intrinsic for bb_relu instruction"; - let description = [{ - Wrapper for int_riscv_bb_relu LLVM intrinsic. - Maps to bb_relu custom instruction. - }]; - let arguments = (ins I64:$rs1, I64:$rs2); - let assemblyFormat = "$rs1 `,` $rs2 attr-dict"; -} +def MsetIntrOp : Buckyball_IntrOpBase<"mset">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def FenceIntrOp : Buckyball_IntrOpBase<"fence">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def MvinIntrOp : Buckyball_IntrOpBase<"mvin">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def MvoutIntrOp : Buckyball_IntrOpBase<"mvout">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def MulWarp16IntrOp : Buckyball_IntrOpBase<"mul.warp16">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def TransposeIntrOp : Buckyball_IntrOpBase<"transpose">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def Im2colIntrOp : Buckyball_IntrOpBase<"im2col">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def QuantIntrOp : Buckyball_IntrOpBase<"quant">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def DequantIntrOp : Buckyball_IntrOpBase<"dequant">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def ReluIntrOp : Buckyball_IntrOpBase<"relu">, + Arguments<(ins LLVM_Type, LLVM_Type)>; + +def SystolicIntrOp : Buckyball_IntrOpBase<"bbfp.mul">, + Arguments<(ins LLVM_Type, LLVM_Type)>; #endif // BUCKYBALL_INTRINSICS diff --git a/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp b/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp index b5f9a0c8..44078448 100644 --- a/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp +++ b/compiler/src/Dialect/Buckyball/Transforms/LegalizeForLLVMExport.cpp @@ -180,7 +180,9 @@ struct BuckyballFenceLowering : public ConvertOpToLLVMPattern { LogicalResult matchAndRewrite(FenceOp op, OpAdaptor, ConversionPatternRewriter &rewriter) const override { - rewriter.replaceOpWithNewOp(op); + Location loc = op.getLoc(); + Value zero = cstI64(rewriter, loc, 0); + rewriter.replaceOpWithNewOp(op, zero, zero); return success(); } }; @@ -483,6 +485,52 @@ struct BuckyballDequantLowering : public ConvertOpToLLVMPattern { } }; +//===----------------------------------------------------------------------===// +// ReLU — bb_relu (funct7=50) +// ISA: bb_relu(input_bank_id, output_bank_id, depth, stride) +// rs1 = BB_BANK0(input_bank_id) | BB_BANK2(output_bank_id) | BB_ITER(depth) +// rs2 = FIELD(stride, 0, 63) +//===----------------------------------------------------------------------===// + +struct BuckyballReluLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(ReluOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value rs1 = packRs1BanksIter(rewriter, loc, adaptor.getInputBankId(), + cstI64(rewriter, loc, 0), + adaptor.getOutputBankId(), adaptor.getDepth()); + Value rs2 = adaptor.getStride(); + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Systolic — bb_bbfp_mul (funct7=65) +// ISA: bb_bbfp_mul(op1_bank_id, op2_bank_id, result_bank_id, config) +// rs1 = BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | +// BB_BANK2(result_bank_id) rs2 = FIELD(config, 0, 63) +//===----------------------------------------------------------------------===// + +struct BuckyballSystolicLowering : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(SystolicOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Value rs1 = packRs1BanksIter( + rewriter, loc, adaptor.getOp1BankId(), adaptor.getOp2BankId(), + adaptor.getResultBankId(), cstI64(rewriter, loc, 0)); + Value rs2 = adaptor.getConfig(); + rewriter.replaceOpWithNewOp(op, rs1, rs2); + return success(); + } +}; + } // namespace //===----------------------------------------------------------------------===// @@ -510,18 +558,21 @@ void mlir::populateBuckyballLegalizeForLLVMExportPatterns( patterns.add(converter); patterns.add(converter); patterns.add(converter); + patterns.add(converter); + patterns.add(converter); } void mlir::configureBuckyballLegalizeForExportTarget( LLVMConversionTarget &target) { target.addLegalOp(); + ReluIntrOp, MsetIntrOp, SystolicIntrOp>(); target.addIllegalOp(); + TransposeOp, Im2colOp, QuantOp, DequantOp, ReluOp, + SystolicOp, BankAllocOp, BankReleaseOp, BankMvinOp, + BankMvoutOp, BankMulWarp16Op, BankTransposeOp, + BankIm2colOp, BankQuantOp, BankDequantOp>(); target.addLegalDialect(); target.addLegalDialect(); + target.addLegalDialect(); } diff --git a/compiler/src/Utils/BankUtils.h b/compiler/src/Utils/BankUtils.h new file mode 100644 index 00000000..84439687 --- /dev/null +++ b/compiler/src/Utils/BankUtils.h @@ -0,0 +1,103 @@ +//===- BankUtils.h - Utilities for Bank operations -----------------------===// +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//===----------------------------------------------------------------------===// +// +// Utility functions for generating Bank-SSA operations. +// +//===----------------------------------------------------------------------===// + +#ifndef BUCKYBALL_CONVERSION_BANKUTILS_H +#define BUCKYBALL_CONVERSION_BANKUTILS_H + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/IR/Builders.h" +#include "mlir/IR/Value.h" + +#include "Buckyball/BuckyballOps.h" + +namespace buddy { +namespace buckyball { + +/// Create i64 constant. +static inline mlir::Value createI64Const(mlir::OpBuilder &b, mlir::Location loc, + int64_t val) { + return b.create(loc, b.getI64Type(), + b.getI64IntegerAttr(val)); +} + +/// Create i64 constant from uint64_t. +static inline mlir::Value createI64ConstU(mlir::OpBuilder &b, + mlir::Location loc, uint64_t val) { + return b.create(loc, b.getI64Type(), + b.getI64IntegerAttr(val)); +} + +/// Pack bit field: extract bits [startBit, endBit] from val and shift to +/// position. +static inline uint64_t packBits(uint64_t val, int startBit, int endBit) { + uint64_t width = endBit - startBit + 1; + uint64_t mask = (1ULL << width) - 1; + return (val & mask) << startBit; +} + +/// Allocate a bank with given row/col dimensions. +static inline mlir::Value allocBank(mlir::OpBuilder &b, mlir::Location loc, + int64_t row, int64_t col) { + auto i64Type = b.getI64Type(); + return b.create(loc, i64Type, b.getI64IntegerAttr(row), + b.getI64IntegerAttr(col)); +} + +/// Release a bank. +static inline void releaseBank(mlir::OpBuilder &b, mlir::Location loc, + mlir::Value bank) { + b.create(loc, bank); +} + +/// Move data from memref into bank. +static inline mlir::Value mvinBank(mlir::OpBuilder &b, mlir::Location loc, + mlir::Value memref, mlir::Value bank, + int64_t depth, int64_t stride = 1) { + mlir::Value depthVal = createI64Const(b, loc, depth); + mlir::Value strideVal = createI64Const(b, loc, stride); + return b.create(loc, bank.getType(), memref, bank, depthVal, + strideVal); +} + +/// Move data from bank to memref. +static inline mlir::Value mvoutBank(mlir::OpBuilder &b, mlir::Location loc, + mlir::Value memref, mlir::Value bank, + int64_t depth, int64_t stride = 1) { + mlir::Value depthVal = createI64Const(b, loc, depth); + mlir::Value strideVal = createI64Const(b, loc, stride); + return b.create(loc, bank.getType(), memref, bank, depthVal, + strideVal); +} + +/// Create mset operation for bank allocation/release. +static inline MsetOp createMset(mlir::OpBuilder &b, mlir::Location loc, + uint64_t bankId, bool alloc, uint64_t row, + uint64_t col) { + auto op = b.create(loc, createI64ConstU(b, loc, bankId)); + op->setAttr("alloc", b.getBoolAttr(alloc)); + op->setAttr("row", b.getI64IntegerAttr(row)); + op->setAttr("col", b.getI64IntegerAttr(col)); + return op; +} + +} // namespace buckyball +} // namespace buddy + +#endif // BUCKYBALL_CONVERSION_BANKUTILS_H diff --git a/compiler/thirdparty/buddy-mlir b/compiler/thirdparty/buddy-mlir index 1fe6cef7..a66b63ef 160000 --- a/compiler/thirdparty/buddy-mlir +++ b/compiler/thirdparty/buddy-mlir @@ -1 +1 @@ -Subproject commit 1fe6cef746320d2d8d13e8e98df50eae93fb3555 +Subproject commit a66b63efc00d4e19d36061aa8f67355f76bfa0b0 From d796817d55fce13da74fe4c30fd58fd7c3357f49 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 30 Apr 2026 01:36:45 +0800 Subject: [PATCH 231/238] [arch/sim] feat: add P2E simulation harness and configurations, remove obsolete verification and palladium target configs --- .claude/CLAUDE.md | 3 +- .gitignore | 4 + arch/src/csrc/include/monitor/trace.h | 13 - .../balldomain/configs/default.json | 3 +- .../toycore/balldomain/configs/default.json | 3 +- .../balldomain/prototype/trace/Trace.scala | 174 +------ .../prototype/trace/TraceBall.scala | 7 +- .../balldomain/prototype/trace/TraceDPI.scala | 189 ------- .../scala/framework/core/bbtile/BBTile.scala | 130 +++-- arch/src/main/scala/sims/README.md | 75 +-- arch/src/main/scala/sims/p2e/P2EHarness.scala | 14 + .../scala/sims/p2e/P2EHarnessBinders.scala | 44 ++ arch/src/main/scala/sims/p2e/P2ETop.scala | 477 ++++++++++++++++++ .../main/scala/sims/p2e/TargetConfigs.scala | 79 +++ arch/src/main/scala/sims/p2e/scu/P2ESCU.scala | 120 +++++ .../scala/sims/palladium/TargetConfigs.scala | 19 - .../main/scala/sims/verify/TargetConfig.scala | 82 --- .../workloads/lib/bbhw/isa/54_bdb_backdoor.c | 25 - ...gemmini_loop_ws.c => 80_gemmini_loop_ws.c} | 0 ...op_conv_ws.c => 96_gemmini_loop_conv_ws.c} | 0 bb-tests/workloads/lib/bbhw/isa/isa.h | 5 +- bb-tests/workloads/lib/kernel | 2 +- bb-tests/workloads/src/CTest/goban/goban.h | 46 +- .../workloads/src/CTest/toy/CMakeLists.txt | 2 - .../src/CTest/toy/bdb_backdoor_test.c | 52 -- bbdev | 2 +- bebop | 2 +- scripts/claude/README.md | 2 +- scripts/claude/mcp_server.py | 11 +- scripts/nix/build-env-tools.nix | 4 +- 30 files changed, 910 insertions(+), 679 deletions(-) create mode 100644 arch/src/main/scala/sims/p2e/P2EHarness.scala create mode 100644 arch/src/main/scala/sims/p2e/P2EHarnessBinders.scala create mode 100644 arch/src/main/scala/sims/p2e/P2ETop.scala create mode 100644 arch/src/main/scala/sims/p2e/TargetConfigs.scala create mode 100644 arch/src/main/scala/sims/p2e/scu/P2ESCU.scala delete mode 100644 arch/src/main/scala/sims/palladium/TargetConfigs.scala delete mode 100644 arch/src/main/scala/sims/verify/TargetConfig.scala delete mode 100644 bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c rename bb-tests/workloads/lib/bbhw/isa/{87_gemmini_loop_ws.c => 80_gemmini_loop_ws.c} (100%) rename bb-tests/workloads/lib/bbhw/isa/{105_gemmini_loop_conv_ws.c => 96_gemmini_loop_conv_ws.c} (100%) delete mode 100644 bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c diff --git a/.claude/CLAUDE.md b/.claude/CLAUDE.md index d91c69c3..96bac76d 100644 --- a/.claude/CLAUDE.md +++ b/.claude/CLAUDE.md @@ -19,7 +19,6 @@ A RISC-V based DSA (Domain Specific Architecture) framework. Built with Chisel 6 - `bbus/busRegister.scala` — Ball generator registration (`match case`) - `arch/src/main/scala/sims/` — simulation configs - `verilator/` — Verilator config - - `verify/` — single-Ball elaboration (`BallTopMain`) - `bb-tests/` — tests - `workloads/lib/bbhw/isa/` — ISA C macros (one `.c` file per instruction) - `workloads/src/CTest/toy/` — C test cases @@ -73,7 +72,7 @@ The project configures the `buckyball-dev` MCP server with the following tools. ### bbdev API wrappers (with automatic server lifecycle management) - `bbdev_workload_build` — build CTests - `bbdev_verilator_run(binary, config?, batch?, coverage?)` — full flow: clean -> verilog -> build -> sim -- `bbdev_verilator_verilog(config, balltype?)` — generate Verilog; `config` is required, `balltype` optional (single-Ball elaboration) +- `bbdev_verilator_verilog(config)` — generate Verilog; `config` is required - `bbdev_verilator_build(jobs?, coverage?)` — build Verilator simulator - `bbdev_verilator_sim(binary, batch?, coverage?)` — run simulation (requires prior build) - `bbdev_sardine_run(workload?, coverage?)` — run batch tests diff --git a/.gitignore b/.gitignore index 0ab80118..c41dc462 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,7 @@ out/ .Xil/ result +.codex/ CLAUDE.local.md node_modules/ @@ -32,3 +33,6 @@ index.html .kiro .tmpCRC/ __pycache__/ + +package-lock.json +package.json diff --git a/arch/src/csrc/include/monitor/trace.h b/arch/src/csrc/include/monitor/trace.h index 31f1474e..055b6ab1 100644 --- a/arch/src/csrc/include/monitor/trace.h +++ b/arch/src/csrc/include/monitor/trace.h @@ -42,19 +42,6 @@ void dpi_ctrace(unsigned char subcmd, // 0=START, 1=STOP, 2=READ unsigned int ctr_id, unsigned long long tag, unsigned long long elapsed, unsigned long long cycle); -// DPI-C functions for bank backdoor (TraceBall) -// RTL calls these to get parameters from C++ testbench -unsigned long long dpi_backdoor_get_read_addr(void); -unsigned long long dpi_backdoor_get_write_addr(void); -void dpi_backdoor_get_write_data(unsigned long long *data_lo, - unsigned long long *data_hi); -void dpi_backdoor_put_read_data(unsigned int bank_id, unsigned int row, - unsigned long long data_lo, - unsigned long long data_hi); -void dpi_backdoor_put_write_done(unsigned int bank_id, unsigned int row, - unsigned long long data_lo, - unsigned long long data_hi); - #ifdef __cplusplus } #endif diff --git a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json index a9620a36..c5785e66 100644 --- a/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json +++ b/arch/src/main/scala/examples/konbi/tiles/konbitile/decodecore/balldomain/configs/default.json @@ -24,7 +24,6 @@ {"mnemonic": "GEMMINI_PRELOAD", "funct7": 53, "bid": 7}, {"mnemonic": "GEMMINI_COMPUTE_PRELOADED", "funct7": 66, "bid": 7}, {"mnemonic": "GEMMINI_COMPUTE_ACCUMULATED", "funct7": 67, "bid": 7}, - {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8}, - {"mnemonic": "BDB_BACKDOOR", "funct7": 54, "bid": 8} + {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8} ] } diff --git a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json index 99d327d0..a7730468 100644 --- a/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json +++ b/arch/src/main/scala/examples/toy/tiles/toytile/toycore/balldomain/configs/default.json @@ -42,7 +42,6 @@ {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_8", "funct7": 103, "bid": 7}, {"mnemonic": "GEMMINI_LOOP_CONV_WS_CONFIG_9", "funct7": 104, "bid": 7}, {"mnemonic": "GEMMINI_LOOP_CONV_WS", "funct7": 105, "bid": 7}, - {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8}, - {"mnemonic": "BDB_BACKDOOR", "funct7": 54, "bid": 8} + {"mnemonic": "BDB_COUNTER", "funct7": 4, "bid": 8} ] } diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala index 6ee8fa89..8cf38009 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/Trace.scala @@ -11,17 +11,7 @@ import framework.top.GlobalConfig /** * Trace — TraceBall inner processing unit. * - * Handles two instruction types: - * - bdb_counter (funct7=48): cycle counter management (START/STOP/READ) - * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C - * - * Backdoor write: C++ generates (row, data) via DPI-C each iteration, - * RTL writes to external bank at (wbank_reg, row). - * Backdoor read: RTL reads external bank at (rbank_reg, row from DPI-C), - * sends data back to C++ via DPI-C for logging. - * - * bank_id always comes from the instruction encoding (rs1), - * row and data come from DPI-C (C++ auto-increments row each call). + * Handles cycle counter management (START/STOP/READ). */ @instantiable class Trace(val b: GlobalConfig) extends Module { @@ -56,9 +46,8 @@ class Trace(val b: GlobalConfig) extends Module { // ============================================================ // State machine // ============================================================ - val idle :: sCounter :: sBdReadExt :: sBdReadExtResp :: sBdGetWriteData :: sBdWriteExt :: sBdWriteExtResp :: complete :: Nil = - Enum(8) - val state = RegInit(idle) + val idle :: sCounter :: complete :: Nil = Enum(3) + val state = RegInit(idle) // ============================================================ // Registers @@ -67,12 +56,6 @@ class Trace(val b: GlobalConfig) extends Module { val is_sub_reg = RegInit(false.B) val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) - // Command decode registers - val isRead_reg = RegInit(false.B) // BB_RD0 flag - val isWrite_reg = RegInit(false.B) // BB_WR flag - val iter_reg = RegInit(0.U(16.W)) - val iterCnt = RegInit(0.U(16.W)) - // Counter-specific registers val subcmd_reg = RegInit(0.U(4.W)) val ctr_id_reg = RegInit(0.U(4.W)) @@ -86,14 +69,6 @@ class Trace(val b: GlobalConfig) extends Module { val ctrTag = RegInit(VecInit(Seq.fill(NUM_COUNTERS)(0.U(56.W)))) val ctrActive = RegInit(VecInit(Seq.fill(NUM_COUNTERS)(false.B))) - // Bank metadata registers (from instruction encoding) - val rbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - val wbank_reg = RegInit(0.U(log2Up(b.memDomain.bankNum).W)) - - // Backdoor address/data (row from DPI-C, data from DPI-C for writes) - val bd_addr_reg = RegInit(0.U(32.W)) - val bd_data_reg = RegInit(0.U(bankWidth.W)) - // ============================================================ // Private SramBank (staging buffer for future use) // ============================================================ @@ -121,35 +96,13 @@ class Trace(val b: GlobalConfig) extends Module { ctraceDpi.io.cycle := cycleCounter ctraceDpi.io.enable := false.B - val bdGetReadAddr = Module(new BackdoorGetReadAddrDPI) - val bdGetWriteAddr = Module(new BackdoorGetWriteAddrDPI) - val bdGetWriteData = Module(new BackdoorGetWriteDataDPI) - val bdPutReadData = Module(new BackdoorPutReadDataDPI) - val bdPutWriteDone = Module(new BackdoorPutWriteDoneDPI) - - bdGetReadAddr.io.enable := false.B - bdGetWriteAddr.io.enable := false.B - bdGetWriteData.io.enable := false.B - - bdPutReadData.io.bank_id := 0.U - bdPutReadData.io.row := 0.U - bdPutReadData.io.data_lo := 0.U - bdPutReadData.io.data_hi := 0.U - bdPutReadData.io.enable := false.B - - bdPutWriteDone.io.bank_id := 0.U - bdPutWriteDone.io.row := 0.U - bdPutWriteDone.io.data_lo := 0.U - bdPutWriteDone.io.data_hi := 0.U - bdPutWriteDone.io.enable := false.B - // ============================================================ // External bank port defaults // ============================================================ for (i <- 0 until inBW) { io.bankRead(i).rob_id := rob_id_reg io.bankRead(i).ball_id := 0.U - io.bankRead(i).bank_id := rbank_reg + io.bankRead(i).bank_id := 0.U io.bankRead(i).group_id := 0.U io.bankRead(i).io.req.valid := false.B io.bankRead(i).io.req.bits.addr := 0.U @@ -159,7 +112,7 @@ class Trace(val b: GlobalConfig) extends Module { for (i <- 0 until outBW) { io.bankWrite(i).rob_id := rob_id_reg io.bankWrite(i).ball_id := 0.U - io.bankWrite(i).bank_id := wbank_reg + io.bankWrite(i).bank_id := 0.U io.bankWrite(i).group_id := 0.U io.bankWrite(i).io.req.valid := false.B io.bankWrite(i).io.req.bits.addr := 0.U @@ -191,32 +144,12 @@ class Trace(val b: GlobalConfig) extends Module { val cmd = io.cmdReq.bits.cmd val rs2 = cmd.rs2 - // Distinguish counter vs backdoor by op1_en / wr_spad_en - val isBackdoor = cmd.op1_en || cmd.wr_spad_en - - isRead_reg := cmd.op1_en // BB_RD0 - isWrite_reg := cmd.wr_spad_en // BB_WR - iter_reg := cmd.iter - iterCnt := 0.U - // Counter fields from rs2 subcmd_reg := rs2(3, 0) ctr_id_reg := rs2(7, 4) payload_reg := rs2(63, 8) - // Bank IDs from decoded cmd - rbank_reg := cmd.op1_bank - wbank_reg := cmd.wr_bank - - when(!isBackdoor) { - state := sCounter - }.elsewhen(cmd.wr_spad_en) { - // Backdoor write: get row+data from DPI-C, write external bank - state := sBdGetWriteData - }.otherwise { - // Backdoor read: get row from DPI-C, read external bank - state := sBdReadExt - } + state := sCounter } } @@ -259,101 +192,6 @@ class Trace(val b: GlobalConfig) extends Module { state := complete } - // ---------------------------------------------------------- - // Backdoor read: get row from DPI-C, read external bank - // ---------------------------------------------------------- - is(sBdReadExt) { - // Get row from DPI-C (C++ auto-increments) - bdGetReadAddr.io.enable := true.B - val row = bdGetReadAddr.io.result(31, 0) - - bd_addr_reg := row - - // Issue read to external bank (bank_id from instruction) - io.bankRead(0).io.req.valid := true.B - io.bankRead(0).io.req.bits.addr := row - io.bankRead(0).io.resp.ready := true.B - - when(io.bankRead(0).io.req.fire) { - state := sBdReadExtResp - } - } - - is(sBdReadExtResp) { - io.bankRead(0).io.resp.ready := true.B - - when(io.bankRead(0).io.resp.valid) { - val data = io.bankRead(0).io.resp.bits.data - - // Output data via DPI-C - bdPutReadData.io.bank_id := rbank_reg - bdPutReadData.io.row := bd_addr_reg - bdPutReadData.io.data_lo := data(63, 0) - bdPutReadData.io.data_hi := data(127, 64) - bdPutReadData.io.enable := true.B - - // Check if more iterations - iterCnt := iterCnt + 1.U - when(iterCnt >= iter_reg) { - state := complete - }.otherwise { - state := sBdReadExt - } - } - } - - // ---------------------------------------------------------- - // Backdoor write: get row+data from DPI-C, write external bank - // ---------------------------------------------------------- - is(sBdGetWriteData) { - // Get row from DPI-C (C++ auto-increments and pre-generates data) - bdGetWriteAddr.io.enable := true.B - val row = bdGetWriteAddr.io.result(31, 0) - bd_addr_reg := row - - // Get data from DPI-C - bdGetWriteData.io.enable := true.B - val fullData = Cat(bdGetWriteData.io.data_hi, bdGetWriteData.io.data_lo) - bd_data_reg := fullData - - state := sBdWriteExt - } - - is(sBdWriteExt) { - // Write to external bank (bank_id from instruction) - io.bankWrite(0).io.req.valid := true.B - io.bankWrite(0).io.req.bits.addr := bd_addr_reg - io.bankWrite(0).io.req.bits.data := bd_data_reg - io.bankWrite(0).io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(1.U(1.W))) - io.bankWrite(0).io.req.bits.wmode := false.B - io.bankWrite(0).io.resp.ready := true.B - - when(io.bankWrite(0).io.req.fire) { - state := sBdWriteExtResp - } - } - - is(sBdWriteExtResp) { - io.bankWrite(0).io.resp.ready := true.B - - when(io.bankWrite(0).io.resp.valid) { - // Log the write via DPI-C - bdPutWriteDone.io.bank_id := wbank_reg - bdPutWriteDone.io.row := bd_addr_reg - bdPutWriteDone.io.data_lo := bd_data_reg(63, 0) - bdPutWriteDone.io.data_hi := bd_data_reg(127, 64) - bdPutWriteDone.io.enable := true.B - - // Check if more iterations - iterCnt := iterCnt + 1.U - when(iterCnt >= iter_reg) { - state := complete - }.otherwise { - state := sBdGetWriteData - } - } - } - // ---------------------------------------------------------- // Complete: fire cmdResp // ---------------------------------------------------------- diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala index fe41b2be..873bd115 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceBall.scala @@ -7,11 +7,10 @@ import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, import framework.top.GlobalConfig /** - * TraceBall — Debug trace Ball providing cycle counters and SRAM backdoor. + * TraceBall — Debug trace Ball providing cycle counters. * - * Uses two funct7 encodings: - * - bdb_counter (funct7=48): cycle counter management - * - bdb_backdoor (funct7=49): SRAM backdoor read/write via DPI-C + * Uses funct7 encoding: + * - bdb_counter (funct7=4): cycle counter management */ @instantiable class TraceBall(val b: GlobalConfig) extends Module with HasBlink { diff --git a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala index 79d6327e..6b5a4aab 100644 --- a/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala +++ b/arch/src/main/scala/framework/balldomain/prototype/trace/TraceDPI.scala @@ -46,192 +46,3 @@ class CTraceDPI extends BlackBox with HasBlackBoxInline { """.stripMargin ) } - -/** - * DPI-C BlackBox for backdoor get_read_addr. - * Returns packed [63:32]=bank_id, [31:0]=row. - */ -class BackdoorGetReadAddrDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val result = Output(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "BackdoorGetReadAddrDPI.v", - """ - |import "DPI-C" function longint unsigned dpi_backdoor_get_read_addr(); - | - |module BackdoorGetReadAddrDPI( - | output [63:0] result, - | input enable - |); - | reg [63:0] result_reg; - | assign result = result_reg; - | always @(*) begin - | result_reg = 64'd0; - | if (enable) begin - | result_reg = dpi_backdoor_get_read_addr(); - | end - | end - |endmodule - """.stripMargin - ) -} - -/** - * DPI-C BlackBox for backdoor get_write_addr. - * Returns packed [63:32]=bank_id, [31:0]=row. - */ -class BackdoorGetWriteAddrDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val result = Output(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "BackdoorGetWriteAddrDPI.v", - """ - |import "DPI-C" function longint unsigned dpi_backdoor_get_write_addr(); - | - |module BackdoorGetWriteAddrDPI( - | output [63:0] result, - | input enable - |); - | reg [63:0] result_reg; - | assign result = result_reg; - | always @(*) begin - | result_reg = 64'd0; - | if (enable) begin - | result_reg = dpi_backdoor_get_write_addr(); - | end - | end - |endmodule - """.stripMargin - ) -} - -/** - * DPI-C BlackBox for backdoor get_write_data. - * Returns 128-bit data as two 64-bit outputs. - */ -class BackdoorGetWriteDataDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val data_lo = Output(UInt(64.W)) - val data_hi = Output(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "BackdoorGetWriteDataDPI.v", - """ - |import "DPI-C" function void dpi_backdoor_get_write_data( - | output longint unsigned data_lo, - | output longint unsigned data_hi - |); - | - |module BackdoorGetWriteDataDPI( - | output [63:0] data_lo, - | output [63:0] data_hi, - | input enable - |); - | reg [63:0] data_lo_reg; - | reg [63:0] data_hi_reg; - | assign data_lo = data_lo_reg; - | assign data_hi = data_hi_reg; - | always @(*) begin - | data_lo_reg = 64'd0; - | data_hi_reg = 64'd0; - | if (enable) begin - | dpi_backdoor_get_write_data(data_lo_reg, data_hi_reg); - | end - | end - |endmodule - """.stripMargin - ) -} - -/** - * DPI-C BlackBox for backdoor put_read_data. - * Reports read data back to C++ for logging. - */ -class BackdoorPutReadDataDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val bank_id = Input(UInt(32.W)) - val row = Input(UInt(32.W)) - val data_lo = Input(UInt(64.W)) - val data_hi = Input(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "BackdoorPutReadDataDPI.v", - """ - |import "DPI-C" function void dpi_backdoor_put_read_data( - | input int unsigned bank_id, - | input int unsigned row, - | input longint unsigned data_lo, - | input longint unsigned data_hi - |); - | - |module BackdoorPutReadDataDPI( - | input [31:0] bank_id, - | input [31:0] row, - | input [63:0] data_lo, - | input [63:0] data_hi, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_backdoor_put_read_data(bank_id, row, data_lo, data_hi); - | end - | end - |endmodule - """.stripMargin - ) -} - -/** - * DPI-C BlackBox for backdoor put_write_done. - * Reports write completion back to C++ for logging. - */ -class BackdoorPutWriteDoneDPI extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val bank_id = Input(UInt(32.W)) - val row = Input(UInt(32.W)) - val data_lo = Input(UInt(64.W)) - val data_hi = Input(UInt(64.W)) - val enable = Input(Bool()) - }) - - setInline( - "BackdoorPutWriteDoneDPI.v", - """ - |import "DPI-C" function void dpi_backdoor_put_write_done( - | input int unsigned bank_id, - | input int unsigned row, - | input longint unsigned data_lo, - | input longint unsigned data_hi - |); - | - |module BackdoorPutWriteDoneDPI( - | input [31:0] bank_id, - | input [31:0] row, - | input [63:0] data_lo, - | input [63:0] data_hi, - | input enable - |); - | always @(*) begin - | if (enable) begin - | dpi_backdoor_put_write_done(bank_id, row, data_lo, data_hi); - | end - | end - |endmodule - """.stripMargin - ) -} diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index bcdc40ea..047a5f89 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -25,6 +25,7 @@ import freechips.rocketchip.tilelink.{ TLBuffer, TLClientNode, TLClientParameters, + TLFragmenter, TLIdentityNode, TLMasterPortParameters, TLWidthWidget, @@ -40,6 +41,7 @@ import framework.core.bbtile.id.RVVRoCCDecode import framework.memdomain.backend.MemRequestIO import framework.memdomain.backend.shared.SharedMemBackend import framework.memdomain.frontend.outside_channel.MemConfigerIO +import sims.p2e.scu.{P2ESCUKey, TLP2ESCU} /** * BBTile — a composable tile containing one Rocket core + optional per-core-index Buckyball slots. @@ -65,7 +67,7 @@ class BBTile private ( )( implicit p: Parameters ) = - this(params, crossing.crossingType, lookup, BBTile.injectBuildRoCC(p, params.withAnyBuckyball)) + this(params, crossing.crossingType, lookup, BBTile.injectBuildRoCC(p, params.withAnyBuckyball, params.nCores)) val nCores = bbParams.nCores val bbPerCore = bbParams.resolvedBuckyballPerCore @@ -133,6 +135,18 @@ class BBTile private ( // --------------------------------------------------------------------------- // Buckyball accelerator TileLink nodes (diplomacy layer) — N pairs of DMA // --------------------------------------------------------------------------- + val extraFrontends: Seq[Frontend] = (1 until nCores).map { _ => + val f = LazyModule(new Frontend(bbParams.icache.get, bbParams.tileId)) + tlMasterXbar.node := TLWidthWidget(bbParams.icache.get.rowBits / 8) := f.masterNode + connectTLSlave(f.slaveNode, bbParams.core.fetchBytes) + f.icache.hartIdSinkNodeOpt.foreach(_ := hartIdNexusNode) + f.icache.mmioAddressPrefixSinkNodeOpt.foreach(_ := mmioAddressPrefixNexusNode) + f.resetVectorSinkNode := resetVectorNexusNode + f + } + + nPTWPorts += extraFrontends.size + val bb_reader_nodes: Seq[Option[TLClientNode]] = (0 until nCores).map { i => if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = s"bb-dma-reader-$i", @@ -163,12 +177,21 @@ class BBTile private ( // --------------------------------------------------------------------------- // TileLink topology // --------------------------------------------------------------------------- + p(P2ESCUKey).foreach { params => + val p2eScu = LazyModule(new TLP2ESCU(params, xBytes, bbParams.tileId)) + p2eScu.node := TLFragmenter( + xBytes, + cacheBlockBytes, + nameSuffix = Some(s"P2ESCU_${bbParams.tileId}") + ) := tlOtherMastersNode + } + tlOtherMastersNode := tile_master_blocker.map(_.node := tlMasterXbar.node).getOrElse(tlMasterXbar.node) masterNode :=* tlOtherMastersNode DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) // DCache port count: core + PTW(via usingVM) + DTIM + vector + RoCC tieoff - nDCachePorts += 1 + (dtim_adapter.isDefined).toInt + + nDCachePorts += nCores + (dtim_adapter.isDefined).toInt + bbParams.core.vector.map(_.useDCache.toInt).getOrElse(0) + hasBuckyball.toInt @@ -236,10 +259,14 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC val nCores = outer.nCores // --- FPU (optional) --- - val fpuOpt = outer.bbParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) + val fpuOpts = Seq.fill(nCores)(outer.bbParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))) // --- Rocket core (using our fork that accepts BBTile) --- - val core = Module(new RocketBB(outer, outer.bbPerCore.head.isDefined)(outer.p)) + val cores = (0 until nCores).map { i => + Module(new RocketBB(outer, outer.bbPerCore(i).isDefined)(outer.p)) + } + + val core = cores.head // Vector unit connections outer.vector_unit.foreach { v => @@ -247,7 +274,8 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC v.module.io.tlb <> outer.dcache.module.io.tlb_port } - core.io.reset_vector := DontCare + core.io.reset_vector := DontCare + cores.tail.foreach(_.io.reset_vector := DontCare) // Report conditions outer.reportHalt(List(outer.dcache.module.io.errors)) @@ -255,38 +283,44 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC !outer.dcache.module.io.cpu.clock_enabled && !outer.frontend.module.io.cpu.clock_enabled && !ptw.io.dpath.clock_enabled && - core.io.cease + cores.map(_.io.cease).reduce(_ && _) )) - outer.reportWFI(Some(core.io.wfi)) + outer.reportWFI(Some(cores.map(_.io.wfi).reduce(_ && _))) // Interrupts - outer.decodeCoreInterrupts(core.io.interrupts) + cores.foreach(c => outer.decodeCoreInterrupts(c.io.interrupts)) outer.bus_error_unit.foreach { beu => - core.io.interrupts.buserror.get := beu.module.io.interrupt - beu.module.io.errors.dcache := outer.dcache.module.io.errors - beu.module.io.errors.icache := outer.frontend.module.io.errors + cores.foreach(_.io.interrupts.buserror.get := beu.module.io.interrupt) + beu.module.io.errors.dcache := outer.dcache.module.io.errors + beu.module.io.errors.icache := outer.frontend.module.io.errors } - core.io.interrupts.nmi.foreach(nmi => nmi := outer.nmiSinkNode.get.bundle) + cores.foreach(_.io.interrupts.nmi.foreach(nmi => nmi := outer.nmiSinkNode.get.bundle)) // Trace and misc outer.traceSourceNode.bundle <> core.io.trace - core.io.traceStall := outer.traceAuxSinkNode.bundle.stall + cores.foreach(_.io.traceStall := outer.traceAuxSinkNode.bundle.stall) outer.bpwatchSourceNode.bundle <> core.io.bpwatch - core.io.hartid := outer.hartIdSinkNode.bundle + cores.zipWithIndex.foreach { case (c, i) => c.io.hartid := outer.hartIdSinkNode.bundle * nCores.U + i.U } // Core pipeline connections outer.frontend.module.io.cpu <> core.io.imem - dcachePorts += core.io.dmem + for ((f, i) <- outer.extraFrontends.zipWithIndex) { + f.module.io.cpu <> cores(i + 1).io.imem + ptwPorts += f.module.io.ptw + } + cores.foreach(c => dcachePorts += c.io.dmem) // FPU - fpuOpt.foreach { fpu => - core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) - fpu.io.cp_req.valid := false.B - fpu.io.cp_req.bits := DontCare - fpu.io.cp_resp.ready := false.B - } - if (fpuOpt.isEmpty) { - core.io.fpu := DontCare + for ((c, fpuOpt) <- cores.zip(fpuOpts)) { + fpuOpt.foreach { fpu => + c.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) + fpu.io.cp_req.valid := false.B + fpu.io.cp_req.bits := DontCare + fpu.io.cp_resp.ready := false.B + } + if (fpuOpt.isEmpty) { + c.io.fpu := DontCare + } } // Vector unit DCache port @@ -299,6 +333,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC } core.io.ptw <> ptw.io.dpath + cores.tail.foreach(_.io.ptw := DontCare) // DTIM adapter outer.dtim_adapter.foreach(lm => dcachePorts += lm.module.io.dmem) @@ -395,7 +430,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC val (tl_reader, edge) = outer.bb_reader_nodes(i).get.out(0) val (tl_writer, _) = outer.bb_writer_nodes(i).get.out(0) val acc = Module(new BuckyballAccelerator(cfg)(edge)) - acc.io.hartid := outer.hartIdSinkNode.bundle + i.U + acc.io.hartid := outer.hartIdSinkNode.bundle * nCores.U + i.U tl_reader <> acc.io.tl_reader tl_writer <> acc.io.tl_writer @@ -407,12 +442,22 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC } } - // Core-0 RoCC wiring (the single Rocket core drives accelerator 0) - val core0Acc = accelerators(0).get - core0Acc.io.cmd <> core.io.rocc.cmd - core.io.rocc.resp <> core0Acc.io.resp - core.io.rocc.busy := core0Acc.io.busy - core.io.rocc.interrupt := core0Acc.io.interrupt + val enabledAccelerators = outer.bbEnabledCoreIds.map(i => accelerators(i).get) + for (i <- 0 until nCores) { + accelerators(i) match { + case Some(acc) => + acc.io.cmd <> cores(i).io.rocc.cmd + cores(i).io.rocc.resp <> acc.io.resp + cores(i).io.rocc.busy := acc.io.busy + cores(i).io.rocc.interrupt := acc.io.interrupt + case None => + cores(i).io.rocc.cmd.ready := false.B + cores(i).io.rocc.resp.valid := false.B + cores(i).io.rocc.resp.bits := DontCare + cores(i).io.rocc.busy := false.B + cores(i).io.rocc.interrupt := false.B + } + } // RoCC mem: tied-off HellaCacheIF for the DCache arbiter port count val roccMemIF = Module(new SimpleHellaCacheIF()) @@ -423,7 +468,7 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC roccMemIF.io.requestor.s2_kill := false.B roccMemIF.io.requestor.keep_clock_enabled := false.B dcachePorts += roccMemIF.io.cache - core.io.rocc.mem := DontCare + cores.foreach(_.io.rocc.mem := DontCare) // SharedMemBackend (tile-level singleton) val sharedBackend = Module(new SharedMemBackend(cfg0)) @@ -440,14 +485,13 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC } // Shared config arbiter: enabled accelerators -> 1 SharedMemBackend config port - val enabledAccelerators = outer.bbEnabledCoreIds.map(i => accelerators(i).get) - val cfgArb = Module(new Arbiter(new MemConfigerIO(cfg0), enabledAccelerators.size)) + val cfgArb = Module(new Arbiter(new MemConfigerIO(cfg0), enabledAccelerators.size)) for ((acc, i) <- enabledAccelerators.zipWithIndex) { cfgArb.io.in(i) <> acc.io.shared_config } sharedBackend.io.config <> cfgArb.io.out - sharedBackend.io.query_vbank_id := core0Acc.io.shared_query_vbank_id + sharedBackend.io.query_vbank_id := enabledAccelerators.head.io.shared_query_vbank_id for (i <- 0 until nCores) { accelerators(i).foreach { acc => acc.io.shared_query_group_count := sharedBackend.io.query_group_count @@ -463,12 +507,14 @@ class BBTileModuleImp(outer: BBTile) extends BaseTileModuleImp(outer) with HasIC } else { // No accelerator — tie off RoCC - core.io.rocc.cmd.ready := false.B - core.io.rocc.resp.valid := false.B - core.io.rocc.resp.bits := DontCare - core.io.rocc.busy := DontCare - core.io.rocc.interrupt := DontCare - core.io.rocc.mem := DontCare + cores.foreach { c => + c.io.rocc.cmd.ready := false.B + c.io.rocc.resp.valid := false.B + c.io.rocc.resp.bits := DontCare + c.io.rocc.busy := DontCare + c.io.rocc.interrupt := DontCare + c.io.rocc.mem := DontCare + } } // --- Finalize DCache arbiter and PTW connections (after all ports added) --- @@ -489,9 +535,9 @@ object BBTile { * HasRocketCoreParameters mixins (CSR, decode, etc.), without actually * using the LazyRoCC mechanism. */ - def injectBuildRoCC(p: Parameters, withBuckyball: Boolean): Parameters = + def injectBuildRoCC(p: Parameters, withBuckyball: Boolean, nCores: Int): Parameters = if (withBuckyball) - p.alterPartial { case BuildRoCC => Seq((_: Parameters) => null.asInstanceOf[LazyRoCC]) } + p.alterPartial { case BuildRoCC => Seq.fill(nCores)((_: Parameters) => null.asInstanceOf[LazyRoCC]) } else p } diff --git a/arch/src/main/scala/sims/README.md b/arch/src/main/scala/sims/README.md index e13c466b..23e3c9da 100644 --- a/arch/src/main/scala/sims/README.md +++ b/arch/src/main/scala/sims/README.md @@ -8,41 +8,30 @@ This directory contains simulation configurations and interfaces for various sim sims/ ├── firesim/ │ └── TargetConfigs.scala - FireSim FPGA simulation configuration -├── verilator/ -│ └── Elaborate.scala - Verilator simulation top-level generation -└── verify/ - └── TargetConfig.scala - Verification configurations +└── verilator/ + └── TargetConfig.scala - Verilator simulation top-level generation ``` ## Verilator Simulation (verilator/) -### Elaborate.scala +### TargetConfig.scala Top-level generator for Verilator simulation: ```scala object Elaborate extends App { - // Select Ball type from command line arguments - val ballType = args.headOption.getOrElse("toy") - - val config = ballType match { - case "toy" => new ToyBuckyballConfig - case "vec" => new WithBlink(TargetBall.VecBall) - case "matrix" => new WithBlink(TargetBall.MatrixBall) - case "transpose" => new WithBlink(TargetBall.TransposeBall) - case "im2col" => new WithBlink(TargetBall.Im2colBall) - case "relu" => new WithBlink(TargetBall.ReluBall) - case _ => new ToyBuckyballConfig + if (args.isEmpty) { + println("Usage: Elaborate [firtool-opts...]") + sys.exit(1) } - val gen = () => LazyModule(new TestHarness()(config)).module + val configClass = Class.forName(args(0)) + val config = configClass.getDeclaredConstructor().newInstance().asInstanceOf[Config] - (new ChiselStage).execute( - args.tail, // Remaining args passed to firtool - Seq( - ChiselGeneratorAnnotation(gen), - TargetDirAnnotation("generated-src/verilator") - ) + ChiselStage.emitSystemVerilogFile( + new BBSimHarness()(config.toInstance), + firtoolOpts = args.drop(1), + args = Array.empty ) } ``` @@ -85,32 +74,6 @@ class FireSimBuckyballConfig extends Config( - Multi-core system performance evaluation - I/O-intensive application verification -## Verification Configurations (verify/) - -### TargetConfig.scala - -Configurations for single Ball device verification: - -```scala -sealed trait TargetBall -object TargetBall { - case object VecBall extends TargetBall - case object MatrixBall extends TargetBall - case object TransposeBall extends TargetBall - case object Im2colBall extends TargetBall - case object ReluBall extends TargetBall -} -``` - -**WithBlink Configuration**: Empty configuration class for composing with Ball-specific configs - -**Usage**: -```bash -# Verify specific Ball device -mill arch.runMain sims.verilator.Elaborate matrix -mill arch.runMain sims.verilator.Elaborate transpose -``` - ## Build and Usage ### Verilator Simulation Build @@ -118,20 +81,18 @@ mill arch.runMain sims.verilator.Elaborate transpose ```bash # Generate Verilog cd arch -mill arch.runMain sims.verilator.Elaborate [ball_type] +mill arch.runMain sims.verilator.Elaborate sims.verilator.BuckyballToyVerilatorConfig # Build simulator (in sims/verilator directory) cd ../../sims/verilator make CONFIG=ToyBuckyball ``` -**Available Ball Types**: -- `toy`: Complete toy system (default) -- `vec`: Vector Ball only -- `matrix`: Matrix Ball only -- `transpose`: Transpose Ball only -- `im2col`: Im2col Ball only -- `relu`: ReLU Ball only +**Available Verilator Configurations**: +- `sims.verilator.BuckyballToyVerilatorConfig` +- `sims.verilator.BuckyballGobanVerilatorConfig` +- `sims.verilator.BuckyballKonbiVerilatorConfig` +- `sims.verilator.BuckyballPolyVerilatorConfig` ### FireSim Deployment diff --git a/arch/src/main/scala/sims/p2e/P2EHarness.scala b/arch/src/main/scala/sims/p2e/P2EHarness.scala new file mode 100644 index 00000000..73680496 --- /dev/null +++ b/arch/src/main/scala/sims/p2e/P2EHarness.scala @@ -0,0 +1,14 @@ +package sims.p2e + +import chisel3._ +import org.chipsalliance.cde.config.Parameters +import chipyard.harness.HasHarnessInstantiators + +class P2EHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { + def referenceClockFreqMHz: Double = 1000.0 + def referenceClock: Clock = clock + def referenceReset: Reset = reset + + val success = WireInit(false.B) + val lazyDuts = instantiateChipTops() +} diff --git a/arch/src/main/scala/sims/p2e/P2EHarnessBinders.scala b/arch/src/main/scala/sims/p2e/P2EHarnessBinders.scala new file mode 100644 index 00000000..2c1ce6e4 --- /dev/null +++ b/arch/src/main/scala/sims/p2e/P2EHarnessBinders.scala @@ -0,0 +1,44 @@ +package sims.p2e + +import chisel3._ +import org.chipsalliance.cde.config.Config + +import chipyard.harness.{HarnessBinder, HasHarnessInstantiators} +import chipyard.iobinders.{AXI4MemPort, UARTPort} + +class WithP2ETieOffAXIMem + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => + val axi = port.io.bits + axi.aw.ready := false.B + axi.w.ready := false.B + axi.b.valid := false.B + axi.b.bits := DontCare + axi.ar.ready := false.B + axi.r.valid := false.B + axi.r.bits := DontCare + }) + +class WithNoUARTAdapter + extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => + port.io.rxd := true.B + }) + +class WithP2EHarness + extends Config( + new WithP2ETieOffAXIMem ++ + new WithNoUARTAdapter ++ + new chipyard.harness.WithSimAXIMMIO ++ + new chipyard.harness.WithSerialTLTiedOff ++ + new chipyard.harness.WithTieOffInterrupts ++ + new chipyard.harness.WithTieOffL2FBusAXI ++ + new chipyard.harness.WithTiedOffJTAG ++ + new chipyard.harness.WithTiedOffDMI ++ + new chipyard.harness.WithClockFromHarness ++ + new chipyard.harness.WithResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.iobinders.WithAXI4MemPunchthrough ++ + new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ + new chipyard.iobinders.WithNMITiedOff + ) diff --git a/arch/src/main/scala/sims/p2e/P2ETop.scala b/arch/src/main/scala/sims/p2e/P2ETop.scala new file mode 100644 index 00000000..6ff164d2 --- /dev/null +++ b/arch/src/main/scala/sims/p2e/P2ETop.scala @@ -0,0 +1,477 @@ +package sims.p2e + +import chisel3._ +import chisel3.experimental.{attach, Analog} +import chisel3.util.HasBlackBoxInline + +class P2ETopIO extends Bundle { + val user_clk = Input(Clock()) + val sys_rstn = Input(Bool()) + + val c0_sys_clk_p = Input(Bool()) + val c0_sys_clk_n = Input(Bool()) + + val c0_ddr4_act_n = Output(Bool()) + val c0_ddr4_adr = Output(UInt(17.W)) + val c0_ddr4_ba = Output(UInt(2.W)) + val c0_ddr4_bg = Output(UInt(2.W)) + val c0_ddr4_cke = Output(UInt(2.W)) + val c0_ddr4_odt = Output(UInt(2.W)) + val c0_ddr4_cs_n = Output(UInt(2.W)) + val c0_ddr4_ck_t = Output(UInt(2.W)) + val c0_ddr4_ck_c = Output(UInt(2.W)) + val c0_ddr4_reset_n = Output(Bool()) + val c0_ddr4_dm_dbi_n = Analog(8.W) + val c0_ddr4_dq = Analog(64.W) + val c0_ddr4_dqs_c = Analog(8.W) + val c0_ddr4_dqs_t = Analog(8.W) + val c0_ddr4_ui_clk = Output(Clock()) + val init_calib_complete = Output(Bool()) + + val ddr4_en_vtt = Output(Bool()) + val ddr4_en_vddq = Output(Bool()) + val ddr4_en_vcc2v5 = Output(Bool()) + val power_good = Input(Bool()) +} + +class P2ETopBlackBox extends BlackBox with HasBlackBoxInline { + val io = IO(new P2ETopIO) + + setInline( + "P2ETopBlackBox.v", + """ + |module p2e_mmio_zero_slave #( + | parameter ADDR_BITS = 32, + | parameter DATA_BITS = 64, + | parameter ID_BITS = 4, + | parameter STRB_BITS = DATA_BITS / 8 + |)( + | input clock, + | input reset, + | output aw_ready, + | input aw_valid, + | input [ID_BITS-1:0] aw_id, + | input [ADDR_BITS-1:0] aw_addr, + | input [7:0] aw_len, + | input [2:0] aw_size, + | input [1:0] aw_burst, + | output w_ready, + | input w_valid, + | input [DATA_BITS-1:0] w_data, + | input [STRB_BITS-1:0] w_strb, + | input w_last, + | input b_ready, + | output reg b_valid, + | output reg [ID_BITS-1:0] b_id, + | output [1:0] b_resp, + | output ar_ready, + | input ar_valid, + | input [ID_BITS-1:0] ar_id, + | input [ADDR_BITS-1:0] ar_addr, + | input [7:0] ar_len, + | input [2:0] ar_size, + | input [1:0] ar_burst, + | input r_ready, + | output reg r_valid, + | output reg [ID_BITS-1:0] r_id, + | output [DATA_BITS-1:0] r_data, + | output [1:0] r_resp, + | output r_last + |); + | assign aw_ready = !b_valid; + | assign w_ready = !b_valid; + | assign b_resp = 2'b00; + | + | assign ar_ready = !r_valid; + | assign r_data = {DATA_BITS{1'b0}}; + | assign r_resp = 2'b00; + | assign r_last = 1'b1; + | + | always @(posedge clock) begin + | if (reset) begin + | b_valid <= 1'b0; + | b_id <= {ID_BITS{1'b0}}; + | r_valid <= 1'b0; + | r_id <= {ID_BITS{1'b0}}; + | end else begin + | if (b_valid && b_ready) begin + | b_valid <= 1'b0; + | end + | if (!b_valid && aw_valid && w_valid) begin + | b_valid <= 1'b1; + | b_id <= aw_id; + | end + | + | if (r_valid && r_ready) begin + | r_valid <= 1'b0; + | end + | if (!r_valid && ar_valid) begin + | r_valid <= 1'b1; + | r_id <= ar_id; + | end + | end + | end + |endmodule + | + |module P2ETopBlackBox( + | input user_clk, + | input sys_rstn, + | input c0_sys_clk_p, + | input c0_sys_clk_n, + | output c0_ddr4_act_n, + | output [16:0] c0_ddr4_adr, + | output [1:0] c0_ddr4_ba, + | output [1:0] c0_ddr4_bg, + | output [1:0] c0_ddr4_cke, + | output [1:0] c0_ddr4_odt, + | output [1:0] c0_ddr4_cs_n, + | output [1:0] c0_ddr4_ck_t, + | output [1:0] c0_ddr4_ck_c, + | output c0_ddr4_reset_n, + | inout [7:0] c0_ddr4_dm_dbi_n, + | inout [63:0] c0_ddr4_dq, + | inout [7:0] c0_ddr4_dqs_c, + | inout [7:0] c0_ddr4_dqs_t, + | output c0_ddr4_ui_clk, + | output init_calib_complete, + | output ddr4_en_vtt, + | output ddr4_en_vddq, + | output ddr4_en_vcc2v5, + | input power_good + |); + | localparam MEM_ADDR_BITS = 64; + | localparam MEM_DATA_BITS = 256; + | localparam MEM_STRB_BITS = 32; + | localparam MEM_ID_BITS = 11; + | localparam MMIO_ADDR_BITS = 32; + | localparam MMIO_DATA_BITS = 64; + | localparam MMIO_STRB_BITS = 8; + | localparam MMIO_ID_BITS = 4; + | + | wire c0_init_calib_complete; + | wire soc_reset = !sys_rstn || !c0_init_calib_complete; + | assign init_calib_complete = c0_init_calib_complete; + | + | wire [MEM_ID_BITS-1:0] mem_awid; + | wire [MEM_ADDR_BITS-1:0] mem_awaddr; + | wire [7:0] mem_awlen; + | wire [2:0] mem_awsize; + | wire [1:0] mem_awburst; + | wire mem_awvalid; + | wire mem_awready; + | wire [MEM_DATA_BITS-1:0] mem_wdata; + | wire [MEM_STRB_BITS-1:0] mem_wstrb; + | wire mem_wlast; + | wire mem_wvalid; + | wire mem_wready; + | wire [MEM_ID_BITS-1:0] mem_bid; + | wire [1:0] mem_bresp; + | wire mem_bvalid; + | wire mem_bready; + | wire [MEM_ID_BITS-1:0] mem_arid; + | wire [MEM_ADDR_BITS-1:0] mem_araddr; + | wire [7:0] mem_arlen; + | wire [2:0] mem_arsize; + | wire [1:0] mem_arburst; + | wire mem_arvalid; + | wire mem_arready; + | wire [MEM_ID_BITS-1:0] mem_rid; + | wire [MEM_DATA_BITS-1:0] mem_rdata; + | wire [1:0] mem_rresp; + | wire mem_rlast; + | wire mem_rvalid; + | wire mem_rready; + | + | wire [MMIO_ID_BITS-1:0] mmio_awid; + | wire [MMIO_ADDR_BITS-1:0] mmio_awaddr; + | wire [7:0] mmio_awlen; + | wire [2:0] mmio_awsize; + | wire [1:0] mmio_awburst; + | wire mmio_awvalid; + | wire mmio_awready; + | wire [MMIO_DATA_BITS-1:0] mmio_wdata; + | wire [MMIO_STRB_BITS-1:0] mmio_wstrb; + | wire mmio_wlast; + | wire mmio_wvalid; + | wire mmio_wready; + | wire [MMIO_ID_BITS-1:0] mmio_bid; + | wire [1:0] mmio_bresp; + | wire mmio_bvalid; + | wire mmio_bready; + | wire [MMIO_ID_BITS-1:0] mmio_arid; + | wire [MMIO_ADDR_BITS-1:0] mmio_araddr; + | wire [7:0] mmio_arlen; + | wire [2:0] mmio_arsize; + | wire [1:0] mmio_arburst; + | wire mmio_arvalid; + | wire mmio_arready; + | wire [MMIO_ID_BITS-1:0] mmio_rid; + | wire [MMIO_DATA_BITS-1:0] mmio_rdata; + | wire [1:0] mmio_rresp; + | wire mmio_rlast; + | wire mmio_rvalid; + | wire mmio_rready; + | + | DigitalTop soc ( + | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (user_clk), + | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset (soc_reset), + | .resetctrl_hartIsInReset_0 (1'b0), + | .debug_clock (user_clk), + | .debug_reset (soc_reset), + | .debug_systemjtag_reset (soc_reset), + | .debug_systemjtag_jtag_TCK (1'b0), + | .debug_systemjtag_jtag_TMS (1'b1), + | .debug_systemjtag_jtag_TDI (1'b1), + | .debug_dmactiveAck (1'b0), + | .mem_axi4_0_aw_ready (mem_awready), + | .mem_axi4_0_aw_valid (mem_awvalid), + | .mem_axi4_0_aw_bits_id (mem_awid), + | .mem_axi4_0_aw_bits_addr (mem_awaddr), + | .mem_axi4_0_aw_bits_len (mem_awlen), + | .mem_axi4_0_aw_bits_size (mem_awsize), + | .mem_axi4_0_aw_bits_burst (mem_awburst), + | .mem_axi4_0_w_ready (mem_wready), + | .mem_axi4_0_w_valid (mem_wvalid), + | .mem_axi4_0_w_bits_data (mem_wdata), + | .mem_axi4_0_w_bits_strb (mem_wstrb), + | .mem_axi4_0_w_bits_last (mem_wlast), + | .mem_axi4_0_b_valid (mem_bvalid), + | .mem_axi4_0_b_ready (mem_bready), + | .mem_axi4_0_b_bits_id (mem_bid), + | .mem_axi4_0_b_bits_resp (mem_bresp), + | .mem_axi4_0_ar_ready (mem_arready), + | .mem_axi4_0_ar_valid (mem_arvalid), + | .mem_axi4_0_ar_bits_id (mem_arid), + | .mem_axi4_0_ar_bits_addr (mem_araddr), + | .mem_axi4_0_ar_bits_len (mem_arlen), + | .mem_axi4_0_ar_bits_size (mem_arsize), + | .mem_axi4_0_ar_bits_burst (mem_arburst), + | .mem_axi4_0_r_valid (mem_rvalid), + | .mem_axi4_0_r_ready (mem_rready), + | .mem_axi4_0_r_bits_id (mem_rid), + | .mem_axi4_0_r_bits_data (mem_rdata), + | .mem_axi4_0_r_bits_resp (mem_rresp), + | .mem_axi4_0_r_bits_last (mem_rlast), + | .mmio_axi4_0_aw_ready (mmio_awready), + | .mmio_axi4_0_aw_valid (mmio_awvalid), + | .mmio_axi4_0_aw_bits_id (mmio_awid), + | .mmio_axi4_0_aw_bits_addr (mmio_awaddr), + | .mmio_axi4_0_aw_bits_len (mmio_awlen), + | .mmio_axi4_0_aw_bits_size (mmio_awsize), + | .mmio_axi4_0_aw_bits_burst (mmio_awburst), + | .mmio_axi4_0_w_ready (mmio_wready), + | .mmio_axi4_0_w_valid (mmio_wvalid), + | .mmio_axi4_0_w_bits_data (mmio_wdata), + | .mmio_axi4_0_w_bits_strb (mmio_wstrb), + | .mmio_axi4_0_w_bits_last (mmio_wlast), + | .mmio_axi4_0_b_valid (mmio_bvalid), + | .mmio_axi4_0_b_ready (mmio_bready), + | .mmio_axi4_0_b_bits_id (mmio_bid), + | .mmio_axi4_0_b_bits_resp (mmio_bresp), + | .mmio_axi4_0_ar_ready (mmio_arready), + | .mmio_axi4_0_ar_valid (mmio_arvalid), + | .mmio_axi4_0_ar_bits_id (mmio_arid), + | .mmio_axi4_0_ar_bits_addr (mmio_araddr), + | .mmio_axi4_0_ar_bits_len (mmio_arlen), + | .mmio_axi4_0_ar_bits_size (mmio_arsize), + | .mmio_axi4_0_ar_bits_burst (mmio_arburst), + | .mmio_axi4_0_r_valid (mmio_rvalid), + | .mmio_axi4_0_r_ready (mmio_rready), + | .mmio_axi4_0_r_bits_id (mmio_rid), + | .mmio_axi4_0_r_bits_data (mmio_rdata), + | .mmio_axi4_0_r_bits_resp (mmio_rresp), + | .mmio_axi4_0_r_bits_last (mmio_rlast), + | .serial_tl_0_in_valid (1'b0), + | .serial_tl_0_in_bits_phit (32'h0), + | .serial_tl_0_out_ready (1'b0), + | .serial_tl_0_clock_in (1'b0), + | .custom_boot (1'b0) + | ); + | + | p2e_mmio_zero_slave #( + | .ADDR_BITS(MMIO_ADDR_BITS), + | .DATA_BITS(MMIO_DATA_BITS), + | .ID_BITS(MMIO_ID_BITS) + | ) mmio_stub ( + | .clock (user_clk), + | .reset (soc_reset), + | .aw_ready (mmio_awready), + | .aw_valid (mmio_awvalid), + | .aw_id (mmio_awid), + | .aw_addr (mmio_awaddr), + | .aw_len (mmio_awlen), + | .aw_size (mmio_awsize), + | .aw_burst (mmio_awburst), + | .w_ready (mmio_wready), + | .w_valid (mmio_wvalid), + | .w_data (mmio_wdata), + | .w_strb (mmio_wstrb), + | .w_last (mmio_wlast), + | .b_ready (mmio_bready), + | .b_valid (mmio_bvalid), + | .b_id (mmio_bid), + | .b_resp (mmio_bresp), + | .ar_ready (mmio_arready), + | .ar_valid (mmio_arvalid), + | .ar_id (mmio_arid), + | .ar_addr (mmio_araddr), + | .ar_len (mmio_arlen), + | .ar_size (mmio_arsize), + | .ar_burst (mmio_arburst), + | .r_ready (mmio_rready), + | .r_valid (mmio_rvalid), + | .r_id (mmio_rid), + | .r_data (mmio_rdata), + | .r_resp (mmio_rresp), + | .r_last (mmio_rlast) + | ); + | + | xepic_ddr4_dc1 ddr ( + | .sys_rstn (sys_rstn), + | .c0_sys_clk_p (c0_sys_clk_p), + | .c0_sys_clk_n (c0_sys_clk_n), + | .c0_ddr4_act_n (c0_ddr4_act_n), + | .c0_ddr4_adr (c0_ddr4_adr), + | .c0_ddr4_ba (c0_ddr4_ba), + | .c0_ddr4_bg (c0_ddr4_bg), + | .c0_ddr4_cke (c0_ddr4_cke), + | .c0_ddr4_odt (c0_ddr4_odt), + | .c0_ddr4_cs_n (c0_ddr4_cs_n), + | .c0_ddr4_ck_t (c0_ddr4_ck_t), + | .c0_ddr4_ck_c (c0_ddr4_ck_c), + | .c0_ddr4_reset_n (c0_ddr4_reset_n), + | .c0_ddr4_dm_dbi_n (c0_ddr4_dm_dbi_n), + | .c0_ddr4_dq (c0_ddr4_dq), + | .c0_ddr4_dqs_c (c0_ddr4_dqs_c), + | .c0_ddr4_dqs_t (c0_ddr4_dqs_t), + | .gclk_100m (1'b0), + | .ddr4_en_vtt_bbox (ddr4_en_vtt), + | .ddr4_en_vddq_bbox (ddr4_en_vddq), + | .ddr4_en_vcc2v5_bbox (ddr4_en_vcc2v5), + | .power_good_bbox (power_good), + | .init_start (1'b1), + | .init_cfg (1'b0), + | .init_busy (), + | .init_calib_complete (), + | .c0_init_calib_complete (c0_init_calib_complete), + | .axi_clk (user_clk), + | .s0_ddr4_s_axi_awid (mem_awid), + | .s0_ddr4_s_axi_awaddr (mem_awaddr), + | .s0_ddr4_s_axi_awlen (mem_awlen), + | .s0_ddr4_s_axi_awsize (mem_awsize), + | .s0_ddr4_s_axi_awburst (mem_awburst), + | .s0_ddr4_s_axi_awlock (1'b0), + | .s0_ddr4_s_axi_awcache (4'b0011), + | .s0_ddr4_s_axi_awprot (3'b000), + | .s0_ddr4_s_axi_awqos (4'b0000), + | .s0_ddr4_s_axi_awvalid (mem_awvalid), + | .s0_ddr4_s_axi_awready (mem_awready), + | .s0_ddr4_s_axi_wdata (mem_wdata), + | .s0_ddr4_s_axi_wstrb (mem_wstrb), + | .s0_ddr4_s_axi_wlast (mem_wlast), + | .s0_ddr4_s_axi_wvalid (mem_wvalid), + | .s0_ddr4_s_axi_wready (mem_wready), + | .s0_ddr4_s_axi_bready (mem_bready), + | .s0_ddr4_s_axi_bid (mem_bid), + | .s0_ddr4_s_axi_bresp (mem_bresp), + | .s0_ddr4_s_axi_bvalid (mem_bvalid), + | .s0_ddr4_s_axi_arid (mem_arid), + | .s0_ddr4_s_axi_araddr (mem_araddr), + | .s0_ddr4_s_axi_arlen (mem_arlen), + | .s0_ddr4_s_axi_arsize (mem_arsize), + | .s0_ddr4_s_axi_arburst (mem_arburst), + | .s0_ddr4_s_axi_arlock (1'b0), + | .s0_ddr4_s_axi_arcache (4'b0011), + | .s0_ddr4_s_axi_arprot (3'b000), + | .s0_ddr4_s_axi_arqos (4'b0000), + | .s0_ddr4_s_axi_arvalid (mem_arvalid), + | .s0_ddr4_s_axi_arready (mem_arready), + | .s0_ddr4_s_axi_rready (mem_rready), + | .s0_ddr4_s_axi_rid (mem_rid), + | .s0_ddr4_s_axi_rdata (mem_rdata), + | .s0_ddr4_s_axi_rresp (mem_rresp), + | .s0_ddr4_s_axi_rlast (mem_rlast), + | .s0_ddr4_s_axi_rvalid (mem_rvalid), + | .c0_ddr4_ui_clk (c0_ddr4_ui_clk), + | .s1_ddr4_s_axi_awid (4'b0), + | .s1_ddr4_s_axi_awaddr (64'b0), + | .s1_ddr4_s_axi_awlen (8'b0), + | .s1_ddr4_s_axi_awsize (3'b0), + | .s1_ddr4_s_axi_awburst (2'b0), + | .s1_ddr4_s_axi_awlock (1'b0), + | .s1_ddr4_s_axi_awcache (4'b0), + | .s1_ddr4_s_axi_awprot (3'b0), + | .s1_ddr4_s_axi_awqos (4'b0), + | .s1_ddr4_s_axi_awvalid (1'b0), + | .s1_ddr4_s_axi_awready (), + | .s1_ddr4_s_axi_wdata (256'b0), + | .s1_ddr4_s_axi_wstrb (32'b0), + | .s1_ddr4_s_axi_wlast (1'b0), + | .s1_ddr4_s_axi_wvalid (1'b0), + | .s1_ddr4_s_axi_wready (), + | .s1_ddr4_s_axi_bready (1'b1), + | .s1_ddr4_s_axi_bid (), + | .s1_ddr4_s_axi_bresp (), + | .s1_ddr4_s_axi_bvalid (), + | .s1_ddr4_s_axi_arid (4'b0), + | .s1_ddr4_s_axi_araddr (64'b0), + | .s1_ddr4_s_axi_arlen (8'b0), + | .s1_ddr4_s_axi_arsize (3'b0), + | .s1_ddr4_s_axi_arburst (2'b0), + | .s1_ddr4_s_axi_arlock (1'b0), + | .s1_ddr4_s_axi_arcache (4'b0), + | .s1_ddr4_s_axi_arprot (3'b0), + | .s1_ddr4_s_axi_arqos (4'b0), + | .s1_ddr4_s_axi_arvalid (1'b0), + | .s1_ddr4_s_axi_arready (), + | .s1_ddr4_s_axi_rready (1'b1), + | .s1_ddr4_s_axi_rid (), + | .s1_ddr4_s_axi_rdata (), + | .s1_ddr4_s_axi_rresp (), + | .s1_ddr4_s_axi_rlast (), + | .s1_ddr4_s_axi_rvalid () + | ); + |endmodule + """.stripMargin + ) +} + +class P2ETop extends RawModule { + val io = IO(new P2ETopIO) + + val top = Module(new P2ETopBlackBox) + top.io.user_clk := io.user_clk + top.io.sys_rstn := io.sys_rstn + top.io.c0_sys_clk_p := io.c0_sys_clk_p + top.io.c0_sys_clk_n := io.c0_sys_clk_n + io.c0_ddr4_act_n := top.io.c0_ddr4_act_n + io.c0_ddr4_adr := top.io.c0_ddr4_adr + io.c0_ddr4_ba := top.io.c0_ddr4_ba + io.c0_ddr4_bg := top.io.c0_ddr4_bg + io.c0_ddr4_cke := top.io.c0_ddr4_cke + io.c0_ddr4_odt := top.io.c0_ddr4_odt + io.c0_ddr4_cs_n := top.io.c0_ddr4_cs_n + io.c0_ddr4_ck_t := top.io.c0_ddr4_ck_t + io.c0_ddr4_ck_c := top.io.c0_ddr4_ck_c + io.c0_ddr4_reset_n := top.io.c0_ddr4_reset_n + attach(io.c0_ddr4_dm_dbi_n, top.io.c0_ddr4_dm_dbi_n) + attach(io.c0_ddr4_dq, top.io.c0_ddr4_dq) + attach(io.c0_ddr4_dqs_c, top.io.c0_ddr4_dqs_c) + attach(io.c0_ddr4_dqs_t, top.io.c0_ddr4_dqs_t) + io.c0_ddr4_ui_clk := top.io.c0_ddr4_ui_clk + io.init_calib_complete := top.io.init_calib_complete + io.ddr4_en_vtt := top.io.ddr4_en_vtt + io.ddr4_en_vddq := top.io.ddr4_en_vddq + io.ddr4_en_vcc2v5 := top.io.ddr4_en_vcc2v5 + top.io.power_good := io.power_good +} + +object ElaborateP2ETop extends App { + import _root_.circt.stage.ChiselStage + + ChiselStage.emitSystemVerilogFile( + new P2ETop, + firtoolOpts = args, + args = Array.empty + ) +} diff --git a/arch/src/main/scala/sims/p2e/TargetConfigs.scala b/arch/src/main/scala/sims/p2e/TargetConfigs.scala new file mode 100644 index 00000000..25b56048 --- /dev/null +++ b/arch/src/main/scala/sims/p2e/TargetConfigs.scala @@ -0,0 +1,79 @@ +package sims.p2e + +import chisel3._ +import _root_.circt.stage.ChiselStage +import org.chipsalliance.cde.config.Config + +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} +import freechips.rocketchip.subsystem.{InSubsystem, WithCustomMMIOPort, WithCustomMemPort} +import sims.p2e.scu.WithP2ESCU + +class WithP2EBootROM + extends Config((site, here, up) => { + case BootROMLocated(InSubsystem) => Some(BootROMParams( + contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" + )) + }) + +class WithP2EDDR4MemPort + extends Config( + new WithCustomMemPort( + base_addr = BigInt("80000000", 16), + base_size = BigInt("10000000", 16), + data_width = 256, + id_bits = 11, + maxXferBytes = 256 + ) + ) + +class P2EBaseConfig + extends Config( + new WithP2EHarness ++ + new WithP2ESCU ++ + new WithCustomMMIOPort( + base_addr = BigInt("60040000", 16), + base_size = BigInt("1ffc0000", 16), + data_width = 64, + id_bits = 4, + maxXferBytes = 64 + ) ++ + new WithP2EDDR4MemPort ++ + new WithP2EBootROM + ) + +class P2EToyConfig + extends Config( + new P2EBaseConfig ++ + new examples.toy.BuckyballToyConfig + ) + +object Elaborate extends App { + if (args.isEmpty) { + println("Usage: Elaborate [firtool-opts...]") + println("Example: Elaborate sims.p2e.P2EToyConfig") + sys.exit(1) + } + + val configClassName = args(0) + println(s"Elaborating P2EHarness with config: $configClassName") + + val config: Config = + try { + val configClass = Class.forName(configClassName) + configClass.getDeclaredConstructor().newInstance().asInstanceOf[Config] + } catch { + case e: ClassNotFoundException => + println(s"Error: Config class not found: $configClassName") + sys.exit(1) + case e: Exception => + println(s"Error loading config class: ${e.getMessage}") + e.printStackTrace() + sys.exit(1) + } + + ChiselStage.emitSystemVerilogFile( + new P2EHarness()(config.toInstance), + firtoolOpts = args.drop(1), + args = Array.empty + ) +} diff --git a/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala b/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala new file mode 100644 index 00000000..4463f00b --- /dev/null +++ b/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala @@ -0,0 +1,120 @@ +package sims.p2e.scu + +import chisel3._ +import chisel3.util.HasBlackBoxInline +import org.chipsalliance.cde.config.{Config, Field, Parameters} + +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ + +case class P2ESCUParams( + address: BigInt = BigInt("60000000", 16), + size: BigInt = BigInt("40000", 16)) + +case object P2ESCUKey extends Field[Option[P2ESCUParams]](None) + +class WithP2ESCU( + address: BigInt = BigInt("60000000", 16), + size: BigInt = BigInt("40000", 16)) + extends Config((site, here, up) => { + case P2ESCUKey => Some(P2ESCUParams(address = address, size = size)) + }) + +class P2ESCUWriteDPI(hartId: Int) extends BlackBox with HasBlackBoxInline { + override def desiredName = s"P2ESCUWriteDPI_$hartId" + + val io = IO(new Bundle { + val clock = Input(Clock()) + val reset = Input(Bool()) + val uart_valid = Input(Bool()) + val uart_data = Input(UInt(8.W)) + val exit_valid = Input(Bool()) + val exit_code = Input(UInt(32.W)) + }) + + setInline( + s"P2ESCUWriteDPI_$hartId.v", + s""" + |import "DPI-C" context function void p2e_uart_write(input int hart_id, input byte ch); + |import "DPI-C" context function void p2e_sim_exit(input int hart_id, input int code); + | + |module P2ESCUWriteDPI_$hartId( + | input clock, + | input reset, + | input uart_valid, + | input [7:0] uart_data, + | input exit_valid, + | input [31:0] exit_code + |); + | export "DPI-C" function p2e_scu_${hartId}_hart_id; + | function int p2e_scu_${hartId}_hart_id(); + | p2e_scu_${hartId}_hart_id = $hartId; + | endfunction + | + | always @(posedge clock) begin + | if (!reset) begin + | if (uart_valid) begin + | p2e_uart_write($hartId, uart_data); + | end + | + | if (exit_valid) begin + | p2e_sim_exit($hartId, exit_code); + | end + | end + | end + |endmodule + """.stripMargin + ) +} + +class TLP2ESCU(params: P2ESCUParams, beatBytes: Int, hartId: Int)(implicit p: Parameters) extends LazyModule { + require(params.size > 0) + require(params.size.isValidInt) + require((params.size & (params.size - 1)) == 0, "P2E SCU size must be a power of two") + + val device = new SimpleDevice(s"p2e-scu-$hartId", Seq("buckyball,p2e-scu")) + + val node = TLRegisterNode( + address = Seq(AddressSet(params.address, params.size - 1)), + device = device, + deviceKey = "reg/control", + beatBytes = beatBytes + ) + + lazy val module = new LazyModuleImp(this) { + val uartValid = WireDefault(false.B) + val uartData = WireDefault(0.U(8.W)) + val exitValid = WireDefault(false.B) + val exitCode = WireDefault(0.U(32.W)) + + val dpi = Module(new P2ESCUWriteDPI(hartId)) + dpi.io.clock := clock + dpi.io.reset := reset.asBool + dpi.io.uart_valid := RegNext(uartValid, false.B) + dpi.io.uart_data := RegNext(uartData, 0.U) + dpi.io.exit_valid := RegNext(exitValid, false.B) + dpi.io.exit_code := RegNext(exitCode, 0.U) + + val simExitWrite = RegWriteFn { (valid, data) => + exitValid := valid + exitCode := data(31, 0) + true.B + } + + val uartWrite = RegWriteFn { (valid, data) => + uartValid := valid + uartData := data(7, 0) + true.B + } + + node.regmap( + 0x00000 -> Seq(RegField.w(32, simExitWrite)), + 0x20000 -> Seq(RegField.w(8, uartWrite)), + 0x20005 -> Seq(RegField.r(8, "h60".U)) + ) + } + +} diff --git a/arch/src/main/scala/sims/palladium/TargetConfigs.scala b/arch/src/main/scala/sims/palladium/TargetConfigs.scala deleted file mode 100644 index 52da638a..00000000 --- a/arch/src/main/scala/sims/palladium/TargetConfigs.scala +++ /dev/null @@ -1,19 +0,0 @@ -package sims.palladium - -import org.chipsalliance.cde.config.Config -import chipyard._ - -// class BuckyballToyP2EConfig -// extends Config( -// new palladium.fpga.WithFPGAFrequency(50) ++ -// new palladium.fpga.WithVCU19PTweaks ++ -// new examples.toy.BuckyballToy256Config // Test with 256 cores + 8 L2 banks -// ) - -// // Cross-bar config -// class BuckyballToyP2ECBConfig -// extends Config( -// new palladium.fpga.WithFPGAFrequency(50) ++ -// new palladium.fpga.WithVCU19PTweaks ++ -// new examples.toy.BuckyballToy256CBConfig -// ) diff --git a/arch/src/main/scala/sims/verify/TargetConfig.scala b/arch/src/main/scala/sims/verify/TargetConfig.scala deleted file mode 100644 index 5bbcfa1d..00000000 --- a/arch/src/main/scala/sims/verify/TargetConfig.scala +++ /dev/null @@ -1,82 +0,0 @@ -package sims.verify - -import chisel3._ -import _root_.circt.stage.ChiselStage -import framework.top.GlobalConfig -import framework.balldomain.blink.{BlinkIO, HasBlink} -import framework.balldomain.prototype.vector.VecBall -import framework.balldomain.prototype.relu.ReluBall -import framework.balldomain.prototype.im2col.Im2colBall -import framework.balldomain.prototype.transpose.TransposeBall - -sealed trait BallType -case object VecBallType extends BallType -case object MatrixBallType extends BallType -case object TransposeBallType extends BallType -case object Im2colBallType extends BallType -case object ReluBallType extends BallType -case object NNLutBallType extends BallType - -class TargetBall(ballType: BallType, b: GlobalConfig) extends Module with HasBlink { - - val ballName = ballType match { - case VecBallType => "VecBall" - case ReluBallType => "ReluBall" - case Im2colBallType => "Im2colBall" - case TransposeBallType => "TransposeBall" - case MatrixBallType => throw new IllegalArgumentException("MatrixBall not implemented") - case NNLutBallType => throw new IllegalArgumentException("NNLutBall not implemented") - case _ => throw new scala.MatchError("TargetBall does not handle this ball type") - } - - val mapping = b.ballDomain.ballIdMappings.find(_.ballName == ballName) - .getOrElse(throw new IllegalArgumentException(s"$ballName not found in config")) - val inBW = mapping.inBW - val outBW = mapping.outBW - - val io = IO(new BlinkIO(b, inBW, outBW)) - - def blink: BlinkIO = io - - val ball = ballType match { - case VecBallType => Module(new VecBall(b)) - case ReluBallType => Module(new ReluBall(b)) - case Im2colBallType => Module(new Im2colBall(b)) - case TransposeBallType => Module(new TransposeBall(b)) - case _ => throw new scala.MatchError("TargetBall does not handle this ball type") - } - - io <> ball.blink -} - -object BallTopMain extends App { - - // Select Ball type from command line arguments - val ballType = - if (args.isEmpty) { - println("Usage: BallTopMain [firtool-opts...]") - println("Available ball types: vecball, matrixball, transposeball, im2colball, reluball, nnlutball") - println("Using default: vecball") - VecBallType - } else { - args(0).toLowerCase match { - case "vecball" => VecBallType - case "matrixball" => MatrixBallType - case "transposeball" => TransposeBallType - case "im2colball" => Im2colBallType - case "reluball" => ReluBallType - case "nnlutball" => NNLutBallType - case other => - println(s"Unknown ball type: $other, using vecball") - VecBallType - } - } - - val b: GlobalConfig = GlobalConfig() - - ChiselStage.emitSystemVerilogFile( - new TargetBall(ballType, b), - firtoolOpts = args.drop(1), - args = Array.empty - ) -} diff --git a/bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c b/bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c deleted file mode 100644 index 27d981be..00000000 --- a/bb-tests/workloads/lib/bbhw/isa/54_bdb_backdoor.c +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _BDB_BACKDOOR_H_ -#define _BDB_BACKDOOR_H_ - -#include "isa.h" - -#define BDB_BACKDOOR_FUNC7 54 - -// Backdoor write: DPI-C provides data, write to external bank -// bank_id = target bank, iter = number of rows -#define bdb_backdoor_write(bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK2(bank_id) | BB_ITER(iter)), 0, \ - BDB_BACKDOOR_FUNC7) - -// Backdoor read: read from external bank, output via DPI-C -// bank_id = source bank, iter = number of rows -#define bdb_backdoor_read(bank_id, iter) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_ITER(iter)), 0, \ - BDB_BACKDOOR_FUNC7) - -// Backdoor peek: read single row from external bank -#define bdb_backdoor_peek(bank_id, row_count) \ - BUCKYBALL_INSTRUCTION_R_R((BB_BANK0(bank_id) | BB_ITER(row_count)), 0, \ - BDB_BACKDOOR_FUNC7) - -#endif // _BDB_BACKDOOR_H_ diff --git a/bb-tests/workloads/lib/bbhw/isa/87_gemmini_loop_ws.c b/bb-tests/workloads/lib/bbhw/isa/80_gemmini_loop_ws.c similarity index 100% rename from bb-tests/workloads/lib/bbhw/isa/87_gemmini_loop_ws.c rename to bb-tests/workloads/lib/bbhw/isa/80_gemmini_loop_ws.c diff --git a/bb-tests/workloads/lib/bbhw/isa/105_gemmini_loop_conv_ws.c b/bb-tests/workloads/lib/bbhw/isa/96_gemmini_loop_conv_ws.c similarity index 100% rename from bb-tests/workloads/lib/bbhw/isa/105_gemmini_loop_conv_ws.c rename to bb-tests/workloads/lib/bbhw/isa/96_gemmini_loop_conv_ws.c diff --git a/bb-tests/workloads/lib/bbhw/isa/isa.h b/bb-tests/workloads/lib/bbhw/isa/isa.h index 02ab92d9..0cd5c8ef 100644 --- a/bb-tests/workloads/lib/bbhw/isa/isa.h +++ b/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -46,7 +46,6 @@ typedef int32_t result_t; #include "02_gemmini_config.c" #include "03_gemmini_flush.c" #include "04_bdb_counter.c" -#include "105_gemmini_loop_conv_ws.c" #include "16_mvout.c" #include "32_mset.c" #include "33_mvin.c" @@ -56,11 +55,11 @@ typedef int32_t result_t; #include "51_quant.c" #include "52_dequant.c" #include "53_gemmini_preload.c" -#include "54_bdb_backdoor.c" #include "64_mul_warp16.c" #include "65_bfp.c" #include "66_gemmini_compute_preloaded.c" #include "67_gemmini_compute_accumulated.c" -#include "87_gemmini_loop_ws.c" +#include "80_gemmini_loop_ws.c" +#include "96_gemmini_loop_conv_ws.c" #endif // BUCKYBALL_ISA_H diff --git a/bb-tests/workloads/lib/kernel b/bb-tests/workloads/lib/kernel index 7e2d56dd..35424fd0 160000 --- a/bb-tests/workloads/lib/kernel +++ b/bb-tests/workloads/lib/kernel @@ -1 +1 @@ -Subproject commit 7e2d56dd4d7fce7b79612d79d0c37e3cfc22311f +Subproject commit 35424fd00242b718bacd1484e516e85485d198e1 diff --git a/bb-tests/workloads/src/CTest/goban/goban.h b/bb-tests/workloads/src/CTest/goban/goban.h index 45f40bb8..68833ecc 100644 --- a/bb-tests/workloads/src/CTest/goban/goban.h +++ b/bb-tests/workloads/src/CTest/goban/goban.h @@ -1,14 +1,54 @@ #ifndef GOBAN_H #define GOBAN_H -#include #include +#include + +/* + * Goban's hardware barrier is tile-local. The default Goban tile currently has + * four RocketBB cores, while BuckyballGoban2TileConfig exposes global mhartid + * values 0..7. Tests should use the tile-local core id for per-tile arrays and + * bank ownership. + */ +#ifndef GOBAN_CORES_PER_TILE +#define GOBAN_CORES_PER_TILE 4 +#endif + +#ifndef GOBAN_MAX_TILES +#define GOBAN_MAX_TILES 2 +#endif -/* Read hart ID from CSR mhartid */ -static inline int bb_get_core_id(void) { +#define GOBAN_MAX_HARTS (GOBAN_CORES_PER_TILE * GOBAN_MAX_TILES) +#define GOBAN_SHARED_BANK_BASE 32 + +static inline int bb_get_hart_id(void) { int hartid; asm volatile("csrr %0, mhartid" : "=r"(hartid)); return hartid; } +static inline int bb_get_tile_core_id(void) { + return bb_get_hart_id() % GOBAN_CORES_PER_TILE; +} + +static inline int bb_get_tile_id(void) { + return bb_get_hart_id() / GOBAN_CORES_PER_TILE; +} + +static inline int bb_get_core_id(void) { return bb_get_tile_core_id(); } + +static inline int bb_shared_bank(int vbank_id) { + return GOBAN_SHARED_BANK_BASE + vbank_id; +} + +static inline void bb_cpu_fence(void) { + asm volatile("fence rw, rw" ::: "memory"); +} + +static inline void bb_tile_barrier(void) { + bb_cpu_fence(); + bb_barrier(); + bb_cpu_fence(); +} + #endif // GOBAN_H diff --git a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt index fbbf56ba..406b38ca 100644 --- a/bb-tests/workloads/src/CTest/toy/CMakeLists.txt +++ b/bb-tests/workloads/src/CTest/toy/CMakeLists.txt @@ -119,7 +119,6 @@ add_cross_platform_test_target(ctest_quant_test quant_test.c) add_cross_platform_test_target(ctest_dequant_test dequant_test.c) add_cross_platform_test_target(ctest_tlb_test tlb_test.c) add_cross_platform_test_target(ctest_bdb_counter_test bdb_counter_test.c) -add_cross_platform_test_target(ctest_bdb_backdoor_test bdb_backdoor_test.c) add_cross_platform_test_target(ctest_gemmini_os_risc_basic_test gemmini_os_risc_basic_test.c) add_cross_platform_test_target(ctest_gemmini_os_risc_shift_test gemmini_os_risc_shift_test.c) add_cross_platform_test_target(ctest_gemmini_os_risc_atranspose_test gemmini_os_risc_atranspose_test.c) @@ -162,7 +161,6 @@ add_custom_target(buckyball-CTest-build ALL DEPENDS ctest_dequant_test ctest_tlb_test ctest_bdb_counter_test - ctest_bdb_backdoor_test ctest_gemmini_os_risc_basic_test ctest_gemmini_os_risc_shift_test ctest_gemmini_os_risc_atranspose_test diff --git a/bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c b/bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c deleted file mode 100644 index be04c941..00000000 --- a/bb-tests/workloads/src/CTest/toy/bdb_backdoor_test.c +++ /dev/null @@ -1,52 +0,0 @@ -#include "buckyball.h" -#include -#include -#include -#include -#include - -// Test bdb_backdoor: SRAM backdoor write + read via DPI-C -// -// C++ side (ctrace.cc) generates test data: each 128-bit row is filled -// with (row*16 + byte_offset) & 0xFF pattern via generate_test_data(). -// -// Flow: -// 1. bdb_backdoor_write: C++ generates (row, data) per iteration via DPI-C, -// RTL writes to external bank 0 -// 2. bdb_backdoor_read: RTL reads bank 0, sends data back via DPI-C, -// C++ logs to bdb.log as [BANK-TRACE] -// 3. mvout + fence: verify data was actually written (no hang = pass) - -#define DIM 16 - -static elem_t output_matrix[DIM * DIM] __attribute__((aligned(64))); - -int main() { -#ifdef MULTICORE - multicore(MULTICORE); -#endif - - // Build expected pattern (must match C++ generate_test_data): - // row i, byte j -> (i*16 + j) & 0xFF - - uint32_t bank_id = 0; - bb_mem_alloc(bank_id, 1, 1); - - // C++ injects DIM rows into bank 0 via DPI-C (data decided by C++) - bdb_backdoor_write(bank_id, DIM); - - // Dump bank 0 contents to bdb.log via DPI-C - bdb_backdoor_read(bank_id, DIM); - - // mvout to verify data integrity - clear_i8_matrix(output_matrix, DIM, DIM); - bb_mvout((uintptr_t)output_matrix, bank_id, DIM, 1); - bb_fence(); - - printf("bdb_backdoor test PASSED\n"); - return 0; - -#ifdef MULTICORE - exit(0); -#endif -} diff --git a/bbdev b/bbdev index df84247c..8823f20d 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit df84247ce206d0591740bec7db5d898ecab3b0dd +Subproject commit 8823f20dd0940a029ef6db59ef70408aa9805998 diff --git a/bebop b/bebop index 2c08a098..f03720d5 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 2c08a098fe5dd446c666d620482ec04f00f89223 +Subproject commit f03720d5d5767aeb9fab77f123ed63f4e6772dbd diff --git a/scripts/claude/README.md b/scripts/claude/README.md index d489d9c9..f40ae6c8 100644 --- a/scripts/claude/README.md +++ b/scripts/claude/README.md @@ -21,7 +21,7 @@ User ──→ Claude Code (slash commands + CLAUDE.md) │ └── bbdev server (Motia workflow backend, lifecycle managed by MCP) ├── POST /verilator/run Full flow: clean->verilog->build->sim - ├── POST /verilator/verilog Generate Verilog (supports --balltype) + ├── POST /verilator/verilog Generate Verilog ├── POST /verilator/build Build Verilator (supports --coverage) ├── POST /verilator/sim Run simulation (supports --coverage) ├── POST /workload/build Build CTest diff --git a/scripts/claude/mcp_server.py b/scripts/claude/mcp_server.py index a5502120..04f4b611 100644 --- a/scripts/claude/mcp_server.py +++ b/scripts/claude/mcp_server.py @@ -295,15 +295,10 @@ def bbdev_verilator_run( @mcp.tool() def bbdev_verilator_verilog( - config: Optional[str] = None, - balltype: Optional[str] = None, + config: str, ) -> str: - """Generate Verilog from Chisel. Supports --balltype for single Ball elaboration. Calls bbdev POST /verilator/verilog.""" - api_params: Dict[str, Any] = {} - if config: - api_params["config"] = config - if balltype: - api_params["balltype"] = balltype + """Generate Verilog from Chisel. Calls bbdev POST /verilator/verilog.""" + api_params: Dict[str, Any] = {"config": config} result = _bbdev_call("/verilator/verilog", api_params, timeout=600) return _fmt(result) diff --git a/scripts/nix/build-env-tools.nix b/scripts/nix/build-env-tools.nix index 07edb2d0..34792be1 100644 --- a/scripts/nix/build-env-tools.nix +++ b/scripts/nix/build-env-tools.nix @@ -1,7 +1,7 @@ { pkgs }: let - # DRAMSim2 from firesim (rev matches chipyard pin); -fPIC for PIE linking under Nix + # DRAMSim2 from firesim (rev matches chipyard pin); -fPIE for PIE linking under Nix dramsim2 = pkgs.stdenv.mkDerivation { pname = "dramsim2"; version = "2023-05-10"; @@ -12,7 +12,7 @@ let hash = "sha256-Vfb+MeWdUESc7gt6GhL6jBO1Uuvx8s1BdfhCikTyTh8="; }; buildPhase = '' - make CXXFLAGS="-DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -fPIC" libdramsim.a + make CXXFLAGS="-DNO_STORAGE -Wall -DDEBUG_BUILD -O3 -fPIE" libdramsim.a ''; installPhase = '' runHook preInstall From a549213d67cecc5cf1c1fe91ed9970a4445331cd Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 30 Apr 2026 23:25:19 +0800 Subject: [PATCH 232/238] [arch] feat: add per-tile private L2 cache configurations for Goban and Toy examples, enhance BBTile with L2 cache support --- .../scala/examples/goban/CustomConfigs.scala | 82 +++++++++++++++++++ .../scala/examples/toy/CustomConfigs.scala | 64 +++++++++++++++ .../scala/framework/core/bbtile/BBTile.scala | 54 +++++++++++- .../framework/core/bbtile/BBTileParams.scala | 29 +++++++ .../scala/framework/core/bbtile/Configs.scala | 8 +- .../main/scala/sims/p2e/TargetConfigs.scala | 2 + arch/src/main/scala/sims/p2e/scu/P2ESCU.scala | 4 +- bebop | 2 +- 8 files changed, 239 insertions(+), 6 deletions(-) diff --git a/arch/src/main/scala/examples/goban/CustomConfigs.scala b/arch/src/main/scala/examples/goban/CustomConfigs.scala index 08bc392a..08f1b1ee 100644 --- a/arch/src/main/scala/examples/goban/CustomConfigs.scala +++ b/arch/src/main/scala/examples/goban/CustomConfigs.scala @@ -2,6 +2,7 @@ package examples.goban import org.chipsalliance.cde.config.Config import examples.goban.tiles.WithNGobanTiles +import framework.core.bbtile.L2CacheParams /** 1 BBTile × 4 buckyball slots (shared SharedMem + BarrierUnit) */ class BuckyballGobanConfig @@ -19,3 +20,84 @@ class BuckyballGoban2TileConfig new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig ) + +// ============================================================================== +// Per-Tile Private L2 Cache Configurations +// ============================================================================== + +/** + * Helper config fragment to add per-tile L2 to all Goban tiles. + * + * Usage: new WithGobanPerTileL2(ways = 4, capacityKB = 512) ++ + * + * @param ways Number of ways (associativity) + * @param capacityKB L2 cache size in KB per tile + * @param memCycles Memory round-trip latency in cycles + */ +class WithGobanPerTileL2( + ways: Int = 8, + capacityKB: Int = 512, + memCycles: Int = 10) + extends Config((site, here, up) => { + case framework.core.bbtile.BBTileAttachParams(tileParams, crossing) => + val cacheBlockBytes = site(freechips.rocketchip.subsystem.CacheBlockBytes) + val sets = (capacityKB * 1024) / (cacheBlockBytes * ways) + framework.core.bbtile.BBTileAttachParams( + tileParams.copy( + l2cache = Some(L2CacheParams( + ways = ways, + sets = sets, + writeBytes = 8, + portFactor = 2, + memCycles = memCycles + )) + ), + crossing + ) + }) + +/** + * Goban configuration with per-tile private L2 cache. + * + * 1 BBTile with 512KB private L2 (8-way, 256 sets, 64B blocks). + * Each tile has 4 Buckyball slots sharing the tile's L2. + * System-level L3 (InclusiveCache) maintains coherence. + */ +class BuckyballGobanConfigWithL2 + extends Config( + new WithGobanPerTileL2(ways = 8, capacityKB = 512) ++ + new WithNGobanTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) + +/** + * 2-tile Goban configuration with per-tile private L2. + * + * 2 BBTiles, each with 512KB private L2 (8-way). + * Total: 8 Buckyball slots (4 per tile), 1MB total L2 cache. + * Reduces inter-tile L2 contention for multi-tile workloads. + */ +class BuckyballGoban2TileConfigWithL2 + extends Config( + new WithGobanPerTileL2(ways = 8, capacityKB = 512) ++ + new WithNGobanTiles ++ + new WithNGobanTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) + +/** + * Large L2 configuration for compute-intensive workloads. + * + * 2 BBTiles, each with 1MB private L2 (8-way, 512 sets). + * Total: 2MB L2 cache for better working set coverage. + */ +class BuckyballGoban2TileConfigWithLargeL2 + extends Config( + new WithGobanPerTileL2(ways = 8, capacityKB = 1024) ++ + new WithNGobanTiles ++ + new WithNGobanTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) diff --git a/arch/src/main/scala/examples/toy/CustomConfigs.scala b/arch/src/main/scala/examples/toy/CustomConfigs.scala index b188a124..fc462946 100644 --- a/arch/src/main/scala/examples/toy/CustomConfigs.scala +++ b/arch/src/main/scala/examples/toy/CustomConfigs.scala @@ -2,6 +2,7 @@ package examples.toy import org.chipsalliance.cde.config.Config import examples.toy.tiles.WithNToyTiles +import framework.core.bbtile.{L2CacheParams, WithBBTile} import freechips.rocketchip.subsystem.{InCluster, InSubsystem} import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} @@ -34,3 +35,66 @@ class WithLargeBootROM(address: BigInt = 0x80000, size: Int = 0x80000) case BootROMLocated(InSubsystem) => up(BootROMLocated(InSubsystem)).map(_.copy(address = address, size = size)) }) + +// ============================================================================== +// Per-Tile Private L2 Cache Configurations +// ============================================================================== + +/** + * Helper config fragment to add per-tile L2 to all tiles. + * + * Usage: new WithPerTileL2(ways = 4, capacityKB = 256) ++ + * + * @param ways Number of ways (associativity) + * @param capacityKB L2 cache size in KB per tile + * @param memCycles Memory round-trip latency in cycles + */ +class WithPerTileL2( + ways: Int = 4, + capacityKB: Int = 256, + memCycles: Int = 10) + extends Config((site, here, up) => { + case framework.core.bbtile.BBTileAttachParams(tileParams, crossing) => + val cacheBlockBytes = site(freechips.rocketchip.subsystem.CacheBlockBytes) + val sets = (capacityKB * 1024) / (cacheBlockBytes * ways) + framework.core.bbtile.BBTileAttachParams( + tileParams.copy( + l2cache = Some(L2CacheParams( + ways = ways, + sets = sets, + writeBytes = 8, + portFactor = 2, + memCycles = memCycles + )) + ), + crossing + ) + }) + +/** + * Toy configuration with per-tile private L2 cache. + * + * Each BBTile gets a 256KB private L2 (4-way, 256 sets, 64B blocks). + * System-level L3 (InclusiveCache) is still present for coherence. + */ +class BuckyballToyConfigWithL2 + extends Config( + new WithPerTileL2(ways = 4, capacityKB = 256) ++ + new WithNToyTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) + +/** + * Multi-tile configuration with per-tile L2. + * + * Each tile has 512KB private L2, plus shared system-level L3. + * Suitable for compute-intensive workloads with good locality. + */ +class BuckyballToyMultiTileWithL2 + extends Config( + new WithPerTileL2(ways = 8, capacityKB = 512, memCycles = 10) ++ + new WithNToyTiles ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig + ) diff --git a/arch/src/main/scala/framework/core/bbtile/BBTile.scala b/arch/src/main/scala/framework/core/bbtile/BBTile.scala index 047a5f89..65cf8c7a 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTile.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTile.scala @@ -42,6 +42,8 @@ import framework.memdomain.backend.MemRequestIO import framework.memdomain.backend.shared.SharedMemBackend import framework.memdomain.frontend.outside_channel.MemConfigerIO import sims.p2e.scu.{P2ESCUKey, TLP2ESCU} +import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} +import freechips.rocketchip.tilelink.{TLCacheCork, TLFilter} /** * BBTile — a composable tile containing one Rocket core + optional per-core-index Buckyball slots. @@ -174,6 +176,42 @@ class BBTile private ( tlOtherMastersNode :=* TLWidthWidget(cfg0.memDomain.dma_buswidth / 8) := TLBuffer() := bb_xbar } + // --------------------------------------------------------------------------- + // Per-tile private L2 cache (optional) + // --------------------------------------------------------------------------- + val tileL2 = bbParams.l2cache.map { l2params => + val l2 = LazyModule(new InclusiveCache( + CacheParameters( + level = 2, + ways = l2params.ways, + sets = l2params.sets, + blockBytes = p(freechips.rocketchip.subsystem.CacheBlockBytes), + beatBytes = masterPortBeatBytes, + hintsSkipProbe = false + ), + InclusiveCacheMicroParameters( + writeBytes = l2params.writeBytes, + portFactor = l2params.portFactor, + memCycles = l2params.memCycles, + innerBuf = l2params.bufInnerInterior, + outerBuf = l2params.bufOuterInterior + ), + None // No control port for per-tile L2 + )) + l2.suggestName(s"tile_l2_${bbParams.tileId}") + + // Create buffers and cork for L2 + val l2_inner_buffer = l2params.bufInnerExterior() + val l2_outer_buffer = l2params.bufOuterExterior() + val cork = LazyModule(new TLCacheCork) + + l2_inner_buffer.suggestName(s"tile_l2_${bbParams.tileId}_inner_buffer") + l2_outer_buffer.suggestName(s"tile_l2_${bbParams.tileId}_outer_buffer") + cork.suggestName(s"tile_l2_${bbParams.tileId}_cork") + + (l2, l2_inner_buffer, l2_outer_buffer, cork) + } + // --------------------------------------------------------------------------- // TileLink topology // --------------------------------------------------------------------------- @@ -187,7 +225,21 @@ class BBTile private ( } tlOtherMastersNode := tile_master_blocker.map(_.node := tlMasterXbar.node).getOrElse(tlMasterXbar.node) - masterNode :=* tlOtherMastersNode + + // Route through L2 if present, otherwise connect directly to masterNode + tileL2 match { + case Some((l2, innerBuf, outerBuf, cork)) => + // Topology: tlOtherMastersNode -> innerBuf -> L2 -> outerBuf -> cork -> masterNode + innerBuf.node :*= tlOtherMastersNode + l2.node :*= innerBuf.node + outerBuf.node :*= l2.node + cork.node :*= outerBuf.node + masterNode :=* cork.node + case None => + // Direct connection (original behavior) + masterNode :=* tlOtherMastersNode + } + DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) // DCache port count: core + PTW(via usingVM) + DTIM + vector + RoCC tieoff diff --git a/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala b/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala index ef66ff4e..6231aaa3 100644 --- a/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala +++ b/arch/src/main/scala/framework/core/bbtile/BBTileParams.scala @@ -7,6 +7,31 @@ import freechips.rocketchip.prci.ClockSinkParameters import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile.LookupByHartIdImpl import framework.top.GlobalConfig +import sifive.blocks.inclusivecache.InclusiveCachePortParameters + +/** + * Parameters for per-tile private L2 cache. + * + * @param ways Number of ways (associativity) + * @param sets Number of sets + * @param writeBytes Backing store update granularity + * @param portFactor numSubBanks = (widest TL port * portFactor) / writeBytes + * @param memCycles Number of L2 clock cycles for a memory round-trip + * @param bufInnerInterior Buffer parameters for inner interior (towards cores, inside scheduler) + * @param bufInnerExterior Buffer parameters for inner exterior (towards cores, outside scheduler) + * @param bufOuterInterior Buffer parameters for outer interior (towards memory, inside scheduler) + * @param bufOuterExterior Buffer parameters for outer exterior (towards memory, outside scheduler) + */ +case class L2CacheParams( + ways: Int = 4, + sets: Int = 256, + writeBytes: Int = 8, + portFactor: Int = 2, + memCycles: Int = 10, + bufInnerInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, + bufInnerExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.flowAD, + bufOuterInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.full, + bufOuterExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.none) /** * Parameters for a BBTile. @@ -14,6 +39,9 @@ import framework.top.GlobalConfig * A BBTile contains one Rocket core and N buckyball slots. * Each slot can be enabled/disabled independently, with independent GlobalConfig. * Internal modules use @instantiable + config style; diplomacy is only used for TileLink ports. + * + * @param l2cache Optional per-tile private L2 cache. When None, tile connects directly to system bus. + * When Some, tile traffic routes through private L2 before reaching system bus. */ case class BBTileParams( nCores: Int = 1, @@ -24,6 +52,7 @@ case class BBTileParams( btb: Option[BTBParams] = Some(BTBParams()), buckyballConfig: GlobalConfig = GlobalConfig(), buckyballPerCore: Seq[Option[GlobalConfig]] = Nil, + l2cache: Option[L2CacheParams] = None, tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, diff --git a/arch/src/main/scala/framework/core/bbtile/Configs.scala b/arch/src/main/scala/framework/core/bbtile/Configs.scala index 62ae1c93..7504d196 100644 --- a/arch/src/main/scala/framework/core/bbtile/Configs.scala +++ b/arch/src/main/scala/framework/core/bbtile/Configs.scala @@ -31,7 +31,8 @@ class WithBBTile( buckyballConfig: GlobalConfig = GlobalConfig(), crossing: Option[RocketCrossingParams] = None, nCoresPerTile: Int = 1, - buckyballPerCore: Option[Seq[Option[GlobalConfig]]] = None) + buckyballPerCore: Option[Seq[Option[GlobalConfig]]] = None, + l2cache: Option[L2CacheParams] = None) extends Config((site, here, up) => { case TilesLocated(`location`) => val prev = up(TilesLocated(`location`), site) @@ -49,6 +50,7 @@ class WithBBTile( withBuckyball = withBuckyball, buckyballConfig = buckyballConfig, buckyballPerCore = resolvedBuckyballPerCore, + l2cache = l2cache, core = RocketCoreParams( mulDiv = Some(MulDivParams( mulUnroll = 8, @@ -88,7 +90,8 @@ class WithNBBTiles( buckyballConfig: GlobalConfig = GlobalConfig(), crossing: Option[RocketCrossingParams] = None, nCoresPerTile: Int = 1, - buckyballPerCore: Option[Seq[Option[GlobalConfig]]] = None) + buckyballPerCore: Option[Seq[Option[GlobalConfig]]] = None, + l2cache: Option[L2CacheParams] = None) extends Config((site, here, up) => { case TilesLocated(`location`) => val prev = up(TilesLocated(`location`), site) @@ -106,6 +109,7 @@ class WithNBBTiles( withBuckyball = withBuckyball, buckyballConfig = buckyballConfig, buckyballPerCore = resolvedBuckyballPerCore, + l2cache = l2cache, core = RocketCoreParams( mulDiv = Some(MulDivParams( mulUnroll = 8, diff --git a/arch/src/main/scala/sims/p2e/TargetConfigs.scala b/arch/src/main/scala/sims/p2e/TargetConfigs.scala index 25b56048..be36a95a 100644 --- a/arch/src/main/scala/sims/p2e/TargetConfigs.scala +++ b/arch/src/main/scala/sims/p2e/TargetConfigs.scala @@ -7,6 +7,7 @@ import org.chipsalliance.cde.config.Config import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.subsystem.{InSubsystem, WithCustomMMIOPort, WithCustomMemPort} import sims.p2e.scu.WithP2ESCU +import chipyard.config.WithNoDebug class WithP2EBootROM extends Config((site, here, up) => { @@ -30,6 +31,7 @@ class P2EBaseConfig extends Config( new WithP2EHarness ++ new WithP2ESCU ++ + new WithNoDebug ++ // Disable Debug module for P2E new WithCustomMMIOPort( base_addr = BigInt("60040000", 16), base_size = BigInt("1ffc0000", 16), diff --git a/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala b/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala index 4463f00b..0b857818 100644 --- a/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala +++ b/arch/src/main/scala/sims/p2e/scu/P2ESCU.scala @@ -38,8 +38,8 @@ class P2ESCUWriteDPI(hartId: Int) extends BlackBox with HasBlackBoxInline { setInline( s"P2ESCUWriteDPI_$hartId.v", s""" - |import "DPI-C" context function void p2e_uart_write(input int hart_id, input byte ch); - |import "DPI-C" context function void p2e_sim_exit(input int hart_id, input int code); + |import "DPI-C" context function void p2e_uart_write(input bit [31:0] hart_id, input bit [7:0] ch); + |import "DPI-C" context function void p2e_sim_exit(input bit [31:0] hart_id, input bit [31:0] code); | |module P2ESCUWriteDPI_$hartId( | input clock, diff --git a/bebop b/bebop index f03720d5..710b0dfb 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit f03720d5d5767aeb9fab77f123ed63f4e6772dbd +Subproject commit 710b0dfbb413cad65820ee76e789e43d5b812cf8 From 020d47511c72adfdedeb809732730b76b36e18db Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Fri, 1 May 2026 15:05:38 +0800 Subject: [PATCH 233/238] [arch] feat: add unused output wire for DDR4 controller and remove debug ports in P2ETop --- arch/src/main/scala/sims/p2e/P2ETop.scala | 20 +++++++++++--------- bebop | 2 +- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/src/main/scala/sims/p2e/P2ETop.scala b/arch/src/main/scala/sims/p2e/P2ETop.scala index 6ff164d2..96bee5b6 100644 --- a/arch/src/main/scala/sims/p2e/P2ETop.scala +++ b/arch/src/main/scala/sims/p2e/P2ETop.scala @@ -149,6 +149,7 @@ class P2ETopBlackBox extends BlackBox with HasBlackBoxInline { | localparam MMIO_ID_BITS = 4; | | wire c0_init_calib_complete; + | wire init_calib_complete_unused; // Unused output from DDR4 controller | wire soc_reset = !sys_rstn || !c0_init_calib_complete; | assign init_calib_complete = c0_init_calib_complete; | @@ -215,14 +216,15 @@ class P2ETopBlackBox extends BlackBox with HasBlackBoxInline { | DigitalTop soc ( | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (user_clk), | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset (soc_reset), - | .resetctrl_hartIsInReset_0 (1'b0), - | .debug_clock (user_clk), - | .debug_reset (soc_reset), - | .debug_systemjtag_reset (soc_reset), - | .debug_systemjtag_jtag_TCK (1'b0), - | .debug_systemjtag_jtag_TMS (1'b1), - | .debug_systemjtag_jtag_TDI (1'b1), - | .debug_dmactiveAck (1'b0), + | // Debug ports removed - WithNoDebug config doesn't generate these ports + | // .resetctrl_hartIsInReset_0 (1'b0), + | // .debug_clock (user_clk), + | // .debug_reset (soc_reset), + | // .debug_systemjtag_reset (soc_reset), + | // .debug_systemjtag_jtag_TCK (1'b0), + | // .debug_systemjtag_jtag_TMS (1'b1), + | // .debug_systemjtag_jtag_TDI (1'b1), + | // .debug_dmactiveAck (1'b0), | .mem_axi4_0_aw_ready (mem_awready), | .mem_axi4_0_aw_valid (mem_awvalid), | .mem_axi4_0_aw_bits_id (mem_awid), @@ -352,7 +354,7 @@ class P2ETopBlackBox extends BlackBox with HasBlackBoxInline { | .init_start (1'b1), | .init_cfg (1'b0), | .init_busy (), - | .init_calib_complete (), + | .init_calib_complete (init_calib_complete_unused), | .c0_init_calib_complete (c0_init_calib_complete), | .axi_clk (user_clk), | .s0_ddr4_s_axi_awid (mem_awid), diff --git a/bebop b/bebop index 710b0dfb..5e323098 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 710b0dfbb413cad65820ee76e789e43d5b812cf8 +Subproject commit 5e32309823c4307a643090656261074de1f2c0f3 From 99442896bf4795db817e3e9302c4e89d9e8f4a07 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Sat, 2 May 2026 22:46:33 +0800 Subject: [PATCH 234/238] [arch] refactor: comment out DDR4 inout port connections in P2ETop --- arch/src/main/scala/sims/p2e/P2ETop.scala | 10 ++++++---- bebop | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/src/main/scala/sims/p2e/P2ETop.scala b/arch/src/main/scala/sims/p2e/P2ETop.scala index 96bee5b6..ee91befd 100644 --- a/arch/src/main/scala/sims/p2e/P2ETop.scala +++ b/arch/src/main/scala/sims/p2e/P2ETop.scala @@ -456,10 +456,12 @@ class P2ETop extends RawModule { io.c0_ddr4_ck_t := top.io.c0_ddr4_ck_t io.c0_ddr4_ck_c := top.io.c0_ddr4_ck_c io.c0_ddr4_reset_n := top.io.c0_ddr4_reset_n - attach(io.c0_ddr4_dm_dbi_n, top.io.c0_ddr4_dm_dbi_n) - attach(io.c0_ddr4_dq, top.io.c0_ddr4_dq) - attach(io.c0_ddr4_dqs_c, top.io.c0_ddr4_dqs_c) - attach(io.c0_ddr4_dqs_t, top.io.c0_ddr4_dqs_t) + // DDR4 inout ports are managed by netlist macro (xepic_ddr4_dc1) + // Do not connect them to avoid VCOM terminal register requirement + // attach(io.c0_ddr4_dm_dbi_n, top.io.c0_ddr4_dm_dbi_n) + // attach(io.c0_ddr4_dq, top.io.c0_ddr4_dq) + // attach(io.c0_ddr4_dqs_c, top.io.c0_ddr4_dqs_c) + // attach(io.c0_ddr4_dqs_t, top.io.c0_ddr4_dqs_t) io.c0_ddr4_ui_clk := top.io.c0_ddr4_ui_clk io.init_calib_complete := top.io.init_calib_complete io.ddr4_en_vtt := top.io.ddr4_en_vtt diff --git a/bebop b/bebop index 5e323098..2bd2c47d 160000 --- a/bebop +++ b/bebop @@ -1 +1 @@ -Subproject commit 5e32309823c4307a643090656261074de1f2c0f3 +Subproject commit 2bd2c47d3ecbd378c6a02fb2adfc6f5387ae4d14 From 645c4430da63255c939df19b810f35f5f1ced145 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Thu, 7 May 2026 15:48:02 +0800 Subject: [PATCH 235/238] [compiler] fix: commit missing cmake files --- .gitignore | 1 - compiler/src/CMakeLists.txt | 29 +++++++++++++++++++ compiler/src/Conversion/CMakeLists.txt | 4 +++ .../Conversion/LowerBuckyball/CMakeLists.txt | 9 ++++++ .../LowerTileToBuckyball/CMakeLists.txt | 7 +++++ compiler/src/Dialect/Buckyball/CMakeLists.txt | 12 ++++++++ .../src/Dialect/Buckyball/IR/CMakeLists.txt | 7 +++++ .../Buckyball/Transforms/CMakeLists.txt | 9 ++++++ compiler/src/Dialect/CMakeLists.txt | 5 ++++ compiler/src/Target/CMakeLists.txt | 3 ++ compiler/src/Target/LLVMIR/CMakeLists.txt | 3 ++ .../LLVMIR/Dialect/Buckyball/CMakeLists.txt | 15 ++++++++++ .../src/Target/LLVMIR/Dialect/CMakeLists.txt | 3 ++ 13 files changed, 106 insertions(+), 1 deletion(-) create mode 100644 compiler/src/CMakeLists.txt create mode 100644 compiler/src/Conversion/CMakeLists.txt create mode 100644 compiler/src/Conversion/LowerBuckyball/CMakeLists.txt create mode 100644 compiler/src/Conversion/LowerTileToBuckyball/CMakeLists.txt create mode 100644 compiler/src/Dialect/Buckyball/CMakeLists.txt create mode 100644 compiler/src/Dialect/Buckyball/IR/CMakeLists.txt create mode 100644 compiler/src/Dialect/Buckyball/Transforms/CMakeLists.txt create mode 100644 compiler/src/Dialect/CMakeLists.txt create mode 100644 compiler/src/Target/CMakeLists.txt create mode 100644 compiler/src/Target/LLVMIR/CMakeLists.txt create mode 100644 compiler/src/Target/LLVMIR/Dialect/Buckyball/CMakeLists.txt create mode 100644 compiler/src/Target/LLVMIR/Dialect/CMakeLists.txt diff --git a/.gitignore b/.gitignore index c41dc462..72d02ccb 100644 --- a/.gitignore +++ b/.gitignore @@ -19,7 +19,6 @@ index.html *.fst *.log *.dot -*.txt # Vivado / Webtalk session files (root-level) /vivado*.jou diff --git a/compiler/src/CMakeLists.txt b/compiler/src/CMakeLists.txt new file mode 100644 index 00000000..1192123c --- /dev/null +++ b/compiler/src/CMakeLists.txt @@ -0,0 +1,29 @@ +# Buckyball External Dialects +# This directory contains Buckyball-specific MLIR dialects maintained +# separately from buddy-mlir and integrated at build time. + +if(NOT DEFINED MLIR_MAIN_SRC_DIR) + message(FATAL_ERROR "MLIR_MAIN_SRC_DIR must be defined. Build as part of buddy-mlir.") +endif() + +message(STATUS "Building Buckyball External Dialects") +message(STATUS " Source: ${CMAKE_CURRENT_SOURCE_DIR}") +message(STATUS " Binary: ${CMAKE_CURRENT_BINARY_DIR}") + +# Include directories for external dialect headers +# This allows #include "Dialect/Buckyball/BuckyballDialect.h" to work +include_directories(${CMAKE_CURRENT_SOURCE_DIR}) +include_directories(${CMAKE_CURRENT_BINARY_DIR}) + +# Also add Dialect subdirectory to include path for #include "Buckyball/BuckyballDialect.h" +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/Dialect) +include_directories(${CMAKE_CURRENT_BINARY_DIR}/Dialect) + +# CRITICAL: Add the generated files directory to include path +# This allows the generated .h.inc files to be found +include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR}/Dialect/Buckyball) + +# Add subdirectories +add_subdirectory(Dialect) +add_subdirectory(Conversion) +add_subdirectory(Target) diff --git a/compiler/src/Conversion/CMakeLists.txt b/compiler/src/Conversion/CMakeLists.txt new file mode 100644 index 00000000..5dd235cf --- /dev/null +++ b/compiler/src/Conversion/CMakeLists.txt @@ -0,0 +1,4 @@ +# Buckyball Conversion Passes + +add_subdirectory(LowerBuckyball) +add_subdirectory(LowerTileToBuckyball) diff --git a/compiler/src/Conversion/LowerBuckyball/CMakeLists.txt b/compiler/src/Conversion/LowerBuckyball/CMakeLists.txt new file mode 100644 index 00000000..fc8ca184 --- /dev/null +++ b/compiler/src/Conversion/LowerBuckyball/CMakeLists.txt @@ -0,0 +1,9 @@ +add_mlir_library(LowerBuckyballPass + AssignBuckyballBanksPass.cpp + LowerBuckyballToBankSSAPass.cpp + ReportBankUsagePass.cpp + LowerBuckyballPass.cpp + + LINK_LIBS PUBLIC + BuddyBuckyballTransforms + ) diff --git a/compiler/src/Conversion/LowerTileToBuckyball/CMakeLists.txt b/compiler/src/Conversion/LowerTileToBuckyball/CMakeLists.txt new file mode 100644 index 00000000..707e83b6 --- /dev/null +++ b/compiler/src/Conversion/LowerTileToBuckyball/CMakeLists.txt @@ -0,0 +1,7 @@ +add_mlir_library(LowerTileToBuckyballPass + LowerTileToBuckyball.cpp + + LINK_LIBS PUBLIC + BuddyTile + BuddyBuckyball + ) diff --git a/compiler/src/Dialect/Buckyball/CMakeLists.txt b/compiler/src/Dialect/Buckyball/CMakeLists.txt new file mode 100644 index 00000000..f6c80b22 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/CMakeLists.txt @@ -0,0 +1,12 @@ +# Generate dialect and ops from TableGen +add_mlir_dialect(Buckyball buckyball) +add_mlir_doc(Buckyball Buckyball Dialects/ -gen-dialect-doc) + +# Generate LLVM IR conversions +set(LLVM_TARGET_DEFINITIONS Buckyball.td) +mlir_tablegen(BuckyballConversions.inc -gen-llvmir-conversions) +add_public_tablegen_target(BuddyBuckyballConversionsIncGen) + +# Add subdirectories +add_subdirectory(IR) +add_subdirectory(Transforms) diff --git a/compiler/src/Dialect/Buckyball/IR/CMakeLists.txt b/compiler/src/Dialect/Buckyball/IR/CMakeLists.txt new file mode 100644 index 00000000..696f8bf9 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/IR/CMakeLists.txt @@ -0,0 +1,7 @@ +add_mlir_dialect_library(BuddyBuckyball + BuckyballDialect.cpp + + LINK_LIBS PUBLIC + MLIRIR + MLIRLLVMDialect +) diff --git a/compiler/src/Dialect/Buckyball/Transforms/CMakeLists.txt b/compiler/src/Dialect/Buckyball/Transforms/CMakeLists.txt new file mode 100644 index 00000000..fcf24e11 --- /dev/null +++ b/compiler/src/Dialect/Buckyball/Transforms/CMakeLists.txt @@ -0,0 +1,9 @@ +add_mlir_dialect_library(BuddyBuckyballTransforms + LegalizeForLLVMExport.cpp + + LINK_LIBS PUBLIC + BuddyBuckyball + MLIRIR + MLIRLLVMCommonConversion + MLIRLLVMDialect + ) diff --git a/compiler/src/Dialect/CMakeLists.txt b/compiler/src/Dialect/CMakeLists.txt new file mode 100644 index 00000000..33d2424f --- /dev/null +++ b/compiler/src/Dialect/CMakeLists.txt @@ -0,0 +1,5 @@ +# Buckyball Dialects + +add_subdirectory(Buckyball) +# add_subdirectory(vecball) +# add_subdirectory(matrixball) diff --git a/compiler/src/Target/CMakeLists.txt b/compiler/src/Target/CMakeLists.txt new file mode 100644 index 00000000..cf3f2b4c --- /dev/null +++ b/compiler/src/Target/CMakeLists.txt @@ -0,0 +1,3 @@ +# Buckyball Target Support + +add_subdirectory(LLVMIR) diff --git a/compiler/src/Target/LLVMIR/CMakeLists.txt b/compiler/src/Target/LLVMIR/CMakeLists.txt new file mode 100644 index 00000000..486c6839 --- /dev/null +++ b/compiler/src/Target/LLVMIR/CMakeLists.txt @@ -0,0 +1,3 @@ +# Buckyball LLVM IR Translation + +add_subdirectory(Dialect) diff --git a/compiler/src/Target/LLVMIR/Dialect/Buckyball/CMakeLists.txt b/compiler/src/Target/LLVMIR/Dialect/Buckyball/CMakeLists.txt new file mode 100644 index 00000000..40e996f6 --- /dev/null +++ b/compiler/src/Target/LLVMIR/Dialect/Buckyball/CMakeLists.txt @@ -0,0 +1,15 @@ +add_mlir_translation_library(BuddyBuckyballToLLVMIRTranslation + BuckyballToLLVMIRTranslation.cpp + + DEPENDS + BuddyBuckyballConversionsIncGen + buddy_intrinsics_gen + + LINK_COMPONENTS + Core + + LINK_LIBS PUBLIC + MLIRIR + MLIRSupport + BuddyBuckyball + ) diff --git a/compiler/src/Target/LLVMIR/Dialect/CMakeLists.txt b/compiler/src/Target/LLVMIR/Dialect/CMakeLists.txt new file mode 100644 index 00000000..890a6514 --- /dev/null +++ b/compiler/src/Target/LLVMIR/Dialect/CMakeLists.txt @@ -0,0 +1,3 @@ +# Buckyball Dialect LLVM IR Translation + +add_subdirectory(Buckyball) From febed8e994134d6c21b39f76147b5e7777b2681a Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Mon, 11 May 2026 21:42:55 +0800 Subject: [PATCH 236/238] [nix] refactor: remove pegasus submodule --- .gitmodules | 3 --- scripts/nix/build-all.sh | 13 ++++++++----- thirdparty/pegasus | 1 - 3 files changed, 8 insertions(+), 9 deletions(-) delete mode 160000 thirdparty/pegasus diff --git a/.gitmodules b/.gitmodules index 5126cf53..c518bd56 100644 --- a/.gitmodules +++ b/.gitmodules @@ -17,9 +17,6 @@ path = bebop url = https://github.com/DangoSys/bebop branch = next -[submodule "thirdparty/pegasus"] - path = thirdparty/pegasus - url = https://github.com/DangoSys/pegasus.git [submodule "bb-tests/workloads/lib/kernel"] path = bb-tests/workloads/lib/kernel url = https://github.com/DangoSys/bbkernel.git diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index c4851e3b..8b1aba0e 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -83,14 +83,17 @@ git submodule update --init --progress \ bebop \ compiler/thirdparty/buddy-mlir \ docs \ - thirdparty/pegasus \ thirdparty/waveform-mcp -# I dont know why below is need for buckyball submodules, but it is -git -C ${BBDIR} submodule update --init --checkout --force thirdparty/pegasus -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress fpga/fpga-shells generators/* tools/* sims/firesim # I dont know why below is need for chipyard submodules, but it is -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde tools/rocket-dsp-utils generators/rocc-acc-utils generators/bar-fetchers +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress fpga/fpga-shells +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress generators/* +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress tools/* +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress sims/firesim +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/rocket-dsp-utils +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force generators/rocc-acc-utils +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force generators/bar-fetchers ########################################## begin_step "0-2" "Nix environment setup" diff --git a/thirdparty/pegasus b/thirdparty/pegasus deleted file mode 160000 index 053536d3..00000000 --- a/thirdparty/pegasus +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 053536d3fbc6ff6b9d7fbdedcaaa66944cb8e236 From 6ca6c27b2bf0a021229f7abfda9117b8fa375cfd Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Tue, 12 May 2026 02:49:51 +0800 Subject: [PATCH 237/238] [arch/sims] del: remove unused pegasus --- .claude/CLAUDE.md | 2 - .github/workflows/test.yml | 2 +- .../scala/sims/pegasus/PegasusHarness.scala | 122 ------- .../sims/pegasus/PegasusHarnessBinders.scala | 97 ------ .../main/scala/sims/pegasus/PegasusTop.scala | 303 ------------------ .../scala/sims/pegasus/TargetConfigs.scala | 32 -- bbdev | 2 +- flake.nix | 2 +- scripts/claude/mcp_server.py | 57 ---- scripts/nix/build-all.sh | 15 +- scripts/nix/build-env-clibs.nix | 2 +- scripts/nix/build-env-python.nix | 35 ++ sourceme.sh | 3 + 13 files changed, 50 insertions(+), 624 deletions(-) delete mode 100644 arch/src/main/scala/sims/pegasus/PegasusHarness.scala delete mode 100644 arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala delete mode 100644 arch/src/main/scala/sims/pegasus/PegasusTop.scala delete mode 100644 arch/src/main/scala/sims/pegasus/TargetConfigs.scala diff --git a/.claude/CLAUDE.md b/.claude/CLAUDE.md index 96bac76d..33172aa6 100644 --- a/.claude/CLAUDE.md +++ b/.claude/CLAUDE.md @@ -77,8 +77,6 @@ The project configures the `buckyball-dev` MCP server with the following tools. - `bbdev_verilator_sim(binary, batch?, coverage?)` — run simulation (requires prior build) - `bbdev_sardine_run(workload?, coverage?)` — run batch tests - `bbdev_yosys_synth(top?, config?)` — Yosys synthesis + OpenSTA timing analysis -- `bbdev_pegasus_flashbitstream(bitstream?, serial?, bus_id?)` — flash bitstream onto AU280 via Vivado + PCIe remove/rescan -- `bbdev_pegasus_runworkload(workload?, board?, timeout?, uart?, control?, h2c?)` — load kernel+rootfs into HBM2 and run on AU280; UART log at `arch/log//pegasus_uart.log` Default config value: `sims.verilator.BuckyballToyVerilatorConfig` Simulation binary naming format: `ctest__test_singlecore-baremetal` diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 988d1e0d..9ec6db99 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -25,7 +25,7 @@ jobs: git clean -fd git checkout ${{ github.head_ref }} git pull - git submodule update bbdev bebop compiler thirdparty/pegasus + git submodule update bbdev bebop compiler - name: Nix build shell: zsh {0} diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala b/arch/src/main/scala/sims/pegasus/PegasusHarness.scala deleted file mode 100644 index 46ba7253..00000000 --- a/arch/src/main/scala/sims/pegasus/PegasusHarness.scala +++ /dev/null @@ -1,122 +0,0 @@ -package sims.pegasus - -import chisel3._ - -import org.chipsalliance.cde.config.Parameters - -import chipyard.harness.HasHarnessInstantiators -import chipyard.iobinders.AXI4MemPort - -import pegasus.PegasusShell - -class PegasusHarness(implicit val p: Parameters) extends Module with HasHarnessInstantiators { - - val io = IO(new Bundle { - val pcie_refclk_p = Input(Bool()) - val pcie_refclk_n = Input(Bool()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) - }) - - val pegasusShell = Module(new PegasusShell) - pegasusShell.io.pcie_refclk_p := io.pcie_refclk_p - pegasusShell.io.pcie_refclk_n := io.pcie_refclk_n - pegasusShell.io.pcie_sys_rst_n := io.pcie_sys_rst_n - io.pcie_exp_txp := pegasusShell.io.pcie_exp_txp - io.pcie_exp_txn := pegasusShell.io.pcie_exp_txn - pegasusShell.io.pcie_exp_rxp := io.pcie_exp_rxp - pegasusShell.io.pcie_exp_rxn := io.pcie_exp_rxn - pegasusShell.io.c0_sys_clk_p := false.B - pegasusShell.io.c0_sys_clk_n := false.B - - pegasusShell.io.uart_tx := true.B - - // Default tie-offs for chip_mem (overridden by connectChipMem) - pegasusShell.io.chip_mem_awid := 0.U - pegasusShell.io.chip_mem_awaddr := 0.U - pegasusShell.io.chip_mem_awlen := 0.U - pegasusShell.io.chip_mem_awsize := 0.U - pegasusShell.io.chip_mem_awburst := 0.U - pegasusShell.io.chip_mem_awvalid := false.B - pegasusShell.io.chip_mem_wdata := 0.U - pegasusShell.io.chip_mem_wstrb := 0.U - pegasusShell.io.chip_mem_wlast := false.B - pegasusShell.io.chip_mem_wvalid := false.B - pegasusShell.io.chip_mem_bready := false.B - pegasusShell.io.chip_mem_arid := 0.U - pegasusShell.io.chip_mem_araddr := 0.U - pegasusShell.io.chip_mem_arlen := 0.U - pegasusShell.io.chip_mem_arsize := 0.U - pegasusShell.io.chip_mem_arburst := 0.U - pegasusShell.io.chip_mem_arvalid := false.B - pegasusShell.io.chip_mem_rready := false.B - - // Default tie-offs for mmio (overridden by connectChipMMIO) - pegasusShell.io.mmio_awid := 0.U - pegasusShell.io.mmio_awaddr := 0.U - pegasusShell.io.mmio_awlen := 0.U - pegasusShell.io.mmio_awsize := 0.U - pegasusShell.io.mmio_awburst := 0.U - pegasusShell.io.mmio_awvalid := false.B - pegasusShell.io.mmio_wdata := 0.U - pegasusShell.io.mmio_wstrb := 0.U - pegasusShell.io.mmio_wlast := false.B - pegasusShell.io.mmio_wvalid := false.B - pegasusShell.io.mmio_bready := false.B - pegasusShell.io.mmio_arid := 0.U - pegasusShell.io.mmio_araddr := 0.U - pegasusShell.io.mmio_arlen := 0.U - pegasusShell.io.mmio_arsize := 0.U - pegasusShell.io.mmio_arburst := 0.U - pegasusShell.io.mmio_arvalid := false.B - pegasusShell.io.mmio_rready := false.B - - def referenceClockFreqMHz: Double = 150.0 - def referenceClock: Clock = pegasusShell.io.dut_clk - def referenceReset: Reset = pegasusShell.io.dut_reset.asAsyncReset - - val success = WireInit(false.B) - - val lazyDuts = instantiateChipTops() - - def connectChipMem(port: AXI4MemPort): Unit = { - val axi = port.io.bits - pegasusShell.io.chip_mem_awid := axi.aw.bits.id.asTypeOf(UInt(4.W)) - pegasusShell.io.chip_mem_awaddr := axi.aw.bits.addr.asTypeOf(UInt(32.W)) - pegasusShell.io.chip_mem_awlen := axi.aw.bits.len - pegasusShell.io.chip_mem_awsize := axi.aw.bits.size - pegasusShell.io.chip_mem_awburst := axi.aw.bits.burst - pegasusShell.io.chip_mem_awvalid := axi.aw.valid - axi.aw.ready := pegasusShell.io.chip_mem_awready - - pegasusShell.io.chip_mem_wdata := axi.w.bits.data.asTypeOf(UInt(64.W)) - pegasusShell.io.chip_mem_wstrb := axi.w.bits.strb.asTypeOf(UInt(8.W)) - pegasusShell.io.chip_mem_wlast := axi.w.bits.last - pegasusShell.io.chip_mem_wvalid := axi.w.valid - axi.w.ready := pegasusShell.io.chip_mem_wready - - axi.b.bits.id := pegasusShell.io.chip_mem_bid.asTypeOf(axi.b.bits.id) - axi.b.bits.resp := pegasusShell.io.chip_mem_bresp - axi.b.valid := pegasusShell.io.chip_mem_bvalid - pegasusShell.io.chip_mem_bready := axi.b.ready - - pegasusShell.io.chip_mem_arid := axi.ar.bits.id.asTypeOf(UInt(4.W)) - pegasusShell.io.chip_mem_araddr := axi.ar.bits.addr.asTypeOf(UInt(32.W)) - pegasusShell.io.chip_mem_arlen := axi.ar.bits.len - pegasusShell.io.chip_mem_arsize := axi.ar.bits.size - pegasusShell.io.chip_mem_arburst := axi.ar.bits.burst - pegasusShell.io.chip_mem_arvalid := axi.ar.valid - axi.ar.ready := pegasusShell.io.chip_mem_arready - - axi.r.bits.id := pegasusShell.io.chip_mem_rid.asTypeOf(axi.r.bits.id) - axi.r.bits.data := pegasusShell.io.chip_mem_rdata.asTypeOf(axi.r.bits.data) - axi.r.bits.resp := pegasusShell.io.chip_mem_rresp - axi.r.bits.last := pegasusShell.io.chip_mem_rlast - axi.r.valid := pegasusShell.io.chip_mem_rvalid - pegasusShell.io.chip_mem_rready := axi.r.ready - } - -} diff --git a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala b/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala deleted file mode 100644 index 014602a3..00000000 --- a/arch/src/main/scala/sims/pegasus/PegasusHarnessBinders.scala +++ /dev/null @@ -1,97 +0,0 @@ -package sims.pegasus - -import chisel3._ - -import org.chipsalliance.cde.config.Config - -import chipyard.harness.{HarnessBinder, HasHarnessInstantiators} -import chipyard.iobinders.{AXI4MMIOPort, AXI4MemPort, DMIPort, JTAGPort, UARTPort} - -class WithPegasusAXIMem - extends HarnessBinder({ - case (th: PegasusHarness, port: AXI4MemPort, chipId: Int) => - th.connectChipMem(port) - }) - -class WithPegasusUART - extends HarnessBinder({ - case (th: PegasusHarness, port: UARTPort, chipId: Int) => - th.pegasusShell.io.uart_tx := port.io.txd - port.io.rxd := true.B - }) - -class WithPegasusAXIMMIO - extends HarnessBinder({ - case (th: PegasusHarness, port: AXI4MMIOPort, chipId: Int) => - val axi = port.io.bits - val shell = th.pegasusShell.io - // Connect mmio_axi4 to shell's MMIO SCU - shell.mmio_awid := axi.aw.bits.id.asTypeOf(UInt(4.W)) - shell.mmio_awaddr := axi.aw.bits.addr.asTypeOf(UInt(32.W)) - shell.mmio_awlen := axi.aw.bits.len - shell.mmio_awsize := axi.aw.bits.size - shell.mmio_awburst := axi.aw.bits.burst - shell.mmio_awvalid := axi.aw.valid - axi.aw.ready := shell.mmio_awready - - shell.mmio_wdata := axi.w.bits.data.asTypeOf(UInt(64.W)) - shell.mmio_wstrb := axi.w.bits.strb.asTypeOf(UInt(8.W)) - shell.mmio_wlast := axi.w.bits.last - shell.mmio_wvalid := axi.w.valid - axi.w.ready := shell.mmio_wready - - axi.b.bits.id := shell.mmio_bid.asTypeOf(axi.b.bits.id) - axi.b.bits.resp := shell.mmio_bresp - axi.b.valid := shell.mmio_bvalid - shell.mmio_bready := axi.b.ready - - shell.mmio_arid := axi.ar.bits.id.asTypeOf(UInt(4.W)) - shell.mmio_araddr := axi.ar.bits.addr.asTypeOf(UInt(32.W)) - shell.mmio_arlen := axi.ar.bits.len - shell.mmio_arsize := axi.ar.bits.size - shell.mmio_arburst := axi.ar.bits.burst - shell.mmio_arvalid := axi.ar.valid - axi.ar.ready := shell.mmio_arready - - axi.r.bits.id := shell.mmio_rid.asTypeOf(axi.r.bits.id) - axi.r.bits.data := shell.mmio_rdata.asTypeOf(axi.r.bits.data) - axi.r.bits.resp := shell.mmio_rresp - axi.r.bits.last := shell.mmio_rlast - axi.r.valid := shell.mmio_rvalid - shell.mmio_rready := axi.r.ready - }) - -class WithPegasusTiedOffJTAG - extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => - port.io.TCK := true.B.asClock - port.io.TMS := true.B - port.io.TDI := true.B - }) - -class WithPegasusTiedOffDMI - extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => - port.io.dmi.req.valid := false.B - port.io.dmi.req.bits := DontCare - port.io.dmi.resp.ready := true.B - port.io.dmiClock := false.B.asClock - port.io.dmiReset := true.B - }) - -class WithPegasusHarness - extends Config( - new WithPegasusAXIMem ++ - new WithPegasusAXIMMIO ++ - new WithPegasusUART ++ - new WithPegasusTiedOffJTAG ++ - new WithPegasusTiedOffDMI ++ - new chipyard.harness.WithSerialTLTiedOff ++ - new chipyard.harness.WithTieOffInterrupts ++ - new chipyard.harness.WithGPIOTiedOff ++ - new chipyard.harness.WithClockFromHarness ++ - new chipyard.harness.WithResetFromHarness ++ - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ - new chipyard.iobinders.WithNMITiedOff - ) diff --git a/arch/src/main/scala/sims/pegasus/PegasusTop.scala b/arch/src/main/scala/sims/pegasus/PegasusTop.scala deleted file mode 100644 index 923ba9b7..00000000 --- a/arch/src/main/scala/sims/pegasus/PegasusTop.scala +++ /dev/null @@ -1,303 +0,0 @@ -package sims.pegasus - -import chisel3._ -import chisel3.util.HasBlackBoxInline - -import pegasus.PegasusShell - -class PegasusTop extends BlackBox with HasBlackBoxInline { - - val io = IO(new Bundle { - val pcie_refclk_p = Input(Bool()) - val pcie_refclk_n = Input(Bool()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) - val c0_sys_clk_p = Input(Bool()) - val c0_sys_clk_n = Input(Bool()) - val c0_ddr4_act_n = Output(Bool()) - val c0_ddr4_adr = Output(UInt(17.W)) - val c0_ddr4_ba = Output(UInt(2.W)) - val c0_ddr4_bg = Output(UInt(2.W)) - val c0_ddr4_cke = Output(UInt(1.W)) - val c0_ddr4_odt = Output(UInt(1.W)) - val c0_ddr4_cs_n = Output(UInt(1.W)) - val c0_ddr4_ck_t = Output(UInt(1.W)) - val c0_ddr4_ck_c = Output(UInt(1.W)) - val c0_ddr4_reset_n = Output(Bool()) - val c0_ddr4_parity = Output(Bool()) - val uart_txd = Output(Bool()) - }) - - setInline( - "PegasusTop.v", - """module PegasusTop( - | input pcie_refclk_p, - | input pcie_refclk_n, - | input pcie_sys_rst_n, - | output [15:0] pcie_exp_txp, - | output [15:0] pcie_exp_txn, - | input [15:0] pcie_exp_rxp, - | input [15:0] pcie_exp_rxn, - | input c0_sys_clk_p, - | input c0_sys_clk_n, - | output c0_ddr4_act_n, - | output [16:0] c0_ddr4_adr, - | output [1:0] c0_ddr4_ba, - | output [1:0] c0_ddr4_bg, - | output [0:0] c0_ddr4_cke, - | output [0:0] c0_ddr4_odt, - | output [0:0] c0_ddr4_cs_n, - | output [0:0] c0_ddr4_ck_t, - | output [0:0] c0_ddr4_ck_c, - | output c0_ddr4_reset_n, - | output c0_ddr4_parity, - | inout [71:0] c0_ddr4_dq, - | inout [17:0] c0_ddr4_dqs_c, - | inout [17:0] c0_ddr4_dqs_t, - | output uart_txd - |); - | - | wire soc_clk; - | wire soc_reset; - | wire cpu_hold_reset; - | - | // mem_axi4: DigitalTop → shell crossbar → DDR4 - | wire [3:0] mem_awid; wire [31:0] mem_awaddr; - | wire [7:0] mem_awlen; wire [2:0] mem_awsize; - | wire [1:0] mem_awburst; wire mem_awvalid, mem_awready; - | wire [63:0] mem_wdata; wire [7:0] mem_wstrb; - | wire mem_wlast, mem_wvalid, mem_wready; - | wire [3:0] mem_bid; wire [1:0] mem_bresp; - | wire mem_bvalid, mem_bready; - | wire [3:0] mem_arid; wire [31:0] mem_araddr; - | wire [7:0] mem_arlen; wire [2:0] mem_arsize; - | wire [1:0] mem_arburst; wire mem_arvalid, mem_arready; - | wire [3:0] mem_rid; wire [63:0] mem_rdata; - | wire [1:0] mem_rresp; wire mem_rlast, mem_rvalid, mem_rready; - | - | // mmio_axi4: DigitalTop → shell SCU - | wire [3:0] mmio_awid; wire [31:0] mmio_awaddr; - | wire [7:0] mmio_awlen; wire [2:0] mmio_awsize; - | wire [1:0] mmio_awburst; wire mmio_awvalid, mmio_awready; - | wire [63:0] mmio_wdata; wire [7:0] mmio_wstrb; - | wire mmio_wlast, mmio_wvalid, mmio_wready; - | wire [3:0] mmio_bid; wire [1:0] mmio_bresp; - | wire mmio_bvalid, mmio_bready; - | wire [3:0] mmio_arid; wire [31:0] mmio_araddr; - | wire [7:0] mmio_arlen; wire [2:0] mmio_arsize; - | wire [1:0] mmio_arburst; wire mmio_arvalid, mmio_arready; - | wire [3:0] mmio_rid; wire [63:0] mmio_rdata; - | wire [1:0] mmio_rresp; wire mmio_rlast, mmio_rvalid, mmio_rready; - | - | PegasusShell shell ( - | .pcie_refclk_p (pcie_refclk_p), - | .pcie_refclk_n (pcie_refclk_n), - | .pcie_sys_rst_n (pcie_sys_rst_n), - | .pcie_exp_txp (pcie_exp_txp), - | .pcie_exp_txn (pcie_exp_txn), - | .pcie_exp_rxp (pcie_exp_rxp), - | .pcie_exp_rxn (pcie_exp_rxn), - | .c0_sys_clk_p (c0_sys_clk_p), - | .c0_sys_clk_n (c0_sys_clk_n), - | .c0_ddr4_act_n (c0_ddr4_act_n), - | .c0_ddr4_adr (c0_ddr4_adr), - | .c0_ddr4_ba (c0_ddr4_ba), - | .c0_ddr4_bg (c0_ddr4_bg), - | .c0_ddr4_cke (c0_ddr4_cke), - | .c0_ddr4_odt (c0_ddr4_odt), - | .c0_ddr4_cs_n (c0_ddr4_cs_n), - | .c0_ddr4_ck_t (c0_ddr4_ck_t), - | .c0_ddr4_ck_c (c0_ddr4_ck_c), - | .c0_ddr4_reset_n (c0_ddr4_reset_n), - | .c0_ddr4_parity (c0_ddr4_parity), - | .c0_ddr4_dq (c0_ddr4_dq), - | .c0_ddr4_dqs_c (c0_ddr4_dqs_c), - | .c0_ddr4_dqs_t (c0_ddr4_dqs_t), - | .dut_clk (soc_clk), - | .dut_reset (soc_reset), - | .cpu_hold_reset (cpu_hold_reset), - | .uart_tx (uart_txd), - | // mem_axi4 → crossbar → DDR4 - | .chip_mem_awid (mem_awid), .chip_mem_awaddr (mem_awaddr), - | .chip_mem_awlen (mem_awlen), .chip_mem_awsize (mem_awsize), - | .chip_mem_awburst(mem_awburst), .chip_mem_awvalid(mem_awvalid), - | .chip_mem_awready(mem_awready), - | .chip_mem_wdata (mem_wdata), .chip_mem_wstrb (mem_wstrb), - | .chip_mem_wlast (mem_wlast), .chip_mem_wvalid (mem_wvalid), - | .chip_mem_wready (mem_wready), - | .chip_mem_bid (mem_bid), .chip_mem_bresp (mem_bresp), - | .chip_mem_bvalid (mem_bvalid), .chip_mem_bready (mem_bready), - | .chip_mem_arid (mem_arid), .chip_mem_araddr (mem_araddr), - | .chip_mem_arlen (mem_arlen), .chip_mem_arsize (mem_arsize), - | .chip_mem_arburst(mem_arburst), .chip_mem_arvalid(mem_arvalid), - | .chip_mem_arready(mem_arready), - | .chip_mem_rid (mem_rid), .chip_mem_rdata (mem_rdata), - | .chip_mem_rresp (mem_rresp), .chip_mem_rlast (mem_rlast), - | .chip_mem_rvalid (mem_rvalid), .chip_mem_rready (mem_rready), - | // mmio_axi4 → SCU - | .mmio_awid (mmio_awid), .mmio_awaddr (mmio_awaddr), - | .mmio_awlen (mmio_awlen), .mmio_awsize (mmio_awsize), - | .mmio_awburst (mmio_awburst), .mmio_awvalid (mmio_awvalid), - | .mmio_awready (mmio_awready), - | .mmio_wdata (mmio_wdata), .mmio_wstrb (mmio_wstrb), - | .mmio_wlast (mmio_wlast), .mmio_wvalid (mmio_wvalid), - | .mmio_wready (mmio_wready), - | .mmio_bid (mmio_bid), .mmio_bresp (mmio_bresp), - | .mmio_bvalid (mmio_bvalid), .mmio_bready (mmio_bready), - | .mmio_arid (mmio_arid), .mmio_araddr (mmio_araddr), - | .mmio_arlen (mmio_arlen), .mmio_arsize (mmio_arsize), - | .mmio_arburst (mmio_arburst), .mmio_arvalid (mmio_arvalid), - | .mmio_arready (mmio_arready), - | .mmio_rid (mmio_rid), .mmio_rdata (mmio_rdata), - | .mmio_rresp (mmio_rresp), .mmio_rlast (mmio_rlast), - | .mmio_rvalid (mmio_rvalid), .mmio_rready (mmio_rready) - | ); - | - | DigitalTop soc ( - | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (soc_clk), - | .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset (soc_reset), - | .resetctrl_hartIsInReset_0 (cpu_hold_reset), - | .debug_clock (soc_clk), - | .debug_reset (soc_reset), - | .debug_systemjtag_reset (soc_reset), - | .debug_systemjtag_jtag_TCK (1'b0), - | .debug_systemjtag_jtag_TMS (1'b1), - | .debug_systemjtag_jtag_TDI (1'b1), - | .debug_dmactiveAck (1'b0), - | .uart_0_txd (uart_txd), - | .uart_0_rxd (1'b1), - | // mem_axi4 → shell → DDR4 - | .mem_axi4_0_aw_ready (mem_awready), - | .mem_axi4_0_aw_valid (mem_awvalid), - | .mem_axi4_0_aw_bits_id (mem_awid), - | .mem_axi4_0_aw_bits_addr (mem_awaddr), - | .mem_axi4_0_aw_bits_len (mem_awlen), - | .mem_axi4_0_aw_bits_size (mem_awsize), - | .mem_axi4_0_aw_bits_burst (mem_awburst), - | .mem_axi4_0_w_ready (mem_wready), - | .mem_axi4_0_w_valid (mem_wvalid), - | .mem_axi4_0_w_bits_data (mem_wdata), - | .mem_axi4_0_w_bits_strb (mem_wstrb), - | .mem_axi4_0_w_bits_last (mem_wlast), - | .mem_axi4_0_b_valid (mem_bvalid), - | .mem_axi4_0_b_ready (mem_bready), - | .mem_axi4_0_b_bits_id (mem_bid), - | .mem_axi4_0_b_bits_resp (mem_bresp), - | .mem_axi4_0_ar_ready (mem_arready), - | .mem_axi4_0_ar_valid (mem_arvalid), - | .mem_axi4_0_ar_bits_id (mem_arid), - | .mem_axi4_0_ar_bits_addr (mem_araddr), - | .mem_axi4_0_ar_bits_len (mem_arlen), - | .mem_axi4_0_ar_bits_size (mem_arsize), - | .mem_axi4_0_ar_bits_burst (mem_arburst), - | .mem_axi4_0_r_valid (mem_rvalid), - | .mem_axi4_0_r_ready (mem_rready), - | .mem_axi4_0_r_bits_id (mem_rid), - | .mem_axi4_0_r_bits_data (mem_rdata), - | .mem_axi4_0_r_bits_resp (mem_rresp), - | .mem_axi4_0_r_bits_last (mem_rlast), - | // mmio_axi4 → shell → SCU - | .mmio_axi4_0_aw_ready (mmio_awready), - | .mmio_axi4_0_aw_valid (mmio_awvalid), - | .mmio_axi4_0_aw_bits_id (mmio_awid), - | .mmio_axi4_0_aw_bits_addr (mmio_awaddr), - | .mmio_axi4_0_aw_bits_len (mmio_awlen), - | .mmio_axi4_0_aw_bits_size (mmio_awsize), - | .mmio_axi4_0_aw_bits_burst (mmio_awburst), - | .mmio_axi4_0_w_ready (mmio_wready), - | .mmio_axi4_0_w_valid (mmio_wvalid), - | .mmio_axi4_0_w_bits_data (mmio_wdata), - | .mmio_axi4_0_w_bits_strb (mmio_wstrb), - | .mmio_axi4_0_w_bits_last (mmio_wlast), - | .mmio_axi4_0_b_valid (mmio_bvalid), - | .mmio_axi4_0_b_ready (mmio_bready), - | .mmio_axi4_0_b_bits_id (mmio_bid), - | .mmio_axi4_0_b_bits_resp (mmio_bresp), - | .mmio_axi4_0_ar_ready (mmio_arready), - | .mmio_axi4_0_ar_valid (mmio_arvalid), - | .mmio_axi4_0_ar_bits_id (mmio_arid), - | .mmio_axi4_0_ar_bits_addr (mmio_araddr), - | .mmio_axi4_0_ar_bits_len (mmio_arlen), - | .mmio_axi4_0_ar_bits_size (mmio_arsize), - | .mmio_axi4_0_ar_bits_burst (mmio_arburst), - | .mmio_axi4_0_r_valid (mmio_rvalid), - | .mmio_axi4_0_r_ready (mmio_rready), - | .mmio_axi4_0_r_bits_id (mmio_rid), - | .mmio_axi4_0_r_bits_data (mmio_rdata), - | .mmio_axi4_0_r_bits_resp (mmio_rresp), - | .mmio_axi4_0_r_bits_last (mmio_rlast), - | // No inbound DMA port (removed WithCustomSlavePort) - | .serial_tl_0_in_valid (1'b0), - | .serial_tl_0_in_bits_phit (32'h0), - | .serial_tl_0_out_ready (1'b0), - | .serial_tl_0_clock_in (1'b0), - | .custom_boot (1'b0) - | ); - | - |endmodule - |""".stripMargin - ) -} - -object ElaboratePegasusTop extends App { - import _root_.circt.stage.ChiselStage - - class PegasusTopWrapper extends RawModule { - - val io = IO(new Bundle { - val pcie_refclk_p = Input(Bool()) - val pcie_refclk_n = Input(Bool()) - val pcie_sys_rst_n = Input(Bool()) - val pcie_exp_txp = Output(UInt(16.W)) - val pcie_exp_txn = Output(UInt(16.W)) - val pcie_exp_rxp = Input(UInt(16.W)) - val pcie_exp_rxn = Input(UInt(16.W)) - val c0_sys_clk_p = Input(Bool()) - val c0_sys_clk_n = Input(Bool()) - val c0_ddr4_act_n = Output(Bool()) - val c0_ddr4_adr = Output(UInt(17.W)) - val c0_ddr4_ba = Output(UInt(2.W)) - val c0_ddr4_bg = Output(UInt(2.W)) - val c0_ddr4_cke = Output(UInt(1.W)) - val c0_ddr4_odt = Output(UInt(1.W)) - val c0_ddr4_cs_n = Output(UInt(1.W)) - val c0_ddr4_ck_t = Output(UInt(1.W)) - val c0_ddr4_ck_c = Output(UInt(1.W)) - val c0_ddr4_reset_n = Output(Bool()) - val c0_ddr4_parity = Output(Bool()) - val uart_txd = Output(Bool()) - }) - - val top = Module(new PegasusTop) - top.io.pcie_refclk_p := io.pcie_refclk_p - top.io.pcie_refclk_n := io.pcie_refclk_n - top.io.pcie_sys_rst_n := io.pcie_sys_rst_n - top.io.pcie_exp_rxp := io.pcie_exp_rxp - top.io.pcie_exp_rxn := io.pcie_exp_rxn - top.io.c0_sys_clk_p := io.c0_sys_clk_p - top.io.c0_sys_clk_n := io.c0_sys_clk_n - io.pcie_exp_txp := top.io.pcie_exp_txp - io.pcie_exp_txn := top.io.pcie_exp_txn - io.c0_ddr4_act_n := top.io.c0_ddr4_act_n - io.c0_ddr4_adr := top.io.c0_ddr4_adr - io.c0_ddr4_ba := top.io.c0_ddr4_ba - io.c0_ddr4_bg := top.io.c0_ddr4_bg - io.c0_ddr4_cke := top.io.c0_ddr4_cke - io.c0_ddr4_odt := top.io.c0_ddr4_odt - io.c0_ddr4_cs_n := top.io.c0_ddr4_cs_n - io.c0_ddr4_ck_t := top.io.c0_ddr4_ck_t - io.c0_ddr4_ck_c := top.io.c0_ddr4_ck_c - io.c0_ddr4_reset_n := top.io.c0_ddr4_reset_n - io.c0_ddr4_parity := top.io.c0_ddr4_parity - io.uart_txd := top.io.uart_txd - } - - ChiselStage.emitSystemVerilogFile( - new PegasusTopWrapper, - firtoolOpts = args, - args = Array.empty - ) -} diff --git a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala b/arch/src/main/scala/sims/pegasus/TargetConfigs.scala deleted file mode 100644 index 42b600e6..00000000 --- a/arch/src/main/scala/sims/pegasus/TargetConfigs.scala +++ /dev/null @@ -1,32 +0,0 @@ -package sims.pegasus - -import _root_.circt.stage.ChiselStage -import org.chipsalliance.cde.config.Config - -import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} -import freechips.rocketchip.subsystem.{InSubsystem, WithDefaultMMIOPort} - -class WithPegasusBootROM - extends Config((site, here, up) => { - case BootROMLocated(InSubsystem) => Some(BootROMParams( - contentFileName = "src/main/resources/bootrom/bootrom.rv64.img" - )) - }) - -class PegasusConfig - extends Config( - new WithPegasusHarness ++ - new WithDefaultMMIOPort ++ - new WithPegasusBootROM ++ - new examples.toy.BuckyballToyConfig - ) - -class PegasusBuckyballToyConfig extends PegasusConfig - -object ElaboratePegasus extends App { - ChiselStage.emitSystemVerilogFile( - new PegasusHarness()(new PegasusConfig().toInstance), - firtoolOpts = args, - args = Array.empty - ) -} diff --git a/bbdev b/bbdev index 8823f20d..ed09ede6 160000 --- a/bbdev +++ b/bbdev @@ -1 +1 @@ -Subproject commit 8823f20dd0940a029ef6db59ef70408aa9805998 +Subproject commit ed09ede6fbf3a8c95e0d0bae5712cbe47572ae4c diff --git a/flake.nix b/flake.nix index 67926ae7..de3f773a 100644 --- a/flake.nix +++ b/flake.nix @@ -55,7 +55,7 @@ bbdev.gnumake bbdev.pkg-config - # Kernel build tools (RISC-V kernel + rootfs for Pegasus) + # Kernel build tools (RISC-V kernel + rootfs) kernel.e2fsprogs # C libraries (headers + link libs) diff --git a/scripts/claude/mcp_server.py b/scripts/claude/mcp_server.py index 04f4b611..cc747180 100644 --- a/scripts/claude/mcp_server.py +++ b/scripts/claude/mcp_server.py @@ -361,62 +361,5 @@ def bbdev_yosys_synth( return _fmt(result) -@mcp.tool() -def bbdev_pegasus_flashbitstream( - bitstream: Optional[str] = None, - serial: Optional[str] = None, - bus_id: Optional[str] = None, -) -> str: - """Flash bitstream onto AU280 via Vivado hw_server + PCIe remove/rescan. Calls bbdev POST /pegasus/flashbitstream. - - Args: - bitstream: Path to .bit file (default: thirdparty/pegasus/vivado/build/PegasusTop.bit) - serial: hw_server target serial/URL (default: auto, first target) - bus_id: PCIe BDF to remove before flashing, e.g. '0000:65:00.0' (default: auto-detect xdma) - """ - api_params: Dict[str, Any] = {} - if bitstream: - api_params["bitstream"] = bitstream - if serial: - api_params["serial"] = serial - if bus_id: - api_params["bus_id"] = bus_id - result = _bbdev_call("/pegasus/flashbitstream", api_params, timeout=600) - return _fmt(result) - - -@mcp.tool() -def bbdev_pegasus_runworkload( - workload: str = "interactive", - board: str = "chipyard", - timeout: int = 300, - uart: str = "/dev/ttyUSB0", - control: str = "/dev/xdma0_user", - h2c: str = "/dev/xdma0_h2c_0", -) -> str: - """Load Linux image into HBM2 and run on AU280. Calls bbdev POST /pegasus/runworkload. - Requires kernel + rootfs images at bb-tests/output/kernel/ (run bbdev kernel --build first). - UART log is saved to arch/log//pegasus_uart.log. - - Args: - workload: Workload name (default: interactive) - board: Board name (default: chipyard) - timeout: UART collection timeout in seconds (default: 300) - uart: UART device path (default: /dev/ttyUSB0) - control: XDMA control device path (default: /dev/xdma0_control) - h2c: XDMA H2C DMA device path (default: /dev/xdma0_h2c_0) - """ - api_params: Dict[str, Any] = { - "workload": workload, - "board": board, - "timeout": timeout, - "uart": uart, - "control": control, - "h2c": h2c, - } - result = _bbdev_call("/pegasus/runworkload", api_params, timeout=timeout + 120) - return _fmt(result) - - if __name__ == "__main__": mcp.run(transport="stdio") diff --git a/scripts/nix/build-all.sh b/scripts/nix/build-all.sh index 8b1aba0e..68400b38 100755 --- a/scripts/nix/build-all.sh +++ b/scripts/nix/build-all.sh @@ -86,13 +86,14 @@ git submodule update --init --progress \ thirdparty/waveform-mcp # I dont know why below is need for chipyard submodules, but it is -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress fpga/fpga-shells -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress generators/* -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress tools/* +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress fpga/fpga-shells +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress generators/* +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress tools/* git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --progress sims/firesim -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/rocket-dsp-utils -git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force generators/rocc-acc-utils +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/cde +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/firrtl2 +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force tools/rocket-dsp-utils +git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force generators/rocc-acc-utils git -C ${BBDIR}/arch/thirdparty/chipyard submodule update --init --checkout --force generators/bar-fetchers ########################################## @@ -119,7 +120,7 @@ fi if run_step "2"; then begin_step "2" "Compiler installation" cd ${BBDIR}/compiler/thirdparty/buddy-mlir - git submodule update --init llvm + git submodule update --init --progress llvm mkdir -p llvm/build && cd llvm/build cmake -G Ninja ../llvm \ diff --git a/scripts/nix/build-env-clibs.nix b/scripts/nix/build-env-clibs.nix index 4474e1c0..bcd6d5e6 100644 --- a/scripts/nix/build-env-clibs.nix +++ b/scripts/nix/build-env-clibs.nix @@ -13,7 +13,7 @@ # buddy DIP imgcodecs (grfmt_png.h) png-dev = pkgs.libpng.dev; png = pkgs.libpng; - # pegasus-driver: ELF parsing for kernel loading + # ELF parsing for kernel loading elfutils-dev = pkgs.elfutils.dev; elfutils = pkgs.elfutils; } diff --git a/scripts/nix/build-env-python.nix b/scripts/nix/build-env-python.nix index d0057416..e992129d 100644 --- a/scripts/nix/build-env-python.nix +++ b/scripts/nix/build-env-python.nix @@ -1,5 +1,27 @@ { pkgs }: +let + # firesim uses Fabric 1.x API (fabric.api), but nixpkgs only has Fabric 2.x/3.x. + # firesim switched to fab-classic (a maintained Fabric 1.x fork) since 2023. + # Build it from PyPI as a custom derivation. + fab-classic = pkgs.python3Packages.buildPythonPackage rec { + pname = "fab-classic"; + version = "1.19.2"; + format = "setuptools"; + + src = pkgs.python3Packages.fetchPypi { + inherit pname version; + hash = "sha256-kn5JLdNQhUoDzzzeIs6r/LDesY7Byc4RHprNm+5RFFg="; + }; + + propagatedBuildInputs = with pkgs.python3Packages; [ + paramiko + ]; + + # No tests in PyPI tarball + doCheck = false; + }; +in { # Python and pip packages python3 = pkgs.python3; @@ -55,5 +77,18 @@ gitpython humanfriendly doit + + # firesim + argcomplete + cryptography + paramiko + fab-classic + boto3 + mypy-boto3-ec2 + mypy-boto3-s3 + colorama + pylddwrap + graphviz # python-graphviz for topology diagrams + aiohttp ]); } diff --git a/sourceme.sh b/sourceme.sh index 6aae6ef2..b7a75762 100644 --- a/sourceme.sh +++ b/sourceme.sh @@ -39,3 +39,6 @@ export PYTHONPATH="${BBDIR}/bbdev/api:${PYTHONPATH}" # sardine export PYTHONPATH="${BBDIR}/lib/python3.13/site-packages:${PYTHONPATH}" + +# firesim manager +export PATH="${BBDIR}/arch/thirdparty/chipyard/sims/firesim/deploy:${PATH}" From 832f88fcdef8cbdb9017c9fe23e847f0e1879f85 Mon Sep 17 00:00:00 2001 From: nustinx <1017364745@qq.com> Date: Wed, 13 May 2026 22:09:27 +0800 Subject: [PATCH 238/238] feat: add Hadamard machine ball for element-wise multiplication --- .../balldomain/prototype/HadamardUnit.scala | 28 +++++++++++++ .../framework/balldomain/prototype/hadamard | 0 .../balldomain/prototype/hadamard.scala | 41 +++++++++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 arch/src/main/scala/framework/balldomain/prototype/HadamardUnit.scala create mode 100644 arch/src/main/scala/framework/balldomain/prototype/hadamard create mode 100644 arch/src/main/scala/framework/balldomain/prototype/hadamard.scala diff --git a/arch/src/main/scala/framework/balldomain/prototype/HadamardUnit.scala b/arch/src/main/scala/framework/balldomain/prototype/HadamardUnit.scala new file mode 100644 index 00000000..140ac2e3 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/HadamardUnit.scala @@ -0,0 +1,28 @@ +package framework.balldomain.prototype.hadamard + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.balldomain.blink.{BlinkIO, BallStatus} +import framework.top.GlobalConfig + +@instantiable +class HadamardUnit(val b: GlobalConfig) extends Module { + val config = b.ballDomain.ballIdMappings.find(_.ballName == "HadamardBall").get + val inBW = config.inBW + val outBW = config.outBW + + @public + val io = IO(new BlinkIO(b,inBW,outBW)) + + + val vecA = io.bankRead(0).data + val vecB = io.bankRead(1).data + val result = vecA.zip(vecB).map {case (a,b) => a*b} + + io.bankWrite(0).data := result + + io.status.idle := true.B + io.status.running := false.B + io.status.error := 0.U +} \ No newline at end of file diff --git a/arch/src/main/scala/framework/balldomain/prototype/hadamard b/arch/src/main/scala/framework/balldomain/prototype/hadamard new file mode 100644 index 00000000..e69de29b diff --git a/arch/src/main/scala/framework/balldomain/prototype/hadamard.scala b/arch/src/main/scala/framework/balldomain/prototype/hadamard.scala new file mode 100644 index 00000000..4e4ab829 --- /dev/null +++ b/arch/src/main/scala/framework/balldomain/prototype/hadamard.scala @@ -0,0 +1,41 @@ +package framework.balldomain.prototype.hadamard + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} +import framework.balldomain.prototype.hadamard.HadamardUnit +import framework.top.GlobalConfig + +@instantiable +class HadamardBall(val b: GlobalConfig) extends Module with HasBlink with HasBallStatus { + + val ballCommonConfig = b.ballDomain.ballIdMappings.find(_.ballName == "HadamardBall") + .getOrElse(throw new IllegalArgumentException("HadamardBall not found in config")) + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + def status: BallStatus = io.status + + val hadamardUnit: Instance[HadamardUnit] = Instantiate(new HadamardUnit(b)) + + hadamardUnit.io.cmdReq <> io.cmdReq + hadamardUnit.io.cmdResp <> io.cmdResp + + for (i <- 0 until inBW) { + hadamardUnit.io.bankRead(i) <> io.bankRead(i) + } + + for (i <- 0 until outBW) { + hadamardUnit.io.bankWrite(i) <> io.bankWrite(i) + } + + io.status <> hadamardUnit.io.status + + io.subRobReq.valid := false.B + io.subRobReq.bits := SubRobRow.tieOff(b) +} \ No newline at end of file
    diff --git a/docs b/docs new file mode 160000 index 00000000..8a156271 --- /dev/null +++ b/docs @@ -0,0 +1 @@ +Subproject commit 8a1562719c7858f59194dd70f0d88b955594768c diff --git a/docs/.gitignore b/docs/.gitignore deleted file mode 100644 index baa790a6..00000000 --- a/docs/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -book/ -index.html diff --git a/docs/bb-note/book.toml b/docs/bb-note/book.toml deleted file mode 100644 index 28791b47..00000000 --- a/docs/bb-note/book.toml +++ /dev/null @@ -1,20 +0,0 @@ -[book] -authors = ["Dango"] -language = "en" -src = "src" -title = "Buckyball Technical Documentation" - -[preprocessor.toc] -command = "mdbook-toc" -renderer = ["html"] -marker = "[[_TOC_]]" -max-level = 5 - -[preprocessor.mermaid] -command = "mdbook-mermaid" - -[output.html] -additional-js = ["mermaid.min.js", "mermaid-init.js"] - -[output.html.fold] -enable = true diff --git a/docs/bb-note/mermaid-init.js b/docs/bb-note/mermaid-init.js deleted file mode 100644 index 0469ff16..00000000 --- a/docs/bb-note/mermaid-init.js +++ /dev/null @@ -1,39 +0,0 @@ -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. 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sans-serif',this.fontSize="16px",this.labelBackground="#181818",this.textColor="#ccc",this.THEME_COLOR_LIMIT=12,this.nodeBkg="calculated",this.nodeBorder="calculated",this.clusterBkg="calculated",this.clusterBorder="calculated",this.defaultLinkColor="calculated",this.titleColor="#F9FFFE",this.edgeLabelBackground="calculated",this.actorBorder="calculated",this.actorBkg="calculated",this.actorTextColor="calculated",this.actorLineColor="calculated",this.signalColor="calculated",this.signalTextColor="calculated",this.labelBoxBkgColor="calculated",this.labelBoxBorderColor="calculated",this.labelTextColor="calculated",this.loopTextColor="calculated",this.noteBorderColor="calculated",this.noteBkgColor="#fff5ad",this.noteTextColor="calculated",this.activationBorderColor="calculated",this.activationBkgColor="calculated",this.sequenceNumberColor="black",this.sectionBkgColor=Ot("#EAE8D9",30),this.altSectionBkgColor="calculated",this.sectionBkgColor2="#EAE8D9",this.excludeBkgColor=Ot(this.sectionBkgColor,10),this.taskBorderColor=qa(255,255,255,70),this.taskBkgColor="calculated",this.taskTextColor="calculated",this.taskTextLightColor="calculated",this.taskTextOutsideColor="calculated",this.taskTextClickableColor="#003163",this.activeTaskBorderColor=qa(255,255,255,50),this.activeTaskBkgColor="#81B1DB",this.gridColor="calculated",this.doneTaskBkgColor="calculated",this.doneTaskBorderColor="grey",this.critBorderColor="#E83737",this.critBkgColor="#E83737",this.taskTextDarkColor="calculated",this.todayLineColor="#DB5757",this.personBorder=this.primaryBorderColor,this.personBkg=this.mainBkg,this.archEdgeColor="calculated",this.archEdgeArrowColor="calculated",this.archEdgeWidth="3",this.archGroupBorderColor=this.primaryBorderColor,this.archGroupBorderWidth="2px",this.rowOdd=this.rowOdd||Dt(this.mainBkg,5)||"#ffffff",this.rowEven=this.rowEven||Ot(this.mainBkg,10),this.labelColor="calculated",this.errorBkgColor="#a44141",this.errorTextColor="#ddd"}updateColors(){this.secondBkg=Dt(this.mainBkg,16),this.lineColor=this.mainContrastColor,this.arrowheadColor=this.mainContrastColor,this.nodeBkg=this.mainBkg,this.nodeBorder=this.border1,this.clusterBkg=this.secondBkg,this.clusterBorder=this.border2,this.defaultLinkColor=this.lineColor,this.edgeLabelBackground=Dt(this.labelBackground,25),this.actorBorder=this.border1,this.actorBkg=this.mainBkg,this.actorTextColor=this.mainContrastColor,this.actorLineColor=this.actorBorder,this.signalColor=this.mainContrastColor,this.signalTextColor=this.mainContrastColor,this.labelBoxBkgColor=this.actorBkg,this.labelBoxBorderColor=this.actorBorder,this.labelTextColor=this.mainContrastColor,this.loopTextColor=this.mainContrastColor,this.noteBorderColor=this.secondaryBorderColor,this.noteBkgColor=this.secondBkg,this.noteTextColor=this.secondaryTextColor,this.activationBorderColor=this.border1,this.activationBkgColor=this.secondBkg,this.altSectionBkgColor=this.background,this.taskBkgColor=Dt(this.mainBkg,23),this.taskTextColor=this.darkTextColor,this.taskTextLightColor=this.mainContrastColor,this.taskTextOutsideColor=this.taskTextLightColor,this.gridColor=this.mainContrastColor,this.doneTaskBkgColor=this.mainContrastColor,this.taskTextDarkColor=this.darkTextColor,this.archEdgeColor=this.lineColor,this.archEdgeArrowColor=this.lineColor,this.transitionColor=this.transitionColor||this.lineColor,this.transitionLabelColor=this.transitionLabelColor||this.textColor,this.stateLabelColor=this.stateLabelColor||this.stateBkg||this.primaryTextColor,this.stateBkg=this.stateBkg||this.mainBkg,this.labelBackgroundColor=this.labelBackgroundColor||this.stateBkg,this.compositeBackground=this.compositeBackground||this.background||this.tertiaryColor,this.altBackground=this.altBackground||"#555",this.compositeTitleBackground=this.compositeTitleBackground||this.mainBkg,this.compositeBorder=this.compositeBorder||this.nodeBorder,this.innerEndBackground=this.primaryBorderColor,this.specialStateColor="#f4f4f4",this.errorBkgColor=this.errorBkgColor||this.tertiaryColor,this.errorTextColor=this.errorTextColor||this.tertiaryTextColor,this.fillType0=this.primaryColor,this.fillType1=this.secondaryColor,this.fillType2=Me(this.primaryColor,{h:64}),this.fillType3=Me(this.secondaryColor,{h:64}),this.fillType4=Me(this.primaryColor,{h:-64}),this.fillType5=Me(this.secondaryColor,{h:-64}),this.fillType6=Me(this.primaryColor,{h:128}),this.fillType7=Me(this.secondaryColor,{h:128}),this.cScale1=this.cScale1||"#0b0000",this.cScale2=this.cScale2||"#4d1037",this.cScale3=this.cScale3||"#3f5258",this.cScale4=this.cScale4||"#4f2f1b",this.cScale5=this.cScale5||"#6e0a0a",this.cScale6=this.cScale6||"#3b0048",this.cScale7=this.cScale7||"#995a01",this.cScale8=this.cScale8||"#154706",this.cScale9=this.cScale9||"#161722",this.cScale10=this.cScale10||"#00296f",this.cScale11=this.cScale11||"#01629c",this.cScale12=this.cScale12||"#010029",this.cScale0=this.cScale0||this.primaryColor,this.cScale1=this.cScale1||this.secondaryColor,this.cScale2=this.cScale2||this.tertiaryColor,this.cScale3=this.cScale3||Me(this.primaryColor,{h:30}),this.cScale4=this.cScale4||Me(this.primaryColor,{h:60}),this.cScale5=this.cScale5||Me(this.primaryColor,{h:90}),this.cScale6=this.cScale6||Me(this.primaryColor,{h:120}),this.cScale7=this.cScale7||Me(this.primaryColor,{h:150}),this.cScale8=this.cScale8||Me(this.primaryColor,{h:210}),this.cScale9=this.cScale9||Me(this.primaryColor,{h:270}),this.cScale10=this.cScale10||Me(this.primaryColor,{h:300}),this.cScale11=this.cScale11||Me(this.primaryColor,{h:330});for(let e=0;e{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},L$=o(t=>{let e=new KC;return e.calculate(t),e},"getThemeVariables")});var QC,oh,_y=N(()=>{"use strict";Ys();o0();Ay();QC=class{static{o(this,"Theme")}constructor(){this.background="#f4f4f4",this.primaryColor="#ECECFF",this.secondaryColor=Me(this.primaryColor,{h:120}),this.secondaryColor="#ffffde",this.tertiaryColor=Me(this.primaryColor,{h:-160}),this.primaryBorderColor=Ti(this.primaryColor,this.darkMode),this.secondaryBorderColor=Ti(this.secondaryColor,this.darkMode),this.tertiaryBorderColor=Ti(this.tertiaryColor,this.darkMode),this.primaryTextColor=wt(this.primaryColor),this.secondaryTextColor=wt(this.secondaryColor),this.tertiaryTextColor=wt(this.tertiaryColor),this.lineColor=wt(this.background),this.textColor=wt(this.background),this.background="white",this.mainBkg="#ECECFF",this.secondBkg="#ffffde",this.lineColor="#333333",this.border1="#9370DB",this.border2="#aaaa33",this.arrowheadColor="#333333",this.fontFamily='"trebuchet ms", verdana, arial, sans-serif',this.fontSize="16px",this.labelBackground="rgba(232,232,232, 0.8)",this.textColor="#333",this.THEME_COLOR_LIMIT=12,this.nodeBkg="calculated",this.nodeBorder="calculated",this.clusterBkg="calculated",this.clusterBorder="calculated",this.defaultLinkColor="calculated",this.titleColor="calculated",this.edgeLabelBackground="calculated",this.actorBorder="calculated",this.actorBkg="calculated",this.actorTextColor="black",this.actorLineColor="calculated",this.signalColor="calculated",this.signalTextColor="calculated",this.labelBoxBkgColor="calculated",this.labelBoxBorderColor="calculated",this.labelTextColor="calculated",this.loopTextColor="calculated",this.noteBorderColor="calculated",this.noteBkgColor="#fff5ad",this.noteTextColor="calculated",this.activationBorderColor="#666",this.activationBkgColor="#f4f4f4",this.sequenceNumberColor="white",this.sectionBkgColor="calculated",this.altSectionBkgColor="calculated",this.sectionBkgColor2="calculated",this.excludeBkgColor="#eeeeee",this.taskBorderColor="calculated",this.taskBkgColor="calculated",this.taskTextLightColor="calculated",this.taskTextColor=this.taskTextLightColor,this.taskTextDarkColor="calculated",this.taskTextOutsideColor=this.taskTextDarkColor,this.taskTextClickableColor="calculated",this.activeTaskBorderColor="calculated",this.activeTaskBkgColor="calculated",this.gridColor="calculated",this.doneTaskBkgColor="calculated",this.doneTaskBorderColor="calculated",this.critBorderColor="calculated",this.critBkgColor="calculated",this.todayLineColor="calculated",this.sectionBkgColor=qa(102,102,255,.49),this.altSectionBkgColor="white",this.sectionBkgColor2="#fff400",this.taskBorderColor="#534fbc",this.taskBkgColor="#8a90dd",this.taskTextLightColor="white",this.taskTextColor="calculated",this.taskTextDarkColor="black",this.taskTextOutsideColor="calculated",this.taskTextClickableColor="#003163",this.activeTaskBorderColor="#534fbc",this.activeTaskBkgColor="#bfc7ff",this.gridColor="lightgrey",this.doneTaskBkgColor="lightgrey",this.doneTaskBorderColor="grey",this.critBorderColor="#ff8888",this.critBkgColor="red",this.todayLineColor="red",this.personBorder=this.primaryBorderColor,this.personBkg=this.mainBkg,this.archEdgeColor="calculated",this.archEdgeArrowColor="calculated",this.archEdgeWidth="3",this.archGroupBorderColor=this.primaryBorderColor,this.archGroupBorderWidth="2px",this.rowOdd="calculated",this.rowEven="calculated",this.labelColor="black",this.errorBkgColor="#552222",this.errorTextColor="#552222",this.updateColors()}updateColors(){this.cScale0=this.cScale0||this.primaryColor,this.cScale1=this.cScale1||this.secondaryColor,this.cScale2=this.cScale2||this.tertiaryColor,this.cScale3=this.cScale3||Me(this.primaryColor,{h:30}),this.cScale4=this.cScale4||Me(this.primaryColor,{h:60}),this.cScale5=this.cScale5||Me(this.primaryColor,{h:90}),this.cScale6=this.cScale6||Me(this.primaryColor,{h:120}),this.cScale7=this.cScale7||Me(this.primaryColor,{h:150}),this.cScale8=this.cScale8||Me(this.primaryColor,{h:210}),this.cScale9=this.cScale9||Me(this.primaryColor,{h:270}),this.cScale10=this.cScale10||Me(this.primaryColor,{h:300}),this.cScale11=this.cScale11||Me(this.primaryColor,{h:330}),this.cScalePeer1=this.cScalePeer1||Ot(this.secondaryColor,45),this.cScalePeer2=this.cScalePeer2||Ot(this.tertiaryColor,40);for(let e=0;e{this[n]==="calculated"&&(this[n]=void 0)}),typeof e!="object"){this.updateColors();return}let r=Object.keys(e);r.forEach(n=>{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},oh=o(t=>{let e=new QC;return e.calculate(t),e},"getThemeVariables")});var ZC,N$,M$=N(()=>{"use strict";Ys();Ay();o0();ZC=class{static{o(this,"Theme")}constructor(){this.background="#f4f4f4",this.primaryColor="#cde498",this.secondaryColor="#cdffb2",this.background="white",this.mainBkg="#cde498",this.secondBkg="#cdffb2",this.lineColor="green",this.border1="#13540c",this.border2="#6eaa49",this.arrowheadColor="green",this.fontFamily='"trebuchet ms", verdana, arial, sans-serif',this.fontSize="16px",this.tertiaryColor=Dt("#cde498",10),this.primaryBorderColor=Ti(this.primaryColor,this.darkMode),this.secondaryBorderColor=Ti(this.secondaryColor,this.darkMode),this.tertiaryBorderColor=Ti(this.tertiaryColor,this.darkMode),this.primaryTextColor=wt(this.primaryColor),this.secondaryTextColor=wt(this.secondaryColor),this.tertiaryTextColor=wt(this.primaryColor),this.lineColor=wt(this.background),this.textColor=wt(this.background),this.THEME_COLOR_LIMIT=12,this.nodeBkg="calculated",this.nodeBorder="calculated",this.clusterBkg="calculated",this.clusterBorder="calculated",this.defaultLinkColor="calculated",this.titleColor="#333",this.edgeLabelBackground="#e8e8e8",this.actorBorder="calculated",this.actorBkg="calculated",this.actorTextColor="black",this.actorLineColor="calculated",this.signalColor="#333",this.signalTextColor="#333",this.labelBoxBkgColor="calculated",this.labelBoxBorderColor="#326932",this.labelTextColor="calculated",this.loopTextColor="calculated",this.noteBorderColor="calculated",this.noteBkgColor="#fff5ad",this.noteTextColor="calculated",this.activationBorderColor="#666",this.activationBkgColor="#f4f4f4",this.sequenceNumberColor="white",this.sectionBkgColor="#6eaa49",this.altSectionBkgColor="white",this.sectionBkgColor2="#6eaa49",this.excludeBkgColor="#eeeeee",this.taskBorderColor="calculated",this.taskBkgColor="#487e3a",this.taskTextLightColor="white",this.taskTextColor="calculated",this.taskTextDarkColor="black",this.taskTextOutsideColor="calculated",this.taskTextClickableColor="#003163",this.activeTaskBorderColor="calculated",this.activeTaskBkgColor="calculated",this.gridColor="lightgrey",this.doneTaskBkgColor="lightgrey",this.doneTaskBorderColor="grey",this.critBorderColor="#ff8888",this.critBkgColor="red",this.todayLineColor="red",this.personBorder=this.primaryBorderColor,this.personBkg=this.mainBkg,this.archEdgeColor="calculated",this.archEdgeArrowColor="calculated",this.archEdgeWidth="3",this.archGroupBorderColor=this.primaryBorderColor,this.archGroupBorderWidth="2px",this.labelColor="black",this.errorBkgColor="#552222",this.errorTextColor="#552222"}updateColors(){this.actorBorder=Ot(this.mainBkg,20),this.actorBkg=this.mainBkg,this.labelBoxBkgColor=this.actorBkg,this.labelTextColor=this.actorTextColor,this.loopTextColor=this.actorTextColor,this.noteBorderColor=this.border2,this.noteTextColor=this.actorTextColor,this.actorLineColor=this.actorBorder,this.cScale0=this.cScale0||this.primaryColor,this.cScale1=this.cScale1||this.secondaryColor,this.cScale2=this.cScale2||this.tertiaryColor,this.cScale3=this.cScale3||Me(this.primaryColor,{h:30}),this.cScale4=this.cScale4||Me(this.primaryColor,{h:60}),this.cScale5=this.cScale5||Me(this.primaryColor,{h:90}),this.cScale6=this.cScale6||Me(this.primaryColor,{h:120}),this.cScale7=this.cScale7||Me(this.primaryColor,{h:150}),this.cScale8=this.cScale8||Me(this.primaryColor,{h:210}),this.cScale9=this.cScale9||Me(this.primaryColor,{h:270}),this.cScale10=this.cScale10||Me(this.primaryColor,{h:300}),this.cScale11=this.cScale11||Me(this.primaryColor,{h:330}),this.cScalePeer1=this.cScalePeer1||Ot(this.secondaryColor,45),this.cScalePeer2=this.cScalePeer2||Ot(this.tertiaryColor,40);for(let e=0;e{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},N$=o(t=>{let e=new ZC;return e.calculate(t),e},"getThemeVariables")});var JC,I$,O$=N(()=>{"use strict";Ys();o0();Ay();JC=class{static{o(this,"Theme")}constructor(){this.primaryColor="#eee",this.contrast="#707070",this.secondaryColor=Dt(this.contrast,55),this.background="#ffffff",this.tertiaryColor=Me(this.primaryColor,{h:-160}),this.primaryBorderColor=Ti(this.primaryColor,this.darkMode),this.secondaryBorderColor=Ti(this.secondaryColor,this.darkMode),this.tertiaryBorderColor=Ti(this.tertiaryColor,this.darkMode),this.primaryTextColor=wt(this.primaryColor),this.secondaryTextColor=wt(this.secondaryColor),this.tertiaryTextColor=wt(this.tertiaryColor),this.lineColor=wt(this.background),this.textColor=wt(this.background),this.mainBkg="#eee",this.secondBkg="calculated",this.lineColor="#666",this.border1="#999",this.border2="calculated",this.note="#ffa",this.text="#333",this.critical="#d42",this.done="#bbb",this.arrowheadColor="#333333",this.fontFamily='"trebuchet ms", verdana, arial, sans-serif',this.fontSize="16px",this.THEME_COLOR_LIMIT=12,this.nodeBkg="calculated",this.nodeBorder="calculated",this.clusterBkg="calculated",this.clusterBorder="calculated",this.defaultLinkColor="calculated",this.titleColor="calculated",this.edgeLabelBackground="white",this.actorBorder="calculated",this.actorBkg="calculated",this.actorTextColor="calculated",this.actorLineColor=this.actorBorder,this.signalColor="calculated",this.signalTextColor="calculated",this.labelBoxBkgColor="calculated",this.labelBoxBorderColor="calculated",this.labelTextColor="calculated",this.loopTextColor="calculated",this.noteBorderColor="calculated",this.noteBkgColor="calculated",this.noteTextColor="calculated",this.activationBorderColor="#666",this.activationBkgColor="#f4f4f4",this.sequenceNumberColor="white",this.sectionBkgColor="calculated",this.altSectionBkgColor="white",this.sectionBkgColor2="calculated",this.excludeBkgColor="#eeeeee",this.taskBorderColor="calculated",this.taskBkgColor="calculated",this.taskTextLightColor="white",this.taskTextColor="calculated",this.taskTextDarkColor="calculated",this.taskTextOutsideColor="calculated",this.taskTextClickableColor="#003163",this.activeTaskBorderColor="calculated",this.activeTaskBkgColor="calculated",this.gridColor="calculated",this.doneTaskBkgColor="calculated",this.doneTaskBorderColor="calculated",this.critBkgColor="calculated",this.critBorderColor="calculated",this.todayLineColor="calculated",this.personBorder=this.primaryBorderColor,this.personBkg=this.mainBkg,this.archEdgeColor="calculated",this.archEdgeArrowColor="calculated",this.archEdgeWidth="3",this.archGroupBorderColor=this.primaryBorderColor,this.archGroupBorderWidth="2px",this.rowOdd=this.rowOdd||Dt(this.mainBkg,75)||"#ffffff",this.rowEven=this.rowEven||"#f4f4f4",this.labelColor="black",this.errorBkgColor="#552222",this.errorTextColor="#552222"}updateColors(){this.secondBkg=Dt(this.contrast,55),this.border2=this.contrast,this.actorBorder=Dt(this.border1,23),this.actorBkg=this.mainBkg,this.actorTextColor=this.text,this.actorLineColor=this.actorBorder,this.signalColor=this.text,this.signalTextColor=this.text,this.labelBoxBkgColor=this.actorBkg,this.labelBoxBorderColor=this.actorBorder,this.labelTextColor=this.text,this.loopTextColor=this.text,this.noteBorderColor="#999",this.noteBkgColor="#666",this.noteTextColor="#fff",this.cScale0=this.cScale0||"#555",this.cScale1=this.cScale1||"#F4F4F4",this.cScale2=this.cScale2||"#555",this.cScale3=this.cScale3||"#BBB",this.cScale4=this.cScale4||"#777",this.cScale5=this.cScale5||"#999",this.cScale6=this.cScale6||"#DDD",this.cScale7=this.cScale7||"#FFF",this.cScale8=this.cScale8||"#DDD",this.cScale9=this.cScale9||"#BBB",this.cScale10=this.cScale10||"#999",this.cScale11=this.cScale11||"#777";for(let e=0;e{this[n]=e[n]}),this.updateColors(),r.forEach(n=>{this[n]=e[n]})}},I$=o(t=>{let e=new JC;return e.calculate(t),e},"getThemeVariables")});var To,q4=N(()=>{"use strict";D$();R$();_y();M$();O$();To={base:{getThemeVariables:_$},dark:{getThemeVariables:L$},default:{getThemeVariables:oh},forest:{getThemeVariables:N$},neutral:{getThemeVariables:I$}}});var ql,P$=N(()=>{"use strict";ql={flowchart:{useMaxWidth:!0,titleTopMargin:25,subGraphTitleMargin:{top:0,bottom:0},diagramPadding:8,htmlLabels:!0,nodeSpacing:50,rankSpacing:50,curve:"basis",padding:15,defaultRenderer:"dagre-wrapper",wrappingWidth:200},sequence:{useMaxWidth:!0,hideUnusedParticipants:!1,activationWidth:10,diagramMarginX:50,diagramMarginY:10,actorMargin:50,width:150,height:65,boxMargin:10,boxTextMargin:5,noteMargin:10,messageMargin:35,messageAlign:"center",mirrorActors:!0,forceMenus:!1,bottomMarginAdj:1,rightAngles:!1,showSequenceNumbers:!1,actorFontSize:14,actorFontFamily:'"Open Sans", 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this.expect("}"),this.nextToken=r,n}parseExpression(e,r){for(var n=[];;){this.mode==="math"&&this.consumeSpaces();var i=this.fetch();if(t.endOfExpression.indexOf(i.text)!==-1||r&&i.text===r||e&&hh[i.text]&&hh[i.text].infix)break;var a=this.parseAtom(r);if(a){if(a.type==="internal")continue}else break;n.push(a)}return this.mode==="text"&&this.formLigatures(n),this.handleInfixNodes(n)}handleInfixNodes(e){for(var r=-1,n,i=0;i=0&&this.settings.reportNonstrict("unicodeTextInMathMode",'Latin-1/Unicode text character "'+r[0]+'" used in math mode',e);var l=An[this.mode][r].group,u=Xs.range(e),h;if(Mbe.hasOwnProperty(l)){var f=l;h={type:"atom",mode:this.mode,family:f,loc:u,text:r}}else h={type:l,mode:this.mode,loc:u,text:r};s=h}else if(r.charCodeAt(0)>=128)this.settings.strict&&($z(r.charCodeAt(0))?this.mode==="math"&&this.settings.reportNonstrict("unicodeTextInMathMode",'Unicode text character "'+r[0]+'" used in math mode',e):this.settings.reportNonstrict("unknownSymbol",'Unrecognized Unicode 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i=f2(n,"#");(this.options.pedantic||!i||this.rules.other.endingSpaceChar.test(i))&&(n=i.trim())}return{type:"heading",raw:r[0],depth:r[1].length,text:n,tokens:this.lexer.inline(n)}}}hr(e){let r=this.rules.block.hr.exec(e);if(r)return{type:"hr",raw:f2(r[0],` -`)}}blockquote(e){let r=this.rules.block.blockquote.exec(e);if(r){let n=f2(r[0],` -`).split(` -`),i="",a="",s=[];for(;n.length>0;){let l=!1,u=[],h;for(h=0;h1,a={type:"list",raw:"",ordered:i,start:i?+n.slice(0,-1):"",loose:!1,items:[]};n=i?`\\d{1,9}\\${n.slice(-1)}`:`\\${n}`,this.options.pedantic&&(n=i?n:"[*+-]");let s=this.rules.other.listItemRegex(n),l=!1;for(;e;){let h=!1,f="",d="";if(!(r=s.exec(e))||this.rules.block.hr.test(e))break;f=r[0],e=e.substring(f.length);let p=r[2].split(` -`,1)[0].replace(this.rules.other.listReplaceTabs,b=>" ".repeat(3*b.length)),m=e.split(` -`,1)[0],g=!p.trim(),y=0;if(this.options.pedantic?(y=2,d=p.trimStart()):g?y=r[1].length+1:(y=r[2].search(this.rules.other.nonSpaceChar),y=y>4?1:y,d=p.slice(y),y+=r[1].length),g&&this.rules.other.blankLine.test(m)&&(f+=m+` -`,e=e.substring(m.length+1),h=!0),!h){let b=this.rules.other.nextBulletRegex(y),w=this.rules.other.hrRegex(y),C=this.rules.other.fencesBeginRegex(y),T=this.rules.other.headingBeginRegex(y),E=this.rules.other.htmlBeginRegex(y);for(;e;){let A=e.split(` -`,1)[0],S;if(m=A,this.options.pedantic?(m=m.replace(this.rules.other.listReplaceNesting," "),S=m):S=m.replace(this.rules.other.tabCharGlobal," "),C.test(m)||T.test(m)||E.test(m)||b.test(m)||w.test(m))break;if(S.search(this.rules.other.nonSpaceChar)>=y||!m.trim())d+=` -`+S.slice(y);else{if(g||p.replace(this.rules.other.tabCharGlobal," ").search(this.rules.other.nonSpaceChar)>=4||C.test(p)||T.test(p)||w.test(p))break;d+=` -`+m}!g&&!m.trim()&&(g=!0),f+=A+` -`,e=e.substring(A.length+1),p=S.slice(y)}}a.loose||(l?a.loose=!0:this.rules.other.doubleBlankLine.test(f)&&(l=!0));let v=null,x;this.options.gfm&&(v=this.rules.other.listIsTask.exec(d),v&&(x=v[0]!=="[ ] ",d=d.replace(this.rules.other.listReplaceTask,""))),a.items.push({type:"list_item",raw:f,task:!!v,checked:x,loose:!1,text:d,tokens:[]}),a.raw+=f}let u=a.items.at(-1);if(u)u.raw=u.raw.trimEnd(),u.text=u.text.trimEnd();else return;a.raw=a.raw.trimEnd();for(let h=0;hp.type==="space"),d=f.length>0&&f.some(p=>this.rules.other.anyLine.test(p.raw));a.loose=d}if(a.loose)for(let h=0;h({text:u,tokens:this.lexer.inline(u),header:!1,align:s.align[h]})));return s}}lheading(e){let r=this.rules.block.lheading.exec(e);if(r)return{type:"heading",raw:r[0],depth:r[2].charAt(0)==="="?1:2,text:r[1],tokens:this.lexer.inline(r[1])}}paragraph(e){let r=this.rules.block.paragraph.exec(e);if(r){let n=r[1].charAt(r[1].length-1)===` -`?r[1].slice(0,-1):r[1];return{type:"paragraph",raw:r[0],text:n,tokens:this.lexer.inline(n)}}}text(e){let r=this.rules.block.text.exec(e);if(r)return{type:"text",raw:r[0],text:r[0],tokens:this.lexer.inline(r[0])}}escape(e){let r=this.rules.inline.escape.exec(e);if(r)return{type:"escape",raw:r[0],text:r[1]}}tag(e){let r=this.rules.inline.tag.exec(e);if(r)return!this.lexer.state.inLink&&this.rules.other.startATag.test(r[0])?this.lexer.state.inLink=!0:this.lexer.state.inLink&&this.rules.other.endATag.test(r[0])&&(this.lexer.state.inLink=!1),!this.lexer.state.inRawBlock&&this.rules.other.startPreScriptTag.test(r[0])?this.lexer.state.inRawBlock=!0:this.lexer.state.inRawBlock&&this.rules.other.endPreScriptTag.test(r[0])&&(this.lexer.state.inRawBlock=!1),{type:"html",raw:r[0],inLink:this.lexer.state.inLink,inRawBlock:this.lexer.state.inRawBlock,block:!1,text:r[0]}}link(e){let r=this.rules.inline.link.exec(e);if(r){let n=r[2].trim();if(!this.options.pedantic&&this.rules.other.startAngleBracket.test(n)){if(!this.rules.other.endAngleBracket.test(n))return;let s=f2(n.slice(0,-1),"\\");if((n.length-s.length)%2===0)return}else{let s=$8e(r[2],"()");if(s>-1){let u=(r[0].indexOf("!")===0?5:4)+r[1].length+s;r[2]=r[2].substring(0,s),r[0]=r[0].substring(0,u).trim(),r[3]=""}}let i=r[2],a="";if(this.options.pedantic){let s=this.rules.other.pedanticHrefTitle.exec(i);s&&(i=s[1],a=s[3])}else a=r[3]?r[3].slice(1,-1):"";return i=i.trim(),this.rules.other.startAngleBracket.test(i)&&(this.options.pedantic&&!this.rules.other.endAngleBracket.test(n)?i=i.slice(1):i=i.slice(1,-1)),zj(r,{href:i&&i.replace(this.rules.inline.anyPunctuation,"$1"),title:a&&a.replace(this.rules.inline.anyPunctuation,"$1")},r[0],this.lexer,this.rules)}}reflink(e,r){let n;if((n=this.rules.inline.reflink.exec(e))||(n=this.rules.inline.nolink.exec(e))){let i=(n[2]||n[1]).replace(this.rules.other.multipleSpaceGlobal," "),a=r[i.toLowerCase()];if(!a){let s=n[0].charAt(0);return{type:"text",raw:s,text:s}}return zj(n,a,n[0],this.lexer,this.rules)}}emStrong(e,r,n=""){let i=this.rules.inline.emStrongLDelim.exec(e);if(!i||i[3]&&n.match(this.rules.other.unicodeAlphaNumeric))return;if(!(i[1]||i[2]||"")||!n||this.rules.inline.punctuation.exec(n)){let s=[...i[0]].length-1,l,u,h=s,f=0,d=i[0][0]==="*"?this.rules.inline.emStrongRDelimAst:this.rules.inline.emStrongRDelimUnd;for(d.lastIndex=0,r=r.slice(-1*e.length+s);(i=d.exec(r))!=null;){if(l=i[1]||i[2]||i[3]||i[4]||i[5]||i[6],!l)continue;if(u=[...l].length,i[3]||i[4]){h+=u;continue}else if((i[5]||i[6])&&s%3&&!((s+u)%3)){f+=u;continue}if(h-=u,h>0)continue;u=Math.min(u,u+h+f);let p=[...i[0]][0].length,m=e.slice(0,s+i.index+p+u);if(Math.min(s,u)%2){let y=m.slice(1,-1);return{type:"em",raw:m,text:y,tokens:this.lexer.inlineTokens(y)}}let g=m.slice(2,-2);return{type:"strong",raw:m,text:g,tokens:this.lexer.inlineTokens(g)}}}}codespan(e){let r=this.rules.inline.code.exec(e);if(r){let n=r[2].replace(this.rules.other.newLineCharGlobal," "),i=this.rules.other.nonSpaceChar.test(n),a=this.rules.other.startingSpaceChar.test(n)&&this.rules.other.endingSpaceChar.test(n);return i&&a&&(n=n.substring(1,n.length-1)),{type:"codespan",raw:r[0],text:n}}}br(e){let r=this.rules.inline.br.exec(e);if(r)return{type:"br",raw:r[0]}}del(e){let r=this.rules.inline.del.exec(e);if(r)return{type:"del",raw:r[0],text:r[2],tokens:this.lexer.inlineTokens(r[2])}}autolink(e){let r=this.rules.inline.autolink.exec(e);if(r){let n,i;return r[2]==="@"?(n=r[1],i="mailto:"+n):(n=r[1],i=n),{type:"link",raw:r[0],text:n,href:i,tokens:[{type:"text",raw:n,text:n}]}}}url(e){let r;if(r=this.rules.inline.url.exec(e)){let n,i;if(r[2]==="@")n=r[0],i="mailto:"+n;else{let a;do a=r[0],r[0]=this.rules.inline._backpedal.exec(r[0])?.[0]??"";while(a!==r[0]);n=r[0],r[1]==="www."?i="http://"+r[0]:i=r[0]}return{type:"link",raw:r[0],text:n,href:i,tokens:[{type:"text",raw:n,text:n}]}}}inlineText(e){let r=this.rules.inline.text.exec(e);if(r){let n=this.lexer.state.inRawBlock;return{type:"text",raw:r[0],text:r[0],escaped:n}}}},Al=class t{static{o(this,"_Lexer")}tokens;options;state;tokenizer;inlineQueue;constructor(e){this.tokens=[],this.tokens.links=Object.create(null),this.options=e||Id,this.options.tokenizer=this.options.tokenizer||new hm,this.tokenizer=this.options.tokenizer,this.tokenizer.options=this.options,this.tokenizer.lexer=this,this.inlineQueue=[],this.state={inLink:!1,inRawBlock:!1,top:!0};let r={other:ts,block:Sw.normal,inline:h2.normal};this.options.pedantic?(r.block=Sw.pedantic,r.inline=h2.pedantic):this.options.gfm&&(r.block=Sw.gfm,this.options.breaks?r.inline=h2.breaks:r.inline=h2.gfm),this.tokenizer.rules=r}static get rules(){return{block:Sw,inline:h2}}static lex(e,r){return new t(r).lex(e)}static lexInline(e,r){return new t(r).inlineTokens(e)}lex(e){e=e.replace(ts.carriageReturn,` -`),this.blockTokens(e,this.tokens);for(let r=0;r(i=s.call({lexer:this},e,r))?(e=e.substring(i.raw.length),r.push(i),!0):!1))continue;if(i=this.tokenizer.space(e)){e=e.substring(i.raw.length);let s=r.at(-1);i.raw.length===1&&s!==void 0?s.raw+=` -`:r.push(i);continue}if(i=this.tokenizer.code(e)){e=e.substring(i.raw.length);let s=r.at(-1);s?.type==="paragraph"||s?.type==="text"?(s.raw+=` -`+i.raw,s.text+=` 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a=e;if(this.options.extensions?.startBlock){let s=1/0,l=e.slice(1),u;this.options.extensions.startBlock.forEach(h=>{u=h.call({lexer:this},l),typeof u=="number"&&u>=0&&(s=Math.min(s,u))}),s<1/0&&s>=0&&(a=e.substring(0,s+1))}if(this.state.top&&(i=this.tokenizer.paragraph(a))){let s=r.at(-1);n&&s?.type==="paragraph"?(s.raw+=` -`+i.raw,s.text+=` -`+i.text,this.inlineQueue.pop(),this.inlineQueue.at(-1).src=s.text):r.push(i),n=a.length!==e.length,e=e.substring(i.raw.length);continue}if(i=this.tokenizer.text(e)){e=e.substring(i.raw.length);let s=r.at(-1);s?.type==="text"?(s.raw+=` -`+i.raw,s.text+=` -`+i.text,this.inlineQueue.pop(),this.inlineQueue.at(-1).src=s.text):r.push(i);continue}if(e){let s="Infinite loop on byte: "+e.charCodeAt(0);if(this.options.silent){console.error(s);break}else throw new Error(s)}}return this.state.top=!0,r}inline(e,r=[]){return this.inlineQueue.push({src:e,tokens:r}),r}inlineTokens(e,r=[]){let n=e,i=null;if(this.tokens.links){let l=Object.keys(this.tokens.links);if(l.length>0)for(;(i=this.tokenizer.rules.inline.reflinkSearch.exec(n))!=null;)l.includes(i[0].slice(i[0].lastIndexOf("[")+1,-1))&&(n=n.slice(0,i.index)+"["+"a".repeat(i[0].length-2)+"]"+n.slice(this.tokenizer.rules.inline.reflinkSearch.lastIndex))}for(;(i=this.tokenizer.rules.inline.blockSkip.exec(n))!=null;)n=n.slice(0,i.index)+"["+"a".repeat(i[0].length-2)+"]"+n.slice(this.tokenizer.rules.inline.blockSkip.lastIndex);for(;(i=this.tokenizer.rules.inline.anyPunctuation.exec(n))!=null;)n=n.slice(0,i.index)+"++"+n.slice(this.tokenizer.rules.inline.anyPunctuation.lastIndex);let a=!1,s="";for(;e;){a||(s=""),a=!1;let l;if(this.options.extensions?.inline?.some(h=>(l=h.call({lexer:this},e,r))?(e=e.substring(l.raw.length),r.push(l),!0):!1))continue;if(l=this.tokenizer.escape(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.tag(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.link(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.reflink(e,this.tokens.links)){e=e.substring(l.raw.length);let h=r.at(-1);l.type==="text"&&h?.type==="text"?(h.raw+=l.raw,h.text+=l.text):r.push(l);continue}if(l=this.tokenizer.emStrong(e,n,s)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.codespan(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.br(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.del(e)){e=e.substring(l.raw.length),r.push(l);continue}if(l=this.tokenizer.autolink(e)){e=e.substring(l.raw.length),r.push(l);continue}if(!this.state.inLink&&(l=this.tokenizer.url(e))){e=e.substring(l.raw.length),r.push(l);continue}let u=e;if(this.options.extensions?.startInline){let h=1/0,f=e.slice(1),d;this.options.extensions.startInline.forEach(p=>{d=p.call({lexer:this},f),typeof d=="number"&&d>=0&&(h=Math.min(h,d))}),h<1/0&&h>=0&&(u=e.substring(0,h+1))}if(l=this.tokenizer.inlineText(u)){e=e.substring(l.raw.length),l.raw.slice(-1)!=="_"&&(s=l.raw.slice(-1)),a=!0;let h=r.at(-1);h?.type==="text"?(h.raw+=l.raw,h.text+=l.text):r.push(l);continue}if(e){let h="Infinite loop on byte: "+e.charCodeAt(0);if(this.options.silent){console.error(h);break}else throw new Error(h)}}return r}},fm=class{static{o(this,"_Renderer")}options;parser;constructor(e){this.options=e||Id}space(e){return""}code({text:e,lang:r,escaped:n}){let i=(r||"").match(ts.notSpaceStart)?.[0],a=e.replace(ts.endingNewline,"")+` -`;return i?'
    '+(n?a:pc(a,!0))+`
    -`:"
    "+(n?a:pc(a,!0))+`
    -`}blockquote({tokens:e}){return`
    -${this.parser.parse(e)}
    -`}html({text:e}){return e}heading({tokens:e,depth:r}){return`${this.parser.parseInline(e)} -`}hr(e){return`
    -`}list(e){let r=e.ordered,n=e.start,i="";for(let l=0;l -`+i+" -`}listitem(e){let r="";if(e.task){let n=this.checkbox({checked:!!e.checked});e.loose?e.tokens[0]?.type==="paragraph"?(e.tokens[0].text=n+" "+e.tokens[0].text,e.tokens[0].tokens&&e.tokens[0].tokens.length>0&&e.tokens[0].tokens[0].type==="text"&&(e.tokens[0].tokens[0].text=n+" "+pc(e.tokens[0].tokens[0].text),e.tokens[0].tokens[0].escaped=!0)):e.tokens.unshift({type:"text",raw:n+" ",text:n+" ",escaped:!0}):r+=n+" "}return r+=this.parser.parse(e.tokens,!!e.loose),`
  • ${r}
    • -`}checkbox({checked:e}){return"'}paragraph({tokens:e}){return`

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70:this.$=ye[Te-3],lt.addVertex(ye[Te-3],ye[Te-1],"lean_right");break;case 71:this.$=ye[Te-3],lt.addVertex(ye[Te-3],ye[Te-1],"lean_left");break;case 72:this.$=ye[Te],lt.addVertex(ye[Te]);break;case 73:ye[Te-1].text=ye[Te],this.$=ye[Te-1];break;case 74:case 75:ye[Te-2].text=ye[Te-1],this.$=ye[Te-2];break;case 76:this.$=ye[Te];break;case 77:var wi=lt.destructLink(ye[Te],ye[Te-2]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length,text:ye[Te-1]};break;case 78:var wi=lt.destructLink(ye[Te],ye[Te-2]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length,text:ye[Te-1],id:ye[Te-3]};break;case 79:this.$={text:ye[Te],type:"text"};break;case 80:this.$={text:ye[Te-1].text+""+ye[Te],type:ye[Te-1].type};break;case 81:this.$={text:ye[Te],type:"string"};break;case 82:this.$={text:ye[Te],type:"markdown"};break;case 83:var wi=lt.destructLink(ye[Te]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length};break;case 84:var wi=lt.destructLink(ye[Te]);this.$={type:wi.type,stroke:wi.stroke,length:wi.length,id:ye[Te-1]};break;case 85:this.$=ye[Te-1];break;case 86:this.$={text:ye[Te],type:"text"};break;case 87:this.$={text:ye[Te-1].text+""+ye[Te],type:ye[Te-1].type};break;case 88:this.$={text:ye[Te],type:"string"};break;case 89:case 104:this.$={text:ye[Te],type:"markdown"};break;case 101:this.$={text:ye[Te],type:"text"};break;case 102:this.$={text:ye[Te-1].text+""+ye[Te],type:ye[Te-1].type};break;case 103:this.$={text:ye[Te],type:"text"};break;case 105:this.$=ye[Te-4],lt.addClass(ye[Te-2],ye[Te]);break;case 106:this.$=ye[Te-4],lt.setClass(ye[Te-2],ye[Te]);break;case 107:case 115:this.$=ye[Te-1],lt.setClickEvent(ye[Te-1],ye[Te]);break;case 108:case 116:this.$=ye[Te-3],lt.setClickEvent(ye[Te-3],ye[Te-2]),lt.setTooltip(ye[Te-3],ye[Te]);break;case 109:this.$=ye[Te-2],lt.setClickEvent(ye[Te-2],ye[Te-1],ye[Te]);break;case 110:this.$=ye[Te-4],lt.setClickEvent(ye[Te-4],ye[Te-3],ye[Te-2]),lt.setTooltip(ye[Te-4],ye[Te]);break;case 111:this.$=ye[Te-2],lt.setLink(ye[Te-2],ye[Te]);break;case 112:this.$=ye[Te-4],lt.setLink(ye[Te-4],ye[Te-2]),lt.setTooltip(ye[Te-4],ye[Te]);break;case 113:this.$=ye[Te-4],lt.setLink(ye[Te-4],ye[Te-2],ye[Te]);break;case 114:this.$=ye[Te-6],lt.setLink(ye[Te-6],ye[Te-4],ye[Te]),lt.setTooltip(ye[Te-6],ye[Te-2]);break;case 117:this.$=ye[Te-1],lt.setLink(ye[Te-1],ye[Te]);break;case 118:this.$=ye[Te-3],lt.setLink(ye[Te-3],ye[Te-2]),lt.setTooltip(ye[Te-3],ye[Te]);break;case 119:this.$=ye[Te-3],lt.setLink(ye[Te-3],ye[Te-2],ye[Te]);break;case 120:this.$=ye[Te-5],lt.setLink(ye[Te-5],ye[Te-4],ye[Te]),lt.setTooltip(ye[Te-5],ye[Te-2]);break;case 121:this.$=ye[Te-4],lt.addVertex(ye[Te-2],void 0,void 0,ye[Te]);break;case 122:this.$=ye[Te-4],lt.updateLink([ye[Te-2]],ye[Te]);break;case 123:this.$=ye[Te-4],lt.updateLink(ye[Te-2],ye[Te]);break;case 124:this.$=ye[Te-8],lt.updateLinkInterpolate([ye[Te-6]],ye[Te-2]),lt.updateLink([ye[Te-6]],ye[Te]);break;case 125:this.$=ye[Te-8],lt.updateLinkInterpolate(ye[Te-6],ye[Te-2]),lt.updateLink(ye[Te-6],ye[Te]);break;case 126:this.$=ye[Te-6],lt.updateLinkInterpolate([ye[Te-4]],ye[Te]);break;case 127:this.$=ye[Te-6],lt.updateLinkInterpolate(ye[Te-4],ye[Te]);break;case 128:case 130:this.$=[ye[Te]];break;case 129:case 131:ye[Te-2].push(ye[Te]),this.$=ye[Te-2];break;case 133:this.$=ye[Te-1]+ye[Te];break;case 181:this.$=ye[Te];break;case 182:this.$=ye[Te-1]+""+ye[Te];break;case 184:this.$=ye[Te-1]+""+ye[Te];break;case 185:this.$={stmt:"dir",value:"TB"};break;case 186:this.$={stmt:"dir",value:"BT"};break;case 187:this.$={stmt:"dir",value:"RL"};break;case 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this.yy=mt||this.yy||{},this._input=et,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var et=this._input[0];this.yytext+=et,this.yyleng++,this.offset++,this.match+=et,this.matched+=et;var mt=et.match(/(?:\r\n?|\n).*/g);return mt?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),et},"input"),unput:o(function(et){var mt=et.length,Kt=et.split(/(?:\r\n?|\n)/g);this._input=et+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-mt),this.offset-=mt;var lt=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),Kt.length-1&&(this.yylineno-=Kt.length-1);var Cn=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:Kt?(Kt.length===lt.length?this.yylloc.first_column:0)+lt[lt.length-Kt.length].length-Kt[0].length:this.yylloc.first_column-mt},this.options.ranges&&(this.yylloc.range=[Cn[0],Cn[0]+this.yyleng-mt]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). -`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(et){this.unput(this.match.slice(et))},"less"),pastInput:o(function(){var et=this.matched.substr(0,this.matched.length-this.match.length);return(et.length>20?"...":"")+et.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var et=this.match;return et.length<20&&(et+=this._input.substr(0,20-et.length)),(et.substr(0,20)+(et.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var et=this.pastInput(),mt=new Array(et.length+1).join("-");return et+this.upcomingInput()+` -`+mt+"^"},"showPosition"),test_match:o(function(et,mt){var Kt,lt,Cn;if(this.options.backtrack_lexer&&(Cn={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(Cn.yylloc.range=this.yylloc.range.slice(0))),lt=et[0].match(/(?:\r\n?|\n).*/g),lt&&(this.yylineno+=lt.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:lt?lt[lt.length-1].length-lt[lt.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+et[0].length},this.yytext+=et[0],this.match+=et[0],this.matches=et,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(et[0].length),this.matched+=et[0],Kt=this.performAction.call(this,this.yy,this,mt,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),Kt)return Kt;if(this._backtrack){for(var ye in Cn)this[ye]=Cn[ye];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var et,mt,Kt,lt;this._more||(this.yytext="",this.match="");for(var Cn=this._currentRules(),ye=0;yemt[0].length)){if(mt=Kt,lt=ye,this.options.backtrack_lexer){if(et=this.test_match(Kt,Cn[ye]),et!==!1)return et;if(this._backtrack){mt=!1;continue}else return!1}else if(!this.options.flex)break}return mt?(et=this.test_match(mt,Cn[lt]),et!==!1?et:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. -`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var mt=this.next();return mt||this.lex()},"lex"),begin:o(function(mt){this.conditionStack.push(mt)},"begin"),popState:o(function(){var mt=this.conditionStack.length-1;return mt>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(mt){return mt=this.conditionStack.length-1-Math.abs(mt||0),mt>=0?this.conditionStack[mt]:"INITIAL"},"topState"),pushState:o(function(mt){this.begin(mt)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{},performAction:o(function(mt,Kt,lt,Cn){var ye=Cn;switch(lt){case 0:return this.begin("acc_title"),34;break;case 1:return this.popState(),"acc_title_value";break;case 2:return this.begin("acc_descr"),36;break;case 3:return this.popState(),"acc_descr_value";break;case 4:this.begin("acc_descr_multiline");break;case 5:this.popState();break;case 6:return"acc_descr_multiline_value";case 7:return this.pushState("shapeData"),Kt.yytext="",40;break;case 8:return this.pushState("shapeDataStr"),40;break;case 9:return this.popState(),40;break;case 10:let Vf=/\n\s*/g;return Kt.yytext=Kt.yytext.replace(Vf,"
    "),40;break;case 11:return 40;case 12:this.popState();break;case 13:this.begin("callbackname");break;case 14:this.popState();break;case 15:this.popState(),this.begin("callbackargs");break;case 16:return 95;case 17:this.popState();break;case 18:return 96;case 19:return"MD_STR";case 20:this.popState();break;case 21:this.begin("md_string");break;case 22:return"STR";case 23:this.popState();break;case 24:this.pushState("string");break;case 25:return 84;case 26:return 102;case 27:return 85;case 28:return 104;case 29:return 86;case 30:return 87;case 31:return 97;case 32:this.begin("click");break;case 33:this.popState();break;case 34:return 88;case 35:return mt.lex.firstGraph()&&this.begin("dir"),12;break;case 36:return mt.lex.firstGraph()&&this.begin("dir"),12;break;case 37:return mt.lex.firstGraph()&&this.begin("dir"),12;break;case 38:return 27;case 39:return 32;case 40:return 98;case 41:return 98;case 42:return 98;case 43:return 98;case 44:return this.popState(),13;break;case 45:return this.popState(),14;break;case 46:return this.popState(),14;break;case 47:return this.popState(),14;break;case 48:return this.popState(),14;break;case 49:return this.popState(),14;break;case 50:return this.popState(),14;break;case 51:return this.popState(),14;break;case 52:return this.popState(),14;break;case 53:return this.popState(),14;break;case 54:return this.popState(),14;break;case 55:return 121;case 56:return 122;case 57:return 123;case 58:return 124;case 59:return 78;case 60:return 105;case 61:return 111;case 62:return 46;case 63:return 60;case 64:return 44;case 65:return 8;case 66:return 106;case 67:return 115;case 68:return this.popState(),77;break;case 69:return this.pushState("edgeText"),75;break;case 70:return 119;case 71:return this.popState(),77;break;case 72:return this.pushState("thickEdgeText"),75;break;case 73:return 119;case 74:return this.popState(),77;break;case 75:return this.pushState("dottedEdgeText"),75;break;case 76:return 119;case 77:return 77;case 78:return this.popState(),53;break;case 79:return"TEXT";case 80:return this.pushState("ellipseText"),52;break;case 81:return this.popState(),55;break;case 82:return this.pushState("text"),54;break;case 83:return this.popState(),57;break;case 84:return this.pushState("text"),56;break;case 85:return 58;case 86:return this.pushState("text"),67;break;case 87:return this.popState(),64;break;case 88:return this.pushState("text"),63;break;case 89:return this.popState(),49;break;case 90:return this.pushState("text"),48;break;case 91:return this.popState(),69;break;case 92:return this.popState(),71;break;case 93:return 117;case 94:return this.pushState("trapText"),68;break;case 95:return this.pushState("trapText"),70;break;case 96:return 118;case 97:return 67;case 98:return 90;case 99:return"SEP";case 100:return 89;case 101:return 115;case 102:return 111;case 103:return 44;case 104:return 109;case 105:return 114;case 106:return 116;case 107:return this.popState(),62;break;case 108:return this.pushState("text"),62;break;case 109:return this.popState(),51;break;case 110:return this.pushState("text"),50;break;case 111:return this.popState(),31;break;case 112:return this.pushState("text"),29;break;case 113:return this.popState(),66;break;case 114:return this.pushState("text"),65;break;case 115:return"TEXT";case 116:return"QUOTE";case 117:return 9;case 118:return 10;case 119:return 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ns([".","\\","[","]","|","^","$","(",")","?","*","+","{"],r=>t.source.indexOf(r)!==-1)===void 0}function Gae(t){let e=t.ignoreCase?"i":"";return new RegExp(`^(?:${t.source})`,e)}function Vae(t){let e=t.ignoreCase?"iy":"y";return new RegExp(`${t.source}`,e)}function Wae(t,e,r){let n=[];return Bt(t,$g)||n.push({message:"A MultiMode Lexer cannot be initialized without a <"+$g+`> property in its definition -`,type:Yn.MULTI_MODE_LEXER_WITHOUT_DEFAULT_MODE}),Bt(t,Mk)||n.push({message:"A MultiMode Lexer cannot be initialized without a <"+Mk+`> property in its definition -`,type:Yn.MULTI_MODE_LEXER_WITHOUT_MODES_PROPERTY}),Bt(t,Mk)&&Bt(t,$g)&&!Bt(t.modes,t.defaultMode)&&n.push({message:`A MultiMode Lexer cannot be initialized with a ${$g}: <${t.defaultMode}>which does not exist -`,type:Yn.MULTI_MODE_LEXER_DEFAULT_MODE_VALUE_DOES_NOT_EXIST}),Bt(t,Mk)&&Ae(t.modes,(i,a)=>{Ae(i,(s,l)=>{if(pr(s))n.push({message:`A Lexer cannot be initialized using an undefined Token Type. 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details.`,type:Yn.NO_LINE_BREAKS_FLAGS}),n}function Yae(t){let e={},r=zr(t);return Ae(r,n=>{let i=t[n];if(Pt(i))e[n]=[];else throw Error("non exhaustive match")}),e}function Xae(t){let e=t.PATTERN;if(zo(e))return!1;if(Si(e))return!0;if(Bt(e,"exec"))return!0;if(yi(e))return!1;throw Error("non exhaustive match")}function $Pe(t){return yi(t)&&t.length===1?t.charCodeAt(0):!1}function Kae(t,e){if(Bt(t,"LINE_BREAKS"))return!1;if(zo(t.PATTERN)){try{Nk(e,t.PATTERN)}catch(r){return{issue:Yn.IDENTIFY_TERMINATOR,errMsg:r.message}}return!1}else{if(yi(t.PATTERN))return!1;if(Xae(t))return{issue:Yn.CUSTOM_LINE_BREAK};throw Error("non exhaustive match")}}function zPe(t,e){if(e.issue===Yn.IDENTIFY_TERMINATOR)return`Warning: unable to identify line terminator usage in pattern. - The problem is in the <${t.name}> Token Type - Root cause: ${e.errMsg}. - For details See: https://chevrotain.io/docs/guide/resolving_lexer_errors.html#IDENTIFY_TERMINATOR`;if(e.issue===Yn.CUSTOM_LINE_BREAK)return`Warning: A Custom Token Pattern should specify the option. - The problem is in the <${t.name}> Token Type - For details See: https://chevrotain.io/docs/guide/resolving_lexer_errors.html#CUSTOM_LINE_BREAK`;throw Error("non exhaustive match")}function Qae(t){return Je(t,r=>yi(r)?r.charCodeAt(0):r)}function CN(t,e,r){t[e]===void 0?t[e]=[r]:t[e].push(r)}function Ic(t){return t255?255+~~(t/255):t}}var lp,$g,Mk,AN,APe,LPe,jae,Fg,Ik,SN=N(()=>{"use strict";j2();ix();qt();Og();zae();Lk();lp="PATTERN",$g="defaultMode",Mk="modes",AN=typeof new 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UPe(t){Ae(t,e=>{_N(e)||(ese[Zae]=e,e.tokenTypeIdx=Zae++),Jae(e)&&!Pt(e.CATEGORIES)&&(e.CATEGORIES=[e.CATEGORIES]),Jae(e)||(e.CATEGORIES=[]),qPe(e)||(e.categoryMatches=[]),YPe(e)||(e.categoryMatchesMap={})})}function HPe(t){Ae(t,e=>{e.categoryMatches=[],Ae(e.categoryMatchesMap,(r,n)=>{e.categoryMatches.push(ese[n].tokenTypeIdx)})})}function WPe(t){Ae(t,e=>{tse([],e)})}function tse(t,e){Ae(t,r=>{e.categoryMatchesMap[r.tokenTypeIdx]=!0}),Ae(e.CATEGORIES,r=>{let n=t.concat(e);qn(n,r)||tse(n,r)})}function _N(t){return Bt(t,"tokenTypeIdx")}function Jae(t){return Bt(t,"CATEGORIES")}function qPe(t){return Bt(t,"categoryMatches")}function YPe(t){return Bt(t,"categoryMatchesMap")}function rse(t){return Bt(t,"tokenTypeIdx")}var Zae,ese,cp=N(()=>{"use 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n=this.config.traceInitPerf;n===!0?(this.traceInitMaxIdent=1/0,this.traceInitPerf=!0):typeof n=="number"&&(this.traceInitMaxIdent=n,this.traceInitPerf=!0),this.traceInitIndent=-1,this.TRACE_INIT("Lexer Constructor",()=>{let i,a=!0;this.TRACE_INIT("Lexer Config handling",()=>{if(this.config.lineTerminatorsPattern===ax.lineTerminatorsPattern)this.config.lineTerminatorsPattern=jae;else if(this.config.lineTerminatorCharacters===ax.lineTerminatorCharacters)throw Error(`Error: Missing property on the Lexer config. - For details See: https://chevrotain.io/docs/guide/resolving_lexer_errors.html#MISSING_LINE_TERM_CHARS`);if(r.safeMode&&r.ensureOptimizations)throw Error('"safeMode" and "ensureOptimizations" flags are mutually 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h;this.TRACE_INIT("analyzeTokenTypes",()=>{h=Uae(l,{lineTerminatorCharacters:this.config.lineTerminatorCharacters,positionTracking:r.positionTracking,ensureOptimizations:r.ensureOptimizations,safeMode:r.safeMode,tracer:this.TRACE_INIT})}),this.patternIdxToConfig[u]=h.patternIdxToConfig,this.charCodeToPatternIdxToConfig[u]=h.charCodeToPatternIdxToConfig,this.emptyGroups=ma({},this.emptyGroups,h.emptyGroups),this.hasCustom=h.hasCustom||this.hasCustom,this.canModeBeOptimized[u]=h.canBeOptimized}})}),this.defaultMode=i.defaultMode,!ur(this.lexerDefinitionErrors)&&!this.config.deferDefinitionErrorsHandling){let u=Je(this.lexerDefinitionErrors,h=>h.message).join(`----------------------- -`);throw new Error(`Errors detected in definition of Lexer: -`+u)}Ae(this.lexerDefinitionWarning,l=>{ex(l.message)}),this.TRACE_INIT("Choosing sub-methods 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i=ya(t,u=>ZPe(u,r)),a=iBe(t,e,r),s=ya(t,u=>tBe(u,r)),l=ya(t,u=>eBe(u,t,n,r));return i.concat(a,s,l)}function ZPe(t,e){let r=new ON;t.accept(r);let n=r.allProductions,i=IL(n,JPe),a=Os(i,l=>l.length>1);return Je(br(a),l=>{let u=ia(l),h=e.buildDuplicateFoundError(t,l),f=Bs(u),d={message:h,type:zi.DUPLICATE_PRODUCTIONS,ruleName:t.name,dslName:f,occurrence:u.idx},p=Ese(u);return p&&(d.parameter=p),d})}function JPe(t){return`${Bs(t)}_#_${t.idx}_#_${Ese(t)}`}function Ese(t){return t instanceof kr?t.terminalType.name:t instanceof on?t.nonTerminalName:""}function eBe(t,e,r,n){let i=[];if(Xr(e,(s,l)=>l.name===t.name?s+1:s,0)>1){let s=n.buildDuplicateRuleNameError({topLevelRule:t,grammarName:r});i.push({message:s,type:zi.DUPLICATE_RULE_NAME,ruleName:t.name})}return i}function Sse(t,e,r){let n=[],i;return qn(e,t)||(i=`Invalid rule override, rule: ->${t}<- cannot be overridden in the grammar: ->${r}<-as it is not defined in any of the super grammars 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ur(h)?[{message:e.buildEmptyAlternationError({topLevelRule:t,alternation:a,emptyChoiceIdx:u}),type:zi.NONE_LAST_EMPTY_ALT,ruleName:t.name,occurrence:a.idx,alternative:u+1}]:[]})})}function Ase(t,e,r){let n=new hx;t.accept(n);let i=n.alternations;return i=Jh(i,s=>s.ignoreAmbiguities===!0),ya(i,s=>{let l=s.idx,u=s.maxLookahead||e,h=Hg(l,t,u,s),f=rBe(h,s,t,r),d=nBe(h,s,t,r);return f.concat(d)})}function tBe(t,e){let r=new hx;t.accept(r);let n=r.alternations;return ya(n,a=>a.definition.length>255?[{message:e.buildTooManyAlternativesError({topLevelRule:t,alternation:a}),type:zi.TOO_MANY_ALTS,ruleName:t.name,occurrence:a.idx}]:[])}function _se(t,e,r){let n=[];return Ae(t,i=>{let a=new PN;i.accept(a);let s=a.allProductions;Ae(s,l=>{let u=ux(l),h=l.maxLookahead||e,f=l.idx,p=Wg(f,i,u,h)[0];if(ur(qr(p))){let m=r.buildEmptyRepetitionError({topLevelRule:i,repetition:l});n.push({message:m,type:zi.NO_NON_EMPTY_LOOKAHEAD,ruleName:i.name})}})}),n}function rBe(t,e,r,n){let i=[],a=Xr(t,(l,u,h)=>(e.definition[h].ignoreAmbiguities===!0||Ae(u,f=>{let d=[h];Ae(t,(p,m)=>{h!==m&&Vk(p,f)&&e.definition[m].ignoreAmbiguities!==!0&&d.push(m)}),d.length>1&&!Vk(i,f)&&(i.push(f),l.push({alts:d,path:f}))}),l),[]);return Je(a,l=>{let u=Je(l.alts,f=>f+1);return{message:n.buildAlternationAmbiguityError({topLevelRule:r,alternation:e,ambiguityIndices:u,prefixPath:l.path}),type:zi.AMBIGUOUS_ALTS,ruleName:r.name,occurrence:e.idx,alternatives:l.alts}})}function nBe(t,e,r,n){let i=Xr(t,(s,l,u)=>{let h=Je(l,f=>({idx:u,path:f}));return s.concat(h)},[]);return Tc(ya(i,s=>{if(e.definition[s.idx].ignoreAmbiguities===!0)return[];let u=s.idx,h=s.path,f=Yr(i,p=>e.definition[p.idx].ignoreAmbiguities!==!0&&p.idx{let m=[p.idx+1,u+1],g=e.idx===0?"":e.idx;return{message:n.buildAlternationPrefixAmbiguityError({topLevelRule:r,alternation:e,ambiguityIndices:m,prefixPath:p.path}),type:zi.AMBIGUOUS_PREFIX_ALTS,ruleName:r.name,occurrence:g,alternatives:m}})}))}function iBe(t,e,r){let n=[],i=Je(e,a=>a.name);return Ae(t,a=>{let s=a.name;if(qn(i,s)){let l=r.buildNamespaceConflictError(a);n.push({message:l,type:zi.CONFLICT_TOKENS_RULES_NAMESPACE,ruleName:s})}}),n}var ON,hx,PN,fx=N(()=>{"use strict";qt();Fs();os();qg();cx();cp();o(Tse,"validateLookahead");o(kse,"validateGrammar");o(ZPe,"validateDuplicateProductions");o(JPe,"identifyProductionForDuplicates");o(Ese,"getExtraProductionArgument");ON=class extends ss{static{o(this,"OccurrenceValidationCollector")}constructor(){super(...arguments),this.allProductions=[]}visitNonTerminal(e){this.allProductions.push(e)}visitOption(e){this.allProductions.push(e)}visitRepetitionWithSeparator(e){this.allProductions.push(e)}visitRepetitionMandatory(e){this.allProductions.push(e)}visitRepetitionMandatoryWithSeparator(e){this.allProductions.push(e)}visitRepetition(e){this.allProductions.push(e)}visitAlternation(e){this.allProductions.push(e)}visitTerminal(e){this.allProductions.push(e)}};o(eBe,"validateRuleDoesNotAlreadyExist");o(Sse,"validateRuleIsOverridden");o(BN,"validateNoLeftRecursion");o(Uk,"getFirstNoneTerminal");hx=class extends ss{static{o(this,"OrCollector")}constructor(){super(...arguments),this.alternations=[]}visitAlternation(e){this.alternations.push(e)}};o(Cse,"validateEmptyOrAlternative");o(Ase,"validateAmbiguousAlternationAlternatives");PN=class extends ss{static{o(this,"RepetitionCollector")}constructor(){super(...arguments),this.allProductions=[]}visitRepetitionWithSeparator(e){this.allProductions.push(e)}visitRepetitionMandatory(e){this.allProductions.push(e)}visitRepetitionMandatoryWithSeparator(e){this.allProductions.push(e)}visitRepetition(e){this.allProductions.push(e)}};o(tBe,"validateTooManyAlts");o(_se,"validateSomeNonEmptyLookaheadPath");o(rBe,"checkAlternativesAmbiguities");o(nBe,"checkPrefixAlternativesAmbiguities");o(iBe,"checkTerminalAndNoneTerminalsNameSpace")});function Dse(t){let e=Qh(t,{errMsgProvider:hse}),r={};return Ae(t.rules,n=>{r[n.name]=n}),fse(r,e.errMsgProvider)}function Lse(t){return t=Qh(t,{errMsgProvider:Pl}),kse(t.rules,t.tokenTypes,t.errMsgProvider,t.grammarName)}var Rse=N(()=>{"use strict";qt();dse();fx();Vg();o(Dse,"resolveGrammar");o(Lse,"validateGrammar")});function lf(t){return qn(Pse,t.name)}var Nse,Mse,Ise,Ose,Pse,Yg,hp,dx,px,mx,Xg=N(()=>{"use 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l=this.getKeyForAutomaticLookahead(n,i),u=this.firstAfterRepMap[l];if(u===void 0){let p=this.getCurrRuleFullName(),m=this.getGAstProductions()[p];u=new a(m,i).startWalking(),this.firstAfterRepMap[l]=u}let h=u.token,f=u.occurrence,d=u.isEndOfRule;this.RULE_STACK.length===1&&d&&h===void 0&&(h=lo,f=1),!(h===void 0||f===void 0)&&this.shouldInRepetitionRecoveryBeTried(h,f,s)&&this.tryInRepetitionRecovery(t,e,r,h)}var FN,zN,$N,Hk,GN=N(()=>{"use strict";up();qt();Xg();bN();Fs();FN={},zN="InRuleRecoveryException",$N=class extends Error{static{o(this,"InRuleRecoveryException")}constructor(e){super(e),this.name=zN}},Hk=class{static{o(this,"Recoverable")}initRecoverable(e){this.firstAfterRepMap={},this.resyncFollows={},this.recoveryEnabled=Bt(e,"recoveryEnabled")?e.recoveryEnabled:ls.recoveryEnabled,this.recoveryEnabled&&(this.attemptInRepetitionRecovery=aBe)}getTokenToInsert(e){let r=$u(e,"",NaN,NaN,NaN,NaN,NaN,NaN);return r.isInsertedInRecovery=!0,r}canTokenTypeBeInsertedInRecovery(e){return!0}canTokenTypeBeDeletedInRecovery(e){return!0}tryInRepetitionRecovery(e,r,n,i){let a=this.findReSyncTokenType(),s=this.exportLexerState(),l=[],u=!1,h=this.LA(1),f=this.LA(1),d=o(()=>{let p=this.LA(0),m=this.errorMessageProvider.buildMismatchTokenMessage({expected:i,actual:h,previous:p,ruleName:this.getCurrRuleFullName()}),g=new hp(m,h,this.LA(0));g.resyncedTokens=Nu(l),this.SAVE_ERROR(g)},"generateErrorMessage");for(;!u;)if(this.tokenMatcher(f,i)){d();return}else if(n.call(this)){d(),e.apply(this,r);return}else this.tokenMatcher(f,a)?u=!0:(f=this.SKIP_TOKEN(),this.addToResyncTokens(f,l));this.importLexerState(s)}shouldInRepetitionRecoveryBeTried(e,r,n){return!(n===!1||this.tokenMatcher(this.LA(1),e)||this.isBackTracking()||this.canPerformInRuleRecovery(e,this.getFollowsForInRuleRecovery(e,r)))}getFollowsForInRuleRecovery(e,r){let n=this.getCurrentGrammarPath(e,r);return this.getNextPossibleTokenTypes(n)}tryInRuleRecovery(e,r){if(this.canRecoverWithSingleTokenInsertion(e,r))return this.getTokenToInsert(e);if(this.canRecoverWithSingleTokenDeletion(e)){let n=this.SKIP_TOKEN();return this.consumeToken(),n}throw new $N("sad sad panda")}canPerformInRuleRecovery(e,r){return this.canRecoverWithSingleTokenInsertion(e,r)||this.canRecoverWithSingleTokenDeletion(e)}canRecoverWithSingleTokenInsertion(e,r){if(!this.canTokenTypeBeInsertedInRecovery(e)||ur(r))return!1;let n=this.LA(1);return ns(r,a=>this.tokenMatcher(n,a))!==void 0}canRecoverWithSingleTokenDeletion(e){return this.canTokenTypeBeDeletedInRecovery(e)?this.tokenMatcher(this.LA(2),e):!1}isInCurrentRuleReSyncSet(e){let r=this.getCurrFollowKey(),n=this.getFollowSetFromFollowKey(r);return qn(n,e)}findReSyncTokenType(){let e=this.flattenFollowSet(),r=this.LA(1),n=2;for(;;){let i=ns(e,a=>sx(r,a));if(i!==void 0)return i;r=this.LA(n),n++}}getCurrFollowKey(){if(this.RULE_STACK.length===1)return FN;let e=this.getLastExplicitRuleShortName(),r=this.getLastExplicitRuleOccurrenceIndex(),n=this.getPreviousExplicitRuleShortName();return{ruleName:this.shortRuleNameToFullName(e),idxInCallingRule:r,inRule:this.shortRuleNameToFullName(n)}}buildFullFollowKeyStack(){let e=this.RULE_STACK,r=this.RULE_OCCURRENCE_STACK;return Je(e,(n,i)=>i===0?FN:{ruleName:this.shortRuleNameToFullName(n),idxInCallingRule:r[i],inRule:this.shortRuleNameToFullName(e[i-1])})}flattenFollowSet(){let e=Je(this.buildFullFollowKeyStack(),r=>this.getFollowSetFromFollowKey(r));return qr(e)}getFollowSetFromFollowKey(e){if(e===FN)return[lo];let r=e.ruleName+e.idxInCallingRule+_k+e.inRule;return this.resyncFollows[r]}addToResyncTokens(e,r){return this.tokenMatcher(e,lo)||r.push(e),r}reSyncTo(e){let r=[],n=this.LA(1);for(;this.tokenMatcher(n,e)===!1;)n=this.SKIP_TOKEN(),this.addToResyncTokens(n,r);return Nu(r)}attemptInRepetitionRecovery(e,r,n,i,a,s,l){}getCurrentGrammarPath(e,r){let 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ss{static{o(this,"DslMethodsCollectorVisitor")}constructor(){super(...arguments),this.dslMethods={option:[],alternation:[],repetition:[],repetitionWithSeparator:[],repetitionMandatory:[],repetitionMandatoryWithSeparator:[]}}reset(){this.dslMethods={option:[],alternation:[],repetition:[],repetitionWithSeparator:[],repetitionMandatory:[],repetitionMandatoryWithSeparator:[]}}visitOption(e){this.dslMethods.option.push(e)}visitRepetitionWithSeparator(e){this.dslMethods.repetitionWithSeparator.push(e)}visitRepetitionMandatory(e){this.dslMethods.repetitionMandatory.push(e)}visitRepetitionMandatoryWithSeparator(e){this.dslMethods.repetitionMandatoryWithSeparator.push(e)}visitRepetition(e){this.dslMethods.repetition.push(e)}visitAlternation(e){this.dslMethods.alternation.push(e)}},Yk=new UN;o(sBe,"collectMethods")});function qN(t,e){isNaN(t.startOffset)===!0?(t.startOffset=e.startOffset,t.endOffset=e.endOffset):t.endOffset{"use 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if(/full/i.test(this.nodeLocationTracking))this.recoveryEnabled?(this.setNodeLocationFromToken=YN,this.setNodeLocationFromNode=YN,this.cstPostRule=ni,this.setInitialNodeLocation=this.setInitialNodeLocationFullRecovery):(this.setNodeLocationFromToken=ni,this.setNodeLocationFromNode=ni,this.cstPostRule=this.cstPostRuleFull,this.setInitialNodeLocation=this.setInitialNodeLocationFullRegular);else if(/onlyOffset/i.test(this.nodeLocationTracking))this.recoveryEnabled?(this.setNodeLocationFromToken=qN,this.setNodeLocationFromNode=qN,this.cstPostRule=ni,this.setInitialNodeLocation=this.setInitialNodeLocationOnlyOffsetRecovery):(this.setNodeLocationFromToken=ni,this.setNodeLocationFromNode=ni,this.cstPostRule=this.cstPostRuleOnlyOffset,this.setInitialNodeLocation=this.setInitialNodeLocationOnlyOffsetRegular);else if(/none/i.test(this.nodeLocationTracking))this.setNodeLocationFromToken=ni,this.setNodeLocationFromNode=ni,this.cstPostRule=ni,this.setInitialNodeLocation=ni;else throw Error(`Invalid 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r=this.LA(0),n=e.location;n.startOffset<=r.startOffset?n.endOffset=r.endOffset:n.startOffset=NaN}cstPostTerminal(e,r){let n=this.CST_STACK[this.CST_STACK.length-1];Fse(n,r,e),this.setNodeLocationFromToken(n.location,r)}cstPostNonTerminal(e,r){let n=this.CST_STACK[this.CST_STACK.length-1];$se(n,r,e),this.setNodeLocationFromNode(n.location,e.location)}getBaseCstVisitorConstructor(){if(pr(this.baseCstVisitorConstructor)){let e=Vse(this.className,zr(this.gastProductionsCache));return this.baseCstVisitorConstructor=e,e}return this.baseCstVisitorConstructor}getBaseCstVisitorConstructorWithDefaults(){if(pr(this.baseCstVisitorWithDefaultsConstructor)){let e=Use(this.className,zr(this.gastProductionsCache),this.getBaseCstVisitorConstructor());return this.baseCstVisitorWithDefaultsConstructor=e,e}return this.baseCstVisitorWithDefaultsConstructor}getLastExplicitRuleShortName(){let e=this.RULE_STACK;return e[e.length-1]}getPreviousExplicitRuleShortName(){let e=this.RULE_STACK;return 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this.subruleInternal(e,2,r)}SUBRULE3(e,r){return this.subruleInternal(e,3,r)}SUBRULE4(e,r){return this.subruleInternal(e,4,r)}SUBRULE5(e,r){return this.subruleInternal(e,5,r)}SUBRULE6(e,r){return this.subruleInternal(e,6,r)}SUBRULE7(e,r){return this.subruleInternal(e,7,r)}SUBRULE8(e,r){return this.subruleInternal(e,8,r)}SUBRULE9(e,r){return this.subruleInternal(e,9,r)}OPTION(e){return this.optionInternal(e,0)}OPTION1(e){return this.optionInternal(e,1)}OPTION2(e){return this.optionInternal(e,2)}OPTION3(e){return this.optionInternal(e,3)}OPTION4(e){return this.optionInternal(e,4)}OPTION5(e){return this.optionInternal(e,5)}OPTION6(e){return this.optionInternal(e,6)}OPTION7(e){return this.optionInternal(e,7)}OPTION8(e){return this.optionInternal(e,8)}OPTION9(e){return this.optionInternal(e,9)}OR(e){return this.orInternal(e,0)}OR1(e){return this.orInternal(e,1)}OR2(e){return this.orInternal(e,2)}OR3(e){return this.orInternal(e,3)}OR4(e){return this.orInternal(e,4)}OR5(e){return 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this.atLeastOneInternal(1,e)}AT_LEAST_ONE2(e){this.atLeastOneInternal(2,e)}AT_LEAST_ONE3(e){this.atLeastOneInternal(3,e)}AT_LEAST_ONE4(e){this.atLeastOneInternal(4,e)}AT_LEAST_ONE5(e){this.atLeastOneInternal(5,e)}AT_LEAST_ONE6(e){this.atLeastOneInternal(6,e)}AT_LEAST_ONE7(e){this.atLeastOneInternal(7,e)}AT_LEAST_ONE8(e){this.atLeastOneInternal(8,e)}AT_LEAST_ONE9(e){this.atLeastOneInternal(9,e)}AT_LEAST_ONE_SEP(e){this.atLeastOneSepFirstInternal(0,e)}AT_LEAST_ONE_SEP1(e){this.atLeastOneSepFirstInternal(1,e)}AT_LEAST_ONE_SEP2(e){this.atLeastOneSepFirstInternal(2,e)}AT_LEAST_ONE_SEP3(e){this.atLeastOneSepFirstInternal(3,e)}AT_LEAST_ONE_SEP4(e){this.atLeastOneSepFirstInternal(4,e)}AT_LEAST_ONE_SEP5(e){this.atLeastOneSepFirstInternal(5,e)}AT_LEAST_ONE_SEP6(e){this.atLeastOneSepFirstInternal(6,e)}AT_LEAST_ONE_SEP7(e){this.atLeastOneSepFirstInternal(7,e)}AT_LEAST_ONE_SEP8(e){this.atLeastOneSepFirstInternal(8,e)}AT_LEAST_ONE_SEP9(e){this.atLeastOneSepFirstInternal(9,e)}RULE(e,r,n=Kg){if(qn(this.definedRulesNames,e)){let s={message:Pl.buildDuplicateRuleNameError({topLevelRule:e,grammarName:this.className}),type:zi.DUPLICATE_RULE_NAME,ruleName:e};this.definitionErrors.push(s)}this.definedRulesNames.push(e);let i=this.defineRule(e,r,n);return this[e]=i,i}OVERRIDE_RULE(e,r,n=Kg){let i=Sse(e,this.definedRulesNames,this.className);this.definitionErrors=this.definitionErrors.concat(i);let a=this.defineRule(e,r,n);return this[e]=a,a}BACKTRACK(e,r){return function(){this.isBackTrackingStack.push(1);let n=this.saveRecogState();try{return e.apply(this,r),!0}catch(i){if(lf(i))return!1;throw i}finally{this.reloadRecogState(n),this.isBackTrackingStack.pop()}}}getGAstProductions(){return this.gastProductionsCache}getSerializedGastProductions(){return Sk(br(this.gastProductionsCache))}}});var tE,Xse=N(()=>{"use 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- For Further details.`)}if(Pt(e))this.tokensMap=Xr(e,(a,s)=>(a[s.name]=s,a),{});else if(Bt(e,"modes")&&Ma(qr(br(e.modes)),rse)){let a=qr(br(e.modes)),s=Bm(a);this.tokensMap=Xr(s,(l,u)=>(l[u.name]=u,l),{})}else if(bn(e))this.tokensMap=an(e);else throw new Error(" argument must be An Array of Token constructors, A dictionary of Token constructors or an IMultiModeLexerDefinition");this.tokensMap.EOF=lo;let n=Bt(e,"modes")?qr(br(e.modes)):br(e),i=Ma(n,a=>ur(a.categoryMatches));this.tokenMatcher=i?zg:Pu,Bu(br(this.tokensMap))}defineRule(e,r,n){if(this.selfAnalysisDone)throw Error(`Grammar rule <${e}> may not be defined after the 'performSelfAnalysis' method has been called' -Make sure that all grammar rule definitions are done before 'performSelfAnalysis' is called.`);let i=Bt(n,"resyncEnabled")?n.resyncEnabled:Kg.resyncEnabled,a=Bt(n,"recoveryValueFunc")?n.recoveryValueFunc:Kg.recoveryValueFunc,s=this.ruleShortNameIdx<<12;this.ruleShortNameIdx++,this.shortRuleNameToFull[s]=e,this.fullRuleNameToShort[e]=s;let l;return this.outputCst===!0?l=o(function(...f){try{this.ruleInvocationStateUpdate(s,e,this.subruleIdx),r.apply(this,f);let d=this.CST_STACK[this.CST_STACK.length-1];return this.cstPostRule(d),d}catch(d){return this.invokeRuleCatch(d,i,a)}finally{this.ruleFinallyStateUpdate()}},"invokeRuleWithTry"):l=o(function(...f){try{return this.ruleInvocationStateUpdate(s,e,this.subruleIdx),r.apply(this,f)}catch(d){return this.invokeRuleCatch(d,i,a)}finally{this.ruleFinallyStateUpdate()}},"invokeRuleWithTryCst"),Object.assign(l,{ruleName:e,originalGrammarAction:r})}invokeRuleCatch(e,r,n){let i=this.RULE_STACK.length===1,a=r&&!this.isBackTracking()&&this.recoveryEnabled;if(lf(e)){let s=e;if(a){let l=this.findReSyncTokenType();if(this.isInCurrentRuleReSyncSet(l))if(s.resyncedTokens=this.reSyncTo(l),this.outputCst){let u=this.CST_STACK[this.CST_STACK.length-1];return u.recoveredNode=!0,u}else return n(e);else{if(this.outputCst){let u=this.CST_STACK[this.CST_STACK.length-1];u.recoveredNode=!0,s.partialCstResult=u}throw s}}else{if(i)return this.moveToTerminatedState(),n(e);throw s}}else throw e}optionInternal(e,r){let n=this.getKeyForAutomaticLookahead(512,r);return this.optionInternalLogic(e,r,n)}optionInternalLogic(e,r,n){let i=this.getLaFuncFromCache(n),a;if(typeof e!="function"){a=e.DEF;let s=e.GATE;if(s!==void 0){let l=i;i=o(()=>s.call(this)&&l.call(this),"lookAheadFunc")}}else a=e;if(i.call(this)===!0)return a.call(this)}atLeastOneInternal(e,r){let n=this.getKeyForAutomaticLookahead(1024,e);return this.atLeastOneInternalLogic(e,r,n)}atLeastOneInternalLogic(e,r,n){let i=this.getLaFuncFromCache(n),a;if(typeof r!="function"){a=r.DEF;let s=r.GATE;if(s!==void 0){let l=i;i=o(()=>s.call(this)&&l.call(this),"lookAheadFunc")}}else a=r;if(i.call(this)===!0){let s=this.doSingleRepetition(a);for(;i.call(this)===!0&&s===!0;)s=this.doSingleRepetition(a)}else throw this.raiseEarlyExitException(e,jn.REPETITION_MANDATORY,r.ERR_MSG);this.attemptInRepetitionRecovery(this.atLeastOneInternal,[e,r],i,1024,e,Bk)}atLeastOneSepFirstInternal(e,r){let n=this.getKeyForAutomaticLookahead(1536,e);this.atLeastOneSepFirstInternalLogic(e,r,n)}atLeastOneSepFirstInternalLogic(e,r,n){let i=r.DEF,a=r.SEP;if(this.getLaFuncFromCache(n).call(this)===!0){i.call(this);let l=o(()=>this.tokenMatcher(this.LA(1),a),"separatorLookAheadFunc");for(;this.tokenMatcher(this.LA(1),a)===!0;)this.CONSUME(a),i.call(this);this.attemptInRepetitionRecovery(this.repetitionSepSecondInternal,[e,a,l,i,lx],l,1536,e,lx)}else throw this.raiseEarlyExitException(e,jn.REPETITION_MANDATORY_WITH_SEPARATOR,r.ERR_MSG)}manyInternal(e,r){let n=this.getKeyForAutomaticLookahead(768,e);return this.manyInternalLogic(e,r,n)}manyInternalLogic(e,r,n){let i=this.getLaFuncFromCache(n),a;if(typeof r!="function"){a=r.DEF;let l=r.GATE;if(l!==void 0){let u=i;i=o(()=>l.call(this)&&u.call(this),"lookaheadFunction")}}else a=r;let s=!0;for(;i.call(this)===!0&&s===!0;)s=this.doSingleRepetition(a);this.attemptInRepetitionRecovery(this.manyInternal,[e,r],i,768,e,Pk,s)}manySepFirstInternal(e,r){let n=this.getKeyForAutomaticLookahead(1280,e);this.manySepFirstInternalLogic(e,r,n)}manySepFirstInternalLogic(e,r,n){let i=r.DEF,a=r.SEP;if(this.getLaFuncFromCache(n).call(this)===!0){i.call(this);let l=o(()=>this.tokenMatcher(this.LA(1),a),"separatorLookAheadFunc");for(;this.tokenMatcher(this.LA(1),a)===!0;)this.CONSUME(a),i.call(this);this.attemptInRepetitionRecovery(this.repetitionSepSecondInternal,[e,a,l,i,ox],l,1280,e,ox)}}repetitionSepSecondInternal(e,r,n,i,a){for(;n();)this.CONSUME(r),i.call(this);this.attemptInRepetitionRecovery(this.repetitionSepSecondInternal,[e,r,n,i,a],n,1536,e,a)}doSingleRepetition(e){let r=this.getLexerPosition();return e.call(this),this.getLexerPosition()>r}orInternal(e,r){let n=this.getKeyForAutomaticLookahead(256,r),i=Pt(e)?e:e.DEF,s=this.getLaFuncFromCache(n).call(this,i);if(s!==void 0)return i[s].ALT.call(this);this.raiseNoAltException(r,e.ERR_MSG)}ruleFinallyStateUpdate(){if(this.RULE_STACK.pop(),this.RULE_OCCURRENCE_STACK.pop(),this.cstFinallyStateUpdate(),this.RULE_STACK.length===0&&this.isAtEndOfInput()===!1){let e=this.LA(1),r=this.errorMessageProvider.buildNotAllInputParsedMessage({firstRedundant:e,ruleName:this.getCurrRuleFullName()});this.SAVE_ERROR(new px(r,e))}}subruleInternal(e,r,n){let i;try{let a=n!==void 0?n.ARGS:void 0;return this.subruleIdx=r,i=e.apply(this,a),this.cstPostNonTerminal(i,n!==void 0&&n.LABEL!==void 0?n.LABEL:e.ruleName),i}catch(a){throw this.subruleInternalError(a,n,e.ruleName)}}subruleInternalError(e,r,n){throw lf(e)&&e.partialCstResult!==void 0&&(this.cstPostNonTerminal(e.partialCstResult,r!==void 0&&r.LABEL!==void 0?r.LABEL:n),delete e.partialCstResult),e}consumeInternal(e,r,n){let i;try{let a=this.LA(1);this.tokenMatcher(a,e)===!0?(this.consumeToken(),i=a):this.consumeInternalError(e,a,n)}catch(a){i=this.consumeInternalRecovery(e,r,a)}return this.cstPostTerminal(n!==void 0&&n.LABEL!==void 0?n.LABEL:e.name,i),i}consumeInternalError(e,r,n){let i,a=this.LA(0);throw n!==void 0&&n.ERR_MSG?i=n.ERR_MSG:i=this.errorMessageProvider.buildMismatchTokenMessage({expected:e,actual:r,previous:a,ruleName:this.getCurrRuleFullName()}),this.SAVE_ERROR(new hp(i,r,a))}consumeInternalRecovery(e,r,n){if(this.recoveryEnabled&&n.name==="MismatchedTokenException"&&!this.isBackTracking()){let i=this.getFollowsForInRuleRecovery(e,r);try{return this.tryInRuleRecovery(e,i)}catch(a){throw a.name===zN?n:a}}else throw n}saveRecogState(){let e=this.errors,r=an(this.RULE_STACK);return{errors:e,lexerState:this.exportLexerState(),RULE_STACK:r,CST_STACK:this.CST_STACK}}reloadRecogState(e){this.errors=e.errors,this.importLexerState(e.lexerState),this.RULE_STACK=e.RULE_STACK}ruleInvocationStateUpdate(e,r,n){this.RULE_OCCURRENCE_STACK.push(n),this.RULE_STACK.push(e),this.cstInvocationStateUpdate(r)}isBackTracking(){return this.isBackTrackingStack.length!==0}getCurrRuleFullName(){let e=this.getLastExplicitRuleShortName();return this.shortRuleNameToFull[e]}shortRuleNameToFullName(e){return this.shortRuleNameToFull[e]}isAtEndOfInput(){return this.tokenMatcher(this.LA(1),lo)}reset(){this.resetLexerState(),this.subruleIdx=0,this.isBackTrackingStack=[],this.errors=[],this.RULE_STACK=[],this.CST_STACK=[],this.RULE_OCCURRENCE_STACK=[]}}});var rE,jse=N(()=>{"use strict";Xg();qt();qg();Fs();rE=class{static{o(this,"ErrorHandler")}initErrorHandler(e){this._errors=[],this.errorMessageProvider=Bt(e,"errorMessageProvider")?e.errorMessageProvider:ls.errorMessageProvider}SAVE_ERROR(e){if(lf(e))return e.context={ruleStack:this.getHumanReadableRuleStack(),ruleOccurrenceStack:an(this.RULE_OCCURRENCE_STACK)},this._errors.push(e),e;throw Error("Trying to save an Error which is not a RecognitionException")}get errors(){return an(this._errors)}set errors(e){this._errors=e}raiseEarlyExitException(e,r,n){let i=this.getCurrRuleFullName(),a=this.getGAstProductions()[i],l=Wg(e,a,r,this.maxLookahead)[0],u=[];for(let f=1;f<=this.maxLookahead;f++)u.push(this.LA(f));let h=this.errorMessageProvider.buildEarlyExitMessage({expectedIterationPaths:l,actual:u,previous:this.LA(0),customUserDescription:n,ruleName:i});throw this.SAVE_ERROR(new mx(h,this.LA(1),this.LA(0)))}raiseNoAltException(e,r){let n=this.getCurrRuleFullName(),i=this.getGAstProductions()[n],a=Hg(e,i,this.maxLookahead),s=[];for(let h=1;h<=this.maxLookahead;h++)s.push(this.LA(h));let l=this.LA(0),u=this.errorMessageProvider.buildNoViableAltMessage({expectedPathsPerAlt:a,actual:s,previous:l,customUserDescription:r,ruleName:this.getCurrRuleFullName()});throw this.SAVE_ERROR(new dx(u,this.LA(1),l))}}});var nE,Kse=N(()=>{"use strict";cx();qt();nE=class{static{o(this,"ContentAssist")}initContentAssist(){}computeContentAssist(e,r){let n=this.gastProductionsCache[e];if(pr(n))throw Error(`Rule ->${e}<- does not exist in this grammar.`);return $k([n],r,this.tokenMatcher,this.maxLookahead)}getNextPossibleTokenTypes(e){let r=ia(e.ruleStack),i=this.getGAstProductions()[r];return new Ok(i,e).startWalking()}}});function yx(t,e,r,n=!1){aE(r);let i=ga(this.recordingProdStack),a=Si(e)?e:e.DEF,s=new t({definition:[],idx:r});return n&&(s.separator=e.SEP),Bt(e,"MAX_LOOKAHEAD")&&(s.maxLookahead=e.MAX_LOOKAHEAD),this.recordingProdStack.push(s),a.call(this),i.definition.push(s),this.recordingProdStack.pop(),sE}function dBe(t,e){aE(e);let r=ga(this.recordingProdStack),n=Pt(t)===!1,i=n===!1?t:t.DEF,a=new Tn({definition:[],idx:e,ignoreAmbiguities:n&&t.IGNORE_AMBIGUITIES===!0});Bt(t,"MAX_LOOKAHEAD")&&(a.maxLookahead=t.MAX_LOOKAHEAD);let s=A2(i,l=>Si(l.GATE));return a.hasPredicates=s,r.definition.push(a),Ae(i,l=>{let u=new Dn({definition:[]});a.definition.push(u),Bt(l,"IGNORE_AMBIGUITIES")?u.ignoreAmbiguities=l.IGNORE_AMBIGUITIES:Bt(l,"GATE")&&(u.ignoreAmbiguities=!0),this.recordingProdStack.push(u),l.ALT.call(this),this.recordingProdStack.pop()}),sE}function Jse(t){return t===0?"":`${t}`}function aE(t){if(t<0||t>Zse){let e=new Error(`Invalid DSL Method idx value: <${t}> - Idx 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You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). -`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(q){this.unput(this.match.slice(q))},"less"),pastInput:o(function(){var q=this.matched.substr(0,this.matched.length-this.match.length);return(q.length>20?"...":"")+q.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var q=this.match;return q.length<20&&(q+=this._input.substr(0,20-q.length)),(q.substr(0,20)+(q.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var q=this.pastInput(),pe=new Array(q.length+1).join("-");return q+this.upcomingInput()+` -`+pe+"^"},"showPosition"),test_match:o(function(q,pe){var ve,Pe,_e;if(this.options.backtrack_lexer&&(_e={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(_e.yylloc.range=this.yylloc.range.slice(0))),Pe=q[0].match(/(?:\r\n?|\n).*/g),Pe&&(this.yylineno+=Pe.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:Pe?Pe[Pe.length-1].length-Pe[Pe.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+q[0].length},this.yytext+=q[0],this.match+=q[0],this.matches=q,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(q[0].length),this.matched+=q[0],ve=this.performAction.call(this,this.yy,this,pe,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),ve)return ve;if(this._backtrack){for(var we in _e)this[we]=_e[we];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var q,pe,ve,Pe;this._more||(this.yytext="",this.match="");for(var _e=this._currentRules(),we=0;we<_e.length;we++)if(ve=this._input.match(this.rules[_e[we]]),ve&&(!pe||ve[0].length>pe[0].length)){if(pe=ve,Pe=we,this.options.backtrack_lexer){if(q=this.test_match(ve,_e[we]),q!==!1)return q;if(this._backtrack){pe=!1;continue}else return!1}else if(!this.options.flex)break}return pe?(q=this.test_match(pe,_e[Pe]),q!==!1?q:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. -`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var pe=this.next();return pe||this.lex()},"lex"),begin:o(function(pe){this.conditionStack.push(pe)},"begin"),popState:o(function(){var pe=this.conditionStack.length-1;return pe>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(pe){return pe=this.conditionStack.length-1-Math.abs(pe||0),pe>=0?this.conditionStack[pe]:"INITIAL"},"topState"),pushState:o(function(pe){this.begin(pe)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{"case-insensitive":!0},performAction:o(function(pe,ve,Pe,_e){var we=_e;switch(Pe){case 0:break;case 1:break;case 2:return 55;case 3:break;case 4:return this.begin("title"),35;break;case 5:return this.popState(),"title_value";break;case 6:return this.begin("acc_title"),37;break;case 7:return this.popState(),"acc_title_value";break;case 8:return this.begin("acc_descr"),39;break;case 9:return this.popState(),"acc_descr_value";break;case 10:this.begin("acc_descr_multiline");break;case 11:this.popState();break;case 12:return"acc_descr_multiline_value";case 13:return 48;case 14:return 50;case 15:return 49;case 16:return 51;case 17:return 52;case 18:return 53;case 19:return 54;case 20:return 25;case 21:this.begin("md_string");break;case 22:return"MD_STR";case 23:this.popState();break;case 24:this.begin("string");break;case 25:this.popState();break;case 26:return"STR";case 27:this.begin("class_name");break;case 28:return this.popState(),47;break;case 29:return this.begin("point_start"),44;break;case 30:return this.begin("point_x"),45;break;case 31:this.popState();break;case 32:this.popState(),this.begin("point_y");break;case 33:return this.popState(),46;break;case 34:return 28;case 35:return 4;case 36:return 11;case 37:return 64;case 38:return 10;case 39:return 65;case 40:return 65;case 41:return 14;case 42:return 13;case 43:return 67;case 44:return 66;case 45:return 12;case 46:return 8;case 47:return 5;case 48:return 18;case 49:return 56;case 50:return 63;case 51:return 57}},"anonymous"),rules:[/^(?:%%(?!\{)[^\n]*)/i,/^(?:[^\}]%%[^\n]*)/i,/^(?:[\n\r]+)/i,/^(?:%%[^\n]*)/i,/^(?:title\b)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accTitle\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*\{\s*)/i,/^(?:[\}])/i,/^(?:[^\}]*)/i,/^(?: *x-axis *)/i,/^(?: *y-axis *)/i,/^(?: *--+> *)/i,/^(?: *quadrant-1 *)/i,/^(?: *quadrant-2 *)/i,/^(?: *quadrant-3 *)/i,/^(?: *quadrant-4 *)/i,/^(?:classDef\b)/i,/^(?:["][`])/i,/^(?:[^`"]+)/i,/^(?:[`]["])/i,/^(?:["])/i,/^(?:["])/i,/^(?:[^"]*)/i,/^(?::::)/i,/^(?:^\w+)/i,/^(?:\s*:\s*\[\s*)/i,/^(?:(1)|(0(.\d+)?))/i,/^(?:\s*\] *)/i,/^(?:\s*,\s*)/i,/^(?:(1)|(0(.\d+)?))/i,/^(?: *quadrantChart *)/i,/^(?:[A-Za-z]+)/i,/^(?::)/i,/^(?:\+)/i,/^(?:,)/i,/^(?:=)/i,/^(?:=)/i,/^(?:\*)/i,/^(?:#)/i,/^(?:[\_])/i,/^(?:\.)/i,/^(?:&)/i,/^(?:-)/i,/^(?:[0-9]+)/i,/^(?:\s)/i,/^(?:;)/i,/^(?:[!"#$%&'*+,-.`?\\_/])/i,/^(?:$)/i],conditions:{class_name:{rules:[28],inclusive:!1},point_y:{rules:[33],inclusive:!1},point_x:{rules:[32],inclusive:!1},point_start:{rules:[30,31],inclusive:!1},acc_descr_multiline:{rules:[11,12],inclusive:!1},acc_descr:{rules:[9],inclusive:!1},acc_title:{rules:[7],inclusive:!1},title:{rules:[5],inclusive:!1},md_string:{rules:[22,23],inclusive:!1},string:{rules:[25,26],inclusive:!1},INITIAL:{rules:[0,1,2,3,4,6,8,10,13,14,15,16,17,18,19,20,21,24,27,29,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51],inclusive:!0}}};return xe}();re.lexer=oe;function V(){this.yy={}}return o(V,"Parser"),V.prototype=re,re.Parser=V,new V}();hO.parser=hO;uhe=hO});var ms,y6,fhe=N(()=>{"use strict";dr();Ya();vt();_y();ms=oh(),y6=class{constructor(){this.classes=new Map;this.config=this.getDefaultConfig(),this.themeConfig=this.getDefaultThemeConfig(),this.data=this.getDefaultData()}static{o(this,"QuadrantBuilder")}getDefaultData(){return{titleText:"",quadrant1Text:"",quadrant2Text:"",quadrant3Text:"",quadrant4Text:"",xAxisLeftText:"",xAxisRightText:"",yAxisBottomText:"",yAxisTopText:"",points:[]}}getDefaultConfig(){return{showXAxis:!0,showYAxis:!0,showTitle:!0,chartHeight:or.quadrantChart?.chartWidth||500,chartWidth:or.quadrantChart?.chartHeight||500,titlePadding:or.quadrantChart?.titlePadding||10,titleFontSize:or.quadrantChart?.titleFontSize||20,quadrantPadding:or.quadrantChart?.quadrantPadding||5,xAxisLabelPadding:or.quadrantChart?.xAxisLabelPadding||5,yAxisLabelPadding:or.quadrantChart?.yAxisLabelPadding||5,xAxisLabelFontSize:or.quadrantChart?.xAxisLabelFontSize||16,yAxisLabelFontSize:or.quadrantChart?.yAxisLabelFontSize||16,quadrantLabelFontSize:or.quadrantChart?.quadrantLabelFontSize||16,quadrantTextTopPadding:or.quadrantChart?.quadrantTextTopPadding||5,pointTextPadding:or.quadrantChart?.pointTextPadding||5,pointLabelFontSize:or.quadrantChart?.pointLabelFontSize||12,pointRadius:or.quadrantChart?.pointRadius||5,xAxisPosition:or.quadrantChart?.xAxisPosition||"top",yAxisPosition:or.quadrantChart?.yAxisPosition||"left",quadrantInternalBorderStrokeWidth:or.quadrantChart?.quadrantInternalBorderStrokeWidth||1,quadrantExternalBorderStrokeWidth:or.quadrantChart?.quadrantExternalBorderStrokeWidth||2}}getDefaultThemeConfig(){return{quadrant1Fill:ms.quadrant1Fill,quadrant2Fill:ms.quadrant2Fill,quadrant3Fill:ms.quadrant3Fill,quadrant4Fill:ms.quadrant4Fill,quadrant1TextFill:ms.quadrant1TextFill,quadrant2TextFill:ms.quadrant2TextFill,quadrant3TextFill:ms.quadrant3TextFill,quadrant4TextFill:ms.quadrant4TextFill,quadrantPointFill:ms.quadrantPointFill,quadrantPointTextFill:ms.quadrantPointTextFill,quadrantXAxisTextFill:ms.quadrantXAxisTextFill,quadrantYAxisTextFill:ms.quadrantYAxisTextFill,quadrantTitleFill:ms.quadrantTitleFill,quadrantInternalBorderStrokeFill:ms.quadrantInternalBorderStrokeFill,quadrantExternalBorderStrokeFill:ms.quadrantExternalBorderStrokeFill}}clear(){this.config=this.getDefaultConfig(),this.themeConfig=this.getDefaultThemeConfig(),this.data=this.getDefaultData(),this.classes=new Map,Y.info("clear called")}setData(e){this.data={...this.data,...e}}addPoints(e){this.data.points=[...e,...this.data.points]}addClass(e,r){this.classes.set(e,r)}setConfig(e){Y.trace("setConfig called with: ",e),this.config={...this.config,...e}}setThemeConfig(e){Y.trace("setThemeConfig called with: ",e),this.themeConfig={...this.themeConfig,...e}}calculateSpace(e,r,n,i){let a=this.config.xAxisLabelPadding*2+this.config.xAxisLabelFontSize,s={top:e==="top"&&r?a:0,bottom:e==="bottom"&&r?a:0},l=this.config.yAxisLabelPadding*2+this.config.yAxisLabelFontSize,u={left:this.config.yAxisPosition==="left"&&n?l:0,right:this.config.yAxisPosition==="right"&&n?l:0},h=this.config.titleFontSize+this.config.titlePadding*2,f={top:i?h:0},d=this.config.quadrantPadding+u.left,p=this.config.quadrantPadding+s.top+f.top,m=this.config.chartWidth-this.config.quadrantPadding*2-u.left-u.right,g=this.config.chartHeight-this.config.quadrantPadding*2-s.top-s.bottom-f.top,y=m/2,v=g/2;return{xAxisSpace:s,yAxisSpace:u,titleSpace:f,quadrantSpace:{quadrantLeft:d,quadrantTop:p,quadrantWidth:m,quadrantHalfWidth:y,quadrantHeight:g,quadrantHalfHeight:v}}}getAxisLabels(e,r,n,i){let{quadrantSpace:a,titleSpace:s}=i,{quadrantHalfHeight:l,quadrantHeight:u,quadrantLeft:h,quadrantHalfWidth:f,quadrantTop:d,quadrantWidth:p}=a,m=!!this.data.xAxisRightText,g=!!this.data.yAxisTopText,y=[];return this.data.xAxisLeftText&&r&&y.push({text:this.data.xAxisLeftText,fill:this.themeConfig.quadrantXAxisTextFill,x:h+(m?f/2:0),y:e==="top"?this.config.xAxisLabelPadding+s.top:this.config.xAxisLabelPadding+d+u+this.config.quadrantPadding,fontSize:this.config.xAxisLabelFontSize,verticalPos:m?"center":"left",horizontalPos:"top",rotation:0}),this.data.xAxisRightText&&r&&y.push({text:this.data.xAxisRightText,fill:this.themeConfig.quadrantXAxisTextFill,x:h+f+(m?f/2:0),y:e==="top"?this.config.xAxisLabelPadding+s.top:this.config.xAxisLabelPadding+d+u+this.config.quadrantPadding,fontSize:this.config.xAxisLabelFontSize,verticalPos:m?"center":"left",horizontalPos:"top",rotation:0}),this.data.yAxisBottomText&&n&&y.push({text:this.data.yAxisBottomText,fill:this.themeConfig.quadrantYAxisTextFill,x:this.config.yAxisPosition==="left"?this.config.yAxisLabelPadding:this.config.yAxisLabelPadding+h+p+this.config.quadrantPadding,y:d+u-(g?l/2:0),fontSize:this.config.yAxisLabelFontSize,verticalPos:g?"center":"left",horizontalPos:"top",rotation:-90}),this.data.yAxisTopText&&n&&y.push({text:this.data.yAxisTopText,fill:this.themeConfig.quadrantYAxisTextFill,x:this.config.yAxisPosition==="left"?this.config.yAxisLabelPadding:this.config.yAxisLabelPadding+h+p+this.config.quadrantPadding,y:d+l-(g?l/2:0),fontSize:this.config.yAxisLabelFontSize,verticalPos:g?"center":"left",horizontalPos:"top",rotation:-90}),y}getQuadrants(e){let{quadrantSpace:r}=e,{quadrantHalfHeight:n,quadrantLeft:i,quadrantHalfWidth:a,quadrantTop:s}=r,l=[{text:{text:this.data.quadrant1Text,fill:this.themeConfig.quadrant1TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i+a,y:s,width:a,height:n,fill:this.themeConfig.quadrant1Fill},{text:{text:this.data.quadrant2Text,fill:this.themeConfig.quadrant2TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i,y:s,width:a,height:n,fill:this.themeConfig.quadrant2Fill},{text:{text:this.data.quadrant3Text,fill:this.themeConfig.quadrant3TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i,y:s+n,width:a,height:n,fill:this.themeConfig.quadrant3Fill},{text:{text:this.data.quadrant4Text,fill:this.themeConfig.quadrant4TextFill,x:0,y:0,fontSize:this.config.quadrantLabelFontSize,verticalPos:"center",horizontalPos:"middle",rotation:0},x:i+a,y:s+n,width:a,height:n,fill:this.themeConfig.quadrant4Fill}];for(let u of l)u.text.x=u.x+u.width/2,this.data.points.length===0?(u.text.y=u.y+u.height/2,u.text.horizontalPos="middle"):(u.text.y=u.y+this.config.quadrantTextTopPadding,u.text.horizontalPos="top");return l}getQuadrantPoints(e){let{quadrantSpace:r}=e,{quadrantHeight:n,quadrantLeft:i,quadrantTop:a,quadrantWidth:s}=r,l=gl().domain([0,1]).range([i,s+i]),u=gl().domain([0,1]).range([n+a,a]);return this.data.points.map(f=>{let d=this.classes.get(f.className);return d&&(f={...d,...f}),{x:l(f.x),y:u(f.y),fill:f.color??this.themeConfig.quadrantPointFill,radius:f.radius??this.config.pointRadius,text:{text:f.text,fill:this.themeConfig.quadrantPointTextFill,x:l(f.x),y:u(f.y)+this.config.pointTextPadding,verticalPos:"center",horizontalPos:"top",fontSize:this.config.pointLabelFontSize,rotation:0},strokeColor:f.strokeColor??this.themeConfig.quadrantPointFill,strokeWidth:f.strokeWidth??"0px"}})}getBorders(e){let r=this.config.quadrantExternalBorderStrokeWidth/2,{quadrantSpace:n}=e,{quadrantHalfHeight:i,quadrantHeight:a,quadrantLeft:s,quadrantHalfWidth:l,quadrantTop:u,quadrantWidth:h}=n;return[{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s-r,y1:u,x2:s+h+r,y2:u},{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s+h,y1:u+r,x2:s+h,y2:u+a-r},{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s-r,y1:u+a,x2:s+h+r,y2:u+a},{strokeFill:this.themeConfig.quadrantExternalBorderStrokeFill,strokeWidth:this.config.quadrantExternalBorderStrokeWidth,x1:s,y1:u+r,x2:s,y2:u+a-r},{strokeFill:this.themeConfig.quadrantInternalBorderStrokeFill,strokeWidth:this.config.quadrantInternalBorderStrokeWidth,x1:s+l,y1:u+r,x2:s+l,y2:u+a-r},{strokeFill:this.themeConfig.quadrantInternalBorderStrokeFill,strokeWidth:this.config.quadrantInternalBorderStrokeWidth,x1:s+r,y1:u+i,x2:s+h-r,y2:u+i}]}getTitle(e){if(e)return{text:this.data.titleText,fill:this.themeConfig.quadrantTitleFill,fontSize:this.config.titleFontSize,horizontalPos:"top",verticalPos:"center",rotation:0,y:this.config.titlePadding,x:this.config.chartWidth/2}}build(){let e=this.config.showXAxis&&!!(this.data.xAxisLeftText||this.data.xAxisRightText),r=this.config.showYAxis&&!!(this.data.yAxisTopText||this.data.yAxisBottomText),n=this.config.showTitle&&!!this.data.titleText,i=this.data.points.length>0?"bottom":this.config.xAxisPosition,a=this.calculateSpace(i,e,r,n);return{points:this.getQuadrantPoints(a),quadrants:this.getQuadrants(a),axisLabels:this.getAxisLabels(i,e,r,a),borderLines:this.getBorders(a),title:this.getTitle(n)}}}});function fO(t){return!/^#?([\dA-Fa-f]{6}|[\dA-Fa-f]{3})$/.test(t)}function dhe(t){return!/^\d+$/.test(t)}function phe(t){return!/^\d+px$/.test(t)}var Ap,mhe=N(()=>{"use strict";Ap=class extends Error{static{o(this,"InvalidStyleError")}constructor(e,r,n){super(`value for ${e} ${r} is invalid, please use a valid ${n}`),this.name="InvalidStyleError"}};o(fO,"validateHexCode");o(dhe,"validateNumber");o(phe,"validateSizeInPixels")});function Xu(t){return Tr(t.trim(),pGe)}function mGe(t){ba.setData({quadrant1Text:Xu(t.text)})}function gGe(t){ba.setData({quadrant2Text:Xu(t.text)})}function yGe(t){ba.setData({quadrant3Text:Xu(t.text)})}function vGe(t){ba.setData({quadrant4Text:Xu(t.text)})}function xGe(t){ba.setData({xAxisLeftText:Xu(t.text)})}function bGe(t){ba.setData({xAxisRightText:Xu(t.text)})}function wGe(t){ba.setData({yAxisTopText:Xu(t.text)})}function TGe(t){ba.setData({yAxisBottomText:Xu(t.text)})}function dO(t){let e={};for(let r of t){let[n,i]=r.trim().split(/\s*:\s*/);if(n==="radius"){if(dhe(i))throw new Ap(n,i,"number");e.radius=parseInt(i)}else if(n==="color"){if(fO(i))throw new Ap(n,i,"hex code");e.color=i}else if(n==="stroke-color"){if(fO(i))throw new Ap(n,i,"hex code");e.strokeColor=i}else if(n==="stroke-width"){if(phe(i))throw new Ap(n,i,"number of pixels (eg. 10px)");e.strokeWidth=i}else throw new Error(`style named ${n} is not supported.`)}return e}function kGe(t,e,r,n,i){let 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this.textDimensionCalculator.getMaxDimension(this.getTickValues().map(e=>e.toString()),this.axisConfig.labelFontSize)}recalculateOuterPaddingToDrawBar(){.7*this.getTickDistance()>this.outerPadding*2&&(this.outerPadding=Math.floor(.7*this.getTickDistance()/2)),this.recalculateScale()}calculateSpaceIfDrawnHorizontally(e){let r=e.height;if(this.axisConfig.showAxisLine&&r>this.axisConfig.axisLineWidth&&(r-=this.axisConfig.axisLineWidth,this.showAxisLine=!0),this.axisConfig.showLabel){let n=this.getLabelDimension(),i=.2*e.width;this.outerPadding=Math.min(n.width/2,i);let a=n.height+this.axisConfig.labelPadding*2;this.labelTextHeight=n.height,a<=r&&(r-=a,this.showLabel=!0)}if(this.axisConfig.showTick&&r>=this.axisConfig.tickLength&&(this.showTick=!0,r-=this.axisConfig.tickLength),this.axisConfig.showTitle&&this.title){let n=this.textDimensionCalculator.getMaxDimension([this.title],this.axisConfig.titleFontSize),i=n.height+this.axisConfig.titlePadding*2;this.titleTextHeight=n.height,i<=r&&(r-=i,this.showTitle=!0)}this.boundingRect.width=e.width,this.boundingRect.height=e.height-r}calculateSpaceIfDrawnVertical(e){let r=e.width;if(this.axisConfig.showAxisLine&&r>this.axisConfig.axisLineWidth&&(r-=this.axisConfig.axisLineWidth,this.showAxisLine=!0),this.axisConfig.showLabel){let n=this.getLabelDimension(),i=.2*e.height;this.outerPadding=Math.min(n.height/2,i);let a=n.width+this.axisConfig.labelPadding*2;a<=r&&(r-=a,this.showLabel=!0)}if(this.axisConfig.showTick&&r>=this.axisConfig.tickLength&&(this.showTick=!0,r-=this.axisConfig.tickLength),this.axisConfig.showTitle&&this.title){let n=this.textDimensionCalculator.getMaxDimension([this.title],this.axisConfig.titleFontSize),i=n.height+this.axisConfig.titlePadding*2;this.titleTextHeight=n.height,i<=r&&(r-=i,this.showTitle=!0)}this.boundingRect.width=e.width-r,this.boundingRect.height=e.height}calculateSpace(e){return this.axisPosition==="left"||this.axisPosition==="right"?this.calculateSpaceIfDrawnVertical(e):this.calculateSpaceIfDrawnHorizontally(e),this.recalculateScale(),{width:this.boundingRect.width,height:this.boundingRect.height}}setBoundingBoxXY(e){this.boundingRect.x=e.x,this.boundingRect.y=e.y}getDrawableElementsForLeftAxis(){let e=[];if(this.showAxisLine){let r=this.boundingRect.x+this.boundingRect.width-this.axisConfig.axisLineWidth/2;e.push({type:"path",groupTexts:["left-axis","axisl-line"],data:[{path:`M ${r},${this.boundingRect.y} L ${r},${this.boundingRect.y+this.boundingRect.height} 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this.showTitle&&e.push({type:"text",groupTexts:["left-axis","title"],data:[{text:this.title,x:this.boundingRect.x+this.axisConfig.titlePadding,y:this.boundingRect.y+this.boundingRect.height/2,fill:this.axisThemeConfig.titleColor,fontSize:this.axisConfig.titleFontSize,rotation:270,verticalPos:"top",horizontalPos:"center"}]}),e}getDrawableElementsForBottomAxis(){let e=[];if(this.showAxisLine){let r=this.boundingRect.y+this.axisConfig.axisLineWidth/2;e.push({type:"path",groupTexts:["bottom-axis","axis-line"],data:[{path:`M ${this.boundingRect.x},${r} L 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this.showTitle&&e.push({type:"text",groupTexts:["bottom-axis","title"],data:[{text:this.title,x:this.range[0]+(this.range[1]-this.range[0])/2,y:this.boundingRect.y+this.boundingRect.height-this.axisConfig.titlePadding-this.titleTextHeight,fill:this.axisThemeConfig.titleColor,fontSize:this.axisConfig.titleFontSize,rotation:0,verticalPos:"top",horizontalPos:"center"}]}),e}getDrawableElementsForTopAxis(){let e=[];if(this.showAxisLine){let r=this.boundingRect.y+this.boundingRect.height-this.axisConfig.axisLineWidth/2;e.push({type:"path",groupTexts:["top-axis","axis-line"],data:[{path:`M ${this.boundingRect.x},${r} L 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68:this.$=ve[_e-1]+ve[_e];break}},"anonymous"),table:[{3:1,4:2,6:e,9:r,11:n,13:i},{1:[3]},{3:8,4:2,5:[1,7],6:e,9:r,11:n,13:i},{5:[1,9]},{10:[1,10]},{12:[1,11]},t(a,[2,6]),{3:12,4:2,6:e,9:r,11:n,13:i},{1:[2,2]},{4:17,5:s,7:13,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},t(a,[2,4]),t(a,[2,5]),{1:[2,1]},{8:[1,41]},{4:17,5:s,7:42,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:43,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:44,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:45,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:46,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:47,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:48,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:49,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{4:17,5:s,7:50,8:l,9:r,11:n,13:i,14:14,15:15,16:16,17:18,18:19,19:20,20:21,21:u,22:h,23:f,24:d,25:23,33:25,41:p,42:m,43:g,44:y,45:v,46:x,54:b,72:w,74:C,77:T,89:E,90:A},{26:51,89:[1,52],90:[1,53]},{55:54,89:[1,55],90:[1,56]},{29:[1,59],61:[1,57],63:[1,58]},t(S,[2,17]),t(S,[2,18]),t(S,[2,19]),t(S,[2,20]),{30:60,33:62,75:_,89:E,90:A},{30:63,33:62,75:_,89:E,90:A},{30:64,33:62,75:_,89:E,90:A},t(I,[2,29]),t(I,[2,30]),t(I,[2,31]),t(I,[2,32]),t(I,[2,33]),t(I,[2,34]),t(D,[2,81]),t(D,[2,82]),{1:[2,3]},{8:[2,8]},{8:[2,9]},{8:[2,10]},{8:[2,11]},{8:[2,12]},{8:[2,13]},{8:[2,14]},{8:[2,15]},{8:[2,16]},{27:[1,65],29:[1,66]},t(k,[2,79]),t(k,[2,80]),{27:[1,67],29:[1,68]},t(k,[2,85]),t(k,[2,86]),{62:69,65:L,66:R,67:O,68:M,69:B,70:F,71:P},{62:77,65:L,66:R,67:O,68:M,69:B,70:F,71:P},{30:78,33:62,75:_,89:E,90:A},{73:79,75:z,76:$,78:81,79:82,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X},t(te,[2,60]),t(te,[2,62]),{73:93,75:z,76:$,78:81,79:82,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X},{30:94,33:62,75:_,76:$,89:E,90:A},{5:[1,95]},{30:96,33:62,75:_,89:E,90:A},{5:[1,97]},{30:98,33:62,75:_,89:E,90:A},{63:[1,99]},t(J,[2,50]),t(J,[2,51]),t(J,[2,52]),t(J,[2,53]),t(J,[2,54]),t(J,[2,55]),t(J,[2,56]),{64:[1,100]},t(S,[2,59],{76:$}),t(S,[2,64],{76:se}),{33:103,75:[1,102],89:E,90:A},t(ue,[2,65],{79:104,75:z,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X}),t(Z,[2,67]),t(Z,[2,69]),t(Z,[2,70]),t(Z,[2,71]),t(Z,[2,72]),t(Z,[2,73]),t(Z,[2,74]),t(Z,[2,75]),t(Z,[2,76]),t(Z,[2,77]),t(Z,[2,78]),t(S,[2,57],{76:se}),t(S,[2,58],{76:$}),{5:Se,28:105,31:ce,34:ae,36:Oe,38:ge,40:ze},{27:[1,112],76:$},{5:He,40:$e,56:113,57:Re,59:Ie},{27:[1,118],76:$},{33:119,89:E,90:A},{33:120,89:E,90:A},{75:z,78:121,79:82,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X},t(te,[2,61]),t(te,[2,63]),t(Z,[2,68]),t(S,[2,21]),{32:[1,122]},{32:[1,123]},{32:[1,124]},{32:[1,125]},{5:Se,28:126,31:ce,34:ae,36:Oe,38:ge,40:ze},t(S,[2,28]),{5:[1,127]},t(S,[2,42]),{32:[1,128]},{32:[1,129]},{5:He,40:$e,56:130,57:Re,59:Ie},t(S,[2,47]),{5:[1,131]},t(S,[2,48]),t(S,[2,49]),t(ue,[2,66],{79:104,75:z,80:H,81:Q,82:j,83:ie,84:ne,85:le,86:he,87:K,88:X}),{33:132,89:E,90:A},{35:133,89:[1,134],90:[1,135]},{37:136,47:[1,137],48:[1,138],49:[1,139]},{39:140,50:[1,141],51:[1,142],52:[1,143],53:[1,144]},t(S,[2,27]),{5:Se,28:145,31:ce,34:ae,36:Oe,38:ge,40:ze},{58:146,89:[1,147],90:[1,148]},{60:149,89:[1,150],90:[1,151]},t(S,[2,46]),{5:He,40:$e,56:152,57:Re,59:Ie},{5:[1,153]},{5:[1,154]},{5:[2,83]},{5:[2,84]},{5:[1,155]},{5:[2,35]},{5:[2,36]},{5:[2,37]},{5:[1,156]},{5:[2,38]},{5:[2,39]},{5:[2,40]},{5:[2,41]},t(S,[2,22]),{5:[1,157]},{5:[2,87]},{5:[2,88]},{5:[1,158]},{5:[2,89]},{5:[2,90]},t(S,[2,43]),{5:Se,28:159,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:Se,28:160,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:Se,28:161,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:Se,28:162,31:ce,34:ae,36:Oe,38:ge,40:ze},{5:He,40:$e,56:163,57:Re,59:Ie},{5:He,40:$e,56:164,57:Re,59:Ie},t(S,[2,23]),t(S,[2,24]),t(S,[2,25]),t(S,[2,26]),t(S,[2,44]),t(S,[2,45])],defaultActions:{8:[2,2],12:[2,1],41:[2,3],42:[2,8],43:[2,9],44:[2,10],45:[2,11],46:[2,12],47:[2,13],48:[2,14],49:[2,15],50:[2,16],134:[2,83],135:[2,84],137:[2,35],138:[2,36],139:[2,37],141:[2,38],142:[2,39],143:[2,40],144:[2,41],147:[2,87],148:[2,88],150:[2,89],151:[2,90]},parseError:o(function(oe,V){if(V.recoverable)this.trace(oe);else{var xe=new Error(oe);throw xe.hash=V,xe}},"parseError"),parse:o(function(oe){var V=this,xe=[0],q=[],pe=[null],ve=[],Pe=this.table,_e="",we=0,Ve=0,De=0,qe=2,at=1,Rt=ve.slice.call(arguments,1),st=Object.create(this.lexer),Ue={yy:{}};for(var ct in this.yy)Object.prototype.hasOwnProperty.call(this.yy,ct)&&(Ue.yy[ct]=this.yy[ct]);st.setInput(oe,Ue.yy),Ue.yy.lexer=st,Ue.yy.parser=this,typeof st.yylloc>"u"&&(st.yylloc={});var We=st.yylloc;ve.push(We);var ot=st.options&&st.options.ranges;typeof Ue.yy.parseError=="function"?this.parseError=Ue.yy.parseError:this.parseError=Object.getPrototypeOf(this).parseError;function Yt(Dr){xe.length=xe.length-2*Dr,pe.length=pe.length-Dr,ve.length=ve.length-Dr}o(Yt,"popStack");function bt(){var Dr;return Dr=q.pop()||st.lex()||at,typeof Dr!="number"&&(Dr instanceof Array&&(q=Dr,Dr=q.pop()),Dr=V.symbols_[Dr]||Dr),Dr}o(bt,"lex");for(var Mt,xt,ut,Et,ft,yt,nt={},dn,Tt,On,tn;;){if(ut=xe[xe.length-1],this.defaultActions[ut]?Et=this.defaultActions[ut]:((Mt===null||typeof Mt>"u")&&(Mt=bt()),Et=Pe[ut]&&Pe[ut][Mt]),typeof Et>"u"||!Et.length||!Et[0]){var _r="";tn=[];for(dn in Pe[ut])this.terminals_[dn]&&dn>qe&&tn.push("'"+this.terminals_[dn]+"'");st.showPosition?_r="Parse error on line "+(we+1)+`: -`+st.showPosition()+` -Expecting `+tn.join(", ")+", got '"+(this.terminals_[Mt]||Mt)+"'":_r="Parse error on line "+(we+1)+": Unexpected "+(Mt==at?"end of input":"'"+(this.terminals_[Mt]||Mt)+"'"),this.parseError(_r,{text:st.match,token:this.terminals_[Mt]||Mt,line:st.yylineno,loc:We,expected:tn})}if(Et[0]instanceof Array&&Et.length>1)throw new Error("Parse Error: multiple actions possible at state: "+ut+", token: "+Mt);switch(Et[0]){case 1:xe.push(Mt),pe.push(st.yytext),ve.push(st.yylloc),xe.push(Et[1]),Mt=null,xt?(Mt=xt,xt=null):(Ve=st.yyleng,_e=st.yytext,we=st.yylineno,We=st.yylloc,De>0&&De--);break;case 2:if(Tt=this.productions_[Et[1]][1],nt.$=pe[pe.length-Tt],nt._$={first_line:ve[ve.length-(Tt||1)].first_line,last_line:ve[ve.length-1].last_line,first_column:ve[ve.length-(Tt||1)].first_column,last_column:ve[ve.length-1].last_column},ot&&(nt._$.range=[ve[ve.length-(Tt||1)].range[0],ve[ve.length-1].range[1]]),yt=this.performAction.apply(nt,[_e,Ve,we,Ue.yy,Et[1],pe,ve].concat(Rt)),typeof yt<"u")return yt;Tt&&(xe=xe.slice(0,-1*Tt*2),pe=pe.slice(0,-1*Tt),ve=ve.slice(0,-1*Tt)),xe.push(this.productions_[Et[1]][0]),pe.push(nt.$),ve.push(nt._$),On=Pe[xe[xe.length-2]][xe[xe.length-1]],xe.push(On);break;case 3:return!0}}return!0},"parse")},W=function(){var re={EOF:1,parseError:o(function(V,xe){if(this.yy.parser)this.yy.parser.parseError(V,xe);else throw new Error(V)},"parseError"),setInput:o(function(oe,V){return this.yy=V||this.yy||{},this._input=oe,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var oe=this._input[0];this.yytext+=oe,this.yyleng++,this.offset++,this.match+=oe,this.matched+=oe;var V=oe.match(/(?:\r\n?|\n).*/g);return V?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),oe},"input"),unput:o(function(oe){var V=oe.length,xe=oe.split(/(?:\r\n?|\n)/g);this._input=oe+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-V),this.offset-=V;var q=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),xe.length-1&&(this.yylineno-=xe.length-1);var pe=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:xe?(xe.length===q.length?this.yylloc.first_column:0)+q[q.length-xe.length].length-xe[0].length:this.yylloc.first_column-V},this.options.ranges&&(this.yylloc.range=[pe[0],pe[0]+this.yyleng-V]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). -`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(oe){this.unput(this.match.slice(oe))},"less"),pastInput:o(function(){var oe=this.matched.substr(0,this.matched.length-this.match.length);return(oe.length>20?"...":"")+oe.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var oe=this.match;return oe.length<20&&(oe+=this._input.substr(0,20-oe.length)),(oe.substr(0,20)+(oe.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var oe=this.pastInput(),V=new Array(oe.length+1).join("-");return oe+this.upcomingInput()+` -`+V+"^"},"showPosition"),test_match:o(function(oe,V){var xe,q,pe;if(this.options.backtrack_lexer&&(pe={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(pe.yylloc.range=this.yylloc.range.slice(0))),q=oe[0].match(/(?:\r\n?|\n).*/g),q&&(this.yylineno+=q.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:q?q[q.length-1].length-q[q.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+oe[0].length},this.yytext+=oe[0],this.match+=oe[0],this.matches=oe,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(oe[0].length),this.matched+=oe[0],xe=this.performAction.call(this,this.yy,this,V,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),xe)return xe;if(this._backtrack){for(var ve in pe)this[ve]=pe[ve];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var oe,V,xe,q;this._more||(this.yytext="",this.match="");for(var pe=this._currentRules(),ve=0;veV[0].length)){if(V=xe,q=ve,this.options.backtrack_lexer){if(oe=this.test_match(xe,pe[ve]),oe!==!1)return oe;if(this._backtrack){V=!1;continue}else return!1}else if(!this.options.flex)break}return V?(oe=this.test_match(V,pe[q]),oe!==!1?oe:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. 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49:return this.begin("style"),77;break;case 50:return 75;case 51:return 81;case 52:return 88;case 53:return"PERCENT";case 54:return 86;case 55:return 84;case 56:break;case 57:this.begin("string");break;case 58:this.popState();break;case 59:return this.begin("style"),72;break;case 60:return this.begin("style"),74;break;case 61:return 61;case 62:return 64;case 63:return 63;case 64:this.begin("string");break;case 65:this.popState();break;case 66:return"qString";case 67:return xe.yytext=xe.yytext.trim(),89;break;case 68:return 75;case 69:return 80;case 70:return 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40:Z[ce-1].unshift({type:"criticalStart",criticalText:se.parseMessage(Z[ce-2]),signalType:se.LINETYPE.CRITICAL_START}),Z[ce-1].push({type:"criticalEnd",signalType:se.LINETYPE.CRITICAL_END}),this.$=Z[ce-1];break;case 41:Z[ce-1].unshift({type:"breakStart",breakText:se.parseMessage(Z[ce-2]),signalType:se.LINETYPE.BREAK_START}),Z[ce-1].push({type:"breakEnd",optText:se.parseMessage(Z[ce-2]),signalType:se.LINETYPE.BREAK_END}),this.$=Z[ce-1];break;case 43:this.$=Z[ce-3].concat([{type:"option",optionText:se.parseMessage(Z[ce-1]),signalType:se.LINETYPE.CRITICAL_OPTION},Z[ce]]);break;case 45:this.$=Z[ce-3].concat([{type:"and",parText:se.parseMessage(Z[ce-1]),signalType:se.LINETYPE.PAR_AND},Z[ce]]);break;case 47:this.$=Z[ce-3].concat([{type:"else",altText:se.parseMessage(Z[ce-1]),signalType:se.LINETYPE.ALT_ELSE},Z[ce]]);break;case 48:Z[ce-3].draw="participant",Z[ce-3].type="addParticipant",Z[ce-3].description=se.parseMessage(Z[ce-1]),this.$=Z[ce-3];break;case 49:Z[ce-1].draw="participant",Z[ce-1].type="addParticipant",this.$=Z[ce-1];break;case 50:Z[ce-3].draw="actor",Z[ce-3].type="addParticipant",Z[ce-3].description=se.parseMessage(Z[ce-1]),this.$=Z[ce-3];break;case 51:Z[ce-1].draw="actor",Z[ce-1].type="addParticipant",this.$=Z[ce-1];break;case 52:Z[ce-1].type="destroyParticipant",this.$=Z[ce-1];break;case 53:this.$=[Z[ce-1],{type:"addNote",placement:Z[ce-2],actor:Z[ce-1].actor,text:Z[ce]}];break;case 54:Z[ce-2]=[].concat(Z[ce-1],Z[ce-1]).slice(0,2),Z[ce-2][0]=Z[ce-2][0].actor,Z[ce-2][1]=Z[ce-2][1].actor,this.$=[Z[ce-1],{type:"addNote",placement:se.PLACEMENT.OVER,actor:Z[ce-2].slice(0,2),text:Z[ce]}];break;case 55:this.$=[Z[ce-1],{type:"addLinks",actor:Z[ce-1].actor,text:Z[ce]}];break;case 56:this.$=[Z[ce-1],{type:"addALink",actor:Z[ce-1].actor,text:Z[ce]}];break;case 57:this.$=[Z[ce-1],{type:"addProperties",actor:Z[ce-1].actor,text:Z[ce]}];break;case 58:this.$=[Z[ce-1],{type:"addDetails",actor:Z[ce-1].actor,text:Z[ce]}];break;case 61:this.$=[Z[ce-2],Z[ce]];break;case 62:this.$=Z[ce];break;case 63:this.$=se.PLACEMENT.LEFTOF;break;case 64:this.$=se.PLACEMENT.RIGHTOF;break;case 65:this.$=[Z[ce-4],Z[ce-1],{type:"addMessage",from:Z[ce-4].actor,to:Z[ce-1].actor,signalType:Z[ce-3],msg:Z[ce],activate:!0},{type:"activeStart",signalType:se.LINETYPE.ACTIVE_START,actor:Z[ce-1].actor}];break;case 66:this.$=[Z[ce-4],Z[ce-1],{type:"addMessage",from:Z[ce-4].actor,to:Z[ce-1].actor,signalType:Z[ce-3],msg:Z[ce]},{type:"activeEnd",signalType:se.LINETYPE.ACTIVE_END,actor:Z[ce-4].actor}];break;case 67:this.$=[Z[ce-3],Z[ce-1],{type:"addMessage",from:Z[ce-3].actor,to:Z[ce-1].actor,signalType:Z[ce-2],msg:Z[ce]}];break;case 68:this.$={type:"addParticipant",actor:Z[ce]};break;case 69:this.$=se.LINETYPE.SOLID_OPEN;break;case 70:this.$=se.LINETYPE.DOTTED_OPEN;break;case 71:this.$=se.LINETYPE.SOLID;break;case 72:this.$=se.LINETYPE.BIDIRECTIONAL_SOLID;break;case 73:this.$=se.LINETYPE.DOTTED;break;case 74:this.$=se.LINETYPE.BIDIRECTIONAL_DOTTED;break;case 75:this.$=se.LINETYPE.SOLID_CROSS;break;case 76:this.$=se.LINETYPE.DOTTED_CROSS;break;case 77:this.$=se.LINETYPE.SOLID_POINT;break;case 78:this.$=se.LINETYPE.DOTTED_POINT;break;case 79:this.$=se.parseMessage(Z[ce].trim().substring(1));break}},"anonymous"),table:[{3:1,4:e,5:r,6:n},{1:[3]},{3:5,4:e,5:r,6:n},{3:6,4:e,5:r,6:n},t([1,4,5,13,14,18,21,23,29,30,31,33,35,36,37,38,39,41,43,44,46,50,52,53,54,59,60,61,62,70],i,{7:7}),{1:[2,1]},{1:[2,2]},{1:[2,3],4:a,5:s,8:8,9:10,12:12,13:l,14:u,17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},t(F,[2,5]),{9:47,12:12,13:l,14:u,17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},t(F,[2,7]),t(F,[2,8]),t(F,[2,14]),{12:48,50:_,52:I,53:D},{15:[1,49]},{5:[1,50]},{5:[1,53],19:[1,51],20:[1,52]},{22:54,70:B},{22:55,70:B},{5:[1,56]},{5:[1,57]},{5:[1,58]},{5:[1,59]},{5:[1,60]},t(F,[2,29]),t(F,[2,30]),{32:[1,61]},{34:[1,62]},t(F,[2,33]),{15:[1,63]},{15:[1,64]},{15:[1,65]},{15:[1,66]},{15:[1,67]},{15:[1,68]},{15:[1,69]},{15:[1,70]},{22:71,70:B},{22:72,70:B},{22:73,70:B},{67:74,71:[1,75],72:[1,76],73:[1,77],74:[1,78],75:[1,79],76:[1,80],77:[1,81],78:[1,82],79:[1,83],80:[1,84]},{55:85,57:[1,86],65:[1,87],66:[1,88]},{22:89,70:B},{22:90,70:B},{22:91,70:B},{22:92,70:B},t([5,51,64,71,72,73,74,75,76,77,78,79,80,81],[2,68]),t(F,[2,6]),t(F,[2,15]),t(P,[2,9],{10:93}),t(F,[2,17]),{5:[1,95],19:[1,94]},{5:[1,96]},t(F,[2,21]),{5:[1,97]},{5:[1,98]},t(F,[2,24]),t(F,[2,25]),t(F,[2,26]),t(F,[2,27]),t(F,[2,28]),t(F,[2,31]),t(F,[2,32]),t(z,i,{7:99}),t(z,i,{7:100}),t(z,i,{7:101}),t($,i,{40:102,7:103}),t(H,i,{42:104,7:105}),t(H,i,{7:105,42:106}),t(Q,i,{45:107,7:108}),t(z,i,{7:109}),{5:[1,111],51:[1,110]},{5:[1,113],51:[1,112]},{5:[1,114]},{22:117,68:[1,115],69:[1,116],70:B},t(j,[2,69]),t(j,[2,70]),t(j,[2,71]),t(j,[2,72]),t(j,[2,73]),t(j,[2,74]),t(j,[2,75]),t(j,[2,76]),t(j,[2,77]),t(j,[2,78]),{22:118,70:B},{22:120,58:119,70:B},{70:[2,63]},{70:[2,64]},{56:121,81:ie},{56:123,81:ie},{56:124,81:ie},{56:125,81:ie},{4:[1,128],5:[1,130],11:127,12:129,16:[1,126],50:_,52:I,53:D},{5:[1,131]},t(F,[2,19]),t(F,[2,20]),t(F,[2,22]),t(F,[2,23]),{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,132],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,133],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,134],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{16:[1,135]},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[2,46],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,49:[1,136],50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{16:[1,137]},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[2,44],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,48:[1,138],50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{16:[1,139]},{16:[1,140]},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[2,42],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,47:[1,141],50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{4:a,5:s,8:8,9:10,12:12,13:l,14:u,16:[1,142],17:15,18:h,21:f,22:40,23:d,24:19,25:20,26:21,27:22,28:23,29:p,30:m,31:g,33:y,35:v,36:x,37:b,38:w,39:C,41:T,43:E,44:A,46:S,50:_,52:I,53:D,54:k,59:L,60:R,61:O,62:M,70:B},{15:[1,143]},t(F,[2,49]),{15:[1,144]},t(F,[2,51]),t(F,[2,52]),{22:145,70:B},{22:146,70:B},{56:147,81:ie},{56:148,81:ie},{56:149,81:ie},{64:[1,150],81:[2,62]},{5:[2,55]},{5:[2,79]},{5:[2,56]},{5:[2,57]},{5:[2,58]},t(F,[2,16]),t(P,[2,10]),{12:151,50:_,52:I,53:D},t(P,[2,12]),t(P,[2,13]),t(F,[2,18]),t(F,[2,34]),t(F,[2,35]),t(F,[2,36]),t(F,[2,37]),{15:[1,152]},t(F,[2,38]),{15:[1,153]},t(F,[2,39]),t(F,[2,40]),{15:[1,154]},t(F,[2,41]),{5:[1,155]},{5:[1,156]},{56:157,81:ie},{56:158,81:ie},{5:[2,67]},{5:[2,53]},{5:[2,54]},{22:159,70:B},t(P,[2,11]),t($,i,{7:103,40:160}),t(H,i,{7:105,42:161}),t(Q,i,{7:108,45:162}),t(F,[2,48]),t(F,[2,50]),{5:[2,65]},{5:[2,66]},{81:[2,61]},{16:[2,47]},{16:[2,45]},{16:[2,43]}],defaultActions:{5:[2,1],6:[2,2],87:[2,63],88:[2,64],121:[2,55],122:[2,79],123:[2,56],124:[2,57],125:[2,58],147:[2,67],148:[2,53],149:[2,54],157:[2,65],158:[2,66],159:[2,61],160:[2,47],161:[2,45],162:[2,43]},parseError:o(function(X,te){if(te.recoverable)this.trace(X);else{var J=new Error(X);throw J.hash=te,J}},"parseError"),parse:o(function(X){var te=this,J=[0],se=[],ue=[null],Z=[],Se=this.table,ce="",ae=0,Oe=0,ge=0,ze=2,He=1,$e=Z.slice.call(arguments,1),Re=Object.create(this.lexer),Ie={yy:{}};for(var be in this.yy)Object.prototype.hasOwnProperty.call(this.yy,be)&&(Ie.yy[be]=this.yy[be]);Re.setInput(X,Ie.yy),Ie.yy.lexer=Re,Ie.yy.parser=this,typeof Re.yylloc>"u"&&(Re.yylloc={});var W=Re.yylloc;Z.push(W);var de=Re.options&&Re.options.ranges;typeof Ie.yy.parseError=="function"?this.parseError=Ie.yy.parseError:this.parseError=Object.getPrototypeOf(this).parseError;function re(Rt){J.length=J.length-2*Rt,ue.length=ue.length-Rt,Z.length=Z.length-Rt}o(re,"popStack");function oe(){var Rt;return Rt=se.pop()||Re.lex()||He,typeof Rt!="number"&&(Rt instanceof Array&&(se=Rt,Rt=se.pop()),Rt=te.symbols_[Rt]||Rt),Rt}o(oe,"lex");for(var V,xe,q,pe,ve,Pe,_e={},we,Ve,De,qe;;){if(q=J[J.length-1],this.defaultActions[q]?pe=this.defaultActions[q]:((V===null||typeof V>"u")&&(V=oe()),pe=Se[q]&&Se[q][V]),typeof pe>"u"||!pe.length||!pe[0]){var at="";qe=[];for(we in Se[q])this.terminals_[we]&&we>ze&&qe.push("'"+this.terminals_[we]+"'");Re.showPosition?at="Parse error on line "+(ae+1)+`: -`+Re.showPosition()+` -Expecting `+qe.join(", ")+", got '"+(this.terminals_[V]||V)+"'":at="Parse error on line "+(ae+1)+": Unexpected "+(V==He?"end of input":"'"+(this.terminals_[V]||V)+"'"),this.parseError(at,{text:Re.match,token:this.terminals_[V]||V,line:Re.yylineno,loc:W,expected:qe})}if(pe[0]instanceof Array&&pe.length>1)throw new Error("Parse Error: multiple actions possible at state: "+q+", token: "+V);switch(pe[0]){case 1:J.push(V),ue.push(Re.yytext),Z.push(Re.yylloc),J.push(pe[1]),V=null,xe?(V=xe,xe=null):(Oe=Re.yyleng,ce=Re.yytext,ae=Re.yylineno,W=Re.yylloc,ge>0&&ge--);break;case 2:if(Ve=this.productions_[pe[1]][1],_e.$=ue[ue.length-Ve],_e._$={first_line:Z[Z.length-(Ve||1)].first_line,last_line:Z[Z.length-1].last_line,first_column:Z[Z.length-(Ve||1)].first_column,last_column:Z[Z.length-1].last_column},de&&(_e._$.range=[Z[Z.length-(Ve||1)].range[0],Z[Z.length-1].range[1]]),Pe=this.performAction.apply(_e,[ce,Oe,ae,Ie.yy,pe[1],ue,Z].concat($e)),typeof Pe<"u")return Pe;Ve&&(J=J.slice(0,-1*Ve*2),ue=ue.slice(0,-1*Ve),Z=Z.slice(0,-1*Ve)),J.push(this.productions_[pe[1]][0]),ue.push(_e.$),Z.push(_e._$),De=Se[J[J.length-2]][J[J.length-1]],J.push(De);break;case 3:return!0}}return!0},"parse")},le=function(){var K={EOF:1,parseError:o(function(te,J){if(this.yy.parser)this.yy.parser.parseError(te,J);else throw new Error(te)},"parseError"),setInput:o(function(X,te){return this.yy=te||this.yy||{},this._input=X,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var X=this._input[0];this.yytext+=X,this.yyleng++,this.offset++,this.match+=X,this.matched+=X;var te=X.match(/(?:\r\n?|\n).*/g);return te?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),X},"input"),unput:o(function(X){var te=X.length,J=X.split(/(?:\r\n?|\n)/g);this._input=X+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-te),this.offset-=te;var se=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),J.length-1&&(this.yylineno-=J.length-1);var ue=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:J?(J.length===se.length?this.yylloc.first_column:0)+se[se.length-J.length].length-J[0].length:this.yylloc.first_column-te},this.options.ranges&&(this.yylloc.range=[ue[0],ue[0]+this.yyleng-te]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. You can only invoke reject() in the lexer when the lexer is of the backtracking persuasion (options.backtrack_lexer = true). -`+this.showPosition(),{text:"",token:null,line:this.yylineno});return this},"reject"),less:o(function(X){this.unput(this.match.slice(X))},"less"),pastInput:o(function(){var X=this.matched.substr(0,this.matched.length-this.match.length);return(X.length>20?"...":"")+X.substr(-20).replace(/\n/g,"")},"pastInput"),upcomingInput:o(function(){var X=this.match;return X.length<20&&(X+=this._input.substr(0,20-X.length)),(X.substr(0,20)+(X.length>20?"...":"")).replace(/\n/g,"")},"upcomingInput"),showPosition:o(function(){var X=this.pastInput(),te=new Array(X.length+1).join("-");return X+this.upcomingInput()+` -`+te+"^"},"showPosition"),test_match:o(function(X,te){var J,se,ue;if(this.options.backtrack_lexer&&(ue={yylineno:this.yylineno,yylloc:{first_line:this.yylloc.first_line,last_line:this.last_line,first_column:this.yylloc.first_column,last_column:this.yylloc.last_column},yytext:this.yytext,match:this.match,matches:this.matches,matched:this.matched,yyleng:this.yyleng,offset:this.offset,_more:this._more,_input:this._input,yy:this.yy,conditionStack:this.conditionStack.slice(0),done:this.done},this.options.ranges&&(ue.yylloc.range=this.yylloc.range.slice(0))),se=X[0].match(/(?:\r\n?|\n).*/g),se&&(this.yylineno+=se.length),this.yylloc={first_line:this.yylloc.last_line,last_line:this.yylineno+1,first_column:this.yylloc.last_column,last_column:se?se[se.length-1].length-se[se.length-1].match(/\r?\n?/)[0].length:this.yylloc.last_column+X[0].length},this.yytext+=X[0],this.match+=X[0],this.matches=X,this.yyleng=this.yytext.length,this.options.ranges&&(this.yylloc.range=[this.offset,this.offset+=this.yyleng]),this._more=!1,this._backtrack=!1,this._input=this._input.slice(X[0].length),this.matched+=X[0],J=this.performAction.call(this,this.yy,this,te,this.conditionStack[this.conditionStack.length-1]),this.done&&this._input&&(this.done=!1),J)return J;if(this._backtrack){for(var Z in ue)this[Z]=ue[Z];return!1}return!1},"test_match"),next:o(function(){if(this.done)return this.EOF;this._input||(this.done=!0);var X,te,J,se;this._more||(this.yytext="",this.match="");for(var ue=this._currentRules(),Z=0;Zte[0].length)){if(te=J,se=Z,this.options.backtrack_lexer){if(X=this.test_match(J,ue[Z]),X!==!1)return X;if(this._backtrack){te=!1;continue}else return!1}else if(!this.options.flex)break}return te?(X=this.test_match(te,ue[se]),X!==!1?X:!1):this._input===""?this.EOF:this.parseError("Lexical error on line "+(this.yylineno+1)+`. Unrecognized text. -`+this.showPosition(),{text:"",token:null,line:this.yylineno})},"next"),lex:o(function(){var te=this.next();return te||this.lex()},"lex"),begin:o(function(te){this.conditionStack.push(te)},"begin"),popState:o(function(){var te=this.conditionStack.length-1;return te>0?this.conditionStack.pop():this.conditionStack[0]},"popState"),_currentRules:o(function(){return this.conditionStack.length&&this.conditionStack[this.conditionStack.length-1]?this.conditions[this.conditionStack[this.conditionStack.length-1]].rules:this.conditions.INITIAL.rules},"_currentRules"),topState:o(function(te){return te=this.conditionStack.length-1-Math.abs(te||0),te>=0?this.conditionStack[te]:"INITIAL"},"topState"),pushState:o(function(te){this.begin(te)},"pushState"),stateStackSize:o(function(){return this.conditionStack.length},"stateStackSize"),options:{"case-insensitive":!0},performAction:o(function(te,J,se,ue){var Z=ue;switch(se){case 0:return 5;case 1:break;case 2:break;case 3:break;case 4:break;case 5:break;case 6:return 19;case 7:return this.begin("LINE"),14;break;case 8:return this.begin("ID"),50;break;case 9:return this.begin("ID"),52;break;case 10:return 13;case 11:return this.begin("ID"),53;break;case 12:return J.yytext=J.yytext.trim(),this.begin("ALIAS"),70;break;case 13:return this.popState(),this.popState(),this.begin("LINE"),51;break;case 14:return this.popState(),this.popState(),5;break;case 15:return this.begin("LINE"),36;break;case 16:return this.begin("LINE"),37;break;case 17:return this.begin("LINE"),38;break;case 18:return this.begin("LINE"),39;break;case 19:return this.begin("LINE"),49;break;case 20:return this.begin("LINE"),41;break;case 21:return this.begin("LINE"),43;break;case 22:return this.begin("LINE"),48;break;case 23:return this.begin("LINE"),44;break;case 24:return this.begin("LINE"),47;break;case 25:return this.begin("LINE"),46;break;case 26:return this.popState(),15;break;case 27:return 16;case 28:return 65;case 29:return 66;case 30:return 59;case 31:return 60;case 32:return 61;case 33:return 62;case 34:return 57;case 35:return 54;case 36:return this.begin("ID"),21;break;case 37:return this.begin("ID"),23;break;case 38:return 29;case 39:return 30;case 40:return this.begin("acc_title"),31;break;case 41:return this.popState(),"acc_title_value";break;case 42:return this.begin("acc_descr"),33;break;case 43:return this.popState(),"acc_descr_value";break;case 44:this.begin("acc_descr_multiline");break;case 45:this.popState();break;case 46:return"acc_descr_multiline_value";case 47:return 6;case 48:return 18;case 49:return 20;case 50:return 64;case 51:return 5;case 52:return J.yytext=J.yytext.trim(),70;break;case 53:return 73;case 54:return 74;case 55:return 75;case 56:return 76;case 57:return 71;case 58:return 72;case 59:return 77;case 60:return 78;case 61:return 79;case 62:return 80;case 63:return 81;case 64:return 68;case 65:return 69;case 66:return 5;case 67:return"INVALID"}},"anonymous"),rules:[/^(?:[\n]+)/i,/^(?:\s+)/i,/^(?:((?!\n)\s)+)/i,/^(?:#[^\n]*)/i,/^(?:%(?!\{)[^\n]*)/i,/^(?:[^\}]%%[^\n]*)/i,/^(?:[0-9]+(?=[ \n]+))/i,/^(?:box\b)/i,/^(?:participant\b)/i,/^(?:actor\b)/i,/^(?:create\b)/i,/^(?:destroy\b)/i,/^(?:[^\<->\->:\n,;]+?([\-]*[^\<->\->:\n,;]+?)*?(?=((?!\n)\s)+as(?!\n)\s|[#\n;]|$))/i,/^(?:as\b)/i,/^(?:(?:))/i,/^(?:loop\b)/i,/^(?:rect\b)/i,/^(?:opt\b)/i,/^(?:alt\b)/i,/^(?:else\b)/i,/^(?:par\b)/i,/^(?:par_over\b)/i,/^(?:and\b)/i,/^(?:critical\b)/i,/^(?:option\b)/i,/^(?:break\b)/i,/^(?:(?:[:]?(?:no)?wrap)?[^#\n;]*)/i,/^(?:end\b)/i,/^(?:left of\b)/i,/^(?:right of\b)/i,/^(?:links\b)/i,/^(?:link\b)/i,/^(?:properties\b)/i,/^(?:details\b)/i,/^(?:over\b)/i,/^(?:note\b)/i,/^(?:activate\b)/i,/^(?:deactivate\b)/i,/^(?:title\s[^#\n;]+)/i,/^(?:title:\s[^#\n;]+)/i,/^(?:accTitle\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*:\s*)/i,/^(?:(?!\n||)*[^\n]*)/i,/^(?:accDescr\s*\{\s*)/i,/^(?:[\}])/i,/^(?:[^\}]*)/i,/^(?:sequenceDiagram\b)/i,/^(?:autonumber\b)/i,/^(?:off\b)/i,/^(?:,)/i,/^(?:;)/i,/^(?:[^\+\<->\->:\n,;]+((?!(-x|--x|-\)|--\)))[\-]*[^\+\<->\->:\n,;]+)*)/i,/^(?:->>)/i,/^(?:<<->>)/i,/^(?:-->>)/i,/^(?:<<-->>)/i,/^(?:->)/i,/^(?:-->)/i,/^(?:-[x])/i,/^(?:--[x])/i,/^(?:-[\)])/i,/^(?:--[\)])/i,/^(?::(?:(?:no)?wrap)?[^#\n;]+)/i,/^(?:\+)/i,/^(?:-)/i,/^(?:$)/i,/^(?:.)/i],conditions:{acc_descr_multiline:{rules:[45,46],inclusive:!1},acc_descr:{rules:[43],inclusive:!1},acc_title:{rules:[41],inclusive:!1},ID:{rules:[2,3,12],inclusive:!1},ALIAS:{rules:[2,3,13,14],inclusive:!1},LINE:{rules:[2,3,26],inclusive:!1},INITIAL:{rules:[0,1,3,4,5,6,7,8,9,10,11,15,16,17,18,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,35,36,37,38,39,40,42,44,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67],inclusive:!0}}};return K}();ne.lexer=le;function he(){this.yy={}}return o(he,"Parser"),he.prototype=ne,ne.Parser=he,new he}();CO.parser=CO;lfe=CO});var iVe,aVe,sVe,_6,ufe=N(()=>{"use strict";zt();vt();s6();gr();mi();iVe={SOLID:0,DOTTED:1,NOTE:2,SOLID_CROSS:3,DOTTED_CROSS:4,SOLID_OPEN:5,DOTTED_OPEN:6,LOOP_START:10,LOOP_END:11,ALT_START:12,ALT_ELSE:13,ALT_END:14,OPT_START:15,OPT_END:16,ACTIVE_START:17,ACTIVE_END:18,PAR_START:19,PAR_AND:20,PAR_END:21,RECT_START:22,RECT_END:23,SOLID_POINT:24,DOTTED_POINT:25,AUTONUMBER:26,CRITICAL_START:27,CRITICAL_OPTION:28,CRITICAL_END:29,BREAK_START:30,BREAK_END:31,PAR_OVER_START:32,BIDIRECTIONAL_SOLID:33,BIDIRECTIONAL_DOTTED:34},aVe={FILLED:0,OPEN:1},sVe={LEFTOF:0,RIGHTOF:1,OVER:2},_6=class{constructor(){this.state=new pf(()=>({prevActor:void 0,actors:new Map,createdActors:new Map,destroyedActors:new Map,boxes:[],messages:[],notes:[],sequenceNumbersEnabled:!1,wrapEnabled:void 0,currentBox:void 0,lastCreated:void 0,lastDestroyed:void 0}));this.setAccTitle=Lr;this.setAccDescription=Nr;this.setDiagramTitle=$r;this.getAccTitle=Rr;this.getAccDescription=Mr;this.getDiagramTitle=Ir;this.apply=this.apply.bind(this),this.parseBoxData=this.parseBoxData.bind(this),this.parseMessage=this.parseMessage.bind(this),this.clear(),this.setWrap(me().wrap),this.LINETYPE=iVe,this.ARROWTYPE=aVe,this.PLACEMENT=sVe}static{o(this,"SequenceDB")}addBox(e){this.state.records.boxes.push({name:e.text,wrap:e.wrap??this.autoWrap(),fill:e.color,actorKeys:[]}),this.state.records.currentBox=this.state.records.boxes.slice(-1)[0]}addActor(e,r,n,i){let a=this.state.records.currentBox,s=this.state.records.actors.get(e);if(s){if(this.state.records.currentBox&&s.box&&this.state.records.currentBox!==s.box)throw new Error(`A same participant should only be defined in one Box: ${s.name} can't be in '${s.box.name}' and in '${this.state.records.currentBox.name}' at the same time.`);if(a=s.box?s.box:this.state.records.currentBox,s.box=a,s&&r===s.name&&n==null)return}if(n?.text==null&&(n={text:r,type:i}),(i==null||n.text==null)&&(n={text:r,type:i}),this.state.records.actors.set(e,{box:a,name:r,description:n.text,wrap:n.wrap??this.autoWrap(),prevActor:this.state.records.prevActor,links:{},properties:{},actorCnt:null,rectData:null,type:i??"participant"}),this.state.records.prevActor){let l=this.state.records.actors.get(this.state.records.prevActor);l&&(l.nextActor=e)}this.state.records.currentBox&&this.state.records.currentBox.actorKeys.push(e),this.state.records.prevActor=e}activationCount(e){let r,n=0;if(!e)return 0;for(r=0;r>-",token:"->>-",line:"1",loc:{first_line:1,last_line:1,first_column:1,last_column:1},expected:["'ACTIVE_PARTICIPANT'"]},l}return this.state.records.messages.push({id:this.state.records.messages.length.toString(),from:e,to:r,message:n?.text??"",wrap:n?.wrap??this.autoWrap(),type:i,activate:a}),!0}hasAtLeastOneBox(){return this.state.records.boxes.length>0}hasAtLeastOneBoxWithTitle(){return this.state.records.boxes.some(e=>e.name)}getMessages(){return this.state.records.messages}getBoxes(){return this.state.records.boxes}getActors(){return this.state.records.actors}getCreatedActors(){return this.state.records.createdActors}getDestroyedActors(){return this.state.records.destroyedActors}getActor(e){return this.state.records.actors.get(e)}getActorKeys(){return[...this.state.records.actors.keys()]}enableSequenceNumbers(){this.state.records.sequenceNumbersEnabled=!0}disableSequenceNumbers(){this.state.records.sequenceNumbersEnabled=!1}showSequenceNumbers(){return this.state.records.sequenceNumbersEnabled}setWrap(e){this.state.records.wrapEnabled=e}extractWrap(e){if(e===void 0)return{};e=e.trim();let r=/^:?wrap:/.exec(e)!==null?!0:/^:?nowrap:/.exec(e)!==null?!1:void 0;return{cleanedText:(r===void 0?e:e.replace(/^:?(?:no)?wrap:/,"")).trim(),wrap:r}}autoWrap(){return this.state.records.wrapEnabled!==void 0?this.state.records.wrapEnabled:me().sequence?.wrap??!1}clear(){this.state.reset(),Ar()}parseMessage(e){let r=e.trim(),{wrap:n,cleanedText:i}=this.extractWrap(r),a={text:i,wrap:n};return Y.debug(`parseMessage: ${JSON.stringify(a)}`),a}parseBoxData(e){let r=/^((?:rgba?|hsla?)\s*\(.*\)|\w*)(.*)$/.exec(e),n=r?.[1]?r[1].trim():"transparent",i=r?.[2]?r[2].trim():void 0;if(window?.CSS)window.CSS.supports("color",n)||(n="transparent",i=e.trim());else{let l=new Option().style;l.color=n,l.color!==n&&(n="transparent",i=e.trim())}let{wrap:a,cleanedText:s}=this.extractWrap(i);return{text:s?Tr(s,me()):void 0,color:n,wrap:a}}addNote(e,r,n){let i={actor:e,placement:r,message:n.text,wrap:n.wrap??this.autoWrap()},a=[].concat(e,e);this.state.records.notes.push(i),this.state.records.messages.push({id:this.state.records.messages.length.toString(),from:a[0],to:a[1],message:n.text,wrap:n.wrap??this.autoWrap(),type:this.LINETYPE.NOTE,placement:r})}addLinks(e,r){let n=this.getActor(e);try{let i=Tr(r.text,me());i=i.replace(/=/g,"="),i=i.replace(/&/g,"&");let a=JSON.parse(i);this.insertLinks(n,a)}catch(i){Y.error("error while parsing actor link text",i)}}addALink(e,r){let n=this.getActor(e);try{let i={},a=Tr(r.text,me()),s=a.indexOf("@");a=a.replace(/=/g,"="),a=a.replace(/&/g,"&");let l=a.slice(0,s-1).trim(),u=a.slice(s+1).trim();i[l]=u,this.insertLinks(n,i)}catch(i){Y.error("error while parsing actor link text",i)}}insertLinks(e,r){if(e.links==null)e.links=r;else for(let n in r)e.links[n]=r[n]}addProperties(e,r){let n=this.getActor(e);try{let i=Tr(r.text,me()),a=JSON.parse(i);this.insertProperties(n,a)}catch(i){Y.error("error while parsing actor properties text",i)}}insertProperties(e,r){if(e.properties==null)e.properties=r;else for(let n in r)e.properties[n]=r[n]}boxEnd(){this.state.records.currentBox=void 0}addDetails(e,r){let n=this.getActor(e),i=document.getElementById(r.text);try{let a=i.innerHTML,s=JSON.parse(a);s.properties&&this.insertProperties(n,s.properties),s.links&&this.insertLinks(n,s.links)}catch(a){Y.error("error while parsing actor details text",a)}}getActorProperty(e,r){if(e?.properties!==void 0)return e.properties[r]}apply(e){if(Array.isArray(e))e.forEach(r=>{this.apply(r)});else switch(e.type){case"sequenceIndex":this.state.records.messages.push({id:this.state.records.messages.length.toString(),from:void 0,to:void 0,message:{start:e.sequenceIndex,step:e.sequenceIndexStep,visible:e.sequenceVisible},wrap:!1,type:e.signalType});break;case"addParticipant":this.addActor(e.actor,e.actor,e.description,e.draw);break;case"createParticipant":if(this.state.records.actors.has(e.actor))throw new Error("It is not possible to have actors with the same id, even if one is destroyed before the next is created. Use 'AS' aliases to simulate the behavior");this.state.records.lastCreated=e.actor,this.addActor(e.actor,e.actor,e.description,e.draw),this.state.records.createdActors.set(e.actor,this.state.records.messages.length);break;case"destroyParticipant":this.state.records.lastDestroyed=e.actor,this.state.records.destroyedActors.set(e.actor,this.state.records.messages.length);break;case"activeStart":this.addSignal(e.actor,void 0,void 0,e.signalType);break;case"activeEnd":this.addSignal(e.actor,void 0,void 0,e.signalType);break;case"addNote":this.addNote(e.actor,e.placement,e.text);break;case"addLinks":this.addLinks(e.actor,e.text);break;case"addALink":this.addALink(e.actor,e.text);break;case"addProperties":this.addProperties(e.actor,e.text);break;case"addDetails":this.addDetails(e.actor,e.text);break;case"addMessage":if(this.state.records.lastCreated){if(e.to!==this.state.records.lastCreated)throw new Error("The created participant "+this.state.records.lastCreated.name+" does not have an associated creating message after its declaration. Please check the sequence diagram.");this.state.records.lastCreated=void 0}else if(this.state.records.lastDestroyed){if(e.to!==this.state.records.lastDestroyed&&e.from!==this.state.records.lastDestroyed)throw new Error("The destroyed participant "+this.state.records.lastDestroyed.name+" does not have an associated destroying message after its declaration. Please check the sequence diagram.");this.state.records.lastDestroyed=void 0}this.addSignal(e.from,e.to,e.msg,e.signalType,e.activate);break;case"boxStart":this.addBox(e.boxData);break;case"boxEnd":this.boxEnd();break;case"loopStart":this.addSignal(void 0,void 0,e.loopText,e.signalType);break;case"loopEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"rectStart":this.addSignal(void 0,void 0,e.color,e.signalType);break;case"rectEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"optStart":this.addSignal(void 0,void 0,e.optText,e.signalType);break;case"optEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"altStart":this.addSignal(void 0,void 0,e.altText,e.signalType);break;case"else":this.addSignal(void 0,void 0,e.altText,e.signalType);break;case"altEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"setAccTitle":Lr(e.text);break;case"parStart":this.addSignal(void 0,void 0,e.parText,e.signalType);break;case"and":this.addSignal(void 0,void 0,e.parText,e.signalType);break;case"parEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"criticalStart":this.addSignal(void 0,void 0,e.criticalText,e.signalType);break;case"option":this.addSignal(void 0,void 0,e.optionText,e.signalType);break;case"criticalEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break;case"breakStart":this.addSignal(void 0,void 0,e.breakText,e.signalType);break;case"breakEnd":this.addSignal(void 0,void 0,void 0,e.signalType);break}}getConfig(){return me().sequence}}});var oVe,hfe,ffe=N(()=>{"use strict";oVe=o(t=>`.actor { - stroke: ${t.actorBorder}; - fill: ${t.actorBkg}; - } - - text.actor > tspan { - fill: ${t.actorTextColor}; - stroke: none; - } - - .actor-line { - stroke: ${t.actorLineColor}; - } - - .messageLine0 { - stroke-width: 1.5; - stroke-dasharray: none; - stroke: ${t.signalColor}; - } - - .messageLine1 { - stroke-width: 1.5; - stroke-dasharray: 2, 2; - stroke: ${t.signalColor}; - } - - #arrowhead path { - fill: ${t.signalColor}; - stroke: ${t.signalColor}; - } - - .sequenceNumber { - fill: ${t.sequenceNumberColor}; - } - - #sequencenumber { - fill: ${t.signalColor}; - } - - #crosshead path { - fill: ${t.signalColor}; - stroke: ${t.signalColor}; - } - - .messageText { - fill: ${t.signalTextColor}; - stroke: none; - } - - .labelBox { - stroke: ${t.labelBoxBorderColor}; - fill: ${t.labelBoxBkgColor}; - } - - .labelText, .labelText > tspan { - fill: ${t.labelTextColor}; - stroke: none; - } - - .loopText, .loopText > tspan { - fill: ${t.loopTextColor}; - stroke: none; - } - - .loopLine { - stroke-width: 2px; - stroke-dasharray: 2, 2; - stroke: ${t.labelBoxBorderColor}; - fill: ${t.labelBoxBorderColor}; - } - - .note { - //stroke: #decc93; - stroke: ${t.noteBorderColor}; - fill: ${t.noteBkgColor}; - } - - .noteText, .noteText > tspan { - fill: ${t.noteTextColor}; - stroke: none; - } - - .activation0 { - fill: ${t.activationBkgColor}; - stroke: ${t.activationBorderColor}; - } - - .activation1 { - fill: ${t.activationBkgColor}; - stroke: ${t.activationBorderColor}; - } - - .activation2 { - fill: ${t.activationBkgColor}; - stroke: ${t.activationBorderColor}; - } - - .actorPopupMenu { - position: absolute; - } - - .actorPopupMenuPanel { - position: absolute; - fill: ${t.actorBkg}; - box-shadow: 0px 8px 16px 0px rgba(0,0,0,0.2); - filter: drop-shadow(3px 5px 2px rgb(0 0 0 / 0.4)); -} - .actor-man line { - stroke: ${t.actorBorder}; - fill: ${t.actorBkg}; - } - .actor-man circle, line { - stroke: ${t.actorBorder}; - fill: ${t.actorBkg}; - stroke-width: 2px; - } -`,"getStyles"),hfe=oVe});var AO,vf,pfe,mfe,lVe,dfe,_O,cVe,uVe,Tb,_p,gfe,Uc,DO,hVe,fVe,dVe,pVe,mVe,gVe,yVe,yfe,vVe,xVe,bVe,wVe,TVe,kVe,EVe,vfe,SVe,LO,CVe,hi,xfe=N(()=>{"use strict";gr();Wv();ir();AO=Sa(z0(),1);ji();vf=18*2,pfe="actor-top",mfe="actor-bottom",lVe="actor-box",dfe="actor-man",_O=o(function(t,e){return kd(t,e)},"drawRect"),cVe=o(function(t,e,r,n,i){if(e.links===void 0||e.links===null||Object.keys(e.links).length===0)return{height:0,width:0};let a=e.links,s=e.actorCnt,l=e.rectData;var u="none";i&&(u="block !important");let h=t.append("g");h.attr("id","actor"+s+"_popup"),h.attr("class","actorPopupMenu"),h.attr("display",u);var f="";l.class!==void 0&&(f=" "+l.class);let d=l.width>r?l.width:r,p=h.append("rect");if(p.attr("class","actorPopupMenuPanel"+f),p.attr("x",l.x),p.attr("y",l.height),p.attr("fill",l.fill),p.attr("stroke",l.stroke),p.attr("width",d),p.attr("height",l.height),p.attr("rx",l.rx),p.attr("ry",l.ry),a!=null){var m=20;for(let v in a){var g=h.append("a"),y=(0,AO.sanitizeUrl)(a[v]);g.attr("xlink:href",y),g.attr("target","_blank"),CVe(n)(v,g,l.x+10,l.height+m,d,20,{class:"actor"},n),m+=30}}return p.attr("height",m),{height:l.height+m,width:d}},"drawPopup"),uVe=o(function(t){return"var pu = document.getElementById('"+t+"'); if (pu != null) { pu.style.display = pu.style.display == 'block' ? 'none' : 'block'; }"},"popupMenuToggle"),Tb=o(async function(t,e,r=null){let n=t.append("foreignObject"),i=await mh(e.text,cr()),s=n.append("xhtml:div").attr("style","width: fit-content;").attr("xmlns","http://www.w3.org/1999/xhtml").html(i).node().getBoundingClientRect();if(n.attr("height",Math.round(s.height)).attr("width",Math.round(s.width)),e.class==="noteText"){let l=t.node().firstChild;l.setAttribute("height",s.height+2*e.textMargin);let u=l.getBBox();n.attr("x",Math.round(u.x+u.width/2-s.width/2)).attr("y",Math.round(u.y+u.height/2-s.height/2))}else if(r){let{startx:l,stopx:u,starty:h}=r;if(l>u){let f=l;l=u,u=f}n.attr("x",Math.round(l+Math.abs(l-u)/2-s.width/2)),e.class==="loopText"?n.attr("y",Math.round(h)):n.attr("y",Math.round(h-s.height))}return[n]},"drawKatex"),_p=o(function(t,e){let r=0,n=0,i=e.text.split(Ze.lineBreakRegex),[a,s]=Bo(e.fontSize),l=[],u=0,h=o(()=>e.y,"yfunc");if(e.valign!==void 0&&e.textMargin!==void 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n=t.append("g"),i=hi.drawRect(n,r),a=Hv();a.x=e.startx,a.y=e.starty,a.width=r.width,a.dy="1em",a.text=e.message,a.class="noteText",a.fontFamily=Ne.noteFontFamily,a.fontSize=Ne.noteFontSize,a.fontWeight=Ne.noteFontWeight,a.anchor=Ne.noteAlign,a.textMargin=Ne.noteMargin,a.valign="center";let s=pi(a.text)?await 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function(t,e,r,n){let{startx:i,stopx:a,starty:s,message:l,type:u,sequenceIndex:h,sequenceVisible:f}=e,d=Gt.calculateTextDimensions(l,Dp(Ne)),p=Hv();p.x=i,p.y=s+10,p.width=a-i,p.class="messageText",p.dy="1em",p.text=l,p.fontFamily=Ne.messageFontFamily,p.fontSize=Ne.messageFontSize,p.fontWeight=Ne.messageFontWeight,p.anchor=Ne.messageAlign,p.valign="center",p.textMargin=Ne.wrapPadding,p.tspan=!1,pi(p.text)?await Tb(t,p,{startx:i,stopx:a,starty:r}):_p(t,p);let m=d.width,g;i===a?Ne.rightAngles?g=t.append("path").attr("d",`M ${i},${r} H ${i+Ze.getMax(Ne.width/2,m/2)} V ${r+25} H ${i}`):g=t.append("path").attr("d","M "+i+","+r+" C "+(i+60)+","+(r-10)+" "+(i+60)+","+(r+30)+" "+i+","+(r+20)):(g=t.append("line"),g.attr("x1",i),g.attr("y1",r),g.attr("x2",a),g.attr("y2",r)),u===n.db.LINETYPE.DOTTED||u===n.db.LINETYPE.DOTTED_CROSS||u===n.db.LINETYPE.DOTTED_POINT||u===n.db.LINETYPE.DOTTED_OPEN||u===n.db.LINETYPE.BIDIRECTIONAL_DOTTED?(g.style("stroke-dasharray","3, 3"),g.attr("class","messageLine1")):g.attr("class","messageLine0");let y="";Ne.arrowMarkerAbsolute&&(y=window.location.protocol+"//"+window.location.host+window.location.pathname+window.location.search,y=y.replace(/\(/g,"\\("),y=y.replace(/\)/g,"\\)")),g.attr("stroke-width",2),g.attr("stroke","none"),g.style("fill","none"),(u===n.db.LINETYPE.SOLID||u===n.db.LINETYPE.DOTTED)&&g.attr("marker-end","url("+y+"#arrowhead)"),(u===n.db.LINETYPE.BIDIRECTIONAL_SOLID||u===n.db.LINETYPE.BIDIRECTIONAL_DOTTED)&&(g.attr("marker-start","url("+y+"#arrowhead)"),g.attr("marker-end","url("+y+"#arrowhead)")),(u===n.db.LINETYPE.SOLID_POINT||u===n.db.LINETYPE.DOTTED_POINT)&&g.attr("marker-end","url("+y+"#filled-head)"),(u===n.db.LINETYPE.SOLID_CROSS||u===n.db.LINETYPE.DOTTED_CROSS)&&g.attr("marker-end","url("+y+"#crosshead)"),(f||Ne.showSequenceNumbers)&&(g.attr("marker-start","url("+y+"#sequencenumber)"),t.append("text").attr("x",i).attr("y",r+4).attr("font-family","sans-serif").attr("font-size","12px").attr("text-anchor","middle").attr("class","sequenceNumber").text(h))},"drawMessage"),LVe=o(function(t,e,r,n,i,a,s){let l=0,u=0,h,f=0;for(let d of n){let p=e.get(d),m=p.box;h&&h!=m&&(s||rt.models.addBox(h),u+=Ne.boxMargin+h.margin),m&&m!=h&&(s||(m.x=l+u,m.y=i),u+=m.margin),p.width=p.width||Ne.width,p.height=Ze.getMax(p.height||Ne.height,Ne.height),p.margin=p.margin||Ne.actorMargin,f=Ze.getMax(f,p.height),r.get(p.name)&&(u+=p.width/2),p.x=l+u,p.starty=rt.getVerticalPos(),rt.insert(p.x,i,p.x+p.width,p.height),l+=p.width+u,p.box&&(p.box.width=l+m.margin-p.box.x),u=p.margin,h=p.box,rt.models.addActor(p)}h&&!s&&rt.models.addBox(h),rt.bumpVerticalPos(f)},"addActorRenderingData"),NO=o(async function(t,e,r,n){if(n){let i=0;rt.bumpVerticalPos(Ne.boxMargin*2);for(let a of r){let s=e.get(a);s.stopy||(s.stopy=rt.getVerticalPos());let l=await hi.drawActor(t,s,Ne,!0);i=Ze.getMax(i,l)}rt.bumpVerticalPos(i+Ne.boxMargin)}else for(let i of r){let a=e.get(i);await hi.drawActor(t,a,Ne,!1)}},"drawActors"),wfe=o(function(t,e,r,n){let i=0,a=0;for(let s of r){let l=e.get(s),u=IVe(l),h=hi.drawPopup(t,l,u,Ne,Ne.forceMenus,n);h.height>i&&(i=h.height),h.width+l.x>a&&(a=h.width+l.x)}return{maxHeight:i,maxWidth:a}},"drawActorsPopup"),Tfe=o(function(t){Gn(Ne,t),t.fontFamily&&(Ne.actorFontFamily=Ne.noteFontFamily=Ne.messageFontFamily=t.fontFamily),t.fontSize&&(Ne.actorFontSize=Ne.noteFontSize=Ne.messageFontSize=t.fontSize),t.fontWeight&&(Ne.actorFontWeight=Ne.noteFontWeight=Ne.messageFontWeight=t.fontWeight)},"setConf"),D6=o(function(t){return rt.activations.filter(function(e){return e.actor===t})},"actorActivations"),bfe=o(function(t,e){let r=e.get(t),n=D6(t),i=n.reduce(function(s,l){return Ze.getMin(s,l.startx)},r.x+r.width/2-1),a=n.reduce(function(s,l){return Ze.getMax(s,l.stopx)},r.x+r.width/2+1);return[i,a]},"activationBounds");o(Hc,"adjustLoopHeightForWrap");o(RVe,"adjustCreatedDestroyedData");NVe=o(async function(t,e,r,n){let{securityLevel:i,sequence:a}=me();Ne=a;let s;i==="sandbox"&&(s=Ge("#i"+e));let l=i==="sandbox"?Ge(s.nodes()[0].contentDocument.body):Ge("body"),u=i==="sandbox"?s.nodes()[0].contentDocument:document;rt.init(),Y.debug(n.db);let h=i==="sandbox"?l.select(`[id="${e}"]`):Ge(`[id="${e}"]`),f=n.db.getActors(),d=n.db.getCreatedActors(),p=n.db.getDestroyedActors(),m=n.db.getBoxes(),g=n.db.getActorKeys(),y=n.db.getMessages(),v=n.db.getDiagramTitle(),x=n.db.hasAtLeastOneBox(),b=n.db.hasAtLeastOneBoxWithTitle(),w=await MVe(f,y,n);if(Ne.height=await OVe(f,w,m),hi.insertComputerIcon(h),hi.insertDatabaseIcon(h),hi.insertClockIcon(h),x&&(rt.bumpVerticalPos(Ne.boxMargin),b&&rt.bumpVerticalPos(m[0].textMaxHeight)),Ne.hideUnusedParticipants===!0){let F=new Set;y.forEach(P=>{F.add(P.from),F.add(P.to)}),g=g.filter(P=>F.has(P))}LVe(h,f,d,g,0,y,!1);let C=await FVe(y,f,w,n);hi.insertArrowHead(h),hi.insertArrowCrossHead(h),hi.insertArrowFilledHead(h),hi.insertSequenceNumber(h);function T(F,P){let z=rt.endActivation(F);z.starty+18>P&&(z.starty=P-6,P+=12),hi.drawActivation(h,z,P,Ne,D6(F.from).length),rt.insert(z.startx,P-10,z.stopx,P)}o(T,"activeEnd");let E=1,A=1,S=[],_=[],I=0;for(let F of y){let P,z,$;switch(F.type){case n.db.LINETYPE.NOTE:rt.resetVerticalPos(),z=F.noteModel,await AVe(h,z);break;case n.db.LINETYPE.ACTIVE_START:rt.newActivation(F,h,f);break;case n.db.LINETYPE.ACTIVE_END:T(F,rt.getVerticalPos());break;case n.db.LINETYPE.LOOP_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.LOOP_END:P=rt.endLoop(),await hi.drawLoop(h,P,"loop",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.RECT_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin,H=>rt.newLoop(void 0,H.message));break;case n.db.LINETYPE.RECT_END:P=rt.endLoop(),_.push(P),rt.models.addLoop(P),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos());break;case n.db.LINETYPE.OPT_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.OPT_END:P=rt.endLoop(),await hi.drawLoop(h,P,"opt",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.ALT_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.ALT_ELSE:Hc(C,F,Ne.boxMargin+Ne.boxTextMargin,Ne.boxMargin,H=>rt.addSectionToLoop(H));break;case n.db.LINETYPE.ALT_END:P=rt.endLoop(),await hi.drawLoop(h,P,"alt",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.PAR_START:case n.db.LINETYPE.PAR_OVER_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H)),rt.saveVerticalPos();break;case n.db.LINETYPE.PAR_AND:Hc(C,F,Ne.boxMargin+Ne.boxTextMargin,Ne.boxMargin,H=>rt.addSectionToLoop(H));break;case n.db.LINETYPE.PAR_END:P=rt.endLoop(),await hi.drawLoop(h,P,"par",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.AUTONUMBER:E=F.message.start||E,A=F.message.step||A,F.message.visible?n.db.enableSequenceNumbers():n.db.disableSequenceNumbers();break;case n.db.LINETYPE.CRITICAL_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.CRITICAL_OPTION:Hc(C,F,Ne.boxMargin+Ne.boxTextMargin,Ne.boxMargin,H=>rt.addSectionToLoop(H));break;case n.db.LINETYPE.CRITICAL_END:P=rt.endLoop(),await hi.drawLoop(h,P,"critical",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;case n.db.LINETYPE.BREAK_START:Hc(C,F,Ne.boxMargin,Ne.boxMargin+Ne.boxTextMargin,H=>rt.newLoop(H));break;case n.db.LINETYPE.BREAK_END:P=rt.endLoop(),await hi.drawLoop(h,P,"break",Ne),rt.bumpVerticalPos(P.stopy-rt.getVerticalPos()),rt.models.addLoop(P);break;default:try{$=F.msgModel,$.starty=rt.getVerticalPos(),$.sequenceIndex=E,$.sequenceVisible=n.db.showSequenceNumbers();let H=await _Ve(h,$);RVe(F,$,H,I,f,d,p),S.push({messageModel:$,lineStartY:H}),rt.models.addMessage($)}catch(H){Y.error("error while drawing message",H)}}[n.db.LINETYPE.SOLID_OPEN,n.db.LINETYPE.DOTTED_OPEN,n.db.LINETYPE.SOLID,n.db.LINETYPE.DOTTED,n.db.LINETYPE.SOLID_CROSS,n.db.LINETYPE.DOTTED_CROSS,n.db.LINETYPE.SOLID_POINT,n.db.LINETYPE.DOTTED_POINT,n.db.LINETYPE.BIDIRECTIONAL_SOLID,n.db.LINETYPE.BIDIRECTIONAL_DOTTED].includes(F.type)&&(E=E+A),I++}Y.debug("createdActors",d),Y.debug("destroyedActors",p),await NO(h,f,g,!1);for(let F of S)await DVe(h,F.messageModel,F.lineStartY,n);Ne.mirrorActors&&await NO(h,f,g,!0),_.forEach(F=>hi.drawBackgroundRect(h,F)),DO(h,f,g,Ne);for(let F of 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g=Gt.calculateTextDimensions(t.message,Dp(Ne));return{width:Ze.getMax(t.wrap?0:g.width+2*Ne.wrapPadding,m+2*Ne.wrapPadding,Ne.width),height:0,startx:u,stopx:h,starty:0,stopy:0,message:t.message,type:t.type,wrap:t.wrap,fromBounds:Math.min.apply(null,p),toBounds:Math.max.apply(null,p)}},"buildMessageModel"),FVe=o(async function(t,e,r,n){let i={},a=[],s,l,u;for(let h of t){switch(h.type){case n.db.LINETYPE.LOOP_START:case n.db.LINETYPE.ALT_START:case n.db.LINETYPE.OPT_START:case n.db.LINETYPE.PAR_START:case n.db.LINETYPE.PAR_OVER_START:case n.db.LINETYPE.CRITICAL_START:case n.db.LINETYPE.BREAK_START:a.push({id:h.id,msg:h.message,from:Number.MAX_SAFE_INTEGER,to:Number.MIN_SAFE_INTEGER,width:0});break;case n.db.LINETYPE.ALT_ELSE:case n.db.LINETYPE.PAR_AND:case n.db.LINETYPE.CRITICAL_OPTION:h.message&&(s=a.pop(),i[s.id]=s,i[h.id]=s,a.push(s));break;case n.db.LINETYPE.LOOP_END:case n.db.LINETYPE.ALT_END:case n.db.LINETYPE.OPT_END:case n.db.LINETYPE.PAR_END:case n.db.LINETYPE.CRITICAL_END:case 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0?s:l.styleEnabled,zoom:Ct(l.zoom)?l.zoom:1,pan:{x:Ur(l.pan)&&Ct(l.pan.x)?l.pan.x:0,y:Ur(l.pan)&&Ct(l.pan.y)?l.pan.y:0},animation:{current:[],queue:[]},hasCompoundNodes:!1,multiClickDebounceTime:u(250,l.multiClickDebounceTime)};this.createEmitter(),this.selectionType(l.selectionType),this.zoomRange({min:l.minZoom,max:l.maxZoom});var f=o(function(g,y){var v=g.some(nWe);if(v)return ey.all(g).then(y);y(g)},"loadExtData");h.styleEnabled&&r.setStyle([]);var d=rr({},l,l.renderer);r.initRenderer(d);var p=o(function(g,y,v){r.notifications(!1);var x=r.mutableElements();x.length>0&&x.remove(),g!=null&&(Ur(g)||En(g))&&r.add(g),r.one("layoutready",function(w){r.notifications(!0),r.emit(w),r.one("load",y),r.emitAndNotify("load")}).one("layoutstop",function(){r.one("done",v),r.emit("done")});var b=rr({},r._private.options.layout);b.eles=r.elements(),r.layout(b).run()},"setElesAndLayout");f([l.style,l.elements],function(m){var g=m[0],y=m[1];h.styleEnabled&&r.style().append(g),p(y,function(){r.startAnimationLoop(),h.ready=!0,si(l.ready)&&r.on("ready",l.ready);for(var v=0;v0,l=!!t.boundingBox,u=e.extent(),h=Hs(l?t.boundingBox:{x1:u.x1,y1:u.y1,w:u.w,h:u.h}),f;if(go(t.roots))f=t.roots;else if(En(t.roots)){for(var d=[],p=0;p0;){var O=R(),M=I(O,k);if(M)O.outgoers().filter(function(ae){return ae.isNode()&&r.has(ae)}).forEach(L);else if(M===null){un("Detected double maximal shift for node `"+O.id()+"`. Bailing maximal adjustment due to cycle. Use `options.maximal: true` only on DAGs.");break}}}var B=0;if(t.avoidOverlap)for(var F=0;F0&&b[0].length<=3?$e/2:0),Ie=2*Math.PI/b[ze].length*He;return ze===0&&b[0].length===1&&(Re=1),{x:se.x+Re*Math.cos(Ie),y:se.y+Re*Math.sin(Ie)}}else{var be=b[ze].length,W=Math.max(be===1?0:l?(h.w-t.padding*2-ue.w)/((t.grid?Se:be)-1):(h.w-t.padding*2-ue.w)/((t.grid?Se:be)+1),B),de={x:se.x+(He+1-(be+1)/2)*W,y:se.y+(ze+1-(ne+1)/2)*Z};return de}},"getPosition");return r.nodes().layoutPositions(this,t,ce),this};rQe={fit:!0,padding:30,boundingBox:void 0,avoidOverlap:!0,nodeDimensionsIncludeLabels:!1,spacingFactor:void 0,radius:void 0,startAngle:3/2*Math.PI,sweep:void 0,clockwise:!0,sort:void 0,animate:!1,animationDuration:500,animationEasing:void 0,animateFilter:o(function(e,r){return!0},"animateFilter"),ready:void 0,stop:void 0,transform:o(function(e,r){return r},"transform")};o(rge,"CircleLayout");rge.prototype.run=function(){var t=this.options,e=t,r=t.cy,n=e.eles,i=e.counterclockwise!==void 0?!e.counterclockwise:e.clockwise,a=n.nodes().not(":parent");e.sort&&(a=a.sort(e.sort));for(var s=Hs(e.boundingBox?e.boundingBox:{x1:0,y1:0,w:r.width(),h:r.height()}),l={x:s.x1+s.w/2,y:s.y1+s.h/2},u=e.sweep===void 0?2*Math.PI-2*Math.PI/a.length:e.sweep,h=u/Math.max(1,a.length-1),f,d=0,p=0;p1&&e.avoidOverlap){d*=1.75;var x=Math.cos(h)-Math.cos(0),b=Math.sin(h)-Math.sin(0),w=Math.sqrt(d*d/(x*x+b*b));f=Math.max(w,f)}var C=o(function(E,A){var S=e.startAngle+A*h*(i?1:-1),_=f*Math.cos(S),I=f*Math.sin(S),D={x:l.x+_,y:l.y+I};return D},"getPos");return n.nodes().layoutPositions(this,e,C),this};nQe={fit:!0,padding:30,startAngle:3/2*Math.PI,sweep:void 0,clockwise:!0,equidistant:!1,minNodeSpacing:10,boundingBox:void 0,avoidOverlap:!0,nodeDimensionsIncludeLabels:!1,height:void 0,width:void 0,spacingFactor:void 0,concentric:o(function(e){return e.degree()},"concentric"),levelWidth:o(function(e){return e.maxDegree()/4},"levelWidth"),animate:!1,animationDuration:500,animationEasing:void 0,animateFilter:o(function(e,r){return!0},"animateFilter"),ready:void 0,stop:void 0,transform:o(function(e,r){return r},"transform")};o(nge,"ConcentricLayout");nge.prototype.run=function(){for(var t=this.options,e=t,r=e.counterclockwise!==void 0?!e.counterclockwise:e.clockwise,n=t.cy,i=e.eles,a=i.nodes().not(":parent"),s=Hs(e.boundingBox?e.boundingBox:{x1:0,y1:0,w:n.width(),h:n.height()}),l={x:s.x1+s.w/2,y:s.y1+s.h/2},u=[],h=0,f=0;f0){var T=Math.abs(b[0].value-C.value);T>=v&&(b=[],x.push(b))}b.push(C)}var E=h+e.minNodeSpacing;if(!e.avoidOverlap){var A=x.length>0&&x[0].length>1,S=Math.min(s.w,s.h)/2-E,_=S/(x.length+A?1:0);E=Math.min(E,_)}for(var I=0,D=0;D1&&e.avoidOverlap){var O=Math.cos(R)-Math.cos(0),M=Math.sin(R)-Math.sin(0),B=Math.sqrt(E*E/(O*O+M*M));I=Math.max(B,I)}k.r=I,I+=E}if(e.equidistant){for(var F=0,P=0,z=0;z=t.numIter||(hQe(n,t),n.temperature=n.temperature*t.coolingFactor,n.temperature=t.animationThreshold&&a(),xS(d)}},"frame");f()}else{for(;h;)h=s(u),u++;E0e(n,t),l()}return this};HS.prototype.stop=function(){return this.stopped=!0,this.thread&&this.thread.stop(),this.emit("layoutstop"),this};HS.prototype.destroy=function(){return this.thread&&this.thread.stop(),this};aQe=o(function(e,r,n){for(var i=n.eles.edges(),a=n.eles.nodes(),s=Hs(n.boundingBox?n.boundingBox:{x1:0,y1:0,w:e.width(),h:e.height()}),l={isCompound:e.hasCompoundNodes(),layoutNodes:[],idToIndex:{},nodeSize:a.size(),graphSet:[],indexToGraph:[],layoutEdges:[],edgeSize:i.size(),temperature:n.initialTemp,clientWidth:s.w,clientHeight:s.h,boundingBox:s},u=n.eles.components(),h={},f=0;f0){l.graphSet.push(S);for(var f=0;fi.count?0:i.graph},"findLCA"),oQe=o(function t(e,r,n,i){var a=i.graphSet[n];if(-10)var d=i.nodeOverlap*f,p=Math.sqrt(l*l+u*u),m=d*l/p,g=d*u/p;else var y=CS(e,l,u),v=CS(r,-1*l,-1*u),x=v.x-y.x,b=v.y-y.y,w=x*x+b*b,p=Math.sqrt(w),d=(e.nodeRepulsion+r.nodeRepulsion)/w,m=d*x/p,g=d*b/p;e.isLocked||(e.offsetX-=m,e.offsetY-=g),r.isLocked||(r.offsetX+=m,r.offsetY+=g)}},"nodeRepulsion"),pQe=o(function(e,r,n,i){if(n>0)var a=e.maxX-r.minX;else var a=r.maxX-e.minX;if(i>0)var s=e.maxY-r.minY;else var s=r.maxY-e.minY;return a>=0&&s>=0?Math.sqrt(a*a+s*s):0},"nodesOverlap"),CS=o(function(e,r,n){var i=e.positionX,a=e.positionY,s=e.height||1,l=e.width||1,u=n/r,h=s/l,f={};return r===0&&0n?(f.x=i,f.y=a+s/2,f):0r&&-1*h<=u&&u<=h?(f.x=i-l/2,f.y=a-l*n/2/r,f):0=h)?(f.x=i+s*r/2/n,f.y=a+s/2,f):(0>n&&(u<=-1*h||u>=h)&&(f.x=i-s*r/2/n,f.y=a-s/2),f)},"findClippingPoint"),mQe=o(function(e,r){for(var n=0;nn){var v=r.gravity*m/y,x=r.gravity*g/y;p.offsetX+=v,p.offsetY+=x}}}}},"calculateGravityForces"),yQe=o(function(e,r){var n=[],i=0,a=-1;for(n.push.apply(n,e.graphSet[0]),a+=e.graphSet[0].length;i<=a;){var s=n[i++],l=e.idToIndex[s],u=e.layoutNodes[l],h=u.children;if(0n)var a={x:n*e/i,y:n*r/i};else var a={x:e,y:r};return a},"limitForce"),bQe=o(function t(e,r){var n=e.parentId;if(n!=null){var i=r.layoutNodes[r.idToIndex[n]],a=!1;if((i.maxX==null||e.maxX+i.padRight>i.maxX)&&(i.maxX=e.maxX+i.padRight,a=!0),(i.minX==null||e.minX-i.padLefti.maxY)&&(i.maxY=e.maxY+i.padBottom,a=!0),(i.minY==null||e.minY-i.padTopx&&(g+=v+r.componentSpacing,m=0,y=0,v=0)}}},"separateComponents"),wQe={fit:!0,padding:30,boundingBox:void 0,avoidOverlap:!0,avoidOverlapPadding:10,nodeDimensionsIncludeLabels:!1,spacingFactor:void 0,condense:!1,rows:void 0,cols:void 0,position:o(function(e){},"position"),sort:void 0,animate:!1,animationDuration:500,animationEasing:void 0,animateFilter:o(function(e,r){return!0},"animateFilter"),ready:void 0,stop:void 0,transform:o(function(e,r){return r},"transform")};o(age,"GridLayout");age.prototype.run=function(){var t=this.options,e=t,r=t.cy,n=e.eles,i=n.nodes().not(":parent");e.sort&&(i=i.sort(e.sort));var a=Hs(e.boundingBox?e.boundingBox:{x1:0,y1:0,w:r.width(),h:r.height()});if(a.h===0||a.w===0)n.nodes().layoutPositions(this,e,function(Q){return{x:a.x1,y:a.y1}});else{var s=i.size(),l=Math.sqrt(s*a.h/a.w),u=Math.round(l),h=Math.round(a.w/a.h*l),f=o(function(j){if(j==null)return Math.min(u,h);var ie=Math.min(u,h);ie==u?u=j:h=j},"small"),d=o(function(j){if(j==null)return Math.max(u,h);var ie=Math.max(u,h);ie==u?u=j:h=j},"large"),p=e.rows,m=e.cols!=null?e.cols:e.columns;if(p!=null&&m!=null)u=p,h=m;else if(p!=null&&m==null)u=p,h=Math.ceil(s/u);else if(p==null&&m!=null)h=m,u=Math.ceil(s/h);else if(h*u>s){var g=f(),y=d();(g-1)*y>=s?f(g-1):(y-1)*g>=s&&d(y-1)}else for(;h*u=s?d(x+1):f(v+1)}var b=a.w/h,w=a.h/u;if(e.condense&&(b=0,w=0),e.avoidOverlap)for(var C=0;C=h&&(O=0,R++)},"moveToNextCell"),B={},F=0;F(O=Wqe(t,e,M[B],M[B+1],M[B+2],M[B+3])))return v(A,O),!0}else if(_.edgeType==="bezier"||_.edgeType==="multibezier"||_.edgeType==="self"||_.edgeType==="compound"){for(var M=_.allpts,B=0;B+5<_.allpts.length;B+=4)if(Gqe(t,e,M[B],M[B+1],M[B+2],M[B+3],M[B+4],M[B+5],R)&&L>(O=Hqe(t,e,M[B],M[B+1],M[B+2],M[B+3],M[B+4],M[B+5])))return v(A,O),!0}for(var F=F||S.source,P=P||S.target,z=i.getArrowWidth(I,D),$=[{name:"source",x:_.arrowStartX,y:_.arrowStartY,angle:_.srcArrowAngle},{name:"target",x:_.arrowEndX,y:_.arrowEndY,angle:_.tgtArrowAngle},{name:"mid-source",x:_.midX,y:_.midY,angle:_.midsrcArrowAngle},{name:"mid-target",x:_.midX,y:_.midY,angle:_.midtgtArrowAngle}],B=0;B<$.length;B++){var H=$[B],Q=a.arrowShapes[A.pstyle(H.name+"-arrow-shape").value],j=A.pstyle("width").pfValue;if(Q.roughCollide(t,e,z,H.angle,{x:H.x,y:H.y},j,f)&&Q.collide(t,e,z,H.angle,{x:H.x,y:H.y},j,f))return v(A),!0}h&&l.length>0&&(x(F),x(P))}o(b,"checkEdge");function w(A,S,_){return Gl(A,S,_)}o(w,"preprop");function C(A,S){var _=A._private,I=p,D;S?D=S+"-":D="",A.boundingBox();var k=_.labelBounds[S||"main"],L=A.pstyle(D+"label").value,R=A.pstyle("text-events").strValue==="yes";if(!(!R||!L)){var O=w(_.rscratch,"labelX",S),M=w(_.rscratch,"labelY",S),B=w(_.rscratch,"labelAngle",S),F=A.pstyle(D+"text-margin-x").pfValue,P=A.pstyle(D+"text-margin-y").pfValue,z=k.x1-I-F,$=k.x2+I-F,H=k.y1-I-P,Q=k.y2+I-P;if(B){var j=Math.cos(B),ie=Math.sin(B),ne=o(function(se,ue){return se=se-O,ue=ue-M,{x:se*j-ue*ie+O,y:se*ie+ue*j+M}},"rotate"),le=ne(z,H),he=ne(z,Q),K=ne($,H),X=ne($,Q),te=[le.x+F,le.y+P,K.x+F,K.y+P,X.x+F,X.y+P,he.x+F,he.y+P];if(Us(t,e,te))return v(A),!0}else if(K1(k,t,e))return v(A),!0}}o(C,"checkLabel");for(var T=s.length-1;T>=0;T--){var E=s[T];E.isNode()?x(E)||C(E):b(E)||C(E)||C(E,"source")||C(E,"target")}return l};qp.getAllInBox=function(t,e,r,n){var i=this.getCachedZSortedEles().interactive,a=[],s=Math.min(t,r),l=Math.max(t,r),u=Math.min(e,n),h=Math.max(e,n);t=s,r=l,e=u,n=h;for(var f=Hs({x1:t,y1:e,x2:r,y2:n}),d=0;d0?-(Math.PI-e.ang):Math.PI+e.ang},"invertVec"),AQe=o(function(e,r,n,i,a){if(e!==D0e?L0e(r,e,qc):CQe(Jo,qc),L0e(r,n,Jo),A0e=qc.nx*Jo.ny-qc.ny*Jo.nx,_0e=qc.nx*Jo.nx-qc.ny*-Jo.ny,Ku=Math.asin(Math.max(-1,Math.min(1,A0e))),Math.abs(Ku)<1e-6){HP=r.x,WP=r.y,Bp=G1=0;return}Fp=1,gS=!1,_0e<0?Ku<0?Ku=Math.PI+Ku:(Ku=Math.PI-Ku,Fp=-1,gS=!0):Ku>0&&(Fp=-1,gS=!0),r.radius!==void 0?G1=r.radius:G1=i,Mp=Ku/2,aS=Math.min(qc.len/2,Jo.len/2),a?(Wc=Math.abs(Math.cos(Mp)*G1/Math.sin(Mp)),Wc>aS?(Wc=aS,Bp=Math.abs(Wc*Math.sin(Mp)/Math.cos(Mp))):Bp=G1):(Wc=Math.min(aS,G1),Bp=Math.abs(Wc*Math.sin(Mp)/Math.cos(Mp))),qP=r.x+Jo.nx*Wc,YP=r.y+Jo.ny*Wc,HP=qP-Jo.ny*Bp*Fp,WP=YP+Jo.nx*Bp*Fp,cge=r.x+qc.nx*Wc,uge=r.y+qc.ny*Wc,D0e=r},"calcCornerArc");o(hge,"drawPreparedRoundCorner");o(vB,"getRoundCorner");Va={};Va.findMidptPtsEtc=function(t,e){var r=e.posPts,n=e.intersectionPts,i=e.vectorNormInverse,a,s=t.pstyle("source-endpoint"),l=t.pstyle("target-endpoint"),u=s.units!=null&&l.units!=null,h=o(function(T,E,A,S){var _=S-E,I=A-T,D=Math.sqrt(I*I+_*_);return{x:-_/D,y:I/D}},"recalcVectorNormInverse"),f=t.pstyle("edge-distances").value;switch(f){case"node-position":a=r;break;case"intersection":a=n;break;case"endpoints":{if(u){var d=this.manualEndptToPx(t.source()[0],s),p=_i(d,2),m=p[0],g=p[1],y=this.manualEndptToPx(t.target()[0],l),v=_i(y,2),x=v[0],b=v[1],w={x1:m,y1:g,x2:x,y2:b};i=h(m,g,x,b),a=w}else un("Edge ".concat(t.id()," has edge-distances:endpoints specified without manual endpoints specified via source-endpoint and target-endpoint. Falling back on edge-distances:intersection (default).")),a=n;break}}return{midptPts:a,vectorNormInverse:i}};Va.findHaystackPoints=function(t){for(var e=0;e0?Math.max(q-pe,0):Math.min(q+pe,0)},"subDWH"),L=k(I,S),R=k(D,_),O=!1;b===h?x=Math.abs(L)>Math.abs(R)?i:n:b===u||b===l?(x=n,O=!0):(b===a||b===s)&&(x=i,O=!0);var M=x===n,B=M?R:L,F=M?D:I,P=mme(F),z=!1;!(O&&(C||E))&&(b===l&&F<0||b===u&&F>0||b===a&&F>0||b===s&&F<0)&&(P*=-1,B=P*Math.abs(B),z=!0);var $;if(C){var H=T<0?1+T:T;$=H*B}else{var Q=T<0?B:0;$=Q+T*P}var j=o(function(q){return Math.abs(q)=Math.abs(B)},"getIsTooClose"),ie=j($),ne=j(Math.abs(B)-Math.abs($)),le=ie||ne;if(le&&!z)if(M){var he=Math.abs(F)<=p/2,K=Math.abs(I)<=m/2;if(he){var X=(f.x1+f.x2)/2,te=f.y1,J=f.y2;r.segpts=[X,te,X,J]}else if(K){var se=(f.y1+f.y2)/2,ue=f.x1,Z=f.x2;r.segpts=[ue,se,Z,se]}else r.segpts=[f.x1,f.y2]}else{var Se=Math.abs(F)<=d/2,ce=Math.abs(D)<=g/2;if(Se){var ae=(f.y1+f.y2)/2,Oe=f.x1,ge=f.x2;r.segpts=[Oe,ae,ge,ae]}else if(ce){var ze=(f.x1+f.x2)/2,He=f.y1,$e=f.y2;r.segpts=[ze,He,ze,$e]}else r.segpts=[f.x2,f.y1]}else if(M){var Re=f.y1+$+(v?p/2*P:0),Ie=f.x1,be=f.x2;r.segpts=[Ie,Re,be,Re]}else{var W=f.x1+$+(v?d/2*P:0),de=f.y1,re=f.y2;r.segpts=[W,de,W,re]}if(r.isRound){var oe=t.pstyle("taxi-radius").value,V=t.pstyle("radius-type").value[0]==="arc-radius";r.radii=new Array(r.segpts.length/2).fill(oe),r.isArcRadius=new Array(r.segpts.length/2).fill(V)}};Va.tryToCorrectInvalidPoints=function(t,e){var r=t._private.rscratch;if(r.edgeType==="bezier"){var n=e.srcPos,i=e.tgtPos,a=e.srcW,s=e.srcH,l=e.tgtW,u=e.tgtH,h=e.srcShape,f=e.tgtShape,d=e.srcCornerRadius,p=e.tgtCornerRadius,m=e.srcRs,g=e.tgtRs,y=!Ct(r.startX)||!Ct(r.startY),v=!Ct(r.arrowStartX)||!Ct(r.arrowStartY),x=!Ct(r.endX)||!Ct(r.endY),b=!Ct(r.arrowEndX)||!Ct(r.arrowEndY),w=3,C=this.getArrowWidth(t.pstyle("width").pfValue,t.pstyle("arrow-scale").value)*this.arrowShapeWidth,T=w*C,E=Gp({x:r.ctrlpts[0],y:r.ctrlpts[1]},{x:r.startX,y:r.startY}),A=ER.poolIndex()){var O=L;L=R,R=O}var M=_.srcPos=L.position(),B=_.tgtPos=R.position(),F=_.srcW=L.outerWidth(),P=_.srcH=L.outerHeight(),z=_.tgtW=R.outerWidth(),$=_.tgtH=R.outerHeight(),H=_.srcShape=r.nodeShapes[e.getNodeShape(L)],Q=_.tgtShape=r.nodeShapes[e.getNodeShape(R)],j=_.srcCornerRadius=L.pstyle("corner-radius").value==="auto"?"auto":L.pstyle("corner-radius").pfValue,ie=_.tgtCornerRadius=R.pstyle("corner-radius").value==="auto"?"auto":R.pstyle("corner-radius").pfValue,ne=_.tgtRs=R._private.rscratch,le=_.srcRs=L._private.rscratch;_.dirCounts={north:0,west:0,south:0,east:0,northwest:0,southwest:0,northeast:0,southeast:0};for(var he=0;he<_.eles.length;he++){var K=_.eles[he],X=K[0]._private.rscratch,te=K.pstyle("curve-style").value,J=te==="unbundled-bezier"||te.endsWith("segments")||te.endsWith("taxi"),se=!L.same(K.source());if(!_.calculatedIntersection&&L!==R&&(_.hasBezier||_.hasUnbundled)){_.calculatedIntersection=!0;var ue=H.intersectLine(M.x,M.y,F,P,B.x,B.y,0,j,le),Z=_.srcIntn=ue,Se=Q.intersectLine(B.x,B.y,z,$,M.x,M.y,0,ie,ne),ce=_.tgtIntn=Se,ae=_.intersectionPts={x1:ue[0],x2:Se[0],y1:ue[1],y2:Se[1]},Oe=_.posPts={x1:M.x,x2:B.x,y1:M.y,y2:B.y},ge=Se[1]-ue[1],ze=Se[0]-ue[0],He=Math.sqrt(ze*ze+ge*ge),$e=_.vector={x:ze,y:ge},Re=_.vectorNorm={x:$e.x/He,y:$e.y/He},Ie={x:-Re.y,y:Re.x};_.nodesOverlap=!Ct(He)||Q.checkPoint(ue[0],ue[1],0,z,$,B.x,B.y,ie,ne)||H.checkPoint(Se[0],Se[1],0,F,P,M.x,M.y,j,le),_.vectorNormInverse=Ie,I={nodesOverlap:_.nodesOverlap,dirCounts:_.dirCounts,calculatedIntersection:!0,hasBezier:_.hasBezier,hasUnbundled:_.hasUnbundled,eles:_.eles,srcPos:B,srcRs:ne,tgtPos:M,tgtRs:le,srcW:z,srcH:$,tgtW:F,tgtH:P,srcIntn:ce,tgtIntn:Z,srcShape:Q,tgtShape:H,posPts:{x1:Oe.x2,y1:Oe.y2,x2:Oe.x1,y2:Oe.y1},intersectionPts:{x1:ae.x2,y1:ae.y2,x2:ae.x1,y2:ae.y1},vector:{x:-$e.x,y:-$e.y},vectorNorm:{x:-Re.x,y:-Re.y},vectorNormInverse:{x:-Ie.x,y:-Ie.y}}}var be=se?I:_;X.nodesOverlap=be.nodesOverlap,X.srcIntn=be.srcIntn,X.tgtIntn=be.tgtIntn,X.isRound=te.startsWith("round"),i&&(L.isParent()||L.isChild()||R.isParent()||R.isChild())&&(L.parents().anySame(R)||R.parents().anySame(L)||L.same(R)&&L.isParent())?e.findCompoundLoopPoints(K,be,he,J):L===R?e.findLoopPoints(K,be,he,J):te.endsWith("segments")?e.findSegmentsPoints(K,be):te.endsWith("taxi")?e.findTaxiPoints(K,be):te==="straight"||!J&&_.eles.length%2===1&&he===Math.floor(_.eles.length/2)?e.findStraightEdgePoints(K):e.findBezierPoints(K,be,he,J,se),e.findEndpoints(K),e.tryToCorrectInvalidPoints(K,be),e.checkForInvalidEdgeWarning(K),e.storeAllpts(K),e.storeEdgeProjections(K),e.calculateArrowAngles(K),e.recalculateEdgeLabelProjections(K),e.calculateLabelAngles(K)}},"_loop"),T=0;T0){var J=a,se=Op(J,U1(r)),ue=Op(J,U1(te)),Z=se;if(ue2){var Se=Op(J,{x:te[2],y:te[3]});Se0){var re=s,oe=Op(re,U1(r)),V=Op(re,U1(de)),xe=oe;if(V2){var q=Op(re,{x:de[2],y:de[3]});q=g||A){v={cp:C,segment:E};break}}if(v)break}var S=v.cp,_=v.segment,I=(g-x)/_.length,D=_.t1-_.t0,k=m?_.t0+D*I:_.t1-D*I;k=Yb(0,k,1),e=W1(S.p0,S.p1,S.p2,k),p=DQe(S.p0,S.p1,S.p2,k);break}case"straight":case"segments":case"haystack":{for(var L=0,R,O,M,B,F=n.allpts.length,P=0;P+3=g));P+=2);var z=g-O,$=z/R;$=Yb(0,$,1),e=Iqe(M,B,$),p=pge(M,B);break}}s("labelX",d,e.x),s("labelY",d,e.y),s("labelAutoAngle",d,p)}},"calculateEndProjection");h("source"),h("target"),this.applyLabelDimensions(t)}};Kc.applyLabelDimensions=function(t){this.applyPrefixedLabelDimensions(t),t.isEdge()&&(this.applyPrefixedLabelDimensions(t,"source"),this.applyPrefixedLabelDimensions(t,"target"))};Kc.applyPrefixedLabelDimensions=function(t,e){var r=t._private,n=this.getLabelText(t,e),i=this.calculateLabelDimensions(t,n),a=t.pstyle("line-height").pfValue,s=t.pstyle("text-wrap").strValue,l=Gl(r.rscratch,"labelWrapCachedLines",e)||[],u=s!=="wrap"?1:Math.max(l.length,1),h=i.height/u,f=h*a,d=i.width,p=i.height+(u-1)*(a-1)*h;kf(r.rstyle,"labelWidth",e,d),kf(r.rscratch,"labelWidth",e,d),kf(r.rstyle,"labelHeight",e,p),kf(r.rscratch,"labelHeight",e,p),kf(r.rscratch,"labelLineHeight",e,f)};Kc.getLabelText=function(t,e){var r=t._private,n=e?e+"-":"",i=t.pstyle(n+"label").strValue,a=t.pstyle("text-transform").value,s=o(function(Q,j){return j?(kf(r.rscratch,Q,e,j),j):Gl(r.rscratch,Q,e)},"rscratch");if(!i)return"";a=="none"||(a=="uppercase"?i=i.toUpperCase():a=="lowercase"&&(i=i.toLowerCase()));var l=t.pstyle("text-wrap").value;if(l==="wrap"){var u=s("labelKey");if(u!=null&&s("labelWrapKey")===u)return s("labelWrapCachedText");for(var h="\u200B",f=i.split(` -`),d=t.pstyle("text-max-width").pfValue,p=t.pstyle("text-overflow-wrap").value,m=p==="anywhere",g=[],y=/[\s\u200b]+|$/g,v=0;vd){var T=x.matchAll(y),E="",A=0,S=mo(T),_;try{for(S.s();!(_=S.n()).done;){var I=_.value,D=I[0],k=x.substring(A,I.index);A=I.index+D.length;var L=E.length===0?k:E+k+D,R=this.calculateLabelDimensions(t,L),O=R.width;O<=d?E+=k+D:(E&&g.push(E),E=k+D)}}catch(H){S.e(H)}finally{S.f()}E.match(/^[\s\u200b]+$/)||g.push(E)}else g.push(x)}s("labelWrapCachedLines",g),i=s("labelWrapCachedText",g.join(` -`)),s("labelWrapKey",u)}else if(l==="ellipsis"){var M=t.pstyle("text-max-width").pfValue,B="",F="\u2026",P=!1;if(this.calculateLabelDimensions(t,i).widthM)break;B+=i[z],z===i.length-1&&(P=!0)}return P||(B+=F),B}return i};Kc.getLabelJustification=function(t){var e=t.pstyle("text-justification").strValue,r=t.pstyle("text-halign").strValue;if(e==="auto")if(t.isNode())switch(r){case"left":return"right";case"right":return"left";default:return"center"}else return"center";else return e};Kc.calculateLabelDimensions=function(t,e){var r=this,n=r.cy.window(),i=n.document,a=_f(e,t._private.labelDimsKey),s=r.labelDimCache||(r.labelDimCache=[]),l=s[a];if(l!=null)return l;var u=0,h=t.pstyle("font-style").strValue,f=t.pstyle("font-size").pfValue,d=t.pstyle("font-family").strValue,p=t.pstyle("font-weight").strValue,m=this.labelCalcCanvas,g=this.labelCalcCanvasContext;if(!m){m=this.labelCalcCanvas=i.createElement("canvas"),g=this.labelCalcCanvasContext=m.getContext("2d");var y=m.style;y.position="absolute",y.left="-9999px",y.top="-9999px",y.zIndex="-1",y.visibility="hidden",y.pointerEvents="none"}g.font="".concat(h," ").concat(p," ").concat(f,"px ").concat(d);for(var v=0,x=0,b=e.split(` -`),w=0;w1&&arguments[1]!==void 0?arguments[1]:!0;if(e.merge(s),l)for(var u=0;u=t.desktopTapThreshold2}var ot=a(W);at&&(t.hoverData.tapholdCancelled=!0);var Yt=o(function(){var Tt=t.hoverData.dragDelta=t.hoverData.dragDelta||[];Tt.length===0?(Tt.push(De[0]),Tt.push(De[1])):(Tt[0]+=De[0],Tt[1]+=De[1])},"updateDragDelta");re=!0,i(_e,["mousemove","vmousemove","tapdrag"],W,{x:q[0],y:q[1]});var bt=o(function(){t.data.bgActivePosistion=void 0,t.hoverData.selecting||oe.emit({originalEvent:W,type:"boxstart",position:{x:q[0],y:q[1]}}),Pe[4]=1,t.hoverData.selecting=!0,t.redrawHint("select",!0),t.redraw()},"goIntoBoxMode");if(t.hoverData.which===3){if(at){var Mt={originalEvent:W,type:"cxtdrag",position:{x:q[0],y:q[1]}};Ve?Ve.emit(Mt):oe.emit(Mt),t.hoverData.cxtDragged=!0,(!t.hoverData.cxtOver||_e!==t.hoverData.cxtOver)&&(t.hoverData.cxtOver&&t.hoverData.cxtOver.emit({originalEvent:W,type:"cxtdragout",position:{x:q[0],y:q[1]}}),t.hoverData.cxtOver=_e,_e&&_e.emit({originalEvent:W,type:"cxtdragover",position:{x:q[0],y:q[1]}}))}}else if(t.hoverData.dragging){if(re=!0,oe.panningEnabled()&&oe.userPanningEnabled()){var xt;if(t.hoverData.justStartedPan){var ut=t.hoverData.mdownPos;xt={x:(q[0]-ut[0])*V,y:(q[1]-ut[1])*V},t.hoverData.justStartedPan=!1}else xt={x:De[0]*V,y:De[1]*V};oe.panBy(xt),oe.emit("dragpan"),t.hoverData.dragged=!0}q=t.projectIntoViewport(W.clientX,W.clientY)}else if(Pe[4]==1&&(Ve==null||Ve.pannable())){if(at){if(!t.hoverData.dragging&&oe.boxSelectionEnabled()&&(ot||!oe.panningEnabled()||!oe.userPanningEnabled()))bt();else if(!t.hoverData.selecting&&oe.panningEnabled()&&oe.userPanningEnabled()){var Et=s(Ve,t.hoverData.downs);Et&&(t.hoverData.dragging=!0,t.hoverData.justStartedPan=!0,Pe[4]=0,t.data.bgActivePosistion=U1(pe),t.redrawHint("select",!0),t.redraw())}Ve&&Ve.pannable()&&Ve.active()&&Ve.unactivate()}}else{if(Ve&&Ve.pannable()&&Ve.active()&&Ve.unactivate(),(!Ve||!Ve.grabbed())&&_e!=we&&(we&&i(we,["mouseout","tapdragout"],W,{x:q[0],y:q[1]}),_e&&i(_e,["mouseover","tapdragover"],W,{x:q[0],y:q[1]}),t.hoverData.last=_e),Ve)if(at){if(oe.boxSelectionEnabled()&&ot)Ve&&Ve.grabbed()&&(x(qe),Ve.emit("freeon"),qe.emit("free"),t.dragData.didDrag&&(Ve.emit("dragfreeon"),qe.emit("dragfree"))),bt();else if(Ve&&Ve.grabbed()&&t.nodeIsDraggable(Ve)){var ft=!t.dragData.didDrag;ft&&t.redrawHint("eles",!0),t.dragData.didDrag=!0,t.hoverData.draggingEles||y(qe,{inDragLayer:!0});var yt={x:0,y:0};if(Ct(De[0])&&Ct(De[1])&&(yt.x+=De[0],yt.y+=De[1],ft)){var nt=t.hoverData.dragDelta;nt&&Ct(nt[0])&&Ct(nt[1])&&(yt.x+=nt[0],yt.y+=nt[1])}t.hoverData.draggingEles=!0,qe.silentShift(yt).emit("position drag"),t.redrawHint("drag",!0),t.redraw()}}else Yt();re=!0}if(Pe[2]=q[0],Pe[3]=q[1],re)return W.stopPropagation&&W.stopPropagation(),W.preventDefault&&W.preventDefault(),!1}},"mousemoveHandler"),!1);var k,L,R;t.registerBinding(e,"mouseup",o(function(W){if(!(t.hoverData.which===1&&W.which!==1&&t.hoverData.capture)){var de=t.hoverData.capture;if(de){t.hoverData.capture=!1;var re=t.cy,oe=t.projectIntoViewport(W.clientX,W.clientY),V=t.selection,xe=t.findNearestElement(oe[0],oe[1],!0,!1),q=t.dragData.possibleDragElements,pe=t.hoverData.down,ve=a(W);if(t.data.bgActivePosistion&&(t.redrawHint("select",!0),t.redraw()),t.hoverData.tapholdCancelled=!0,t.data.bgActivePosistion=void 0,pe&&pe.unactivate(),t.hoverData.which===3){var Pe={originalEvent:W,type:"cxttapend",position:{x:oe[0],y:oe[1]}};if(pe?pe.emit(Pe):re.emit(Pe),!t.hoverData.cxtDragged){var _e={originalEvent:W,type:"cxttap",position:{x:oe[0],y:oe[1]}};pe?pe.emit(_e):re.emit(_e)}t.hoverData.cxtDragged=!1,t.hoverData.which=null}else if(t.hoverData.which===1){if(i(xe,["mouseup","tapend","vmouseup"],W,{x:oe[0],y:oe[1]}),!t.dragData.didDrag&&!t.hoverData.dragged&&!t.hoverData.selecting&&!t.hoverData.isOverThresholdDrag&&(i(pe,["click","tap","vclick"],W,{x:oe[0],y:oe[1]}),L=!1,W.timeStamp-R<=re.multiClickDebounceTime()?(k&&clearTimeout(k),L=!0,R=null,i(pe,["dblclick","dbltap","vdblclick"],W,{x:oe[0],y:oe[1]})):(k=setTimeout(function(){L||i(pe,["oneclick","onetap","voneclick"],W,{x:oe[0],y:oe[1]})},re.multiClickDebounceTime()),R=W.timeStamp)),pe==null&&!t.dragData.didDrag&&!t.hoverData.selecting&&!t.hoverData.dragged&&!a(W)&&(re.$(r).unselect(["tapunselect"]),q.length>0&&t.redrawHint("eles",!0),t.dragData.possibleDragElements=q=re.collection()),xe==pe&&!t.dragData.didDrag&&!t.hoverData.selecting&&xe!=null&&xe._private.selectable&&(t.hoverData.dragging||(re.selectionType()==="additive"||ve?xe.selected()?xe.unselect(["tapunselect"]):xe.select(["tapselect"]):ve||(re.$(r).unmerge(xe).unselect(["tapunselect"]),xe.select(["tapselect"]))),t.redrawHint("eles",!0)),t.hoverData.selecting){var we=re.collection(t.getAllInBox(V[0],V[1],V[2],V[3]));t.redrawHint("select",!0),we.length>0&&t.redrawHint("eles",!0),re.emit({type:"boxend",originalEvent:W,position:{x:oe[0],y:oe[1]}});var Ve=o(function(at){return at.selectable()&&!at.selected()},"eleWouldBeSelected");re.selectionType()==="additive"||ve||re.$(r).unmerge(we).unselect(),we.emit("box").stdFilter(Ve).select().emit("boxselect"),t.redraw()}if(t.hoverData.dragging&&(t.hoverData.dragging=!1,t.redrawHint("select",!0),t.redrawHint("eles",!0),t.redraw()),!V[4]){t.redrawHint("drag",!0),t.redrawHint("eles",!0);var De=pe&&pe.grabbed();x(q),De&&(pe.emit("freeon"),q.emit("free"),t.dragData.didDrag&&(pe.emit("dragfreeon"),q.emit("dragfree")))}}V[4]=0,t.hoverData.down=null,t.hoverData.cxtStarted=!1,t.hoverData.draggingEles=!1,t.hoverData.selecting=!1,t.hoverData.isOverThresholdDrag=!1,t.dragData.didDrag=!1,t.hoverData.dragged=!1,t.hoverData.dragDelta=[],t.hoverData.mdownPos=null,t.hoverData.mdownGPos=null,t.hoverData.which=null}}},"mouseupHandler"),!1);var O=o(function(W){if(!t.scrollingPage){var de=t.cy,re=de.zoom(),oe=de.pan(),V=t.projectIntoViewport(W.clientX,W.clientY),xe=[V[0]*re+oe.x,V[1]*re+oe.y];if(t.hoverData.draggingEles||t.hoverData.dragging||t.hoverData.cxtStarted||_()){W.preventDefault();return}if(de.panningEnabled()&&de.userPanningEnabled()&&de.zoomingEnabled()&&de.userZoomingEnabled()){W.preventDefault(),t.data.wheelZooming=!0,clearTimeout(t.data.wheelTimeout),t.data.wheelTimeout=setTimeout(function(){t.data.wheelZooming=!1,t.redrawHint("eles",!0),t.redraw()},150);var q;W.deltaY!=null?q=W.deltaY/-250:W.wheelDeltaY!=null?q=W.wheelDeltaY/1e3:q=W.wheelDelta/1e3,q=q*t.wheelSensitivity;var pe=W.deltaMode===1;pe&&(q*=33);var ve=de.zoom()*Math.pow(10,q);W.type==="gesturechange"&&(ve=t.gestureStartZoom*W.scale),de.zoom({level:ve,renderedPosition:{x:xe[0],y:xe[1]}}),de.emit(W.type==="gesturechange"?"pinchzoom":"scrollzoom")}}},"wheelHandler");t.registerBinding(t.container,"wheel",O,!0),t.registerBinding(e,"scroll",o(function(W){t.scrollingPage=!0,clearTimeout(t.scrollingPageTimeout),t.scrollingPageTimeout=setTimeout(function(){t.scrollingPage=!1},250)},"scrollHandler"),!0),t.registerBinding(t.container,"gesturestart",o(function(W){t.gestureStartZoom=t.cy.zoom(),t.hasTouchStarted||W.preventDefault()},"gestureStartHandler"),!0),t.registerBinding(t.container,"gesturechange",function(be){t.hasTouchStarted||O(be)},!0),t.registerBinding(t.container,"mouseout",o(function(W){var de=t.projectIntoViewport(W.clientX,W.clientY);t.cy.emit({originalEvent:W,type:"mouseout",position:{x:de[0],y:de[1]}})},"mouseOutHandler"),!1),t.registerBinding(t.container,"mouseover",o(function(W){var de=t.projectIntoViewport(W.clientX,W.clientY);t.cy.emit({originalEvent:W,type:"mouseover",position:{x:de[0],y:de[1]}})},"mouseOverHandler"),!1);var M,B,F,P,z,$,H,Q,j,ie,ne,le,he,K=o(function(W,de,re,oe){return Math.sqrt((re-W)*(re-W)+(oe-de)*(oe-de))},"distance"),X=o(function(W,de,re,oe){return(re-W)*(re-W)+(oe-de)*(oe-de)},"distanceSq"),te;t.registerBinding(t.container,"touchstart",te=o(function(W){if(t.hasTouchStarted=!0,!!I(W)){w(),t.touchData.capture=!0,t.data.bgActivePosistion=void 0;var de=t.cy,re=t.touchData.now,oe=t.touchData.earlier;if(W.touches[0]){var V=t.projectIntoViewport(W.touches[0].clientX,W.touches[0].clientY);re[0]=V[0],re[1]=V[1]}if(W.touches[1]){var V=t.projectIntoViewport(W.touches[1].clientX,W.touches[1].clientY);re[2]=V[0],re[3]=V[1]}if(W.touches[2]){var V=t.projectIntoViewport(W.touches[2].clientX,W.touches[2].clientY);re[4]=V[0],re[5]=V[1]}if(W.touches[1]){t.touchData.singleTouchMoved=!0,x(t.dragData.touchDragEles);var xe=t.findContainerClientCoords();j=xe[0],ie=xe[1],ne=xe[2],le=xe[3],M=W.touches[0].clientX-j,B=W.touches[0].clientY-ie,F=W.touches[1].clientX-j,P=W.touches[1].clientY-ie,he=0<=M&&M<=ne&&0<=F&&F<=ne&&0<=B&&B<=le&&0<=P&&P<=le;var q=de.pan(),pe=de.zoom();z=K(M,B,F,P),$=X(M,B,F,P),H=[(M+F)/2,(B+P)/2],Q=[(H[0]-q.x)/pe,(H[1]-q.y)/pe];var ve=200,Pe=ve*ve;if($=1){for(var st=t.touchData.startPosition=[null,null,null,null,null,null],Ue=0;Ue=t.touchTapThreshold2}if(de&&t.touchData.cxt){W.preventDefault();var st=W.touches[0].clientX-j,Ue=W.touches[0].clientY-ie,ct=W.touches[1].clientX-j,We=W.touches[1].clientY-ie,ot=X(st,Ue,ct,We),Yt=ot/$,bt=150,Mt=bt*bt,xt=1.5,ut=xt*xt;if(Yt>=ut||ot>=Mt){t.touchData.cxt=!1,t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);var Et={originalEvent:W,type:"cxttapend",position:{x:V[0],y:V[1]}};t.touchData.start?(t.touchData.start.unactivate().emit(Et),t.touchData.start=null):oe.emit(Et)}}if(de&&t.touchData.cxt){var Et={originalEvent:W,type:"cxtdrag",position:{x:V[0],y:V[1]}};t.data.bgActivePosistion=void 0,t.redrawHint("select",!0),t.touchData.start?t.touchData.start.emit(Et):oe.emit(Et),t.touchData.start&&(t.touchData.start._private.grabbed=!1),t.touchData.cxtDragged=!0;var ft=t.findNearestElement(V[0],V[1],!0,!0);(!t.touchData.cxtOver||ft!==t.touchData.cxtOver)&&(t.touchData.cxtOver&&t.touchData.cxtOver.emit({originalEvent:W,type:"cxtdragout",position:{x:V[0],y:V[1]}}),t.touchData.cxtOver=ft,ft&&ft.emit({originalEvent:W,type:"cxtdragover",position:{x:V[0],y:V[1]}}))}else if(de&&W.touches[2]&&oe.boxSelectionEnabled())W.preventDefault(),t.data.bgActivePosistion=void 0,this.lastThreeTouch=+new Date,t.touchData.selecting||oe.emit({originalEvent:W,type:"boxstart",position:{x:V[0],y:V[1]}}),t.touchData.selecting=!0,t.touchData.didSelect=!0,re[4]=1,!re||re.length===0||re[0]===void 0?(re[0]=(V[0]+V[2]+V[4])/3,re[1]=(V[1]+V[3]+V[5])/3,re[2]=(V[0]+V[2]+V[4])/3+1,re[3]=(V[1]+V[3]+V[5])/3+1):(re[2]=(V[0]+V[2]+V[4])/3,re[3]=(V[1]+V[3]+V[5])/3),t.redrawHint("select",!0),t.redraw();else if(de&&W.touches[1]&&!t.touchData.didSelect&&oe.zoomingEnabled()&&oe.panningEnabled()&&oe.userZoomingEnabled()&&oe.userPanningEnabled()){W.preventDefault(),t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);var yt=t.dragData.touchDragEles;if(yt){t.redrawHint("drag",!0);for(var nt=0;nt0&&!t.hoverData.draggingEles&&!t.swipePanning&&t.data.bgActivePosistion!=null&&(t.data.bgActivePosistion=void 0,t.redrawHint("select",!0),t.redraw())}},"touchmoveHandler"),!1);var se;t.registerBinding(e,"touchcancel",se=o(function(W){var de=t.touchData.start;t.touchData.capture=!1,de&&de.unactivate()},"touchcancelHandler"));var ue,Z,Se,ce;if(t.registerBinding(e,"touchend",ue=o(function(W){var de=t.touchData.start,re=t.touchData.capture;if(re)W.touches.length===0&&(t.touchData.capture=!1),W.preventDefault();else return;var oe=t.selection;t.swipePanning=!1,t.hoverData.draggingEles=!1;var V=t.cy,xe=V.zoom(),q=t.touchData.now,pe=t.touchData.earlier;if(W.touches[0]){var ve=t.projectIntoViewport(W.touches[0].clientX,W.touches[0].clientY);q[0]=ve[0],q[1]=ve[1]}if(W.touches[1]){var ve=t.projectIntoViewport(W.touches[1].clientX,W.touches[1].clientY);q[2]=ve[0],q[3]=ve[1]}if(W.touches[2]){var ve=t.projectIntoViewport(W.touches[2].clientX,W.touches[2].clientY);q[4]=ve[0],q[5]=ve[1]}de&&de.unactivate();var Pe;if(t.touchData.cxt){if(Pe={originalEvent:W,type:"cxttapend",position:{x:q[0],y:q[1]}},de?de.emit(Pe):V.emit(Pe),!t.touchData.cxtDragged){var _e={originalEvent:W,type:"cxttap",position:{x:q[0],y:q[1]}};de?de.emit(_e):V.emit(_e)}t.touchData.start&&(t.touchData.start._private.grabbed=!1),t.touchData.cxt=!1,t.touchData.start=null,t.redraw();return}if(!W.touches[2]&&V.boxSelectionEnabled()&&t.touchData.selecting){t.touchData.selecting=!1;var we=V.collection(t.getAllInBox(oe[0],oe[1],oe[2],oe[3]));oe[0]=void 0,oe[1]=void 0,oe[2]=void 0,oe[3]=void 0,oe[4]=0,t.redrawHint("select",!0),V.emit({type:"boxend",originalEvent:W,position:{x:q[0],y:q[1]}});var Ve=o(function(Mt){return Mt.selectable()&&!Mt.selected()},"eleWouldBeSelected");we.emit("box").stdFilter(Ve).select().emit("boxselect"),we.nonempty()&&t.redrawHint("eles",!0),t.redraw()}if(de?.unactivate(),W.touches[2])t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);else if(!W.touches[1]){if(!W.touches[0]){if(!W.touches[0]){t.data.bgActivePosistion=void 0,t.redrawHint("select",!0);var De=t.dragData.touchDragEles;if(de!=null){var qe=de._private.grabbed;x(De),t.redrawHint("drag",!0),t.redrawHint("eles",!0),qe&&(de.emit("freeon"),De.emit("free"),t.dragData.didDrag&&(de.emit("dragfreeon"),De.emit("dragfree"))),i(de,["touchend","tapend","vmouseup","tapdragout"],W,{x:q[0],y:q[1]}),de.unactivate(),t.touchData.start=null}else{var at=t.findNearestElement(q[0],q[1],!0,!0);i(at,["touchend","tapend","vmouseup","tapdragout"],W,{x:q[0],y:q[1]})}var Rt=t.touchData.startPosition[0]-q[0],st=Rt*Rt,Ue=t.touchData.startPosition[1]-q[1],ct=Ue*Ue,We=st+ct,ot=We*xe*xe;t.touchData.singleTouchMoved||(de||V.$(":selected").unselect(["tapunselect"]),i(de,["tap","vclick"],W,{x:q[0],y:q[1]}),Z=!1,W.timeStamp-ce<=V.multiClickDebounceTime()?(Se&&clearTimeout(Se),Z=!0,ce=null,i(de,["dbltap","vdblclick"],W,{x:q[0],y:q[1]})):(Se=setTimeout(function(){Z||i(de,["onetap","voneclick"],W,{x:q[0],y:q[1]})},V.multiClickDebounceTime()),ce=W.timeStamp)),de!=null&&!t.dragData.didDrag&&de._private.selectable&&ot"u"){var ae=[],Oe=o(function(W){return{clientX:W.clientX,clientY:W.clientY,force:1,identifier:W.pointerId,pageX:W.pageX,pageY:W.pageY,radiusX:W.width/2,radiusY:W.height/2,screenX:W.screenX,screenY:W.screenY,target:W.target}},"makeTouch"),ge=o(function(W){return{event:W,touch:Oe(W)}},"makePointer"),ze=o(function(W){ae.push(ge(W))},"addPointer"),He=o(function(W){for(var de=0;de0)return H[0]}return null},"getCurveT"),g=Object.keys(p),y=0;y0?m:vme(a,s,e,r,n,i,l,u)},"intersectLine"),checkPoint:o(function(e,r,n,i,a,s,l,u){u=u==="auto"?Vp(i,a):u;var h=2*u;if(Zu(e,r,this.points,s,l,i,a-h,[0,-1],n)||Zu(e,r,this.points,s,l,i-h,a,[0,-1],n))return!0;var f=i/2+2*n,d=a/2+2*n,p=[s-f,l-d,s-f,l,s+f,l,s+f,l-d];return!!(Us(e,r,p)||$p(e,r,h,h,s+i/2-u,l+a/2-u,n)||$p(e,r,h,h,s-i/2+u,l+a/2-u,n))},"checkPoint")}};eh.registerNodeShapes=function(){var t=this.nodeShapes={},e=this;this.generateEllipse(),this.generatePolygon("triangle",gs(3,0)),this.generateRoundPolygon("round-triangle",gs(3,0)),this.generatePolygon("rectangle",gs(4,0)),t.square=t.rectangle,this.generateRoundRectangle(),this.generateCutRectangle(),this.generateBarrel(),this.generateBottomRoundrectangle();{var r=[0,1,1,0,0,-1,-1,0];this.generatePolygon("diamond",r),this.generateRoundPolygon("round-diamond",r)}this.generatePolygon("pentagon",gs(5,0)),this.generateRoundPolygon("round-pentagon",gs(5,0)),this.generatePolygon("hexagon",gs(6,0)),this.generateRoundPolygon("round-hexagon",gs(6,0)),this.generatePolygon("heptagon",gs(7,0)),this.generateRoundPolygon("round-heptagon",gs(7,0)),this.generatePolygon("octagon",gs(8,0)),this.generateRoundPolygon("round-octagon",gs(8,0));var n=new Array(20);{var i=PP(5,0),a=PP(5,Math.PI/5),s=.5*(3-Math.sqrt(5));s*=1.57;for(var l=0;l=e.deqFastCost*C)break}else if(h){if(b>=e.deqCost*m||b>=e.deqAvgCost*p)break}else if(w>=e.deqNoDrawCost*DP)break;var T=e.deq(n,v,y);if(T.length>0)for(var E=0;E0&&(e.onDeqd(n,g),!h&&e.shouldRedraw(n,g,v,y)&&a())},"dequeue"),l=e.priority||rB;i.beforeRender(s,l(n))}},"setupDequeueingImpl")},"setupDequeueing")},RQe=function(){function t(e){var r=arguments.length>1&&arguments[1]!==void 0?arguments[1]:bS;Mf(this,t),this.idsByKey=new Xc,this.keyForId=new Xc,this.cachesByLvl=new Xc,this.lvls=[],this.getKey=e,this.doesEleInvalidateKey=r}return o(t,"ElementTextureCacheLookup"),If(t,[{key:"getIdsFor",value:o(function(r){r==null&&ai("Can not get id list for null key");var n=this.idsByKey,i=this.idsByKey.get(r);return i||(i=new J1,n.set(r,i)),i},"getIdsFor")},{key:"addIdForKey",value:o(function(r,n){r!=null&&this.getIdsFor(r).add(n)},"addIdForKey")},{key:"deleteIdForKey",value:o(function(r,n){r!=null&&this.getIdsFor(r).delete(n)},"deleteIdForKey")},{key:"getNumberOfIdsForKey",value:o(function(r){return r==null?0:this.getIdsFor(r).size},"getNumberOfIdsForKey")},{key:"updateKeyMappingFor",value:o(function(r){var n=r.id(),i=this.keyForId.get(n),a=this.getKey(r);this.deleteIdForKey(i,n),this.addIdForKey(a,n),this.keyForId.set(n,a)},"updateKeyMappingFor")},{key:"deleteKeyMappingFor",value:o(function(r){var n=r.id(),i=this.keyForId.get(n);this.deleteIdForKey(i,n),this.keyForId.delete(n)},"deleteKeyMappingFor")},{key:"keyHasChangedFor",value:o(function(r){var n=r.id(),i=this.keyForId.get(n),a=this.getKey(r);return i!==a},"keyHasChangedFor")},{key:"isInvalid",value:o(function(r){return this.keyHasChangedFor(r)||this.doesEleInvalidateKey(r)},"isInvalid")},{key:"getCachesAt",value:o(function(r){var n=this.cachesByLvl,i=this.lvls,a=n.get(r);return a||(a=new Xc,n.set(r,a),i.push(r)),a},"getCachesAt")},{key:"getCache",value:o(function(r,n){return this.getCachesAt(n).get(r)},"getCache")},{key:"get",value:o(function(r,n){var i=this.getKey(r),a=this.getCache(i,n);return a!=null&&this.updateKeyMappingFor(r),a},"get")},{key:"getForCachedKey",value:o(function(r,n){var i=this.keyForId.get(r.id()),a=this.getCache(i,n);return a},"getForCachedKey")},{key:"hasCache",value:o(function(r,n){return this.getCachesAt(n).has(r)},"hasCache")},{key:"has",value:o(function(r,n){var i=this.getKey(r);return this.hasCache(i,n)},"has")},{key:"setCache",value:o(function(r,n,i){i.key=r,this.getCachesAt(n).set(r,i)},"setCache")},{key:"set",value:o(function(r,n,i){var a=this.getKey(r);this.setCache(a,n,i),this.updateKeyMappingFor(r)},"set")},{key:"deleteCache",value:o(function(r,n){this.getCachesAt(n).delete(r)},"deleteCache")},{key:"delete",value:o(function(r,n){var i=this.getKey(r);this.deleteCache(i,n)},"_delete")},{key:"invalidateKey",value:o(function(r){var n=this;this.lvls.forEach(function(i){return n.deleteCache(r,i)})},"invalidateKey")},{key:"invalidate",value:o(function(r){var n=r.id(),i=this.keyForId.get(n);this.deleteKeyMappingFor(r);var a=this.doesEleInvalidateKey(r);return a&&this.invalidateKey(i),a||this.getNumberOfIdsForKey(i)===0},"invalidate")}]),t}(),I0e=25,sS=50,yS=-4,XP=3,bge=7.99,NQe=8,MQe=1024,IQe=1024,OQe=1024,PQe=.2,BQe=.8,FQe=10,$Qe=.15,zQe=.1,GQe=.9,VQe=.9,UQe=100,HQe=1,H1={dequeue:"dequeue",downscale:"downscale",highQuality:"highQuality"},WQe=la({getKey:null,doesEleInvalidateKey:bS,drawElement:null,getBoundingBox:null,getRotationPoint:null,getRotationOffset:null,isVisible:ume,allowEdgeTxrCaching:!0,allowParentTxrCaching:!0}),Fb=o(function(e,r){var n=this;n.renderer=e,n.onDequeues=[];var i=WQe(r);rr(n,i),n.lookup=new RQe(i.getKey,i.doesEleInvalidateKey),n.setupDequeueing()},"ElementTextureCache"),qi=Fb.prototype;qi.reasons=H1;qi.getTextureQueue=function(t){var e=this;return e.eleImgCaches=e.eleImgCaches||{},e.eleImgCaches[t]=e.eleImgCaches[t]||[]};qi.getRetiredTextureQueue=function(t){var e=this,r=e.eleImgCaches.retired=e.eleImgCaches.retired||{},n=r[t]=r[t]||[];return n};qi.getElementQueue=function(){var t=this,e=t.eleCacheQueue=t.eleCacheQueue||new i4(function(r,n){return n.reqs-r.reqs});return e};qi.getElementKeyToQueue=function(){var t=this,e=t.eleKeyToCacheQueue=t.eleKeyToCacheQueue||{};return e};qi.getElement=function(t,e,r,n,i){var a=this,s=this.renderer,l=s.cy.zoom(),u=this.lookup;if(!e||e.w===0||e.h===0||isNaN(e.w)||isNaN(e.h)||!t.visible()||t.removed()||!a.allowEdgeTxrCaching&&t.isEdge()||!a.allowParentTxrCaching&&t.isParent())return null;if(n==null&&(n=Math.ceil(iB(l*r))),n=bge||n>XP)return null;var h=Math.pow(2,n),f=e.h*h,d=e.w*h,p=s.eleTextBiggerThanMin(t,h);if(!this.isVisible(t,p))return null;var m=u.get(t,n);if(m&&m.invalidated&&(m.invalidated=!1,m.texture.invalidatedWidth-=m.width),m)return m;var g;if(f<=I0e?g=I0e:f<=sS?g=sS:g=Math.ceil(f/sS)*sS,f>OQe||d>IQe)return null;var y=a.getTextureQueue(g),v=y[y.length-2],x=o(function(){return a.recycleTexture(g,d)||a.addTexture(g,d)},"addNewTxr");v||(v=y[y.length-1]),v||(v=x()),v.width-v.usedWidthn;D--)_=a.getElement(t,e,r,D,H1.downscale);I()}else return a.queueElement(t,E.level-1),E;else{var k;if(!w&&!C&&!T)for(var L=n-1;L>=yS;L--){var R=u.get(t,L);if(R){k=R;break}}if(b(k))return a.queueElement(t,n),k;v.context.translate(v.usedWidth,0),v.context.scale(h,h),this.drawElement(v.context,t,e,p,!1),v.context.scale(1/h,1/h),v.context.translate(-v.usedWidth,0)}return m={x:v.usedWidth,texture:v,level:n,scale:h,width:d,height:f,scaledLabelShown:p},v.usedWidth+=Math.ceil(d+NQe),v.eleCaches.push(m),u.set(t,n,m),a.checkTextureFullness(v),m};qi.invalidateElements=function(t){for(var e=0;e=PQe*t.width&&this.retireTexture(t)};qi.checkTextureFullness=function(t){var e=this,r=e.getTextureQueue(t.height);t.usedWidth/t.width>BQe&&t.fullnessChecks>=FQe?Df(r,t):t.fullnessChecks++};qi.retireTexture=function(t){var e=this,r=t.height,n=e.getTextureQueue(r),i=this.lookup;Df(n,t),t.retired=!0;for(var a=t.eleCaches,s=0;s=e)return s.retired=!1,s.usedWidth=0,s.invalidatedWidth=0,s.fullnessChecks=0,nB(s.eleCaches),s.context.setTransform(1,0,0,1,0,0),s.context.clearRect(0,0,s.width,s.height),Df(i,s),n.push(s),s}};qi.queueElement=function(t,e){var r=this,n=r.getElementQueue(),i=r.getElementKeyToQueue(),a=this.getKey(t),s=i[a];if(s)s.level=Math.max(s.level,e),s.eles.merge(t),s.reqs++,n.updateItem(s);else{var l={eles:t.spawn().merge(t),level:e,reqs:1,key:a};n.push(l),i[a]=l}};qi.dequeue=function(t){for(var e=this,r=e.getElementQueue(),n=e.getElementKeyToQueue(),i=[],a=e.lookup,s=0;s0;s++){var l=r.pop(),u=l.key,h=l.eles[0],f=a.hasCache(h,l.level);if(n[u]=null,f)continue;i.push(l);var d=e.getBoundingBox(h);e.getElement(h,d,t,l.level,H1.dequeue)}return i};qi.removeFromQueue=function(t){var e=this,r=e.getElementQueue(),n=e.getElementKeyToQueue(),i=this.getKey(t),a=n[i];a!=null&&(a.eles.length===1?(a.reqs=tB,r.updateItem(a),r.pop(),n[i]=null):a.eles.unmerge(t))};qi.onDequeue=function(t){this.onDequeues.push(t)};qi.offDequeue=function(t){Df(this.onDequeues,t)};qi.setupDequeueing=xge.setupDequeueing({deqRedrawThreshold:UQe,deqCost:$Qe,deqAvgCost:zQe,deqNoDrawCost:GQe,deqFastCost:VQe,deq:o(function(e,r,n){return e.dequeue(r,n)},"deq"),onDeqd:o(function(e,r){for(var n=0;n=YQe||r>_S)return null}n.validateLayersElesOrdering(r,t);var u=n.layersByLevel,h=Math.pow(2,r),f=u[r]=u[r]||[],d,p=n.levelIsComplete(r,t),m,g=o(function(){var I=o(function(O){if(n.validateLayersElesOrdering(O,t),n.levelIsComplete(O,t))return m=u[O],!0},"canUseAsTmpLvl"),D=o(function(O){if(!m)for(var M=r+O;zb<=M&&M<=_S&&!I(M);M+=O);},"checkLvls");D(1),D(-1);for(var k=f.length-1;k>=0;k--){var L=f[k];L.invalid&&Df(f,L)}},"checkTempLevels");if(!p)g();else return f;var y=o(function(){if(!d){d=Hs();for(var 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m=n.padding();a=n.width()+2*m,s=n.height()+2*m}l.colorFillStyle(r,f[0],f[1],f[2],h),l.nodeShapes[d].draw(r,i.x,i.y,a+u*2,s+u*2,p),r.fill()}}}},"drawNodeOverlayUnderlay");ly.drawNodeOverlay=Ege("overlay");ly.drawNodeUnderlay=Ege("underlay");ly.hasPie=function(t){return t=t[0],t._private.hasPie};ly.drawPie=function(t,e,r,n){e=e[0],n=n||e.position();var i=e.cy().style(),a=e.pstyle("pie-size"),s=n.x,l=n.y,u=e.width(),h=e.height(),f=Math.min(u,h)/2,d=0,p=this.usePaths();p&&(s=0,l=0),a.units==="%"?f=f*a.pfValue:a.pfValue!==void 0&&(f=a.pfValue/2);for(var m=1;m<=i.pieBackgroundN;m++){var g=e.pstyle("pie-"+m+"-background-size").value,y=e.pstyle("pie-"+m+"-background-color").value,v=e.pstyle("pie-"+m+"-background-opacity").value*r,x=g/100;x+d>1&&(x=1-d);var b=1.5*Math.PI+2*Math.PI*d,w=2*Math.PI*x,C=b+w;g===0||d>=1||d+x>1||(t.beginPath(),t.moveTo(s,l),t.arc(s,l,f,b,C),t.closePath(),this.colorFillStyle(t,y[0],y[1],y[2],v),t.fill(),d+=x)}};ys={},dZe=100;ys.getPixelRatio=function(){var t=this.data.contexts[0];if(this.forcedPixelRatio!=null)return this.forcedPixelRatio;var e=this.cy.window(),r=t.backingStorePixelRatio||t.webkitBackingStorePixelRatio||t.mozBackingStorePixelRatio||t.msBackingStorePixelRatio||t.oBackingStorePixelRatio||t.backingStorePixelRatio||1;return(e.devicePixelRatio||1)/r};ys.paintCache=function(t){for(var e=this.paintCaches=this.paintCaches||[],r=!0,n,i=0;ie.minMbLowQualFrames&&(e.motionBlurPxRatio=e.mbPxRBlurry)),e.clearingMotionBlur&&(e.motionBlurPxRatio=1),e.textureDrawLastFrame&&!d&&(f[e.NODE]=!0,f[e.SELECT_BOX]=!0);var b=r.style(),w=r.zoom(),C=s!==void 0?s:w,T=r.pan(),E={x:T.x,y:T.y},A={zoom:w,pan:{x:T.x,y:T.y}},S=e.prevViewport,_=S===void 0||A.zoom!==S.zoom||A.pan.x!==S.pan.x||A.pan.y!==S.pan.y;!_&&!(y&&!g)&&(e.motionBlurPxRatio=1),l&&(E=l),C*=u,E.x*=u,E.y*=u;var I=e.getCachedZSortedEles();function D(K,X,te,J,se){var ue=K.globalCompositeOperation;K.globalCompositeOperation="destination-out",e.colorFillStyle(K,255,255,255,e.motionBlurTransparency),K.fillRect(X,te,J,se),K.globalCompositeOperation=ue}o(D,"mbclear");function k(K,X){var te,J,se,ue;!e.clearingMotionBlur&&(K===h.bufferContexts[e.MOTIONBLUR_BUFFER_NODE]||K===h.bufferContexts[e.MOTIONBLUR_BUFFER_DRAG])?(te={x:T.x*m,y:T.y*m},J=w*m,se=e.canvasWidth*m,ue=e.canvasHeight*m):(te=E,J=C,se=e.canvasWidth,ue=e.canvasHeight),K.setTransform(1,0,0,1,0,0),X==="motionBlur"?D(K,0,0,se,ue):!n&&(X===void 0||X)&&K.clearRect(0,0,se,ue),i||(K.translate(te.x,te.y),K.scale(J,J)),l&&K.translate(l.x,l.y),s&&K.scale(s,s)}if(o(k,"setContextTransform"),d||(e.textureDrawLastFrame=!1),d){if(e.textureDrawLastFrame=!0,!e.textureCache){e.textureCache={},e.textureCache.bb=r.mutableElements().boundingBox(),e.textureCache.texture=e.data.bufferCanvases[e.TEXTURE_BUFFER];var L=e.data.bufferContexts[e.TEXTURE_BUFFER];L.setTransform(1,0,0,1,0,0),L.clearRect(0,0,e.canvasWidth*e.textureMult,e.canvasHeight*e.textureMult),e.render({forcedContext:L,drawOnlyNodeLayer:!0,forcedPxRatio:u*e.textureMult});var A=e.textureCache.viewport={zoom:r.zoom(),pan:r.pan(),width:e.canvasWidth,height:e.canvasHeight};A.mpan={x:(0-A.pan.x)/A.zoom,y:(0-A.pan.y)/A.zoom}}f[e.DRAG]=!1,f[e.NODE]=!1;var R=h.contexts[e.NODE],O=e.textureCache.texture,A=e.textureCache.viewport;R.setTransform(1,0,0,1,0,0),p?D(R,0,0,A.width,A.height):R.clearRect(0,0,A.width,A.height);var M=b.core("outside-texture-bg-color").value,B=b.core("outside-texture-bg-opacity").value;e.colorFillStyle(R,M[0],M[1],M[2],B),R.fillRect(0,0,A.width,A.height);var w=r.zoom();k(R,!1),R.clearRect(A.mpan.x,A.mpan.y,A.width/A.zoom/u,A.height/A.zoom/u),R.drawImage(O,A.mpan.x,A.mpan.y,A.width/A.zoom/u,A.height/A.zoom/u)}else e.textureOnViewport&&!n&&(e.textureCache=null);var F=r.extent(),P=e.pinching||e.hoverData.dragging||e.swipePanning||e.data.wheelZooming||e.hoverData.draggingEles||e.cy.animated(),z=e.hideEdgesOnViewport&&P,$=[];if($[e.NODE]=!f[e.NODE]&&p&&!e.clearedForMotionBlur[e.NODE]||e.clearingMotionBlur,$[e.NODE]&&(e.clearedForMotionBlur[e.NODE]=!0),$[e.DRAG]=!f[e.DRAG]&&p&&!e.clearedForMotionBlur[e.DRAG]||e.clearingMotionBlur,$[e.DRAG]&&(e.clearedForMotionBlur[e.DRAG]=!0),f[e.NODE]||i||a||$[e.NODE]){var H=p&&!$[e.NODE]&&m!==1,R=n||(H?e.data.bufferContexts[e.MOTIONBLUR_BUFFER_NODE]:h.contexts[e.NODE]),Q=p&&!H?"motionBlur":void 0;k(R,Q),z?e.drawCachedNodes(R,I.nondrag,u,F):e.drawLayeredElements(R,I.nondrag,u,F),e.debug&&e.drawDebugPoints(R,I.nondrag),!i&&!p&&(f[e.NODE]=!1)}if(!a&&(f[e.DRAG]||i||$[e.DRAG])){var H=p&&!$[e.DRAG]&&m!==1,R=n||(H?e.data.bufferContexts[e.MOTIONBLUR_BUFFER_DRAG]:h.contexts[e.DRAG]);k(R,p&&!H?"motionBlur":void 0),z?e.drawCachedNodes(R,I.drag,u,F):e.drawCachedElements(R,I.drag,u,F),e.debug&&e.drawDebugPoints(R,I.drag),!i&&!p&&(f[e.DRAG]=!1)}if(this.drawSelectionRectangle(t,k),p&&m!==1){var j=h.contexts[e.NODE],ie=e.data.bufferCanvases[e.MOTIONBLUR_BUFFER_NODE],ne=h.contexts[e.DRAG],le=e.data.bufferCanvases[e.MOTIONBLUR_BUFFER_DRAG],he=o(function(X,te,J){X.setTransform(1,0,0,1,0,0),J||!x?X.clearRect(0,0,e.canvasWidth,e.canvasHeight):D(X,0,0,e.canvasWidth,e.canvasHeight);var se=m;X.drawImage(te,0,0,e.canvasWidth*se,e.canvasHeight*se,0,0,e.canvasWidth,e.canvasHeight)},"drawMotionBlur");(f[e.NODE]||$[e.NODE])&&(he(j,ie,$[e.NODE]),f[e.NODE]=!1),(f[e.DRAG]||$[e.DRAG])&&(he(ne,le,$[e.DRAG]),f[e.DRAG]=!1)}e.prevViewport=A,e.clearingMotionBlur&&(e.clearingMotionBlur=!1,e.motionBlurCleared=!0,e.motionBlur=!0),p&&(e.motionBlurTimeout=setTimeout(function(){e.motionBlurTimeout=null,e.clearedForMotionBlur[e.NODE]=!1,e.clearedForMotionBlur[e.DRAG]=!1,e.motionBlur=!1,e.clearingMotionBlur=!d,e.mbFrames=0,f[e.NODE]=!0,f[e.DRAG]=!0,e.redraw()},dZe)),n||r.emit("render")};ys.drawSelectionRectangle=function(t,e){var r=this,n=r.cy,i=r.data,a=n.style(),s=t.drawOnlyNodeLayer,l=t.drawAllLayers,u=i.canvasNeedsRedraw,h=t.forcedContext;if(r.showFps||!s&&u[r.SELECT_BOX]&&!l){var f=h||i.contexts[r.SELECT_BOX];if(e(f),r.selection[4]==1&&(r.hoverData.selecting||r.touchData.selecting)){var d=r.cy.zoom(),p=a.core("selection-box-border-width").value/d;f.lineWidth=p,f.fillStyle="rgba("+a.core("selection-box-color").value[0]+","+a.core("selection-box-color").value[1]+","+a.core("selection-box-color").value[2]+","+a.core("selection-box-opacity").value+")",f.fillRect(r.selection[0],r.selection[1],r.selection[2]-r.selection[0],r.selection[3]-r.selection[1]),p>0&&(f.strokeStyle="rgba("+a.core("selection-box-border-color").value[0]+","+a.core("selection-box-border-color").value[1]+","+a.core("selection-box-border-color").value[2]+","+a.core("selection-box-opacity").value+")",f.strokeRect(r.selection[0],r.selection[1],r.selection[2]-r.selection[0],r.selection[3]-r.selection[1]))}if(i.bgActivePosistion&&!r.hoverData.selecting){var d=r.cy.zoom(),m=i.bgActivePosistion;f.fillStyle="rgba("+a.core("active-bg-color").value[0]+","+a.core("active-bg-color").value[1]+","+a.core("active-bg-color").value[2]+","+a.core("active-bg-opacity").value+")",f.beginPath(),f.arc(m.x,m.y,a.core("active-bg-size").pfValue/d,0,2*Math.PI),f.fill()}var g=r.lastRedrawTime;if(r.showFps&&g){g=Math.round(g);var y=Math.round(1e3/g),v="1 frame = "+g+" ms = "+y+" fps";if(f.setTransform(1,0,0,1,0,0),f.fillStyle="rgba(255, 0, 0, 0.75)",f.strokeStyle="rgba(255, 0, 0, 0.75)",f.font="30px Arial",!Nb){var x=f.measureText(v);Nb=x.actualBoundingBoxAscent}f.fillText(v,0,Nb);var b=60;f.strokeRect(0,Nb+10,250,20),f.fillRect(0,Nb+10,250*Math.min(y/b,1),20)}l||(u[r.SELECT_BOX]=!1)}};o(z0e,"compileShader");o(pZe,"createProgram");o(mZe,"createTextureCanvas");o(wB,"getEffectivePanZoom");o(NP,"modelToRenderedPosition");o(oS,"toWebGLColor");o(lS,"indexToVec4");o(gZe,"vec4ToIndex");o(yZe,"createTexture");o(Sge,"getTypeInfo");o(Cge,"createTypedArray");o(vZe,"createTypedArrayView");o(xZe,"createBufferStaticDraw");o(po,"createBufferDynamicDraw");o(bZe,"createPickingFrameBuffer");G0e=typeof Float32Array<"u"?Float32Array:Array;Math.hypot||(Math.hypot=function(){for(var t=0,e=arguments.length;e--;)t+=arguments[e]*arguments[e];return Math.sqrt(t)});o(Gb,"create");o(Age,"identity");o(wZe,"multiply");o(DS,"translate");o(_ge,"rotate");o(TB,"scale");o(TZe,"projection");Vb={SCREEN:{name:"screen",screen:!0},PICKING:{name:"picking",picking:!0}},Mb=la({getKey:null,drawElement:null,getBoundingBox:null,getRotation:null,getRotationPoint:null,getRotationOffset:null,isVisible:null,getPadding:null}),kZe=function(){function t(e,r){Mf(this,t),this.debugID=Math.floor(Math.random()*1e4),this.r=e,this.atlasSize=r.webglTexSize,this.rows=r.webglTexRows,this.enableWrapping=r.enableWrapping,this.texHeight=Math.floor(this.atlasSize/this.rows),this.maxTexWidth=this.atlasSize,this.texture=null,this.canvas=null,this.needsBuffer=!0,this.freePointer={x:0,row:0},this.keyToLocation=new Map,this.canvas=r.createTextureCanvas(e,this.atlasSize,this.atlasSize),this.scratch=r.createTextureCanvas(e,this.atlasSize,this.texHeight,"scratch")}return o(t,"Atlas"),If(t,[{key:"getKeys",value:o(function(){return new Set(this.keyToLocation.keys())},"getKeys")},{key:"getScale",value:o(function(r){var n=r.w,i=r.h,a=this.texHeight,s=this.maxTexWidth,l=a/i,u=n*l,h=i*l;return u>s&&(l=s/n,u=n*l,h=i*l),{scale:l,texW:u,texH:h}},"getScale")},{key:"draw",value:o(function(r,n,i){var a=this,s=this.atlasSize,l=this.rows,u=this.texHeight,h=this.getScale(n),f=h.scale,d=h.texW,p=h.texH,m=[null,null],g=o(function(w,C){if(i&&C){var T=C.context,E=w.x,A=w.row,S=E,_=u*A;T.save(),T.translate(S,_),T.scale(f,f),i(T,n),T.restore()}},"drawAt"),y=o(function(){g(a.freePointer,a.canvas),m[0]={x:a.freePointer.x,y:a.freePointer.row*u,w:d,h:p},m[1]={x:a.freePointer.x+d,y:a.freePointer.row*u,w:0,h:p},a.freePointer.x+=d,a.freePointer.x==s&&(a.freePointer.x=0,a.freePointer.row++)},"drawNormal"),v=o(function(){var w=a.scratch,C=a.canvas;w.clear(),g({x:0,row:0},w);var T=s-a.freePointer.x,E=d-T,A=u;{var S=a.freePointer.x,_=a.freePointer.row*u,I=T;C.context.drawImage(w,0,0,I,A,S,_,I,A),m[0]={x:S,y:_,w:I,h:p}}{var D=T,k=(a.freePointer.row+1)*u,L=E;C&&C.context.drawImage(w,D,0,L,A,0,k,L,A),m[1]={x:0,y:k,w:L,h:p}}a.freePointer.x=E,a.freePointer.row++},"drawWrapped"),x=o(function(){a.freePointer.x=0,a.freePointer.row++},"moveToStartOfNextRow");if(this.freePointer.x+d<=s)y();else{if(this.freePointer.row>=l-1)return!1;this.freePointer.x===s?(x(),y()):this.enableWrapping?v():(x(),y())}return this.keyToLocation.set(r,m),this.needsBuffer=!0,m},"draw")},{key:"getOffsets",value:o(function(r){return this.keyToLocation.get(r)},"getOffsets")},{key:"isEmpty",value:o(function(){return this.freePointer.x===0&&this.freePointer.row===0},"isEmpty")},{key:"canFit",value:o(function(r){var n=this.atlasSize,i=this.rows,a=this.getScale(r),s=a.texW;return this.freePointer.x+s>n?this.freePointer.row1&&arguments[1]!==void 0?arguments[1]:{},i=n.forceRedraw,a=i===void 0?!1:i,s=n.filterEle,l=s===void 0?function(){return!0}:s,u=n.filterType,h=u===void 0?function(){return!0}:u,f=!1,d=mo(r),p;try{for(d.s();!(p=d.n()).done;){var m=p.value;if(l(m)){var g=m.id(),y=mo(this.getRenderTypes()),v;try{for(y.s();!(v=y.n()).done;){var x=v.value;if(h(x.type)){var b=x.getKey(m);a?(x.atlasCollection.deleteKey(g,b),x.atlasCollection.styleKeyNeedsRedraw.add(b),f=!0):f|=x.atlasCollection.checkKeyIsInvalid(g,b)}}}catch(w){y.e(w)}finally{y.f()}}}}catch(w){d.e(w)}finally{d.f()}return f},"invalidate")},{key:"gc",value:o(function(){var r=mo(this.getRenderTypes()),n;try{for(r.s();!(n=r.n()).done;){var i=n.value;i.atlasCollection.gc()}}catch(a){r.e(a)}finally{r.f()}},"gc")},{key:"isRenderable",value:o(function(r,n){var i=this.getRenderTypeOpts(n);return i&&i.isVisible(r)},"isRenderable")},{key:"startBatch",value:o(function(){this.batchAtlases=[]},"startBatch")},{key:"getAtlasCount",value:o(function(){return this.batchAtlases.length},"getAtlasCount")},{key:"getAtlases",value:o(function(){return this.batchAtlases},"getAtlases")},{key:"getOrCreateAtlas",value:o(function(r,n,i){var a=this.renderTypes.get(i),s=a.getKey(r),l=r.id();return a.atlasCollection.draw(l,s,n,function(u){a.drawElement(u,r,n,!0,!0)})},"getOrCreateAtlas")},{key:"getAtlasIndexForBatch",value:o(function(r){var n=this.batchAtlases.indexOf(r);if(n<0){if(this.batchAtlases.length===this.maxAtlasesPerBatch)return;this.batchAtlases.push(r),n=this.batchAtlases.length-1}return n},"getAtlasIndexForBatch")},{key:"getIndexArray",value:o(function(){return Array.from({length:this.maxAtlases},function(r,n){return n})},"getIndexArray")},{key:"getAtlasInfo",value:o(function(r,n){var i=this.renderTypes.get(n),a=i.getBoundingBox(r),s=this.getOrCreateAtlas(r,a,n),l=this.getAtlasIndexForBatch(s);if(l!==void 0){var u=i.getKey(r),h=s.getOffsets(u),f=_i(h,2),d=f[0],p=f[1];return{atlasID:l,tex:d,tex1:d,tex2:p,bb:a,type:n,styleKey:u}}},"getAtlasInfo")},{key:"canAddToCurrentBatch",value:o(function(r,n){if(this.batchAtlases.length===this.maxAtlasesPerBatch){var i=this.renderTypes.get(n),a=i.getKey(r),s=i.atlasCollection.getAtlas(a);return s&&this.batchAtlases.includes(s)}return!0},"canAddToCurrentBatch")},{key:"setTransformMatrix",value:o(function(r,n,i){var a=arguments.length>3&&arguments[3]!==void 0?arguments[3]:!0,s=n.bb,l=n.type,u=n.tex1,h=n.tex2,f=this.getRenderTypeOpts(l),d=f.getPadding?f.getPadding(i):0,p=u.w/(u.w+h.w);a||(p=1-p);var m=this.getAdjustedBB(s,d,a,p),g,y;Age(r);var v=f.getRotation?f.getRotation(i):0;if(v!==0){var x=f.getRotationPoint(i),b=x.x,w=x.y;DS(r,r,[b,w]),_ge(r,r,v);var C=f.getRotationOffset(i);g=C.x+m.xOffset,y=C.y}else g=m.x1,y=m.y1;DS(r,r,[g,y]),TB(r,r,[m.w,m.h])},"setTransformMatrix")},{key:"getTransformMatrix",value:o(function(r,n){var i=arguments.length>2&&arguments[2]!==void 0?arguments[2]:!0,a=Gb();return this.setTransformMatrix(a,r,n,i),a},"getTransformMatrix")},{key:"getAdjustedBB",value:o(function(r,n,i,a){var s=r.x1,l=r.y1,u=r.w,h=r.h;n&&(s-=n,l-=n,u+=2*n,h+=2*n);var f=0,d=u*a;return i&&a<1?u=d:!i&&a<1&&(f=u-d,s+=f,u=d),{x1:s,y1:l,w:u,h,xOffset:f}},"getAdjustedBB")},{key:"getDebugInfo",value:o(function(){var r=[],n=mo(this.renderTypes),i;try{for(n.s();!(i=n.n()).done;){var a=_i(i.value,2),s=a[0],l=a[1],u=l.atlasCollection.getCounts(),h=u.keyCount,f=u.atlasCount;r.push({type:s,keyCount:h,atlasCount:f})}}catch(d){n.e(d)}finally{n.f()}return r},"getDebugInfo")}]),t}(),MP=0,V0e=1,U0e=2,IP=3,AZe=function(){function t(e,r,n){Mf(this,t),this.r=e,this.gl=r,this.maxInstances=n.webglBatchSize,this.maxAtlases=n.webglTexPerBatch,this.atlasSize=n.webglTexSize,this.bgColor=n.bgColor,n.enableWrapping=!0,n.createTextureCanvas=mZe,this.atlasManager=new CZe(e,n),this.program=this.createShaderProgram(Vb.SCREEN),this.pickingProgram=this.createShaderProgram(Vb.PICKING),this.vao=this.createVAO(),this.debugInfo=[]}return o(t,"ElementDrawingWebGL"),If(t,[{key:"addTextureRenderType",value:o(function(r,n){this.atlasManager.addRenderType(r,n)},"addTextureRenderType")},{key:"invalidate",value:o(function(r){var n=arguments.length>1&&arguments[1]!==void 0?arguments[1]:{},i=n.type,a=this.atlasManager;return i?a.invalidate(r,{filterType:o(function(l){return l===i},"filterType"),forceRedraw:!0}):a.invalidate(r)},"invalidate")},{key:"gc",value:o(function(){this.atlasManager.gc()},"gc")},{key:"createShaderProgram",value:o(function(r){var n=this.gl,i=`#version 300 es - precision highp float; - - uniform mat3 uPanZoomMatrix; - uniform int uAtlasSize; - - // instanced - in vec2 aPosition; - - // what are we rendering? - in int aVertType; - - // for picking - in vec4 aIndex; - - // For textures - in int aAtlasId; // which shader unit/atlas to use - in vec4 aTex1; // x/y/w/h of texture in atlas - in vec4 aTex2; - - // for any transforms that are needed - in vec4 aScaleRotate1; // vectors use fewer attributes than matrices - in vec2 aTranslate1; - in vec4 aScaleRotate2; - in vec2 aTranslate2; - - // for edges - in vec4 aPointAPointB; - in vec4 aPointCPointD; - in float aLineWidth; - in vec4 aEdgeColor; - - out vec2 vTexCoord; - out vec4 vEdgeColor; - flat out int vAtlasId; - flat out vec4 vIndex; - flat out int vVertType; - - void main(void) { - int vid = gl_VertexID; - vec2 position = aPosition; - - if(aVertType == `.concat(MP,`) { - float texX; - float texY; - float texW; - float texH; - mat3 texMatrix; - - int vid = gl_VertexID; - if(vid <= 5) { - texX = aTex1.x; - texY = aTex1.y; - texW = aTex1.z; - texH = aTex1.w; - texMatrix = mat3( - vec3(aScaleRotate1.xy, 0.0), - vec3(aScaleRotate2.zw, 0.0), - vec3(aTranslate1, 1.0) - ); - } else { - texX = aTex2.x; - texY = aTex2.y; - texW = aTex2.z; - texH = aTex2.w; - texMatrix = mat3( - vec3(aScaleRotate2.xy, 0.0), - vec3(aScaleRotate2.zw, 0.0), - vec3(aTranslate2, 1.0) - ); - } - - if(vid == 1 || vid == 2 || vid == 4 || vid == 7 || vid == 8 || vid == 10) { - texX += texW; - } - if(vid == 2 || vid == 4 || vid == 5 || vid == 8 || vid == 10 || vid == 11) { - texY += texH; - } - - float d = float(uAtlasSize); - vTexCoord = vec2(texX / d, texY / d); // tex coords must be between 0 and 1 - - gl_Position = vec4(uPanZoomMatrix * texMatrix * vec3(position, 1.0), 1.0); - } - else if(aVertType == `).concat(V0e,` && vid < 6) { - vec2 source = aPointAPointB.xy; - vec2 target = aPointAPointB.zw; - - // adjust the geometry so that the line is centered on the edge - position.y = position.y - 0.5; - - vec2 xBasis = target - source; - vec2 yBasis = normalize(vec2(-xBasis.y, xBasis.x)); - vec2 point = source + xBasis * position.x + yBasis * aLineWidth * position.y; - - gl_Position = vec4(uPanZoomMatrix * vec3(point, 1.0), 1.0); - vEdgeColor = aEdgeColor; - } - else if(aVertType == `).concat(U0e,` && vid < 6) { - vec2 pointA = aPointAPointB.xy; - vec2 pointB = aPointAPointB.zw; - vec2 pointC = aPointCPointD.xy; - vec2 pointD = aPointCPointD.zw; - - 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Adjust the position so that there's no overlap. - vec2 point = 0.5 * width * normal * -sigma / dot(normal, p01Norm); - gl_Position = vec4(uPanZoomMatrix * vec3(p1 + point, 1.0), 1.0); - } else { - // This is a non-intersecting vertex. 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s(u,h,f){n.call(this,f),this.isOverlapingSourceAndTarget=!1,this.vGraphObject=f,this.bendpoints=[],this.source=u,this.target=h}o(s,"LEdge"),s.prototype=Object.create(n.prototype);for(var l in n)s[l]=n[l];s.prototype.getSource=function(){return this.source},s.prototype.getTarget=function(){return this.target},s.prototype.isInterGraph=function(){return this.isInterGraph},s.prototype.getLength=function(){return this.length},s.prototype.isOverlapingSourceAndTarget=function(){return this.isOverlapingSourceAndTarget},s.prototype.getBendpoints=function(){return this.bendpoints},s.prototype.getLca=function(){return this.lca},s.prototype.getSourceInLca=function(){return this.sourceInLca},s.prototype.getTargetInLca=function(){return this.targetInLca},s.prototype.getOtherEnd=function(u){if(this.source===u)return this.target;if(this.target===u)return this.source;throw"Node is not incident with this edge"},s.prototype.getOtherEndInGraph=function(u,h){for(var f=this.getOtherEnd(u),d=h.getGraphManager().getRoot();;){if(f.getOwner()==h)return f;if(f.getOwner()==d)break;f=f.getOwner().getParent()}return null},s.prototype.updateLength=function(){var u=new Array(4);this.isOverlapingSourceAndTarget=i.getIntersection(this.target.getRect(),this.source.getRect(),u),this.isOverlapingSourceAndTarget||(this.lengthX=u[0]-u[2],this.lengthY=u[1]-u[3],Math.abs(this.lengthX)<1&&(this.lengthX=a.sign(this.lengthX)),Math.abs(this.lengthY)<1&&(this.lengthY=a.sign(this.lengthY)),this.length=Math.sqrt(this.lengthX*this.lengthX+this.lengthY*this.lengthY))},s.prototype.updateLengthSimple=function(){this.lengthX=this.target.getCenterX()-this.source.getCenterX(),this.lengthY=this.target.getCenterY()-this.source.getCenterY(),Math.abs(this.lengthX)<1&&(this.lengthX=a.sign(this.lengthX)),Math.abs(this.lengthY)<1&&(this.lengthY=a.sign(this.lengthY)),this.length=Math.sqrt(this.lengthX*this.lengthX+this.lengthY*this.lengthY)},t.exports=s},function(t,e,r){"use strict";function n(i){this.vGraphObject=i}o(n,"LGraphObject"),t.exports=n},function(t,e,r){"use strict";var n=r(2),i=r(10),a=r(13),s=r(0),l=r(16),u=r(4);function h(d,p,m,g){m==null&&g==null&&(g=p),n.call(this,g),d.graphManager!=null&&(d=d.graphManager),this.estimatedSize=i.MIN_VALUE,this.inclusionTreeDepth=i.MAX_VALUE,this.vGraphObject=g,this.edges=[],this.graphManager=d,m!=null&&p!=null?this.rect=new a(p.x,p.y,m.width,m.height):this.rect=new a}o(h,"LNode"),h.prototype=Object.create(n.prototype);for(var f in n)h[f]=n[f];h.prototype.getEdges=function(){return this.edges},h.prototype.getChild=function(){return this.child},h.prototype.getOwner=function(){return this.owner},h.prototype.getWidth=function(){return this.rect.width},h.prototype.setWidth=function(d){this.rect.width=d},h.prototype.getHeight=function(){return this.rect.height},h.prototype.setHeight=function(d){this.rect.height=d},h.prototype.getCenterX=function(){return this.rect.x+this.rect.width/2},h.prototype.getCenterY=function(){return this.rect.y+this.rect.height/2},h.prototype.getCenter=function(){return new u(this.rect.x+this.rect.width/2,this.rect.y+this.rect.height/2)},h.prototype.getLocation=function(){return new u(this.rect.x,this.rect.y)},h.prototype.getRect=function(){return this.rect},h.prototype.getDiagonal=function(){return Math.sqrt(this.rect.width*this.rect.width+this.rect.height*this.rect.height)},h.prototype.getHalfTheDiagonal=function(){return Math.sqrt(this.rect.height*this.rect.height+this.rect.width*this.rect.width)/2},h.prototype.setRect=function(d,p){this.rect.x=d.x,this.rect.y=d.y,this.rect.width=p.width,this.rect.height=p.height},h.prototype.setCenter=function(d,p){this.rect.x=d-this.rect.width/2,this.rect.y=p-this.rect.height/2},h.prototype.setLocation=function(d,p){this.rect.x=d,this.rect.y=p},h.prototype.moveBy=function(d,p){this.rect.x+=d,this.rect.y+=p},h.prototype.getEdgeListToNode=function(d){var p=[],m,g=this;return g.edges.forEach(function(y){if(y.target==d){if(y.source!=g)throw"Incorrect edge source!";p.push(y)}}),p},h.prototype.getEdgesBetween=function(d){var p=[],m,g=this;return g.edges.forEach(function(y){if(!(y.source==g||y.target==g))throw"Incorrect edge source and/or target";(y.target==d||y.source==d)&&p.push(y)}),p},h.prototype.getNeighborsList=function(){var d=new Set,p=this;return p.edges.forEach(function(m){if(m.source==p)d.add(m.target);else{if(m.target!=p)throw"Incorrect incidency!";d.add(m.source)}}),d},h.prototype.withChildren=function(){var d=new Set,p,m;if(d.add(this),this.child!=null)for(var g=this.child.getNodes(),y=0;yp&&(this.rect.x-=(this.labelWidth-p)/2,this.setWidth(this.labelWidth)),this.labelHeight>m&&(this.labelPos=="center"?this.rect.y-=(this.labelHeight-m)/2:this.labelPos=="top"&&(this.rect.y-=this.labelHeight-m),this.setHeight(this.labelHeight))}}},h.prototype.getInclusionTreeDepth=function(){if(this.inclusionTreeDepth==i.MAX_VALUE)throw"assert failed";return this.inclusionTreeDepth},h.prototype.transform=function(d){var p=this.rect.x;p>s.WORLD_BOUNDARY?p=s.WORLD_BOUNDARY:p<-s.WORLD_BOUNDARY&&(p=-s.WORLD_BOUNDARY);var m=this.rect.y;m>s.WORLD_BOUNDARY?m=s.WORLD_BOUNDARY:m<-s.WORLD_BOUNDARY&&(m=-s.WORLD_BOUNDARY);var g=new u(p,m),y=d.inverseTransformPoint(g);this.setLocation(y.x,y.y)},h.prototype.getLeft=function(){return this.rect.x},h.prototype.getRight=function(){return this.rect.x+this.rect.width},h.prototype.getTop=function(){return this.rect.y},h.prototype.getBottom=function(){return this.rect.y+this.rect.height},h.prototype.getParent=function(){return this.owner==null?null:this.owner.getParent()},t.exports=h},function(t,e,r){"use strict";function n(i,a){i==null&&a==null?(this.x=0,this.y=0):(this.x=i,this.y=a)}o(n,"PointD"),n.prototype.getX=function(){return this.x},n.prototype.getY=function(){return this.y},n.prototype.setX=function(i){this.x=i},n.prototype.setY=function(i){this.y=i},n.prototype.getDifference=function(i){return new DimensionD(this.x-i.x,this.y-i.y)},n.prototype.getCopy=function(){return new n(this.x,this.y)},n.prototype.translate=function(i){return this.x+=i.width,this.y+=i.height,this},t.exports=n},function(t,e,r){"use strict";var n=r(2),i=r(10),a=r(0),s=r(6),l=r(3),u=r(1),h=r(13),f=r(12),d=r(11);function p(g,y,v){n.call(this,v),this.estimatedSize=i.MIN_VALUE,this.margin=a.DEFAULT_GRAPH_MARGIN,this.edges=[],this.nodes=[],this.isConnected=!1,this.parent=g,y!=null&&y instanceof s?this.graphManager=y:y!=null&&y instanceof Layout&&(this.graphManager=y.graphManager)}o(p,"LGraph"),p.prototype=Object.create(n.prototype);for(var m in n)p[m]=n[m];p.prototype.getNodes=function(){return this.nodes},p.prototype.getEdges=function(){return this.edges},p.prototype.getGraphManager=function(){return this.graphManager},p.prototype.getParent=function(){return this.parent},p.prototype.getLeft=function(){return this.left},p.prototype.getRight=function(){return this.right},p.prototype.getTop=function(){return this.top},p.prototype.getBottom=function(){return this.bottom},p.prototype.isConnected=function(){return this.isConnected},p.prototype.add=function(g,y,v){if(y==null&&v==null){var x=g;if(this.graphManager==null)throw"Graph has no graph mgr!";if(this.getNodes().indexOf(x)>-1)throw"Node already in graph!";return x.owner=this,this.getNodes().push(x),x}else{var b=g;if(!(this.getNodes().indexOf(y)>-1&&this.getNodes().indexOf(v)>-1))throw"Source or target not in graph!";if(!(y.owner==v.owner&&y.owner==this))throw"Both owners must be this graph!";return y.owner!=v.owner?null:(b.source=y,b.target=v,b.isInterGraph=!1,this.getEdges().push(b),y.edges.push(b),v!=y&&v.edges.push(b),b)}},p.prototype.remove=function(g){var y=g;if(g instanceof l){if(y==null)throw"Node is null!";if(!(y.owner!=null&&y.owner==this))throw"Owner graph is invalid!";if(this.graphManager==null)throw"Owner graph manager is invalid!";for(var v=y.edges.slice(),x,b=v.length,w=0;w-1&&E>-1))throw"Source and/or target doesn't know this edge!";x.source.edges.splice(T,1),x.target!=x.source&&x.target.edges.splice(E,1);var C=x.source.owner.getEdges().indexOf(x);if(C==-1)throw"Not in owner's edge list!";x.source.owner.getEdges().splice(C,1)}},p.prototype.updateLeftTop=function(){for(var g=i.MAX_VALUE,y=i.MAX_VALUE,v,x,b,w=this.getNodes(),C=w.length,T=0;Tv&&(g=v),y>x&&(y=x)}return g==i.MAX_VALUE?null:(w[0].getParent().paddingLeft!=null?b=w[0].getParent().paddingLeft:b=this.margin,this.left=y-b,this.top=g-b,new f(this.left,this.top))},p.prototype.updateBounds=function(g){for(var y=i.MAX_VALUE,v=-i.MAX_VALUE,x=i.MAX_VALUE,b=-i.MAX_VALUE,w,C,T,E,A,S=this.nodes,_=S.length,I=0;I<_;I++){var D=S[I];g&&D.child!=null&&D.updateBounds(),w=D.getLeft(),C=D.getRight(),T=D.getTop(),E=D.getBottom(),y>w&&(y=w),vT&&(x=T),bw&&(y=w),vT&&(x=T),b=this.nodes.length){var _=0;v.forEach(function(I){I.owner==g&&_++}),_==this.nodes.length&&(this.isConnected=!0)}},t.exports=p},function(t,e,r){"use strict";var n,i=r(1);function a(s){n=r(5),this.layout=s,this.graphs=[],this.edges=[]}o(a,"LGraphManager"),a.prototype.addRoot=function(){var s=this.layout.newGraph(),l=this.layout.newNode(null),u=this.add(s,l);return this.setRootGraph(u),this.rootGraph},a.prototype.add=function(s,l,u,h,f){if(u==null&&h==null&&f==null){if(s==null)throw"Graph is null!";if(l==null)throw"Parent node is null!";if(this.graphs.indexOf(s)>-1)throw"Graph already in this graph mgr!";if(this.graphs.push(s),s.parent!=null)throw"Already has a parent!";if(l.child!=null)throw"Already has a child!";return s.parent=l,l.child=s,s}else{f=u,h=l,u=s;var d=h.getOwner(),p=f.getOwner();if(!(d!=null&&d.getGraphManager()==this))throw"Source not in this graph mgr!";if(!(p!=null&&p.getGraphManager()==this))throw"Target not in this graph mgr!";if(d==p)return u.isInterGraph=!1,d.add(u,h,f);if(u.isInterGraph=!0,u.source=h,u.target=f,this.edges.indexOf(u)>-1)throw"Edge already in inter-graph edge list!";if(this.edges.push(u),!(u.source!=null&&u.target!=null))throw"Edge source and/or target is null!";if(!(u.source.edges.indexOf(u)==-1&&u.target.edges.indexOf(u)==-1))throw"Edge already in source and/or target incidency list!";return u.source.edges.push(u),u.target.edges.push(u),u}},a.prototype.remove=function(s){if(s instanceof n){var l=s;if(l.getGraphManager()!=this)throw"Graph not in this graph mgr";if(!(l==this.rootGraph||l.parent!=null&&l.parent.graphManager==this))throw"Invalid parent node!";var u=[];u=u.concat(l.getEdges());for(var h,f=u.length,d=0;d=s.getRight()?l[0]+=Math.min(s.getX()-a.getX(),a.getRight()-s.getRight()):s.getX()<=a.getX()&&s.getRight()>=a.getRight()&&(l[0]+=Math.min(a.getX()-s.getX(),s.getRight()-a.getRight())),a.getY()<=s.getY()&&a.getBottom()>=s.getBottom()?l[1]+=Math.min(s.getY()-a.getY(),a.getBottom()-s.getBottom()):s.getY()<=a.getY()&&s.getBottom()>=a.getBottom()&&(l[1]+=Math.min(a.getY()-s.getY(),s.getBottom()-a.getBottom()));var f=Math.abs((s.getCenterY()-a.getCenterY())/(s.getCenterX()-a.getCenterX()));s.getCenterY()===a.getCenterY()&&s.getCenterX()===a.getCenterX()&&(f=1);var d=f*l[0],p=l[1]/f;l[0]d)return l[0]=u,l[1]=m,l[2]=f,l[3]=S,!1;if(hf)return l[0]=p,l[1]=h,l[2]=E,l[3]=d,!1;if(uf?(l[0]=y,l[1]=v,k=!0):(l[0]=g,l[1]=m,k=!0):R===M&&(u>f?(l[0]=p,l[1]=m,k=!0):(l[0]=x,l[1]=v,k=!0)),-O===M?f>u?(l[2]=A,l[3]=S,L=!0):(l[2]=E,l[3]=T,L=!0):O===M&&(f>u?(l[2]=C,l[3]=T,L=!0):(l[2]=_,l[3]=S,L=!0)),k&&L)return!1;if(u>f?h>d?(B=this.getCardinalDirection(R,M,4),F=this.getCardinalDirection(O,M,2)):(B=this.getCardinalDirection(-R,M,3),F=this.getCardinalDirection(-O,M,1)):h>d?(B=this.getCardinalDirection(-R,M,1),F=this.getCardinalDirection(-O,M,3)):(B=this.getCardinalDirection(R,M,2),F=this.getCardinalDirection(O,M,4)),!k)switch(B){case 1:z=m,P=u+-w/M,l[0]=P,l[1]=z;break;case 2:P=x,z=h+b*M,l[0]=P,l[1]=z;break;case 3:z=v,P=u+w/M,l[0]=P,l[1]=z;break;case 4:P=y,z=h+-b*M,l[0]=P,l[1]=z;break}if(!L)switch(F){case 1:H=T,$=f+-D/M,l[2]=$,l[3]=H;break;case 2:$=_,H=d+I*M,l[2]=$,l[3]=H;break;case 3:H=S,$=f+D/M,l[2]=$,l[3]=H;break;case 4:$=A,H=d+-I*M,l[2]=$,l[3]=H;break}}return!1},i.getCardinalDirection=function(a,s,l){return a>s?l:1+l%4},i.getIntersection=function(a,s,l,u){if(u==null)return this.getIntersection2(a,s,l);var h=a.x,f=a.y,d=s.x,p=s.y,m=l.x,g=l.y,y=u.x,v=u.y,x=void 0,b=void 0,w=void 0,C=void 0,T=void 0,E=void 0,A=void 0,S=void 0,_=void 0;return w=p-f,T=h-d,A=d*f-h*p,C=v-g,E=m-y,S=y*g-m*v,_=w*E-C*T,_===0?null:(x=(T*S-E*A)/_,b=(C*A-w*S)/_,new n(x,b))},i.angleOfVector=function(a,s,l,u){var h=void 0;return a!==l?(h=Math.atan((u-s)/(l-a)),l0?1:i<0?-1:0},n.floor=function(i){return i<0?Math.ceil(i):Math.floor(i)},n.ceil=function(i){return i<0?Math.floor(i):Math.ceil(i)},t.exports=n},function(t,e,r){"use strict";function n(){}o(n,"Integer"),n.MAX_VALUE=2147483647,n.MIN_VALUE=-2147483648,t.exports=n},function(t,e,r){"use strict";var n=function(){function h(f,d){for(var p=0;p"u"?"undefined":n(a);return a==null||s!="object"&&s!="function"},t.exports=i},function(t,e,r){"use strict";function n(m){if(Array.isArray(m)){for(var g=0,y=Array(m.length);g0&&g;){for(w.push(T[0]);w.length>0&&g;){var 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i(a,s){this.lworldOrgX=0,this.lworldOrgY=0,this.ldeviceOrgX=0,this.ldeviceOrgY=0,this.lworldExtX=1,this.lworldExtY=1,this.ldeviceExtX=1,this.ldeviceExtY=1}o(i,"Transform"),i.prototype.getWorldOrgX=function(){return this.lworldOrgX},i.prototype.setWorldOrgX=function(a){this.lworldOrgX=a},i.prototype.getWorldOrgY=function(){return this.lworldOrgY},i.prototype.setWorldOrgY=function(a){this.lworldOrgY=a},i.prototype.getWorldExtX=function(){return this.lworldExtX},i.prototype.setWorldExtX=function(a){this.lworldExtX=a},i.prototype.getWorldExtY=function(){return this.lworldExtY},i.prototype.setWorldExtY=function(a){this.lworldExtY=a},i.prototype.getDeviceOrgX=function(){return this.ldeviceOrgX},i.prototype.setDeviceOrgX=function(a){this.ldeviceOrgX=a},i.prototype.getDeviceOrgY=function(){return this.ldeviceOrgY},i.prototype.setDeviceOrgY=function(a){this.ldeviceOrgY=a},i.prototype.getDeviceExtX=function(){return this.ldeviceExtX},i.prototype.setDeviceExtX=function(a){this.ldeviceExtX=a},i.prototype.getDeviceExtY=function(){return this.ldeviceExtY},i.prototype.setDeviceExtY=function(a){this.ldeviceExtY=a},i.prototype.transformX=function(a){var s=0,l=this.lworldExtX;return l!=0&&(s=this.ldeviceOrgX+(a-this.lworldOrgX)*this.ldeviceExtX/l),s},i.prototype.transformY=function(a){var s=0,l=this.lworldExtY;return l!=0&&(s=this.ldeviceOrgY+(a-this.lworldOrgY)*this.ldeviceExtY/l),s},i.prototype.inverseTransformX=function(a){var s=0,l=this.ldeviceExtX;return l!=0&&(s=this.lworldOrgX+(a-this.ldeviceOrgX)*this.lworldExtX/l),s},i.prototype.inverseTransformY=function(a){var s=0,l=this.ldeviceExtY;return l!=0&&(s=this.lworldOrgY+(a-this.ldeviceOrgY)*this.lworldExtY/l),s},i.prototype.inverseTransformPoint=function(a){var s=new n(this.inverseTransformX(a.x),this.inverseTransformY(a.y));return s},t.exports=i},function(t,e,r){"use strict";function n(d){if(Array.isArray(d)){for(var p=0,m=Array(d.length);pa.ADAPTATION_LOWER_NODE_LIMIT&&(this.coolingFactor=Math.max(this.coolingFactor*a.COOLING_ADAPTATION_FACTOR,this.coolingFactor-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*this.coolingFactor*(1-a.COOLING_ADAPTATION_FACTOR))),this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT_INCREMENTAL):(d>a.ADAPTATION_LOWER_NODE_LIMIT?this.coolingFactor=Math.max(a.COOLING_ADAPTATION_FACTOR,1-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*(1-a.COOLING_ADAPTATION_FACTOR)):this.coolingFactor=1,this.initialCoolingFactor=this.coolingFactor,this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT),this.maxIterations=Math.max(this.getAllNodes().length*5,this.maxIterations),this.totalDisplacementThreshold=this.displacementThresholdPerNode*this.getAllNodes().length,this.repulsionRange=this.calcRepulsionRange()},h.prototype.calcSpringForces=function(){for(var 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O=E[L][0].getParent(),M=new l(T.graphManager);M.id=R,M.paddingLeft=O.paddingLeft||0,M.paddingRight=O.paddingRight||0,M.paddingBottom=O.paddingBottom||0,M.paddingTop=O.paddingTop||0,T.idToDummyNode[R]=M;var B=T.getGraphManager().add(T.newGraph(),M),F=O.getChild();F.add(M);for(var P=0;P=0;T--){var E=this.compoundOrder[T],A=E.id,S=E.paddingLeft,_=E.paddingTop;this.adjustLocations(this.tiledMemberPack[A],E.rect.x,E.rect.y,S,_)}},w.prototype.repopulateZeroDegreeMembers=function(){var T=this,E=this.tiledZeroDegreePack;Object.keys(E).forEach(function(A){var S=T.idToDummyNode[A],_=S.paddingLeft,I=S.paddingTop;T.adjustLocations(E[A],S.rect.x,S.rect.y,_,I)})},w.prototype.getToBeTiled=function(T){var E=T.id;if(this.toBeTiled[E]!=null)return this.toBeTiled[E];var A=T.getChild();if(A==null)return this.toBeTiled[E]=!1,!1;for(var S=A.getNodes(),_=0;_0)return this.toBeTiled[E]=!1,!1;if(I.getChild()==null){this.toBeTiled[I.id]=!1;continue}if(!this.getToBeTiled(I))return this.toBeTiled[E]=!1,!1}return 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E=-1,A=Number.MAX_VALUE,S=0;SA&&(E=S,A=T.rowWidth[S]);return E},w.prototype.canAddHorizontal=function(T,E,A){var S=this.getShortestRowIndex(T);if(S<0)return!0;var _=T.rowWidth[S];if(_+T.horizontalPadding+E<=T.width)return!0;var I=0;T.rowHeight[S]0&&(I=A+T.verticalPadding-T.rowHeight[S]);var D;T.width-_>=E+T.horizontalPadding?D=(T.height+I)/(_+E+T.horizontalPadding):D=(T.height+I)/T.width,I=A+T.verticalPadding;var k;return T.widthI&&E!=A){S.splice(-1,1),T.rows[A].push(_),T.rowWidth[E]=T.rowWidth[E]-I,T.rowWidth[A]=T.rowWidth[A]+I,T.width=T.rowWidth[instance.getLongestRowIndex(T)];for(var D=Number.MIN_VALUE,k=0;kD&&(D=S[k].height);E>0&&(D+=T.verticalPadding);var L=T.rowHeight[E]+T.rowHeight[A];T.rowHeight[E]=D,T.rowHeight[A]<_.height+T.verticalPadding&&(T.rowHeight[A]=_.height+T.verticalPadding);var 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38:this.$={type:"applyStyles",id:_[D-1].trim(),stylesStr:_[D].trim()};break}},"anonymous"),table:[{9:1,10:[1,2]},{1:[3]},{11:3,13:4,19:5,20:6,21:e,22:8,23:9,24:10,25:11,26:12,28:r,29:n,31:i,32:a,40:s,44:l,47:u},{8:[1,20]},t(h,[2,12],{13:4,19:5,20:6,22:8,23:9,24:10,25:11,26:12,11:21,21:e,28:r,29:n,31:i,32:a,40:s,44:l,47:u}),t(f,[2,16],{14:22,15:d,16:p}),t(f,[2,17]),t(f,[2,18]),t(f,[2,19]),t(f,[2,20]),t(f,[2,21]),t(f,[2,22]),t(m,[2,25],{27:[1,25]}),t(f,[2,26]),{19:26,26:12,32:a},{11:27,13:4,19:5,20:6,21:e,22:8,23:9,24:10,25:11,26:12,28:r,29:n,31:i,32:a,40:s,44:l,47:u},{41:[1,28],43:[1,29]},{45:[1,30]},{48:[1,31]},t(g,[2,29],{33:32,36:[1,33],38:[1,34]}),{1:[2,7]},t(h,[2,13]),{26:35,32:a},{32:[2,14]},{17:[1,36]},t(m,[2,24]),{11:37,13:4,14:22,15:d,16:p,19:5,20:6,21:e,22:8,23:9,24:10,25:11,26:12,28:r,29:n,31:i,32:a,40:s,44:l,47:u},{30:[1,38]},{42:[1,39]},{42:[1,40]},{46:[1,41]},{49:[1,42]},t(g,[2,30]),{18:[1,43]},{18:[1,44]},t(m,[2,23]),{18:[1,45]},{30:[1,46]},t(f,[2,28]),t(f,[2,35]),t(f,[2,36]),t(f,[2,37]),t(f,[2,38]),{37:[1,47]},{34:48,35:y},{15:[1,50]},t(f,[2,27]),t(g,[2,33]),{39:[1,51]},{34:52,35:y,39:[2,31]},{32:[2,15]},t(g,[2,34]),{39:[2,32]}],defaultActions:{20:[2,7],23:[2,14],50:[2,15],52:[2,32]},parseError:o(function(C,T){if(T.recoverable)this.trace(C);else{var E=new Error(C);throw E.hash=T,E}},"parseError"),parse:o(function(C){var T=this,E=[0],A=[],S=[null],_=[],I=this.table,D="",k=0,L=0,R=0,O=2,M=1,B=_.slice.call(arguments,1),F=Object.create(this.lexer),P={yy:{}};for(var z in this.yy)Object.prototype.hasOwnProperty.call(this.yy,z)&&(P.yy[z]=this.yy[z]);F.setInput(C,P.yy),P.yy.lexer=F,P.yy.parser=this,typeof F.yylloc>"u"&&(F.yylloc={});var $=F.yylloc;_.push($);var H=F.options&&F.options.ranges;typeof P.yy.parseError=="function"?this.parseError=P.yy.parseError:this.parseError=Object.getPrototypeOf(this).parseError;function Q(ce){E.length=E.length-2*ce,S.length=S.length-ce,_.length=_.length-ce}o(Q,"popStack");function j(){var ce;return ce=A.pop()||F.lex()||M,typeof ce!="number"&&(ce instanceof Array&&(A=ce,ce=A.pop()),ce=T.symbols_[ce]||ce),ce}o(j,"lex");for(var ie,ne,le,he,K,X,te={},J,se,ue,Z;;){if(le=E[E.length-1],this.defaultActions[le]?he=this.defaultActions[le]:((ie===null||typeof ie>"u")&&(ie=j()),he=I[le]&&I[le][ie]),typeof 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this.yy=T||this.yy||{},this._input=C,this._more=this._backtrack=this.done=!1,this.yylineno=this.yyleng=0,this.yytext=this.matched=this.match="",this.conditionStack=["INITIAL"],this.yylloc={first_line:1,first_column:0,last_line:1,last_column:0},this.options.ranges&&(this.yylloc.range=[0,0]),this.offset=0,this},"setInput"),input:o(function(){var C=this._input[0];this.yytext+=C,this.yyleng++,this.offset++,this.match+=C,this.matched+=C;var T=C.match(/(?:\r\n?|\n).*/g);return T?(this.yylineno++,this.yylloc.last_line++):this.yylloc.last_column++,this.options.ranges&&this.yylloc.range[1]++,this._input=this._input.slice(1),C},"input"),unput:o(function(C){var T=C.length,E=C.split(/(?:\r\n?|\n)/g);this._input=C+this._input,this.yytext=this.yytext.substr(0,this.yytext.length-T),this.offset-=T;var A=this.match.split(/(?:\r\n?|\n)/g);this.match=this.match.substr(0,this.match.length-1),this.matched=this.matched.substr(0,this.matched.length-1),E.length-1&&(this.yylineno-=E.length-1);var S=this.yylloc.range;return this.yylloc={first_line:this.yylloc.first_line,last_line:this.yylineno+1,first_column:this.yylloc.first_column,last_column:E?(E.length===A.length?this.yylloc.first_column:0)+A[A.length-E.length].length-E[0].length:this.yylloc.first_column-T},this.options.ranges&&(this.yylloc.range=[S[0],S[0]+this.yyleng-T]),this.yyleng=this.yytext.length,this},"unput"),more:o(function(){return this._more=!0,this},"more"),reject:o(function(){if(this.options.backtrack_lexer)this._backtrack=!0;else return this.parseError("Lexical error on line "+(this.yylineno+1)+`. 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T.getLogger().debug("Found nl-block"),31;break;case 3:return T.getLogger().debug("Found space-block"),29;break;case 4:T.getLogger().debug(".",E.yytext);break;case 5:T.getLogger().debug("_",E.yytext);break;case 6:return 5;case 7:return E.yytext=-1,28;break;case 8:return E.yytext=E.yytext.replace(/columns\s+/,""),T.getLogger().debug("COLUMNS (LEX)",E.yytext),28;break;case 9:this.pushState("md_string");break;case 10:return"MD_STR";case 11:this.popState();break;case 12:this.pushState("string");break;case 13:T.getLogger().debug("LEX: POPPING STR:",E.yytext),this.popState();break;case 14:return T.getLogger().debug("LEX: STR end:",E.yytext),"STR";break;case 15:return E.yytext=E.yytext.replace(/space\:/,""),T.getLogger().debug("SPACE NUM (LEX)",E.yytext),21;break;case 16:return E.yytext="1",T.getLogger().debug("COLUMNS (LEX)",E.yytext),21;break;case 17:return 43;case 18:return"LINKSTYLE";case 19:return"INTERPOLATE";case 20:return this.pushState("CLASSDEF"),40;break;case 21:return this.popState(),this.pushState("CLASSDEFID"),"DEFAULT_CLASSDEF_ID";break;case 22:return this.popState(),this.pushState("CLASSDEFID"),41;break;case 23:return this.popState(),42;break;case 24:return this.pushState("CLASS"),44;break;case 25:return this.popState(),this.pushState("CLASS_STYLE"),45;break;case 26:return this.popState(),46;break;case 27:return this.pushState("STYLE_STMNT"),47;break;case 28:return this.popState(),this.pushState("STYLE_DEFINITION"),48;break;case 29:return this.popState(),49;break;case 30:return this.pushState("acc_title"),"acc_title";break;case 31:return this.popState(),"acc_title_value";break;case 32:return this.pushState("acc_descr"),"acc_descr";break;case 33:return this.popState(),"acc_descr_value";break;case 34:this.pushState("acc_descr_multiline");break;case 35:this.popState();break;case 36:return"acc_descr_multiline_value";case 37:return 30;case 38:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 39:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 40:return this.popState(),T.getLogger().debug("Lex: ))"),"NODE_DEND";break;case 41:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 42:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 43:return this.popState(),T.getLogger().debug("Lex: (-"),"NODE_DEND";break;case 44:return this.popState(),T.getLogger().debug("Lex: -)"),"NODE_DEND";break;case 45:return this.popState(),T.getLogger().debug("Lex: (("),"NODE_DEND";break;case 46:return this.popState(),T.getLogger().debug("Lex: ]]"),"NODE_DEND";break;case 47:return this.popState(),T.getLogger().debug("Lex: ("),"NODE_DEND";break;case 48:return this.popState(),T.getLogger().debug("Lex: ])"),"NODE_DEND";break;case 49:return this.popState(),T.getLogger().debug("Lex: /]"),"NODE_DEND";break;case 50:return this.popState(),T.getLogger().debug("Lex: /]"),"NODE_DEND";break;case 51:return this.popState(),T.getLogger().debug("Lex: )]"),"NODE_DEND";break;case 52:return this.popState(),T.getLogger().debug("Lex: )"),"NODE_DEND";break;case 53:return this.popState(),T.getLogger().debug("Lex: ]>"),"NODE_DEND";break;case 54:return this.popState(),T.getLogger().debug("Lex: ]"),"NODE_DEND";break;case 55:return T.getLogger().debug("Lexa: -)"),this.pushState("NODE"),36;break;case 56:return T.getLogger().debug("Lexa: (-"),this.pushState("NODE"),36;break;case 57:return T.getLogger().debug("Lexa: ))"),this.pushState("NODE"),36;break;case 58:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 59:return T.getLogger().debug("Lex: ((("),this.pushState("NODE"),36;break;case 60:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 61:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 62:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 63:return T.getLogger().debug("Lexc: >"),this.pushState("NODE"),36;break;case 64:return T.getLogger().debug("Lexa: (["),this.pushState("NODE"),36;break;case 65:return T.getLogger().debug("Lexa: )"),this.pushState("NODE"),36;break;case 66:return this.pushState("NODE"),36;break;case 67:return this.pushState("NODE"),36;break;case 68:return this.pushState("NODE"),36;break;case 69:return this.pushState("NODE"),36;break;case 70:return this.pushState("NODE"),36;break;case 71:return this.pushState("NODE"),36;break;case 72:return this.pushState("NODE"),36;break;case 73:return T.getLogger().debug("Lexa: ["),this.pushState("NODE"),36;break;case 74:return this.pushState("BLOCK_ARROW"),T.getLogger().debug("LEX ARR START"),38;break;case 75:return T.getLogger().debug("Lex: NODE_ID",E.yytext),32;break;case 76:return T.getLogger().debug("Lex: EOF",E.yytext),8;break;case 77:this.pushState("md_string");break;case 78:this.pushState("md_string");break;case 79:return"NODE_DESCR";case 80:this.popState();break;case 81:T.getLogger().debug("Lex: Starting string"),this.pushState("string");break;case 82:T.getLogger().debug("LEX ARR: Starting string"),this.pushState("string");break;case 83:return T.getLogger().debug("LEX: NODE_DESCR:",E.yytext),"NODE_DESCR";break;case 84:T.getLogger().debug("LEX POPPING"),this.popState();break;case 85:T.getLogger().debug("Lex: =>BAE"),this.pushState("ARROW_DIR");break;case 86:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (right): dir:",E.yytext),"DIR";break;case 87:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (left):",E.yytext),"DIR";break;case 88:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (x):",E.yytext),"DIR";break;case 89:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (y):",E.yytext),"DIR";break;case 90:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex (up):",E.yytext),"DIR";break;case 91:return E.yytext=E.yytext.replace(/^,\s*/,""),T.getLogger().debug("Lex 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g=this.child.getNodes(),y=0;yp?(this.rect.x-=(this.labelWidth-p)/2,this.setWidth(this.labelWidth)):this.labelPosHorizontal=="right"&&this.setWidth(p+this.labelWidth)),this.labelHeight&&(this.labelPosVertical=="top"?(this.rect.y-=this.labelHeight,this.setHeight(m+this.labelHeight)):this.labelPosVertical=="center"&&this.labelHeight>m?(this.rect.y-=(this.labelHeight-m)/2,this.setHeight(this.labelHeight)):this.labelPosVertical=="bottom"&&this.setHeight(m+this.labelHeight))}}},h.prototype.getInclusionTreeDepth=function(){if(this.inclusionTreeDepth==i.MAX_VALUE)throw"assert failed";return this.inclusionTreeDepth},h.prototype.transform=function(d){var p=this.rect.x;p>s.WORLD_BOUNDARY?p=s.WORLD_BOUNDARY:p<-s.WORLD_BOUNDARY&&(p=-s.WORLD_BOUNDARY);var m=this.rect.y;m>s.WORLD_BOUNDARY?m=s.WORLD_BOUNDARY:m<-s.WORLD_BOUNDARY&&(m=-s.WORLD_BOUNDARY);var g=new u(p,m),y=d.inverseTransformPoint(g);this.setLocation(y.x,y.y)},h.prototype.getLeft=function(){return this.rect.x},h.prototype.getRight=function(){return this.rect.x+this.rect.width},h.prototype.getTop=function(){return this.rect.y},h.prototype.getBottom=function(){return this.rect.y+this.rect.height},h.prototype.getParent=function(){return this.owner==null?null:this.owner.getParent()},t.exports=h},function(t,e,r){"use strict";var n=r(0);function i(){}o(i,"FDLayoutConstants");for(var a in n)i[a]=n[a];i.MAX_ITERATIONS=2500,i.DEFAULT_EDGE_LENGTH=50,i.DEFAULT_SPRING_STRENGTH=.45,i.DEFAULT_REPULSION_STRENGTH=4500,i.DEFAULT_GRAVITY_STRENGTH=.4,i.DEFAULT_COMPOUND_GRAVITY_STRENGTH=1,i.DEFAULT_GRAVITY_RANGE_FACTOR=3.8,i.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR=1.5,i.DEFAULT_USE_SMART_IDEAL_EDGE_LENGTH_CALCULATION=!0,i.DEFAULT_USE_SMART_REPULSION_RANGE_CALCULATION=!0,i.DEFAULT_COOLING_FACTOR_INCREMENTAL=.3,i.COOLING_ADAPTATION_FACTOR=.33,i.ADAPTATION_LOWER_NODE_LIMIT=1e3,i.ADAPTATION_UPPER_NODE_LIMIT=5e3,i.MAX_NODE_DISPLACEMENT_INCREMENTAL=100,i.MAX_NODE_DISPLACEMENT=i.MAX_NODE_DISPLACEMENT_INCREMENTAL*3,i.MIN_REPULSION_DIST=i.DEFAULT_EDGE_LENGTH/10,i.CONVERGENCE_CHECK_PERIOD=100,i.PER_LEVEL_IDEAL_EDGE_LENGTH_FACTOR=.1,i.MIN_EDGE_LENGTH=1,i.GRID_CALCULATION_CHECK_PERIOD=10,t.exports=i},function(t,e,r){"use strict";function n(i,a){i==null&&a==null?(this.x=0,this.y=0):(this.x=i,this.y=a)}o(n,"PointD"),n.prototype.getX=function(){return this.x},n.prototype.getY=function(){return this.y},n.prototype.setX=function(i){this.x=i},n.prototype.setY=function(i){this.y=i},n.prototype.getDifference=function(i){return new DimensionD(this.x-i.x,this.y-i.y)},n.prototype.getCopy=function(){return new n(this.x,this.y)},n.prototype.translate=function(i){return this.x+=i.width,this.y+=i.height,this},t.exports=n},function(t,e,r){"use strict";var n=r(2),i=r(10),a=r(0),s=r(7),l=r(3),u=r(1),h=r(13),f=r(12),d=r(11);function p(g,y,v){n.call(this,v),this.estimatedSize=i.MIN_VALUE,this.margin=a.DEFAULT_GRAPH_MARGIN,this.edges=[],this.nodes=[],this.isConnected=!1,this.parent=g,y!=null&&y instanceof s?this.graphManager=y:y!=null&&y instanceof Layout&&(this.graphManager=y.graphManager)}o(p,"LGraph"),p.prototype=Object.create(n.prototype);for(var m in n)p[m]=n[m];p.prototype.getNodes=function(){return this.nodes},p.prototype.getEdges=function(){return this.edges},p.prototype.getGraphManager=function(){return this.graphManager},p.prototype.getParent=function(){return this.parent},p.prototype.getLeft=function(){return this.left},p.prototype.getRight=function(){return this.right},p.prototype.getTop=function(){return this.top},p.prototype.getBottom=function(){return this.bottom},p.prototype.isConnected=function(){return this.isConnected},p.prototype.add=function(g,y,v){if(y==null&&v==null){var x=g;if(this.graphManager==null)throw"Graph has no graph mgr!";if(this.getNodes().indexOf(x)>-1)throw"Node already in graph!";return x.owner=this,this.getNodes().push(x),x}else{var b=g;if(!(this.getNodes().indexOf(y)>-1&&this.getNodes().indexOf(v)>-1))throw"Source or target not in graph!";if(!(y.owner==v.owner&&y.owner==this))throw"Both owners must be this graph!";return y.owner!=v.owner?null:(b.source=y,b.target=v,b.isInterGraph=!1,this.getEdges().push(b),y.edges.push(b),v!=y&&v.edges.push(b),b)}},p.prototype.remove=function(g){var y=g;if(g instanceof l){if(y==null)throw"Node is null!";if(!(y.owner!=null&&y.owner==this))throw"Owner graph is invalid!";if(this.graphManager==null)throw"Owner graph manager is invalid!";for(var v=y.edges.slice(),x,b=v.length,w=0;w-1&&E>-1))throw"Source and/or target doesn't know this edge!";x.source.edges.splice(T,1),x.target!=x.source&&x.target.edges.splice(E,1);var C=x.source.owner.getEdges().indexOf(x);if(C==-1)throw"Not in owner's edge list!";x.source.owner.getEdges().splice(C,1)}},p.prototype.updateLeftTop=function(){for(var g=i.MAX_VALUE,y=i.MAX_VALUE,v,x,b,w=this.getNodes(),C=w.length,T=0;Tv&&(g=v),y>x&&(y=x)}return g==i.MAX_VALUE?null:(w[0].getParent().paddingLeft!=null?b=w[0].getParent().paddingLeft:b=this.margin,this.left=y-b,this.top=g-b,new f(this.left,this.top))},p.prototype.updateBounds=function(g){for(var y=i.MAX_VALUE,v=-i.MAX_VALUE,x=i.MAX_VALUE,b=-i.MAX_VALUE,w,C,T,E,A,S=this.nodes,_=S.length,I=0;I<_;I++){var D=S[I];g&&D.child!=null&&D.updateBounds(),w=D.getLeft(),C=D.getRight(),T=D.getTop(),E=D.getBottom(),y>w&&(y=w),vT&&(x=T),bw&&(y=w),vT&&(x=T),b=this.nodes.length){var _=0;v.forEach(function(I){I.owner==g&&_++}),_==this.nodes.length&&(this.isConnected=!0)}},t.exports=p},function(t,e,r){"use strict";var n,i=r(1);function a(s){n=r(6),this.layout=s,this.graphs=[],this.edges=[]}o(a,"LGraphManager"),a.prototype.addRoot=function(){var s=this.layout.newGraph(),l=this.layout.newNode(null),u=this.add(s,l);return this.setRootGraph(u),this.rootGraph},a.prototype.add=function(s,l,u,h,f){if(u==null&&h==null&&f==null){if(s==null)throw"Graph is null!";if(l==null)throw"Parent node is null!";if(this.graphs.indexOf(s)>-1)throw"Graph already in this graph mgr!";if(this.graphs.push(s),s.parent!=null)throw"Already has a parent!";if(l.child!=null)throw"Already has a child!";return s.parent=l,l.child=s,s}else{f=u,h=l,u=s;var d=h.getOwner(),p=f.getOwner();if(!(d!=null&&d.getGraphManager()==this))throw"Source not in this graph mgr!";if(!(p!=null&&p.getGraphManager()==this))throw"Target not in this graph mgr!";if(d==p)return u.isInterGraph=!1,d.add(u,h,f);if(u.isInterGraph=!0,u.source=h,u.target=f,this.edges.indexOf(u)>-1)throw"Edge already in inter-graph edge list!";if(this.edges.push(u),!(u.source!=null&&u.target!=null))throw"Edge source and/or target is null!";if(!(u.source.edges.indexOf(u)==-1&&u.target.edges.indexOf(u)==-1))throw"Edge already in source and/or target incidency list!";return u.source.edges.push(u),u.target.edges.push(u),u}},a.prototype.remove=function(s){if(s instanceof n){var l=s;if(l.getGraphManager()!=this)throw"Graph not in this graph mgr";if(!(l==this.rootGraph||l.parent!=null&&l.parent.graphManager==this))throw"Invalid parent node!";var u=[];u=u.concat(l.getEdges());for(var h,f=u.length,d=0;d=s.getRight()?l[0]+=Math.min(s.getX()-a.getX(),a.getRight()-s.getRight()):s.getX()<=a.getX()&&s.getRight()>=a.getRight()&&(l[0]+=Math.min(a.getX()-s.getX(),s.getRight()-a.getRight())),a.getY()<=s.getY()&&a.getBottom()>=s.getBottom()?l[1]+=Math.min(s.getY()-a.getY(),a.getBottom()-s.getBottom()):s.getY()<=a.getY()&&s.getBottom()>=a.getBottom()&&(l[1]+=Math.min(a.getY()-s.getY(),s.getBottom()-a.getBottom()));var f=Math.abs((s.getCenterY()-a.getCenterY())/(s.getCenterX()-a.getCenterX()));s.getCenterY()===a.getCenterY()&&s.getCenterX()===a.getCenterX()&&(f=1);var d=f*l[0],p=l[1]/f;l[0]d)return l[0]=u,l[1]=m,l[2]=f,l[3]=S,!1;if(hf)return l[0]=p,l[1]=h,l[2]=E,l[3]=d,!1;if(uf?(l[0]=y,l[1]=v,k=!0):(l[0]=g,l[1]=m,k=!0):R===M&&(u>f?(l[0]=p,l[1]=m,k=!0):(l[0]=x,l[1]=v,k=!0)),-O===M?f>u?(l[2]=A,l[3]=S,L=!0):(l[2]=E,l[3]=T,L=!0):O===M&&(f>u?(l[2]=C,l[3]=T,L=!0):(l[2]=_,l[3]=S,L=!0)),k&&L)return!1;if(u>f?h>d?(B=this.getCardinalDirection(R,M,4),F=this.getCardinalDirection(O,M,2)):(B=this.getCardinalDirection(-R,M,3),F=this.getCardinalDirection(-O,M,1)):h>d?(B=this.getCardinalDirection(-R,M,1),F=this.getCardinalDirection(-O,M,3)):(B=this.getCardinalDirection(R,M,2),F=this.getCardinalDirection(O,M,4)),!k)switch(B){case 1:z=m,P=u+-w/M,l[0]=P,l[1]=z;break;case 2:P=x,z=h+b*M,l[0]=P,l[1]=z;break;case 3:z=v,P=u+w/M,l[0]=P,l[1]=z;break;case 4:P=y,z=h+-b*M,l[0]=P,l[1]=z;break}if(!L)switch(F){case 1:H=T,$=f+-D/M,l[2]=$,l[3]=H;break;case 2:$=_,H=d+I*M,l[2]=$,l[3]=H;break;case 3:H=S,$=f+D/M,l[2]=$,l[3]=H;break;case 4:$=A,H=d+-I*M,l[2]=$,l[3]=H;break}}return!1},i.getCardinalDirection=function(a,s,l){return a>s?l:1+l%4},i.getIntersection=function(a,s,l,u){if(u==null)return this.getIntersection2(a,s,l);var h=a.x,f=a.y,d=s.x,p=s.y,m=l.x,g=l.y,y=u.x,v=u.y,x=void 0,b=void 0,w=void 0,C=void 0,T=void 0,E=void 0,A=void 0,S=void 0,_=void 0;return w=p-f,T=h-d,A=d*f-h*p,C=v-g,E=m-y,S=y*g-m*v,_=w*E-C*T,_===0?null:(x=(T*S-E*A)/_,b=(C*A-w*S)/_,new n(x,b))},i.angleOfVector=function(a,s,l,u){var h=void 0;return a!==l?(h=Math.atan((u-s)/(l-a)),l=0){var v=(-m+Math.sqrt(m*m-4*p*g))/(2*p),x=(-m-Math.sqrt(m*m-4*p*g))/(2*p),b=null;return v>=0&&v<=1?[v]:x>=0&&x<=1?[x]:b}else return null},i.HALF_PI=.5*Math.PI,i.ONE_AND_HALF_PI=1.5*Math.PI,i.TWO_PI=2*Math.PI,i.THREE_PI=3*Math.PI,t.exports=i},function(t,e,r){"use strict";function n(){}o(n,"IMath"),n.sign=function(i){return i>0?1:i<0?-1:0},n.floor=function(i){return i<0?Math.ceil(i):Math.floor(i)},n.ceil=function(i){return i<0?Math.floor(i):Math.ceil(i)},t.exports=n},function(t,e,r){"use strict";function n(){}o(n,"Integer"),n.MAX_VALUE=2147483647,n.MIN_VALUE=-2147483648,t.exports=n},function(t,e,r){"use strict";var n=function(){function h(f,d){for(var p=0;p"u"?"undefined":n(a);return a==null||s!="object"&&s!="function"},t.exports=i},function(t,e,r){"use strict";function n(m){if(Array.isArray(m)){for(var g=0,y=Array(m.length);g0&&g;){for(w.push(T[0]);w.length>0&&g;){var E=w[0];w.splice(0,1),b.add(E);for(var A=E.getEdges(),x=0;x-1&&T.splice(D,1)}b=new Set,C=new Map}}return m},p.prototype.createDummyNodesForBendpoints=function(m){for(var g=[],y=m.source,v=this.graphManager.calcLowestCommonAncestor(m.source,m.target),x=0;x0){for(var v=this.edgeToDummyNodes.get(y),x=0;x=0&&g.splice(S,1);var _=C.getNeighborsList();_.forEach(function(k){if(y.indexOf(k)<0){var L=v.get(k),R=L-1;R==1&&E.push(k),v.set(k,R)}})}y=y.concat(E),(g.length==1||g.length==2)&&(x=!0,b=g[0])}return b},p.prototype.setGraphManager=function(m){this.graphManager=m},t.exports=p},function(t,e,r){"use strict";function n(){}o(n,"RandomSeed"),n.seed=1,n.x=0,n.nextDouble=function(){return n.x=Math.sin(n.seed++)*1e4,n.x-Math.floor(n.x)},t.exports=n},function(t,e,r){"use strict";var n=r(5);function i(a,s){this.lworldOrgX=0,this.lworldOrgY=0,this.ldeviceOrgX=0,this.ldeviceOrgY=0,this.lworldExtX=1,this.lworldExtY=1,this.ldeviceExtX=1,this.ldeviceExtY=1}o(i,"Transform"),i.prototype.getWorldOrgX=function(){return this.lworldOrgX},i.prototype.setWorldOrgX=function(a){this.lworldOrgX=a},i.prototype.getWorldOrgY=function(){return this.lworldOrgY},i.prototype.setWorldOrgY=function(a){this.lworldOrgY=a},i.prototype.getWorldExtX=function(){return this.lworldExtX},i.prototype.setWorldExtX=function(a){this.lworldExtX=a},i.prototype.getWorldExtY=function(){return this.lworldExtY},i.prototype.setWorldExtY=function(a){this.lworldExtY=a},i.prototype.getDeviceOrgX=function(){return this.ldeviceOrgX},i.prototype.setDeviceOrgX=function(a){this.ldeviceOrgX=a},i.prototype.getDeviceOrgY=function(){return this.ldeviceOrgY},i.prototype.setDeviceOrgY=function(a){this.ldeviceOrgY=a},i.prototype.getDeviceExtX=function(){return this.ldeviceExtX},i.prototype.setDeviceExtX=function(a){this.ldeviceExtX=a},i.prototype.getDeviceExtY=function(){return this.ldeviceExtY},i.prototype.setDeviceExtY=function(a){this.ldeviceExtY=a},i.prototype.transformX=function(a){var s=0,l=this.lworldExtX;return l!=0&&(s=this.ldeviceOrgX+(a-this.lworldOrgX)*this.ldeviceExtX/l),s},i.prototype.transformY=function(a){var s=0,l=this.lworldExtY;return l!=0&&(s=this.ldeviceOrgY+(a-this.lworldOrgY)*this.ldeviceExtY/l),s},i.prototype.inverseTransformX=function(a){var s=0,l=this.ldeviceExtX;return l!=0&&(s=this.lworldOrgX+(a-this.ldeviceOrgX)*this.lworldExtX/l),s},i.prototype.inverseTransformY=function(a){var s=0,l=this.ldeviceExtY;return l!=0&&(s=this.lworldOrgY+(a-this.ldeviceOrgY)*this.lworldExtY/l),s},i.prototype.inverseTransformPoint=function(a){var s=new n(this.inverseTransformX(a.x),this.inverseTransformY(a.y));return s},t.exports=i},function(t,e,r){"use strict";function n(d){if(Array.isArray(d)){for(var p=0,m=Array(d.length);pa.ADAPTATION_LOWER_NODE_LIMIT&&(this.coolingFactor=Math.max(this.coolingFactor*a.COOLING_ADAPTATION_FACTOR,this.coolingFactor-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*this.coolingFactor*(1-a.COOLING_ADAPTATION_FACTOR))),this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT_INCREMENTAL):(d>a.ADAPTATION_LOWER_NODE_LIMIT?this.coolingFactor=Math.max(a.COOLING_ADAPTATION_FACTOR,1-(d-a.ADAPTATION_LOWER_NODE_LIMIT)/(a.ADAPTATION_UPPER_NODE_LIMIT-a.ADAPTATION_LOWER_NODE_LIMIT)*(1-a.COOLING_ADAPTATION_FACTOR)):this.coolingFactor=1,this.initialCoolingFactor=this.coolingFactor,this.maxNodeDisplacement=a.MAX_NODE_DISPLACEMENT),this.maxIterations=Math.max(this.getAllNodes().length*5,this.maxIterations),this.displacementThresholdPerNode=3*a.DEFAULT_EDGE_LENGTH/100,this.totalDisplacementThreshold=this.displacementThresholdPerNode*this.getAllNodes().length,this.repulsionRange=this.calcRepulsionRange()},h.prototype.calcSpringForces=function(){for(var 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n(){}o(n,"SVD"),n.svd=function(i){this.U=null,this.V=null,this.s=null,this.m=0,this.n=0,this.m=i.length,this.n=i[0].length;var a=Math.min(this.m,this.n);this.s=function(xt){for(var ut=[];xt-- >0;)ut.push(0);return ut}(Math.min(this.m+1,this.n)),this.U=function(xt){var ut=o(function Et(ft){if(ft.length==0)return 0;for(var yt=[],nt=0;nt0;)ut.push(0);return ut}(this.n),l=function(xt){for(var ut=[];xt-- >0;)ut.push(0);return ut}(this.m),u=!0,h=!0,f=Math.min(this.m-1,this.n),d=Math.max(0,Math.min(this.n-2,this.m)),p=0;p=0;M--)if(this.s[M]!==0){for(var B=M+1;B=0;j--){if(function(xt,ut){return xt&&ut}(j0;){var ue=void 0,Z=void 0;for(ue=L-2;ue>=-1&&ue!==-1;ue--)if(Math.abs(s[ue])<=se+J*(Math.abs(this.s[ue])+Math.abs(this.s[ue+1]))){s[ue]=0;break}if(ue===L-2)Z=4;else{var Se=void 0;for(Se=L-1;Se>=ue&&Se!==ue;Se--){var ce=(Se!==L?Math.abs(s[Se]):0)+(Se!==ue+1?Math.abs(s[Se-1]):0);if(Math.abs(this.s[Se])<=se+J*ce){this.s[Se]=0;break}}Se===ue?Z=3:Se===L-1?Z=1:(Z=2,ue=Se)}switch(ue++,Z){case 1:{var ae=s[L-2];s[L-2]=0;for(var Oe=L-2;Oe>=ue;Oe--){var ge=n.hypot(this.s[Oe],ae),ze=this.s[Oe]/ge,He=ae/ge;if(this.s[Oe]=ge,Oe!==ue&&(ae=-He*s[Oe-1],s[Oe-1]=ze*s[Oe-1]),h)for(var $e=0;$e=this.s[ue+1]);){var ot=this.s[ue];if(this.s[ue]=this.s[ue+1],this.s[ue+1]=ot,h&&ueMath.abs(a)?(s=a/i,s=Math.abs(i)*Math.sqrt(1+s*s)):a!=0?(s=i/a,s=Math.abs(a)*Math.sqrt(1+s*s)):s=0,s},t.exports=n},function(t,e,r){"use strict";var n=function(){function s(l,u){for(var h=0;h2&&arguments[2]!==void 0?arguments[2]:1,f=arguments.length>3&&arguments[3]!==void 0?arguments[3]:-1,d=arguments.length>4&&arguments[4]!==void 0?arguments[4]:-1;i(this,s),this.sequence1=l,this.sequence2=u,this.match_score=h,this.mismatch_penalty=f,this.gap_penalty=d,this.iMax=l.length+1,this.jMax=u.length+1,this.grid=new Array(this.iMax);for(var p=0;p=0;l--){var u=this.listeners[l];u.event===a&&u.callback===s&&this.listeners.splice(l,1)}},i.emit=function(a,s){for(var l=0;l{"use strict";o(function(e,r){typeof k4=="object"&&typeof pF=="object"?pF.exports=r(dF()):typeof define=="function"&&define.amd?define(["layout-base"],r):typeof k4=="object"?k4.coseBase=r(dF()):e.coseBase=r(e.layoutBase)},"webpackUniversalModuleDefinition")(k4,function(t){return(()=>{"use strict";var e={45:(a,s,l)=>{var u={};u.layoutBase=l(551),u.CoSEConstants=l(806),u.CoSEEdge=l(767),u.CoSEGraph=l(880),u.CoSEGraphManager=l(578),u.CoSELayout=l(765),u.CoSENode=l(991),u.ConstraintHandler=l(902),a.exports=u},806:(a,s,l)=>{var u=l(551).FDLayoutConstants;function h(){}o(h,"CoSEConstants");for(var f in u)h[f]=u[f];h.DEFAULT_USE_MULTI_LEVEL_SCALING=!1,h.DEFAULT_RADIAL_SEPARATION=u.DEFAULT_EDGE_LENGTH,h.DEFAULT_COMPONENT_SEPERATION=60,h.TILE=!0,h.TILING_PADDING_VERTICAL=10,h.TILING_PADDING_HORIZONTAL=10,h.TRANSFORM_ON_CONSTRAINT_HANDLING=!0,h.ENFORCE_CONSTRAINTS=!0,h.APPLY_LAYOUT=!0,h.RELAX_MOVEMENT_ON_CONSTRAINTS=!0,h.TREE_REDUCTION_ON_INCREMENTAL=!0,h.PURE_INCREMENTAL=h.DEFAULT_INCREMENTAL,a.exports=h},767:(a,s,l)=>{var u=l(551).FDLayoutEdge;function h(d,p,m){u.call(this,d,p,m)}o(h,"CoSEEdge"),h.prototype=Object.create(u.prototype);for(var f in u)h[f]=u[f];a.exports=h},880:(a,s,l)=>{var u=l(551).LGraph;function h(d,p,m){u.call(this,d,p,m)}o(h,"CoSEGraph"),h.prototype=Object.create(u.prototype);for(var f in u)h[f]=u[f];a.exports=h},578:(a,s,l)=>{var u=l(551).LGraphManager;function h(d){u.call(this,d)}o(h,"CoSEGraphManager"),h.prototype=Object.create(u.prototype);for(var f in u)h[f]=u[f];a.exports=h},765:(a,s,l)=>{var u=l(551).FDLayout,h=l(578),f=l(880),d=l(991),p=l(767),m=l(806),g=l(902),y=l(551).FDLayoutConstants,v=l(551).LayoutConstants,x=l(551).Point,b=l(551).PointD,w=l(551).DimensionD,C=l(551).Layout,T=l(551).Integer,E=l(551).IGeometry,A=l(551).LGraph,S=l(551).Transform,_=l(551).LinkedList;function I(){u.call(this),this.toBeTiled={},this.constraints={}}o(I,"CoSELayout"),I.prototype=Object.create(u.prototype);for(var D in u)I[D]=u[D];I.prototype.newGraphManager=function(){var k=new h(this);return this.graphManager=k,k},I.prototype.newGraph=function(k){return new f(null,this.graphManager,k)},I.prototype.newNode=function(k){return new d(this.graphManager,k)},I.prototype.newEdge=function(k){return new p(null,null,k)},I.prototype.initParameters=function(){u.prototype.initParameters.call(this,arguments),this.isSubLayout||(m.DEFAULT_EDGE_LENGTH<10?this.idealEdgeLength=10:this.idealEdgeLength=m.DEFAULT_EDGE_LENGTH,this.useSmartIdealEdgeLengthCalculation=m.DEFAULT_USE_SMART_IDEAL_EDGE_LENGTH_CALCULATION,this.gravityConstant=y.DEFAULT_GRAVITY_STRENGTH,this.compoundGravityConstant=y.DEFAULT_COMPOUND_GRAVITY_STRENGTH,this.gravityRangeFactor=y.DEFAULT_GRAVITY_RANGE_FACTOR,this.compoundGravityRangeFactor=y.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR,this.prunedNodesAll=[],this.growTreeIterations=0,this.afterGrowthIterations=0,this.isTreeGrowing=!1,this.isGrowthFinished=!1)},I.prototype.initSpringEmbedder=function(){u.prototype.initSpringEmbedder.call(this),this.coolingCycle=0,this.maxCoolingCycle=this.maxIterations/y.CONVERGENCE_CHECK_PERIOD,this.finalTemperature=.04,this.coolingAdjuster=1},I.prototype.layout=function(){var k=v.DEFAULT_CREATE_BENDS_AS_NEEDED;return k&&(this.createBendpoints(),this.graphManager.resetAllEdges()),this.level=0,this.classicLayout()},I.prototype.classicLayout=function(){if(this.nodesWithGravity=this.calculateNodesToApplyGravitationTo(),this.graphManager.setAllNodesToApplyGravitation(this.nodesWithGravity),this.calcNoOfChildrenForAllNodes(),this.graphManager.calcLowestCommonAncestors(),this.graphManager.calcInclusionTreeDepths(),this.graphManager.getRoot().calcEstimatedSize(),this.calcIdealEdgeLengths(),this.incremental){if(m.TREE_REDUCTION_ON_INCREMENTAL){this.reduceTrees(),this.graphManager.resetAllNodesToApplyGravitation();var L=new Set(this.getAllNodes()),R=this.nodesWithGravity.filter(function(B){return L.has(B)});this.graphManager.setAllNodesToApplyGravitation(R)}}else{var k=this.getFlatForest();if(k.length>0)this.positionNodesRadially(k);else{this.reduceTrees(),this.graphManager.resetAllNodesToApplyGravitation();var L=new Set(this.getAllNodes()),R=this.nodesWithGravity.filter(function(O){return L.has(O)});this.graphManager.setAllNodesToApplyGravitation(R),this.positionNodesRandomly()}}return Object.keys(this.constraints).length>0&&(g.handleConstraints(this),this.initConstraintVariables()),this.initSpringEmbedder(),m.APPLY_LAYOUT&&this.runSpringEmbedder(),!0},I.prototype.tick=function(){if(this.totalIterations++,this.totalIterations===this.maxIterations&&!this.isTreeGrowing&&!this.isGrowthFinished)if(this.prunedNodesAll.length>0)this.isTreeGrowing=!0;else return!0;if(this.totalIterations%y.CONVERGENCE_CHECK_PERIOD==0&&!this.isTreeGrowing&&!this.isGrowthFinished){if(this.isConverged())if(this.prunedNodesAll.length>0)this.isTreeGrowing=!0;else return!0;this.coolingCycle++,this.layoutQuality==0?this.coolingAdjuster=this.coolingCycle:this.layoutQuality==1&&(this.coolingAdjuster=this.coolingCycle/3),this.coolingFactor=Math.max(this.initialCoolingFactor-Math.pow(this.coolingCycle,Math.log(100*(this.initialCoolingFactor-this.finalTemperature))/Math.log(this.maxCoolingCycle))/100*this.coolingAdjuster,this.finalTemperature),this.animationPeriod=Math.ceil(this.initialAnimationPeriod*Math.sqrt(this.coolingFactor))}if(this.isTreeGrowing){if(this.growTreeIterations%10==0)if(this.prunedNodesAll.length>0){this.graphManager.updateBounds(),this.updateGrid(),this.growTree(this.prunedNodesAll),this.graphManager.resetAllNodesToApplyGravitation();var k=new Set(this.getAllNodes()),L=this.nodesWithGravity.filter(function(M){return k.has(M)});this.graphManager.setAllNodesToApplyGravitation(L),this.graphManager.updateBounds(),this.updateGrid(),m.PURE_INCREMENTAL?this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL/2:this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL}else this.isTreeGrowing=!1,this.isGrowthFinished=!0;this.growTreeIterations++}if(this.isGrowthFinished){if(this.isConverged())return!0;this.afterGrowthIterations%10==0&&(this.graphManager.updateBounds(),this.updateGrid()),m.PURE_INCREMENTAL?this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL/2*((100-this.afterGrowthIterations)/100):this.coolingFactor=y.DEFAULT_COOLING_FACTOR_INCREMENTAL*((100-this.afterGrowthIterations)/100),this.afterGrowthIterations++}var R=!this.isTreeGrowing&&!this.isGrowthFinished,O=this.growTreeIterations%10==1&&this.isTreeGrowing||this.afterGrowthIterations%10==1&&this.isGrowthFinished;return this.totalDisplacement=0,this.graphManager.updateBounds(),this.calcSpringForces(),this.calcRepulsionForces(R,O),this.calcGravitationalForces(),this.moveNodes(),this.animate(),!1},I.prototype.getPositionsData=function(){for(var k=this.graphManager.getAllNodes(),L={},R=0;R0&&this.updateDisplacements();for(var R=0;R0&&(O.fixedNodeWeight=B)}}if(this.constraints.relativePlacementConstraint){var F=new Map,P=new Map;if(this.dummyToNodeForVerticalAlignment=new Map,this.dummyToNodeForHorizontalAlignment=new Map,this.fixedNodesOnHorizontal=new Set,this.fixedNodesOnVertical=new Set,this.fixedNodeSet.forEach(function(le){k.fixedNodesOnHorizontal.add(le),k.fixedNodesOnVertical.add(le)}),this.constraints.alignmentConstraint){if(this.constraints.alignmentConstraint.vertical)for(var z=this.constraints.alignmentConstraint.vertical,R=0;R=2*le.length/3;X--)he=Math.floor(Math.random()*(X+1)),K=le[X],le[X]=le[he],le[he]=K;return le},this.nodesInRelativeHorizontal=[],this.nodesInRelativeVertical=[],this.nodeToRelativeConstraintMapHorizontal=new Map,this.nodeToRelativeConstraintMapVertical=new Map,this.nodeToTempPositionMapHorizontal=new Map,this.nodeToTempPositionMapVertical=new Map,this.constraints.relativePlacementConstraint.forEach(function(le){if(le.left){var he=F.has(le.left)?F.get(le.left):le.left,K=F.has(le.right)?F.get(le.right):le.right;k.nodesInRelativeHorizontal.includes(he)||(k.nodesInRelativeHorizontal.push(he),k.nodeToRelativeConstraintMapHorizontal.set(he,[]),k.dummyToNodeForVerticalAlignment.has(he)?k.nodeToTempPositionMapHorizontal.set(he,k.idToNodeMap.get(k.dummyToNodeForVerticalAlignment.get(he)[0]).getCenterX()):k.nodeToTempPositionMapHorizontal.set(he,k.idToNodeMap.get(he).getCenterX())),k.nodesInRelativeHorizontal.includes(K)||(k.nodesInRelativeHorizontal.push(K),k.nodeToRelativeConstraintMapHorizontal.set(K,[]),k.dummyToNodeForVerticalAlignment.has(K)?k.nodeToTempPositionMapHorizontal.set(K,k.idToNodeMap.get(k.dummyToNodeForVerticalAlignment.get(K)[0]).getCenterX()):k.nodeToTempPositionMapHorizontal.set(K,k.idToNodeMap.get(K).getCenterX())),k.nodeToRelativeConstraintMapHorizontal.get(he).push({right:K,gap:le.gap}),k.nodeToRelativeConstraintMapHorizontal.get(K).push({left:he,gap:le.gap})}else{var X=P.has(le.top)?P.get(le.top):le.top,te=P.has(le.bottom)?P.get(le.bottom):le.bottom;k.nodesInRelativeVertical.includes(X)||(k.nodesInRelativeVertical.push(X),k.nodeToRelativeConstraintMapVertical.set(X,[]),k.dummyToNodeForHorizontalAlignment.has(X)?k.nodeToTempPositionMapVertical.set(X,k.idToNodeMap.get(k.dummyToNodeForHorizontalAlignment.get(X)[0]).getCenterY()):k.nodeToTempPositionMapVertical.set(X,k.idToNodeMap.get(X).getCenterY())),k.nodesInRelativeVertical.includes(te)||(k.nodesInRelativeVertical.push(te),k.nodeToRelativeConstraintMapVertical.set(te,[]),k.dummyToNodeForHorizontalAlignment.has(te)?k.nodeToTempPositionMapVertical.set(te,k.idToNodeMap.get(k.dummyToNodeForHorizontalAlignment.get(te)[0]).getCenterY()):k.nodeToTempPositionMapVertical.set(te,k.idToNodeMap.get(te).getCenterY())),k.nodeToRelativeConstraintMapVertical.get(X).push({bottom:te,gap:le.gap}),k.nodeToRelativeConstraintMapVertical.get(te).push({top:X,gap:le.gap})}});else{var H=new Map,Q=new Map;this.constraints.relativePlacementConstraint.forEach(function(le){if(le.left){var he=F.has(le.left)?F.get(le.left):le.left,K=F.has(le.right)?F.get(le.right):le.right;H.has(he)?H.get(he).push(K):H.set(he,[K]),H.has(K)?H.get(K).push(he):H.set(K,[he])}else{var X=P.has(le.top)?P.get(le.top):le.top,te=P.has(le.bottom)?P.get(le.bottom):le.bottom;Q.has(X)?Q.get(X).push(te):Q.set(X,[te]),Q.has(te)?Q.get(te).push(X):Q.set(te,[X])}});var j=o(function(he,K){var X=[],te=[],J=new _,se=new Set,ue=0;return he.forEach(function(Z,Se){if(!se.has(Se)){X[ue]=[],te[ue]=!1;var ce=Se;for(J.push(ce),se.add(ce),X[ue].push(ce);J.length!=0;){ce=J.shift(),K.has(ce)&&(te[ue]=!0);var ae=he.get(ce);ae.forEach(function(Oe){se.has(Oe)||(J.push(Oe),se.add(Oe),X[ue].push(Oe))})}ue++}}),{components:X,isFixed:te}},"constructComponents"),ie=j(H,k.fixedNodesOnHorizontal);this.componentsOnHorizontal=ie.components,this.fixedComponentsOnHorizontal=ie.isFixed;var ne=j(Q,k.fixedNodesOnVertical);this.componentsOnVertical=ne.components,this.fixedComponentsOnVertical=ne.isFixed}}},I.prototype.updateDisplacements=function(){var k=this;if(this.constraints.fixedNodeConstraint&&this.constraints.fixedNodeConstraint.forEach(function(ne){var le=k.idToNodeMap.get(ne.nodeId);le.displacementX=0,le.displacementY=0}),this.constraints.alignmentConstraint){if(this.constraints.alignmentConstraint.vertical)for(var L=this.constraints.alignmentConstraint.vertical,R=0;R1){var P;for(P=0;PO&&(O=Math.floor(F.y)),B=Math.floor(F.x+m.DEFAULT_COMPONENT_SEPERATION)}this.transform(new b(v.WORLD_CENTER_X-F.x/2,v.WORLD_CENTER_Y-F.y/2))},I.radialLayout=function(k,L,R){var O=Math.max(this.maxDiagonalInTree(k),m.DEFAULT_RADIAL_SEPARATION);I.branchRadialLayout(L,null,0,359,0,O);var M=A.calculateBounds(k),B=new S;B.setDeviceOrgX(M.getMinX()),B.setDeviceOrgY(M.getMinY()),B.setWorldOrgX(R.x),B.setWorldOrgY(R.y);for(var F=0;F1;){var X=K[0];K.splice(0,1);var te=j.indexOf(X);te>=0&&j.splice(te,1),le--,ie--}L!=null?he=(j.indexOf(K[0])+1)%le:he=0;for(var J=Math.abs(O-R)/ie,se=he;ne!=ie;se=++se%le){var ue=j[se].getOtherEnd(k);if(ue!=L){var Z=(R+ne*J)%360,Se=(Z+J)%360;I.branchRadialLayout(ue,k,Z,Se,M+B,B),ne++}}},I.maxDiagonalInTree=function(k){for(var L=T.MIN_VALUE,R=0;RL&&(L=M)}return L},I.prototype.calcRepulsionRange=function(){return 2*(this.level+1)*this.idealEdgeLength},I.prototype.groupZeroDegreeMembers=function(){var k=this,L={};this.memberGroups={},this.idToDummyNode={};for(var R=[],O=this.graphManager.getAllNodes(),M=0;M"u"&&(L[P]=[]),L[P]=L[P].concat(B)}Object.keys(L).forEach(function(z){if(L[z].length>1){var $="DummyCompound_"+z;k.memberGroups[$]=L[z];var H=L[z][0].getParent(),Q=new d(k.graphManager);Q.id=$,Q.paddingLeft=H.paddingLeft||0,Q.paddingRight=H.paddingRight||0,Q.paddingBottom=H.paddingBottom||0,Q.paddingTop=H.paddingTop||0,k.idToDummyNode[$]=Q;var j=k.getGraphManager().add(k.newGraph(),Q),ie=H.getChild();ie.add(Q);for(var ne=0;neM?(O.rect.x-=(O.labelWidth-M)/2,O.setWidth(O.labelWidth),O.labelMarginLeft=(O.labelWidth-M)/2):O.labelPosHorizontal=="right"&&O.setWidth(M+O.labelWidth)),O.labelHeight&&(O.labelPosVertical=="top"?(O.rect.y-=O.labelHeight,O.setHeight(B+O.labelHeight),O.labelMarginTop=O.labelHeight):O.labelPosVertical=="center"&&O.labelHeight>B?(O.rect.y-=(O.labelHeight-B)/2,O.setHeight(O.labelHeight),O.labelMarginTop=(O.labelHeight-B)/2):O.labelPosVertical=="bottom"&&O.setHeight(B+O.labelHeight))}})},I.prototype.repopulateCompounds=function(){for(var k=this.compoundOrder.length-1;k>=0;k--){var L=this.compoundOrder[k],R=L.id,O=L.paddingLeft,M=L.paddingTop,B=L.labelMarginLeft,F=L.labelMarginTop;this.adjustLocations(this.tiledMemberPack[R],L.rect.x,L.rect.y,O,M,B,F)}},I.prototype.repopulateZeroDegreeMembers=function(){var k=this,L=this.tiledZeroDegreePack;Object.keys(L).forEach(function(R){var O=k.idToDummyNode[R],M=O.paddingLeft,B=O.paddingTop,F=O.labelMarginLeft,P=O.labelMarginTop;k.adjustLocations(L[R],O.rect.x,O.rect.y,M,B,F,P)})},I.prototype.getToBeTiled=function(k){var L=k.id;if(this.toBeTiled[L]!=null)return this.toBeTiled[L];var R=k.getChild();if(R==null)return this.toBeTiled[L]=!1,!1;for(var O=R.getNodes(),M=0;M0)return this.toBeTiled[L]=!1,!1;if(B.getChild()==null){this.toBeTiled[B.id]=!1;continue}if(!this.getToBeTiled(B))return this.toBeTiled[L]=!1,!1}return this.toBeTiled[L]=!0,!0},I.prototype.getNodeDegree=function(k){for(var L=k.id,R=k.getEdges(),O=0,M=0;MH&&(H=j.rect.height)}R+=H+k.verticalPadding}},I.prototype.tileCompoundMembers=function(k,L){var R=this;this.tiledMemberPack=[],Object.keys(k).forEach(function(O){var M=L[O];if(R.tiledMemberPack[O]=R.tileNodes(k[O],M.paddingLeft+M.paddingRight),M.rect.width=R.tiledMemberPack[O].width,M.rect.height=R.tiledMemberPack[O].height,M.setCenter(R.tiledMemberPack[O].centerX,R.tiledMemberPack[O].centerY),M.labelMarginLeft=0,M.labelMarginTop=0,m.NODE_DIMENSIONS_INCLUDE_LABELS){var B=M.rect.width,F=M.rect.height;M.labelWidth&&(M.labelPosHorizontal=="left"?(M.rect.x-=M.labelWidth,M.setWidth(B+M.labelWidth),M.labelMarginLeft=M.labelWidth):M.labelPosHorizontal=="center"&&M.labelWidth>B?(M.rect.x-=(M.labelWidth-B)/2,M.setWidth(M.labelWidth),M.labelMarginLeft=(M.labelWidth-B)/2):M.labelPosHorizontal=="right"&&M.setWidth(B+M.labelWidth)),M.labelHeight&&(M.labelPosVertical=="top"?(M.rect.y-=M.labelHeight,M.setHeight(F+M.labelHeight),M.labelMarginTop=M.labelHeight):M.labelPosVertical=="center"&&M.labelHeight>F?(M.rect.y-=(M.labelHeight-F)/2,M.setHeight(M.labelHeight),M.labelMarginTop=(M.labelHeight-F)/2):M.labelPosVertical=="bottom"&&M.setHeight(F+M.labelHeight))}})},I.prototype.tileNodes=function(k,L){var R=this.tileNodesByFavoringDim(k,L,!0),O=this.tileNodesByFavoringDim(k,L,!1),M=this.getOrgRatio(R),B=this.getOrgRatio(O),F;return BP&&(P=ne.getWidth())});var z=B/M,$=F/M,H=Math.pow(R-O,2)+4*(z+O)*($+R)*M,Q=(O-R+Math.sqrt(H))/(2*(z+O)),j;L?(j=Math.ceil(Q),j==Q&&j++):j=Math.floor(Q);var ie=j*(z+O)-O;return P>ie&&(ie=P),ie+=O*2,ie},I.prototype.tileNodesByFavoringDim=function(k,L,R){var O=m.TILING_PADDING_VERTICAL,M=m.TILING_PADDING_HORIZONTAL,B=m.TILING_COMPARE_BY,F={rows:[],rowWidth:[],rowHeight:[],width:0,height:L,verticalPadding:O,horizontalPadding:M,centerX:0,centerY:0};B&&(F.idealRowWidth=this.calcIdealRowWidth(k,R));var P=o(function(le){return le.rect.width*le.rect.height},"getNodeArea"),z=o(function(le,he){return P(he)-P(le)},"areaCompareFcn");k.sort(function(ne,le){var he=z;return F.idealRowWidth?(he=B,he(ne.id,le.id)):he(ne,le)});for(var $=0,H=0,Q=0;Q0&&(F+=k.horizontalPadding),k.rowWidth[R]=F,k.width0&&(P+=k.verticalPadding);var z=0;P>k.rowHeight[R]&&(z=k.rowHeight[R],k.rowHeight[R]=P,z=k.rowHeight[R]-z),k.height+=z,k.rows[R].push(L)},I.prototype.getShortestRowIndex=function(k){for(var L=-1,R=Number.MAX_VALUE,O=0;OR&&(L=O,R=k.rowWidth[O]);return L},I.prototype.canAddHorizontal=function(k,L,R){if(k.idealRowWidth){var O=k.rows.length-1,M=k.rowWidth[O];return M+L+k.horizontalPadding<=k.idealRowWidth}var B=this.getShortestRowIndex(k);if(B<0)return!0;var F=k.rowWidth[B];if(F+k.horizontalPadding+L<=k.width)return!0;var P=0;k.rowHeight[B]0&&(P=R+k.verticalPadding-k.rowHeight[B]);var z;k.width-F>=L+k.horizontalPadding?z=(k.height+P)/(F+L+k.horizontalPadding):z=(k.height+P)/k.width,P=R+k.verticalPadding;var $;return k.widthB&&L!=R){O.splice(-1,1),k.rows[R].push(M),k.rowWidth[L]=k.rowWidth[L]-B,k.rowWidth[R]=k.rowWidth[R]+B,k.width=k.rowWidth[instance.getLongestRowIndex(k)];for(var F=Number.MIN_VALUE,P=0;PF&&(F=O[P].height);L>0&&(F+=k.verticalPadding);var z=k.rowHeight[L]+k.rowHeight[R];k.rowHeight[L]=F,k.rowHeight[R]0)for(var ie=M;ie<=B;ie++)j[0]+=this.grid[ie][F-1].length+this.grid[ie][F].length-1;if(B0)for(var ie=F;ie<=P;ie++)j[3]+=this.grid[M-1][ie].length+this.grid[M][ie].length-1;for(var ne=T.MAX_VALUE,le,he,K=0;K{var u=l(551).FDLayoutNode,h=l(551).IMath;function f(p,m,g,y){u.call(this,p,m,g,y)}o(f,"CoSENode"),f.prototype=Object.create(u.prototype);for(var d in u)f[d]=u[d];f.prototype.calculateDisplacement=function(){var p=this.graphManager.getLayout();this.getChild()!=null&&this.fixedNodeWeight?(this.displacementX+=p.coolingFactor*(this.springForceX+this.repulsionForceX+this.gravitationForceX)/this.fixedNodeWeight,this.displacementY+=p.coolingFactor*(this.springForceY+this.repulsionForceY+this.gravitationForceY)/this.fixedNodeWeight):(this.displacementX+=p.coolingFactor*(this.springForceX+this.repulsionForceX+this.gravitationForceX)/this.noOfChildren,this.displacementY+=p.coolingFactor*(this.springForceY+this.repulsionForceY+this.gravitationForceY)/this.noOfChildren),Math.abs(this.displacementX)>p.coolingFactor*p.maxNodeDisplacement&&(this.displacementX=p.coolingFactor*p.maxNodeDisplacement*h.sign(this.displacementX)),Math.abs(this.displacementY)>p.coolingFactor*p.maxNodeDisplacement&&(this.displacementY=p.coolingFactor*p.maxNodeDisplacement*h.sign(this.displacementY)),this.child&&this.child.getNodes().length>0&&this.propogateDisplacementToChildren(this.displacementX,this.displacementY)},f.prototype.propogateDisplacementToChildren=function(p,m){for(var g=this.getChild().getNodes(),y,v=0;v{function u(g){if(Array.isArray(g)){for(var y=0,v=Array(g.length);y0){var ct=0;Ue.forEach(function(ot){xe=="horizontal"?(we.set(ot,x.has(ot)?b[x.get(ot)]:pe.get(ot)),ct+=we.get(ot)):(we.set(ot,x.has(ot)?w[x.get(ot)]:pe.get(ot)),ct+=we.get(ot))}),ct=ct/Ue.length,st.forEach(function(ot){q.has(ot)||we.set(ot,ct)})}else{var We=0;st.forEach(function(ot){xe=="horizontal"?We+=x.has(ot)?b[x.get(ot)]:pe.get(ot):We+=x.has(ot)?w[x.get(ot)]:pe.get(ot)}),We=We/st.length,st.forEach(function(ot){we.set(ot,We)})}});for(var qe=o(function(){var Ue=De.shift(),ct=V.get(Ue);ct.forEach(function(We){if(we.get(We.id)ot&&(ot=yt),ntYt&&(Yt=nt)}}catch(At){Mt=!0,xt=At}finally{try{!bt&&ut.return&&ut.return()}finally{if(Mt)throw xt}}var dn=(ct+ot)/2-(We+Yt)/2,Tt=!0,On=!1,tn=void 0;try{for(var _r=st[Symbol.iterator](),Dr;!(Tt=(Dr=_r.next()).done);Tt=!0){var Pn=Dr.value;we.set(Pn,we.get(Pn)+dn)}}catch(At){On=!0,tn=At}finally{try{!Tt&&_r.return&&_r.return()}finally{if(On)throw tn}}})}return we},"findAppropriatePositionForRelativePlacement"),D=o(function(V){var xe=0,q=0,pe=0,ve=0;if(V.forEach(function(Ve){Ve.left?b[x.get(Ve.left)]-b[x.get(Ve.right)]>=0?xe++:q++:w[x.get(Ve.top)]-w[x.get(Ve.bottom)]>=0?pe++:ve++}),xe>q&&pe>ve)for(var Pe=0;Peq)for(var _e=0;_eve)for(var we=0;we1)y.fixedNodeConstraint.forEach(function(oe,V){O[V]=[oe.position.x,oe.position.y],M[V]=[b[x.get(oe.nodeId)],w[x.get(oe.nodeId)]]}),B=!0;else if(y.alignmentConstraint)(function(){var oe=0;if(y.alignmentConstraint.vertical){for(var V=y.alignmentConstraint.vertical,xe=o(function(we){var Ve=new Set;V[we].forEach(function(at){Ve.add(at)});var De=new Set([].concat(u(Ve)).filter(function(at){return P.has(at)})),qe=void 0;De.size>0?qe=b[x.get(De.values().next().value)]:qe=_(Ve).x,V[we].forEach(function(at){O[oe]=[qe,w[x.get(at)]],M[oe]=[b[x.get(at)],w[x.get(at)]],oe++})},"_loop2"),q=0;q0?qe=b[x.get(De.values().next().value)]:qe=_(Ve).y,pe[we].forEach(function(at){O[oe]=[b[x.get(at)],qe],M[oe]=[b[x.get(at)],w[x.get(at)]],oe++})},"_loop3"),Pe=0;PeQ&&(Q=H[ie].length,j=ie);if(Q<$.size/2)D(y.relativePlacementConstraint),B=!1,F=!1;else{var ne=new Map,le=new Map,he=[];H[j].forEach(function(oe){z.get(oe).forEach(function(V){V.direction=="horizontal"?(ne.has(oe)?ne.get(oe).push(V):ne.set(oe,[V]),ne.has(V.id)||ne.set(V.id,[]),he.push({left:oe,right:V.id})):(le.has(oe)?le.get(oe).push(V):le.set(oe,[V]),le.has(V.id)||le.set(V.id,[]),he.push({top:oe,bottom:V.id}))})}),D(he),F=!1;var K=I(ne,"horizontal"),X=I(le,"vertical");H[j].forEach(function(oe,V){M[V]=[b[x.get(oe)],w[x.get(oe)]],O[V]=[],K.has(oe)?O[V][0]=K.get(oe):O[V][0]=b[x.get(oe)],X.has(oe)?O[V][1]=X.get(oe):O[V][1]=w[x.get(oe)]}),B=!0}}if(B){for(var te=void 0,J=d.transpose(O),se=d.transpose(M),ue=0;ue0){var ze={x:0,y:0};y.fixedNodeConstraint.forEach(function(oe,V){var xe={x:b[x.get(oe.nodeId)],y:w[x.get(oe.nodeId)]},q=oe.position,pe=S(q,xe);ze.x+=pe.x,ze.y+=pe.y}),ze.x/=y.fixedNodeConstraint.length,ze.y/=y.fixedNodeConstraint.length,b.forEach(function(oe,V){b[V]+=ze.x}),w.forEach(function(oe,V){w[V]+=ze.y}),y.fixedNodeConstraint.forEach(function(oe){b[x.get(oe.nodeId)]=oe.position.x,w[x.get(oe.nodeId)]=oe.position.y})}if(y.alignmentConstraint){if(y.alignmentConstraint.vertical)for(var He=y.alignmentConstraint.vertical,$e=o(function(V){var xe=new Set;He[V].forEach(function(ve){xe.add(ve)});var q=new Set([].concat(u(xe)).filter(function(ve){return P.has(ve)})),pe=void 0;q.size>0?pe=b[x.get(q.values().next().value)]:pe=_(xe).x,xe.forEach(function(ve){P.has(ve)||(b[x.get(ve)]=pe)})},"_loop4"),Re=0;Re0?pe=w[x.get(q.values().next().value)]:pe=_(xe).y,xe.forEach(function(ve){P.has(ve)||(w[x.get(ve)]=pe)})},"_loop5"),W=0;W{a.exports=t}},r={};function n(a){var s=r[a];if(s!==void 0)return s.exports;var l=r[a]={exports:{}};return e[a](l,l.exports,n),l.exports}o(n,"__webpack_require__");var i=n(45);return i})()})});var Pve=Mi((E4,gF)=>{"use strict";o(function(e,r){typeof E4=="object"&&typeof gF=="object"?gF.exports=r(mF()):typeof define=="function"&&define.amd?define(["cose-base"],r):typeof E4=="object"?E4.cytoscapeFcose=r(mF()):e.cytoscapeFcose=r(e.coseBase)},"webpackUniversalModuleDefinition")(E4,function(t){return(()=>{"use strict";var e={658:a=>{a.exports=Object.assign!=null?Object.assign.bind(Object):function(s){for(var l=arguments.length,u=Array(l>1?l-1:0),h=1;h{var u=function(){function d(p,m){var g=[],y=!0,v=!1,x=void 0;try{for(var b=p[Symbol.iterator](),w;!(y=(w=b.next()).done)&&(g.push(w.value),!(m&&g.length===m));y=!0);}catch(C){v=!0,x=C}finally{try{!y&&b.return&&b.return()}finally{if(v)throw x}}return g}return o(d,"sliceIterator"),function(p,m){if(Array.isArray(p))return p;if(Symbol.iterator in Object(p))return d(p,m);throw new TypeError("Invalid attempt to destructure non-iterable instance")}}(),h=l(140).layoutBase.LinkedList,f={};f.getTopMostNodes=function(d){for(var p={},m=0;m0&&B.merge($)});for(var F=0;F1){w=x[0],C=w.connectedEdges().length,x.forEach(function(M){M.connectedEdges().length0&&g.set("dummy"+(g.size+1),A),S},f.relocateComponent=function(d,p,m){if(!m.fixedNodeConstraint){var g=Number.POSITIVE_INFINITY,y=Number.NEGATIVE_INFINITY,v=Number.POSITIVE_INFINITY,x=Number.NEGATIVE_INFINITY;if(m.quality=="draft"){var b=!0,w=!1,C=void 0;try{for(var T=p.nodeIndexes[Symbol.iterator](),E;!(b=(E=T.next()).done);b=!0){var A=E.value,S=u(A,2),_=S[0],I=S[1],D=m.cy.getElementById(_);if(D){var k=D.boundingBox(),L=p.xCoords[I]-k.w/2,R=p.xCoords[I]+k.w/2,O=p.yCoords[I]-k.h/2,M=p.yCoords[I]+k.h/2;Ly&&(y=R),Ox&&(x=M)}}}catch($){w=!0,C=$}finally{try{!b&&T.return&&T.return()}finally{if(w)throw C}}var B=d.x-(y+g)/2,F=d.y-(x+v)/2;p.xCoords=p.xCoords.map(function($){return $+B}),p.yCoords=p.yCoords.map(function($){return $+F})}else{Object.keys(p).forEach(function($){var H=p[$],Q=H.getRect().x,j=H.getRect().x+H.getRect().width,ie=H.getRect().y,ne=H.getRect().y+H.getRect().height;Qy&&(y=j),iex&&(x=ne)});var P=d.x-(y+g)/2,z=d.y-(x+v)/2;Object.keys(p).forEach(function($){var H=p[$];H.setCenter(H.getCenterX()+P,H.getCenterY()+z)})}}},f.calcBoundingBox=function(d,p,m,g){for(var y=Number.MAX_SAFE_INTEGER,v=Number.MIN_SAFE_INTEGER,x=Number.MAX_SAFE_INTEGER,b=Number.MIN_SAFE_INTEGER,w=void 0,C=void 0,T=void 0,E=void 0,A=d.descendants().not(":parent"),S=A.length,_=0;_w&&(y=w),vT&&(x=T),b{var u=l(548),h=l(140).CoSELayout,f=l(140).CoSENode,d=l(140).layoutBase.PointD,p=l(140).layoutBase.DimensionD,m=l(140).layoutBase.LayoutConstants,g=l(140).layoutBase.FDLayoutConstants,y=l(140).CoSEConstants,v=o(function(b,w){var C=b.cy,T=b.eles,E=T.nodes(),A=T.edges(),S=void 0,_=void 0,I=void 0,D={};b.randomize&&(S=w.nodeIndexes,_=w.xCoords,I=w.yCoords);var k=o(function($){return typeof $=="function"},"isFn"),L=o(function($,H){return k($)?$(H):$},"optFn"),R=u.calcParentsWithoutChildren(C,T),O=o(function z($,H,Q,j){for(var ie=H.length,ne=0;ne0){var J=void 0;J=Q.getGraphManager().add(Q.newGraph(),K),z(J,he,Q,j)}}},"processChildrenList"),M=o(function($,H,Q){for(var j=0,ie=0,ne=0;ne0?y.DEFAULT_EDGE_LENGTH=g.DEFAULT_EDGE_LENGTH=j/ie:k(b.idealEdgeLength)?y.DEFAULT_EDGE_LENGTH=g.DEFAULT_EDGE_LENGTH=50:y.DEFAULT_EDGE_LENGTH=g.DEFAULT_EDGE_LENGTH=b.idealEdgeLength,y.MIN_REPULSION_DIST=g.MIN_REPULSION_DIST=g.DEFAULT_EDGE_LENGTH/10,y.DEFAULT_RADIAL_SEPARATION=g.DEFAULT_EDGE_LENGTH)},"processEdges"),B=o(function($,H){H.fixedNodeConstraint&&($.constraints.fixedNodeConstraint=H.fixedNodeConstraint),H.alignmentConstraint&&($.constraints.alignmentConstraint=H.alignmentConstraint),H.relativePlacementConstraint&&($.constraints.relativePlacementConstraint=H.relativePlacementConstraint)},"processConstraints");b.nestingFactor!=null&&(y.PER_LEVEL_IDEAL_EDGE_LENGTH_FACTOR=g.PER_LEVEL_IDEAL_EDGE_LENGTH_FACTOR=b.nestingFactor),b.gravity!=null&&(y.DEFAULT_GRAVITY_STRENGTH=g.DEFAULT_GRAVITY_STRENGTH=b.gravity),b.numIter!=null&&(y.MAX_ITERATIONS=g.MAX_ITERATIONS=b.numIter),b.gravityRange!=null&&(y.DEFAULT_GRAVITY_RANGE_FACTOR=g.DEFAULT_GRAVITY_RANGE_FACTOR=b.gravityRange),b.gravityCompound!=null&&(y.DEFAULT_COMPOUND_GRAVITY_STRENGTH=g.DEFAULT_COMPOUND_GRAVITY_STRENGTH=b.gravityCompound),b.gravityRangeCompound!=null&&(y.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR=g.DEFAULT_COMPOUND_GRAVITY_RANGE_FACTOR=b.gravityRangeCompound),b.initialEnergyOnIncremental!=null&&(y.DEFAULT_COOLING_FACTOR_INCREMENTAL=g.DEFAULT_COOLING_FACTOR_INCREMENTAL=b.initialEnergyOnIncremental),b.tilingCompareBy!=null&&(y.TILING_COMPARE_BY=b.tilingCompareBy),b.quality=="proof"?m.QUALITY=2:m.QUALITY=0,y.NODE_DIMENSIONS_INCLUDE_LABELS=g.NODE_DIMENSIONS_INCLUDE_LABELS=m.NODE_DIMENSIONS_INCLUDE_LABELS=b.nodeDimensionsIncludeLabels,y.DEFAULT_INCREMENTAL=g.DEFAULT_INCREMENTAL=m.DEFAULT_INCREMENTAL=!b.randomize,y.ANIMATE=g.ANIMATE=m.ANIMATE=b.animate,y.TILE=b.tile,y.TILING_PADDING_VERTICAL=typeof b.tilingPaddingVertical=="function"?b.tilingPaddingVertical.call():b.tilingPaddingVertical,y.TILING_PADDING_HORIZONTAL=typeof b.tilingPaddingHorizontal=="function"?b.tilingPaddingHorizontal.call():b.tilingPaddingHorizontal,y.DEFAULT_INCREMENTAL=g.DEFAULT_INCREMENTAL=m.DEFAULT_INCREMENTAL=!0,y.PURE_INCREMENTAL=!b.randomize,m.DEFAULT_UNIFORM_LEAF_NODE_SIZES=b.uniformNodeDimensions,b.step=="transformed"&&(y.TRANSFORM_ON_CONSTRAINT_HANDLING=!0,y.ENFORCE_CONSTRAINTS=!1,y.APPLY_LAYOUT=!1),b.step=="enforced"&&(y.TRANSFORM_ON_CONSTRAINT_HANDLING=!1,y.ENFORCE_CONSTRAINTS=!0,y.APPLY_LAYOUT=!1),b.step=="cose"&&(y.TRANSFORM_ON_CONSTRAINT_HANDLING=!1,y.ENFORCE_CONSTRAINTS=!1,y.APPLY_LAYOUT=!0),b.step=="all"&&(b.randomize?y.TRANSFORM_ON_CONSTRAINT_HANDLING=!0:y.TRANSFORM_ON_CONSTRAINT_HANDLING=!1,y.ENFORCE_CONSTRAINTS=!0,y.APPLY_LAYOUT=!0),b.fixedNodeConstraint||b.alignmentConstraint||b.relativePlacementConstraint?y.TREE_REDUCTION_ON_INCREMENTAL=!1:y.TREE_REDUCTION_ON_INCREMENTAL=!0;var F=new h,P=F.newGraphManager();return O(P.addRoot(),u.getTopMostNodes(E),F,b),M(F,P,A),B(F,b),F.runLayout(),D},"coseLayout");a.exports={coseLayout:v}},212:(a,s,l)=>{var u=function(){function b(w,C){for(var T=0;T0)if(M){var P=d.getTopMostNodes(T.eles.nodes());if(k=d.connectComponents(E,T.eles,P),k.forEach(function(ce){var ae=ce.boundingBox();L.push({x:ae.x1+ae.w/2,y:ae.y1+ae.h/2})}),T.randomize&&k.forEach(function(ce){T.eles=ce,S.push(m(T))}),T.quality=="default"||T.quality=="proof"){var z=E.collection();if(T.tile){var $=new Map,H=[],Q=[],j=0,ie={nodeIndexes:$,xCoords:H,yCoords:Q},ne=[];if(k.forEach(function(ce,ae){ce.edges().length==0&&(ce.nodes().forEach(function(Oe,ge){z.merge(ce.nodes()[ge]),Oe.isParent()||(ie.nodeIndexes.set(ce.nodes()[ge].id(),j++),ie.xCoords.push(ce.nodes()[0].position().x),ie.yCoords.push(ce.nodes()[0].position().y))}),ne.push(ae))}),z.length>1){var le=z.boundingBox();L.push({x:le.x1+le.w/2,y:le.y1+le.h/2}),k.push(z),S.push(ie);for(var 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D[ae][He.id()]&&ge.nodes.push({x:D[ae][He.id()].getLeft(),y:D[ae][He.id()].getTop(),width:D[ae][He.id()].getWidth(),height:D[ae][He.id()].getHeight()})}),ce.edges().forEach(function(He){var $e=He.source(),Re=He.target();if($e.css("display")!="none"&&Re.css("display")!="none")if(T.quality=="draft"){var Ie=Oe.get($e.id()),be=Oe.get(Re.id()),W=[],de=[];if($e.isParent()){var re=d.calcBoundingBox($e,S[ae].xCoords,S[ae].yCoords,Oe);W.push(re.topLeftX+re.width/2),W.push(re.topLeftY+re.height/2)}else W.push(S[ae].xCoords[Ie]),W.push(S[ae].yCoords[Ie]);if(Re.isParent()){var oe=d.calcBoundingBox(Re,S[ae].xCoords,S[ae].yCoords,Oe);de.push(oe.topLeftX+oe.width/2),de.push(oe.topLeftY+oe.height/2)}else de.push(S[ae].xCoords[be]),de.push(S[ae].yCoords[be]);ge.edges.push({startX:W[0],startY:W[1],endX:de[0],endY:de[1]})}else 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MIT License: http://en.wikipedia.org/wiki/MIT_License *) -*/ -globalThis.mermaid = globalThis.__esbuild_esm_mermaid.default; diff --git a/docs/bb-note/src/README.md b/docs/bb-note/src/README.md deleted file mode 120000 index 8a33348c..00000000 --- a/docs/bb-note/src/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../README.md \ No newline at end of file diff --git a/docs/bb-note/src/SUMMARY.md b/docs/bb-note/src/SUMMARY.md deleted file mode 100644 index 63297bfc..00000000 --- a/docs/bb-note/src/SUMMARY.md +++ /dev/null @@ -1,43 +0,0 @@ -# Summary - -- [Project Overview](./README.md) - - [Project Structure](./overview/overview.md) - - [Development Tutorial](./tutorial/tutorial.md) - -- [Architecture Design](./arch/arch.md) - - [Scala Source Code](./arch/src/main/scala/README.md) - - [Util](./arch/src/main/scala/Util/README.md) - - [framework](./arch/src/main/scala/framework/README.md) - - [prototype](./arch/src/main/scala/prototype/README.md) - - [format](./arch/src/main/scala/prototype/format/README.md) - - [im2col](./arch/src/main/scala/prototype/im2col/README.md) - - [matrix](./arch/src/main/scala/prototype/matrix/README.md) - - [transpose](./arch/src/main/scala/prototype/transpose/README.md) - - [vector](./arch/src/main/scala/prototype/vector/README.md) - - [bond](./arch/src/main/scala/prototype/vector/bond/README.md) - - [op](./arch/src/main/scala/prototype/vector/op/README.md) - - [thread](./arch/src/main/scala/prototype/vector/thread/README.md) - - [warp](./arch/src/main/scala/prototype/vector/warp/README.md) - - [examples](./arch/src/main/scala/examples/README.md) - - [toy](./arch/src/main/scala/examples/toy/README.md) - - [balldomain](./arch/src/main/scala/examples/toy/balldomain/README.md) - - [bbus](./arch/src/main/scala/examples/toy/balldomain/bbus/README.md) - - [rs](./arch/src/main/scala/examples/toy/balldomain/rs/README.md) - - [sims](./arch/src/main/scala/sims/README.md) - - [firesim](./arch/src/main/scala/sims/firesim/README.md) - - [verilator](./arch/src/main/scala/sims/verilator/README.md) -- [compiler](./compiler/README.md) - - [BuckyballDialect](./compiler/BuckyballDilact/README.md) -- [bbdev](./workflow/README.md) - - [agent](./workflow/steps/agent/README.md) - - [compiler](./workflow/steps/compiler/README.md) - - [doc-agent](./workflow/steps/doc-agent/README.md) - - [marshal](./workflow/steps/marshal/README.md) - - [sardine](./workflow/steps/sardine/README.md) - - [uvm](./workflow/steps/uvm/README.md) - - [verilator](./workflow/steps/verilator/README.md) - - [workload](./workflow/steps/workload/README.md) - ---- - -[Contributors](misc/contributors.md) diff --git a/docs/bb-note/src/arch/arch.md b/docs/bb-note/src/arch/arch.md deleted file mode 100644 index 8439785c..00000000 --- a/docs/bb-note/src/arch/arch.md +++ /dev/null @@ -1,68 +0,0 @@ -# Buckyball Architecture Design Overview - -The Buckyball architecture module contains complete hardware design implementations, based on the RISC-V instruction set architecture, developed using the Scala/Chisel hardware description language. The architecture design follows modular and extensible principles, supporting various configurations and custom extensions. - -## Architecture Hierarchy - -### System-Level Architecture -Buckyball adopts a layered design, including from top to bottom: -- **SoC Subsystem**: Integrates multi-core processors, cache hierarchy, interconnect networks -- **Processor Core**: Custom implementation based on Rocket core -- **Coprocessor**: Dedicated accelerators supporting RoCC interface -- **Memory Subsystem**: High-performance memory controllers and DMA engines - -### Core Features -- **Configurability**: Supports parameter configuration for core count, cache size, bus width, etc. -- **Extensibility**: Provides standardized coprocessor interfaces and extension mechanisms -- **Compatibility**: Maintains compatibility with the standard RISC-V ecosystem -- **Performance Optimization**: Performance-optimized design for specific application scenarios - -## Directory Structure - -``` -arch/ -├── src/main/scala/ -│ └── framework/ - Buckyball framework core -│ ├── rocket/ - Rocket core custom implementation -│ └── builtin/ - Built-in component library -│ └── memdomain/ - Memory domain implementation -│ ├── mem/ - Memory components -│ └── dma/ - DMA engine -└── thirdparty/ - Third-party dependencies - └── chipyard/ - Chipyard framework -``` - -## Design Principles - -### Modular Design -Each functional module has clear interface definitions and independent implementations, facilitating testing, verification, and reuse. Modules communicate through standardized interfaces, reducing coupling. - -### Parameterized Configuration -All hardware modules support parameterized configuration, achieving flexible hardware generation through Scala's type system and configuration framework. Configuration parameters include: -- Data path width -- Cache size and organization -- Parallelism and pipeline depth -- Coprocessor types and quantities - -### Performance Optimization -Specialized performance optimizations for target application scenarios: -- Memory access pattern optimization -- Data pipeline design -- Parallel computing support -- Low-latency communication mechanisms - -## Development Workflow - -1. **Requirement Analysis**: Determine performance and functional requirements for target applications -2. **Architecture Design**: Select appropriate configuration parameters and extension modules -3. **RTL Implementation**: Use Chisel for hardware description and implementation -4. **Functional Verification**: Verify functional correctness through unit tests and integration tests -5. **Performance Evaluation**: Use simulators and FPGA for performance analysis and optimization - -## Toolchain Support - -- **Chisel/FIRRTL**: Hardware description and synthesis toolchain -- **Verilator**: Fast simulation and verification -- **VCS**: Commercial-grade simulation tools -- **FireSim**: FPGA accelerated simulation platform -- **Chipyard**: Integrated development environment and toolchain diff --git a/docs/bb-note/src/arch/src/main/scala/README.md b/docs/bb-note/src/arch/src/main/scala/README.md deleted file mode 120000 index 74e333ea..00000000 --- a/docs/bb-note/src/arch/src/main/scala/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../arch/src/main/scala/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/Util/README.md b/docs/bb-note/src/arch/src/main/scala/Util/README.md deleted file mode 120000 index 48297a46..00000000 --- a/docs/bb-note/src/arch/src/main/scala/Util/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../arch/src/main/scala/Util/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/examples/README.md b/docs/bb-note/src/arch/src/main/scala/examples/README.md deleted file mode 120000 index d8f07b00..00000000 --- a/docs/bb-note/src/arch/src/main/scala/examples/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../arch/src/main/scala/examples/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/examples/toy/README.md b/docs/bb-note/src/arch/src/main/scala/examples/toy/README.md deleted file mode 120000 index f6d2314b..00000000 --- a/docs/bb-note/src/arch/src/main/scala/examples/toy/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/examples/toy/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/README.md b/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/README.md deleted file mode 120000 index 6309bf6e..00000000 --- a/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../arch/src/main/scala/examples/toy/balldomain/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/bbus/README.md b/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/bbus/README.md deleted file mode 120000 index 01677810..00000000 --- a/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/bbus/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../../arch/src/main/scala/examples/toy/balldomain/bbus/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/rs/README.md b/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/rs/README.md deleted file mode 120000 index 3175d85d..00000000 --- a/docs/bb-note/src/arch/src/main/scala/examples/toy/balldomain/rs/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../../arch/src/main/scala/examples/toy/balldomain/rs/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/framework/README.md b/docs/bb-note/src/arch/src/main/scala/framework/README.md deleted file mode 120000 index 17a49722..00000000 --- a/docs/bb-note/src/arch/src/main/scala/framework/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../arch/src/main/scala/framework/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/framework/builtin/README.md b/docs/bb-note/src/arch/src/main/scala/framework/builtin/README.md deleted file mode 120000 index 45c7b104..00000000 --- a/docs/bb-note/src/arch/src/main/scala/framework/builtin/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/framework/builtin/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/framework/builtin/builtin.md b/docs/bb-note/src/arch/src/main/scala/framework/builtin/builtin.md deleted file mode 100644 index dfa8cdef..00000000 --- a/docs/bb-note/src/arch/src/main/scala/framework/builtin/builtin.md +++ /dev/null @@ -1 +0,0 @@ -# builtin diff --git a/docs/bb-note/src/arch/src/main/scala/framework/builtin/util/README.md b/docs/bb-note/src/arch/src/main/scala/framework/builtin/util/README.md deleted file mode 120000 index dbbf2331..00000000 --- a/docs/bb-note/src/arch/src/main/scala/framework/builtin/util/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../arch/src/main/scala/framework/builtin/util/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/framework/framework.md b/docs/bb-note/src/arch/src/main/scala/framework/framework.md deleted file mode 100644 index 6843d6ed..00000000 --- a/docs/bb-note/src/arch/src/main/scala/framework/framework.md +++ /dev/null @@ -1 +0,0 @@ -# framework diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/README.md deleted file mode 120000 index e157e9a5..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../arch/src/main/scala/prototype/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/format/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/format/README.md deleted file mode 120000 index 41014440..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/format/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/prototype/format/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/im2col/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/im2col/README.md deleted file mode 120000 index b6df17ce..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/im2col/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/prototype/im2col/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/matrix/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/matrix/README.md deleted file mode 120000 index 2e67de76..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/matrix/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/prototype/matrix/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/transpose/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/transpose/README.md deleted file mode 120000 index be6c792c..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/transpose/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/prototype/transpose/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/vector/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/vector/README.md deleted file mode 120000 index db1f585d..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/vector/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/prototype/vector/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/vector/bond/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/vector/bond/README.md deleted file mode 120000 index fd054912..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/vector/bond/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../arch/src/main/scala/prototype/vector/bond/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/vector/op/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/vector/op/README.md deleted file mode 120000 index efe9e6c4..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/vector/op/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../arch/src/main/scala/prototype/vector/op/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/vector/thread/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/vector/thread/README.md deleted file mode 120000 index a20e5317..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/vector/thread/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../arch/src/main/scala/prototype/vector/thread/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/prototype/vector/warp/README.md b/docs/bb-note/src/arch/src/main/scala/prototype/vector/warp/README.md deleted file mode 120000 index 5850ac88..00000000 --- a/docs/bb-note/src/arch/src/main/scala/prototype/vector/warp/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../../arch/src/main/scala/prototype/vector/warp/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/sims/README.md b/docs/bb-note/src/arch/src/main/scala/sims/README.md deleted file mode 120000 index 4cf84ab2..00000000 --- a/docs/bb-note/src/arch/src/main/scala/sims/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../arch/src/main/scala/sims/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/sims/firesim/README.md b/docs/bb-note/src/arch/src/main/scala/sims/firesim/README.md deleted file mode 120000 index a292a501..00000000 --- a/docs/bb-note/src/arch/src/main/scala/sims/firesim/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/sims/firesim/README.md \ No newline at end of file diff --git a/docs/bb-note/src/arch/src/main/scala/sims/verilator/README.md b/docs/bb-note/src/arch/src/main/scala/sims/verilator/README.md deleted file mode 120000 index f0a79884..00000000 --- a/docs/bb-note/src/arch/src/main/scala/sims/verilator/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../../../../arch/src/main/scala/sims/verilator/README.md \ No newline at end of file diff --git a/docs/bb-note/src/compiler/BuckyballDilact/README.md b/docs/bb-note/src/compiler/BuckyballDilact/README.md deleted file mode 100644 index fdeeb7b6..00000000 --- a/docs/bb-note/src/compiler/BuckyballDilact/README.md +++ /dev/null @@ -1,41 +0,0 @@ -# Tile Dialect Refactoring Documentation - -## Refactoring Background and Goals - -The core goal of this refactoring is to introduce a new intermediate layer between Linalg Dialect and Buckyball Dialect - the Tile Dialect - to achieve clearer separation of responsibilities and better code organization. In the original architecture, the conversion from `linalg.matmul` to hardware instructions was completed in one step through `convert-linalg-to-buckyball`, which caused Buckyball Dialect to handle both the slicing logic for arbitrary-size matrices and hardware-level memory management and computation scheduling, resulting in overly mixed responsibilities. The new architecture splits the conversion process into two phases: `convert-linalg-to-tile` and `convert-tile-to-buckyball`, making each layer have a clear and single responsibility. - -## New Architecture Design - -The entire compilation flow is now divided into three clear layers. First is the Linalg layer, which represents high-level linear algebra operations, such as `linalg.matmul` representing matrix multiplication of arbitrary size. This layer does not care about hardware constraints. Next is the newly introduced Tile layer, whose core responsibility is to tile arbitrary-size matrix operations into fixed-size blocks that conform to hardware constraints. The Tile layer expresses this high-level tiling intent through the `tile.tile_matmul` operation. The specific tiling strategy, loop generation, and boundary handling are all implemented in the `convert-tile-to-buckyball` pass. Finally, the Buckyball layer focuses on hardware-level operations. `buckyball.bb_matmul` receives pre-tiled fixed-size matrix blocks and is responsible for generating precise hardware instruction sequences, including data movement (mvin/mvout), computation scheduling (mul_warp16), and memory address calculation. - -## Tile Dialect Design Details - -The Tile Dialect defines the `TileMatMulOp` operation, which accepts three memref parameters representing matrices A, B, and C respectively. The semantics of this operation are: perform multiplication on input matrices of arbitrary size, automatically handling tiling, padding, and loops. In implementation, `TileMatMulOp` will be converted by the `convert-tile-to-buckyball` pass into multiple `buckyball.bb_matmul` operations and corresponding `memref.subview` operations. This conversion process will consider hardware scratchpad size limitations, warp and lane parallelism constraints, and generate an optimal tiling strategy. The design philosophy of the Tile layer is to provide a platform-independent intermediate representation, allowing upper-layer optimizations to transform matrix operations without understanding specific hardware details. - -## Buckyball Dialect Simplification - -In the new architecture, the Buckyball Dialect has been significantly simplified. The original four operations `VecTileMatMulOp`, `MergeTileMatMulOp`, `MetaTileMatMulOp`, and `VecMulWarp16Op` have been unified into a single `MatMulOp`. This simplification is reasonable because the tiling logic has been moved up to the Tile layer, and the Buckyball layer only needs to express the single concept of "performing hardware-level multiplication on a matrix block that already conforms to hardware constraints." The lowering process of `buckyball.bb_matmul` will directly generate LLVM intrinsics: first load matrices A and B into the scratchpad through `Mvin_IntrOp`, then generate multiple `Mul_Warp16_IntrOp` operations based on warp and lane parameters for computation, and finally write the results back to main memory through `Mvout_IntrOp`. All address calculations and encodings are completed in this lowering process. - -## Key Implementation Details - -When implementing the `convert-linalg-to-tile` pass, the core logic is very simple: match the `linalg.matmul` operation and directly replace it with `tile.tile_matmul`, passing the same three memref operands. The role of this pass is mainly type and semantic conversion, indicating that we have moved from the general linear algebra operation domain into the hardware-oriented tile operation domain. - -The `convert-tile-to-buckyball` pass is the most complex part of the entire refactoring. It needs to extract matrix dimension information (M, K, N) from the operands of `tile.tile_matmul`, then calculate the optimal tiling strategy based on hardware parameters (dim, warp, lane). For the K dimension, it will tile according to warp size; for M and N dimensions, it will consider scratchpad capacity limitations. Each tile corresponds to a `buckyball.bb_matmul` operation, and tiles are connected through `memref.subview` to create matrix views. Special attention should be paid to handling boundary cases: when matrix dimensions cannot be evenly divided by tile size, the actual size of the last tile needs to be calculated to avoid out-of-bounds access. - -When implementing `BuckyballMatMulLowering`, we encountered an important concept in MLIR's type conversion system: OpAdaptor. In conversion patterns, the types of the original operation (such as `memref<32x16xi8>`) will be converted to LLVM types (such as LLVM struct types) by the TypeConverter during the lowering process. OpAdaptor provides converted values, but we need to obtain type information (such as shape) from the original operation because this static information may no longer exist in the same form after conversion. Therefore, the correct approach is: obtain the original `MemRefType` from `matMulOp.getOperandTypes()` to extract shape information for address calculation and loop generation; for actual value operations (such as `ExtractAlignedPointerAsIndexOp`), use the original memref value, because MLIR's memref operations still require MemRefType. - -Another key design decision is: `MatMulOp`'s lowering should directly generate intrinsic operations (`Mvin_IntrOp`, `Mul_Warp16_IntrOp`, `Mvout_IntrOp`), rather than generating `MvinOp`, `MvoutOp` and then waiting for them to be lowered. The reason is that in the LLVM lowering stage, the type system has already been converted, and creating high-level Buckyball operations again would cause type mismatch issues. Directly generating intrinsics avoids multiple type conversions and makes the code clearer and more efficient. Referring to the Gemmini dialect implementation, we adopted the same strategy. - -## Test System - -To verify the correctness of the new architecture, we created complete test cases in the `bb-tests/workloads/src/OpTest/tile/` directory. Tests are divided into two categories: staged tests and end-to-end tests. - -`tile-matmul.mlir` tests the conversion from Linalg to Tile, verifying that `linalg.matmul` is correctly converted to `tile.tile_matmul`. This is the most basic type conversion test. `tile-to-buckyball.mlir` tests the conversion from Tile to Buckyball, verifying that the tiling logic is correct and that the correct number of `buckyball.bb_matmul` operations and `memref.subview` operations are generated. `buckyball-to-llvm.mlir` tests the conversion from Buckyball MatMulOp to LLVM intrinsics, verifying that the correct sequences of `buckyball.intr.bb_mvin`, `buckyball.intr.bb_mul_warp16`, and `buckyball.intr.bb_mvout` instructions are generated. - -`end-to-end.mlir` is the most important test, testing the complete conversion flow: starting from `linalg.matmul`, sequentially passing through the three passes `-convert-linalg-to-tile`, `-convert-tile-to-buckyball`, `-lower-buckyball`, and finally generating LLVM intrinsics. This test ensures that each part of the entire pipeline works correctly and that there are no issues with the connections between parts. - -## Pass Registration and Toolchain Integration - -The two newly added passes need to be registered in multiple places. First, register the pass creation functions `registerLowerLinalgToTilePass()` and `registerLowerTileToBuckyballPass()` in `InitAll.cpp`, and also register `buddy::tile::TileDialect`. In the `buddy-opt` tool, `buddy::tile::TileDialect` needs to be added to the dialect registry so that the tool can recognize and parse tile dialect operations. In the CMake build system, the new libraries `BuddyTile`, `LowerLinalgToTilePass`, and `LowerTileToBuckyballPass` need to be added to the link dependencies, ensuring correct dependency relationships. - -It is particularly worth noting that in the `configureBuckyballLegalizeForExportTarget` function in `LegalizeForLLVMExport.cpp`, we need to add `target.addLegalDialect()` and `target.addLegalDialect()`, because memref and arith operations will be used during the lowering process of `MatMulOp`. If these dialects are not marked as legal, the conversion framework will attempt to lower these operations, causing type conversion conflicts. diff --git a/docs/bb-note/src/compiler/README.md b/docs/bb-note/src/compiler/README.md deleted file mode 100644 index be7db00d..00000000 --- a/docs/bb-note/src/compiler/README.md +++ /dev/null @@ -1,28 +0,0 @@ -# Compiler Build Guide - -## Basic Workload Compilation - -To build the workload, follow these steps: - -```bash -mkdir build && cd build -cmake -G Ninja .. -ninja -``` - -## Model-Level Testing - -To enable model-level testing with specific models and architectures: - -```bash -mkdir build && cd build -cmake -G Ninja .. \ - -DMODEL="lenet,resnet18,mobilenetv3,bert,stablediffusion,llama2,deepseekr1" \ - -DARCH="gemmini,buckyball" -ninja -``` - -Note: -1. Model downloads for bert, whisper, stable-diffusion, llama2, DeepseekR1 require pre-configured HuggingFace access -2. whisper is currently not supported -3. llama2 model download requires additional API-key or cached credentials diff --git a/docs/bb-note/src/misc/contributors.md b/docs/bb-note/src/misc/contributors.md deleted file mode 100644 index 4be3bf33..00000000 --- a/docs/bb-note/src/misc/contributors.md +++ /dev/null @@ -1,50 +0,0 @@ -# Contributors - -Thank you to all developers and researchers who have contributed to the Buckyball project. - -## Core Development Team - -The Buckyball project is primarily developed by the DangoSys team, dedicated to building a high-performance domain-specific architecture framework. - -## Contribution Methods - -We welcome contributions of all kinds: - -### Code Contributions -- Hardware architecture design and optimization -- Software toolchain improvements -- Test cases and benchmark programs -- Documentation writing and maintenance - -### Issue Feedback -- Bug reports and fix suggestions -- Feature requirements and improvement suggestions -- Performance optimization suggestions -- Usage experience feedback - -### Academic Collaboration -- Research papers and technical reports -- Conference presentations and technical sharing -- Open source community promotion - -## Participation Guidelines - -1. **Fork Project**: Create a project branch from GitHub -2. **Local Development**: Set up development environment according to documentation -3. **Submit Changes**: Follow code standards and commit format -4. **Create PR**: Describe changes and test results in detail -5. **Code Review**: Cooperate with maintainers to complete code review process - -## Contact - -- **GitHub**: [DangoSys/buckyball](https://github.com/DangoSys/buckyball) -- **Issues**: Report issues through GitHub Issues -- **Discussions**: Participate in [Slack](https://buckyballhq.slack.com/) for discussions - -## Acknowledgments - -Special thanks to the following open source projects and communities: -- Buddy-Compiler development team -- Chipyard project -- RISCV Foundation -- All test users and feedback providers diff --git a/docs/bb-note/src/overview/overview.md b/docs/bb-note/src/overview/overview.md deleted file mode 100644 index a9c6e69a..00000000 --- a/docs/bb-note/src/overview/overview.md +++ /dev/null @@ -1,68 +0,0 @@ -# Buckyball Project Structure Overview - -Buckyball is a scalable framework for domain-specific architectures. The project adopts a modular design with clear directory responsibilities, supporting a complete toolchain from hardware design to software development. - -## Main Directory Structure - -### Core Architecture Module -- **`arch/`** - Hardware architecture implementation, containing RTL code written in Scala/Chisel - - Based on Rocket-chip and Chipyard framework - - Implements custom RoCC coprocessors and memory subsystems - - Supports various configuration and extension options - -### Test Verification Module -- **`bb-tests/`** - Unified test framework - - `workloads/` - Application workload tests - - `customext/` - Custom extension verification - - `sardine/` - Sardine test framework - - `uvbb/` - Unit test suite - -### Simulation Environment Module -- **`sims/`** - Simulators and verification environments - - Supports Verilator, VCS and other simulators - - Integrates FireSim FPGA accelerated simulation - - Provides performance analysis and debugging tools - -### Development Tools Module -- **`scripts/`** - Build and deployment scripts - - Environment initialization scripts - - Automated build tools - - Dependency management and configuration - -- **`workflow/`** - Development workflows and automation - - CI/CD pipeline configuration - - Documentation generation tools - - Code quality checks - -### Documentation System -- **`docs/`** - Project documentation - - `bb-note/` - Technical documentation based on mdBook - - `img/` - Documentation image resources - - Supports automatic generation and updates - -### Third-party Dependencies -- **`thirdparty/`** - External dependency modules (**submodules**) - - `chipyard/` - Berkeley Chipyard SoC design framework - - `circt/` - CIRCT circuit compiler toolchain - -## Development Workflow - -1. **Environment Setup**: Use `scripts/init.sh` to initialize the development environment -2. **Architecture Development**: Perform hardware design and modifications in the `arch/` directory -3. **Test Verification**: Use test suites in `bb-tests/` for functional verification -4. **Simulation Debugging**: Perform performance analysis through simulation environments in the `sims/` directory -5. **Documentation Updates**: Automatically generate or manually update technical documentation in `docs/` - -## Build System - -The project supports multiple build methods: -- **Make**: Traditional Makefile builds -- **SBT**: Scala project build tool -- **CMake**: Test framework build system -- **Conda**: Python environment and dependency management - -## Version Management Notes - -- **Submodules**: Modules under `thirdparty/` need independent updates -- **Main Repository**: Core code and configuration update synchronously with the main branch -- **Documentation**: Supports automatic generation, keeping in sync with code changes diff --git a/docs/bb-note/src/tutorial/tutorial.md b/docs/bb-note/src/tutorial/tutorial.md deleted file mode 100644 index f70aa591..00000000 --- a/docs/bb-note/src/tutorial/tutorial.md +++ /dev/null @@ -1,337 +0,0 @@ -# Tutorial for buckyball - -> by - Bohan Wang -> -> This document will be gradually updated as the author continues to solve and summarize encountered issues. - -This document explains the step-by-step process and problem-solving approaches for a complete `buckyball` development workflow. We use building a ball operator module for executing the `relu()` function as an example: - -First, we need to complete the hardware code writing for this module, i.e., write hardware code in Scala's Chisel language and generate corresponding `verilog` code. - -Second, we need to write test software to implement `relu()`, which can be a reference function that runs on `CPU` with software code and an experimental function that runs software code on the dedicated hardware written in step one. If the test results match, it's successful, or proceed to step three for testing. - -Third, simulate at the hardware level, view waveform diagrams for debugging. Additionally, there are other details such as compiler documentation changes, instruction set updates, etc., which will be explained below. - -When encountering issues during development, you can visit [DangoSys/buckyball | DeepWiki](https://deepwiki.com/DangoSys/buckyball) or [Project Overview - Buckyball Technical Documentation](https://dangosys.github.io/buckyball/index.html) - -Chisel learning resources: [binder](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master) - -Before starting officially, let's initialize the environment: - -``` -cd /path/to/buckyball -source env.sh -// source ./env.sh if this gives an error -// All paths in this document are relative paths starting from ./buckyball -``` - -## I. Writing Chisel Hardware Module - -Create a Chisel implementation of the `ReLU` accelerator in the `arch/src/main/scala/prototype/` directory. Referring to existing accelerator structures, it's recommended to create a new subdirectory under `prototype/`, for example `prototype/relu/Relu.scala`, and write the hardware code. - -## II. Hardware Instruction Decoding - -Next, decode hardware instructions. Support for ReLU instructions needs to be added on the **hardware side** so that the hardware decoder recognizes this instruction, and register the instruction set for this ball. - -This work is mainly divided into the following five aspects: - -- Instruction enumeration (DISA) defines func7 → instruction name (RELU) -- Decoder (DomainDecoder) defines func7 → decoding rules (read/write/address/iter) → BID (e.g., 4) -- Bus registration (busRegister) defines BID → actual Ball instance (ReluBall indexed at 4) -- Reservation station registration (rsRegister) is used for RS/issue descriptions, aligned with BID, facilitating system issue/completion management and debugging -If any link is missing or inconsistent, the ReLU instruction cannot be correctly recognized/routed/executed on actual hardware. -- Create a new Ball execution unit `class ReluUnit` to handle ReLU operations. - -#### 1. Define RELU_BITPAT in DISA.scala - -`arch/src/main/scala/examples/toy/balldomain/DISA.scala` defines the funct7 encoding (BitPat) for Ball instructions, such as TRANSPOSE, IM2COL, etc. It can be viewed as an "instruction set enumeration table" for decoder matching. - -Add the bit pattern definition for the ReLU instruction in this file: - -``` -val RELU_BITPAT = BitPat("b0100110") // func7 = 38 = 0x23 -``` - -#### 2. Add ReLU instruction to Ball domain decoder - -`arch/src/main/scala/examples/toy/balldomain/DomainDecoder.scala` is the Ball domain decoder. -Its functions are as follows: -- Input: PostGDCmd from global decoding (already determined to be a Ball category command). -- Output: Structured BallDecodeCmd, including: - - Whether to use op1/op2, whether to write back to scratchpad, whether operands come from scratchpad - - Operand/writeback bank and address - - Iteration count iter - - Target Ball ID (BID) - - Other dedicated fields special, etc. -- Internally maps different funct7 instructions to a set of boolean switches and field extraction rules through ListLookup(func7, ...). - -Add the decoding entry for the ReLU instruction in the decoding list in this file. Referring to the implementation of other instructions (e.g., TRANSPOSE_FUNC7 = 38), you need: - -``` -// Add to BallDecodeFields ListLookup -RELU -> List(Y,N,Y,Y,N, rs1(spAddrLen-1,0), 0.U(spAddrLen.W), rs2(spAddrLen-1,0), rs2(spAddrLen + 9,spAddrLen), 7.U, rs2(63,spAddrLen + 10), Y) // Fill in decoding fields according to specific ReLU instruction requirements, the number of list parameters must be consistent, you can refer to other instructions -``` - -#### 3. Add ReLuBall generator and register it - -a. `arch/src/main/scala/examples/toy/balldomain/bbus/busRegister.scala` is the Ball bus registration table, using a `Seq(() => new SomeBall(...))` to register the actual Ball modules to be instantiated in the system. - -Find and add the new ID for ReLuBall in this file. - -``` -class BBusModule(implicit b: CustomBuckyballConfig, p: Parameters) - extends BBus( - // Define Ball device generator to register - Seq( - () => new examples.toy.balldomain.vecball.VecBall(0), - () => new examples.toy.balldomain.matrixball.MatrixBall(1), - () => new examples.toy.balldomain.im2colball.Im2colBall(2), - () => new examples.toy.balldomain.transposeball.TransposeBall(3), - ... - () =>new examples.toy.balldomain.reluball.ReluBall(7) // Ball ID 7 - newly added - ) - ) { - override lazy val desiredName = "BBusModule" -} -``` - -b. `arch/src/main/scala/examples/toy/balldomain/rs/rsRegister.scala` is the "Ball reservation station" registration table, using a list to register which Balls exist in the system (specifying ID and name by ballId). The reservation station (RS) is responsible for managing Ball issue, occupancy, completion and other metadata, usually also used for visualization/statistics, naming and logging. - -Register ReluBall in this file: - -``` -class BallRSModule(implicit b: CustomBuckyballConfig, p: Parameters) - extends BallReservationStation( - // Define Ball device information to register - Seq( - BallRsRegist(ballId = 0, ballName = "VecBall"), - BallRsRegist(ballId = 1, ballName = "MatrixBall"), - BallRsRegist(ballId = 2, ballName = "Im2colBall"), - BallRsRegist(ballId = 3, ballName = "TransposeBall"), - ... - BallRsRegist(ballId = 7, ballName = "ReluBall") // Ball ID 7 - newly added - ) - ) { - override lazy val desiredName = "BallRSModule" -} -``` -#### 4. Write ReluBall interface file - -Create a `reluball` folder in the `arch/src/main/scala/examples/toy/balldomain` directory, enter the folder and create `ReluBall.scala` to write the interface code. - -## III. Writing Test Software and Compilation Settings - -### 1. Create test file - -Create `relu_test.c` under `bb-tests/workloads/src/CTest/toy/`, write test code. The core function in the code will execute `void bb_relu(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter);` Note the declaration and definition of this function below. - -### 2. Modify CMakeLists.txt - -Add test target in `bb-tests/workloads/src/CTest/toy/CMakeLists.txt`: CMakeLists.txt:120-127 - -``` -add_cross_platform_test_target(ctest_relu_test relu_test.c) -``` - -And add to the main build target: CMakeLists.txt:137-162 - -``` -add_custom_target(buckyball-CTest-build ALL DEPENDS - # ... other tests ... - ctest_relu_test - COMMENT "Building all workloads for Buckyball" - VERBATIM) -``` - -### 3. Need to add ReLU instruction API - -#### a. isa.h - -- Add declaration for `ReLU` instruction in `bb-tests/workloads/lib/bbhw/isa/isa.h`: `isa.h:33-43` - -- Add to `InstructionType` enum: - -``` -RELU_FUNC7 = 38, // 0x26 - ReLU function code (or other value you choose) -``` - -- Add to function declaration section: `isa.h:72-73` - -``` -void bb_relu(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter); -``` - -#### b. isa.c - -- Add `38_relu.c` in `bb-tests/workloads/lib/bbhw/isa`, implement `void bb_relu(uint32_t op1_addr, uint32_t wr_addr, uint32_t iter)` inside - -- Add declaration in `bb-tests/workloads/lib/bbhw/isa/isa.c`: `isa.c:53-76` - -``` -case RELU_FUNC7: - return &relu_config; -``` - -- In `isa.c:37-47` - -``` -extern const InstructionConfig relu_config; -``` - -### 4. Update CMakeLists.txt - -Add compilation and linking of `38_relu.c` in all three compilation commands in `bb-tests/workloads/lib/bbhw/isa/CMakeLists.txt`: - -1. **Linux version**: Add in `COMMAND` of `add_custom_command`: - - ``` - && riscv64-unknown-linux-gnu-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/38_relu.c -march=rv64gc -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o linux-38_relu.o - ``` - - And add `linux-38_relu.o` to the `ar rcs` command - -2. **Baremetal version**: Add in `COMMAND` of `add_custom_command`: - - ``` - && riscv64-unknown-elf-gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/38_relu.c -g -fno-common -O2 -static -march=rv64gc -mcmodel=medany -fno-builtin-printf -D__BAREMETAL__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o baremetal-38_relu.o - ``` - - And add `baremetal-38_relu.o` to the `ar rcs` command - -3. **x86 version**: Add in `COMMAND` of `add_custom_command`: - - ``` - && gcc -c ${CMAKE_CURRENT_SOURCE_DIR}/38_relu.c -fPIC -D__x86_64__ -I${CMAKE_CURRENT_SOURCE_DIR} -I${CMAKE_CURRENT_SOURCE_DIR}/.. -o x86-38_relu.o - ``` - - And add `x86-38_relu.o` to the `ar rcs` command - -4. The ISA submodule library at the beginning needs to add the corresponding **38_relu.c** file. - - -## IV. Test Operation Steps - -### Step 1: Compile test program - -``` -cd bb-tests/build -rm -rf * -cmake -G Ninja ../ -``` - -**Warning**: Before executing `rm -rf *`, make sure you are in the `bb-tests/build` directory, otherwise forcing deletion in the wrong folder will be catastrophic! - -If a disaster occurs, you can pull the initial documents from GitHub again, but files updated on the server side cannot be recovered. - -``` -ninja ctest_relu_test // Software compilation -``` - -If `ninja ctest_relu_test` reports an error after execution, this means software compilation failed, please check **"III. Writing Test Software"** and related files. - -``` -bbdev workload --build -``` - -Compile/package the selected workload source code or configuration into artifacts (such as executable files, images, runtime scripts, input data packages, etc.) that can be used in the simulation or runtime environment for subsequent running on the Verilator/simulation platform or host side. - -### Step 2: Generate Verilog - -``` -cd buckyball -bbdev verilator --verilog '--config sims.verilator.BuckyballToyVerilatorConfig' -``` - -If `bbdev verilator --verilog` reports an error after execution, this means hardware compilation failed, please check **"I. Writing Chisel Hardware Module II. Compilation Adaptation Preparation"** related files. - - -### Step 3: Run simulation - -``` -bbdev verilator --run '--jobs 16 --binary ctest_relu_test_singlecore-baremetal --config sims.verilator.BuckyballToyVerilatorConfig --batch' -``` - -If `bbdev verilator --verilog` reports an error after execution, this means the hardware system has timeout, deadlock and other issues, please check **I. Writing Chisel Hardware Module** related files. - -### Step 5: View simulation files - -In `arch/waveform/SimulationFileName(E.g.2025-10-08-00-03-ctest_vecunit_matmul_random1_singlecore-baremetal)`, download the `waveform.fst` file to your local system using software like `Filezilla`, and view the waveform using a local simulation waveform viewer (E.g. GTKWave). - -Note that the simulation file folder should only contain the `waveform.fst` file. If a `waveform.fst.hier` file exists, it means the simulation failed. - -If the waveform does not meet theoretical conditions, check **I. Writing Chisel Hardware Module** related files when the software test code is correct. - -To check if the software code has problems, you can refer to its execution results on `CPU`. You can temporarily completely remove hardware accelerator calls from the `relu_test.c` file and only test the CPU version. - -## V. Simulation Waveform -After importing `waveform.fst` locally, use [GTKWAVE](https://zhuanlan.zhihu.com/p/647533706) to find in the project index: -`TOP.TestHarness.chiptop0.system.tile_prci_domain.element_reset_domain_tile.buckyball.ballDomain.bbus.balls_4.reluUnit` The constants under this file are all hardware constants used by Relu.scala, double-click to view the waveform! - -> Some naming for different routines may not be exactly the same, but they are basically similar - -## VI. Performance Testing - -### Query number of clock cycles used - speed performance metric -```Scala -cat /home/MikeNotFound/code/buckyball/arch/log/2025-10-24-16-59-ctest_relu_test_singlecore-baremetal/disasm.log | grep "PMC" -``` - -### DC Test - Check Timing, Frequency, Area, and Related Parameters - -* **Preparation** - -1. In the `/home//bash.sh` file, add the required environment variables at the end: - - ```bash - export SNPSLMD_LICENSE_FILE=27000@amax - export PATH="$PATH:/opt/riscv/bin" - export VCS_HOME="/data0/tools/Synopsys/vcs/vcs/W-2024.09-SP1" - export PATH="$PATH:$VCS_HOME/bin" - export VERDI_HOME="/data0/tools/Synopsys/verdi/verdi/W-2024.09-SP1" - export PATH="$PATH:$VERDI_HOME/bin" - export SCL_HOME="/data0/tools/Synopsys/scl/scl/2024.06" - export PATH="$PATH:$SCL_HOME/linux64/bin" - export DC_HOME="/data0/tools/Synopsys/dc/syn/W-2024.09-SP1" - export PATH="$PATH:$DC_HOME/bin" - export PT_HOME="/data0/tools/Synopsys/ptpx/prime/W-2024.09-SP1/" - export PATH="$PATH:$PT_HOME/bin" - - export LM_LICENSE_FILE=/data0/tools/Synopsys/lic/Synopsys.dat - - alias vcs="vcs -full64" - alias lmli="lmgrd -c /data0/tools/Synopsys/lic/Synopsys.dat" - ``` - -2. In the `/home//code/buckyball/evals/run-dc.sh` file, remove the `-retime` option around line 126. - ---- - -* **Formal Test** - -1. Go back to the `buckyball` directory and run the command - - ```bash - bbdev verilator --verilog "--balltype ReluBall --output_dir ReluBall_1" - ``` - - This will generate a Verilog folder for the specified ball under the `arch` directory. - -2. Grant execution permission to the script: - - ```bash - chmod 777 evals/run-dc.sh - ``` - -3. Run the DC command: - - ```bash - ./evals/run-dc.sh --srcdir arch/ReluBall_1 --top ReluBall - ``` - - This means performing the DC test on the top-level file `ReluBall.sv` located in the `arch/ReluBall_1` folder. - -4. You can find the test results in - - ``` - /home//buckyball/bb-tests/output/dc/reports - ``` diff --git a/docs/bb-note/src/workflow/README.md b/docs/bb-note/src/workflow/README.md deleted file mode 100644 index e69de29b..00000000 diff --git a/docs/bb-note/src/workflow/steps/agent/README.md b/docs/bb-note/src/workflow/steps/agent/README.md deleted file mode 120000 index 039f1835..00000000 --- a/docs/bb-note/src/workflow/steps/agent/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/agent/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/compiler/README.md b/docs/bb-note/src/workflow/steps/compiler/README.md deleted file mode 120000 index 09be4abc..00000000 --- a/docs/bb-note/src/workflow/steps/compiler/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/compiler/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/doc-agent/README.md b/docs/bb-note/src/workflow/steps/doc-agent/README.md deleted file mode 120000 index 0a6a9422..00000000 --- a/docs/bb-note/src/workflow/steps/doc-agent/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/doc-agent/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/firesim/README.md b/docs/bb-note/src/workflow/steps/firesim/README.md deleted file mode 120000 index c11df3c6..00000000 --- a/docs/bb-note/src/workflow/steps/firesim/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/firesim/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/marshal/README.md b/docs/bb-note/src/workflow/steps/marshal/README.md deleted file mode 120000 index 49253fcd..00000000 --- a/docs/bb-note/src/workflow/steps/marshal/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/marshal/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/sardine/README.md b/docs/bb-note/src/workflow/steps/sardine/README.md deleted file mode 120000 index 438b4dc8..00000000 --- a/docs/bb-note/src/workflow/steps/sardine/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/sardine/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/uvm/README.md b/docs/bb-note/src/workflow/steps/uvm/README.md deleted file mode 120000 index 91c79b4e..00000000 --- a/docs/bb-note/src/workflow/steps/uvm/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/uvm/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/verilator/README.md b/docs/bb-note/src/workflow/steps/verilator/README.md deleted file mode 120000 index 89b70019..00000000 --- a/docs/bb-note/src/workflow/steps/verilator/README.md +++ /dev/null @@ -1 +0,0 @@ -../../../../../../workflow/steps/verilator/README.md \ No newline at end of file diff --git a/docs/bb-note/src/workflow/steps/workload/README.md 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    - - From 65fbf8311f53b5b8b8009ac9e8e6ed37b184d674 Mon Sep 17 00:00:00 2001 From: shirohasuki Date: Wed, 4 Mar 2026 08:46:00 +0800 Subject: [PATCH 131/238] [docs] update: bump documentation submodule to latest commit --- docs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs b/docs index 8a156271..0b1e11a5 160000 --- a/docs +++ b/docs @@ -1 +1 @@ -Subproject commit 8a1562719c7858f59194dd70f0d88b955594768c +Subproject commit 0b1e11a5ef548ed8927344eff83e4012e1e96c44 From a547d5ae0cfed76223448def465c897b3f6eee96 Mon Sep 17 00:00:00 2001 From: Shiroha Date: Wed, 4 Mar 2026 20:06:52 +0800 Subject: [PATCH 132/238] Update README links and badges --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index ec2e7879..79b59a18 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ [![Ask DeepWiki](https://deepwiki.com/badge.svg)](https://deepwiki.com/DangoSys/buckyball) [![zread](https://img.shields.io/badge/Ask_Zread-_.svg?style=flat&color=00b0aa&labelColor=000000&logo=data%3Aimage%2Fsvg%2Bxml%3Bbase64%2CPHN2ZyB3aWR0aD0iMTYiIGhlaWdodD0iMTYiIHZpZXdCb3g9IjAgMCAxNiAxNiIgZmlsbD0ibm9uZSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIj4KPHBhdGggZD0iTTQuOTYxNTYgMS42MDAxSDIuMjQxNTZDMS44ODgxIDEuNjAwMSAxLjYwMTU2IDEuODg2NjQgMS42MDE1NiAyLjI0MDFWNC45NjAxQzEuNjAxNTYgNS4zMTM1NiAxLjg4ODEgNS42MDAxIDIuMjQxNTYgNS42MDAxSDQuOTYxNTZDNS4zMTUwMiA1LjYwMDEgNS42MDE1NiA1LjMxMzU2IDUuNjAxNTYgNC45NjAxVjIuMjQwMUM1LjYwMTU2IDEuODg2NjQgNS4zMTUwMiAxLjYwMDEgNC45NjE1NiAxLjYwMDFaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00Ljk2MTU2IDEwLjM5OTlIMi4yNDE1NkMxLjg4ODEgMTAuMzk5OSAxLjYwMTU2IDEwLjY4NjQgMS42MDE1NiAxMS4wMzk5VjEzLjc1OTlDMS42MDE1NiAxNC4xMTM0IDEuODg4MSAxNC4zOTk5IDIuMjQxNTYgMTQuMzk5OUg0Ljk2MTU2QzUuMzE1MDIgMTQuMzk5OSA1LjYwMTU2IDE0LjExMzQgNS42MDE1NiAxMy43NTk5VjExLjAzOTlDNS42MDE1NiAxMC42ODY0IDUuMzE1MDIgMTAuMzk5OSA0Ljk2MTU2IDEwLjM5OTlaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik0xMy43NTg0IDEuNjAwMUgxMS4wMzg0QzEwLjY4NSAxLjYwMDEgMTAuMzk4NCAxLjg4NjY0IDEwLjM5ODQgMi4yNDAxVjQuOTYwMUMxMC4zOTg0IDUuMzEzNTYgMTAuNjg1IDUuNjAwMSAxMS4wMzg0IDUuNjAwMUgxMy43NTg0QzE0LjExMTkgNS42MDAxIDE0LjM5ODQgNS4zMTM1NiAxNC4zOTg0IDQuOTYwMVYyLjI0MDFDMTQuMzk4NCAxLjg4NjY0IDE0LjExMTkgMS42MDAxIDEzLjc1ODQgMS42MDAxWiIgZmlsbD0iI2ZmZiIvPgo8cGF0aCBkPSJNNCAxMkwxMiA0TDQgMTJaIiBmaWxsPSIjZmZmIi8%2BCjxwYXRoIGQ9Ik00IDEyTDEyIDQiIHN0cm9rZT0iI2ZmZiIgc3Ryb2tlLXdpZHRoPSIxLjUiIHN0cm9rZS1saW5lY2FwPSJyb3VuZCIvPgo8L3N2Zz4K&logoColor=ffffff)](https://zread.ai/DangoSys/buckyball) -[![Document](https://github.com/DangoSys/buckyball/actions/workflows/doc.yml/badge.svg?branch=main)](https://dangosys.github.io/buckyball) +[![Document](https://img.shields.io/badge/documents-online-30c452?style=plastic&logo=gitbook)](http://175.178.48.176/docs/en/Overview.md) [![buckyball CI](https://github.com/DangoSys/buckyball/actions/workflows/test.yml/badge.svg)](https://github.com/DangoSys/buckyball/actions/workflows/test.yml)