Based on the proposal.md and implementation.md documents, implementing visual FSM editor.
- Initialize Next.js 14 project with TypeScript strict mode
- Configure ESLint/Prettier with Verilog-specific rules
- Set up project structure (src/, lib/, components/, app/)
- Configure testing framework (Vitest + React Testing Library)
- Set up CI/CD pipeline (GitHub Actions)
- Set up ESLint and linting workflows
- Design and implement database schema (projects, modules, prompt_history, validation_cache)
- Create database migrations with Drizzle ORM
- Set up API structure scaffolding (Projects, Modules, FSM, LLM endpoints)
- Research parsing approaches (Chevrotain chosen)
- Implement lexer for Verilog tokens (50 tests passing)
- Implement parser for core subset (modules, always blocks, assign, FSMs)
- Generate AST representation (types.ts with full type definitions)
- Write comprehensive parser tests (86 tests total)
- Implement AST → Verilog code generator
- Implement formatting rules (2-space indent, consistent style)
- Add comment preservation logic (via options)
- Create template system for common patterns
- Verify round-trip parsing (8 tests)
- Implement lint rules (6 rules: undriven-signal, blocking-in-sequential, nonblocking-in-combinational, missing-default-case, incomplete-sensitivity, multi-driven-signal)
- Integrate with iverilog for syntax validation
- Implement error message formatting and source mapping
- Unit tests for all parser components
- Integration tests with real Verilog files (19 tests)
- Property-based testing with fast-check (13 tests)
- Parser coverage: 99.22% lines, Lexer: 100% lines
- Total: 179 tests passing
- Define FSM TypeScript interfaces (FSMState, FSMTransition, FSM)
- Create FSM store using Zustand
- Implement state encoding utilities (binary, one-hot, gray)
- Set up ReactFlow with custom node/edge types
- Create FSMState custom node component
- Create FSMTransition custom edge component
- Implement state encoding generator (binary/onehot/gray)
- Generate state register with reset logic
- Generate combinational next-state logic
- Generate output logic (Moore/Mealy)
- Create FSM template system with customization options
- Add FSM validation (unreachable states, dead transitions)
- Pattern matching for FSM structures in AST
- State encoding detection
- Transition condition extraction
- State output assignment extraction
- Heuristic layout algorithm for visual representation
- Handle complex FSM patterns (nested states, multiple FSMs)
- State properties panel (name, outputs, isInitial)
- Transition condition editor with autocomplete
- Drag-and-drop state creation
- Connection validation (no dangling transitions)
- Auto-layout algorithm (force-directed)
- Undo/redo support with Zustand middleware
- Real-time Verilog sync (FSM changes → code updates)
- Design system prompt for Verilog generation
- Build few-shot examples database
- Context injection (existing module ports, signals)
- Output formatting constraints
- Define LLM Provider Interface (Generic)
- Implement Anthropic (Claude) Provider
- Implement OpenAI (GPT/Ollama) Provider
- Create Generic API Route
- Analyze module interface (inputs/outputs)
- Generate clock/reset stimulus
- Generate test vectors for common cases
- Add assertion checks
- Autocomplete Logic (Signal names, Keywords)
- Smart Suggestions (Linting/Fixes)
- Module Instantiation Templates
- Editor Setup (Monaco Install, Theme)
- Language Features (Completion, Linting)
- Template Insertion Actions
- File Tree: Visual explorer for projects/modules
- Tab System: Manage state for multiple open files
- Split-View: Integrate Code + FSM editors side-by-side
- Dockerfile with iverilog/verilator
- Simulation Runner (compile, run, parse output)
- Simulation API Endpoint
- VCD Parser (header, value changes)
- Unit Tests for Parser
- WaveformViewer Component (Canvas/SVG)
- Integration with Toolbar
- Performance optimization (security headers, icon optimization)
- E2E testing with Playwright (6 tests, CI workflow)
- Security audit (npm audit, CSP headers)
- Documentation & tutorials (QUICKSTART.md, ARCHITECTURE.md)
- Production deployment (manual: Vercel setup)
| Component | Coverage |
|---|---|
| Lexer | 100% |
| Parser | 99.22% |
| Generator | ~85% |
| Validator | ~90% |
Each task completion = 1 commit with descriptive message following format:
feat(scope): description or test(scope): description