diff --git a/src/cpu/operators/CpuGemmConv2d.cpp b/src/cpu/operators/CpuGemmConv2d.cpp
index 23ad31e353..c856456de4 100644
--- a/src/cpu/operators/CpuGemmConv2d.cpp
+++ b/src/cpu/operators/CpuGemmConv2d.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2025 Arm Limited.
+ * Copyright (c) 2021-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -185,8 +185,10 @@ CpuGemmConv2d::SkipInfo CpuGemmConv2d::skip_im_col_info(const ITensorInfo
     unsigned int       conv_h        = 0;
     std::tie(conv_w, conv_h) = scaled_dimensions(src->dimension(idx_width), src->dimension(idx_height), kernel_width,
                                                  kernel_height, conv_info, dilation);
-    const bool skip_im2col   = (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
-                              conv_info.stride().first == 1 && conv_info.stride().second == 1);
+
+    const bool skip_im2col = (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
+                              conv_info.stride().first == 1 && conv_info.stride().second == 1) &&
+                             !conv_info.has_padding();
 
     if (skip_im2col)
     {
diff --git a/tests/datasets/SmallConvolutionLayerDataset.h b/tests/datasets/SmallConvolutionLayerDataset.h
index 1a8aaa29fe..0196c9df50 100644
--- a/tests/datasets/SmallConvolutionLayerDataset.h
+++ b/tests/datasets/SmallConvolutionLayerDataset.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, 2025 Arm Limited.
+ * Copyright (c) 2017-2021, 2025-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -181,6 +181,8 @@ class SmallConvolutionLayerDataset final : public ConvolutionLayerDataset
         // 1x1 Kernel with Stride (1, 1) and NHWC data layout in order to test skipping Im2Col
         add_config(TensorShape(1U, 5U, 2U), TensorShape(1U, 1U, 2U, 3U), TensorShape(3U), TensorShape(1U, 5U, 3U),
                    PadStrideInfo(1, 1, 0, 0));
+        add_config(TensorShape(1U, 5U, 2U), TensorShape(1U, 1U, 2U, 3U), TensorShape(3U), TensorShape(3U, 7U, 3U),
+                   PadStrideInfo(1, 1, 1, 1));
 
         // Batch size 1
         add_config(TensorShape(23U, 27U, 5U), TensorShape(3U, 3U, 5U, 2U), TensorShape(2U), TensorShape(11U, 25U, 2U),