From c7b184007097818e8d6c155843d051be64f25cfc Mon Sep 17 00:00:00 2001
From: Ryan Ilgen <Ryan.Ilgen@amd.com>
Date: Thu, 5 Mar 2026 11:26:20 -0600
Subject: [PATCH] Updated seagull and falcon dts to match EVT2 spec

- Adjusted dts for VR sensors on seagull and falcon
- Fixed issues with VR updates on falcon

Signed-off-by: Ryan Ilgen <Ryan.Ilgen@amd.com>
---
 .../boot/dts/aspeed/aspeed-bmc-amd-falcon.dts | 20 +++++++++----------
 .../dts/aspeed/aspeed-bmc-amd-seagull.dts     |  8 ++++----
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts
index fc831ade635b3f..8632549943a2c7 100644
--- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts
+++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts
@@ -329,13 +329,13 @@
 				compatible = "mps,mp29608";
 				reg = <0x42>;
 			};
-			vdd33s5run@47 {
+			vdd33s5run@08 {
 				// P0_VDD_18_S5_RUN
 				// Infineon: TDA38740A
 				compatible = "pmbus";
-				reg = <0x47>;
+				reg = <0x08>;
 			};
-			vdd18s5run@08 {
+			vdd18s5run@47 {
 				// P0_VDD_33_S5_RUN
 				// TDK:FS1604
 				compatible = "pmbus";
@@ -362,19 +362,19 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			vdd33dual@43 {
-				// 47 in EVT2
+			vdd33dual@4F {
+				// 4F in EVT2
 				// P3V3_AUX
 				// Infineon: TDA38725A
 				compatible = "pmbus";
-				reg = <0x43>;
+				reg = <0x4F>;
 			};
-			p2v5_aux@8{
+			p2v5_aux@0B{
 				// 0B in EVT2
 				// P5V_S5
 				// TDK:FS1006
 				compatible = "pmbus";
-				reg = <0x8>;
+				reg = <0x0B>;
 			};
 			p1v8_aux@9{
 				// P1V8_AUX
@@ -382,11 +382,11 @@
 				compatible = "pmbus";
 				reg = <0x9>;
 			};
-			p1v0_aux@a{
+			p1v0_aux@0A{
 				// P0V85_AUX
 				// TDK:FS1606
 				compatible = "pmbus";
-				reg = <0xa>;
+				reg = <0x0A>;
 			};
 		};
 
diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts
index 945e186cf41f1b..7e3c35ad240bcc 100644
--- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts
+++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts
@@ -377,15 +377,15 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			p3v3aux@43 {
+			p3v3aux@4F {
 				//P3V3_AUX VRM
 				compatible = "pmbus";
-				reg = <0x43>;
+				reg = <0x4F>;
 			};
-			p5vs5@08 {
+			p5vs5@0B {
 				//P5V_S5 VRM
 				compatible = "pmbus";
-				reg = <0x08>;
+				reg = <0x0B>;
 			};
 			p1v8aux@09 {
 				//P1V8_AUX VRM